├── MIPS31 ├── 1952650-陈子翔-CPU31.zip ├── 31条指令CPU实验报告_1952650_陈子翔.docx ├── 31条指令CPU实验报告_1952650_陈子翔.pdf ├── IP_coe │ ├── _1_addi.coe │ ├── _1_addiu.coe │ ├── _1_lui.coe │ ├── _2_add.coe │ ├── _2_addu.coe │ ├── _2_and.coe │ ├── _2_andi.coe │ ├── _2_lwsw.coe │ ├── _2_lwsw2.coe │ ├── _2_nor.coe │ ├── _2_or.coe │ ├── _2_ori.coe │ ├── _2_sll.coe │ ├── _2_sllv.coe │ ├── _2_slt.coe │ ├── _2_slti.coe │ ├── _2_sltiu.coe │ ├── _2_sltu.coe │ ├── _2_sra.coe │ ├── _2_srav.coe │ ├── _2_srl.coe │ ├── _2_srlv.coe │ ├── _2_sub.coe │ ├── _2_subu.coe │ ├── _2_xor.coe │ ├── _2_xori.coe │ ├── _3.5_beq.coe │ ├── _3.5_bne.coe │ ├── _3_j.coe │ ├── _3_jal.coe │ ├── _4_jr.coe │ └── mips_31_mars_simulate.coe ├── cpu_31 │ ├── cpu_31.cache │ │ └── wt │ │ │ ├── java_command_handlers.wdf │ │ │ ├── project.wpc │ │ │ ├── synthesis.wdf │ │ │ ├── webtalk_pa.xml │ │ │ └── xsim.wdf │ ├── cpu_31.hw │ │ └── cpu_31.lpr │ ├── cpu_31.ip_user_files │ │ ├── README.txt │ │ ├── ip │ │ │ └── imem │ │ │ │ ├── imem.veo │ │ │ │ ├── imem.vho │ │ │ │ ├── imem_stub.v │ │ │ │ └── imem_stub.vhdl │ │ ├── ipstatic │ │ │ └── dist_mem_gen_v8_0_10 │ │ │ │ └── simulation │ │ │ │ └── dist_mem_gen_v8_0.v │ │ ├── mem_init_files │ │ │ ├── IM.mif │ │ │ ├── _1_addi.coe │ │ │ ├── _1_addiu.coe │ │ │ ├── _1_lui.coe │ │ │ ├── _2_add.coe │ │ │ ├── _2_addu.coe │ │ │ ├── _2_and.coe │ │ │ ├── _2_andi.coe │ │ │ ├── _2_lwsw.coe │ │ │ ├── _2_lwsw2.coe │ │ │ ├── _2_nor.coe │ │ │ ├── _2_or.coe │ │ │ ├── _2_ori.coe │ │ │ ├── _2_sll.coe │ │ │ ├── _2_sllv.coe │ │ │ ├── _2_slt.coe │ │ │ ├── _2_slti.coe │ │ │ ├── _2_sltiu.coe │ │ │ ├── _2_sltu.coe │ │ │ ├── _2_sra.coe │ │ │ ├── _2_srav.coe │ │ │ ├── _2_srl.coe │ │ │ ├── _2_srlv.coe │ │ │ ├── _2_sub.coe │ │ │ ├── _2_subu.coe │ │ │ ├── _2_xor.coe │ │ │ ├── _2_xori.coe │ │ │ ├── _3.5_beq.coe │ │ │ ├── _3.5_bne.coe │ │ │ ├── _3_j.coe │ │ │ ├── _3_jal.coe │ │ │ ├── _4_jr.coe │ │ │ ├── imem.mif │ │ │ └── mips_31_mars_simulate.coe │ │ └── sim_scripts │ │ │ └── imem │ │ │ ├── README.txt │ │ │ ├── activehdl │ │ │ ├── README.txt │ │ │ ├── compile.do │ │ │ ├── file_info.txt │ │ │ ├── glbl.v │ │ │ ├── imem.mif │ │ │ ├── imem.sh │ │ │ ├── imem.udo │ │ │ ├── mips_31_mars_simulate.coe │ │ │ ├── simulate.do │ │ │ └── wave.do │ │ │ ├── ies │ │ │ ├── README.txt │ │ │ ├── file_info.txt │ │ │ ├── glbl.v │ │ │ ├── imem.mif │ │ │ ├── imem.sh │ │ │ ├── mips_31_mars_simulate.coe │ │ │ └── run.f │ │ │ ├── modelsim │ │ │ ├── README.txt │ │ │ ├── compile.do │ │ │ ├── file_info.txt │ │ │ ├── glbl.v │ │ │ ├── imem.mif │ │ │ ├── imem.sh │ │ │ ├── imem.udo │ │ │ ├── mips_31_mars_simulate.coe │ │ │ ├── simulate.do │ │ │ └── wave.do │ │ │ ├── questa │ │ │ ├── README.txt │ │ │ ├── compile.do │ │ │ ├── elaborate.do │ │ │ ├── file_info.txt │ │ │ ├── glbl.v │ │ │ ├── imem.mif │ │ │ ├── imem.sh │ │ │ ├── imem.udo │ │ │ ├── mips_31_mars_simulate.coe │ │ │ ├── simulate.do │ │ │ └── wave.do │ │ │ ├── riviera │ │ │ ├── README.txt │ │ │ ├── compile.do │ │ │ ├── file_info.txt │ │ │ ├── glbl.v │ │ │ ├── imem.mif │ │ │ ├── imem.sh │ │ │ ├── imem.udo │ │ │ ├── mips_31_mars_simulate.coe │ │ │ ├── simulate.do │ │ │ └── wave.do │ │ │ ├── vcs │ │ │ ├── README.txt │ │ │ ├── file_info.txt │ │ │ ├── glbl.v │ │ │ ├── imem.mif │ │ │ ├── imem.sh │ │ │ ├── mips_31_mars_simulate.coe │ │ │ └── simulate.do │ │ │ └── xsim │ │ │ ├── README.txt │ │ │ ├── cmd.tcl │ │ │ ├── elab.opt │ │ │ ├── file_info.txt │ │ │ ├── glbl.v │ │ │ ├── imem.mif │ │ │ ├── imem.sh │ │ │ ├── mips_31_mars_simulate.coe │ │ │ ├── vlog.prj │ │ │ └── xsim.ini │ ├── cpu_31.runs │ │ ├── .jobs │ │ │ ├── vrs_config_1.xml │ │ │ ├── vrs_config_10.xml │ │ │ ├── vrs_config_11.xml │ │ │ ├── vrs_config_12.xml │ │ │ ├── vrs_config_13.xml │ │ │ ├── vrs_config_14.xml │ │ │ ├── vrs_config_15.xml │ │ │ ├── vrs_config_16.xml │ │ │ ├── vrs_config_17.xml │ │ │ ├── vrs_config_18.xml │ │ │ ├── vrs_config_19.xml │ │ │ ├── vrs_config_2.xml │ │ │ ├── vrs_config_20.xml │ │ │ ├── vrs_config_21.xml │ │ │ ├── vrs_config_22.xml │ │ │ ├── vrs_config_23.xml │ │ │ ├── vrs_config_24.xml │ │ │ ├── vrs_config_25.xml │ │ │ ├── vrs_config_26.xml │ │ │ ├── vrs_config_27.xml │ │ │ ├── vrs_config_28.xml │ │ │ ├── vrs_config_29.xml │ │ │ ├── vrs_config_3.xml │ │ │ ├── vrs_config_30.xml │ │ │ ├── vrs_config_31.xml │ │ │ ├── vrs_config_32.xml │ │ │ ├── vrs_config_33.xml │ │ │ ├── vrs_config_34.xml │ │ │ ├── vrs_config_35.xml │ │ │ ├── vrs_config_36.xml │ │ │ ├── vrs_config_37.xml │ │ │ ├── vrs_config_38.xml │ │ │ ├── vrs_config_39.xml │ │ │ ├── vrs_config_4.xml │ │ │ ├── vrs_config_40.xml │ │ │ ├── vrs_config_41.xml │ │ │ ├── vrs_config_42.xml │ │ │ ├── vrs_config_43.xml │ │ │ ├── vrs_config_44.xml │ │ │ ├── vrs_config_45.xml │ │ │ ├── vrs_config_46.xml │ │ │ ├── vrs_config_47.xml │ │ │ ├── vrs_config_5.xml │ │ │ ├── vrs_config_6.xml │ │ │ ├── vrs_config_7.xml │ │ │ ├── vrs_config_8.xml │ │ │ └── vrs_config_9.xml │ │ └── imem_synth_1 │ │ │ ├── .Vivado_Synthesis.queue.rst │ │ │ ├── .vivado.begin.rst │ │ │ ├── .vivado.end.rst │ │ │ ├── ISEWrap.js │ │ │ ├── ISEWrap.sh │ │ │ ├── dont_touch.xdc │ │ │ ├── gen_run.xml │ │ │ ├── htr.txt │ │ │ ├── imem.dcp │ │ │ ├── imem.tcl │ │ │ ├── imem.vds │ │ │ ├── imem_utilization_synth.pb │ │ │ ├── imem_utilization_synth.rpt │ │ │ ├── project.wdf │ │ │ ├── rundef.js │ │ │ ├── runme.bat │ │ │ ├── runme.log │ │ │ ├── runme.sh │ │ │ ├── vivado.jou │ │ │ └── vivado.pb │ ├── cpu_31.sim │ │ └── sim_1 │ │ │ └── behav │ │ │ ├── _1_addi.coe │ │ │ ├── _1_addiu.coe │ │ │ ├── _1_lui.coe │ │ │ ├── _2_add.coe │ │ │ ├── _2_addu.coe │ │ │ ├── _2_and.coe │ │ │ ├── _2_andi.coe │ │ │ ├── _2_lwsw.coe │ │ │ ├── _2_lwsw2.coe │ │ │ ├── _2_nor.coe │ │ │ ├── _2_or.coe │ │ │ ├── _2_ori.coe │ │ │ ├── _2_sll.coe │ │ │ ├── _2_sllv.coe │ │ │ ├── _2_slt.coe │ │ │ ├── _2_slti.coe │ │ │ ├── _2_sltiu.coe │ │ │ ├── _2_sltu.coe │ │ │ ├── _2_sra.coe │ │ │ ├── _2_srav.coe │ │ │ ├── _2_srl.coe │ │ │ ├── _2_srlv.coe │ │ │ ├── _2_sub.coe │ │ │ ├── _2_subu.coe │ │ │ ├── _2_xor.coe │ │ │ ├── _2_xori.coe │ │ │ ├── _3.5_beq.coe │ │ │ ├── _3.5_bne.coe │ │ │ ├── _3_j.coe │ │ │ ├── _3_jal.coe │ │ │ ├── _4_jr.coe │ │ │ ├── compile.bat │ │ │ ├── compile.log │ │ │ ├── cpu_tb.udo │ │ │ ├── cpu_tb_compile.do │ │ │ ├── cpu_tb_simulate.do │ │ │ ├── cpu_tb_wave.do │ │ │ ├── glbl.v │ │ │ ├── imem.mif │ │ │ ├── mips_31_mars_simulate.coe │ │ │ ├── modelsim.ini │ │ │ ├── msim │ │ │ ├── _info │ │ │ ├── dist_mem_gen_v8_0_10 │ │ │ │ ├── _info │ │ │ │ ├── _lib.qdb │ │ │ │ ├── _lib1_0.qdb │ │ │ │ ├── _lib1_0.qpg │ │ │ │ ├── _lib1_0.qtl │ │ │ │ └── _vmake │ │ │ └── xil_defaultlib │ │ │ │ ├── _info │ │ │ │ ├── _lib.qdb │ │ │ │ ├── _lib1_0.qdb │ │ │ │ ├── _lib1_0.qpg │ │ │ │ ├── _lib1_0.qtl │ │ │ │ └── _vmake │ │ │ ├── sccomp_dataflow.udo │ │ │ ├── simulate.bat │ │ │ ├── simulate.log │ │ │ ├── vsim.wlf │ │ │ └── work │ │ │ └── _info │ ├── cpu_31.srcs │ │ ├── sim_1 │ │ │ └── new │ │ │ │ └── cpu_tb.v │ │ └── sources_1 │ │ │ ├── ip │ │ │ └── imem │ │ │ │ ├── dist_mem_gen_v8_0_10 │ │ │ │ ├── hdl │ │ │ │ │ ├── dist_mem_gen_v8_0.vhd │ │ │ │ │ └── dist_mem_gen_v8_0_vhsyn_rfs.vhd │ │ │ │ └── simulation │ │ │ │ │ └── dist_mem_gen_v8_0.v │ │ │ │ ├── doc │ │ │ │ └── dist_mem_gen_v8_0_changelog.txt │ │ │ │ ├── imem.dcp │ │ │ │ ├── imem.mif │ │ │ │ ├── imem.veo │ │ │ │ ├── imem.vho │ │ │ │ ├── imem.xci │ │ │ │ ├── imem.xml │ │ │ │ ├── imem_ooc.xdc │ │ │ │ ├── imem_sim_netlist.v │ │ │ │ ├── imem_sim_netlist.vhdl │ │ │ │ ├── imem_stub.v │ │ │ │ ├── imem_stub.vhdl │ │ │ │ ├── sim │ │ │ │ └── imem.v │ │ │ │ └── synth │ │ │ │ └── imem.vhd │ │ │ └── new │ │ │ ├── Dram.v │ │ │ ├── Ext16.v │ │ │ ├── Ext5.v │ │ │ ├── MUX.v │ │ │ ├── MUX_5bit.v │ │ │ ├── S_Ext16.v │ │ │ ├── S_Ext18.v │ │ │ ├── alu.v │ │ │ ├── cpu.v │ │ │ ├── pcreg.v │ │ │ ├── regfile.v │ │ │ └── sccomp_dataflow.v │ └── cpu_31.xpr └── result.txt ├── MIPS54 ├── 1952650-陈子翔-CPU54.zip ├── cpu_54.zip ├── cpu_54 │ ├── cpu_54.cache │ │ └── wt │ │ │ ├── java_command_handlers.wdf │ │ │ ├── project.wpc │ │ │ ├── synthesis.wdf │ │ │ ├── synthesis_details.wdf │ │ │ ├── webtalk_pa.xml │ │ │ └── xsim.wdf │ ├── cpu_54.hw │ │ ├── cpu_54.lpr │ │ ├── hw_1 │ │ │ └── hw.xml │ │ └── webtalk │ │ │ ├── .xsim_webtallk.info │ │ │ ├── labtool_webtalk.log │ │ │ ├── usage_statistics_ext_labtool.html │ │ │ └── usage_statistics_ext_labtool.xml │ ├── cpu_54.ip_user_files │ │ ├── README.txt │ │ ├── ip │ │ │ └── imen │ │ │ │ ├── imen.veo │ │ │ │ ├── imen.vho │ │ │ │ ├── imen_stub.v │ │ │ │ └── imen_stub.vhdl │ │ ├── ipstatic │ │ │ └── dist_mem_gen_v8_0_10 │ │ │ │ └── simulation │ │ │ │ └── dist_mem_gen_v8_0.v │ │ ├── mem_init_files │ │ │ ├── 13_j.hex.coe │ │ │ ├── 1_addi.hex.coe │ │ │ ├── 2_addiu.hex.coe │ │ │ ├── 32_clz.hex.coe │ │ │ ├── 33_divu.hex.coe │ │ │ ├── 35_jalr.hex.coe │ │ │ ├── 36.39_lbsb.hex.coe │ │ │ ├── 36.39_lbsb2.hex.coe │ │ │ ├── 37_lbu.hex.coe │ │ │ ├── 37_lbu2.hex.coe │ │ │ ├── 38_lhu.hex.coe │ │ │ ├── 38_lhu2.hex.coe │ │ │ ├── 40.41_lhsh.hex.coe │ │ │ ├── 40.41_lhsh2.hex.coe │ │ │ ├── 42.45_mfc0mtc0.hex.coe │ │ │ ├── 43.46_mfhi.mthi.hex.coe │ │ │ ├── 44.47_mflo.mtlo.hex.coe │ │ │ ├── 48_mult.hex.coe │ │ │ ├── 49_multu.hex.coe │ │ │ ├── 54_div.hex.coe │ │ │ ├── _1_addi.coe │ │ │ ├── imen.mif │ │ │ ├── mips_31_mars_simulate.coe │ │ │ └── mips_54_mars_simulate_student_ForWeb.coe │ │ └── sim_scripts │ │ │ └── imen │ │ │ ├── README.txt │ │ │ ├── activehdl │ │ │ ├── README.txt │ │ │ ├── compile.do │ │ │ ├── file_info.txt │ │ │ ├── glbl.v │ │ │ ├── imen.mif │ │ │ ├── imen.sh │ │ │ ├── imen.udo │ │ │ ├── mips_54_mars_simulate_student_ForWeb.coe │ │ │ ├── simulate.do │ │ │ └── wave.do │ │ │ ├── ies │ │ │ ├── README.txt │ │ │ ├── file_info.txt │ │ │ ├── glbl.v │ │ │ ├── imen.mif │ │ │ ├── imen.sh │ │ │ ├── mips_54_mars_simulate_student_ForWeb.coe │ │ │ └── run.f │ │ │ ├── modelsim │ │ │ ├── README.txt │ │ │ ├── compile.do │ │ │ ├── file_info.txt │ │ │ ├── glbl.v │ │ │ ├── imen.mif │ │ │ ├── imen.sh │ │ │ ├── imen.udo │ │ │ ├── mips_54_mars_simulate_student_ForWeb.coe │ │ │ ├── simulate.do │ │ │ └── wave.do │ │ │ ├── questa │ │ │ ├── README.txt │ │ │ ├── compile.do │ │ │ ├── elaborate.do │ │ │ ├── file_info.txt │ │ │ ├── glbl.v │ │ │ ├── imen.mif │ │ │ ├── imen.sh │ │ │ ├── imen.udo │ │ │ ├── mips_54_mars_simulate_student_ForWeb.coe │ │ │ ├── simulate.do │ │ │ └── wave.do │ │ │ ├── riviera │ │ │ ├── README.txt │ │ │ ├── compile.do │ │ │ ├── file_info.txt │ │ │ ├── glbl.v │ │ │ ├── imen.mif │ │ │ ├── imen.sh │ │ │ ├── imen.udo │ │ │ ├── mips_54_mars_simulate_student_ForWeb.coe │ │ │ ├── simulate.do │ │ │ └── wave.do │ │ │ ├── vcs │ │ │ ├── README.txt │ │ │ ├── file_info.txt │ │ │ ├── glbl.v │ │ │ ├── imen.mif │ │ │ ├── imen.sh │ │ │ ├── mips_54_mars_simulate_student_ForWeb.coe │ │ │ └── simulate.do │ │ │ └── xsim │ │ │ ├── README.txt │ │ │ ├── cmd.tcl │ │ │ ├── elab.opt │ │ │ ├── file_info.txt │ │ │ ├── glbl.v │ │ │ ├── imen.mif │ │ │ ├── imen.sh │ │ │ ├── mips_54_mars_simulate_student_ForWeb.coe │ │ │ ├── vlog.prj │ │ │ └── xsim.ini │ ├── cpu_54.runs │ │ ├── .jobs │ │ │ ├── vrs_config_1.xml │ │ │ ├── vrs_config_10.xml │ │ │ ├── vrs_config_11.xml │ │ │ ├── vrs_config_12.xml │ │ │ ├── vrs_config_13.xml │ │ │ ├── vrs_config_14.xml │ │ │ ├── vrs_config_15.xml │ │ │ ├── vrs_config_16.xml │ │ │ ├── vrs_config_17.xml │ │ │ ├── vrs_config_18.xml │ │ │ ├── vrs_config_19.xml │ │ │ ├── vrs_config_2.xml │ │ │ ├── vrs_config_20.xml │ │ │ ├── vrs_config_21.xml │ │ │ ├── vrs_config_22.xml │ │ │ ├── vrs_config_23.xml │ │ │ ├── vrs_config_24.xml │ │ │ ├── vrs_config_25.xml │ │ │ ├── vrs_config_26.xml │ │ │ ├── vrs_config_27.xml │ │ │ ├── vrs_config_28.xml │ │ │ ├── vrs_config_29.xml │ │ │ ├── vrs_config_3.xml │ │ │ ├── vrs_config_30.xml │ │ │ ├── vrs_config_31.xml │ │ │ ├── vrs_config_32.xml │ │ │ ├── vrs_config_33.xml │ │ │ ├── vrs_config_34.xml │ │ │ ├── vrs_config_35.xml │ │ │ ├── vrs_config_36.xml │ │ │ ├── vrs_config_37.xml │ │ │ ├── vrs_config_38.xml │ │ │ ├── vrs_config_39.xml │ │ │ ├── vrs_config_4.xml │ │ │ ├── vrs_config_40.xml │ │ │ ├── vrs_config_41.xml │ │ │ ├── vrs_config_42.xml │ │ │ ├── vrs_config_43.xml │ │ │ ├── vrs_config_44.xml │ │ │ ├── vrs_config_45.xml │ │ │ ├── vrs_config_46.xml │ │ │ ├── vrs_config_47.xml │ │ │ ├── vrs_config_48.xml │ │ │ ├── vrs_config_49.xml │ │ │ ├── vrs_config_5.xml │ │ │ ├── vrs_config_50.xml │ │ │ ├── vrs_config_51.xml │ │ │ ├── vrs_config_52.xml │ │ │ ├── vrs_config_53.xml │ │ │ ├── vrs_config_54.xml │ │ │ ├── vrs_config_55.xml │ │ │ ├── vrs_config_56.xml │ │ │ ├── vrs_config_57.xml │ │ │ ├── vrs_config_58.xml │ │ │ ├── vrs_config_59.xml │ │ │ ├── vrs_config_6.xml │ │ │ ├── vrs_config_60.xml │ │ │ ├── vrs_config_61.xml │ │ │ ├── vrs_config_62.xml │ │ │ ├── vrs_config_7.xml │ │ │ ├── vrs_config_8.xml │ │ │ └── vrs_config_9.xml │ │ ├── imen_synth_1 │ │ │ ├── .Vivado_Synthesis.queue.rst │ │ │ ├── .vivado.begin.rst │ │ │ ├── .vivado.end.rst │ │ │ ├── ISEWrap.js │ │ │ ├── ISEWrap.sh │ │ │ ├── dont_touch.xdc │ │ │ ├── gen_run.xml │ │ │ ├── htr.txt │ │ │ ├── imen.dcp │ │ │ ├── imen.tcl │ │ │ ├── imen.vds │ │ │ ├── imen_utilization_synth.pb │ │ │ ├── imen_utilization_synth.rpt │ │ │ ├── rundef.js │ │ │ ├── runme.bat │ │ │ ├── runme.log │ │ │ ├── runme.sh │ │ │ ├── vivado.jou │ │ │ └── vivado.pb │ │ ├── impl_1 │ │ │ ├── .Vivado_Implementation.queue.rst │ │ │ ├── .init_design.begin.rst │ │ │ ├── .init_design.end.rst │ │ │ ├── .opt_design.begin.rst │ │ │ ├── .opt_design.end.rst │ │ │ ├── .place_design.begin.rst │ │ │ ├── .place_design.end.rst │ │ │ ├── .route_design.begin.rst │ │ │ ├── .route_design.end.rst │ │ │ ├── .vivado.begin.rst │ │ │ ├── .vivado.end.rst │ │ │ ├── .write_bitstream.begin.rst │ │ │ ├── .write_bitstream.end.rst │ │ │ ├── ISEWrap.js │ │ │ ├── ISEWrap.sh │ │ │ ├── gen_run.xml │ │ │ ├── htr.txt │ │ │ ├── init_design.pb │ │ │ ├── opt_design.pb │ │ │ ├── place_design.pb │ │ │ ├── project.wdf │ │ │ ├── route_design.pb │ │ │ ├── rundef.js │ │ │ ├── runme.bat │ │ │ ├── runme.log │ │ │ ├── runme.sh │ │ │ ├── sccomp_dataflow.bit │ │ │ ├── sccomp_dataflow.tcl │ │ │ ├── sccomp_dataflow.vdi │ │ │ ├── sccomp_dataflow_7524.backup.vdi │ │ │ ├── sccomp_dataflow_clock_utilization_routed.rpt │ │ │ ├── sccomp_dataflow_control_sets_placed.rpt │ │ │ ├── sccomp_dataflow_drc_opted.rpt │ │ │ ├── sccomp_dataflow_drc_routed.pb │ │ │ ├── sccomp_dataflow_drc_routed.rpt │ │ │ ├── sccomp_dataflow_io_placed.rpt │ │ │ ├── sccomp_dataflow_opt.dcp │ │ │ ├── sccomp_dataflow_placed.dcp │ │ │ ├── sccomp_dataflow_power_routed.rpt │ │ │ ├── sccomp_dataflow_power_routed.rpx │ │ │ ├── sccomp_dataflow_power_summary_routed.pb │ │ │ ├── sccomp_dataflow_route_status.pb │ │ │ ├── sccomp_dataflow_route_status.rpt │ │ │ ├── sccomp_dataflow_routed.dcp │ │ │ ├── sccomp_dataflow_timing_summary_routed.rpt │ │ │ ├── sccomp_dataflow_timing_summary_routed.rpx │ │ │ ├── sccomp_dataflow_utilization_placed.pb │ │ │ ├── sccomp_dataflow_utilization_placed.rpt │ │ │ ├── usage_statistics_webtalk.html │ │ │ ├── usage_statistics_webtalk.xml │ │ │ ├── vivado.jou │ │ │ ├── vivado.pb │ │ │ ├── vivado_10552.backup.jou │ │ │ ├── vivado_7524.backup.jou │ │ │ └── write_bitstream.pb │ │ └── synth_1 │ │ │ ├── .Vivado_Synthesis.queue.rst │ │ │ ├── .Xil │ │ │ └── sccomp_dataflow_propImpl.xdc │ │ │ ├── .vivado.begin.rst │ │ │ ├── .vivado.end.rst │ │ │ ├── ISEWrap.js │ │ │ ├── ISEWrap.sh │ │ │ ├── gen_run.xml │ │ │ ├── htr.txt │ │ │ ├── rundef.js │ │ │ ├── runme.bat │ │ │ ├── runme.log │ │ │ ├── runme.sh │ │ │ ├── sccomp_dataflow.dcp │ │ │ ├── sccomp_dataflow.tcl │ │ │ ├── sccomp_dataflow.vds │ │ │ ├── sccomp_dataflow_utilization_synth.pb │ │ │ ├── sccomp_dataflow_utilization_synth.rpt │ │ │ ├── vivado.jou │ │ │ └── vivado.pb │ ├── cpu_54.sim │ │ └── sim_1 │ │ │ ├── behav │ │ │ ├── 32_clz.hex.coe │ │ │ ├── 33_divu.hex.coe │ │ │ ├── 35_jalr.hex.coe │ │ │ ├── 36.39_lbsb.hex.coe │ │ │ ├── 36.39_lbsb2.hex.coe │ │ │ ├── 37_lbu.hex.coe │ │ │ ├── 37_lbu2.hex.coe │ │ │ ├── 38_lhu.hex.coe │ │ │ ├── 38_lhu2.hex.coe │ │ │ ├── 40.41_lhsh.hex.coe │ │ │ ├── 40.41_lhsh2.hex.coe │ │ │ ├── 42.45_mfc0mtc0.hex.coe │ │ │ ├── 43.46_mfhi.mthi.hex.coe │ │ │ ├── 44.47_mflo.mtlo.hex.coe │ │ │ ├── 48_mult.hex.coe │ │ │ ├── 49_multu.hex.coe │ │ │ ├── 54_div.hex.coe │ │ │ ├── compile.bat │ │ │ ├── compile.log │ │ │ ├── cpu_tb.udo │ │ │ ├── cpu_tb_compile.do │ │ │ ├── cpu_tb_simulate.do │ │ │ ├── cpu_tb_vlog.prj │ │ │ ├── cpu_tb_wave.do │ │ │ ├── elaborate.bat │ │ │ ├── elaborate.log │ │ │ ├── glbl.v │ │ │ ├── imen.mif │ │ │ ├── mips_31_mars_simulate.coe │ │ │ ├── mips_54_mars_simulate_student_ForWeb.coe │ │ │ ├── modelsim.ini │ │ │ ├── msim │ │ │ │ ├── _info │ │ │ │ ├── dist_mem_gen_v8_0_10 │ │ │ │ │ ├── _info │ │ │ │ │ ├── _lib.qdb │ │ │ │ │ ├── _lib1_0.qdb │ │ │ │ │ ├── _lib1_0.qpg │ │ │ │ │ ├── _lib1_0.qtl │ │ │ │ │ └── _vmake │ │ │ │ └── xil_defaultlib │ │ │ │ │ ├── _info │ │ │ │ │ ├── _lib.qdb │ │ │ │ │ ├── _lib1_2.qdb │ │ │ │ │ ├── _lib1_2.qpg │ │ │ │ │ ├── _lib1_2.qtl │ │ │ │ │ └── _vmake │ │ │ ├── simulate.bat │ │ │ ├── simulate.log │ │ │ ├── tcl_stacktrace.txt │ │ │ ├── vsim.wlf │ │ │ ├── wlftzn7ejr │ │ │ ├── work │ │ │ │ └── _info │ │ │ ├── xelab.pb │ │ │ ├── xsim.dir │ │ │ │ ├── dist_mem_gen_v8_0_10 │ │ │ │ │ ├── dist_mem_gen_v8_0_10.rlx │ │ │ │ │ └── dist_mem_gen_v8_0_10.sdb │ │ │ │ ├── xil_defaultlib │ │ │ │ │ ├── @c@l@z.sdb │ │ │ │ │ ├── @c@p0.sdb │ │ │ │ │ ├── @d@i@v.sdb │ │ │ │ │ ├── @d@i@v@u.sdb │ │ │ │ │ ├── @dram.sdb │ │ │ │ │ ├── @ext16.sdb │ │ │ │ │ ├── @ext5.sdb │ │ │ │ │ ├── @ext8.sdb │ │ │ │ │ ├── @m@u@l@t.sdb │ │ │ │ │ ├── @m@u@x.sdb │ │ │ │ │ ├── @m@u@x8.sdb │ │ │ │ │ ├── @m@u@x_5bit.sdb │ │ │ │ │ ├── @s_@ext16.sdb │ │ │ │ │ ├── @s_@ext18.sdb │ │ │ │ │ ├── @s_@ext8.sdb │ │ │ │ │ ├── alu.sdb │ │ │ │ │ ├── cpu.sdb │ │ │ │ │ ├── cpu_tb.sdb │ │ │ │ │ ├── glbl.sdb │ │ │ │ │ ├── imen.sdb │ │ │ │ │ ├── multu.sdb │ │ │ │ │ ├── pcreg.sdb │ │ │ │ │ ├── regfile.sdb │ │ │ │ │ ├── sccomp_dataflow.sdb │ │ │ │ │ └── xil_defaultlib.rlx │ │ │ │ └── xsim.svtype │ │ │ ├── xsim.ini │ │ │ ├── xvlog.log │ │ │ └── xvlog.pb │ │ │ └── synth │ │ │ └── timing │ │ │ ├── 32_clz.hex.coe │ │ │ ├── 33_divu.hex.coe │ │ │ ├── 35_jalr.hex.coe │ │ │ ├── 36.39_lbsb.hex.coe │ │ │ ├── 36.39_lbsb2.hex.coe │ │ │ ├── 37_lbu.hex.coe │ │ │ ├── 37_lbu2.hex.coe │ │ │ ├── 38_lhu.hex.coe │ │ │ ├── 38_lhu2.hex.coe │ │ │ ├── 40.41_lhsh.hex.coe │ │ │ ├── 40.41_lhsh2.hex.coe │ │ │ ├── 42.45_mfc0mtc0.hex.coe │ │ │ ├── 43.46_mfhi.mthi.hex.coe │ │ │ ├── 44.47_mflo.mtlo.hex.coe │ │ │ ├── 48_mult.hex.coe │ │ │ ├── 49_multu.hex.coe │ │ │ ├── 54_div.hex.coe │ │ │ ├── compile.bat │ │ │ ├── compile.log │ │ │ ├── cpu_tb.udo │ │ │ ├── cpu_tb_compile.do │ │ │ ├── cpu_tb_simulate.do │ │ │ ├── cpu_tb_time_synth.sdf │ │ │ ├── cpu_tb_time_synth.sdf_typ.csd │ │ │ ├── cpu_tb_time_synth.v │ │ │ ├── cpu_tb_wave.do │ │ │ ├── imen.mif │ │ │ ├── mips_31_mars_simulate.coe │ │ │ ├── mips_54_mars_simulate_student_ForWeb.coe │ │ │ ├── modelsim.ini │ │ │ ├── msim │ │ │ ├── _info │ │ │ └── xil_defaultlib │ │ │ │ ├── _info │ │ │ │ ├── _lib.qdb │ │ │ │ ├── _lib1_3.qdb │ │ │ │ ├── _lib1_3.qpg │ │ │ │ ├── _lib1_3.qtl │ │ │ │ └── _vmake │ │ │ ├── simulate.bat │ │ │ ├── simulate.log │ │ │ ├── tcl_stacktrace.txt │ │ │ ├── vsim.wlf │ │ │ └── work │ │ │ └── _info │ ├── cpu_54.srcs │ │ ├── constrs_1 │ │ │ └── new │ │ │ │ └── icf.xdc │ │ ├── sim_1 │ │ │ └── new │ │ │ │ └── cpu_tb.v │ │ └── sources_1 │ │ │ ├── ip │ │ │ └── imen │ │ │ │ ├── dist_mem_gen_v8_0_10 │ │ │ │ ├── hdl │ │ │ │ │ ├── dist_mem_gen_v8_0.vhd │ │ │ │ │ └── dist_mem_gen_v8_0_vhsyn_rfs.vhd │ │ │ │ └── simulation │ │ │ │ │ └── dist_mem_gen_v8_0.v │ │ │ │ ├── doc │ │ │ │ └── dist_mem_gen_v8_0_changelog.txt │ │ │ │ ├── imen.dcp │ │ │ │ ├── imen.mif │ │ │ │ ├── imen.veo │ │ │ │ ├── imen.vho │ │ │ │ ├── imen.xci │ │ │ │ ├── imen.xml │ │ │ │ ├── imen_ooc.xdc │ │ │ │ ├── imen_sim_netlist.v │ │ │ │ ├── imen_sim_netlist.vhdl │ │ │ │ ├── imen_stub.v │ │ │ │ ├── imen_stub.vhdl │ │ │ │ ├── sim │ │ │ │ └── imen.v │ │ │ │ └── synth │ │ │ │ └── imen.vhd │ │ │ └── new │ │ │ ├── CLZ.v │ │ │ ├── CP0.v │ │ │ ├── DIV.v │ │ │ ├── DIVU.v │ │ │ ├── Dram.v │ │ │ ├── Ext16.v │ │ │ ├── Ext5.v │ │ │ ├── Ext8.v │ │ │ ├── MULT.v │ │ │ ├── MUX.v │ │ │ ├── MUX8.v │ │ │ ├── MUX_5bit.v │ │ │ ├── S_Ext16.v │ │ │ ├── S_Ext18.v │ │ │ ├── S_Ext8.v │ │ │ ├── alu.v │ │ │ ├── cpu.v │ │ │ ├── multu.v │ │ │ ├── pcreg.v │ │ │ ├── regfile.v │ │ │ ├── sccomp_dataflow.v │ │ │ └── seg7x16.v │ └── cpu_54.xpr └── cpu_54实验报告 │ ├── 54条指令CPU实验报告_1952650_陈子翔.docx │ ├── 54条指令CPU实验报告_1952650_陈子翔.pdf │ ├── My数据通路.xlsx │ ├── 仿真图 │ ├── CPU下板.jpg │ ├── CPU后仿真.jpg │ ├── QQ图片20210708212513.png │ ├── QQ图片20210708212626.png │ ├── QQ图片20210708212845.png │ ├── QQ图片20210708212921.png │ ├── QQ图片20210708213100.png │ └── 前仿真.png │ ├── 数据通路图 │ ├── 32CLZ.jpg │ ├── 33DIVU.jpg │ ├── 34ERET.jpg │ ├── 35JALR.jpg │ ├── 36LB.jpg │ ├── 37LBU.jpg │ ├── 38LHU.jpg │ ├── 39SB.jpg │ ├── 40SH.jpg │ ├── 41LH.jpg │ ├── 42MFC0.jpg │ ├── 43MFHI.jpg │ ├── 44MFLO.jpg │ ├── 45MTC0.jpg │ ├── 46MTHI.jpg │ ├── 47MTLO.jpg │ ├── 48MUL.jpg │ ├── 49MULTU.jpg │ ├── 50SYSCALL.jpg │ ├── 51TEQ.jpg │ ├── 52BGEZ.jpg │ ├── 53BREAK.jpg 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