├── .gitignore ├── .holpath ├── LICENSE ├── README.md ├── ag32 ├── Holmakefile ├── ag32AddAcceleratorScript.sml ├── ag32EqScript.sml ├── ag32HaltScript.sml ├── ag32MachineScript.sml ├── ag32PaperScript.sml ├── ag32ProgramsScript.sml ├── ag32StepLib.sml ├── cakeml_connection │ ├── Holmakefile │ ├── ag32AssemblerLib.sml │ ├── commonVerilogProofLib.sml │ ├── commonVerilogProofScript.sml │ ├── compiler │ │ ├── Holmakefile │ │ └── cakeVerilogProofScript.sml │ ├── helloVerilogProofScript.sml │ ├── opentheory-reader │ │ ├── Holmakefile │ │ ├── README.md │ │ ├── articles │ │ │ ├── base.art │ │ │ ├── bool.art │ │ │ ├── real.art │ │ │ └── word.art │ │ └── readerVerilogProofScript.sml │ ├── sortVerilogProofScript.sml │ └── wordcountVerilogProofScript.sml ├── compilation │ ├── Holmakefile │ ├── ag32VerilogPrintLib.sml │ └── ag32VerilogScript.sml ├── ctrl │ ├── run_on_fpga.py │ ├── to_coe.py │ └── to_py.py ├── isa │ ├── Holmakefile │ └── ag32.spec └── verilog_glue │ ├── README.md │ ├── axi_computer_ctrl.v │ ├── cache.sv │ ├── cache_bram.sv │ ├── cache_none.sv │ ├── cache_wrapper.v │ └── processor_wrapper.v ├── compiler ├── GreedyTechMapLib.sml ├── Holmakefile ├── LECLib.sml ├── LECScript.sml ├── PreCompilerProofScript.sml ├── PreCompilerScript.sml ├── RTLBlasterProofScript.sml ├── RTLBlasterScript.sml ├── RTLCompilerProofScript.sml ├── RTLCompilerScript.sml ├── RTLDeterminizerProofScript.sml ├── RTLDeterminizerScript.sml ├── RTLExamplesScript.sml ├── RTLLib.sml ├── RTLOptimizerScript.sml ├── RTLPPLib.sml ├── RTLPrintLib.sml ├── RTLPropsScript.sml ├── RTLScript.sml ├── RTLStatsScript.sml ├── RTLSyntax.sig ├── RTLSyntax.sml ├── RTLTypeScript.sml ├── RTLUnusedRegsScript.sml ├── SMLRTLLib.sml ├── balanced_mapExtraScript.sml ├── compileLib.sml ├── compileScript.sml └── fullCompilerScript.sml ├── examples ├── FSMCircuitsScript.sml ├── Holmakefile ├── avgCircuitScript.sml ├── compilation │ ├── FSMCircuitsCompileScript.sml │ ├── Holmakefile │ ├── avgCircuitCompileScript.sml │ ├── loop.c │ ├── loop.sv │ ├── loopScript.sml │ ├── mixedCircuitCompileScript.sml │ └── pulseCounterCircuitCompileScript.sml ├── mixedCircuitScript.sml └── pulseCounterCircuitScript.sml ├── hardwareMiscScript.sml ├── hardwarePreamble.sml ├── misc ├── old-translator │ ├── Holmakefile │ ├── README.md │ ├── moduleTranslatorScript.sml │ ├── verilogLiftLib.sml │ ├── verilogTranslatorConfigLib.sml │ ├── verilogTranslatorCoreLib.sml │ ├── verilogTranslatorLib.sml │ └── verilogTranslatorScript.sml ├── regexp │ ├── Holmakefile │ ├── README.md │ ├── compilation │ │ ├── Holmakefile │ │ ├── regexpExampleVerilogPrintLib.sml │ │ └── regexpExampleVerilogScript.sml │ └── regexpExampleScript.sml └── semanticstest │ ├── Holmakefile │ ├── README.md │ ├── circuitExampleScript.sml │ └── compilation │ ├── Holmakefile │ └── circuitExampleVerilogScript.sml ├── oracleScript.sml ├── sumExtraScript.sml ├── translator ├── Holmakefile ├── translatorCoreLib.sml ├── translatorExpLib.sml ├── translatorLib.sml ├── translatorScript.sml └── translatorStmLib.sml ├── verilog ├── Holmakefile ├── topological_sortScript.sml ├── verilogMetaScript.sml ├── verilogPrintLib.sml ├── verilogPrintScript.sml ├── verilogScript.sml ├── verilogSortScript.sml ├── verilogSyntax.sig ├── verilogSyntax.sml ├── verilogTypeCheckerScript.sml ├── verilogTypeScript.sml └── verilogWriteCheckerScript.sml ├── verilog_parser ├── .gitignore ├── Holmakefile ├── Makefile ├── README.md ├── Verilog.cf ├── buildTree.hs └── test_cases │ ├── bad │ ├── case_full.sv │ ├── case_in_if.sv │ ├── case_missing.sv │ ├── comb_actually_seq.sv │ ├── comb_inter_cycle.sv │ ├── comb_intra_cycle.sv │ ├── comb_missing_branch.sv │ ├── comb_missing_branch2.sv │ ├── comb_partly_comb.sv │ ├── dynamic_read_comb.sv │ └── dynamic_write_comb.sv │ ├── good │ ├── case_default.sv │ ├── case_ff.sv │ ├── case_overfull.sv │ ├── cava_ex1_fixed.sv │ ├── comb_after.sv │ ├── comb_after_reg.sv │ ├── comb_array.sv │ ├── comb_before.sv │ ├── comb_double_write.sv │ ├── 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