├── SPL
├── stm32f10x_i2c.c
├── stm32f10x_rcc.c
├── stm32f10x_gpio.h
├── stm32f10x_gpio.c
├── stm32f10x_i2c.h
└── stm32f10x_rcc.h
├── MAC_EEPROM.c
├── RFID.c
├── I2C.h
├── EEPROM.c
├── README.md
└── I2C.c
/SPL/stm32f10x_i2c.c:
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https://raw.githubusercontent.com/Catethysis/stm32_i2c/HEAD/SPL/stm32f10x_i2c.c
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/SPL/stm32f10x_rcc.c:
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https://raw.githubusercontent.com/Catethysis/stm32_i2c/HEAD/SPL/stm32f10x_rcc.c
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/MAC_EEPROM.c:
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1 | #include "I2C.h"
2 |
3 | void main()
4 | {
5 | uint8_t MAC_Address[6] = { 0 };
6 |
7 | I2C_init(I2C1, 100000);
8 | delay();
9 | I2C_burst_read(I2C1, 0xA0, 0xFA, 6, MAC_Address);
10 |
11 | while(1);
12 | }
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/RFID.c:
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1 | #include "I2C.h"
2 |
3 | void delay()
4 | {
5 | for(volatile uint16_t del = 0; del<250000; del++);
6 | }
7 |
8 | int main()
9 | {
10 | uint8_t burst_data_write[2] = {0x01, 0x01}, burst_data_read[11] = { 0 };
11 |
12 | I2C_init(I2C1, 100000);
13 | delay();
14 | I2C_RFID_burst_write(I2C1, 0xA0, 2, burst_data_write);
15 | delay();
16 | I2C_RFID_burst_read(I2C1, 0xA0, 11, burst_data_read);
17 |
18 | while(1);
19 | }
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/I2C.h:
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1 | void I2C_init(I2C_TypeDef* I2Cx, uint32_t speed);
2 | void I2C_single_write(I2C_TypeDef* I2Cx, uint8_t HW_address, uint8_t addr, uint8_t data);
3 | void I2C_burst_write(I2C_TypeDef* I2Cx, uint8_t HW_address, uint8_t addr, uint8_t n_data, uint8_t *data);
4 | uint8_t I2C_single_read(I2C_TypeDef* I2Cx, uint8_t HW_address, uint8_t addr);
5 | void I2C_burst_read(I2C_TypeDef* I2Cx, uint8_t HW_address, uint8_t addr, uint8_t n_data, uint8_t *data);
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/EEPROM.c:
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1 | #include "I2C.h"
2 |
3 | void main()
4 | {
5 | uint8_t burst_data_write[5] = {0x24, 0x48, 0x52, 0x59, 0x73}, burst_data_read[6] = { 0 };
6 | uint8_t single_data_read = 0;
7 |
8 | I2C_init(I2C1, 100000);
9 | delay();
10 |
11 | I2C_single_write(I2C1, 0xA0, 0x20, 0x15);
12 | delay();
13 | I2C_burst_write(I2C1, 0xA0, 0x11, 5, burst_data_write);
14 | delay();
15 |
16 | single_data_read = I2C_single_read(I2C1, 0xA0, 0x20);
17 | delay();
18 | I2C_burst_read(I2C1, 0xA0, 0x11, 5, burst_data_read);
19 |
20 | while(1);
21 | }
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/README.md:
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1 | stm32_i2c
2 | =========
3 |
4 | Библиотека функций работы с I2C для STM32F1. Подробнее - http://catethysis.ru/stm32-i2c/
5 |
6 | # Функции
7 | * I2C_init (I2Cx, speed) - инициализирует выбранный модуль I2C с указанной скоростью связи
8 | * I2C_single_write (I2Cx, HW_address, addr, data) - записывает один байт data по адресу addr
9 | * I2C_burst_write (I2Cx, HW_address, addr, n_data, *data) - записывает несколько байт *data, начиная с адреса addr
10 | * I2C_single_read (I2Cx, HW_address, addr) - читает один байт data по адресу addr
11 | * I2C_burst_read (I2Cx, HW_address, addr, n_data, *data) - читает несколько байт *data, начиная с адреса addr
12 |
13 | Функции чтения и записи принимают линию I2C (I2Cx) и адрес устройства (HW_address).
14 |
15 | # Примеры применения
16 | В EEPROM.c - пример работы с EEPROM-памятью: запись/чтение одного байта и массива из нескольких байт.
17 |
18 | MAC_EEPROM.c - чтение 6-байтного MAC-адреса из микросхем памяти типа 24AA02E48 с предзаписанным MAC-адресом.
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/I2C.c:
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1 | #include "stm32f10x_rcc.h"
2 | #include "stm32f10x_gpio.h"
3 | #include "stm32f10x_i2c.h"
4 | #include "I2C.h"
5 |
6 | void I2C_init(I2C_TypeDef* I2Cx, uint32_t speed)
7 | {
8 | RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOB | RCC_APB2Periph_AFIO, ENABLE);
9 | GPIO_InitTypeDef GPIO_InitStructure;
10 | GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz;
11 | GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_OD;
12 | GPIO_InitStructure.GPIO_Pin = GPIO_Pin_6 | GPIO_Pin_7;
13 | GPIO_Init(GPIOB, &GPIO_InitStructure);
14 |
15 | RCC_APB1PeriphClockCmd(I2Cx == I2C1 ? RCC_APB1Periph_I2C1 : RCC_APB1Periph_I2C2, ENABLE);
16 | I2C_InitTypeDef I2C_InitStructure;
17 | I2C_StructInit(&I2C_InitStructure);
18 | I2C_InitStructure.I2C_ClockSpeed = speed;
19 | I2C_InitStructure.I2C_OwnAddress1 = 1;
20 | I2C_InitStructure.I2C_Ack = I2C_Ack_Enable;
21 | I2C_Init(I2Cx, &I2C_InitStructure);
22 | I2C_Cmd(I2Cx, ENABLE);
23 | }
24 |
25 | void I2C_single_write(I2C_TypeDef* I2Cx, uint8_t HW_address, uint8_t addr, uint8_t data)
26 | {
27 | I2C_GenerateSTART(I2Cx, ENABLE);
28 | while(!I2C_CheckEvent(I2Cx, I2C_EVENT_MASTER_MODE_SELECT));
29 | I2C_Send7bitAddress(I2Cx, HW_address, I2C_Direction_Transmitter);
30 | while(!I2C_CheckEvent(I2Cx, I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED));
31 | I2C_SendData(I2Cx, addr);
32 | while(!I2C_CheckEvent(I2Cx, I2C_EVENT_MASTER_BYTE_TRANSMITTED));
33 | I2C_SendData(I2Cx, data);
34 | while(!I2C_CheckEvent(I2Cx, I2C_EVENT_MASTER_BYTE_TRANSMITTED));
35 | I2C_GenerateSTOP(I2Cx, ENABLE);
36 | while(I2C_GetFlagStatus(I2Cx, I2C_FLAG_BUSY));
37 | }
38 |
39 | void I2C_burst_write(I2C_TypeDef* I2Cx, uint8_t HW_address, uint8_t addr, uint8_t n_data, uint8_t *data)
40 | {
41 | I2C_GenerateSTART(I2Cx, ENABLE);
42 | while(!I2C_CheckEvent(I2Cx, I2C_EVENT_MASTER_MODE_SELECT));
43 | I2C_Send7bitAddress(I2Cx, HW_address, I2C_Direction_Transmitter);
44 | while(!I2C_CheckEvent(I2Cx, I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED));
45 | I2C_SendData(I2Cx, addr);
46 | while(!I2C_CheckEvent(I2Cx, I2C_EVENT_MASTER_BYTE_TRANSMITTED));
47 | while(n_data--) {
48 | I2C_SendData(I2Cx, *data++);
49 | while(!I2C_CheckEvent(I2Cx, I2C_EVENT_MASTER_BYTE_TRANSMITTED));
50 | }
51 | I2C_GenerateSTOP(I2Cx, ENABLE);
52 | while(I2C_GetFlagStatus(I2Cx, I2C_FLAG_BUSY));
53 | }
54 |
55 | uint8_t I2C_single_read(I2C_TypeDef* I2Cx, uint8_t HW_address, uint8_t addr)
56 | {
57 | uint8_t data;
58 | while(I2C_GetFlagStatus(I2Cx, I2C_FLAG_BUSY));
59 | I2C_GenerateSTART(I2Cx, ENABLE);
60 | while(!I2C_CheckEvent(I2Cx, I2C_EVENT_MASTER_MODE_SELECT));
61 | I2C_Send7bitAddress(I2Cx, HW_address, I2C_Direction_Transmitter);
62 | while(!I2C_CheckEvent(I2Cx, I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED));
63 | I2C_SendData(I2Cx, addr);
64 | while(!I2C_CheckEvent(I2Cx, I2C_EVENT_MASTER_BYTE_TRANSMITTED));
65 | I2C_GenerateSTART(I2Cx, ENABLE);
66 | while(!I2C_CheckEvent(I2Cx, I2C_EVENT_MASTER_MODE_SELECT));
67 | I2C_Send7bitAddress(I2Cx, HW_address, I2C_Direction_Receiver);
68 | while(!I2C_CheckEvent(I2Cx,I2C_EVENT_MASTER_BYTE_RECEIVED));
69 | data = I2C_ReceiveData(I2Cx);
70 | while(!I2C_CheckEvent(I2Cx, I2C_EVENT_MASTER_BYTE_RECEIVED));
71 | I2C_AcknowledgeConfig(I2Cx, DISABLE);
72 | I2C_GenerateSTOP(I2Cx, ENABLE);
73 | while(I2C_GetFlagStatus(I2Cx, I2C_FLAG_BUSY));
74 | return data;
75 | }
76 |
77 | void I2C_burst_read(I2C_TypeDef* I2Cx, uint8_t HW_address, uint8_t addr, uint8_t n_data, uint8_t *data)
78 | {
79 | while(I2C_GetFlagStatus(I2Cx, I2C_FLAG_BUSY));
80 | I2C_GenerateSTART(I2Cx, ENABLE);
81 | while(!I2C_CheckEvent(I2Cx, I2C_EVENT_MASTER_MODE_SELECT));
82 | I2C_Send7bitAddress(I2Cx, HW_address, I2C_Direction_Transmitter);
83 | while(!I2C_CheckEvent(I2Cx, I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED));
84 | I2C_SendData(I2Cx, addr);
85 | while(!I2C_CheckEvent(I2Cx, I2C_EVENT_MASTER_BYTE_TRANSMITTED));
86 | I2C_GenerateSTOP(I2Cx, ENABLE);
87 | I2C_GenerateSTART(I2Cx, ENABLE);
88 | while(!I2C_CheckEvent(I2Cx, I2C_EVENT_MASTER_MODE_SELECT));
89 | I2C_Send7bitAddress(I2Cx, HW_address, I2C_Direction_Receiver);
90 | while (!I2C_CheckEvent(I2Cx, I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED));
91 | I2C_AcknowledgeConfig(I2Cx, ENABLE);
92 | while(n_data--) {
93 | if(!n_data) I2C_AcknowledgeConfig(I2Cx, DISABLE);
94 | while (!I2C_CheckEvent(I2Cx, I2C_EVENT_MASTER_BYTE_RECEIVED));
95 | *data++ = I2C_ReceiveData(I2Cx);
96 | }
97 | I2C_AcknowledgeConfig(I2Cx, DISABLE);
98 | I2C_GenerateSTOP(I2Cx, ENABLE);
99 | while(I2C_GetFlagStatus(I2Cx, I2C_FLAG_BUSY));
100 | }
101 |
102 | void I2C_RFID_burst_write(I2C_TypeDef* I2Cx, uint8_t HW_address, uint8_t n_data, uint8_t *data)
103 | {
104 | I2C_GenerateSTART(I2Cx, ENABLE);
105 | while(!I2C_CheckEvent(I2Cx, I2C_EVENT_MASTER_MODE_SELECT));
106 | I2C_Send7bitAddress(I2Cx, HW_address, I2C_Direction_Transmitter);
107 | while(!I2C_CheckEvent(I2Cx, I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED));
108 | while(n_data--) {
109 | I2C_SendData(I2Cx, *data++);
110 | while(!I2C_CheckEvent(I2Cx, I2C_EVENT_MASTER_BYTE_TRANSMITTED));
111 | }
112 | I2C_GenerateSTOP(I2Cx, ENABLE);
113 | while(I2C_GetFlagStatus(I2Cx, I2C_FLAG_BUSY));
114 | }
115 |
116 | void I2C_RFID_burst_read(I2C_TypeDef* I2Cx, uint8_t HW_address, uint8_t n_data, uint8_t *data)
117 | {
118 | while(I2C_GetFlagStatus(I2Cx, I2C_FLAG_BUSY));
119 | I2C_GenerateSTART(I2Cx, ENABLE);
120 | while(!I2C_CheckEvent(I2Cx, I2C_EVENT_MASTER_MODE_SELECT));
121 | I2C_Send7bitAddress(I2Cx, HW_address, I2C_Direction_Receiver);
122 | while (!I2C_CheckEvent(I2Cx, I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED));
123 | I2C_AcknowledgeConfig(I2Cx, ENABLE);
124 | while(n_data--) {
125 | if(!n_data) I2C_AcknowledgeConfig(I2Cx, DISABLE);
126 | while (!I2C_CheckEvent(I2Cx, I2C_EVENT_MASTER_BYTE_RECEIVED));
127 | *data++ = I2C_ReceiveData(I2Cx);
128 | }
129 | I2C_AcknowledgeConfig(I2Cx, DISABLE);
130 | I2C_GenerateSTOP(I2Cx, ENABLE);
131 | while(I2C_GetFlagStatus(I2Cx, I2C_FLAG_BUSY));
132 | }
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/SPL/stm32f10x_gpio.h:
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1 | /**
2 | ******************************************************************************
3 | * @file stm32f10x_gpio.h
4 | * @author MCD Application Team
5 | * @version V3.3.0
6 | * @date 04/16/2010
7 | * @brief This file contains all the functions prototypes for the GPIO
8 | * firmware library.
9 | ******************************************************************************
10 | * @copy
11 | *
12 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
13 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
14 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
15 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
16 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
17 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
18 | *
19 | * © COPYRIGHT 2010 STMicroelectronics
20 | */
21 |
22 | /* Define to prevent recursive inclusion -------------------------------------*/
23 | #ifndef __STM32F10x_GPIO_H
24 | #define __STM32F10x_GPIO_H
25 |
26 | #ifdef __cplusplus
27 | extern "C" {
28 | #endif
29 |
30 | /* Includes ------------------------------------------------------------------*/
31 | #include "stm32f10x.h"
32 |
33 | /** @addtogroup STM32F10x_StdPeriph_Driver
34 | * @{
35 | */
36 |
37 | /** @addtogroup GPIO
38 | * @{
39 | */
40 |
41 | /** @defgroup GPIO_Exported_Types
42 | * @{
43 | */
44 |
45 | #define IS_GPIO_ALL_PERIPH(PERIPH) (((PERIPH) == GPIOA) || \
46 | ((PERIPH) == GPIOB) || \
47 | ((PERIPH) == GPIOC) || \
48 | ((PERIPH) == GPIOD) || \
49 | ((PERIPH) == GPIOE) || \
50 | ((PERIPH) == GPIOF) || \
51 | ((PERIPH) == GPIOG))
52 |
53 | /**
54 | * @brief Output Maximum frequency selection
55 | */
56 |
57 | typedef enum
58 | {
59 | GPIO_Speed_10MHz = 1,
60 | GPIO_Speed_2MHz,
61 | GPIO_Speed_50MHz
62 | }GPIOSpeed_TypeDef;
63 | #define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_Speed_10MHz) || ((SPEED) == GPIO_Speed_2MHz) || \
64 | ((SPEED) == GPIO_Speed_50MHz))
65 |
66 | /**
67 | * @brief Configuration Mode enumeration
68 | */
69 |
70 | typedef enum
71 | { GPIO_Mode_AIN = 0x0,
72 | GPIO_Mode_IN_FLOATING = 0x04,
73 | GPIO_Mode_IPD = 0x28,
74 | GPIO_Mode_IPU = 0x48,
75 | GPIO_Mode_Out_OD = 0x14,
76 | GPIO_Mode_Out_PP = 0x10,
77 | GPIO_Mode_AF_OD = 0x1C,
78 | GPIO_Mode_AF_PP = 0x18
79 | }GPIOMode_TypeDef;
80 |
81 | #define IS_GPIO_MODE(MODE) (((MODE) == GPIO_Mode_AIN) || ((MODE) == GPIO_Mode_IN_FLOATING) || \
82 | ((MODE) == GPIO_Mode_IPD) || ((MODE) == GPIO_Mode_IPU) || \
83 | ((MODE) == GPIO_Mode_Out_OD) || ((MODE) == GPIO_Mode_Out_PP) || \
84 | ((MODE) == GPIO_Mode_AF_OD) || ((MODE) == GPIO_Mode_AF_PP))
85 |
86 | /**
87 | * @brief GPIO Init structure definition
88 | */
89 |
90 | typedef struct
91 | {
92 | uint16_t GPIO_Pin; /*!< Specifies the GPIO pins to be configured.
93 | This parameter can be any value of @ref GPIO_pins_define */
94 |
95 | GPIOSpeed_TypeDef GPIO_Speed; /*!< Specifies the speed for the selected pins.
96 | This parameter can be a value of @ref GPIOSpeed_TypeDef */
97 |
98 | GPIOMode_TypeDef GPIO_Mode; /*!< Specifies the operating mode for the selected pins.
99 | This parameter can be a value of @ref GPIOMode_TypeDef */
100 | }GPIO_InitTypeDef;
101 |
102 |
103 | /**
104 | * @brief Bit_SET and Bit_RESET enumeration
105 | */
106 |
107 | typedef enum
108 | { Bit_RESET = 0,
109 | Bit_SET
110 | }BitAction;
111 |
112 | #define IS_GPIO_BIT_ACTION(ACTION) (((ACTION) == Bit_RESET) || ((ACTION) == Bit_SET))
113 |
114 | /**
115 | * @}
116 | */
117 |
118 | /** @defgroup GPIO_Exported_Constants
119 | * @{
120 | */
121 |
122 | /** @defgroup GPIO_pins_define
123 | * @{
124 | */
125 |
126 | #define GPIO_Pin_0 ((uint16_t)0x0001) /*!< Pin 0 selected */
127 | #define GPIO_Pin_1 ((uint16_t)0x0002) /*!< Pin 1 selected */
128 | #define GPIO_Pin_2 ((uint16_t)0x0004) /*!< Pin 2 selected */
129 | #define GPIO_Pin_3 ((uint16_t)0x0008) /*!< Pin 3 selected */
130 | #define GPIO_Pin_4 ((uint16_t)0x0010) /*!< Pin 4 selected */
131 | #define GPIO_Pin_5 ((uint16_t)0x0020) /*!< Pin 5 selected */
132 | #define GPIO_Pin_6 ((uint16_t)0x0040) /*!< Pin 6 selected */
133 | #define GPIO_Pin_7 ((uint16_t)0x0080) /*!< Pin 7 selected */
134 | #define GPIO_Pin_8 ((uint16_t)0x0100) /*!< Pin 8 selected */
135 | #define GPIO_Pin_9 ((uint16_t)0x0200) /*!< Pin 9 selected */
136 | #define GPIO_Pin_10 ((uint16_t)0x0400) /*!< Pin 10 selected */
137 | #define GPIO_Pin_11 ((uint16_t)0x0800) /*!< Pin 11 selected */
138 | #define GPIO_Pin_12 ((uint16_t)0x1000) /*!< Pin 12 selected */
139 | #define GPIO_Pin_13 ((uint16_t)0x2000) /*!< Pin 13 selected */
140 | #define GPIO_Pin_14 ((uint16_t)0x4000) /*!< Pin 14 selected */
141 | #define GPIO_Pin_15 ((uint16_t)0x8000) /*!< Pin 15 selected */
142 | #define GPIO_Pin_All ((uint16_t)0xFFFF) /*!< All pins selected */
143 |
144 | #define IS_GPIO_PIN(PIN) ((((PIN) & (uint16_t)0x00) == 0x00) && ((PIN) != (uint16_t)0x00))
145 |
146 | #define IS_GET_GPIO_PIN(PIN) (((PIN) == GPIO_Pin_0) || \
147 | ((PIN) == GPIO_Pin_1) || \
148 | ((PIN) == GPIO_Pin_2) || \
149 | ((PIN) == GPIO_Pin_3) || \
150 | ((PIN) == GPIO_Pin_4) || \
151 | ((PIN) == GPIO_Pin_5) || \
152 | ((PIN) == GPIO_Pin_6) || \
153 | ((PIN) == GPIO_Pin_7) || \
154 | ((PIN) == GPIO_Pin_8) || \
155 | ((PIN) == GPIO_Pin_9) || \
156 | ((PIN) == GPIO_Pin_10) || \
157 | ((PIN) == GPIO_Pin_11) || \
158 | ((PIN) == GPIO_Pin_12) || \
159 | ((PIN) == GPIO_Pin_13) || \
160 | ((PIN) == GPIO_Pin_14) || \
161 | ((PIN) == GPIO_Pin_15))
162 |
163 | /**
164 | * @}
165 | */
166 |
167 | /** @defgroup GPIO_Remap_define
168 | * @{
169 | */
170 |
171 | #define GPIO_Remap_SPI1 ((uint32_t)0x00000001) /*!< SPI1 Alternate Function mapping */
172 | #define GPIO_Remap_I2C1 ((uint32_t)0x00000002) /*!< I2C1 Alternate Function mapping */
173 | #define GPIO_Remap_USART1 ((uint32_t)0x00000004) /*!< USART1 Alternate Function mapping */
174 | #define GPIO_Remap_USART2 ((uint32_t)0x00000008) /*!< USART2 Alternate Function mapping */
175 | #define GPIO_PartialRemap_USART3 ((uint32_t)0x00140010) /*!< USART3 Partial Alternate Function mapping */
176 | #define GPIO_FullRemap_USART3 ((uint32_t)0x00140030) /*!< USART3 Full Alternate Function mapping */
177 | #define GPIO_PartialRemap_TIM1 ((uint32_t)0x00160040) /*!< TIM1 Partial Alternate Function mapping */
178 | #define GPIO_FullRemap_TIM1 ((uint32_t)0x001600C0) /*!< TIM1 Full Alternate Function mapping */
179 | #define GPIO_PartialRemap1_TIM2 ((uint32_t)0x00180100) /*!< TIM2 Partial1 Alternate Function mapping */
180 | #define GPIO_PartialRemap2_TIM2 ((uint32_t)0x00180200) /*!< TIM2 Partial2 Alternate Function mapping */
181 | #define GPIO_FullRemap_TIM2 ((uint32_t)0x00180300) /*!< TIM2 Full Alternate Function mapping */
182 | #define GPIO_PartialRemap_TIM3 ((uint32_t)0x001A0800) /*!< TIM3 Partial Alternate Function mapping */
183 | #define GPIO_FullRemap_TIM3 ((uint32_t)0x001A0C00) /*!< TIM3 Full Alternate Function mapping */
184 | #define GPIO_Remap_TIM4 ((uint32_t)0x00001000) /*!< TIM4 Alternate Function mapping */
185 | #define GPIO_Remap1_CAN1 ((uint32_t)0x001D4000) /*!< CAN1 Alternate Function mapping */
186 | #define GPIO_Remap2_CAN1 ((uint32_t)0x001D6000) /*!< CAN1 Alternate Function mapping */
187 | #define GPIO_Remap_PD01 ((uint32_t)0x00008000) /*!< PD01 Alternate Function mapping */
188 | #define GPIO_Remap_TIM5CH4_LSI ((uint32_t)0x00200001) /*!< LSI connected to TIM5 Channel4 input capture for calibration */
189 | #define GPIO_Remap_ADC1_ETRGINJ ((uint32_t)0x00200002) /*!< ADC1 External Trigger Injected Conversion remapping */
190 | #define GPIO_Remap_ADC1_ETRGREG ((uint32_t)0x00200004) /*!< ADC1 External Trigger Regular Conversion remapping */
191 | #define GPIO_Remap_ADC2_ETRGINJ ((uint32_t)0x00200008) /*!< ADC2 External Trigger Injected Conversion remapping */
192 | #define GPIO_Remap_ADC2_ETRGREG ((uint32_t)0x00200010) /*!< ADC2 External Trigger Regular Conversion remapping */
193 | #define GPIO_Remap_ETH ((uint32_t)0x00200020) /*!< Ethernet remapping (only for Connectivity line devices) */
194 | #define GPIO_Remap_CAN2 ((uint32_t)0x00200040) /*!< CAN2 remapping (only for Connectivity line devices) */
195 | #define GPIO_Remap_SWJ_NoJTRST ((uint32_t)0x00300100) /*!< Full SWJ Enabled (JTAG-DP + SW-DP) but without JTRST */
196 | #define GPIO_Remap_SWJ_JTAGDisable ((uint32_t)0x00300200) /*!< JTAG-DP Disabled and SW-DP Enabled */
197 | #define GPIO_Remap_SWJ_Disable ((uint32_t)0x00300400) /*!< Full SWJ Disabled (JTAG-DP + SW-DP) */
198 | #define GPIO_Remap_SPI3 ((uint32_t)0x00201000) /*!< SPI3/I2S3 Alternate Function mapping (only for Connectivity line devices) */
199 | #define GPIO_Remap_TIM2ITR1_PTP_SOF ((uint32_t)0x00202000) /*!< Ethernet PTP output or USB OTG SOF (Start of Frame) connected
200 | to TIM2 Internal Trigger 1 for calibration
201 | (only for Connectivity line devices) */
202 | #define GPIO_Remap_PTP_PPS ((uint32_t)0x00204000) /*!< Ethernet MAC PPS_PTS output on PB05 (only for Connectivity line devices) */
203 |
204 | #define GPIO_Remap_TIM15 ((uint32_t)0x80000001) /*!< TIM15 Alternate Function mapping (only for Value line devices) */
205 | #define GPIO_Remap_TIM16 ((uint32_t)0x80000002) /*!< TIM16 Alternate Function mapping (only for Value line devices) */
206 | #define GPIO_Remap_TIM17 ((uint32_t)0x80000004) /*!< TIM17 Alternate Function mapping (only for Value line devices) */
207 | #define GPIO_Remap_CEC ((uint32_t)0x80000008) /*!< CEC Alternate Function mapping (only for Value line devices) */
208 | #define GPIO_Remap_TIM1_DMA ((uint32_t)0x80000010) /*!< TIM1 DMA requests mapping (only for Value line devices) */
209 |
210 | #define GPIO_Remap_TIM9 ((uint32_t)0x80000020) /*!< TIM9 Alternate Function mapping (only for XL-density devices) */
211 | #define GPIO_Remap_TIM10 ((uint32_t)0x80000040) /*!< TIM10 Alternate Function mapping (only for XL-density devices) */
212 | #define GPIO_Remap_TIM11 ((uint32_t)0x80000080) /*!< TIM11 Alternate Function mapping (only for XL-density devices) */
213 | #define GPIO_Remap_TIM13 ((uint32_t)0x80000100) /*!< TIM13 Alternate Function mapping (only for XL-density devices) */
214 | #define GPIO_Remap_TIM14 ((uint32_t)0x80000200) /*!< TIM14 Alternate Function mapping (only for XL-density devices) */
215 | #define GPIO_Remap_FSMC_NADV ((uint32_t)0x80000400) /*!< FSMC_NADV Alternate Function mapping (only for XL-density devices) */
216 |
217 |
218 | #define IS_GPIO_REMAP(REMAP) (((REMAP) == GPIO_Remap_SPI1) || ((REMAP) == GPIO_Remap_I2C1) || \
219 | ((REMAP) == GPIO_Remap_USART1) || ((REMAP) == GPIO_Remap_USART2) || \
220 | ((REMAP) == GPIO_PartialRemap_USART3) || ((REMAP) == GPIO_FullRemap_USART3) || \
221 | ((REMAP) == GPIO_PartialRemap_TIM1) || ((REMAP) == GPIO_FullRemap_TIM1) || \
222 | ((REMAP) == GPIO_PartialRemap1_TIM2) || ((REMAP) == GPIO_PartialRemap2_TIM2) || \
223 | ((REMAP) == GPIO_FullRemap_TIM2) || ((REMAP) == GPIO_PartialRemap_TIM3) || \
224 | ((REMAP) == GPIO_FullRemap_TIM3) || ((REMAP) == GPIO_Remap_TIM4) || \
225 | ((REMAP) == GPIO_Remap1_CAN1) || ((REMAP) == GPIO_Remap2_CAN1) || \
226 | ((REMAP) == GPIO_Remap_PD01) || ((REMAP) == GPIO_Remap_TIM5CH4_LSI) || \
227 | ((REMAP) == GPIO_Remap_ADC1_ETRGINJ) ||((REMAP) == GPIO_Remap_ADC1_ETRGREG) || \
228 | ((REMAP) == GPIO_Remap_ADC2_ETRGINJ) ||((REMAP) == GPIO_Remap_ADC2_ETRGREG) || \
229 | ((REMAP) == GPIO_Remap_ETH) ||((REMAP) == GPIO_Remap_CAN2) || \
230 | ((REMAP) == GPIO_Remap_SWJ_NoJTRST) || ((REMAP) == GPIO_Remap_SWJ_JTAGDisable) || \
231 | ((REMAP) == GPIO_Remap_SWJ_Disable)|| ((REMAP) == GPIO_Remap_SPI3) || \
232 | ((REMAP) == GPIO_Remap_TIM2ITR1_PTP_SOF) || ((REMAP) == GPIO_Remap_PTP_PPS) || \
233 | ((REMAP) == GPIO_Remap_TIM15) || ((REMAP) == GPIO_Remap_TIM16) || \
234 | ((REMAP) == GPIO_Remap_TIM17) || ((REMAP) == GPIO_Remap_CEC) || \
235 | ((REMAP) == GPIO_Remap_TIM1_DMA) || ((REMAP) == GPIO_Remap_TIM9) || \
236 | ((REMAP) == GPIO_Remap_TIM10) || ((REMAP) == GPIO_Remap_TIM11) || \
237 | ((REMAP) == GPIO_Remap_TIM13) || ((REMAP) == GPIO_Remap_TIM14) || \
238 | ((REMAP) == GPIO_Remap_FSMC_NADV))
239 |
240 | /**
241 | * @}
242 | */
243 |
244 | /** @defgroup GPIO_Port_Sources
245 | * @{
246 | */
247 |
248 | #define GPIO_PortSourceGPIOA ((uint8_t)0x00)
249 | #define GPIO_PortSourceGPIOB ((uint8_t)0x01)
250 | #define GPIO_PortSourceGPIOC ((uint8_t)0x02)
251 | #define GPIO_PortSourceGPIOD ((uint8_t)0x03)
252 | #define GPIO_PortSourceGPIOE ((uint8_t)0x04)
253 | #define GPIO_PortSourceGPIOF ((uint8_t)0x05)
254 | #define GPIO_PortSourceGPIOG ((uint8_t)0x06)
255 | #define IS_GPIO_EVENTOUT_PORT_SOURCE(PORTSOURCE) (((PORTSOURCE) == GPIO_PortSourceGPIOA) || \
256 | ((PORTSOURCE) == GPIO_PortSourceGPIOB) || \
257 | ((PORTSOURCE) == GPIO_PortSourceGPIOC) || \
258 | ((PORTSOURCE) == GPIO_PortSourceGPIOD) || \
259 | ((PORTSOURCE) == GPIO_PortSourceGPIOE))
260 |
261 | #define IS_GPIO_EXTI_PORT_SOURCE(PORTSOURCE) (((PORTSOURCE) == GPIO_PortSourceGPIOA) || \
262 | ((PORTSOURCE) == GPIO_PortSourceGPIOB) || \
263 | ((PORTSOURCE) == GPIO_PortSourceGPIOC) || \
264 | ((PORTSOURCE) == GPIO_PortSourceGPIOD) || \
265 | ((PORTSOURCE) == GPIO_PortSourceGPIOE) || \
266 | ((PORTSOURCE) == GPIO_PortSourceGPIOF) || \
267 | ((PORTSOURCE) == GPIO_PortSourceGPIOG))
268 |
269 | /**
270 | * @}
271 | */
272 |
273 | /** @defgroup GPIO_Pin_sources
274 | * @{
275 | */
276 |
277 | #define GPIO_PinSource0 ((uint8_t)0x00)
278 | #define GPIO_PinSource1 ((uint8_t)0x01)
279 | #define GPIO_PinSource2 ((uint8_t)0x02)
280 | #define GPIO_PinSource3 ((uint8_t)0x03)
281 | #define GPIO_PinSource4 ((uint8_t)0x04)
282 | #define GPIO_PinSource5 ((uint8_t)0x05)
283 | #define GPIO_PinSource6 ((uint8_t)0x06)
284 | #define GPIO_PinSource7 ((uint8_t)0x07)
285 | #define GPIO_PinSource8 ((uint8_t)0x08)
286 | #define GPIO_PinSource9 ((uint8_t)0x09)
287 | #define GPIO_PinSource10 ((uint8_t)0x0A)
288 | #define GPIO_PinSource11 ((uint8_t)0x0B)
289 | #define GPIO_PinSource12 ((uint8_t)0x0C)
290 | #define GPIO_PinSource13 ((uint8_t)0x0D)
291 | #define GPIO_PinSource14 ((uint8_t)0x0E)
292 | #define GPIO_PinSource15 ((uint8_t)0x0F)
293 |
294 | #define IS_GPIO_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == GPIO_PinSource0) || \
295 | ((PINSOURCE) == GPIO_PinSource1) || \
296 | ((PINSOURCE) == GPIO_PinSource2) || \
297 | ((PINSOURCE) == GPIO_PinSource3) || \
298 | ((PINSOURCE) == GPIO_PinSource4) || \
299 | ((PINSOURCE) == GPIO_PinSource5) || \
300 | ((PINSOURCE) == GPIO_PinSource6) || \
301 | ((PINSOURCE) == GPIO_PinSource7) || \
302 | ((PINSOURCE) == GPIO_PinSource8) || \
303 | ((PINSOURCE) == GPIO_PinSource9) || \
304 | ((PINSOURCE) == GPIO_PinSource10) || \
305 | ((PINSOURCE) == GPIO_PinSource11) || \
306 | ((PINSOURCE) == GPIO_PinSource12) || \
307 | ((PINSOURCE) == GPIO_PinSource13) || \
308 | ((PINSOURCE) == GPIO_PinSource14) || \
309 | ((PINSOURCE) == GPIO_PinSource15))
310 |
311 | /**
312 | * @}
313 | */
314 |
315 | /** @defgroup Ethernet_Media_Interface
316 | * @{
317 | */
318 | #define GPIO_ETH_MediaInterface_MII ((u32)0x00000000)
319 | #define GPIO_ETH_MediaInterface_RMII ((u32)0x00000001)
320 |
321 | #define IS_GPIO_ETH_MEDIA_INTERFACE(INTERFACE) (((INTERFACE) == GPIO_ETH_MediaInterface_MII) || \
322 | ((INTERFACE) == GPIO_ETH_MediaInterface_RMII))
323 |
324 | /**
325 | * @}
326 | */
327 | /**
328 | * @}
329 | */
330 |
331 | /** @defgroup GPIO_Exported_Macros
332 | * @{
333 | */
334 |
335 | /**
336 | * @}
337 | */
338 |
339 | /** @defgroup GPIO_Exported_Functions
340 | * @{
341 | */
342 |
343 | void GPIO_DeInit(GPIO_TypeDef* GPIOx);
344 | void GPIO_AFIODeInit(void);
345 | void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct);
346 | void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct);
347 | uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
348 | uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx);
349 | uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
350 | uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx);
351 | void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
352 | void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
353 | void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal);
354 | void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal);
355 | void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
356 | void GPIO_EventOutputConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource);
357 | void GPIO_EventOutputCmd(FunctionalState NewState);
358 | void GPIO_PinRemapConfig(uint32_t GPIO_Remap, FunctionalState NewState);
359 | void GPIO_EXTILineConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource);
360 | void GPIO_ETH_MediaInterfaceConfig(uint32_t GPIO_ETH_MediaInterface);
361 |
362 | #ifdef __cplusplus
363 | }
364 | #endif
365 |
366 | #endif /* __STM32F10x_GPIO_H */
367 | /**
368 | * @}
369 | */
370 |
371 | /**
372 | * @}
373 | */
374 |
375 | /**
376 | * @}
377 | */
378 |
379 | /******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
380 |
--------------------------------------------------------------------------------
/SPL/stm32f10x_gpio.c:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file stm32f10x_gpio.c
4 | * @author MCD Application Team
5 | * @version V3.3.0
6 | * @date 04/16/2010
7 | * @brief This file provides all the GPIO firmware functions.
8 | ******************************************************************************
9 | * @copy
10 | *
11 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
12 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
13 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
14 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
15 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
16 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
17 | *
18 | * © COPYRIGHT 2010 STMicroelectronics
19 | */
20 |
21 | /* Includes ------------------------------------------------------------------*/
22 | #include "stm32f10x_gpio.h"
23 | #include "stm32f10x_rcc.h"
24 |
25 | /** @addtogroup STM32F10x_StdPeriph_Driver
26 | * @{
27 | */
28 |
29 | /** @defgroup GPIO
30 | * @brief GPIO driver modules
31 | * @{
32 | */
33 |
34 | /** @defgroup GPIO_Private_TypesDefinitions
35 | * @{
36 | */
37 |
38 | /**
39 | * @}
40 | */
41 |
42 | /** @defgroup GPIO_Private_Defines
43 | * @{
44 | */
45 |
46 | /* ------------ RCC registers bit address in the alias region ----------------*/
47 | #define AFIO_OFFSET (AFIO_BASE - PERIPH_BASE)
48 |
49 | /* --- EVENTCR Register -----*/
50 |
51 | /* Alias word address of EVOE bit */
52 | #define EVCR_OFFSET (AFIO_OFFSET + 0x00)
53 | #define EVOE_BitNumber ((uint8_t)0x07)
54 | #define EVCR_EVOE_BB (PERIPH_BB_BASE + (EVCR_OFFSET * 32) + (EVOE_BitNumber * 4))
55 |
56 |
57 | /* --- MAPR Register ---*/
58 | /* Alias word address of MII_RMII_SEL bit */
59 | #define MAPR_OFFSET (AFIO_OFFSET + 0x04)
60 | #define MII_RMII_SEL_BitNumber ((u8)0x17)
61 | #define MAPR_MII_RMII_SEL_BB (PERIPH_BB_BASE + (MAPR_OFFSET * 32) + (MII_RMII_SEL_BitNumber * 4))
62 |
63 |
64 | #define EVCR_PORTPINCONFIG_MASK ((uint16_t)0xFF80)
65 | #define LSB_MASK ((uint16_t)0xFFFF)
66 | #define DBGAFR_POSITION_MASK ((uint32_t)0x000F0000)
67 | #define DBGAFR_SWJCFG_MASK ((uint32_t)0xF0FFFFFF)
68 | #define DBGAFR_LOCATION_MASK ((uint32_t)0x00200000)
69 | #define DBGAFR_NUMBITS_MASK ((uint32_t)0x00100000)
70 | /**
71 | * @}
72 | */
73 |
74 | /** @defgroup GPIO_Private_Macros
75 | * @{
76 | */
77 |
78 | /**
79 | * @}
80 | */
81 |
82 | /** @defgroup GPIO_Private_Variables
83 | * @{
84 | */
85 |
86 | /**
87 | * @}
88 | */
89 |
90 | /** @defgroup GPIO_Private_FunctionPrototypes
91 | * @{
92 | */
93 |
94 | /**
95 | * @}
96 | */
97 |
98 | /** @defgroup GPIO_Private_Functions
99 | * @{
100 | */
101 |
102 | /**
103 | * @brief Deinitializes the GPIOx peripheral registers to their default reset values.
104 | * @param GPIOx: where x can be (A..G) to select the GPIO peripheral.
105 | * @retval None
106 | */
107 | void GPIO_DeInit(GPIO_TypeDef* GPIOx)
108 | {
109 | /* Check the parameters */
110 | assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
111 |
112 | if (GPIOx == GPIOA)
113 | {
114 | RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOA, ENABLE);
115 | RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOA, DISABLE);
116 | }
117 | else if (GPIOx == GPIOB)
118 | {
119 | RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOB, ENABLE);
120 | RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOB, DISABLE);
121 | }
122 | else if (GPIOx == GPIOC)
123 | {
124 | RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOC, ENABLE);
125 | RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOC, DISABLE);
126 | }
127 | else if (GPIOx == GPIOD)
128 | {
129 | RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOD, ENABLE);
130 | RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOD, DISABLE);
131 | }
132 | else if (GPIOx == GPIOE)
133 | {
134 | RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOE, ENABLE);
135 | RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOE, DISABLE);
136 | }
137 | else if (GPIOx == GPIOF)
138 | {
139 | RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOF, ENABLE);
140 | RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOF, DISABLE);
141 | }
142 | else
143 | {
144 | if (GPIOx == GPIOG)
145 | {
146 | RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOG, ENABLE);
147 | RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOG, DISABLE);
148 | }
149 | }
150 | }
151 |
152 | /**
153 | * @brief Deinitializes the Alternate Functions (remap, event control
154 | * and EXTI configuration) registers to their default reset values.
155 | * @param None
156 | * @retval None
157 | */
158 | void GPIO_AFIODeInit(void)
159 | {
160 | RCC_APB2PeriphResetCmd(RCC_APB2Periph_AFIO, ENABLE);
161 | RCC_APB2PeriphResetCmd(RCC_APB2Periph_AFIO, DISABLE);
162 | }
163 |
164 | /**
165 | * @brief Initializes the GPIOx peripheral according to the specified
166 | * parameters in the GPIO_InitStruct.
167 | * @param GPIOx: where x can be (A..G) to select the GPIO peripheral.
168 | * @param GPIO_InitStruct: pointer to a GPIO_InitTypeDef structure that
169 | * contains the configuration information for the specified GPIO peripheral.
170 | * @retval None
171 | */
172 | void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct)
173 | {
174 | uint32_t currentmode = 0x00, currentpin = 0x00, pinpos = 0x00, pos = 0x00;
175 | uint32_t tmpreg = 0x00, pinmask = 0x00;
176 | /* Check the parameters */
177 | assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
178 | assert_param(IS_GPIO_MODE(GPIO_InitStruct->GPIO_Mode));
179 | assert_param(IS_GPIO_PIN(GPIO_InitStruct->GPIO_Pin));
180 |
181 | /*---------------------------- GPIO Mode Configuration -----------------------*/
182 | currentmode = ((uint32_t)GPIO_InitStruct->GPIO_Mode) & ((uint32_t)0x0F);
183 | if ((((uint32_t)GPIO_InitStruct->GPIO_Mode) & ((uint32_t)0x10)) != 0x00)
184 | {
185 | /* Check the parameters */
186 | assert_param(IS_GPIO_SPEED(GPIO_InitStruct->GPIO_Speed));
187 | /* Output mode */
188 | currentmode |= (uint32_t)GPIO_InitStruct->GPIO_Speed;
189 | }
190 | /*---------------------------- GPIO CRL Configuration ------------------------*/
191 | /* Configure the eight low port pins */
192 | if (((uint32_t)GPIO_InitStruct->GPIO_Pin & ((uint32_t)0x00FF)) != 0x00)
193 | {
194 | tmpreg = GPIOx->CRL;
195 | for (pinpos = 0x00; pinpos < 0x08; pinpos++)
196 | {
197 | pos = ((uint32_t)0x01) << pinpos;
198 | /* Get the port pins position */
199 | currentpin = (GPIO_InitStruct->GPIO_Pin) & pos;
200 | if (currentpin == pos)
201 | {
202 | pos = pinpos << 2;
203 | /* Clear the corresponding low control register bits */
204 | pinmask = ((uint32_t)0x0F) << pos;
205 | tmpreg &= ~pinmask;
206 | /* Write the mode configuration in the corresponding bits */
207 | tmpreg |= (currentmode << pos);
208 | /* Reset the corresponding ODR bit */
209 | if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD)
210 | {
211 | GPIOx->BRR = (((uint32_t)0x01) << pinpos);
212 | }
213 | else
214 | {
215 | /* Set the corresponding ODR bit */
216 | if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU)
217 | {
218 | GPIOx->BSRR = (((uint32_t)0x01) << pinpos);
219 | }
220 | }
221 | }
222 | }
223 | GPIOx->CRL = tmpreg;
224 | }
225 | /*---------------------------- GPIO CRH Configuration ------------------------*/
226 | /* Configure the eight high port pins */
227 | if (GPIO_InitStruct->GPIO_Pin > 0x00FF)
228 | {
229 | tmpreg = GPIOx->CRH;
230 | for (pinpos = 0x00; pinpos < 0x08; pinpos++)
231 | {
232 | pos = (((uint32_t)0x01) << (pinpos + 0x08));
233 | /* Get the port pins position */
234 | currentpin = ((GPIO_InitStruct->GPIO_Pin) & pos);
235 | if (currentpin == pos)
236 | {
237 | pos = pinpos << 2;
238 | /* Clear the corresponding high control register bits */
239 | pinmask = ((uint32_t)0x0F) << pos;
240 | tmpreg &= ~pinmask;
241 | /* Write the mode configuration in the corresponding bits */
242 | tmpreg |= (currentmode << pos);
243 | /* Reset the corresponding ODR bit */
244 | if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD)
245 | {
246 | GPIOx->BRR = (((uint32_t)0x01) << (pinpos + 0x08));
247 | }
248 | /* Set the corresponding ODR bit */
249 | if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU)
250 | {
251 | GPIOx->BSRR = (((uint32_t)0x01) << (pinpos + 0x08));
252 | }
253 | }
254 | }
255 | GPIOx->CRH = tmpreg;
256 | }
257 | }
258 |
259 | /**
260 | * @brief Fills each GPIO_InitStruct member with its default value.
261 | * @param GPIO_InitStruct : pointer to a GPIO_InitTypeDef structure which will
262 | * be initialized.
263 | * @retval None
264 | */
265 | void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct)
266 | {
267 | /* Reset GPIO init structure parameters values */
268 | GPIO_InitStruct->GPIO_Pin = GPIO_Pin_All;
269 | GPIO_InitStruct->GPIO_Speed = GPIO_Speed_2MHz;
270 | GPIO_InitStruct->GPIO_Mode = GPIO_Mode_IN_FLOATING;
271 | }
272 |
273 | /**
274 | * @brief Reads the specified input port pin.
275 | * @param GPIOx: where x can be (A..G) to select the GPIO peripheral.
276 | * @param GPIO_Pin: specifies the port bit to read.
277 | * This parameter can be GPIO_Pin_x where x can be (0..15).
278 | * @retval The input port pin value.
279 | */
280 | uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
281 | {
282 | uint8_t bitstatus = 0x00;
283 |
284 | /* Check the parameters */
285 | assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
286 | assert_param(IS_GET_GPIO_PIN(GPIO_Pin));
287 |
288 | if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)Bit_RESET)
289 | {
290 | bitstatus = (uint8_t)Bit_SET;
291 | }
292 | else
293 | {
294 | bitstatus = (uint8_t)Bit_RESET;
295 | }
296 | return bitstatus;
297 | }
298 |
299 | /**
300 | * @brief Reads the specified GPIO input data port.
301 | * @param GPIOx: where x can be (A..G) to select the GPIO peripheral.
302 | * @retval GPIO input data port value.
303 | */
304 | uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx)
305 | {
306 | /* Check the parameters */
307 | assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
308 |
309 | return ((uint16_t)GPIOx->IDR);
310 | }
311 |
312 | /**
313 | * @brief Reads the specified output data port bit.
314 | * @param GPIOx: where x can be (A..G) to select the GPIO peripheral.
315 | * @param GPIO_Pin: specifies the port bit to read.
316 | * This parameter can be GPIO_Pin_x where x can be (0..15).
317 | * @retval The output port pin value.
318 | */
319 | uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
320 | {
321 | uint8_t bitstatus = 0x00;
322 | /* Check the parameters */
323 | assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
324 | assert_param(IS_GET_GPIO_PIN(GPIO_Pin));
325 |
326 | if ((GPIOx->ODR & GPIO_Pin) != (uint32_t)Bit_RESET)
327 | {
328 | bitstatus = (uint8_t)Bit_SET;
329 | }
330 | else
331 | {
332 | bitstatus = (uint8_t)Bit_RESET;
333 | }
334 | return bitstatus;
335 | }
336 |
337 | /**
338 | * @brief Reads the specified GPIO output data port.
339 | * @param GPIOx: where x can be (A..G) to select the GPIO peripheral.
340 | * @retval GPIO output data port value.
341 | */
342 | uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx)
343 | {
344 | /* Check the parameters */
345 | assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
346 |
347 | return ((uint16_t)GPIOx->ODR);
348 | }
349 |
350 | /**
351 | * @brief Sets the selected data port bits.
352 | * @param GPIOx: where x can be (A..G) to select the GPIO peripheral.
353 | * @param GPIO_Pin: specifies the port bits to be written.
354 | * This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
355 | * @retval None
356 | */
357 | void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
358 | {
359 | /* Check the parameters */
360 | assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
361 | assert_param(IS_GPIO_PIN(GPIO_Pin));
362 |
363 | GPIOx->BSRR = GPIO_Pin;
364 | }
365 |
366 | /**
367 | * @brief Clears the selected data port bits.
368 | * @param GPIOx: where x can be (A..G) to select the GPIO peripheral.
369 | * @param GPIO_Pin: specifies the port bits to be written.
370 | * This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
371 | * @retval None
372 | */
373 | void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
374 | {
375 | /* Check the parameters */
376 | assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
377 | assert_param(IS_GPIO_PIN(GPIO_Pin));
378 |
379 | GPIOx->BRR = GPIO_Pin;
380 | }
381 |
382 | /**
383 | * @brief Sets or clears the selected data port bit.
384 | * @param GPIOx: where x can be (A..G) to select the GPIO peripheral.
385 | * @param GPIO_Pin: specifies the port bit to be written.
386 | * This parameter can be one of GPIO_Pin_x where x can be (0..15).
387 | * @param BitVal: specifies the value to be written to the selected bit.
388 | * This parameter can be one of the BitAction enum values:
389 | * @arg Bit_RESET: to clear the port pin
390 | * @arg Bit_SET: to set the port pin
391 | * @retval None
392 | */
393 | void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal)
394 | {
395 | /* Check the parameters */
396 | assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
397 | assert_param(IS_GET_GPIO_PIN(GPIO_Pin));
398 | assert_param(IS_GPIO_BIT_ACTION(BitVal));
399 |
400 | if (BitVal != Bit_RESET)
401 | {
402 | GPIOx->BSRR = GPIO_Pin;
403 | }
404 | else
405 | {
406 | GPIOx->BRR = GPIO_Pin;
407 | }
408 | }
409 |
410 | /**
411 | * @brief Writes data to the specified GPIO data port.
412 | * @param GPIOx: where x can be (A..G) to select the GPIO peripheral.
413 | * @param PortVal: specifies the value to be written to the port output data register.
414 | * @retval None
415 | */
416 | void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal)
417 | {
418 | /* Check the parameters */
419 | assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
420 |
421 | GPIOx->ODR = PortVal;
422 | }
423 |
424 | /**
425 | * @brief Locks GPIO Pins configuration registers.
426 | * @param GPIOx: where x can be (A..G) to select the GPIO peripheral.
427 | * @param GPIO_Pin: specifies the port bit to be written.
428 | * This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
429 | * @retval None
430 | */
431 | void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
432 | {
433 | uint32_t tmp = 0x00010000;
434 |
435 | /* Check the parameters */
436 | assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
437 | assert_param(IS_GPIO_PIN(GPIO_Pin));
438 |
439 | tmp |= GPIO_Pin;
440 | /* Set LCKK bit */
441 | GPIOx->LCKR = tmp;
442 | /* Reset LCKK bit */
443 | GPIOx->LCKR = GPIO_Pin;
444 | /* Set LCKK bit */
445 | GPIOx->LCKR = tmp;
446 | /* Read LCKK bit*/
447 | tmp = GPIOx->LCKR;
448 | /* Read LCKK bit*/
449 | tmp = GPIOx->LCKR;
450 | }
451 |
452 | /**
453 | * @brief Selects the GPIO pin used as Event output.
454 | * @param GPIO_PortSource: selects the GPIO port to be used as source
455 | * for Event output.
456 | * This parameter can be GPIO_PortSourceGPIOx where x can be (A..E).
457 | * @param GPIO_PinSource: specifies the pin for the Event output.
458 | * This parameter can be GPIO_PinSourcex where x can be (0..15).
459 | * @retval None
460 | */
461 | void GPIO_EventOutputConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource)
462 | {
463 | uint32_t tmpreg = 0x00;
464 | /* Check the parameters */
465 | assert_param(IS_GPIO_EVENTOUT_PORT_SOURCE(GPIO_PortSource));
466 | assert_param(IS_GPIO_PIN_SOURCE(GPIO_PinSource));
467 |
468 | tmpreg = AFIO->EVCR;
469 | /* Clear the PORT[6:4] and PIN[3:0] bits */
470 | tmpreg &= EVCR_PORTPINCONFIG_MASK;
471 | tmpreg |= (uint32_t)GPIO_PortSource << 0x04;
472 | tmpreg |= GPIO_PinSource;
473 | AFIO->EVCR = tmpreg;
474 | }
475 |
476 | /**
477 | * @brief Enables or disables the Event Output.
478 | * @param NewState: new state of the Event output.
479 | * This parameter can be: ENABLE or DISABLE.
480 | * @retval None
481 | */
482 | void GPIO_EventOutputCmd(FunctionalState NewState)
483 | {
484 | /* Check the parameters */
485 | assert_param(IS_FUNCTIONAL_STATE(NewState));
486 |
487 | *(__IO uint32_t *) EVCR_EVOE_BB = (uint32_t)NewState;
488 | }
489 |
490 | /**
491 | * @brief Changes the mapping of the specified pin.
492 | * @param GPIO_Remap: selects the pin to remap.
493 | * This parameter can be one of the following values:
494 | * @arg GPIO_Remap_SPI1
495 | * @arg GPIO_Remap_I2C1
496 | * @arg GPIO_Remap_USART1
497 | * @arg GPIO_Remap_USART2
498 | * @arg GPIO_PartialRemap_USART3
499 | * @arg GPIO_FullRemap_USART3
500 | * @arg GPIO_PartialRemap_TIM1
501 | * @arg GPIO_FullRemap_TIM1
502 | * @arg GPIO_PartialRemap1_TIM2
503 | * @arg GPIO_PartialRemap2_TIM2
504 | * @arg GPIO_FullRemap_TIM2
505 | * @arg GPIO_PartialRemap_TIM3
506 | * @arg GPIO_FullRemap_TIM3
507 | * @arg GPIO_Remap_TIM4
508 | * @arg GPIO_Remap1_CAN1
509 | * @arg GPIO_Remap2_CAN1
510 | * @arg GPIO_Remap_PD01
511 | * @arg GPIO_Remap_TIM5CH4_LSI
512 | * @arg GPIO_Remap_ADC1_ETRGINJ
513 | * @arg GPIO_Remap_ADC1_ETRGREG
514 | * @arg GPIO_Remap_ADC2_ETRGINJ
515 | * @arg GPIO_Remap_ADC2_ETRGREG
516 | * @arg GPIO_Remap_ETH
517 | * @arg GPIO_Remap_CAN2
518 | * @arg GPIO_Remap_SWJ_NoJTRST
519 | * @arg GPIO_Remap_SWJ_JTAGDisable
520 | * @arg GPIO_Remap_SWJ_Disable
521 | * @arg GPIO_Remap_SPI3
522 | * @arg GPIO_Remap_TIM2ITR1_PTP_SOF
523 | * @arg GPIO_Remap_PTP_PPS
524 | * @arg GPIO_Remap_TIM15
525 | * @arg GPIO_Remap_TIM16
526 | * @arg GPIO_Remap_TIM17
527 | * @arg GPIO_Remap_CEC
528 | * @arg GPIO_Remap_TIM1_DMA
529 | * @arg GPIO_Remap_TIM9
530 | * @arg GPIO_Remap_TIM10
531 | * @arg GPIO_Remap_TIM11
532 | * @arg GPIO_Remap_TIM13
533 | * @arg GPIO_Remap_TIM14
534 | * @arg GPIO_Remap_FSMC_NADV
535 | * @note If the GPIO_Remap_TIM2ITR1_PTP_SOF is enabled the TIM2 ITR1 is connected
536 | * to Ethernet PTP output. When Reset TIM2 ITR1 is connected to USB OTG SOF output.
537 | * @param NewState: new state of the port pin remapping.
538 | * This parameter can be: ENABLE or DISABLE.
539 | * @retval None
540 | */
541 | void GPIO_PinRemapConfig(uint32_t GPIO_Remap, FunctionalState NewState)
542 | {
543 | uint32_t tmp = 0x00, tmp1 = 0x00, tmpreg = 0x00, tmpmask = 0x00;
544 |
545 | /* Check the parameters */
546 | assert_param(IS_GPIO_REMAP(GPIO_Remap));
547 | assert_param(IS_FUNCTIONAL_STATE(NewState));
548 |
549 | if((GPIO_Remap & 0x80000000) == 0x80000000)
550 | {
551 | tmpreg = AFIO->MAPR2;
552 | }
553 | else
554 | {
555 | tmpreg = AFIO->MAPR;
556 | }
557 |
558 | tmpmask = (GPIO_Remap & DBGAFR_POSITION_MASK) >> 0x10;
559 | tmp = GPIO_Remap & LSB_MASK;
560 |
561 | if ((GPIO_Remap & (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK)) == (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK))
562 | {
563 | tmpreg &= DBGAFR_SWJCFG_MASK;
564 | AFIO->MAPR &= DBGAFR_SWJCFG_MASK;
565 | }
566 | else if ((GPIO_Remap & DBGAFR_NUMBITS_MASK) == DBGAFR_NUMBITS_MASK)
567 | {
568 | tmp1 = ((uint32_t)0x03) << tmpmask;
569 | tmpreg &= ~tmp1;
570 | tmpreg |= ~DBGAFR_SWJCFG_MASK;
571 | }
572 | else
573 | {
574 | tmpreg &= ~(tmp << ((GPIO_Remap >> 0x15)*0x10));
575 | tmpreg |= ~DBGAFR_SWJCFG_MASK;
576 | }
577 |
578 | if (NewState != DISABLE)
579 | {
580 | tmpreg |= (tmp << ((GPIO_Remap >> 0x15)*0x10));
581 | }
582 |
583 | if((GPIO_Remap & 0x80000000) == 0x80000000)
584 | {
585 | AFIO->MAPR2 = tmpreg;
586 | }
587 | else
588 | {
589 | AFIO->MAPR = tmpreg;
590 | }
591 | }
592 |
593 | /**
594 | * @brief Selects the GPIO pin used as EXTI Line.
595 | * @param GPIO_PortSource: selects the GPIO port to be used as source for EXTI lines.
596 | * This parameter can be GPIO_PortSourceGPIOx where x can be (A..G).
597 | * @param GPIO_PinSource: specifies the EXTI line to be configured.
598 | * This parameter can be GPIO_PinSourcex where x can be (0..15).
599 | * @retval None
600 | */
601 | void GPIO_EXTILineConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource)
602 | {
603 | uint32_t tmp = 0x00;
604 | /* Check the parameters */
605 | assert_param(IS_GPIO_EXTI_PORT_SOURCE(GPIO_PortSource));
606 | assert_param(IS_GPIO_PIN_SOURCE(GPIO_PinSource));
607 |
608 | tmp = ((uint32_t)0x0F) << (0x04 * (GPIO_PinSource & (uint8_t)0x03));
609 | AFIO->EXTICR[GPIO_PinSource >> 0x02] &= ~tmp;
610 | AFIO->EXTICR[GPIO_PinSource >> 0x02] |= (((uint32_t)GPIO_PortSource) << (0x04 * (GPIO_PinSource & (uint8_t)0x03)));
611 | }
612 |
613 | /**
614 | * @brief Selects the Ethernet media interface.
615 | * @note This function applies only to STM32 Connectivity line devices.
616 | * @param GPIO_ETH_MediaInterface: specifies the Media Interface mode.
617 | * This parameter can be one of the following values:
618 | * @arg GPIO_ETH_MediaInterface_MII: MII mode
619 | * @arg GPIO_ETH_MediaInterface_RMII: RMII mode
620 | * @retval None
621 | */
622 | void GPIO_ETH_MediaInterfaceConfig(uint32_t GPIO_ETH_MediaInterface)
623 | {
624 | assert_param(IS_GPIO_ETH_MEDIA_INTERFACE(GPIO_ETH_MediaInterface));
625 |
626 | /* Configure MII_RMII selection bit */
627 | *(__IO uint32_t *) MAPR_MII_RMII_SEL_BB = GPIO_ETH_MediaInterface;
628 | }
629 |
630 | /**
631 | * @}
632 | */
633 |
634 | /**
635 | * @}
636 | */
637 |
638 | /**
639 | * @}
640 | */
641 |
642 | /******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
643 |
--------------------------------------------------------------------------------
/SPL/stm32f10x_i2c.h:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file stm32f10x_i2c.h
4 | * @author MCD Application Team
5 | * @version V3.3.0
6 | * @date 04/16/2010
7 | * @brief This file contains all the functions prototypes for the I2C firmware
8 | * library.
9 | ******************************************************************************
10 | * @copy
11 | *
12 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
13 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
14 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
15 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
16 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
17 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
18 | *
19 | * © COPYRIGHT 2010 STMicroelectronics
20 | */
21 |
22 | /* Define to prevent recursive inclusion -------------------------------------*/
23 | #ifndef __STM32F10x_I2C_H
24 | #define __STM32F10x_I2C_H
25 |
26 | #ifdef __cplusplus
27 | extern "C" {
28 | #endif
29 |
30 | /* Includes ------------------------------------------------------------------*/
31 | #include "stm32f10x.h"
32 |
33 | /** @addtogroup STM32F10x_StdPeriph_Driver
34 | * @{
35 | */
36 |
37 | /** @addtogroup I2C
38 | * @{
39 | */
40 |
41 | /** @defgroup I2C_Exported_Types
42 | * @{
43 | */
44 |
45 | /**
46 | * @brief I2C Init structure definition
47 | */
48 |
49 | typedef struct
50 | {
51 | uint32_t I2C_ClockSpeed; /*!< Specifies the clock frequency.
52 | This parameter must be set to a value lower than 400kHz */
53 |
54 | uint16_t I2C_Mode; /*!< Specifies the I2C mode.
55 | This parameter can be a value of @ref I2C_mode */
56 |
57 | uint16_t I2C_DutyCycle; /*!< Specifies the I2C fast mode duty cycle.
58 | This parameter can be a value of @ref I2C_duty_cycle_in_fast_mode */
59 |
60 | uint16_t I2C_OwnAddress1; /*!< Specifies the first device own address.
61 | This parameter can be a 7-bit or 10-bit address. */
62 |
63 | uint16_t I2C_Ack; /*!< Enables or disables the acknowledgement.
64 | This parameter can be a value of @ref I2C_acknowledgement */
65 |
66 | uint16_t I2C_AcknowledgedAddress; /*!< Specifies if 7-bit or 10-bit address is acknowledged.
67 | This parameter can be a value of @ref I2C_acknowledged_address */
68 | }I2C_InitTypeDef;
69 |
70 | /**
71 | * @}
72 | */
73 |
74 |
75 | /** @defgroup I2C_Exported_Constants
76 | * @{
77 | */
78 |
79 | #define IS_I2C_ALL_PERIPH(PERIPH) (((PERIPH) == I2C1) || \
80 | ((PERIPH) == I2C2))
81 | /** @defgroup I2C_mode
82 | * @{
83 | */
84 |
85 | #define I2C_Mode_I2C ((uint16_t)0x0000)
86 | #define I2C_Mode_SMBusDevice ((uint16_t)0x0002)
87 | #define I2C_Mode_SMBusHost ((uint16_t)0x000A)
88 | #define IS_I2C_MODE(MODE) (((MODE) == I2C_Mode_I2C) || \
89 | ((MODE) == I2C_Mode_SMBusDevice) || \
90 | ((MODE) == I2C_Mode_SMBusHost))
91 | /**
92 | * @}
93 | */
94 |
95 | /** @defgroup I2C_duty_cycle_in_fast_mode
96 | * @{
97 | */
98 |
99 | #define I2C_DutyCycle_16_9 ((uint16_t)0x4000) /*!< I2C fast mode Tlow/Thigh = 16/9 */
100 | #define I2C_DutyCycle_2 ((uint16_t)0xBFFF) /*!< I2C fast mode Tlow/Thigh = 2 */
101 | #define IS_I2C_DUTY_CYCLE(CYCLE) (((CYCLE) == I2C_DutyCycle_16_9) || \
102 | ((CYCLE) == I2C_DutyCycle_2))
103 | /**
104 | * @}
105 | */
106 |
107 | /** @defgroup I2C_acknowledgement
108 | * @{
109 | */
110 |
111 | #define I2C_Ack_Enable ((uint16_t)0x0400)
112 | #define I2C_Ack_Disable ((uint16_t)0x0000)
113 | #define IS_I2C_ACK_STATE(STATE) (((STATE) == I2C_Ack_Enable) || \
114 | ((STATE) == I2C_Ack_Disable))
115 | /**
116 | * @}
117 | */
118 |
119 | /** @defgroup I2C_transfer_direction
120 | * @{
121 | */
122 |
123 | #define I2C_Direction_Transmitter ((uint8_t)0x00)
124 | #define I2C_Direction_Receiver ((uint8_t)0x01)
125 | #define IS_I2C_DIRECTION(DIRECTION) (((DIRECTION) == I2C_Direction_Transmitter) || \
126 | ((DIRECTION) == I2C_Direction_Receiver))
127 | /**
128 | * @}
129 | */
130 |
131 | /** @defgroup I2C_acknowledged_address
132 | * @{
133 | */
134 |
135 | #define I2C_AcknowledgedAddress_7bit ((uint16_t)0x4000)
136 | #define I2C_AcknowledgedAddress_10bit ((uint16_t)0xC000)
137 | #define IS_I2C_ACKNOWLEDGE_ADDRESS(ADDRESS) (((ADDRESS) == I2C_AcknowledgedAddress_7bit) || \
138 | ((ADDRESS) == I2C_AcknowledgedAddress_10bit))
139 | /**
140 | * @}
141 | */
142 |
143 | /** @defgroup I2C_registers
144 | * @{
145 | */
146 |
147 | #define I2C_Register_CR1 ((uint8_t)0x00)
148 | #define I2C_Register_CR2 ((uint8_t)0x04)
149 | #define I2C_Register_OAR1 ((uint8_t)0x08)
150 | #define I2C_Register_OAR2 ((uint8_t)0x0C)
151 | #define I2C_Register_DR ((uint8_t)0x10)
152 | #define I2C_Register_SR1 ((uint8_t)0x14)
153 | #define I2C_Register_SR2 ((uint8_t)0x18)
154 | #define I2C_Register_CCR ((uint8_t)0x1C)
155 | #define I2C_Register_TRISE ((uint8_t)0x20)
156 | #define IS_I2C_REGISTER(REGISTER) (((REGISTER) == I2C_Register_CR1) || \
157 | ((REGISTER) == I2C_Register_CR2) || \
158 | ((REGISTER) == I2C_Register_OAR1) || \
159 | ((REGISTER) == I2C_Register_OAR2) || \
160 | ((REGISTER) == I2C_Register_DR) || \
161 | ((REGISTER) == I2C_Register_SR1) || \
162 | ((REGISTER) == I2C_Register_SR2) || \
163 | ((REGISTER) == I2C_Register_CCR) || \
164 | ((REGISTER) == I2C_Register_TRISE))
165 | /**
166 | * @}
167 | */
168 |
169 | /** @defgroup I2C_SMBus_alert_pin_level
170 | * @{
171 | */
172 |
173 | #define I2C_SMBusAlert_Low ((uint16_t)0x2000)
174 | #define I2C_SMBusAlert_High ((uint16_t)0xDFFF)
175 | #define IS_I2C_SMBUS_ALERT(ALERT) (((ALERT) == I2C_SMBusAlert_Low) || \
176 | ((ALERT) == I2C_SMBusAlert_High))
177 | /**
178 | * @}
179 | */
180 |
181 | /** @defgroup I2C_PEC_position
182 | * @{
183 | */
184 |
185 | #define I2C_PECPosition_Next ((uint16_t)0x0800)
186 | #define I2C_PECPosition_Current ((uint16_t)0xF7FF)
187 | #define IS_I2C_PEC_POSITION(POSITION) (((POSITION) == I2C_PECPosition_Next) || \
188 | ((POSITION) == I2C_PECPosition_Current))
189 | /**
190 | * @}
191 | */
192 |
193 | /** @defgroup I2C_interrupts_definition
194 | * @{
195 | */
196 |
197 | #define I2C_IT_BUF ((uint16_t)0x0400)
198 | #define I2C_IT_EVT ((uint16_t)0x0200)
199 | #define I2C_IT_ERR ((uint16_t)0x0100)
200 | #define IS_I2C_CONFIG_IT(IT) ((((IT) & (uint16_t)0xF8FF) == 0x00) && ((IT) != 0x00))
201 | /**
202 | * @}
203 | */
204 |
205 | /** @defgroup I2C_interrupts_definition
206 | * @{
207 | */
208 |
209 | #define I2C_IT_SMBALERT ((uint32_t)0x01008000)
210 | #define I2C_IT_TIMEOUT ((uint32_t)0x01004000)
211 | #define I2C_IT_PECERR ((uint32_t)0x01001000)
212 | #define I2C_IT_OVR ((uint32_t)0x01000800)
213 | #define I2C_IT_AF ((uint32_t)0x01000400)
214 | #define I2C_IT_ARLO ((uint32_t)0x01000200)
215 | #define I2C_IT_BERR ((uint32_t)0x01000100)
216 | #define I2C_IT_TXE ((uint32_t)0x06000080)
217 | #define I2C_IT_RXNE ((uint32_t)0x06000040)
218 | #define I2C_IT_STOPF ((uint32_t)0x02000010)
219 | #define I2C_IT_ADD10 ((uint32_t)0x02000008)
220 | #define I2C_IT_BTF ((uint32_t)0x02000004)
221 | #define I2C_IT_ADDR ((uint32_t)0x02000002)
222 | #define I2C_IT_SB ((uint32_t)0x02000001)
223 |
224 | #define IS_I2C_CLEAR_IT(IT) ((((IT) & (uint16_t)0x20FF) == 0x00) && ((IT) != (uint16_t)0x00))
225 |
226 | #define IS_I2C_GET_IT(IT) (((IT) == I2C_IT_SMBALERT) || ((IT) == I2C_IT_TIMEOUT) || \
227 | ((IT) == I2C_IT_PECERR) || ((IT) == I2C_IT_OVR) || \
228 | ((IT) == I2C_IT_AF) || ((IT) == I2C_IT_ARLO) || \
229 | ((IT) == I2C_IT_BERR) || ((IT) == I2C_IT_TXE) || \
230 | ((IT) == I2C_IT_RXNE) || ((IT) == I2C_IT_STOPF) || \
231 | ((IT) == I2C_IT_ADD10) || ((IT) == I2C_IT_BTF) || \
232 | ((IT) == I2C_IT_ADDR) || ((IT) == I2C_IT_SB))
233 | /**
234 | * @}
235 | */
236 |
237 | /** @defgroup I2C_flags_definition
238 | * @{
239 | */
240 |
241 | /**
242 | * @brief SR2 register flags
243 | */
244 |
245 | #define I2C_FLAG_DUALF ((uint32_t)0x00800000)
246 | #define I2C_FLAG_SMBHOST ((uint32_t)0x00400000)
247 | #define I2C_FLAG_SMBDEFAULT ((uint32_t)0x00200000)
248 | #define I2C_FLAG_GENCALL ((uint32_t)0x00100000)
249 | #define I2C_FLAG_TRA ((uint32_t)0x00040000)
250 | #define I2C_FLAG_BUSY ((uint32_t)0x00020000)
251 | #define I2C_FLAG_MSL ((uint32_t)0x00010000)
252 |
253 | /**
254 | * @brief SR1 register flags
255 | */
256 |
257 | #define I2C_FLAG_SMBALERT ((uint32_t)0x10008000)
258 | #define I2C_FLAG_TIMEOUT ((uint32_t)0x10004000)
259 | #define I2C_FLAG_PECERR ((uint32_t)0x10001000)
260 | #define I2C_FLAG_OVR ((uint32_t)0x10000800)
261 | #define I2C_FLAG_AF ((uint32_t)0x10000400)
262 | #define I2C_FLAG_ARLO ((uint32_t)0x10000200)
263 | #define I2C_FLAG_BERR ((uint32_t)0x10000100)
264 | #define I2C_FLAG_TXE ((uint32_t)0x10000080)
265 | #define I2C_FLAG_RXNE ((uint32_t)0x10000040)
266 | #define I2C_FLAG_STOPF ((uint32_t)0x10000010)
267 | #define I2C_FLAG_ADD10 ((uint32_t)0x10000008)
268 | #define I2C_FLAG_BTF ((uint32_t)0x10000004)
269 | #define I2C_FLAG_ADDR ((uint32_t)0x10000002)
270 | #define I2C_FLAG_SB ((uint32_t)0x10000001)
271 |
272 | #define IS_I2C_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0x20FF) == 0x00) && ((FLAG) != (uint16_t)0x00))
273 |
274 | #define IS_I2C_GET_FLAG(FLAG) (((FLAG) == I2C_FLAG_DUALF) || ((FLAG) == I2C_FLAG_SMBHOST) || \
275 | ((FLAG) == I2C_FLAG_SMBDEFAULT) || ((FLAG) == I2C_FLAG_GENCALL) || \
276 | ((FLAG) == I2C_FLAG_TRA) || ((FLAG) == I2C_FLAG_BUSY) || \
277 | ((FLAG) == I2C_FLAG_MSL) || ((FLAG) == I2C_FLAG_SMBALERT) || \
278 | ((FLAG) == I2C_FLAG_TIMEOUT) || ((FLAG) == I2C_FLAG_PECERR) || \
279 | ((FLAG) == I2C_FLAG_OVR) || ((FLAG) == I2C_FLAG_AF) || \
280 | ((FLAG) == I2C_FLAG_ARLO) || ((FLAG) == I2C_FLAG_BERR) || \
281 | ((FLAG) == I2C_FLAG_TXE) || ((FLAG) == I2C_FLAG_RXNE) || \
282 | ((FLAG) == I2C_FLAG_STOPF) || ((FLAG) == I2C_FLAG_ADD10) || \
283 | ((FLAG) == I2C_FLAG_BTF) || ((FLAG) == I2C_FLAG_ADDR) || \
284 | ((FLAG) == I2C_FLAG_SB))
285 | /**
286 | * @}
287 | */
288 |
289 | /** @defgroup I2C_Events
290 | * @{
291 | */
292 |
293 | /*========================================
294 |
295 | I2C Master Events (Events grouped in order of communication)
296 | ==========================================*/
297 | /**
298 | * @brief Communication start
299 | *
300 | * After sending the START condition (I2C_GenerateSTART() function) the master
301 | * has to wait for this event. It means that the Start condition has been correctly
302 | * released on the I2C bus (the bus is free, no other devices is communicating).
303 | *
304 | */
305 | /* --EV5 */
306 | #define I2C_EVENT_MASTER_MODE_SELECT ((uint32_t)0x00030001) /* BUSY, MSL and SB flag */
307 |
308 | /**
309 | * @brief Address Acknowledge
310 | *
311 | * After checking on EV5 (start condition correctly released on the bus), the
312 | * master sends the address of the slave(s) with which it will communicate
313 | * (I2C_Send7bitAddress() function, it also determines the direction of the communication:
314 | * Master transmitter or Receiver). Then the master has to wait that a slave acknowledges
315 | * his address. If an acknowledge is sent on the bus, one of the following events will
316 | * be set:
317 | *
318 | * 1) In case of Master Receiver (7-bit addressing): the I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED
319 | * event is set.
320 | *
321 | * 2) In case of Master Transmitter (7-bit addressing): the I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED
322 | * is set
323 | *
324 | * 3) In case of 10-Bit addressing mode, the master (just after generating the START
325 | * and checking on EV5) has to send the header of 10-bit addressing mode (I2C_SendData()
326 | * function). Then master should wait on EV9. It means that the 10-bit addressing
327 | * header has been correctly sent on the bus. Then master should send the second part of
328 | * the 10-bit address (LSB) using the function I2C_Send7bitAddress(). Then master
329 | * should wait for event EV6.
330 | *
331 | */
332 |
333 | /* --EV6 */
334 | #define I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED ((uint32_t)0x00070082) /* BUSY, MSL, ADDR, TXE and TRA flags */
335 | #define I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED ((uint32_t)0x00030002) /* BUSY, MSL and ADDR flags */
336 | /* --EV9 */
337 | #define I2C_EVENT_MASTER_MODE_ADDRESS10 ((uint32_t)0x00030008) /* BUSY, MSL and ADD10 flags */
338 |
339 | /**
340 | * @brief Communication events
341 | *
342 | * If a communication is established (START condition generated and slave address
343 | * acknowledged) then the master has to check on one of the following events for
344 | * communication procedures:
345 | *
346 | * 1) Master Receiver mode: The master has to wait on the event EV7 then to read
347 | * the data received from the slave (I2C_ReceiveData() function).
348 | *
349 | * 2) Master Transmitter mode: The master has to send data (I2C_SendData()
350 | * function) then to wait on event EV8 or EV8_2.
351 | * These two events are similar:
352 | * - EV8 means that the data has been written in the data register and is
353 | * being shifted out.
354 | * - EV8_2 means that the data has been physically shifted out and output
355 | * on the bus.
356 | * In most cases, using EV8 is sufficient for the application.
357 | * Using EV8_2 leads to a slower communication but ensure more reliable test.
358 | * EV8_2 is also more suitable than EV8 for testing on the last data transmission
359 | * (before Stop condition generation).
360 | *
361 | * @note In case the user software does not guarantee that this event EV7 is
362 | * managed before the current byte end of transfer, then user may check on EV7
363 | * and BTF flag at the same time (ie. (I2C_EVENT_MASTER_BYTE_RECEIVED | I2C_FLAG_BTF)).
364 | * In this case the communication may be slower.
365 | *
366 | */
367 |
368 | /* Master RECEIVER mode -----------------------------*/
369 | /* --EV7 */
370 | #define I2C_EVENT_MASTER_BYTE_RECEIVED ((uint32_t)0x00030040) /* BUSY, MSL and RXNE flags */
371 |
372 | /* Master TRANSMITTER mode --------------------------*/
373 | /* --EV8 */
374 | #define I2C_EVENT_MASTER_BYTE_TRANSMITTING ((uint32_t)0x00070080) /* TRA, BUSY, MSL, TXE flags */
375 | /* --EV8_2 */
376 | #define I2C_EVENT_MASTER_BYTE_TRANSMITTED ((uint32_t)0x00070084) /* TRA, BUSY, MSL, TXE and BTF flags */
377 |
378 |
379 | /*========================================
380 |
381 | I2C Slave Events (Events grouped in order of communication)
382 | ==========================================*/
383 |
384 | /**
385 | * @brief Communication start events
386 | *
387 | * Wait on one of these events at the start of the communication. It means that
388 | * the I2C peripheral detected a Start condition on the bus (generated by master
389 | * device) followed by the peripheral address. The peripheral generates an ACK
390 | * condition on the bus (if the acknowledge feature is enabled through function
391 | * I2C_AcknowledgeConfig()) and the events listed above are set :
392 | *
393 | * 1) In normal case (only one address managed by the slave), when the address
394 | * sent by the master matches the own address of the peripheral (configured by
395 | * I2C_OwnAddress1 field) the I2C_EVENT_SLAVE_XXX_ADDRESS_MATCHED event is set
396 | * (where XXX could be TRANSMITTER or RECEIVER).
397 | *
398 | * 2) In case the address sent by the master matches the second address of the
399 | * peripheral (configured by the function I2C_OwnAddress2Config() and enabled
400 | * by the function I2C_DualAddressCmd()) the events I2C_EVENT_SLAVE_XXX_SECONDADDRESS_MATCHED
401 | * (where XXX could be TRANSMITTER or RECEIVER) are set.
402 | *
403 | * 3) In case the address sent by the master is General Call (address 0x00) and
404 | * if the General Call is enabled for the peripheral (using function I2C_GeneralCallCmd())
405 | * the following event is set I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED.
406 | *
407 | */
408 |
409 | /* --EV1 (all the events below are variants of EV1) */
410 | /* 1) Case of One Single Address managed by the slave */
411 | #define I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED ((uint32_t)0x00020002) /* BUSY and ADDR flags */
412 | #define I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED ((uint32_t)0x00060082) /* TRA, BUSY, TXE and ADDR flags */
413 |
414 | /* 2) Case of Dual address managed by the slave */
415 | #define I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED ((uint32_t)0x00820000) /* DUALF and BUSY flags */
416 | #define I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED ((uint32_t)0x00860080) /* DUALF, TRA, BUSY and TXE flags */
417 |
418 | /* 3) Case of General Call enabled for the slave */
419 | #define I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED ((uint32_t)0x00120000) /* GENCALL and BUSY flags */
420 |
421 | /**
422 | * @brief Communication events
423 | *
424 | * Wait on one of these events when EV1 has already been checked and:
425 | *
426 | * - Slave RECEIVER mode:
427 | * - EV2: When the application is expecting a data byte to be received.
428 | * - EV4: When the application is expecting the end of the communication: master
429 | * sends a stop condition and data transmission is stopped.
430 | *
431 | * - Slave Transmitter mode:
432 | * - EV3: When a byte has been transmitted by the slave and the application is expecting
433 | * the end of the byte transmission. The two events I2C_EVENT_SLAVE_BYTE_TRANSMITTED and
434 | * I2C_EVENT_SLAVE_BYTE_TRANSMITTING are similar. The second one can optionally be
435 | * used when the user software doesn't guarantee the EV3 is managed before the
436 | * current byte end of tranfer.
437 | * - EV3_2: When the master sends a NACK in order to tell slave that data transmission
438 | * shall end (before sending the STOP condition). In this case slave has to stop sending
439 | * data bytes and expect a Stop condition on the bus.
440 | *
441 | * @note In case the user software does not guarantee that the event EV2 is
442 | * managed before the current byte end of transfer, then user may check on EV2
443 | * and BTF flag at the same time (ie. (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_BTF)).
444 | * In this case the communication may be slower.
445 | *
446 | */
447 |
448 | /* Slave RECEIVER mode --------------------------*/
449 | /* --EV2 */
450 | #define I2C_EVENT_SLAVE_BYTE_RECEIVED ((uint32_t)0x00020040) /* BUSY and RXNE flags */
451 | /* --EV4 */
452 | #define I2C_EVENT_SLAVE_STOP_DETECTED ((uint32_t)0x00000010) /* STOPF flag */
453 |
454 | /* Slave TRANSMITTER mode -----------------------*/
455 | /* --EV3 */
456 | #define I2C_EVENT_SLAVE_BYTE_TRANSMITTED ((uint32_t)0x00060084) /* TRA, BUSY, TXE and BTF flags */
457 | #define I2C_EVENT_SLAVE_BYTE_TRANSMITTING ((uint32_t)0x00060080) /* TRA, BUSY and TXE flags */
458 | /* --EV3_2 */
459 | #define I2C_EVENT_SLAVE_ACK_FAILURE ((uint32_t)0x00000400) /* AF flag */
460 |
461 | /*=========================== End of Events Description ==========================================*/
462 |
463 | #define IS_I2C_EVENT(EVENT) (((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED) || \
464 | ((EVENT) == I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED) || \
465 | ((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED) || \
466 | ((EVENT) == I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED) || \
467 | ((EVENT) == I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED) || \
468 | ((EVENT) == I2C_EVENT_SLAVE_BYTE_RECEIVED) || \
469 | ((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_DUALF)) || \
470 | ((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_GENCALL)) || \
471 | ((EVENT) == I2C_EVENT_SLAVE_BYTE_TRANSMITTED) || \
472 | ((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_DUALF)) || \
473 | ((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_GENCALL)) || \
474 | ((EVENT) == I2C_EVENT_SLAVE_STOP_DETECTED) || \
475 | ((EVENT) == I2C_EVENT_MASTER_MODE_SELECT) || \
476 | ((EVENT) == I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED) || \
477 | ((EVENT) == I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED) || \
478 | ((EVENT) == I2C_EVENT_MASTER_BYTE_RECEIVED) || \
479 | ((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTED) || \
480 | ((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTING) || \
481 | ((EVENT) == I2C_EVENT_MASTER_MODE_ADDRESS10) || \
482 | ((EVENT) == I2C_EVENT_SLAVE_ACK_FAILURE))
483 | /**
484 | * @}
485 | */
486 |
487 | /** @defgroup I2C_own_address1
488 | * @{
489 | */
490 |
491 | #define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x3FF)
492 | /**
493 | * @}
494 | */
495 |
496 | /** @defgroup I2C_clock_speed
497 | * @{
498 | */
499 |
500 | #define IS_I2C_CLOCK_SPEED(SPEED) (((SPEED) >= 0x1) && ((SPEED) <= 400000))
501 | /**
502 | * @}
503 | */
504 |
505 | /**
506 | * @}
507 | */
508 |
509 | /** @defgroup I2C_Exported_Macros
510 | * @{
511 | */
512 |
513 | /**
514 | * @}
515 | */
516 |
517 | /** @defgroup I2C_Exported_Functions
518 | * @{
519 | */
520 |
521 | void I2C_DeInit(I2C_TypeDef* I2Cx);
522 | void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct);
523 | void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct);
524 | void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
525 | void I2C_DMACmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
526 | void I2C_DMALastTransferCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
527 | void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState);
528 | void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState);
529 | void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState);
530 | void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint8_t Address);
531 | void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
532 | void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
533 | void I2C_ITConfig(I2C_TypeDef* I2Cx, uint16_t I2C_IT, FunctionalState NewState);
534 | void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data);
535 | uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx);
536 | void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, uint8_t Address, uint8_t I2C_Direction);
537 | uint16_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register);
538 | void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
539 | void I2C_SMBusAlertConfig(I2C_TypeDef* I2Cx, uint16_t I2C_SMBusAlert);
540 | void I2C_TransmitPEC(I2C_TypeDef* I2Cx, FunctionalState NewState);
541 | void I2C_PECPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_PECPosition);
542 | void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState);
543 | uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx);
544 | void I2C_ARPCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
545 | void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
546 | void I2C_FastModeDutyCycleConfig(I2C_TypeDef* I2Cx, uint16_t I2C_DutyCycle);
547 |
548 | /**
549 | * @brief
550 | ****************************************************************************************
551 | *
552 | * I2C State Monitoring Functions
553 | *
554 | ****************************************************************************************
555 | * This I2C driver provides three different ways for I2C state monitoring
556 | * depending on the application requirements and constraints:
557 | *
558 | *
559 | * 1) Basic state monitoring:
560 | * Using I2C_CheckEvent() function:
561 | * It compares the status registers (SR1 and SR2) content to a given event
562 | * (can be the combination of one or more flags).
563 | * It returns SUCCESS if the current status includes the given flags
564 | * and returns ERROR if one or more flags are missing in the current status.
565 | * - When to use:
566 | * - This function is suitable for most applications as well as for startup
567 | * activity since the events are fully described in the product reference manual
568 | * (RM0008).
569 | * - It is also suitable for users who need to define their own events.
570 | * - Limitations:
571 | * - If an error occurs (ie. error flags are set besides to the monitored flags),
572 | * the I2C_CheckEvent() function may return SUCCESS despite the communication
573 | * hold or corrupted real state.
574 | * In this case, it is advised to use error interrupts to monitor the error
575 | * events and handle them in the interrupt IRQ handler.
576 | *
577 | * @note
578 | * For error management, it is advised to use the following functions:
579 | * - I2C_ITConfig() to configure and enable the error interrupts (I2C_IT_ERR).
580 | * - I2Cx_ER_IRQHandler() which is called when the error interurpt occurs.
581 | * Where x is the peripheral instance (I2C1, I2C2 ...)
582 | * - I2C_GetFlagStatus() or I2C_GetITStatus() to be called into I2Cx_ER_IRQHandler()
583 | * in order to determine which error occured.
584 | * - I2C_ClearFlag() or I2C_ClearITPendingBit() and/or I2C_SoftwareResetCmd()
585 | * and/or I2C_GenerateStop() in order to clear the error flag and source,
586 | * and return to correct communication status.
587 | *
588 | *
589 | * 2) Advanced state monitoring:
590 | * Using the function I2C_GetLastEvent() which returns the image of both status
591 | * registers in a single word (uint32_t) (Status Register 2 value is shifted left
592 | * by 16 bits and concatenated to Status Register 1).
593 | * - When to use:
594 | * - This function is suitable for the same applications above but it allows to
595 | * overcome the limitations of I2C_GetFlagStatus() function (see below).
596 | * The returned value could be compared to events already defined in the
597 | * library (stm32f10x_i2c.h) or to custom values defined by user.
598 | * - This function is suitable when multiple flags are monitored at the same time.
599 | * - At the opposite of I2C_CheckEvent() function, this function allows user to
600 | * choose when an event is accepted (when all events flags are set and no
601 | * other flags are set or just when the needed flags are set like
602 | * I2C_CheckEvent() function).
603 | * - Limitations:
604 | * - User may need to define his own events.
605 | * - Same remark concerning the error management is applicable for this
606 | * function if user decides to check only regular communication flags (and
607 | * ignores error flags).
608 | *
609 | *
610 | * 3) Flag-based state monitoring:
611 | * Using the function I2C_GetFlagStatus() which simply returns the status of
612 | * one single flag (ie. I2C_FLAG_RXNE ...).
613 | * - When to use:
614 | * - This function could be used for specific applications or in debug phase.
615 | * - It is suitable when only one flag checking is needed (most I2C events
616 | * are monitored through multiple flags).
617 | * - Limitations:
618 | * - When calling this function, the Status register is accessed. Some flags are
619 | * cleared when the status register is accessed. So checking the status
620 | * of one Flag, may clear other ones.
621 | * - Function may need to be called twice or more in order to monitor one
622 | * single event.
623 | *
624 | */
625 |
626 | /**
627 | *
628 | * 1) Basic state monitoring
629 | *******************************************************************************
630 | */
631 | ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, uint32_t I2C_EVENT);
632 | /**
633 | *
634 | * 2) Advanced state monitoring
635 | *******************************************************************************
636 | */
637 | uint32_t I2C_GetLastEvent(I2C_TypeDef* I2Cx);
638 | /**
639 | *
640 | * 3) Flag-based state monitoring
641 | *******************************************************************************
642 | */
643 | FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG);
644 | /**
645 | *
646 | *******************************************************************************
647 | */
648 |
649 | void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG);
650 | ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT);
651 | void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT);
652 |
653 | #ifdef __cplusplus
654 | }
655 | #endif
656 |
657 | #endif /*__STM32F10x_I2C_H */
658 | /**
659 | * @}
660 | */
661 |
662 | /**
663 | * @}
664 | */
665 |
666 | /**
667 | * @}
668 | */
669 |
670 | /******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
671 |
--------------------------------------------------------------------------------
/SPL/stm32f10x_rcc.h:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file stm32f10x_rcc.h
4 | * @author MCD Application Team
5 | * @version V3.3.0
6 | * @date 04/16/2010
7 | * @brief This file contains all the functions prototypes for the RCC firmware
8 | * library.
9 | ******************************************************************************
10 | * @copy
11 | *
12 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
13 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
14 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
15 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
16 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
17 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
18 | *
19 | * © COPYRIGHT 2010 STMicroelectronics
20 | */
21 |
22 | /* Define to prevent recursive inclusion -------------------------------------*/
23 | #ifndef __STM32F10x_RCC_H
24 | #define __STM32F10x_RCC_H
25 |
26 | #ifdef __cplusplus
27 | extern "C" {
28 | #endif
29 |
30 | /* Includes ------------------------------------------------------------------*/
31 | #include "stm32f10x.h"
32 |
33 | /** @addtogroup STM32F10x_StdPeriph_Driver
34 | * @{
35 | */
36 |
37 | /** @addtogroup RCC
38 | * @{
39 | */
40 |
41 | /** @defgroup RCC_Exported_Types
42 | * @{
43 | */
44 |
45 | typedef struct
46 | {
47 | uint32_t SYSCLK_Frequency; /*!< returns SYSCLK clock frequency expressed in Hz */
48 | uint32_t HCLK_Frequency; /*!< returns HCLK clock frequency expressed in Hz */
49 | uint32_t PCLK1_Frequency; /*!< returns PCLK1 clock frequency expressed in Hz */
50 | uint32_t PCLK2_Frequency; /*!< returns PCLK2 clock frequency expressed in Hz */
51 | uint32_t ADCCLK_Frequency; /*!< returns ADCCLK clock frequency expressed in Hz */
52 | }RCC_ClocksTypeDef;
53 |
54 | /**
55 | * @}
56 | */
57 |
58 | /** @defgroup RCC_Exported_Constants
59 | * @{
60 | */
61 |
62 | /** @defgroup HSE_configuration
63 | * @{
64 | */
65 |
66 | #define RCC_HSE_OFF ((uint32_t)0x00000000)
67 | #define RCC_HSE_ON ((uint32_t)0x00010000)
68 | #define RCC_HSE_Bypass ((uint32_t)0x00040000)
69 | #define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \
70 | ((HSE) == RCC_HSE_Bypass))
71 |
72 | /**
73 | * @}
74 | */
75 |
76 | /** @defgroup PLL_entry_clock_source
77 | * @{
78 | */
79 |
80 | #define RCC_PLLSource_HSI_Div2 ((uint32_t)0x00000000)
81 |
82 | #if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_CL)
83 | #define RCC_PLLSource_HSE_Div1 ((uint32_t)0x00010000)
84 | #define RCC_PLLSource_HSE_Div2 ((uint32_t)0x00030000)
85 | #define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI_Div2) || \
86 | ((SOURCE) == RCC_PLLSource_HSE_Div1) || \
87 | ((SOURCE) == RCC_PLLSource_HSE_Div2))
88 | #else
89 | #define RCC_PLLSource_PREDIV1 ((uint32_t)0x00010000)
90 | #define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI_Div2) || \
91 | ((SOURCE) == RCC_PLLSource_PREDIV1))
92 | #endif /* STM32F10X_CL */
93 |
94 | /**
95 | * @}
96 | */
97 |
98 | /** @defgroup PLL_multiplication_factor
99 | * @{
100 | */
101 | #ifndef STM32F10X_CL
102 | #define RCC_PLLMul_2 ((uint32_t)0x00000000)
103 | #define RCC_PLLMul_3 ((uint32_t)0x00040000)
104 | #define RCC_PLLMul_4 ((uint32_t)0x00080000)
105 | #define RCC_PLLMul_5 ((uint32_t)0x000C0000)
106 | #define RCC_PLLMul_6 ((uint32_t)0x00100000)
107 | #define RCC_PLLMul_7 ((uint32_t)0x00140000)
108 | #define RCC_PLLMul_8 ((uint32_t)0x00180000)
109 | #define RCC_PLLMul_9 ((uint32_t)0x001C0000)
110 | #define RCC_PLLMul_10 ((uint32_t)0x00200000)
111 | #define RCC_PLLMul_11 ((uint32_t)0x00240000)
112 | #define RCC_PLLMul_12 ((uint32_t)0x00280000)
113 | #define RCC_PLLMul_13 ((uint32_t)0x002C0000)
114 | #define RCC_PLLMul_14 ((uint32_t)0x00300000)
115 | #define RCC_PLLMul_15 ((uint32_t)0x00340000)
116 | #define RCC_PLLMul_16 ((uint32_t)0x00380000)
117 | #define IS_RCC_PLL_MUL(MUL) (((MUL) == RCC_PLLMul_2) || ((MUL) == RCC_PLLMul_3) || \
118 | ((MUL) == RCC_PLLMul_4) || ((MUL) == RCC_PLLMul_5) || \
119 | ((MUL) == RCC_PLLMul_6) || ((MUL) == RCC_PLLMul_7) || \
120 | ((MUL) == RCC_PLLMul_8) || ((MUL) == RCC_PLLMul_9) || \
121 | ((MUL) == RCC_PLLMul_10) || ((MUL) == RCC_PLLMul_11) || \
122 | ((MUL) == RCC_PLLMul_12) || ((MUL) == RCC_PLLMul_13) || \
123 | ((MUL) == RCC_PLLMul_14) || ((MUL) == RCC_PLLMul_15) || \
124 | ((MUL) == RCC_PLLMul_16))
125 |
126 | #else
127 | #define RCC_PLLMul_4 ((uint32_t)0x00080000)
128 | #define RCC_PLLMul_5 ((uint32_t)0x000C0000)
129 | #define RCC_PLLMul_6 ((uint32_t)0x00100000)
130 | #define RCC_PLLMul_7 ((uint32_t)0x00140000)
131 | #define RCC_PLLMul_8 ((uint32_t)0x00180000)
132 | #define RCC_PLLMul_9 ((uint32_t)0x001C0000)
133 | #define RCC_PLLMul_6_5 ((uint32_t)0x00340000)
134 |
135 | #define IS_RCC_PLL_MUL(MUL) (((MUL) == RCC_PLLMul_4) || ((MUL) == RCC_PLLMul_5) || \
136 | ((MUL) == RCC_PLLMul_6) || ((MUL) == RCC_PLLMul_7) || \
137 | ((MUL) == RCC_PLLMul_8) || ((MUL) == RCC_PLLMul_9) || \
138 | ((MUL) == RCC_PLLMul_6_5))
139 | #endif /* STM32F10X_CL */
140 | /**
141 | * @}
142 | */
143 |
144 | /** @defgroup PREDIV1_division_factor
145 | * @{
146 | */
147 | #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_CL)
148 | #define RCC_PREDIV1_Div1 ((uint32_t)0x00000000)
149 | #define RCC_PREDIV1_Div2 ((uint32_t)0x00000001)
150 | #define RCC_PREDIV1_Div3 ((uint32_t)0x00000002)
151 | #define RCC_PREDIV1_Div4 ((uint32_t)0x00000003)
152 | #define RCC_PREDIV1_Div5 ((uint32_t)0x00000004)
153 | #define RCC_PREDIV1_Div6 ((uint32_t)0x00000005)
154 | #define RCC_PREDIV1_Div7 ((uint32_t)0x00000006)
155 | #define RCC_PREDIV1_Div8 ((uint32_t)0x00000007)
156 | #define RCC_PREDIV1_Div9 ((uint32_t)0x00000008)
157 | #define RCC_PREDIV1_Div10 ((uint32_t)0x00000009)
158 | #define RCC_PREDIV1_Div11 ((uint32_t)0x0000000A)
159 | #define RCC_PREDIV1_Div12 ((uint32_t)0x0000000B)
160 | #define RCC_PREDIV1_Div13 ((uint32_t)0x0000000C)
161 | #define RCC_PREDIV1_Div14 ((uint32_t)0x0000000D)
162 | #define RCC_PREDIV1_Div15 ((uint32_t)0x0000000E)
163 | #define RCC_PREDIV1_Div16 ((uint32_t)0x0000000F)
164 |
165 | #define IS_RCC_PREDIV1(PREDIV1) (((PREDIV1) == RCC_PREDIV1_Div1) || ((PREDIV1) == RCC_PREDIV1_Div2) || \
166 | ((PREDIV1) == RCC_PREDIV1_Div3) || ((PREDIV1) == RCC_PREDIV1_Div4) || \
167 | ((PREDIV1) == RCC_PREDIV1_Div5) || ((PREDIV1) == RCC_PREDIV1_Div6) || \
168 | ((PREDIV1) == RCC_PREDIV1_Div7) || ((PREDIV1) == RCC_PREDIV1_Div8) || \
169 | ((PREDIV1) == RCC_PREDIV1_Div9) || ((PREDIV1) == RCC_PREDIV1_Div10) || \
170 | ((PREDIV1) == RCC_PREDIV1_Div11) || ((PREDIV1) == RCC_PREDIV1_Div12) || \
171 | ((PREDIV1) == RCC_PREDIV1_Div13) || ((PREDIV1) == RCC_PREDIV1_Div14) || \
172 | ((PREDIV1) == RCC_PREDIV1_Div15) || ((PREDIV1) == RCC_PREDIV1_Div16))
173 | #endif
174 | /**
175 | * @}
176 | */
177 |
178 |
179 | /** @defgroup PREDIV1_clock_source
180 | * @{
181 | */
182 | #ifdef STM32F10X_CL
183 | /* PREDIV1 clock source (for STM32 connectivity line devices) */
184 | #define RCC_PREDIV1_Source_HSE ((uint32_t)0x00000000)
185 | #define RCC_PREDIV1_Source_PLL2 ((uint32_t)0x00010000)
186 |
187 | #define IS_RCC_PREDIV1_SOURCE(SOURCE) (((SOURCE) == RCC_PREDIV1_Source_HSE) || \
188 | ((SOURCE) == RCC_PREDIV1_Source_PLL2))
189 | #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL)
190 | /* PREDIV1 clock source (for STM32 Value line devices) */
191 | #define RCC_PREDIV1_Source_HSE ((uint32_t)0x00000000)
192 |
193 | #define IS_RCC_PREDIV1_SOURCE(SOURCE) (((SOURCE) == RCC_PREDIV1_Source_HSE))
194 | #endif
195 | /**
196 | * @}
197 | */
198 |
199 | #ifdef STM32F10X_CL
200 | /** @defgroup PREDIV2_division_factor
201 | * @{
202 | */
203 |
204 | #define RCC_PREDIV2_Div1 ((uint32_t)0x00000000)
205 | #define RCC_PREDIV2_Div2 ((uint32_t)0x00000010)
206 | #define RCC_PREDIV2_Div3 ((uint32_t)0x00000020)
207 | #define RCC_PREDIV2_Div4 ((uint32_t)0x00000030)
208 | #define RCC_PREDIV2_Div5 ((uint32_t)0x00000040)
209 | #define RCC_PREDIV2_Div6 ((uint32_t)0x00000050)
210 | #define RCC_PREDIV2_Div7 ((uint32_t)0x00000060)
211 | #define RCC_PREDIV2_Div8 ((uint32_t)0x00000070)
212 | #define RCC_PREDIV2_Div9 ((uint32_t)0x00000080)
213 | #define RCC_PREDIV2_Div10 ((uint32_t)0x00000090)
214 | #define RCC_PREDIV2_Div11 ((uint32_t)0x000000A0)
215 | #define RCC_PREDIV2_Div12 ((uint32_t)0x000000B0)
216 | #define RCC_PREDIV2_Div13 ((uint32_t)0x000000C0)
217 | #define RCC_PREDIV2_Div14 ((uint32_t)0x000000D0)
218 | #define RCC_PREDIV2_Div15 ((uint32_t)0x000000E0)
219 | #define RCC_PREDIV2_Div16 ((uint32_t)0x000000F0)
220 |
221 | #define IS_RCC_PREDIV2(PREDIV2) (((PREDIV2) == RCC_PREDIV2_Div1) || ((PREDIV2) == RCC_PREDIV2_Div2) || \
222 | ((PREDIV2) == RCC_PREDIV2_Div3) || ((PREDIV2) == RCC_PREDIV2_Div4) || \
223 | ((PREDIV2) == RCC_PREDIV2_Div5) || ((PREDIV2) == RCC_PREDIV2_Div6) || \
224 | ((PREDIV2) == RCC_PREDIV2_Div7) || ((PREDIV2) == RCC_PREDIV2_Div8) || \
225 | ((PREDIV2) == RCC_PREDIV2_Div9) || ((PREDIV2) == RCC_PREDIV2_Div10) || \
226 | ((PREDIV2) == RCC_PREDIV2_Div11) || ((PREDIV2) == RCC_PREDIV2_Div12) || \
227 | ((PREDIV2) == RCC_PREDIV2_Div13) || ((PREDIV2) == RCC_PREDIV2_Div14) || \
228 | ((PREDIV2) == RCC_PREDIV2_Div15) || ((PREDIV2) == RCC_PREDIV2_Div16))
229 | /**
230 | * @}
231 | */
232 |
233 |
234 | /** @defgroup PLL2_multiplication_factor
235 | * @{
236 | */
237 |
238 | #define RCC_PLL2Mul_8 ((uint32_t)0x00000600)
239 | #define RCC_PLL2Mul_9 ((uint32_t)0x00000700)
240 | #define RCC_PLL2Mul_10 ((uint32_t)0x00000800)
241 | #define RCC_PLL2Mul_11 ((uint32_t)0x00000900)
242 | #define RCC_PLL2Mul_12 ((uint32_t)0x00000A00)
243 | #define RCC_PLL2Mul_13 ((uint32_t)0x00000B00)
244 | #define RCC_PLL2Mul_14 ((uint32_t)0x00000C00)
245 | #define RCC_PLL2Mul_16 ((uint32_t)0x00000E00)
246 | #define RCC_PLL2Mul_20 ((uint32_t)0x00000F00)
247 |
248 | #define IS_RCC_PLL2_MUL(MUL) (((MUL) == RCC_PLL2Mul_8) || ((MUL) == RCC_PLL2Mul_9) || \
249 | ((MUL) == RCC_PLL2Mul_10) || ((MUL) == RCC_PLL2Mul_11) || \
250 | ((MUL) == RCC_PLL2Mul_12) || ((MUL) == RCC_PLL2Mul_13) || \
251 | ((MUL) == RCC_PLL2Mul_14) || ((MUL) == RCC_PLL2Mul_16) || \
252 | ((MUL) == RCC_PLL2Mul_20))
253 | /**
254 | * @}
255 | */
256 |
257 |
258 | /** @defgroup PLL3_multiplication_factor
259 | * @{
260 | */
261 |
262 | #define RCC_PLL3Mul_8 ((uint32_t)0x00006000)
263 | #define RCC_PLL3Mul_9 ((uint32_t)0x00007000)
264 | #define RCC_PLL3Mul_10 ((uint32_t)0x00008000)
265 | #define RCC_PLL3Mul_11 ((uint32_t)0x00009000)
266 | #define RCC_PLL3Mul_12 ((uint32_t)0x0000A000)
267 | #define RCC_PLL3Mul_13 ((uint32_t)0x0000B000)
268 | #define RCC_PLL3Mul_14 ((uint32_t)0x0000C000)
269 | #define RCC_PLL3Mul_16 ((uint32_t)0x0000E000)
270 | #define RCC_PLL3Mul_20 ((uint32_t)0x0000F000)
271 |
272 | #define IS_RCC_PLL3_MUL(MUL) (((MUL) == RCC_PLL3Mul_8) || ((MUL) == RCC_PLL3Mul_9) || \
273 | ((MUL) == RCC_PLL3Mul_10) || ((MUL) == RCC_PLL3Mul_11) || \
274 | ((MUL) == RCC_PLL3Mul_12) || ((MUL) == RCC_PLL3Mul_13) || \
275 | ((MUL) == RCC_PLL3Mul_14) || ((MUL) == RCC_PLL3Mul_16) || \
276 | ((MUL) == RCC_PLL3Mul_20))
277 | /**
278 | * @}
279 | */
280 |
281 | #endif /* STM32F10X_CL */
282 |
283 |
284 | /** @defgroup System_clock_source
285 | * @{
286 | */
287 |
288 | #define RCC_SYSCLKSource_HSI ((uint32_t)0x00000000)
289 | #define RCC_SYSCLKSource_HSE ((uint32_t)0x00000001)
290 | #define RCC_SYSCLKSource_PLLCLK ((uint32_t)0x00000002)
291 | #define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_HSI) || \
292 | ((SOURCE) == RCC_SYSCLKSource_HSE) || \
293 | ((SOURCE) == RCC_SYSCLKSource_PLLCLK))
294 | /**
295 | * @}
296 | */
297 |
298 | /** @defgroup AHB_clock_source
299 | * @{
300 | */
301 |
302 | #define RCC_SYSCLK_Div1 ((uint32_t)0x00000000)
303 | #define RCC_SYSCLK_Div2 ((uint32_t)0x00000080)
304 | #define RCC_SYSCLK_Div4 ((uint32_t)0x00000090)
305 | #define RCC_SYSCLK_Div8 ((uint32_t)0x000000A0)
306 | #define RCC_SYSCLK_Div16 ((uint32_t)0x000000B0)
307 | #define RCC_SYSCLK_Div64 ((uint32_t)0x000000C0)
308 | #define RCC_SYSCLK_Div128 ((uint32_t)0x000000D0)
309 | #define RCC_SYSCLK_Div256 ((uint32_t)0x000000E0)
310 | #define RCC_SYSCLK_Div512 ((uint32_t)0x000000F0)
311 | #define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_Div1) || ((HCLK) == RCC_SYSCLK_Div2) || \
312 | ((HCLK) == RCC_SYSCLK_Div4) || ((HCLK) == RCC_SYSCLK_Div8) || \
313 | ((HCLK) == RCC_SYSCLK_Div16) || ((HCLK) == RCC_SYSCLK_Div64) || \
314 | ((HCLK) == RCC_SYSCLK_Div128) || ((HCLK) == RCC_SYSCLK_Div256) || \
315 | ((HCLK) == RCC_SYSCLK_Div512))
316 | /**
317 | * @}
318 | */
319 |
320 | /** @defgroup APB1_APB2_clock_source
321 | * @{
322 | */
323 |
324 | #define RCC_HCLK_Div1 ((uint32_t)0x00000000)
325 | #define RCC_HCLK_Div2 ((uint32_t)0x00000400)
326 | #define RCC_HCLK_Div4 ((uint32_t)0x00000500)
327 | #define RCC_HCLK_Div8 ((uint32_t)0x00000600)
328 | #define RCC_HCLK_Div16 ((uint32_t)0x00000700)
329 | #define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_Div1) || ((PCLK) == RCC_HCLK_Div2) || \
330 | ((PCLK) == RCC_HCLK_Div4) || ((PCLK) == RCC_HCLK_Div8) || \
331 | ((PCLK) == RCC_HCLK_Div16))
332 | /**
333 | * @}
334 | */
335 |
336 | /** @defgroup RCC_Interrupt_source
337 | * @{
338 | */
339 |
340 | #define RCC_IT_LSIRDY ((uint8_t)0x01)
341 | #define RCC_IT_LSERDY ((uint8_t)0x02)
342 | #define RCC_IT_HSIRDY ((uint8_t)0x04)
343 | #define RCC_IT_HSERDY ((uint8_t)0x08)
344 | #define RCC_IT_PLLRDY ((uint8_t)0x10)
345 | #define RCC_IT_CSS ((uint8_t)0x80)
346 |
347 | #ifndef STM32F10X_CL
348 | #define IS_RCC_IT(IT) ((((IT) & (uint8_t)0xE0) == 0x00) && ((IT) != 0x00))
349 | #define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \
350 | ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \
351 | ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_CSS))
352 | #define IS_RCC_CLEAR_IT(IT) ((((IT) & (uint8_t)0x60) == 0x00) && ((IT) != 0x00))
353 | #else
354 | #define RCC_IT_PLL2RDY ((uint8_t)0x20)
355 | #define RCC_IT_PLL3RDY ((uint8_t)0x40)
356 | #define IS_RCC_IT(IT) ((((IT) & (uint8_t)0x80) == 0x00) && ((IT) != 0x00))
357 | #define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \
358 | ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \
359 | ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_CSS) || \
360 | ((IT) == RCC_IT_PLL2RDY) || ((IT) == RCC_IT_PLL3RDY))
361 | #define IS_RCC_CLEAR_IT(IT) ((IT) != 0x00)
362 | #endif /* STM32F10X_CL */
363 |
364 |
365 | /**
366 | * @}
367 | */
368 |
369 | #ifndef STM32F10X_CL
370 | /** @defgroup USB_Device_clock_source
371 | * @{
372 | */
373 |
374 | #define RCC_USBCLKSource_PLLCLK_1Div5 ((uint8_t)0x00)
375 | #define RCC_USBCLKSource_PLLCLK_Div1 ((uint8_t)0x01)
376 |
377 | #define IS_RCC_USBCLK_SOURCE(SOURCE) (((SOURCE) == RCC_USBCLKSource_PLLCLK_1Div5) || \
378 | ((SOURCE) == RCC_USBCLKSource_PLLCLK_Div1))
379 | /**
380 | * @}
381 | */
382 | #else
383 | /** @defgroup USB_OTG_FS_clock_source
384 | * @{
385 | */
386 | #define RCC_OTGFSCLKSource_PLLVCO_Div3 ((uint8_t)0x00)
387 | #define RCC_OTGFSCLKSource_PLLVCO_Div2 ((uint8_t)0x01)
388 |
389 | #define IS_RCC_OTGFSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_OTGFSCLKSource_PLLVCO_Div3) || \
390 | ((SOURCE) == RCC_OTGFSCLKSource_PLLVCO_Div2))
391 | /**
392 | * @}
393 | */
394 | #endif /* STM32F10X_CL */
395 |
396 |
397 | #ifdef STM32F10X_CL
398 | /** @defgroup I2S2_clock_source
399 | * @{
400 | */
401 | #define RCC_I2S2CLKSource_SYSCLK ((uint8_t)0x00)
402 | #define RCC_I2S2CLKSource_PLL3_VCO ((uint8_t)0x01)
403 |
404 | #define IS_RCC_I2S2CLK_SOURCE(SOURCE) (((SOURCE) == RCC_I2S2CLKSource_SYSCLK) || \
405 | ((SOURCE) == RCC_I2S2CLKSource_PLL3_VCO))
406 | /**
407 | * @}
408 | */
409 |
410 | /** @defgroup I2S3_clock_source
411 | * @{
412 | */
413 | #define RCC_I2S3CLKSource_SYSCLK ((uint8_t)0x00)
414 | #define RCC_I2S3CLKSource_PLL3_VCO ((uint8_t)0x01)
415 |
416 | #define IS_RCC_I2S3CLK_SOURCE(SOURCE) (((SOURCE) == RCC_I2S3CLKSource_SYSCLK) || \
417 | ((SOURCE) == RCC_I2S3CLKSource_PLL3_VCO))
418 | /**
419 | * @}
420 | */
421 | #endif /* STM32F10X_CL */
422 |
423 |
424 | /** @defgroup ADC_clock_source
425 | * @{
426 | */
427 |
428 | #define RCC_PCLK2_Div2 ((uint32_t)0x00000000)
429 | #define RCC_PCLK2_Div4 ((uint32_t)0x00004000)
430 | #define RCC_PCLK2_Div6 ((uint32_t)0x00008000)
431 | #define RCC_PCLK2_Div8 ((uint32_t)0x0000C000)
432 | #define IS_RCC_ADCCLK(ADCCLK) (((ADCCLK) == RCC_PCLK2_Div2) || ((ADCCLK) == RCC_PCLK2_Div4) || \
433 | ((ADCCLK) == RCC_PCLK2_Div6) || ((ADCCLK) == RCC_PCLK2_Div8))
434 | /**
435 | * @}
436 | */
437 |
438 | /** @defgroup LSE_configuration
439 | * @{
440 | */
441 |
442 | #define RCC_LSE_OFF ((uint8_t)0x00)
443 | #define RCC_LSE_ON ((uint8_t)0x01)
444 | #define RCC_LSE_Bypass ((uint8_t)0x04)
445 | #define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \
446 | ((LSE) == RCC_LSE_Bypass))
447 | /**
448 | * @}
449 | */
450 |
451 | /** @defgroup RTC_clock_source
452 | * @{
453 | */
454 |
455 | #define RCC_RTCCLKSource_LSE ((uint32_t)0x00000100)
456 | #define RCC_RTCCLKSource_LSI ((uint32_t)0x00000200)
457 | #define RCC_RTCCLKSource_HSE_Div128 ((uint32_t)0x00000300)
458 | #define IS_RCC_RTCCLK_SOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSource_LSE) || \
459 | ((SOURCE) == RCC_RTCCLKSource_LSI) || \
460 | ((SOURCE) == RCC_RTCCLKSource_HSE_Div128))
461 | /**
462 | * @}
463 | */
464 |
465 | /** @defgroup AHB_peripheral
466 | * @{
467 | */
468 |
469 | #define RCC_AHBPeriph_DMA1 ((uint32_t)0x00000001)
470 | #define RCC_AHBPeriph_DMA2 ((uint32_t)0x00000002)
471 | #define RCC_AHBPeriph_SRAM ((uint32_t)0x00000004)
472 | #define RCC_AHBPeriph_FLITF ((uint32_t)0x00000010)
473 | #define RCC_AHBPeriph_CRC ((uint32_t)0x00000040)
474 |
475 | #ifndef STM32F10X_CL
476 | #define RCC_AHBPeriph_FSMC ((uint32_t)0x00000100)
477 | #define RCC_AHBPeriph_SDIO ((uint32_t)0x00000400)
478 | #define IS_RCC_AHB_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFAA8) == 0x00) && ((PERIPH) != 0x00))
479 | #else
480 | #define RCC_AHBPeriph_OTG_FS ((uint32_t)0x00001000)
481 | #define RCC_AHBPeriph_ETH_MAC ((uint32_t)0x00004000)
482 | #define RCC_AHBPeriph_ETH_MAC_Tx ((uint32_t)0x00008000)
483 | #define RCC_AHBPeriph_ETH_MAC_Rx ((uint32_t)0x00010000)
484 |
485 | #define IS_RCC_AHB_PERIPH(PERIPH) ((((PERIPH) & 0xFFFE2FA8) == 0x00) && ((PERIPH) != 0x00))
486 | #define IS_RCC_AHB_PERIPH_RESET(PERIPH) ((((PERIPH) & 0xFFFFAFFF) == 0x00) && ((PERIPH) != 0x00))
487 | #endif /* STM32F10X_CL */
488 | /**
489 | * @}
490 | */
491 |
492 | /** @defgroup APB2_peripheral
493 | * @{
494 | */
495 |
496 | #define RCC_APB2Periph_AFIO ((uint32_t)0x00000001)
497 | #define RCC_APB2Periph_GPIOA ((uint32_t)0x00000004)
498 | #define RCC_APB2Periph_GPIOB ((uint32_t)0x00000008)
499 | #define RCC_APB2Periph_GPIOC ((uint32_t)0x00000010)
500 | #define RCC_APB2Periph_GPIOD ((uint32_t)0x00000020)
501 | #define RCC_APB2Periph_GPIOE ((uint32_t)0x00000040)
502 | #define RCC_APB2Periph_GPIOF ((uint32_t)0x00000080)
503 | #define RCC_APB2Periph_GPIOG ((uint32_t)0x00000100)
504 | #define RCC_APB2Periph_ADC1 ((uint32_t)0x00000200)
505 | #define RCC_APB2Periph_ADC2 ((uint32_t)0x00000400)
506 | #define RCC_APB2Periph_TIM1 ((uint32_t)0x00000800)
507 | #define RCC_APB2Periph_SPI1 ((uint32_t)0x00001000)
508 | #define RCC_APB2Periph_TIM8 ((uint32_t)0x00002000)
509 | #define RCC_APB2Periph_USART1 ((uint32_t)0x00004000)
510 | #define RCC_APB2Periph_ADC3 ((uint32_t)0x00008000)
511 | #define RCC_APB2Periph_TIM15 ((uint32_t)0x00010000)
512 | #define RCC_APB2Periph_TIM16 ((uint32_t)0x00020000)
513 | #define RCC_APB2Periph_TIM17 ((uint32_t)0x00040000)
514 | #define RCC_APB2Periph_TIM9 ((uint32_t)0x00080000)
515 | #define RCC_APB2Periph_TIM10 ((uint32_t)0x00100000)
516 | #define RCC_APB2Periph_TIM11 ((uint32_t)0x00200000)
517 |
518 | #define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFC00002) == 0x00) && ((PERIPH) != 0x00))
519 | /**
520 | * @}
521 | */
522 |
523 | /** @defgroup APB1_peripheral
524 | * @{
525 | */
526 |
527 | #define RCC_APB1Periph_TIM2 ((uint32_t)0x00000001)
528 | #define RCC_APB1Periph_TIM3 ((uint32_t)0x00000002)
529 | #define RCC_APB1Periph_TIM4 ((uint32_t)0x00000004)
530 | #define RCC_APB1Periph_TIM5 ((uint32_t)0x00000008)
531 | #define RCC_APB1Periph_TIM6 ((uint32_t)0x00000010)
532 | #define RCC_APB1Periph_TIM7 ((uint32_t)0x00000020)
533 | #define RCC_APB1Periph_TIM12 ((uint32_t)0x00000040)
534 | #define RCC_APB1Periph_TIM13 ((uint32_t)0x00000080)
535 | #define RCC_APB1Periph_TIM14 ((uint32_t)0x00000100)
536 | #define RCC_APB1Periph_WWDG ((uint32_t)0x00000800)
537 | #define RCC_APB1Periph_SPI2 ((uint32_t)0x00004000)
538 | #define RCC_APB1Periph_SPI3 ((uint32_t)0x00008000)
539 | #define RCC_APB1Periph_USART2 ((uint32_t)0x00020000)
540 | #define RCC_APB1Periph_USART3 ((uint32_t)0x00040000)
541 | #define RCC_APB1Periph_UART4 ((uint32_t)0x00080000)
542 | #define RCC_APB1Periph_UART5 ((uint32_t)0x00100000)
543 | #define RCC_APB1Periph_I2C1 ((uint32_t)0x00200000)
544 | #define RCC_APB1Periph_I2C2 ((uint32_t)0x00400000)
545 | #define RCC_APB1Periph_USB ((uint32_t)0x00800000)
546 | #define RCC_APB1Periph_CAN1 ((uint32_t)0x02000000)
547 | #define RCC_APB1Periph_CAN2 ((uint32_t)0x04000000)
548 | #define RCC_APB1Periph_BKP ((uint32_t)0x08000000)
549 | #define RCC_APB1Periph_PWR ((uint32_t)0x10000000)
550 | #define RCC_APB1Periph_DAC ((uint32_t)0x20000000)
551 | #define RCC_APB1Periph_CEC ((uint32_t)0x40000000)
552 |
553 | #define IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH) & 0x81013600) == 0x00) && ((PERIPH) != 0x00))
554 |
555 | /**
556 | * @}
557 | */
558 |
559 | /** @defgroup Clock_source_to_output_on_MCO_pin
560 | * @{
561 | */
562 |
563 | #define RCC_MCO_NoClock ((uint8_t)0x00)
564 | #define RCC_MCO_SYSCLK ((uint8_t)0x04)
565 | #define RCC_MCO_HSI ((uint8_t)0x05)
566 | #define RCC_MCO_HSE ((uint8_t)0x06)
567 | #define RCC_MCO_PLLCLK_Div2 ((uint8_t)0x07)
568 |
569 | #ifndef STM32F10X_CL
570 | #define IS_RCC_MCO(MCO) (((MCO) == RCC_MCO_NoClock) || ((MCO) == RCC_MCO_HSI) || \
571 | ((MCO) == RCC_MCO_SYSCLK) || ((MCO) == RCC_MCO_HSE) || \
572 | ((MCO) == RCC_MCO_PLLCLK_Div2))
573 | #else
574 | #define RCC_MCO_PLL2CLK ((uint8_t)0x08)
575 | #define RCC_MCO_PLL3CLK_Div2 ((uint8_t)0x09)
576 | #define RCC_MCO_XT1 ((uint8_t)0x0A)
577 | #define RCC_MCO_PLL3CLK ((uint8_t)0x0B)
578 |
579 | #define IS_RCC_MCO(MCO) (((MCO) == RCC_MCO_NoClock) || ((MCO) == RCC_MCO_HSI) || \
580 | ((MCO) == RCC_MCO_SYSCLK) || ((MCO) == RCC_MCO_HSE) || \
581 | ((MCO) == RCC_MCO_PLLCLK_Div2) || ((MCO) == RCC_MCO_PLL2CLK) || \
582 | ((MCO) == RCC_MCO_PLL3CLK_Div2) || ((MCO) == RCC_MCO_XT1) || \
583 | ((MCO) == RCC_MCO_PLL3CLK))
584 | #endif /* STM32F10X_CL */
585 |
586 | /**
587 | * @}
588 | */
589 |
590 | /** @defgroup RCC_Flag
591 | * @{
592 | */
593 |
594 | #define RCC_FLAG_HSIRDY ((uint8_t)0x21)
595 | #define RCC_FLAG_HSERDY ((uint8_t)0x31)
596 | #define RCC_FLAG_PLLRDY ((uint8_t)0x39)
597 | #define RCC_FLAG_LSERDY ((uint8_t)0x41)
598 | #define RCC_FLAG_LSIRDY ((uint8_t)0x61)
599 | #define RCC_FLAG_PINRST ((uint8_t)0x7A)
600 | #define RCC_FLAG_PORRST ((uint8_t)0x7B)
601 | #define RCC_FLAG_SFTRST ((uint8_t)0x7C)
602 | #define RCC_FLAG_IWDGRST ((uint8_t)0x7D)
603 | #define RCC_FLAG_WWDGRST ((uint8_t)0x7E)
604 | #define RCC_FLAG_LPWRRST ((uint8_t)0x7F)
605 |
606 | #ifndef STM32F10X_CL
607 | #define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \
608 | ((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \
609 | ((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_PINRST) || \
610 | ((FLAG) == RCC_FLAG_PORRST) || ((FLAG) == RCC_FLAG_SFTRST) || \
611 | ((FLAG) == RCC_FLAG_IWDGRST)|| ((FLAG) == RCC_FLAG_WWDGRST)|| \
612 | ((FLAG) == RCC_FLAG_LPWRRST))
613 | #else
614 | #define RCC_FLAG_PLL2RDY ((uint8_t)0x3B)
615 | #define RCC_FLAG_PLL3RDY ((uint8_t)0x3D)
616 | #define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \
617 | ((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \
618 | ((FLAG) == RCC_FLAG_PLL2RDY) || ((FLAG) == RCC_FLAG_PLL3RDY) || \
619 | ((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_PINRST) || \
620 | ((FLAG) == RCC_FLAG_PORRST) || ((FLAG) == RCC_FLAG_SFTRST) || \
621 | ((FLAG) == RCC_FLAG_IWDGRST)|| ((FLAG) == RCC_FLAG_WWDGRST)|| \
622 | ((FLAG) == RCC_FLAG_LPWRRST))
623 | #endif /* STM32F10X_CL */
624 |
625 | #define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F)
626 | /**
627 | * @}
628 | */
629 |
630 | /**
631 | * @}
632 | */
633 |
634 | /** @defgroup RCC_Exported_Macros
635 | * @{
636 | */
637 |
638 | /**
639 | * @}
640 | */
641 |
642 | /** @defgroup RCC_Exported_Functions
643 | * @{
644 | */
645 |
646 | void RCC_DeInit(void);
647 | void RCC_HSEConfig(uint32_t RCC_HSE);
648 | ErrorStatus RCC_WaitForHSEStartUp(void);
649 | void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue);
650 | void RCC_HSICmd(FunctionalState NewState);
651 | void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul);
652 | void RCC_PLLCmd(FunctionalState NewState);
653 |
654 | #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_CL)
655 | void RCC_PREDIV1Config(uint32_t RCC_PREDIV1_Source, uint32_t RCC_PREDIV1_Div);
656 | #endif
657 |
658 | #ifdef STM32F10X_CL
659 | void RCC_PREDIV2Config(uint32_t RCC_PREDIV2_Div);
660 | void RCC_PLL2Config(uint32_t RCC_PLL2Mul);
661 | void RCC_PLL2Cmd(FunctionalState NewState);
662 | void RCC_PLL3Config(uint32_t RCC_PLL3Mul);
663 | void RCC_PLL3Cmd(FunctionalState NewState);
664 | #endif /* STM32F10X_CL */
665 |
666 | void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource);
667 | uint8_t RCC_GetSYSCLKSource(void);
668 | void RCC_HCLKConfig(uint32_t RCC_SYSCLK);
669 | void RCC_PCLK1Config(uint32_t RCC_HCLK);
670 | void RCC_PCLK2Config(uint32_t RCC_HCLK);
671 | void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState);
672 |
673 | #ifndef STM32F10X_CL
674 | void RCC_USBCLKConfig(uint32_t RCC_USBCLKSource);
675 | #else
676 | void RCC_OTGFSCLKConfig(uint32_t RCC_OTGFSCLKSource);
677 | #endif /* STM32F10X_CL */
678 |
679 | void RCC_ADCCLKConfig(uint32_t RCC_PCLK2);
680 |
681 | #ifdef STM32F10X_CL
682 | void RCC_I2S2CLKConfig(uint32_t RCC_I2S2CLKSource);
683 | void RCC_I2S3CLKConfig(uint32_t RCC_I2S3CLKSource);
684 | #endif /* STM32F10X_CL */
685 |
686 | void RCC_LSEConfig(uint8_t RCC_LSE);
687 | void RCC_LSICmd(FunctionalState NewState);
688 | void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource);
689 | void RCC_RTCCLKCmd(FunctionalState NewState);
690 | void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks);
691 | void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState);
692 | void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
693 | void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
694 |
695 | #ifdef STM32F10X_CL
696 | void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState);
697 | #endif /* STM32F10X_CL */
698 |
699 | void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
700 | void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
701 | void RCC_BackupResetCmd(FunctionalState NewState);
702 | void RCC_ClockSecuritySystemCmd(FunctionalState NewState);
703 | void RCC_MCOConfig(uint8_t RCC_MCO);
704 | FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG);
705 | void RCC_ClearFlag(void);
706 | ITStatus RCC_GetITStatus(uint8_t RCC_IT);
707 | void RCC_ClearITPendingBit(uint8_t RCC_IT);
708 |
709 | #ifdef __cplusplus
710 | }
711 | #endif
712 |
713 | #endif /* __STM32F10x_RCC_H */
714 | /**
715 | * @}
716 | */
717 |
718 | /**
719 | * @}
720 | */
721 |
722 | /**
723 | * @}
724 | */
725 |
726 | /******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
727 |
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