├── .gitignore ├── mig_example.srcs ├── sources_1 │ ├── ip │ │ ├── pll.xcix │ │ └── mig │ │ │ ├── mig │ │ │ ├── example_design │ │ │ │ ├── sim │ │ │ │ │ ├── sim.do │ │ │ │ │ ├── ies_run.sh │ │ │ │ │ ├── vcs_run.sh │ │ │ │ │ ├── xsim_options.tcl │ │ │ │ │ ├── xsim_run.sh │ │ │ │ │ ├── wiredly.v │ │ │ │ │ ├── readme.txt │ │ │ │ │ └── xsim_files.prj │ │ │ │ ├── par │ │ │ │ │ ├── readme.txt │ │ │ │ │ └── example_top.xdc │ │ │ │ └── rtl │ │ │ │ │ └── traffic_gen │ │ │ │ │ ├── mig_7series_v4_2_data_prbs_gen.v │ │ │ │ │ ├── mig_7series_v4_2_tg_status.v │ │ │ │ │ ├── mig_7series_v4_2_afifo.v │ │ │ │ │ ├── mig_7series_v4_2_write_data_path.v │ │ │ │ │ ├── mig_7series_v4_2_read_posted_fifo.v │ │ │ │ │ ├── mig_7series_v4_2_cmd_prbs_gen.v │ │ │ │ │ ├── mig_7series_v4_2_tg_prbs_gen.v │ │ │ │ │ ├── mig_7series_v4_2_rd_data_gen.v │ │ │ │ │ ├── mig_7series_v4_2_vio_init_pattern_bram.v │ │ │ │ │ └── mig_7series_v4_2_wr_data_gen.v │ │ │ ├── docs │ │ │ │ └── phy_only_support_readme.txt │ │ │ ├── datasheet.txt │ │ │ └── mig.prj │ │ │ ├── xil_txt.out │ │ │ ├── xil_txt.in │ │ │ ├── mig_a.prj │ │ │ └── mig_xmdf.tcl │ └── new │ │ ├── ff_sync.v │ │ ├── flag_sync.v │ │ ├── mig_example_tb.v │ │ └── mem_example.v ├── io_def.vh └── mig_example_top.v ├── Nexys 4 Onboard DDR2 MIG Configuration.odt ├── Nexys 4 Onboard DDR2 MIG Configuration.pdf ├── README.md ├── mig.ucf └── mig_example.xpr /.gitignore: -------------------------------------------------------------------------------- 1 | mig_example.* 2 | !mig_example.xpr 3 | !mig_example.srcs 4 | -------------------------------------------------------------------------------- /mig_example.srcs/sources_1/ip/pll.xcix: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ChrisPVille/mig_example/HEAD/mig_example.srcs/sources_1/ip/pll.xcix -------------------------------------------------------------------------------- /Nexys 4 Onboard DDR2 MIG Configuration.odt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ChrisPVille/mig_example/HEAD/Nexys 4 Onboard DDR2 MIG Configuration.odt -------------------------------------------------------------------------------- /Nexys 4 Onboard DDR2 MIG Configuration.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ChrisPVille/mig_example/HEAD/Nexys 4 Onboard DDR2 MIG Configuration.pdf -------------------------------------------------------------------------------- /mig_example.srcs/io_def.vh: -------------------------------------------------------------------------------- 1 | //Raisin64 IO related defines 2 | 3 | `define RAM_WIDTH64 2'h0 4 | `define RAM_WIDTH32 2'h1 5 | `define RAM_WIDTH16 2'h2 6 | `define RAM_WIDTH8 2'h3 7 | -------------------------------------------------------------------------------- /mig_example.srcs/sources_1/ip/mig/mig/example_design/sim/sim.do: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ChrisPVille/mig_example/HEAD/mig_example.srcs/sources_1/ip/mig/mig/example_design/sim/sim.do -------------------------------------------------------------------------------- /mig_example.srcs/sources_1/ip/mig/xil_txt.out: -------------------------------------------------------------------------------- 1 | SET_ERROR_CODE 0 2 | SET_XMDF_PATH ./mig_xmdf.tcl 3 | SET_PARAMETER component_name mig 4 | SET_PARAMETER xml_input_file ./mig/mig.prj 5 | -------------------------------------------------------------------------------- /mig_example.srcs/sources_1/ip/mig/mig/example_design/sim/ies_run.sh: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ChrisPVille/mig_example/HEAD/mig_example.srcs/sources_1/ip/mig/mig/example_design/sim/ies_run.sh -------------------------------------------------------------------------------- /mig_example.srcs/sources_1/ip/mig/mig/example_design/sim/vcs_run.sh: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ChrisPVille/mig_example/HEAD/mig_example.srcs/sources_1/ip/mig/mig/example_design/sim/vcs_run.sh -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # Xilinx MIG Example 2 | This project serves as a simple reference design for using the onboard DDR2 memory with Xilinx MIG IP of the Nexys 4 DDR / Nexys A7 FPGA Trainer board. 3 | 4 | The included [step-by-step PDF guide](Nexys%204%20Onboard%20DDR2%20MIG%20Configuration.pdf) walks through the configuration process. 5 | -------------------------------------------------------------------------------- /mig_example.srcs/sources_1/new/ff_sync.v: -------------------------------------------------------------------------------- 1 | module ff_sync #(parameter WIDTH=1)( 2 | input clk, 3 | input rst_p, 4 | input[WIDTH-1:0] in_async, 5 | output reg[WIDTH-1:0] out); 6 | 7 | (* ASYNC_REG = "TRUE" *) reg[WIDTH-1:0] sync_reg; 8 | always @(posedge clk, posedge rst_p) begin 9 | if(rst_p) begin 10 | sync_reg <= 0; 11 | out <= 0; 12 | end else begin 13 | {out, sync_reg} <= {sync_reg, in_async}; 14 | end 15 | end 16 | 17 | endmodule 18 | -------------------------------------------------------------------------------- /mig_example.srcs/sources_1/new/flag_sync.v: -------------------------------------------------------------------------------- 1 | module flag_sync( 2 | input a_rst_n, 3 | input a_clk, 4 | input a_flag, 5 | input b_rst_n, 6 | input b_clk, 7 | output b_flag 8 | ); 9 | 10 | reg flag; 11 | always @(posedge a_clk or negedge a_rst_n) begin 12 | if(~a_rst_n) flag <= 0; 13 | else flag <= flag ^ a_flag; 14 | end 15 | 16 | (* ASYNC_REG = "TRUE" *) reg[2:0] flag_sync; 17 | always @(posedge b_clk or negedge b_rst_n) begin 18 | if(~b_rst_n) flag_sync <= 3'h0; 19 | else flag_sync <= {flag_sync[1:0], flag}; 20 | end 21 | 22 | assign b_flag = flag_sync[1] ^ flag_sync[2]; 23 | 24 | endmodule 25 | -------------------------------------------------------------------------------- /mig_example.srcs/sources_1/ip/mig/mig/docs/phy_only_support_readme.txt: -------------------------------------------------------------------------------- 1 | This file includes the information about the PHY layer support: 2 | 3 | - Folder "/user_design/rtl/phy" includes the PHY layer 4 | RTL modules. 5 | - The top-level PHY module to be instantiated is ddr_phy_top (ddr_phy_top.v) 6 | - PHY modules can be used in any environment by taking the RTL modules 7 | listed in "phy" folder and PHY layer needs to be connected to 8 | the memory controller. 9 | - Refer to User Guide (UG586) section "Physical Layer Interface (Non-Memory 10 | Controller Design)" for more details on PHY interface signaling, 11 | parameter(s) and timing information. 12 | 13 | -------------------------------------------------------------------------------- /mig_example.srcs/sources_1/ip/mig/mig/example_design/par/readme.txt: -------------------------------------------------------------------------------- 1 | Files in PAR folder : 2 | 3 | * "example_top.xdc" file is the constraint file for the design. This is used 4 | by Vivado. It has clock constraints, location constraints, IO standards 5 | and false path/SLICE constraints if any. 6 | 7 | * LTX/probe file is required when programming BIT file to FPGA as it contains 8 | the information of debug signals like signal name and position with respect 9 | to ILA/VIO core. The probe file (debug_nets.ltx) is auto generated by 10 | vivado tool and is found in .runs/impl_1/debug_nets.ltx 11 | 12 | 13 | compatible_ucf folder: 14 | 15 | * MIG outputs this folder only when Pin Compatible FPGAs are checked in GUI 16 | (Pin Compatible FPGAs page in GUI). It generates the XDC files for all 17 | the Compatible FPGAs selected in GUI. If you want to switch to any of the 18 | Compatible FPGAs follow the steps mentioned below. 19 | 20 | -------------------------------------------------------------------------------- /mig_example.srcs/sources_1/ip/mig/xil_txt.in: -------------------------------------------------------------------------------- 1 | SET_FLAG MODE BATCH 2 | SET_FLAG STANDALONE_MODE TRUE 3 | SET_PREFERENCE ipi_mode no 4 | SET_PREFERENCE is_ip_locked false 5 | SET_PREFERENCE devicefamily artix7 6 | SET_PREFERENCE device xc7a100t 7 | SET_PREFERENCE speedgrade -1 8 | SET_PREFERENCE package csg324 9 | SET_PREFERENCE verilogsim true 10 | SET_PREFERENCE vhdlsim false 11 | SET_PREFERENCE designentry Verilog 12 | SET_PREFERENCE outputdirectory /home/christopher/git/mig_example/mig_example.srcs/sources_1/ip/mig/_tmp/ 13 | SET_PREFERENCE subworkingdirectory /home/christopher/git/mig_example/mig_example.srcs/sources_1/ip/mig/_tmp/ 14 | SET_PREFERENCE flowvendor Other 15 | SET_PREFERENCE tool vivado 16 | SET_PREFERENCE compnamestatus 0 17 | SET_PARAMETER component_name mig 18 | SET_PARAMETER xml_input_file /home/christopher/git/mig_example/mig_example.srcs/sources_1/ip/mig/mig_a.prj 19 | SET_PARAMETER data_dir_path /home/christopher/storage/Vivado/2018.3/data/ip/xilinx/mig_7series_v4_2 20 | SET_CORE_NAME Memory Interface Generator (MIG 7 Series) 21 | SET_CORE_VERSION 4.2 22 | SET_CORE_VLNV xilinx.com:ip:mig_7series:4.2 23 | SET_CORE_PATH /home/christopher/storage/Vivado/2018.3/data/ip/xilinx/mig_7series_v4_2 24 | SET_CORE_DATASHEET /home/christopher/storage/Vivado/2018.3/data/ip/xilinx/mig_7series_v4_2/data/docs/ds176_7series_MIS.pdf 25 | -------------------------------------------------------------------------------- /mig_example.srcs/sources_1/ip/mig/mig/example_design/par/example_top.xdc: -------------------------------------------------------------------------------- 1 | ################################################################################################## 2 | ## 3 | ## Xilinx, Inc. 2010 www.xilinx.com 4 | ## Tue May 14 22:13:37 2019 5 | 6 | ## Generated by MIG Version 4.2 7 | ## 8 | ################################################################################################## 9 | ## File name : example_top.xdc 10 | ## Details : Constraints file 11 | ## FPGA Family: ARTIX7 12 | ## FPGA Part: XC7A100T-CSG324 13 | ## Speedgrade: -1 14 | ## Design Entry: VERILOG 15 | ## Frequency: 300.02999999999997 MHz 16 | ## Time Period: 3333 ps 17 | ################################################################################################## 18 | 19 | ################################################################################################## 20 | ## Controller 0 21 | ## Memory Device: DDR2_SDRAM->Components->MT47H64M16HR-25E 22 | ## Data Width: 16 23 | ## Time Period: 3333 24 | ## Data Mask: 1 25 | ################################################################################################## 26 | ############## NET - IOSTANDARD ################## 27 | 28 | 29 | 30 | set_property INTERNAL_VREF 0.900 [get_iobanks 34] -------------------------------------------------------------------------------- /mig_example.srcs/sources_1/new/mig_example_tb.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns/1ns 2 | 3 | module mig_example_tb(); 4 | 5 | reg clk, rst_n; 6 | wire[15:0] LED; 7 | 8 | ////// DDR2 Model ////// 9 | wire ddr2_ck_p, ddr2_ck_n, ddr2_cke, ddr2_cs_n, ddr2_ras_n, ddr2_cas_n, ddr2_we_n, ddr2_odt; 10 | wire[15:0] ddr2_dq; 11 | wire[1:0] ddr2_dqs_n; 12 | wire[1:0] ddr2_dqs_p; 13 | wire[12:0] ddr2_addr; 14 | wire[2:0] ddr2_ba; 15 | wire[1:0] ddr2_dm; 16 | 17 | ddr2_model fake_ddr2( 18 | .ck(ddr2_ck_p), 19 | .ck_n(ddr2_ck_n), 20 | .cke(ddr2_cke), 21 | .cs_n(ddr2_cs_n), 22 | .ras_n(ddr2_ras_n), 23 | .cas_n(ddr2_cas_n), 24 | .we_n(ddr2_we_n), 25 | .dm_rdqs(ddr2_dm), 26 | .ba(ddr2_ba), 27 | .addr(ddr2_addr), 28 | .dq(ddr2_dq), 29 | .dqs(ddr2_dqs_p), 30 | .dqs_n(ddr2_dqs_n), 31 | .rdqs_n(), 32 | .odt(ddr2_odt) 33 | ); 34 | 35 | ////////// DUT ////////// 36 | mig_example_top dut( 37 | .CLK100MHZ(clk), 38 | .CPU_RESETN(rst_n), 39 | 40 | .LED(LED), 41 | 42 | .ddr2_addr(ddr2_addr), 43 | .ddr2_ba(ddr2_ba), 44 | .ddr2_cas_n(ddr2_cas_n), 45 | .ddr2_ck_n(ddr2_ck_n), 46 | .ddr2_ck_p(ddr2_ck_p), 47 | .ddr2_cke(ddr2_cke), 48 | .ddr2_ras_n(ddr2_ras_n), 49 | .ddr2_we_n(ddr2_we_n), 50 | .ddr2_dq(ddr2_dq), 51 | .ddr2_dqs_n(ddr2_dqs_n), 52 | .ddr2_dqs_p(ddr2_dqs_p), 53 | .ddr2_cs_n(ddr2_cs_n), 54 | .ddr2_dm(ddr2_dm), 55 | .ddr2_odt(ddr2_odt) 56 | ); 57 | 58 | ////////// Test Process ////////// 59 | 60 | initial begin 61 | clk = 1; 62 | forever #5 clk = ~clk; 63 | end 64 | 65 | initial 66 | begin 67 | rst_n = 0; 68 | #15 rst_n = 1; 69 | 70 | #100000 $finish; 71 | end 72 | 73 | endmodule 74 | -------------------------------------------------------------------------------- /mig_example.srcs/sources_1/ip/mig/mig/datasheet.txt: -------------------------------------------------------------------------------- 1 | 2 | 3 | Vivado Project Options: 4 | Target Device : xc7a100t-csg324 5 | Speed Grade : -1 6 | HDL : verilog 7 | Synthesis Tool : VIVADO 8 | 9 | MIG Output Options: 10 | Module Name : mig 11 | No of Controllers : 1 12 | Selected Compatible Device(s) : -- 13 | 14 | FPGA Options: 15 | System Clock Type : No Buffer 16 | Reference Clock Type : Use System Clock 17 | Debug Port : OFF 18 | Internal Vref : enabled 19 | IO Power Reduction : ON 20 | XADC instantiation in MIG : Enabled 21 | 22 | Extended FPGA Options: 23 | DCI for DQ,DQS/DQS#,DM : enabled 24 | Internal Termination (HR Banks) : 50 Ohms 25 | 26 | /*******************************************************/ 27 | /* Controller 0 */ 28 | /*******************************************************/ 29 | Controller Options : 30 | Memory : DDR2_SDRAM 31 | Interface : NATIVE 32 | Design Clock Frequency : 3333 ps ( 0.00 MHz) 33 | Phy to Controller Clock Ratio : 2:1 34 | Input Clock Period : 4999 ps 35 | CLKFBOUT_MULT (PLL) : 6 36 | DIVCLK_DIVIDE (PLL) : 1 37 | VCC_AUX IO : 1.8V 38 | Memory Type : Components 39 | Memory Part : MT47H64M16HR-25E 40 | Equivalent Part(s) : -- 41 | Data Width : 16 42 | ECC : Disabled 43 | Data Mask : enabled 44 | ORDERING : Strict 45 | 46 | AXI Parameters : 47 | Data Width : 64 48 | Arbitration Scheme : RD_PRI_REG 49 | Narrow Burst Support : 0 50 | ID Width : 4 51 | 52 | Memory Options: 53 | Burst Length (MR0[1:0]) : 8 54 | CAS Latency (MR0[6:4]) : 5 55 | Output Drive Strength (MR1[5,1]) : Fullstrength 56 | Controller CS option : Enable 57 | Rtt_NOM - ODT (MR1[9,6,2]) : 50ohms 58 | Memory Address Mapping : BANK_ROW_COLUMN 59 | 60 | 61 | Bank Selections: 62 | Bank: 34 63 | Byte Group T0: Address/Ctrl-1 64 | Byte Group T1: DQ[8-15] 65 | Byte Group T2: Address/Ctrl-0 66 | Byte Group T3: DQ[0-7] 67 | 68 | System_Control: 69 | SignalName: sys_rst 70 | PadLocation: No connect Bank: Select Bank 71 | SignalName: init_calib_complete 72 | PadLocation: No connect Bank: Select Bank 73 | SignalName: tg_compare_error 74 | PadLocation: No connect Bank: Select Bank 75 | 76 | 77 | 78 | 79 | -------------------------------------------------------------------------------- /mig_example.srcs/sources_1/ip/mig/mig/example_design/sim/xsim_options.tcl: -------------------------------------------------------------------------------- 1 | ############################################################################### 2 | ## (c) Copyright 2012 Xilinx, Inc. All rights reserved. 3 | ## 4 | ## This file contains confidential and proprietary information 5 | ## of Xilinx, Inc. and is protected under U.S. and 6 | ## international copyright and other intellectual property 7 | ## laws. 8 | ## 9 | ## DISCLAIMER 10 | ## This disclaimer is not a license and does not grant any 11 | ## rights to the materials distributed herewith. Except as 12 | ## otherwise provided in a valid license issued to you by 13 | ## Xilinx, and to the maximum extent permitted by applicable 14 | ## law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 15 | ## WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 16 | ## AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 17 | ## BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 18 | ## INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 19 | ## (2) Xilinx shall not be liable (whether in contract or tort, 20 | ## including negligence, or under any other theory of 21 | ## liability) for any loss or damage of any kind or nature 22 | ## related to, arising under or in connection with these 23 | ## materials, including for any direct, or any indirect, 24 | ## special, incidental, or consequential loss or damage 25 | ## (including loss of data, profits, goodwill, or any type of 26 | ## loss or damage suffered as a result of any action brought 27 | ## by a third party) even if such damage or loss was 28 | ## reasonably foreseeable or Xilinx had been advised of the 29 | ## possibility of the same. 30 | ## 31 | ## CRITICAL APPLICATIONS 32 | ## Xilinx products are not designed or intended to be fail- 33 | ## safe, or for use in any application requiring fail-safe 34 | ## performance, such as life-support or safety devices or 35 | ## systems, Class III medical devices, nuclear facilities, 36 | ## applications related to the deployment of airbags, or any 37 | ## other applications that could lead to death, personal 38 | ## injury, or severe property or environmental damage 39 | ## (individually and collectively, "Critical 40 | ## Applications"). Customer assumes the sole risk and 41 | ## liability of any use of Xilinx products in Critical 42 | ## Applications, subject only to applicable laws and 43 | ## regulations governing limitations on product liability. 44 | ## 45 | ## THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 46 | ## PART OF THIS FILE AT ALL TIMES. 47 | ## 48 | ############################################################################### 49 | ## ____ ____ 50 | ## / /\/ / 51 | ## /___/ \ / Vendor : Xilinx 52 | ## \ \ \/ Version : 4.2 53 | ## \ \ Application : MIG 54 | ## / / Filename : xsim_options.tcl 55 | ## /___/ /\ Date Last Modified : $Date: 2011/06/02 08:31:16 $ 56 | ## \ \ / \ Date Created : Tue Jun 05 2012 57 | ## \___\/\___\ 58 | ## 59 | ## Device : 7 Series 60 | ## Design Name : DDR2 SDRAM 61 | ## Purpose : To give commands to XSIM Simulator through batch mode 62 | ## Assumptions: 63 | ## - Simulation takes place in \sim folder of MIG output directory 64 | ## Reference : 65 | ## Revision History: 66 | ############################################################################### 67 | 68 | 69 | add_wave -radix hex /sim_tb_top 70 | run 1000 us 71 | 72 | -------------------------------------------------------------------------------- /mig_example.srcs/sources_1/ip/mig/mig/example_design/sim/xsim_run.sh: -------------------------------------------------------------------------------- 1 | #!/bin/csh -f 2 | #***************************************************************************** 3 | # (c) Copyright 2012 Xilinx, Inc. All rights reserved. 4 | # 5 | # This file contains confidential and proprietary information 6 | # of Xilinx, Inc. and is protected under U.S. and 7 | # international copyright and other intellectual property 8 | # laws. 9 | # 10 | # DISCLAIMER 11 | # This disclaimer is not a license and does not grant any 12 | # rights to the materials distributed herewith. Except as 13 | # otherwise provided in a valid license issued to you by 14 | # Xilinx, and to the maximum extent permitted by applicable 15 | # law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 16 | # WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 17 | # AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 18 | # BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 19 | # INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 20 | # (2) Xilinx shall not be liable (whether in contract or tort, 21 | # including negligence, or under any other theory of 22 | # liability) for any loss or damage of any kind or nature 23 | # related to, arising under or in connection with these 24 | # materials, including for any direct, or any indirect, 25 | # special, incidental, or consequential loss or damage 26 | # (including loss of data, profits, goodwill, or any type of 27 | # loss or damage suffered as a result of any action brought 28 | # by a third party) even if such damage or loss was 29 | # reasonably foreseeable or Xilinx had been advised of the 30 | # possibility of the same. 31 | # 32 | # CRITICAL APPLICATIONS 33 | # Xilinx products are not designed or intended to be fail- 34 | # safe, or for use in any application requiring fail-safe 35 | # performance, such as life-support or safety devices or 36 | # systems, Class III medical devices, nuclear facilities, 37 | # applications related to the deployment of airbags, or any 38 | # other applications that could lead to death, personal 39 | # injury, or severe property or environmental damage 40 | # (individually and collectively, "Critical 41 | # Applications"). Customer assumes the sole risk and 42 | # liability of any use of Xilinx products in Critical 43 | # Applications, subject only to applicable laws and 44 | # regulations governing limitations on product liability. 45 | # 46 | # THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 47 | # PART OF THIS FILE AT ALL TIMES. 48 | # 49 | # **************************************************************************** 50 | # ____ ____ 51 | # / /\/ / 52 | # /___/ \ / Vendor : Xilinx 53 | # \ \ \/ Version : 4.2 54 | # \ \ Application : MIG 55 | # / / Filename : xsim_run.bat 56 | # /___/ /\ Date Last Modified : $Date: 2011/06/02 08:31:16 $ 57 | # \ \ / \ Date Created : Tue Jun 05 2012 58 | # \___\/\___\ 59 | # 60 | # Device : 7 Series 61 | # Design Name : DDR2 SDRAM 62 | # Purpose : Batch file to run Simulation through Vivado Simulator 63 | # Reference : 64 | # Revision History : 65 | # **************************************************************************** 66 | 67 | 68 | echo Simulation Tool: Viavdo Simulator 69 | xelab work.sim_tb_top work.glbl -prj xsim_files.prj -L unisims_ver -L secureip -s xsim_test -debug typical 70 | xsim -g -t xsim_options.tcl -wdb xsim_database.wdb xsim_test 71 | echo done 72 | 73 | -------------------------------------------------------------------------------- /mig_example.srcs/mig_example_top.v: -------------------------------------------------------------------------------- 1 | module mig_example_top( 2 | input CLK100MHZ, 3 | input CPU_RESETN, 4 | 5 | output[15:0] LED, 6 | 7 | //RAM Interface 8 | inout[15:0] ddr2_dq, 9 | inout[1:0] ddr2_dqs_n, 10 | inout[1:0] ddr2_dqs_p, 11 | output[12:0] ddr2_addr, 12 | output[2:0] ddr2_ba, 13 | output ddr2_ras_n, 14 | output ddr2_cas_n, 15 | output ddr2_we_n, 16 | output ddr2_ck_p, 17 | output ddr2_ck_n, 18 | output ddr2_cke, 19 | output ddr2_cs_n, 20 | output[1:0] ddr2_dm, 21 | output ddr2_odt 22 | ); 23 | 24 | ////////// Clock Generation ////////// 25 | wire clk_cpu, clk_mem; 26 | wire pll_locked; 27 | 28 | pll pll1( 29 | .locked(pll_locked), 30 | .clk_in(CLK100MHZ), 31 | .clk_mem(clk_mem), //200MHz Memory Reference Clock 32 | .clk_cpu(clk_cpu) //Clock used for traffic generator 33 | ); 34 | 35 | ////////// Reset Sync/Stretch ////////// 36 | reg[31:0] rst_stretch = 32'hFFFFFFFF; 37 | wire reset_req_n, rst_n; 38 | 39 | assign reset_req_n = CPU_RESETN & pll_locked; 40 | 41 | always @(posedge clk_cpu) rst_stretch = {reset_req_n,rst_stretch[31:1]}; 42 | assign rst_n = reset_req_n & &rst_stretch; 43 | 44 | ////////// DUT ////////// 45 | wire[63:0] mem_d_from_ram; 46 | wire mem_transaction_complete; 47 | wire mem_ready; 48 | 49 | reg[27:0] mem_addr; 50 | reg[63:0] mem_d_to_ram; 51 | reg[1:0] mem_transaction_width; 52 | reg mem_wstrobe, mem_rstrobe; 53 | 54 | mem_example mem_ex( 55 | .clk_mem(clk_mem), 56 | .rst_n(rst_n), 57 | 58 | .ddr2_addr(ddr2_addr), 59 | .ddr2_ba(ddr2_ba), 60 | .ddr2_cas_n(ddr2_cas_n), 61 | .ddr2_ck_n(ddr2_ck_n), 62 | .ddr2_ck_p(ddr2_ck_p), 63 | .ddr2_cke(ddr2_cke), 64 | .ddr2_ras_n(ddr2_ras_n), 65 | .ddr2_we_n(ddr2_we_n), 66 | .ddr2_dq(ddr2_dq), 67 | .ddr2_dqs_n(ddr2_dqs_n), 68 | .ddr2_dqs_p(ddr2_dqs_p), 69 | .ddr2_cs_n(ddr2_cs_n), 70 | .ddr2_dm(ddr2_dm), 71 | .ddr2_odt(ddr2_odt), 72 | 73 | .cpu_clk(clk_cpu), 74 | .addr(mem_addr), 75 | .width(mem_transaction_width), 76 | .data_in(mem_d_to_ram), 77 | .data_out(mem_d_from_ram), 78 | .rstrobe(mem_rstrobe), 79 | .wstrobe(mem_wstrobe), 80 | .transaction_complete(mem_transaction_complete), 81 | .ready(mem_ready) 82 | ); 83 | 84 | ////////// Traffic Generator ////////// 85 | reg[31:0] lfsr; 86 | 87 | always @(posedge clk_cpu or negedge rst_n) begin 88 | if(~rst_n) lfsr <= 32'h0; 89 | else begin 90 | lfsr[31:1] <= lfsr[30:0]; 91 | lfsr[0] <= ~^{lfsr[31], lfsr[21], lfsr[1:0]}; 92 | end 93 | end 94 | 95 | localparam TGEN_GEN_AD = 3'h0; 96 | localparam TGEN_WRITE = 3'h1; 97 | localparam TGEN_WWAIT = 3'h2; 98 | localparam TGEN_READ = 3'h3; 99 | localparam TGEN_RWAIT = 3'h4; 100 | 101 | reg[2:0] tgen_state; 102 | reg dequ; //Data read from RAM equals data written 103 | 104 | always @(posedge clk_cpu or negedge rst_n) begin 105 | if(~rst_n) begin 106 | tgen_state <= TGEN_GEN_AD; 107 | mem_rstrobe <= 1'b0; 108 | mem_wstrobe <= 1'b0; 109 | mem_addr <= 64'h0; 110 | mem_d_to_ram <= 28'h0; 111 | mem_transaction_width <= 3'h0; 112 | dequ <= 1'b0; 113 | end else begin 114 | case(tgen_state) 115 | TGEN_GEN_AD: begin 116 | mem_addr <= lfsr[27:0]; 117 | mem_d_to_ram <= {~lfsr,lfsr}; 118 | tgen_state <= TGEN_WRITE; 119 | end 120 | TGEN_WRITE: begin 121 | if(mem_ready) begin 122 | mem_wstrobe <= 1; 123 | //Write the entire 64-bit word 124 | mem_transaction_width <= `RAM_WIDTH64; 125 | tgen_state <= TGEN_WWAIT; 126 | end 127 | end 128 | TGEN_WWAIT: begin 129 | mem_wstrobe <= 0; 130 | if(mem_transaction_complete) begin 131 | tgen_state <= TGEN_READ; 132 | end 133 | end 134 | TGEN_READ: begin 135 | if(mem_ready) begin 136 | mem_rstrobe <= 1; 137 | //Load only the single byte at that address 138 | mem_transaction_width <= `RAM_WIDTH16; 139 | tgen_state <= TGEN_RWAIT; 140 | end 141 | end 142 | TGEN_RWAIT: begin 143 | mem_rstrobe <= 0; 144 | if(mem_transaction_complete) begin 145 | tgen_state <= TGEN_GEN_AD; 146 | if(mem_d_from_ram[63:48] == mem_d_to_ram[63:48]) dequ <= 1; 147 | else dequ <= 0; 148 | end 149 | end 150 | endcase 151 | end 152 | end 153 | 154 | assign LED[0] = dequ; 155 | 156 | endmodule 157 | -------------------------------------------------------------------------------- /mig_example.srcs/sources_1/ip/mig/mig/example_design/rtl/traffic_gen/mig_7series_v4_2_data_prbs_gen.v: -------------------------------------------------------------------------------- 1 | //***************************************************************************** 2 | // (c) Copyright 2008-2010 Xilinx, Inc. All rights reserved. 3 | // 4 | // This file contains confidential and proprietary information 5 | // of Xilinx, Inc. and is protected under U.S. and 6 | // international copyright and other intellectual property 7 | // laws. 8 | // 9 | // DISCLAIMER 10 | // This disclaimer is not a license and does not grant any 11 | // rights to the materials distributed herewith. Except as 12 | // otherwise provided in a valid license issued to you by 13 | // Xilinx, and to the maximum extent permitted by applicable 14 | // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 15 | // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 16 | // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 17 | // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 18 | // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 19 | // (2) Xilinx shall not be liable (whether in contract or tort, 20 | // including negligence, or under any other theory of 21 | // liability) for any loss or damage of any kind or nature 22 | // related to, arising under or in connection with these 23 | // materials, including for any direct, or any indirect, 24 | // special, incidental, or consequential loss or damage 25 | // (including loss of data, profits, goodwill, or any type of 26 | // loss or damage suffered as a result of any action brought 27 | // by a third party) even if such damage or loss was 28 | // reasonably foreseeable or Xilinx had been advised of the 29 | // possibility of the same. 30 | // 31 | // CRITICAL APPLICATIONS 32 | // Xilinx products are not designed or intended to be fail- 33 | // safe, or for use in any application requiring fail-safe 34 | // performance, such as life-support or safety devices or 35 | // systems, Class III medical devices, nuclear facilities, 36 | // applications related to the deployment of airbags, or any 37 | // other applications that could lead to death, personal 38 | // injury, or severe property or environmental damage 39 | // (individually and collectively, "Critical 40 | // Applications"). Customer assumes the sole risk and 41 | // liability of any use of Xilinx products in Critical 42 | // Applications, subject only to applicable laws and 43 | // regulations governing limitations on product liability. 44 | // 45 | // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 46 | // PART OF THIS FILE AT ALL TIMES. 47 | // 48 | //***************************************************************************** 49 | // ____ ____ 50 | // / /\/ / 51 | // /___/ \ / Vendor: Xilinx 52 | // \ \ \/ Version: %version 53 | // \ \ Application: MIG 54 | // / / Filename: data_prbs_gen.v 55 | // /___/ /\ Date Last Modified: $Date: 2011/06/02 08:37:19 $ 56 | // \ \ / \ Date Created: Fri Sep 01 2006 57 | // \___\/\___\ 58 | // 59 | //Device: Spartan6 60 | //Design Name: DDR/DDR2/DDR3/LPDDR 61 | //Purpose: This module is used LFSR to generate random data for memory 62 | // data write or memory data read comparison.The first data is 63 | // seeded by the input prbs_seed_i which is connected to memory address. 64 | //Reference: 65 | //Revision History: 66 | //***************************************************************************** 67 | 68 | `timescale 1ps/1ps 69 | 70 | module mig_7series_v4_2_data_prbs_gen # 71 | ( 72 | parameter TCQ = 100, 73 | 74 | parameter EYE_TEST = "FALSE", 75 | parameter PRBS_WIDTH = 32, // "SEQUENTIAL_BUrst_i" 76 | parameter SEED_WIDTH = 32 77 | ) 78 | ( 79 | input clk_i, 80 | input clk_en, 81 | input rst_i, 82 | input prbs_seed_init, // when high the prbs_x_seed will be loaded 83 | input [PRBS_WIDTH - 1:0] prbs_seed_i, 84 | 85 | output [PRBS_WIDTH - 1:0] prbs_o // generated address 86 | ); 87 | 88 | reg [PRBS_WIDTH - 1 :0] prbs; 89 | reg [PRBS_WIDTH :1] lfsr_q; 90 | integer i; 91 | 92 | 93 | 94 | always @ (posedge clk_i) 95 | begin 96 | if (prbs_seed_init && EYE_TEST == "FALSE" || rst_i ) //reset it to a known good state to prevent it locks up 97 | // if (rst_i ) //reset it to a known good state to prevent it locks up 98 | 99 | begin 100 | lfsr_q[4:1] <= #TCQ prbs_seed_i[3:0] | 4'h5; 101 | // lfsr_q[PRBS_WIDTH-1:4] <= #TCQ prbs_seed_i[PRBS_WIDTH-1:4] ; 102 | 103 | lfsr_q[PRBS_WIDTH:5] <= #TCQ prbs_seed_i[PRBS_WIDTH-1:4] ; 104 | end 105 | else if (clk_en) begin 106 | 107 | lfsr_q[32:9] <= #TCQ lfsr_q[31:8]; 108 | lfsr_q[8] <= #TCQ lfsr_q[32] ^ lfsr_q[7]; 109 | lfsr_q[7] <= #TCQ lfsr_q[32] ^ lfsr_q[6]; 110 | lfsr_q[6:4] <= #TCQ lfsr_q[5:3]; 111 | 112 | lfsr_q[3] <= #TCQ lfsr_q[32] ^ lfsr_q[2]; 113 | lfsr_q[2] <= #TCQ lfsr_q[1] ; 114 | lfsr_q[1] <= #TCQ lfsr_q[32]; 115 | 116 | 117 | end 118 | end 119 | 120 | always @ (lfsr_q[PRBS_WIDTH:1]) begin 121 | prbs = lfsr_q[PRBS_WIDTH:1]; 122 | end 123 | 124 | assign prbs_o = prbs; 125 | 126 | endmodule 127 | 128 | 129 | -------------------------------------------------------------------------------- /mig_example.srcs/sources_1/ip/mig/mig/example_design/rtl/traffic_gen/mig_7series_v4_2_tg_status.v: -------------------------------------------------------------------------------- 1 | //***************************************************************************** 2 | // (c) Copyright 2008-2010 Xilinx, Inc. All rights reserved. 3 | // 4 | // This file contains confidential and proprietary information 5 | // of Xilinx, Inc. and is protected under U.S. and 6 | // international copyright and other intellectual property 7 | // laws. 8 | // 9 | // DISCLAIMER 10 | // This disclaimer is not a license and does not grant any 11 | // rights to the materials distributed herewith. Except as 12 | // otherwise provided in a valid license issued to you by 13 | // Xilinx, and to the maximum extent permitted by applicable 14 | // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 15 | // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 16 | // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 17 | // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 18 | // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 19 | // (2) Xilinx shall not be liable (whether in contract or tort, 20 | // including negligence, or under any other theory of 21 | // liability) for any loss or damage of any kind or nature 22 | // related to, arising under or in connection with these 23 | // materials, including for any direct, or any indirect, 24 | // special, incidental, or consequential loss or damage 25 | // (including loss of data, profits, goodwill, or any type of 26 | // loss or damage suffered as a result of any action brought 27 | // by a third party) even if such damage or loss was 28 | // reasonably foreseeable or Xilinx had been advised of the 29 | // possibility of the same. 30 | // 31 | // CRITICAL APPLICATIONS 32 | // Xilinx products are not designed or intended to be fail- 33 | // safe, or for use in any application requiring fail-safe 34 | // performance, such as life-support or safety devices or 35 | // systems, Class III medical devices, nuclear facilities, 36 | // applications related to the deployment of airbags, or any 37 | // other applications that could lead to death, personal 38 | // injury, or severe property or environmental damage 39 | // (individually and collectively, "Critical 40 | // Applications"). Customer assumes the sole risk and 41 | // liability of any use of Xilinx products in Critical 42 | // Applications, subject only to applicable laws and 43 | // regulations governing limitations on product liability. 44 | // 45 | // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 46 | // PART OF THIS FILE AT ALL TIMES. 47 | // 48 | //***************************************************************************** 49 | // ____ ____ 50 | // / /\/ / 51 | // /___/ \ / Vendor: Xilinx 52 | // \ \ \/ Version: %version 53 | // \ \ Application: MIG 54 | // / / Filename: tg_status.v 55 | // /___/ /\ Date Last Modified: 56 | // \ \ / \ Date Created: 57 | // \___\/\___\ 58 | // 59 | //Device: Spartan6 60 | //Design Name: DDR/DDR2/DDR3/LPDDR 61 | //Purpose: This module compare the memory read data agaisnt compare data that generated from data_gen module. 62 | // Error signal will be asserted if the comparsion is not equal. 63 | //Reference: 64 | //Revision History: 65 | //***************************************************************************** 66 | 67 | `timescale 1ps/1ps 68 | 69 | 70 | module mig_7series_v4_2_tg_status #( 71 | parameter TCQ = 100, 72 | 73 | parameter DWIDTH = 32 74 | ) 75 | ( 76 | 77 | 78 | input clk_i , 79 | input rst_i , 80 | input manual_clear_error, 81 | input data_error_i , 82 | input [DWIDTH-1:0] cmp_data_i, 83 | input [DWIDTH-1:0] rd_data_i , 84 | input [31:0] cmp_addr_i , 85 | input [5:0] cmp_bl_i , 86 | input mcb_cmd_full_i , 87 | input mcb_wr_full_i, 88 | input mcb_rd_empty_i, 89 | output reg [64 + (2*DWIDTH - 1):0] error_status, 90 | output error 91 | ); 92 | 93 | reg data_error_r; 94 | reg error_set; 95 | assign error = error_set; 96 | 97 | always @ (posedge clk_i) 98 | data_error_r <= #TCQ data_error_i; 99 | 100 | always @ (posedge clk_i) 101 | begin 102 | 103 | if (rst_i || manual_clear_error) begin 104 | error_status <= #TCQ 'b0; 105 | error_set <= #TCQ 1'b0; 106 | end 107 | else begin 108 | // latch the first error only 109 | if (data_error_i && ~data_error_r && ~error_set ) begin 110 | error_status[31:0] <= #TCQ cmp_addr_i; 111 | error_status[37:32] <= #TCQ cmp_bl_i; 112 | error_status[40] <= #TCQ mcb_cmd_full_i; 113 | error_status[41] <= #TCQ mcb_wr_full_i; 114 | error_status[42] <= #TCQ mcb_rd_empty_i; 115 | error_set <= #TCQ 1'b1; 116 | error_status[64 + (DWIDTH - 1) :64] <= #TCQ cmp_data_i; 117 | error_status[64 + (2*DWIDTH - 1):64 + DWIDTH] <= #TCQ rd_data_i; 118 | 119 | end 120 | 121 | error_status[39:38] <= #TCQ 'b0; // reserved 122 | error_status[63:43] <= #TCQ 'b0; // reserved 123 | 124 | 125 | end end 126 | 127 | endmodule 128 | -------------------------------------------------------------------------------- /mig_example.srcs/sources_1/ip/mig/mig/example_design/sim/wiredly.v: -------------------------------------------------------------------------------- 1 | //***************************************************************************** 2 | // (c) Copyright 2009 - 2011 Xilinx, Inc. All rights reserved. 3 | // 4 | // This file contains confidential and proprietary information 5 | // of Xilinx, Inc. and is protected under U.S. and 6 | // international copyright and other intellectual property 7 | // laws. 8 | // 9 | // DISCLAIMER 10 | // This disclaimer is not a license and does not grant any 11 | // rights to the materials distributed herewith. Except as 12 | // otherwise provided in a valid license issued to you by 13 | // Xilinx, and to the maximum extent permitted by applicable 14 | // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 15 | // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 16 | // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 17 | // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 18 | // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 19 | // (2) Xilinx shall not be liable (whether in contract or tort, 20 | // including negligence, or under any other theory of 21 | // liability) for any loss or damage of any kind or nature 22 | // related to, arising under or in connection with these 23 | // materials, including for any direct, or any indirect, 24 | // special, incidental, or consequential loss or damage 25 | // (including loss of data, profits, goodwill, or any type of 26 | // loss or damage suffered as a result of any action brought 27 | // by a third party) even if such damage or loss was 28 | // reasonably foreseeable or Xilinx had been advised of the 29 | // possibility of the same. 30 | // 31 | // CRITICAL APPLICATIONS 32 | // Xilinx products are not designed or intended to be fail- 33 | // safe, or for use in any application requiring fail-safe 34 | // performance, such as life-support or safety devices or 35 | // systems, Class III medical devices, nuclear facilities, 36 | // applications related to the deployment of airbags, or any 37 | // other applications that could lead to death, personal 38 | // injury, or severe property or environmental damage 39 | // (individually and collectively, "Critical 40 | // Applications"). Customer assumes the sole risk and 41 | // liability of any use of Xilinx products in Critical 42 | // Applications, subject only to applicable laws and 43 | // regulations governing limitations on product liability. 44 | // 45 | // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 46 | // PART OF THIS FILE AT ALL TIMES. 47 | // 48 | //***************************************************************************** 49 | // ____ ____ 50 | // / /\/ / 51 | // /___/ \ / Vendor : Xilinx 52 | // \ \ \/ Version : 4.2 53 | // \ \ Application : MIG 54 | // / / Filename : wiredly.v 55 | // /___/ /\ Date Last Modified : $Date: 2011/06/23 08:25:20 $ 56 | // \ \ / \ Date Created : Fri Oct 14 2011 57 | // \___\/\___\ 58 | // 59 | // Device : 7Series 60 | // Design Name : DDR2 SDRAM 61 | // Purpose : 62 | // This module provide the definition of a zero ohm component (A, B). 63 | // 64 | // The applications of this component include: 65 | // . Normal operation of a jumper wire (data flowing in both directions) 66 | // This can corrupt data from DRAM to FPGA useful for verifying ECC function. 67 | // 68 | // The component consists of 2 ports: 69 | // . Port A: One side of the pass-through switch 70 | // . Port B: The other side of the pass-through switch 71 | 72 | // The model is sensitive to transactions on all ports. Once a transaction 73 | // is detected, all other transactions are ignored for that simulation time 74 | // (i.e. further transactions in that delta time are ignored). 75 | 76 | // Model Limitations and Restrictions: 77 | // Signals asserted on the ports of the error injector should not have 78 | // transactions occuring in multiple delta times because the model 79 | // is sensitive to transactions on port A, B ONLY ONCE during 80 | // a simulation time. Thus, once fired, a process will 81 | // not refire if there are multiple transactions occuring in delta times. 82 | // This condition may occur in gate level simulations with 83 | // ZERO delays because transactions may occur in multiple delta times. 84 | // 85 | // Reference : 86 | // Revision History : 87 | //***************************************************************************** 88 | 89 | `timescale 1ns / 1ps 90 | 91 | module WireDelay # ( 92 | parameter Delay_g = 0, 93 | parameter Delay_rd = 0, 94 | parameter ERR_INSERT = "OFF" 95 | ) 96 | ( 97 | inout A, 98 | inout B, 99 | input reset, 100 | input phy_init_done 101 | ); 102 | 103 | reg A_r; 104 | reg B_r; 105 | reg B_inv ; 106 | reg line_en; 107 | 108 | reg B_nonX; 109 | 110 | assign A = A_r; 111 | assign B = B_r; 112 | 113 | always @ (*) 114 | begin 115 | if (B === 1'bx) 116 | B_nonX <= $random; 117 | else 118 | B_nonX <= B; 119 | end 120 | 121 | always@(*) 122 | begin 123 | if((B_nonX == 'b1) || (B_nonX == 'b0)) 124 | B_inv <= #0 ~B_nonX ; 125 | else 126 | B_inv <= #0 'bz ; 127 | end 128 | 129 | always @(*) begin 130 | if (!reset) begin 131 | A_r <= 1'bz; 132 | B_r <= 1'bz; 133 | line_en <= 1'b0; 134 | end else begin 135 | if (line_en) begin 136 | B_r <= 1'bz; 137 | if ((ERR_INSERT == "ON") & (phy_init_done)) 138 | A_r <= #Delay_rd B_inv; 139 | else 140 | A_r <= #Delay_rd B_nonX; 141 | end else begin 142 | B_r <= #Delay_g A; 143 | A_r <= 1'bz; 144 | end 145 | end 146 | end 147 | 148 | always @(A or B) begin 149 | if (!reset) begin 150 | line_en <= 1'b0; 151 | end else if (A !== A_r) begin 152 | line_en <= 1'b0; 153 | end else if (B_r !== B) begin 154 | line_en <= 1'b1; 155 | end else begin 156 | line_en <= line_en; 157 | end 158 | end 159 | endmodule 160 | 161 | -------------------------------------------------------------------------------- /mig.ucf: -------------------------------------------------------------------------------- 1 | NET "ddr2_dq[0]" LOC = "R7" | IOSTANDARD = SSTL18_II ; 2 | NET "ddr2_dq[1]" LOC = "V6" | IOSTANDARD = SSTL18_II ; 3 | NET "ddr2_dq[2]" LOC = "R8" | IOSTANDARD = SSTL18_II ; 4 | NET "ddr2_dq[3]" LOC = "U7" | IOSTANDARD = SSTL18_II ; 5 | NET "ddr2_dq[4]" LOC = "V7" | IOSTANDARD = SSTL18_II ; 6 | NET "ddr2_dq[5]" LOC = "R6" | IOSTANDARD = SSTL18_II ; 7 | NET "ddr2_dq[6]" LOC = "U6" | IOSTANDARD = SSTL18_II ; 8 | NET "ddr2_dq[7]" LOC = "R5" | IOSTANDARD = SSTL18_II ; 9 | NET "ddr2_dq[8]" LOC = "T5" | IOSTANDARD = SSTL18_II ; 10 | NET "ddr2_dq[9]" LOC = "U3" | IOSTANDARD = SSTL18_II ; 11 | NET "ddr2_dq[10]" LOC = "V5" | IOSTANDARD = SSTL18_II ; 12 | NET "ddr2_dq[11]" LOC = "U4" | IOSTANDARD = SSTL18_II ; 13 | NET "ddr2_dq[12]" LOC = "V4" | IOSTANDARD = SSTL18_II ; 14 | NET "ddr2_dq[13]" LOC = "T4" | IOSTANDARD = SSTL18_II ; 15 | NET "ddr2_dq[14]" LOC = "V1" | IOSTANDARD = SSTL18_II ; 16 | NET "ddr2_dq[15]" LOC = "T3" | IOSTANDARD = SSTL18_II ; 17 | NET "ddr2_dm[0]" LOC = "T6" | IOSTANDARD = SSTL18_II ; 18 | NET "ddr2_dm[1]" LOC = "U1" | IOSTANDARD = SSTL18_II ; 19 | NET "ddr2_dqs_p[0]" LOC = "U9" | IOSTANDARD = DIFF_SSTL18_II ; 20 | NET "ddr2_dqs_n[0]" LOC = "V9" | IOSTANDARD = DIFF_SSTL18_II ; 21 | NET "ddr2_dqs_p[1]" LOC = "U2" | IOSTANDARD = DIFF_SSTL18_II ; 22 | NET "ddr2_dqs_n[1]" LOC = "V2" | IOSTANDARD = DIFF_SSTL18_II ; 23 | NET "ddr2_addr[12]" LOC = "N6" | IOSTANDARD = SSTL18_II ; 24 | NET "ddr2_addr[11]" LOC = "K5" | IOSTANDARD = SSTL18_II ; 25 | NET "ddr2_addr[10]" LOC = "R2" | IOSTANDARD = SSTL18_II ; 26 | NET "ddr2_addr[9]" LOC = "N5" | IOSTANDARD = SSTL18_II ; 27 | NET "ddr2_addr[8]" LOC = "L4" | IOSTANDARD = SSTL18_II ; 28 | NET "ddr2_addr[7]" LOC = "N1" | IOSTANDARD = SSTL18_II ; 29 | NET "ddr2_addr[6]" LOC = "M2" | IOSTANDARD = SSTL18_II ; 30 | NET "ddr2_addr[5]" LOC = "P5" | IOSTANDARD = SSTL18_II ; 31 | NET "ddr2_addr[4]" LOC = "L3" | IOSTANDARD = SSTL18_II ; 32 | NET "ddr2_addr[3]" LOC = "T1" | IOSTANDARD = SSTL18_II ; 33 | NET "ddr2_addr[2]" LOC = "M6" | IOSTANDARD = SSTL18_II ; 34 | NET "ddr2_addr[1]" LOC = "P4" | IOSTANDARD = SSTL18_II ; 35 | NET "ddr2_addr[0]" LOC = "M4" | IOSTANDARD = SSTL18_II ; 36 | NET "ddr2_ba[2]" LOC = "R1" | IOSTANDARD = SSTL18_II ; 37 | NET "ddr2_ba[1]" LOC = "P3" | IOSTANDARD = SSTL18_II ; 38 | NET "ddr2_ba[0]" LOC = "P2" | IOSTANDARD = SSTL18_II ; 39 | NET "ddr2_ck_p[0]" LOC = "L6" | IOSTANDARD = DIFF_SSTL18_II ; 40 | NET "ddr2_ck_n[0]" LOC = "L5" | IOSTANDARD = DIFF_SSTL18_II ; 41 | NET "ddr2_ras_n" LOC = "N4" | IOSTANDARD = SSTL18_II ; 42 | NET "ddr2_cas_n" LOC = "L1" | IOSTANDARD = SSTL18_II ; 43 | NET "ddr2_we_n" LOC = "N2" | IOSTANDARD = SSTL18_II ; 44 | NET "ddr2_cke[0]" LOC = "M1" | IOSTANDARD = SSTL18_II ; 45 | NET "ddr2_odt[0]" LOC = "M3" | IOSTANDARD = SSTL18_II ; 46 | NET "ddr2_cs_n[0]" LOC = "K6" | IOSTANDARD = SSTL18_II ; 47 | -------------------------------------------------------------------------------- /mig_example.srcs/sources_1/ip/mig/mig/example_design/rtl/traffic_gen/mig_7series_v4_2_afifo.v: -------------------------------------------------------------------------------- 1 | //***************************************************************************** 2 | // (c) Copyright 2008-2010 Xilinx, Inc. All rights reserved. 3 | // 4 | // This file contains confidential and proprietary information 5 | // of Xilinx, Inc. and is protected under U.S. and 6 | // international copyright and other intellectual property 7 | // laws. 8 | // 9 | // DISCLAIMER 10 | // This disclaimer is not a license and does not grant any 11 | // rights to the materials distributed herewith. Except as 12 | // otherwise provided in a valid license issued to you by 13 | // Xilinx, and to the maximum extent permitted by applicable 14 | // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 15 | // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 16 | // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 17 | // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 18 | // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 19 | // (2) Xilinx shall not be liable (whether in contract or tort, 20 | // including negligence, or under any other theory of 21 | // liability) for any loss or damage of any kind or nature 22 | // related to, arising under or in connection with these 23 | // materials, including for any direct, or any indirect, 24 | // special, incidental, or consequential loss or damage 25 | // (including loss of data, profits, goodwill, or any type of 26 | // loss or damage suffered as a result of any action brought 27 | // by a third party) even if such damage or loss was 28 | // reasonably foreseeable or Xilinx had been advised of the 29 | // possibility of the same. 30 | // 31 | // CRITICAL APPLICATIONS 32 | // Xilinx products are not designed or intended to be fail- 33 | // safe, or for use in any application requiring fail-safe 34 | // performance, such as life-support or safety devices or 35 | // systems, Class III medical devices, nuclear facilities, 36 | // applications related to the deployment of airbags, or any 37 | // other applications that could lead to death, personal 38 | // injury, or severe property or environmental damage 39 | // (individually and collectively, "Critical 40 | // Applications"). Customer assumes the sole risk and 41 | // liability of any use of Xilinx products in Critical 42 | // Applications, subject only to applicable laws and 43 | // regulations governing limitations on product liability. 44 | // 45 | // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 46 | // PART OF THIS FILE AT ALL TIMES. 47 | // 48 | //***************************************************************************** 49 | // ____ ____ 50 | // / /\/ / 51 | // /___/ \ / Vendor: Xilinx 52 | // \ \ \/ Version: %version 53 | // \ \ Application: MIG 54 | // / / Filename: afifo.v 55 | // /___/ /\ Date Last Modified: $Date: 2011/06/02 08:37:18 $ 56 | // \ \ / \ Date Created: Oct 21 2008 57 | // \___\/\___\ 58 | // 59 | //Device: Spartan6 60 | //Design Name: DDR/DDR2/DDR3/LPDDR 61 | //Purpose: A generic synchronous fifo. 62 | //Reference: 63 | //Revision History: 1.2 11/8/2010 Removed unused signals. 64 | 65 | //***************************************************************************** 66 | 67 | `timescale 1ps/1ps 68 | 69 | module mig_7series_v4_2_afifo # 70 | ( 71 | parameter TCQ = 100, 72 | parameter DSIZE = 32, 73 | parameter FIFO_DEPTH = 16, 74 | parameter ASIZE = 4, 75 | parameter SYNC = 1 // only has always '1' logic. 76 | ) 77 | ( 78 | input wr_clk, 79 | input rst, 80 | input wr_en, 81 | input [DSIZE-1:0] wr_data, 82 | input rd_en, 83 | input rd_clk, 84 | output [DSIZE-1:0] rd_data, 85 | output reg full, 86 | output reg empty, 87 | output reg almost_full 88 | ); 89 | 90 | // memory array 91 | reg [DSIZE-1:0] mem [0:FIFO_DEPTH-1]; 92 | 93 | //Read Capture Logic 94 | // if Sync = 1, then no need to remove metastability logic because wrclk = rdclk 95 | reg [ASIZE:0] rd_capture_ptr; 96 | reg [ASIZE:0] pre_rd_capture_gray_ptr; 97 | reg [ASIZE:0] rd_capture_gray_ptr; 98 | 99 | reg [ASIZE:0] wr_capture_ptr; 100 | reg [ASIZE:0] pre_wr_capture_gray_ptr; 101 | reg [ASIZE:0] wr_capture_gray_ptr; 102 | wire [ASIZE:0] buf_avail; 103 | wire [ASIZE:0] buf_filled; 104 | wire [ASIZE-1:0] wr_addr, rd_addr; 105 | wire COutb,COutd; 106 | reg COuta,COutc; 107 | reg [ASIZE:0] wr_ptr, rd_ptr,rd_ptr_cp; 108 | integer i,j,k; 109 | 110 | 111 | always @ (rd_ptr) 112 | rd_capture_ptr = rd_ptr; 113 | 114 | 115 | 116 | //capture the wr_gray_pointers to rd_clk domains and convert the gray pointers to binary pointers 117 | // before do comparison. 118 | 119 | 120 | 121 | always @ (wr_ptr) 122 | wr_capture_ptr = wr_ptr; 123 | 124 | // dualport ram 125 | // Memory (RAM) that holds the contents of the FIFO 126 | 127 | 128 | assign wr_addr = wr_ptr[ASIZE-1:0]; 129 | assign rd_data = mem[rd_addr]; 130 | always @(posedge wr_clk) 131 | begin 132 | if (wr_en && !full) 133 | mem[wr_addr] <= #TCQ wr_data; 134 | 135 | end 136 | 137 | 138 | // Read Side Logic 139 | 140 | 141 | assign rd_addr = rd_ptr_cp[ASIZE-1:0]; 142 | assign rd_strobe = rd_en && !empty; 143 | 144 | integer n; 145 | // change the binary pointer to gray pointer 146 | 147 | 148 | always @(posedge rd_clk) 149 | begin 150 | if (rst) 151 | begin 152 | rd_ptr <= #TCQ 'b0; 153 | rd_ptr_cp <= #TCQ 'b0; 154 | 155 | end 156 | else begin 157 | if (rd_strobe) begin 158 | {COuta,rd_ptr} <= #TCQ rd_ptr + 1'b1; 159 | rd_ptr_cp <= #TCQ rd_ptr_cp + 1'b1; 160 | 161 | end 162 | 163 | // change the binary pointer to gray pointer 164 | end 165 | 166 | end 167 | 168 | //generate empty signal 169 | assign {COutb,buf_filled} = wr_capture_ptr - rd_ptr; 170 | 171 | always @ (posedge rd_clk ) 172 | begin 173 | if (rst) 174 | empty <= #TCQ 1'b1; 175 | else if ((buf_filled == 0) || (buf_filled == 1 && rd_strobe)) 176 | empty <= #TCQ 1'b1; 177 | else 178 | empty <= #TCQ 1'b0; 179 | end 180 | 181 | 182 | // write side logic; 183 | 184 | reg [ASIZE:0] wbin; 185 | wire [ASIZE:0] wgraynext, wbinnext; 186 | 187 | 188 | 189 | always @(posedge rd_clk) 190 | begin 191 | if (rst) 192 | begin 193 | wr_ptr <= #TCQ 'b0; 194 | end 195 | else begin 196 | if (wr_en) 197 | {COutc, wr_ptr} <= #TCQ wr_ptr + 1'b1; 198 | 199 | // change the binary pointer to gray pointer 200 | end 201 | 202 | end 203 | 204 | 205 | // calculate how many buf still available 206 | //assign {COutd,buf_avail }= (rd_capture_ptr + 5'd16) - wr_ptr; 207 | assign {COutd,buf_avail }= rd_capture_ptr - wr_ptr + + 5'd16; 208 | 209 | 210 | always @ (posedge wr_clk ) 211 | begin 212 | if (rst) 213 | full <= #TCQ 1'b0; 214 | else if ((buf_avail == 0) || (buf_avail == 1 && wr_en)) 215 | full <= #TCQ 1'b1; 216 | else 217 | full <= #TCQ 1'b0; 218 | end 219 | 220 | 221 | always @ (posedge wr_clk ) 222 | begin 223 | if (rst) 224 | almost_full <= #TCQ 1'b0; 225 | else if ((buf_avail == FIFO_DEPTH - 2 ) || ((buf_avail == FIFO_DEPTH -3) && wr_en)) 226 | almost_full <= #TCQ 1'b1; 227 | else 228 | almost_full <= #TCQ 1'b0; 229 | end 230 | 231 | endmodule 232 | -------------------------------------------------------------------------------- /mig_example.srcs/sources_1/ip/mig/mig/example_design/rtl/traffic_gen/mig_7series_v4_2_write_data_path.v: -------------------------------------------------------------------------------- 1 | //***************************************************************************** 2 | // (c) Copyright 2008-2010 Xilinx, Inc. All rights reserved. 3 | // 4 | // This file contains confidential and proprietary information 5 | // of Xilinx, Inc. and is protected under U.S. and 6 | // international copyright and other intellectual property 7 | // laws. 8 | // 9 | // DISCLAIMER 10 | // This disclaimer is not a license and does not grant any 11 | // rights to the materials distributed herewith. Except as 12 | // otherwise provided in a valid license issued to you by 13 | // Xilinx, and to the maximum extent permitted by applicable 14 | // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 15 | // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 16 | // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 17 | // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 18 | // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 19 | // (2) Xilinx shall not be liable (whether in contract or tort, 20 | // including negligence, or under any other theory of 21 | // liability) for any loss or damage of any kind or nature 22 | // related to, arising under or in connection with these 23 | // materials, including for any direct, or any indirect, 24 | // special, incidental, or consequential loss or damage 25 | // (including loss of data, profits, goodwill, or any type of 26 | // loss or damage suffered as a result of any action brought 27 | // by a third party) even if such damage or loss was 28 | // reasonably foreseeable or Xilinx had been advised of the 29 | // possibility of the same. 30 | // 31 | // CRITICAL APPLICATIONS 32 | // Xilinx products are not designed or intended to be fail- 33 | // safe, or for use in any application requiring fail-safe 34 | // performance, such as life-support or safety devices or 35 | // systems, Class III medical devices, nuclear facilities, 36 | // applications related to the deployment of airbags, or any 37 | // other applications that could lead to death, personal 38 | // injury, or severe property or environmental damage 39 | // (individually and collectively, "Critical 40 | // Applications"). Customer assumes the sole risk and 41 | // liability of any use of Xilinx products in Critical 42 | // Applications, subject only to applicable laws and 43 | // regulations governing limitations on product liability. 44 | // 45 | // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 46 | // PART OF THIS FILE AT ALL TIMES. 47 | // 48 | //***************************************************************************** 49 | // ____ ____ 50 | // / /\/ / 51 | // /___/ \ / Vendor: Xilinx 52 | // \ \ \/ Version: %version 53 | // \ \ Application: MIG 54 | // / / Filename: write_data_path.v 55 | // /___/ /\ Date Last Modified: 56 | // \ \ / \ Date Created: 57 | // \___\/\___\ 58 | // 59 | //Device: Spartan6 60 | //Design Name: DDR/DDR2/DDR3/LPDDR 61 | //Purpose: This is top level of write path . 62 | 63 | //Reference: 64 | //Revision History: 65 | //***************************************************************************** 66 | 67 | `timescale 1ps/1ps 68 | 69 | 70 | module mig_7series_v4_2_write_data_path #( 71 | parameter TCQ = 100, 72 | parameter FAMILY = "SPARTAN6", 73 | parameter MEM_TYPE = "DDR3", 74 | 75 | parameter ADDR_WIDTH = 32, 76 | parameter START_ADDR = 32'h00000000, 77 | parameter BL_WIDTH = 6, 78 | parameter nCK_PER_CLK = 4, // DRAM clock : MC clock 79 | parameter MEM_BURST_LEN = 8, 80 | parameter DWIDTH = 32, 81 | parameter DATA_PATTERN = "DGEN_ALL", //"DGEN__HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL" 82 | parameter NUM_DQ_PINS = 8, 83 | parameter SEL_VICTIM_LINE = 3, // VICTIM LINE is one of the DQ pins is selected to be different than hammer pattern 84 | 85 | parameter MEM_COL_WIDTH = 10, 86 | parameter EYE_TEST = "FALSE" 87 | 88 | ) 89 | ( 90 | 91 | input clk_i, 92 | input [9:0] rst_i, 93 | output cmd_rdy_o, 94 | input cmd_valid_i, 95 | input cmd_validB_i, 96 | input cmd_validC_i, 97 | input [31:0] prbs_fseed_i, 98 | input [3:0] data_mode_i, 99 | input mem_init_done_i, 100 | input wr_data_mask_gen_i, 101 | // input [31:0] m_addr_i, 102 | 103 | input [31:0] simple_data0 , 104 | input [31:0] simple_data1 , 105 | input [31:0] simple_data2 , 106 | input [31:0] simple_data3 , 107 | input [31:0] simple_data4 , 108 | input [31:0] simple_data5 , 109 | input [31:0] simple_data6 , 110 | input [31:0] simple_data7 , 111 | 112 | input [31:0] fixed_data_i, 113 | input mode_load_i, 114 | 115 | input [31:0] addr_i, 116 | input [BL_WIDTH-1:0] bl_i, 117 | 118 | // input [5:0] port_data_counts_i,// connect to data port fifo counts 119 | input memc_cmd_full_i, 120 | input data_rdy_i, 121 | output data_valid_o, 122 | output last_word_wr_o, 123 | output [NUM_DQ_PINS*nCK_PER_CLK*2-1:0] data_o, 124 | output [(NUM_DQ_PINS*nCK_PER_CLK*2/8) - 1:0] data_mask_o, 125 | output data_wr_end_o 126 | 127 | ); 128 | 129 | wire data_valid; 130 | reg cmd_rdy; 131 | 132 | assign data_valid_o = data_valid;// & data_rdy_i; 133 | 134 | 135 | mig_7series_v4_2_wr_data_gen # 136 | ( 137 | .TCQ (TCQ), 138 | .FAMILY (FAMILY), 139 | .MEM_TYPE (MEM_TYPE), 140 | .NUM_DQ_PINS (NUM_DQ_PINS), 141 | .MEM_BURST_LEN (MEM_BURST_LEN), 142 | .BL_WIDTH (BL_WIDTH), 143 | .START_ADDR (START_ADDR), 144 | .nCK_PER_CLK (nCK_PER_CLK), 145 | .SEL_VICTIM_LINE (SEL_VICTIM_LINE), 146 | .DATA_PATTERN (DATA_PATTERN), 147 | .DWIDTH (DWIDTH), 148 | .COLUMN_WIDTH (MEM_COL_WIDTH), 149 | .EYE_TEST (EYE_TEST) 150 | 151 | ) 152 | wr_data_gen( 153 | .clk_i (clk_i ), 154 | .rst_i (rst_i[9:5]), 155 | .prbs_fseed_i (prbs_fseed_i), 156 | .wr_data_mask_gen_i (wr_data_mask_gen_i), 157 | .mem_init_done_i (mem_init_done_i), 158 | .data_mode_i (data_mode_i ), 159 | .cmd_rdy_o (cmd_rdy_o ), 160 | .cmd_valid_i (cmd_valid_i ), 161 | .cmd_validB_i (cmd_validB_i ), 162 | .cmd_validC_i (cmd_validC_i ), 163 | 164 | .last_word_o (last_word_wr_o ), 165 | // .port_data_counts_i (port_data_counts_i), 166 | // .m_addr_i (m_addr_i ), 167 | .fixed_data_i (fixed_data_i), 168 | .simple_data0 (simple_data0), 169 | .simple_data1 (simple_data1), 170 | .simple_data2 (simple_data2), 171 | .simple_data3 (simple_data3), 172 | .simple_data4 (simple_data4), 173 | .simple_data5 (simple_data5), 174 | .simple_data6 (simple_data6), 175 | .simple_data7 (simple_data7), 176 | 177 | 178 | .mode_load_i (mode_load_i), 179 | 180 | .addr_i (addr_i ), 181 | .bl_i (bl_i ), 182 | .memc_cmd_full_i (memc_cmd_full_i), 183 | 184 | .data_rdy_i (data_rdy_i ), 185 | .data_valid_o ( data_valid ), 186 | .data_o (data_o ), 187 | .data_wr_end_o (data_wr_end_o), 188 | .data_mask_o (data_mask_o) 189 | ); 190 | 191 | 192 | 193 | endmodule 194 | -------------------------------------------------------------------------------- /mig_example.srcs/sources_1/ip/mig/mig_a.prj: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | mig 5 | 6 | 1 7 | 8 | 1 9 | 10 | OFF 11 | 12 | 1024 13 | 14 | ON 15 | 16 | Enabled 17 | 18 | xc7a100t-csg324/-1 19 | 20 | 4.2 21 | 22 | No Buffer 23 | 24 | Use System Clock 25 | 26 | ACTIVE LOW 27 | 28 | FALSE 29 | 30 | 1 31 | 32 | 50 Ohms 33 | 34 | 0 35 | 36 | 37 | DDR2_SDRAM/Components/MT47H64M16HR-25E 38 | 3333 39 | 1.8V 40 | 2:1 41 | 200.02 42 | 0 43 | 1200 44 | 1.000 45 | 1 46 | 1 47 | 1 48 | 1 49 | 16 50 | 1 51 | 1 52 | Disabled 53 | Strict 54 | 4 55 | FALSE 56 | 57 | 13 58 | 10 59 | 3 60 | BANK_ROW_COLUMN 61 | 62 | 63 | 64 | 65 | 66 | 67 | 68 | 69 | 70 | 71 | 72 | 73 | 74 | 75 | 76 | 77 | 78 | 79 | 80 | 81 | 82 | 83 | 84 | 85 | 86 | 87 | 88 | 89 | 90 | 91 | 92 | 93 | 94 | 95 | 96 | 97 | 98 | 99 | 100 | 101 | 102 | 103 | 104 | 105 | 106 | 107 | 108 | 109 | 110 | 111 | 112 | 113 | 114 | 115 | 116 | 117 | 8 118 | Sequential 119 | 5 120 | Normal 121 | No 122 | Fast exit 123 | 5 124 | Enable-Normal 125 | Fullstrength 126 | Enable 127 | 1 128 | 50ohms 129 | 0 130 | OCD Exit 131 | Enable 132 | Disable 133 | Enable 134 | NATIVE 135 | 136 | 137 | 138 | -------------------------------------------------------------------------------- /mig_example.srcs/sources_1/ip/mig/mig/mig.prj: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | mig 5 | 6 | 1 7 | 8 | 1 9 | 10 | OFF 11 | 12 | 1024 13 | 14 | ON 15 | 16 | Enabled 17 | 18 | xc7a100t-csg324/-1 19 | 20 | 4.2 21 | 22 | No Buffer 23 | 24 | Use System Clock 25 | 26 | ACTIVE LOW 27 | 28 | FALSE 29 | 30 | 1 31 | 32 | 50 Ohms 33 | 34 | 0 35 | 36 | 37 | DDR2_SDRAM/Components/MT47H64M16HR-25E 38 | 3333 39 | 1.8V 40 | 2:1 41 | 200.02 42 | 0 43 | 1200 44 | 1.000 45 | 1 46 | 1 47 | 1 48 | 1 49 | 16 50 | 1 51 | 1 52 | Disabled 53 | Strict 54 | 4 55 | FALSE 56 | 57 | 13 58 | 10 59 | 3 60 | BANK_ROW_COLUMN 61 | 62 | 63 | 64 | 65 | 66 | 67 | 68 | 69 | 70 | 71 | 72 | 73 | 74 | 75 | 76 | 77 | 78 | 79 | 80 | 81 | 82 | 83 | 84 | 85 | 86 | 87 | 88 | 89 | 90 | 91 | 92 | 93 | 94 | 95 | 96 | 97 | 98 | 99 | 100 | 101 | 102 | 103 | 104 | 105 | 106 | 107 | 108 | 109 | 110 | 111 | 112 | 113 | 114 | 115 | 116 | 117 | 8 118 | Sequential 119 | 5 120 | Normal 121 | No 122 | Fast exit 123 | 5 124 | Enable-Normal 125 | Fullstrength 126 | Enable 127 | 1 128 | 50ohms 129 | 0 130 | OCD Exit 131 | Enable 132 | Disable 133 | Enable 134 | NATIVE 135 | 136 | 137 | 138 | -------------------------------------------------------------------------------- /mig_example.srcs/sources_1/ip/mig/mig/example_design/rtl/traffic_gen/mig_7series_v4_2_read_posted_fifo.v: -------------------------------------------------------------------------------- 1 | //***************************************************************************** 2 | // (c) Copyright 2008-2010 Xilinx, Inc. All rights reserved. 3 | // 4 | // This file contains confidential and proprietary information 5 | // of Xilinx, Inc. and is protected under U.S. and 6 | // international copyright and other intellectual property 7 | // laws. 8 | // 9 | // DISCLAIMER 10 | // This disclaimer is not a license and does not grant any 11 | // rights to the materials distributed herewith. Except as 12 | // otherwise provided in a valid license issued to you by 13 | // Xilinx, and to the maximum extent permitted by applicable 14 | // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 15 | // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 16 | // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 17 | // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 18 | // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 19 | // (2) Xilinx shall not be liable (whether in contract or tort, 20 | // including negligence, or under any other theory of 21 | // liability) for any loss or damage of any kind or nature 22 | // related to, arising under or in connection with these 23 | // materials, including for any direct, or any indirect, 24 | // special, incidental, or consequential loss or damage 25 | // (including loss of data, profits, goodwill, or any type of 26 | // loss or damage suffered as a result of any action brought 27 | // by a third party) even if such damage or loss was 28 | // reasonably foreseeable or Xilinx had been advised of the 29 | // possibility of the same. 30 | // 31 | // CRITICAL APPLICATIONS 32 | // Xilinx products are not designed or intended to be fail- 33 | // safe, or for use in any application requiring fail-safe 34 | // performance, such as life-support or safety devices or 35 | // systems, Class III medical devices, nuclear facilities, 36 | // applications related to the deployment of airbags, or any 37 | // other applications that could lead to death, personal 38 | // injury, or severe property or environmental damage 39 | // (individually and collectively, "Critical 40 | // Applications"). Customer assumes the sole risk and 41 | // liability of any use of Xilinx products in Critical 42 | // Applications, subject only to applicable laws and 43 | // regulations governing limitations on product liability. 44 | // 45 | // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 46 | // PART OF THIS FILE AT ALL TIMES. 47 | // 48 | //***************************************************************************** 49 | // ____ ____ 50 | // / /\/ / 51 | // /___/ \ / Vendor: Xilinx 52 | // \ \ \/ Version: %version 53 | // \ \ Application: MIG 54 | // / / Filename: read_posted_fifo.v 55 | // /___/ /\ Date Last Modified: 56 | // \ \ / \ Date Created: 57 | // \___\/\___\ 58 | // 59 | //Device: Spartan6 60 | //Design Name: DDR/DDR2/DDR3/LPDDR 61 | //Purpose: This module instantiated by read_data_path module and sits between 62 | // mcb_flow_control module and read_data_gen module to buffer up the 63 | // commands that has sent to memory controller. 64 | //Reference: 65 | //Revision History: 3/14/2012 Adding support for "nCK_PER_CLK == 2" abd MEM_BURST_LEN == 2 " 66 | //***************************************************************************** 67 | `timescale 1ps/1ps 68 | 69 | module mig_7series_v4_2_read_posted_fifo # 70 | ( 71 | parameter TCQ = 100, 72 | parameter FAMILY = "SPARTAN6", 73 | parameter nCK_PER_CLK = 4, 74 | parameter MEM_BURST_LEN = 4, 75 | 76 | parameter ADDR_WIDTH = 32, 77 | parameter BL_WIDTH = 6 78 | ) 79 | ( 80 | input clk_i, 81 | input rst_i, 82 | output reg cmd_rdy_o, 83 | input memc_cmd_full_i, 84 | input cmd_valid_i, 85 | input data_valid_i, 86 | input cmd_start_i, 87 | input [ADDR_WIDTH-1:0] addr_i, 88 | input [BL_WIDTH-1:0] bl_i, 89 | input [2:0] cmd_sent, 90 | input [5:0] bl_sent , 91 | input cmd_en_i , 92 | 93 | 94 | output gen_valid_o, 95 | output [ADDR_WIDTH-1:0] gen_addr_o, 96 | output [BL_WIDTH-1:0] gen_bl_o, 97 | output rd_mdata_en 98 | 99 | ); 100 | 101 | //reg empty_r; 102 | reg rd_en_r; 103 | wire full; 104 | wire empty; 105 | wire wr_en; 106 | reg mcb_rd_fifo_port_almost_full; 107 | reg [6:0] buf_avail_r; 108 | reg [6:0] rd_data_received_counts; 109 | reg [6:0] rd_data_counts_asked; 110 | 111 | reg dfifo_has_enough_room; 112 | reg [1:0] wait_cnt; 113 | reg wait_done; 114 | 115 | assign rd_mdata_en = rd_en_r; 116 | 117 | generate 118 | if (FAMILY == "SPARTAN6") 119 | begin: gen_sp6_cmd_rdy 120 | 121 | always @ (posedge clk_i) 122 | cmd_rdy_o <= #TCQ !full & dfifo_has_enough_room ;//& wait_done; 123 | end 124 | 125 | // if ((FAMILY == "VIRTEX7") || (FAMILY == "7SERIES") || (FAMILY == "KINTEX7") || (FAMILY == "ARTIX7") || 126 | // (FAMILY == "VIRTEX6") ) 127 | else 128 | begin: gen_v6_cmd_rdy 129 | 130 | always @ (posedge clk_i) 131 | cmd_rdy_o <= #TCQ !full & wait_done & dfifo_has_enough_room; 132 | end 133 | endgenerate 134 | 135 | always @ (posedge clk_i) 136 | begin 137 | if (rst_i) 138 | wait_cnt <= #TCQ 'b0; 139 | else if (cmd_rdy_o && cmd_valid_i) 140 | wait_cnt <= #TCQ 2'b10; 141 | else if (wait_cnt > 0) 142 | wait_cnt <= #TCQ wait_cnt - 1'b1; 143 | 144 | end 145 | 146 | always @(posedge clk_i) 147 | begin 148 | if (rst_i) 149 | wait_done <= #TCQ 1'b1; 150 | else if (cmd_rdy_o && cmd_valid_i) 151 | wait_done <= #TCQ 1'b0; 152 | else if (wait_cnt == 0) 153 | wait_done <= #TCQ 1'b1; 154 | else 155 | wait_done <= #TCQ 1'b0; 156 | 157 | end 158 | 159 | reg dfifo_has_enough_room_d1; 160 | always @ (posedge clk_i) 161 | begin 162 | dfifo_has_enough_room <= #TCQ (buf_avail_r >= 32 ) ? 1'b1: 1'b0; 163 | dfifo_has_enough_room_d1 <= #TCQ dfifo_has_enough_room ; 164 | end 165 | 166 | // remove the dfifo_has_enough_room term. Just need to push pressure to the front to stop 167 | // sending more read commands but still accepting it if there is one coming. 168 | assign wr_en = cmd_valid_i & !full & wait_done; 169 | 170 | 171 | 172 | always @ (posedge clk_i) 173 | begin 174 | if (rst_i) begin 175 | rd_data_counts_asked <= #TCQ 'b0; 176 | end 177 | else if (cmd_en_i && cmd_sent[0] == 1 && ~memc_cmd_full_i) begin 178 | if (FAMILY == "SPARTAN6") 179 | rd_data_counts_asked <= #TCQ rd_data_counts_asked + (bl_sent + 7'b0000001) ; 180 | else 181 | // if (nCK_PER_CLK == 2 ) 182 | // rd_data_counts_asked <= #TCQ rd_data_counts_asked + 2'b10 ; 183 | // else 184 | // rd_data_counts_asked <= #TCQ rd_data_counts_asked + 1'b1 ; 185 | 186 | if (nCK_PER_CLK == 4 || (nCK_PER_CLK == 2 && (MEM_BURST_LEN == 4 || MEM_BURST_LEN == 2 ) )) 187 | rd_data_counts_asked <= #TCQ rd_data_counts_asked + 1'b1 ; 188 | else if (nCK_PER_CLK == 2 && MEM_BURST_LEN == 8) 189 | rd_data_counts_asked <= #TCQ rd_data_counts_asked + 2'b10 ; 190 | 191 | 192 | 193 | end 194 | end 195 | 196 | always @ (posedge clk_i) 197 | begin 198 | if (rst_i) begin 199 | rd_data_received_counts <= #TCQ 'b0; 200 | end 201 | else if (data_valid_i) begin 202 | rd_data_received_counts <= #TCQ rd_data_received_counts + 1'b1; 203 | end 204 | end 205 | 206 | // calculate how many buf still available 207 | always @ (posedge clk_i) 208 | if (rd_data_received_counts[6] == rd_data_counts_asked[6]) 209 | buf_avail_r <= #TCQ (rd_data_received_counts[5:0] - rd_data_counts_asked[5:0] + 7'd64 ); 210 | 211 | else 212 | buf_avail_r <= #TCQ ( rd_data_received_counts[5:0] - rd_data_counts_asked[5:0] ); 213 | 214 | 215 | always @ (posedge clk_i) begin 216 | rd_en_r <= #TCQ cmd_start_i; 217 | end 218 | 219 | 220 | 221 | assign gen_valid_o = !empty; 222 | mig_7series_v4_2_afifo # 223 | ( 224 | .TCQ (TCQ), 225 | .DSIZE (BL_WIDTH+ADDR_WIDTH), 226 | .FIFO_DEPTH (16), 227 | .ASIZE (4), 228 | .SYNC (1) // set the SYNC to 1 because rd_clk = wr_clk to reduce latency 229 | 230 | 231 | ) 232 | rd_fifo 233 | ( 234 | .wr_clk (clk_i), 235 | .rst (rst_i), 236 | .wr_en (wr_en), 237 | .wr_data ({bl_i,addr_i}), 238 | .rd_en (rd_en_r), 239 | .rd_clk (clk_i), 240 | .rd_data ({gen_bl_o,gen_addr_o}), 241 | .full (full), 242 | .empty (empty), 243 | .almost_full () 244 | 245 | ); 246 | 247 | 248 | 249 | 250 | 251 | endmodule 252 | -------------------------------------------------------------------------------- /mig_example.srcs/sources_1/ip/mig/mig/example_design/sim/readme.txt: -------------------------------------------------------------------------------- 1 | ############################################################################### 2 | ## (c) Copyright 2009 - 2012 Xilinx, Inc. All rights reserved. 3 | ## 4 | ## This file contains confidential and proprietary information 5 | ## of Xilinx, Inc. and is protected under U.S. and 6 | ## international copyright and other intellectual property 7 | ## laws. 8 | ## 9 | ## DISCLAIMER 10 | ## This disclaimer is not a license and does not grant any 11 | ## rights to the materials distributed herewith. Except as 12 | ## otherwise provided in a valid license issued to you by 13 | ## Xilinx, and to the maximum extent permitted by applicable 14 | ## law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 15 | ## WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 16 | ## AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 17 | ## BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 18 | ## INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 19 | ## (2) Xilinx shall not be liable (whether in contract or tort, 20 | ## including negligence, or under any other theory of 21 | ## liability) for any loss or damage of any kind or nature 22 | ## related to, arising under or in connection with these 23 | ## materials, including for any direct, or any indirect, 24 | ## special, incidental, or consequential loss or damage 25 | ## (including loss of data, profits, goodwill, or any type of 26 | ## loss or damage suffered as a result of any action brought 27 | ## by a third party) even if such damage or loss was 28 | ## reasonably foreseeable or Xilinx had been advised of the 29 | ## possibility of the same. 30 | ## 31 | ## CRITICAL APPLICATIONS 32 | ## Xilinx products are not designed or intended to be fail- 33 | ## safe, or for use in any application requiring fail-safe 34 | ## performance, such as life-support or safety devices or 35 | ## systems, Class III medical devices, nuclear facilities, 36 | ## applications related to the deployment of airbags, or any 37 | ## other applications that could lead to death, personal 38 | ## injury, or severe property or environmental damage 39 | ## (individually and collectively, "Critical 40 | ## Applications"). Customer assumes the sole risk and 41 | ## liability of any use of Xilinx products in Critical 42 | ## Applications, subject only to applicable laws and 43 | ## regulations governing limitations on product liability. 44 | ## 45 | ## THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 46 | ## PART OF THIS FILE AT ALL TIMES. 47 | ## 48 | ############################################################################### 49 | ## ____ ____ 50 | ## / /\/ / 51 | ## /___/ \ / Vendor : Xilinx 52 | ## \ \ \/ Version : 4.2 53 | ## \ \ Application : MIG 54 | ## / / Filename : readme.txt 55 | ## /___/ /\ Date Last Modified : $Date: 2011/06/02 08:31:16 $ 56 | ## \ \ / \ Date Created : Fri Oct 14 2011 57 | ## \___\/\___\ 58 | ## 59 | ## Device : 7 Series 60 | ## Design Name : DDR2 SDRAM 61 | ## Purpose : Steps to run simulations using Modelsim/QuestaSim, 62 | ## Cadence IES, and Synopsys VCS 63 | ## Assumptions : Simulations are run in \sim folder of MIG output "Open IP 64 | ## Example Design" directory 65 | ## Reference : 66 | ## Revision History: 67 | ############################################################################### 68 | 69 | MIG outputs script files required to run the simulations for Modelsim/QuestaSim, 70 | Vivado Simulator, IES and VCS. These scripts are valid only for running 71 | simulations for "Open IP Example Design" 72 | 73 | 1. How to run simulations in Modelsim/QuestaSim simulator 74 | 75 | A) sim.do File : 76 | 77 | a) The 'sim.do' file has commands to compile and simulate memory 78 | interface design and run the simulation for specified period of time. 79 | 80 | b) It has the syntax to Map the required libraries (unisims_ver, 81 | unisim and secureip). The libraries should be mapped using 82 | the following command 83 | vmap unisims_ver 84 | vmap unisim 85 | vmap secureip 86 | 87 | Also, $XILINX_VIVADO environment variable must be set in order to compile glbl.v file 88 | 89 | c) Displays the waveforms that are listed with "add wave" command. 90 | 91 | B) Steps to run the Modelsim/QuestaSim simulation: 92 | 93 | a) The user should invoke the Modelsim/QuestaSim simulator GUI. 94 | 95 | b) Change the present working directory path to the sim folder. 96 | In Transcript window, at Modelsim/QuestaSim prompt, type the following 97 | command to change directory path. 98 | cd 99 | 100 | c) Run the simulation using sim.do file. 101 | At Modelsim/QuestaSim prompt, type the following command: 102 | do sim.do 103 | 104 | d) To exit simulation, type the following command at Modelsim/QuestaSim 105 | prompt: 106 | quit -f 107 | 108 | e) Verify the transcript file for the memory transactions. 109 | 110 | 2. How to run simulations in Vivado simulator 111 | 112 | A) Following files are provided : 113 | 114 | a) The 'xsim_run.bat' is the executable file for Vivado simulator under 115 | MicroSoft Windows environment. 116 | 117 | b) The 'xsim_run.sh' is the executable file for Vivado simulator under 118 | Linux environment. 119 | 120 | c) The 'xsim_run.bat'/'xsim_run.sh' file has commands to compile and 121 | simulate memory interface design and run the simulation for specified 122 | period of time. 123 | 124 | d) xsim_options.tcl file has commands to add waveforms and simulation 125 | period. 126 | 127 | e) xsim_files.prj file has list of rtl files for simulating the design. 128 | 129 | f) $XILINX_VIVADO environment variable must be set in order to compile 130 | glbl.v file 131 | 132 | B) Steps to run the Vivado Simulator simulation: 133 | 134 | a) Change the present working directory path to the sim folder of "Open 135 | IP Example Design" path in the OS terminal. 136 | 137 | b) Run the simulation using xsim_run.sh file under Linux environment and 138 | xsim_run.bat under MicroSoft Windows environment. 139 | 140 | c) Verify the transcript file for the memory transactions. 141 | 142 | 3. How to run Cadence IES Simulations 143 | 144 | A) ies_run.sh File : 145 | 146 | a) The "ies_run.sh" file contains the commands for simulation of the 147 | hdl files. 148 | 149 | b) Libraries must be mapped before running simulations. Following 150 | procedure must be followed to before running simulations 151 | 152 | 1. Create two files named cds.lib and hdl.var in this directory 153 | 2. Create a directory 'worklib' in same directory. 154 | mkdir worklib 155 | 3. Add following lines in the cds.lib file to map Xilinx libraries 156 | 157 | DEFINE unisim /proj/xbuilds/2014.4_daily_latest/clibs/ius/13.20.005/lin64/lib/./unisim 158 | DEFINE unisims_ver /proj/xbuilds/2014.4_daily_latest/clibs/ius/13.20.005/lin64/lib/./unisims_ver 159 | DEFINE secureip /proj/xbuilds/2014.4_daily_latest/clibs/ius/13.20.005/lin64/lib/./secureip 160 | DEFINE worklib ./worklib 161 | 162 | 4. ATTENTION: In above lines replace the path for libraries as per your 163 | compiled Xilinx libraries directory 164 | 5. ATTENTION: Add the lines in the same order given above 165 | 6. Please make sure you need to map all Xilinx libraries mentioned above 166 | 7. Save and close the cds.lib file 167 | 168 | Also, $XILINX_VIVADO environment variable must be set in order to 169 | compile glbl.v file and the above mentioned library files 170 | 171 | B) Steps to run the IES simulation: 172 | 173 | a) Change the present working directory path to the sim folder of "Open 174 | IP Example Design" path in the OS terminal. 175 | 176 | b) Run the simulation using ies_run.sh file. Type the following command: 177 | ./ies_run.sh 178 | 179 | c) Verify the ies_sim.log file for the memory transactions. 180 | 181 | 4. How to run Synopsys VCS Simulations 182 | 183 | A) vcs_run.sh File : 184 | 185 | a) The "vcs_run.sh" file contains the commands for simulation of hdl files. 186 | 187 | b) Libraries must be mapped before running simulations. Following 188 | procedure must be followed to before running simulations 189 | 190 | 1. Create a file named synopsys_sim.setup in this directory 191 | 2. Add following lines in the synopsys_sim.setup file to map Xilinx 192 | libraries 193 | 194 | unisim : /proj/xbuilds/2014.4_daily_latest/clibs/vcs/I-2014.03/lin64/lib/unisim 195 | secureip : /proj/xbuilds/2014.4_daily_latest/clibs/vcs/I-2014.03/lin64/lib/secureip 196 | unisims_ver : /proj/xbuilds/2014.4_daily_latest/clibs/vcs/I-2014.03/lin64/lib/unisims_ver 197 | 198 | 3. ATTENTION: In above lines replace the path for libraries as per your 199 | Compiled Xilinx libraries directory 200 | 4. Please make sure you need to map all Xilinx libraries mentioned above 201 | 202 | Also, $XILINX_VIVADO environment variable must be set in order to 203 | compile glbl.v file and the above mentioned library files 204 | 205 | B) Steps to run the VCS simulation: 206 | 207 | a) Change the present working directory path to the sim folder of "Open 208 | IP Example Design" path in the OS terminal. 209 | 210 | b) Run the simulation using vcs_run.sh file. Type the following command: 211 | ./vcs_run.sh 212 | 213 | c) Verify the vcs_sim.log file for the memory transactions. 214 | 215 | 5. SIM_BYPASS_INIT_CAL parameter value of SKIP, skips memory initialization sequence 216 | and calibration sequence. This could lead to simulation errors since design is not 217 | calibrated at all. Preferred values for parameter SIM_BYPASS_INIT_CAL to run 218 | simulations are FAST and OFF. 219 | 220 | 221 | -------------------------------------------------------------------------------- /mig_example.srcs/sources_1/ip/mig/mig/example_design/sim/xsim_files.prj: -------------------------------------------------------------------------------- 1 | ------------------------------------------------------------------------------- 2 | -- (c) Copyright 2012 Xilinx, Inc. All rights reserved. 3 | -- 4 | -- This file contains confidential and proprietary information 5 | -- of Xilinx, Inc. and is protected under U.S. and 6 | -- international copyright and other intellectual property 7 | -- laws. 8 | -- 9 | -- DISCLAIMER 10 | -- This disclaimer is not a license and does not grant any 11 | -- rights to the materials distributed herewith. Except as 12 | -- otherwise provided in a valid license issued to you by 13 | -- Xilinx, and to the maximum extent permitted by applicable 14 | -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 15 | -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 16 | -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 17 | -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 18 | -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 19 | -- (2) Xilinx shall not be liable (whether in contract or tort, 20 | -- including negligence, or under any other theory of 21 | -- liability) for any loss or damage of any kind or nature 22 | -- related to, arising under or in connection with these 23 | -- materials, including for any direct, or any indirect, 24 | -- special, incidental, or consequential loss or damage 25 | -- (including loss of data, profits, goodwill, or any type of 26 | -- loss or damage suffered as a result of any action brought 27 | -- by a third party) even if such damage or loss was 28 | -- reasonably foreseeable or Xilinx had been advised of the 29 | -- possibility of the same. 30 | -- 31 | -- CRITICAL APPLICATIONS 32 | -- Xilinx products are not designed or intended to be fail- 33 | -- safe, or for use in any application requiring fail-safe 34 | -- performance, such as life-support or safety devices or 35 | -- systems, Class III medical devices, nuclear facilities, 36 | -- applications related to the deployment of airbags, or any 37 | -- other applications that could lead to death, personal 38 | -- injury, or severe property or environmental damage 39 | -- (individually and collectively, "Critical 40 | -- Applications"). Customer assumes the sole risk and 41 | -- liability of any use of Xilinx products in Critical 42 | -- Applications, subject only to applicable laws and 43 | -- regulations governing limitations on product liability. 44 | -- 45 | -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 46 | -- PART OF THIS FILE AT ALL TIMES. 47 | -- 48 | ------------------------------------------------------------------------------- 49 | -- ____ ____ 50 | -- / /\/ / 51 | -- /___/ \ / Vendor : Xilinx 52 | -- \ \ \/ Version : 4.2 53 | -- \ \ Application : MIG 54 | -- / / Filename : xsim_files.prj 55 | -- /___/ /\ Date Last Modified : $Date: 2011/06/02 08:31:16 $ 56 | -- \ \ / \ Date Created : Tue Jun 05 2012 57 | -- \___\/\___\ 58 | -- 59 | -- Device : 7 Series 60 | -- Design Name : DDR2 SDRAM 61 | -- Purpose : Contains a list of all the files associated with a design 62 | -- Assumptions: 63 | -- - Simulation takes place in \sim folder of MIG output directory 64 | -- Reference : 65 | -- Revision History: 66 | ------------------------------------------------------------------------------- 67 | 68 | verilog work mig_7series_v4_2_afifo.v 69 | verilog work mig_7series_v4_2_cmd_gen.v 70 | verilog work mig_7series_v4_2_cmd_prbs_gen.v 71 | verilog work mig_7series_v4_2_data_prbs_gen.v 72 | verilog work mig_7series_v4_2_init_mem_pattern_ctr.v 73 | verilog work mig_7series_v4_2_memc_flow_vcontrol.v 74 | verilog work mig_7series_v4_2_memc_traffic_gen.v 75 | verilog work mig_7series_v4_2_rd_data_gen.v 76 | verilog work mig_7series_v4_2_read_data_path.v 77 | verilog work mig_7series_v4_2_read_posted_fifo.v 78 | verilog work mig_7series_v4_2_s7ven_data_gen.v 79 | verilog work mig_7series_v4_2_tg_prbs_gen.v 80 | verilog work mig_7series_v4_2_tg_status.v 81 | verilog work mig_7series_v4_2_traffic_gen_top.v 82 | verilog work mig_7series_v4_2_vio_init_pattern_bram.v 83 | verilog work mig_7series_v4_2_wr_data_gen.v 84 | verilog work mig_7series_v4_2_write_data_path.v 85 | verilog work example_top.v 86 | verilog work ../mig_ex.srcs/sources_1/ip/mig/mig/user_design/rtl/clocking/mig_7series_v4_2_clk_ibuf.v 87 | verilog work ../mig_ex.srcs/sources_1/ip/mig/mig/user_design/rtl/clocking/mig_7series_v4_2_infrastructure.v 88 | verilog work ../mig_ex.srcs/sources_1/ip/mig/mig/user_design/rtl/clocking/mig_7series_v4_2_iodelay_ctrl.v 89 | verilog work ../mig_ex.srcs/sources_1/ip/mig/mig/user_design/rtl/clocking/mig_7series_v4_2_tempmon.v 90 | verilog work ../mig_ex.srcs/sources_1/ip/mig/mig/user_design/rtl/controller/mig_7series_v4_2_arb_mux.v 91 | verilog work ../mig_ex.srcs/sources_1/ip/mig/mig/user_design/rtl/controller/mig_7series_v4_2_arb_row_col.v 92 | verilog work ../mig_ex.srcs/sources_1/ip/mig/mig/user_design/rtl/controller/mig_7series_v4_2_arb_select.v 93 | verilog work ../mig_ex.srcs/sources_1/ip/mig/mig/user_design/rtl/controller/mig_7series_v4_2_bank_cntrl.v 94 | verilog work ../mig_ex.srcs/sources_1/ip/mig/mig/user_design/rtl/controller/mig_7series_v4_2_bank_common.v 95 | verilog work ../mig_ex.srcs/sources_1/ip/mig/mig/user_design/rtl/controller/mig_7series_v4_2_bank_compare.v 96 | verilog work ../mig_ex.srcs/sources_1/ip/mig/mig/user_design/rtl/controller/mig_7series_v4_2_bank_mach.v 97 | verilog work ../mig_ex.srcs/sources_1/ip/mig/mig/user_design/rtl/controller/mig_7series_v4_2_bank_queue.v 98 | verilog work ../mig_ex.srcs/sources_1/ip/mig/mig/user_design/rtl/controller/mig_7series_v4_2_bank_state.v 99 | verilog work ../mig_ex.srcs/sources_1/ip/mig/mig/user_design/rtl/controller/mig_7series_v4_2_col_mach.v 100 | verilog work ../mig_ex.srcs/sources_1/ip/mig/mig/user_design/rtl/controller/mig_7series_v4_2_mc.v 101 | verilog work ../mig_ex.srcs/sources_1/ip/mig/mig/user_design/rtl/controller/mig_7series_v4_2_rank_cntrl.v 102 | verilog work ../mig_ex.srcs/sources_1/ip/mig/mig/user_design/rtl/controller/mig_7series_v4_2_rank_common.v 103 | verilog work ../mig_ex.srcs/sources_1/ip/mig/mig/user_design/rtl/controller/mig_7series_v4_2_rank_mach.v 104 | verilog work ../mig_ex.srcs/sources_1/ip/mig/mig/user_design/rtl/controller/mig_7series_v4_2_round_robin_arb.v 105 | verilog work ../mig_ex.srcs/sources_1/ip/mig/mig/user_design/rtl/ecc/mig_7series_v4_2_ecc_buf.v 106 | verilog work ../mig_ex.srcs/sources_1/ip/mig/mig/user_design/rtl/ecc/mig_7series_v4_2_ecc_dec_fix.v 107 | verilog work ../mig_ex.srcs/sources_1/ip/mig/mig/user_design/rtl/ecc/mig_7series_v4_2_ecc_gen.v 108 | verilog work ../mig_ex.srcs/sources_1/ip/mig/mig/user_design/rtl/ecc/mig_7series_v4_2_ecc_merge_enc.v 109 | verilog work ../mig_ex.srcs/sources_1/ip/mig/mig/user_design/rtl/ecc/mig_7series_v4_2_fi_xor.v 110 | verilog work ../mig_ex.srcs/sources_1/ip/mig/mig/user_design/rtl/ip_top/mig_7series_v4_2_mem_intfc.v 111 | verilog work ../mig_ex.srcs/sources_1/ip/mig/mig/user_design/rtl/ip_top/mig_7series_v4_2_memc_ui_top_std.v 112 | verilog work ../mig_ex.srcs/sources_1/ip/mig/mig/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v 113 | verilog work ../mig_ex.srcs/sources_1/ip/mig/mig/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v 114 | verilog work ../mig_ex.srcs/sources_1/ip/mig/mig/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_tempmon.v 115 | verilog work ../mig_ex.srcs/sources_1/ip/mig/mig/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v 116 | verilog work ../mig_ex.srcs/sources_1/ip/mig/mig/user_design/rtl/phy/mig_7series_v4_2_ddr_if_post_fifo.v 117 | verilog work ../mig_ex.srcs/sources_1/ip/mig/mig/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy.v 118 | verilog work ../mig_ex.srcs/sources_1/ip/mig/mig/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v 119 | verilog work ../mig_ex.srcs/sources_1/ip/mig/mig/user_design/rtl/phy/mig_7series_v4_2_ddr_of_pre_fifo.v 120 | verilog work ../mig_ex.srcs/sources_1/ip/mig/mig/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_4lanes.v 121 | verilog work ../mig_ex.srcs/sources_1/ip/mig/mig/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v 122 | verilog work ../mig_ex.srcs/sources_1/ip/mig/mig/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_dqs_found_cal.v 123 | verilog work ../mig_ex.srcs/sources_1/ip/mig/mig/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_dqs_found_cal_hr.v 124 | verilog work ../mig_ex.srcs/sources_1/ip/mig/mig/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_oclkdelay_cal.v 125 | verilog work ../mig_ex.srcs/sources_1/ip/mig/mig/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_prbs_rdlvl.v 126 | verilog work ../mig_ex.srcs/sources_1/ip/mig/mig/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v 127 | verilog work ../mig_ex.srcs/sources_1/ip/mig/mig/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_top.v 128 | verilog work ../mig_ex.srcs/sources_1/ip/mig/mig/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrcal.v 129 | verilog work ../mig_ex.srcs/sources_1/ip/mig/mig/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrlvl_off_delay.v 130 | verilog work ../mig_ex.srcs/sources_1/ip/mig/mig/user_design/rtl/phy/mig_7series_v4_2_ddr_prbs_gen.v 131 | verilog work ../mig_ex.srcs/sources_1/ip/mig/mig/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ck_addr_cmd_delay.v 132 | verilog work ../mig_ex.srcs/sources_1/ip/mig/mig/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrlvl.v 133 | verilog work ../mig_ex.srcs/sources_1/ip/mig/mig/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ocd_lim.v 134 | verilog work ../mig_ex.srcs/sources_1/ip/mig/mig/user_design/rtl/phy/mig_7series_v4_2_poc_top.v 135 | verilog work ../mig_ex.srcs/sources_1/ip/mig/mig/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ocd_mux.v 136 | verilog work ../mig_ex.srcs/sources_1/ip/mig/mig/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ocd_data.v 137 | verilog work ../mig_ex.srcs/sources_1/ip/mig/mig/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ocd_samp.v 138 | verilog work ../mig_ex.srcs/sources_1/ip/mig/mig/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ocd_edge.v 139 | verilog work ../mig_ex.srcs/sources_1/ip/mig/mig/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ocd_cntlr.v 140 | verilog work ../mig_ex.srcs/sources_1/ip/mig/mig/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ocd_po_cntlr.v 141 | verilog work ../mig_ex.srcs/sources_1/ip/mig/mig/user_design/rtl/phy/mig_7series_v4_2_poc_pd.v 142 | verilog work ../mig_ex.srcs/sources_1/ip/mig/mig/user_design/rtl/phy/mig_7series_v4_2_poc_tap_base.v 143 | verilog work ../mig_ex.srcs/sources_1/ip/mig/mig/user_design/rtl/phy/mig_7series_v4_2_poc_meta.v 144 | verilog work ../mig_ex.srcs/sources_1/ip/mig/mig/user_design/rtl/phy/mig_7series_v4_2_poc_edge_store.v 145 | verilog work ../mig_ex.srcs/sources_1/ip/mig/mig/user_design/rtl/phy/mig_7series_v4_2_poc_cc.v 146 | verilog work ../mig_ex.srcs/sources_1/ip/mig/mig/user_design/rtl/ui/mig_7series_v4_2_ui_cmd.v 147 | verilog work ../mig_ex.srcs/sources_1/ip/mig/mig/user_design/rtl/ui/mig_7series_v4_2_ui_rd_data.v 148 | verilog work ../mig_ex.srcs/sources_1/ip/mig/mig/user_design/rtl/ui/mig_7series_v4_2_ui_top.v 149 | verilog work ../mig_ex.srcs/sources_1/ip/mig/mig/user_design/rtl/ui/mig_7series_v4_2_ui_wr_data.v 150 | verilog work ../mig_ex.srcs/sources_1/ip/mig/mig/user_design/rtl/mig_mig_sim.v 151 | verilog work ../mig_ex.srcs/sources_1/ip/mig/mig/user_design/rtl/mig.v 152 | verilog work ../mig_ex.srcs/sources_1/ip/mig/mig/user_design/rtl/mig_mig_sim.v 153 | verilog work ../mig_ex.srcs/sources_1/ip/mig/mig/user_design/rtl/mig.v 154 | verilog work $XILINX_VIVADO/data/verilog/src/glbl.v 155 | verilog work sim_tb_top.v 156 | verilog work wiredly.v 157 | verilog work ddr2_model.v -d x1Gb -d sg25E -d x16 158 | 159 | -------------------------------------------------------------------------------- /mig_example.srcs/sources_1/ip/mig/mig/example_design/rtl/traffic_gen/mig_7series_v4_2_cmd_prbs_gen.v: -------------------------------------------------------------------------------- 1 | //***************************************************************************** 2 | // (c) Copyright 2008-2010 Xilinx, Inc. All rights reserved. 3 | // 4 | // This file contains confidential and proprietary information 5 | // of Xilinx, Inc. and is protected under U.S. and 6 | // international copyright and other intellectual property 7 | // laws. 8 | // 9 | // DISCLAIMER 10 | // This disclaimer is not a license and does not grant any 11 | // rights to the materials distributed herewith. Except as 12 | // otherwise provided in a valid license issued to you by 13 | // Xilinx, and to the maximum extent permitted by applicable 14 | // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 15 | // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 16 | // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 17 | // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 18 | // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 19 | // (2) Xilinx shall not be liable (whether in contract or tort, 20 | // including negligence, or under any other theory of 21 | // liability) for any loss or damage of any kind or nature 22 | // related to, arising under or in connection with these 23 | // materials, including for any direct, or any indirect, 24 | // special, incidental, or consequential loss or damage 25 | // (including loss of data, profits, goodwill, or any type of 26 | // loss or damage suffered as a result of any action brought 27 | // by a third party) even if such damage or loss was 28 | // reasonably foreseeable or Xilinx had been advised of the 29 | // possibility of the same. 30 | // 31 | // CRITICAL APPLICATIONS 32 | // Xilinx products are not designed or intended to be fail- 33 | // safe, or for use in any application requiring fail-safe 34 | // performance, such as life-support or safety devices or 35 | // systems, Class III medical devices, nuclear facilities, 36 | // applications related to the deployment of airbags, or any 37 | // other applications that could lead to death, personal 38 | // injury, or severe property or environmental damage 39 | // (individually and collectively, "Critical 40 | // Applications"). Customer assumes the sole risk and 41 | // liability of any use of Xilinx products in Critical 42 | // Applications, subject only to applicable laws and 43 | // regulations governing limitations on product liability. 44 | // 45 | // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 46 | // PART OF THIS FILE AT ALL TIMES. 47 | // 48 | //***************************************************************************** 49 | // ____ ____ 50 | // / /\/ / 51 | // /___/ \ / Vendor: Xilinx 52 | // \ \ \/ Version: %version 53 | // \ \ Application: MIG 54 | // / / Filename: cmd_prbs_gen.v 55 | // /___/ /\ Date Last Modified: 56 | // \ \ / \ Date Created: 57 | // \___\/\___\ 58 | // 59 | //Device: Spartan6 60 | //Design Name: DDR/DDR2/DDR3/LPDDR 61 | //Purpose: This moduel use LFSR to generate random address, isntructions 62 | // or burst_length. 63 | //Reference: 64 | //Revision History: 1.1 7/9/2009 Added condition to zero out the LSB address bits according to 65 | // DWIDTH and FAMILY. 7/9/2009 66 | // 1.2 11/8/2010 Fixed the PRBS Address generation. 67 | //***************************************************************************** 68 | 69 | `timescale 1ps/1ps 70 | 71 | module mig_7series_v4_2_cmd_prbs_gen # 72 | ( 73 | parameter TCQ = 100, 74 | parameter FAMILY = "SPARTAN6", 75 | parameter MEM_BURST_LEN = 8, 76 | parameter ADDR_WIDTH = 29, 77 | parameter DWIDTH = 32, 78 | parameter PRBS_CMD = "ADDRESS", // "INSTR", "BLEN","ADDRESS" 79 | parameter PRBS_WIDTH = 64, // 64,15,20 80 | parameter SEED_WIDTH = 32, // 32,15,4 81 | 82 | parameter PRBS_EADDR_MASK_POS = 32'hFFFFD000, 83 | parameter PRBS_SADDR_MASK_POS = 32'h00002000, 84 | parameter PRBS_EADDR = 32'h00002000, 85 | parameter PRBS_SADDR = 32'h00002000 86 | ) 87 | ( 88 | input clk_i, 89 | input prbs_seed_init, // when high the prbs_x_seed will be loaded 90 | input clk_en, 91 | input [SEED_WIDTH-1:0] prbs_seed_i, 92 | 93 | output[SEED_WIDTH-1:0] prbs_o // generated address 94 | ); 95 | 96 | wire[ADDR_WIDTH - 1:0] ZEROS; 97 | reg [SEED_WIDTH - 1:0] prbs; 98 | reg [PRBS_WIDTH :1] lfsr_q; 99 | 100 | assign ZEROS = 'b0; 101 | 102 | 103 | function integer logb2; 104 | input integer number; 105 | integer i; 106 | begin 107 | i = number; 108 | for(logb2=1; i>0; logb2=logb2+1) 109 | i = i >> 1; 110 | end 111 | endfunction 112 | 113 | 114 | // 115 | //************************************************************** 116 | //#################################################################################################################### 117 | // # 118 | // # 119 | // 64 taps: [64,63,61,60]: {{8'b01011000}, {56'b0}} # 120 | // upper 32 bits are loadable # 121 | // # 122 | // 123 | // 124 | // ........................................................................................ 125 | // ^ ^ ^ ^ | 126 | // | ____ | ___ ___ | ___ | ___ ___ ___ | 127 | // | | | |---|<- | | | | |---|<- | | |---|<- | |...| | | | | The first 32 bits are parallel loadable. 128 | // ----|64 |<--|xor|<-- |63 |-->|62 |-|xor|<--|61 |<-|xor|<--|60 |...|33 |<--|1|<<-- 129 | // |___| --- |___| |___| --- |___| --- |___|...|___| |___| 130 | // 131 | // 132 | // <<-- shifting -- 133 | //##################################################################################################################### 134 | 135 | // use SRLC32E for lower 32 stages and 32 registers for upper 32 stages. 136 | // we need to provide 30 bits addres. SRLC32 has only one bit output. 137 | // address seed will be loaded to upper 32 bits. 138 | // 139 | // parallel load and serial shift out to LFSR during INIT time 140 | 141 | generate 142 | if(PRBS_CMD == "ADDRESS" && PRBS_WIDTH == 64) 143 | begin :gen64_taps 144 | always @ (posedge clk_i) begin 145 | if(prbs_seed_init) begin//reset it to a known good state to prevent it locks up 146 | lfsr_q <= #TCQ {31'b0,prbs_seed_i}; 147 | end else if(clk_en) begin 148 | lfsr_q[64] <= #TCQ lfsr_q[64] ^ lfsr_q[63]; 149 | lfsr_q[63] <= #TCQ lfsr_q[62]; 150 | lfsr_q[62] <= #TCQ lfsr_q[64] ^ lfsr_q[61]; 151 | lfsr_q[61] <= #TCQ lfsr_q[64] ^ lfsr_q[60]; 152 | lfsr_q[60:2] <= #TCQ lfsr_q[59:1]; 153 | lfsr_q[1] <= #TCQ lfsr_q[64]; 154 | end 155 | end 156 | 157 | always @(lfsr_q[32:1]) begin 158 | prbs = lfsr_q[32:1]; 159 | end 160 | end 161 | //endgenerate 162 | //generate 163 | else if(PRBS_CMD == "ADDRESS" && PRBS_WIDTH == 32) 164 | begin :gen32_taps 165 | always @ (posedge clk_i) begin 166 | if(prbs_seed_init) begin //reset it to a known good state to prevent it locks up 167 | lfsr_q <= #TCQ {prbs_seed_i}; 168 | end else if(clk_en) begin 169 | lfsr_q[32:9] <= #TCQ lfsr_q[31:8]; 170 | lfsr_q[8] <= #TCQ lfsr_q[32] ^ lfsr_q[7]; 171 | lfsr_q[7] <= #TCQ lfsr_q[32] ^ lfsr_q[6]; 172 | lfsr_q[6:4] <= #TCQ lfsr_q[5:3]; 173 | 174 | lfsr_q[3] <= #TCQ lfsr_q[32] ^ lfsr_q[2]; 175 | lfsr_q[2] <= #TCQ lfsr_q[1] ; 176 | lfsr_q[1] <= #TCQ lfsr_q[32]; 177 | end 178 | end 179 | 180 | integer i; 181 | always @(lfsr_q[32:1]) begin 182 | 183 | if (FAMILY == "SPARTAN6" ) begin // for 32 bits 184 | 185 | for(i = logb2(DWIDTH) + 1; i <= SEED_WIDTH - 1; i = i + 1) 186 | 187 | if(PRBS_SADDR_MASK_POS[i] == 1) 188 | prbs[i] = PRBS_SADDR[i] | lfsr_q[i+1]; 189 | else if(PRBS_EADDR_MASK_POS[i] == 1) 190 | prbs[i] = PRBS_EADDR[i] & lfsr_q[i+1]; 191 | else 192 | prbs[i] = lfsr_q[i+1]; 193 | 194 | prbs[logb2(DWIDTH ) :0] = {logb2(DWIDTH ) + 1{1'b0}}; 195 | 196 | end 197 | else begin 198 | for(i = logb2(MEM_BURST_LEN) - 2; i <= SEED_WIDTH - 1; i = i + 1) 199 | // for(i = 3; i <= SEED_WIDTH - 1; i = i + 1) 200 | 201 | // BL8: 0,8 202 | //BL4: incremnt by 4 203 | // for(i = 3; i <= SEED_WIDTH - 1; i = i + 1) 204 | 205 | if(PRBS_SADDR_MASK_POS[i] == 1) 206 | prbs[i] = PRBS_SADDR[i] | lfsr_q[i+1]; 207 | else if(PRBS_EADDR_MASK_POS[i] == 0) 208 | prbs[i] = PRBS_EADDR[i] & lfsr_q[i+1]; 209 | else 210 | prbs[i] = 1'b0;// lfsr_q[i+1]; 211 | // 3 1 212 | prbs[logb2(MEM_BURST_LEN)-3:0] = 'b0;//{logb2(MEM_BURST_LEN) -3{1'b0}}; 213 | // prbs[2:0] = {3{1'b0}}; 214 | 215 | 216 | end 217 | 218 | end 219 | end 220 | //endgenerate 221 | 222 | ////////////////////////////////////////////////////////////////////////// 223 | //#################################################################################################################### 224 | // # 225 | // # 226 | // 15 taps: [15,14]: # 227 | // # 228 | // # 229 | // 230 | // 231 | // ............................................................. 232 | // ^ ^ . ^ 233 | // | ____ | ___ ___ ___ ___ ___ | 234 | // | | | |---|<- | | | | | |...| | | | | 235 | // ----|15 |<--|xor|<-- |14 |<--|13 |<--|12 |...|2 |<--|1 |<<-- 236 | // |___| --- |___| |___| |___|...|___| |___| 237 | // 238 | // 239 | // <<-- shifting -- 240 | //##################################################################################################################### 241 | 242 | //generate 243 | // if(PRBS_CMD == "INSTR" | PRBS_CMD == "BLEN") 244 | else 245 | begin :gen20_taps 246 | always @(posedge clk_i) begin 247 | if(prbs_seed_init) begin//reset it to a known good state to prevent it locks up 248 | lfsr_q <= #TCQ {5'b0,prbs_seed_i[14:0]}; 249 | end else if(clk_en) begin 250 | lfsr_q[20] <= #TCQ lfsr_q[19]; 251 | lfsr_q[19] <= #TCQ lfsr_q[18]; 252 | 253 | lfsr_q[18] <= #TCQ lfsr_q[20] ^lfsr_q[17]; 254 | 255 | lfsr_q[17:2] <= #TCQ lfsr_q[16:1]; 256 | lfsr_q[1] <= #TCQ lfsr_q[20]; 257 | end 258 | end 259 | 260 | always @ (lfsr_q[SEED_WIDTH - 1:1], ZEROS) begin 261 | prbs = {ZEROS[SEED_WIDTH - 1:6],lfsr_q[6:1]}; 262 | end 263 | end 264 | endgenerate 265 | 266 | assign prbs_o = prbs; 267 | 268 | endmodule 269 | -------------------------------------------------------------------------------- /mig_example.srcs/sources_1/ip/mig/mig/example_design/rtl/traffic_gen/mig_7series_v4_2_tg_prbs_gen.v: -------------------------------------------------------------------------------- 1 | //***************************************************************************** 2 | // (c) Copyright 2008-2010 Xilinx, Inc. All rights reserved. 3 | // 4 | // This file contains confidential and proprietary information 5 | // of Xilinx, Inc. and is protected under U.S. and 6 | // international copyright and other intellectual property 7 | // laws. 8 | // 9 | // DISCLAIMER 10 | // This disclaimer is not a license and does not grant any 11 | // rights to the materials distributed herewith. Except as 12 | // otherwise provided in a valid license issued to you by 13 | // Xilinx, and to the maximum extent permitted by applicable 14 | // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 15 | // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 16 | // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 17 | // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 18 | // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 19 | // (2) Xilinx shall not be liable (whether in contract or tort, 20 | // including negligence, or under any other theory of 21 | // liability) for any loss or damage of any kind or nature 22 | // related to, arising under or in connection with these 23 | // materials, including for any direct, or any indirect, 24 | // special, incidental, or consequential loss or damage 25 | // (including loss of data, profits, goodwill, or any type of 26 | // loss or damage suffered as a result of any action brought 27 | // by a third party) even if such damage or loss was 28 | // reasonably foreseeable or Xilinx had been advised of the 29 | // possibility of the same. 30 | // 31 | // CRITICAL APPLICATIONS 32 | // Xilinx products are not designed or intended to be fail- 33 | // safe, or for use in any application requiring fail-safe 34 | // performance, such as life-support or safety devices or 35 | // systems, Class III medical devices, nuclear facilities, 36 | // applications related to the deployment of airbags, or any 37 | // other applications that could lead to death, personal 38 | // injury, or severe property or environmental damage 39 | // (individually and collectively, "Critical 40 | // Applications"). Customer assumes the sole risk and 41 | // liability of any use of Xilinx products in Critical 42 | // Applications, subject only to applicable laws and 43 | // regulations governing limitations on product liability. 44 | // 45 | // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 46 | // PART OF THIS FILE AT ALL TIMES. 47 | // 48 | //***************************************************************************** 49 | // ____ ____ 50 | // / /\/ / 51 | // /___/ \ / Vendor: Xilinx 52 | // \ \ \/ Version: %version 53 | // \ \ Application: MIG 54 | // / / Filename: tb_cmd_gen.v 55 | // /___/ /\ Date Last Modified: $Date: 2011/06/02 08:37:24 $ 56 | // \ \ / \ Date Created: Fri Sep 01 2006 57 | // \___\/\___\ 58 | // 59 | //Device: 7 Series 60 | //Design Name: PRBS_Generator 61 | //Purpose: 62 | // Overview: 63 | // Implements a "pseudo-PRBS" generator. Basically this is a standard 64 | // PRBS generator (using an linear feedback shift register) along with 65 | // logic to force the repetition of the sequence after 2^PRBS_WIDTH 66 | // samples (instead of 2^PRBS_WIDTH - 1). The LFSR is based on the design 67 | // from Table 1 of XAPP 210. Note that only 8- and 10-tap long LFSR chains 68 | // are supported in this code 69 | // Parameter Requirements: 70 | // 1. PRBS_WIDTH = 8 or 10 71 | // 2. PRBS_WIDTH >= 2*nCK_PER_CLK 72 | // Output notes: 73 | // The output of this module consists of 2*nCK_PER_CLK bits, these contain 74 | // the value of the LFSR output for the next 2*CK_PER_CLK bit times. Note 75 | // that prbs_o[0] contains the bit value for the "earliest" bit time. 76 | //Reference: 77 | //Revision History: 78 | //***************************************************************************** 79 | 80 | `timescale 1ps/1ps 81 | 82 | module mig_7series_v4_2_tg_prbs_gen # 83 | ( 84 | parameter TCQ = 100, // clk->out delay (sim only) 85 | parameter PRBS_WIDTH = 10, // LFSR shift register length 86 | parameter nCK_PER_CLK = 4 // output:internal clock freq ratio 87 | ) 88 | ( 89 | input clk_i, // input clock 90 | input clk_en_i, // clock enable 91 | input rst_i, // synchronous reset 92 | input [PRBS_WIDTH-1:0] prbs_seed_i, // initial LFSR seed 93 | output [2*nCK_PER_CLK-1:0] prbs_o, // generated address 94 | // ReSeedcounter used to indicate when pseudo-PRBS sequence has reached 95 | // the end of it's cycle. May not be needed, but for now included to 96 | // maintain compatibility with current TG code 97 | output [31:0] ReSeedcounter_o 98 | ); 99 | 100 | //*************************************************************************** 101 | 102 | function integer clogb2 (input integer size); 103 | begin 104 | size = size - 1; 105 | for (clogb2=1; size>1; clogb2=clogb2+1) 106 | size = size >> 1; 107 | end 108 | endfunction 109 | 110 | // Number of internal clock cycles before the PRBS sequence will repeat 111 | localparam PRBS_SEQ_LEN_CYCLES = (2**PRBS_WIDTH) / (2*nCK_PER_CLK); 112 | localparam PRBS_SEQ_LEN_CYCLES_BITS = clogb2(PRBS_SEQ_LEN_CYCLES); 113 | 114 | reg [PRBS_WIDTH-1:0] lfsr_reg_r; 115 | wire [PRBS_WIDTH-1:0] next_lfsr_reg; 116 | reg [PRBS_WIDTH-1:0] reseed_cnt_r; 117 | reg reseed_prbs_r; 118 | reg [PRBS_SEQ_LEN_CYCLES_BITS-1:0] sample_cnt_r; 119 | 120 | genvar i; 121 | 122 | //*************************************************************************** 123 | 124 | assign ReSeedcounter_o = {{(32-PRBS_WIDTH){1'b0}}, reseed_cnt_r}; 125 | always @ (posedge clk_i) 126 | if (rst_i) 127 | reseed_cnt_r <= 'b0; 128 | else if (clk_en_i) 129 | if (reseed_cnt_r == {PRBS_WIDTH {1'b1}}) 130 | reseed_cnt_r <= 'b0; 131 | else 132 | reseed_cnt_r <= reseed_cnt_r + 1; 133 | 134 | //*************************************************************************** 135 | 136 | // Generate PRBS reset signal to ensure that PRBS sequence repeats after 137 | // every 2**PRBS_WIDTH samples. Basically what happens is that we let the 138 | // LFSR run for an extra cycle after "truly PRBS" 2**PRBS_WIDTH - 1 139 | // samples have past. Once that extra cycle is finished, we reseed the LFSR 140 | always @(posedge clk_i) 141 | if (rst_i) begin 142 | sample_cnt_r <= #TCQ 'b0; 143 | reseed_prbs_r <= #TCQ 1'b0; 144 | end else if (clk_en_i) begin 145 | // The rollver count should always be [(power of 2) - 1] 146 | sample_cnt_r <= #TCQ sample_cnt_r + 1; 147 | // Assert PRBS reset signal so that it is simultaneously with the 148 | // last sample of the sequence 149 | if (sample_cnt_r == PRBS_SEQ_LEN_CYCLES - 2) 150 | reseed_prbs_r <= #TCQ 1'b1; 151 | else 152 | reseed_prbs_r <= #TCQ 1'b0; 153 | end 154 | 155 | // Load initial seed or update LFSR contents 156 | always @(posedge clk_i) 157 | if (rst_i) 158 | lfsr_reg_r <= #TCQ prbs_seed_i; 159 | else if (clk_en_i) 160 | if (reseed_prbs_r) 161 | lfsr_reg_r <= #TCQ prbs_seed_i; 162 | else begin 163 | lfsr_reg_r <= #TCQ next_lfsr_reg; 164 | end 165 | 166 | // Calculate next set of nCK_PER_CLK samplse for LFSR 167 | // Basically we calculate all PRBS_WIDTH samples in parallel, rather 168 | // than serially shifting the LFSR to determine future sample values. 169 | // Shifting is possible, but requires multiple shift registers to be 170 | // instantiated because the fabric clock frequency is running at a 171 | // fraction of the output clock frequency 172 | generate 173 | if (PRBS_WIDTH == 8) begin: gen_next_lfsr_prbs8 174 | if (nCK_PER_CLK == 2) begin: gen_ck_per_clk2 175 | assign next_lfsr_reg[7] = lfsr_reg_r[3]; 176 | assign next_lfsr_reg[6] = lfsr_reg_r[2]; 177 | assign next_lfsr_reg[5] = lfsr_reg_r[1]; 178 | assign next_lfsr_reg[4] = lfsr_reg_r[0]; 179 | assign next_lfsr_reg[3] = ~(lfsr_reg_r[7] ^ lfsr_reg_r[5] ^ 180 | lfsr_reg_r[4] ^ lfsr_reg_r[3]); 181 | assign next_lfsr_reg[2] = ~(lfsr_reg_r[6] ^ lfsr_reg_r[4] ^ 182 | lfsr_reg_r[3] ^ lfsr_reg_r[2]); 183 | assign next_lfsr_reg[1] = ~(lfsr_reg_r[5] ^ lfsr_reg_r[3] ^ 184 | lfsr_reg_r[2] ^ lfsr_reg_r[1]); 185 | assign next_lfsr_reg[0] = ~(lfsr_reg_r[4] ^ lfsr_reg_r[2] ^ 186 | lfsr_reg_r[1] ^ lfsr_reg_r[0]); 187 | end else if (nCK_PER_CLK == 4) begin: gen_ck_per_clk4 188 | assign next_lfsr_reg[7] = ~(lfsr_reg_r[7] ^ lfsr_reg_r[5] ^ 189 | lfsr_reg_r[4] ^ lfsr_reg_r[3]); 190 | assign next_lfsr_reg[6] = ~(lfsr_reg_r[6] ^ lfsr_reg_r[4] ^ 191 | lfsr_reg_r[3] ^ lfsr_reg_r[2]) ; 192 | assign next_lfsr_reg[5] = ~(lfsr_reg_r[5] ^ lfsr_reg_r[3] ^ 193 | lfsr_reg_r[2] ^ lfsr_reg_r[1]); 194 | assign next_lfsr_reg[4] = ~(lfsr_reg_r[4] ^ lfsr_reg_r[2] ^ 195 | lfsr_reg_r[1] ^ lfsr_reg_r[0]); 196 | assign next_lfsr_reg[3] = ~(lfsr_reg_r[3] ^ lfsr_reg_r[1] ^ 197 | lfsr_reg_r[0] ^ next_lfsr_reg[7]); 198 | assign next_lfsr_reg[2] = ~(lfsr_reg_r[2] ^ lfsr_reg_r[0] ^ 199 | next_lfsr_reg[7] ^ next_lfsr_reg[6]); 200 | assign next_lfsr_reg[1] = ~(lfsr_reg_r[1] ^ next_lfsr_reg[7] ^ 201 | next_lfsr_reg[6] ^ next_lfsr_reg[5]); 202 | assign next_lfsr_reg[0] = ~(lfsr_reg_r[0] ^ next_lfsr_reg[6] ^ 203 | next_lfsr_reg[5] ^ next_lfsr_reg[4]); 204 | end 205 | end else if (PRBS_WIDTH == 10) begin: gen_next_lfsr_prbs10 206 | if (nCK_PER_CLK == 2) begin: gen_ck_per_clk2 207 | assign next_lfsr_reg[9] = lfsr_reg_r[5]; 208 | assign next_lfsr_reg[8] = lfsr_reg_r[4]; 209 | assign next_lfsr_reg[7] = lfsr_reg_r[3]; 210 | assign next_lfsr_reg[6] = lfsr_reg_r[2]; 211 | assign next_lfsr_reg[5] = lfsr_reg_r[1]; 212 | assign next_lfsr_reg[4] = lfsr_reg_r[0]; 213 | assign next_lfsr_reg[3] = ~(lfsr_reg_r[9] ^ lfsr_reg_r[6]); 214 | assign next_lfsr_reg[2] = ~(lfsr_reg_r[8] ^ lfsr_reg_r[5]); 215 | assign next_lfsr_reg[1] = ~(lfsr_reg_r[7] ^ lfsr_reg_r[4]); 216 | assign next_lfsr_reg[0] = ~(lfsr_reg_r[6] ^ lfsr_reg_r[3]); 217 | end else if (nCK_PER_CLK == 4) begin: gen_ck_per_clk4 218 | assign next_lfsr_reg[9] = lfsr_reg_r[1]; 219 | assign next_lfsr_reg[8] = lfsr_reg_r[0]; 220 | assign next_lfsr_reg[7] = ~(lfsr_reg_r[9] ^ lfsr_reg_r[6]); 221 | assign next_lfsr_reg[6] = ~(lfsr_reg_r[8] ^ lfsr_reg_r[5]); 222 | assign next_lfsr_reg[5] = ~(lfsr_reg_r[7] ^ lfsr_reg_r[4]); 223 | assign next_lfsr_reg[4] = ~(lfsr_reg_r[6] ^ lfsr_reg_r[3]); 224 | assign next_lfsr_reg[3] = ~(lfsr_reg_r[5] ^ lfsr_reg_r[2]); 225 | assign next_lfsr_reg[2] = ~(lfsr_reg_r[4] ^ lfsr_reg_r[1]); 226 | assign next_lfsr_reg[1] = ~(lfsr_reg_r[3] ^ lfsr_reg_r[0]); 227 | assign next_lfsr_reg[0] = ~(lfsr_reg_r[2] ^ next_lfsr_reg[7]); 228 | end 229 | end 230 | endgenerate 231 | 232 | // Output highest (2*nCK_PER_CLK) taps of LFSR - note that the "earliest" 233 | // tap is highest tap (e.g. for an 8-bit LFSR, tap[7] contains the first 234 | // data sent out the shift register), therefore tap[PRBS_WIDTH-1] must be 235 | // routed to bit[0] of the output, tap[PRBS_WIDTH-2] to bit[1] of the 236 | // output, etc. 237 | generate 238 | for (i = 0; i < 2*nCK_PER_CLK; i = i + 1) begin: gen_prbs_transpose 239 | assign prbs_o[i] = lfsr_reg_r[PRBS_WIDTH-1-i]; 240 | end 241 | endgenerate 242 | 243 | 244 | endmodule 245 | 246 | 247 | -------------------------------------------------------------------------------- /mig_example.srcs/sources_1/new/mem_example.v: -------------------------------------------------------------------------------- 1 | //We have configured the MIG in 2:1 mode to simplify the clocking 2 | //requirements. Note that the underlying transaction size is still 128-bits. 3 | //In 2:1 mode, we are required to read and write our data across 2 cycles 4 | //in 64-bit chunks. This can be done internal to the module so we still present 5 | //128-bit ports to the rest of the design. 6 | // 7 | //As the 128-bit mode is a bit of overkill for this example, the upper 64-bits are 8 | //always masked off and aren't available external to the module. 9 | // 10 | //A happy side-effect of the 2:1 mode (vs 4:1 mode) is that ui_clk runs at 11 | //double the speed, decreasing the delay of the clock domain crossing from the 12 | //CPU into the ui_*/app_* memory controller domain. 13 | 14 | `include "io_def.vh" 15 | 16 | module mem_example( 17 | input clk_mem, 18 | input rst_n, 19 | 20 | inout[15:0] ddr2_dq, 21 | inout[1:0] ddr2_dqs_n, 22 | inout[1:0] ddr2_dqs_p, 23 | output[12:0] ddr2_addr, 24 | output[2:0] ddr2_ba, 25 | output ddr2_ras_n, 26 | output ddr2_cas_n, 27 | output ddr2_we_n, 28 | output[0:0] ddr2_ck_p, 29 | output[0:0] ddr2_ck_n, 30 | output[0:0] ddr2_cke, 31 | output[0:0] ddr2_cs_n, 32 | output[1:0] ddr2_dm, 33 | output[0:0] ddr2_odt, 34 | 35 | input cpu_clk, 36 | input[27:0] addr, 37 | input[1:0] width, 38 | input[63:0] data_in, 39 | output reg[63:0] data_out, 40 | input rstrobe, 41 | input wstrobe, 42 | output transaction_complete, 43 | output ready 44 | ); 45 | 46 | wire ui_clk, ui_clk_sync_rst; 47 | 48 | reg[2:0] mem_cmd; 49 | reg mem_en; 50 | wire mem_rdy; 51 | 52 | wire mem_rd_data_end, mem_rd_data_valid; 53 | wire[63:0] mem_rd_data; 54 | 55 | reg[63:0] mem_wdf_data; 56 | reg mem_wdf_end, mem_wdf_wren; 57 | reg[7:0] mem_wdf_mask; 58 | wire mem_wdf_rdy; 59 | 60 | mig mig1 ( 61 | .ddr2_addr(ddr2_addr), 62 | .ddr2_ba(ddr2_ba), 63 | .ddr2_cas_n(ddr2_cas_n), 64 | .ddr2_ck_n(ddr2_ck_n), 65 | .ddr2_ck_p(ddr2_ck_p), 66 | .ddr2_cke(ddr2_cke), 67 | .ddr2_ras_n(ddr2_ras_n), 68 | .ddr2_we_n(ddr2_we_n), 69 | .ddr2_dq(ddr2_dq), 70 | .ddr2_dqs_n(ddr2_dqs_n), 71 | .ddr2_dqs_p(ddr2_dqs_p), 72 | .init_calib_complete(), 73 | 74 | .ddr2_cs_n(ddr2_cs_n), 75 | .ddr2_dm(ddr2_dm), 76 | .ddr2_odt(ddr2_odt), 77 | 78 | .app_addr(addr[27:1]), 79 | .app_cmd(mem_cmd), 80 | .app_en(mem_en), 81 | .app_wdf_data(mem_wdf_data), 82 | .app_wdf_end(mem_wdf_end), 83 | .app_wdf_wren(mem_wdf_wren), 84 | .app_rd_data(mem_rd_data), 85 | .app_rd_data_end(mem_rd_data_end), 86 | .app_rd_data_valid(mem_rd_data_valid), 87 | .app_rdy(mem_rdy), 88 | .app_wdf_rdy(mem_wdf_rdy), 89 | .app_sr_req(1'b0), 90 | .app_ref_req(1'b0), 91 | .app_zq_req(1'b0), 92 | .app_sr_active(), 93 | .app_ref_ack(), 94 | .app_zq_ack(), 95 | .ui_clk(ui_clk), 96 | .ui_clk_sync_rst(ui_clk_sync_rst), 97 | 98 | .app_wdf_mask(mem_wdf_mask), 99 | 100 | .sys_clk_i(clk_mem), 101 | .sys_rst(rst_n) 102 | ); 103 | 104 | //Addresses and data remain stable from the initial strobe till the end of 105 | //the transaction. It is only necessary to synchronize the strobes. 106 | wire rstrobe_sync, wstrobe_sync; 107 | 108 | flag_sync rs_sync( 109 | .a_rst_n(rst_n), 110 | .a_clk(cpu_clk), 111 | .a_flag(rstrobe), 112 | .b_rst_n(~ui_clk_sync_rst), 113 | .b_clk(ui_clk), 114 | .b_flag(rstrobe_sync) 115 | ); 116 | 117 | flag_sync ws_sync( 118 | .a_rst_n(rst_n), 119 | .a_clk(cpu_clk), 120 | .a_flag(wstrobe), 121 | .b_rst_n(~ui_clk_sync_rst), 122 | .b_clk(ui_clk), 123 | .b_flag(wstrobe_sync) 124 | ); 125 | 126 | reg complete; 127 | 128 | flag_sync complete_sync( 129 | .a_rst_n(~ui_clk_sync_rst), 130 | .a_clk(ui_clk), 131 | .a_flag(complete), 132 | .b_rst_n(rst_n), 133 | .b_clk(cpu_clk), 134 | .b_flag(transaction_complete) 135 | ); 136 | 137 | ff_sync ready_sync( 138 | .clk(cpu_clk), 139 | .rst_p(~rst_n), 140 | .in_async(~ui_clk_sync_rst), 141 | .out(ready) 142 | ); 143 | 144 | reg[2:0] state; 145 | 146 | localparam STATE_IDLE = 3'h0; 147 | localparam STATE_PREREAD = 3'h1; 148 | localparam STATE_READ = 3'h2; 149 | localparam STATE_WRITE = 3'h4; 150 | localparam STATE_WRITEDATA_H = 3'h5; 151 | localparam STATE_WRITEDATA_L = 3'h6; 152 | 153 | localparam CMD_READ = 3'h1; 154 | localparam CMD_WRITE = 3'h0; 155 | 156 | //mem_rd_data becomes ready the same cycle as mem_rdy is asserted and 157 | //otherwise has no relationship with mem_rdy. mem_rd_data_valid is the 158 | //only authoritative trigger for registering read bytes. 159 | always @(posedge ui_clk) begin 160 | if(ui_clk_sync_rst) begin 161 | data_out <= 64'h0; 162 | end else begin 163 | if (state == STATE_READ && mem_rd_data_valid || //Data is available normally 164 | state == STATE_PREREAD && mem_rdy && mem_rd_data_valid) begin //Data happens to be available immediately 165 | if(~addr[0]) begin 166 | if(~mem_rd_data_end) case(width) 167 | `RAM_WIDTH64: data_out[63:0] <= {mem_rd_data[7:0],mem_rd_data[15:8], 168 | mem_rd_data[23:16],mem_rd_data[31:24], 169 | mem_rd_data[39:32],mem_rd_data[47:40], 170 | mem_rd_data[55:48],mem_rd_data[63:56]}; 171 | `RAM_WIDTH32: data_out[63:0] <= {mem_rd_data[7:0],mem_rd_data[15:8], 172 | mem_rd_data[23:16],mem_rd_data[31:24],32'h0}; 173 | `RAM_WIDTH16: data_out[63:0] <= {mem_rd_data[7:0],mem_rd_data[15:8],48'h0}; 174 | `RAM_WIDTH8: data_out[63:0] <= {mem_rd_data[7:0],56'h0}; 175 | endcase 176 | end else begin 177 | if(mem_rd_data_end) begin 178 | if(width == `RAM_WIDTH64) data_out[7:0] <= mem_rd_data[7:0]; 179 | end else case(width) 180 | `RAM_WIDTH64: data_out[63:8] <= {mem_rd_data[15:8],mem_rd_data[23:16], 181 | mem_rd_data[31:24],mem_rd_data[39:32], 182 | mem_rd_data[47:40],mem_rd_data[55:48], 183 | mem_rd_data[63:56]}; 184 | `RAM_WIDTH32: data_out[63:0] <= {mem_rd_data[15:8],mem_rd_data[23:16], 185 | mem_rd_data[31:24],mem_rd_data[39:32],32'h0}; 186 | `RAM_WIDTH16: data_out[63:0] <= {mem_rd_data[15:8],mem_rd_data[23:16],48'h0}; 187 | `RAM_WIDTH8: data_out[63:0] <= {mem_rd_data[15:8],56'h0}; 188 | endcase 189 | end 190 | end 191 | end 192 | end 193 | 194 | //The Command and Write Data queues are independent 195 | always @(posedge ui_clk) begin 196 | if(ui_clk_sync_rst) begin 197 | state <= STATE_IDLE; 198 | complete <= 0; 199 | mem_cmd <= CMD_WRITE; 200 | mem_wdf_mask <= 8'h00; 201 | mem_wdf_data <= 64'h0; 202 | mem_wdf_wren <= 0; 203 | mem_wdf_end <= 0; 204 | mem_en <= 0; 205 | end else begin 206 | complete <= 0; 207 | 208 | case(state) 209 | 210 | STATE_IDLE: begin 211 | mem_wdf_wren <= 0; 212 | if(wstrobe_sync) begin 213 | mem_en <= 1; 214 | mem_cmd <= CMD_WRITE; 215 | mem_wdf_end <= 0; 216 | state <= STATE_WRITE; 217 | end 218 | else if(rstrobe_sync) begin 219 | mem_en <= 1; 220 | mem_cmd <= CMD_READ; 221 | state <= STATE_PREREAD; 222 | end 223 | end 224 | 225 | STATE_WRITEDATA_H: begin 226 | if(mem_wdf_rdy) begin //Wait for Write Data queue to have space 227 | if(~addr[0]) case(width) 228 | `RAM_WIDTH64: begin 229 | mem_wdf_mask <= 8'h00; 230 | mem_wdf_data <= {data_in[7:0],data_in[15:8],data_in[23:16],data_in[31:24], 231 | data_in[39:32],data_in[47:40],data_in[55:48],data_in[63:56]}; 232 | end 233 | `RAM_WIDTH32: begin 234 | mem_wdf_mask <= 8'hF0; 235 | mem_wdf_data <= {32'h0,data_in[7:0],data_in[15:8],data_in[23:16],data_in[31:24]}; 236 | end 237 | `RAM_WIDTH16: begin 238 | mem_wdf_mask <= 8'hFC; 239 | mem_wdf_data <= {48'h0,data_in[7:0],data_in[15:8]}; 240 | end 241 | `RAM_WIDTH8: begin 242 | mem_wdf_mask <= 8'hFE; 243 | mem_wdf_data <= {56'h0,data_in[7:0]}; 244 | end 245 | endcase 246 | else case(width) 247 | `RAM_WIDTH64: begin 248 | mem_wdf_mask <= 8'h01; 249 | mem_wdf_data <= {data_in[15:8],data_in[23:16],data_in[31:24], 250 | data_in[39:32],data_in[47:40],data_in[55:48],data_in[63:56],8'h0}; 251 | end 252 | `RAM_WIDTH32: begin 253 | mem_wdf_mask <= 8'hE1; 254 | mem_wdf_data <= {24'h0,data_in[7:0],data_in[15:8],data_in[23:16],data_in[31:24],8'h0}; 255 | end 256 | `RAM_WIDTH16: begin 257 | mem_wdf_mask <= 8'hF9; 258 | mem_wdf_data <= {40'h0,data_in[7:0],data_in[15:8],8'h0}; 259 | end 260 | `RAM_WIDTH8: begin 261 | mem_wdf_mask <= 8'hFD; 262 | mem_wdf_data <= {48'h0,data_in[7:0],8'h0}; 263 | end 264 | endcase 265 | 266 | mem_wdf_wren <= 1; 267 | state <= STATE_WRITEDATA_L; 268 | end 269 | end 270 | 271 | STATE_WRITEDATA_L: begin 272 | if(mem_wdf_rdy) begin //Wait for Write Data queue to have space 273 | if(~addr[0]) begin 274 | mem_wdf_mask <= 8'hFF; 275 | mem_wdf_data <= 64'h0; 276 | end else begin 277 | mem_wdf_mask <= 8'hFE; 278 | mem_wdf_data <= {56'h0,data_in[7:0]}; 279 | end 280 | mem_wdf_wren <= 1; 281 | mem_wdf_end <= 1; 282 | complete <= 1; 283 | state <= STATE_IDLE; 284 | end 285 | end 286 | 287 | STATE_PREREAD: begin 288 | if(mem_rdy) begin //Wait for command queue to accept command 289 | mem_en <= 0; 290 | state <= STATE_READ; 291 | if(mem_rd_data_valid & mem_rd_data_end) begin //If data happens to be available now 292 | state <= STATE_IDLE; 293 | complete <= 1; 294 | end 295 | end 296 | end 297 | 298 | STATE_READ: begin 299 | if(mem_rd_data_valid & mem_rd_data_end) begin 300 | state <= STATE_IDLE; 301 | complete <= 1; 302 | end 303 | end 304 | 305 | STATE_WRITE: begin 306 | if(mem_rdy) begin //Wait for command queue to accept command 307 | mem_en <= 0; 308 | state <= STATE_WRITEDATA_H; 309 | end 310 | end 311 | endcase 312 | end 313 | end 314 | endmodule 315 | -------------------------------------------------------------------------------- /mig_example.srcs/sources_1/ip/mig/mig/example_design/rtl/traffic_gen/mig_7series_v4_2_rd_data_gen.v: -------------------------------------------------------------------------------- 1 | //***************************************************************************** 2 | // (c) Copyright 2008-2010 Xilinx, Inc. All rights reserved. 3 | // 4 | // This file contains confidential and proprietary information 5 | // of Xilinx, Inc. and is protected under U.S. and 6 | // international copyright and other intellectual property 7 | // laws. 8 | // 9 | // DISCLAIMER 10 | // This disclaimer is not a license and does not grant any 11 | // rights to the materials distributed herewith. Except as 12 | // otherwise provided in a valid license issued to you by 13 | // Xilinx, and to the maximum extent permitted by applicable 14 | // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 15 | // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 16 | // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 17 | // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 18 | // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 19 | // (2) Xilinx shall not be liable (whether in contract or tort, 20 | // including negligence, or under any other theory of 21 | // liability) for any loss or damage of any kind or nature 22 | // related to, arising under or in connection with these 23 | // materials, including for any direct, or any indirect, 24 | // special, incidental, or consequential loss or damage 25 | // (including loss of data, profits, goodwill, or any type of 26 | // loss or damage suffered as a result of any action brought 27 | // by a third party) even if such damage or loss was 28 | // reasonably foreseeable or Xilinx had been advised of the 29 | // possibility of the same. 30 | // 31 | // CRITICAL APPLICATIONS 32 | // Xilinx products are not designed or intended to be fail- 33 | // safe, or for use in any application requiring fail-safe 34 | // performance, such as life-support or safety devices or 35 | // systems, Class III medical devices, nuclear facilities, 36 | // applications related to the deployment of airbags, or any 37 | // other applications that could lead to death, personal 38 | // injury, or severe property or environmental damage 39 | // (individually and collectively, "Critical 40 | // Applications"). Customer assumes the sole risk and 41 | // liability of any use of Xilinx products in Critical 42 | // Applications, subject only to applicable laws and 43 | // regulations governing limitations on product liability. 44 | // 45 | // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 46 | // PART OF THIS FILE AT ALL TIMES. 47 | // 48 | //***************************************************************************** 49 | // ____ ____ 50 | // / /\/ / 51 | // /___/ \ / Vendor: Xilinx 52 | // \ \ \/ Version: %version 53 | // \ \ Application: MIG 54 | // / / Filename: rd_data_gen.v 55 | // /___/ /\ Date Last Modified: 56 | // \ \ / \ Date Created: 57 | // \___\/\___\ 58 | // 59 | //Device: Spartan6 60 | //Design Name: DDR/DDR2/DDR3/LPDDR 61 | //Purpose: This module has all the timing control for generating "compare data" 62 | // to compare the read data from memory. 63 | //Reference: 64 | //Revision History: 65 | //***************************************************************************** 66 | 67 | `timescale 1ps/1ps 68 | 69 | module mig_7series_v4_2_rd_data_gen # 70 | ( 71 | parameter TCQ = 100, 72 | parameter FAMILY = "VIRTEX7", // "SPARTAN6", "VIRTEX6" 73 | parameter MEM_TYPE = "DDR3", 74 | parameter nCK_PER_CLK = 4, // DRAM clock : MC clock 75 | 76 | parameter MEM_BURST_LEN = 8, 77 | parameter START_ADDR = 32'h00000000, 78 | 79 | parameter ADDR_WIDTH = 32, 80 | parameter BL_WIDTH = 6, 81 | parameter DWIDTH = 32, 82 | parameter DATA_PATTERN = "DGEN_ALL", //"DGEN__HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL" 83 | parameter NUM_DQ_PINS = 8, 84 | parameter SEL_VICTIM_LINE = 3, // VICTIM LINE is one of the DQ pins is selected to be different than hammer pattern 85 | 86 | parameter COLUMN_WIDTH = 10 87 | 88 | ) 89 | ( 90 | input clk_i, // 91 | input [4:0] rst_i, 92 | input [31:0] prbs_fseed_i, 93 | input [3:0] data_mode_i, // "00" = bram; 94 | input mode_load_i, 95 | input [3:0] vio_instr_mode_value, 96 | 97 | output cmd_rdy_o, // ready to receive command. It should assert when data_port is ready at the // beginning and will be deasserted once see the cmd_valid_i is asserted. 98 | // And then it should reasserted when 99 | // it is generating the last_word. 100 | input cmd_valid_i, // when both cmd_valid_i and cmd_rdy_o is high, the command is valid. 101 | output reg cmd_start_o, 102 | // input [ADDR_WIDTH-1:0] m_addr_i, // generated address used to determine data pattern. 103 | 104 | input [31:0] simple_data0 , 105 | input [31:0] simple_data1 , 106 | input [31:0] simple_data2 , 107 | input [31:0] simple_data3 , 108 | input [31:0] simple_data4 , 109 | input [31:0] simple_data5 , 110 | input [31:0] simple_data6 , 111 | input [31:0] simple_data7 , 112 | 113 | 114 | input [31:0] fixed_data_i, 115 | input [ADDR_WIDTH-1:0] addr_i, // generated address used to determine data pattern. 116 | input [BL_WIDTH-1:0] bl_i, // generated burst length for control the burst data 117 | output user_bl_cnt_is_1_o, 118 | input data_rdy_i, // connect from mcb_wr_full when used as wr_data_gen in sp6 119 | // connect from mcb_rd_empty when used as rd_data_gen in sp6 120 | // connect from rd_data_valid in v6 121 | // When both data_rdy and data_valid is asserted, the ouput data is valid. 122 | output reg data_valid_o, // connect to wr_en or rd_en and is asserted whenever the 123 | // pattern is available. 124 | // output [DWIDTH-1:0] data_o // generated data pattern NUM_DQ_PINS*nCK_PER_CLK*2-1 125 | output [31:0] tg_st_addr_o, 126 | output [NUM_DQ_PINS*nCK_PER_CLK*2-1:0] data_o // generated data pattern NUM_DQ_PINS*nCK_PER_CLK*2-1 127 | 128 | ); 129 | // 130 | 131 | 132 | 133 | wire [31:0] prbs_data; 134 | reg cmd_start; 135 | reg [31:0] adata; 136 | reg [31:0] hdata; 137 | reg [31:0] ndata; 138 | reg [31:0] w1data; 139 | reg [NUM_DQ_PINS*4-1:0] v6_w1data; 140 | 141 | reg [31:0] w0data; 142 | reg [DWIDTH-1:0] data; 143 | reg cmd_rdy; 144 | reg [BL_WIDTH:0]user_burst_cnt; 145 | reg [31:0] w3data; 146 | reg prefetch; 147 | assign data_port_fifo_rdy = data_rdy_i; 148 | 149 | 150 | 151 | 152 | reg user_bl_cnt_is_1; 153 | assign user_bl_cnt_is_1_o = user_bl_cnt_is_1; 154 | always @ (posedge clk_i) 155 | begin 156 | if (data_port_fifo_rdy) 157 | if ((user_burst_cnt == 2 && FAMILY == "SPARTAN6") 158 | || (user_burst_cnt == 2 && FAMILY == "VIRTEX6") 159 | ) 160 | 161 | user_bl_cnt_is_1 <= #TCQ 1'b1; 162 | else 163 | user_bl_cnt_is_1 <= #TCQ 1'b0; 164 | end 165 | 166 | 167 | //reg cmd_start_b; 168 | always @(cmd_valid_i,data_port_fifo_rdy,cmd_rdy,user_bl_cnt_is_1,prefetch) 169 | begin 170 | 171 | cmd_start = cmd_valid_i & cmd_rdy & ( data_port_fifo_rdy | prefetch) ; 172 | cmd_start_o = cmd_valid_i & cmd_rdy & ( data_port_fifo_rdy | prefetch) ; 173 | 174 | end 175 | 176 | 177 | 178 | 179 | // counter to count user burst length 180 | // verilint STARC-2.2.3.3 off 181 | always @( posedge clk_i) 182 | begin 183 | if ( rst_i[0] ) 184 | user_burst_cnt <= #TCQ 'd0; 185 | else if(cmd_valid_i && cmd_rdy && ( data_port_fifo_rdy | prefetch) ) begin 186 | 187 | // SPATAN6 has maximum of burst length of 64. 188 | if (FAMILY == "SPARTAN6" && bl_i[5:0] == 6'b000000) 189 | begin 190 | user_burst_cnt[6:0] <= #TCQ 7'd64; 191 | user_burst_cnt[BL_WIDTH:7] <= 'b0; 192 | end 193 | else if (FAMILY == "VIRTEX6" && bl_i[BL_WIDTH - 1:0] == {BL_WIDTH {1'b0}}) 194 | user_burst_cnt <= #TCQ {1'b1, {BL_WIDTH{1'b0}}}; 195 | else 196 | user_burst_cnt <= #TCQ {1'b0,bl_i }; 197 | end 198 | else if(data_port_fifo_rdy) 199 | if (user_burst_cnt != 6'd0) 200 | user_burst_cnt <= #TCQ user_burst_cnt - 1'b1; 201 | else 202 | user_burst_cnt <= #TCQ 'd0; 203 | 204 | end 205 | // verilint STARC-2.2.3.3 on 206 | 207 | // cmd_rdy_o assert when the dat fifo is not full and deassert once cmd_valid_i 208 | // is assert and reassert during the last data 209 | 210 | //data_valid_o logic 211 | 212 | always @( posedge clk_i) 213 | begin 214 | if ( rst_i[0] ) 215 | prefetch <= #TCQ 1'b1; 216 | else if (data_port_fifo_rdy || cmd_start) 217 | prefetch <= #TCQ 1'b0; 218 | 219 | else if (user_burst_cnt == 0 && ~data_port_fifo_rdy) 220 | prefetch <= #TCQ 1'b1; 221 | 222 | end 223 | assign cmd_rdy_o = cmd_rdy ; 224 | 225 | always @( posedge clk_i) 226 | begin 227 | if ( rst_i[0] ) 228 | cmd_rdy <= #TCQ 1'b1; 229 | 230 | else if (cmd_valid_i && cmd_rdy && (data_port_fifo_rdy || prefetch )) 231 | cmd_rdy <= #TCQ 1'b0; 232 | else if ((data_port_fifo_rdy && user_burst_cnt == 2 && vio_instr_mode_value != 7 ) || 233 | (data_port_fifo_rdy && user_burst_cnt == 1 && vio_instr_mode_value == 7 )) 234 | 235 | cmd_rdy <= #TCQ 1'b1; 236 | 237 | 238 | end 239 | 240 | 241 | 242 | 243 | always @ (data_port_fifo_rdy) 244 | if (FAMILY == "SPARTAN6") 245 | data_valid_o = data_port_fifo_rdy; 246 | else 247 | data_valid_o = data_port_fifo_rdy; 248 | 249 | 250 | /* 251 | generate 252 | if (FAMILY == "SPARTAN6") 253 | begin : SP6_DGEN 254 | s7ven_data_gen # 255 | 256 | ( 257 | .TCQ (TCQ), 258 | .DMODE ("READ"), 259 | .nCK_PER_CLK (nCK_PER_CLK), 260 | .FAMILY (FAMILY), 261 | 262 | .ADDR_WIDTH (32 ), 263 | .BL_WIDTH (BL_WIDTH ), 264 | .MEM_BURST_LEN (MEM_BURST_LEN), 265 | .DWIDTH (DWIDTH ), 266 | .DATA_PATTERN (DATA_PATTERN ), 267 | .NUM_DQ_PINS (NUM_DQ_PINS ), 268 | .SEL_VICTIM_LINE (SEL_VICTIM_LINE), 269 | .START_ADDR (START_ADDR), 270 | 271 | .COLUMN_WIDTH (COLUMN_WIDTH) 272 | 273 | ) 274 | s7ven_data_gen 275 | ( 276 | .clk_i (clk_i ), 277 | .rst_i (rst_i[1] ), 278 | .data_rdy_i (data_rdy_i ), 279 | .mem_init_done_i (1'b1), 280 | .wr_data_mask_gen_i (1'b0), 281 | 282 | .prbs_fseed_i (prbs_fseed_i), 283 | .mode_load_i (mode_load_i), 284 | .data_mode_i (data_mode_i ), 285 | .cmd_startA (cmd_start ), 286 | .cmd_startB (cmd_start ), 287 | .cmd_startC (cmd_start ), 288 | .cmd_startD (cmd_start ), 289 | .cmd_startE (cmd_start ), 290 | .m_addr_i (addr_i),//(m_addr_i ), 291 | 292 | .simple_data0 (simple_data0), 293 | .simple_data1 (simple_data1), 294 | .simple_data2 (simple_data2), 295 | .simple_data3 (simple_data3), 296 | .simple_data4 (simple_data4), 297 | .simple_data5 (simple_data5), 298 | .simple_data6 (simple_data6), 299 | .simple_data7 (simple_data7), 300 | .fixed_data_i (fixed_data_i), 301 | 302 | .addr_i (addr_i ), 303 | .user_burst_cnt (user_burst_cnt), 304 | .fifo_rdy_i (data_port_fifo_rdy ), 305 | .data_o (data_o ), 306 | .data_mask_o (), 307 | 308 | .bram_rd_valid_o () 309 | ); 310 | 311 | end 312 | 313 | endgenerate*/ 314 | //generate 315 | //if (FAMILY == "VIRTEX6") 316 | //begin : V_DGEN 317 | mig_7series_v4_2_s7ven_data_gen # 318 | ( 319 | .TCQ (TCQ), 320 | .DMODE ("READ"), 321 | .nCK_PER_CLK (nCK_PER_CLK), 322 | .FAMILY (FAMILY), 323 | .MEM_TYPE (MEM_TYPE), 324 | 325 | .ADDR_WIDTH (32 ), 326 | .BL_WIDTH (BL_WIDTH ), 327 | .MEM_BURST_LEN (MEM_BURST_LEN), 328 | .DWIDTH (DWIDTH ), 329 | .DATA_PATTERN (DATA_PATTERN ), 330 | .NUM_DQ_PINS (NUM_DQ_PINS ), 331 | .SEL_VICTIM_LINE (SEL_VICTIM_LINE), 332 | .START_ADDR (START_ADDR), 333 | 334 | .COLUMN_WIDTH (COLUMN_WIDTH) 335 | 336 | ) 337 | s7ven_data_gen 338 | ( 339 | .clk_i (clk_i ), 340 | .rst_i (rst_i[1] ), 341 | .data_rdy_i (data_rdy_i ), 342 | .mem_init_done_i (1'b1), 343 | .wr_data_mask_gen_i (1'b0), 344 | 345 | .prbs_fseed_i (prbs_fseed_i), 346 | .mode_load_i (mode_load_i), 347 | .data_mode_i (data_mode_i ), 348 | .cmd_startA (cmd_start ), 349 | .cmd_startB (cmd_start ), 350 | .cmd_startC (cmd_start ), 351 | .cmd_startD (cmd_start ), 352 | .cmd_startE (cmd_start ), 353 | .m_addr_i (addr_i),//(m_addr_i ), 354 | 355 | .simple_data0 (simple_data0), 356 | .simple_data1 (simple_data1), 357 | .simple_data2 (simple_data2), 358 | .simple_data3 (simple_data3), 359 | .simple_data4 (simple_data4), 360 | .simple_data5 (simple_data5), 361 | .simple_data6 (simple_data6), 362 | .simple_data7 (simple_data7), 363 | .fixed_data_i (fixed_data_i), 364 | 365 | .addr_i (addr_i ), 366 | .user_burst_cnt (user_burst_cnt), 367 | .fifo_rdy_i (data_port_fifo_rdy ), 368 | .data_o (data_o ), 369 | .tg_st_addr_o (tg_st_addr_o), 370 | .data_mask_o (), 371 | 372 | .bram_rd_valid_o () 373 | ); 374 | 375 | //end 376 | //endgenerate 377 | 378 | 379 | 380 | 381 | 382 | endmodule 383 | -------------------------------------------------------------------------------- /mig_example.srcs/sources_1/ip/mig/mig/example_design/rtl/traffic_gen/mig_7series_v4_2_vio_init_pattern_bram.v: -------------------------------------------------------------------------------- 1 | //***************************************************************************** 2 | // (c) Copyright 2008-2010 Xilinx, Inc. All rights reserved. 3 | // 4 | // This file contains confidential and proprietary information 5 | // of Xilinx, Inc. and is protected under U.S. and 6 | // international copyright and other intellectual property 7 | // laws. 8 | // 9 | // DISCLAIMER 10 | // This disclaimer is not a license and does not grant any 11 | // rights to the materials distributed herewith. Except as 12 | // otherwise provided in a valid license issued to you by 13 | // Xilinx, and to the maximum extent permitted by applicable 14 | // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 15 | // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 16 | // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 17 | // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 18 | // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 19 | // (2) Xilinx shall not be liable (whether in contract or tort, 20 | // including negligence, or under any other theory of 21 | // liability) for any loss or damage of any kind or nature 22 | // related to, arising under or in connection with these 23 | // materials, including for any direct, or any indirect, 24 | // special, incidental, or consequential loss or damage 25 | // (including loss of data, profits, goodwill, or any type of 26 | // loss or damage suffered as a result of any action brought 27 | // by a third party) even if such damage or loss was 28 | // reasonably foreseeable or Xilinx had been advised of the 29 | // possibility of the same. 30 | // 31 | // CRITICAL APPLICATIONS 32 | // Xilinx products are not designed or intended to be fail- 33 | // safe, or for use in any application requiring fail-safe 34 | // performance, such as life-support or safety devices or 35 | // systems, Class III medical devices, nuclear facilities, 36 | // applications related to the deployment of airbags, or any 37 | // other applications that could lead to death, personal 38 | // injury, or severe property or environmental damage 39 | // (individually and collectively, "Critical 40 | // Applications"). Customer assumes the sole risk and 41 | // liability of any use of Xilinx products in Critical 42 | // Applications, subject only to applicable laws and 43 | // regulations governing limitations on product liability. 44 | // 45 | // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 46 | // PART OF THIS FILE AT ALL TIMES. 47 | // 48 | //***************************************************************************** 49 | // ____ ____ 50 | // / /\/ / 51 | // /___/ \ / Vendor: Xilinx 52 | // \ \ \/ Version: %version 53 | // \ \ Application: MIG 54 | // / / Filename: tb_cmd_gen.v 55 | // /___/ /\ Date Last Modified: $Date: 2011/06/02 08:37:25 $ 56 | // \ \ / \ Date Created: Fri Sep 01 2006 57 | // \___\/\___\ 58 | // 59 | //Device: Fuji 60 | //Design Name: vio_init_pattern_bram 61 | //Purpose: This moduel takes external defined data inputs as its bram init pattern. 62 | // It allows users to change simple test data pattern withoug recompilation. 63 | //Revision History: 64 | //***************************************************************************** 65 | 66 | `timescale 1ps/1ps 67 | `ifndef TCQ 68 | `define TCQ 100 69 | `endif 70 | module mig_7series_v4_2_vio_init_pattern_bram # 71 | ( 72 | parameter TCQ = 100, 73 | parameter START_ADDR = 32'h00000000, 74 | parameter MEM_BURST_LEN = 8, 75 | parameter ADDR_WIDTH = 4, 76 | parameter DEPTH = 16, 77 | parameter NUM_DQ_PINS = 8, 78 | parameter SEL_VICTIM_LINE = NUM_DQ_PINS // possible value : 0 to NUM_DQ_PINS 79 | 80 | ) 81 | ( 82 | input clk_i, 83 | input rst_i, 84 | input cmd_start, 85 | input [31:0] cmd_addr, // 86 | input mode_load_i, // signal to initialze internal bram 87 | // with input data1 through data9. 88 | input [3:0] data_mode_i, // selection of data pattern. 89 | input [31:0] data0, // data1 through data8 are 90 | input [31:0] data1, // used as simple traffic data 91 | input [31:0] data2, // pattern that repeats continuously 92 | input [31:0] data3, 93 | input [31:0] data4, 94 | input [31:0] data5, 95 | input [31:0] data6, 96 | input [31:0] data7, 97 | input [31:0] data8, // used a fixed input data 98 | 99 | output reg bram_rd_valid_o, 100 | input bram_rd_rdy_i, 101 | output [31:0] dout_o 102 | ); 103 | 104 | function integer logb2; 105 | input [31:0] number; 106 | integer i; 107 | begin 108 | i = number; 109 | for(logb2=1; i>0; logb2=logb2+1) 110 | i = i >> 1; 111 | end 112 | endfunction 113 | 114 | reg [ADDR_WIDTH - 1:0] wr_addr /* synthesis syn_maxfan = 8 */; 115 | reg [ADDR_WIDTH - 1:0] rd_addr /* synthesis syn_maxfan = 8 */; 116 | reg init_write; 117 | reg mode_load_r1; 118 | reg mode_load_r2; 119 | reg [31:0] data_in0; 120 | reg [31:0] data_in1; 121 | reg [31:0] data_in2; 122 | reg [31:0] data_in3; 123 | reg [31:0] data_in4; 124 | reg [31:0] data_in5; 125 | reg [31:0] data_in6; 126 | reg [31:0] data_in7; 127 | reg [31:0] data_in8; 128 | reg [31:0] data_in9; 129 | reg [31:0] data_in10; 130 | reg [31:0] data_in11; 131 | reg [31:0] data_in12; 132 | reg [31:0] data_in13; 133 | reg [31:0] data_in14; 134 | reg [31:0] data_in15; 135 | reg [31:0] hdata; 136 | reg [7:0] mem_0 [0:DEPTH - 1]; 137 | reg [7:0] mem_1 [0:DEPTH - 1]; 138 | reg [7:0] mem_2 [0:DEPTH - 1]; 139 | reg [7:0] mem_3 [0:DEPTH - 1]; 140 | reg [31:0] data_in; 141 | reg wr_en; 142 | reg cmd_addr_r9; 143 | integer i,j,k; 144 | 145 | always @ (posedge clk_i) 146 | begin 147 | mode_load_r1 <= mode_load_i; 148 | mode_load_r2 <= mode_load_r1; 149 | end 150 | 151 | always @ (posedge clk_i) 152 | begin 153 | if (rst_i) 154 | init_write <= 'b0; 155 | else if (wr_addr == {4'b0111}) 156 | init_write <= 'b1; 157 | else if (mode_load_r1 && ~mode_load_r2 && data_mode_i != 4'b0010) 158 | init_write <= 'b1; 159 | end 160 | 161 | // generate a mutil_cycle control siganl to improve timing. 162 | always @ (posedge clk_i) 163 | begin 164 | if (rst_i) 165 | wr_en <= 1'b1; 166 | else if (init_write && data_mode_i != 4'b0010) 167 | wr_en <= 1'b1; 168 | end 169 | 170 | always @ (posedge clk_i) 171 | begin 172 | if (rst_i) 173 | wr_addr <= 'b0; 174 | else if (data_mode_i == 4'h1) 175 | wr_addr <= 4'b1000; 176 | else if (data_mode_i == 4'b0011) 177 | wr_addr <= 4'b1001; 178 | else if (~init_write && data_mode_i == 4'b0100) 179 | wr_addr <= 4'b0000; 180 | else if (init_write && wr_en && data_mode_i != 4'b0010 && wr_addr != 15) 181 | wr_addr <= wr_addr + 1'b1; 182 | end 183 | 184 | // HAMMER_PATTERN_MINUS: generate walking HAMMER data pattern except 1 bit for the whole burst. 185 | // The incoming addr_i[5:2] determine the position of the pin driving oppsite polarity 186 | // addr_i[6:2] = 5'h0f ; 32 bit data port 187 | // => the rsing data pattern will be 32'b11111111_11111111_01111111_11111111 188 | // => the falling data pattern will be 32'b00000000_00000000_00000000_00000000 189 | 190 | // Only generate NUM_DQ_PINS width of hdata and will do concatenation in above level. 191 | always @ (posedge clk_i) 192 | begin 193 | for (i= 0; i <= 31; i= i+1) //begin: hammer_data 194 | if (i >= NUM_DQ_PINS) begin 195 | if (SEL_VICTIM_LINE == NUM_DQ_PINS) 196 | hdata[i] <= 1'b0; 197 | else if ( 198 | ((i == SEL_VICTIM_LINE-1) || (i-NUM_DQ_PINS) == SEL_VICTIM_LINE || 199 | (i-(NUM_DQ_PINS*2)) == SEL_VICTIM_LINE || 200 | (i-(NUM_DQ_PINS*3)) == SEL_VICTIM_LINE)) 201 | hdata[i] <= 1'b1; 202 | else 203 | hdata[i] <= 1'b0; 204 | end 205 | else 206 | hdata[i] <= 1'b1; 207 | end 208 | 209 | // content formats 210 | // {burst length, instruction, address} 211 | initial begin 212 | mem_0[0] = {2'b00,6'h00}; 213 | mem_1[0] = 8'h0; 214 | mem_2[0] = 8'h0; 215 | mem_3[0] = 8'h0; 216 | mem_0[1] = {2'b00,6'h04}; 217 | mem_1[1] = 8'h0; 218 | mem_2[1] = 8'h0; 219 | mem_3[1] = 8'h0; 220 | mem_0[2] = {2'b00,6'h08}; 221 | mem_1[2] = 8'h0; 222 | mem_2[2] = 8'h0; 223 | mem_3[2] = 8'h0; 224 | mem_0[3] = {2'b00,6'h0c}; 225 | mem_1[3] = 8'h0; 226 | mem_2[3] = 8'h0; 227 | mem_3[3] = 8'h0; 228 | mem_0[4] = {2'b00,6'h10}; 229 | mem_1[4] = 8'h0; 230 | mem_2[4] = 8'h0; 231 | mem_3[4] = 8'h0; 232 | mem_0[5] = {2'b00,6'h14}; 233 | mem_1[5] = 8'h0; 234 | mem_2[5] = 8'h0; 235 | mem_3[5] = 8'h0; 236 | mem_0[6] = {2'b00,6'h18}; 237 | mem_1[6] = 8'h0; 238 | mem_2[6] = 8'h0; 239 | mem_3[6] = 8'h0; 240 | mem_0[7] = {2'b00,6'h1c}; 241 | mem_1[7] = 8'h0; 242 | mem_2[7] = 8'h0; 243 | mem_3[7] = 8'h0; 244 | mem_0[8] = {2'b00,6'h20}; 245 | mem_1[8] = 8'h0; 246 | mem_2[8] = 8'h0; 247 | mem_3[8] = 8'h0; 248 | mem_0[9] = {2'b00,6'h24}; 249 | mem_1[9] = 8'h0; 250 | mem_2[9] = 8'h0; 251 | mem_3[9] = 8'h0; 252 | mem_0[10] = 8'hff; 253 | mem_1[10] = 8'hff; 254 | mem_2[10] = 8'hff; 255 | mem_3[10] = 8'hff; 256 | mem_0[11] = 8'h0; 257 | mem_1[11] = 8'h0; 258 | mem_2[11] = 8'h0; 259 | mem_3[11] = 8'h0; 260 | mem_0[12] = {2'b00,6'h30}; 261 | mem_1[12] = 8'h0; 262 | mem_2[12] = 8'h0; 263 | mem_3[12] = 8'h0; 264 | mem_0[13] = {2'b00,6'h34}; 265 | mem_1[13] = 8'h0; 266 | mem_2[13] = 8'h0; 267 | mem_3[13] = 8'h0; 268 | mem_0[14] = {2'b00,6'h38}; 269 | mem_1[14] = 8'h0; 270 | mem_2[14] = 8'h0; 271 | mem_3[14] = 8'h0; 272 | mem_0[15] = {2'b00,6'h3c}; 273 | mem_1[15] = 8'h0; 274 | mem_2[15] = 8'h0; 275 | mem_3[15] = 8'h0; 276 | end 277 | 278 | // address is one cycle earlier. 279 | always @ (posedge clk_i) 280 | begin 281 | if (rst_i) 282 | data_in <= #TCQ data0; 283 | else begin 284 | case(wr_addr) 285 | 0: if (init_write) 286 | data_in <= #TCQ data_in1; 287 | else 288 | data_in <= #TCQ data_in0; 289 | 1: data_in <= #TCQ data_in2; 290 | 2: data_in <= #TCQ data_in3; 291 | 3: data_in <= #TCQ data_in4; 292 | 4: data_in <= #TCQ data_in5; 293 | 5: data_in <= #TCQ data_in6; 294 | 6: data_in <= #TCQ data_in7; 295 | 7: data_in <= #TCQ data_in7; 296 | 8: data_in <= #TCQ data_in8; 297 | 9: data_in <= #TCQ data_in9; 298 | 10: data_in <= #TCQ data_in10; 299 | 11: data_in <= #TCQ data_in11; 300 | 12: data_in <= #TCQ data_in12; 301 | 13: data_in <= #TCQ data_in13; 302 | 14: data_in <= #TCQ data_in14; 303 | 15: data_in <= #TCQ data_in15; 304 | default: data_in <= data8; 305 | endcase 306 | end 307 | end 308 | 309 | always @(posedge clk_i) begin 310 | mem_0[wr_addr] <= data_in[7:0]; 311 | mem_1[wr_addr] <= data_in[15:8]; 312 | mem_2[wr_addr] <= data_in[23:16]; 313 | mem_3[wr_addr] <= data_in[31:24]; 314 | end 315 | 316 | always @ (data_mode_i, data0,data1,data2,data3,data4,data5,data6,data7,data8,hdata) 317 | begin 318 | data_in0[31:0] = #TCQ data0; 319 | data_in1[31:0] = #TCQ data1; 320 | data_in2[31:0] = #TCQ data2; 321 | data_in3[31:0] = #TCQ data3; 322 | data_in4[31:0] = #TCQ data4; 323 | data_in5[31:0] = #TCQ data5; 324 | data_in6[31:0] = #TCQ data6; 325 | data_in7[31:0] = #TCQ data7; 326 | data_in8[31:0] = #TCQ data8; 327 | data_in9[31:0] = #TCQ hdata; 328 | data_in10[31:0] = #TCQ 32'hffffffff; 329 | data_in11[31:0] = #TCQ 32'h00000000; 330 | data_in12[31:0] = #TCQ 'b0; 331 | data_in13[31:0] = #TCQ 'b0; 332 | data_in14[31:0] = #TCQ 'b0; 333 | data_in15[31:0] = #TCQ 'b0; 334 | end 335 | 336 | always @ (posedge clk_i) 337 | begin 338 | if (cmd_start) 339 | cmd_addr_r9 <= cmd_addr[9]; 340 | end 341 | 342 | always @ (posedge clk_i) 343 | if (rst_i) 344 | bram_rd_valid_o <= 1'b0; 345 | else if (wr_addr[3:0] == {ADDR_WIDTH - 1{1'b1}} || data_mode_i == 2 || data_mode_i == 3) 346 | bram_rd_valid_o <= 1'b1; 347 | 348 | // rd_address generation depending on data pattern mode. 349 | always @ (posedge clk_i) 350 | begin 351 | if (rst_i) begin 352 | if (data_mode_i == 9) begin 353 | rd_addr[3:1] <= #TCQ 3'b101; 354 | rd_addr[0] <= #TCQ cmd_addr[9]; 355 | end 356 | else if (data_mode_i == 1) 357 | rd_addr[3:0] <= #TCQ 8; 358 | else if (data_mode_i == 3) // address as data pattern 359 | rd_addr <= #TCQ 9; 360 | else 361 | rd_addr <= #TCQ 0; 362 | end 363 | else if (cmd_start) begin 364 | if (data_mode_i == 3) 365 | rd_addr[3:0] <= #TCQ 9; 366 | else if (data_mode_i == 1) 367 | rd_addr[3:0] <= #TCQ 8; 368 | else if (data_mode_i == 9) begin 369 | rd_addr[3:1] <= #TCQ 3'b101; 370 | rd_addr[0] <= #TCQ cmd_addr[9]; 371 | end 372 | else 373 | rd_addr[3:0] <= #TCQ 0; 374 | end 375 | else if (bram_rd_rdy_i) begin 376 | case (data_mode_i) 377 | 4'h2: rd_addr <= #TCQ 0; 378 | 4'h4: if (rd_addr == 7) 379 | rd_addr <= #TCQ 0; 380 | else 381 | rd_addr <= #TCQ rd_addr+ 1'b1; 382 | 4'h1: rd_addr <= #TCQ 8; 383 | 4'h3: rd_addr <= #TCQ 9; 384 | 4'h9: begin 385 | rd_addr[3:1] <= #TCQ 3'b101; 386 | rd_addr[0] <= #TCQ cmd_addr_r9; 387 | end 388 | default: rd_addr <= #TCQ 0; 389 | endcase 390 | end 391 | end 392 | 393 | // need to infer distributed RAM to meet output timing 394 | // in upper level 395 | assign dout_o = {mem_3[rd_addr],mem_2[rd_addr],mem_1[rd_addr],mem_0[rd_addr]}; // 396 | 397 | endmodule 398 | -------------------------------------------------------------------------------- /mig_example.srcs/sources_1/ip/mig/mig/example_design/rtl/traffic_gen/mig_7series_v4_2_wr_data_gen.v: -------------------------------------------------------------------------------- 1 | //***************************************************************************** 2 | // (c) Copyright 2008-2010 Xilinx, Inc. All rights reserved. 3 | // 4 | // This file contains confidential and proprietary information 5 | // of Xilinx, Inc. and is protected under U.S. and 6 | // international copyright and other intellectual property 7 | // laws. 8 | // 9 | // DISCLAIMER 10 | // This disclaimer is not a license and does not grant any 11 | // rights to the materials distributed herewith. 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Customer assumes the sole risk and 41 | // liability of any use of Xilinx products in Critical 42 | // Applications, subject only to applicable laws and 43 | // regulations governing limitations on product liability. 44 | // 45 | // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 46 | // PART OF THIS FILE AT ALL TIMES. 47 | // 48 | //***************************************************************************** 49 | // ____ ____ 50 | // / /\/ / 51 | // /___/ \ / Vendor: Xilinx 52 | // \ \ \/ Version: %version 53 | // \ \ Application: MIG 54 | // / / Filename: wr_data_gen.v 55 | // /___/ /\ Date Last Modified: 56 | // \ \ / \ Date Created: 57 | // \___\/\___\ 58 | // 59 | //Device: Spartan6 60 | //Design Name: DDR/DDR2/DDR3/LPDDR 61 | //Purpose: 62 | //Reference: 63 | //Revision History: 5/2/2012 Fixed data_wr_end_r logic which didn't hold its state when data_rdy_i was deasserted and 64 | // data_valid was asserted. 65 | // 66 | //***************************************************************************** 67 | 68 | `timescale 1ps/1ps 69 | 70 | module mig_7series_v4_2_wr_data_gen # 71 | 72 | ( 73 | parameter TCQ = 100, 74 | parameter FAMILY = "SPARTAN6", // "SPARTAN6", "VIRTEX6" 75 | parameter MEM_BURST_LEN = 8, 76 | parameter START_ADDR = 32'h00000000, 77 | parameter nCK_PER_CLK = 4, // DRAM clock : MC clock 78 | parameter MEM_TYPE = "DDR3", 79 | 80 | parameter MODE = "WR", //"WR", "RD" 81 | parameter ADDR_WIDTH = 32, 82 | parameter BL_WIDTH = 6, 83 | parameter DWIDTH = 32, 84 | parameter DATA_PATTERN = "DGEN_PRBS", //"DGEN__HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL" 85 | parameter NUM_DQ_PINS = 8, 86 | parameter SEL_VICTIM_LINE = 3, // VICTIM LINE is one of the DQ pins is selected to be different than hammer pattern 87 | 88 | parameter COLUMN_WIDTH = 10, 89 | parameter EYE_TEST = "FALSE" 90 | 91 | ) 92 | ( 93 | input clk_i, // 94 | input [4:0] rst_i, 95 | input [31:0] prbs_fseed_i, 96 | input mode_load_i, 97 | 98 | input [3:0] data_mode_i, // "00" = bram; 99 | input mem_init_done_i, 100 | input wr_data_mask_gen_i, 101 | 102 | output cmd_rdy_o, // ready to receive command. It should assert when data_port is ready at the // beginning and will be deasserted once see the cmd_valid_i is asserted. 103 | // And then it should reasserted when 104 | // it is generating the last_word. 105 | input cmd_valid_i, // when both cmd_valid_i and cmd_rdy_o is high, the command is valid. 106 | input cmd_validB_i, 107 | input cmd_validC_i, 108 | 109 | output last_word_o, 110 | 111 | // input [5:0] port_data_counts_i,// connect to data port fifo counts 112 | // input [ADDR_WIDTH-1:0] m_addr_i, 113 | input [31:0] simple_data0 , 114 | input [31:0] simple_data1 , 115 | input [31:0] simple_data2 , 116 | input [31:0] simple_data3 , 117 | input [31:0] simple_data4 , 118 | input [31:0] simple_data5 , 119 | input [31:0] simple_data6 , 120 | input [31:0] simple_data7 , 121 | 122 | input [31:0] fixed_data_i, 123 | 124 | input [ADDR_WIDTH-1:0] addr_i, // generated address used to determine data pattern. 125 | input [BL_WIDTH-1:0] bl_i, // generated burst length for control the burst data 126 | input memc_cmd_full_i, 127 | 128 | input data_rdy_i, // connect from mcb_wr_full when used as wr_data_gen 129 | // connect from mcb_rd_empty when used as rd_data_gen 130 | // When both data_rdy and data_valid is asserted, the ouput data is valid. 131 | output data_valid_o, // connect to wr_en or rd_en and is asserted whenever the 132 | // pattern is available. 133 | output [NUM_DQ_PINS*nCK_PER_CLK*2-1:0] data_o, // generated data pattern 134 | output data_wr_end_o, 135 | output [(NUM_DQ_PINS*nCK_PER_CLK*2/8) - 1:0] data_mask_o 136 | 137 | 138 | 139 | ); 140 | // 141 | 142 | 143 | reg [DWIDTH-1:0] data; 144 | 145 | 146 | 147 | (*EQUIVALENT_REGISTER_REMOVAL="NO"*) reg cmd_rdy,cmd_rdyB, cmd_rdyC,cmd_rdyD,cmd_rdyE,cmd_rdyF; 148 | (*EQUIVALENT_REGISTER_REMOVAL="NO"*) reg cmd_start,cmd_startB,cmd_startC,cmd_startD,cmd_startE,cmd_startF; 149 | 150 | 151 | 152 | 153 | reg burst_count_reached2; 154 | 155 | reg data_valid; 156 | reg [BL_WIDTH:0]user_burst_cnt; 157 | reg [2:0] walk_cnt; 158 | wire fifo_not_full; 159 | integer i,j; 160 | reg [31:0] w3data; 161 | reg data_wr_end_r; 162 | wire data_wr_end; 163 | wire bram_rd_valid_o; 164 | 165 | function integer logb2; 166 | input [31:0] number; 167 | integer i; 168 | begin 169 | i = number; 170 | for(logb2=1; i>0; logb2=logb2+1) 171 | i = i >> 1; 172 | end 173 | endfunction 174 | 175 | 176 | assign fifo_not_full = data_rdy_i; 177 | 178 | 179 | // data_wr_end_r is used in nCK_PER_CLK == 2; when nCK_PER_CLK = 4, data_wr_end_o == data_valid_o; 180 | 181 | always @(posedge clk_i) 182 | begin 183 | if (~user_burst_cnt[0] && data_valid && data_rdy_i && MEM_BURST_LEN == 8) 184 | data_wr_end_r <= #TCQ 1'b1; 185 | else if (data_rdy_i) // keep the data_wr_end_r asserted if data_rdy_i is deasserted because of mc's write 186 | // data fifo full. 187 | data_wr_end_r <= #TCQ 1'b0; 188 | end 189 | 190 | //assign data_wr_end_o = data_wr_end_r && fifo_not_full; */ 191 | assign data_wr_end_o = (nCK_PER_CLK == 4 || nCK_PER_CLK == 2 && MEM_BURST_LEN == 4) ? data_valid_o :data_wr_end_r ;//(MEM_BURST_LEN == 8) ? user_burst_cnt[0] & data_valid_o : 192 | 193 | assign data_valid_o = data_valid ;//& ~memc_cmd_full_i;// (nCK_PER_CLK == 4)?data_valid_r: data_valid ;//& fifo_not_full; 194 | 195 | //assign data_wr_end_o = data_wr_end_r; 196 | 197 | 198 | always @ (posedge clk_i) 199 | begin 200 | cmd_start <= #TCQ cmd_validC_i & cmd_rdyC ; 201 | cmd_startB <= #TCQ cmd_valid_i & cmd_rdyB; 202 | cmd_startC <= #TCQ cmd_validB_i & cmd_rdyC; 203 | cmd_startD <= #TCQ cmd_validB_i & cmd_rdyD; 204 | cmd_startE <= #TCQ cmd_validB_i & cmd_rdyE; 205 | cmd_startF <= #TCQ cmd_validB_i & cmd_rdyF; 206 | end 207 | 208 | 209 | // counter to count user burst length 210 | // verilint STARC-2.2.3.3 off 211 | always @( posedge clk_i) 212 | begin 213 | if ( rst_i[0] ) 214 | user_burst_cnt <= #TCQ 'd0; 215 | else if(cmd_start) 216 | // if (FAMILY == "SPARTAN6") begin 217 | // SPATAN6 has maximum of burst length of 64. 218 | if (FAMILY == "SPARTAN6" && bl_i[5:0] == 6'b000000) 219 | // user_burst_cnt <= #TCQ 7'b1000000; 220 | begin 221 | user_burst_cnt[6:0] <= #TCQ 7'd64; 222 | user_burst_cnt[BL_WIDTH:7] <= 'b0; 223 | end 224 | else if (FAMILY == "VIRTEX6" && bl_i[BL_WIDTH - 1:0] == {BL_WIDTH {1'b0}}) 225 | user_burst_cnt <= #TCQ {1'b1, {BL_WIDTH{1'b0}}}; 226 | 227 | else 228 | user_burst_cnt <= #TCQ {1'b0,bl_i}; 229 | 230 | // else 231 | // user_burst_cnt <= #TCQ bl_i; 232 | // else if(fifo_not_full && data_valid && ~memc_cmd_full_i) 233 | // verilint STARC-2.2.3.3 on 234 | else if(fifo_not_full && data_valid ) 235 | 236 | if (user_burst_cnt != 6'd0) 237 | user_burst_cnt <= #TCQ user_burst_cnt - 1'b1; 238 | else 239 | user_burst_cnt <=#TCQ 'd0; 240 | 241 | end 242 | 243 | reg u_bcount_2; 244 | wire last_word_t; 245 | always @ (posedge clk_i) 246 | begin 247 | if ((user_burst_cnt == 2 && fifo_not_full )|| (cmd_startC && bl_i == 1)) 248 | u_bcount_2 <= #TCQ 1'b1; 249 | else if (last_word_o) 250 | u_bcount_2 <= #TCQ 1'b0; 251 | end 252 | 253 | 254 | assign last_word_o = u_bcount_2 & fifo_not_full; 255 | 256 | // cmd_rdy_o assert when the dat fifo is not full and deassert once cmd_valid_i 257 | // is assert and reassert during the last data 258 | 259 | assign cmd_rdy_o = cmd_rdy & fifo_not_full; 260 | 261 | 262 | always @( posedge clk_i) 263 | begin 264 | if ( rst_i[0] ) 265 | cmd_rdy <= #TCQ 1'b1; // the state should be '0' for bram_interface during reset. 266 | else if (bram_rd_valid_o) // need work here. 267 | cmd_rdy <= #TCQ 1'b1; 268 | 269 | else if (cmd_start) 270 | if (bl_i == 1) 271 | cmd_rdy <= #TCQ 1'b1; 272 | else 273 | cmd_rdy <= #TCQ 1'b0; 274 | else if ((user_burst_cnt == 6'd2 && fifo_not_full ) ) 275 | 276 | cmd_rdy <= #TCQ bram_rd_valid_o;//1'b1; 277 | 278 | 279 | end 280 | 281 | always @( posedge clk_i) 282 | begin 283 | if ( rst_i [0]) 284 | cmd_rdyB <= #TCQ 1'b1; 285 | else if (cmd_startB) 286 | if (bl_i == 1) 287 | cmd_rdyB <= #TCQ 1'b1; 288 | else 289 | cmd_rdyB <= #TCQ 1'b0; 290 | else if ((user_burst_cnt == 6'd2 && fifo_not_full ) ) 291 | 292 | 293 | cmd_rdyB <= #TCQ 1'b1; 294 | 295 | 296 | end 297 | 298 | always @( posedge clk_i) 299 | begin 300 | if ( rst_i[0] ) 301 | cmd_rdyC <= #TCQ 1'b1; 302 | else if (cmd_startC) 303 | if (bl_i == 1) 304 | cmd_rdyC <= #TCQ 1'b1; 305 | else 306 | cmd_rdyC <= #TCQ 1'b0; 307 | else if ((user_burst_cnt == 6'd2 && fifo_not_full ) ) 308 | 309 | 310 | cmd_rdyC <= #TCQ 1'b1; 311 | 312 | 313 | end 314 | 315 | always @( posedge clk_i) 316 | begin 317 | if ( rst_i[0] ) 318 | cmd_rdyD <= #TCQ 1'b1; 319 | else if (cmd_startD) 320 | if (bl_i == 1) 321 | cmd_rdyD <= #TCQ 1'b1; 322 | else 323 | cmd_rdyD <= #TCQ 1'b0; 324 | else if ((user_burst_cnt == 6'd2 && fifo_not_full ) ) 325 | 326 | 327 | cmd_rdyD <= #TCQ 1'b1; 328 | 329 | 330 | end 331 | 332 | always @( posedge clk_i) 333 | begin 334 | if ( rst_i[0] ) 335 | cmd_rdyE <= #TCQ 1'b1; 336 | else if (cmd_startE) 337 | if (bl_i == 1) 338 | cmd_rdyE <= #TCQ 1'b1; 339 | else 340 | cmd_rdyE <= #TCQ 1'b0; 341 | else if ((user_burst_cnt == 6'd2 && fifo_not_full ) ) 342 | 343 | 344 | cmd_rdyE <= #TCQ 1'b1; 345 | 346 | 347 | end 348 | 349 | 350 | 351 | always @( posedge clk_i) 352 | begin 353 | if ( rst_i[0] ) 354 | cmd_rdyF <= #TCQ 1'b1; 355 | else if (cmd_startF) 356 | if (bl_i == 1) 357 | cmd_rdyF <= #TCQ 1'b1; 358 | else 359 | cmd_rdyF <= #TCQ 1'b0; 360 | else if ((user_burst_cnt == 6'd2 && fifo_not_full ) ) 361 | 362 | cmd_rdyF <= #TCQ 1'b1; 363 | 364 | 365 | end 366 | 367 | 368 | reg dvalid; 369 | 370 | always @ (posedge clk_i) 371 | begin 372 | if (rst_i[1]) 373 | data_valid <= #TCQ 'd0; 374 | else if(cmd_start) 375 | data_valid <= #TCQ 1'b1; 376 | else if (fifo_not_full && user_burst_cnt <= 6'd1) 377 | data_valid <= #TCQ 1'b0; 378 | 379 | // data_valid <= dvalid ; 380 | end 381 | 382 | mig_7series_v4_2_s7ven_data_gen # 383 | ( 384 | .TCQ (TCQ), 385 | .ADDR_WIDTH (32 ), 386 | .FAMILY (FAMILY), 387 | .MEM_TYPE (MEM_TYPE), 388 | .BL_WIDTH (BL_WIDTH), 389 | .DWIDTH (DWIDTH), 390 | .MEM_BURST_LEN (MEM_BURST_LEN), 391 | .nCK_PER_CLK (nCK_PER_CLK), 392 | .START_ADDR (START_ADDR), 393 | .DATA_PATTERN (DATA_PATTERN), 394 | .NUM_DQ_PINS (NUM_DQ_PINS), 395 | .SEL_VICTIM_LINE (SEL_VICTIM_LINE), 396 | .COLUMN_WIDTH (COLUMN_WIDTH), 397 | .EYE_TEST (EYE_TEST) 398 | ) 399 | s7ven_data_gen 400 | ( 401 | .clk_i (clk_i ), 402 | .rst_i (rst_i[1] ), 403 | .data_rdy_i (data_rdy_i ), 404 | .prbs_fseed_i (prbs_fseed_i), 405 | .mem_init_done_i (mem_init_done_i), 406 | .mode_load_i (mode_load_i), 407 | .wr_data_mask_gen_i (wr_data_mask_gen_i), 408 | .data_mode_i (data_mode_i ), 409 | .cmd_startA (cmd_start ), 410 | .cmd_startB (cmd_startB ), 411 | .cmd_startC (cmd_startC ), 412 | .cmd_startD (cmd_startD ), 413 | .cmd_startE (cmd_startE ), 414 | .m_addr_i (addr_i ), 415 | .fixed_data_i (fixed_data_i), 416 | .simple_data0 (simple_data0), 417 | .simple_data1 (simple_data1), 418 | .simple_data2 (simple_data2), 419 | .simple_data3 (simple_data3), 420 | .simple_data4 (simple_data4), 421 | .simple_data5 (simple_data5), 422 | .simple_data6 (simple_data6), 423 | .simple_data7 (simple_data7), 424 | .addr_i (addr_i ), 425 | .user_burst_cnt (user_burst_cnt), 426 | .fifo_rdy_i (fifo_not_full ), 427 | .data_o (data_o ), 428 | .data_mask_o (data_mask_o), 429 | .bram_rd_valid_o (bram_rd_valid_o), 430 | .tg_st_addr_o () 431 | ); 432 | 433 | endmodule 434 | -------------------------------------------------------------------------------- /mig_example.xpr: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 59 | 60 | 61 | 62 | 63 | 64 | 65 | 66 | 67 | 68 | 69 | 70 | 71 | 72 | 73 | 74 | 75 | 76 | 77 | 78 | 79 | 80 | 81 | 82 | 83 | 84 | 85 | 86 | 87 | 88 | 89 | 90 | 91 | 92 | 93 | 94 | 95 | 96 | 97 | 98 | 99 | 100 | 101 | 102 | 103 | 104 | 105 | 106 | 107 | 108 | 109 | 110 | 111 | 112 | 113 | 114 | 115 | 116 | 117 | 118 | 119 | 120 | 121 | 122 | 126 | 127 | 128 | 129 | 130 | 131 | 132 | 133 | 134 | 135 | 136 | 139 | 140 | 141 | 142 | 143 | 150 | 151 | 152 | 153 | 154 | 156 | 157 | 158 | 159 | 160 | 161 | 162 | 163 | 164 | 165 | 166 | 169 | 170 | 171 | 172 | 173 | 174 | 175 | 176 | 177 | 178 | 179 | 180 | 181 | 182 | 183 | 184 | 185 | 186 | 189 | 190 | 191 | 192 | 193 | 196 | 197 | 199 | 200 | 202 | 203 | 205 | 206 | 208 | 209 | 211 | 212 | 214 | 215 | 216 | 217 | 218 | 219 | 220 | 221 | 222 | 223 | 224 | 225 | 226 | 227 | 228 | 229 | 230 | 231 | 232 | 233 | 234 | 235 | 236 | 237 | 238 | 239 | 240 | 241 | 242 | 243 | 244 | 245 | 246 | 247 | 248 | 249 | 250 | 251 | 252 | 253 | 254 | 255 | 256 | 257 | 258 | 259 | 260 | 261 | 262 | 263 | 264 | 265 | 266 | 267 | 268 | 269 | 270 | 271 | 272 | 273 | 274 | 275 | 276 | 277 | 278 | 279 | 280 | 281 | 282 | 283 | 284 | 285 | 286 | 287 | 288 | 289 | 290 | 291 | 292 | 293 | 294 | 295 | 296 | 297 | 298 | 299 | 300 | 301 | 302 | 303 | 304 | 305 | 306 | 307 | 308 | 309 | 310 | 311 | 312 | 313 | 314 | 315 | 316 | default_dashboard 317 | 318 | 319 | 320 | 321 | 322 | 323 | -------------------------------------------------------------------------------- /mig_example.srcs/sources_1/ip/mig/mig_xmdf.tcl: -------------------------------------------------------------------------------- 1 | # The package naming convention is _xmdf 2 | package provide mig_xmdf 1.0 3 | 4 | # This includes some utilities that support common XMDF operations 5 | package require utilities_xmdf 6 | 7 | # Define a namespace for this package. The name of the name space 8 | # is _xmdf 9 | namespace eval ::mig_xmdf { 10 | # Use this to define any statics 11 | } 12 | 13 | # Function called by client to rebuild the params and port arrays 14 | # Optional when the use context does not require the param or ports 15 | # arrays to be available. 16 | proc ::mig_xmdf::xmdfInit { instance } { 17 | # Variable containing name of library into which module is compiled 18 | # Recommendation: 19 | # Required 20 | utilities_xmdf::xmdfSetData $instance Module Attributes Name mig 21 | } 22 | # ::mig_xmdf::xmdfInit 23 | 24 | # Function called by client to fill in all the xmdf* data variables 25 | # based on the current settings of the parameters 26 | proc ::mig_xmdf::xmdfApplyParams { instance } { 27 | 28 | set fcount 0 29 | # Array containing libraries that are assumed to exist 30 | # Examples include unisim and xilinxcorelib 31 | # Optional 32 | # In this example, we assume that the unisim library will 33 | # be magically 34 | # available to the simulation and synthesis tool 35 | utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library 36 | utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim 37 | incr fcount 38 | 39 | utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path mig/user_design/rtl/clocking/mig_7series_v4_2_clk_ibuf.v 40 | utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog 41 | incr fcount 42 | 43 | utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path mig/user_design/rtl/clocking/mig_7series_v4_2_infrastructure.v 44 | utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog 45 | incr fcount 46 | 47 | utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path mig/user_design/rtl/clocking/mig_7series_v4_2_iodelay_ctrl.v 48 | utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog 49 | incr fcount 50 | 51 | utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path mig/user_design/rtl/clocking/mig_7series_v4_2_tempmon.v 52 | utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog 53 | incr fcount 54 | 55 | utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path mig/user_design/rtl/controller/mig_7series_v4_2_arb_mux.v 56 | utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog 57 | incr fcount 58 | 59 | utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path mig/user_design/rtl/controller/mig_7series_v4_2_arb_row_col.v 60 | utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog 61 | incr fcount 62 | 63 | utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path mig/user_design/rtl/controller/mig_7series_v4_2_arb_select.v 64 | utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog 65 | incr fcount 66 | 67 | utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path mig/user_design/rtl/controller/mig_7series_v4_2_bank_cntrl.v 68 | utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog 69 | incr fcount 70 | 71 | utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path mig/user_design/rtl/controller/mig_7series_v4_2_bank_common.v 72 | utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog 73 | incr fcount 74 | 75 | utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path mig/user_design/rtl/controller/mig_7series_v4_2_bank_compare.v 76 | utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog 77 | incr fcount 78 | 79 | utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path mig/user_design/rtl/controller/mig_7series_v4_2_bank_mach.v 80 | utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog 81 | incr fcount 82 | 83 | utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path mig/user_design/rtl/controller/mig_7series_v4_2_bank_queue.v 84 | utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog 85 | incr fcount 86 | 87 | utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path mig/user_design/rtl/controller/mig_7series_v4_2_bank_state.v 88 | utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog 89 | incr fcount 90 | 91 | utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path mig/user_design/rtl/controller/mig_7series_v4_2_col_mach.v 92 | utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog 93 | incr fcount 94 | 95 | utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path mig/user_design/rtl/controller/mig_7series_v4_2_mc.v 96 | utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog 97 | incr fcount 98 | 99 | utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path mig/user_design/rtl/controller/mig_7series_v4_2_rank_cntrl.v 100 | utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog 101 | incr fcount 102 | 103 | utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path mig/user_design/rtl/controller/mig_7series_v4_2_rank_common.v 104 | utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog 105 | incr fcount 106 | 107 | utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path mig/user_design/rtl/controller/mig_7series_v4_2_rank_mach.v 108 | utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog 109 | incr fcount 110 | 111 | utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path mig/user_design/rtl/controller/mig_7series_v4_2_round_robin_arb.v 112 | utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog 113 | incr fcount 114 | 115 | utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path mig/user_design/rtl/ecc/mig_7series_v4_2_ecc_buf.v 116 | utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog 117 | incr fcount 118 | 119 | utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path mig/user_design/rtl/ecc/mig_7series_v4_2_ecc_dec_fix.v 120 | utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog 121 | incr fcount 122 | 123 | utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path mig/user_design/rtl/ecc/mig_7series_v4_2_ecc_gen.v 124 | utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog 125 | incr fcount 126 | 127 | utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path mig/user_design/rtl/ecc/mig_7series_v4_2_ecc_merge_enc.v 128 | utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog 129 | incr fcount 130 | 131 | utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path mig/user_design/rtl/ecc/mig_7series_v4_2_fi_xor.v 132 | utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog 133 | incr fcount 134 | 135 | utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path mig/user_design/rtl/ip_top/mig_7series_v4_2_mem_intfc.v 136 | utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog 137 | incr fcount 138 | 139 | utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path mig/user_design/rtl/ip_top/mig_7series_v4_2_memc_ui_top_std.v 140 | utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog 141 | incr fcount 142 | 143 | utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path mig/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v 144 | utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog 145 | incr fcount 146 | 147 | utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path mig/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v 148 | utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog 149 | incr fcount 150 | 151 | utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path mig/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_tempmon.v 152 | utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog 153 | incr fcount 154 | 155 | utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path mig/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v 156 | utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog 157 | incr fcount 158 | 159 | utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path mig/user_design/rtl/phy/mig_7series_v4_2_ddr_if_post_fifo.v 160 | utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog 161 | incr fcount 162 | 163 | utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path mig/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy.v 164 | utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog 165 | incr fcount 166 | 167 | utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path mig/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v 168 | utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog 169 | incr fcount 170 | 171 | utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path mig/user_design/rtl/phy/mig_7series_v4_2_ddr_of_pre_fifo.v 172 | utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog 173 | incr fcount 174 | 175 | utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path mig/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_4lanes.v 176 | utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog 177 | incr fcount 178 | 179 | utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path mig/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v 180 | utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog 181 | incr fcount 182 | 183 | utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path mig/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_dqs_found_cal.v 184 | utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog 185 | incr fcount 186 | 187 | utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path mig/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_dqs_found_cal_hr.v 188 | utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog 189 | incr fcount 190 | 191 | utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path mig/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_oclkdelay_cal.v 192 | utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog 193 | incr fcount 194 | 195 | utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path mig/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_prbs_rdlvl.v 196 | utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog 197 | incr fcount 198 | 199 | utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path mig/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v 200 | utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog 201 | incr fcount 202 | 203 | utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path mig/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_top.v 204 | utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog 205 | incr fcount 206 | 207 | utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path mig/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrcal.v 208 | utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog 209 | incr fcount 210 | 211 | utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path mig/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrlvl_off_delay.v 212 | utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog 213 | incr fcount 214 | 215 | utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path mig/user_design/rtl/phy/mig_7series_v4_2_ddr_prbs_gen.v 216 | utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog 217 | incr fcount 218 | 219 | utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path mig/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ck_addr_cmd_delay.v 220 | utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog 221 | incr fcount 222 | 223 | utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path mig/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrlvl.v 224 | utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog 225 | incr fcount 226 | 227 | utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path mig/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ocd_lim.v 228 | utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog 229 | incr fcount 230 | 231 | utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path mig/user_design/rtl/phy/mig_7series_v4_2_poc_top.v 232 | utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog 233 | incr fcount 234 | 235 | utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path mig/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ocd_mux.v 236 | utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog 237 | incr fcount 238 | 239 | utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path mig/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ocd_data.v 240 | utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog 241 | incr fcount 242 | 243 | utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path mig/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ocd_samp.v 244 | utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog 245 | incr fcount 246 | 247 | utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path mig/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ocd_edge.v 248 | utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog 249 | incr fcount 250 | 251 | utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path mig/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ocd_cntlr.v 252 | utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog 253 | incr fcount 254 | 255 | utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path mig/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ocd_po_cntlr.v 256 | utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog 257 | incr fcount 258 | 259 | utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path mig/user_design/rtl/phy/mig_7series_v4_2_poc_pd.v 260 | utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog 261 | incr fcount 262 | 263 | utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path mig/user_design/rtl/phy/mig_7series_v4_2_poc_tap_base.v 264 | utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog 265 | incr fcount 266 | 267 | utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path mig/user_design/rtl/phy/mig_7series_v4_2_poc_meta.v 268 | utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog 269 | incr fcount 270 | 271 | utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path mig/user_design/rtl/phy/mig_7series_v4_2_poc_edge_store.v 272 | utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog 273 | incr fcount 274 | 275 | utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path mig/user_design/rtl/phy/mig_7series_v4_2_poc_cc.v 276 | utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog 277 | incr fcount 278 | 279 | utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path mig/user_design/rtl/ui/mig_7series_v4_2_ui_cmd.v 280 | utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog 281 | incr fcount 282 | 283 | utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path mig/user_design/rtl/ui/mig_7series_v4_2_ui_rd_data.v 284 | utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog 285 | incr fcount 286 | 287 | utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path mig/user_design/rtl/ui/mig_7series_v4_2_ui_top.v 288 | utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog 289 | incr fcount 290 | 291 | utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path mig/user_design/rtl/ui/mig_7series_v4_2_ui_wr_data.v 292 | utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog 293 | incr fcount 294 | 295 | utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path mig/user_design/rtl/mig_mig.v 296 | utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog 297 | incr fcount 298 | 299 | utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path mig/user_design/rtl/mig.v 300 | utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog 301 | incr fcount 302 | 303 | utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path mig/user_design/constraints/mig.ucf 304 | utilities_xmdf::xmdfSetData $instance FileSet $fcount type ucf 305 | utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module mig 306 | incr fcount 307 | 308 | utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path mig/user_design/constraints/mig.xdc 309 | utilities_xmdf::xmdfSetData $instance FileSet $fcount type xdc 310 | utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module mig 311 | incr fcount 312 | 313 | } 314 | 315 | # ::gen_comp_name_xmdf::xmdfApplyParams 316 | --------------------------------------------------------------------------------