├── e-clock.zip ├── e-clock ├── 100f.bdf ├── 100f.bsf ├── 12-24.bdf ├── 12-24.bsf ├── 2c1.bdf ├── 2c1.bsf ├── 3c1.bdf ├── 3c1.bsf ├── 74.bdf ├── 74.bsf ├── 7447pro.bdf ├── 7447pro.bsf ├── 7448pro.bdf ├── 7448pro.bsf ├── ANDpro.bdf ├── ANDpro.bsf ├── CLOCK.bdf ├── LEDpro.bdf ├── LEDpro.bsf ├── LSD.bdf ├── LSD.dpf ├── LSD.qsf ├── LSD.qws ├── LSD_nativelink_simulation.rpt ├── but.bdf ├── but.bsf ├── but.vwf ├── butpro.bdf ├── butpro.bsf ├── clk_100.bdf ├── clk_100.bsf ├── clk_1k.bdf ├── clk_1k.bsf ├── clk_2.bdf ├── clk_2.bsf ├── clk_25.bdf ├── clk_25.bsf ├── clk_5k.bdf ├── clk_5k.bsf ├── clock.vwf ├── clock24.bdf ├── cnt-100.bdf ├── cnt-100.bsf ├── cnt-2.bdf ├── cnt-2.bsf ├── cnt-25.bdf ├── cnt-25.bsf ├── cnt100plus.bdf ├── cnt100plus.bsf ├── cnt100plus.vwf ├── db │ ├── .cmp.kpt │ ├── LSD.(0).cnf.cdb │ ├── LSD.(0).cnf.hdb │ ├── LSD.(1).cnf.cdb │ ├── LSD.(1).cnf.hdb │ ├── LSD.(10).cnf.cdb │ ├── LSD.(10).cnf.hdb │ ├── LSD.(11).cnf.cdb │ ├── LSD.(11).cnf.hdb │ ├── LSD.(12).cnf.cdb │ ├── LSD.(12).cnf.hdb │ ├── LSD.(13).cnf.cdb │ ├── LSD.(13).cnf.hdb │ ├── LSD.(14).cnf.cdb │ ├── LSD.(14).cnf.hdb │ ├── LSD.(15).cnf.cdb │ ├── LSD.(15).cnf.hdb │ ├── LSD.(16).cnf.cdb │ ├── LSD.(16).cnf.hdb │ ├── LSD.(17).cnf.cdb │ ├── LSD.(17).cnf.hdb │ ├── LSD.(18).cnf.cdb │ ├── LSD.(18).cnf.hdb │ ├── LSD.(19).cnf.cdb │ ├── LSD.(19).cnf.hdb │ ├── LSD.(2).cnf.cdb │ ├── LSD.(2).cnf.hdb │ ├── LSD.(20).cnf.cdb │ ├── LSD.(20).cnf.hdb │ ├── LSD.(21).cnf.cdb │ ├── LSD.(21).cnf.hdb │ ├── LSD.(22).cnf.cdb │ ├── LSD.(22).cnf.hdb │ ├── LSD.(23).cnf.cdb │ ├── LSD.(23).cnf.hdb │ ├── LSD.(24).cnf.cdb │ ├── LSD.(24).cnf.hdb │ ├── LSD.(25).cnf.cdb │ ├── LSD.(25).cnf.hdb │ ├── LSD.(26).cnf.cdb │ ├── LSD.(26).cnf.hdb │ ├── LSD.(27).cnf.cdb │ ├── LSD.(27).cnf.hdb │ ├── LSD.(28).cnf.cdb │ ├── LSD.(28).cnf.hdb │ ├── LSD.(29).cnf.cdb │ ├── LSD.(29).cnf.hdb │ ├── LSD.(3).cnf.cdb │ ├── LSD.(3).cnf.hdb │ ├── LSD.(30).cnf.cdb │ ├── LSD.(30).cnf.hdb │ ├── LSD.(31).cnf.cdb │ ├── LSD.(31).cnf.hdb │ ├── LSD.(32).cnf.cdb │ ├── LSD.(32).cnf.hdb │ ├── LSD.(33).cnf.cdb │ ├── LSD.(33).cnf.hdb │ ├── LSD.(34).cnf.cdb │ ├── LSD.(34).cnf.hdb │ ├── LSD.(35).cnf.cdb │ ├── LSD.(35).cnf.hdb │ ├── LSD.(36).cnf.cdb │ ├── LSD.(36).cnf.hdb │ ├── LSD.(37).cnf.cdb │ ├── LSD.(37).cnf.hdb │ ├── LSD.(38).cnf.cdb │ ├── LSD.(38).cnf.hdb │ ├── LSD.(4).cnf.cdb │ ├── LSD.(4).cnf.hdb │ ├── LSD.(5).cnf.cdb │ ├── LSD.(5).cnf.hdb │ ├── LSD.(6).cnf.cdb │ ├── LSD.(6).cnf.hdb │ ├── LSD.(7).cnf.cdb │ ├── LSD.(7).cnf.hdb │ ├── LSD.(8).cnf.cdb │ ├── LSD.(8).cnf.hdb │ ├── LSD.(9).cnf.cdb │ ├── LSD.(9).cnf.hdb │ ├── LSD.ace_cmp.bpm │ ├── LSD.ace_cmp.cdb │ ├── LSD.ace_cmp.hdb │ ├── LSD.asm.qmsg │ ├── LSD.asm.rdb │ ├── LSD.asm_labs.ddb │ ├── LSD.cbx.xml │ ├── LSD.cmp.bpm │ ├── LSD.cmp.cdb │ ├── LSD.cmp.hdb │ ├── LSD.cmp.idb │ ├── LSD.cmp.logdb │ ├── LSD.cmp.rdb │ ├── LSD.cmp_merge.kpt │ ├── LSD.cycloneive_io_sim_cache.45um_ff_1200mv_0c_fast.hsd │ ├── LSD.cycloneive_io_sim_cache.45um_ss_1200mv_0c_slow.hsd │ ├── LSD.cycloneive_io_sim_cache.45um_ss_1200mv_85c_slow.hsd │ ├── LSD.db_info │ ├── LSD.eco.cdb │ ├── LSD.eda.qmsg │ ├── LSD.fit.qmsg │ ├── LSD.hier_info │ ├── LSD.hif │ ├── LSD.ipinfo │ ├── LSD.lpc.html │ ├── LSD.lpc.rdb │ ├── LSD.lpc.txt │ ├── LSD.map.ammdb │ ├── LSD.map.bpm │ ├── LSD.map.cdb │ ├── LSD.map.hdb │ ├── LSD.map.kpt │ ├── LSD.map.logdb │ ├── LSD.map.qmsg │ ├── LSD.map.rdb │ ├── LSD.map_bb.cdb │ ├── LSD.map_bb.hdb │ ├── LSD.map_bb.logdb │ ├── LSD.pplq.rdb │ ├── LSD.pre_map.hdb │ ├── LSD.pti_db_list.ddb │ ├── LSD.root_partition.map.reg_db.cdb │ ├── LSD.routing.rdb │ ├── LSD.rtlv.hdb │ ├── LSD.rtlv_sg.cdb │ ├── LSD.rtlv_sg_swap.cdb │ ├── LSD.sgdiff.cdb │ ├── LSD.sgdiff.hdb │ ├── LSD.sld_design_entry.sci │ ├── LSD.sld_design_entry_dsc.sci │ ├── LSD.smart_action.txt │ ├── LSD.sta.qmsg │ ├── LSD.sta.rdb │ ├── LSD.sta_cmp.8_slow_1200mv_85c.tdb │ ├── LSD.tis_db_list.ddb │ ├── LSD.tiscmp.fast_1200mv_0c.ddb │ ├── LSD.tiscmp.fastest_slow_1200mv_0c.ddb │ ├── LSD.tiscmp.fastest_slow_1200mv_85c.ddb │ ├── LSD.tiscmp.slow_1200mv_0c.ddb │ ├── LSD.tiscmp.slow_1200mv_85c.ddb │ ├── LSD.tmw_info │ ├── LSD.vpr.ammdb │ ├── e-clock.map_bb.logdb │ ├── logic_util_heursitic.dat │ └── prev_cmp_LSD.qmsg ├── e-clock.qpf ├── hour.bdf ├── hour.bsf ├── hour.vwf ├── hour12.bdf ├── hour12.bsf ├── hour12.vwf ├── hour24.bsf ├── incremental_db │ ├── README │ └── compiled_partitions │ │ ├── LSD.db_info │ │ ├── LSD.root_partition.cmp.ammdb │ │ ├── LSD.root_partition.cmp.cdb │ │ ├── LSD.root_partition.cmp.dfp │ │ ├── LSD.root_partition.cmp.hdb │ │ ├── LSD.root_partition.cmp.logdb │ │ ├── LSD.root_partition.cmp.rcfdb │ │ ├── LSD.root_partition.map.cdb │ │ ├── LSD.root_partition.map.dpi │ │ ├── LSD.root_partition.map.hbdb.cdb │ │ ├── LSD.root_partition.map.hbdb.hb_info │ │ ├── LSD.root_partition.map.hbdb.hdb │ │ ├── LSD.root_partition.map.hbdb.sig │ │ ├── LSD.root_partition.map.hdb │ │ └── LSD.root_partition.map.kpt ├── kzdl.bdf ├── kzdl.bsf ├── kzdl.vwf ├── min.bdf ├── min.bsf ├── min.vwf ├── mxh.bdf ├── mxh.bsf ├── output_files │ ├── LSD.asm.rpt │ ├── LSD.cdf │ ├── LSD.done │ ├── LSD.eda.rpt │ ├── LSD.fit.rpt │ ├── LSD.fit.smsg │ ├── LSD.fit.summary │ ├── LSD.flow.rpt │ ├── LSD.jdi │ ├── LSD.map.rpt │ ├── LSD.map.summary │ ├── LSD.pin │ ├── LSD.sof │ ├── LSD.sta.rpt │ └── LSD.sta.summary ├── sec.bdf ├── sec.bsf ├── sec.vwf ├── simulation │ └── qsim │ │ ├── 100.vwf.vt │ │ ├── 100f.vwf.vt │ │ ├── LSD.do │ │ ├── LSD.msim.vcd │ │ ├── LSD.sft │ │ ├── LSD.sim.vwf │ │ ├── LSD.vo │ │ ├── LSD_8_1200mv_0c_slow.vo │ │ ├── LSD_8_1200mv_0c_v_slow.sdo │ │ ├── LSD_8_1200mv_85c_slow.vo │ │ ├── LSD_8_1200mv_85c_v_slow.sdo │ │ ├── LSD_min_1200mv_0c_fast.vo │ │ ├── LSD_min_1200mv_0c_v_fast.sdo │ │ ├── LSD_modelsim.xrf │ │ ├── LSD_v.sdo │ │ ├── but.vwf.vt │ │ ├── clock.vwf.vt │ │ ├── cnt100plus.vwf.vt │ │ ├── hour.vwf.vt │ │ ├── hour12.vwf.vt │ │ ├── kzdl.vwf.vt │ │ ├── min.vwf.vt │ │ ├── modelsim.ini │ │ ├── sec.vwf.vt │ │ ├── switch.vwf.vt │ │ ├── transcript │ │ ├── verilog_libs │ │ ├── altera_lnsim_ver │ │ │ ├── _info │ │ │ ├── _lib.qdb │ │ │ ├── _lib1_3.qdb │ │ │ ├── _lib1_3.qpg │ │ │ ├── _lib1_3.qtl │ │ │ └── _vmake │ │ ├── altera_mf_ver │ │ │ ├── _info │ │ │ ├── _lib.qdb │ │ │ ├── _lib1_3.qdb │ │ │ ├── _lib1_3.qpg │ │ │ ├── _lib1_3.qtl │ │ │ └── _vmake │ │ ├── altera_ver │ │ │ ├── _info │ │ │ ├── _lib.qdb │ │ │ ├── _lib1_1.qdb │ │ │ ├── _lib1_1.qpg │ │ │ ├── _lib1_1.qtl │ │ │ └── _vmake │ │ ├── cycloneive_ver │ │ │ ├── _info │ │ │ ├── _lib.qdb │ │ │ ├── _lib1_3.qdb │ │ │ ├── _lib1_3.qpg │ │ │ ├── _lib1_3.qtl │ │ │ └── _vmake │ │ ├── lpm_ver │ │ │ ├── _info │ │ │ ├── _lib.qdb │ │ │ ├── _lib1_1.qdb │ │ │ ├── _lib1_1.qpg │ │ │ ├── _lib1_1.qtl │ │ │ └── _vmake │ │ └── sgate_ver │ │ │ ├── _info │ │ │ ├── _lib.qdb │ │ │ ├── _lib1_1.qdb │ │ │ ├── _lib1_1.qpg │ │ │ ├── _lib1_1.qtl │ │ │ └── _vmake │ │ └── work │ │ ├── _info │ │ ├── _lib.qdb │ │ ├── _lib1_16.qdb │ │ ├── _lib1_16.qpg │ │ ├── _lib1_16.qtl │ │ └── _vmake ├── switch.bdf ├── switch.bsf ├── switch.vwf └── switch_pro.bdf ├── md_pic ├── wps1.png ├── wps10.jpg ├── wps11.jpg ├── wps12.jpg ├── wps13.jpg ├── wps14.jpg ├── wps15.jpg ├── wps16.jpg ├── wps17.jpg ├── wps18.jpg ├── wps19.jpg ├── wps2.png ├── wps20.jpg ├── wps21.jpg ├── wps22.jpg ├── wps23.jpg ├── wps24.jpg ├── wps25.jpg ├── wps26.jpg ├── wps27.jpg ├── wps28.jpg ├── wps29.jpg ├── wps3.jpg ├── wps30.jpg ├── wps31.jpg ├── wps32.jpg ├── wps33.jpg ├── wps34.jpg ├── wps35.jpg ├── wps36.jpg ├── wps37.jpg ├── wps38.jpg ├── wps39.jpg ├── wps4.jpg ├── wps40.jpg ├── wps5.jpg ├── wps6.jpg ├── wps7.jpg ├── wps8.jpg └── wps9.jpg ├── readme.md └── 数电综设实验报告.pdf /e-clock.zip: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CodeAlanqian/e-clock/ac6929bfe0df785b47a94b848983913f0d3df45b/e-clock.zip -------------------------------------------------------------------------------- /e-clock/100f.bsf: -------------------------------------------------------------------------------- 1 | /* 2 | WARNING: Do NOT edit the input and output ports in this file in a text 3 | editor if you plan to continue editing the block that represents it in 4 | the Block Editor! File corruption is VERY likely to occur. 5 | */ 6 | /* 7 | Copyright (C) 1991-2013 Altera Corporation 8 | Your use of Altera Corporation's design tools, logic functions 9 | and other software and tools, and its AMPP partner logic 10 | functions, and any output files from any of the foregoing 11 | (including device programming or simulation files), and any 12 | associated documentation or information are expressly subject 13 | to the terms and conditions of the Altera Program License 14 | Subscription Agreement, Altera MegaCore Function License 15 | Agreement, or other applicable license agreement, including, 16 | without limitation, that your use is for the sole purpose of 17 | programming logic devices manufactured by Altera and sold by 18 | Altera or its authorized distributors. Please refer to the 19 | applicable agreement for further details. 20 | */ 21 | (header "symbol" (version "1.2")) 22 | (symbol 23 | (rect 16 16 160 112) 24 | (text "100f" (rect 5 0 30 14)(font "Arial" (font_size 8))) 25 | (text "inst" (rect 8 80 25 92)(font "Arial" )) 26 | (port 27 | (pt 0 32) 28 | (input) 29 | (text "clk_100Hz" (rect 0 0 50 12)(font "Arial" )) 30 | (text "clk_100Hz" (rect 21 27 71 39)(font "Arial" )) 31 | (line (pt 0 32)(pt 16 32)) 32 | ) 33 | (port 34 | (pt 0 48) 35 | (input) 36 | (text "RD" (rect 0 0 16 12)(font "Arial" )) 37 | (text "RD" (rect 21 43 37 55)(font "Arial" )) 38 | (line (pt 0 48)(pt 16 48)) 39 | ) 40 | (port 41 | (pt 144 32) 42 | (output) 43 | (text "SL[3..0]" (rect 0 0 38 12)(font "Arial" )) 44 | (text "SL[3..0]" (rect 85 27 123 39)(font "Arial" )) 45 | (line (pt 144 32)(pt 128 32)(line_width 3)) 46 | ) 47 | (port 48 | (pt 144 48) 49 | (output) 50 | (text "SH[3..0]" (rect 0 0 41 12)(font "Arial" )) 51 | (text "SH[3..0]" (rect 82 43 123 55)(font "Arial" )) 52 | (line (pt 144 48)(pt 128 48)(line_width 3)) 53 | ) 54 | (port 55 | (pt 144 64) 56 | (output) 57 | (text "SC" (rect 0 0 15 12)(font "Arial" )) 58 | (text "SC" (rect 108 59 123 71)(font "Arial" )) 59 | (line (pt 144 64)(pt 128 64)) 60 | ) 61 | (drawing 62 | (rectangle (rect 16 16 128 80)) 63 | ) 64 | ) 65 | -------------------------------------------------------------------------------- /e-clock/12-24.bsf: -------------------------------------------------------------------------------- 1 | /* 2 | WARNING: Do NOT edit the input and output ports in this file in a text 3 | editor if you plan to continue editing the block that represents it in 4 | the Block Editor! File corruption is VERY likely to occur. 5 | */ 6 | /* 7 | Copyright (C) 1991-2013 Altera Corporation 8 | Your use of Altera Corporation's design tools, logic functions 9 | and other software and tools, and its AMPP partner logic 10 | functions, and any output files from any of the foregoing 11 | (including device programming or simulation files), and any 12 | associated documentation or information are expressly subject 13 | to the terms and conditions of the Altera Program License 14 | Subscription Agreement, Altera MegaCore Function License 15 | Agreement, or other applicable license agreement, including, 16 | without limitation, that your use is for the sole purpose of 17 | programming logic devices manufactured by Altera and sold by 18 | Altera or its authorized distributors. Please refer to the 19 | applicable agreement for further details. 20 | */ 21 | (header "symbol" (version "1.2")) 22 | (symbol 23 | (rect 16 16 152 112) 24 | (text "12-24" (rect 5 0 38 14)(font "Arial" (font_size 8))) 25 | (text "inst" (rect 8 80 25 92)(font "Arial" )) 26 | (port 27 | (pt 0 32) 28 | (input) 29 | (text "K" (rect 0 0 7 12)(font "Arial" )) 30 | (text "K" (rect 21 27 28 39)(font "Arial" )) 31 | (line (pt 0 32)(pt 16 32)) 32 | ) 33 | (port 34 | (pt 0 48) 35 | (input) 36 | (text "H24[3..0]" (rect 0 0 46 12)(font "Arial" )) 37 | (text "H24[3..0]" (rect 21 43 67 55)(font "Arial" )) 38 | (line (pt 0 48)(pt 16 48)(line_width 3)) 39 | ) 40 | (port 41 | (pt 0 64) 42 | (input) 43 | (text "H12[3..0]" (rect 0 0 46 12)(font "Arial" )) 44 | (text "H12[3..0]" (rect 21 59 67 71)(font "Arial" )) 45 | (line (pt 0 64)(pt 16 64)(line_width 3)) 46 | ) 47 | (port 48 | (pt 136 32) 49 | (output) 50 | (text "R[3..0]" (rect 0 0 34 12)(font "Arial" )) 51 | (text "R[3..0]" (rect 81 27 115 39)(font "Arial" )) 52 | (line (pt 136 32)(pt 120 32)(line_width 3)) 53 | ) 54 | (drawing 55 | (rectangle (rect 16 16 120 80)) 56 | ) 57 | ) 58 | -------------------------------------------------------------------------------- /e-clock/2c1.bsf: -------------------------------------------------------------------------------- 1 | /* 2 | WARNING: Do NOT edit the input and output ports in this file in a text 3 | editor if you plan to continue editing the block that represents it in 4 | the Block Editor! File corruption is VERY likely to occur. 5 | */ 6 | /* 7 | Copyright (C) 1991-2013 Altera Corporation 8 | Your use of Altera Corporation's design tools, logic functions 9 | and other software and tools, and its AMPP partner logic 10 | functions, and any output files from any of the foregoing 11 | (including device programming or simulation files), and any 12 | associated documentation or information are expressly subject 13 | to the terms and conditions of the Altera Program License 14 | Subscription Agreement, Altera MegaCore Function License 15 | Agreement, or other applicable license agreement, including, 16 | without limitation, that your use is for the sole purpose of 17 | programming logic devices manufactured by Altera and sold by 18 | Altera or its authorized distributors. Please refer to the 19 | applicable agreement for further details. 20 | */ 21 | (header "symbol" (version "1.2")) 22 | (symbol 23 | (rect 16 16 152 112) 24 | (text "2c1" (rect 5 0 26 14)(font "Arial" (font_size 8))) 25 | (text "inst" (rect 8 80 25 92)(font "Arial" )) 26 | (port 27 | (pt 0 32) 28 | (input) 29 | (text "K" (rect 0 0 7 12)(font "Arial" )) 30 | (text "K" (rect 21 27 28 39)(font "Arial" )) 31 | (line (pt 0 32)(pt 16 32)) 32 | ) 33 | (port 34 | (pt 0 48) 35 | (input) 36 | (text "H24[3..0]" (rect 0 0 46 12)(font "Arial" )) 37 | (text "H24[3..0]" (rect 21 43 67 55)(font "Arial" )) 38 | (line (pt 0 48)(pt 16 48)(line_width 3)) 39 | ) 40 | (port 41 | (pt 0 64) 42 | (input) 43 | (text "H12[3..0]" (rect 0 0 46 12)(font "Arial" )) 44 | (text "H12[3..0]" (rect 21 59 67 71)(font "Arial" )) 45 | (line (pt 0 64)(pt 16 64)(line_width 3)) 46 | ) 47 | (port 48 | (pt 136 32) 49 | (output) 50 | (text "R[3..0]" (rect 0 0 34 12)(font "Arial" )) 51 | (text "R[3..0]" (rect 81 27 115 39)(font "Arial" )) 52 | (line (pt 136 32)(pt 120 32)(line_width 3)) 53 | ) 54 | (drawing 55 | (rectangle (rect 16 16 120 80)) 56 | ) 57 | ) 58 | -------------------------------------------------------------------------------- /e-clock/3c1.bsf: -------------------------------------------------------------------------------- 1 | /* 2 | WARNING: Do NOT edit the input and output ports in this file in a text 3 | editor if you plan to continue editing the block that represents it in 4 | the Block Editor! File corruption is VERY likely to occur. 5 | */ 6 | /* 7 | Copyright (C) 1991-2013 Altera Corporation 8 | Your use of Altera Corporation's design tools, logic functions 9 | and other software and tools, and its AMPP partner logic 10 | functions, and any output files from any of the foregoing 11 | (including device programming or simulation files), and any 12 | associated documentation or information are expressly subject 13 | to the terms and conditions of the Altera Program License 14 | Subscription Agreement, Altera MegaCore Function License 15 | Agreement, or other applicable license agreement, including, 16 | without limitation, that your use is for the sole purpose of 17 | programming logic devices manufactured by Altera and sold by 18 | Altera or its authorized distributors. Please refer to the 19 | applicable agreement for further details. 20 | */ 21 | (header "symbol" (version "1.2")) 22 | (symbol 23 | (rect 16 16 152 144) 24 | (text "3c1" (rect 5 0 26 14)(font "Arial" (font_size 8))) 25 | (text "inst" (rect 8 112 25 124)(font "Arial" )) 26 | (port 27 | (pt 0 32) 28 | (input) 29 | (text "K0" (rect 0 0 12 12)(font "Arial" )) 30 | (text "K0" (rect 21 27 33 39)(font "Arial" )) 31 | (line (pt 0 32)(pt 16 32)) 32 | ) 33 | (port 34 | (pt 0 48) 35 | (input) 36 | (text "K4" (rect 0 0 12 12)(font "Arial" )) 37 | (text "K4" (rect 21 43 33 55)(font "Arial" )) 38 | (line (pt 0 48)(pt 16 48)) 39 | ) 40 | (port 41 | (pt 0 64) 42 | (input) 43 | (text "H24[3..0]" (rect 0 0 46 12)(font "Arial" )) 44 | (text "H24[3..0]" (rect 21 59 67 71)(font "Arial" )) 45 | (line (pt 0 64)(pt 16 64)(line_width 3)) 46 | ) 47 | (port 48 | (pt 0 80) 49 | (input) 50 | (text "H12[3..0]" (rect 0 0 46 12)(font "Arial" )) 51 | (text "H12[3..0]" (rect 21 75 67 87)(font "Arial" )) 52 | (line (pt 0 80)(pt 16 80)(line_width 3)) 53 | ) 54 | (port 55 | (pt 0 96) 56 | (input) 57 | (text "M60[3..0]" (rect 0 0 46 12)(font "Arial" )) 58 | (text "M60[3..0]" (rect 21 91 67 103)(font "Arial" )) 59 | (line (pt 0 96)(pt 16 96)(line_width 3)) 60 | ) 61 | (port 62 | (pt 136 32) 63 | (output) 64 | (text "R[3..0]" (rect 0 0 34 12)(font "Arial" )) 65 | (text "R[3..0]" (rect 81 27 115 39)(font "Arial" )) 66 | (line (pt 136 32)(pt 120 32)(line_width 3)) 67 | ) 68 | (drawing 69 | (rectangle (rect 16 16 120 112)) 70 | ) 71 | ) 72 | -------------------------------------------------------------------------------- /e-clock/74.bsf: -------------------------------------------------------------------------------- 1 | /* 2 | WARNING: Do NOT edit the input and output ports in this file in a text 3 | editor if you plan to continue editing the block that represents it in 4 | the Block Editor! File corruption is VERY likely to occur. 5 | */ 6 | /* 7 | Copyright (C) 1991-2013 Altera Corporation 8 | Your use of Altera Corporation's design tools, logic functions 9 | and other software and tools, and its AMPP partner logic 10 | functions, and any output files from any of the foregoing 11 | (including device programming or simulation files), and any 12 | associated documentation or information are expressly subject 13 | to the terms and conditions of the Altera Program License 14 | Subscription Agreement, Altera MegaCore Function License 15 | Agreement, or other applicable license agreement, including, 16 | without limitation, that your use is for the sole purpose of 17 | programming logic devices manufactured by Altera and sold by 18 | Altera or its authorized distributors. Please refer to the 19 | applicable agreement for further details. 20 | */ 21 | (header "symbol" (version "1.2")) 22 | (symbol 23 | (rect 16 16 112 176) 24 | (text "74" (rect 5 0 19 14)(font "Arial" (font_size 8))) 25 | (text "inst" (rect 8 144 25 156)(font "Arial" )) 26 | (port 27 | (pt 0 32) 28 | (input) 29 | (text "A" (rect 0 0 9 14)(font "Arial" (font_size 8))) 30 | (text "A" (rect 21 27 30 41)(font "Arial" (font_size 8))) 31 | (line (pt 0 32)(pt 16 32)) 32 | ) 33 | (port 34 | (pt 0 48) 35 | (input) 36 | (text "B" (rect 0 0 8 14)(font "Arial" (font_size 8))) 37 | (text "B" (rect 21 43 29 57)(font "Arial" (font_size 8))) 38 | (line (pt 0 48)(pt 16 48)) 39 | ) 40 | (port 41 | (pt 0 64) 42 | (input) 43 | (text "C" (rect 0 0 8 14)(font "Arial" (font_size 8))) 44 | (text "C" (rect 21 59 29 73)(font "Arial" (font_size 8))) 45 | (line (pt 0 64)(pt 16 64)) 46 | ) 47 | (port 48 | (pt 0 80) 49 | (input) 50 | (text "D" (rect 0 0 8 14)(font "Arial" (font_size 8))) 51 | (text "D" (rect 21 75 29 89)(font "Arial" (font_size 8))) 52 | (line (pt 0 80)(pt 16 80)) 53 | ) 54 | (port 55 | (pt 96 32) 56 | (output) 57 | (text "OA" (rect 0 0 18 14)(font "Arial" (font_size 8))) 58 | (text "OA" (rect 57 27 75 41)(font "Arial" (font_size 8))) 59 | (line (pt 96 32)(pt 80 32)) 60 | ) 61 | (port 62 | (pt 96 48) 63 | (output) 64 | (text "OB" (rect 0 0 17 14)(font "Arial" (font_size 8))) 65 | (text "OB" (rect 58 43 75 57)(font "Arial" (font_size 8))) 66 | (line (pt 96 48)(pt 80 48)) 67 | ) 68 | (port 69 | (pt 96 64) 70 | (output) 71 | (text "OC" (rect 0 0 17 14)(font "Arial" (font_size 8))) 72 | (text "OC" (rect 58 59 75 73)(font "Arial" (font_size 8))) 73 | (line (pt 96 64)(pt 80 64)) 74 | ) 75 | (port 76 | (pt 96 80) 77 | (output) 78 | (text "OD" (rect 0 0 17 14)(font "Arial" (font_size 8))) 79 | (text "OD" (rect 58 75 75 89)(font "Arial" (font_size 8))) 80 | (line (pt 96 80)(pt 80 80)) 81 | ) 82 | (port 83 | (pt 96 96) 84 | (output) 85 | (text "OE" (rect 0 0 16 14)(font "Arial" (font_size 8))) 86 | (text "OE" (rect 59 91 75 105)(font "Arial" (font_size 8))) 87 | (line (pt 96 96)(pt 80 96)) 88 | ) 89 | (port 90 | (pt 96 112) 91 | (output) 92 | (text "OF" (rect 0 0 16 14)(font "Arial" (font_size 8))) 93 | (text "OF" (rect 59 107 75 121)(font "Arial" (font_size 8))) 94 | (line (pt 96 112)(pt 80 112)) 95 | ) 96 | (port 97 | (pt 96 128) 98 | (output) 99 | (text "OG" (rect 0 0 18 14)(font "Arial" (font_size 8))) 100 | (text "OG" (rect 57 123 75 137)(font "Arial" (font_size 8))) 101 | (line (pt 96 128)(pt 80 128)) 102 | ) 103 | (drawing 104 | (rectangle (rect 16 16 80 144)) 105 | ) 106 | ) 107 | -------------------------------------------------------------------------------- /e-clock/7447pro.bsf: -------------------------------------------------------------------------------- 1 | /* 2 | WARNING: Do NOT edit the input and output ports in this file in a text 3 | editor if you plan to continue editing the block that represents it in 4 | the Block Editor! File corruption is VERY likely to occur. 5 | */ 6 | /* 7 | Copyright (C) 1991-2013 Altera Corporation 8 | Your use of Altera Corporation's design tools, logic functions 9 | and other software and tools, and its AMPP partner logic 10 | functions, and any output files from any of the foregoing 11 | (including device programming or simulation files), and any 12 | associated documentation or information are expressly subject 13 | to the terms and conditions of the Altera Program License 14 | Subscription Agreement, Altera MegaCore Function License 15 | Agreement, or other applicable license agreement, including, 16 | without limitation, that your use is for the sole purpose of 17 | programming logic devices manufactured by Altera and sold by 18 | Altera or its authorized distributors. Please refer to the 19 | applicable agreement for further details. 20 | */ 21 | (header "symbol" (version "1.2")) 22 | (symbol 23 | (rect 16 16 136 112) 24 | (text "7447pro" (rect 5 0 52 14)(font "Arial" (font_size 8))) 25 | (text "inst" (rect 8 80 25 92)(font "Arial" )) 26 | (port 27 | (pt 0 32) 28 | (input) 29 | (text "D[3..0]" (rect 0 0 34 12)(font "Arial" )) 30 | (text "D[3..0]" (rect 21 27 55 39)(font "Arial" )) 31 | (line (pt 0 32)(pt 16 32)(line_width 3)) 32 | ) 33 | (port 34 | (pt 120 32) 35 | (output) 36 | (text "O[6..0]" (rect 0 0 34 12)(font "Arial" )) 37 | (text "O[6..0]" (rect 65 27 99 39)(font "Arial" )) 38 | (line (pt 120 32)(pt 104 32)(line_width 3)) 39 | ) 40 | (drawing 41 | (rectangle (rect 16 16 104 80)) 42 | ) 43 | ) 44 | -------------------------------------------------------------------------------- /e-clock/7448pro.bsf: -------------------------------------------------------------------------------- 1 | /* 2 | WARNING: Do NOT edit the input and output ports in this file in a text 3 | editor if you plan to continue editing the block that represents it in 4 | the Block Editor! File corruption is VERY likely to occur. 5 | */ 6 | /* 7 | Copyright (C) 1991-2013 Altera Corporation 8 | Your use of Altera Corporation's design tools, logic functions 9 | and other software and tools, and its AMPP partner logic 10 | functions, and any output files from any of the foregoing 11 | (including device programming or simulation files), and any 12 | associated documentation or information are expressly subject 13 | to the terms and conditions of the Altera Program License 14 | Subscription Agreement, Altera MegaCore Function License 15 | Agreement, or other applicable license agreement, including, 16 | without limitation, that your use is for the sole purpose of 17 | programming logic devices manufactured by Altera and sold by 18 | Altera or its authorized distributors. Please refer to the 19 | applicable agreement for further details. 20 | */ 21 | (header "symbol" (version "1.2")) 22 | (symbol 23 | (rect 16 16 144 112) 24 | (text "7448pro" (rect 5 0 52 14)(font "Arial" (font_size 8))) 25 | (text "inst" (rect 8 80 25 92)(font "Arial" )) 26 | (port 27 | (pt 0 32) 28 | (input) 29 | (text "D[3..0]" (rect 0 0 36 14)(font "Arial" (font_size 8))) 30 | (text "D[3..0]" (rect 21 27 57 41)(font "Arial" (font_size 8))) 31 | (line (pt 0 32)(pt 16 32)(line_width 3)) 32 | ) 33 | (port 34 | (pt 128 32) 35 | (output) 36 | (text "O[6..0]" (rect 0 0 37 14)(font "Arial" (font_size 8))) 37 | (text "O[6..0]" (rect 70 27 107 41)(font "Arial" (font_size 8))) 38 | (line (pt 128 32)(pt 112 32)(line_width 3)) 39 | ) 40 | (drawing 41 | (rectangle (rect 16 16 112 80)) 42 | ) 43 | ) 44 | -------------------------------------------------------------------------------- /e-clock/ANDpro.bsf: -------------------------------------------------------------------------------- 1 | /* 2 | WARNING: Do NOT edit the input and output ports in this file in a text 3 | editor if you plan to continue editing the block that represents it in 4 | the Block Editor! File corruption is VERY likely to occur. 5 | */ 6 | /* 7 | Copyright (C) 1991-2013 Altera Corporation 8 | Your use of Altera Corporation's design tools, logic functions 9 | and other software and tools, and its AMPP partner logic 10 | functions, and any output files from any of the foregoing 11 | (including device programming or simulation files), and any 12 | associated documentation or information are expressly subject 13 | to the terms and conditions of the Altera Program License 14 | Subscription Agreement, Altera MegaCore Function License 15 | Agreement, or other applicable license agreement, including, 16 | without limitation, that your use is for the sole purpose of 17 | programming logic devices manufactured by Altera and sold by 18 | Altera or its authorized distributors. Please refer to the 19 | applicable agreement for further details. 20 | */ 21 | (header "symbol" (version "1.2")) 22 | (symbol 23 | (rect 16 16 112 144) 24 | (text "ANDpro" (rect 5 0 49 14)(font "Arial" (font_size 8))) 25 | (text "inst" (rect 8 112 25 124)(font "Arial" )) 26 | (port 27 | (pt 0 32) 28 | (input) 29 | (text "S" (rect 0 0 7 12)(font "Arial" )) 30 | (text "S" (rect 21 27 28 39)(font "Arial" )) 31 | (line (pt 0 32)(pt 16 32)) 32 | ) 33 | (port 34 | (pt 0 48) 35 | (input) 36 | (text "N3" (rect 0 0 14 12)(font "Arial" )) 37 | (text "N3" (rect 21 43 35 55)(font "Arial" )) 38 | (line (pt 0 48)(pt 16 48)) 39 | ) 40 | (port 41 | (pt 0 64) 42 | (input) 43 | (text "N2" (rect 0 0 14 12)(font "Arial" )) 44 | (text "N2" (rect 21 59 35 71)(font "Arial" )) 45 | (line (pt 0 64)(pt 16 64)) 46 | ) 47 | (port 48 | (pt 0 80) 49 | (input) 50 | (text "N1" (rect 0 0 14 12)(font "Arial" )) 51 | (text "N1" (rect 21 75 35 87)(font "Arial" )) 52 | (line (pt 0 80)(pt 16 80)) 53 | ) 54 | (port 55 | (pt 0 96) 56 | (input) 57 | (text "N0" (rect 0 0 14 12)(font "Arial" )) 58 | (text "N0" (rect 21 91 35 103)(font "Arial" )) 59 | (line (pt 0 96)(pt 16 96)) 60 | ) 61 | (port 62 | (pt 96 32) 63 | (output) 64 | (text "N3out" (rect 0 0 29 12)(font "Arial" )) 65 | (text "N3out" (rect 46 27 75 39)(font "Arial" )) 66 | (line (pt 96 32)(pt 80 32)) 67 | ) 68 | (port 69 | (pt 96 48) 70 | (output) 71 | (text "N2out" (rect 0 0 29 12)(font "Arial" )) 72 | (text "N2out" (rect 46 43 75 55)(font "Arial" )) 73 | (line (pt 96 48)(pt 80 48)) 74 | ) 75 | (port 76 | (pt 96 64) 77 | (output) 78 | (text "N1out" (rect 0 0 29 12)(font "Arial" )) 79 | (text "N1out" (rect 46 59 75 71)(font "Arial" )) 80 | (line (pt 96 64)(pt 80 64)) 81 | ) 82 | (port 83 | (pt 96 80) 84 | (output) 85 | (text "N0out" (rect 0 0 29 12)(font "Arial" )) 86 | (text "N0out" (rect 46 75 75 87)(font "Arial" )) 87 | (line (pt 96 80)(pt 80 80)) 88 | ) 89 | (drawing 90 | (rectangle (rect 16 16 80 112)) 91 | ) 92 | ) 93 | -------------------------------------------------------------------------------- /e-clock/LEDpro.bsf: -------------------------------------------------------------------------------- 1 | /* 2 | WARNING: Do NOT edit the input and output ports in this file in a text 3 | editor if you plan to continue editing the block that represents it in 4 | the Block Editor! File corruption is VERY likely to occur. 5 | */ 6 | /* 7 | Copyright (C) 1991-2013 Altera Corporation 8 | Your use of Altera Corporation's design tools, logic functions 9 | and other software and tools, and its AMPP partner logic 10 | functions, and any output files from any of the foregoing 11 | (including device programming or simulation files), and any 12 | associated documentation or information are expressly subject 13 | to the terms and conditions of the Altera Program License 14 | Subscription Agreement, Altera MegaCore Function License 15 | Agreement, or other applicable license agreement, including, 16 | without limitation, that your use is for the sole purpose of 17 | programming logic devices manufactured by Altera and sold by 18 | Altera or its authorized distributors. Please refer to the 19 | applicable agreement for further details. 20 | */ 21 | (header "symbol" (version "1.2")) 22 | (symbol 23 | (rect 16 16 152 112) 24 | (text "LEDpro" (rect 5 0 46 14)(font "Arial" (font_size 8))) 25 | (text "inst" (rect 8 80 25 92)(font "Arial" )) 26 | (port 27 | (pt 0 32) 28 | (input) 29 | (text "L[0..7]" (rect 0 0 31 12)(font "Arial" )) 30 | (text "L[0..7]" (rect 21 27 52 39)(font "Arial" )) 31 | (line (pt 0 32)(pt 16 32)(line_width 3)) 32 | ) 33 | (port 34 | (pt 136 32) 35 | (output) 36 | (text "LED[0..7]" (rect 0 0 47 12)(font "Arial" )) 37 | (text "LED[0..7]" (rect 68 27 115 39)(font "Arial" )) 38 | (line (pt 136 32)(pt 120 32)(line_width 3)) 39 | ) 40 | (drawing 41 | (rectangle (rect 16 16 120 80)) 42 | ) 43 | ) 44 | -------------------------------------------------------------------------------- /e-clock/LSD.dpf: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 | 39 | 40 | 41 | 42 | 43 | 44 | 45 | 46 | 47 | 48 | 49 | 50 | 51 | 52 | 53 | 54 | 55 | -------------------------------------------------------------------------------- /e-clock/LSD.qws: -------------------------------------------------------------------------------- 1 | @(last_workspace -------------------------------------------------------------------------------- /e-clock/LSD_nativelink_simulation.rpt: -------------------------------------------------------------------------------- 1 | Info: Start Nativelink Simulation process 2 | Error: NativeLink did not detect any HDL files in the project 3 | Error: NativeLink simulation flow was NOT successful 4 | 5 | 6 | 7 | ================The following additional information is provided to help identify the cause of error while running nativelink scripts================= 8 | Nativelink TCL script failed with errorCode: NONE 9 | Nativelink TCL script failed with errorInfo: NativeLink did not detect any HDL files in the project 10 | (procedure "run_eda_simulation_tool" line 1) 11 | invoked from within 12 | "run_eda_simulation_tool eda_opts_hash" 13 | -------------------------------------------------------------------------------- /e-clock/but.bsf: -------------------------------------------------------------------------------- 1 | /* 2 | WARNING: Do NOT edit the input and output ports in this file in a text 3 | editor if you plan to continue editing the block that represents it in 4 | the Block Editor! File corruption is VERY likely to occur. 5 | */ 6 | /* 7 | Copyright (C) 1991-2013 Altera Corporation 8 | Your use of Altera Corporation's design tools, logic functions 9 | and other software and tools, and its AMPP partner logic 10 | functions, and any output files from any of the foregoing 11 | (including device programming or simulation files), and any 12 | associated documentation or information are expressly subject 13 | to the terms and conditions of the Altera Program License 14 | Subscription Agreement, Altera MegaCore Function License 15 | Agreement, or other applicable license agreement, including, 16 | without limitation, that your use is for the sole purpose of 17 | programming logic devices manufactured by Altera and sold by 18 | Altera or its authorized distributors. Please refer to the 19 | applicable agreement for further details. 20 | */ 21 | (header "symbol" (version "1.2")) 22 | (symbol 23 | (rect 16 16 168 112) 24 | (text "but" (rect 5 0 22 14)(font "Arial" (font_size 8))) 25 | (text "inst" (rect 8 80 25 92)(font "Arial" )) 26 | (port 27 | (pt 0 32) 28 | (input) 29 | (text "ButInput" (rect 0 0 41 12)(font "Arial" )) 30 | (text "ButInput" (rect 21 27 62 39)(font "Arial" )) 31 | (line (pt 0 32)(pt 16 32)) 32 | ) 33 | (port 34 | (pt 0 48) 35 | (input) 36 | (text "clk_100Hz" (rect 0 0 50 12)(font "Arial" )) 37 | (text "clk_100Hz" (rect 21 43 71 55)(font "Arial" )) 38 | (line (pt 0 48)(pt 16 48)) 39 | ) 40 | (port 41 | (pt 152 32) 42 | (output) 43 | (text "ButOutput" (rect 0 0 49 12)(font "Arial" )) 44 | (text "ButOutput" (rect 82 27 131 39)(font "Arial" )) 45 | (line (pt 152 32)(pt 136 32)) 46 | ) 47 | (drawing 48 | (rectangle (rect 16 16 136 80)) 49 | ) 50 | ) 51 | -------------------------------------------------------------------------------- /e-clock/but.vwf: -------------------------------------------------------------------------------- 1 | /* 2 | WARNING: Do NOT edit the input and output ports in this file in a text 3 | editor if you plan to continue editing the block that represents it in 4 | the Block Editor! File corruption is VERY likely to occur. 5 | */ 6 | 7 | /* 8 | Copyright (C) 1991-2013 Altera Corporation 9 | Your use of Altera Corporation's design tools, logic functions 10 | and other software and tools, and its AMPP partner logic 11 | functions, and any output files from any of the foregoing 12 | (including device programming or simulation files), and any 13 | associated documentation or information are expressly subject 14 | to the terms and conditions of the Altera Program License 15 | Subscription Agreement, Altera MegaCore Function License 16 | Agreement, or other applicable license agreement, including, 17 | without limitation, that your use is for the sole purpose of 18 | programming logic devices manufactured by Altera and sold by 19 | Altera or its authorized distributors. Please refer to the 20 | applicable agreement for further details. 21 | */ 22 | 23 | HEADER 24 | { 25 | VERSION = 1; 26 | TIME_UNIT = ns; 27 | DATA_OFFSET = 0.0; 28 | DATA_DURATION = 1000.0; 29 | SIMULATION_TIME = 0.0; 30 | GRID_PHASE = 0.0; 31 | GRID_PERIOD = 10.0; 32 | GRID_DUTY_CYCLE = 50; 33 | } 34 | 35 | SIGNAL("ButInput") 36 | { 37 | VALUE_TYPE = NINE_LEVEL_BIT; 38 | SIGNAL_TYPE = SINGLE_BIT; 39 | WIDTH = 1; 40 | LSB_INDEX = -1; 41 | DIRECTION = INPUT; 42 | PARENT = ""; 43 | } 44 | 45 | SIGNAL("ButOutput") 46 | { 47 | VALUE_TYPE = NINE_LEVEL_BIT; 48 | SIGNAL_TYPE = SINGLE_BIT; 49 | WIDTH = 1; 50 | LSB_INDEX = -1; 51 | DIRECTION = OUTPUT; 52 | PARENT = ""; 53 | } 54 | 55 | SIGNAL("clk_100Hz") 56 | { 57 | VALUE_TYPE = NINE_LEVEL_BIT; 58 | SIGNAL_TYPE = SINGLE_BIT; 59 | WIDTH = 1; 60 | LSB_INDEX = -1; 61 | DIRECTION = INPUT; 62 | PARENT = ""; 63 | } 64 | 65 | TRANSITION_LIST("ButInput") 66 | { 67 | NODE 68 | { 69 | REPEAT = 1; 70 | LEVEL 1 FOR 30.0; 71 | LEVEL 0 FOR 20.0; 72 | LEVEL 1 FOR 10.0; 73 | LEVEL 0 FOR 40.0; 74 | LEVEL 1 FOR 20.0; 75 | LEVEL 0 FOR 50.0; 76 | LEVEL 1 FOR 30.0; 77 | LEVEL 0 FOR 10.0; 78 | LEVEL 1 FOR 30.0; 79 | LEVEL 0 FOR 20.0; 80 | LEVEL 1 FOR 30.0; 81 | LEVEL 0 FOR 20.0; 82 | LEVEL 1 FOR 20.0; 83 | LEVEL 0 FOR 10.0; 84 | LEVEL 1 FOR 10.0; 85 | LEVEL 0 FOR 10.0; 86 | LEVEL 1 FOR 10.0; 87 | LEVEL 0 FOR 20.0; 88 | LEVEL 1 FOR 20.0; 89 | LEVEL 0 FOR 10.0; 90 | LEVEL 1 FOR 10.0; 91 | LEVEL 0 FOR 70.0; 92 | LEVEL 1 FOR 10.0; 93 | LEVEL 0 FOR 10.0; 94 | LEVEL 1 FOR 30.0; 95 | LEVEL 0 FOR 10.0; 96 | LEVEL 1 FOR 30.0; 97 | LEVEL 0 FOR 20.0; 98 | LEVEL 1 FOR 10.0; 99 | LEVEL 0 FOR 40.0; 100 | LEVEL 1 FOR 10.0; 101 | LEVEL 0 FOR 10.0; 102 | LEVEL 1 FOR 20.0; 103 | LEVEL 0 FOR 10.0; 104 | LEVEL 1 FOR 40.0; 105 | LEVEL 0 FOR 10.0; 106 | LEVEL 1 FOR 10.0; 107 | LEVEL 0 FOR 50.0; 108 | LEVEL 1 FOR 20.0; 109 | LEVEL 0 FOR 20.0; 110 | LEVEL 1 FOR 10.0; 111 | LEVEL 0 FOR 10.0; 112 | LEVEL 1 FOR 30.0; 113 | LEVEL 0 FOR 10.0; 114 | LEVEL 1 FOR 10.0; 115 | LEVEL 0 FOR 10.0; 116 | LEVEL 1 FOR 20.0; 117 | LEVEL 0 FOR 10.0; 118 | LEVEL 1 FOR 10.0; 119 | LEVEL 0 FOR 20.0; 120 | } 121 | } 122 | 123 | TRANSITION_LIST("ButOutput") 124 | { 125 | NODE 126 | { 127 | REPEAT = 1; 128 | LEVEL X FOR 1000.0; 129 | } 130 | } 131 | 132 | TRANSITION_LIST("clk_100Hz") 133 | { 134 | NODE 135 | { 136 | REPEAT = 1; 137 | NODE 138 | { 139 | REPEAT = 100; 140 | LEVEL 0 FOR 5.0; 141 | LEVEL 1 FOR 5.0; 142 | } 143 | } 144 | } 145 | 146 | DISPLAY_LINE 147 | { 148 | CHANNEL = "ButInput"; 149 | EXPAND_STATUS = COLLAPSED; 150 | RADIX = Binary; 151 | TREE_INDEX = 0; 152 | TREE_LEVEL = 0; 153 | } 154 | 155 | DISPLAY_LINE 156 | { 157 | CHANNEL = "ButOutput"; 158 | EXPAND_STATUS = COLLAPSED; 159 | RADIX = Binary; 160 | TREE_INDEX = 1; 161 | TREE_LEVEL = 0; 162 | } 163 | 164 | DISPLAY_LINE 165 | { 166 | CHANNEL = "clk_100Hz"; 167 | EXPAND_STATUS = COLLAPSED; 168 | RADIX = Binary; 169 | TREE_INDEX = 2; 170 | TREE_LEVEL = 0; 171 | } 172 | 173 | TIME_BAR 174 | { 175 | TIME = 0; 176 | MASTER = TRUE; 177 | } 178 | ; 179 | -------------------------------------------------------------------------------- /e-clock/butpro.bsf: -------------------------------------------------------------------------------- 1 | /* 2 | WARNING: Do NOT edit the input and output ports in this file in a text 3 | editor if you plan to continue editing the block that represents it in 4 | the Block Editor! File corruption is VERY likely to occur. 5 | */ 6 | /* 7 | Copyright (C) 1991-2013 Altera Corporation 8 | Your use of Altera Corporation's design tools, logic functions 9 | and other software and tools, and its AMPP partner logic 10 | functions, and any output files from any of the foregoing 11 | (including device programming or simulation files), and any 12 | associated documentation or information are expressly subject 13 | to the terms and conditions of the Altera Program License 14 | Subscription Agreement, Altera MegaCore Function License 15 | Agreement, or other applicable license agreement, including, 16 | without limitation, that your use is for the sole purpose of 17 | programming logic devices manufactured by Altera and sold by 18 | Altera or its authorized distributors. Please refer to the 19 | applicable agreement for further details. 20 | */ 21 | (header "symbol" (version "1.2")) 22 | (symbol 23 | (rect 16 16 144 112) 24 | (text "butpro" (rect 5 0 41 14)(font "Arial" (font_size 8))) 25 | (text "inst" (rect 8 80 25 92)(font "Arial" )) 26 | (port 27 | (pt 0 32) 28 | (input) 29 | (text "clk100" (rect 0 0 31 12)(font "Arial" )) 30 | (text "clk100" (rect 21 27 52 39)(font "Arial" )) 31 | (line (pt 0 32)(pt 16 32)) 32 | ) 33 | (port 34 | (pt 0 48) 35 | (input) 36 | (text "K[0..7]" (rect 0 0 33 12)(font "Arial" )) 37 | (text "K[0..7]" (rect 21 43 54 55)(font "Arial" )) 38 | (line (pt 0 48)(pt 16 48)(line_width 3)) 39 | ) 40 | (port 41 | (pt 128 32) 42 | (output) 43 | (text "but[0..7]" (rect 0 0 41 12)(font "Arial" )) 44 | (text "but[0..7]" (rect 66 27 107 39)(font "Arial" )) 45 | (line (pt 128 32)(pt 112 32)(line_width 3)) 46 | ) 47 | (drawing 48 | (rectangle (rect 16 16 112 80)) 49 | ) 50 | ) 51 | -------------------------------------------------------------------------------- /e-clock/clk_100.bdf: -------------------------------------------------------------------------------- 1 | /* 2 | WARNING: Do NOT edit the input and output ports in this file in a text 3 | editor if you plan to continue editing the block that represents it in 4 | the Block Editor! File corruption is VERY likely to occur. 5 | */ 6 | /* 7 | Copyright (C) 1991-2013 Altera Corporation 8 | Your use of Altera Corporation's design tools, logic functions 9 | and other software and tools, and its AMPP partner logic 10 | functions, and any output files from any of the foregoing 11 | (including device programming or simulation files), and any 12 | associated documentation or information are expressly subject 13 | to the terms and conditions of the Altera Program License 14 | Subscription Agreement, Altera MegaCore Function License 15 | Agreement, or other applicable license agreement, including, 16 | without limitation, that your use is for the sole purpose of 17 | programming logic devices manufactured by Altera and sold by 18 | Altera or its authorized distributors. Please refer to the 19 | applicable agreement for further details. 20 | */ 21 | (header "graphic" (version "1.4")) 22 | (pin 23 | (input) 24 | (rect 416 264 584 280) 25 | (text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6))) 26 | (text "clk_50m" (rect 5 0 46 12)(font "Arial" )) 27 | (pt 168 8) 28 | (drawing 29 | (line (pt 84 12)(pt 109 12)) 30 | (line (pt 84 4)(pt 109 4)) 31 | (line (pt 113 8)(pt 168 8)) 32 | (line (pt 84 12)(pt 84 4)) 33 | (line (pt 109 4)(pt 113 8)) 34 | (line (pt 109 12)(pt 113 8)) 35 | ) 36 | (text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6))) 37 | ) 38 | (pin 39 | (output) 40 | (rect 1176 376 1352 392) 41 | (text "OUTPUT" (rect 137 0 175 10)(font "Arial" (font_size 6))) 42 | (text "clk_out_100" (rect 5 0 64 12)(font "Arial" )) 43 | (pt 176 8) 44 | (drawing 45 | (line (pt 176 8)(pt 124 8)) 46 | (line (pt 124 4)(pt 98 4)) 47 | (line (pt 124 12)(pt 98 12)) 48 | (line (pt 124 12)(pt 124 4)) 49 | (line (pt 98 4)(pt 94 8)) 50 | (line (pt 94 8)(pt 98 12)) 51 | (line (pt 98 12)(pt 94 8)) 52 | ) 53 | (flipy) 54 | ) 55 | (symbol 56 | (rect 592 240 760 336) 57 | (text "cnt-100" (rect 5 0 48 14)(font "Arial" (font_size 8))) 58 | (text "inst" (rect 8 80 25 92)(font "Arial" )) 59 | (port 60 | (pt 0 32) 61 | (input) 62 | (text "clk_in_100" (rect 0 0 60 14)(font "Arial" (font_size 8))) 63 | (text "clk_in_100" (rect 21 27 81 41)(font "Arial" (font_size 8))) 64 | (line (pt 0 32)(pt 16 32)) 65 | ) 66 | (port 67 | (pt 168 32) 68 | (output) 69 | (text "clk_out_1" (rect 0 0 54 14)(font "Arial" (font_size 8))) 70 | (text "clk_out_1" (rect 93 27 147 41)(font "Arial" (font_size 8))) 71 | (line (pt 168 32)(pt 152 32)) 72 | ) 73 | (drawing 74 | (rectangle (rect 16 16 152 80)) 75 | ) 76 | ) 77 | (symbol 78 | (rect 784 240 952 336) 79 | (text "cnt-100" (rect 5 0 48 14)(font "Arial" (font_size 8))) 80 | (text "inst1" (rect 8 80 31 92)(font "Arial" )) 81 | (port 82 | (pt 0 32) 83 | (input) 84 | (text "clk_in_100" (rect 0 0 60 14)(font "Arial" (font_size 8))) 85 | (text "clk_in_100" (rect 21 27 81 41)(font "Arial" (font_size 8))) 86 | (line (pt 0 32)(pt 16 32)) 87 | ) 88 | (port 89 | (pt 168 32) 90 | (output) 91 | (text "clk_out_1" (rect 0 0 54 14)(font "Arial" (font_size 8))) 92 | (text "clk_out_1" (rect 93 27 147 41)(font "Arial" (font_size 8))) 93 | (line (pt 168 32)(pt 152 32)) 94 | ) 95 | (drawing 96 | (rectangle (rect 16 16 152 80)) 97 | ) 98 | ) 99 | (symbol 100 | (rect 984 240 1144 336) 101 | (text "cnt-25" (rect 5 0 41 14)(font "Arial" (font_size 8))) 102 | (text "inst2" (rect 8 80 31 92)(font "Arial" )) 103 | (port 104 | (pt 0 32) 105 | (input) 106 | (text "clk_in_25" (rect 0 0 53 14)(font "Arial" (font_size 8))) 107 | (text "clk_in_25" (rect 21 27 74 41)(font "Arial" (font_size 8))) 108 | (line (pt 0 32)(pt 16 32)) 109 | ) 110 | (port 111 | (pt 160 32) 112 | (output) 113 | (text "clk_out_1" (rect 0 0 54 14)(font "Arial" (font_size 8))) 114 | (text "clk_out_1" (rect 85 27 139 41)(font "Arial" (font_size 8))) 115 | (line (pt 160 32)(pt 144 32)) 116 | ) 117 | (drawing 118 | (rectangle (rect 16 16 144 80)) 119 | ) 120 | ) 121 | (symbol 122 | (rect 1152 240 1304 336) 123 | (text "cnt-2" (rect 5 0 34 14)(font "Arial" (font_size 8))) 124 | (text "inst3" (rect 8 80 31 92)(font "Arial" )) 125 | (port 126 | (pt 0 32) 127 | (input) 128 | (text "clk_in_2" (rect 0 0 46 14)(font "Arial" (font_size 8))) 129 | (text "clk_in_2" (rect 21 27 67 41)(font "Arial" (font_size 8))) 130 | (line (pt 0 32)(pt 16 32)) 131 | ) 132 | (port 133 | (pt 152 32) 134 | (output) 135 | (text "clk_out_1" (rect 0 0 54 14)(font "Arial" (font_size 8))) 136 | (text "clk_out_1" (rect 77 27 131 41)(font "Arial" (font_size 8))) 137 | (line (pt 152 32)(pt 136 32)) 138 | ) 139 | (drawing 140 | (rectangle (rect 16 16 136 80)) 141 | ) 142 | ) 143 | (connector 144 | (pt 584 272) 145 | (pt 592 272) 146 | ) 147 | (connector 148 | (pt 760 272) 149 | (pt 784 272) 150 | ) 151 | (connector 152 | (pt 952 272) 153 | (pt 984 272) 154 | ) 155 | (connector 156 | (pt 1144 272) 157 | (pt 1152 272) 158 | ) 159 | (connector 160 | (pt 1360 384) 161 | (pt 1352 384) 162 | ) 163 | (connector 164 | (pt 1360 384) 165 | (pt 1360 272) 166 | ) 167 | (connector 168 | (pt 1304 272) 169 | (pt 1360 272) 170 | ) 171 | -------------------------------------------------------------------------------- /e-clock/clk_100.bsf: -------------------------------------------------------------------------------- 1 | /* 2 | WARNING: Do NOT edit the input and output ports in this file in a text 3 | editor if you plan to continue editing the block that represents it in 4 | the Block Editor! File corruption is VERY likely to occur. 5 | */ 6 | /* 7 | Copyright (C) 1991-2013 Altera Corporation 8 | Your use of Altera Corporation's design tools, logic functions 9 | and other software and tools, and its AMPP partner logic 10 | functions, and any output files from any of the foregoing 11 | (including device programming or simulation files), and any 12 | associated documentation or information are expressly subject 13 | to the terms and conditions of the Altera Program License 14 | Subscription Agreement, Altera MegaCore Function License 15 | Agreement, or other applicable license agreement, including, 16 | without limitation, that your use is for the sole purpose of 17 | programming logic devices manufactured by Altera and sold by 18 | Altera or its authorized distributors. Please refer to the 19 | applicable agreement for further details. 20 | */ 21 | (header "symbol" (version "1.2")) 22 | (symbol 23 | (rect 16 16 168 112) 24 | (text "clk_100" (rect 5 0 48 14)(font "Arial" (font_size 8))) 25 | (text "inst" (rect 8 80 25 92)(font "Arial" )) 26 | (port 27 | (pt 0 32) 28 | (input) 29 | (text "clk_50m" (rect 0 0 41 12)(font "Arial" )) 30 | (text "clk_50m" (rect 21 27 62 39)(font "Arial" )) 31 | (line (pt 0 32)(pt 16 32)) 32 | ) 33 | (port 34 | (pt 152 32) 35 | (output) 36 | (text "clk_out_100" (rect 0 0 59 12)(font "Arial" )) 37 | (text "clk_out_100" (rect 72 27 131 39)(font "Arial" )) 38 | (line (pt 152 32)(pt 136 32)) 39 | ) 40 | (drawing 41 | (rectangle (rect 16 16 136 80)) 42 | ) 43 | ) 44 | -------------------------------------------------------------------------------- /e-clock/clk_1k.bdf: -------------------------------------------------------------------------------- 1 | /* 2 | WARNING: Do NOT edit the input and output ports in this file in a text 3 | editor if you plan to continue editing the block that represents it in 4 | the Block Editor! File corruption is VERY likely to occur. 5 | */ 6 | /* 7 | Copyright (C) 1991-2013 Altera Corporation 8 | Your use of Altera Corporation's design tools, logic functions 9 | and other software and tools, and its AMPP partner logic 10 | functions, and any output files from any of the foregoing 11 | (including device programming or simulation files), and any 12 | associated documentation or information are expressly subject 13 | to the terms and conditions of the Altera Program License 14 | Subscription Agreement, Altera MegaCore Function License 15 | Agreement, or other applicable license agreement, including, 16 | without limitation, that your use is for the sole purpose of 17 | programming logic devices manufactured by Altera and sold by 18 | Altera or its authorized distributors. Please refer to the 19 | applicable agreement for further details. 20 | */ 21 | (header "graphic" (version "1.4")) 22 | (pin 23 | (input) 24 | (rect 160 304 328 320) 25 | (text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6))) 26 | (text "clk_50m" (rect 5 0 46 12)(font "Arial" )) 27 | (pt 168 8) 28 | (drawing 29 | (line (pt 84 12)(pt 109 12)) 30 | (line (pt 84 4)(pt 109 4)) 31 | (line (pt 113 8)(pt 168 8)) 32 | (line (pt 84 12)(pt 84 4)) 33 | (line (pt 109 4)(pt 113 8)) 34 | (line (pt 109 12)(pt 113 8)) 35 | ) 36 | (text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6))) 37 | ) 38 | (pin 39 | (output) 40 | (rect 1136 304 1312 320) 41 | (text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6))) 42 | (text "clk_out_1k" (rect 90 0 143 12)(font "Arial" )) 43 | (pt 0 8) 44 | (drawing 45 | (line (pt 0 8)(pt 52 8)) 46 | (line (pt 52 4)(pt 78 4)) 47 | (line (pt 52 12)(pt 78 12)) 48 | (line (pt 52 12)(pt 52 4)) 49 | (line (pt 78 4)(pt 82 8)) 50 | (line (pt 82 8)(pt 78 12)) 51 | (line (pt 78 12)(pt 82 8)) 52 | ) 53 | ) 54 | (symbol 55 | (rect 528 280 696 376) 56 | (text "cnt-100" (rect 5 0 48 14)(font "Arial" (font_size 8))) 57 | (text "inst" (rect 8 80 25 92)(font "Arial" )) 58 | (port 59 | (pt 0 32) 60 | (input) 61 | (text "clk_in_100" (rect 0 0 60 14)(font "Arial" (font_size 8))) 62 | (text "clk_in_100" (rect 21 27 81 41)(font "Arial" (font_size 8))) 63 | (line (pt 0 32)(pt 16 32)) 64 | ) 65 | (port 66 | (pt 168 32) 67 | (output) 68 | (text "clk_out_1" (rect 0 0 54 14)(font "Arial" (font_size 8))) 69 | (text "clk_out_1" (rect 93 27 147 41)(font "Arial" (font_size 8))) 70 | (line (pt 168 32)(pt 152 32)) 71 | ) 72 | (drawing 73 | (rectangle (rect 16 16 152 80)) 74 | ) 75 | ) 76 | (symbol 77 | (rect 336 280 504 376) 78 | (text "cnt-100" (rect 5 0 48 14)(font "Arial" (font_size 8))) 79 | (text "inst3" (rect 8 80 31 92)(font "Arial" )) 80 | (port 81 | (pt 0 32) 82 | (input) 83 | (text "clk_in_100" (rect 0 0 60 14)(font "Arial" (font_size 8))) 84 | (text "clk_in_100" (rect 21 27 81 41)(font "Arial" (font_size 8))) 85 | (line (pt 0 32)(pt 16 32)) 86 | ) 87 | (port 88 | (pt 168 32) 89 | (output) 90 | (text "clk_out_1" (rect 0 0 54 14)(font "Arial" (font_size 8))) 91 | (text "clk_out_1" (rect 93 27 147 41)(font "Arial" (font_size 8))) 92 | (line (pt 168 32)(pt 152 32)) 93 | ) 94 | (drawing 95 | (rectangle (rect 16 16 152 80)) 96 | ) 97 | ) 98 | (symbol 99 | (rect 744 280 896 376) 100 | (text "cnt-2" (rect 5 0 34 14)(font "Arial" (font_size 8))) 101 | (text "inst1" (rect 8 80 31 92)(font "Arial" )) 102 | (port 103 | (pt 0 32) 104 | (input) 105 | (text "clk_in_2" (rect 0 0 46 14)(font "Arial" (font_size 8))) 106 | (text "clk_in_2" (rect 21 27 67 41)(font "Arial" (font_size 8))) 107 | (line (pt 0 32)(pt 16 32)) 108 | ) 109 | (port 110 | (pt 152 32) 111 | (output) 112 | (text "clk_out_1" (rect 0 0 54 14)(font "Arial" (font_size 8))) 113 | (text "clk_out_1" (rect 77 27 131 41)(font "Arial" (font_size 8))) 114 | (line (pt 152 32)(pt 136 32)) 115 | ) 116 | (drawing 117 | (rectangle (rect 16 16 136 80)) 118 | ) 119 | ) 120 | (symbol 121 | (rect 920 280 1072 376) 122 | (text "cnt-2" (rect 5 0 34 14)(font "Arial" (font_size 8))) 123 | (text "inst2" (rect 8 80 31 92)(font "Arial" )) 124 | (port 125 | (pt 0 32) 126 | (input) 127 | (text "clk_in_2" (rect 0 0 46 14)(font "Arial" (font_size 8))) 128 | (text "clk_in_2" (rect 21 27 67 41)(font "Arial" (font_size 8))) 129 | (line (pt 0 32)(pt 16 32)) 130 | ) 131 | (port 132 | (pt 152 32) 133 | (output) 134 | (text "clk_out_1" (rect 0 0 54 14)(font "Arial" (font_size 8))) 135 | (text "clk_out_1" (rect 77 27 131 41)(font "Arial" (font_size 8))) 136 | (line (pt 152 32)(pt 136 32)) 137 | ) 138 | (drawing 139 | (rectangle (rect 16 16 136 80)) 140 | ) 141 | ) 142 | (connector 143 | (pt 328 312) 144 | (pt 336 312) 145 | ) 146 | (connector 147 | (pt 504 312) 148 | (pt 528 312) 149 | ) 150 | (connector 151 | (pt 696 312) 152 | (pt 744 312) 153 | ) 154 | (connector 155 | (pt 896 312) 156 | (pt 920 312) 157 | ) 158 | (connector 159 | (pt 1072 312) 160 | (pt 1136 312) 161 | ) 162 | -------------------------------------------------------------------------------- /e-clock/clk_1k.bsf: -------------------------------------------------------------------------------- 1 | /* 2 | WARNING: Do NOT edit the input and output ports in this file in a text 3 | editor if you plan to continue editing the block that represents it in 4 | the Block Editor! File corruption is VERY likely to occur. 5 | */ 6 | /* 7 | Copyright (C) 1991-2013 Altera Corporation 8 | Your use of Altera Corporation's design tools, logic functions 9 | and other software and tools, and its AMPP partner logic 10 | functions, and any output files from any of the foregoing 11 | (including device programming or simulation files), and any 12 | associated documentation or information are expressly subject 13 | to the terms and conditions of the Altera Program License 14 | Subscription Agreement, Altera MegaCore Function License 15 | Agreement, or other applicable license agreement, including, 16 | without limitation, that your use is for the sole purpose of 17 | programming logic devices manufactured by Altera and sold by 18 | Altera or its authorized distributors. Please refer to the 19 | applicable agreement for further details. 20 | */ 21 | (header "symbol" (version "1.2")) 22 | (symbol 23 | (rect 16 16 168 112) 24 | (text "clk_1k" (rect 5 0 40 14)(font "Arial" (font_size 8))) 25 | (text "inst" (rect 8 80 25 92)(font "Arial" )) 26 | (port 27 | (pt 0 32) 28 | (input) 29 | (text "clk_50m" (rect 0 0 41 12)(font "Arial" )) 30 | (text "clk_50m" (rect 21 27 62 39)(font "Arial" )) 31 | (line (pt 0 32)(pt 16 32)) 32 | ) 33 | (port 34 | (pt 152 32) 35 | (output) 36 | (text "clk_out_1k" (rect 0 0 53 12)(font "Arial" )) 37 | (text "clk_out_1k" (rect 78 27 131 39)(font "Arial" )) 38 | (line (pt 152 32)(pt 136 32)) 39 | ) 40 | (drawing 41 | (rectangle (rect 16 16 136 80)) 42 | ) 43 | ) 44 | -------------------------------------------------------------------------------- /e-clock/clk_2.bdf: -------------------------------------------------------------------------------- 1 | /* 2 | WARNING: Do NOT edit the input and output ports in this file in a text 3 | editor if you plan to continue editing the block that represents it in 4 | the Block Editor! File corruption is VERY likely to occur. 5 | */ 6 | /* 7 | Copyright (C) 1991-2013 Altera Corporation 8 | Your use of Altera Corporation's design tools, logic functions 9 | and other software and tools, and its AMPP partner logic 10 | functions, and any output files from any of the foregoing 11 | (including device programming or simulation files), and any 12 | associated documentation or information are expressly subject 13 | to the terms and conditions of the Altera Program License 14 | Subscription Agreement, Altera MegaCore Function License 15 | Agreement, or other applicable license agreement, including, 16 | without limitation, that your use is for the sole purpose of 17 | programming logic devices manufactured by Altera and sold by 18 | Altera or its authorized distributors. Please refer to the 19 | applicable agreement for further details. 20 | */ 21 | (header "graphic" (version "1.4")) 22 | (pin 23 | (input) 24 | (rect 536 624 704 640) 25 | (text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6))) 26 | (text "clk_50M" (rect 5 0 46 12)(font "Arial" )) 27 | (pt 168 8) 28 | (drawing 29 | (line (pt 84 12)(pt 109 12)) 30 | (line (pt 84 4)(pt 109 4)) 31 | (line (pt 113 8)(pt 168 8)) 32 | (line (pt 84 12)(pt 84 4)) 33 | (line (pt 109 4)(pt 113 8)) 34 | (line (pt 109 12)(pt 113 8)) 35 | ) 36 | (text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6))) 37 | ) 38 | (pin 39 | (output) 40 | (rect 1512 624 1688 640) 41 | (text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6))) 42 | (text "clk_2" (rect 90 0 115 12)(font "Arial" )) 43 | (pt 0 8) 44 | (drawing 45 | (line (pt 0 8)(pt 52 8)) 46 | (line (pt 52 4)(pt 78 4)) 47 | (line (pt 52 12)(pt 78 12)) 48 | (line (pt 52 12)(pt 52 4)) 49 | (line (pt 78 4)(pt 82 8)) 50 | (line (pt 82 8)(pt 78 12)) 51 | (line (pt 78 12)(pt 82 8)) 52 | ) 53 | ) 54 | (symbol 55 | (rect 728 600 896 696) 56 | (text "cnt-100" (rect 5 0 48 14)(font "Arial" (font_size 8))) 57 | (text "inst" (rect 8 80 25 92)(font "Arial" )) 58 | (port 59 | (pt 0 32) 60 | (input) 61 | (text "clk_in_100" (rect 0 0 60 14)(font "Arial" (font_size 8))) 62 | (text "clk_in_100" (rect 21 27 81 41)(font "Arial" (font_size 8))) 63 | (line (pt 0 32)(pt 16 32)) 64 | ) 65 | (port 66 | (pt 168 32) 67 | (output) 68 | (text "clk_out_1" (rect 0 0 54 14)(font "Arial" (font_size 8))) 69 | (text "clk_out_1" (rect 93 27 147 41)(font "Arial" (font_size 8))) 70 | (line (pt 168 32)(pt 152 32)) 71 | ) 72 | (drawing 73 | (rectangle (rect 16 16 152 80)) 74 | ) 75 | ) 76 | (symbol 77 | (rect 1296 600 1456 696) 78 | (text "cnt-25" (rect 5 0 41 14)(font "Arial" (font_size 8))) 79 | (text "inst1" (rect 8 80 31 92)(font "Arial" )) 80 | (port 81 | (pt 0 32) 82 | (input) 83 | (text "clk_in_25" (rect 0 0 53 14)(font "Arial" (font_size 8))) 84 | (text "clk_in_25" (rect 21 27 74 41)(font "Arial" (font_size 8))) 85 | (line (pt 0 32)(pt 16 32)) 86 | ) 87 | (port 88 | (pt 160 32) 89 | (output) 90 | (text "clk_out_1" (rect 0 0 54 14)(font "Arial" (font_size 8))) 91 | (text "clk_out_1" (rect 85 27 139 41)(font "Arial" (font_size 8))) 92 | (line (pt 160 32)(pt 144 32)) 93 | ) 94 | (drawing 95 | (rectangle (rect 16 16 144 80)) 96 | ) 97 | ) 98 | (symbol 99 | (rect 1112 600 1280 696) 100 | (text "cnt-100" (rect 5 0 48 14)(font "Arial" (font_size 8))) 101 | (text "inst7" (rect 8 80 31 92)(font "Arial" )) 102 | (port 103 | (pt 0 32) 104 | (input) 105 | (text "clk_in_100" (rect 0 0 60 14)(font "Arial" (font_size 8))) 106 | (text "clk_in_100" (rect 21 27 81 41)(font "Arial" (font_size 8))) 107 | (line (pt 0 32)(pt 16 32)) 108 | ) 109 | (port 110 | (pt 168 32) 111 | (output) 112 | (text "clk_out_1" (rect 0 0 54 14)(font "Arial" (font_size 8))) 113 | (text "clk_out_1" (rect 93 27 147 41)(font "Arial" (font_size 8))) 114 | (line (pt 168 32)(pt 152 32)) 115 | ) 116 | (drawing 117 | (rectangle (rect 16 16 152 80)) 118 | ) 119 | ) 120 | (symbol 121 | (rect 928 600 1096 696) 122 | (text "cnt-100" (rect 5 0 48 14)(font "Arial" (font_size 8))) 123 | (text "inst8" (rect 8 80 31 92)(font "Arial" )) 124 | (port 125 | (pt 0 32) 126 | (input) 127 | (text "clk_in_100" (rect 0 0 60 14)(font "Arial" (font_size 8))) 128 | (text "clk_in_100" (rect 21 27 81 41)(font "Arial" (font_size 8))) 129 | (line (pt 0 32)(pt 16 32)) 130 | ) 131 | (port 132 | (pt 168 32) 133 | (output) 134 | (text "clk_out_1" (rect 0 0 54 14)(font "Arial" (font_size 8))) 135 | (text "clk_out_1" (rect 93 27 147 41)(font "Arial" (font_size 8))) 136 | (line (pt 168 32)(pt 152 32)) 137 | ) 138 | (drawing 139 | (rectangle (rect 16 16 152 80)) 140 | ) 141 | ) 142 | (connector 143 | (pt 704 632) 144 | (pt 728 632) 145 | ) 146 | (connector 147 | (pt 1280 632) 148 | (pt 1296 632) 149 | ) 150 | (connector 151 | (pt 1456 632) 152 | (pt 1512 632) 153 | ) 154 | (connector 155 | (pt 896 632) 156 | (pt 928 632) 157 | ) 158 | (connector 159 | (pt 1112 632) 160 | (pt 1096 632) 161 | ) 162 | -------------------------------------------------------------------------------- /e-clock/clk_2.bsf: -------------------------------------------------------------------------------- 1 | /* 2 | WARNING: Do NOT edit the input and output ports in this file in a text 3 | editor if you plan to continue editing the block that represents it in 4 | the Block Editor! File corruption is VERY likely to occur. 5 | */ 6 | /* 7 | Copyright (C) 1991-2013 Altera Corporation 8 | Your use of Altera Corporation's design tools, logic functions 9 | and other software and tools, and its AMPP partner logic 10 | functions, and any output files from any of the foregoing 11 | (including device programming or simulation files), and any 12 | associated documentation or information are expressly subject 13 | to the terms and conditions of the Altera Program License 14 | Subscription Agreement, Altera MegaCore Function License 15 | Agreement, or other applicable license agreement, including, 16 | without limitation, that your use is for the sole purpose of 17 | programming logic devices manufactured by Altera and sold by 18 | Altera or its authorized distributors. Please refer to the 19 | applicable agreement for further details. 20 | */ 21 | (header "symbol" (version "1.2")) 22 | (symbol 23 | (rect 16 16 136 112) 24 | (text "clk_2" (rect 5 0 34 14)(font "Arial" (font_size 8))) 25 | (text "inst" (rect 8 80 25 92)(font "Arial" )) 26 | (port 27 | (pt 0 32) 28 | (input) 29 | (text "clk_50M" (rect 0 0 40 12)(font "Arial" )) 30 | (text "clk_50M" (rect 21 27 61 39)(font "Arial" )) 31 | (line (pt 0 32)(pt 16 32)) 32 | ) 33 | (port 34 | (pt 120 32) 35 | (output) 36 | (text "clk_2" (rect 0 0 25 12)(font "Arial" )) 37 | (text "clk_2" (rect 74 27 99 39)(font "Arial" )) 38 | (line (pt 120 32)(pt 104 32)) 39 | ) 40 | (drawing 41 | (rectangle (rect 16 16 104 80)) 42 | ) 43 | ) 44 | -------------------------------------------------------------------------------- /e-clock/clk_25.bdf: -------------------------------------------------------------------------------- 1 | /* 2 | WARNING: Do NOT edit the input and output ports in this file in a text 3 | editor if you plan to continue editing the block that represents it in 4 | the Block Editor! File corruption is VERY likely to occur. 5 | */ 6 | /* 7 | Copyright (C) 1991-2013 Altera Corporation 8 | Your use of Altera Corporation's design tools, logic functions 9 | and other software and tools, and its AMPP partner logic 10 | functions, and any output files from any of the foregoing 11 | (including device programming or simulation files), and any 12 | associated documentation or information are expressly subject 13 | to the terms and conditions of the Altera Program License 14 | Subscription Agreement, Altera MegaCore Function License 15 | Agreement, or other applicable license agreement, including, 16 | without limitation, that your use is for the sole purpose of 17 | programming logic devices manufactured by Altera and sold by 18 | Altera or its authorized distributors. Please refer to the 19 | applicable agreement for further details. 20 | */ 21 | (header "graphic" (version "1.4")) 22 | (pin 23 | (input) 24 | (rect 480 320 648 336) 25 | (text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6))) 26 | (text "clk_50m" (rect 5 0 46 12)(font "Arial" )) 27 | (pt 168 8) 28 | (drawing 29 | (line (pt 84 12)(pt 109 12)) 30 | (line (pt 84 4)(pt 109 4)) 31 | (line (pt 113 8)(pt 168 8)) 32 | (line (pt 84 12)(pt 84 4)) 33 | (line (pt 109 4)(pt 113 8)) 34 | (line (pt 109 12)(pt 113 8)) 35 | ) 36 | (text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6))) 37 | ) 38 | (pin 39 | (output) 40 | (rect 1040 536 1216 552) 41 | (text "OUTPUT" (rect 137 0 175 10)(font "Arial" (font_size 6))) 42 | (text "clk_out_100" (rect 5 0 64 12)(font "Arial" )) 43 | (pt 176 8) 44 | (drawing 45 | (line (pt 176 8)(pt 124 8)) 46 | (line (pt 124 4)(pt 98 4)) 47 | (line (pt 124 12)(pt 98 12)) 48 | (line (pt 124 12)(pt 124 4)) 49 | (line (pt 98 4)(pt 94 8)) 50 | (line (pt 94 8)(pt 98 12)) 51 | (line (pt 98 12)(pt 94 8)) 52 | ) 53 | (flipy) 54 | ) 55 | (symbol 56 | (rect 656 296 824 392) 57 | (text "cnt-100" (rect 5 0 48 14)(font "Arial" (font_size 8))) 58 | (text "inst" (rect 8 80 25 92)(font "Arial" )) 59 | (port 60 | (pt 0 32) 61 | (input) 62 | (text "clk_in_100" (rect 0 0 60 14)(font "Arial" (font_size 8))) 63 | (text "clk_in_100" (rect 21 27 81 41)(font "Arial" (font_size 8))) 64 | (line (pt 0 32)(pt 16 32)) 65 | ) 66 | (port 67 | (pt 168 32) 68 | (output) 69 | (text "clk_out_1" (rect 0 0 54 14)(font "Arial" (font_size 8))) 70 | (text "clk_out_1" (rect 93 27 147 41)(font "Arial" (font_size 8))) 71 | (line (pt 168 32)(pt 152 32)) 72 | ) 73 | (drawing 74 | (rectangle (rect 16 16 152 80)) 75 | ) 76 | ) 77 | (symbol 78 | (rect 848 296 1016 392) 79 | (text "cnt-100" (rect 5 0 48 14)(font "Arial" (font_size 8))) 80 | (text "inst1" (rect 8 80 31 92)(font "Arial" )) 81 | (port 82 | (pt 0 32) 83 | (input) 84 | (text "clk_in_100" (rect 0 0 60 14)(font "Arial" (font_size 8))) 85 | (text "clk_in_100" (rect 21 27 81 41)(font "Arial" (font_size 8))) 86 | (line (pt 0 32)(pt 16 32)) 87 | ) 88 | (port 89 | (pt 168 32) 90 | (output) 91 | (text "clk_out_1" (rect 0 0 54 14)(font "Arial" (font_size 8))) 92 | (text "clk_out_1" (rect 93 27 147 41)(font "Arial" (font_size 8))) 93 | (line (pt 168 32)(pt 152 32)) 94 | ) 95 | (drawing 96 | (rectangle (rect 16 16 152 80)) 97 | ) 98 | ) 99 | (symbol 100 | (rect 1048 296 1208 392) 101 | (text "cnt-25" (rect 5 0 41 14)(font "Arial" (font_size 8))) 102 | (text "inst2" (rect 8 80 31 92)(font "Arial" )) 103 | (port 104 | (pt 0 32) 105 | (input) 106 | (text "clk_in_25" (rect 0 0 53 14)(font "Arial" (font_size 8))) 107 | (text "clk_in_25" (rect 21 27 74 41)(font "Arial" (font_size 8))) 108 | (line (pt 0 32)(pt 16 32)) 109 | ) 110 | (port 111 | (pt 160 32) 112 | (output) 113 | (text "clk_out_1" (rect 0 0 54 14)(font "Arial" (font_size 8))) 114 | (text "clk_out_1" (rect 85 27 139 41)(font "Arial" (font_size 8))) 115 | (line (pt 160 32)(pt 144 32)) 116 | ) 117 | (drawing 118 | (rectangle (rect 16 16 144 80)) 119 | ) 120 | ) 121 | (symbol 122 | (rect 1232 280 1384 376) 123 | (text "cnt-2" (rect 5 0 34 14)(font "Arial" (font_size 8))) 124 | (text "inst3" (rect 8 80 31 92)(font "Arial" )) 125 | (port 126 | (pt 0 32) 127 | (input) 128 | (text "clk_in_2" (rect 0 0 46 14)(font "Arial" (font_size 8))) 129 | (text "clk_in_2" (rect 21 27 67 41)(font "Arial" (font_size 8))) 130 | (line (pt 0 32)(pt 16 32)) 131 | ) 132 | (port 133 | (pt 152 32) 134 | (output) 135 | (text "clk_out_1" (rect 0 0 54 14)(font "Arial" (font_size 8))) 136 | (text "clk_out_1" (rect 77 27 131 41)(font "Arial" (font_size 8))) 137 | (line (pt 152 32)(pt 136 32)) 138 | ) 139 | (drawing 140 | (rectangle (rect 16 16 136 80)) 141 | ) 142 | ) 143 | (symbol 144 | (rect 1576 280 1728 376) 145 | (text "cnt-2" (rect 5 0 34 14)(font "Arial" (font_size 8))) 146 | (text "inst5" (rect 8 80 31 92)(font "Arial" )) 147 | (port 148 | (pt 0 32) 149 | (input) 150 | (text "clk_in_2" (rect 0 0 46 14)(font "Arial" (font_size 8))) 151 | (text "clk_in_2" (rect 21 27 67 41)(font "Arial" (font_size 8))) 152 | (line (pt 0 32)(pt 16 32)) 153 | ) 154 | (port 155 | (pt 152 32) 156 | (output) 157 | (text "clk_out_1" (rect 0 0 54 14)(font "Arial" (font_size 8))) 158 | (text "clk_out_1" (rect 77 27 131 41)(font "Arial" (font_size 8))) 159 | (line (pt 152 32)(pt 136 32)) 160 | ) 161 | (drawing 162 | (rectangle (rect 16 16 136 80)) 163 | ) 164 | ) 165 | (connector 166 | (pt 648 328) 167 | (pt 656 328) 168 | ) 169 | (connector 170 | (pt 824 328) 171 | (pt 848 328) 172 | ) 173 | (connector 174 | (pt 1016 328) 175 | (pt 1048 328) 176 | ) 177 | (connector 178 | (pt 1208 328) 179 | (pt 1208 312) 180 | ) 181 | (connector 182 | (pt 1208 312) 183 | (pt 1232 312) 184 | ) 185 | (connector 186 | (pt 1224 544) 187 | (pt 1224 456) 188 | ) 189 | (connector 190 | (pt 1216 544) 191 | (pt 1224 544) 192 | ) 193 | (connector 194 | (pt 1728 312) 195 | (pt 1768 312) 196 | ) 197 | (connector 198 | (pt 1768 456) 199 | (pt 1224 456) 200 | ) 201 | (connector 202 | (pt 1768 312) 203 | (pt 1768 456) 204 | ) 205 | (connector 206 | (pt 1384 312) 207 | (pt 1576 312) 208 | ) 209 | -------------------------------------------------------------------------------- /e-clock/clk_25.bsf: -------------------------------------------------------------------------------- 1 | /* 2 | WARNING: Do NOT edit the input and output ports in this file in a text 3 | editor if you plan to continue editing the block that represents it in 4 | the Block Editor! File corruption is VERY likely to occur. 5 | */ 6 | /* 7 | Copyright (C) 1991-2013 Altera Corporation 8 | Your use of Altera Corporation's design tools, logic functions 9 | and other software and tools, and its AMPP partner logic 10 | functions, and any output files from any of the foregoing 11 | (including device programming or simulation files), and any 12 | associated documentation or information are expressly subject 13 | to the terms and conditions of the Altera Program License 14 | Subscription Agreement, Altera MegaCore Function License 15 | Agreement, or other applicable license agreement, including, 16 | without limitation, that your use is for the sole purpose of 17 | programming logic devices manufactured by Altera and sold by 18 | Altera or its authorized distributors. Please refer to the 19 | applicable agreement for further details. 20 | */ 21 | (header "symbol" (version "1.2")) 22 | (symbol 23 | (rect 16 16 168 112) 24 | (text "clk_25" (rect 5 0 41 14)(font "Arial" (font_size 8))) 25 | (text "inst" (rect 8 80 25 92)(font "Arial" )) 26 | (port 27 | (pt 0 32) 28 | (input) 29 | (text "clk_50m" (rect 0 0 41 12)(font "Arial" )) 30 | (text "clk_50m" (rect 21 27 62 39)(font "Arial" )) 31 | (line (pt 0 32)(pt 16 32)) 32 | ) 33 | (port 34 | (pt 152 32) 35 | (output) 36 | (text "clk_out_100" (rect 0 0 59 12)(font "Arial" )) 37 | (text "clk_out_100" (rect 72 27 131 39)(font "Arial" )) 38 | (line (pt 152 32)(pt 136 32)) 39 | ) 40 | (drawing 41 | (rectangle (rect 16 16 136 80)) 42 | ) 43 | ) 44 | -------------------------------------------------------------------------------- /e-clock/clk_5k.bdf: -------------------------------------------------------------------------------- 1 | /* 2 | WARNING: Do NOT edit the input and output ports in this file in a text 3 | editor if you plan to continue editing the block that represents it in 4 | the Block Editor! File corruption is VERY likely to occur. 5 | */ 6 | /* 7 | Copyright (C) 1991-2013 Altera Corporation 8 | Your use of Altera Corporation's design tools, logic functions 9 | and other software and tools, and its AMPP partner logic 10 | functions, and any output files from any of the foregoing 11 | (including device programming or simulation files), and any 12 | associated documentation or information are expressly subject 13 | to the terms and conditions of the Altera Program License 14 | Subscription Agreement, Altera MegaCore Function License 15 | Agreement, or other applicable license agreement, including, 16 | without limitation, that your use is for the sole purpose of 17 | programming logic devices manufactured by Altera and sold by 18 | Altera or its authorized distributors. Please refer to the 19 | applicable agreement for further details. 20 | */ 21 | (header "graphic" (version "1.4")) 22 | (pin 23 | (input) 24 | (rect 160 304 328 320) 25 | (text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6))) 26 | (text "clk_50m" (rect 5 0 47 12)(font "Arial" )) 27 | (pt 168 8) 28 | (drawing 29 | (line (pt 84 12)(pt 109 12)) 30 | (line (pt 84 4)(pt 109 4)) 31 | (line (pt 113 8)(pt 168 8)) 32 | (line (pt 84 12)(pt 84 4)) 33 | (line (pt 109 4)(pt 113 8)) 34 | (line (pt 109 12)(pt 113 8)) 35 | ) 36 | (text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6))) 37 | ) 38 | (pin 39 | (output) 40 | (rect 720 304 896 320) 41 | (text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6))) 42 | (text "clk_out_5k" (rect 90 0 143 12)(font "Arial" )) 43 | (pt 0 8) 44 | (drawing 45 | (line (pt 0 8)(pt 52 8)) 46 | (line (pt 52 4)(pt 78 4)) 47 | (line (pt 52 12)(pt 78 12)) 48 | (line (pt 52 12)(pt 52 4)) 49 | (line (pt 78 4)(pt 82 8)) 50 | (line (pt 82 8)(pt 78 12)) 51 | (line (pt 78 12)(pt 82 8)) 52 | ) 53 | ) 54 | (symbol 55 | (rect 528 280 696 376) 56 | (text "cnt-100" (rect 5 0 48 14)(font "Arial" (font_size 8))) 57 | (text "inst" (rect 8 80 25 92)(font "Arial" )) 58 | (port 59 | (pt 0 32) 60 | (input) 61 | (text "clk_in_100" (rect 0 0 60 14)(font "Arial" (font_size 8))) 62 | (text "clk_in_100" (rect 21 27 81 41)(font "Arial" (font_size 8))) 63 | (line (pt 0 32)(pt 16 32)) 64 | ) 65 | (port 66 | (pt 168 32) 67 | (output) 68 | (text "clk_out_1" (rect 0 0 54 14)(font "Arial" (font_size 8))) 69 | (text "clk_out_1" (rect 93 27 147 41)(font "Arial" (font_size 8))) 70 | (line (pt 168 32)(pt 152 32)) 71 | ) 72 | (drawing 73 | (rectangle (rect 16 16 152 80)) 74 | ) 75 | ) 76 | (symbol 77 | (rect 336 280 504 376) 78 | (text "cnt-100" (rect 5 0 48 14)(font "Arial" (font_size 8))) 79 | (text "inst3" (rect 8 80 31 92)(font "Arial" )) 80 | (port 81 | (pt 0 32) 82 | (input) 83 | (text "clk_in_100" (rect 0 0 60 14)(font "Arial" (font_size 8))) 84 | (text "clk_in_100" (rect 21 27 81 41)(font "Arial" (font_size 8))) 85 | (line (pt 0 32)(pt 16 32)) 86 | ) 87 | (port 88 | (pt 168 32) 89 | (output) 90 | (text "clk_out_1" (rect 0 0 54 14)(font "Arial" (font_size 8))) 91 | (text "clk_out_1" (rect 93 27 147 41)(font "Arial" (font_size 8))) 92 | (line (pt 168 32)(pt 152 32)) 93 | ) 94 | (drawing 95 | (rectangle (rect 16 16 152 80)) 96 | ) 97 | ) 98 | (connector 99 | (pt 328 312) 100 | (pt 336 312) 101 | ) 102 | (connector 103 | (pt 504 312) 104 | (pt 528 312) 105 | ) 106 | (connector 107 | (pt 696 312) 108 | (pt 720 312) 109 | ) 110 | -------------------------------------------------------------------------------- /e-clock/clk_5k.bsf: -------------------------------------------------------------------------------- 1 | /* 2 | WARNING: Do NOT edit the input and output ports in this file in a text 3 | editor if you plan to continue editing the block that represents it in 4 | the Block Editor! File corruption is VERY likely to occur. 5 | */ 6 | /* 7 | Copyright (C) 1991-2013 Altera Corporation 8 | Your use of Altera Corporation's design tools, logic functions 9 | and other software and tools, and its AMPP partner logic 10 | functions, and any output files from any of the foregoing 11 | (including device programming or simulation files), and any 12 | associated documentation or information are expressly subject 13 | to the terms and conditions of the Altera Program License 14 | Subscription Agreement, Altera MegaCore Function License 15 | Agreement, or other applicable license agreement, including, 16 | without limitation, that your use is for the sole purpose of 17 | programming logic devices manufactured by Altera and sold by 18 | Altera or its authorized distributors. Please refer to the 19 | applicable agreement for further details. 20 | */ 21 | (header "symbol" (version "1.2")) 22 | (symbol 23 | (rect 16 16 176 112) 24 | (text "clk_5k" (rect 5 0 40 14)(font "Arial" (font_size 8))) 25 | (text "inst" (rect 8 80 25 92)(font "Arial" )) 26 | (port 27 | (pt 0 32) 28 | (input) 29 | (text "clk_50m" (rect 0 0 46 14)(font "Arial" (font_size 8))) 30 | (text "clk_50m" (rect 21 27 67 41)(font "Arial" (font_size 8))) 31 | (line (pt 0 32)(pt 16 32)) 32 | ) 33 | (port 34 | (pt 160 32) 35 | (output) 36 | (text "clk_out_5k" (rect 0 0 60 14)(font "Arial" (font_size 8))) 37 | (text "clk_out_5k" (rect 79 27 139 41)(font "Arial" (font_size 8))) 38 | (line (pt 160 32)(pt 144 32)) 39 | ) 40 | (drawing 41 | (rectangle (rect 16 16 144 80)) 42 | ) 43 | ) 44 | -------------------------------------------------------------------------------- /e-clock/cnt-100.bsf: -------------------------------------------------------------------------------- 1 | /* 2 | WARNING: Do NOT edit the input and output ports in this file in a text 3 | editor if you plan to continue editing the block that represents it in 4 | the Block Editor! File corruption is VERY likely to occur. 5 | */ 6 | /* 7 | Copyright (C) 1991-2013 Altera Corporation 8 | Your use of Altera Corporation's design tools, logic functions 9 | and other software and tools, and its AMPP partner logic 10 | functions, and any output files from any of the foregoing 11 | (including device programming or simulation files), and any 12 | associated documentation or information are expressly subject 13 | to the terms and conditions of the Altera Program License 14 | Subscription Agreement, Altera MegaCore Function License 15 | Agreement, or other applicable license agreement, including, 16 | without limitation, that your use is for the sole purpose of 17 | programming logic devices manufactured by Altera and sold by 18 | Altera or its authorized distributors. Please refer to the 19 | applicable agreement for further details. 20 | */ 21 | (header "symbol" (version "1.2")) 22 | (symbol 23 | (rect 16 16 184 112) 24 | (text "cnt-100" (rect 5 0 48 14)(font "Arial" (font_size 8))) 25 | (text "inst" (rect 8 80 25 92)(font "Arial" )) 26 | (port 27 | (pt 0 32) 28 | (input) 29 | (text "clk_in_100" (rect 0 0 60 14)(font "Arial" (font_size 8))) 30 | (text "clk_in_100" (rect 21 27 81 41)(font "Arial" (font_size 8))) 31 | (line (pt 0 32)(pt 16 32)) 32 | ) 33 | (port 34 | (pt 168 32) 35 | (output) 36 | (text "clk_out_1" (rect 0 0 54 14)(font "Arial" (font_size 8))) 37 | (text "clk_out_1" (rect 93 27 147 41)(font "Arial" (font_size 8))) 38 | (line (pt 168 32)(pt 152 32)) 39 | ) 40 | (drawing 41 | (rectangle (rect 16 16 152 80)) 42 | ) 43 | ) 44 | -------------------------------------------------------------------------------- /e-clock/cnt-2.bdf: -------------------------------------------------------------------------------- 1 | /* 2 | WARNING: Do NOT edit the input and output ports in this file in a text 3 | editor if you plan to continue editing the block that represents it in 4 | the Block Editor! File corruption is VERY likely to occur. 5 | */ 6 | /* 7 | Copyright (C) 1991-2013 Altera Corporation 8 | Your use of Altera Corporation's design tools, logic functions 9 | and other software and tools, and its AMPP partner logic 10 | functions, and any output files from any of the foregoing 11 | (including device programming or simulation files), and any 12 | associated documentation or information are expressly subject 13 | to the terms and conditions of the Altera Program License 14 | Subscription Agreement, Altera MegaCore Function License 15 | Agreement, or other applicable license agreement, including, 16 | without limitation, that your use is for the sole purpose of 17 | programming logic devices manufactured by Altera and sold by 18 | Altera or its authorized distributors. Please refer to the 19 | applicable agreement for further details. 20 | */ 21 | (header "graphic" (version "1.4")) 22 | (pin 23 | (input) 24 | (rect 512 320 680 336) 25 | (text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6))) 26 | (text "clk_in_2" (rect 5 0 46 12)(font "Arial" )) 27 | (pt 168 8) 28 | (drawing 29 | (line (pt 84 12)(pt 109 12)) 30 | (line (pt 84 4)(pt 109 4)) 31 | (line (pt 113 8)(pt 168 8)) 32 | (line (pt 84 12)(pt 84 4)) 33 | (line (pt 109 4)(pt 113 8)) 34 | (line (pt 109 12)(pt 113 8)) 35 | ) 36 | (text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6))) 37 | ) 38 | (pin 39 | (output) 40 | (rect 840 304 1016 320) 41 | (text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6))) 42 | (text "clk_out_1" (rect 90 0 137 12)(font "Arial" )) 43 | (pt 0 8) 44 | (drawing 45 | (line (pt 0 8)(pt 52 8)) 46 | (line (pt 52 4)(pt 78 4)) 47 | (line (pt 52 12)(pt 78 12)) 48 | (line (pt 52 12)(pt 52 4)) 49 | (line (pt 78 4)(pt 82 8)) 50 | (line (pt 82 8)(pt 78 12)) 51 | (line (pt 78 12)(pt 82 8)) 52 | ) 53 | ) 54 | (symbol 55 | (rect 728 288 792 368) 56 | (text "DFF" (rect 1 0 19 10)(font "Arial" (font_size 6))) 57 | (text "inst" (rect 3 68 20 80)(font "Arial" )) 58 | (port 59 | (pt 32 80) 60 | (input) 61 | (text "CLRN" (rect 21 59 44 71)(font "Courier New" (bold))) 62 | (text "CLRN" (rect 21 58 44 70)(font "Courier New" (bold))) 63 | (line (pt 32 80)(pt 32 76)) 64 | ) 65 | (port 66 | (pt 0 40) 67 | (input) 68 | (text "CLK" (rect 3 29 20 41)(font "Courier New" (bold))(invisible)) 69 | (text "CLK" (rect 3 29 20 41)(font "Courier New" (bold))(invisible)) 70 | (line (pt 0 40)(pt 12 40)) 71 | ) 72 | (port 73 | (pt 0 24) 74 | (input) 75 | (text "D" (rect 14 20 19 32)(font "Courier New" (bold))) 76 | (text "D" (rect 14 20 19 32)(font "Courier New" (bold))) 77 | (line (pt 0 24)(pt 12 24)) 78 | ) 79 | (port 80 | (pt 32 0) 81 | (input) 82 | (text "PRN" (rect 24 13 41 25)(font "Courier New" (bold))) 83 | (text "PRN" (rect 24 11 41 23)(font "Courier New" (bold))) 84 | (line (pt 32 4)(pt 32 0)) 85 | ) 86 | (port 87 | (pt 64 24) 88 | (output) 89 | (text "Q" (rect 45 20 50 32)(font "Courier New" (bold))) 90 | (text "Q" (rect 43 20 48 32)(font "Courier New" (bold))) 91 | (line (pt 52 24)(pt 64 24)) 92 | ) 93 | (drawing 94 | (line (pt 12 12)(pt 52 12)) 95 | (line (pt 12 68)(pt 52 68)) 96 | (line (pt 52 68)(pt 52 12)) 97 | (line (pt 12 68)(pt 12 12)) 98 | (line (pt 19 40)(pt 12 47)) 99 | (line (pt 12 32)(pt 20 40)) 100 | (circle (rect 28 4 36 12)) 101 | (circle (rect 28 68 36 76)) 102 | ) 103 | ) 104 | (symbol 105 | (rect 744 240 776 256) 106 | (text "VCC" (rect 7 0 27 10)(font "Arial" (font_size 6))) 107 | (text "inst2" (rect 3 5 26 17)(font "Arial" )(invisible)) 108 | (port 109 | (pt 16 16) 110 | (output) 111 | (text "1" (rect 19 7 24 19)(font "Courier New" (bold))(invisible)) 112 | (text "1" (rect 19 7 24 19)(font "Courier New" (bold))(invisible)) 113 | (line (pt 16 16)(pt 16 8)) 114 | ) 115 | (drawing 116 | (line (pt 8 8)(pt 24 8)) 117 | ) 118 | ) 119 | (symbol 120 | (rect 736 384 784 416) 121 | (text "NOT" (rect 27 0 47 10)(font "Arial" (font_size 6))) 122 | (text "inst4" (rect 22 21 45 33)(font "Arial" )) 123 | (port 124 | (pt 48 16) 125 | (input) 126 | (text "IN" (rect 2 7 13 19)(font "Courier New" (bold))(invisible)) 127 | (text "IN" (rect 35 7 46 19)(font "Courier New" (bold))(invisible)) 128 | (line (pt 48 16)(pt 35 16)) 129 | ) 130 | (port 131 | (pt 0 16) 132 | (output) 133 | (text "OUT" (rect 32 7 49 19)(font "Courier New" (bold))(invisible)) 134 | (text "OUT" (rect -1 7 16 19)(font "Courier New" (bold))(invisible)) 135 | (line (pt 9 16)(pt 0 16)) 136 | ) 137 | (drawing 138 | (line (pt 35 25)(pt 35 7)) 139 | (line (pt 35 7)(pt 17 16)) 140 | (line (pt 35 25)(pt 17 16)) 141 | (circle (rect 9 12 17 20)) 142 | ) 143 | (flipy) 144 | ) 145 | (connector 146 | (pt 680 328) 147 | (pt 728 328) 148 | ) 149 | (connector 150 | (pt 728 312) 151 | (pt 704 312) 152 | ) 153 | (connector 154 | (pt 760 368) 155 | (pt 760 376) 156 | ) 157 | (connector 158 | (pt 760 376) 159 | (pt 808 376) 160 | ) 161 | (connector 162 | (pt 808 376) 163 | (pt 808 264) 164 | ) 165 | (connector 166 | (pt 808 264) 167 | (pt 760 264) 168 | ) 169 | (connector 170 | (pt 760 256) 171 | (pt 760 264) 172 | ) 173 | (connector 174 | (pt 760 264) 175 | (pt 760 288) 176 | ) 177 | (connector 178 | (pt 704 312) 179 | (pt 704 400) 180 | ) 181 | (connector 182 | (pt 704 400) 183 | (pt 736 400) 184 | ) 185 | (connector 186 | (pt 824 400) 187 | (pt 784 400) 188 | ) 189 | (connector 190 | (pt 824 312) 191 | (pt 824 400) 192 | ) 193 | (connector 194 | (pt 792 312) 195 | (pt 824 312) 196 | ) 197 | (connector 198 | (pt 824 312) 199 | (pt 840 312) 200 | ) 201 | (junction (pt 824 312)) 202 | (junction (pt 760 264)) 203 | -------------------------------------------------------------------------------- /e-clock/cnt-2.bsf: -------------------------------------------------------------------------------- 1 | /* 2 | WARNING: Do NOT edit the input and output ports in this file in a text 3 | editor if you plan to continue editing the block that represents it in 4 | the Block Editor! File corruption is VERY likely to occur. 5 | */ 6 | /* 7 | Copyright (C) 1991-2013 Altera Corporation 8 | Your use of Altera Corporation's design tools, logic functions 9 | and other software and tools, and its AMPP partner logic 10 | functions, and any output files from any of the foregoing 11 | (including device programming or simulation files), and any 12 | associated documentation or information are expressly subject 13 | to the terms and conditions of the Altera Program License 14 | Subscription Agreement, Altera MegaCore Function License 15 | Agreement, or other applicable license agreement, including, 16 | without limitation, that your use is for the sole purpose of 17 | programming logic devices manufactured by Altera and sold by 18 | Altera or its authorized distributors. Please refer to the 19 | applicable agreement for further details. 20 | */ 21 | (header "symbol" (version "1.2")) 22 | (symbol 23 | (rect 16 16 168 112) 24 | (text "cnt-2" (rect 5 0 34 14)(font "Arial" (font_size 8))) 25 | (text "inst" (rect 8 80 25 92)(font "Arial" )) 26 | (port 27 | (pt 0 32) 28 | (input) 29 | (text "clk_in_2" (rect 0 0 46 14)(font "Arial" (font_size 8))) 30 | (text "clk_in_2" (rect 21 27 67 41)(font "Arial" (font_size 8))) 31 | (line (pt 0 32)(pt 16 32)) 32 | ) 33 | (port 34 | (pt 152 32) 35 | (output) 36 | (text "clk_out_1" (rect 0 0 54 14)(font "Arial" (font_size 8))) 37 | (text "clk_out_1" (rect 77 27 131 41)(font "Arial" (font_size 8))) 38 | (line (pt 152 32)(pt 136 32)) 39 | ) 40 | (drawing 41 | (rectangle (rect 16 16 136 80)) 42 | ) 43 | ) 44 | -------------------------------------------------------------------------------- /e-clock/cnt-25.bsf: -------------------------------------------------------------------------------- 1 | /* 2 | WARNING: Do NOT edit the input and output ports in this file in a text 3 | editor if you plan to continue editing the block that represents it in 4 | the Block Editor! File corruption is VERY likely to occur. 5 | */ 6 | /* 7 | Copyright (C) 1991-2013 Altera Corporation 8 | Your use of Altera Corporation's design tools, logic functions 9 | and other software and tools, and its AMPP partner logic 10 | functions, and any output files from any of the foregoing 11 | (including device programming or simulation files), and any 12 | associated documentation or information are expressly subject 13 | to the terms and conditions of the Altera Program License 14 | Subscription Agreement, Altera MegaCore Function License 15 | Agreement, or other applicable license agreement, including, 16 | without limitation, that your use is for the sole purpose of 17 | programming logic devices manufactured by Altera and sold by 18 | Altera or its authorized distributors. Please refer to the 19 | applicable agreement for further details. 20 | */ 21 | (header "symbol" (version "1.2")) 22 | (symbol 23 | (rect 16 16 176 112) 24 | (text "cnt-25" (rect 5 0 41 14)(font "Arial" (font_size 8))) 25 | (text "inst" (rect 8 80 25 92)(font "Arial" )) 26 | (port 27 | (pt 0 32) 28 | (input) 29 | (text "clk_in_25" (rect 0 0 53 14)(font "Arial" (font_size 8))) 30 | (text "clk_in_25" (rect 21 27 74 41)(font "Arial" (font_size 8))) 31 | (line (pt 0 32)(pt 16 32)) 32 | ) 33 | (port 34 | (pt 160 32) 35 | (output) 36 | (text "clk_out_1" (rect 0 0 54 14)(font "Arial" (font_size 8))) 37 | (text "clk_out_1" (rect 85 27 139 41)(font "Arial" (font_size 8))) 38 | (line (pt 160 32)(pt 144 32)) 39 | ) 40 | (drawing 41 | (rectangle (rect 16 16 144 80)) 42 | ) 43 | ) 44 | -------------------------------------------------------------------------------- /e-clock/cnt100plus.bsf: -------------------------------------------------------------------------------- 1 | /* 2 | WARNING: Do NOT edit the input and output ports in this file in a text 3 | editor if you plan to continue editing the block that represents it in 4 | the Block Editor! File corruption is VERY likely to occur. 5 | */ 6 | /* 7 | Copyright (C) 1991-2013 Altera Corporation 8 | Your use of Altera Corporation's design tools, logic functions 9 | and other software and tools, and its AMPP partner logic 10 | functions, and any output files from any of the foregoing 11 | (including device programming or simulation files), and any 12 | associated documentation or information are expressly subject 13 | to the terms and conditions of the Altera Program License 14 | Subscription Agreement, Altera MegaCore Function License 15 | Agreement, or other applicable license agreement, including, 16 | without limitation, that your use is for the sole purpose of 17 | programming logic devices manufactured by Altera and sold by 18 | Altera or its authorized distributors. Please refer to the 19 | applicable agreement for further details. 20 | */ 21 | (header "symbol" (version "1.2")) 22 | (symbol 23 | (rect 16 16 184 208) 24 | (text "cnt100plus" (rect 5 0 67 14)(font "Arial" (font_size 8))) 25 | (text "inst" (rect 8 176 25 188)(font "Arial" )) 26 | (port 27 | (pt 0 32) 28 | (input) 29 | (text "clk_in_100" (rect 0 0 60 14)(font "Arial" (font_size 8))) 30 | (text "clk_in_100" (rect 21 27 81 41)(font "Arial" (font_size 8))) 31 | (line (pt 0 32)(pt 16 32)) 32 | ) 33 | (port 34 | (pt 168 32) 35 | (output) 36 | (text "s11" (rect 0 0 21 14)(font "Arial" (font_size 8))) 37 | (text "s11" (rect 126 27 147 41)(font "Arial" (font_size 8))) 38 | (line (pt 168 32)(pt 152 32)) 39 | ) 40 | (port 41 | (pt 168 48) 42 | (output) 43 | (text "s12" (rect 0 0 21 14)(font "Arial" (font_size 8))) 44 | (text "s12" (rect 126 43 147 57)(font "Arial" (font_size 8))) 45 | (line (pt 168 48)(pt 152 48)) 46 | ) 47 | (port 48 | (pt 168 64) 49 | (output) 50 | (text "s13" (rect 0 0 21 14)(font "Arial" (font_size 8))) 51 | (text "s13" (rect 126 59 147 73)(font "Arial" (font_size 8))) 52 | (line (pt 168 64)(pt 152 64)) 53 | ) 54 | (port 55 | (pt 168 80) 56 | (output) 57 | (text "s14" (rect 0 0 21 14)(font "Arial" (font_size 8))) 58 | (text "s14" (rect 126 75 147 89)(font "Arial" (font_size 8))) 59 | (line (pt 168 80)(pt 152 80)) 60 | ) 61 | (port 62 | (pt 168 96) 63 | (output) 64 | (text "s15" (rect 0 0 21 14)(font "Arial" (font_size 8))) 65 | (text "s15" (rect 126 91 147 105)(font "Arial" (font_size 8))) 66 | (line (pt 168 96)(pt 152 96)) 67 | ) 68 | (port 69 | (pt 168 112) 70 | (output) 71 | (text "s16" (rect 0 0 21 14)(font "Arial" (font_size 8))) 72 | (text "s16" (rect 126 107 147 121)(font "Arial" (font_size 8))) 73 | (line (pt 168 112)(pt 152 112)) 74 | ) 75 | (port 76 | (pt 168 128) 77 | (output) 78 | (text "s17" (rect 0 0 21 14)(font "Arial" (font_size 8))) 79 | (text "s17" (rect 126 123 147 137)(font "Arial" (font_size 8))) 80 | (line (pt 168 128)(pt 152 128)) 81 | ) 82 | (port 83 | (pt 168 144) 84 | (output) 85 | (text "s18" (rect 0 0 21 14)(font "Arial" (font_size 8))) 86 | (text "s18" (rect 126 139 147 153)(font "Arial" (font_size 8))) 87 | (line (pt 168 144)(pt 152 144)) 88 | ) 89 | (port 90 | (pt 168 160) 91 | (output) 92 | (text "clk_out_1" (rect 0 0 54 14)(font "Arial" (font_size 8))) 93 | (text "clk_out_1" (rect 93 155 147 169)(font "Arial" (font_size 8))) 94 | (line (pt 168 160)(pt 152 160)) 95 | ) 96 | (drawing 97 | (rectangle (rect 16 16 152 176)) 98 | ) 99 | ) 100 | -------------------------------------------------------------------------------- /e-clock/cnt100plus.vwf: -------------------------------------------------------------------------------- 1 | /* 2 | WARNING: Do NOT edit the input and output ports in this file in a text 3 | editor if you plan to continue editing the block that represents it in 4 | the Block Editor! File corruption is VERY likely to occur. 5 | */ 6 | 7 | /* 8 | Copyright (C) 1991-2013 Altera Corporation 9 | Your use of Altera Corporation's design tools, logic functions 10 | and other software and tools, and its AMPP partner logic 11 | functions, and any output files from any of the foregoing 12 | (including device programming or simulation files), and any 13 | associated documentation or information are expressly subject 14 | to the terms and conditions of the Altera Program License 15 | Subscription Agreement, Altera MegaCore Function License 16 | Agreement, or other applicable license agreement, including, 17 | without limitation, that your use is for the sole purpose of 18 | programming logic devices manufactured by Altera and sold by 19 | Altera or its authorized distributors. Please refer to the 20 | applicable agreement for further details. 21 | */ 22 | 23 | HEADER 24 | { 25 | VERSION = 1; 26 | TIME_UNIT = ns; 27 | DATA_OFFSET = 0.0; 28 | DATA_DURATION = 1000.0; 29 | SIMULATION_TIME = 0.0; 30 | GRID_PHASE = 0.0; 31 | GRID_PERIOD = 10.0; 32 | GRID_DUTY_CYCLE = 50; 33 | } 34 | 35 | SIGNAL("clk_in_100") 36 | { 37 | VALUE_TYPE = NINE_LEVEL_BIT; 38 | SIGNAL_TYPE = SINGLE_BIT; 39 | WIDTH = 1; 40 | LSB_INDEX = -1; 41 | DIRECTION = INPUT; 42 | PARENT = ""; 43 | } 44 | 45 | SIGNAL("clk_out_1") 46 | { 47 | VALUE_TYPE = NINE_LEVEL_BIT; 48 | SIGNAL_TYPE = SINGLE_BIT; 49 | WIDTH = 1; 50 | LSB_INDEX = -1; 51 | DIRECTION = OUTPUT; 52 | PARENT = ""; 53 | } 54 | 55 | SIGNAL("s11") 56 | { 57 | VALUE_TYPE = NINE_LEVEL_BIT; 58 | SIGNAL_TYPE = SINGLE_BIT; 59 | WIDTH = 1; 60 | LSB_INDEX = -1; 61 | DIRECTION = OUTPUT; 62 | PARENT = ""; 63 | } 64 | 65 | SIGNAL("s12") 66 | { 67 | VALUE_TYPE = NINE_LEVEL_BIT; 68 | SIGNAL_TYPE = SINGLE_BIT; 69 | WIDTH = 1; 70 | LSB_INDEX = -1; 71 | DIRECTION = OUTPUT; 72 | PARENT = ""; 73 | } 74 | 75 | SIGNAL("s13") 76 | { 77 | VALUE_TYPE = NINE_LEVEL_BIT; 78 | SIGNAL_TYPE = SINGLE_BIT; 79 | WIDTH = 1; 80 | LSB_INDEX = -1; 81 | DIRECTION = OUTPUT; 82 | PARENT = ""; 83 | } 84 | 85 | SIGNAL("s14") 86 | { 87 | VALUE_TYPE = NINE_LEVEL_BIT; 88 | SIGNAL_TYPE = SINGLE_BIT; 89 | WIDTH = 1; 90 | LSB_INDEX = -1; 91 | DIRECTION = OUTPUT; 92 | PARENT = ""; 93 | } 94 | 95 | SIGNAL("s15") 96 | { 97 | VALUE_TYPE = NINE_LEVEL_BIT; 98 | SIGNAL_TYPE = SINGLE_BIT; 99 | WIDTH = 1; 100 | LSB_INDEX = -1; 101 | DIRECTION = OUTPUT; 102 | PARENT = ""; 103 | } 104 | 105 | SIGNAL("s16") 106 | { 107 | VALUE_TYPE = NINE_LEVEL_BIT; 108 | SIGNAL_TYPE = SINGLE_BIT; 109 | WIDTH = 1; 110 | LSB_INDEX = -1; 111 | DIRECTION = OUTPUT; 112 | PARENT = ""; 113 | } 114 | 115 | SIGNAL("s17") 116 | { 117 | VALUE_TYPE = NINE_LEVEL_BIT; 118 | SIGNAL_TYPE = SINGLE_BIT; 119 | WIDTH = 1; 120 | LSB_INDEX = -1; 121 | DIRECTION = OUTPUT; 122 | PARENT = ""; 123 | } 124 | 125 | SIGNAL("s18") 126 | { 127 | VALUE_TYPE = NINE_LEVEL_BIT; 128 | SIGNAL_TYPE = SINGLE_BIT; 129 | WIDTH = 1; 130 | LSB_INDEX = -1; 131 | DIRECTION = OUTPUT; 132 | PARENT = ""; 133 | } 134 | 135 | TRANSITION_LIST("clk_in_100") 136 | { 137 | NODE 138 | { 139 | REPEAT = 1; 140 | NODE 141 | { 142 | REPEAT = 100; 143 | LEVEL 0 FOR 5.0; 144 | LEVEL 1 FOR 5.0; 145 | } 146 | } 147 | } 148 | 149 | TRANSITION_LIST("clk_out_1") 150 | { 151 | NODE 152 | { 153 | REPEAT = 1; 154 | LEVEL X FOR 1000.0; 155 | } 156 | } 157 | 158 | TRANSITION_LIST("s11") 159 | { 160 | NODE 161 | { 162 | REPEAT = 1; 163 | LEVEL X FOR 1000.0; 164 | } 165 | } 166 | 167 | TRANSITION_LIST("s12") 168 | { 169 | NODE 170 | { 171 | REPEAT = 1; 172 | LEVEL X FOR 1000.0; 173 | } 174 | } 175 | 176 | TRANSITION_LIST("s13") 177 | { 178 | NODE 179 | { 180 | REPEAT = 1; 181 | LEVEL X FOR 1000.0; 182 | } 183 | } 184 | 185 | TRANSITION_LIST("s14") 186 | { 187 | NODE 188 | { 189 | REPEAT = 1; 190 | LEVEL X FOR 1000.0; 191 | } 192 | } 193 | 194 | TRANSITION_LIST("s15") 195 | { 196 | NODE 197 | { 198 | REPEAT = 1; 199 | LEVEL X FOR 1000.0; 200 | } 201 | } 202 | 203 | TRANSITION_LIST("s16") 204 | { 205 | NODE 206 | { 207 | REPEAT = 1; 208 | LEVEL X FOR 1000.0; 209 | } 210 | } 211 | 212 | TRANSITION_LIST("s17") 213 | { 214 | NODE 215 | { 216 | REPEAT = 1; 217 | LEVEL X FOR 1000.0; 218 | } 219 | } 220 | 221 | TRANSITION_LIST("s18") 222 | { 223 | NODE 224 | { 225 | REPEAT = 1; 226 | LEVEL X FOR 1000.0; 227 | } 228 | } 229 | 230 | DISPLAY_LINE 231 | { 232 | CHANNEL = "clk_in_100"; 233 | EXPAND_STATUS = COLLAPSED; 234 | RADIX = Binary; 235 | TREE_INDEX = 0; 236 | TREE_LEVEL = 0; 237 | } 238 | 239 | DISPLAY_LINE 240 | { 241 | CHANNEL = "clk_out_1"; 242 | EXPAND_STATUS = COLLAPSED; 243 | RADIX = Binary; 244 | TREE_INDEX = 1; 245 | TREE_LEVEL = 0; 246 | } 247 | 248 | DISPLAY_LINE 249 | { 250 | CHANNEL = "s11"; 251 | EXPAND_STATUS = COLLAPSED; 252 | RADIX = Binary; 253 | TREE_INDEX = 2; 254 | TREE_LEVEL = 0; 255 | } 256 | 257 | DISPLAY_LINE 258 | { 259 | CHANNEL = "s12"; 260 | EXPAND_STATUS = COLLAPSED; 261 | RADIX = Binary; 262 | TREE_INDEX = 3; 263 | TREE_LEVEL = 0; 264 | } 265 | 266 | DISPLAY_LINE 267 | { 268 | CHANNEL = "s13"; 269 | EXPAND_STATUS = COLLAPSED; 270 | RADIX = Binary; 271 | TREE_INDEX = 4; 272 | TREE_LEVEL = 0; 273 | } 274 | 275 | DISPLAY_LINE 276 | { 277 | CHANNEL = "s14"; 278 | EXPAND_STATUS = COLLAPSED; 279 | RADIX = Binary; 280 | TREE_INDEX = 5; 281 | TREE_LEVEL = 0; 282 | } 283 | 284 | DISPLAY_LINE 285 | { 286 | CHANNEL = "s15"; 287 | EXPAND_STATUS = COLLAPSED; 288 | RADIX = Binary; 289 | TREE_INDEX = 6; 290 | TREE_LEVEL = 0; 291 | } 292 | 293 | DISPLAY_LINE 294 | { 295 | CHANNEL = "s16"; 296 | EXPAND_STATUS = COLLAPSED; 297 | RADIX = Binary; 298 | TREE_INDEX = 7; 299 | TREE_LEVEL = 0; 300 | } 301 | 302 | DISPLAY_LINE 303 | { 304 | CHANNEL = "s17"; 305 | EXPAND_STATUS = COLLAPSED; 306 | RADIX = Binary; 307 | TREE_INDEX = 8; 308 | TREE_LEVEL = 0; 309 | } 310 | 311 | DISPLAY_LINE 312 | { 313 | CHANNEL = "s18"; 314 | EXPAND_STATUS = COLLAPSED; 315 | RADIX = Binary; 316 | TREE_INDEX = 9; 317 | TREE_LEVEL = 0; 318 | } 319 | 320 | TIME_BAR 321 | { 322 | TIME = 0; 323 | MASTER = TRUE; 324 | } 325 | ; 326 | -------------------------------------------------------------------------------- /e-clock/db/.cmp.kpt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CodeAlanqian/e-clock/ac6929bfe0df785b47a94b848983913f0d3df45b/e-clock/db/.cmp.kpt -------------------------------------------------------------------------------- /e-clock/db/LSD.(0).cnf.cdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CodeAlanqian/e-clock/ac6929bfe0df785b47a94b848983913f0d3df45b/e-clock/db/LSD.(0).cnf.cdb -------------------------------------------------------------------------------- /e-clock/db/LSD.(0).cnf.hdb: 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64-Bit " "Running Quartus II 64-Bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Full Version " "Version 13.1.0 Build 162 10/23/2013 SJ Full Version" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1684857217457 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue May 23 23:53:37 2023 " "Processing started: Tue May 23 23:53:37 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1684857217457 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1684857217457 ""} 3 | { "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off e-clock -c LSD " "Command: quartus_asm --read_settings_files=off --write_settings_files=off e-clock -c LSD" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1684857217457 ""} 4 | { "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1684857217977 ""} 5 | { "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1684857217994 ""} 6 | { "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 64-Bit " "Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4578 " "Peak virtual memory: 4578 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1684857218163 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue May 23 23:53:38 2023 " "Processing ended: Tue May 23 23:53:38 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1684857218163 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1684857218163 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1684857218163 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1684857218163 ""} 7 | -------------------------------------------------------------------------------- /e-clock/db/LSD.asm.rdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CodeAlanqian/e-clock/ac6929bfe0df785b47a94b848983913f0d3df45b/e-clock/db/LSD.asm.rdb -------------------------------------------------------------------------------- /e-clock/db/LSD.asm_labs.ddb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CodeAlanqian/e-clock/ac6929bfe0df785b47a94b848983913f0d3df45b/e-clock/db/LSD.asm_labs.ddb -------------------------------------------------------------------------------- /e-clock/db/LSD.cbx.xml: -------------------------------------------------------------------------------- 1 | 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-------------------------------------------------------------------------------- 1 | { "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1684857227950 ""} 2 | { "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus II 64-Bit " "Running Quartus II 64-Bit EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Full Version " "Version 13.1.0 Build 162 10/23/2013 SJ Full Version" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1684857227950 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue May 23 23:53:47 2023 " "Processing started: Tue May 23 23:53:47 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1684857227950 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1684857227950 ""} 3 | { "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off e-clock -c LSD " "Command: quartus_eda --read_settings_files=off --write_settings_files=off e-clock -c LSD" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1684857227950 ""} 4 | { "Info" "IWSC_DONE_HDL_GENERATION" "LSD.vo E:/DC_WS/clock/Test01/simulation/qsim// simulation " "Generated file LSD.vo in folder \"E:/DC_WS/clock/Test01/simulation/qsim//\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1684857228324 ""} 5 | { "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 0 s Quartus II 64-Bit " "Quartus II 64-Bit EDA Netlist Writer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4554 " "Peak virtual memory: 4554 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1684857228370 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue May 23 23:53:48 2023 " "Processing ended: Tue May 23 23:53:48 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1684857228370 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1684857228370 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1684857228370 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1684857228370 ""} 6 | -------------------------------------------------------------------------------- /e-clock/db/LSD.hif: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CodeAlanqian/e-clock/ac6929bfe0df785b47a94b848983913f0d3df45b/e-clock/db/LSD.hif -------------------------------------------------------------------------------- /e-clock/db/LSD.ipinfo: -------------------------------------------------------------------------------- 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-------------------------------------------------------------------------------- /e-clock/e-clock.qpf: -------------------------------------------------------------------------------- 1 | # -------------------------------------------------------------------------- # 2 | # 3 | # Copyright (C) 1991-2013 Altera Corporation 4 | # Your use of Altera Corporation's design tools, logic functions 5 | # and other software and tools, and its AMPP partner logic 6 | # functions, and any output files from any of the foregoing 7 | # (including device programming or simulation files), and any 8 | # associated documentation or information are expressly subject 9 | # to the terms and conditions of the Altera Program License 10 | # Subscription Agreement, Altera MegaCore Function License 11 | # Agreement, or other applicable license agreement, including, 12 | # without limitation, that your use is for the sole purpose of 13 | # programming logic devices manufactured by Altera and sold by 14 | # Altera or its authorized distributors. Please refer to the 15 | # applicable agreement for further details. 16 | # 17 | # -------------------------------------------------------------------------- # 18 | # 19 | # Quartus II 64-Bit 20 | # Version 13.1.0 Build 162 10/23/2013 SJ Full Version 21 | # Date created = 08:45:25 October 21, 2022 22 | # 23 | # -------------------------------------------------------------------------- # 24 | 25 | QUARTUS_VERSION = "13.1" 26 | DATE = "08:45:25 October 21, 2022" 27 | 28 | # Revisions 29 | 30 | PROJECT_REVISION = "LSD" 31 | -------------------------------------------------------------------------------- /e-clock/hour.bsf: -------------------------------------------------------------------------------- 1 | /* 2 | WARNING: Do NOT edit the input and output ports in this file in a text 3 | editor if you plan to continue editing the block that represents it in 4 | the Block Editor! File corruption is VERY likely to occur. 5 | */ 6 | /* 7 | Copyright (C) 1991-2013 Altera Corporation 8 | Your use of Altera Corporation's design tools, logic functions 9 | and other software and tools, and its AMPP partner logic 10 | functions, and any output files from any of the foregoing 11 | (including device programming or simulation files), and any 12 | associated documentation or information are expressly subject 13 | to the terms and conditions of the Altera Program License 14 | Subscription Agreement, Altera MegaCore Function License 15 | Agreement, or other applicable license agreement, including, 16 | without limitation, that your use is for the sole purpose of 17 | programming logic devices manufactured by Altera and sold by 18 | Altera or its authorized distributors. Please refer to the 19 | applicable agreement for further details. 20 | */ 21 | (header "symbol" (version "1.2")) 22 | (symbol 23 | (rect 16 16 152 112) 24 | (text "hour" (rect 5 0 30 14)(font "Arial" (font_size 8))) 25 | (text "inst" (rect 8 80 25 92)(font "Arial" )) 26 | (port 27 | (pt 0 32) 28 | (input) 29 | (text "hour_clk" (rect 0 0 41 12)(font "Arial" )) 30 | (text "hour_clk" (rect 21 27 62 39)(font "Arial" )) 31 | (line (pt 0 32)(pt 16 32)) 32 | ) 33 | (port 34 | (pt 0 48) 35 | (input) 36 | (text "RD" (rect 0 0 16 12)(font "Arial" )) 37 | (text "RD" (rect 21 43 37 55)(font "Arial" )) 38 | (line (pt 0 48)(pt 16 48)) 39 | ) 40 | (port 41 | (pt 0 64) 42 | (input) 43 | (text "SC" (rect 0 0 15 12)(font "Arial" )) 44 | (text "SC" (rect 21 59 36 71)(font "Arial" )) 45 | (line (pt 0 64)(pt 16 64)) 46 | ) 47 | (port 48 | (pt 136 32) 49 | (output) 50 | (text "HL[3..0]" (rect 0 0 40 12)(font "Arial" )) 51 | (text "HL[3..0]" (rect 75 27 115 39)(font "Arial" )) 52 | (line (pt 136 32)(pt 120 32)(line_width 3)) 53 | ) 54 | (port 55 | (pt 136 48) 56 | (output) 57 | (text "HH[3..0]" (rect 0 0 42 12)(font "Arial" )) 58 | (text "HH[3..0]" (rect 73 43 115 55)(font "Arial" )) 59 | (line (pt 136 48)(pt 120 48)(line_width 3)) 60 | ) 61 | (port 62 | (pt 136 64) 63 | (output) 64 | (text "HC" (rect 0 0 16 12)(font "Arial" )) 65 | (text "HC" (rect 99 59 115 71)(font "Arial" )) 66 | (line (pt 136 64)(pt 120 64)) 67 | ) 68 | (drawing 69 | (rectangle (rect 16 16 120 80)) 70 | ) 71 | ) 72 | -------------------------------------------------------------------------------- /e-clock/hour12.bsf: -------------------------------------------------------------------------------- 1 | /* 2 | WARNING: Do NOT edit the input and output ports in this file in a text 3 | editor if you plan to continue editing the block that represents it in 4 | the Block Editor! File corruption is VERY likely to occur. 5 | */ 6 | /* 7 | Copyright (C) 1991-2013 Altera Corporation 8 | Your use of Altera Corporation's design tools, logic functions 9 | and other software and tools, and its AMPP partner logic 10 | functions, and any output files from any of the foregoing 11 | (including device programming or simulation files), and any 12 | associated documentation or information are expressly subject 13 | to the terms and conditions of the Altera Program License 14 | Subscription Agreement, Altera MegaCore Function License 15 | Agreement, or other applicable license agreement, including, 16 | without limitation, that your use is for the sole purpose of 17 | programming logic devices manufactured by Altera and sold by 18 | Altera or its authorized distributors. Please refer to the 19 | applicable agreement for further details. 20 | */ 21 | (header "symbol" (version "1.2")) 22 | (symbol 23 | (rect 16 16 152 112) 24 | (text "hour12" (rect 5 0 45 14)(font "Arial" (font_size 8))) 25 | (text "inst" (rect 8 80 25 92)(font "Arial" )) 26 | (port 27 | (pt 0 32) 28 | (input) 29 | (text "hour_clk" (rect 0 0 41 12)(font "Arial" )) 30 | (text "hour_clk" (rect 21 27 62 39)(font "Arial" )) 31 | (line (pt 0 32)(pt 16 32)) 32 | ) 33 | (port 34 | (pt 0 48) 35 | (input) 36 | (text "RD" (rect 0 0 16 12)(font "Arial" )) 37 | (text "RD" (rect 21 43 37 55)(font "Arial" )) 38 | (line (pt 0 48)(pt 16 48)) 39 | ) 40 | (port 41 | (pt 0 64) 42 | (input) 43 | (text "SC" (rect 0 0 15 12)(font "Arial" )) 44 | (text "SC" (rect 21 59 36 71)(font "Arial" )) 45 | (line (pt 0 64)(pt 16 64)) 46 | ) 47 | (port 48 | (pt 136 32) 49 | (output) 50 | (text "HL[3..0]" (rect 0 0 40 12)(font "Arial" )) 51 | (text "HL[3..0]" (rect 75 27 115 39)(font "Arial" )) 52 | (line (pt 136 32)(pt 120 32)(line_width 3)) 53 | ) 54 | (port 55 | (pt 136 48) 56 | (output) 57 | (text "HH[3..0]" (rect 0 0 42 12)(font "Arial" )) 58 | (text "HH[3..0]" (rect 73 43 115 55)(font "Arial" )) 59 | (line (pt 136 48)(pt 120 48)(line_width 3)) 60 | ) 61 | (port 62 | (pt 136 64) 63 | (output) 64 | (text "HC" (rect 0 0 16 12)(font "Arial" )) 65 | (text "HC" (rect 99 59 115 71)(font "Arial" )) 66 | (line (pt 136 64)(pt 120 64)) 67 | ) 68 | (drawing 69 | (rectangle (rect 16 16 120 80)) 70 | ) 71 | ) 72 | -------------------------------------------------------------------------------- /e-clock/hour24.bsf: -------------------------------------------------------------------------------- 1 | /* 2 | WARNING: Do NOT edit the input and output ports in this file in a text 3 | editor if you plan to continue editing the block that represents it in 4 | the Block Editor! File corruption is VERY likely to occur. 5 | */ 6 | /* 7 | Copyright (C) 1991-2013 Altera Corporation 8 | Your use of Altera Corporation's design tools, logic functions 9 | and other software and tools, and its AMPP partner logic 10 | functions, and any output files from any of the foregoing 11 | (including device programming or simulation files), and any 12 | associated documentation or information are expressly subject 13 | to the terms and conditions of the Altera Program License 14 | Subscription Agreement, Altera MegaCore Function License 15 | Agreement, or other applicable license agreement, including, 16 | without limitation, that your use is for the sole purpose of 17 | programming logic devices manufactured by Altera and sold by 18 | Altera or its authorized distributors. Please refer to the 19 | applicable agreement for further details. 20 | */ 21 | (header "symbol" (version "1.2")) 22 | (symbol 23 | (rect 16 16 160 144) 24 | (text "hour" (rect 5 0 30 14)(font "Arial" (font_size 8))) 25 | (text "inst" (rect 8 112 25 124)(font "Arial" )) 26 | (port 27 | (pt 0 32) 28 | (input) 29 | (text "hour_clk" (rect 0 0 48 14)(font "Arial" (font_size 8))) 30 | (text "hour_clk" (rect 21 27 69 41)(font "Arial" (font_size 8))) 31 | (line (pt 0 32)(pt 16 32)) 32 | ) 33 | (port 34 | (pt 0 48) 35 | (input) 36 | (text "RD" (rect 0 0 16 14)(font "Arial" (font_size 8))) 37 | (text "RD" (rect 21 43 37 57)(font "Arial" (font_size 8))) 38 | (line (pt 0 48)(pt 16 48)) 39 | ) 40 | (port 41 | (pt 0 64) 42 | (input) 43 | (text "fent" (rect 0 0 22 14)(font "Arial" (font_size 8))) 44 | (text "fent" (rect 21 59 43 73)(font "Arial" (font_size 8))) 45 | (line (pt 0 64)(pt 16 64)) 46 | ) 47 | (port 48 | (pt 0 80) 49 | (input) 50 | (text "K3" (rect 0 0 15 14)(font "Arial" (font_size 8))) 51 | (text "K3" (rect 21 75 36 89)(font "Arial" (font_size 8))) 52 | (line (pt 0 80)(pt 16 80)) 53 | ) 54 | (port 55 | (pt 0 96) 56 | (input) 57 | (text "SC" (rect 0 0 16 14)(font "Arial" (font_size 8))) 58 | (text "SC" (rect 21 91 37 105)(font "Arial" (font_size 8))) 59 | (line (pt 0 96)(pt 16 96)) 60 | ) 61 | (port 62 | (pt 144 32) 63 | (output) 64 | (text "HL[3..0]" (rect 0 0 43 14)(font "Arial" (font_size 8))) 65 | (text "HL[3..0]" (rect 80 27 123 41)(font "Arial" (font_size 8))) 66 | (line (pt 144 32)(pt 128 32)(line_width 3)) 67 | ) 68 | (port 69 | (pt 144 48) 70 | (output) 71 | (text "HH[3..0]" (rect 0 0 44 14)(font "Arial" (font_size 8))) 72 | (text "HH[3..0]" (rect 79 43 123 57)(font "Arial" (font_size 8))) 73 | (line (pt 144 48)(pt 128 48)(line_width 3)) 74 | ) 75 | (port 76 | (pt 144 64) 77 | (output) 78 | (text "HC" (rect 0 0 16 14)(font "Arial" (font_size 8))) 79 | (text "HC" (rect 107 59 123 73)(font "Arial" (font_size 8))) 80 | (line (pt 144 64)(pt 128 64)) 81 | ) 82 | (drawing 83 | (rectangle (rect 16 16 128 112)) 84 | ) 85 | ) 86 | -------------------------------------------------------------------------------- /e-clock/incremental_db/README: -------------------------------------------------------------------------------- 1 | This folder contains data for incremental compilation. 2 | 3 | The compiled_partitions sub-folder contains previous compilation results for each partition. 4 | As long as this folder is preserved, incremental compilation results from earlier compiles 5 | can be re-used. To perform a clean compilation from source files for all partitions, both 6 | the db and incremental_db folder should be removed. 7 | 8 | The imported_partitions sub-folder contains the last imported QXP for each imported partition. 9 | As long as this folder is preserved, imported partitions will be automatically re-imported 10 | when the db or incremental_db/compiled_partitions folders are removed. 11 | 12 | -------------------------------------------------------------------------------- /e-clock/incremental_db/compiled_partitions/LSD.db_info: -------------------------------------------------------------------------------- 1 | Quartus_Version = Version 13.1.0 Build 162 10/23/2013 SJ Full Version 2 | Version_Index = 318808576 3 | Creation_Time = Fri Oct 21 09:01:28 2022 4 | -------------------------------------------------------------------------------- /e-clock/incremental_db/compiled_partitions/LSD.root_partition.cmp.ammdb: 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File corruption is VERY likely to occur. 5 | */ 6 | /* 7 | Copyright (C) 1991-2013 Altera Corporation 8 | Your use of Altera Corporation's design tools, logic functions 9 | and other software and tools, and its AMPP partner logic 10 | functions, and any output files from any of the foregoing 11 | (including device programming or simulation files), and any 12 | associated documentation or information are expressly subject 13 | to the terms and conditions of the Altera Program License 14 | Subscription Agreement, Altera MegaCore Function License 15 | Agreement, or other applicable license agreement, including, 16 | without limitation, that your use is for the sole purpose of 17 | programming logic devices manufactured by Altera and sold by 18 | Altera or its authorized distributors. Please refer to the 19 | applicable agreement for further details. 20 | */ 21 | (header "symbol" (version "1.2")) 22 | (symbol 23 | (rect 16 16 144 208) 24 | (text "kzdl" (rect 5 0 27 14)(font "Arial" (font_size 8))) 25 | (text "inst" (rect 8 176 25 188)(font "Arial" )) 26 | (port 27 | (pt 0 32) 28 | (input) 29 | (text "clk_1Hz" (rect 0 0 44 14)(font "Arial" (font_size 8))) 30 | (text "clk_1Hz" (rect 21 27 65 41)(font "Arial" (font_size 8))) 31 | (line (pt 0 32)(pt 16 32)) 32 | ) 33 | (port 34 | (pt 128 32) 35 | (output) 36 | (text "LED1" (rect 0 0 29 14)(font "Arial" (font_size 8))) 37 | (text "LED1" (rect 78 27 107 41)(font "Arial" (font_size 8))) 38 | (line (pt 128 32)(pt 112 32)) 39 | ) 40 | (port 41 | (pt 128 48) 42 | (output) 43 | (text "LED2" (rect 0 0 29 14)(font "Arial" (font_size 8))) 44 | (text "LED2" (rect 78 43 107 57)(font "Arial" (font_size 8))) 45 | (line (pt 128 48)(pt 112 48)) 46 | ) 47 | (port 48 | (pt 128 64) 49 | (output) 50 | (text "LED3" (rect 0 0 29 14)(font "Arial" (font_size 8))) 51 | (text "LED3" (rect 78 59 107 73)(font "Arial" (font_size 8))) 52 | (line (pt 128 64)(pt 112 64)) 53 | ) 54 | (port 55 | (pt 128 80) 56 | (output) 57 | (text "LED4" (rect 0 0 29 14)(font "Arial" (font_size 8))) 58 | (text "LED4" (rect 78 75 107 89)(font "Arial" (font_size 8))) 59 | (line (pt 128 80)(pt 112 80)) 60 | ) 61 | (port 62 | (pt 128 96) 63 | (output) 64 | (text "LED5" (rect 0 0 29 14)(font "Arial" (font_size 8))) 65 | (text "LED5" (rect 78 91 107 105)(font "Arial" (font_size 8))) 66 | (line (pt 128 96)(pt 112 96)) 67 | ) 68 | (port 69 | (pt 128 112) 70 | (output) 71 | (text "LED6" (rect 0 0 29 14)(font "Arial" (font_size 8))) 72 | (text "LED6" (rect 78 107 107 121)(font "Arial" (font_size 8))) 73 | (line (pt 128 112)(pt 112 112)) 74 | ) 75 | (port 76 | (pt 128 128) 77 | (output) 78 | (text "LED7" (rect 0 0 29 14)(font "Arial" (font_size 8))) 79 | (text "LED7" (rect 78 123 107 137)(font "Arial" (font_size 8))) 80 | (line (pt 128 128)(pt 112 128)) 81 | ) 82 | (port 83 | (pt 128 144) 84 | (output) 85 | (text "LED8" (rect 0 0 29 14)(font "Arial" (font_size 8))) 86 | (text "LED8" (rect 78 139 107 153)(font "Arial" (font_size 8))) 87 | (line (pt 128 144)(pt 112 144)) 88 | ) 89 | (drawing 90 | (rectangle (rect 16 16 112 176)) 91 | ) 92 | ) 93 | -------------------------------------------------------------------------------- /e-clock/kzdl.vwf: -------------------------------------------------------------------------------- 1 | /* 2 | WARNING: Do NOT edit the input and output ports in this file in a text 3 | editor if you plan to continue editing the block that represents it in 4 | the Block Editor! File corruption is VERY likely to occur. 5 | */ 6 | 7 | /* 8 | Copyright (C) 1991-2013 Altera Corporation 9 | Your use of Altera Corporation's design tools, logic functions 10 | and other software and tools, and its AMPP partner logic 11 | functions, and any output files from any of the foregoing 12 | (including device programming or simulation files), and any 13 | associated documentation or information are expressly subject 14 | to the terms and conditions of the Altera Program License 15 | Subscription Agreement, Altera MegaCore Function License 16 | Agreement, or other applicable license agreement, including, 17 | without limitation, that your use is for the sole purpose of 18 | programming logic devices manufactured by Altera and sold by 19 | Altera or its authorized distributors. Please refer to the 20 | applicable agreement for further details. 21 | */ 22 | 23 | HEADER 24 | { 25 | VERSION = 1; 26 | TIME_UNIT = ns; 27 | DATA_OFFSET = 0.0; 28 | DATA_DURATION = 1000.0; 29 | SIMULATION_TIME = 0.0; 30 | GRID_PHASE = 0.0; 31 | GRID_PERIOD = 10.0; 32 | GRID_DUTY_CYCLE = 50; 33 | } 34 | 35 | SIGNAL("clk_1Hz") 36 | { 37 | VALUE_TYPE = NINE_LEVEL_BIT; 38 | SIGNAL_TYPE = SINGLE_BIT; 39 | WIDTH = 1; 40 | LSB_INDEX = -1; 41 | DIRECTION = INPUT; 42 | PARENT = ""; 43 | } 44 | 45 | SIGNAL("LED1") 46 | { 47 | VALUE_TYPE = NINE_LEVEL_BIT; 48 | SIGNAL_TYPE = SINGLE_BIT; 49 | WIDTH = 1; 50 | LSB_INDEX = -1; 51 | DIRECTION = OUTPUT; 52 | PARENT = ""; 53 | } 54 | 55 | SIGNAL("LED2") 56 | { 57 | VALUE_TYPE = NINE_LEVEL_BIT; 58 | SIGNAL_TYPE = SINGLE_BIT; 59 | WIDTH = 1; 60 | LSB_INDEX = -1; 61 | DIRECTION = OUTPUT; 62 | PARENT = ""; 63 | } 64 | 65 | SIGNAL("LED3") 66 | { 67 | VALUE_TYPE = NINE_LEVEL_BIT; 68 | SIGNAL_TYPE = SINGLE_BIT; 69 | WIDTH = 1; 70 | LSB_INDEX = -1; 71 | DIRECTION = OUTPUT; 72 | PARENT = ""; 73 | } 74 | 75 | SIGNAL("LED4") 76 | { 77 | VALUE_TYPE = NINE_LEVEL_BIT; 78 | SIGNAL_TYPE = SINGLE_BIT; 79 | WIDTH = 1; 80 | LSB_INDEX = -1; 81 | DIRECTION = OUTPUT; 82 | PARENT = ""; 83 | } 84 | 85 | SIGNAL("LED5") 86 | { 87 | VALUE_TYPE = NINE_LEVEL_BIT; 88 | SIGNAL_TYPE = SINGLE_BIT; 89 | WIDTH = 1; 90 | LSB_INDEX = -1; 91 | DIRECTION = OUTPUT; 92 | PARENT = ""; 93 | } 94 | 95 | SIGNAL("LED6") 96 | { 97 | VALUE_TYPE = NINE_LEVEL_BIT; 98 | SIGNAL_TYPE = SINGLE_BIT; 99 | WIDTH = 1; 100 | LSB_INDEX = -1; 101 | DIRECTION = OUTPUT; 102 | PARENT = ""; 103 | } 104 | 105 | SIGNAL("LED7") 106 | { 107 | VALUE_TYPE = NINE_LEVEL_BIT; 108 | SIGNAL_TYPE = SINGLE_BIT; 109 | WIDTH = 1; 110 | LSB_INDEX = -1; 111 | DIRECTION = OUTPUT; 112 | PARENT = ""; 113 | } 114 | 115 | SIGNAL("LED8") 116 | { 117 | VALUE_TYPE = NINE_LEVEL_BIT; 118 | SIGNAL_TYPE = SINGLE_BIT; 119 | WIDTH = 1; 120 | LSB_INDEX = -1; 121 | DIRECTION = OUTPUT; 122 | PARENT = ""; 123 | } 124 | 125 | TRANSITION_LIST("clk_1Hz") 126 | { 127 | NODE 128 | { 129 | REPEAT = 1; 130 | NODE 131 | { 132 | REPEAT = 100; 133 | LEVEL 0 FOR 5.0; 134 | LEVEL 1 FOR 5.0; 135 | } 136 | } 137 | } 138 | 139 | TRANSITION_LIST("LED1") 140 | { 141 | NODE 142 | { 143 | REPEAT = 1; 144 | LEVEL X FOR 1000.0; 145 | } 146 | } 147 | 148 | TRANSITION_LIST("LED2") 149 | { 150 | NODE 151 | { 152 | REPEAT = 1; 153 | LEVEL X FOR 1000.0; 154 | } 155 | } 156 | 157 | TRANSITION_LIST("LED3") 158 | { 159 | NODE 160 | { 161 | REPEAT = 1; 162 | LEVEL X FOR 1000.0; 163 | } 164 | } 165 | 166 | TRANSITION_LIST("LED4") 167 | { 168 | NODE 169 | { 170 | REPEAT = 1; 171 | LEVEL X FOR 1000.0; 172 | } 173 | } 174 | 175 | TRANSITION_LIST("LED5") 176 | { 177 | NODE 178 | { 179 | REPEAT = 1; 180 | LEVEL X FOR 1000.0; 181 | } 182 | } 183 | 184 | TRANSITION_LIST("LED6") 185 | { 186 | NODE 187 | { 188 | REPEAT = 1; 189 | LEVEL X FOR 1000.0; 190 | } 191 | } 192 | 193 | TRANSITION_LIST("LED7") 194 | { 195 | NODE 196 | { 197 | REPEAT = 1; 198 | LEVEL X FOR 1000.0; 199 | } 200 | } 201 | 202 | TRANSITION_LIST("LED8") 203 | { 204 | NODE 205 | { 206 | REPEAT = 1; 207 | LEVEL X FOR 1000.0; 208 | } 209 | } 210 | 211 | DISPLAY_LINE 212 | { 213 | CHANNEL = "clk_1Hz"; 214 | EXPAND_STATUS = COLLAPSED; 215 | RADIX = Binary; 216 | TREE_INDEX = 0; 217 | TREE_LEVEL = 0; 218 | } 219 | 220 | DISPLAY_LINE 221 | { 222 | CHANNEL = "LED1"; 223 | EXPAND_STATUS = COLLAPSED; 224 | RADIX = Binary; 225 | TREE_INDEX = 1; 226 | TREE_LEVEL = 0; 227 | } 228 | 229 | DISPLAY_LINE 230 | { 231 | CHANNEL = "LED2"; 232 | EXPAND_STATUS = COLLAPSED; 233 | RADIX = Binary; 234 | TREE_INDEX = 2; 235 | TREE_LEVEL = 0; 236 | } 237 | 238 | DISPLAY_LINE 239 | { 240 | CHANNEL = "LED3"; 241 | EXPAND_STATUS = COLLAPSED; 242 | RADIX = Binary; 243 | TREE_INDEX = 3; 244 | TREE_LEVEL = 0; 245 | } 246 | 247 | DISPLAY_LINE 248 | { 249 | CHANNEL = "LED4"; 250 | EXPAND_STATUS = COLLAPSED; 251 | RADIX = Binary; 252 | TREE_INDEX = 4; 253 | TREE_LEVEL = 0; 254 | } 255 | 256 | DISPLAY_LINE 257 | { 258 | CHANNEL = "LED5"; 259 | EXPAND_STATUS = COLLAPSED; 260 | RADIX = Binary; 261 | TREE_INDEX = 5; 262 | TREE_LEVEL = 0; 263 | } 264 | 265 | DISPLAY_LINE 266 | { 267 | CHANNEL = "LED6"; 268 | EXPAND_STATUS = COLLAPSED; 269 | RADIX = Binary; 270 | TREE_INDEX = 6; 271 | TREE_LEVEL = 0; 272 | } 273 | 274 | DISPLAY_LINE 275 | { 276 | CHANNEL = "LED7"; 277 | EXPAND_STATUS = COLLAPSED; 278 | RADIX = Binary; 279 | TREE_INDEX = 7; 280 | TREE_LEVEL = 0; 281 | } 282 | 283 | DISPLAY_LINE 284 | { 285 | CHANNEL = "LED8"; 286 | EXPAND_STATUS = COLLAPSED; 287 | RADIX = Binary; 288 | TREE_INDEX = 8; 289 | TREE_LEVEL = 0; 290 | } 291 | 292 | TIME_BAR 293 | { 294 | TIME = 0; 295 | MASTER = TRUE; 296 | } 297 | ; 298 | -------------------------------------------------------------------------------- /e-clock/min.bsf: -------------------------------------------------------------------------------- 1 | /* 2 | WARNING: Do NOT edit the input and output ports in this file in a text 3 | editor if you plan to continue editing the block that represents it in 4 | the Block Editor! File corruption is VERY likely to occur. 5 | */ 6 | /* 7 | Copyright (C) 1991-2013 Altera Corporation 8 | Your use of Altera Corporation's design tools, logic functions 9 | and other software and tools, and its AMPP partner logic 10 | functions, and any output files from any of the foregoing 11 | (including device programming or simulation files), and any 12 | associated documentation or information are expressly subject 13 | to the terms and conditions of the Altera Program License 14 | Subscription Agreement, Altera MegaCore Function License 15 | Agreement, or other applicable license agreement, including, 16 | without limitation, that your use is for the sole purpose of 17 | programming logic devices manufactured by Altera and sold by 18 | Altera or its authorized distributors. Please refer to the 19 | applicable agreement for further details. 20 | */ 21 | (header "symbol" (version "1.2")) 22 | (symbol 23 | (rect 16 16 152 112) 24 | (text "min" (rect 5 0 23 14)(font "Arial" (font_size 8))) 25 | (text "inst" (rect 8 80 25 92)(font "Arial" )) 26 | (port 27 | (pt 0 32) 28 | (input) 29 | (text "min_clk" (rect 0 0 37 12)(font "Arial" )) 30 | (text "min_clk" (rect 21 27 58 39)(font "Arial" )) 31 | (line (pt 0 32)(pt 16 32)) 32 | ) 33 | (port 34 | (pt 0 48) 35 | (input) 36 | (text "RD" (rect 0 0 16 12)(font "Arial" )) 37 | (text "RD" (rect 21 43 37 55)(font "Arial" )) 38 | (line (pt 0 48)(pt 16 48)) 39 | ) 40 | (port 41 | (pt 0 64) 42 | (input) 43 | (text "SC" (rect 0 0 15 12)(font "Arial" )) 44 | (text "SC" (rect 21 59 36 71)(font "Arial" )) 45 | (line (pt 0 64)(pt 16 64)) 46 | ) 47 | (port 48 | (pt 136 32) 49 | (output) 50 | (text "ML[3..0]" (rect 0 0 40 12)(font "Arial" )) 51 | (text "ML[3..0]" (rect 75 27 115 39)(font "Arial" )) 52 | (line (pt 136 32)(pt 120 32)(line_width 3)) 53 | ) 54 | (port 55 | (pt 136 48) 56 | (output) 57 | (text "MH[3..0]" (rect 0 0 42 12)(font "Arial" )) 58 | (text "MH[3..0]" (rect 73 43 115 55)(font "Arial" )) 59 | (line (pt 136 48)(pt 120 48)(line_width 3)) 60 | ) 61 | (port 62 | (pt 136 64) 63 | (output) 64 | (text "MC" (rect 0 0 16 12)(font "Arial" )) 65 | (text "MC" (rect 99 59 115 71)(font "Arial" )) 66 | (line (pt 136 64)(pt 120 64)) 67 | ) 68 | (drawing 69 | (rectangle (rect 16 16 120 80)) 70 | ) 71 | ) 72 | -------------------------------------------------------------------------------- /e-clock/mxh.bdf: -------------------------------------------------------------------------------- 1 | /* 2 | WARNING: Do NOT edit the input and output ports in this file in a text 3 | editor if you plan to continue editing the block that represents it in 4 | the Block Editor! File corruption is VERY likely to occur. 5 | */ 6 | /* 7 | Copyright (C) 1991-2013 Altera Corporation 8 | Your use of Altera Corporation's design tools, logic functions 9 | and other software and tools, and its AMPP partner logic 10 | functions, and any output files from any of the foregoing 11 | (including device programming or simulation files), and any 12 | associated documentation or information are expressly subject 13 | to the terms and conditions of the Altera Program License 14 | Subscription Agreement, Altera MegaCore Function License 15 | Agreement, or other applicable license agreement, including, 16 | without limitation, that your use is for the sole purpose of 17 | programming logic devices manufactured by Altera and sold by 18 | Altera or its authorized distributors. Please refer to the 19 | applicable agreement for further details. 20 | */ 21 | (header "graphic" (version "1.4")) 22 | (pin 23 | (input) 24 | (rect 528 112 696 128) 25 | (text "INPUT" (rect 15 0 43 10)(font "Arial" (font_size 6))) 26 | (text "clk_50m" (rect 114 0 155 12)(font "Arial" )) 27 | (pt 0 8) 28 | (drawing 29 | (line (pt 84 12)(pt 59 12)) 30 | (line (pt 84 4)(pt 59 4)) 31 | (line (pt 55 8)(pt 0 8)) 32 | (line (pt 84 12)(pt 84 4)) 33 | (line (pt 59 4)(pt 55 8)) 34 | (line (pt 59 12)(pt 55 8)) 35 | ) 36 | (flipy) 37 | (text "VCC" (rect 20 7 40 17)(font "Arial" (font_size 6))) 38 | ) 39 | (pin 40 | (output) 41 | (rect 776 520 952 536) 42 | (text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6))) 43 | (text "clk_1Hz" (rect 90 0 128 12)(font "Arial" )) 44 | (pt 0 8) 45 | (drawing 46 | (line (pt 0 8)(pt 52 8)) 47 | (line (pt 52 4)(pt 78 4)) 48 | (line (pt 52 12)(pt 78 12)) 49 | (line (pt 52 12)(pt 52 4)) 50 | (line (pt 78 4)(pt 82 8)) 51 | (line (pt 82 8)(pt 78 12)) 52 | (line (pt 78 12)(pt 82 8)) 53 | ) 54 | ) 55 | (symbol 56 | (rect 536 200 704 296) 57 | (text "cnt-100" (rect 5 0 48 14)(font "Arial" (font_size 8))) 58 | (text "inst" (rect 8 80 25 92)(font "Arial" )) 59 | (port 60 | (pt 0 32) 61 | (input) 62 | (text "clk_in_100" (rect 0 0 60 14)(font "Arial" (font_size 8))) 63 | (text "clk_in_100" (rect 21 27 81 41)(font "Arial" (font_size 8))) 64 | (line (pt 0 32)(pt 16 32)) 65 | ) 66 | (port 67 | (pt 168 32) 68 | (output) 69 | (text "clk_out_1" (rect 0 0 54 14)(font "Arial" (font_size 8))) 70 | (text "clk_out_1" (rect 93 27 147 41)(font "Arial" (font_size 8))) 71 | (line (pt 168 32)(pt 152 32)) 72 | ) 73 | (drawing 74 | (rectangle (rect 16 16 152 80)) 75 | ) 76 | ) 77 | (symbol 78 | (rect 736 200 904 296) 79 | (text "cnt-100" (rect 5 0 48 14)(font "Arial" (font_size 8))) 80 | (text "inst2" (rect 8 80 31 92)(font "Arial" )) 81 | (port 82 | (pt 0 32) 83 | (input) 84 | (text "clk_in_100" (rect 0 0 60 14)(font "Arial" (font_size 8))) 85 | (text "clk_in_100" (rect 21 27 81 41)(font "Arial" (font_size 8))) 86 | (line (pt 0 32)(pt 16 32)) 87 | ) 88 | (port 89 | (pt 168 32) 90 | (output) 91 | (text "clk_out_1" (rect 0 0 54 14)(font "Arial" (font_size 8))) 92 | (text "clk_out_1" (rect 93 27 147 41)(font "Arial" (font_size 8))) 93 | (line (pt 168 32)(pt 152 32)) 94 | ) 95 | (drawing 96 | (rectangle (rect 16 16 152 80)) 97 | ) 98 | ) 99 | (symbol 100 | (rect 744 344 912 440) 101 | (text "cnt-100" (rect 120 0 163 14)(font "Arial" (font_size 8))) 102 | (text "inst3" (rect 137 80 160 92)(font "Arial" )) 103 | (port 104 | (pt 168 32) 105 | (input) 106 | (text "clk_in_100" (rect 0 0 60 14)(font "Arial" (font_size 8))) 107 | (text "clk_in_100" (rect 87 27 147 41)(font "Arial" (font_size 8))) 108 | (line (pt 168 32)(pt 152 32)) 109 | ) 110 | (port 111 | (pt 0 32) 112 | (output) 113 | (text "clk_out_1" (rect 0 0 54 14)(font "Arial" (font_size 8))) 114 | (text "clk_out_1" (rect 21 27 75 41)(font "Arial" (font_size 8))) 115 | (line (pt 0 32)(pt 16 32)) 116 | ) 117 | (drawing 118 | (rectangle (rect 16 16 152 80)) 119 | ) 120 | (flipy) 121 | ) 122 | (symbol 123 | (rect 544 344 704 440) 124 | (text "cnt-25" (rect 119 0 155 14)(font "Arial" (font_size 8))) 125 | (text "inst4" (rect 129 80 152 92)(font "Arial" )) 126 | (port 127 | (pt 160 32) 128 | (input) 129 | (text "clk_in_25" (rect 0 0 53 14)(font "Arial" (font_size 8))) 130 | (text "clk_in_25" (rect 86 27 139 41)(font "Arial" (font_size 8))) 131 | (line (pt 160 32)(pt 144 32)) 132 | ) 133 | (port 134 | (pt 0 32) 135 | (output) 136 | (text "clk_out_1" (rect 0 0 54 14)(font "Arial" (font_size 8))) 137 | (text "clk_out_1" (rect 21 27 75 41)(font "Arial" (font_size 8))) 138 | (line (pt 0 32)(pt 16 32)) 139 | ) 140 | (drawing 141 | (rectangle (rect 16 16 144 80)) 142 | ) 143 | (flipy) 144 | ) 145 | (symbol 146 | (rect 560 496 712 592) 147 | (text "cnt-2" (rect 5 0 34 14)(font "Arial" (font_size 8))) 148 | (text "inst5" (rect 8 80 31 92)(font "Arial" )) 149 | (port 150 | (pt 0 32) 151 | (input) 152 | (text "clk_in_2" (rect 0 0 46 14)(font "Arial" (font_size 8))) 153 | (text "clk_in_2" (rect 21 27 67 41)(font "Arial" (font_size 8))) 154 | (line (pt 0 32)(pt 16 32)) 155 | ) 156 | (port 157 | (pt 152 32) 158 | (output) 159 | (text "clk_out_1" (rect 0 0 54 14)(font "Arial" (font_size 8))) 160 | (text "clk_out_1" (rect 77 27 131 41)(font "Arial" (font_size 8))) 161 | (line (pt 152 32)(pt 136 32)) 162 | ) 163 | (drawing 164 | (rectangle (rect 16 16 136 80)) 165 | ) 166 | ) 167 | (connector 168 | (pt 528 120) 169 | (pt 488 120) 170 | ) 171 | (connector 172 | (pt 488 120) 173 | (pt 488 232) 174 | ) 175 | (connector 176 | (pt 488 232) 177 | (pt 536 232) 178 | ) 179 | (connector 180 | (pt 704 232) 181 | (pt 736 232) 182 | ) 183 | (connector 184 | (pt 904 232) 185 | (pt 944 232) 186 | ) 187 | (connector 188 | (pt 944 232) 189 | (pt 944 376) 190 | ) 191 | (connector 192 | (pt 944 376) 193 | (pt 912 376) 194 | ) 195 | (connector 196 | (pt 744 376) 197 | (pt 704 376) 198 | ) 199 | (connector 200 | (pt 544 376) 201 | (pt 520 376) 202 | ) 203 | (connector 204 | (pt 520 376) 205 | (pt 520 528) 206 | ) 207 | (connector 208 | (pt 520 528) 209 | (pt 560 528) 210 | ) 211 | (connector 212 | (pt 712 528) 213 | (pt 776 528) 214 | ) 215 | -------------------------------------------------------------------------------- /e-clock/mxh.bsf: -------------------------------------------------------------------------------- 1 | /* 2 | WARNING: Do NOT edit the input and output ports in this file in a text 3 | editor if you plan to continue editing the block that represents it in 4 | the Block Editor! File corruption is VERY likely to occur. 5 | */ 6 | /* 7 | Copyright (C) 1991-2013 Altera Corporation 8 | Your use of Altera Corporation's design tools, logic functions 9 | and other software and tools, and its AMPP partner logic 10 | functions, and any output files from any of the foregoing 11 | (including device programming or simulation files), and any 12 | associated documentation or information are expressly subject 13 | to the terms and conditions of the Altera Program License 14 | Subscription Agreement, Altera MegaCore Function License 15 | Agreement, or other applicable license agreement, including, 16 | without limitation, that your use is for the sole purpose of 17 | programming logic devices manufactured by Altera and sold by 18 | Altera or its authorized distributors. Please refer to the 19 | applicable agreement for further details. 20 | */ 21 | (header "symbol" (version "1.2")) 22 | (symbol 23 | (rect 16 16 160 112) 24 | (text "mxh" (rect 5 0 28 14)(font "Arial" (font_size 8))) 25 | (text "inst" (rect 8 80 25 92)(font "Arial" )) 26 | (port 27 | (pt 0 32) 28 | (input) 29 | (text "clk_50m" (rect 0 0 46 14)(font "Arial" (font_size 8))) 30 | (text "clk_50m" (rect 21 27 67 41)(font "Arial" (font_size 8))) 31 | (line (pt 0 32)(pt 16 32)) 32 | ) 33 | (port 34 | (pt 144 32) 35 | (output) 36 | (text "clk_1Hz" (rect 0 0 44 14)(font "Arial" (font_size 8))) 37 | (text "clk_1Hz" (rect 79 27 123 41)(font "Arial" (font_size 8))) 38 | (line (pt 144 32)(pt 128 32)) 39 | ) 40 | (drawing 41 | (rectangle (rect 16 16 128 80)) 42 | ) 43 | ) 44 | -------------------------------------------------------------------------------- /e-clock/output_files/LSD.cdf: -------------------------------------------------------------------------------- 1 | /* Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version */ 2 | JedecChain; 3 | FileRevision(JESD32A); 4 | DefaultMfr(6E); 5 | 6 | P ActionCode(Cfg) 7 | Device PartName(EP4CE6E22) Path("E:/DC_WS/clock/Test01/output_files/") File("LSD.sof") MfrSpec(OpMask(1)); 8 | 9 | ChainEnd; 10 | 11 | AlteraBegin; 12 | ChainType(JTAG); 13 | AlteraEnd; 14 | -------------------------------------------------------------------------------- /e-clock/output_files/LSD.done: -------------------------------------------------------------------------------- 1 | Tue May 23 23:53:49 2023 2 | -------------------------------------------------------------------------------- /e-clock/output_files/LSD.eda.rpt: -------------------------------------------------------------------------------- 1 | EDA Netlist Writer report for LSD 2 | Tue May 23 23:53:48 2023 3 | Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version 4 | 5 | 6 | --------------------- 7 | ; Table of Contents ; 8 | --------------------- 9 | 1. Legal Notice 10 | 2. EDA Netlist Writer Summary 11 | 3. Simulation Settings 12 | 4. Simulation Generated Files 13 | 5. EDA Netlist Writer Messages 14 | 15 | 16 | 17 | ---------------- 18 | ; Legal Notice ; 19 | ---------------- 20 | Copyright (C) 1991-2013 Altera Corporation 21 | Your use of Altera Corporation's design tools, logic functions 22 | and other software and tools, and its AMPP partner logic 23 | functions, and any output files from any of the foregoing 24 | (including device programming or simulation files), and any 25 | associated documentation or information are expressly subject 26 | to the terms and conditions of the Altera Program License 27 | Subscription Agreement, Altera MegaCore Function License 28 | Agreement, or other applicable license agreement, including, 29 | without limitation, that your use is for the sole purpose of 30 | programming logic devices manufactured by Altera and sold by 31 | Altera or its authorized distributors. Please refer to the 32 | applicable agreement for further details. 33 | 34 | 35 | 36 | +-------------------------------------------------------------------+ 37 | ; EDA Netlist Writer Summary ; 38 | +---------------------------+---------------------------------------+ 39 | ; EDA Netlist Writer Status ; Successful - Tue May 23 23:53:48 2023 ; 40 | ; Revision Name ; LSD ; 41 | ; Top-level Entity Name ; clock24 ; 42 | ; Family ; Cyclone IV E ; 43 | ; Simulation Files Creation ; Successful ; 44 | +---------------------------+---------------------------------------+ 45 | 46 | 47 | +-------------------------------------------------------------------------------------------------------------------------------+ 48 | ; Simulation Settings ; 49 | +---------------------------------------------------------------------------------------------------+---------------------------+ 50 | ; Option ; Setting ; 51 | +---------------------------------------------------------------------------------------------------+---------------------------+ 52 | ; Tool Name ; ModelSim-Altera (Verilog) ; 53 | ; Generate netlist for functional simulation only ; On ; 54 | ; Truncate long hierarchy paths ; Off ; 55 | ; Map illegal HDL characters ; Off ; 56 | ; Flatten buses into individual nodes ; Off ; 57 | ; Maintain hierarchy ; Off ; 58 | ; Bring out device-wide set/reset signals as ports ; Off ; 59 | ; Enable glitch filtering ; Off ; 60 | ; Do not write top level VHDL entity ; Off ; 61 | ; Disable detection of setup and hold time violations in the input registers of bi-directional pins ; Off ; 62 | ; Architecture name in VHDL output netlist ; structure ; 63 | ; Generate third-party EDA tool command script for RTL functional simulation ; Off ; 64 | ; Generate third-party EDA tool command script for gate-level simulation ; Off ; 65 | +---------------------------------------------------------------------------------------------------+---------------------------+ 66 | 67 | 68 | +-----------------------------------------------+ 69 | ; Simulation Generated Files ; 70 | +-----------------------------------------------+ 71 | ; Generated Files ; 72 | +-----------------------------------------------+ 73 | ; E:/DC_WS/clock/Test01/simulation/qsim//LSD.vo ; 74 | +-----------------------------------------------+ 75 | 76 | 77 | +-----------------------------+ 78 | ; EDA Netlist Writer Messages ; 79 | +-----------------------------+ 80 | Info: ******************************************************************* 81 | Info: Running Quartus II 64-Bit EDA Netlist Writer 82 | Info: Version 13.1.0 Build 162 10/23/2013 SJ Full Version 83 | Info: Processing started: Tue May 23 23:53:47 2023 84 | Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off e-clock -c LSD 85 | Info (204019): Generated file LSD.vo in folder "E:/DC_WS/clock/Test01/simulation/qsim//" for EDA simulation tool 86 | Info: Quartus II 64-Bit EDA Netlist Writer was successful. 0 errors, 0 warnings 87 | Info: Peak virtual memory: 4554 megabytes 88 | Info: Processing ended: Tue May 23 23:53:48 2023 89 | Info: Elapsed time: 00:00:01 90 | Info: Total CPU time (on all processors): 00:00:00 91 | 92 | 93 | -------------------------------------------------------------------------------- /e-clock/output_files/LSD.fit.rpt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CodeAlanqian/e-clock/ac6929bfe0df785b47a94b848983913f0d3df45b/e-clock/output_files/LSD.fit.rpt -------------------------------------------------------------------------------- /e-clock/output_files/LSD.fit.smsg: -------------------------------------------------------------------------------- 1 | Extra Info (176273): Performing register packing on registers with non-logic cell location assignments 2 | Extra Info (176274): Completed register packing on registers with non-logic cell location assignments 3 | Extra Info (176236): Started Fast Input/Output/OE register processing 4 | Extra Info (176237): Finished Fast Input/Output/OE register processing 5 | Extra Info (176238): Start inferring scan chains for DSP blocks 6 | Extra Info (176239): Inferring scan chains for DSP blocks is complete 7 | Extra Info (176248): Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density 8 | Extra Info (176249): Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks 9 | -------------------------------------------------------------------------------- /e-clock/output_files/LSD.fit.summary: -------------------------------------------------------------------------------- 1 | Fitter Status : Successful - Tue May 23 23:53:35 2023 2 | Quartus II 64-Bit Version : 13.1.0 Build 162 10/23/2013 SJ Full Version 3 | Revision Name : LSD 4 | Top-level Entity Name : clock24 5 | Family : Cyclone IV E 6 | Device : EP4CE6E22C8 7 | Timing Models : Final 8 | Total logic elements : 372 / 6,272 ( 6 % ) 9 | Total combinational functions : 341 / 6,272 ( 5 % ) 10 | Dedicated logic registers : 218 / 6,272 ( 3 % ) 11 | Total registers : 218 12 | Total pins : 30 / 92 ( 33 % ) 13 | Total virtual pins : 0 14 | Total memory bits : 0 / 276,480 ( 0 % ) 15 | Embedded Multiplier 9-bit elements : 0 / 30 ( 0 % ) 16 | Total PLLs : 0 / 2 ( 0 % ) 17 | -------------------------------------------------------------------------------- /e-clock/output_files/LSD.jdi: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | -------------------------------------------------------------------------------- /e-clock/output_files/LSD.map.summary: -------------------------------------------------------------------------------- 1 | Analysis & Synthesis Status : Successful - Tue May 23 23:53:27 2023 2 | Quartus II 64-Bit Version : 13.1.0 Build 162 10/23/2013 SJ Full Version 3 | Revision Name : LSD 4 | Top-level Entity Name : clock24 5 | Family : Cyclone IV E 6 | Total logic elements : 362 7 | Total combinational functions : 341 8 | Dedicated logic registers : 218 9 | Total registers : 218 10 | Total pins : 30 11 | Total virtual pins : 0 12 | Total memory bits : 0 13 | Embedded Multiplier 9-bit elements : 0 14 | Total PLLs : 0 15 | -------------------------------------------------------------------------------- /e-clock/output_files/LSD.sof: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CodeAlanqian/e-clock/ac6929bfe0df785b47a94b848983913f0d3df45b/e-clock/output_files/LSD.sof -------------------------------------------------------------------------------- /e-clock/sec.bsf: -------------------------------------------------------------------------------- 1 | /* 2 | WARNING: Do NOT edit the input and output ports in this file in a text 3 | editor if you plan to continue editing the block that represents it in 4 | the Block Editor! File corruption is VERY likely to occur. 5 | */ 6 | /* 7 | Copyright (C) 1991-2013 Altera Corporation 8 | Your use of Altera Corporation's design tools, logic functions 9 | and other software and tools, and its AMPP partner logic 10 | functions, and any output files from any of the foregoing 11 | (including device programming or simulation files), and any 12 | associated documentation or information are expressly subject 13 | to the terms and conditions of the Altera Program License 14 | Subscription Agreement, Altera MegaCore Function License 15 | Agreement, or other applicable license agreement, including, 16 | without limitation, that your use is for the sole purpose of 17 | programming logic devices manufactured by Altera and sold by 18 | Altera or its authorized distributors. Please refer to the 19 | applicable agreement for further details. 20 | */ 21 | (header "symbol" (version "1.2")) 22 | (symbol 23 | (rect 16 16 152 112) 24 | (text "sec" (rect 5 0 26 14)(font "Arial" (font_size 8))) 25 | (text "inst" (rect 8 80 25 92)(font "Arial" )) 26 | (port 27 | (pt 0 32) 28 | (input) 29 | (text "clk_1Hz" (rect 0 0 38 12)(font "Arial" )) 30 | (text "clk_1Hz" (rect 21 27 59 39)(font "Arial" )) 31 | (line (pt 0 32)(pt 16 32)) 32 | ) 33 | (port 34 | (pt 0 48) 35 | (input) 36 | (text "RD" (rect 0 0 16 12)(font "Arial" )) 37 | (text "RD" (rect 21 43 37 55)(font "Arial" )) 38 | (line (pt 0 48)(pt 16 48)) 39 | ) 40 | (port 41 | (pt 136 32) 42 | (output) 43 | (text "SL[3..0]" (rect 0 0 38 12)(font "Arial" )) 44 | (text "SL[3..0]" (rect 77 27 115 39)(font "Arial" )) 45 | (line (pt 136 32)(pt 120 32)(line_width 3)) 46 | ) 47 | (port 48 | (pt 136 48) 49 | (output) 50 | (text "SH[3..0]" (rect 0 0 41 12)(font "Arial" )) 51 | (text "SH[3..0]" (rect 74 43 115 55)(font "Arial" )) 52 | (line (pt 136 48)(pt 120 48)(line_width 3)) 53 | ) 54 | (port 55 | (pt 136 64) 56 | (output) 57 | (text "SC" (rect 0 0 15 12)(font "Arial" )) 58 | (text "SC" (rect 100 59 115 71)(font "Arial" )) 59 | (line (pt 136 64)(pt 120 64)) 60 | ) 61 | (drawing 62 | (rectangle (rect 16 16 120 80)) 63 | ) 64 | ) 65 | -------------------------------------------------------------------------------- /e-clock/simulation/qsim/LSD.do: -------------------------------------------------------------------------------- 1 | onerror {exit -code 1} 2 | vlib work 3 | vlog -work work LSD.vo 4 | vlog -work work sec.vwf.vt 5 | vsim -novopt -c -t 1ps -L cycloneive_ver -L altera_ver -L altera_mf_ver -L 220model_ver -L sgate work.sec_vlg_vec_tst -voptargs="+acc" 6 | vcd file -direction LSD.msim.vcd 7 | vcd add -internal sec_vlg_vec_tst/* 8 | vcd add -internal sec_vlg_vec_tst/i1/* 9 | run -all 10 | quit -f 11 | -------------------------------------------------------------------------------- /e-clock/simulation/qsim/LSD.sft: -------------------------------------------------------------------------------- 1 | set tool_name "ModelSim-Altera (Verilog)" 2 | -------------------------------------------------------------------------------- /e-clock/simulation/qsim/kzdl.vwf.vt: -------------------------------------------------------------------------------- 1 | // Copyright (C) 1991-2013 Altera Corporation 2 | // Your use of Altera Corporation's design tools, logic functions 3 | // and other software and tools, and its AMPP partner logic 4 | // functions, and any output files from any of the foregoing 5 | // (including device programming or simulation files), and any 6 | // associated documentation or information are expressly subject 7 | // to the terms and conditions of the Altera Program License 8 | // Subscription Agreement, Altera MegaCore Function License 9 | // Agreement, or other applicable license agreement, including, 10 | // without limitation, that your use is for the sole purpose of 11 | // programming logic devices manufactured by Altera and sold by 12 | // Altera or its authorized distributors. Please refer to the 13 | // applicable agreement for further details. 14 | 15 | // ***************************************************************************** 16 | // This file contains a Verilog test bench with test vectors .The test vectors 17 | // are exported from a vector file in the Quartus Waveform Editor and apply to 18 | // the top level entity of the current Quartus project .The user can use this 19 | // testbench to simulate his design using a third-party simulation tool . 20 | // ***************************************************************************** 21 | // Generated on "10/28/2022 09:59:05" 22 | 23 | // Verilog Self-Checking Test Bench (with test vectors) for design : CLOCK 24 | // 25 | // Simulation tool : 3rd Party 26 | // 27 | 28 | `timescale 1 ps/ 1 ps 29 | module CLOCK_vlg_vec_tst(); 30 | // constants 31 | // general purpose registers 32 | reg clk; 33 | // wires 34 | wire POS1; 35 | 36 | // assign statements (if any) 37 | CLOCK i1 ( 38 | // port map - connection between master ports and signals/registers 39 | .clk(clk), 40 | .POS1(POS1) 41 | ); 42 | initial 43 | begin 44 | #1000000 $finish; 45 | end 46 | initial 47 | begin 48 | #1000000 $finish; 49 | end 50 | endmodule 51 | 52 | -------------------------------------------------------------------------------- /e-clock/simulation/qsim/switch.vwf.vt: -------------------------------------------------------------------------------- 1 | // Copyright (C) 1991-2013 Altera Corporation 2 | // Your use of Altera Corporation's design tools, logic functions 3 | // and other software and tools, and its AMPP partner logic 4 | // functions, and any output files from any of the foregoing 5 | // (including device programming or simulation files), and any 6 | // associated documentation or information are expressly subject 7 | // to the terms and conditions of the Altera Program License 8 | // Subscription Agreement, Altera MegaCore Function License 9 | // Agreement, or other applicable license agreement, including, 10 | // without limitation, that your use is for the sole purpose of 11 | // programming logic devices manufactured by Altera and sold by 12 | // Altera or its authorized distributors. Please refer to the 13 | // applicable agreement for further details. 14 | 15 | // ***************************************************************************** 16 | // This file contains a Verilog test bench with test vectors .The test vectors 17 | // are exported from a vector file in the Quartus Waveform Editor and apply to 18 | // the top level entity of the current Quartus project .The user can use this 19 | // testbench to simulate his design using a third-party simulation tool . 20 | // ***************************************************************************** 21 | // Generated on "11/23/2022 13:36:33" 22 | 23 | // Verilog Self-Checking Test Bench (with test vectors) for design : CLOCK 24 | // 25 | // Simulation tool : 3rd Party 26 | // 27 | 28 | `timescale 1 ps/ 1 ps 29 | module CLOCK_vlg_vec_tst(); 30 | // constants 31 | // general purpose registers 32 | reg clk; 33 | // wires 34 | wire a; 35 | wire b; 36 | wire c; 37 | wire d; 38 | wire k; 39 | wire pin_name1; 40 | wire pin_name2; 41 | wire pin_name3; 42 | wire pin_name4; 43 | wire pin_name5; 44 | wire pin_name6; 45 | wire pin_name7; 46 | wire pin_name8; 47 | wire POS1; 48 | 49 | // assign statements (if any) 50 | CLOCK i1 ( 51 | // port map - connection between master ports and signals/registers 52 | .a(a), 53 | .b(b), 54 | .c(c), 55 | .clk(clk), 56 | .d(d), 57 | .k(k), 58 | .pin_name1(pin_name1), 59 | .pin_name2(pin_name2), 60 | .pin_name3(pin_name3), 61 | .pin_name4(pin_name4), 62 | .pin_name5(pin_name5), 63 | .pin_name6(pin_name6), 64 | .pin_name7(pin_name7), 65 | .pin_name8(pin_name8), 66 | .POS1(POS1) 67 | ); 68 | initial 69 | begin 70 | #1000000 $finish; 71 | end 72 | initial 73 | begin 74 | #1000000 $finish; 75 | end 76 | endmodule 77 | 78 | -------------------------------------------------------------------------------- /e-clock/simulation/qsim/transcript: -------------------------------------------------------------------------------- 1 | # do LSD.do 2 | # ** Warning: (vlib-34) Library already exists at "work". 3 | # 4 | # Model Technology ModelSim SE-64 vlog 10.4 Compiler 2014.12 Dec 3 2014 5 | # Start time: 19:41:34 on Feb 26,2023 6 | # vlog -work work LSD.vo 7 | # -- Compiling module sec 8 | # 9 | # Top level modules: 10 | # sec 11 | # End time: 19:41:34 on Feb 26,2023, Elapsed time: 0:00:00 12 | # Errors: 0, Warnings: 0 13 | # Model Technology ModelSim SE-64 vlog 10.4 Compiler 2014.12 Dec 3 2014 14 | # Start time: 19:41:34 on Feb 26,2023 15 | # vlog -work work sec.vwf.vt 16 | # -- Compiling module sec_vlg_sample_tst 17 | # -- Compiling module sec_vlg_check_tst 18 | # -- Compiling module sec_vlg_vec_tst 19 | # 20 | # Top level modules: 21 | # sec_vlg_vec_tst 22 | # End time: 19:41:34 on Feb 26,2023, Elapsed time: 0:00:00 23 | # Errors: 0, Warnings: 0 24 | # vsim -c -do "LSD.do" 25 | # Start time: 19:41:34 on Feb 26,2023 26 | # ** Warning: (vsim-8891) All optimizations are turned off because the -novopt switch is in effect. This will cause your simulation to run very slowly. If you are using this switch to preserve visibility for Debug or PLI features please see the User's Manual section on Preserving Object Visibility with vopt. 27 | # 28 | # // ModelSim SE-64 10.4 Dec 3 2014 29 | # // 30 | # // Copyright 1991-2014 Mentor Graphics Corporation 31 | # // All Rights Reserved. 32 | # // 33 | # // THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION 34 | # // WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION OR ITS 35 | # // LICENSORS AND IS SUBJECT TO LICENSE TERMS. 36 | # // THIS DOCUMENT CONTAINS TRADE SECRETS AND COMMERCIAL OR FINANCIAL 37 | # // INFORMATION THAT ARE PRIVILEGED, CONFIDENTIAL, AND EXEMPT FROM 38 | # // DISCLOSURE UNDER THE FREEDOM OF INFORMATION ACT, 5 U.S.C. SECTION 552. 39 | # // FURTHERMORE, THIS INFORMATION IS PROHIBITED FROM DISCLOSURE UNDER 40 | # // THE TRADE SECRETS ACT, 18 U.S.C. SECTION 1905. 41 | # // 42 | # Refreshing E:/DC_WS/clock/Test01/simulation/qsim/work.sec_vlg_vec_tst 43 | # Loading work.sec_vlg_vec_tst 44 | # ** Error: (vsim-19) Failed to access library '220model_ver' at "220model_ver". 45 | # 46 | # No such file or directory. (errno = ENOENT) 47 | # ** Error: (vsim-19) Failed to access library 'sgate' at "sgate". 48 | # 49 | # No such file or directory. (errno = ENOENT) 50 | # Refreshing E:/DC_WS/clock/Test01/simulation/qsim/work.sec 51 | # Loading work.sec 52 | # Loading cycloneive_ver.cycloneive_io_obuf 53 | # Loading cycloneive_ver.cycloneive_io_ibuf 54 | # Loading cycloneive_ver.cycloneive_clkctrl 55 | # Loading cycloneive_ver.cycloneive_mux41 56 | # Loading cycloneive_ver.cycloneive_ena_reg 57 | # Loading cycloneive_ver.cycloneive_lcell_comb 58 | # Loading altera_ver.dffeas 59 | # ** Error: (vsim-19) Failed to access library '220model_ver' at "220model_ver". 60 | # 61 | # No such file or directory. (errno = ENOENT) 62 | # ** Error: (vsim-19) Failed to access library 'sgate' at "sgate". 63 | # 64 | # No such file or directory. (errno = ENOENT) 65 | # Refreshing E:/DC_WS/clock/Test01/simulation/qsim/work.sec_vlg_sample_tst 66 | # Loading work.sec_vlg_sample_tst 67 | # ** Error: (vsim-19) Failed to access library '220model_ver' at "220model_ver". 68 | # 69 | # No such file or directory. (errno = ENOENT) 70 | # ** Error: (vsim-19) Failed to access library 'sgate' at "sgate". 71 | # 72 | # No such file or directory. (errno = ENOENT) 73 | # Refreshing E:/DC_WS/clock/Test01/simulation/qsim/work.sec_vlg_check_tst 74 | # Loading work.sec_vlg_check_tst 75 | # Loading altera_ver.PRIM_GDFF_LOW 76 | # Simulation passed ! 77 | # ** Note: $finish : sec.vwf.vt(312) 78 | # Time: 1 us Iteration: 0 Instance: /sec_vlg_vec_tst/tb_out 79 | # End time: 19:41:36 on Feb 26,2023, Elapsed time: 0:00:02 80 | # Errors: 6, Warnings: 1 81 | -------------------------------------------------------------------------------- /e-clock/simulation/qsim/verilog_libs/altera_lnsim_ver/_lib.qdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CodeAlanqian/e-clock/ac6929bfe0df785b47a94b848983913f0d3df45b/e-clock/simulation/qsim/verilog_libs/altera_lnsim_ver/_lib.qdb -------------------------------------------------------------------------------- /e-clock/simulation/qsim/verilog_libs/altera_lnsim_ver/_lib1_3.qdb: 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/e-clock/simulation/qsim/verilog_libs/lpm_ver/_vmake: -------------------------------------------------------------------------------- 1 | m255 2 | K4 3 | z0 4 | cModel Technology 5 | -------------------------------------------------------------------------------- /e-clock/simulation/qsim/verilog_libs/sgate_ver/_info: -------------------------------------------------------------------------------- 1 | m255 2 | K4 3 | z2 4 | 13 5 | !s112 1.1 6 | !i10d 8192 7 | !i10e 25 8 | !i10f 100 9 | cModel Technology 10 | dD:/codealan/Test01/simulation/qsim 11 | vio_buf_opdrn 12 | Z0 !s110 1677338823 13 | !i10b 1 14 | !s100 =^iWBb8W^X47cYOP6oA1 16 | Z1 VDg1SIo80bB@j0V0VzS_@n1 17 | Z2 dE:/DC_WS/clock/Test01/simulation/qsim 18 | Z3 w1382638997 19 | Z4 8d:/altera/13.1/quartus/eda/sim_lib/sgate.v 20 | Z5 Fd:/altera/13.1/quartus/eda/sim_lib/sgate.v 21 | L0 248 22 | Z6 OL;L;10.4;61 23 | r1 24 | !s85 0 25 | 31 26 | Z7 !s108 1677338823.480000 27 | Z8 !s107 d:/altera/13.1/quartus/eda/sim_lib/sgate.v| 28 | Z9 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| !s100 iZXLc]>>jEPo^MZifMO:93 375 | IDz0XR9EnN^zFlK:[SVPz^3 376 | R1 377 | R2 378 | R3 379 | R4 380 | R5 381 | L0 347 382 | R6 383 | r1 384 | !s85 0 385 | 31 386 | R7 387 | R8 388 | R9 389 | !i113 0 390 | R10 391 | -------------------------------------------------------------------------------- /e-clock/simulation/qsim/verilog_libs/sgate_ver/_lib.qdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CodeAlanqian/e-clock/ac6929bfe0df785b47a94b848983913f0d3df45b/e-clock/simulation/qsim/verilog_libs/sgate_ver/_lib.qdb -------------------------------------------------------------------------------- /e-clock/simulation/qsim/verilog_libs/sgate_ver/_lib1_1.qdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CodeAlanqian/e-clock/ac6929bfe0df785b47a94b848983913f0d3df45b/e-clock/simulation/qsim/verilog_libs/sgate_ver/_lib1_1.qdb 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editor if you plan to continue editing the block that represents it in 4 | the Block Editor! File corruption is VERY likely to occur. 5 | */ 6 | /* 7 | Copyright (C) 1991-2013 Altera Corporation 8 | Your use of Altera Corporation's design tools, logic functions 9 | and other software and tools, and its AMPP partner logic 10 | functions, and any output files from any of the foregoing 11 | (including device programming or simulation files), and any 12 | associated documentation or information are expressly subject 13 | to the terms and conditions of the Altera Program License 14 | Subscription Agreement, Altera MegaCore Function License 15 | Agreement, or other applicable license agreement, including, 16 | without limitation, that your use is for the sole purpose of 17 | programming logic devices manufactured by Altera and sold by 18 | Altera or its authorized distributors. Please refer to the 19 | applicable agreement for further details. 20 | */ 21 | (header "symbol" (version "1.2")) 22 | (symbol 23 | (rect 16 16 160 112) 24 | (text "switch" (rect 5 0 43 14)(font "Arial" (font_size 8))) 25 | (text "inst" (rect 8 80 25 92)(font "Arial" )) 26 | (port 27 | (pt 0 32) 28 | (input) 29 | (text "clk_1kHz" (rect 0 0 50 14)(font "Arial" (font_size 8))) 30 | (text "clk_1kHz" (rect 21 27 71 41)(font "Arial" (font_size 8))) 31 | (line (pt 0 32)(pt 16 32)) 32 | ) 33 | (port 34 | (pt 144 32) 35 | (output) 36 | (text "S[0..5]" (rect 0 0 36 14)(font "Arial" (font_size 8))) 37 | (text "S[0..5]" (rect 87 27 123 41)(font "Arial" (font_size 8))) 38 | (line (pt 144 32)(pt 128 32)(line_width 3)) 39 | ) 40 | (drawing 41 | (rectangle (rect 16 16 128 80)) 42 | ) 43 | ) 44 | -------------------------------------------------------------------------------- /e-clock/switch.vwf: -------------------------------------------------------------------------------- 1 | /* 2 | WARNING: Do NOT edit the input and output ports in this file in a text 3 | editor if you plan to continue editing the block that represents it in 4 | the Block Editor! File corruption is VERY likely to occur. 5 | */ 6 | 7 | /* 8 | Copyright (C) 1991-2013 Altera Corporation 9 | Your use of Altera Corporation's design tools, logic functions 10 | and other software and tools, and its AMPP partner logic 11 | functions, and any output files from any of the foregoing 12 | (including device programming or simulation files), and any 13 | associated documentation or information are expressly subject 14 | to the terms and conditions of the Altera Program License 15 | Subscription Agreement, Altera MegaCore Function License 16 | Agreement, or other applicable license agreement, including, 17 | without limitation, that your use is for the sole purpose of 18 | programming logic devices manufactured by Altera and sold by 19 | Altera or its authorized distributors. Please refer to the 20 | applicable agreement for further details. 21 | */ 22 | 23 | HEADER 24 | { 25 | VERSION = 1; 26 | TIME_UNIT = ns; 27 | DATA_OFFSET = 0.0; 28 | DATA_DURATION = 1000.0; 29 | SIMULATION_TIME = 0.0; 30 | GRID_PHASE = 0.0; 31 | GRID_PERIOD = 10.0; 32 | GRID_DUTY_CYCLE = 50; 33 | } 34 | 35 | SIGNAL("clk_1kHz") 36 | { 37 | VALUE_TYPE = NINE_LEVEL_BIT; 38 | SIGNAL_TYPE = SINGLE_BIT; 39 | WIDTH = 1; 40 | LSB_INDEX = -1; 41 | DIRECTION = INPUT; 42 | PARENT = ""; 43 | } 44 | 45 | SIGNAL("S") 46 | { 47 | VALUE_TYPE = NINE_LEVEL_BIT; 48 | SIGNAL_TYPE = BUS; 49 | WIDTH = 6; 50 | LSB_INDEX = 0; 51 | DIRECTION = OUTPUT; 52 | PARENT = ""; 53 | } 54 | 55 | SIGNAL("S[5]") 56 | { 57 | VALUE_TYPE = NINE_LEVEL_BIT; 58 | SIGNAL_TYPE = SINGLE_BIT; 59 | WIDTH = 1; 60 | LSB_INDEX = -1; 61 | DIRECTION = OUTPUT; 62 | PARENT = "S"; 63 | } 64 | 65 | SIGNAL("S[4]") 66 | { 67 | VALUE_TYPE = NINE_LEVEL_BIT; 68 | SIGNAL_TYPE = SINGLE_BIT; 69 | WIDTH = 1; 70 | LSB_INDEX = -1; 71 | DIRECTION = OUTPUT; 72 | PARENT = "S"; 73 | } 74 | 75 | SIGNAL("S[3]") 76 | { 77 | VALUE_TYPE = NINE_LEVEL_BIT; 78 | SIGNAL_TYPE = SINGLE_BIT; 79 | WIDTH = 1; 80 | LSB_INDEX = -1; 81 | DIRECTION = OUTPUT; 82 | PARENT = "S"; 83 | } 84 | 85 | SIGNAL("S[2]") 86 | { 87 | VALUE_TYPE = NINE_LEVEL_BIT; 88 | SIGNAL_TYPE = SINGLE_BIT; 89 | WIDTH = 1; 90 | LSB_INDEX = -1; 91 | DIRECTION = OUTPUT; 92 | PARENT = "S"; 93 | } 94 | 95 | SIGNAL("S[1]") 96 | { 97 | VALUE_TYPE = NINE_LEVEL_BIT; 98 | SIGNAL_TYPE = SINGLE_BIT; 99 | WIDTH = 1; 100 | LSB_INDEX = -1; 101 | DIRECTION = OUTPUT; 102 | PARENT = "S"; 103 | } 104 | 105 | SIGNAL("S[0]") 106 | { 107 | VALUE_TYPE = NINE_LEVEL_BIT; 108 | SIGNAL_TYPE = SINGLE_BIT; 109 | WIDTH = 1; 110 | LSB_INDEX = -1; 111 | DIRECTION = OUTPUT; 112 | PARENT = "S"; 113 | } 114 | 115 | TRANSITION_LIST("clk_1kHz") 116 | { 117 | NODE 118 | { 119 | REPEAT = 1; 120 | NODE 121 | { 122 | REPEAT = 100; 123 | LEVEL 0 FOR 5.0; 124 | LEVEL 1 FOR 5.0; 125 | } 126 | } 127 | } 128 | 129 | TRANSITION_LIST("S[5]") 130 | { 131 | NODE 132 | { 133 | REPEAT = 1; 134 | LEVEL X FOR 1000.0; 135 | } 136 | } 137 | 138 | TRANSITION_LIST("S[4]") 139 | { 140 | NODE 141 | { 142 | REPEAT = 1; 143 | LEVEL X FOR 1000.0; 144 | } 145 | } 146 | 147 | TRANSITION_LIST("S[3]") 148 | { 149 | NODE 150 | { 151 | REPEAT = 1; 152 | LEVEL X FOR 1000.0; 153 | } 154 | } 155 | 156 | TRANSITION_LIST("S[2]") 157 | { 158 | NODE 159 | { 160 | REPEAT = 1; 161 | LEVEL X FOR 1000.0; 162 | } 163 | } 164 | 165 | TRANSITION_LIST("S[1]") 166 | { 167 | NODE 168 | { 169 | REPEAT = 1; 170 | LEVEL X FOR 1000.0; 171 | } 172 | } 173 | 174 | TRANSITION_LIST("S[0]") 175 | { 176 | NODE 177 | { 178 | REPEAT = 1; 179 | LEVEL X FOR 1000.0; 180 | } 181 | } 182 | 183 | DISPLAY_LINE 184 | { 185 | CHANNEL = "clk_1kHz"; 186 | EXPAND_STATUS = COLLAPSED; 187 | RADIX = Binary; 188 | TREE_INDEX = 0; 189 | TREE_LEVEL = 0; 190 | } 191 | 192 | DISPLAY_LINE 193 | { 194 | CHANNEL = "S"; 195 | EXPAND_STATUS = COLLAPSED; 196 | RADIX = Binary; 197 | TREE_INDEX = 1; 198 | TREE_LEVEL = 0; 199 | CHILDREN = 2, 3, 4, 5, 6, 7; 200 | } 201 | 202 | DISPLAY_LINE 203 | { 204 | CHANNEL = "S[0]"; 205 | EXPAND_STATUS = COLLAPSED; 206 | RADIX = Binary; 207 | TREE_INDEX = 2; 208 | TREE_LEVEL = 1; 209 | PARENT = 1; 210 | } 211 | 212 | DISPLAY_LINE 213 | { 214 | CHANNEL = "S[1]"; 215 | EXPAND_STATUS = COLLAPSED; 216 | RADIX = Binary; 217 | TREE_INDEX = 3; 218 | TREE_LEVEL = 1; 219 | PARENT = 1; 220 | } 221 | 222 | DISPLAY_LINE 223 | { 224 | CHANNEL = "S[2]"; 225 | EXPAND_STATUS = COLLAPSED; 226 | RADIX = Binary; 227 | TREE_INDEX = 4; 228 | TREE_LEVEL = 1; 229 | PARENT = 1; 230 | } 231 | 232 | DISPLAY_LINE 233 | { 234 | CHANNEL = "S[3]"; 235 | EXPAND_STATUS = COLLAPSED; 236 | RADIX = Binary; 237 | TREE_INDEX = 5; 238 | TREE_LEVEL = 1; 239 | PARENT = 1; 240 | } 241 | 242 | DISPLAY_LINE 243 | { 244 | CHANNEL = "S[4]"; 245 | EXPAND_STATUS = COLLAPSED; 246 | RADIX = Binary; 247 | TREE_INDEX = 6; 248 | TREE_LEVEL = 1; 249 | PARENT = 1; 250 | } 251 | 252 | DISPLAY_LINE 253 | { 254 | CHANNEL = "S[5]"; 255 | EXPAND_STATUS = COLLAPSED; 256 | RADIX = Binary; 257 | TREE_INDEX = 7; 258 | TREE_LEVEL = 1; 259 | PARENT = 1; 260 | } 261 | 262 | TIME_BAR 263 | { 264 | TIME = 0; 265 | MASTER = TRUE; 266 | } 267 | ; 268 | -------------------------------------------------------------------------------- /md_pic/wps1.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CodeAlanqian/e-clock/ac6929bfe0df785b47a94b848983913f0d3df45b/md_pic/wps1.png -------------------------------------------------------------------------------- /md_pic/wps10.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CodeAlanqian/e-clock/ac6929bfe0df785b47a94b848983913f0d3df45b/md_pic/wps10.jpg -------------------------------------------------------------------------------- /md_pic/wps11.jpg: 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