├── .gitignore ├── LICENSE ├── README.md ├── iirLowPassSinglePole.v ├── lib.xml ├── oscillator.v ├── sdDac.v ├── servo.v ├── sigmaDelta2ndOrder.v ├── sinc3Filter.v └── testbenches ├── iirLowPassSinglePole_tb.v ├── sdDac_tb.v └── servo_tb.v /.gitignore: -------------------------------------------------------------------------------- 1 | modelsim.ini 2 | work/ 3 | transcript 4 | vsim.wlf 5 | *.swp 6 | 7 | -------------------------------------------------------------------------------- /LICENSE: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Cognoscan/VerilogCogs/HEAD/LICENSE -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Cognoscan/VerilogCogs/HEAD/README.md -------------------------------------------------------------------------------- /iirLowPassSinglePole.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Cognoscan/VerilogCogs/HEAD/iirLowPassSinglePole.v -------------------------------------------------------------------------------- /lib.xml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Cognoscan/VerilogCogs/HEAD/lib.xml -------------------------------------------------------------------------------- /oscillator.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Cognoscan/VerilogCogs/HEAD/oscillator.v -------------------------------------------------------------------------------- /sdDac.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Cognoscan/VerilogCogs/HEAD/sdDac.v -------------------------------------------------------------------------------- /servo.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Cognoscan/VerilogCogs/HEAD/servo.v -------------------------------------------------------------------------------- /sigmaDelta2ndOrder.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Cognoscan/VerilogCogs/HEAD/sigmaDelta2ndOrder.v -------------------------------------------------------------------------------- /sinc3Filter.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Cognoscan/VerilogCogs/HEAD/sinc3Filter.v -------------------------------------------------------------------------------- /testbenches/iirLowPassSinglePole_tb.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Cognoscan/VerilogCogs/HEAD/testbenches/iirLowPassSinglePole_tb.v -------------------------------------------------------------------------------- /testbenches/sdDac_tb.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Cognoscan/VerilogCogs/HEAD/testbenches/sdDac_tb.v -------------------------------------------------------------------------------- /testbenches/servo_tb.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Cognoscan/VerilogCogs/HEAD/testbenches/servo_tb.v --------------------------------------------------------------------------------