├── .gitignore ├── Ben8bit.srcs ├── sim_1 │ └── new │ │ └── top_sim.v └── sources_1 │ ├── ip │ └── ram │ │ └── ram.xci │ ├── new │ ├── alu.v │ ├── control.v │ ├── control.vh │ ├── register.v │ └── top.v │ └── program.coe ├── Ben8bit.xpr ├── README.md ├── ReadmeAssets ├── schematic.pdf └── schematics_top.png └── top_sim_behav.wcfg /.gitignore: -------------------------------------------------------------------------------- 1 | /*.cache 2 | /*.hw 3 | /*.runs 4 | /*.sim 5 | /*.ip_user_files 6 | /*.gen 7 | 8 | .*.swp 9 | -------------------------------------------------------------------------------- /Ben8bit.srcs/sim_1/new/top_sim.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 09/12/2021 01:19:32 PM 7 | // Design Name: 8 | // Module Name: top_sim 9 | // Project Name: 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | 23 | module top_sim( 24 | 25 | ); 26 | 27 | reg clock; 28 | reg reset; 29 | wire [7:0] out; 30 | 31 | top testee( 32 | .clock_in(clock), 33 | .bReset(reset), 34 | .out(out) 35 | ); 36 | 37 | initial 38 | begin 39 | clock = 0; 40 | reset = 0; 41 | forever begin 42 | #500 clock = ~clock; 43 | end 44 | end 45 | 46 | initial begin 47 | #3002 reset = 1; 48 | 49 | #50007 reset = 0; 50 | #10 reset = 1; 51 | end 52 | 53 | endmodule 54 | -------------------------------------------------------------------------------- /Ben8bit.srcs/sources_1/ip/ram/ram.xci: -------------------------------------------------------------------------------- 1 | 2 | 3 | xilinx.com 4 | xci 5 | unknown 6 | 1.0 7 | 8 | 9 | ram 10 | 11 | 12 | 4 13 | 0 14 | 16 15 | ./ 16 | spartan7 17 | 1 18 | 1 19 | 0 20 | 0 21 | 0 22 | 0 23 | 0 24 | 0 25 | 0 26 | 0 27 | 0 28 | 0 29 | 0 30 | 0 31 | 1 32 | 1 33 | ram.mif 34 | 1 35 | 1 36 | 0 37 | 0 38 | 0 39 | 1 40 | 0 41 | 0 42 | 1 43 | 8 44 | ram 45 | 0 46 | ce_overrides_sync_controls 47 | ../../program.coe 48 | false 49 | false 50 | 8 51 | 0 52 | 16 53 | 16 54 | non_registered 55 | false 56 | false 57 | non_registered 58 | single_port_ram 59 | non_registered 60 | false 61 | false 62 | false 63 | false 64 | non_registered 65 | false 66 | false 67 | false 68 | false 69 | false 70 | spartan7 71 | 72 | 73 | xc7s15 74 | ftgb196 75 | VERILOG 76 | 77 | MIXED 78 | -1 79 | 80 | 81 | TRUE 82 | TRUE 83 | IP_Flow 84 | 13 85 | TRUE 86 | ../../../../Ben8bit.gen/sources_1/ip/ram 87 | 88 | . 89 | 2021.1 90 | OUT_OF_CONTEXT 91 | 92 | 93 | 94 | 95 | 96 | 97 | 98 | 99 | 100 | 101 | 102 | 103 | 104 | 105 | 106 | 107 | 108 | 109 | 110 | -------------------------------------------------------------------------------- /Ben8bit.srcs/sources_1/new/alu.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 09/11/2021 08:06:22 PM 7 | // Design Name: 8 | // Module Name: alu 9 | // Project Name: 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | 23 | module alu#(parameter DataBits = 8)( 24 | input [DataBits-1:0] a, 25 | input [DataBits-1:0] b, 26 | input sub_bAdd, 27 | output [DataBits-1:0] result, 28 | output carry_flag, 29 | output zero_flag 30 | ); 31 | 32 | wire [DataBits:0]expanded_result; 33 | assign expanded_result = a+(sub_bAdd ? ~b + 1 : b); 34 | assign result = expanded_result[DataBits-1:0]; 35 | assign carry_flag = expanded_result[DataBits]; 36 | assign zero_flag = expanded_result[DataBits-1:0] == 0; 37 | 38 | endmodule 39 | -------------------------------------------------------------------------------- /Ben8bit.srcs/sources_1/new/control.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 09/11/2021 09:13:34 PM 7 | // Design Name: 8 | // Module Name: control 9 | // Project Name: 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | `include "control.vh" 23 | 24 | module control 25 | ( 26 | input [3:0] instruction, 27 | input clock, 28 | input bReset, 29 | input carry_flag, 30 | input zero_flag, 31 | output reg hlt, 32 | output reg memory_in, 33 | output reg ram_in, 34 | output reg instruction_in, 35 | output reg reg_a_in, 36 | output reg subtract, 37 | output reg reg_b_in, 38 | output reg out_in, 39 | output reg advance_pc, 40 | output reg pc_in, 41 | output reg flags_in, 42 | output reg [`BusSelectorBits-1:0] bus_selector 43 | ); 44 | 45 | reg [2:0]step; 46 | 47 | initial 48 | reset_everything(); 49 | 50 | always@(negedge clock, negedge bReset) 51 | begin 52 | if( ! bReset ) begin 53 | reset_everything(); 54 | end else begin 55 | reset_controls(); 56 | step <= step+1; 57 | if( step<2 ) begin 58 | perform_fetch_cycle(); 59 | end else begin 60 | if( instruction==4'b0000 ) 61 | perform_ins_nop(); 62 | else if( instruction==4'b0001 ) 63 | perform_ins_lda(); 64 | else if( instruction==4'b0010 ) 65 | perform_ins_add(); 66 | else if( instruction==4'b0011 ) 67 | perform_ins_sub(); 68 | else if( instruction==4'b0100 ) 69 | perform_ins_sta(); 70 | else if( instruction==4'b0101 ) 71 | perform_ins_ldi(); 72 | else if( instruction==4'b0110 ) 73 | perform_ins_jmp(); 74 | else if( instruction==4'b1110 ) 75 | perform_ins_out(); 76 | else if( instruction==4'b1111 ) 77 | perform_ins_hlt(); 78 | else 79 | perform_ins_nop(); 80 | end 81 | end 82 | end 83 | 84 | task perform_fetch_cycle(); 85 | begin 86 | if( step==0 ) begin 87 | bus_selector <= `BusIn_PC; 88 | memory_in <= 1; 89 | end else begin 90 | bus_selector <= `BusIn_Memory; 91 | instruction_in <= 1; 92 | advance_pc <= 1; 93 | end 94 | end 95 | endtask 96 | 97 | task perform_ins_nop(); 98 | step <= 0; 99 | endtask 100 | 101 | task perform_ins_lda(); 102 | begin 103 | if( step==2 ) begin 104 | bus_selector <= `BusIn_InstructionRegister; 105 | memory_in <= 1; 106 | end else begin 107 | bus_selector <= `BusIn_Memory; 108 | reg_a_in <= 1; 109 | step <= 0; 110 | end 111 | end 112 | endtask 113 | 114 | task perform_ins_add(); 115 | begin 116 | if( step==2 ) begin 117 | bus_selector <= `BusIn_InstructionRegister; 118 | memory_in <= 1; 119 | end else if( step==3 ) begin 120 | bus_selector <= `BusIn_Memory; 121 | reg_b_in <= 1; 122 | end else begin 123 | bus_selector <= `BusIn_ALU; 124 | reg_a_in <= 1; 125 | step <= 0; 126 | end 127 | end 128 | endtask 129 | 130 | task perform_ins_sub(); 131 | begin 132 | if( step==2 ) begin 133 | bus_selector <= `BusIn_InstructionRegister; 134 | memory_in <= 1; 135 | end else if( step==3 ) begin 136 | bus_selector <= `BusIn_Memory; 137 | reg_b_in <= 1; 138 | end else begin 139 | bus_selector <= `BusIn_ALU; 140 | reg_a_in <= 1; 141 | subtract <= 1; 142 | step <= 0; 143 | end 144 | end 145 | endtask 146 | 147 | task perform_ins_sta(); 148 | begin 149 | if( step==2 ) begin 150 | bus_selector <= `BusIn_InstructionRegister; 151 | memory_in <= 1; 152 | end else begin 153 | bus_selector <= `BusIn_RegA; 154 | ram_in <= 1; 155 | step <= 0; 156 | end 157 | end 158 | endtask 159 | 160 | task perform_ins_ldi(); 161 | begin 162 | bus_selector <= `BusIn_InstructionRegister; 163 | reg_a_in <= 1; 164 | step <= 0; 165 | end 166 | endtask 167 | 168 | task perform_ins_jmp(); 169 | begin 170 | bus_selector <= `BusIn_InstructionRegister; 171 | pc_in <= 1; 172 | step <= 0; 173 | end 174 | endtask 175 | 176 | task perform_ins_out(); 177 | begin 178 | bus_selector <= `BusIn_RegA; 179 | out_in <= 1; 180 | step <= 0; 181 | end 182 | endtask 183 | 184 | task perform_ins_hlt(); 185 | begin 186 | hlt <= 1; 187 | step <= 0; 188 | end 189 | endtask 190 | 191 | task reset_everything(); 192 | begin 193 | step = 0; 194 | reset_controls(); 195 | end 196 | endtask 197 | 198 | task reset_controls(); 199 | begin 200 | hlt <= 0; 201 | memory_in <= 0; 202 | ram_in <= 0; 203 | instruction_in <= 0; 204 | reg_a_in <= 0; 205 | subtract <= 0; 206 | reg_b_in <= 0; 207 | out_in <= 0; 208 | advance_pc <= 0; 209 | pc_in <= 0; 210 | flags_in <= 0; 211 | bus_selector <= `BusIn_None; 212 | end 213 | endtask 214 | 215 | endmodule 216 | -------------------------------------------------------------------------------- /Ben8bit.srcs/sources_1/new/control.vh: -------------------------------------------------------------------------------- 1 | `define BusIn_None 0 2 | `define BusIn_PC 1 3 | `define BusIn_RegA 2 4 | `define BusIn_ALU 3 5 | `define BusIn_RegB 4 6 | 7 | `define BusIn_Memory 5 8 | `define BusIn_InstructionRegister 6 9 | 10 | `define BusIn_NumOptions 7 11 | 12 | `define BusSelectorBits $clog2(`BusIn_NumOptions-1) -------------------------------------------------------------------------------- /Ben8bit.srcs/sources_1/new/register.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 09/11/2021 06:02:01 PM 7 | // Design Name: 8 | // Module Name: register 9 | // Project Name: 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | 23 | module register#(parameter DataBits = 8)( 24 | input [DataBits-1:0] data_in, 25 | output [DataBits-1:0] data_out, 26 | input clock, 27 | input write_enable, 28 | input bReset 29 | ); 30 | 31 | reg [DataBits-1:0]data; 32 | assign data_out = data; 33 | 34 | always@(posedge clock, negedge bReset) 35 | begin 36 | if( !bReset ) 37 | data = 0; 38 | else if( write_enable ) 39 | data = data_in; 40 | end 41 | 42 | endmodule 43 | -------------------------------------------------------------------------------- /Ben8bit.srcs/sources_1/new/top.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 09/11/2021 06:00:10 PM 7 | // Design Name: 8 | // Module Name: top 9 | // Project Name: 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | `include "control.vh" 23 | 24 | module top( 25 | output [7:0] out, 26 | input clock_in, 27 | input bReset 28 | ); 29 | 30 | wire [7:0]bus; 31 | 32 | wire [7:0]bus_inputs[`BusIn_NumOptions-1:0]; 33 | assign bus = bus_inputs[ctl_bus_selector]; 34 | 35 | assign bus_inputs[`BusIn_None] = 0; 36 | 37 | wire clock = clock_in || ctl_hlt; 38 | 39 | wire [3:0]memory_address_value; 40 | register#(.DataBits(4)) memory_address_register( 41 | .data_in(bus), 42 | .data_out(memory_address_value), 43 | .clock(clock), 44 | .write_enable(ctl_memory_in), 45 | .bReset(bReset) 46 | ); 47 | 48 | ram ram( 49 | .a(memory_address_value), 50 | .d(bus), 51 | .clk( clock ), 52 | .we( ctl_ram_in ), 53 | .spo( bus_inputs[`BusIn_Memory] ) 54 | ); 55 | 56 | wire [7:0]instruction_register_value; 57 | register instruction_register( 58 | .data_in(bus), 59 | .data_out(instruction_register_value), 60 | .clock(clock), 61 | .write_enable(ctl_instruction_in), 62 | .bReset(bReset) 63 | ); 64 | assign bus_inputs[`BusIn_InstructionRegister] = {4'b0, instruction_register_value[3:0]}; 65 | 66 | // Control lines 67 | wire ctl_hlt; 68 | wire ctl_memory_in; 69 | wire ctl_ram_in; 70 | wire ctl_instruction_in; 71 | wire ctl_reg_a_in; 72 | wire ctl_subtract; 73 | wire ctl_reg_b_in; 74 | wire ctl_out_in; 75 | wire ctl_advance_pc; 76 | wire ctl_pc_in; 77 | wire ctl_flags_in; 78 | wire [`BusSelectorBits-1:0]ctl_bus_selector; 79 | 80 | // Flags 81 | reg carry_flag; 82 | reg zero_flag; 83 | control control( 84 | .instruction(instruction_register_value[7:4]), 85 | .clock(clock), 86 | .bReset(bReset), 87 | .carry_flag(carry_flag), 88 | .zero_flag(zero_flag), 89 | 90 | // Control lines 91 | .hlt(ctl_hlt), 92 | .memory_in(ctl_memory_in), 93 | .ram_in(ctl_ram_in), 94 | .instruction_in(ctl_instruction_in), 95 | .reg_a_in(ctl_reg_a_in), 96 | .subtract(ctl_subtract), 97 | .reg_b_in(ctl_reg_b_in), 98 | .out_in(ctl_out_in), 99 | .advance_pc(ctl_advance_pc), 100 | .pc_in(ctl_pc_in), 101 | .flags_in(ctl_flags_in), 102 | .bus_selector(ctl_bus_selector) 103 | ); 104 | 105 | wire [3:0]program_counter_value; 106 | register#(.DataBits(4)) program_counter( 107 | .data_in( program_counter_value+1 ), 108 | .data_out( program_counter_value ), 109 | .clock(clock), 110 | .write_enable(ctl_advance_pc), 111 | .bReset(bReset) 112 | ); 113 | assign bus_inputs[`BusIn_PC] = {4'b0, program_counter_value}; 114 | 115 | register reg_a( 116 | .data_in(bus), 117 | .data_out(bus_inputs[`BusIn_RegA]), 118 | .clock(clock), 119 | .write_enable(ctl_reg_a_in), 120 | .bReset(bReset) 121 | ); 122 | 123 | wire carry_flag_value, zero_flag_value; 124 | alu alu( 125 | .a(bus_inputs[`BusIn_RegA]), 126 | .b(bus_inputs[`BusIn_RegB]), 127 | .result(bus_inputs[`BusIn_ALU]), 128 | .sub_bAdd(ctl_subtract), 129 | .carry_flag(carry_flag_value), 130 | .zero_flag(zero_flag_value) 131 | ); 132 | 133 | register reg_b( 134 | .data_in(bus), 135 | .data_out(bus_inputs[`BusIn_RegB]), 136 | .clock(clock), 137 | .write_enable(ctl_reg_b_in), 138 | .bReset(bReset) 139 | ); 140 | register reg_out( 141 | .data_in(bus), 142 | .data_out(out), 143 | .clock(clock), 144 | .write_enable(ctl_out_in), 145 | .bReset(bReset) 146 | ); 147 | 148 | initial 149 | reset_everything(); 150 | 151 | task reset_everything(); 152 | begin 153 | carry_flag <= 0; 154 | zero_flag <= 0; 155 | end 156 | endtask 157 | 158 | endmodule 159 | -------------------------------------------------------------------------------- /Ben8bit.srcs/sources_1/program.coe: -------------------------------------------------------------------------------- 1 | memory_initialization_radix=16; 2 | memory_initialization_vector= 1F, 2E, 4D, E0, F0, 00, 00, 00, 00, 00, 00, 00, 00, 00, 19, 11; 3 | ; 0 - LDA 15 4 | ; 1 - ADD 14 5 | ; 2 - STA 13 6 | ; 3 - OUT 7 | ; 4 - Hlt 8 | ; E - 25 9 | ; F - 17 -------------------------------------------------------------------------------- /Ben8bit.xpr: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 90 | 91 | 92 | 93 | 94 | 95 | 96 | 97 | 98 | 99 | 100 | 101 | 102 | 103 | 104 | 105 | 106 | 107 | 108 | 109 | 110 | 111 | 112 | 113 | 114 | 115 | 116 | 117 | 118 | 119 | 120 | 121 | 122 | 123 | 124 | 125 | 126 | 127 | 128 | 129 | 130 | 131 | 132 | 133 | 134 | 138 | 139 | 140 | 141 | 142 | 144 | 145 | 146 | 147 | 148 | 149 | 150 | 151 | 152 | 153 | 154 | 155 | 156 | 157 | 158 | 159 | 172 | 173 | 174 | 175 | 176 | 178 | 179 | 180 | 181 | 182 | 183 | 184 | 185 | 186 | 187 | 188 | 191 | 192 | 193 | 194 | 195 | 198 | 199 | 201 | 202 | 204 | 205 | 207 | 208 | 210 | 211 | 213 | 214 | 216 | 217 | 218 | 219 | 220 | 221 | Vivado Synthesis Defaults 222 | 223 | 224 | 225 | 226 | 227 | 228 | 229 | 230 | 231 | 232 | Vivado Synthesis Defaults 233 | 234 | 235 | 236 | 237 | 238 | 239 | 240 | 241 | 242 | 243 | 244 | Default settings for Implementation. 245 | 246 | 247 | 248 | 249 | 250 | 251 | 252 | 253 | 254 | 255 | 256 | 257 | 258 | 259 | 260 | 261 | 262 | 263 | Default settings for Implementation. 264 | 265 | 266 | 267 | 268 | 269 | 270 | 271 | 272 | 273 | 274 | 275 | 276 | 277 | 278 | 279 | 280 | 281 | 282 | 283 | 284 | 285 | 286 | 287 | 288 | 289 | 290 | 291 | 292 | 293 | 294 | 295 | 296 | 297 | 298 | 299 | 300 | 301 | 302 | 303 | 304 | 305 | 306 | 307 | default_dashboard 308 | 309 | 310 | 311 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # Verilog Implementation of Ben Eater's 8-bit Breadboard Computer 2 | 3 | ## What is this madness? 4 | This repository contains an implementation, in Verilog, of [Ben Eater's 8-bit computer on a breadboard](https://eater.net/8bit) project. 5 | 6 | ![Project](https://cdn.shopify.com/s/files/1/0089/0647/3536/products/computer-hero-42_550x825.png?v=1544158524) 7 | 8 | ## What's in this repo? 9 | The Verilog in this repo tries to follow closely the schematics for the original, breadboard, project 10 | 11 | ![Schematics](ReadmeAssets/schematics_top.png) 12 | 13 | With that said, moving from breadboards to verilog did require a few changes: 14 | 15 | * The Bus doesn't use tri-state logic. Instead, a demultiplexer is used to select which source drives the bus. 16 | * The project uses Xilinx's RAM IP. As the writes there are clocked, the logic is somewhat different. 17 | * The program is loaded into memory using a `COE` file. No "run time" setting of the memory is possible. 18 | * An external clock is assumed. The only clock related logic is disabling it using an OR gate if the HLT signal is high. 19 | 20 | Most of the changes are in the control logic: 21 | * Since we're not bound by external ICs, all control signals are active high. No inverters needed. 22 | * Due to the changes to the bus, the control circuit sets a 3 bit bus source number (defined in `control.vh`) rather than discreate signals. 23 | * Direct logic is employed to set the microcode. It is not stored in an EEPROM. 24 | * All this really does is move the code from the Arduino flasher to the logic itself. The end result uses LUTs, which are not fundementally 25 | different than an EEPROM. 26 | * The microcode resets the step counter when the instruction is done. This means that different instructions take a different number of cycles. 27 | -------------------------------------------------------------------------------- /ReadmeAssets/schematic.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CompuSAR/Ben8Bit/8b713bd57b47f194c650db5e00591ec73f3f20ee/ReadmeAssets/schematic.pdf -------------------------------------------------------------------------------- /ReadmeAssets/schematics_top.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CompuSAR/Ben8Bit/8b713bd57b47f194c650db5e00591ec73f3f20ee/ReadmeAssets/schematics_top.png -------------------------------------------------------------------------------- /top_sim_behav.wcfg: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | clock 25 | clock 26 | 27 | 28 | reset 29 | reset 30 | 31 | 32 | out[7:0] 33 | out[7:0] 34 | 35 | 36 | bus[7:0] 37 | bus[7:0] 38 | 39 | 40 | bus_inputs[6:0][7:0] 41 | bus_inputs[6:0][7:0] 42 | 43 | 44 | label 45 | [6][7:0] 46 | [6][7:0] 47 | InstReg 48 | 49 | 50 | label 51 | [5][7:0] 52 | [5][7:0] 53 | Memory 54 | 55 | 56 | label 57 | [4][7:0] 58 | [4][7:0] 59 | RegB 60 | 61 | 62 | label 63 | [3][7:0] 64 | [3][7:0] 65 | ALU 66 | 67 | 68 | label 69 | [2][7:0] 70 | [2][7:0] 71 | RegA 72 | 73 | 74 | label 75 | [1][7:0] 76 | [1][7:0] 77 | PC 78 | 79 | 80 | [0][7:0] 81 | [0][7:0] 82 | 83 | 84 | 85 | memory_address_value[3:0] 86 | memory_address_value[3:0] 87 | 88 | 89 | data[3:0] 90 | data[3:0] 91 | 92 | 93 | step[2:0] 94 | step[2:0] 95 | 96 | 97 | instruction_register_value[7:0] 98 | instruction_register_value[7:0] 99 | 100 | 101 | label 102 | expanded_result[8:0] 103 | expanded_result[8:0] 104 | ALU expanded_result[8:0] 105 | 106 | 107 | --------------------------------------------------------------------------------