├── .gitignore ├── sar6502.gen └── .placeholder ├── sar6502.ip_user_files ├── .gitignore └── README.txt ├── sar6502.srcs ├── 14Mhz │ └── new │ │ └── timing.xdc ├── sim_1 │ └── new │ │ ├── .gitignore │ │ ├── Makefile │ │ ├── test_bench.sv │ │ ├── test_bench_behav.wcfg │ │ ├── test_plan.mem │ │ ├── test_program.mem │ │ └── test_program.s ├── sources_1 │ └── new │ │ ├── alu.sv │ │ ├── bus_sources.sv │ │ ├── control_signals.sv │ │ ├── decoder.sv │ │ ├── program_counter.sv │ │ ├── register.sv │ │ ├── sar6502.sv │ │ └── status_register.sv └── utils_1 │ └── imports │ └── synth_1 │ └── .gitignore └── sar6502.xpr /.gitignore: -------------------------------------------------------------------------------- 1 | .*.swp 2 | 3 | /sar6502 4 | 5 | /*.cache 6 | /*.runs 7 | /*.sim 8 | /*.hw 9 | /*.jou 10 | /*.log 11 | -------------------------------------------------------------------------------- /sar6502.gen/.placeholder: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CompuSAR/sar6502/fc8329891279f16bc6fcf804ee25b9667bc0a54b/sar6502.gen/.placeholder -------------------------------------------------------------------------------- /sar6502.ip_user_files/.gitignore: -------------------------------------------------------------------------------- 1 | * 2 | -------------------------------------------------------------------------------- /sar6502.ip_user_files/README.txt: -------------------------------------------------------------------------------- 1 | The files in this directory structure are automatically generated and managed by Vivado. Editing these files is not recommended. 2 | -------------------------------------------------------------------------------- /sar6502.srcs/14Mhz/new/timing.xdc: -------------------------------------------------------------------------------- 1 | create_clock -period 70.000 -name phi2 -waveform {0.000 35.000} [get_ports phi2] 2 | set_input_delay -clock [get_clocks phi2] -clock_fall -min -add_delay 10.000 [get_ports {data_in[*]}] 3 | set_input_delay -clock [get_clocks phi2] -clock_fall -max -add_delay 60.000 [get_ports {data_in[*]}] 4 | set_input_delay -clock [get_clocks phi2] -clock_fall -min -add_delay 10.000 [get_ports RES] 5 | set_input_delay -clock [get_clocks phi2] -clock_fall -max -add_delay 60.000 [get_ports RES] 6 | set_output_delay -clock [get_clocks phi2] -clock_fall -min -add_delay -1.000 [get_ports {address[*]}] 7 | set_output_delay -clock [get_clocks phi2] -clock_fall -max -add_delay 41.000 [get_ports {address[*]}] 8 | set_output_delay -clock [get_clocks phi2] -clock_fall -min -add_delay -1.000 [get_ports {data_out[*]}] 9 | set_output_delay -clock [get_clocks phi2] -clock_fall -max -add_delay 11.000 [get_ports {data_out[*]}] 10 | set_output_delay -clock [get_clocks phi2] -clock_fall -min -add_delay -1.000 [get_ports ML] 11 | set_output_delay -clock [get_clocks phi2] -clock_fall -max -add_delay 41.000 [get_ports ML] 12 | set_output_delay -clock [get_clocks phi2] -clock_fall -min -add_delay -1.000 [get_ports VP] 13 | set_output_delay -clock [get_clocks phi2] -clock_fall -max -add_delay 41.000 [get_ports VP] 14 | set_output_delay -clock [get_clocks phi2] -clock_fall -min -add_delay -1.000 [get_ports rW] 15 | set_output_delay -clock [get_clocks phi2] -clock_fall -max -add_delay 41.000 [get_ports rW] 16 | set_output_delay -clock [get_clocks phi2] -clock_fall -min -add_delay -1.000 [get_ports sync] 17 | set_output_delay -clock [get_clocks phi2] -clock_fall -max -add_delay 41.000 [get_ports sync] 18 | -------------------------------------------------------------------------------- /sar6502.srcs/sim_1/new/.gitignore: -------------------------------------------------------------------------------- 1 | *.dep 2 | *.lst 3 | *_wdc.mem 4 | *.out 5 | -------------------------------------------------------------------------------- /sar6502.srcs/sim_1/new/Makefile: -------------------------------------------------------------------------------- 1 | TEST_HARNESS_PROJECT:=$(shell realpath ../../../../test_harness) 2 | USBPORT=/dev/ttyUSB0 3 | 4 | test_program.mem: test_program_wdc.mem 5 | cp -a $< $@ 6 | 7 | test_program_wdc.mem: test_program.s 8 | $(MAKE) -f $(TEST_HARNESS_PROJECT)/test_program/Makefile BASEDIR=$(TEST_HARNESS_PROJECT)/test_program $@ 9 | 10 | test_plan.mem: test_program.mem 11 | PYTHONPATH=$(TEST_HARNESS_PROJECT)/host $(TEST_HARNESS_PROJECT)/host/gen_test_plan $< $@ -p $(USBPORT) 12 | 13 | clean: 14 | $(RM) *.mem *.lst *.out 15 | 16 | generate: test_plan.mem 17 | .PHONY: generate clean 18 | -------------------------------------------------------------------------------- /sar6502.srcs/sim_1/new/test_bench.sv: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Design Name: 7 | // Project Name: 8 | // Target Devices: 9 | // Tool Versions: 10 | // Description: 11 | // 12 | // Dependencies: 13 | // 14 | // Revision: 15 | // Revision 0.01 - File Created 16 | // Additional Comments: 17 | // 18 | ////////////////////////////////////////////////////////////////////////////////// 19 | 20 | 21 | ////////////////////////////////////////////////////////////////////////////////// 22 | // Company: Some Assembly Required 23 | // Engineer: Shachar Shemesh 24 | // 25 | // Create Date: 02/24/2022 05:26:21 AM 26 | // Design Name: sar6502 27 | // Module Name: test_bench 28 | // Project Name: CompuSAR 29 | // Target Devices: 30 | // Tool Versions: 31 | // Description: CPU test bench 32 | // 33 | // Dependencies: 34 | // 35 | // Revision: 36 | // Revision 0.01 - File Created 37 | // Additional Comments: 38 | // 39 | // License: 40 | // Copyright (C) 2022. 41 | // Copyright owners listed in AUTHORS file. 42 | // 43 | // This program is free software; you can redistribute it and/or modify 44 | // it under the terms of the GNU General Public License as published by 45 | // the Free Software Foundation; either version 2 of the License, or 46 | // (at your option) any later version. 47 | // 48 | // This program is distributed in the hope that it will be useful, 49 | // but WITHOUT ANY WARRANTY; without even the implied warranty of 50 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 51 | // GNU General Public License for more details. 52 | // 53 | // You should have received a copy of the GNU General Public License 54 | // along with this program; if not, write to the Free Software 55 | // Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA 56 | // 57 | ////////////////////////////////////////////////////////////////////////////////// 58 | 59 | module test_bench( 60 | ); 61 | 62 | // Timing parameters for 14Mhz operation 63 | localparam tACC = 30; // Access time (min) 64 | localparam tAH = 10; // Address hold time (min) 65 | localparam tADS = 30; // Address setup time (max) 66 | localparam tBVD = 25; // BE to valid data (max) 67 | localparam tPWH = 35; // Clock pulse width high (min) 68 | localparam tPWL = 35; // Clock pulse width low (min) 69 | localparam tCYC = tPWH+tPWL; // Cycle time (min) 70 | localparam tF = 5; // Fall time (max) 71 | localparam tR = 5; // Rise time (max) 72 | localparam tPCH = 10; // Processor control hold time (min) 73 | localparam tPCS = 10; // Processor control setup time (min) 74 | localparam tDHR = 10; // Read data hold time (min) 75 | localparam tDSR = 10; // Read data setup time (min) 76 | localparam tMDS = 25; // Write data delay time (max) 77 | localparam tDHW = 10; // Write data hold time (min) 78 | 79 | logic clock; 80 | logic [15:0] address_bus; 81 | logic [7:0] data_in, data_out; 82 | 83 | logic read_Write, vector_pull, memory_lock, sync, incompatible; 84 | 85 | typedef enum { SigReset, SigIrq, SigNmi, SigSo, SigReady, Sig_NumElements } signal_types; 86 | logic signals[Sig_NumElements-1:0]; 87 | 88 | sar6502#(.CPU_VARIANT(2)) cpu( 89 | .phi2(clock), 90 | .data_in(data_in), 91 | .RES( !signals[SigReset] ), 92 | .rdy( !signals[SigReady] ), 93 | .IRQ( !signals[SigIrq] ), 94 | .NMI( !signals[SigNmi] ), 95 | .SO( !signals[SigSo] ), 96 | 97 | .address(address_bus), 98 | .data_out(data_out), 99 | .rW(read_Write), 100 | .VP(vector_pull), 101 | .ML(memory_lock), 102 | .sync(sync), 103 | .incompatible(incompatible) 104 | ); 105 | 106 | logic [7:0]memory[65536]; 107 | logic [35:0]test_plan[30000]; 108 | 109 | struct { 110 | int delay; 111 | int count; 112 | } pending_signals[Sig_NumElements-1:0]; 113 | 114 | logic [15:0]address_latched; 115 | 116 | initial begin 117 | // Clock and memory read handling 118 | clock = 0; 119 | $readmemh("test_program.mem", memory); 120 | $readmemh("test_plan.mem", test_plan); 121 | 122 | foreach( signals[i] ) begin 123 | pending_signals[i].delay = 0; 124 | pending_signals[i].count = 0; 125 | signals[i] = 0; 126 | end 127 | 128 | pending_signals[SigReset].delay = 2; 129 | pending_signals[SigReset].count = 5; 130 | 131 | forever begin 132 | #tDHR data_in = 8'bX; 133 | #(tPWL-tDHR) clock = 1; 134 | address_latched = address_bus; 135 | clock_high(); 136 | #(tPWH-tDSR) data_in=memory[address_latched]; 137 | #tDSR 138 | clock_low(); 139 | clock = 0; 140 | end 141 | end 142 | 143 | int cycle_num = 0; 144 | 145 | task clock_high(); 146 | // Signal control 147 | foreach( signals[i] ) begin 148 | if( signals[i]==1 || pending_signals[i].delay>0 ) begin 149 | if( pending_signals[i].delay>0 ) begin 150 | pending_signals[i].delay--; 151 | 152 | if( pending_signals[i].delay==0 ) 153 | signals[i] = 1; 154 | end else begin 155 | pending_signals[i].count--; 156 | 157 | if( pending_signals[i].count==0 ) 158 | signals[i] = 0; 159 | end 160 | end 161 | end 162 | endtask 163 | 164 | task clock_low(); 165 | automatic logic [35:0]plan_line; 166 | begin 167 | // Verification 168 | if( cycle_num==0 ) begin 169 | if( address_bus !== 16'hfffc ) 170 | // Waiting to begin 171 | return; 172 | else 173 | cycle_num=1; 174 | end 175 | 176 | plan_line = test_plan[cycle_num]; 177 | casex( plan_line[35:32] ) 178 | 4'h1: verify_cycle(plan_line); 179 | default: begin 180 | $display("Unknown instruction type at cycle %d", cycle_num); 181 | $finish(); 182 | end 183 | endcase 184 | 185 | if( address_bus[15:8]===8'h02 && read_Write===1'b0 ) 186 | perform_io(); 187 | 188 | cycle_num++; 189 | end 190 | endtask 191 | 192 | task verify_cycle( input logic [35:0]plan_line ); 193 | begin 194 | if( !incompatible || read_Write==0 || plan_line[0]==0 ) begin 195 | assert_state( address_bus, plan_line[31:16], "Address bus" ); 196 | end else 197 | $display("Known incompatibility cycle %d. Not comparing address %x to desired %x", cycle_num, address_bus, plan_line[31:16]); 198 | assert_state( read_Write, plan_line[0], "Read/write" ); 199 | assert_state( sync, plan_line[1], "Sync" ); 200 | if( plan_line[2]==1 ) // Due to bug in wd65c02, allow our ML to be active while theirs isn't. 201 | assert_state( memory_lock, !plan_line[2], "Memory lock" ); 202 | assert_state( vector_pull, !plan_line[3], "Vector pull" ); 203 | 204 | if( read_Write ) begin 205 | // Read 206 | if( !incompatible ) 207 | assert_state( data_in, plan_line[15:8], "Data in" ); 208 | end else begin 209 | // Write 210 | memory[address_bus] = data_out; 211 | assert_state( data_out, plan_line[15:8], "Data out" ); 212 | end 213 | end 214 | endtask 215 | 216 | task assert_state( input logic [15:0]actual, input logic [15:0]expected, input string name ); 217 | if( actual === expected ) 218 | return; 219 | 220 | $display("Verification failed on cycle %d time %t pin %s: expected %x, received %x on address %04x", 221 | cycle_num, $time, name, expected, actual, address_bus); 222 | $finish(); 223 | endtask 224 | 225 | task perform_io(); 226 | $display("Cycle %d: IO writing %x to %x", cycle_num, data_out, address_bus); 227 | 228 | casex( address_bus[7:0] ) 229 | 8'h00: begin 230 | $display("Test finished successfully"); 231 | $finish(); 232 | end 233 | 8'h80: pending_signals[SigReady].count = data_out; 234 | 8'h81: pending_signals[SigReady].delay = data_out; 235 | 8'h82: pending_signals[SigSo].count = data_out; 236 | 8'h83: pending_signals[SigSo].delay = data_out; 237 | 8'hfa: pending_signals[SigNmi].count = data_out; 238 | 8'hfb: pending_signals[SigNmi].delay = data_out; 239 | 8'hfc: pending_signals[SigReset].count = data_out; 240 | 8'hfd: pending_signals[SigReset].delay = data_out; 241 | 8'hfe: pending_signals[SigIrq].count = data_out; 242 | 8'hff: pending_signals[SigIrq].delay = data_out; 243 | endcase 244 | endtask 245 | 246 | endmodule 247 | -------------------------------------------------------------------------------- /sar6502.srcs/sim_1/new/test_bench_behav.wcfg: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | clock 27 | clock 28 | 29 | 30 | sync 31 | sync 32 | 33 | 34 | address_bus[15:0] 35 | address_bus[15:0] 36 | #008080 37 | true 38 | 39 | 40 | incompatible 41 | incompatible 42 | #800080 43 | true 44 | 45 | 46 | data_in[7:0] 47 | data_in[7:0] 48 | #00FFFF 49 | true 50 | 51 | 52 | data_out[7:0] 53 | data_out[7:0] 54 | #00FFFF 55 | true 56 | 57 | 58 | read_Write 59 | read_Write 60 | 61 | 62 | op_cycle[15:0] 63 | op_cycle[15:0] 64 | #0000FF 65 | true 66 | 67 | 68 | label 69 | address_out[15:0] 70 | address_out[15:0] 71 | PC 72 | 73 | 74 | label 75 | data_out[7:0] 76 | data_out[7:0] 77 | A 78 | #800080 79 | true 80 | 81 | 82 | label 83 | data_out[7:0] 84 | data_out[7:0] 85 | X 86 | #800080 87 | true 88 | 89 | 90 | label 91 | data_out[7:0] 92 | data_out[7:0] 93 | Y 94 | #800080 95 | true 96 | 97 | 98 | label 99 | data_out[7:0] 100 | data_out[7:0] 101 | SP 102 | 103 | 104 | label 105 | data_out[7:0] 106 | data_out[7:0] 107 | DL low 108 | 109 | 110 | label 111 | data_out[7:0] 112 | data_out[7:0] 113 | DL high 114 | 115 | 116 | label 117 | a[7:0] 118 | a[7:0] 119 | ALU a 120 | 121 | 122 | label 123 | b[7:0] 124 | b[7:0] 125 | ALU b 126 | 127 | 128 | label 129 | carry_in 130 | carry_in 131 | ALU carry_in 132 | 133 | 134 | inverse_b 135 | inverse_b 136 | 137 | 138 | label 139 | control[31:0] 140 | control[31:0] 141 | ALU op 142 | 143 | 144 | label 145 | result[7:0] 146 | result[7:0] 147 | ALU result 148 | 149 | 150 | label 151 | carry_out 152 | carry_out 153 | ALU carry_out 154 | 155 | 156 | label 157 | overflow_out 158 | overflow_out 159 | ALU overflow_out 160 | 161 | 162 | label 163 | data_in_l[7:0] 164 | data_in_l[7:0] 165 | Data in latched 166 | 167 | 168 | label 169 | data_in_l[7:0] 170 | data_in_l[7:0] 171 | data_in latched 172 | 173 | 174 | RES 175 | RES 176 | 177 | 178 | rdy 179 | rdy 180 | 181 | 182 | IRQ 183 | IRQ 184 | 185 | 186 | NMI 187 | NMI 188 | 189 | 190 | SO 191 | SO 192 | 193 | 194 | vector_pull 195 | vector_pull 196 | 197 | 198 | memory_lock 199 | memory_lock 200 | 201 | 202 | ctrl_signals[18:0] 203 | ctrl_signals[18:0] 204 | 205 | 206 | cycle_num[31:0] 207 | cycle_num[31:0] 208 | UNSIGNEDDECRADIX 209 | #FFFFFF 210 | true 211 | 212 | 213 | address_bus_high_source[31:0] 214 | address_bus_high_source[31:0] 215 | 216 | 217 | address_bus_low_source[31:0] 218 | address_bus_low_source[31:0] 219 | 220 | 221 | data_bus_source[31:0] 222 | data_bus_source[31:0] 223 | 224 | 225 | active_addr_mode[31:0] 226 | active_addr_mode[31:0] 227 | 228 | 229 | active_op[31:0] 230 | active_op[31:0] 231 | 232 | 233 | int_state[31:0] 234 | int_state[31:0] 235 | 236 | 237 | -------------------------------------------------------------------------------- /sar6502.srcs/sim_1/new/test_program.mem: -------------------------------------------------------------------------------- 1 | @0000 5e // test_program.s:24 .byte $5e ; eor zp,x and (zp,x) tests (MSB) 2 | @000a cc // test_program.s:27 .byte $cc, $d2 ; cmp zp,x test 3 | @000b d2 4 | @000e f3 // test_program.s:30 bit_zp_test: .byte $f3 5 | @0014 01 // test_program.s:33 .byte $01 ; dec zp,x test 6 | @0028 7a // test_program.s:36 .byte $7a ; bit zp,x test 7 | @0029 6e // test_program.s:37 .byte $6e ; asl zp,x test 8 | @002a 00 // test_program.s:39 sta_zp_test: .byte 0, 0, $34 9 | @002b 00 10 | @002c 34 11 | @002e 65 // test_program.s:42 rmb_zp_test: .byte $65, $65 ^ $ff 12 | @002f 9a 13 | @0030 f0 // test_program.s:43 smb_zp_test: .byte $f0, $f0 ^ $ff 14 | @0031 0f 15 | @0034 a8 // test_program.s:46 .byte $a8 ; ldy zp,x 16 | @003f 2c // test_program.s:48 ldy_zp_test: .byte $2c 17 | @004e 41 // test_program.s:51 rol_zp_test: .byte $41, $9b, $60 18 | @004f 9b 19 | @0050 60 20 | @005f 88 // test_program.s:55 .byte $88, $70 21 | @0060 70 22 | @0066 75 // test_program.s:58 trb_zp_test: .byte $75, $42 23 | @0067 42 24 | @0068 a3 // test_program.s:59 tsb_zp_test: .byte $a3 25 | @0069 d3 // test_program.s:62 asl_zp_test: .byte $d3 26 | @0074 f8 // test_program.s:64 dec_zp_test: .byte $f8 27 | @0078 4d // test_program.s:67 ldx_zp_test: .byte $4d 28 | @0092 6e // test_program.s:70 .byte $6e ; lsr zp,x 29 | @0099 50 // test_program.s:73 branch_bit_test: .byte $50 30 | @009a f5 // test_program.s:75 .byte $f5 ; ldx zp,y 31 | @009d 7e // test_program.s:78 lsr_zp_test: .byte $7e 32 | @00a9 38 ae // test_program.s:81 lda_zp_test: .word lda_indirect_test 33 | @00ec 88 // test_program.s:84 .byte $88, $d5, $13 34 | @00ed d5 35 | @00ee 13 36 | @00ef c2 // test_program.s:86 .byte $c2 37 | @00f0 4f // test_program.s:89 .byte $4f, $0a, $8f 38 | @00f1 0a 39 | @00f2 8f 40 | @00ff e6 // test_program.s:92 .byte $e6 ; eor zp,x and (zp,x) tests (LSB) 41 | @0100 7a // test_program.s:95 .dc $ff,$7a ; Put stack in known state 42 | 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a 7a // Array 43 | @01ff 7a // test_program.s:96 .byte $7a ; Due to a limitation of our lst parser, need to mark the end point 44 | @0300 ea // test_program.s:101 nop 45 | @0301 ea // test_program.s:102 nop 46 | @0302 ea // test_program.s:103 nop 47 | @0303 20 ef 40 // test_program.s:104 jsr flags_dump 48 | @0306 a9 03 // test_program.s:106 lda #$03 49 | @0308 20 ef 40 // test_program.s:107 jsr flags_dump 50 | @030b a5 a9 // test_program.s:108 lda lda_zp_test ; Make sure we don't treat the operand as an opcode 51 | @030d 20 ef 40 // test_program.s:109 jsr flags_dump 52 | @0310 ad 21 6d // test_program.s:111 lda lda_abs_test 53 | @0313 20 ef 40 // test_program.s:112 jsr flags_dump 54 | @0316 a2 c0 // test_program.s:114 ldx #$c0 55 | @0318 a0 30 // test_program.s:115 ldy #$30 56 | @031a da // test_program.s:116 phx 57 | @031b 5a // test_program.s:117 phy 58 | @031c a9 ff // test_program.s:120 lda #$ff 59 | @031e 8d fe 01 // test_program.s:121 sta $1fe 60 | @0321 9c ff 01 // test_program.s:122 stz $1ff 61 | @0324 28 // test_program.s:124 plp 62 | @0325 20 ef 40 // test_program.s:125 jsr flags_dump 63 | @0328 28 // test_program.s:126 plp 64 | @0329 20 ef 40 // test_program.s:127 jsr flags_dump 65 | @032c 38 // test_program.s:128 sec 66 | @032d 20 ef 40 // test_program.s:129 jsr flags_dump 67 | @0330 f8 // test_program.s:130 sed 68 | @0331 20 ef 40 // test_program.s:131 jsr flags_dump 69 | @0334 78 // test_program.s:132 sei 70 | @0335 20 ef 40 // test_program.s:133 jsr flags_dump 71 | @0338 18 // test_program.s:134 clc 72 | @0339 20 ef 40 // test_program.s:135 jsr flags_dump 73 | @033c d8 // test_program.s:136 cld 74 | @033d 20 ef 40 // test_program.s:137 jsr flags_dump 75 | @0340 58 // test_program.s:138 cli 76 | @0341 20 ef 40 // test_program.s:139 jsr flags_dump 77 | @0344 b8 // test_program.s:140 clv 78 | @0345 20 ef 40 // test_program.s:141 jsr flags_dump 79 | @0348 ad 21 6d // test_program.s:144 lda lda_abs_test 80 | @034b bd 21 6d // test_program.s:145 lda lda_abs_test,x ; No page transition 81 | @034e bd 61 6c // test_program.s:146 lda lda_abs_test-$c0,x ; With page transition 82 | @0351 b9 21 6d // test_program.s:147 lda lda_abs_test,y ; No page transition 83 | @0354 b9 f1 6c // test_program.s:148 lda lda_abs_test-$30,y ; With page transition 84 | @0357 a5 a9 // test_program.s:149 lda lda_zp_test 85 | @0359 a1 e9 // test_program.s:151 lda (lda_zp_test+$100-$c0,x) 86 | @035b b5 e9 // test_program.s:153 lda lda_zp_test+$100-$c0,x 87 | @035d b2 a9 // test_program.s:155 lda (lda_zp_test) 88 | @035f b1 a9 // test_program.s:157 lda (lda_zp_test),y ; No page transition 89 | @0361 a0 f0 // test_program.s:158 ldy #$f0 90 | @0363 b1 a9 // test_program.s:159 lda (lda_zp_test),y ; With page transition 91 | @0365 a9 01 // test_program.s:163 lda #1 92 | @0367 0e 10 85 // test_program.s:165 asl asl_abs_test 93 | @036a 20 ef 40 // test_program.s:166 jsr flags_dump 94 | @036d 1e 10 85 // test_program.s:167 asl asl_abs_test,x 95 | @0370 20 ef 40 // test_program.s:168 jsr flags_dump 96 | @0373 06 69 // test_program.s:169 asl asl_zp_test 97 | @0375 20 ef 40 // test_program.s:170 jsr flags_dump 98 | @0378 16 69 // test_program.s:171 asl asl_zp_test,x 99 | @037a 20 ef 40 // test_program.s:172 jsr flags_dump 100 | @037d 0a // test_program.s:173 asl 101 | @037e 20 ef 40 // test_program.s:174 jsr flags_dump 102 | @0381 d0 e4 // test_program.s:175 bne asl_loop 103 | @0383 a2 02 // test_program.s:178 ldx #2 104 | @0385 a0 01 // test_program.s:179 ldy #1 105 | @0387 6d ce 7a // test_program.s:181 adc adc_abs_test 106 | @038a 48 // test_program.s:182 pha 107 | @038b 08 // test_program.s:183 php 108 | @038c 2d ce 7a // test_program.s:184 and adc_abs_test 109 | @038f 48 // test_program.s:185 pha 110 | @0390 08 // test_program.s:186 php 111 | @0391 7d ce 7a // test_program.s:187 adc adc_abs_test,x 112 | @0394 48 // test_program.s:188 pha 113 | @0395 08 // test_program.s:189 php 114 | @0396 3d ce 7a // test_program.s:190 and adc_abs_test,x 115 | @0399 48 // test_program.s:191 pha 116 | @039a 08 // test_program.s:192 php 117 | @039b 79 ce 7a // test_program.s:193 adc adc_abs_test,y 118 | @039e 48 // test_program.s:194 pha 119 | @039f 08 // test_program.s:195 php 120 | @03a0 39 ce 7a // test_program.s:196 and adc_abs_test,y 121 | @03a3 48 // test_program.s:197 pha 122 | @03a4 08 // test_program.s:198 php 123 | @03a5 69 cd // test_program.s:199 adc #$cd 124 | @03a7 48 // test_program.s:200 pha 125 | @03a8 08 // test_program.s:201 php 126 | @03a9 29 a7 // test_program.s:202 and #$a7 127 | @03ab 48 // test_program.s:203 pha 128 | @03ac 08 // test_program.s:204 php 129 | @03ad 65 ec // test_program.s:205 adc adc_zp_test 130 | @03af 48 // test_program.s:206 pha 131 | @03b0 08 // test_program.s:207 php 132 | @03b1 25 ec // test_program.s:208 and adc_zp_test 133 | @03b3 48 // test_program.s:209 pha 134 | @03b4 08 // test_program.s:210 php 135 | @03b5 61 ec // test_program.s:211 adc (adc_zp_test,x) 136 | @03b7 48 // test_program.s:212 pha 137 | @03b8 08 // test_program.s:213 php 138 | @03b9 21 ec // test_program.s:214 and (adc_zp_test,x) 139 | @03bb 48 // test_program.s:215 pha 140 | @03bc 08 // test_program.s:216 php 141 | @03bd 75 ec // test_program.s:217 adc adc_zp_test,x 142 | @03bf 48 // test_program.s:218 pha 143 | @03c0 08 // test_program.s:219 php 144 | @03c1 35 ec // test_program.s:220 and adc_zp_test,x 145 | @03c3 48 // test_program.s:221 pha 146 | @03c4 08 // test_program.s:222 php 147 | @03c5 72 ec // test_program.s:223 adc (adc_zp_test) 148 | @03c7 48 // test_program.s:224 pha 149 | @03c8 08 // test_program.s:225 php 150 | @03c9 32 ec // test_program.s:226 and (adc_zp_test) 151 | @03cb 48 // test_program.s:227 pha 152 | @03cc 08 // test_program.s:228 php 153 | @03cd 71 ec // test_program.s:229 adc (adc_zp_test),y 154 | @03cf 48 // test_program.s:230 pha 155 | @03d0 08 // test_program.s:231 php 156 | @03d1 31 ec // test_program.s:232 and (adc_zp_test),y 157 | @03d3 48 // test_program.s:233 pha 158 | @03d4 08 // test_program.s:234 php 159 | @03d5 c8 // test_program.s:235 iny 160 | @03d6 ca // test_program.s:236 dex 161 | @03d7 d0 ae // test_program.s:237 bne adc_loop 162 | @03d9 ed ce 7a // test_program.s:240 sbc adc_abs_test 163 | @03dc 48 // test_program.s:241 pha 164 | @03dd 08 // test_program.s:242 php 165 | @03de 0d ce 7a // test_program.s:243 ora adc_abs_test 166 | @03e1 48 // test_program.s:244 pha 167 | @03e2 08 // test_program.s:245 php 168 | @03e3 fd ce 7a // test_program.s:246 sbc adc_abs_test,x 169 | @03e6 48 // test_program.s:247 pha 170 | @03e7 08 // test_program.s:248 php 171 | @03e8 1d ce 7a // test_program.s:249 ora adc_abs_test,x 172 | @03eb 48 // test_program.s:250 pha 173 | @03ec 08 // test_program.s:251 php 174 | @03ed f9 ce 7a // test_program.s:252 sbc adc_abs_test,y 175 | @03f0 48 // test_program.s:253 pha 176 | @03f1 08 // test_program.s:254 php 177 | @03f2 19 ce 7a // test_program.s:255 ora adc_abs_test,y 178 | @03f5 48 // test_program.s:256 pha 179 | @03f6 08 // test_program.s:257 php 180 | @03f7 e9 cd // test_program.s:258 sbc #$cd 181 | @03f9 48 // test_program.s:259 pha 182 | @03fa 08 // test_program.s:260 php 183 | @03fb 09 cd // test_program.s:261 ora #$cd 184 | @03fd 48 // test_program.s:262 pha 185 | @03fe 08 // test_program.s:263 php 186 | @03ff e5 ec // test_program.s:264 sbc adc_zp_test 187 | @0401 48 // test_program.s:265 pha 188 | @0402 08 // test_program.s:266 php 189 | @0403 05 ec // test_program.s:267 ora adc_zp_test 190 | @0405 48 // test_program.s:268 pha 191 | @0406 08 // test_program.s:269 php 192 | @0407 e1 ec // test_program.s:270 sbc (adc_zp_test,x) 193 | @0409 48 // test_program.s:271 pha 194 | @040a 08 // test_program.s:272 php 195 | @040b 01 ec // test_program.s:273 ora (adc_zp_test,x) 196 | @040d 48 // test_program.s:274 pha 197 | @040e 08 // test_program.s:275 php 198 | @040f f5 ec // test_program.s:276 sbc adc_zp_test,x 199 | @0411 48 // test_program.s:277 pha 200 | @0412 08 // test_program.s:278 php 201 | @0413 15 ec // test_program.s:279 ora adc_zp_test,x 202 | @0415 48 // test_program.s:280 pha 203 | @0416 08 // test_program.s:281 php 204 | @0417 f2 ec // test_program.s:282 sbc (adc_zp_test) 205 | @0419 48 // test_program.s:283 pha 206 | @041a 08 // test_program.s:284 php 207 | @041b 12 ec // test_program.s:285 ora (adc_zp_test) 208 | @041d 48 // test_program.s:286 pha 209 | @041e 08 // test_program.s:287 php 210 | @041f f1 ec // test_program.s:288 sbc (adc_zp_test),y 211 | @0421 48 // test_program.s:289 pha 212 | @0422 08 // test_program.s:290 php 213 | @0423 11 ec // test_program.s:291 ora (adc_zp_test),y 214 | @0425 48 // test_program.s:292 pha 215 | @0426 08 // test_program.s:293 php 216 | @0427 e8 // test_program.s:294 inx 217 | @0428 88 // test_program.s:295 dey 218 | @0429 d0 ae // test_program.s:296 bne sbc_loop 219 | @042b a9 4f // test_program.s:299 lda #$4f 220 | @042d 08 // test_program.s:300 php 221 | @042e a2 1a // test_program.s:301 ldx #$1a 222 | @0430 08 // test_program.s:302 php 223 | @0431 a0 22 // test_program.s:303 ldy #$22 224 | @0433 08 // test_program.s:304 php 225 | @0434 2c 90 16 // test_program.s:306 bit bit_abs_test 226 | @0437 08 // test_program.s:307 php 227 | @0438 3c 90 16 // test_program.s:308 bit bit_abs_test,x 228 | @043b 08 // test_program.s:309 php 229 | @043c 89 b0 // test_program.s:310 bit #$b0 230 | @043e 08 // test_program.s:311 php 231 | @043f 24 0e // test_program.s:312 bit bit_zp_test 232 | @0441 08 // test_program.s:313 php 233 | @0442 34 0e // test_program.s:314 bit bit_zp_test,x 234 | @0444 08 // test_program.s:315 php 235 | @0445 f8 // test_program.s:318 sed 236 | @0446 58 // test_program.s:319 cli 237 | @0447 00 // test_program.s:320 brk 238 | @0448 01 // test_program.s:321 .byte $1 239 | @0449 d8 // test_program.s:322 cld 240 | @044a 78 // test_program.s:323 sei 241 | @044b 00 // test_program.s:324 brk 242 | @044c 02 // test_program.s:325 .byte $2 243 | @044d cd 87 37 // test_program.s:328 cmp cmp_abs_test 244 | @0450 08 // test_program.s:329 php 245 | @0451 dd 87 37 // test_program.s:330 cmp cmp_abs_test,x 246 | @0454 08 // test_program.s:331 php 247 | @0455 d9 87 37 // test_program.s:332 cmp cmp_abs_test,y 248 | @0458 08 // test_program.s:333 php 249 | @0459 c9 db // test_program.s:334 cmp #$db 250 | @045b 08 // test_program.s:335 php 251 | @045c c5 f0 // test_program.s:336 cmp cmp_zp_test 252 | @045e 08 // test_program.s:337 php 253 | @045f c1 f0 // test_program.s:338 cmp (cmp_zp_test,x) 254 | @0461 08 // test_program.s:339 php 255 | @0462 d5 f0 // test_program.s:340 cmp cmp_zp_test,x 256 | @0464 08 // test_program.s:341 php 257 | @0465 d2 f0 // test_program.s:342 cmp (cmp_zp_test) 258 | @0467 08 // test_program.s:343 php 259 | @0468 d1 f0 // test_program.s:344 cmp (cmp_zp_test),y 260 | @046a 08 // test_program.s:345 php 261 | @046b c9 4e // test_program.s:346 cmp #$4e 262 | @046d 08 // test_program.s:347 php 263 | @046e c9 4f // test_program.s:348 cmp #$4f 264 | @0470 08 // test_program.s:349 php 265 | @0471 c9 50 // test_program.s:350 cmp #$50 266 | @0473 08 // test_program.s:351 php 267 | @0474 ec 87 37 // test_program.s:354 cpx cmp_abs_test 268 | @0477 08 // test_program.s:355 php 269 | @0478 e0 db // test_program.s:356 cpx #$db 270 | @047a 08 // test_program.s:357 php 271 | @047b e4 f0 // test_program.s:358 cpx cmp_zp_test 272 | @047d 08 // test_program.s:359 php 273 | @047e e0 19 // test_program.s:360 cpx #$19 274 | @0480 08 // test_program.s:361 php 275 | @0481 e0 1a // test_program.s:362 cpx #$1a 276 | @0483 08 // test_program.s:363 php 277 | @0484 e0 1b // test_program.s:364 cpx #$1b 278 | @0486 08 // test_program.s:365 php 279 | @0487 a2 a0 // test_program.s:366 ldx #$a0 280 | @0489 e0 00 // test_program.s:367 cpx #$0 281 | @048b 08 // test_program.s:368 php 282 | @048c cc 87 37 // test_program.s:371 cpy cmp_abs_test 283 | @048f 08 // test_program.s:372 php 284 | @0490 c0 db // test_program.s:373 cpy #$db 285 | @0492 08 // test_program.s:374 php 286 | @0493 c4 f0 // test_program.s:375 cpy cmp_zp_test 287 | @0495 08 // test_program.s:376 php 288 | @0496 c0 19 // test_program.s:377 cpy #$19 289 | @0498 08 // test_program.s:378 php 290 | @0499 c0 1a // test_program.s:379 cpy #$1a 291 | @049b 08 // test_program.s:380 php 292 | @049c c0 1b // test_program.s:381 cpy #$1b 293 | @049e 08 // test_program.s:382 php 294 | @049f a2 a0 // test_program.s:383 ldx #$a0 295 | @04a1 c0 00 // test_program.s:384 cpy #$0 296 | @04a3 08 // test_program.s:385 php 297 | @04a4 ce da 61 // test_program.s:388 dec dec_abs_test 298 | @04a7 08 // test_program.s:389 php 299 | @04a8 de da 61 // test_program.s:390 dec dec_abs_test,x 300 | @04ab 08 // test_program.s:391 php 301 | @04ac c6 74 // test_program.s:392 dec dec_zp_test 302 | @04ae 08 // test_program.s:393 php 303 | @04af d6 74 // test_program.s:394 dec dec_zp_test,x 304 | @04b1 08 // test_program.s:395 php 305 | @04b2 3a // test_program.s:398 dec 306 | @04b3 08 // test_program.s:399 php 307 | @04b4 d0 fc // test_program.s:400 bne dec_loop 308 | @04b6 3a // test_program.s:401 dec 309 | @04b7 08 // test_program.s:402 php 310 | @04b8 20 ef 41 // test_program.s:404 jsr bb_test 311 | @04bb a5 99 // test_program.s:405 lda branch_bit_test 312 | @04bd 49 ff // test_program.s:406 eor #$ff 313 | @04bf 85 99 // test_program.s:407 sta branch_bit_test 314 | @04c1 20 ef 41 // test_program.s:408 jsr bb_test 315 | @04c4 08 // test_program.s:411 php 316 | @04c5 4d 74 d0 // test_program.s:412 eor eor_abs_test 317 | @04c8 48 // test_program.s:413 pha 318 | @04c9 08 // test_program.s:414 php 319 | @04ca 5d 74 d0 // test_program.s:415 eor eor_abs_test,x 320 | @04cd 48 // test_program.s:416 pha 321 | @04ce 08 // test_program.s:417 php 322 | @04cf 59 74 d0 // test_program.s:418 eor eor_abs_test,y 323 | @04d2 48 // test_program.s:419 pha 324 | @04d3 08 // test_program.s:420 php 325 | @04d4 49 f4 // test_program.s:421 eor #$f4 326 | @04d6 48 // test_program.s:422 pha 327 | @04d7 08 // test_program.s:423 php 328 | @04d8 45 5f // test_program.s:424 eor eor_zp_test 329 | @04da 48 // test_program.s:425 pha 330 | @04db 08 // test_program.s:426 php 331 | @04dc 41 5f // test_program.s:427 eor (eor_zp_test,x) 332 | @04de 48 // test_program.s:428 pha 333 | @04df 08 // test_program.s:429 php 334 | @04e0 55 5f // test_program.s:430 eor eor_zp_test,x 335 | @04e2 48 // test_program.s:431 pha 336 | @04e3 08 // test_program.s:432 php 337 | @04e4 52 5f // test_program.s:433 eor (eor_zp_test) 338 | @04e6 48 // test_program.s:434 pha 339 | @04e7 08 // test_program.s:435 php 340 | @04e8 51 5f // test_program.s:436 eor (eor_zp_test),y 341 | @04ea 48 // test_program.s:437 pha 342 | @04eb 08 // test_program.s:438 php 343 | @04ec 3a // test_program.s:442 dec 344 | @04ed 3a // test_program.s:443 dec 345 | @04ee a2 03 // test_program.s:444 ldx #$3 346 | @04f0 ee ff 61 // test_program.s:447 inc inc_abs_test 347 | @04f3 08 // test_program.s:448 php 348 | @04f4 fe ff 61 // test_program.s:449 inc inc_abs_test,x 349 | @04f7 08 // test_program.s:450 php 350 | @04f8 1a // test_program.s:451 inc 351 | @04f9 08 // test_program.s:452 php 352 | @04fa e6 ef // test_program.s:453 inc inc_zp_test 353 | @04fc 08 // test_program.s:454 php 354 | @04fd f6 ef // test_program.s:455 inc inc_zp_test,x 355 | @04ff 08 // test_program.s:456 php 356 | @0500 ca // test_program.s:458 dex 357 | @0501 d0 ed // test_program.s:459 bne inc_loop 358 | @0503 4c aa 55 // test_program.s:461 jmp jmp_tests 359 | @0506 00 // test_program.s:462 brk ; Unreachable 360 | @0507 08 // test_program.s:464 php 361 | @0508 ae 10 1a // test_program.s:468 ldx ldx_abs_test 362 | @050b 08 // test_program.s:469 php 363 | @050c 8e 00 ff // test_program.s:470 stx value_dump 364 | @050f be 10 1a // test_program.s:471 ldx ldx_abs_test,y 365 | @0512 08 // test_program.s:472 php 366 | @0513 8e 00 ff // test_program.s:473 stx value_dump 367 | @0516 be ee 19 // test_program.s:474 ldx ldx_abs_test-$22,y 368 | @0519 08 // test_program.s:475 php 369 | @051a 8e 00 ff // test_program.s:476 stx value_dump 370 | @051d a2 04 // test_program.s:477 ldx #$04 371 | @051f 08 // test_program.s:478 php 372 | @0520 8e 00 ff // test_program.s:479 stx value_dump 373 | @0523 a6 78 // test_program.s:480 ldx ldx_zp_test 374 | @0525 08 // test_program.s:481 php 375 | @0526 8e 00 ff // test_program.s:482 stx value_dump 376 | @0529 b6 78 // test_program.s:483 ldx ldx_zp_test,y 377 | @052b 08 // test_program.s:484 php 378 | @052c 8e 00 ff // test_program.s:485 stx value_dump 379 | @052f ac 08 e3 // test_program.s:489 ldy ldy_abs_test 380 | @0532 08 // test_program.s:490 php 381 | @0533 8c 00 ff // test_program.s:491 sty value_dump 382 | @0536 bc 08 e3 // test_program.s:492 ldy ldy_abs_test,x 383 | @0539 08 // test_program.s:493 php 384 | @053a 8c 00 ff // test_program.s:494 sty value_dump 385 | @053d a0 6c // test_program.s:495 ldy #$6c 386 | @053f 08 // test_program.s:496 php 387 | @0540 8c 00 ff // test_program.s:497 sty value_dump 388 | @0543 a4 3f // test_program.s:498 ldy ldy_zp_test 389 | @0545 08 // test_program.s:499 php 390 | @0546 8c 00 ff // test_program.s:500 sty value_dump 391 | @0549 b4 3f // test_program.s:501 ldy ldy_zp_test,x 392 | @054b 08 // test_program.s:502 php 393 | @054c 8c 00 ff // test_program.s:503 sty value_dump 394 | @054f 4e a8 7e // test_program.s:507 lsr lsr_abs_test 395 | @0552 08 // test_program.s:508 php 396 | @0553 5e a8 7e // test_program.s:509 lsr lsr_abs_test,x 397 | @0556 08 // test_program.s:510 php 398 | @0557 4a // test_program.s:511 lsr 399 | @0558 08 // test_program.s:512 php 400 | @0559 8d 00 ff // test_program.s:513 sta value_dump 401 | @055c 46 9d // test_program.s:514 lsr lsr_zp_test 402 | @055e 08 // test_program.s:515 php 403 | @055f 56 9d // test_program.s:516 lsr lsr_zp_test,x 404 | @0561 08 // test_program.s:517 php 405 | @0562 a9 fc // test_program.s:521 lda #$fc 406 | @0564 8d a3 01 // test_program.s:522 sta $1a3 ; A 407 | @0567 9c a4 01 // test_program.s:523 stz $1a4 ; Y 408 | @056a a9 55 // test_program.s:524 lda #$55 409 | @056c 8d a5 01 // test_program.s:525 sta $1a5 ; A 410 | @056f a9 dd // test_program.s:526 lda #$dd 411 | @0571 8d a6 01 // test_program.s:527 sta $1a6 ; Y 412 | @0574 9c a7 01 // test_program.s:528 stz $1a7 ; A 413 | @0577 a9 03 // test_program.s:529 lda #$03 414 | @0579 8d a8 01 // test_program.s:530 sta $1a8 ; Y 415 | @057c a9 9b // test_program.s:531 lda #$9b 416 | @057e 8d a9 01 // test_program.s:532 sta $1a9 ; X 417 | @0581 a9 2d // test_program.s:533 lda #$2d 418 | @0583 8d aa 01 // test_program.s:534 sta $1aa ; X 419 | @0586 9c ab 01 // test_program.s:535 stz $1ab ; X 420 | @0589 a2 03 // test_program.s:537 ldx #$03 421 | @058b 68 // test_program.s:539 pla 422 | @058c 8d 00 ff // test_program.s:540 sta value_dump 423 | @058f 08 // test_program.s:541 php 424 | @0590 28 // test_program.s:542 plp 425 | @0591 7a // test_program.s:543 ply 426 | @0592 8c 00 ff // test_program.s:544 sty value_dump 427 | @0595 08 // test_program.s:545 php 428 | @0596 28 // test_program.s:546 plp 429 | @0597 ca // test_program.s:548 dex 430 | @0598 d0 f1 // test_program.s:549 bne pull_test_loop1 431 | @059a fa // test_program.s:552 plx 432 | @059b 8e 00 ff // test_program.s:553 stx value_dump 433 | @059e 08 // test_program.s:554 php 434 | @059f 28 // test_program.s:555 plp 435 | @05a0 88 // test_program.s:557 dey 436 | @05a1 d0 f7 // test_program.s:558 bne pull_test_loop2 437 | @05a3 07 2e // test_program.s:562 rmb 0,rmb_zp_test 438 | @05a5 07 2f // test_program.s:563 rmb 0,rmb_zp_test+1 439 | @05a7 17 2e // test_program.s:564 rmb 1,rmb_zp_test 440 | @05a9 17 2f // test_program.s:565 rmb 1,rmb_zp_test+1 441 | @05ab 27 2e // test_program.s:566 rmb 2,rmb_zp_test 442 | @05ad 27 2f // test_program.s:567 rmb 2,rmb_zp_test+1 443 | @05af 37 2e // test_program.s:568 rmb 3,rmb_zp_test 444 | @05b1 37 2f // test_program.s:569 rmb 3,rmb_zp_test+1 445 | @05b3 47 2e // test_program.s:570 rmb 4,rmb_zp_test 446 | @05b5 47 2f // test_program.s:571 rmb 4,rmb_zp_test+1 447 | @05b7 57 2e // test_program.s:572 rmb 5,rmb_zp_test 448 | @05b9 57 2f // test_program.s:573 rmb 5,rmb_zp_test+1 449 | @05bb 67 2e // test_program.s:574 rmb 6,rmb_zp_test 450 | @05bd 67 2f // test_program.s:575 rmb 6,rmb_zp_test+1 451 | @05bf 77 2e // test_program.s:576 rmb 7,rmb_zp_test 452 | @05c1 77 2f // test_program.s:577 rmb 7,rmb_zp_test+1 453 | @05c3 87 30 // test_program.s:579 smb 0,smb_zp_test 454 | @05c5 87 31 // test_program.s:580 smb 0,smb_zp_test+1 455 | @05c7 97 30 // test_program.s:581 smb 1,smb_zp_test 456 | @05c9 97 31 // test_program.s:582 smb 1,smb_zp_test+1 457 | @05cb a7 30 // test_program.s:583 smb 2,smb_zp_test 458 | @05cd a7 31 // test_program.s:584 smb 2,smb_zp_test+1 459 | @05cf b7 30 // test_program.s:585 smb 3,smb_zp_test 460 | @05d1 b7 31 // test_program.s:586 smb 3,smb_zp_test+1 461 | @05d3 c7 30 // test_program.s:587 smb 4,smb_zp_test 462 | @05d5 c7 31 // test_program.s:588 smb 4,smb_zp_test+1 463 | @05d7 d7 30 // test_program.s:589 smb 5,smb_zp_test 464 | @05d9 d7 31 // test_program.s:590 smb 5,smb_zp_test+1 465 | @05db e7 30 // test_program.s:591 smb 6,smb_zp_test 466 | @05dd e7 31 // test_program.s:592 smb 6,smb_zp_test+1 467 | @05df f7 30 // test_program.s:593 smb 7,smb_zp_test 468 | @05e1 f7 31 // test_program.s:594 smb 7,smb_zp_test+1 469 | @05e3 a2 01 // test_program.s:598 ldx #1 470 | @05e5 a9 af // test_program.s:599 lda #$af 471 | @05e7 2e f8 f9 // test_program.s:600 rol rol_abs_test 472 | @05ea 08 // test_program.s:601 php 473 | @05eb 2a // test_program.s:602 rol 474 | @05ec 08 // test_program.s:603 php 475 | @05ed 8d 00 ff // test_program.s:604 sta value_dump 476 | @05f0 6e f9 f9 // test_program.s:605 ror rol_abs_test+1 477 | @05f3 08 // test_program.s:606 php 478 | @05f4 3e f8 f9 // test_program.s:607 rol rol_abs_test,x 479 | @05f7 08 // test_program.s:608 php 480 | @05f8 7e f9 f9 // test_program.s:609 ror rol_abs_test+1,x 481 | @05fb 08 // test_program.s:610 php 482 | @05fc 6a // test_program.s:611 ror 483 | @05fd 08 // test_program.s:612 php 484 | @05fe 8d 00 ff // test_program.s:613 sta value_dump 485 | @0601 26 4e // test_program.s:614 rol rol_zp_test 486 | @0603 08 // test_program.s:615 php 487 | @0604 66 4f // test_program.s:616 ror rol_zp_test+1 488 | @0606 08 // test_program.s:617 php 489 | @0607 36 4e // test_program.s:618 rol rol_zp_test,x 490 | @0609 08 // test_program.s:619 php 491 | @060a 76 4f // test_program.s:620 ror rol_zp_test+1,x 492 | @060c 08 // test_program.s:621 php 493 | @060d a9 01 // test_program.s:623 lda #1 494 | @060f 18 // test_program.s:624 clc 495 | @0610 6a // test_program.s:625 ror 496 | @0611 08 // test_program.s:626 php 497 | @0612 8d 00 ff // test_program.s:627 sta value_dump 498 | @0615 2a // test_program.s:628 rol 499 | @0616 08 // test_program.s:629 php 500 | @0617 8d 00 ff // test_program.s:630 sta value_dump 501 | @061a 38 // test_program.s:631 sec 502 | @061b 6a // test_program.s:632 ror 503 | @061c 08 // test_program.s:633 php 504 | @061d 8d 00 ff // test_program.s:634 sta value_dump 505 | @0620 18 // test_program.s:635 clc 506 | @0621 2a // test_program.s:636 rol 507 | @0622 08 // test_program.s:637 php 508 | @0623 8d 00 ff // test_program.s:638 sta value_dump 509 | @0626 a0 02 // test_program.s:642 ldy #$02 510 | @0628 8d 94 46 // test_program.s:643 sta sta_abs_test 511 | @062b 1a // test_program.s:644 inc 512 | @062c 9d 94 46 // test_program.s:645 sta sta_abs_test,x 513 | @062f 1a // test_program.s:646 inc 514 | @0630 99 94 46 // test_program.s:647 sta sta_abs_test,y 515 | @0633 1a // test_program.s:648 inc 516 | @0634 85 2a // test_program.s:649 sta sta_zp_test 517 | @0636 1a // test_program.s:650 inc 518 | @0637 95 2a // test_program.s:651 sta sta_zp_test,x 519 | @0639 1a // test_program.s:652 inc 520 | @063a 81 2a // test_program.s:653 sta (sta_zp_test,x) 521 | @063c 1a // test_program.s:654 inc 522 | @063d 92 2a // test_program.s:655 sta (sta_zp_test) 523 | @063f 1a // test_program.s:656 inc 524 | @0640 91 2a // test_program.s:657 sta (sta_zp_test),y 525 | @0642 1a // test_program.s:658 inc 526 | @0643 a2 80 // test_program.s:659 ldx #$80 527 | @0645 9d 94 46 // test_program.s:660 sta sta_abs_test,x 528 | @0648 1a // test_program.s:661 inc 529 | @0649 a0 ff // test_program.s:662 ldy #$ff 530 | @064b 99 94 46 // test_program.s:663 sta sta_abs_test,y 531 | @064e 1a // test_program.s:664 inc 532 | @064f 91 2a // test_program.s:665 sta (sta_zp_test),y 533 | @0651 08 // test_program.s:666 php 534 | @0652 8e 94 46 // test_program.s:670 stx sta_abs_test 535 | @0655 e8 // test_program.s:671 inx 536 | @0656 86 2b // test_program.s:672 stx sta_zp_test+1 537 | @0658 e8 // test_program.s:673 inx 538 | @0659 96 2b // test_program.s:674 stx sta_zp_test+1,y 539 | @065b 08 // test_program.s:675 php 540 | @065c a2 02 // test_program.s:679 ldx #$2 541 | @065e 8c 94 46 // test_program.s:680 sty sta_abs_test 542 | @0661 c8 // test_program.s:681 iny 543 | @0662 84 2a // test_program.s:682 sty sta_zp_test 544 | @0664 c8 // test_program.s:683 iny 545 | @0665 94 2a // test_program.s:684 sty sta_zp_test,x 546 | @0667 08 // test_program.s:685 php 547 | @0668 9c 94 46 // test_program.s:689 stz sta_abs_test 548 | @066b 9e 94 46 // test_program.s:690 stz sta_abs_test,x 549 | @066e 64 2a // test_program.s:691 stz sta_zp_test 550 | @0670 74 2a // test_program.s:692 stz sta_zp_test,x 551 | @0672 08 // test_program.s:693 php 552 | @0673 a9 85 // test_program.s:697 lda #$85 553 | @0675 20 ab 07 // test_program.s:698 jsr transfer_tests 554 | @0678 a9 00 // test_program.s:699 lda #$00 555 | @067a 20 ab 07 // test_program.s:700 jsr transfer_tests 556 | @067d ba // test_program.s:702 tsx 557 | @067e 20 c9 07 // test_program.s:703 jsr dump_state 558 | @0681 a2 ff // test_program.s:704 ldx #$ff 559 | @0683 a9 00 // test_program.s:705 lda #$00 560 | @0685 9a // test_program.s:706 txs 561 | @0686 20 c9 07 // test_program.s:707 jsr dump_state 562 | @0689 a9 89 // test_program.s:711 lda #$89 563 | @068b 1c 15 7d // test_program.s:712 trb trb_abs_test 564 | @068e 20 c9 07 // test_program.s:713 jsr dump_state 565 | @0691 1c 16 7d // test_program.s:714 trb trb_abs_test+1 566 | @0694 20 c9 07 // test_program.s:715 jsr dump_state 567 | @0697 0c 17 7d // test_program.s:717 tsb tsb_abs_test 568 | @069a 20 c9 07 // test_program.s:718 jsr dump_state 569 | @069d 14 66 // test_program.s:720 trb trb_zp_test 570 | @069f 20 c9 07 // test_program.s:721 jsr dump_state 571 | @06a2 14 67 // test_program.s:722 trb trb_zp_test+1 572 | @06a4 20 c9 07 // test_program.s:723 jsr dump_state 573 | @06a7 04 68 // test_program.s:725 tsb tsb_zp_test 574 | @06a9 20 c9 07 // test_program.s:726 jsr dump_state 575 | @06ac a9 00 // test_program.s:728 lda #$00 576 | @06ae 0c 16 7d // test_program.s:729 tsb trb_abs_test+1 577 | @06b1 20 c9 07 // test_program.s:730 jsr dump_state 578 | @06b4 04 69 // test_program.s:731 tsb tsb_zp_test+1 579 | @06b6 20 c9 07 // test_program.s:732 jsr dump_state 580 | @06b9 20 00 f8 // test_program.s:735 jsr regression1_apple2_disassembly 581 | @06bc a9 06 // test_program.s:739 lda #$6 582 | @06be 8d fe 02 // test_program.s:740 sta IRQ_TRIGGER_COUNT 583 | @06c1 8d ff 02 // test_program.s:741 sta IRQ_TRIGGER_DELAY 584 | @06c4 ea // test_program.s:742 nop 585 | @06c5 ea // test_program.s:743 nop 586 | @06c6 ea // test_program.s:744 nop 587 | @06c7 ea // test_program.s:745 nop 588 | @06c8 ea // test_program.s:746 nop 589 | @06c9 ea // test_program.s:747 nop 590 | @06ca ea // test_program.s:748 nop 591 | @06cb ea // test_program.s:749 nop 592 | @06cc ea // test_program.s:750 nop 593 | @06cd ea // test_program.s:751 nop 594 | @06ce a9 1e // test_program.s:753 lda #30 595 | @06d0 8d fe 02 // test_program.s:754 sta IRQ_TRIGGER_COUNT 596 | @06d3 a2 04 // test_program.s:755 ldx #4 597 | @06d5 8e ff 02 // test_program.s:756 stx IRQ_TRIGGER_DELAY 598 | @06d8 ea // test_program.s:757 nop 599 | @06d9 ea // test_program.s:758 nop 600 | @06da ea // test_program.s:759 nop 601 | @06db ea // test_program.s:760 nop 602 | @06dc 58 // test_program.s:761 cli 603 | @06dd ea // test_program.s:762 nop 604 | @06de ea // test_program.s:763 nop 605 | @06df ea // test_program.s:764 nop 606 | @06e0 ea // test_program.s:765 nop 607 | @06e1 ea // test_program.s:766 nop 608 | @06e2 ea // test_program.s:767 nop 609 | @06e3 a9 28 // test_program.s:771 lda #40 610 | @06e5 8d fa 02 // test_program.s:772 sta NMI_TRIGGER_COUNT 611 | @06e8 8d fe 02 // test_program.s:773 sta IRQ_TRIGGER_COUNT 612 | @06eb a2 0f // test_program.s:774 ldx #15 613 | @06ed a0 0b // test_program.s:775 ldy #11 614 | @06ef 8e ff 02 // test_program.s:776 stx IRQ_TRIGGER_DELAY 615 | @06f2 8c fb 02 // test_program.s:777 sty NMI_TRIGGER_DELAY 616 | @06f5 ea // test_program.s:779 nop 617 | @06f6 ea // test_program.s:780 nop 618 | @06f7 ea // test_program.s:781 nop 619 | @06f8 ea // test_program.s:782 nop 620 | @06f9 ea // test_program.s:783 nop 621 | @06fa ea // test_program.s:784 nop 622 | @06fb ea // test_program.s:785 nop 623 | @06fc ea // test_program.s:786 nop 624 | @06fd ea // test_program.s:787 nop 625 | @06fe ea // test_program.s:788 nop 626 | @06ff ea // test_program.s:789 nop 627 | @0700 ea // test_program.s:790 nop 628 | @0701 ea // test_program.s:791 nop 629 | @0702 ea // test_program.s:792 nop 630 | @0703 ea // test_program.s:793 nop 631 | @0704 ea // test_program.s:794 nop 632 | @0705 b8 // test_program.s:798 clv 633 | @0706 a9 0a // test_program.s:800 lda #10 634 | @0708 8d 80 02 // test_program.s:801 sta READY_TRIGGER_COUNT 635 | @070b a9 02 // test_program.s:802 lda #2 636 | @070d 8d 82 02 // test_program.s:803 sta SO_TRIGGER_COUNT 637 | @0710 a2 09 // test_program.s:804 ldx #9 638 | @0712 a0 1e // test_program.s:805 ldy #30 639 | @0714 8e 81 02 // test_program.s:806 stx READY_TRIGGER_DELAY 640 | @0717 8c 83 02 // test_program.s:807 sty SO_TRIGGER_DELAY 641 | @071a 50 fe // test_program.s:810 bvc so_test_loop 642 | @071c a9 31 // test_program.s:814 lda #(stp_test_cont1 % 256) 643 | @071e 8d fc ff // test_program.s:815 sta reset_vector 644 | @0721 a9 07 // test_program.s:816 lda #(stp_test_cont1 / 256) 645 | @0723 8d fd ff // test_program.s:817 sta reset_vector+1 646 | @0726 a9 04 // test_program.s:818 lda #$04 647 | @0728 8d fc 02 // test_program.s:819 sta RESET_TRIGGER_COUNT 648 | @072b a9 10 // test_program.s:820 lda #$10 649 | @072d 8d fd 02 // test_program.s:821 sta RESET_TRIGGER_DELAY 650 | @0730 db // test_program.s:823 stp 651 | @0731 20 c9 07 // test_program.s:826 jsr dump_state 652 | @0734 a9 55 // test_program.s:828 lda #(stp_test_cont2 % 256) 653 | @0736 8d fc ff // test_program.s:829 sta reset_vector 654 | @0739 a9 07 // test_program.s:830 lda #(stp_test_cont2 / 256) 655 | @073b 8d fd ff // test_program.s:831 sta reset_vector+1 656 | @073e a9 ff // test_program.s:833 lda #$ff 657 | @0740 48 // test_program.s:834 pha 658 | @0741 28 // test_program.s:835 plp 659 | @0742 20 c9 07 // test_program.s:836 jsr dump_state 660 | @0745 a9 04 // test_program.s:838 lda #$04 661 | @0747 8d fc 02 // test_program.s:839 sta RESET_TRIGGER_COUNT 662 | @074a 8d fd 02 // test_program.s:840 sta RESET_TRIGGER_DELAY 663 | @074d ea // test_program.s:842 nop 664 | @074e ea // test_program.s:843 nop 665 | @074f ea // test_program.s:844 nop 666 | @0750 ea // test_program.s:845 nop 667 | @0751 ea // test_program.s:846 nop 668 | @0752 ea // test_program.s:847 nop 669 | @0753 ea // test_program.s:848 nop 670 | @0754 ea // test_program.s:849 nop 671 | @0755 a9 00 // test_program.s:853 lda #$00 672 | @0757 b8 // test_program.s:854 clv 673 | @0758 18 // test_program.s:855 clc 674 | @0759 20 c9 07 // test_program.s:856 jsr dump_state 675 | @075c a9 7d // test_program.s:858 lda #(stp_test_cont3 % 256) 676 | @075e 8d fc ff // test_program.s:859 sta reset_vector 677 | @0761 a9 07 // test_program.s:860 lda #(stp_test_cont3 / 256) 678 | @0763 8d fd ff // test_program.s:861 sta reset_vector+1 679 | @0766 a9 00 // test_program.s:863 lda #$00 680 | @0768 48 // test_program.s:864 pha 681 | @0769 28 // test_program.s:865 plp 682 | @076a 20 c9 07 // test_program.s:866 jsr dump_state 683 | @076d a9 04 // test_program.s:868 lda #$04 684 | @076f 8d fc 02 // test_program.s:869 sta RESET_TRIGGER_COUNT 685 | @0772 8d fd 02 // test_program.s:870 sta RESET_TRIGGER_DELAY 686 | @0775 ea // test_program.s:872 nop 687 | @0776 ea // test_program.s:873 nop 688 | @0777 ea // test_program.s:874 nop 689 | @0778 ea // test_program.s:875 nop 690 | @0779 ea // test_program.s:876 nop 691 | @077a ea // test_program.s:877 nop 692 | @077b ea // test_program.s:878 nop 693 | @077c ea // test_program.s:879 nop 694 | @077d a9 00 // test_program.s:883 lda #$00 695 | @077f b8 // test_program.s:884 clv 696 | @0780 18 // test_program.s:885 clc 697 | @0781 20 c9 07 // test_program.s:886 jsr dump_state 698 | @0784 58 // test_program.s:890 cli 699 | @0785 a9 06 // test_program.s:891 lda #6 700 | @0787 8d fe 02 // test_program.s:892 sta IRQ_TRIGGER_COUNT 701 | @078a a9 0a // test_program.s:893 lda #10 702 | @078c 8d ff 02 // test_program.s:894 sta IRQ_TRIGGER_DELAY 703 | @078f cb // test_program.s:895 wai 704 | @0790 78 // test_program.s:897 sei 705 | @0791 a9 06 // test_program.s:898 lda #6 706 | @0793 8d fe 02 // test_program.s:899 sta IRQ_TRIGGER_COUNT 707 | @0796 a9 0a // test_program.s:900 lda #10 708 | @0798 8d ff 02 // test_program.s:901 sta IRQ_TRIGGER_DELAY 709 | @079b cb // test_program.s:902 wai 710 | @079c a9 06 // test_program.s:904 lda #6 711 | @079e 8d fa 02 // test_program.s:905 sta NMI_TRIGGER_COUNT 712 | @07a1 a9 0a // test_program.s:906 lda #10 713 | @07a3 8d fb 02 // test_program.s:907 sta NMI_TRIGGER_DELAY 714 | @07a6 cb // test_program.s:908 wai 715 | @07a7 8d 00 02 // test_program.s:911 sta FINISHED_TRIGGER 716 | @07aa 00 // test_program.s:912 .byte 00 717 | @07ab 20 c9 07 // test_program.s:915 jsr dump_state 718 | @07ae a0 01 // test_program.s:916 ldy #$01 719 | @07b0 a8 // test_program.s:917 tay 720 | @07b1 20 c9 07 // test_program.s:918 jsr dump_state 721 | @07b4 a2 02 // test_program.s:919 ldx #$02 722 | @07b6 aa // test_program.s:920 tax 723 | @07b7 20 c9 07 // test_program.s:921 jsr dump_state 724 | @07ba 49 ff // test_program.s:922 eor #$ff 725 | @07bc a0 01 // test_program.s:923 ldy #$01 726 | @07be 98 // test_program.s:924 tya 727 | @07bf 20 c9 07 // test_program.s:925 jsr dump_state 728 | @07c2 a2 01 // test_program.s:926 ldx #$01 729 | @07c4 8a // test_program.s:927 txa 730 | @07c5 20 c9 07 // test_program.s:928 jsr dump_state 731 | @07c8 60 // test_program.s:929 rts 732 | @07c9 08 // test_program.s:933 php 733 | @07ca 8d 00 ff // test_program.s:934 sta value_dump 734 | @07cd 8e 00 ff // test_program.s:935 stx value_dump 735 | @07d0 8c 00 ff // test_program.s:936 sty value_dump 736 | @07d3 28 // test_program.s:937 plp 737 | @07d4 60 // test_program.s:938 rts 738 | @07d5 a2 ff // test_program.s:941 ldx #$ff 739 | @07d7 9a // test_program.s:942 txs 740 | @07d8 a9 03 // test_program.s:943 lda #start/256 741 | @07da 48 // test_program.s:944 pha 742 | @07db a9 00 // test_program.s:945 lda #start%256 743 | @07dd 48 // test_program.s:946 pha 744 | @07de a9 44 // test_program.s:947 lda #INTMASK+OVERFLOW 745 | @07e0 48 // test_program.s:948 pha 746 | @07e1 40 // test_program.s:949 rti 747 | @07e2 00 // test_program.s:950 brk ; Unreachable 748 | @0a4f 8f // test_program.s:954 .byte $8f ; cmp (zp) test 749 | @0a71 25 // test_program.s:957 .byte $25 ; cmp (zp),y test 750 | @13d5 dd // test_program.s:960 .byte $dd ; adc (zp,x) test 751 | @1690 6b // test_program.s:964 .byte $6b 752 | @16aa 03 // test_program.s:967 .byte $03 ; bit abs,x 753 | @1a10 6d // test_program.s:971 .byte $6d 754 | @1a32 d7 // test_program.s:974 .byte $d7 ; ldx abs,y 755 | @26ff 03 a3 // test_program.s:978 .word jmp_dest2 756 | @2701 00 // test_program.s:979 .byte 0 757 | @2702 11 a3 // test_program.s:980 .word jmp_dest4 758 | @2746 07 05 // test_program.s:983 .word jmp_test_continues 759 | @274f 0b a3 // test_program.s:986 .word jmp_dest5 760 | @27b8 13 a3 // test_program.s:990 .word jmp_dest1 761 | @27ba 00 // test_program.s:991 .byte 0 762 | @27bb 07 a3 // test_program.s:992 .word jmp_dest3 763 | @27ff 07 a3 // test_program.s:995 .word jmp_dest3 764 | @2808 07 a3 // test_program.s:998 .word jmp_dest3 765 | @3787 b8 // test_program.s:1002 .byte $b8 766 | @37a1 6f // test_program.s:1005 .byte $6f 767 | @37a9 0e // test_program.s:1008 .byte $0e 768 | @40ef 08 // test_program.s:1013 php 769 | @40f0 b0 0c // test_program.s:1014 bcs .1 770 | @40f2 90 0a // test_program.s:1015 bcc .1 771 | @40f4 70 04 // test_program.s:1017 .2 bvs .3 772 | @40f6 50 02 // test_program.s:1018 bvc .3 773 | @40f8 80 08 // test_program.s:1020 .4 bra .5 774 | @40fa d0 fc // test_program.s:1022 .3 bne .4 775 | @40fc f0 fa // test_program.s:1023 beq .4 776 | @40fe 30 f4 // test_program.s:1025 .1 bmi .2 777 | @4100 10 f2 // test_program.s:1026 bpl .2 778 | @4102 28 // test_program.s:1029 plp 779 | @4103 60 // test_program.s:1030 rts 780 | @4104 00 // test_program.s:1031 .byte 00 781 | @41ef 0f 99 28 // test_program.s:1036 bbr 0, branch_bit_test, .1 782 | @41f2 8f 99 25 // test_program.s:1037 bbs 0, branch_bit_test, .1 783 | @41f5 2f 99 1c // test_program.s:1039 .2 bbr 2, branch_bit_test, .3 784 | @41f8 af 99 19 // test_program.s:1040 bbs 2, branch_bit_test, .3 785 | @41fb 4f 99 10 // test_program.s:1042 .4 bbr 4, branch_bit_test, .5 786 | @41fe cf 99 0d // test_program.s:1043 bbs 4, branch_bit_test, .5 787 | @4201 6f 99 04 // test_program.s:1045 .6 bbr 6, branch_bit_test, .7 788 | @4204 ef 99 01 // test_program.s:1046 bbs 6, branch_bit_test, .7 789 | @4207 60 // test_program.s:1048 .8 rts 790 | @4208 7f 99 fc // test_program.s:1050 .7 bbr 7, branch_bit_test, .8 791 | @420b ff 99 f9 // test_program.s:1051 bbs 7, branch_bit_test, .8 792 | @420e 5f 99 f0 // test_program.s:1053 .5 bbr 5, branch_bit_test, .6 793 | @4211 df 99 ed // test_program.s:1054 bbs 5, branch_bit_test, .6 794 | @4214 3f 99 e4 // test_program.s:1056 .3 bbr 3, branch_bit_test, .4 795 | @4217 bf 99 e1 // test_program.s:1057 bbs 3, branch_bit_test, .4 796 | @421a 1f 99 d8 // test_program.s:1059 .1 bbr 1, branch_bit_test, .2 797 | @421d 9f 99 d5 // test_program.s:1060 bbs 1, branch_bit_test, .2 798 | @4220 00 // test_program.s:1062 brk ; Unreachable 799 | @4221 08 // test_program.s:1065 php 800 | @4222 28 // test_program.s:1066 plp 801 | @4223 40 // test_program.s:1067 rti 802 | @4224 00 // test_program.s:1068 brk ; Unreachable 803 | @4225 4c 21 42 // test_program.s:1071 jmp int_handler 804 | @4228 00 // test_program.s:1072 brk ; Unreachable 805 | @4694 87 // test_program.s:1075 sta_abs_test: .byte $87, $91, $20 806 | @4695 91 807 | @4696 20 808 | @55aa a2 03 // test_program.s:1079 ldx #$3 809 | @55ac 6c b8 27 // test_program.s:1081 jmp (jmp_ind_test1) 810 | @55af 00 // test_program.s:1082 brk ; Unreachable 811 | @5ee6 3f // test_program.s:1085 .byte $3f ; eor (zp,x) test 812 | @61da 7b // test_program.s:1088 dec_abs_test .byte $7b 813 | @61ff fe // test_program.s:1091 inc_abs_test .byte $fe, $30, $22, $48 ; inc abs, int abs,x tests 814 | @6200 30 815 | @6201 22 816 | @6202 48 817 | @627a 01 // test_program.s:1094 .byte $01 ; dec abs,x test 818 | @6d21 74 // test_program.s:1097 lda_abs_test .byte $74 819 | @6d51 c7 // test_program.s:1099 .byte $c7 ; lda abs,y 820 | @6de1 08 // test_program.s:1101 .byte $08 ; lda abs,x 821 | @7088 29 // test_program.s:1104 .byte $29 ; eor (zp) 822 | @70aa 50 // test_program.s:1106 .byte $50 ; eor (zp),y 823 | @7ace 65 // test_program.s:1109 adc_abs_test: .byte $65, $ca, $26, $6b 824 | @7acf ca 825 | @7ad0 26 826 | @7ad1 6b 827 | @7d15 d7 // test_program.s:1112 trb_abs_test: .byte $d7, $36 828 | @7d16 36 829 | @7d17 a5 // test_program.s:1113 tsb_abs_test: .byte $a5, $00 830 | @7d18 00 831 | @7ea8 9b // test_program.s:1117 .byte $9b 832 | @7f9d 49 // test_program.s:1120 .byte $49 ; lsr abs,x 833 | @8510 56 // test_program.s:1123 asl_abs_test: .byte $56 834 | @85d0 40 // test_program.s:1125 .byte $40 ; asl abs,x test 835 | @a303 7c b8 27 // test_program.s:1129 jmp (jmp_ind_test1,x) 836 | @a306 00 // test_program.s:1130 brk ; Unreachable 837 | @a307 7c ff 26 // test_program.s:1133 jmp (jmp_ind_test2,x) 838 | @a30a 00 // test_program.s:1134 brk 839 | @a30b a2 47 // test_program.s:1137 ldx #$47 840 | @a30d 4c 13 a3 // test_program.s:1138 jmp jmp_dest1 841 | @a310 00 // test_program.s:1139 brk ; Unreachable 842 | @a311 a2 50 // test_program.s:1142 ldx #$50 843 | @a313 6c ff 26 // test_program.s:1145 jmp (jmp_ind_test2) 844 | @a316 00 // test_program.s:1146 brk ; Unreachable 845 | @ae38 bf // test_program.s:1149 lda_indirect_test .byte $bf 846 | @ae68 20 // test_program.s:1151 .byte $20 ; lda (zp),y test 847 | @af28 22 // test_program.s:1153 .byte $22 ; lda (zp),y test 848 | @c213 25 // test_program.s:1156 .byte $25 ; adc (zp,x) test 849 | @d074 17 // test_program.s:1159 eor_abs_test .byte $17 850 | @d096 11 // test_program.s:1162 .byte $11 ; eor abs,y 851 | @d114 49 // test_program.s:1165 .byte $49 ; eor abs,x test 852 | @d2cc 38 // test_program.s:1168 .byte $38 ; cmp (zp,x) test 853 | @d588 15 // test_program.s:1171 .byte $15 ; adc (zp,x) test 854 | @d589 8e // test_program.s:1172 .byte $8e, $9b, $f5 ; adc (zp),y test 855 | @d58a 9b 856 | @d58b f5 857 | @e308 ff // test_program.s:1176 .byte $ff 858 | @e3fd 93 // test_program.s:1179 .byte $93 ; ldy abs,x 859 | @f800 a9 a9 // test_program.s:1184 lda #$a9 ; Should have registered as LDA immediate, registers as ??? 860 | @f802 20 82 f8 // test_program.s:1185 jsr .0 861 | @f805 a9 85 // test_program.s:1186 lda #$85 ; Should have registered as STA zp, registers as ??? 862 | @f807 20 82 f8 // test_program.s:1187 jsr .0 863 | @f80a a9 ad // test_program.s:1188 lda #$ad ; Should have registered as LDA abs, registers as LDA zp 864 | @f80c 20 82 f8 // test_program.s:1189 jsr .0 865 | @f80f 60 // test_program.s:1191 rts 866 | @f810 00 // test_program.s:1192 brk ; Unreachable 867 | @f882 a8 // test_program.s:1197 tay 868 | @f883 4a // test_program.s:1198 lsr 869 | @f884 90 09 // test_program.s:1199 bcc .1 870 | @f886 6a // test_program.s:1200 ror 871 | @f887 b0 10 // test_program.s:1201 bcs .2 872 | @f889 c9 a2 // test_program.s:1202 cmp #$A2 873 | @f88b f0 0c // test_program.s:1203 beq .2 874 | @f88d 29 87 // test_program.s:1204 and #$87 875 | @f88f 4a // test_program.s:1206 lsr 876 | @f890 aa // test_program.s:1207 tax 877 | @f891 bd b1 f8 // test_program.s:1208 lda FMT1,x 878 | @f894 20 a8 f8 // test_program.s:1209 jsr .8 879 | @f897 d0 04 // test_program.s:1210 bne .5 880 | @f899 a0 80 // test_program.s:1212 ldy #$80 881 | @f89b a9 00 // test_program.s:1213 lda #$00 882 | @f89d aa // test_program.s:1215 tax 883 | @f89e bd f5 f8 // test_program.s:1216 lda FMT2,x 884 | @f8a1 85 2e // test_program.s:1217 sta $2e ; F8.MASK 885 | @f8a3 29 03 // test_program.s:1218 and #$03 886 | @f8a5 85 2f // test_program.s:1219 sta $2f ; LENGTH 887 | @f8a7 60 // test_program.s:1221 rts 888 | @f8a8 90 04 // test_program.s:1223 .8 bcc .9 889 | @f8aa 4a // test_program.s:1224 lsr A 890 | @f8ab 4a // test_program.s:1225 lsr A 891 | @f8ac 4a // test_program.s:1226 lsr A 892 | @f8ad 4a // test_program.s:1227 lsr A 893 | @f8ae 29 0f // test_program.s:1228 .9 and #$0f 894 | @f8b0 60 // test_program.s:1229 rts 895 | @f8b1 04 // test_program.s:1231 FMT1 .byte $04,$20,$54,$30,$0d,$80,$04,$90,$03,$22,$54,$33,$0d,$80,$04,$90 896 | @f8b2 20 897 | @f8b3 54 898 | @f8b4 30 899 | @f8b5 0d 900 | @f8b6 80 901 | @f8b7 04 902 | @f8b8 90 903 | @f8b9 03 904 | @f8ba 22 905 | @f8bb 54 906 | @f8bc 33 907 | @f8bd 0d 908 | @f8be 80 909 | @f8bf 04 910 | @f8c0 90 911 | @f8c1 04 // test_program.s:1232 .byte $04,$20,$54,$33,$0d,$80,$04,$90,$04,$20,$54,$3b,$0d,$80,$04,$90 912 | @f8c2 20 913 | @f8c3 54 914 | @f8c4 33 915 | @f8c5 0d 916 | @f8c6 80 917 | @f8c7 04 918 | @f8c8 90 919 | @f8c9 04 920 | @f8ca 20 921 | @f8cb 54 922 | @f8cc 3b 923 | @f8cd 0d 924 | @f8ce 80 925 | @f8cf 04 926 | @f8d0 90 927 | @f8d1 00 // test_program.s:1233 .byte $00,$22,$44,$33,$0d,$c8,$44,$00,$11,$22,$44,$33,$0d,$c8,$44,$a9 928 | @f8d2 22 929 | @f8d3 44 930 | @f8d4 33 931 | @f8d5 0d 932 | @f8d6 c8 933 | @f8d7 44 934 | @f8d8 00 935 | @f8d9 11 936 | @f8da 22 937 | @f8db 44 938 | @f8dc 33 939 | @f8dd 0d 940 | @f8de c8 941 | @f8df 44 942 | @f8e0 a9 943 | @f8e1 01 // test_program.s:1234 .byte $01,$22,$44,$33,$0d,$80,$04,$90,$01,$22,$44,$33,$0d,$80,$04,$90 944 | @f8e2 22 945 | @f8e3 44 946 | @f8e4 33 947 | @f8e5 0d 948 | @f8e6 80 949 | @f8e7 04 950 | @f8e8 90 951 | @f8e9 01 952 | @f8ea 22 953 | @f8eb 44 954 | @f8ec 33 955 | @f8ed 0d 956 | @f8ee 80 957 | @f8ef 04 958 | @f8f0 90 959 | @f8f1 26 // test_program.s:1235 .byte $26,$31,$87,$9a 960 | @f8f2 31 961 | @f8f3 87 962 | @f8f4 9a 963 | @f8f5 00 // test_program.s:1236 FMT2 .data $00,$21,$81,$82,$00,$00,$59,$4d,$91,$92,$86,$4a,$85,$9d 964 | @f8f6 21 965 | @f8f7 81 966 | @f8f8 82 967 | @f8f9 00 968 | @f8fa 00 969 | @f8fb 59 970 | @f8fc 4d 971 | @f8fd 91 972 | @f8fe 92 973 | @f8ff 86 974 | @f900 4a 975 | @f901 85 976 | @f902 9d 977 | @f9f8 cd // test_program.s:1240 .byte $cd, $71, $e4 978 | @f9f9 71 979 | @f9fa e4 980 | @fffa 25 42 // test_program.s:1243 nmi_vector: .word nmi_handler 981 | @fffc d5 07 // test_program.s:1244 reset_vector: .word reset_handler 982 | @fffe 21 42 // test_program.s:1245 irq_vector: .word int_handler 983 | -------------------------------------------------------------------------------- /sar6502.srcs/sim_1/new/test_program.s: -------------------------------------------------------------------------------- 1 | CARRY = %00000001 2 | ZERO = %00000010 3 | INTMASK = %00000100 4 | DECIMAL = %00001000 5 | BRK = %00100000 6 | OVERFLOW = %01000000 7 | NEGATIVE = %10000000 8 | 9 | FINISHED_TRIGGER = $200 10 | READY_TRIGGER_COUNT = $280 11 | READY_TRIGGER_DELAY = $281 12 | SO_TRIGGER_COUNT = $282 13 | SO_TRIGGER_DELAY = $283 14 | NMI_TRIGGER_COUNT = $2fa 15 | NMI_TRIGGER_DELAY = $2fb 16 | RESET_TRIGGER_COUNT = $2fc 17 | RESET_TRIGGER_DELAY = $2fd 18 | IRQ_TRIGGER_COUNT = $2fe 19 | IRQ_TRIGGER_DELAY = $2ff 20 | 21 | value_dump = $ff00 22 | 23 | .org $0000 24 | .byte $5e ; eor zp,x and (zp,x) tests (MSB) 25 | 26 | .org $000a 27 | .byte $cc, $d2 ; cmp zp,x test 28 | 29 | .org $000e 30 | bit_zp_test: .byte $f3 31 | 32 | .org $0014 33 | .byte $01 ; dec zp,x test 34 | 35 | .org $0028 36 | .byte $7a ; bit zp,x test 37 | .byte $6e ; asl zp,x test 38 | 39 | sta_zp_test: .byte 0, 0, $34 40 | 41 | .org $002e 42 | rmb_zp_test: .byte $65, $65 ^ $ff 43 | smb_zp_test: .byte $f0, $f0 ^ $ff 44 | 45 | .org $0034 46 | .byte $a8 ; ldy zp,x 47 | .org $003f 48 | ldy_zp_test: .byte $2c 49 | 50 | .org $004e 51 | rol_zp_test: .byte $41, $9b, $60 52 | 53 | .org $005f 54 | eor_zp_test: 55 | .byte $88, $70 56 | 57 | .org $0066 58 | trb_zp_test: .byte $75, $42 59 | tsb_zp_test: .byte $a3 60 | 61 | .org $0069 62 | asl_zp_test: .byte $d3 63 | .org $0074 64 | dec_zp_test: .byte $f8 65 | 66 | .org $0078 67 | ldx_zp_test: .byte $4d 68 | 69 | .org $0092 70 | .byte $6e ; lsr zp,x 71 | 72 | .org $0099 73 | branch_bit_test: .byte $50 74 | 75 | .byte $f5 ; ldx zp,y 76 | 77 | .org $009d 78 | lsr_zp_test: .byte $7e 79 | 80 | .org $00a9 81 | lda_zp_test: .word lda_indirect_test 82 | .org $ec 83 | adc_zp_test: 84 | .byte $88, $d5, $13 85 | inc_zp_test: 86 | .byte $c2 87 | 88 | cmp_zp_test: 89 | .byte $4f, $0a, $8f 90 | 91 | .org $00ff 92 | .byte $e6 ; eor zp,x and (zp,x) tests (LSB) 93 | 94 | .org $0100 95 | .dc $ff,$7a ; Put stack in known state 96 | .byte $7a ; Due to a limitation of our lst parser, need to mark the end point 97 | 98 | .org $0300 99 | 100 | start: 101 | nop 102 | nop 103 | nop 104 | jsr flags_dump 105 | 106 | lda #$03 107 | jsr flags_dump 108 | lda lda_zp_test ; Make sure we don't treat the operand as an opcode 109 | jsr flags_dump 110 | 111 | lda lda_abs_test 112 | jsr flags_dump 113 | 114 | ldx #$c0 115 | ldy #$30 116 | phx 117 | phy 118 | 119 | ; Direct flags manipulation 120 | lda #$ff 121 | sta $1fe 122 | stz $1ff 123 | 124 | plp 125 | jsr flags_dump 126 | plp 127 | jsr flags_dump 128 | sec 129 | jsr flags_dump 130 | sed 131 | jsr flags_dump 132 | sei 133 | jsr flags_dump 134 | clc 135 | jsr flags_dump 136 | cld 137 | jsr flags_dump 138 | cli 139 | jsr flags_dump 140 | clv 141 | jsr flags_dump 142 | 143 | ; Test addressing modes 144 | lda lda_abs_test 145 | lda lda_abs_test,x ; No page transition 146 | lda lda_abs_test-$c0,x ; With page transition 147 | lda lda_abs_test,y ; No page transition 148 | lda lda_abs_test-$30,y ; With page transition 149 | lda lda_zp_test 150 | .if c02 151 | lda (lda_zp_test+$100-$c0,x) 152 | .endif 153 | lda lda_zp_test+$100-$c0,x 154 | .if c02 155 | lda (lda_zp_test) 156 | .endif 157 | lda (lda_zp_test),y ; No page transition 158 | ldy #$f0 159 | lda (lda_zp_test),y ; With page transition 160 | 161 | 162 | ; ASL test 163 | lda #1 164 | asl_loop: 165 | asl asl_abs_test 166 | jsr flags_dump 167 | asl asl_abs_test,x 168 | jsr flags_dump 169 | asl asl_zp_test 170 | jsr flags_dump 171 | asl asl_zp_test,x 172 | jsr flags_dump 173 | asl 174 | jsr flags_dump 175 | bne asl_loop 176 | 177 | ; ADC tests 178 | ldx #2 179 | ldy #1 180 | adc_loop: 181 | adc adc_abs_test 182 | pha 183 | php 184 | and adc_abs_test 185 | pha 186 | php 187 | adc adc_abs_test,x 188 | pha 189 | php 190 | and adc_abs_test,x 191 | pha 192 | php 193 | adc adc_abs_test,y 194 | pha 195 | php 196 | and adc_abs_test,y 197 | pha 198 | php 199 | adc #$cd 200 | pha 201 | php 202 | and #$a7 203 | pha 204 | php 205 | adc adc_zp_test 206 | pha 207 | php 208 | and adc_zp_test 209 | pha 210 | php 211 | adc (adc_zp_test,x) 212 | pha 213 | php 214 | and (adc_zp_test,x) 215 | pha 216 | php 217 | adc adc_zp_test,x 218 | pha 219 | php 220 | and adc_zp_test,x 221 | pha 222 | php 223 | adc (adc_zp_test) 224 | pha 225 | php 226 | and (adc_zp_test) 227 | pha 228 | php 229 | adc (adc_zp_test),y 230 | pha 231 | php 232 | and (adc_zp_test),y 233 | pha 234 | php 235 | iny 236 | dex 237 | bne adc_loop 238 | 239 | sbc_loop: 240 | sbc adc_abs_test 241 | pha 242 | php 243 | ora adc_abs_test 244 | pha 245 | php 246 | sbc adc_abs_test,x 247 | pha 248 | php 249 | ora adc_abs_test,x 250 | pha 251 | php 252 | sbc adc_abs_test,y 253 | pha 254 | php 255 | ora adc_abs_test,y 256 | pha 257 | php 258 | sbc #$cd 259 | pha 260 | php 261 | ora #$cd 262 | pha 263 | php 264 | sbc adc_zp_test 265 | pha 266 | php 267 | ora adc_zp_test 268 | pha 269 | php 270 | sbc (adc_zp_test,x) 271 | pha 272 | php 273 | ora (adc_zp_test,x) 274 | pha 275 | php 276 | sbc adc_zp_test,x 277 | pha 278 | php 279 | ora adc_zp_test,x 280 | pha 281 | php 282 | sbc (adc_zp_test) 283 | pha 284 | php 285 | ora (adc_zp_test) 286 | pha 287 | php 288 | sbc (adc_zp_test),y 289 | pha 290 | php 291 | ora (adc_zp_test),y 292 | pha 293 | php 294 | inx 295 | dey 296 | bne sbc_loop 297 | 298 | ; BIT test 299 | lda #$4f 300 | php 301 | ldx #$1a 302 | php 303 | ldy #$22 304 | php 305 | 306 | bit bit_abs_test 307 | php 308 | bit bit_abs_test,x 309 | php 310 | bit #$b0 311 | php 312 | bit bit_zp_test 313 | php 314 | bit bit_zp_test,x 315 | php 316 | 317 | ; BRK test 318 | sed 319 | cli 320 | brk 321 | .byte $1 322 | cld 323 | sei 324 | brk 325 | .byte $2 326 | 327 | ; CMP test 328 | cmp cmp_abs_test 329 | php 330 | cmp cmp_abs_test,x 331 | php 332 | cmp cmp_abs_test,y 333 | php 334 | cmp #$db 335 | php 336 | cmp cmp_zp_test 337 | php 338 | cmp (cmp_zp_test,x) 339 | php 340 | cmp cmp_zp_test,x 341 | php 342 | cmp (cmp_zp_test) 343 | php 344 | cmp (cmp_zp_test),y 345 | php 346 | cmp #$4e 347 | php 348 | cmp #$4f 349 | php 350 | cmp #$50 351 | php 352 | 353 | ; CPX test 354 | cpx cmp_abs_test 355 | php 356 | cpx #$db 357 | php 358 | cpx cmp_zp_test 359 | php 360 | cpx #$19 361 | php 362 | cpx #$1a 363 | php 364 | cpx #$1b 365 | php 366 | ldx #$a0 367 | cpx #$0 368 | php 369 | 370 | ; CPY test 371 | cpy cmp_abs_test 372 | php 373 | cpy #$db 374 | php 375 | cpy cmp_zp_test 376 | php 377 | cpy #$19 378 | php 379 | cpy #$1a 380 | php 381 | cpy #$1b 382 | php 383 | ldx #$a0 384 | cpy #$0 385 | php 386 | 387 | ; DEC test 388 | dec dec_abs_test 389 | php 390 | dec dec_abs_test,x 391 | php 392 | dec dec_zp_test 393 | php 394 | dec dec_zp_test,x 395 | php 396 | 397 | dec_loop: 398 | dec 399 | php 400 | bne dec_loop 401 | dec 402 | php 403 | 404 | jsr bb_test 405 | lda branch_bit_test 406 | eor #$ff 407 | sta branch_bit_test 408 | jsr bb_test 409 | 410 | ; EOR test 411 | php 412 | eor eor_abs_test 413 | pha 414 | php 415 | eor eor_abs_test,x 416 | pha 417 | php 418 | eor eor_abs_test,y 419 | pha 420 | php 421 | eor #$f4 422 | pha 423 | php 424 | eor eor_zp_test 425 | pha 426 | php 427 | eor (eor_zp_test,x) 428 | pha 429 | php 430 | eor eor_zp_test,x 431 | pha 432 | php 433 | eor (eor_zp_test) 434 | pha 435 | php 436 | eor (eor_zp_test),y 437 | pha 438 | php 439 | 440 | 441 | ; inc tests 442 | dec 443 | dec 444 | ldx #$3 445 | 446 | inc_loop: 447 | inc inc_abs_test 448 | php 449 | inc inc_abs_test,x 450 | php 451 | inc 452 | php 453 | inc inc_zp_test 454 | php 455 | inc inc_zp_test,x 456 | php 457 | 458 | dex 459 | bne inc_loop 460 | 461 | jmp jmp_tests 462 | brk ; Unreachable 463 | jmp_test_continues: 464 | php 465 | 466 | 467 | ; LDX test 468 | ldx ldx_abs_test 469 | php 470 | stx value_dump 471 | ldx ldx_abs_test,y 472 | php 473 | stx value_dump 474 | ldx ldx_abs_test-$22,y 475 | php 476 | stx value_dump 477 | ldx #$04 478 | php 479 | stx value_dump 480 | ldx ldx_zp_test 481 | php 482 | stx value_dump 483 | ldx ldx_zp_test,y 484 | php 485 | stx value_dump 486 | 487 | 488 | ; LDY test 489 | ldy ldy_abs_test 490 | php 491 | sty value_dump 492 | ldy ldy_abs_test,x 493 | php 494 | sty value_dump 495 | ldy #$6c 496 | php 497 | sty value_dump 498 | ldy ldy_zp_test 499 | php 500 | sty value_dump 501 | ldy ldy_zp_test,x 502 | php 503 | sty value_dump 504 | 505 | 506 | ; LSR test 507 | lsr lsr_abs_test 508 | php 509 | lsr lsr_abs_test,x 510 | php 511 | lsr 512 | php 513 | sta value_dump 514 | lsr lsr_zp_test 515 | php 516 | lsr lsr_zp_test,x 517 | php 518 | 519 | 520 | ; Stack pull tests 521 | lda #$fc 522 | sta $1a3 ; A 523 | stz $1a4 ; Y 524 | lda #$55 525 | sta $1a5 ; A 526 | lda #$dd 527 | sta $1a6 ; Y 528 | stz $1a7 ; A 529 | lda #$03 530 | sta $1a8 ; Y 531 | lda #$9b 532 | sta $1a9 ; X 533 | lda #$2d 534 | sta $1aa ; X 535 | stz $1ab ; X 536 | 537 | ldx #$03 538 | pull_test_loop1: 539 | pla 540 | sta value_dump 541 | php 542 | plp 543 | ply 544 | sty value_dump 545 | php 546 | plp 547 | 548 | dex 549 | bne pull_test_loop1 550 | 551 | pull_test_loop2: 552 | plx 553 | stx value_dump 554 | php 555 | plp 556 | 557 | dey 558 | bne pull_test_loop2 559 | 560 | 561 | ; RMB/SMB test 562 | rmb 0,rmb_zp_test 563 | rmb 0,rmb_zp_test+1 564 | rmb 1,rmb_zp_test 565 | rmb 1,rmb_zp_test+1 566 | rmb 2,rmb_zp_test 567 | rmb 2,rmb_zp_test+1 568 | rmb 3,rmb_zp_test 569 | rmb 3,rmb_zp_test+1 570 | rmb 4,rmb_zp_test 571 | rmb 4,rmb_zp_test+1 572 | rmb 5,rmb_zp_test 573 | rmb 5,rmb_zp_test+1 574 | rmb 6,rmb_zp_test 575 | rmb 6,rmb_zp_test+1 576 | rmb 7,rmb_zp_test 577 | rmb 7,rmb_zp_test+1 578 | 579 | smb 0,smb_zp_test 580 | smb 0,smb_zp_test+1 581 | smb 1,smb_zp_test 582 | smb 1,smb_zp_test+1 583 | smb 2,smb_zp_test 584 | smb 2,smb_zp_test+1 585 | smb 3,smb_zp_test 586 | smb 3,smb_zp_test+1 587 | smb 4,smb_zp_test 588 | smb 4,smb_zp_test+1 589 | smb 5,smb_zp_test 590 | smb 5,smb_zp_test+1 591 | smb 6,smb_zp_test 592 | smb 6,smb_zp_test+1 593 | smb 7,smb_zp_test 594 | smb 7,smb_zp_test+1 595 | 596 | 597 | ; ROL/ROR test 598 | ldx #1 599 | lda #$af 600 | rol rol_abs_test 601 | php 602 | rol 603 | php 604 | sta value_dump 605 | ror rol_abs_test+1 606 | php 607 | rol rol_abs_test,x 608 | php 609 | ror rol_abs_test+1,x 610 | php 611 | ror 612 | php 613 | sta value_dump 614 | rol rol_zp_test 615 | php 616 | ror rol_zp_test+1 617 | php 618 | rol rol_zp_test,x 619 | php 620 | ror rol_zp_test+1,x 621 | php 622 | 623 | lda #1 624 | clc 625 | ror 626 | php 627 | sta value_dump 628 | rol 629 | php 630 | sta value_dump 631 | sec 632 | ror 633 | php 634 | sta value_dump 635 | clc 636 | rol 637 | php 638 | sta value_dump 639 | 640 | 641 | ; STA test 642 | ldy #$02 643 | sta sta_abs_test 644 | inc 645 | sta sta_abs_test,x 646 | inc 647 | sta sta_abs_test,y 648 | inc 649 | sta sta_zp_test 650 | inc 651 | sta sta_zp_test,x 652 | inc 653 | sta (sta_zp_test,x) 654 | inc 655 | sta (sta_zp_test) 656 | inc 657 | sta (sta_zp_test),y 658 | inc 659 | ldx #$80 660 | sta sta_abs_test,x 661 | inc 662 | ldy #$ff 663 | sta sta_abs_test,y 664 | inc 665 | sta (sta_zp_test),y 666 | php 667 | 668 | 669 | ; STX test 670 | stx sta_abs_test 671 | inx 672 | stx sta_zp_test+1 673 | inx 674 | stx sta_zp_test+1,y 675 | php 676 | 677 | 678 | ; STY test 679 | ldx #$2 680 | sty sta_abs_test 681 | iny 682 | sty sta_zp_test 683 | iny 684 | sty sta_zp_test,x 685 | php 686 | 687 | 688 | ; STZ test 689 | stz sta_abs_test 690 | stz sta_abs_test,x 691 | stz sta_zp_test 692 | stz sta_zp_test,x 693 | php 694 | 695 | 696 | ; Transfer test 697 | lda #$85 698 | jsr transfer_tests 699 | lda #$00 700 | jsr transfer_tests 701 | 702 | tsx 703 | jsr dump_state 704 | ldx #$ff 705 | lda #$00 706 | txs 707 | jsr dump_state 708 | 709 | 710 | ; TSB/TRB test 711 | lda #$89 712 | trb trb_abs_test 713 | jsr dump_state 714 | trb trb_abs_test+1 715 | jsr dump_state 716 | 717 | tsb tsb_abs_test 718 | jsr dump_state 719 | 720 | trb trb_zp_test 721 | jsr dump_state 722 | trb trb_zp_test+1 723 | jsr dump_state 724 | 725 | tsb tsb_zp_test 726 | jsr dump_state 727 | 728 | lda #$00 729 | tsb trb_abs_test+1 730 | jsr dump_state 731 | tsb tsb_zp_test+1 732 | jsr dump_state 733 | 734 | 735 | jsr regression1_apple2_disassembly 736 | 737 | 738 | ; IRQ test 739 | lda #$6 740 | sta IRQ_TRIGGER_COUNT 741 | sta IRQ_TRIGGER_DELAY 742 | nop 743 | nop 744 | nop 745 | nop 746 | nop 747 | nop 748 | nop 749 | nop 750 | nop 751 | nop 752 | 753 | lda #30 754 | sta IRQ_TRIGGER_COUNT 755 | ldx #4 756 | stx IRQ_TRIGGER_DELAY 757 | nop 758 | nop 759 | nop 760 | nop 761 | cli 762 | nop 763 | nop 764 | nop 765 | nop 766 | nop 767 | nop 768 | 769 | 770 | ; NMI test 771 | lda #40 772 | sta NMI_TRIGGER_COUNT 773 | sta IRQ_TRIGGER_COUNT 774 | ldx #15 775 | ldy #11 776 | stx IRQ_TRIGGER_DELAY 777 | sty NMI_TRIGGER_DELAY 778 | 779 | nop 780 | nop 781 | nop 782 | nop 783 | nop 784 | nop 785 | nop 786 | nop 787 | nop 788 | nop 789 | nop 790 | nop 791 | nop 792 | nop 793 | nop 794 | nop 795 | 796 | 797 | ; Ready and SO tests 798 | clv 799 | 800 | lda #10 801 | sta READY_TRIGGER_COUNT 802 | lda #2 803 | sta SO_TRIGGER_COUNT 804 | ldx #9 805 | ldy #30 806 | stx READY_TRIGGER_DELAY 807 | sty SO_TRIGGER_DELAY 808 | 809 | so_test_loop: 810 | bvc so_test_loop 811 | 812 | 813 | ; STP test 814 | lda #(stp_test_cont1 % 256) 815 | sta reset_vector 816 | lda #(stp_test_cont1 / 256) 817 | sta reset_vector+1 818 | lda #$04 819 | sta RESET_TRIGGER_COUNT 820 | lda #$10 821 | sta RESET_TRIGGER_DELAY 822 | 823 | stp 824 | 825 | stp_test_cont1: 826 | jsr dump_state 827 | 828 | lda #(stp_test_cont2 % 256) 829 | sta reset_vector 830 | lda #(stp_test_cont2 / 256) 831 | sta reset_vector+1 832 | 833 | lda #$ff 834 | pha 835 | plp 836 | jsr dump_state 837 | 838 | lda #$04 839 | sta RESET_TRIGGER_COUNT 840 | sta RESET_TRIGGER_DELAY 841 | 842 | nop 843 | nop 844 | nop 845 | nop 846 | nop 847 | nop 848 | nop 849 | nop 850 | 851 | stp_test_cont2: 852 | ; We don't care about the status flags, only D and I 853 | lda #$00 854 | clv 855 | clc 856 | jsr dump_state 857 | 858 | lda #(stp_test_cont3 % 256) 859 | sta reset_vector 860 | lda #(stp_test_cont3 / 256) 861 | sta reset_vector+1 862 | 863 | lda #$00 864 | pha 865 | plp 866 | jsr dump_state 867 | 868 | lda #$04 869 | sta RESET_TRIGGER_COUNT 870 | sta RESET_TRIGGER_DELAY 871 | 872 | nop 873 | nop 874 | nop 875 | nop 876 | nop 877 | nop 878 | nop 879 | nop 880 | 881 | stp_test_cont3: 882 | ; We don't care about the status flags, only D and I 883 | lda #$00 884 | clv 885 | clc 886 | jsr dump_state 887 | 888 | 889 | ; WAI tests 890 | cli 891 | lda #6 892 | sta IRQ_TRIGGER_COUNT 893 | lda #10 894 | sta IRQ_TRIGGER_DELAY 895 | wai 896 | 897 | sei 898 | lda #6 899 | sta IRQ_TRIGGER_COUNT 900 | lda #10 901 | sta IRQ_TRIGGER_DELAY 902 | wai 903 | 904 | lda #6 905 | sta NMI_TRIGGER_COUNT 906 | lda #10 907 | sta NMI_TRIGGER_DELAY 908 | wai 909 | 910 | 911 | sta FINISHED_TRIGGER 912 | .byte 00 913 | 914 | transfer_tests: 915 | jsr dump_state 916 | ldy #$01 917 | tay 918 | jsr dump_state 919 | ldx #$02 920 | tax 921 | jsr dump_state 922 | eor #$ff 923 | ldy #$01 924 | tya 925 | jsr dump_state 926 | ldx #$01 927 | txa 928 | jsr dump_state 929 | rts 930 | 931 | 932 | dump_state: 933 | php 934 | sta value_dump 935 | stx value_dump 936 | sty value_dump 937 | plp 938 | rts 939 | 940 | reset_handler: 941 | ldx #$ff 942 | txs 943 | lda #start/256 944 | pha 945 | lda #start%256 946 | pha 947 | lda #INTMASK+OVERFLOW 948 | pha 949 | rti 950 | brk ; Unreachable 951 | 952 | 953 | .org $0a4f 954 | .byte $8f ; cmp (zp) test 955 | 956 | .org $0a71 957 | .byte $25 ; cmp (zp),y test 958 | 959 | .org $13d5 960 | .byte $dd ; adc (zp,x) test 961 | 962 | .org $1690 963 | bit_abs_test: 964 | .byte $6b 965 | 966 | .org $16aa 967 | .byte $03 ; bit abs,x 968 | 969 | .org $1a10 970 | ldx_abs_test: 971 | .byte $6d 972 | 973 | .org $1a32 974 | .byte $d7 ; ldx abs,y 975 | 976 | .org $26ff 977 | jmp_ind_test2: 978 | .word jmp_dest2 979 | .byte 0 980 | .word jmp_dest4 981 | 982 | .org $2746 983 | .word jmp_test_continues 984 | 985 | .org $274f 986 | .word jmp_dest5 987 | 988 | .org $27b8 989 | jmp_ind_test1: 990 | .word jmp_dest1 991 | .byte 0 992 | .word jmp_dest3 993 | 994 | .org $27ff 995 | .word jmp_dest3 996 | 997 | .org $2808 998 | .word jmp_dest3 999 | 1000 | .org $3787 1001 | cmp_abs_test: 1002 | .byte $b8 1003 | 1004 | .org $37a1 1005 | .byte $6f 1006 | 1007 | .org $37a9 1008 | .byte $0e 1009 | 1010 | .org $40ef 1011 | 1012 | flags_dump: 1013 | php 1014 | bcs .1 1015 | bcc .1 1016 | 1017 | .2 bvs .3 1018 | bvc .3 1019 | 1020 | .4 bra .5 1021 | 1022 | .3 bne .4 1023 | beq .4 1024 | 1025 | .1 bmi .2 1026 | bpl .2 1027 | 1028 | .5 1029 | plp 1030 | rts 1031 | .byte 00 1032 | 1033 | .org $41ef 1034 | bb_test: 1035 | ; Branch bit tests 1036 | bbr 0, branch_bit_test, .1 1037 | bbs 0, branch_bit_test, .1 1038 | 1039 | .2 bbr 2, branch_bit_test, .3 1040 | bbs 2, branch_bit_test, .3 1041 | 1042 | .4 bbr 4, branch_bit_test, .5 1043 | bbs 4, branch_bit_test, .5 1044 | 1045 | .6 bbr 6, branch_bit_test, .7 1046 | bbs 6, branch_bit_test, .7 1047 | 1048 | .8 rts 1049 | 1050 | .7 bbr 7, branch_bit_test, .8 1051 | bbs 7, branch_bit_test, .8 1052 | 1053 | .5 bbr 5, branch_bit_test, .6 1054 | bbs 5, branch_bit_test, .6 1055 | 1056 | .3 bbr 3, branch_bit_test, .4 1057 | bbs 3, branch_bit_test, .4 1058 | 1059 | .1 bbr 1, branch_bit_test, .2 1060 | bbs 1, branch_bit_test, .2 1061 | 1062 | brk ; Unreachable 1063 | 1064 | int_handler: 1065 | php 1066 | plp 1067 | rti 1068 | brk ; Unreachable 1069 | 1070 | nmi_handler: 1071 | jmp int_handler 1072 | brk ; Unreachable 1073 | 1074 | .org $4694 1075 | sta_abs_test: .byte $87, $91, $20 1076 | 1077 | .org $55aa 1078 | jmp_tests: 1079 | ldx #$3 1080 | 1081 | jmp (jmp_ind_test1) 1082 | brk ; Unreachable 1083 | 1084 | .org $5ee6 1085 | .byte $3f ; eor (zp,x) test 1086 | 1087 | .org $61da 1088 | dec_abs_test .byte $7b 1089 | 1090 | .org $61ff 1091 | inc_abs_test .byte $fe, $30, $22, $48 ; inc abs, int abs,x tests 1092 | 1093 | .org $627a 1094 | .byte $01 ; dec abs,x test 1095 | 1096 | .org $6d21 1097 | lda_abs_test .byte $74 1098 | .org $6d51 1099 | .byte $c7 ; lda abs,y 1100 | .org $6de1 1101 | .byte $08 ; lda abs,x 1102 | 1103 | .org $7088 1104 | .byte $29 ; eor (zp) 1105 | .org $70aa 1106 | .byte $50 ; eor (zp),y 1107 | 1108 | .org $7ace 1109 | adc_abs_test: .byte $65, $ca, $26, $6b 1110 | 1111 | .org $7d15 1112 | trb_abs_test: .byte $d7, $36 1113 | tsb_abs_test: .byte $a5, $00 1114 | 1115 | .org $7ea8 1116 | lsr_abs_test: 1117 | .byte $9b 1118 | 1119 | .org $7f9d 1120 | .byte $49 ; lsr abs,x 1121 | 1122 | .org $8510 1123 | asl_abs_test: .byte $56 1124 | .org $85d0 1125 | .byte $40 ; asl abs,x test 1126 | 1127 | .org $a303 1128 | jmp_dest2: 1129 | jmp (jmp_ind_test1,x) 1130 | brk ; Unreachable 1131 | 1132 | jmp_dest3: 1133 | jmp (jmp_ind_test2,x) 1134 | brk 1135 | 1136 | jmp_dest5: 1137 | ldx #$47 1138 | jmp jmp_dest1 1139 | brk ; Unreachable 1140 | 1141 | jmp_dest4: 1142 | ldx #$50 1143 | 1144 | jmp_dest1: 1145 | jmp (jmp_ind_test2) 1146 | brk ; Unreachable 1147 | 1148 | .org $ae38 1149 | lda_indirect_test .byte $bf 1150 | .org $ae68 1151 | .byte $20 ; lda (zp),y test 1152 | .org $af28 1153 | .byte $22 ; lda (zp),y test 1154 | 1155 | .org $c213 1156 | .byte $25 ; adc (zp,x) test 1157 | 1158 | .org $d074 1159 | eor_abs_test .byte $17 1160 | 1161 | .org $d096 1162 | .byte $11 ; eor abs,y 1163 | 1164 | .org $d114 1165 | .byte $49 ; eor abs,x test 1166 | 1167 | .org $d2cc 1168 | .byte $38 ; cmp (zp,x) test 1169 | 1170 | .org $d588 1171 | .byte $15 ; adc (zp,x) test 1172 | .byte $8e, $9b, $f5 ; adc (zp),y test 1173 | 1174 | .org $e308 1175 | ldy_abs_test: 1176 | .byte $ff 1177 | 1178 | .org $e3fd 1179 | .byte $93 ; ldy abs,x 1180 | 1181 | 1182 | .org $f800 1183 | regression1_apple2_disassembly: 1184 | lda #$a9 ; Should have registered as LDA immediate, registers as ??? 1185 | jsr .0 1186 | lda #$85 ; Should have registered as STA zp, registers as ??? 1187 | jsr .0 1188 | lda #$ad ; Should have registered as LDA abs, registers as LDA zp 1189 | jsr .0 1190 | 1191 | rts 1192 | brk ; Unreachable 1193 | 1194 | .org $f882 1195 | ; Apple 2 autostart ROM INSDS1 routine 1196 | .0 1197 | tay 1198 | lsr 1199 | bcc .1 1200 | ror 1201 | bcs .2 1202 | cmp #$A2 1203 | beq .2 1204 | and #$87 1205 | .1 ; IEVEN 1206 | lsr 1207 | tax 1208 | lda FMT1,x 1209 | jsr .8 1210 | bne .5 1211 | .2 ; ERR 1212 | ldy #$80 1213 | lda #$00 1214 | .5 ; GETFMT 1215 | tax 1216 | lda FMT2,x 1217 | sta $2e ; F8.MASK 1218 | and #$03 1219 | sta $2f ; LENGTH 1220 | 1221 | rts 1222 | 1223 | .8 bcc .9 1224 | lsr A 1225 | lsr A 1226 | lsr A 1227 | lsr A 1228 | .9 and #$0f 1229 | rts 1230 | 1231 | FMT1 .byte $04,$20,$54,$30,$0d,$80,$04,$90,$03,$22,$54,$33,$0d,$80,$04,$90 1232 | .byte $04,$20,$54,$33,$0d,$80,$04,$90,$04,$20,$54,$3b,$0d,$80,$04,$90 1233 | .byte $00,$22,$44,$33,$0d,$c8,$44,$00,$11,$22,$44,$33,$0d,$c8,$44,$a9 1234 | .byte $01,$22,$44,$33,$0d,$80,$04,$90,$01,$22,$44,$33,$0d,$80,$04,$90 1235 | .byte $26,$31,$87,$9a 1236 | FMT2 .data $00,$21,$81,$82,$00,$00,$59,$4d,$91,$92,$86,$4a,$85,$9d 1237 | 1238 | .org $f9f8 1239 | rol_abs_test: 1240 | .byte $cd, $71, $e4 1241 | 1242 | .org $fffa 1243 | nmi_vector: .word nmi_handler 1244 | reset_vector: .word reset_handler 1245 | irq_vector: .word int_handler 1246 | -------------------------------------------------------------------------------- /sar6502.srcs/sources_1/new/alu.sv: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: Some Assembly Required Youtube channel https://www.youtube.com/channel/UCp5Z7utSI2IHQUsnkPH41bw 4 | // Engineer: Shachar Shemesh 5 | // 6 | // Create Date: 09/19/2021 05:42:25 PM 7 | // Design Name: WD65C02S core almost compatible design 8 | // Module Name: alu 9 | // Project Name: CompuSAR 10 | // Target Devices: Xilinx Spartan-7 11 | // Tool Versions: Vivado 2021.1 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | // License: 21 | // Copyright (C) 2021. 22 | // Copyright owners listed in AUTHORS file. 23 | // 24 | // This program is free software; you can redistribute it and/or modify 25 | // it under the terms of the GNU General Public License as published by 26 | // the Free Software Foundation; either version 2 of the License, or 27 | // (at your option) any later version. 28 | // 29 | // This program is distributed in the hope that it will be useful, 30 | // but WITHOUT ANY WARRANTY; without even the implied warranty of 31 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 32 | // GNU General Public License for more details. 33 | // 34 | // You should have received a copy of the GNU General Public License 35 | // along with this program; if not, write to the Free Software 36 | // Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA 37 | // 38 | ////////////////////////////////////////////////////////////////////////////////// 39 | 40 | module alu( 41 | input [7:0]a, 42 | input [7:0]b, 43 | input carry_in, 44 | input inverse_b, 45 | input control_signals::alu_control control, 46 | 47 | output logic [7:0]result, 48 | output logic carry_out, 49 | output logic overflow_out 50 | ); 51 | 52 | logic [7:0]effective_b; 53 | 54 | always_comb 55 | begin 56 | result = 8'bX; 57 | carry_out = 1'bX; 58 | overflow_out = 'X; 59 | 60 | if( inverse_b ) 61 | effective_b = ~b; 62 | else 63 | effective_b = b; 64 | 65 | case(control) 66 | control_signals::AluOp_pass: result = a; 67 | control_signals::AluOp_add: do_plus(); 68 | control_signals::AluOp_and: result = a & effective_b; 69 | control_signals::AluOp_or: result = a | effective_b; 70 | control_signals::AluOp_xor: result = a ^ effective_b; 71 | control_signals::AluOp_shift_left: { carry_out, result } = { a, carry_in }; 72 | control_signals::AluOp_shift_right_logical: { result, carry_out } = { carry_in, a }; 73 | endcase 74 | end 75 | 76 | logic [8:0]intermediate_result; 77 | 78 | task do_plus(); 79 | begin 80 | intermediate_result = a+effective_b+carry_in; 81 | result = intermediate_result[7:0]; 82 | 83 | carry_out = intermediate_result[8]; 84 | 85 | if( a[7]==effective_b[7] && a[7]!=result[7] ) 86 | // Adding same sign integer resulted in opposite sign integer: must be an overflow 87 | overflow_out = 1; 88 | else 89 | overflow_out = 0; 90 | end 91 | endtask 92 | 93 | endmodule 94 | -------------------------------------------------------------------------------- /sar6502.srcs/sources_1/new/bus_sources.sv: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | package bus_sources; 4 | 5 | typedef enum logic[31:0] { 6 | DataBusSrc_Invalid = 'X, 7 | DataBusSrc_Zero = 0, 8 | DataBusSrc_Ones, 9 | 10 | DataBusSrc_A, 11 | DataBusSrc_X, 12 | DataBusSrc_Y, 13 | DataBusSrc_SP, 14 | DataBusSrc_Status, 15 | DataBusSrc_Alu, 16 | DataBusSrc_Alu_Latched, 17 | 18 | DataBusSrc_Pc_Low, 19 | DataBusSrc_Pc_High, 20 | 21 | DataBusSrc_Dl_Low, 22 | 23 | DataBusSrc_Mem, 24 | DataBusSrc_Mem_Unlatched, 25 | 26 | DataBusSrc_End_Marker 27 | } DataBusSourceCtl; 28 | 29 | localparam DataBusSourceCtlLast = DataBusSrc_End_Marker - 1; 30 | 31 | typedef enum logic[31:0] { 32 | AddrBusLowSrc_Invalid = 'X, 33 | 34 | AddrBusLowSrc_Mem = 0, 35 | AddrBusLowSrc_Alu, 36 | AddrBusLowSrc_PC, 37 | AddrBusLowSrc_SP, 38 | AddrBusLowSrc_DataLatch, 39 | AddrBusLowSrc_DataLatch_High, 40 | 41 | AddrBusLowSrc_End_Marker 42 | } AddressBusLowSourceCtl; 43 | 44 | localparam AddressBusLowSourceCtlLast = AddrBusLowSrc_End_Marker - 1; 45 | 46 | typedef enum logic[31:0] { 47 | AddrBusHighSrc_Invalid = 'X, 48 | 49 | AddrBusHighSrc_Zero = 0, 50 | AddrBusHighSrc_One, 51 | AddrBusHighSrc_Mem, 52 | AddrBusHighSrc_Alu, 53 | AddrBusHighSrc_Alu_Unlatched, 54 | AddrBusHighSrc_PC, 55 | AddrBusHighSrc_DataLatch, 56 | 57 | AddrBusHighSrc_End_Marker 58 | } AddressBusHighSourceCtl; 59 | 60 | localparam AddressBusHighSourceCtlLast = AddrBusHighSrc_End_Marker - 1; 61 | 62 | typedef enum logic[31:0] { 63 | PcLowSource_Invalid = 'X, 64 | 65 | PcLowSource_CurrentValue = 0, 66 | PcLowSource_Mem, 67 | PcLowSource_Dl, 68 | 69 | PcLowSource_End_Marker 70 | } PcLowSourceCtl; 71 | 72 | localparam PcLowSourceCtlLast = PcLowSource_End_Marker - 1; 73 | 74 | typedef enum logic[31:0] { 75 | PcHighSource_Invalid = 'X, 76 | 77 | PcHighSource_CurrentValue = 0, 78 | PcHighSource_Mem, 79 | PcHighSource_Dl, 80 | PcHighSource_Alu_Latched, 81 | 82 | PcHighSource_End_Marker 83 | } PcHighSourceCtl; 84 | 85 | localparam PcHighSourceCtlLast = PcHighSource_End_Marker - 1; 86 | 87 | typedef enum logic[31:0] { 88 | DataLatchLowSource_Invalid = 'X, 89 | 90 | DataLatchLowSource_Mem = 0, 91 | DataLatchLowSource_Alu, 92 | DataLatchLowSource_Alu_Latched, 93 | DataLatchLowSource_PC, 94 | 95 | DataLatchLowSource_FA, 96 | DataLatchLowSource_FC, 97 | DataLatchLowSource_FE, 98 | 99 | DataLatchLowSource_End_Marker 100 | } DataLatchLowSourceCtl; 101 | 102 | localparam DataLatchLowSourceCtlLast = DataLatchLowSource_End_Marker - 1; 103 | 104 | typedef enum logic[31:0] { 105 | DataLatchHighSource_Invalid = 'X, 106 | 107 | DataLatchHighSource_Zero = 0, 108 | DataLatchHighSource_Mem, 109 | DataLatchHighSource_Alu, 110 | DataLatchHighSource_Alu_Latched, 111 | DataLatchHighSource_PC, 112 | 113 | DataLatchHighSource_FF, 114 | 115 | DataLatchHighSource_End_Marker 116 | } DataLatchHighSourceCtl; 117 | 118 | localparam DataLatchHighSourceCtlLast = DataLatchHighSource_End_Marker - 1; 119 | 120 | typedef enum logic[31:0] { 121 | StackPointerSource_Invalid = 'X, 122 | 123 | StackPointerSource_Alu = 0, 124 | StackPointerSource_DataBus, 125 | 126 | StackPointerSource_End_Marker 127 | } StackPointerSourceCtl; 128 | 129 | localparam StackPointerSourceCtlLast = StackPointerSource_End_Marker -1; 130 | 131 | typedef enum logic[31:0] { 132 | AluASourceCtl_Invalid = 'X, 133 | 134 | AluASourceCtl_Zero = 0, 135 | AluASourceCtl_A, 136 | AluASourceCtl_X, 137 | AluASourceCtl_Y, 138 | AluASourceCtl_DataLatchLow, 139 | AluASourceCtl_DataLatchHigh, 140 | AluASourceCtl_SP, 141 | AluASourceCtl_PC_Low, 142 | AluASourceCtl_PC_High, 143 | AluASourceCtl_Mem, 144 | AluASourceCtl_Alu, 145 | 146 | AluASourceCtl_End_Marker 147 | } AluASourceCtl; 148 | 149 | localparam AluASourceCtlLast = AluASourceCtl_End_Marker - 1; 150 | 151 | typedef enum logic[31:0] { 152 | AluBSourceCtl_Invalid = 'X, 153 | 154 | AluBSourceCtl_Zero = 0, 155 | AluBSourceCtl_Bit0, 156 | AluBSourceCtl_Bit1, 157 | AluBSourceCtl_Bit2, 158 | AluBSourceCtl_Bit3, 159 | AluBSourceCtl_Bit4, 160 | AluBSourceCtl_Bit5, 161 | AluBSourceCtl_Bit6, 162 | AluBSourceCtl_Bit7, 163 | AluBSourceCtl_Mem, 164 | AluBSourceCtl_A, 165 | 166 | AluBSourceCtl_End_Marker 167 | } AluBSourceCtl; 168 | 169 | localparam AluBSourceCtlLast = AluBSourceCtl_End_Marker - 1; 170 | 171 | typedef enum logic[31:0] { 172 | AluCarrySource_Invalid = 'X, 173 | 174 | AluCarrySource_Zero = 0, 175 | AluCarrySource_One, 176 | AluCarrySource_Carry, 177 | 178 | AluCarrySource_End_Marker 179 | } AluCarrySourceCtl; 180 | 181 | localparam AluCarrySourceCtlLast = AluCarrySource_End_Marker - 1; 182 | 183 | endpackage // bus_sources 184 | -------------------------------------------------------------------------------- /sar6502.srcs/sources_1/new/control_signals.sv: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | package control_signals; 4 | 5 | typedef enum logic[31:0] { 6 | CTL_SIG_INVALID = 'X, 7 | 8 | LOAD_A = 0, 9 | LOAD_X, 10 | LOAD_Y, 11 | LOAD_SP, 12 | LOAD_DataLow, 13 | LOAD_DataHigh, 14 | 15 | PC_LOAD, 16 | PC_ADVANCE, 17 | 18 | UpdateFlagC, 19 | UpdateFlagZ, 20 | UpdateFlagI, 21 | UpdateFlagD, 22 | OutputFlagB, 23 | UpdateFlagV, 24 | UpdateFlagN, 25 | 26 | LastLoadSignal, 27 | 28 | UseAluFlags, 29 | CalculateFlagZ, 30 | AluBInverse, 31 | 32 | CtrlSignals_EndMarker 33 | } ctrl_signals; 34 | 35 | localparam ctrl_signals_last = CtrlSignals_EndMarker-1; 36 | 37 | typedef enum logic[31:0] { 38 | AluOp_INVALID = 'X, 39 | 40 | AluOp_pass = 0, 41 | AluOp_add, 42 | AluOp_and, 43 | AluOp_or, 44 | AluOp_xor, 45 | AluOp_shift_left, 46 | AluOp_shift_right_logical 47 | } alu_control; 48 | 49 | typedef enum { 50 | FlagsCarry = 0, 51 | FlagsZero = 1, 52 | FlagsIrqMask = 2, 53 | FlagsDecimal = 3, 54 | FlagsBrk = 4, 55 | FlagsOverflow = 6, 56 | FlagsNegative = 7 57 | } Flags; 58 | 59 | endpackage // control_signals 60 | -------------------------------------------------------------------------------- /sar6502.srcs/sources_1/new/program_counter.sv: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: Some Assembly Required 4 | // Engineer: Shachar Shemesh 5 | // 6 | // Create Date: 02/23/2022 09:12:28 PM 7 | // Design Name: sar6502 8 | // Module Name: sar6502 9 | // Project Name: CompuSAR 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: Customizable implementation of the 6502 CPU 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | // License: 21 | // Copyright (C) 2022. 22 | // Copyright owners listed in AUTHORS file. 23 | // 24 | // This program is free software; you can redistribute it and/or modify 25 | // it under the terms of the GNU General Public License as published by 26 | // the Free Software Foundation; either version 2 of the License, or 27 | // (at your option) any later version. 28 | // 29 | // This program is distributed in the hope that it will be useful, 30 | // but WITHOUT ANY WARRANTY; without even the implied warranty of 31 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 32 | // GNU General Public License for more details. 33 | // 34 | // You should have received a copy of the GNU General Public License 35 | // along with this program; if not, write to the Free Software 36 | // Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA 37 | // 38 | ////////////////////////////////////////////////////////////////////////////////// 39 | 40 | module program_counter( 41 | input [15:0] address_in, 42 | input ctl_advance, 43 | input ctl_load, 44 | input clock, 45 | 46 | input ready, 47 | 48 | output [15:0] address_out 49 | ); 50 | 51 | logic [15:0] address_stored = 0; 52 | 53 | assign address_out = ctl_load ? address_in : address_stored; 54 | 55 | always_ff@(negedge clock) begin 56 | if( ready ) begin 57 | if( ctl_advance ) 58 | address_stored <= address_out + 1; 59 | else 60 | address_stored <= address_out; 61 | end 62 | end 63 | 64 | endmodule 65 | -------------------------------------------------------------------------------- /sar6502.srcs/sources_1/new/register.sv: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: Some Assembly Required 4 | // Engineer: Shachar Shemesh 5 | // 6 | // Create Date: 02/23/2022 05:55:53 AM 7 | // Design Name: sar6502 8 | // Module Name: register 9 | // Project Name: CompuSAR 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 8 bit register, falling edge latch 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | // License: 21 | // Copyright (C) 2022. 22 | // Copyright owners listed in AUTHORS file. 23 | // 24 | // This program is free software; you can redistribute it and/or modify 25 | // it under the terms of the GNU General Public License as published by 26 | // the Free Software Foundation; either version 2 of the License, or 27 | // (at your option) any later version. 28 | // 29 | // This program is distributed in the hope that it will be useful, 30 | // but WITHOUT ANY WARRANTY; without even the implied warranty of 31 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 32 | // GNU General Public License for more details. 33 | // 34 | // You should have received a copy of the GNU General Public License 35 | // along with this program; if not, write to the Free Software 36 | // Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA 37 | // 38 | ////////////////////////////////////////////////////////////////////////////////// 39 | 40 | 41 | module register( 42 | input [7:0]data_in, 43 | input latch, 44 | input clock, 45 | 46 | input ready, 47 | 48 | output reg [7:0]data_out = 0 49 | ); 50 | 51 | always_ff@(negedge clock) 52 | begin 53 | if( latch && ready ) 54 | data_out <= data_in; 55 | end 56 | 57 | endmodule 58 | -------------------------------------------------------------------------------- /sar6502.srcs/sources_1/new/sar6502.sv: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: Some Assembly Required 4 | // Engineer: Shachar Shemesh 5 | // 6 | // Create Date: 02/23/2022 05:40:43 AM 7 | // Design Name: sar6502 8 | // Module Name: sar6502 9 | // Project Name: CompuSAR 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: Customizable implementation of the 6502 CPU 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | // License: 21 | // Copyright (C) 2022. 22 | // Copyright owners listed in AUTHORS file. 23 | // 24 | // This program is free software; you can redistribute it and/or modify 25 | // it under the terms of the GNU General Public License as published by 26 | // the Free Software Foundation; either version 2 of the License, or 27 | // (at your option) any later version. 28 | // 29 | // This program is distributed in the hope that it will be useful, 30 | // but WITHOUT ANY WARRANTY; without even the implied warranty of 31 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 32 | // GNU General Public License for more details. 33 | // 34 | // You should have received a copy of the GNU General Public License 35 | // along with this program; if not, write to the Free Software 36 | // Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA 37 | // 38 | ////////////////////////////////////////////////////////////////////////////////// 39 | 40 | module sar6502#(parameter CPU_VARIANT = 0) 41 | ( 42 | input phi2, 43 | input [7:0] data_in, 44 | input RES, 45 | input rdy, 46 | input IRQ, 47 | input NMI, 48 | input SO, 49 | output [15:0] address, 50 | output [7:0] data_out, 51 | output rW, 52 | output VP, 53 | output ML, 54 | output sync, 55 | 56 | output incompatible // Address bus is deliberately incompatible with our base CPU 57 | ); 58 | 59 | // Input latches 60 | logic [7:0] data_in_l; 61 | logic RESET_L; 62 | logic IRQ_L; 63 | logic NMI_L; 64 | logic SO_L; 65 | logic [15:0]pc_value, prev_pc_value; 66 | logic [7:0]alu_result, alu_result_latched; 67 | 68 | // Control 69 | logic ctrl_signals[control_signals::ctrl_signals_last:0]; 70 | 71 | // Buses 72 | logic [7:0]data_bus; 73 | logic [7:0]data_bus_inputs[bus_sources::DataBusSourceCtlLast:0]; 74 | bus_sources::DataBusSourceCtl data_bus_source; 75 | assign data_bus = data_bus_inputs[data_bus_source]; 76 | assign data_out = data_bus; 77 | 78 | logic [7:0]address_bus_low; 79 | logic [7:0]address_bus_low_inputs[bus_sources::AddressBusLowSourceCtlLast:0]; 80 | bus_sources::AddressBusLowSourceCtl address_bus_low_source; 81 | 82 | logic [7:0]address_bus_high; 83 | logic [7:0]address_bus_high_inputs[bus_sources::AddressBusHighSourceCtlLast:0]; 84 | bus_sources::AddressBusHighSourceCtl address_bus_high_source; 85 | 86 | assign address = { address_bus_high_inputs[address_bus_high_source], address_bus_low_inputs[address_bus_low_source] }; 87 | 88 | logic [7:0]alu_a_inputs[bus_sources::AluASourceCtlLast:0]; 89 | bus_sources::AluASourceCtl alu_a_source; 90 | logic [7:0]alu_b_inputs[bus_sources::AluBSourceCtlLast:0]; 91 | bus_sources::AluBSourceCtl alu_b_source; 92 | 93 | logic alu_carry_inputs[bus_sources::AluCarrySourceCtlLast:0]; 94 | bus_sources::AluCarrySourceCtl alu_carry_source; 95 | control_signals::alu_control alu_control; 96 | logic alu_carry, alu_overflow; 97 | logic alu_carry_latched; 98 | 99 | alu alu( .a(alu_a_inputs[alu_a_source]), .b(alu_b_inputs[alu_b_source]), 100 | .carry_in(alu_carry_inputs[alu_carry_source]), 101 | .inverse_b(ctrl_signals[control_signals::AluBInverse]), 102 | .control(alu_control), .result(alu_result), .carry_out(alu_carry), .overflow_out(alu_overflow) ); 103 | 104 | // Registers 105 | register register_a(.data_in(data_bus), .clock(phi2), .ready(rdy), .latch(ctrl_signals[control_signals::LOAD_A]), 106 | .data_out(data_bus_inputs[bus_sources::DataBusSrc_A])); 107 | register register_x(.data_in(data_bus), .clock(phi2), .ready(rdy), .latch(ctrl_signals[control_signals::LOAD_X]), 108 | .data_out(data_bus_inputs[bus_sources::DataBusSrc_X])); 109 | register register_y(.data_in(data_bus), .clock(phi2), .ready(rdy), .latch(ctrl_signals[control_signals::LOAD_Y]), 110 | .data_out(data_bus_inputs[bus_sources::DataBusSrc_Y])); 111 | 112 | logic [7:0]stack_pointer_inputs[bus_sources::StackPointerSourceCtlLast : 0]; 113 | bus_sources::StackPointerSourceCtl stack_pointer_source; 114 | register register_stack( 115 | .data_in(stack_pointer_inputs[stack_pointer_source]), 116 | .clock(phi2), 117 | .ready(rdy), 118 | .latch(ctrl_signals[control_signals::LOAD_SP]), 119 | .data_out(data_bus_inputs[bus_sources::DataBusSrc_SP])); 120 | 121 | logic [7:0]status_value; 122 | status_register register_p(.data_in(data_bus), .data_out(status_value), .clock(phi2), 123 | .alu_carry(alu_carry), 124 | .alu_overflow(alu_overflow), 125 | .use_alu_flags(ctrl_signals[control_signals::UseAluFlags]), .calculate_zero(ctrl_signals[control_signals::CalculateFlagZ]), 126 | .update_c(ctrl_signals[control_signals::UpdateFlagC]), 127 | .update_z(ctrl_signals[control_signals::UpdateFlagZ]), 128 | .update_i(ctrl_signals[control_signals::UpdateFlagI]), 129 | .update_d(ctrl_signals[control_signals::UpdateFlagD]), 130 | .output_b(ctrl_signals[control_signals::OutputFlagB]), 131 | .update_v(ctrl_signals[control_signals::UpdateFlagV]), 132 | .update_n(ctrl_signals[control_signals::UpdateFlagN]), 133 | .ready(rdy), .so(SO_L) 134 | ); 135 | 136 | logic [15:0]data_latch_value; 137 | bus_sources::DataLatchLowSourceCtl data_latch_low_source; 138 | logic [7:0]data_latch_low_inputs[bus_sources::DataLatchLowSourceCtlLast : 0]; 139 | bus_sources::DataLatchHighSourceCtl data_latch_high_source; 140 | logic [7:0]data_latch_high_inputs[bus_sources::DataLatchHighSourceCtlLast : 0]; 141 | 142 | register data_latch_low( .data_in(data_latch_low_inputs[data_latch_low_source]), 143 | .clock(phi2), .ready(rdy), .latch(ctrl_signals[control_signals::LOAD_DataLow]), 144 | .data_out(data_latch_value[7:0])); 145 | register data_latch_high( .data_in(data_latch_high_inputs[data_latch_high_source]), 146 | .clock(phi2), .ready(rdy), .latch(ctrl_signals[control_signals::LOAD_DataHigh]), 147 | .data_out(data_latch_value[15:8])); 148 | 149 | bus_sources::PcLowSourceCtl pc_low_source; 150 | logic [7:0]pc_low_inputs[bus_sources::PcLowSourceCtlLast : 0]; 151 | 152 | bus_sources::PcHighSourceCtl pc_high_source; 153 | logic [7:0]pc_high_inputs[bus_sources::PcHighSourceCtlLast : 0]; 154 | 155 | program_counter register_pc( 156 | .address_in({pc_high_inputs[pc_high_source], pc_low_inputs[pc_low_source]}), 157 | .ctl_advance(ctrl_signals[control_signals::PC_ADVANCE]), 158 | .ctl_load(ctrl_signals[control_signals::PC_LOAD]), .clock(phi2), .ready(rdy), 159 | .address_out(pc_value)); 160 | 161 | decoder#(.CPU_VARIANT(CPU_VARIANT)) decoder( 162 | .memory_in(data_in_l), 163 | .status( status_value ), 164 | .alu_carry( alu_carry_latched ), 165 | .clock(phi2), 166 | .RESET(RESET_L), 167 | .IRQ(IRQ_L), 168 | .NMI(NMI_L), 169 | 170 | .ready(rdy), 171 | 172 | .address_bus_low_source( address_bus_low_source ), 173 | .address_bus_high_source( address_bus_high_source ), 174 | .data_bus_source( data_bus_source ), 175 | .pc_low_source( pc_low_source ), 176 | .pc_high_source( pc_high_source ), 177 | .data_latch_low_source( data_latch_low_source ), 178 | .data_latch_high_source( data_latch_high_source ), 179 | .stack_pointer_source( stack_pointer_source ), 180 | .alu_op(alu_control), 181 | .alu_a_source(alu_a_source), 182 | .alu_b_source(alu_b_source), 183 | .alu_carry_source(alu_carry_source), 184 | .ctrl_signals( ctrl_signals ), 185 | 186 | .rW( rW ), 187 | .sync( sync ), 188 | .ML( ML ), 189 | .VP( VP ), 190 | .incompatible( incompatible ) 191 | ); 192 | 193 | // Assign the rest of the bus inputs 194 | assign data_bus_inputs[bus_sources::DataBusSrc_Zero] = 8'b0; 195 | assign data_bus_inputs[bus_sources::DataBusSrc_Ones] = 8'hff; 196 | assign data_bus_inputs[bus_sources::DataBusSrc_Status] = status_value; 197 | assign data_bus_inputs[bus_sources::DataBusSrc_Alu] = alu_result; 198 | assign data_bus_inputs[bus_sources::DataBusSrc_Alu_Latched] = alu_result_latched; 199 | assign data_bus_inputs[bus_sources::DataBusSrc_Pc_Low] = pc_value[7:0]; 200 | assign data_bus_inputs[bus_sources::DataBusSrc_Pc_High] = pc_value[15:8]; 201 | assign data_bus_inputs[bus_sources::DataBusSrc_Dl_Low] = data_latch_value[7:0]; 202 | assign data_bus_inputs[bus_sources::DataBusSrc_Mem] = data_in_l; 203 | assign data_bus_inputs[bus_sources::DataBusSrc_Mem_Unlatched] = data_in; 204 | 205 | assign address_bus_low_inputs[bus_sources::AddrBusLowSrc_Mem] = data_in_l; 206 | assign address_bus_low_inputs[bus_sources::AddrBusLowSrc_Alu] = alu_result_latched; 207 | assign address_bus_low_inputs[bus_sources::AddrBusLowSrc_SP] = data_bus_inputs[bus_sources::DataBusSrc_SP]; 208 | assign address_bus_low_inputs[bus_sources::AddrBusLowSrc_PC] = pc_value[7:0]; 209 | assign address_bus_low_inputs[bus_sources::AddrBusLowSrc_DataLatch] = data_latch_value[7:0]; 210 | assign address_bus_low_inputs[bus_sources::AddrBusLowSrc_DataLatch_High] = data_latch_value[15:8]; 211 | 212 | assign address_bus_high_inputs[bus_sources::AddrBusHighSrc_Zero] = 8'b0; 213 | assign address_bus_high_inputs[bus_sources::AddrBusHighSrc_One] = 8'b1; 214 | assign address_bus_high_inputs[bus_sources::AddrBusHighSrc_Mem] = data_in_l; 215 | assign address_bus_high_inputs[bus_sources::AddrBusHighSrc_Alu] = alu_result_latched; 216 | assign address_bus_high_inputs[bus_sources::AddrBusHighSrc_Alu_Unlatched] = alu_result; 217 | assign address_bus_high_inputs[bus_sources::AddrBusHighSrc_PC] = pc_value[15:8]; 218 | assign address_bus_high_inputs[bus_sources::AddrBusHighSrc_DataLatch] = data_latch_value[15:8]; 219 | 220 | assign pc_low_inputs[bus_sources::PcLowSource_CurrentValue] = prev_pc_value[7:0]; 221 | assign pc_low_inputs[bus_sources::PcLowSource_Mem] = data_in_l; 222 | assign pc_low_inputs[bus_sources::PcLowSource_Dl] = data_latch_value[7:0]; 223 | 224 | assign pc_high_inputs[bus_sources::PcHighSource_CurrentValue] = prev_pc_value[15:8]; 225 | assign pc_high_inputs[bus_sources::PcHighSource_Mem] = data_in_l; 226 | assign pc_high_inputs[bus_sources::PcHighSource_Dl] = data_latch_value[15:8]; 227 | assign pc_high_inputs[bus_sources::PcHighSource_Alu_Latched] = alu_result_latched; 228 | 229 | assign data_latch_low_inputs[bus_sources::DataLatchLowSource_Mem] = data_in_l; 230 | assign data_latch_low_inputs[bus_sources::DataLatchLowSource_Alu] = alu_result; 231 | assign data_latch_low_inputs[bus_sources::DataLatchLowSource_Alu_Latched] = alu_result_latched; 232 | assign data_latch_low_inputs[bus_sources::DataLatchLowSource_PC] = pc_value[7:0]; 233 | assign data_latch_low_inputs[bus_sources::DataLatchLowSource_FA] = 8'hfa; 234 | assign data_latch_low_inputs[bus_sources::DataLatchLowSource_FC] = 8'hfc; 235 | assign data_latch_low_inputs[bus_sources::DataLatchLowSource_FE] = 8'hfe; 236 | 237 | assign data_latch_high_inputs[bus_sources::DataLatchHighSource_Zero] = 8'h00; 238 | assign data_latch_high_inputs[bus_sources::DataLatchHighSource_Mem] = data_in_l; 239 | assign data_latch_high_inputs[bus_sources::DataLatchHighSource_Alu] = alu_result; 240 | assign data_latch_high_inputs[bus_sources::DataLatchHighSource_Alu_Latched] = alu_result_latched; 241 | assign data_latch_high_inputs[bus_sources::DataLatchHighSource_PC] = pc_value[15:8]; 242 | assign data_latch_high_inputs[bus_sources::DataLatchHighSource_FF] = 8'hff; 243 | 244 | assign stack_pointer_inputs[bus_sources::StackPointerSource_Alu] = alu_result; 245 | assign stack_pointer_inputs[bus_sources::StackPointerSource_DataBus] = data_bus; 246 | 247 | assign alu_a_inputs[bus_sources::AluASourceCtl_Zero] = 0; 248 | assign alu_a_inputs[bus_sources::AluASourceCtl_A] = data_bus_inputs[bus_sources::DataBusSrc_A]; 249 | assign alu_a_inputs[bus_sources::AluASourceCtl_X] = data_bus_inputs[bus_sources::DataBusSrc_X]; 250 | assign alu_a_inputs[bus_sources::AluASourceCtl_Y] = data_bus_inputs[bus_sources::DataBusSrc_Y]; 251 | assign alu_a_inputs[bus_sources::AluASourceCtl_DataLatchLow] = data_latch_value[7:0]; 252 | assign alu_a_inputs[bus_sources::AluASourceCtl_DataLatchHigh] = data_latch_value[15:8]; 253 | assign alu_a_inputs[bus_sources::AluASourceCtl_SP] = data_bus_inputs[bus_sources::DataBusSrc_SP]; 254 | assign alu_a_inputs[bus_sources::AluASourceCtl_PC_Low] = pc_value[7:0]; 255 | assign alu_a_inputs[bus_sources::AluASourceCtl_PC_High] = pc_value[15:8]; 256 | assign alu_a_inputs[bus_sources::AluASourceCtl_Mem] = data_in_l; 257 | assign alu_a_inputs[bus_sources::AluASourceCtl_Alu] = alu_result_latched; 258 | 259 | assign alu_b_inputs[bus_sources::AluBSourceCtl_Zero] = 8'b0; 260 | assign alu_b_inputs[bus_sources::AluBSourceCtl_Bit0] = 8'b0000_0001; 261 | assign alu_b_inputs[bus_sources::AluBSourceCtl_Bit1] = 8'b0000_0010; 262 | assign alu_b_inputs[bus_sources::AluBSourceCtl_Bit2] = 8'b0000_0100; 263 | assign alu_b_inputs[bus_sources::AluBSourceCtl_Bit3] = 8'b0000_1000; 264 | assign alu_b_inputs[bus_sources::AluBSourceCtl_Bit4] = 8'b0001_0000; 265 | assign alu_b_inputs[bus_sources::AluBSourceCtl_Bit5] = 8'b0010_0000; 266 | assign alu_b_inputs[bus_sources::AluBSourceCtl_Bit6] = 8'b0100_0000; 267 | assign alu_b_inputs[bus_sources::AluBSourceCtl_Bit7] = 8'b1000_0000; 268 | assign alu_b_inputs[bus_sources::AluBSourceCtl_Mem] = data_in_l; 269 | assign alu_b_inputs[bus_sources::AluBSourceCtl_A] = data_bus_inputs[bus_sources::DataBusSrc_A]; 270 | 271 | assign alu_carry_inputs[bus_sources::AluCarrySource_Zero] = 0; 272 | assign alu_carry_inputs[bus_sources::AluCarrySource_One] = 1; 273 | assign alu_carry_inputs[bus_sources::AluCarrySource_Carry] = 274 | data_bus_inputs[bus_sources::DataBusSrc_Status][control_signals::FlagsCarry]; 275 | 276 | always_ff@(negedge phi2) begin 277 | RESET_L <= RES; 278 | 279 | if( rdy ) begin 280 | data_in_l <= data_in; 281 | IRQ_L <= IRQ; 282 | NMI_L <= NMI; 283 | SO_L <= SO; 284 | prev_pc_value <= pc_value; 285 | alu_result_latched <= alu_result; 286 | alu_carry_latched <= alu_carry; 287 | end 288 | end 289 | 290 | endmodule 291 | -------------------------------------------------------------------------------- /sar6502.srcs/sources_1/new/status_register.sv: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: Some Assembly Required 4 | // Engineer: Shachar Shemesh 5 | // 6 | // Create Date: 02/26/2022 07:38:22 PM 7 | // Design Name: sar6502 8 | // Module Name: status_register 9 | // Project Name: CompuSAR 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 6502 flags register 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | // License: 21 | // Copyright (C) 2022. 22 | // Copyright owners listed in AUTHORS file. 23 | // 24 | // This program is free software; you can redistribute it and/or modify 25 | // it under the terms of the GNU General Public License as published by 26 | // the Free Software Foundation; either version 2 of the License, or 27 | // (at your option) any later version. 28 | // 29 | // This program is distributed in the hope that it will be useful, 30 | // but WITHOUT ANY WARRANTY; without even the implied warranty of 31 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 32 | // GNU General Public License for more details. 33 | // 34 | // You should have received a copy of the GNU General Public License 35 | // along with this program; if not, write to the Free Software 36 | // Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA 37 | // 38 | ////////////////////////////////////////////////////////////////////////////////// 39 | 40 | 41 | module status_register( 42 | input [7:0] data_in, 43 | output [7:0]data_out, 44 | input clock, 45 | input alu_carry, 46 | input alu_overflow, 47 | 48 | input update_c, 49 | input update_z, 50 | input update_i, 51 | input update_d, 52 | input output_b, 53 | input update_v, 54 | input update_n, 55 | 56 | input use_alu_flags, 57 | input calculate_zero, 58 | 59 | input ready, 60 | input so 61 | ); 62 | 63 | logic negative, overflow, decimal, irq_mask, zero, carry; 64 | logic prev_so = 0; 65 | 66 | assign data_out = { negative, overflow, 1'b1, output_b, decimal, irq_mask, zero, carry }; 67 | 68 | always_ff@(negedge clock) 69 | begin 70 | if( ready ) begin 71 | if( update_n ) 72 | negative <= data_in[7]; 73 | if( update_v ) 74 | overflow <= use_alu_flags ? alu_overflow : data_in[6]; 75 | if( update_d ) 76 | decimal <= data_in[3]; 77 | if( update_i ) 78 | irq_mask <= data_in[2]; 79 | if( update_z ) begin 80 | if( calculate_zero ) 81 | zero <= data_in==0 ? 1 : 0; 82 | else 83 | zero <= data_in[1]; 84 | end 85 | if( update_c ) 86 | carry <= use_alu_flags ? alu_carry : data_in[0]; 87 | end 88 | 89 | if( prev_so==1 && so==0 ) 90 | overflow <= 1; 91 | 92 | prev_so <= so; 93 | end 94 | 95 | endmodule 96 | -------------------------------------------------------------------------------- /sar6502.srcs/utils_1/imports/synth_1/.gitignore: -------------------------------------------------------------------------------- 1 | /*.dcp 2 | -------------------------------------------------------------------------------- /sar6502.xpr: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 88 | 89 | 90 | 91 | 92 | 93 | 94 | 95 | 96 | 97 | 98 | 99 | 100 | 101 | 102 | 103 | 104 | 105 | 106 | 107 | 108 | 109 | 110 | 111 | 112 | 113 | 114 | 115 | 116 | 117 | 118 | 119 | 120 | 121 | 122 | 123 | 124 | 125 | 126 | 127 | 128 | 129 | 130 | 131 | 132 | 133 | 134 | 135 | 136 | 137 | 138 | 139 | 140 | 141 | 142 | 143 | 144 | 145 | 146 | 147 | 148 | 152 | 153 | 154 | 155 | 156 | 157 | 158 | 159 | 160 | 161 | 162 | 163 | 164 | 165 | 166 | 167 | 168 | 169 | 170 | 171 | 172 | 173 | 174 | 175 | 176 | 177 | 178 | 179 | 180 | 194 | 195 | 196 | 197 | 198 | 199 | 200 | 201 | 202 | 203 | 204 | 205 | 206 | 207 | 208 | 209 | 210 | 211 | 212 | 213 | 214 | 216 | 217 | 218 | 219 | 220 | 221 | 222 | 223 | 224 | 225 | 228 | 229 | 230 | 231 | 232 | 235 | 236 | 238 | 239 | 241 | 242 | 244 | 245 | 247 | 248 | 250 | 251 | 252 | 253 | 254 | 255 | 256 | 257 | 258 | 259 | 260 | 261 | 262 | 263 | 264 | 265 | 266 | 267 | 268 | 269 | 270 | 271 | 272 | 273 | 274 | 275 | 276 | 277 | 278 | 279 | 280 | 281 | 282 | 283 | 284 | 285 | 286 | 287 | 288 | 289 | 290 | 291 | 292 | 293 | 294 | 295 | 296 | 297 | 298 | 299 | 300 | 301 | 302 | 303 | 304 | 305 | 306 | 307 | default_dashboard 308 | 309 | 310 | 311 | --------------------------------------------------------------------------------