├── .gitignore ├── docs ├── pulse_wave_0.png ├── pulse_wave_1.png └── pulse_wave_1_real.png ├── shell ├── switch_level.v ├── registered_output.v ├── sync_chain.v ├── button_pulse.v ├── debouncer.v ├── driver_74lv595.v ├── driver_74lv165.v └── hardware_top.v ├── include ├── S011HD1P_X32Y2D128.v ├── README.md └── S011HD1P_X32Y2D128_BW.v ├── README.md └── core ├── start_reg.v ├── select_reg.v ├── memory_fpga.v ├── operator.v ├── arith_unit.v ├── pulse_unit.v ├── memory_asic.v ├── io_unit.v ├── arith_ctrl.v └── core_top.v /.gitignore: -------------------------------------------------------------------------------- 1 | .vscode -------------------------------------------------------------------------------- /docs/pulse_wave_0.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Computer-103/hardware/HEAD/docs/pulse_wave_0.png -------------------------------------------------------------------------------- /docs/pulse_wave_1.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Computer-103/hardware/HEAD/docs/pulse_wave_1.png -------------------------------------------------------------------------------- /docs/pulse_wave_1_real.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Computer-103/hardware/HEAD/docs/pulse_wave_1_real.png -------------------------------------------------------------------------------- /shell/switch_level.v: -------------------------------------------------------------------------------- 1 | module switch_level ( 2 | input clk, 3 | input resetn, 4 | 5 | input sw, // switch 6 | output level // level 7 | ); 8 | 9 | debouncer sw_debouncer ( 10 | .clk (clk), 11 | .resetn (resetn), 12 | .original_sig (sw), 13 | .debounced_sig (level) 14 | ); 15 | 16 | endmodule 17 | -------------------------------------------------------------------------------- /shell/registered_output.v: -------------------------------------------------------------------------------- 1 | module registered_output #( 2 | parameter width = 1 3 | ) ( 4 | input clk, 5 | input resetn, 6 | input [width - 1:0] output_sig, 7 | output [width - 1:0] registered_sig 8 | ); 9 | 10 | reg [width - 1:0] ff; 11 | 12 | always @ (posedge clk) begin 13 | if (~resetn) begin 14 | ff <= 0; 15 | end else begin 16 | ff <= output_sig; 17 | end 18 | end 19 | 20 | assign registered_sig = ff; 21 | 22 | endmodule 23 | -------------------------------------------------------------------------------- /include/S011HD1P_X32Y2D128.v: -------------------------------------------------------------------------------- 1 | module S011HD1P_X32Y2D128( 2 | Q, CLK, CEN, WEN, A, D 3 | ); 4 | parameter Bits = 128; 5 | parameter Word_Depth = 64; 6 | parameter Add_Width = 6; 7 | 8 | output reg [Bits-1:0] Q; 9 | input CLK; 10 | input CEN; 11 | input WEN; 12 | input [Add_Width-1:0] A; 13 | input [Bits-1:0] D; 14 | 15 | reg [Bits-1:0] ram [0:Word_Depth-1]; 16 | always @(posedge CLK) begin 17 | if(!CEN && !WEN) begin 18 | ram[A] <= D; 19 | end 20 | Q <= !CEN && WEN ? ram[A] : {4{$random}}; 21 | end 22 | 23 | endmodule 24 | -------------------------------------------------------------------------------- /shell/sync_chain.v: -------------------------------------------------------------------------------- 1 | module sync_chain #( 2 | parameter width = 1 3 | ) ( 4 | input clk, 5 | input resetn, 6 | input [width - 1:0] input_sig, 7 | output [width - 1:0] sync_sig 8 | ); 9 | 10 | reg [width - 1:0] ff_1; 11 | reg [width - 1:0] ff_2; 12 | reg [width - 1:0] ff_3; 13 | 14 | always @ (posedge clk) begin 15 | if (~resetn) begin 16 | ff_1 <= 0; 17 | ff_2 <= 0; 18 | ff_3 <= 0; 19 | end else begin 20 | ff_1 <= input_sig; 21 | ff_2 <= ff_1; 22 | ff_3 <= ff_2; 23 | end 24 | end 25 | 26 | assign sync_sig = ff_3; 27 | 28 | endmodule 29 | -------------------------------------------------------------------------------- /shell/button_pulse.v: -------------------------------------------------------------------------------- 1 | module button_pulse ( 2 | input clk, 3 | input resetn, 4 | 5 | input btn, // button 6 | output pulse // pulse 7 | ); 8 | 9 | wire btn_now; 10 | 11 | debouncer sw_debouncer ( 12 | .clk (clk), 13 | .resetn (resetn), 14 | .original_sig (btn), 15 | .debounced_sig (btn_now) 16 | ); 17 | 18 | reg btn_last; 19 | reg pulse_r; 20 | 21 | always @(posedge clk) begin 22 | if (~resetn) begin 23 | btn_last <= 1'b0; 24 | pulse_r <= 1'b0; 25 | end else begin 26 | btn_last <= btn_now; 27 | pulse_r <= btn_last && !btn_now; 28 | end 29 | end 30 | 31 | assign pulse = pulse_r; 32 | 33 | endmodule 34 | -------------------------------------------------------------------------------- /include/README.md: -------------------------------------------------------------------------------- 1 | 2 | ## 接口与流片用RAM一致的简化行为模型 3 | 4 | ### 不带写掩码的128bitx64单口RAM 5 | 6 | 文件名为`S011HD1P_X32Y2D128.v`. 7 | 8 | | 端口 | 说明 | 9 | | --- | --- | 10 | | output [127:0] Q | 读数据 | 11 | | input CLK | 时钟 | 12 | | input CEN | 使能信号, 低电平有效 | 13 | | input WEN | 写使能信号, 低电平有效 | 14 | | input [5:0] A | 读写地址 | 15 | | input [127:0] D | 写数据 | 16 | 17 | ### 带写掩码的128bitx64单口RAM 18 | 19 | 文件名为`S011HD1P_X32Y2D128_BW.v`. 20 | 21 | | 端口 | 说明 | 22 | | --- | --- | 23 | | output [127:0] Q | 读数据 | 24 | | input CLK | 时钟 | 25 | | input CEN | 使能信号, 低电平有效 | 26 | | input WEN | 写使能信号, 低电平有效 | 27 | | input [127:0] BWEN | 写掩码信号, 掩码粒度为1bit, 低电平有效 | 28 | | input [5:0] A | 读写地址 | 29 | | input [127:0] D | 写数据 | 30 | -------------------------------------------------------------------------------- /include/S011HD1P_X32Y2D128_BW.v: -------------------------------------------------------------------------------- 1 | module S011HD1P_X32Y2D128_BW( 2 | Q, CLK, CEN, WEN, BWEN, A, D 3 | ); 4 | parameter Bits = 128; 5 | parameter Word_Depth = 64; 6 | parameter Add_Width = 6; 7 | parameter Wen_Width = 128; 8 | 9 | output reg [Bits-1:0] Q; 10 | input CLK; 11 | input CEN; 12 | input WEN; 13 | input [Wen_Width-1:0] BWEN; 14 | input [Add_Width-1:0] A; 15 | input [Bits-1:0] D; 16 | 17 | wire cen = ~CEN; 18 | wire wen = ~WEN; 19 | wire [Wen_Width-1:0] bwen = ~BWEN; 20 | 21 | reg [Bits-1:0] ram [0:Word_Depth-1]; 22 | always @(posedge CLK) begin 23 | if(cen && wen) begin 24 | ram[A] <= (D & bwen) | (ram[A] & ~bwen); 25 | end 26 | Q <= cen && !wen ? ram[A] : {4{$random}}; 27 | end 28 | 29 | endmodule 30 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # 103 计算机 现代硬件电路源码 2 | 3 | ``` 4 | . 5 | ├── README.md # 说明文档 6 | ├── core # 内核部分电路 7 | │ ├── core_top.v # 内核部分顶层模块 8 | │ ├── arith_unit.v # 运算器 АУ 9 | │ ├── arith_ctrl.v # 局部程序发送器 МПД 10 | │ ├── operator.v # 操作器 БО 11 | │ ├── start_reg.v # 启动寄存器 ПР 12 | │ ├── select_reg.v # 选择寄存器 СР 13 | │ ├── pulse_unit.v # 脉冲分配器 РИ 14 | │ ├── memory.v # 存贮器 ЗУ & МП 15 | │ └── io_unit.v # 输入输出电子部件 ЭУВВ 16 | ├── shell # 外壳部分电路 17 | │ ├── shell_top.v # 外壳部分顶层模块 18 | │ ├── driver_74lv165.v # 74LV165 串行输入驱动模块 19 | │ ├── driver_74lv595.v # 74LV595 串行输出驱动模块 20 | │ ├── button_pulse.v # 按钮-脉冲信号 21 | │ └── switch_level.v # 开关-电平信号 22 | ├── include # 涉及的外部模块 23 | └── docs # 文档 24 | ``` -------------------------------------------------------------------------------- /core/start_reg.v: -------------------------------------------------------------------------------- 1 | /** 2 | * ПР 3 | * пускового регистра 4 | * 启动寄存器 5 | **/ 6 | 7 | module start_reg ( 8 | input clk, 9 | input resetn, 10 | 11 | input do_arr_strt_from_pnl, 12 | input [11:0] arr_strt_data_from_pnl, 13 | 14 | input do_inc_strt_from_pu, 15 | 16 | input do_sel_to_strt_from_pu, 17 | input [11:0] sel_value_from_sel, 18 | 19 | input [11:0] cmp_value_from_pnl, 20 | output cmp_match_to_io, 21 | 22 | output [11:0] strt_value_to_sel, 23 | output [11:0] strt_value_to_pnl 24 | ); 25 | 26 | reg [11:0] reg_start; 27 | 28 | always @(posedge clk) begin 29 | if (~resetn) begin 30 | reg_start <= 0; 31 | end else if (do_arr_strt_from_pnl) begin 32 | reg_start <= arr_strt_data_from_pnl; 33 | end else if (do_inc_strt_from_pu) begin 34 | reg_start <= reg_start + 12'o1; 35 | end else if (do_sel_to_strt_from_pu) begin 36 | reg_start <= sel_value_from_sel; 37 | end 38 | end 39 | 40 | assign strt_value_to_sel = reg_start; 41 | assign strt_value_to_pnl = reg_start; 42 | 43 | assign cmp_match_to_io = 44 | reg_start == cmp_value_from_pnl; 45 | 46 | endmodule 47 | -------------------------------------------------------------------------------- /shell/debouncer.v: -------------------------------------------------------------------------------- 1 | module debouncer # ( 2 | parameter cnt_depth = 1048576 3 | ) ( 4 | input clk, 5 | input resetn, 6 | 7 | input original_sig, // original signal 8 | output debounced_sig // debounced signal 9 | ); 10 | 11 | localparam cnt_width = $clog2(cnt_depth); 12 | 13 | reg [cnt_width:0] counter; 14 | 15 | reg reg_sig; 16 | always @(posedge clk) begin 17 | if (~resetn) begin 18 | reg_sig <= 1'b0; 19 | end else if (counter == cnt_depth - 1) begin 20 | reg_sig <= original_sig; 21 | end 22 | end 23 | assign debounced_sig = reg_sig; 24 | 25 | // way 1 26 | always @(posedge clk) begin 27 | if (~resetn) begin 28 | counter <= 0; 29 | end else if (reg_sig != original_sig) begin 30 | if (counter != cnt_depth - 1) begin 31 | counter <= counter + 1; 32 | end 33 | end else begin 34 | counter <= 0; 35 | end 36 | end 37 | 38 | // way 2 39 | // always @(posedge clk) begin 40 | // if (~resetn) begin 41 | // counter <= 0; 42 | // end else if (counter == 0) begin 43 | // if (reg_sig != original_sig) begin 44 | // counter <= 1; 45 | // end 46 | // end else begin 47 | // if (counter == cnt_depth - 1) begin 48 | // counter <= 0; 49 | // end else begin 50 | // counter <= counter + 1; 51 | // end 52 | // end 53 | // end 54 | 55 | endmodule 56 | -------------------------------------------------------------------------------- /core/select_reg.v: -------------------------------------------------------------------------------- 1 | /** 2 | * СР 3 | * селекционного регистра 4 | * 选择寄存器 5 | **/ 6 | 7 | module select_reg ( 8 | input clk, 9 | input resetn, 10 | 11 | input do_arr_sel_from_pnl, 12 | input [11:0] arr_sel_data_from_pnl, 13 | 14 | input do_strt_to_sel_from_pu, 15 | input [11:0] strt_value_from_strt, 16 | 17 | input do_addr1_to_sel_from_pu, 18 | input [11:0] addr1_value_from_au, 19 | 20 | input [11:0] cmp_value_from_pnl, 21 | output cmp_match_to_io, 22 | 23 | input do_addr2_to_sel_from_pu, 24 | input do_addr2_to_sel_from_io, 25 | input [11:0] addr2_value_from_au, 26 | 27 | output [11:0] sel_value_to_strt, 28 | output [11:0] sel_value_to_mem, 29 | output [11:0] sel_value_to_pnl 30 | ); 31 | 32 | reg [11:0] reg_select; 33 | 34 | always @(posedge clk) begin 35 | if (~resetn) begin 36 | reg_select <= 12'o0000; 37 | end else if (do_arr_sel_from_pnl) begin 38 | reg_select <= arr_sel_data_from_pnl; 39 | end else if (do_strt_to_sel_from_pu) begin 40 | reg_select <= strt_value_from_strt; 41 | end else if (do_addr1_to_sel_from_pu) begin 42 | reg_select <= addr1_value_from_au; 43 | end else if (do_addr2_to_sel_from_pu || do_addr2_to_sel_from_io) begin 44 | reg_select <= addr2_value_from_au; 45 | end 46 | end 47 | 48 | assign sel_value_to_strt = reg_select; 49 | assign sel_value_to_mem = reg_select; 50 | assign sel_value_to_pnl = reg_select; 51 | 52 | assign cmp_match_to_io = 53 | reg_select == cmp_value_from_pnl; 54 | 55 | endmodule 56 | -------------------------------------------------------------------------------- /shell/driver_74lv595.v: -------------------------------------------------------------------------------- 1 | module driver_74lv595 ( 2 | input clk, 3 | input resetn, 4 | 5 | input [31:0] data_0, 6 | input [31:0] data_1, 7 | 8 | output RCLK, // storage register clock 9 | output SRCLK, // shift register clock 10 | 11 | output SER_0, // serial output 12 | output SER_1 // serial output 13 | ); 14 | 15 | reg serial_clk; 16 | reg shift_clk; 17 | reg store_clk; 18 | 19 | reg [ 5:0] cnt; 20 | 21 | reg [31:0] data_0_r; 22 | reg [31:0] data_1_r; 23 | 24 | always @(posedge clk) begin 25 | if (~resetn) begin 26 | serial_clk <= 1'b0; 27 | end else begin 28 | serial_clk <= ~serial_clk; 29 | end 30 | end 31 | 32 | always @(posedge clk) begin 33 | if (~resetn) begin 34 | cnt <= 6'd0; 35 | end else if (!serial_clk) begin 36 | if (cnt == 6'd32) begin 37 | cnt <= 6'd0; 38 | end else begin 39 | cnt <= cnt + 6'd1; 40 | end 41 | end 42 | end 43 | 44 | always @(posedge clk) begin 45 | if (~resetn) begin 46 | shift_clk <= 1'b0; 47 | end else if (serial_clk) begin 48 | shift_clk <= 1'b0; 49 | end else begin 50 | if (cnt == 6'd32) begin 51 | shift_clk <= 1'b0; 52 | end else begin 53 | shift_clk <= 1'b1; 54 | end 55 | end 56 | end 57 | 58 | always @(posedge clk) begin 59 | if (~resetn) begin 60 | store_clk <= 1'b0; 61 | end else if (serial_clk) begin 62 | store_clk <= 1'b0; 63 | end else begin 64 | if (cnt == 6'd32) begin 65 | store_clk <= 1'b1; 66 | end else begin 67 | store_clk <= 1'b0; 68 | end 69 | end 70 | end 71 | 72 | always @(posedge clk) begin 73 | if (~resetn) begin 74 | data_0_r <= 32'd0; 75 | data_1_r <= 32'd0; 76 | end else if (serial_clk) begin 77 | if (cnt == 6'd0) begin 78 | data_0_r <= data_0; 79 | data_1_r <= data_1; 80 | end else begin 81 | data_0_r <= {data_0_r[30:0], 1'b0}; 82 | data_1_r <= {data_1_r[30:0], 1'b0}; 83 | end 84 | end 85 | end 86 | 87 | assign RCLK = store_clk; 88 | assign SRCLK = shift_clk; 89 | assign SER_0 = data_0_r[31]; 90 | assign SER_1 = data_1_r[31]; 91 | 92 | endmodule 93 | -------------------------------------------------------------------------------- /shell/driver_74lv165.v: -------------------------------------------------------------------------------- 1 | module driver_74lv165 ( 2 | input clk, 3 | input resetn, 4 | 5 | output [23:0] data_0, 6 | output [23:0] data_1, 7 | output [23:0] data_2, 8 | 9 | output SH_LDn, // high for shift, low for load 10 | output RCLK, // clock 11 | 12 | input QH_0, // serial input 13 | input QH_1, // serial input 14 | input QH_2 // serial input 15 | ); 16 | 17 | reg serial_clk; 18 | reg shift_clk; 19 | reg shiftn_load; 20 | 21 | reg [ 4:0] cnt; 22 | 23 | reg [23:0] data_0_r; 24 | reg [23:0] data_1_r; 25 | reg [23:0] data_2_r; 26 | 27 | reg [23:0] data_0_s; 28 | reg [23:0] data_1_s; 29 | reg [23:0] data_2_s; 30 | 31 | always @(posedge clk) begin 32 | if (~resetn) begin 33 | serial_clk <= 1'b0; 34 | end else begin 35 | serial_clk <= ~serial_clk; 36 | end 37 | end 38 | 39 | always @(posedge clk) begin 40 | if (~resetn) begin 41 | cnt <= 5'd0; 42 | end else if (!serial_clk) begin 43 | if (cnt == 5'd24) begin 44 | cnt <= 5'd0; 45 | end else begin 46 | cnt <= cnt + 5'd1; 47 | end 48 | end 49 | end 50 | 51 | always @(posedge clk) begin 52 | if (~resetn) begin 53 | shift_clk <= 1'b0; 54 | end else if (serial_clk) begin 55 | shift_clk <= 1'b0; 56 | end else begin 57 | if (cnt == 5'd24) begin 58 | shift_clk <= 1'b0; 59 | end else begin 60 | shift_clk <= 1'b1; 61 | end 62 | end 63 | end 64 | 65 | always @(posedge clk) begin 66 | if (~resetn) begin 67 | shiftn_load <= 1'b0; 68 | end else if (serial_clk) begin 69 | shiftn_load <= 1'b0; 70 | end else begin 71 | if (cnt == 5'd24) begin 72 | shiftn_load <= 1'b1; 73 | end else begin 74 | shiftn_load <= 1'b0; 75 | end 76 | end 77 | end 78 | 79 | always @(posedge clk) begin 80 | if (~resetn) begin 81 | data_0_r <= 24'd0; 82 | data_1_r <= 24'd0; 83 | data_2_r <= 24'd0; 84 | end else if (!serial_clk && cnt == 5'd24) begin 85 | data_0_r <= data_0_s; 86 | data_1_r <= data_1_s; 87 | data_2_r <= data_2_s; 88 | end 89 | end 90 | 91 | always @(posedge clk) begin 92 | if (~resetn) begin 93 | data_0_s <= 24'd0; 94 | data_1_s <= 24'd0; 95 | data_2_s <= 24'd0; 96 | end else if (!serial_clk && cnt != 5'd24) begin 97 | data_0_s <= {data_0_s[22:0], QH_0}; 98 | data_1_s <= {data_1_s[22:0], QH_1}; 99 | data_2_s <= {data_2_s[22:0], QH_2}; 100 | end 101 | end 102 | 103 | assign SH_LDn = !shiftn_load; 104 | assign RCLK = shift_clk; 105 | assign data_0 = data_0_r; 106 | assign data_1 = data_1_r; 107 | assign data_2 = data_2_r; 108 | 109 | endmodule 110 | -------------------------------------------------------------------------------- /core/memory_fpga.v: -------------------------------------------------------------------------------- 1 | /** 2 | * ЗУ 3 | * запоминающее устройство 4 | * 存贮器 5 | * for ASIC 6 | **/ 7 | 8 | module memory_fpga ( 9 | input clk, 10 | input resetn, 11 | 12 | input mem_read_from_pu, 13 | input mem_read_from_pnl, 14 | input mem_write_from_io, 15 | input mem_write_from_pnl, 16 | output mem_read_reply_to_pu, 17 | output mem_read_reply_to_ac, 18 | output mem_write_reply_to_op, 19 | output mem_write_reply_to_io, 20 | output mem_reply_to_io, 21 | 22 | input [11:0] sel_value_from_sel, 23 | 24 | input write_sign_from_ac, 25 | input [29:0] write_data_from_au, 26 | output read_sign_to_ac, 27 | output [29:0] read_data_to_au 28 | ); 29 | 30 | // ctrl 31 | wire do_mem_read; 32 | wire do_mem_write; 33 | 34 | reg write_finish_r; 35 | reg read_finish_r; 36 | reg reading; 37 | reg writing; 38 | 39 | wire ram_write_enable; 40 | 41 | // machine side 42 | wire [11:0] addr; 43 | wire [30:0] write_data; 44 | wire [30:0] read_data; 45 | 46 | // middleware 47 | reg [30:0] write_data_r; 48 | reg [30:0] read_data_r; 49 | 50 | // ram side 51 | wire [10:0] ram_addr; 52 | wire [30:0] ram_read_word; 53 | wire [30:0] ram_write_word; 54 | 55 | // ram 56 | Gowin_SP ram ( 57 | .dout(ram_read_word), 58 | .clk(clk), 59 | .oce(1'b0), 60 | .ce(1'b1), 61 | .reset(~resetn), 62 | .wre(ram_write_enable), 63 | .ad(ram_addr), 64 | .din(ram_write_word) 65 | ); 66 | 67 | // ctrl 68 | assign do_mem_read = 69 | mem_read_from_pu || mem_read_from_pnl; 70 | assign do_mem_write = 71 | mem_write_from_io || mem_write_from_pnl; 72 | 73 | assign addr = sel_value_from_sel; 74 | assign ram_addr = addr[10:0]; 75 | assign ram_write_enable = writing; 76 | 77 | // buffer registers 78 | // read_data <- read_data_r <- ram_read_word 79 | assign read_data = read_data_r; 80 | always @(posedge clk) begin 81 | if (~resetn) begin 82 | read_data_r <= 31'b0; 83 | end else if (reading) begin 84 | read_data_r <= ram_read_word; 85 | end 86 | end 87 | 88 | // write_data -> write_data_r -> ram_write_word 89 | assign ram_write_word = write_data_r; 90 | always @(posedge clk) begin 91 | if (~resetn) begin 92 | write_data_r <= 31'b0; 93 | end else if (do_mem_write) begin 94 | write_data_r <= write_data; 95 | end 96 | end 97 | 98 | // sequence control signals 99 | always @(posedge clk) begin 100 | if (~resetn) begin 101 | reading <= 1'b0; 102 | end else if (do_mem_read) begin 103 | reading <= 1'b1; 104 | end else begin 105 | reading <= 1'b0; 106 | end 107 | end 108 | 109 | always @(posedge clk) begin 110 | if (~resetn) begin 111 | writing <= 1'b0; 112 | end else if (do_mem_write) begin 113 | writing <= 1'b1; 114 | end else begin 115 | writing <= 1'b0; 116 | end 117 | end 118 | 119 | always @(posedge clk) begin 120 | if (~resetn) begin 121 | write_finish_r <= 1'b0; 122 | read_finish_r <= 1'b0; 123 | end else begin 124 | write_finish_r <= writing; 125 | read_finish_r <= reading; 126 | end 127 | end 128 | 129 | // reply signals 130 | assign mem_write_reply_to_io = write_finish_r; 131 | assign mem_write_reply_to_op = write_finish_r; 132 | assign mem_read_reply_to_pu = read_finish_r; 133 | assign mem_read_reply_to_ac = read_finish_r; 134 | 135 | assign mem_reply_to_io = write_finish_r || read_finish_r; 136 | 137 | // concatenation of sign and data 138 | assign write_data = {write_sign_from_ac, write_data_from_au}; 139 | assign {read_sign_to_ac, read_data_to_au} = read_data; 140 | 141 | endmodule 142 | -------------------------------------------------------------------------------- /core/operator.v: -------------------------------------------------------------------------------- 1 | /** 2 | * БО 3 | * блока операций 4 | * 操作器 or 操作部件 5 | **/ 6 | 7 | module operator ( 8 | input clk, 9 | input resetn, 10 | 11 | input clear_pu_from_pnl, // pulse, from pnl 12 | 13 | input do_code_to_op_from_pu, // pulse, from pu 14 | input operate_pulse_from_pu, // pulse, from pu 15 | input do_move_b_to_c_from_pu, // pulse, from pu 16 | input do_move_c_to_a_from_pu, // pulse, from pu 17 | input mem_write_reply_from_mem, // pulse, from pu 18 | 19 | input ac_answer_from_ac, // pulse, from ac 20 | 21 | input reg_a_sign_from_ac, // level, from ac 22 | input reg_b_sign_from_ac, // level, from ac 23 | 24 | input [ 5:0] op_code_from_au, // level, from au 25 | 26 | output order_add_to_ac, // pulse, to ac 27 | output order_sub_to_ac, // pulse, to ac 28 | output order_mul_to_ac, // pulse, to ac 29 | output order_div_to_ac, // pulse, to ac 30 | output order_and_to_ac, // pulse, to ac 31 | output order_input_to_io, // pulse, to io 32 | 33 | output order_write_to_io, // pulse, to io 34 | output order_output_to_io, // pulse, to io 35 | output start_pulse_to_io, // pulse, to io 36 | 37 | output ctrl_abs_to_ac, // level, to ac 38 | output [ 5:0] ctrl_bus_to_pu, // level bus, to pu 39 | 40 | output [ 5:0] op_code_to_pnl // level bus, to pnl 41 | ); 42 | 43 | // operate code register 44 | reg [ 5:0] op_code; 45 | 46 | wire [ 2:0] op_code_p1; 47 | wire [ 2:0] op_code_p2; 48 | 49 | // decode for pu 50 | wire ctrl_select_to_start_at_4; 51 | wire ctrl_select_to_start_at_7; 52 | wire ctrl_move_b_to_c_at_7; // opp: ctrl_move_c_to_b_at_7 53 | wire ctrl_mem_read_at_3; 54 | wire ctrl_mem_read_at_5; 55 | wire wait_start_at_6; 56 | 57 | // operate code register 58 | always @ (posedge clk) begin 59 | if (~resetn) begin 60 | op_code <= 6'h0; 61 | end else if (clear_pu_from_pnl) begin 62 | op_code <= 6'h0; 63 | end else if (do_code_to_op_from_pu) begin 64 | op_code <= op_code_from_au; 65 | end 66 | end 67 | 68 | assign op_code_to_pnl = op_code; 69 | 70 | assign op_code_p1 = op_code[5:3]; 71 | assign op_code_p2 = op_code[2:0]; 72 | 73 | // decode for ac 74 | assign order_add_to_ac = 75 | operate_pulse_from_pu && ( 76 | (op_code_p2 == 3'o0 && reg_a_sign_from_ac == reg_b_sign_from_ac) || // (+ [+] +) || (- [+] -) 77 | (op_code_p2 == 3'o1 && reg_a_sign_from_ac != reg_b_sign_from_ac) // (+ [-] -) || (- [-] +) 78 | ); 79 | assign order_sub_to_ac = 80 | operate_pulse_from_pu && ( 81 | (op_code_p2 == 3'o1 && reg_a_sign_from_ac == reg_b_sign_from_ac) || // (+ [-] +) || (- [-] -) 82 | (op_code_p2 == 3'o0 && reg_a_sign_from_ac != reg_b_sign_from_ac) // (+ [+] -) || (- [+] +) 83 | ); 84 | assign order_div_to_ac = 85 | operate_pulse_from_pu && op_code_p2 == 3'o2; 86 | assign order_mul_to_ac = 87 | operate_pulse_from_pu && op_code_p2 == 3'o3; 88 | assign order_and_to_ac = 89 | operate_pulse_from_pu && op_code_p2 == 3'o6; 90 | 91 | assign ctrl_abs_to_ac = 92 | op_code_p1[2] && op_code_p1[0]; 93 | 94 | // decode for io 95 | assign order_input_to_io = 96 | operate_pulse_from_pu && op_code_p2 == 3'o7 && ~op_code_p1[0]; 97 | 98 | // decode for pu 99 | assign ctrl_select_to_start_at_4 = op_code_p2 == 3'o4 && op_code_p1[1]; 100 | assign ctrl_select_to_start_at_7 = op_code_p2 == 3'o4 && op_code_p1[1] && op_code_p1[0] && ~reg_b_sign_from_ac; 101 | assign ctrl_move_b_to_c_at_7 = op_code_p1[1]; 102 | assign ctrl_mem_read_at_3 = op_code_p2 != 3'o4; 103 | assign ctrl_mem_read_at_5 = ~op_code_p1[1] && op_code_p2 != 3'o5; 104 | assign wait_start_at_6 = ~op_code_p1[1]; 105 | 106 | assign ctrl_bus_to_pu = { 107 | ctrl_select_to_start_at_4, 108 | ctrl_select_to_start_at_7, 109 | ctrl_move_b_to_c_at_7, 110 | ctrl_mem_read_at_3, 111 | ctrl_mem_read_at_5, 112 | wait_start_at_6 113 | }; 114 | 115 | // for finish (delay one cycle in io) 116 | assign order_write_to_io = 117 | (do_move_b_to_c_from_pu && op_code_p1[0] == 1'b0 && op_code_p2 == 3'o4) || // 04,24,44,64 118 | (do_move_c_to_a_from_pu && op_code_p2 == 3'o5) || // X5 119 | (ac_answer_from_ac && op_code_p1[0] == 1'b0); 120 | assign order_output_to_io = 121 | (mem_write_reply_from_mem && op_code_p1[2] == 1'b1); 122 | assign start_pulse_to_io = 123 | (operate_pulse_from_pu && (op_code_p2 == 3'o5 || op_code == 6'o34 || op_code == 6'o74)) || 124 | (ac_answer_from_ac && op_code_p1[0] == 1'b1); 125 | 126 | endmodule 127 | -------------------------------------------------------------------------------- /core/arith_unit.v: -------------------------------------------------------------------------------- 1 | /** 2 | * АУ 3 | * арифметический узел 4 | * 运算器 5 | **/ 6 | 7 | module arith_unit ( 8 | input clk, 9 | input resetn, 10 | 11 | input do_clear_a_from_ac, 12 | input do_clear_b_from_ac, 13 | input do_clear_c_from_ac, 14 | input do_not_a_from_ac, 15 | input do_not_b_from_ac, 16 | input do_sum_from_ac, 17 | input do_and_from_ac, 18 | input do_set_c_30_from_ac, 19 | input do_left_shift_b_from_ac, 20 | input do_left_shift_c_from_ac, 21 | input do_left_shift_c29_from_ac, 22 | input do_right_shift_bc_from_ac, 23 | input do_move_c_to_a_from_ac, 24 | input do_move_c_to_b_from_ac, 25 | input do_move_b_to_c_from_ac, 26 | 27 | output carry_out_to_ac, 28 | output reg_b0_to_ac, 29 | output reg_c1_to_ac, 30 | output reg_c30_to_ac, 31 | 32 | output [ 5:0] op_code_to_op, 33 | output [11:0] addr1_value_to_sel, 34 | output [11:0] addr2_value_to_sel, 35 | 36 | input [ 4:0] input_data_from_io, 37 | output [ 3:0] output_data_to_io, 38 | 39 | input do_arr_c_from_pnl, 40 | input [29:0] arr_reg_c_value_from_pnl, 41 | output [29:0] reg_c_value_to_pnl, 42 | 43 | input do_mem_to_c_from_ac, 44 | input [29:0] read_data_from_mem, 45 | output [29:0] write_data_to_mem 46 | ); 47 | 48 | // use big endian to declare this registers instead of little endian. 49 | reg [29:0] val_reg_a; 50 | reg [30:0] val_reg_b; 51 | reg [29:0] val_reg_c; 52 | 53 | reg carry_in; 54 | wire [30:0] val_sum; 55 | wire [29:0] val_not_a; 56 | wire [29:0] val_not_b; 57 | wire [29:0] val_and; 58 | 59 | assign val_sum[30:0] = {1'b0, val_reg_a[29:0]} + {1'b0, val_reg_b[29:0]} + {30'b0, carry_in}; 60 | assign val_not_a[29:0] = ~val_reg_a[29:0]; 61 | assign val_not_b[29:0] = ~val_reg_b[29:0]; 62 | assign val_and[29:0] = val_reg_a[29:0] & val_reg_c[29:0]; 63 | 64 | always @(posedge clk) begin 65 | if (~resetn) begin 66 | val_reg_a[29:0] <= 30'b0; 67 | end else if (do_clear_a_from_ac) begin 68 | val_reg_a[29:0] <= 30'b0; 69 | end else if (do_not_a_from_ac) begin 70 | val_reg_a[29:0] <= val_not_a[29:0]; 71 | end else if (do_move_c_to_a_from_ac) begin 72 | val_reg_a[29:0] <= val_reg_c[29:0]; 73 | end 74 | end 75 | 76 | always @(posedge clk) begin 77 | if (~resetn) begin 78 | val_reg_b[30:0] <= 31'b0; 79 | end else if (do_clear_b_from_ac) begin 80 | val_reg_b[30:0] <= 31'b0; 81 | end else if (do_not_b_from_ac) begin 82 | val_reg_b[30:0] <= {1'b0, val_not_b[29:0]}; 83 | end else if (do_move_c_to_b_from_ac) begin 84 | val_reg_b[30:0] <= {1'b0, val_reg_c[29:0]}; 85 | end else if (do_left_shift_b_from_ac) begin 86 | val_reg_b[30:0] <= {val_reg_b[29:0], 1'b0}; 87 | end else if (do_right_shift_bc_from_ac) begin 88 | val_reg_b[30:0] <= {1'b0, val_reg_b[30:1]}; 89 | end else if (do_sum_from_ac) begin 90 | val_reg_b[30:0] <= val_sum[30:0]; 91 | end 92 | end 93 | 94 | always @(posedge clk) begin 95 | if (~resetn) begin 96 | val_reg_c[29:0] <= 30'b0; 97 | end else if (do_clear_c_from_ac) begin 98 | val_reg_c[29:0] <= 30'b0; 99 | end else if (do_move_b_to_c_from_ac) begin 100 | val_reg_c[29:0] <= val_reg_b[29:0]; 101 | end else if (do_left_shift_c_from_ac) begin 102 | val_reg_c[29:3] <= val_reg_c[28:2]; 103 | val_reg_c[2] <= do_left_shift_c29_from_ac ? val_reg_c[1] : input_data_from_io[3]; 104 | val_reg_c[1] <= val_reg_c[0]; 105 | val_reg_c[0] <= input_data_from_io[2]; 106 | end else if (do_right_shift_bc_from_ac) begin 107 | val_reg_c[29:0] <= {1'b0, val_reg_c[29:1]}; 108 | end else if (do_and_from_ac) begin 109 | val_reg_c[29:0] <= val_and[29:0]; 110 | end else if (do_set_c_30_from_ac) begin 111 | val_reg_c[29:0] <= {val_reg_c[29:1], 1'b1}; 112 | end else if (do_mem_to_c_from_ac) begin 113 | val_reg_c[29:0] <= read_data_from_mem[29:0]; 114 | end else if (do_arr_c_from_pnl) begin 115 | val_reg_c[29:0] <= arr_reg_c_value_from_pnl[29:0]; 116 | end 117 | end 118 | 119 | always @(posedge clk) begin 120 | if (~resetn) begin 121 | carry_in <= 1'b0; 122 | end else if (do_not_a_from_ac || do_not_b_from_ac) begin 123 | carry_in <= 1'b1; 124 | end else if (do_clear_a_from_ac || do_clear_b_from_ac || do_move_c_to_a_from_ac || do_move_c_to_b_from_ac) begin 125 | carry_in <= 1'b0; 126 | end 127 | end 128 | 129 | assign reg_c_value_to_pnl[29:0] = val_reg_c[29: 0]; 130 | assign write_data_to_mem[29:0] = val_reg_c[29: 0]; 131 | assign op_code_to_op[5:0] = val_reg_c[29:24]; 132 | assign addr1_value_to_sel[11:0] = val_reg_c[23:12]; 133 | assign addr2_value_to_sel[11:0] = val_reg_c[11: 0]; 134 | assign output_data_to_io[3:0] = val_reg_c[29:26]; 135 | 136 | assign carry_out_to_ac = val_sum[30]; 137 | assign reg_b0_to_ac = val_reg_b[30]; 138 | assign reg_c1_to_ac = val_reg_c[29]; 139 | assign reg_c30_to_ac = val_reg_c[0]; 140 | 141 | endmodule 142 | -------------------------------------------------------------------------------- /core/pulse_unit.v: -------------------------------------------------------------------------------- 1 | /** 2 | * РИ 3 | * распределителя импульсов 4 | * 脉冲分配器 5 | **/ 6 | 7 | module pulse_unit ( 8 | input clk, 9 | input resetn, 10 | 11 | output do_code_to_op_to_op, // pulse, to op 12 | output do_inc_strt_to_strt, // pulse, to start_reg 13 | output do_addr1_to_sel_to_sel, // pulse, to select_reg 14 | output do_addr2_to_sel_to_sel, // pulse, to select_reg 15 | output do_strt_to_sel_to_sel, // pulse, to select_reg 16 | output do_sel_to_strt_to_strt, // pulse, to start_reg 17 | // output do_mem_to_c_to_ac, // pulse, to airth_ctrl 18 | output do_clear_a_to_ac, // pulse, to airth_ctrl 19 | output do_move_c_to_a_to_ac, // pulse, to airth_ctrl 20 | output do_move_c_to_b_to_ac, // pulse, to airth_ctrl 21 | output do_move_b_to_c_to_ac, // pulse, to airth_ctrl 22 | 23 | output do_move_c_to_a_to_op, // pulse, to op 24 | output do_move_b_to_c_to_op, // pulse, to op 25 | 26 | output operate_pulse_to_op, // pulse, to op 27 | output mem_read_to_mem, // pulse, to mem 28 | 29 | input mem_read_reply_from_mem, // pulse, from mem 30 | input start_pulse_from_io, // pulse, from io_unit 31 | input clear_pu_from_pnl, // pulse, from pnl 32 | 33 | input [ 5:0] ctrl_bus_from_op, // level bus, from op 34 | 35 | output [ 2:0] pu_state_to_pnl // level, to pnl 36 | ); 37 | 38 | reg [ 2:0] cur_pulse; 39 | reg [ 2:0] next_pulse; 40 | 41 | wire [7:0] do_pulse; 42 | // wire do_pulse; 43 | wire [7:0] at_pulse; 44 | wire [7:0] entering_pulse; 45 | 46 | wire ctrl_select_to_start_at_4; 47 | wire ctrl_select_to_start_at_7; 48 | wire ctrl_move_b_to_c_at_7; // opp: ctrl_move_c_to_b_at_7 49 | wire ctrl_move_c_to_b_at_7; // new 50 | wire ctrl_mem_read_at_3; 51 | wire ctrl_mem_read_at_5; 52 | wire wait_start_at_4; 53 | wire wait_start_at_6; 54 | 55 | // pulse ctrl 56 | 57 | assign { 58 | ctrl_select_to_start_at_4, 59 | ctrl_select_to_start_at_7, 60 | ctrl_move_b_to_c_at_7, 61 | ctrl_mem_read_at_3, 62 | ctrl_mem_read_at_5, 63 | wait_start_at_6 64 | } = ctrl_bus_from_op; 65 | 66 | assign ctrl_move_c_to_b_at_7 = !ctrl_move_b_to_c_at_7; 67 | assign wait_start_at_4 = ctrl_mem_read_at_3; 68 | 69 | // state machine of pulse 70 | assign pu_state_to_pnl = cur_pulse; 71 | 72 | always @(posedge clk) begin 73 | if (~resetn) begin 74 | cur_pulse <= 3'o0; 75 | end else if (clear_pu_from_pnl) begin 76 | cur_pulse <= 3'o0; 77 | end else begin 78 | cur_pulse <= next_pulse; 79 | end 80 | end 81 | 82 | always @ (*) begin 83 | if (|do_pulse) begin 84 | next_pulse = cur_pulse + 3'o1; 85 | end else begin 86 | next_pulse = cur_pulse; 87 | end 88 | end 89 | 90 | assign at_pulse[0] = cur_pulse == 3'o0; 91 | assign at_pulse[1] = cur_pulse == 3'o1; 92 | assign at_pulse[2] = cur_pulse == 3'o2; 93 | assign at_pulse[3] = cur_pulse == 3'o3; 94 | assign at_pulse[4] = cur_pulse == 3'o4; 95 | assign at_pulse[5] = cur_pulse == 3'o5; 96 | assign at_pulse[6] = cur_pulse == 3'o6; 97 | assign at_pulse[7] = cur_pulse == 3'o7; 98 | 99 | assign entering_pulse[1] = do_pulse[0]; 100 | assign entering_pulse[2] = do_pulse[1]; 101 | assign entering_pulse[3] = do_pulse[2]; 102 | assign entering_pulse[4] = do_pulse[3]; 103 | assign entering_pulse[5] = do_pulse[4]; 104 | assign entering_pulse[6] = do_pulse[5]; 105 | assign entering_pulse[7] = do_pulse[6]; 106 | assign entering_pulse[0] = do_pulse[7]; 107 | 108 | assign do_pulse[0] = at_pulse[0] && start_pulse_from_io; 109 | assign do_pulse[1] = at_pulse[1]; 110 | assign do_pulse[2] = at_pulse[2] && start_pulse_from_io; 111 | assign do_pulse[3] = at_pulse[3]; 112 | assign do_pulse[4] = at_pulse[4] && (start_pulse_from_io || !wait_start_at_4); 113 | assign do_pulse[5] = at_pulse[5]; 114 | assign do_pulse[6] = at_pulse[6] && (start_pulse_from_io || !wait_start_at_6); 115 | assign do_pulse[7] = at_pulse[7]; 116 | 117 | 118 | // output control signals 119 | assign do_code_to_op_to_op = entering_pulse[3]; 120 | assign do_inc_strt_to_strt = entering_pulse[3]; 121 | assign do_addr1_to_sel_to_sel = entering_pulse[3]; 122 | assign do_addr2_to_sel_to_sel = 123 | (at_pulse[4] && mem_read_reply_from_mem && wait_start_at_4) || 124 | (entering_pulse[4] && !wait_start_at_4); 125 | assign do_strt_to_sel_to_sel = entering_pulse[1]; 126 | assign do_sel_to_strt_to_strt = 127 | (at_pulse[3] && ctrl_select_to_start_at_4) || 128 | (at_pulse[7] && ctrl_select_to_start_at_7); 129 | assign do_move_c_to_a_to_ac = entering_pulse[5]; 130 | assign do_move_c_to_b_to_ac = 131 | (entering_pulse[7] && ctrl_move_c_to_b_at_7); 132 | assign do_move_b_to_c_to_ac = 133 | (entering_pulse[7] && ctrl_move_b_to_c_at_7); 134 | // assign do_mem_to_c_to_ac = 135 | // (at_pulse[2] && mem_read_reply_from_mem) || 136 | // (at_pulse[4] && mem_read_reply_from_mem && ctrl_mem_read_at_3) || 137 | // (at_pulse[6] && mem_read_reply_from_mem && ctrl_mem_read_at_5); 138 | assign mem_read_to_mem = 139 | (at_pulse[1]) || 140 | (at_pulse[3] && ctrl_mem_read_at_3) || 141 | (at_pulse[5] && ctrl_mem_read_at_5); 142 | assign operate_pulse_to_op = at_pulse[7]; 143 | assign do_clear_a_to_ac = at_pulse[1]; 144 | 145 | assign do_move_c_to_a_to_op = do_move_c_to_a_to_ac; 146 | assign do_move_b_to_c_to_op = do_move_b_to_c_to_ac; 147 | 148 | endmodule 149 | -------------------------------------------------------------------------------- /core/memory_asic.v: -------------------------------------------------------------------------------- 1 | /** 2 | * ЗУ 3 | * запоминающее устройство 4 | * 存贮器 5 | * for ASIC 6 | **/ 7 | 8 | module memory_asic ( 9 | input clk, 10 | input resetn, 11 | 12 | input mem_read_from_pu, 13 | input mem_read_from_pnl, 14 | input mem_write_from_io, 15 | input mem_write_from_pnl, 16 | output mem_read_reply_to_pu, 17 | output mem_read_reply_to_ac, 18 | output mem_write_reply_to_op, 19 | output mem_write_reply_to_io, 20 | output mem_reply_to_io, 21 | 22 | input [11:0] sel_value_from_sel, 23 | 24 | input write_sign_from_ac, 25 | input [29:0] write_data_from_au, 26 | output read_sign_to_ac, 27 | output [29:0] read_data_to_au 28 | ); 29 | 30 | wire do_mem_read; 31 | wire do_mem_write; 32 | 33 | wire [11:0] addr; 34 | wire [30:0] write_data; 35 | wire [30:0] read_data; 36 | 37 | wire [30:0] ram_read_word; 38 | wire [30:0] ram_write_word; 39 | 40 | wire [127:0] ram_read_line; 41 | wire [127:0] ram_write_line; 42 | wire [127:0] ram_write_bit; 43 | 44 | reg [30:0] write_data_r; 45 | reg [30:0] read_data_r; 46 | 47 | reg write_finish_r; 48 | reg read_finish_r; 49 | reg reading; 50 | reg writing; 51 | 52 | // ram_0 53 | 54 | wire ram_0_enable; 55 | wire ram_0_write_enable; 56 | wire [127:0] ram_0_read_line; 57 | wire [127:0] ram_0_write_line; 58 | wire [127:0] ram_0_write_bit; 59 | wire [ 5:0] ram_0_addr; 60 | 61 | S011HD1P_X32Y2D128_BW ram_0 ( 62 | .Q (ram_0_read_line), 63 | .CLK (clk), 64 | .CEN (ram_0_enable), 65 | .WEN (ram_0_write_enable), 66 | .BWEN (ram_0_write_bit), 67 | .A (ram_0_addr), 68 | .D (ram_0_write_line) 69 | ); 70 | 71 | // ram_1 72 | 73 | wire ram_1_enable; 74 | wire ram_1_write_enable; 75 | wire [127:0] ram_1_read_line; 76 | wire [127:0] ram_1_write_line; 77 | wire [127:0] ram_1_write_bit; 78 | wire [ 5:0] ram_1_addr; 79 | 80 | S011HD1P_X32Y2D128_BW ram_1 ( 81 | .Q (ram_1_read_line), 82 | .CLK (clk), 83 | .CEN (ram_1_enable), 84 | .WEN (ram_1_write_enable), 85 | .BWEN (ram_1_write_bit), 86 | .A (ram_1_addr), 87 | .D (ram_1_write_line) 88 | ); 89 | 90 | // ram_2 91 | 92 | wire ram_2_enable; 93 | wire ram_2_write_enable; 94 | wire [127:0] ram_2_read_line; 95 | wire [127:0] ram_2_write_line; 96 | wire [127:0] ram_2_write_bit; 97 | wire [ 5:0] ram_2_addr; 98 | 99 | S011HD1P_X32Y2D128_BW ram_2 ( 100 | .Q (ram_2_read_line), 101 | .CLK (clk), 102 | .CEN (ram_2_enable), 103 | .WEN (ram_2_write_enable), 104 | .BWEN (ram_2_write_bit), 105 | .A (ram_2_addr), 106 | .D (ram_2_write_line) 107 | ); 108 | 109 | // ram_3 110 | 111 | wire ram_3_enable; 112 | wire ram_3_write_enable; 113 | wire [127:0] ram_3_read_line; 114 | wire [127:0] ram_3_write_line; 115 | wire [127:0] ram_3_write_bit; 116 | wire [ 5:0] ram_3_addr; 117 | 118 | S011HD1P_X32Y2D128_BW ram_3 ( 119 | .Q (ram_3_read_line), 120 | .CLK (clk), 121 | .CEN (ram_3_enable), 122 | .WEN (ram_3_write_enable), 123 | .BWEN (ram_3_write_bit), 124 | .A (ram_3_addr), 125 | .D (ram_3_write_line) 126 | ); 127 | 128 | // ram_4 129 | 130 | wire ram_4_enable; 131 | wire ram_4_write_enable; 132 | wire [127:0] ram_4_read_line; 133 | wire [127:0] ram_4_write_line; 134 | wire [127:0] ram_4_write_bit; 135 | wire [ 5:0] ram_4_addr; 136 | 137 | S011HD1P_X32Y2D128_BW ram_4 ( 138 | .Q (ram_4_read_line), 139 | .CLK (clk), 140 | .CEN (ram_4_enable), 141 | .WEN (ram_4_write_enable), 142 | .BWEN (ram_4_write_bit), 143 | .A (ram_4_addr), 144 | .D (ram_4_write_line) 145 | ); 146 | 147 | // ram_5 148 | 149 | wire ram_5_enable; 150 | wire ram_5_write_enable; 151 | wire [127:0] ram_5_read_line; 152 | wire [127:0] ram_5_write_line; 153 | wire [127:0] ram_5_write_bit; 154 | wire [ 5:0] ram_5_addr; 155 | 156 | S011HD1P_X32Y2D128_BW ram_5 ( 157 | .Q (ram_5_read_line), 158 | .CLK (clk), 159 | .CEN (ram_5_enable), 160 | .WEN (ram_5_write_enable), 161 | .BWEN (ram_5_write_bit), 162 | .A (ram_5_addr), 163 | .D (ram_5_write_line) 164 | ); 165 | 166 | // ram_6 167 | 168 | wire ram_6_enable; 169 | wire ram_6_write_enable; 170 | wire [127:0] ram_6_read_line; 171 | wire [127:0] ram_6_write_line; 172 | wire [127:0] ram_6_write_bit; 173 | wire [ 5:0] ram_6_addr; 174 | 175 | S011HD1P_X32Y2D128_BW ram_6 ( 176 | .Q (ram_6_read_line), 177 | .CLK (clk), 178 | .CEN (ram_6_enable), 179 | .WEN (ram_6_write_enable), 180 | .BWEN (ram_6_write_bit), 181 | .A (ram_6_addr), 182 | .D (ram_6_write_line) 183 | ); 184 | 185 | // ram_7 186 | 187 | wire ram_7_enable; 188 | wire ram_7_write_enable; 189 | wire [127:0] ram_7_read_line; 190 | wire [127:0] ram_7_write_line; 191 | wire [127:0] ram_7_write_bit; 192 | wire [ 5:0] ram_7_addr; 193 | 194 | S011HD1P_X32Y2D128_BW ram_7 ( 195 | .Q (ram_7_read_line), 196 | .CLK (clk), 197 | .CEN (ram_7_enable), 198 | .WEN (ram_7_write_enable), 199 | .BWEN (ram_7_write_bit), 200 | .A (ram_7_addr), 201 | .D (ram_7_write_line) 202 | ); 203 | 204 | assign do_mem_read = 205 | mem_read_from_pu || mem_read_from_pnl; 206 | assign do_mem_write = 207 | mem_write_from_io || mem_write_from_pnl; 208 | 209 | assign addr = sel_value_from_sel; 210 | 211 | // select 212 | assign ram_0_enable = ~(addr[11:8] == 4'o0); 213 | assign ram_1_enable = ~(addr[11:8] == 4'o1); 214 | assign ram_2_enable = ~(addr[11:8] == 4'o2); 215 | assign ram_3_enable = ~(addr[11:8] == 4'o3); 216 | assign ram_4_enable = ~(addr[11:8] == 4'o4); 217 | assign ram_5_enable = ~(addr[11:8] == 4'o5); 218 | assign ram_6_enable = ~(addr[11:8] == 4'o6); 219 | assign ram_7_enable = ~(addr[11:8] == 4'o7); 220 | 221 | assign ram_0_addr = addr[7:2]; 222 | assign ram_1_addr = addr[7:2]; 223 | assign ram_2_addr = addr[7:2]; 224 | assign ram_3_addr = addr[7:2]; 225 | assign ram_4_addr = addr[7:2]; 226 | assign ram_5_addr = addr[7:2]; 227 | assign ram_6_addr = addr[7:2]; 228 | assign ram_7_addr = addr[7:2]; 229 | 230 | assign ram_read_line = 231 | ({128{~ram_0_enable}} & ram_0_read_line) | 232 | ({128{~ram_1_enable}} & ram_1_read_line) | 233 | ({128{~ram_2_enable}} & ram_2_read_line) | 234 | ({128{~ram_3_enable}} & ram_3_read_line) | 235 | ({128{~ram_4_enable}} & ram_4_read_line) | 236 | ({128{~ram_5_enable}} & ram_5_read_line) | 237 | ({128{~ram_6_enable}} & ram_6_read_line) | 238 | ({128{~ram_7_enable}} & ram_7_read_line); 239 | 240 | assign ram_read_word = 241 | ({31{addr[1:0] == 2'o0}} & ram_read_line[ 30: 0]) | 242 | ({31{addr[1:0] == 2'o1}} & ram_read_line[ 62:32]) | 243 | ({31{addr[1:0] == 2'o2}} & ram_read_line[ 94:64]) | 244 | ({31{addr[1:0] == 2'o3}} & ram_read_line[126:96]); 245 | 246 | assign ram_write_line = {4{1'b0, ram_write_word}}; 247 | 248 | assign ram_0_write_line = ram_write_line; 249 | assign ram_1_write_line = ram_write_line; 250 | assign ram_2_write_line = ram_write_line; 251 | assign ram_3_write_line = ram_write_line; 252 | assign ram_4_write_line = ram_write_line; 253 | assign ram_5_write_line = ram_write_line; 254 | assign ram_6_write_line = ram_write_line; 255 | assign ram_7_write_line = ram_write_line; 256 | 257 | assign ram_write_bit = 258 | ({128{addr[1:0] == 2'o0}} & (128'h7fff_ffff << 0)) | 259 | ({128{addr[1:0] == 2'o1}} & (128'h7fff_ffff << 32)) | 260 | ({128{addr[1:0] == 2'o2}} & (128'h7fff_ffff << 64)) | 261 | ({128{addr[1:0] == 2'o3}} & (128'h7fff_ffff << 96)); 262 | 263 | assign ram_0_write_bit = ~ram_write_bit; 264 | assign ram_1_write_bit = ~ram_write_bit; 265 | assign ram_2_write_bit = ~ram_write_bit; 266 | assign ram_3_write_bit = ~ram_write_bit; 267 | assign ram_4_write_bit = ~ram_write_bit; 268 | assign ram_5_write_bit = ~ram_write_bit; 269 | assign ram_6_write_bit = ~ram_write_bit; 270 | assign ram_7_write_bit = ~ram_write_bit; 271 | 272 | assign ram_0_write_enable = ~(writing); 273 | assign ram_1_write_enable = ~(writing); 274 | assign ram_2_write_enable = ~(writing); 275 | assign ram_3_write_enable = ~(writing); 276 | assign ram_4_write_enable = ~(writing); 277 | assign ram_5_write_enable = ~(writing); 278 | assign ram_6_write_enable = ~(writing); 279 | assign ram_7_write_enable = ~(writing); 280 | 281 | // buffer registers 282 | // read_data <- read_data_r <- ram_read_word 283 | assign read_data = read_data_r; 284 | always @(posedge clk) begin 285 | if (~resetn) begin 286 | read_data_r <= 31'b0; 287 | end else if (reading) begin 288 | read_data_r <= ram_read_word; 289 | end 290 | end 291 | 292 | // write_data -> write_data_r -> ram_write_word 293 | assign ram_write_word = write_data_r; 294 | always @(posedge clk) begin 295 | if (~resetn) begin 296 | write_data_r <= 31'b0; 297 | end else if (do_mem_write) begin 298 | write_data_r <= write_data; 299 | end 300 | end 301 | 302 | // sequence control signals 303 | 304 | always @(posedge clk) begin 305 | if (~resetn) begin 306 | reading <= 1'b0; 307 | end else if (do_mem_read) begin 308 | reading <= 1'b1; 309 | end else begin 310 | reading <= 1'b0; 311 | end 312 | end 313 | 314 | always @(posedge clk) begin 315 | if (~resetn) begin 316 | writing <= 1'b0; 317 | end else if (do_mem_write) begin 318 | writing <= 1'b1; 319 | end else begin 320 | writing <= 1'b0; 321 | end 322 | end 323 | 324 | always @(posedge clk) begin 325 | if (~resetn) begin 326 | write_finish_r <= 1'b0; 327 | read_finish_r <= 1'b0; 328 | end else begin 329 | write_finish_r <= writing; 330 | read_finish_r <= reading; 331 | end 332 | end 333 | 334 | // reply signals 335 | assign mem_write_reply_to_io = write_finish_r; 336 | assign mem_write_reply_to_op = write_finish_r; 337 | assign mem_read_reply_to_pu = read_finish_r; 338 | assign mem_read_reply_to_ac = read_finish_r; 339 | 340 | assign mem_reply_to_io = write_finish_r || read_finish_r; 341 | 342 | // concatenation of sign and data 343 | assign write_data = {write_sign_from_ac, write_data_from_au}; 344 | assign {read_sign_to_ac, read_data_to_au} = read_data; 345 | 346 | endmodule 347 | -------------------------------------------------------------------------------- /shell/hardware_top.v: -------------------------------------------------------------------------------- 1 | module hardware_top ( 2 | input clk, 3 | input resetn, 4 | 5 | output dev_input_rdy, // handshake 6 | input dev_input_val, // handshake 7 | 8 | output dev_output_rdy, // handshake 9 | input dev_output_ack, // handshake 10 | 11 | input [ 4:0] dev_input_data, // level 12 | output [ 4:0] dev_output_data, // level 13 | 14 | input btn_start_pulse, // btn 15 | input btn_clear_pu, // btn 16 | 17 | input btn_mem_read, // btn 18 | input btn_mem_write, // btn 19 | 20 | input btn_start_input, // btn 21 | input btn_stop_input, // btn 22 | input btn_start_output, // btn 23 | input btn_stop_output, // btn 24 | 25 | input sw_input_dec, // switch 26 | input sw_output_dec, // switch 27 | 28 | input sw_continuous_input, // switch 29 | input sw_stop_after_output, // switch 30 | input sw_automatic, // switch 31 | input sw_stop_at_cmp, // switch 32 | input sw_cmp_with_strt, // switch 33 | 34 | input sw_allow_arr, // switch 35 | 36 | 37 | input btn_do_arr_c, // btn 38 | input btn_do_arr_sel, // btn 39 | input btn_do_arr_strt, // btn 40 | 41 | output [ 2:0] pnl_pu_state, // level 42 | 43 | output serial_out_rclk, 44 | output serial_out_srclk, 45 | output serial_out_ser_0, 46 | output serial_out_ser_1, 47 | 48 | output serial_in_rclk, 49 | output serial_in_shldn, 50 | input serial_in_ser_0, 51 | input serial_in_ser_1, 52 | input serial_in_ser_2, 53 | 54 | output pnl_input_active, // level 55 | output pnl_output_active // level 56 | 57 | ); 58 | 59 | // dev sync 60 | wire dev_input_rdy_orig; 61 | wire dev_input_val_sync; 62 | wire dev_output_rdy_orig; 63 | wire dev_output_ack_sync; 64 | wire [ 4:0] dev_input_data_sync; 65 | wire [ 4:0] dev_output_data_orig; 66 | 67 | // pnl pulse 68 | wire pnl_start_pulse; 69 | wire pnl_clear_pu; 70 | wire pnl_mem_read; 71 | wire pnl_mem_write; 72 | wire pnl_start_input; 73 | wire pnl_stop_input; 74 | wire pnl_start_output; 75 | wire pnl_stop_output; 76 | wire pnl_do_arr_c; 77 | wire pnl_do_arr_sel; 78 | wire pnl_do_arr_strt; 79 | 80 | // pnl level 81 | wire pnl_input_dec; 82 | wire pnl_output_dec; 83 | wire pnl_continuous_input; 84 | wire pnl_stop_after_output; 85 | wire pnl_automatic; 86 | wire pnl_stop_at_cmp; 87 | wire pnl_cmp_with_strt; 88 | wire pnl_allow_arr; 89 | 90 | // pnl serial 91 | wire [30:0] pnl_arr_reg_c_value; 92 | wire [11:0] pnl_arr_strt_value; 93 | wire [11:0] pnl_arr_sel_value; 94 | wire [11:0] pnl_arr_cmp_value; 95 | 96 | wire [30:0] ser_arr_reg_c_value; 97 | wire [11:0] ser_arr_strt_value; 98 | wire [11:0] ser_arr_sel_value; 99 | wire [11:0] ser_arr_cmp_value; 100 | 101 | wire [23:0] serial_in_0; 102 | wire [23:0] serial_in_1; 103 | wire [23:0] serial_in_2; 104 | 105 | wire [30:0] pnl_reg_c_value; 106 | wire [ 5:0] pnl_op_code; 107 | wire [11:0] pnl_strt_value; 108 | wire [11:0] pnl_sel_value; 109 | 110 | wire [31:0] serial_out_0; 111 | wire [31:0] serial_out_1; 112 | 113 | core_top u_core_top ( 114 | .clk ( clk ), 115 | .resetn ( resetn ), 116 | .dev_input_val ( dev_input_val_sync ), 117 | .dev_output_ack ( dev_output_ack_sync ), 118 | .dev_input_data ( dev_input_data_sync ), 119 | .pnl_start_pulse ( pnl_start_pulse ), 120 | .pnl_clear_pu ( pnl_clear_pu ), 121 | .pnl_automatic ( pnl_automatic ), 122 | .pnl_mem_read ( pnl_mem_read ), 123 | .pnl_mem_write ( pnl_mem_write ), 124 | .pnl_start_input ( pnl_start_input ), 125 | .pnl_stop_input ( pnl_stop_input ), 126 | .pnl_start_output ( pnl_start_output ), 127 | .pnl_stop_output ( pnl_stop_output ), 128 | .pnl_input_dec ( pnl_input_dec ), 129 | .pnl_output_dec ( pnl_output_dec ), 130 | .pnl_continuous_input ( pnl_continuous_input ), 131 | .pnl_stop_after_output ( pnl_stop_after_output ), 132 | .pnl_stop_at_cmp ( pnl_stop_at_cmp ), 133 | .pnl_cmp_with_strt ( pnl_cmp_with_strt ), 134 | .pnl_do_arr_c ( pnl_do_arr_c ), 135 | .pnl_arr_reg_c_value ( pnl_arr_reg_c_value ), 136 | .pnl_do_arr_sel ( pnl_do_arr_sel ), 137 | .pnl_arr_sel_value ( pnl_arr_sel_value ), 138 | .pnl_do_arr_strt ( pnl_do_arr_strt ), 139 | .pnl_arr_strt_value ( pnl_arr_strt_value ), 140 | .pnl_arr_cmp_value ( pnl_arr_cmp_value ), 141 | 142 | .dev_input_rdy ( dev_input_rdy_orig ), 143 | .dev_output_rdy ( dev_output_rdy_orig ), 144 | .dev_output_data ( dev_output_data_orig ), 145 | .pnl_input_active ( pnl_input_active ), 146 | .pnl_output_active ( pnl_output_active ), 147 | .pnl_op_code ( pnl_op_code ), 148 | .pnl_sel_value ( pnl_sel_value ), 149 | .pnl_strt_value ( pnl_strt_value ), 150 | .pnl_reg_c_value ( pnl_reg_c_value ), 151 | .pnl_pu_state ( pnl_pu_state ) 152 | ); 153 | 154 | registered_output dev_input_rdy_registered_output ( 155 | .clk ( clk ), .resetn ( resetn ), 156 | .output_sig ( dev_input_rdy_orig ), 157 | .registered_sig ( dev_input_rdy ) 158 | ); 159 | registered_output dev_output_rdy_registered_output ( 160 | .clk ( clk ), .resetn ( resetn ), 161 | .output_sig ( dev_output_rdy_orig ), 162 | .registered_sig ( dev_output_rdy ) 163 | ); 164 | registered_output # ( 165 | .width ( 5 ) 166 | ) dev_output_data_registered_output ( 167 | .clk ( clk ), .resetn ( resetn ), 168 | .output_sig ( dev_output_data_orig ), 169 | .registered_sig ( dev_output_data ) 170 | ); 171 | 172 | sync_chain dev_input_val_sync_chain ( 173 | .clk ( clk ), .resetn ( resetn ), 174 | .input_sig ( dev_input_val ), 175 | .sync_sig ( dev_input_val_sync ) 176 | ); 177 | sync_chain dev_output_ack_sync_chain ( 178 | .clk ( clk ), .resetn ( resetn ), 179 | .input_sig ( dev_output_ack ), 180 | .sync_sig ( dev_output_ack_sync ) 181 | ); 182 | sync_chain # ( 183 | .width ( 5 ) 184 | ) dev_input_data_sync_chain ( 185 | .clk ( clk ), .resetn ( resetn ), 186 | .input_sig ( dev_input_data ), 187 | .sync_sig ( dev_input_data_sync ) 188 | ); 189 | 190 | button_pulse start_pulse_button_pulse ( 191 | .clk ( clk ), .resetn ( resetn ), 192 | .btn ( btn_start_pulse ), 193 | .pulse ( pnl_start_pulse ) 194 | ); 195 | button_pulse clear_pu_button_pulse ( 196 | .clk ( clk ), .resetn ( resetn ), 197 | .btn ( btn_clear_pu ), 198 | .pulse ( pnl_clear_pu ) 199 | ); 200 | button_pulse mem_read_button_pulse ( 201 | .clk ( clk ), .resetn ( resetn ), 202 | .btn ( btn_mem_read ), 203 | .pulse ( pnl_mem_read ) 204 | ); 205 | button_pulse mem_write_button_pulse ( 206 | .clk ( clk ), .resetn ( resetn ), 207 | .btn ( btn_mem_write ), 208 | .pulse ( pnl_mem_write ) 209 | ); 210 | button_pulse start_input_button_pulse ( 211 | .clk ( clk ), .resetn ( resetn ), 212 | .btn ( btn_start_input ), 213 | .pulse ( pnl_start_input ) 214 | ); 215 | button_pulse stop_input_button_pulse ( 216 | .clk ( clk ), .resetn ( resetn ), 217 | .btn ( btn_stop_input ), 218 | .pulse ( pnl_stop_input ) 219 | ); 220 | button_pulse start_output_button_pulse ( 221 | .clk ( clk ), .resetn ( resetn ), 222 | .btn ( btn_start_output ), 223 | .pulse ( pnl_start_output ) 224 | ); 225 | button_pulse stop_output_button_pulse ( 226 | .clk ( clk ), .resetn ( resetn ), 227 | .btn ( btn_stop_output ), 228 | .pulse ( pnl_stop_output ) 229 | ); 230 | button_pulse do_arr_c_button_pulse ( 231 | .clk ( clk ), .resetn ( resetn ), 232 | .btn ( btn_do_arr_c ), 233 | .pulse ( pnl_do_arr_c ) 234 | ); 235 | button_pulse do_arr_sel_button_pulse ( 236 | .clk ( clk ), .resetn ( resetn ), 237 | .btn ( btn_do_arr_sel ), 238 | .pulse ( pnl_do_arr_sel ) 239 | ); 240 | button_pulse do_arr_strt_button_pulse ( 241 | .clk ( clk ), .resetn ( resetn ), 242 | .btn ( btn_do_arr_strt ), 243 | .pulse ( pnl_do_arr_strt ) 244 | ); 245 | 246 | switch_level input_dec_switch_level ( 247 | .clk ( clk ), .resetn ( resetn ), 248 | .sw ( sw_input_dec ), 249 | .level ( pnl_input_dec ) 250 | ); 251 | switch_level output_dec_switch_level ( 252 | .clk ( clk ), .resetn ( resetn ), 253 | .sw ( sw_output_dec ), 254 | .level ( pnl_output_dec ) 255 | ); 256 | switch_level continuous_input_switch_level ( 257 | .clk ( clk ), .resetn ( resetn ), 258 | .sw ( sw_continuous_input ), 259 | .level ( pnl_continuous_input ) 260 | ); 261 | switch_level stop_after_output_switch_level ( 262 | .clk ( clk ), .resetn ( resetn ), 263 | .sw ( sw_stop_after_output ), 264 | .level ( pnl_stop_after_output ) 265 | ); 266 | switch_level automatic_switch_level ( 267 | .clk ( clk ), .resetn ( resetn ), 268 | .sw ( sw_automatic ), 269 | .level ( pnl_automatic ) 270 | ); 271 | switch_level stop_at_cmp_switch_level ( 272 | .clk ( clk ), .resetn ( resetn ), 273 | .sw ( sw_stop_at_cmp ), 274 | .level ( pnl_stop_at_cmp ) 275 | ); 276 | switch_level cmp_with_strt_switch_level ( 277 | .clk ( clk ), .resetn ( resetn ), 278 | .sw ( sw_cmp_with_strt ), 279 | .level ( pnl_cmp_with_strt ) 280 | ); 281 | switch_level allow_arr_switch_level ( 282 | .clk ( clk ), .resetn ( resetn ), 283 | .sw ( sw_allow_arr ), 284 | .level ( pnl_allow_arr ) 285 | ); 286 | 287 | assign serial_out_0 = 288 | { 1'b0, pnl_reg_c_value[30:0] }; 289 | assign serial_out_1 = 290 | { 2'b0, pnl_op_code[5:0], pnl_sel_value[11:0], pnl_strt_value[11:0] }; 291 | 292 | driver_74lv595 u_driver_74lv595 ( 293 | .clk ( clk ), .resetn ( resetn ), 294 | .data_0 ( serial_out_0 ), .data_1 ( serial_out_1 ), 295 | .RCLK ( serial_out_rclk ), .SRCLK ( serial_out_srclk ), 296 | .SER_0 ( serial_out_ser_0 ), .SER_1 ( serial_out_ser_1 ) 297 | ); 298 | 299 | driver_74lv165 u_driver_74lv165 ( 300 | .clk ( clk ), .resetn ( resetn ), 301 | .data_0 ( serial_in_0 ), .data_1 ( serial_in_1 ), 302 | .data_2 ( serial_in_2 ), 303 | .RCLK ( serial_in_rclk ), .SH_LDn ( serial_in_shldn ), 304 | .QH_0 ( serial_in_ser_0 ), .QH_1 ( serial_in_ser_1 ), 305 | .QH_2 ( serial_in_ser_2 ) 306 | ); 307 | 308 | assign ser_arr_reg_c_value = 309 | {serial_in_1[22:16], serial_in_0[23:0]}; 310 | assign {ser_arr_sel_value, ser_arr_strt_value} = 311 | {serial_in_2[23:0]}; 312 | assign ser_arr_cmp_value = 313 | {serial_in_1[11:0]}; 314 | 315 | assign pnl_arr_reg_c_value = 316 | {31{pnl_allow_arr}} & ser_arr_reg_c_value; 317 | assign pnl_arr_sel_value = 318 | {12{pnl_allow_arr}} & ser_arr_sel_value; 319 | assign pnl_arr_strt_value = 320 | {12{pnl_allow_arr}} & ser_arr_strt_value; 321 | assign pnl_arr_cmp_value = 322 | {12{pnl_allow_arr}} & ser_arr_cmp_value; 323 | 324 | endmodule 325 | -------------------------------------------------------------------------------- /core/io_unit.v: -------------------------------------------------------------------------------- 1 | /** 2 | * ЭУВВ 3 | * электронный блок устройства ввода и вывода 4 | * 输入输出电子部件 5 | **/ 6 | 7 | module io_unit ( 8 | input clk, 9 | input resetn, 10 | 11 | input order_write_from_op, // pulse, from op 12 | input order_input_from_op, // pulse, from op 13 | input order_output_from_op, // pulse, from op 14 | input start_pulse_from_op, // pulse, from op 15 | 16 | input do_left_shift_c_from_ac, // pulse, from ac 17 | input ac_answer_from_ac, // pulse, from ac 18 | 19 | input mem_write_reply_from_mem, // pulse, from mem 20 | input mem_reply_from_mem, // pulse, from mem 21 | 22 | input start_pulse_from_pnl, // pulse, from pnl 23 | input automatic_from_pnl, // level, from pnl 24 | 25 | input start_input_from_pnl, // pulse, from pnl 26 | input stop_input_from_pnl, // pulse, from pnl 27 | input start_output_from_pnl, // pulse, from pnl 28 | input stop_output_from_pnl, // pulse, from pnl 29 | input input_oct_from_pnl, // level, from pnl 30 | input input_dec_from_pnl, // level, from pnl 31 | input output_oct_from_pnl, // level, from pnl 32 | input output_dec_from_pnl, // level, from pnl 33 | input continuous_input_from_pnl, // level, from pnl 34 | input stop_after_output_from_pnl, // level, from pnl 35 | 36 | input stop_at_cmp_from_pnl, // level, from pnl 37 | input cmp_with_strt_from_pnl, // level, from pnl 38 | input cmp_match_from_strt, // level, from strt 39 | input cmp_match_from_sel, // level, from sel 40 | 41 | output input_active_to_pnl, // level, to pnl 42 | output output_active_to_pnl, // level, to pnl 43 | 44 | output shift_3_bit_to_ac, // level, to ac 45 | output shift_4_bit_to_ac, // level, to ac 46 | 47 | output order_io_to_ac, // pulse, to ac 48 | output do_addr2_to_sel_to_sel, // pulse, to sel 49 | output mem_write_to_mem, // pulse, to mem 50 | output start_pulse_to_pu, // pulse, to pu 51 | 52 | input output_sign_from_ac, // value, from ac 53 | input [ 3:0] output_data_from_au, // value, from au 54 | output [ 4:0] input_data_to_au, // value, to au 55 | 56 | output input_rdy_to_dev, // handshake 57 | input input_val_from_dev, // handshake 58 | input [ 4:0] input_data_from_dev, // value, from dev 59 | 60 | output output_rdy_to_dev, // handshake 61 | input output_ack_from_dev, // handshake 62 | output [ 4:0] output_data_to_dev // value, to dev 63 | ); 64 | 65 | `define IN_IDLE 0 66 | `define IN_RDY 1 67 | `define IN_VAL 2 68 | `define IN_DONE 3 69 | `define IN_NUM 4 70 | `define IN_WRITE 5 71 | 72 | `define OUT_IDLE 7'b0000_000 73 | `define OUT_RDY 0 74 | `define OUT_ACK 1 75 | `define OUT_DONE 2 76 | `define OUT_SHIFT 3 77 | 78 | // input statement machine 79 | reg input_active; 80 | reg [ 5:0] input_state; 81 | reg [ 5:0] input_state_next; 82 | reg [ 4:0] reg_input; 83 | 84 | wire input_is_num; 85 | wire input_is_write; 86 | wire input_is_end; 87 | wire input_is_sel; 88 | 89 | wire order_io_from_input; 90 | wire order_write_from_input; 91 | wire stop_input_from_input; 92 | 93 | // output statement machine 94 | reg output_active; 95 | reg [ 3:0] output_state_a; 96 | reg [ 3:0] output_state_b; 97 | reg [ 3:0] output_state_a_next; 98 | reg [ 3:0] output_state_b_next; 99 | 100 | wire output_sign; 101 | wire output_num; 102 | wire output_finish; 103 | 104 | wire order_io_from_output; 105 | wire start_pulse_from_output; 106 | wire stop_output_from_output; 107 | 108 | // order_write & start_pulse 109 | reg order_write_r; 110 | wire start_pulse_delay; 111 | reg start_pulse_r; 112 | wire start_pulse_auto; 113 | wire stop_because_cmp; 114 | reg stop_because_cmp_r; 115 | 116 | // input statement machine 117 | always @(posedge clk) begin 118 | if (~resetn) begin 119 | input_active <= 1'b0; 120 | end else if (stop_input_from_input || stop_input_from_pnl) begin 121 | input_active <= 1'b0; 122 | end else if ((order_input_from_op || start_input_from_pnl) && !output_active) begin 123 | input_active <= 1'b1; 124 | end 125 | end 126 | assign input_active_to_pnl = input_active; 127 | 128 | always @(posedge clk) begin 129 | if (~resetn) begin 130 | input_state <= 0; 131 | // input_state[`IN_IDLE] <= 1; 132 | // ? need clear signal? 133 | end else begin 134 | input_state <= input_state_next; 135 | end 136 | end 137 | 138 | always @(*) begin 139 | input_state_next = 0; 140 | case (1'b1) 141 | input_state[`IN_IDLE]: begin 142 | if (input_active) begin 143 | input_state_next[`IN_RDY] = 1; 144 | end else begin 145 | input_state_next[`IN_IDLE] = 1; 146 | end 147 | end 148 | input_state[`IN_RDY]: begin 149 | if (input_val_from_dev) begin 150 | input_state_next[`IN_VAL] = 1; 151 | end else begin 152 | input_state_next[`IN_RDY] = 1; 153 | end 154 | end 155 | input_state[`IN_VAL]: begin 156 | if (!input_val_from_dev) begin 157 | input_state_next[`IN_DONE] = 1; 158 | end else begin 159 | input_state_next[`IN_VAL] = 1; 160 | end 161 | end 162 | input_state[`IN_DONE]: begin 163 | if (input_is_num) begin 164 | input_state_next[`IN_NUM] = 1; 165 | end else if (input_is_write) begin 166 | input_state_next[`IN_WRITE] = 1; 167 | end else begin 168 | input_state_next[`IN_IDLE] = 1; 169 | end 170 | end 171 | input_state[`IN_NUM]: begin 172 | if (ac_answer_from_ac) begin 173 | input_state_next[`IN_IDLE] = 1; 174 | end else begin 175 | input_state_next[`IN_NUM] = 1; 176 | end 177 | end 178 | input_state[`IN_WRITE]: begin 179 | if (mem_write_reply_from_mem) begin 180 | input_state_next[`IN_IDLE] = 1; 181 | end else begin 182 | input_state_next[`IN_WRITE] = 1; 183 | end 184 | end 185 | default: begin 186 | input_state_next[`IN_IDLE] = 1; 187 | end 188 | endcase 189 | end 190 | 191 | assign input_rdy_to_dev = input_state[`IN_RDY]; 192 | 193 | always @(posedge clk) begin 194 | if (~resetn) begin 195 | reg_input <= 5'b0; 196 | end else if (input_state[`IN_RDY] && input_val_from_dev) begin 197 | reg_input <= input_data_from_dev; 198 | end else if (do_left_shift_c_from_ac) begin 199 | reg_input <= {reg_input[3:0], 1'b0}; 200 | end 201 | end 202 | assign input_data_to_au = 203 | {5{input_active}} & reg_input; 204 | 205 | assign input_is_num = 206 | (reg_input & 5'b10000) == 5'b10000; 207 | assign input_is_write = 208 | (reg_input & 5'b10111) == 5'b00110; 209 | assign input_is_end = 210 | (reg_input & 5'b10111) == 5'b00111; 211 | assign input_is_sel = 212 | (reg_input & 5'b10111) == 5'b00001; 213 | 214 | assign order_io_from_input = 215 | input_state[`IN_DONE] && input_is_num; 216 | assign order_write_from_input = 217 | input_state[`IN_DONE] && input_is_write; 218 | assign do_addr2_to_sel_to_sel = 219 | input_state[`IN_DONE] && input_is_sel; 220 | assign stop_input_from_input = 221 | input_state[`IN_DONE] && ( 222 | (input_is_write && !continuous_input_from_pnl) || 223 | input_is_end 224 | ); 225 | 226 | // output statement machine 227 | always @(posedge clk) begin 228 | if (~resetn) begin 229 | output_active <= 1'b0; 230 | end else if (stop_output_from_output || stop_output_from_pnl) begin 231 | output_active <= 1'b0; 232 | end else if ((order_output_from_op || start_output_from_pnl) && !input_active) begin 233 | output_active <= 1'b1; 234 | end 235 | end 236 | assign output_active_to_pnl = output_active; 237 | 238 | always @(posedge clk) begin 239 | if (~resetn) begin 240 | output_state_a <= 4'd0; 241 | output_state_b <= 4'b0000; 242 | end else begin 243 | output_state_a <= output_state_a_next; 244 | output_state_b <= output_state_b_next; 245 | end 246 | end 247 | 248 | always @(*) begin 249 | if (output_state_b[`OUT_DONE]) begin 250 | if (output_finish) begin 251 | output_state_a_next = 4'd0; 252 | end else begin 253 | output_state_a_next = output_state_a + 4'd1; 254 | end 255 | end else begin 256 | output_state_a_next = output_state_a; 257 | end 258 | 259 | output_state_b_next = 0; 260 | case (1'b1) 261 | output_state_b[`OUT_RDY]: begin 262 | if (output_ack_from_dev) begin 263 | output_state_b_next[`OUT_ACK] = 1; 264 | end else begin 265 | output_state_b_next[`OUT_RDY] = 1; 266 | end 267 | end 268 | output_state_b[`OUT_ACK]: begin 269 | if (~output_ack_from_dev) begin 270 | output_state_b_next[`OUT_DONE] = 1; 271 | end else begin 272 | output_state_b_next[`OUT_ACK] = 1; 273 | end 274 | end 275 | output_state_b[`OUT_DONE]: begin 276 | if (!output_finish) begin 277 | if (output_num) begin 278 | output_state_b_next[`OUT_SHIFT] = 1; 279 | end else begin 280 | output_state_b_next[`OUT_RDY] = 1; 281 | end 282 | end 283 | end 284 | output_state_b[`OUT_SHIFT]: begin 285 | if (ac_answer_from_ac) begin 286 | output_state_b_next[`OUT_RDY] = 1; 287 | end else begin 288 | output_state_b_next[`OUT_SHIFT] = 1; 289 | end 290 | end 291 | default: begin 292 | if (output_active) begin 293 | output_state_b_next[`OUT_RDY] = 1; 294 | end 295 | end 296 | endcase 297 | end 298 | 299 | assign output_rdy_to_dev = output_state_b[`OUT_RDY]; 300 | 301 | assign output_data_to_dev = 302 | ({5{output_sign}} & {4'b1111, output_sign_from_ac}) | 303 | ({5{output_num && output_oct_from_pnl}} & {2'b10, output_data_from_au[3:1]}) | 304 | ({5{output_num && output_dec_from_pnl}} & {1'b1, output_data_from_au[3:0]}) | 305 | ({5{output_finish}} & 5'b00110); 306 | 307 | assign output_sign = 308 | output_state_a == 4'd00; 309 | assign output_num = 310 | output_state_a == 4'd01 || 311 | output_state_a == 4'd02 || 312 | output_state_a == 4'd03 || 313 | output_state_a == 4'd04 || 314 | output_state_a == 4'd05 || 315 | output_state_a == 4'd06 || 316 | output_state_a == 4'd07 || 317 | (output_oct_from_pnl && output_state_a == 4'd08) || 318 | (output_oct_from_pnl && output_state_a == 4'd09) || 319 | (output_oct_from_pnl && output_state_a == 4'd10); 320 | assign output_finish = 321 | (output_oct_from_pnl && output_state_a == 4'd11) || 322 | (output_dec_from_pnl && output_state_a == 4'd08); 323 | 324 | assign order_io_from_output = 325 | output_num && output_state_b[`OUT_DONE]; 326 | assign start_pulse_from_output = 327 | output_finish && output_state_b[`OUT_DONE] && 328 | !stop_after_output_from_pnl; 329 | assign stop_output_from_output = 330 | output_finish && output_state_b[`OUT_DONE]; 331 | 332 | // level for oct/dec 333 | assign shift_3_bit_to_ac = 334 | (input_active && input_oct_from_pnl) || 335 | (output_active && output_oct_from_pnl); 336 | assign shift_4_bit_to_ac = 337 | (input_active && input_dec_from_pnl) || 338 | (output_active && output_dec_from_pnl); 339 | 340 | // pulses 341 | assign start_pulse_delay = 342 | start_pulse_from_op || 343 | (mem_reply_from_mem && !order_output_from_op); 344 | 345 | always @(posedge clk) begin 346 | if (~resetn) begin 347 | order_write_r <= 1'b0; 348 | start_pulse_r <= 1'b0; 349 | end else begin 350 | order_write_r <= order_write_from_op; 351 | start_pulse_r <= start_pulse_delay; 352 | end 353 | end 354 | 355 | always @(posedge clk) begin 356 | if (~resetn) begin 357 | stop_because_cmp_r <= 1'b0; 358 | end else begin 359 | stop_because_cmp_r <= stop_because_cmp; 360 | end 361 | end 362 | 363 | assign mem_write_to_mem = 364 | order_write_r || order_write_from_input; 365 | 366 | assign start_pulse_auto = 367 | start_pulse_r || start_pulse_from_output; 368 | assign stop_because_cmp = 369 | stop_at_cmp_from_pnl && ( 370 | ( cmp_with_strt_from_pnl && cmp_match_from_strt) || 371 | (!cmp_with_strt_from_pnl && cmp_match_from_sel) 372 | ); 373 | assign start_pulse_to_pu = 374 | start_pulse_from_pnl || ( 375 | automatic_from_pnl && 376 | !stop_because_cmp && !stop_because_cmp_r && 377 | start_pulse_auto 378 | ); 379 | 380 | assign order_io_to_ac = 381 | order_io_from_input || order_io_from_output; 382 | 383 | endmodule 384 | -------------------------------------------------------------------------------- /core/arith_ctrl.v: -------------------------------------------------------------------------------- 1 | /** 2 | * МПД 3 | * местного программного датчика 4 | * 局部程序发送器 5 | **/ 6 | 7 | module arith_ctrl ( 8 | input clk, 9 | input resetn, 10 | 11 | input do_clear_a_from_pu, // pulse, from pu 12 | input do_move_b_to_c_from_pu, // pulse, from pu 13 | input do_move_c_to_b_from_pu, // pulse, from pu 14 | input do_move_c_to_a_from_pu, // pulse, from pu 15 | 16 | input order_add_from_op, // pulse, from op 17 | input order_sub_from_op, // pulse, from op 18 | input order_mul_from_op, // pulse, from op 19 | input order_div_from_op, // pulse, from op 20 | input order_and_from_op, // pulse, from op 21 | input order_io_from_io, // pulse, from io 22 | 23 | input ctrl_abs_from_op, // level, from op 24 | 25 | input shift_3_bit_from_io, // level, from io 26 | input shift_4_bit_from_io, // level, from io 27 | 28 | input read_sign_from_mem, // level, from mem 29 | 30 | input carry_out_from_au, // level, from au 31 | input reg_c1_from_au, // level, from au 32 | input reg_c30_from_au, // level, from au 33 | input reg_b0_from_au, // level, from au 34 | input arr_reg_c_sign_from_pnl, // level, from pnl 35 | 36 | // input do_mem_to_c_from_pu, // level, from pu 37 | input mem_read_reply_from_mem, // pulse, from mem 38 | input do_arr_c_from_pnl, // level, from pnl 39 | 40 | output ac_answer_to_op, // pulse, to op 41 | output ac_answer_to_io, // pulse, to io 42 | 43 | output do_clear_a_to_au, // pulse, to au 44 | output do_clear_b_to_au, // pulse, to au 45 | output do_clear_c_to_au, // pulse, to au 46 | output do_not_a_to_au, // pulse, to au 47 | output do_not_b_to_au, // pulse, to au 48 | output do_sum_to_au, // pulse, to au 49 | output do_and_to_au, // pulse, to au 50 | output do_set_c_30_to_au, // pulse, to au 51 | output do_left_shift_b_to_au, // pulse, to au 52 | output do_left_shift_c_to_au, // pulse, to au 53 | output do_left_shift_c_to_io, // pulse, to io 54 | output do_left_shift_c29_to_au, // pulse, to au 55 | output do_right_shift_bc_to_au, // pulse, to au 56 | output do_move_c_to_a_to_au, // pulse, to au 57 | output do_move_c_to_b_to_au, // pulse, to au 58 | output do_move_b_to_c_to_au, // pulse, to au 59 | output do_mem_to_c_to_au, // pulse, to au 60 | 61 | output reg_a_sign_to_op, // level, to op 62 | output reg_b_sign_to_op, // level, to op 63 | // output reg_b_sign_to_pu, // level, to pu 64 | output reg_c_sign_to_pnl, // level, to pnl 65 | output write_sign_to_mem, // level, to mem 66 | output output_sign_to_io // level, to io 67 | ); 68 | 69 | // counter_r for mul, div, io 70 | reg [ 4:0] counter_r; 71 | 72 | wire counter_clear; 73 | wire counter_clear_mul; 74 | wire counter_clear_div; 75 | wire counter_clear_io; 76 | 77 | wire counter_count; 78 | wire counter_count_mul; 79 | wire counter_count_div; 80 | wire counter_count_io; 81 | 82 | wire counter_finish_mul_div; 83 | wire counter_finish_io; 84 | 85 | // add 86 | reg [ 2:0] add_state; 87 | reg [ 2:0] add_state_next; 88 | wire add_do_sum; 89 | wire add_do_move_b_to_c; 90 | wire add_ac_answer; 91 | 92 | // sub 93 | reg [ 4:0] sub_state; 94 | reg [ 4:0] sub_state_next; 95 | wire sub_do_not_a; 96 | wire sub_do_not_b; 97 | wire sub_do_sign; 98 | wire sub_do_sum; 99 | wire sub_do_move_b_to_c; 100 | wire sub_ac_answer; 101 | 102 | // mul 103 | reg [ 4:0] mul_state; 104 | reg [ 4:0] mul_state_next; 105 | wire mul_do_clear_b; 106 | wire mul_do_sign; 107 | wire mul_do_sum; 108 | wire mul_do_right_shift_bc; 109 | wire mul_do_move_b_to_c; 110 | wire mul_ac_answer; 111 | 112 | // div 113 | reg [ 5:0] div_state; 114 | reg [ 5:0] div_state_next; 115 | wire div_do_not_a; 116 | wire div_do_sign; 117 | wire div_do_left_shift_b; 118 | wire div_do_left_shift_c; 119 | wire div_do_left_shift_c29; 120 | wire div_do_sum; 121 | wire div_do_set_c_30; 122 | wire div_do_move_c_to_b; 123 | wire div_ac_answer; 124 | 125 | // and 126 | reg [ 2:0] and_state; 127 | reg [ 2:0] and_state_next; 128 | wire and_do_and; 129 | wire and_do_move_c_to_b; 130 | wire and_ac_answer; 131 | 132 | // io 133 | reg [ 2:0] io_state; 134 | reg [ 2:0] io_state_next; 135 | wire io_do_left_shift_c; 136 | wire io_do_left_shift_c29; 137 | wire io_ac_answer; 138 | 139 | // sign 140 | wire sign_mul_div; 141 | wire sign_sub; 142 | wire do_move_sign; 143 | 144 | reg reg_a_sign; 145 | reg reg_b_sign; 146 | reg reg_c_sign; 147 | 148 | // counter_r for mul, div, io 149 | always @(posedge clk) begin 150 | if (~resetn) begin 151 | counter_r <= 5'b0; 152 | end else if (do_clear_a_from_pu) begin 153 | counter_r <= 5'b0; 154 | end else if (counter_clear) begin 155 | counter_r <= 5'b0; 156 | end else if (counter_count) begin 157 | counter_r <= counter_r + 5'b1; 158 | end 159 | end 160 | 161 | assign counter_clear = 162 | counter_clear_mul || counter_clear_div || counter_clear_io; 163 | 164 | assign counter_count = 165 | counter_count_mul || counter_count_div || counter_count_io; 166 | 167 | assign counter_finish_mul_div = 168 | counter_r == 5'd29; 169 | assign counter_finish_io = 170 | (shift_3_bit_from_io && counter_r == 5'd2) || 171 | (shift_4_bit_from_io && counter_r == 5'd3); 172 | 173 | // add 174 | always @(posedge clk) begin 175 | if (~resetn) begin 176 | add_state <= 0; 177 | // add_state[0] <= 1'b1; 178 | end else if (do_clear_a_from_pu) begin 179 | add_state <= 0; 180 | // add_state[0] <= 1'b1; 181 | end else begin 182 | add_state <= add_state_next; 183 | end 184 | end 185 | 186 | always @(*) begin 187 | add_state_next = 0; 188 | case (1'b1) 189 | add_state[0]: begin 190 | if (order_add_from_op) begin 191 | add_state_next[1] = 1'b1; 192 | end else begin 193 | add_state_next[0] = 1'b1; 194 | end 195 | end 196 | add_state[1]: begin 197 | if (carry_out_from_au) begin 198 | add_state_next[0] = 1'b1; 199 | end else begin 200 | add_state_next[2] = 1'b1; 201 | end 202 | end 203 | add_state[2]: begin 204 | add_state_next[0] = 1'b1; 205 | end 206 | default: begin 207 | add_state_next[0] = 1'b1; 208 | end 209 | endcase 210 | end 211 | 212 | assign add_do_sum = 213 | add_state[1] && !carry_out_from_au; 214 | assign add_do_move_b_to_c = 215 | add_state[2]; 216 | assign add_ac_answer = 217 | add_state[2]; 218 | 219 | // sub 220 | always @(posedge clk) begin 221 | if (~resetn) begin 222 | sub_state <= 0; 223 | // sub_state[0] <= 1'b1; 224 | end else if (do_clear_a_from_pu) begin 225 | sub_state <= 0; 226 | // sub_state[0] <= 1'b1; 227 | end else begin 228 | sub_state <= sub_state_next; 229 | end 230 | end 231 | 232 | always @(*) begin 233 | sub_state_next = 0; 234 | case (1'b1) 235 | sub_state[0]: begin 236 | if (order_sub_from_op) begin 237 | sub_state_next[1] = 1'b1; 238 | end else begin 239 | sub_state_next[0] = 1'b1; 240 | end 241 | end 242 | sub_state[1]: begin 243 | sub_state_next[2] = 1'b1; 244 | end 245 | sub_state[2]: begin 246 | if (carry_out_from_au) begin 247 | sub_state_next[4] = 1'b1; 248 | end else begin 249 | sub_state_next[3] = 1'b1; 250 | end 251 | end 252 | sub_state[3]: begin 253 | sub_state_next[4] = 1'b1; 254 | end 255 | sub_state[4]: begin 256 | sub_state_next[0] = 1'b1; 257 | end 258 | default: begin 259 | sub_state_next[0] = 1'b1; 260 | end 261 | endcase 262 | end 263 | 264 | assign sub_do_not_a = 265 | sub_state[1] || 266 | (sub_state[2] && !carry_out_from_au); 267 | assign sub_do_not_b = 268 | (sub_state[2] && !carry_out_from_au); 269 | assign sub_do_sign = 270 | sub_state[2]; 271 | assign sub_do_sum = 272 | (sub_state[2] && carry_out_from_au) || 273 | (sub_state[3]); 274 | assign sub_do_move_b_to_c = 275 | (sub_state[4]); 276 | assign sub_ac_answer = 277 | (sub_state[4]); 278 | 279 | // mul 280 | always @(posedge clk) begin 281 | if (~resetn) begin 282 | mul_state <= 0; 283 | // mul_state[0] <= 1'b1; 284 | end else if (do_clear_a_from_pu) begin 285 | mul_state <= 0; 286 | // mul_state[0] <= 1'b1; 287 | end else begin 288 | mul_state <= mul_state_next; 289 | end 290 | end 291 | 292 | always @(*) begin 293 | mul_state_next = 0; 294 | case (1'b1) 295 | mul_state[0]: begin 296 | if (order_mul_from_op) begin 297 | mul_state_next[1] = 1'b1; 298 | end else begin 299 | mul_state_next[0] = 1'b1; 300 | end 301 | end 302 | mul_state[1]: begin 303 | mul_state_next[2] = 1'b1; 304 | end 305 | mul_state[2]: begin 306 | mul_state_next[3] = 1'b1; 307 | end 308 | mul_state[3]: begin 309 | if (counter_finish_mul_div) begin 310 | mul_state_next[4] = 1'b1; 311 | end else begin 312 | mul_state_next[2] = 1'b1; 313 | end 314 | end 315 | mul_state[4]: begin 316 | mul_state_next[0] = 1'b1; 317 | end 318 | default: begin 319 | mul_state_next[0] = 1'b1; 320 | end 321 | endcase 322 | end 323 | 324 | assign mul_do_clear_b = 325 | mul_state[1]; 326 | assign mul_do_sign = 327 | mul_state[1]; 328 | assign mul_do_sum = 329 | reg_c30_from_au && mul_state[2]; 330 | assign mul_do_right_shift_bc = 331 | mul_state[3]; 332 | assign mul_do_move_b_to_c = 333 | mul_state[4]; 334 | assign mul_ac_answer = 335 | mul_state[4]; 336 | assign counter_clear_mul = 337 | mul_state[4]; 338 | assign counter_count_mul = 339 | mul_state[3]; 340 | 341 | // div 342 | always @(posedge clk) begin 343 | if (~resetn) begin 344 | div_state <= 0; 345 | // div_state[0] <= 1'b1; 346 | end else if (do_clear_a_from_pu) begin 347 | div_state <= 0; 348 | // div_state[0] <= 1'b1; 349 | end else begin 350 | div_state <= div_state_next; 351 | end 352 | end 353 | 354 | always @(*) begin 355 | div_state_next = 0; 356 | case (1'b1) 357 | div_state[0]: begin 358 | if (order_div_from_op) begin 359 | div_state_next[1] = 1'b1; 360 | end else begin 361 | div_state_next[0] = 1'b1; 362 | end 363 | end 364 | div_state[1]: begin 365 | div_state_next[2] = 1'b1; 366 | end 367 | div_state[2]: begin 368 | if (carry_out_from_au) begin 369 | div_state_next[0] = 1'b1; 370 | end else begin 371 | div_state_next[3] = 1'b1; 372 | end 373 | end 374 | div_state[3]: begin 375 | div_state_next[4] = 1'b1; 376 | end 377 | div_state[4]: begin 378 | if (counter_finish_mul_div) begin 379 | div_state_next[5] = 1'b1; 380 | end else begin 381 | div_state_next[3] = 1'b1; 382 | end 383 | end 384 | div_state[5]: begin 385 | div_state_next[0] = 1'b1; 386 | end 387 | default: begin 388 | div_state_next[0] = 1'b1; 389 | end 390 | endcase 391 | end 392 | 393 | assign div_do_not_a = 394 | div_state[1]; 395 | assign div_do_sign = 396 | div_state[1]; 397 | assign div_do_left_shift_b = 398 | div_state[3]; 399 | assign div_do_left_shift_c = div_do_left_shift_b; 400 | assign div_do_left_shift_c29 = div_do_left_shift_b; 401 | assign div_do_sum = 402 | div_state[4] && (carry_out_from_au != reg_b0_from_au); 403 | assign div_do_set_c_30 = div_do_sum; 404 | assign div_do_move_c_to_b = 405 | div_state[5]; 406 | assign div_ac_answer = 407 | div_state[5]; 408 | assign counter_clear_div = 409 | div_state[5]; 410 | assign counter_count_div = 411 | div_state[4]; 412 | 413 | // and 414 | always @(posedge clk) begin 415 | if (~resetn) begin 416 | and_state <= 0; 417 | // and_state[0] <= 1'b1; 418 | end else if (do_clear_a_from_pu) begin 419 | and_state <= 0; 420 | // and_state[0] <= 1'b1; 421 | end else begin 422 | and_state <= and_state_next; 423 | end 424 | end 425 | 426 | always @(*) begin 427 | and_state_next = 0; 428 | case (1'b1) 429 | and_state[0]: begin 430 | if (order_and_from_op) begin 431 | and_state_next[1] = 1'b1; 432 | end else begin 433 | and_state_next[0] = 1'b1; 434 | end 435 | end 436 | and_state[1]: begin 437 | and_state_next[2] = 1'b1; 438 | end 439 | and_state[2]: begin 440 | and_state_next[0] = 1'b1; 441 | end 442 | default: begin 443 | and_state_next[0] = 1'b1; 444 | end 445 | endcase 446 | end 447 | 448 | assign and_do_and = 449 | and_state[1]; 450 | assign and_do_move_c_to_b = 451 | and_state[2]; 452 | assign and_ac_answer = 453 | and_state[2]; 454 | 455 | // io 456 | always @(posedge clk) begin 457 | if (~resetn) begin 458 | io_state <= 0; 459 | // io_state[0] <= 1'b1; 460 | end else if (do_clear_a_from_pu) begin 461 | io_state <= 0; 462 | // io_state[0] <= 1'b1; 463 | end else begin 464 | io_state <= io_state_next; 465 | end 466 | end 467 | 468 | always @(*) begin 469 | io_state_next = 0; 470 | case (1'b1) 471 | io_state[0]: begin 472 | if (order_io_from_io) begin 473 | io_state_next[1] = 1'b1; 474 | end else begin 475 | io_state_next[0] = 1'b1; 476 | end 477 | end 478 | io_state[1]: begin 479 | if (counter_finish_io) begin 480 | io_state_next[2] = 1'b1; 481 | end else begin 482 | io_state_next[1] = 1'b1; 483 | end 484 | end 485 | io_state[2]: begin 486 | io_state_next[0] = 1'b1; 487 | end 488 | default: begin 489 | io_state_next[0] = 1'b1; 490 | end 491 | endcase 492 | end 493 | 494 | assign io_do_left_shift_c = 495 | io_state[1]; 496 | assign io_do_left_shift_c29 = 497 | io_state[1] && shift_3_bit_from_io; 498 | assign io_ac_answer = 499 | io_state[2]; 500 | assign counter_clear_io = 501 | io_state[2]; 502 | assign counter_count_io = 503 | io_state[1]; 504 | 505 | // sign 506 | assign sign_mul_div = reg_a_sign ^ reg_b_sign; 507 | assign sign_sub = reg_b_sign ^ !carry_out_from_au; 508 | 509 | always @(posedge clk) begin 510 | if (~resetn) begin 511 | reg_a_sign <= 1'b0; 512 | end else if (do_move_c_to_a_from_pu) begin 513 | reg_a_sign <= reg_c_sign && (!ctrl_abs_from_op); 514 | end else if (do_clear_a_to_au) begin 515 | reg_a_sign <= 1'b0; 516 | end 517 | end 518 | 519 | always @(posedge clk) begin 520 | if (~resetn) begin 521 | reg_b_sign <= 1'b0; 522 | end else if (do_move_c_to_b_from_pu) begin 523 | reg_b_sign <= reg_c_sign && (!ctrl_abs_from_op); 524 | end else if (do_move_b_to_c_from_pu) begin 525 | reg_b_sign <= reg_b_sign && (!ctrl_abs_from_op); 526 | end else if (mul_do_sign || div_do_sign) begin 527 | reg_b_sign <= sign_mul_div; 528 | end else if (sub_do_sign) begin 529 | reg_b_sign <= sign_sub; 530 | end else if (do_clear_b_to_au) begin 531 | reg_b_sign <= 1'b0; 532 | end 533 | end 534 | 535 | always @(posedge clk) begin 536 | if (~resetn) begin 537 | reg_c_sign <= 1'b0; 538 | end else if (do_move_b_to_c_from_pu) begin 539 | reg_c_sign <= reg_b_sign && (!ctrl_abs_from_op); 540 | end else if (do_move_sign) begin 541 | reg_c_sign <= reg_b_sign; 542 | end else if (do_clear_c_to_au) begin 543 | reg_c_sign <= 1'b0; 544 | end else if (do_left_shift_c_to_au) begin 545 | reg_c_sign <= reg_c1_from_au; 546 | end else if (mem_read_reply_from_mem) begin 547 | reg_c_sign <= read_sign_from_mem; 548 | end else if (do_arr_c_from_pnl) begin 549 | reg_c_sign <= arr_reg_c_sign_from_pnl; 550 | end 551 | end 552 | 553 | // output 554 | assign ac_answer_to_op = 555 | add_ac_answer || 556 | sub_ac_answer || 557 | mul_ac_answer || 558 | div_ac_answer || 559 | and_ac_answer; 560 | assign ac_answer_to_io = 561 | io_ac_answer; 562 | assign do_clear_a_to_au = 563 | do_clear_a_from_pu; 564 | assign do_clear_b_to_au = 565 | mul_do_clear_b; 566 | assign do_clear_c_to_au = 567 | 1'b0; 568 | assign do_not_a_to_au = 569 | sub_do_not_a || 570 | div_do_not_a; 571 | assign do_not_b_to_au = 572 | sub_do_not_b; 573 | assign do_sum_to_au = 574 | add_do_sum || 575 | sub_do_sum || 576 | mul_do_sum || 577 | div_do_sum; 578 | assign do_and_to_au = 579 | and_do_and; 580 | assign do_set_c_30_to_au = 581 | div_do_set_c_30; 582 | assign do_left_shift_b_to_au = 583 | div_do_left_shift_b; 584 | assign do_left_shift_c_to_au = 585 | div_do_left_shift_c || 586 | io_do_left_shift_c; 587 | assign do_left_shift_c_to_io = do_left_shift_c_to_au; 588 | assign do_left_shift_c29_to_au = 589 | div_do_left_shift_c29 || 590 | io_do_left_shift_c29; 591 | assign do_right_shift_bc_to_au = 592 | mul_do_right_shift_bc; 593 | assign do_move_c_to_a_to_au = 594 | do_move_c_to_a_from_pu; 595 | assign do_move_c_to_b_to_au = 596 | do_move_c_to_b_from_pu || 597 | div_do_move_c_to_b || 598 | and_do_move_c_to_b; 599 | assign do_move_b_to_c_to_au = 600 | do_move_b_to_c_from_pu || 601 | add_do_move_b_to_c || 602 | sub_do_move_b_to_c || 603 | mul_do_move_b_to_c; 604 | assign do_move_sign = 605 | add_do_move_b_to_c || 606 | sub_do_move_b_to_c || 607 | mul_do_move_b_to_c || 608 | div_do_move_c_to_b || 609 | and_do_move_c_to_b; 610 | assign do_mem_to_c_to_au = 611 | mem_read_reply_from_mem; 612 | 613 | assign reg_a_sign_to_op = reg_a_sign; 614 | assign reg_b_sign_to_op = reg_b_sign; 615 | // assign reg_b_sign_to_pu = reg_b_sign; 616 | assign reg_c_sign_to_pnl = reg_c_sign; 617 | assign write_sign_to_mem = reg_c_sign; 618 | assign output_sign_to_io = reg_c_sign; 619 | 620 | endmodule 621 | -------------------------------------------------------------------------------- /core/core_top.v: -------------------------------------------------------------------------------- 1 | module core_top ( 2 | input clk, 3 | input resetn, 4 | 5 | output dev_input_rdy, // handshake 6 | input dev_input_val, // handshake 7 | 8 | output dev_output_rdy, // handshake 9 | input dev_output_ack, // handshake 10 | 11 | input [ 4:0] dev_input_data, // level 12 | output [ 4:0] dev_output_data, // level 13 | 14 | input pnl_start_pulse, // pulse 15 | input pnl_clear_pu, // pulse 16 | input pnl_automatic, // level 17 | 18 | input pnl_mem_read, // pulse 19 | input pnl_mem_write, // pulse 20 | 21 | input pnl_start_input, // pulse 22 | input pnl_stop_input, // pulse 23 | input pnl_start_output, // pulse 24 | input pnl_stop_output, // pulse 25 | 26 | input pnl_input_dec, // level 27 | input pnl_output_dec, // level 28 | 29 | input pnl_continuous_input, // level 30 | input pnl_stop_after_output, // level 31 | 32 | input pnl_stop_at_cmp, // level 33 | input pnl_cmp_with_strt, // level 34 | 35 | input pnl_do_arr_c, // pulse 36 | input [30:0] pnl_arr_reg_c_value, // level 37 | 38 | input pnl_do_arr_sel, // pulse 39 | input [11:0] pnl_arr_sel_value, // level 40 | 41 | input pnl_do_arr_strt, // pulse 42 | input [11:0] pnl_arr_strt_value, // level 43 | 44 | input [11:0] pnl_arr_cmp_value, // level 45 | 46 | output pnl_input_active, // level 47 | output pnl_output_active, // level 48 | 49 | output [ 5:0] pnl_op_code, // level 50 | output [11:0] pnl_sel_value, // level 51 | output [11:0] pnl_strt_value, // level 52 | output [30:0] pnl_reg_c_value, // level 53 | output [ 2:0] pnl_pu_state // level 54 | ); 55 | 56 | // arith_unit output signals 57 | wire carry_out_from_au_to_ac; 58 | wire reg_b0_from_au_to_ac; 59 | wire reg_c1_from_au_to_ac; 60 | wire reg_c30_from_au_to_ac; 61 | wire [ 5:0] op_code_from_au_to_op; 62 | wire [11:0] addr1_value_from_au_to_sel; 63 | wire [11:0] addr2_value_from_au_to_sel; 64 | wire [ 3:0] output_data_from_au_to_io; 65 | wire [29:0] reg_c_value_from_au_to_pnl; 66 | wire [29:0] write_data_from_au_to_mem; 67 | 68 | // arith_ctrl output signals 69 | wire ac_answer_from_ac_to_op; 70 | wire ac_answer_from_ac_to_io; 71 | wire do_clear_a_from_ac_to_au; 72 | wire do_clear_b_from_ac_to_au; 73 | wire do_clear_c_from_ac_to_au; 74 | wire do_not_a_from_ac_to_au; 75 | wire do_not_b_from_ac_to_au; 76 | wire do_sum_from_ac_to_au; 77 | wire do_and_from_ac_to_au; 78 | wire do_set_c_30_from_ac_to_au; 79 | wire do_left_shift_b_from_ac_to_au; 80 | wire do_left_shift_c_from_ac_to_au; 81 | wire do_left_shift_c_from_ac_to_io; 82 | wire do_left_shift_c29_from_ac_to_au; 83 | wire do_right_shift_bc_from_ac_to_au; 84 | wire do_move_c_to_a_from_ac_to_au; 85 | wire do_move_c_to_b_from_ac_to_au; 86 | wire do_move_b_to_c_from_ac_to_au; 87 | wire do_mem_to_c_from_ac_to_au; 88 | wire reg_a_sign_from_ac_to_op; 89 | wire reg_b_sign_from_ac_to_op; 90 | // wire reg_b_sign_from_ac_to_pu; 91 | wire reg_c_sign_from_ac_to_pnl; 92 | wire write_sign_from_ac_to_mem; 93 | wire output_sign_from_ac_to_io; 94 | 95 | // operator output signals 96 | wire order_add_from_op_to_ac; 97 | wire order_sub_from_op_to_ac; 98 | wire order_mul_from_op_to_ac; 99 | wire order_div_from_op_to_ac; 100 | wire order_and_from_op_to_ac; 101 | wire order_input_from_op_to_io; 102 | wire order_write_from_op_to_io; 103 | wire order_output_from_op_to_io; 104 | wire start_pulse_from_op_to_io; 105 | wire ctrl_abs_from_op_to_ac; 106 | wire [ 5:0] ctrl_bus_from_op_to_pu; 107 | wire [ 5:0] op_code_from_op_to_pnl; 108 | 109 | // select_reg output signals 110 | wire cmp_match_from_sel_to_io; 111 | wire [11:0] sel_value_from_sel_to_strt; 112 | wire [11:0] sel_value_from_sel_to_mem; 113 | wire [11:0] sel_value_from_sel_to_pnl; 114 | 115 | // start_reg output signals 116 | wire cmp_match_from_strt_to_io; 117 | wire [11:0] strt_value_from_strt_to_sel; 118 | wire [11:0] strt_value_from_strt_to_pnl; 119 | 120 | // pulse_unit output signals 121 | wire do_code_to_op_from_pu_to_op; 122 | wire do_inc_strt_from_pu_to_strt; 123 | wire do_addr1_to_sel_from_pu_to_sel; 124 | wire do_addr2_to_sel_from_pu_to_sel; 125 | wire do_strt_to_sel_from_pu_to_sel; 126 | wire do_sel_to_strt_from_pu_to_strt; 127 | // wire do_mem_to_c_from_pu_to_ac; 128 | wire do_clear_a_from_pu_to_ac; 129 | wire do_move_c_to_a_from_pu_to_ac; 130 | wire do_move_c_to_b_from_pu_to_ac; 131 | wire do_move_b_to_c_from_pu_to_ac; 132 | wire do_move_c_to_a_from_pu_to_op; 133 | wire do_move_b_to_c_from_pu_to_op; 134 | wire operate_pulse_from_pu_to_op; 135 | wire mem_read_from_pu_to_mem; 136 | wire [ 2:0] pu_state_from_pu_to_pnl; 137 | 138 | // memory output signals 139 | wire mem_read_reply_from_mem_to_pu; 140 | wire mem_read_reply_from_mem_to_ac; 141 | wire mem_write_reply_from_mem_to_op; 142 | wire mem_write_reply_from_mem_to_io; 143 | wire mem_reply_from_mem_to_io; 144 | wire read_sign_from_mem_to_ac; 145 | wire [29:0] read_data_from_mem_to_au; 146 | 147 | // io_unit output signals 148 | wire shift_3_bit_from_io_to_ac; 149 | wire shift_4_bit_from_io_to_ac; 150 | wire order_io_from_io_to_ac; 151 | wire do_addr2_to_sel_from_io_to_sel; 152 | wire mem_write_from_io_to_mem; 153 | wire start_pulse_from_io_to_pu; 154 | wire [ 4:0] input_data_from_io_to_au; 155 | wire input_rdy_from_io_to_dev; 156 | wire output_rdy_from_io_to_dev; 157 | wire [ 4:0] output_data_from_io_to_dev; 158 | wire input_active_from_io_to_pnl; 159 | wire output_active_from_io_to_pnl; 160 | 161 | // dev signals 162 | wire input_val_from_dev_to_io; 163 | wire output_ack_from_dev_to_io; 164 | wire [4:0] input_data_from_dev_to_io; 165 | 166 | // pnl signals 167 | wire do_arr_c_from_pnl_to_au; 168 | wire do_arr_c_from_pnl_to_ac; 169 | wire arr_reg_c_sign_from_pnl_to_ac; 170 | wire [29:0] arr_reg_c_value_from_pnl_to_au; 171 | 172 | wire do_arr_sel_from_pnl_to_sel; 173 | wire [11:0] arr_sel_data_from_pnl_to_sel; 174 | 175 | wire do_arr_strt_from_pnl_to_strt; 176 | wire [11:0] arr_strt_data_from_pnl_to_strt; 177 | 178 | wire [11:0] cmp_value_from_pnl_to_strt; 179 | wire [11:0] cmp_value_from_pnl_to_sel; 180 | 181 | wire start_pulse_from_pnl_to_io; 182 | wire clear_pu_from_pnl_to_pu; 183 | wire clear_pu_from_pnl_to_op; 184 | wire automatic_from_pnl_to_io; 185 | wire start_input_from_pnl_to_io; 186 | wire stop_input_from_pnl_to_io; 187 | wire start_output_from_pnl_to_io; 188 | wire stop_output_from_pnl_to_io; 189 | 190 | wire mem_read_from_pnl_to_mem; 191 | wire mem_write_from_pnl_to_mem; 192 | 193 | wire input_oct_from_pnl_to_io; 194 | wire input_dec_from_pnl_to_io; 195 | wire output_oct_from_pnl_to_io; 196 | wire output_dec_from_pnl_to_io; 197 | wire continuous_input_from_pnl_to_io; 198 | wire stop_after_output_from_pnl_to_io; 199 | 200 | wire stop_at_cmp_from_pnl_to_io; 201 | wire cmp_with_strt_from_pnl_to_io; 202 | 203 | arith_unit u_arith_unit ( 204 | .clk ( clk ), 205 | .resetn ( resetn ), 206 | .do_clear_a_from_ac ( do_clear_a_from_ac_to_au ), 207 | .do_clear_b_from_ac ( do_clear_b_from_ac_to_au ), 208 | .do_clear_c_from_ac ( do_clear_c_from_ac_to_au ), 209 | .do_not_a_from_ac ( do_not_a_from_ac_to_au ), 210 | .do_not_b_from_ac ( do_not_b_from_ac_to_au ), 211 | .do_sum_from_ac ( do_sum_from_ac_to_au ), 212 | .do_and_from_ac ( do_and_from_ac_to_au ), 213 | .do_set_c_30_from_ac ( do_set_c_30_from_ac_to_au ), 214 | .do_left_shift_b_from_ac ( do_left_shift_b_from_ac_to_au ), 215 | .do_left_shift_c_from_ac ( do_left_shift_c_from_ac_to_au ), 216 | .do_left_shift_c29_from_ac ( do_left_shift_c29_from_ac_to_au ), 217 | .do_right_shift_bc_from_ac ( do_right_shift_bc_from_ac_to_au ), 218 | .do_move_c_to_a_from_ac ( do_move_c_to_a_from_ac_to_au ), 219 | .do_move_c_to_b_from_ac ( do_move_c_to_b_from_ac_to_au ), 220 | .do_move_b_to_c_from_ac ( do_move_b_to_c_from_ac_to_au ), 221 | .input_data_from_io ( input_data_from_io_to_au ), 222 | .do_arr_c_from_pnl ( do_arr_c_from_pnl_to_au ), 223 | .arr_reg_c_value_from_pnl ( arr_reg_c_value_from_pnl_to_au ), 224 | .do_mem_to_c_from_ac ( do_mem_to_c_from_ac_to_au ), 225 | .read_data_from_mem ( read_data_from_mem_to_au ), 226 | 227 | .carry_out_to_ac ( carry_out_from_au_to_ac ), 228 | .reg_b0_to_ac ( reg_b0_from_au_to_ac ), 229 | .reg_c1_to_ac ( reg_c1_from_au_to_ac ), 230 | .reg_c30_to_ac ( reg_c30_from_au_to_ac ), 231 | .op_code_to_op ( op_code_from_au_to_op ), 232 | .addr1_value_to_sel ( addr1_value_from_au_to_sel ), 233 | .addr2_value_to_sel ( addr2_value_from_au_to_sel ), 234 | .output_data_to_io ( output_data_from_au_to_io ), 235 | .reg_c_value_to_pnl ( reg_c_value_from_au_to_pnl ), 236 | .write_data_to_mem ( write_data_from_au_to_mem ) 237 | ); 238 | 239 | arith_ctrl u_arith_ctrl ( 240 | .clk ( clk ), 241 | .resetn ( resetn ), 242 | .do_clear_a_from_pu ( do_clear_a_from_pu_to_ac ), 243 | .do_move_b_to_c_from_pu ( do_move_b_to_c_from_pu_to_ac ), 244 | .do_move_c_to_b_from_pu ( do_move_c_to_b_from_pu_to_ac ), 245 | .do_move_c_to_a_from_pu ( do_move_c_to_a_from_pu_to_ac ), 246 | .order_add_from_op ( order_add_from_op_to_ac ), 247 | .order_sub_from_op ( order_sub_from_op_to_ac ), 248 | .order_mul_from_op ( order_mul_from_op_to_ac ), 249 | .order_div_from_op ( order_div_from_op_to_ac ), 250 | .order_and_from_op ( order_and_from_op_to_ac ), 251 | .order_io_from_io ( order_io_from_io_to_ac ), 252 | .ctrl_abs_from_op ( ctrl_abs_from_op_to_ac ), 253 | .shift_3_bit_from_io ( shift_3_bit_from_io_to_ac ), 254 | .shift_4_bit_from_io ( shift_4_bit_from_io_to_ac ), 255 | .read_sign_from_mem ( read_sign_from_mem_to_ac ), 256 | .carry_out_from_au ( carry_out_from_au_to_ac ), 257 | .reg_c1_from_au ( reg_c1_from_au_to_ac ), 258 | .reg_c30_from_au ( reg_c30_from_au_to_ac ), 259 | .reg_b0_from_au ( reg_b0_from_au_to_ac ), 260 | .arr_reg_c_sign_from_pnl ( arr_reg_c_sign_from_pnl_to_ac ), 261 | // .do_mem_to_c_from_pu ( do_mem_to_c_from_pu_to_ac ), 262 | .mem_read_reply_from_mem ( mem_read_reply_from_mem_to_ac ), 263 | .do_arr_c_from_pnl ( do_arr_c_from_pnl_to_ac ), 264 | 265 | .ac_answer_to_op ( ac_answer_from_ac_to_op ), 266 | .ac_answer_to_io ( ac_answer_from_ac_to_io ), 267 | .do_clear_a_to_au ( do_clear_a_from_ac_to_au ), 268 | .do_clear_b_to_au ( do_clear_b_from_ac_to_au ), 269 | .do_clear_c_to_au ( do_clear_c_from_ac_to_au ), 270 | .do_not_a_to_au ( do_not_a_from_ac_to_au ), 271 | .do_not_b_to_au ( do_not_b_from_ac_to_au ), 272 | .do_sum_to_au ( do_sum_from_ac_to_au ), 273 | .do_and_to_au ( do_and_from_ac_to_au ), 274 | .do_set_c_30_to_au ( do_set_c_30_from_ac_to_au ), 275 | .do_left_shift_b_to_au ( do_left_shift_b_from_ac_to_au ), 276 | .do_left_shift_c_to_au ( do_left_shift_c_from_ac_to_au ), 277 | .do_left_shift_c_to_io ( do_left_shift_c_from_ac_to_io ), 278 | .do_left_shift_c29_to_au ( do_left_shift_c29_from_ac_to_au ), 279 | .do_right_shift_bc_to_au ( do_right_shift_bc_from_ac_to_au ), 280 | .do_move_c_to_a_to_au ( do_move_c_to_a_from_ac_to_au ), 281 | .do_move_c_to_b_to_au ( do_move_c_to_b_from_ac_to_au ), 282 | .do_move_b_to_c_to_au ( do_move_b_to_c_from_ac_to_au ), 283 | .do_mem_to_c_to_au ( do_mem_to_c_from_ac_to_au ), 284 | 285 | .reg_a_sign_to_op ( reg_a_sign_from_ac_to_op ), 286 | .reg_b_sign_to_op ( reg_b_sign_from_ac_to_op ), 287 | // .reg_b_sign_to_pu ( reg_b_sign_from_ac_to_pu ), 288 | .reg_c_sign_to_pnl ( reg_c_sign_from_ac_to_pnl ), 289 | .write_sign_to_mem ( write_sign_from_ac_to_mem ), 290 | .output_sign_to_io ( output_sign_from_ac_to_io ) 291 | ); 292 | 293 | operator u_operator ( 294 | .clk ( clk ), 295 | .resetn ( resetn ), 296 | .clear_pu_from_pnl ( clear_pu_from_pnl_to_op ), 297 | .do_code_to_op_from_pu ( do_code_to_op_from_pu_to_op ), 298 | .operate_pulse_from_pu ( operate_pulse_from_pu_to_op ), 299 | .do_move_b_to_c_from_pu ( do_move_b_to_c_from_pu_to_op ), 300 | .do_move_c_to_a_from_pu ( do_move_c_to_a_from_pu_to_op ), 301 | .mem_write_reply_from_mem ( mem_write_reply_from_mem_to_op ), 302 | .ac_answer_from_ac ( ac_answer_from_ac_to_op ), 303 | .reg_a_sign_from_ac ( reg_a_sign_from_ac_to_op ), 304 | .reg_b_sign_from_ac ( reg_b_sign_from_ac_to_op ), 305 | .op_code_from_au ( op_code_from_au_to_op ), 306 | 307 | .order_add_to_ac ( order_add_from_op_to_ac ), 308 | .order_sub_to_ac ( order_sub_from_op_to_ac ), 309 | .order_mul_to_ac ( order_mul_from_op_to_ac ), 310 | .order_div_to_ac ( order_div_from_op_to_ac ), 311 | .order_and_to_ac ( order_and_from_op_to_ac ), 312 | .order_input_to_io ( order_input_from_op_to_io ), 313 | .order_write_to_io ( order_write_from_op_to_io ), 314 | .order_output_to_io ( order_output_from_op_to_io ), 315 | .start_pulse_to_io ( start_pulse_from_op_to_io ), 316 | .ctrl_abs_to_ac ( ctrl_abs_from_op_to_ac ), 317 | .ctrl_bus_to_pu ( ctrl_bus_from_op_to_pu ), 318 | .op_code_to_pnl ( op_code_from_op_to_pnl ) 319 | ); 320 | 321 | select_reg u_select_reg ( 322 | .clk ( clk ), 323 | .resetn ( resetn ), 324 | .do_arr_sel_from_pnl ( do_arr_sel_from_pnl_to_sel ), 325 | .arr_sel_data_from_pnl ( arr_sel_data_from_pnl_to_sel ), 326 | .do_strt_to_sel_from_pu ( do_strt_to_sel_from_pu_to_sel ), 327 | .strt_value_from_strt ( strt_value_from_strt_to_sel ), 328 | .do_addr1_to_sel_from_pu ( do_addr1_to_sel_from_pu_to_sel ), 329 | .addr1_value_from_au ( addr1_value_from_au_to_sel ), 330 | .do_addr2_to_sel_from_pu ( do_addr2_to_sel_from_pu_to_sel ), 331 | .do_addr2_to_sel_from_io ( do_addr2_to_sel_from_io_to_sel ), 332 | .addr2_value_from_au ( addr2_value_from_au_to_sel ), 333 | .cmp_value_from_pnl ( cmp_value_from_pnl_to_sel ), 334 | 335 | .cmp_match_to_io ( cmp_match_from_sel_to_io ), 336 | .sel_value_to_strt ( sel_value_from_sel_to_strt ), 337 | .sel_value_to_mem ( sel_value_from_sel_to_mem ), 338 | .sel_value_to_pnl ( sel_value_from_sel_to_pnl ) 339 | ); 340 | 341 | start_reg u_start_reg ( 342 | .clk ( clk ), 343 | .resetn ( resetn ), 344 | .do_arr_strt_from_pnl ( do_arr_strt_from_pnl_to_strt ), 345 | .arr_strt_data_from_pnl ( arr_strt_data_from_pnl_to_strt ), 346 | .do_inc_strt_from_pu ( do_inc_strt_from_pu_to_strt ), 347 | .do_sel_to_strt_from_pu ( do_sel_to_strt_from_pu_to_strt ), 348 | .sel_value_from_sel ( sel_value_from_sel_to_strt ), 349 | .cmp_value_from_pnl ( cmp_value_from_pnl_to_strt ), 350 | 351 | .cmp_match_to_io ( cmp_match_from_strt_to_io ), 352 | .strt_value_to_sel ( strt_value_from_strt_to_sel ), 353 | .strt_value_to_pnl ( strt_value_from_strt_to_pnl ) 354 | ); 355 | 356 | pulse_unit u_pulse_unit ( 357 | .clk ( clk ), 358 | .resetn ( resetn ), 359 | .mem_read_reply_from_mem ( mem_read_reply_from_mem_to_pu ), 360 | .start_pulse_from_io ( start_pulse_from_io_to_pu ), 361 | .clear_pu_from_pnl ( clear_pu_from_pnl_to_pu ), 362 | .ctrl_bus_from_op ( ctrl_bus_from_op_to_pu ), 363 | 364 | .do_code_to_op_to_op ( do_code_to_op_from_pu_to_op ), 365 | .do_inc_strt_to_strt ( do_inc_strt_from_pu_to_strt ), 366 | .do_addr1_to_sel_to_sel ( do_addr1_to_sel_from_pu_to_sel ), 367 | .do_addr2_to_sel_to_sel ( do_addr2_to_sel_from_pu_to_sel ), 368 | .do_strt_to_sel_to_sel ( do_strt_to_sel_from_pu_to_sel ), 369 | .do_sel_to_strt_to_strt ( do_sel_to_strt_from_pu_to_strt ), 370 | // .do_mem_to_c_to_ac ( do_mem_to_c_from_pu_to_ac ), 371 | .do_clear_a_to_ac ( do_clear_a_from_pu_to_ac ), 372 | .do_move_c_to_a_to_ac ( do_move_c_to_a_from_pu_to_ac ), 373 | .do_move_c_to_b_to_ac ( do_move_c_to_b_from_pu_to_ac ), 374 | .do_move_b_to_c_to_ac ( do_move_b_to_c_from_pu_to_ac ), 375 | .do_move_c_to_a_to_op ( do_move_c_to_a_from_pu_to_op ), 376 | .do_move_b_to_c_to_op ( do_move_b_to_c_from_pu_to_op ), 377 | .operate_pulse_to_op ( operate_pulse_from_pu_to_op ), 378 | .mem_read_to_mem ( mem_read_from_pu_to_mem ), 379 | .pu_state_to_pnl ( pu_state_from_pu_to_pnl ) 380 | ); 381 | 382 | memory_fpga u_memory ( 383 | // memory_asic u_memory ( 384 | .clk ( clk ), 385 | .resetn ( resetn ), 386 | .mem_read_from_pu ( mem_read_from_pu_to_mem ), 387 | .mem_read_from_pnl ( mem_read_from_pnl_to_mem ), 388 | .mem_write_from_io ( mem_write_from_io_to_mem ), 389 | .mem_write_from_pnl ( mem_write_from_pnl_to_mem ), 390 | .sel_value_from_sel ( sel_value_from_sel_to_mem ), 391 | .write_sign_from_ac ( write_sign_from_ac_to_mem ), 392 | .write_data_from_au ( write_data_from_au_to_mem ), 393 | 394 | .mem_read_reply_to_pu ( mem_read_reply_from_mem_to_pu ), 395 | .mem_read_reply_to_ac ( mem_read_reply_from_mem_to_ac ), 396 | .mem_write_reply_to_op ( mem_write_reply_from_mem_to_op ), 397 | .mem_write_reply_to_io ( mem_write_reply_from_mem_to_io ), 398 | .mem_reply_to_io ( mem_reply_from_mem_to_io ), 399 | .read_sign_to_ac ( read_sign_from_mem_to_ac ), 400 | .read_data_to_au ( read_data_from_mem_to_au ) 401 | ); 402 | 403 | io_unit u_io_unit ( 404 | .clk ( clk ), 405 | .resetn ( resetn ), 406 | .order_write_from_op ( order_write_from_op_to_io ), 407 | .order_input_from_op ( order_input_from_op_to_io ), 408 | .order_output_from_op ( order_output_from_op_to_io ), 409 | .start_pulse_from_op ( start_pulse_from_op_to_io ), 410 | .do_left_shift_c_from_ac ( do_left_shift_c_from_ac_to_io ), 411 | .ac_answer_from_ac ( ac_answer_from_ac_to_io ), 412 | .mem_write_reply_from_mem ( mem_write_reply_from_mem_to_io ), 413 | .mem_reply_from_mem ( mem_reply_from_mem_to_io ), 414 | .start_pulse_from_pnl ( start_pulse_from_pnl_to_io ), 415 | .automatic_from_pnl ( automatic_from_pnl_to_io ), 416 | .start_input_from_pnl ( start_input_from_pnl_to_io ), 417 | .stop_input_from_pnl ( stop_input_from_pnl_to_io ), 418 | .start_output_from_pnl ( start_output_from_pnl_to_io ), 419 | .stop_output_from_pnl ( stop_output_from_pnl_to_io ), 420 | .input_oct_from_pnl ( input_oct_from_pnl_to_io ), 421 | .input_dec_from_pnl ( input_dec_from_pnl_to_io ), 422 | .output_oct_from_pnl ( output_oct_from_pnl_to_io ), 423 | .output_dec_from_pnl ( output_dec_from_pnl_to_io ), 424 | .continuous_input_from_pnl ( continuous_input_from_pnl_to_io ), 425 | .stop_after_output_from_pnl ( stop_after_output_from_pnl_to_io ), 426 | .output_sign_from_ac ( output_sign_from_ac_to_io ), 427 | .output_data_from_au ( output_data_from_au_to_io ), 428 | .input_val_from_dev ( input_val_from_dev_to_io ), 429 | .input_data_from_dev ( input_data_from_dev_to_io ), 430 | .output_ack_from_dev ( output_ack_from_dev_to_io ), 431 | .stop_at_cmp_from_pnl ( stop_at_cmp_from_pnl_to_io ), 432 | .cmp_with_strt_from_pnl ( cmp_with_strt_from_pnl_to_io ), 433 | .cmp_match_from_strt ( cmp_match_from_strt_to_io ), 434 | .cmp_match_from_sel ( cmp_match_from_sel_to_io ), 435 | 436 | .input_active_to_pnl ( input_active_from_io_to_pnl ), 437 | .output_active_to_pnl ( output_active_from_io_to_pnl ), 438 | .shift_3_bit_to_ac ( shift_3_bit_from_io_to_ac ), 439 | .shift_4_bit_to_ac ( shift_4_bit_from_io_to_ac ), 440 | .order_io_to_ac ( order_io_from_io_to_ac ), 441 | .do_addr2_to_sel_to_sel ( do_addr2_to_sel_from_io_to_sel ), 442 | .mem_write_to_mem ( mem_write_from_io_to_mem ), 443 | .start_pulse_to_pu ( start_pulse_from_io_to_pu ), 444 | .input_data_to_au ( input_data_from_io_to_au ), 445 | .input_rdy_to_dev ( input_rdy_from_io_to_dev ), 446 | .output_rdy_to_dev ( output_rdy_from_io_to_dev ), 447 | .output_data_to_dev ( output_data_from_io_to_dev ) 448 | ); 449 | 450 | // dev 451 | assign dev_input_rdy = input_rdy_from_io_to_dev; 452 | assign input_val_from_dev_to_io = dev_input_val; 453 | 454 | assign dev_output_rdy = output_rdy_from_io_to_dev; 455 | assign output_ack_from_dev_to_io = dev_output_ack; 456 | 457 | assign input_data_from_dev_to_io = dev_input_data; 458 | assign dev_output_data = output_data_from_io_to_dev; 459 | 460 | // pnl 461 | assign start_pulse_from_pnl_to_io = pnl_start_pulse; 462 | assign clear_pu_from_pnl_to_pu = pnl_clear_pu; 463 | assign clear_pu_from_pnl_to_op = pnl_clear_pu; 464 | assign automatic_from_pnl_to_io = pnl_automatic; 465 | assign start_input_from_pnl_to_io = pnl_start_input; 466 | assign stop_input_from_pnl_to_io = pnl_stop_input; 467 | assign start_output_from_pnl_to_io = pnl_start_output; 468 | assign stop_output_from_pnl_to_io = pnl_stop_output; 469 | 470 | assign mem_read_from_pnl_to_mem = pnl_mem_read; 471 | assign mem_write_from_pnl_to_mem = pnl_mem_write; 472 | 473 | assign input_oct_from_pnl_to_io = !pnl_input_dec; 474 | assign input_dec_from_pnl_to_io = pnl_input_dec; 475 | assign output_oct_from_pnl_to_io = !pnl_output_dec; 476 | assign output_dec_from_pnl_to_io = pnl_output_dec; 477 | assign continuous_input_from_pnl_to_io = pnl_continuous_input; 478 | assign stop_after_output_from_pnl_to_io = pnl_stop_after_output; 479 | 480 | assign stop_at_cmp_from_pnl_to_io = pnl_stop_at_cmp; 481 | assign cmp_with_strt_from_pnl_to_io = pnl_cmp_with_strt; 482 | 483 | assign do_arr_c_from_pnl_to_au = pnl_do_arr_c; 484 | assign do_arr_c_from_pnl_to_ac = pnl_do_arr_c; 485 | assign {arr_reg_c_sign_from_pnl_to_ac, arr_reg_c_value_from_pnl_to_au} = pnl_arr_reg_c_value; 486 | 487 | assign do_arr_sel_from_pnl_to_sel = pnl_do_arr_sel; 488 | assign arr_sel_data_from_pnl_to_sel = pnl_arr_sel_value; 489 | 490 | assign do_arr_strt_from_pnl_to_strt = pnl_do_arr_strt; 491 | assign arr_strt_data_from_pnl_to_strt = pnl_arr_strt_value; 492 | 493 | assign cmp_value_from_pnl_to_strt = pnl_arr_cmp_value; 494 | assign cmp_value_from_pnl_to_sel = pnl_arr_cmp_value; 495 | 496 | assign pnl_op_code = op_code_from_op_to_pnl; 497 | assign pnl_sel_value = sel_value_from_sel_to_pnl; 498 | assign pnl_strt_value = strt_value_from_strt_to_pnl; 499 | assign pnl_reg_c_value = {reg_c_sign_from_ac_to_pnl, reg_c_value_from_au_to_pnl}; 500 | assign pnl_pu_state = pu_state_from_pu_to_pnl; 501 | 502 | assign pnl_input_active = input_active_from_io_to_pnl; 503 | assign pnl_output_active = output_active_from_io_to_pnl; 504 | 505 | endmodule 506 | --------------------------------------------------------------------------------