├── Makefile ├── main.c ├── ov7670.c └── ov7670.h /Makefile: -------------------------------------------------------------------------------- 1 | 2 | ######### AVR Project Makefile Template ######### 3 | ###### ###### 4 | ###### Copyright (C) 2003-2005,Pat Deegan, ###### 5 | ###### Psychogenic Inc ###### 6 | ###### All Rights Reserved ###### 7 | ###### ###### 8 | ###### You are free to use this code as part ###### 9 | ###### of your own applications provided ###### 10 | ###### you keep this copyright notice intact ###### 11 | ###### and acknowledge its authorship with ###### 12 | ###### the words: ###### 13 | ###### ###### 14 | ###### "Contains software by Pat Deegan of ###### 15 | ###### Psychogenic Inc (www.psychogenic.com)" ###### 16 | ###### ###### 17 | ###### If you use it as part of a web site ###### 18 | ###### please include a link to our site, ###### 19 | ###### http://electrons.psychogenic.com or ###### 20 | ###### http://www.psychogenic.com ###### 21 | ###### ###### 22 | #################################################### 23 | 24 | 25 | ##### This Makefile will make compiling Atmel AVR 26 | ##### micro controller projects simple with Linux 27 | ##### or other Unix workstations and the AVR-GCC 28 | ##### tools. 29 | ##### 30 | ##### It supports C, C++ and Assembly source files. 31 | ##### 32 | ##### Customize the values as indicated below and : 33 | ##### make 34 | ##### make disasm 35 | ##### make stats 36 | ##### make hex 37 | ##### make writeflash 38 | ##### make gdbinit 39 | ##### or make clean 40 | ##### 41 | ##### See the http://electrons.psychogenic.com/ 42 | ##### website for detailed instructions 43 | 44 | 45 | #################################################### 46 | ##### ##### 47 | ##### Configuration ##### 48 | ##### ##### 49 | ##### Customize the values in this section for ##### 50 | ##### your project. MCU, PROJECTNAME and ##### 51 | ##### PRJSRC must be setup for all projects, ##### 52 | ##### the remaining variables are only ##### 53 | ##### relevant to those needing additional ##### 54 | ##### include dirs or libraries and those ##### 55 | ##### who wish to use the avrdude programmer ##### 56 | ##### ##### 57 | ##### See http://electrons.psychogenic.com/ ##### 58 | ##### for further details. ##### 59 | ##### ##### 60 | #################################################### 61 | 62 | 63 | ##### Target Specific Details ##### 64 | ##### Customize these for your project ##### 65 | 66 | # Name of target controller 67 | # (e.g. 'at90s8515', see the available avr-gcc mmcu 68 | # options for possible values) 69 | MCU=atmega328p 70 | 71 | # id to use with programmer 72 | # default: PROGRAMMER_MCU=$(MCU) 73 | # In case the programer used, e.g avrdude, doesn't 74 | # accept the same MCU name as avr-gcc (for example 75 | # for ATmega8s, avr-gcc expects 'atmega8' and 76 | # avrdude requires 'm8') 77 | PROGRAMMER_MCU=m328p 78 | 79 | # Name of our project 80 | # (use a single word, e.g. 'myproject') 81 | PROJECTNAME=sccb 82 | 83 | # Source files 84 | # List C/C++/Assembly source files: 85 | # (list all files to compile, e.g. 'a.c b.cpp as.S'): 86 | # Use .cc, .cpp or .C suffix for C++ files, use .S 87 | # (NOT .s !!!) for assembly source code files. 88 | PRJSRC=main.c ov7670.c 89 | 90 | # additional includes (e.g. -I/path/to/mydir) 91 | INC= 92 | 93 | # libraries to link in (e.g. -lmylib) 94 | LIBS= 95 | 96 | # Optimization level, 97 | # use s (size opt), 1, 2, 3 or 0 (off) 98 | OPTLEVEL=2 99 | 100 | 101 | ##### AVR Dude 'writeflash' options ##### 102 | ##### If you are using the avrdude program 103 | ##### (http://www.bsdhome.com/avrdude/) to write 104 | ##### to the MCU, you can set the following config 105 | ##### options and use 'make writeflash' to program 106 | ##### the device. 107 | 108 | 109 | # programmer id--check the avrdude for complete list 110 | # of available opts. These should include stk500, 111 | # avr910, avrisp, bsd, pony and more. Set this to 112 | # one of the valid "-c PROGRAMMER-ID" values 113 | # described in the avrdude info page. 114 | # 115 | AVRDUDE_PROGRAMMERID=arduino 116 | 117 | # port--serial or parallel port to which your 118 | # hardware programmer is attached 119 | # 120 | AVRDUDE_PORT=/dev/ttyACM0 121 | 122 | 123 | #################################################### 124 | ##### Config Done ##### 125 | ##### ##### 126 | ##### You shouldn't need to edit anything ##### 127 | ##### below to use the makefile but may wish ##### 128 | ##### to override a few of the flags ##### 129 | ##### nonetheless ##### 130 | ##### ##### 131 | #################################################### 132 | 133 | 134 | ##### Flags #### 135 | 136 | # HEXFORMAT -- format for .hex file output 137 | HEXFORMAT=ihex 138 | 139 | # compiler 140 | CFLAGS=-L/usr/lib64/binutils/avr/2.23.1/ldscripts/ -I. $(INC) -g -mmcu=$(MCU) -O$(OPTLEVEL) -flto \ 141 | -fpack-struct -fshort-enums \ 142 | -funsigned-bitfields -funsigned-char \ 143 | -Wall -Wstrict-prototypes \ 144 | -Wa,-ahlms=$(firstword \ 145 | $(filter %.lst, $(<:.c=.lst))) 146 | 147 | # c++ specific flags 148 | CPPFLAGS=-fno-exceptions -flto\ 149 | -Wa,-ahlms=$(firstword \ 150 | $(filter %.lst, $(<:.cpp=.lst))\ 151 | $(filter %.lst, $(<:.cc=.lst)) \ 152 | $(filter %.lst, $(<:.C=.lst))) 153 | 154 | # assembler 155 | ASMFLAGS =-I. $(INC) -mmcu=$(MCU) \ 156 | -x assembler-with-cpp \ 157 | -Wa,-gstabs,-ahlms=$(firstword \ 158 | $(<:.S=.lst) $(<.s=.lst)) 159 | 160 | 161 | # linker 162 | LDFLAGS=-L/usr/lib64/binutils/avr/2.23.1/ldscripts/ -Wl,-gc-sections,-Map,$(TRG).map -mmcu=$(MCU) -flto -O$(OPTLEVEL) $(LIBS) 163 | 164 | ##### executables #### 165 | CC=avr-gcc 166 | OBJCOPY=avr-objcopy 167 | OBJDUMP=avr-objdump 168 | SIZE=avr-size 169 | AVRDUDE=avrdude 170 | REMOVE=rm -f 171 | 172 | ##### automatic target names #### 173 | TRG=$(PROJECTNAME).out 174 | DUMPTRG=$(PROJECTNAME).s 175 | 176 | HEXROMTRG=$(PROJECTNAME).hex 177 | HEXTRG=$(HEXROMTRG) $(PROJECTNAME).ee.hex 178 | GDBINITFILE=gdbinit-$(PROJECTNAME) 179 | 180 | # Define all object files. 181 | 182 | # Start by splitting source files by type 183 | # C++ 184 | CPPFILES=$(filter %.cpp, $(PRJSRC)) 185 | CCFILES=$(filter %.cc, $(PRJSRC)) 186 | BIGCFILES=$(filter %.C, $(PRJSRC)) 187 | # C 188 | CFILES=$(filter %.c, $(PRJSRC)) 189 | # Assembly 190 | ASMFILES=$(filter %.S, $(PRJSRC)) 191 | 192 | 193 | # List all object files we need to create 194 | OBJDEPS=$(CFILES:.c=.o) \ 195 | $(CPPFILES:.cpp=.o)\ 196 | $(BIGCFILES:.C=.o) \ 197 | $(CCFILES:.cc=.o) \ 198 | $(ASMFILES:.S=.o) 199 | 200 | # Define all lst files. 201 | LST=$(filter %.lst, $(OBJDEPS:.o=.lst)) 202 | 203 | # All the possible generated assembly 204 | # files (.s files) 205 | GENASMFILES=$(filter %.s, $(OBJDEPS:.o=.s)) 206 | 207 | 208 | .SUFFIXES : .c .cc .cpp .C .o .out .s .S \ 209 | .hex .ee.hex .h .hh .hpp 210 | 211 | 212 | .PHONY: writeflash clean stats gdbinit stats 213 | 214 | # Make targets: 215 | # all, disasm, stats, hex, writeflash/install, clean 216 | all: $(TRG) 217 | 218 | disasm: $(DUMPTRG) stats 219 | 220 | stats: $(TRG) 221 | $(OBJDUMP) -h $(TRG) 222 | $(SIZE) $(TRG) 223 | 224 | hex: $(HEXTRG) 225 | 226 | 227 | writeflash: hex 228 | $(AVRDUDE) -c $(AVRDUDE_PROGRAMMERID) \ 229 | -p $(PROGRAMMER_MCU) -P $(AVRDUDE_PORT) -e \ 230 | -U flash:w:$(HEXROMTRG) 231 | 232 | install: writeflash 233 | 234 | $(DUMPTRG): $(TRG) 235 | $(OBJDUMP) -S $< > $@ 236 | 237 | 238 | $(TRG): $(OBJDEPS) 239 | $(CC) $(LDFLAGS) -o $(TRG) $(OBJDEPS) 240 | 241 | 242 | #### Generating assembly #### 243 | # asm from C 244 | %.s: %.c 245 | $(CC) -S $(CFLAGS) $< -o $@ 246 | 247 | # asm from (hand coded) asm 248 | %.s: %.S 249 | $(CC) -S $(ASMFLAGS) $< > $@ 250 | 251 | 252 | # asm from C++ 253 | .cpp.s .cc.s .C.s : 254 | $(CC) -S $(CFLAGS) $(CPPFLAGS) $< -o $@ 255 | 256 | 257 | 258 | #### Generating object files #### 259 | # object from C 260 | .c.o: 261 | $(CC) $(CFLAGS) -c $< -o $@ 262 | 263 | 264 | # object from C++ (.cc, .cpp, .C files) 265 | .cc.o .cpp.o .C.o : 266 | $(CC) $(CFLAGS) $(CPPFLAGS) -c $< -o $@ 267 | 268 | # object from asm 269 | .S.o : 270 | $(CC) $(ASMFLAGS) -c $< -o $@ 271 | 272 | 273 | #### Generating hex files #### 274 | # hex files from elf 275 | ##### Generating a gdb initialisation file ##### 276 | .out.hex: 277 | $(OBJCOPY) -j .text \ 278 | -j .data \ 279 | -O $(HEXFORMAT) $< $@ 280 | 281 | .out.ee.hex: 282 | $(OBJCOPY) -j .eeprom \ 283 | --change-section-lma .eeprom=0 \ 284 | -O $(HEXFORMAT) $< $@ 285 | 286 | 287 | ##### Generating a gdb initialisation file ##### 288 | ##### Use by launching simulavr and avr-gdb: ##### 289 | ##### avr-gdb -x gdbinit-myproject ##### 290 | gdbinit: $(GDBINITFILE) 291 | 292 | $(GDBINITFILE): $(TRG) 293 | @echo "file $(TRG)" > $(GDBINITFILE) 294 | 295 | @echo "target remote localhost:1212" \ 296 | >> $(GDBINITFILE) 297 | 298 | @echo "load" >> $(GDBINITFILE) 299 | @echo "break main" >> $(GDBINITFILE) 300 | @echo "continue" >> $(GDBINITFILE) 301 | @echo 302 | @echo "Use 'avr-gdb -x $(GDBINITFILE)'" 303 | 304 | 305 | #### Cleanup #### 306 | clean: 307 | $(REMOVE) $(TRG) $(TRG).map $(DUMPTRG) 308 | $(REMOVE) $(OBJDEPS) 309 | $(REMOVE) $(LST) $(GDBINITFILE) 310 | $(REMOVE) $(GENASMFILES) 311 | $(REMOVE) $(HEXTRG) 312 | 313 | 314 | 315 | ##### EOF ##### 316 | 317 | -------------------------------------------------------------------------------- /main.c: -------------------------------------------------------------------------------- 1 | #define F_CPU 16000000UL 2 | #include 3 | #include 4 | #include 5 | #include 6 | #include 7 | #include 8 | #include "ov7670.h" 9 | //#define qqvga 10 | //#define qvga 11 | //#define rgb565 12 | #define rawRGB 13 | static inline void spiCSt(void){//selects the RAM chip and resets it 14 | //toggles spi CS used for reseting sram 15 | PORTB|=4;//cs high 16 | PORTB&=~4;//cs low 17 | } 18 | static inline void spiWrB(uint8_t dat){ 19 | SPDR=dat; 20 | while(!(SPSR & (1< 4 | #include 5 | #include 6 | #include 7 | static void error_led(void){ 8 | DDRB|=32;//make sure led is output 9 | while(1){//wait for reset 10 | PORTB^=32;// toggle led 11 | _delay_ms(100); 12 | } 13 | } 14 | static void twiStart(void){ 15 | TWCR=_BV(TWINT)| _BV(TWSTA)| _BV(TWEN);//send start 16 | while(!(TWCR & (1< 2 | void wrReg(uint8_t reg,uint8_t dat); 3 | uint8_t rdReg(uint8_t reg); 4 | #define camAddr_WR 0x42 5 | #define camAddr_RD 0x43 6 | /* Registers */ 7 | #define REG_GAIN 0x00 /* Gain lower 8 bits (rest in vref) */ 8 | #define REG_BLUE 0x01 /* blue gain */ 9 | #define REG_RED 0x02 /* red gain */ 10 | #define REG_VREF 0x03 /* Pieces of GAIN, VSTART, VSTOP */ 11 | #define REG_COM1 0x04 /* Control 1 */ 12 | #define COM1_CCIR656 0x40 /* CCIR656 enable */ 13 | #define REG_BAVE 0x05 /* U/B Average level */ 14 | #define REG_GbAVE 0x06 /* Y/Gb Average level */ 15 | #define REG_AECHH 0x07 /* AEC MS 5 bits */ 16 | #define REG_RAVE 0x08 /* V/R Average level */ 17 | #define REG_COM2 0x09 /* Control 2 */ 18 | #define COM2_SSLEEP 0x10 /* Soft sleep mode */ 19 | #define REG_PID 0x0a /* Product ID MSB */ 20 | #define REG_VER 0x0b /* Product ID LSB */ 21 | #define REG_COM3 0x0c /* Control 3 */ 22 | #define COM3_SWAP 0x40 /* Byte swap */ 23 | #define COM3_SCALEEN 0x08 /* Enable scaling */ 24 | #define COM3_DCWEN 0x04 /* Enable downsamp/crop/window */ 25 | #define REG_COM4 0x0d /* Control 4 */ 26 | #define REG_COM5 0x0e /* All "reserved" */ 27 | #define REG_COM6 0x0f /* Control 6 */ 28 | #define REG_AECH 0x10 /* More bits of AEC value */ 29 | #define REG_CLKRC 0x11 /* Clocl control */ 30 | #define CLK_EXT 0x40 /* Use external clock directly */ 31 | #define CLK_SCALE 0x3f /* Mask for internal clock scale */ 32 | #define REG_COM7 0x12 /* Control 7 */ 33 | #define COM7_RESET 0x80 /* Register reset */ 34 | #define COM7_FMT_MASK 0x38 35 | #define COM7_FMT_VGA 0x00 36 | #define COM7_FMT_CIF 0x20 /* CIF format */ 37 | #define COM7_FMT_QVGA 0x10 /* QVGA format */ 38 | #define COM7_FMT_QCIF 0x08 /* QCIF format */ 39 | #define COM7_RGB 0x04 /* bits 0 and 2 - RGB format */ 40 | #define COM7_YUV 0x00 /* YUV */ 41 | #define COM7_BAYER 0x01 /* Bayer format */ 42 | #define COM7_PBAYER 0x05 /* "Processed bayer" */ 43 | #define REG_COM8 0x13 /* Control 8 */ 44 | #define COM8_FASTAEC 0x80 /* Enable fast AGC/AEC */ 45 | #define COM8_AECSTEP 0x40 /* Unlimited AEC step size */ 46 | #define COM8_BFILT 0x20 /* Band filter enable */ 47 | #define COM8_AGC 0x04 /* Auto gain enable */ 48 | #define COM8_AWB 0x02 /* White balance enable */ 49 | #define COM8_AEC 0x01 /* Auto exposure enable */ 50 | #define REG_COM9 0x14 /* Control 9 - gain ceiling */ 51 | #define REG_COM10 0x15 /* Control 10 */ 52 | #define COM10_HSYNC 0x40 /* HSYNC instead of HREF */ 53 | #define COM10_PCLK_HB 0x20 /* Suppress PCLK on horiz blank */ 54 | #define COM10_HREF_REV 0x08 /* Reverse HREF */ 55 | #define COM10_VS_LEAD 0x04 /* VSYNC on clock leading edge */ 56 | #define COM10_VS_NEG 0x02 /* VSYNC negative */ 57 | #define COM10_HS_NEG 0x01 /* HSYNC negative */ 58 | #define REG_HSTART 0x17 /* Horiz start high bits */ 59 | #define REG_HSTOP 0x18 /* Horiz stop high bits */ 60 | #define REG_VSTART 0x19 /* Vert start high bits */ 61 | #define REG_VSTOP 0x1a /* Vert stop high bits */ 62 | #define REG_PSHFT 0x1b /* Pixel delay after HREF */ 63 | #define REG_MIDH 0x1c /* Manuf. ID high */ 64 | #define REG_MIDL 0x1d /* Manuf. ID low */ 65 | #define REG_MVFP 0x1e /* Mirror / vflip */ 66 | #define MVFP_MIRROR 0x20 /* Mirror image */ 67 | #define MVFP_FLIP 0x10 /* Vertical flip */ 68 | 69 | #define REG_AEW 0x24 /* AGC upper limit */ 70 | #define REG_AEB 0x25 /* AGC lower limit */ 71 | #define REG_VPT 0x26 /* AGC/AEC fast mode op region */ 72 | #define REG_HSYST 0x30 /* HSYNC rising edge delay */ 73 | #define REG_HSYEN 0x31 /* HSYNC falling edge delay */ 74 | #define REG_HREF 0x32 /* HREF pieces */ 75 | #define REG_TSLB 0x3a /* lots of stuff */ 76 | #define TSLB_YLAST 0x04 /* UYVY or VYUY - see com13 */ 77 | #define REG_COM11 0x3b /* Control 11 */ 78 | #define COM11_NIGHT 0x80 /* NIght mode enable */ 79 | #define COM11_NMFR 0x60 /* Two bit NM frame rate */ 80 | #define COM11_HZAUTO 0x10 /* Auto detect 50/60 Hz */ 81 | #define COM11_50HZ 0x08 /* Manual 50Hz select */ 82 | #define COM11_EXP 0x02 83 | #define REG_COM12 0x3c /* Control 12 */ 84 | #define COM12_HREF 0x80 /* HREF always */ 85 | #define REG_COM13 0x3d /* Control 13 */ 86 | #define COM13_GAMMA 0x80 /* Gamma enable */ 87 | #define COM13_UVSAT 0x40 /* UV saturation auto adjustment */ 88 | #define COM13_UVSWAP 0x01 /* V before U - w/TSLB */ 89 | #define REG_COM14 0x3e /* Control 14 */ 90 | #define COM14_DCWEN 0x10 /* DCW/PCLK-scale enable */ 91 | #define REG_EDGE 0x3f /* Edge enhancement factor */ 92 | #define REG_COM15 0x40 /* Control 15 */ 93 | #define COM15_R10F0 0x00 /* Data range 10 to F0 */ 94 | #define COM15_R01FE 0x80 /* 01 to FE */ 95 | #define COM15_R00FF 0xc0 /* 00 to FF */ 96 | #define COM15_RGB565 0x10 /* RGB565 output */ 97 | #define COM15_RGB555 0x30 /* RGB555 output */ 98 | #define REG_COM16 0x41 /* Control 16 */ 99 | #define COM16_AWBGAIN 0x08 /* AWB gain enable */ 100 | #define REG_COM17 0x42 /* Control 17 */ 101 | #define COM17_AECWIN 0xc0 /* AEC window - must match COM4 */ 102 | #define COM17_CBAR 0x08 /* DSP Color bar */ 103 | 104 | /* 105 | * This matrix defines how the colors are generated, must be 106 | * tweaked to adjust hue and saturation. 107 | * 108 | * Order: v-red, v-green, v-blue, u-red, u-green, u-blue 109 | * 110 | * They are nine-bit signed quantities, with the sign bit 111 | * stored in 0x58. Sign for v-red is bit 0, and up from there. 112 | */ 113 | #define REG_CMATRIX_BASE 0x4f 114 | #define CMATRIX_LEN 6 115 | #define REG_CMATRIX_SIGN 0x58 116 | 117 | 118 | #define REG_BRIGHT 0x55 /* Brightness */ 119 | #define REG_CONTRAS 0x56 /* Contrast control */ 120 | 121 | #define REG_GFIX 0x69 /* Fix gain control */ 122 | 123 | #define REG_REG76 0x76 /* OV's name */ 124 | #define R76_BLKPCOR 0x80 /* Black pixel correction enable */ 125 | #define R76_WHTPCOR 0x40 /* White pixel correction enable */ 126 | 127 | #define REG_RGB444 0x8c /* RGB 444 control */ 128 | #define R444_ENABLE 0x02 /* Turn on RGB444, overrides 5x5 */ 129 | #define R444_RGBX 0x01 /* Empty nibble at end */ 130 | 131 | #define REG_HAECC1 0x9f /* Hist AEC/AGC control 1 */ 132 | #define REG_HAECC2 0xa0 /* Hist AEC/AGC control 2 */ 133 | 134 | #define REG_BD50MAX 0xa5 /* 50hz banding step limit */ 135 | #define REG_HAECC3 0xa6 /* Hist AEC/AGC control 3 */ 136 | #define REG_HAECC4 0xa7 /* Hist AEC/AGC control 4 */ 137 | #define REG_HAECC5 0xa8 /* Hist AEC/AGC control 5 */ 138 | #define REG_HAECC6 0xa9 /* Hist AEC/AGC control 6 */ 139 | #define REG_HAECC7 0xaa /* Hist AEC/AGC control 7 */ 140 | #define REG_BD60MAX 0xab /* 60hz banding step limit */ 141 | 142 | 143 | #define REG_GAIN 0x00 /* Gain lower 8 bits (rest in vref) */ 144 | #define REG_BLUE 0x01 /* blue gain */ 145 | #define REG_RED 0x02 /* red gain */ 146 | #define REG_VREF 0x03 /* Pieces of GAIN, VSTART, VSTOP */ 147 | #define REG_COM1 0x04 /* Control 1 */ 148 | #define COM1_CCIR656 0x40 /* CCIR656 enable */ 149 | #define REG_BAVE 0x05 /* U/B Average level */ 150 | #define REG_GbAVE 0x06 /* Y/Gb Average level */ 151 | #define REG_AECHH 0x07 /* AEC MS 5 bits */ 152 | #define REG_RAVE 0x08 /* V/R Average level */ 153 | #define REG_COM2 0x09 /* Control 2 */ 154 | #define COM2_SSLEEP 0x10 /* Soft sleep mode */ 155 | #define REG_PID 0x0a /* Product ID MSB */ 156 | #define REG_VER 0x0b /* Product ID LSB */ 157 | #define REG_COM3 0x0c /* Control 3 */ 158 | #define COM3_SWAP 0x40 /* Byte swap */ 159 | #define COM3_SCALEEN 0x08 /* Enable scaling */ 160 | #define COM3_DCWEN 0x04 /* Enable downsamp/crop/window */ 161 | #define REG_COM4 0x0d /* Control 4 */ 162 | #define REG_COM5 0x0e /* All "reserved" */ 163 | #define REG_COM6 0x0f /* Control 6 */ 164 | #define REG_AECH 0x10 /* More bits of AEC value */ 165 | #define REG_CLKRC 0x11 /* Clocl control */ 166 | #define CLK_EXT 0x40 /* Use external clock directly */ 167 | #define CLK_SCALE 0x3f /* Mask for internal clock scale */ 168 | #define REG_COM7 0x12 /* Control 7 */ 169 | #define COM7_RESET 0x80 /* Register reset */ 170 | #define COM7_FMT_MASK 0x38 171 | #define COM7_FMT_VGA 0x00 172 | #define COM7_FMT_CIF 0x20 /* CIF format */ 173 | #define COM7_FMT_QVGA 0x10 /* QVGA format */ 174 | #define COM7_FMT_QCIF 0x08 /* QCIF format */ 175 | #define COM7_RGB 0x04 /* bits 0 and 2 - RGB format */ 176 | #define COM7_YUV 0x00 /* YUV */ 177 | #define COM7_BAYER 0x01 /* Bayer format */ 178 | #define COM7_PBAYER 0x05 /* "Processed bayer" */ 179 | #define REG_COM8 0x13 /* Control 8 */ 180 | #define COM8_FASTAEC 0x80 /* Enable fast AGC/AEC */ 181 | #define COM8_AECSTEP 0x40 /* Unlimited AEC step size */ 182 | #define COM8_BFILT 0x20 /* Band filter enable */ 183 | #define COM8_AGC 0x04 /* Auto gain enable */ 184 | #define COM8_AWB 0x02 /* White balance enable */ 185 | #define COM8_AEC 0x01 /* Auto exposure enable */ 186 | #define REG_COM9 0x14 /* Control 9 - gain ceiling */ 187 | #define REG_COM10 0x15 /* Control 10 */ 188 | #define COM10_HSYNC 0x40 /* HSYNC instead of HREF */ 189 | #define COM10_PCLK_HB 0x20 /* Suppress PCLK on horiz blank */ 190 | #define COM10_HREF_REV 0x08 /* Reverse HREF */ 191 | #define COM10_VS_LEAD 0x04 /* VSYNC on clock leading edge */ 192 | #define COM10_VS_NEG 0x02 /* VSYNC negative */ 193 | #define COM10_HS_NEG 0x01 /* HSYNC negative */ 194 | #define REG_HSTART 0x17 /* Horiz start high bits */ 195 | #define REG_HSTOP 0x18 /* Horiz stop high bits */ 196 | #define REG_VSTART 0x19 /* Vert start high bits */ 197 | #define REG_VSTOP 0x1a /* Vert stop high bits */ 198 | #define REG_PSHFT 0x1b /* Pixel delay after HREF */ 199 | #define REG_MIDH 0x1c /* Manuf. ID high */ 200 | #define REG_MIDL 0x1d /* Manuf. ID low */ 201 | #define REG_MVFP 0x1e /* Mirror / vflip */ 202 | #define MVFP_MIRROR 0x20 /* Mirror image */ 203 | #define MVFP_FLIP 0x10 /* Vertical flip */ 204 | #define REG_AEW 0x24 /* AGC upper limit */ 205 | #define REG_AEB 0x25 /* AGC lower limit */ 206 | #define REG_VPT 0x26 /* AGC/AEC fast mode op region */ 207 | #define REG_HSYST 0x30 /* HSYNC rising edge delay */ 208 | #define REG_HSYEN 0x31 /* HSYNC falling edge delay */ 209 | #define REG_HREF 0x32 /* HREF pieces */ 210 | #define REG_TSLB 0x3a /* lots of stuff */ 211 | #define TSLB_YLAST 0x04 /* UYVY or VYUY - see com13 */ 212 | #define REG_COM11 0x3b /* Control 11 */ 213 | #define COM11_NIGHT 0x80 /* NIght mode enable */ 214 | #define COM11_NMFR 0x60 /* Two bit NM frame rate */ 215 | #define COM11_HZAUTO 0x10 /* Auto detect 50/60 Hz */ 216 | #define COM11_50HZ 0x08 /* Manual 50Hz select */ 217 | #define COM11_EXP 0x02 218 | #define REG_COM12 0x3c /* Control 12 */ 219 | #define COM12_HREF 0x80 /* HREF always */ 220 | #define REG_COM13 0x3d /* Control 13 */ 221 | #define COM13_GAMMA 0x80 /* Gamma enable */ 222 | #define COM13_UVSAT 0x40 /* UV saturation auto adjustment */ 223 | #define COM13_UVSWAP 0x01 /* V before U - w/TSLB */ 224 | #define REG_COM14 0x3e /* Control 14 */ 225 | #define COM14_DCWEN 0x10 /* DCW/PCLK-scale enable */ 226 | #define REG_EDGE 0x3f /* Edge enhancement factor */ 227 | #define REG_COM15 0x40 /* Control 15 */ 228 | #define COM15_R10F0 0x00 /* Data range 10 to F0 */ 229 | #define COM15_R01FE 0x80 /* 01 to FE */ 230 | #define COM15_R00FF 0xc0 /* 00 to FF */ 231 | #define COM15_RGB565 0x10 /* RGB565 output */ 232 | #define COM15_RGB555 0x30 /* RGB555 output */ 233 | #define REG_COM16 0x41 /* Control 16 */ 234 | #define COM16_AWBGAIN 0x08 /* AWB gain enable */ 235 | #define REG_COM17 0x42 /* Control 17 */ 236 | #define COM17_AECWIN 0xc0 /* AEC window - must match COM4 */ 237 | #define COM17_CBAR 0x08 /* DSP Color bar */ 238 | 239 | #define CMATRIX_LEN 6 240 | #define REG_BRIGHT 0x55 /* Brightness */ 241 | #define REG_REG76 0x76 /* OV's name */ 242 | #define R76_BLKPCOR 0x80 /* Black pixel correction enable */ 243 | #define R76_WHTPCOR 0x40 /* White pixel correction enable */ 244 | #define REG_RGB444 0x8c /* RGB 444 control */ 245 | #define R444_ENABLE 0x02 /* Turn on RGB444, overrides 5x5 */ 246 | #define R444_RGBX 0x01 /* Empty nibble at end */ 247 | #define REG_HAECC1 0x9f /* Hist AEC/AGC control 1 */ 248 | #define REG_HAECC2 0xa0 /* Hist AEC/AGC control 2 */ 249 | #define REG_BD50MAX 0xa5 /* 50hz banding step limit */ 250 | #define REG_HAECC3 0xa6 /* Hist AEC/AGC control 3 */ 251 | #define REG_HAECC4 0xa7 /* Hist AEC/AGC control 4 */ 252 | #define REG_HAECC5 0xa8 /* Hist AEC/AGC control 5 */ 253 | #define REG_HAECC6 0xa9 /* Hist AEC/AGC control 6 */ 254 | #define REG_HAECC7 0xaa /* Hist AEC/AGC control 7 */ 255 | #define REG_BD60MAX 0xab /* 60hz banding step limit */ 256 | 257 | #define MTX1 0x4f /* Matrix Coefficient 1 */ 258 | #define MTX2 0x50 /* Matrix Coefficient 2 */ 259 | #define MTX3 0x51 /* Matrix Coefficient 3 */ 260 | #define MTX4 0x52 /* Matrix Coefficient 4 */ 261 | #define MTX5 0x53 /* Matrix Coefficient 5 */ 262 | #define MTX6 0x54 /* Matrix Coefficient 6 */ 263 | #define REG_CONTRAS 0x56 /* Contrast control */ 264 | #define MTXS 0x58 /* Matrix Coefficient Sign */ 265 | #define AWBC7 0x59 /* AWB Control 7 */ 266 | #define AWBC8 0x5a /* AWB Control 8 */ 267 | #define AWBC9 0x5b /* AWB Control 9 */ 268 | #define AWBC10 0x5c /* AWB Control 10 */ 269 | #define AWBC11 0x5d /* AWB Control 11 */ 270 | #define AWBC12 0x5e /* AWB Control 12 */ 271 | #define REG_GFIX 0x69 /* Fix gain control */ 272 | #define GGAIN 0x6a /* G Channel AWB Gain */ 273 | #define DBLV 0x6b 274 | #define AWBCTR3 0x6c /* AWB Control 3 */ 275 | #define AWBCTR2 0x6d /* AWB Control 2 */ 276 | #define AWBCTR1 0x6e /* AWB Control 1 */ 277 | #define AWBCTR0 0x6f /* AWB Control 0 */ 278 | 279 | 280 | --------------------------------------------------------------------------------