├── MIPS汇编语言程序设计实验 ├── 18329015-郝裕玮-实验一.doc ├── 18329015-郝裕玮-实验一.pdf └── 实验一.asm ├── README.md ├── 单周期CPU ├── 18329015 郝裕玮 02 单周期CPU.pdf ├── Abacus_Verilog_SrcFiles │ ├── Adder_Subtractor.v │ ├── Basys3_Abacus_Top.v │ ├── Binary_to_BCD_B1_bcdout1.v │ ├── Binary_to_BCD_B2_bcdout2.v │ ├── Binary_to_BCD_B_bcdout.v │ ├── Display_QU.v │ ├── Display_REM.v │ ├── Divider.v │ ├── README.txt │ ├── Seg_7_Display.v │ ├── Segment_Scroll.v │ ├── multi_4_4_pp0.v │ ├── multi_4_4_pp1.v │ ├── multi_4_4_pp2.v │ └── multi_4_4_pp3.v ├── Single-Cycle-CPU │ ├── SingleCPU.cache │ │ └── wt │ │ │ ├── gui_handlers.wdf │ │ │ ├── java_command_handlers.wdf │ │ │ ├── project.wpc │ │ │ ├── synthesis.wdf │ │ │ ├── synthesis_details.wdf │ │ │ ├── webtalk_pa.xml │ │ │ └── xsim.wdf │ ├── SingleCPU.hw │ │ ├── SingleCPU.lpr │ │ └── hw_1 │ │ │ └── hw.xml │ ├── SingleCPU.ip_user_files │ │ └── README.txt │ ├── SingleCPU.runs │ │ ├── .jobs │ │ │ ├── vrs_config_1.xml │ │ │ ├── vrs_config_2.xml │ │ │ ├── vrs_config_3.xml │ │ │ ├── vrs_config_4.xml │ │ │ ├── vrs_config_5.xml │ │ │ ├── vrs_config_6.xml │ │ │ └── vrs_config_7.xml │ │ ├── impl_1 │ │ │ ├── .Vivado_Implementation.queue.rst │ │ │ ├── .init_design.begin.rst │ │ │ ├── .init_design.end.rst │ │ │ ├── .opt_design.begin.rst │ │ │ ├── .opt_design.end.rst │ │ │ ├── .phys_opt_design.begin.rst │ │ │ ├── .phys_opt_design.end.rst │ │ │ ├── .place_design.begin.rst │ │ │ ├── .place_design.end.rst │ │ │ ├── .route_design.begin.rst │ │ │ ├── .route_design.end.rst │ │ │ ├── .vivado.begin.rst │ │ │ ├── .vivado.end.rst │ │ │ ├── .write_bitstream.begin.rst │ │ │ ├── .write_bitstream.end.rst │ │ │ ├── Basy3.bit │ │ │ ├── Basy3.tcl │ │ │ ├── Basy3.vdi │ │ │ ├── Basy3_bus_skew_routed.pb │ │ │ ├── Basy3_bus_skew_routed.rpt │ │ │ ├── Basy3_bus_skew_routed.rpx │ │ │ ├── Basy3_clock_utilization_routed.rpt │ │ │ ├── Basy3_control_sets_placed.rpt │ │ │ ├── Basy3_drc_opted.pb │ │ │ ├── Basy3_drc_opted.rpt │ │ │ ├── Basy3_drc_opted.rpx │ │ │ ├── Basy3_drc_routed.pb │ │ │ ├── Basy3_drc_routed.rpt │ │ │ ├── Basy3_drc_routed.rpx │ │ │ ├── Basy3_io_placed.rpt │ │ │ ├── Basy3_methodology_drc_routed.pb │ │ │ ├── Basy3_methodology_drc_routed.rpt │ │ │ ├── Basy3_methodology_drc_routed.rpx │ │ │ ├── Basy3_opt.dcp │ │ │ ├── Basy3_physopt.dcp │ │ │ ├── Basy3_placed.dcp │ │ │ ├── Basy3_power_routed.rpt │ │ │ ├── Basy3_power_routed.rpx │ │ │ ├── Basy3_power_summary_routed.pb │ │ │ ├── Basy3_route_status.pb │ │ │ ├── Basy3_route_status.rpt │ │ │ ├── Basy3_routed.dcp │ │ │ ├── Basy3_timing_summary_routed.pb │ │ │ ├── Basy3_timing_summary_routed.rpt │ │ │ ├── Basy3_timing_summary_routed.rpx │ │ │ ├── Basy3_utilization_placed.pb │ │ │ ├── Basy3_utilization_placed.rpt │ │ │ ├── ISEWrap.js │ │ │ ├── ISEWrap.sh │ │ │ ├── gen_run.xml │ │ │ ├── htr.txt │ │ │ ├── init_design.pb │ │ │ ├── opt_design.pb │ │ │ ├── phys_opt_design.pb │ │ │ ├── place_design.pb │ │ │ ├── project.wdf │ │ │ ├── route_design.pb │ │ │ ├── rundef.js │ │ │ ├── runme.bat │ │ │ ├── runme.log │ │ │ ├── runme.sh │ │ │ ├── usage_statistics_webtalk.html │ │ │ ├── usage_statistics_webtalk.xml │ │ │ ├── vivado.jou │ │ │ ├── vivado.pb │ │ │ └── write_bitstream.pb │ │ └── synth_1 │ │ │ ├── .Vivado_Synthesis.queue.rst │ │ │ ├── .Xil │ │ │ └── Basy3_propImpl.xdc │ │ │ ├── .vivado.begin.rst │ │ │ ├── .vivado.end.rst │ │ │ ├── Basy3.dcp │ │ │ ├── Basy3.tcl │ │ │ ├── Basy3.vds │ │ │ ├── Basy3_utilization_synth.pb │ │ │ ├── Basy3_utilization_synth.rpt │ │ │ ├── ISEWrap.js │ │ │ ├── ISEWrap.sh │ │ │ ├── __synthesis_is_complete__ │ │ │ ├── gen_run.xml │ │ │ ├── htr.txt │ │ │ ├── rundef.js │ │ │ ├── runme.bat │ │ │ ├── runme.log │ │ │ ├── runme.sh │ │ │ ├── vivado.jou │ │ │ └── vivado.pb │ ├── SingleCPU.sim │ │ └── sim_1 │ │ │ └── behav │ │ │ └── xsim │ │ │ ├── compile.bat │ │ │ ├── compile.log │ │ │ ├── elaborate.bat │ │ │ ├── elaborate.log │ │ │ ├── glbl.v │ │ │ ├── sim.tcl │ │ │ ├── sim_behav.wdb │ │ │ ├── sim_vlog.prj │ │ │ ├── simulate.bat │ │ │ ├── simulate.log │ │ │ ├── webtalk.jou │ │ │ ├── webtalk.log │ │ │ ├── webtalk_12628.backup.jou │ │ │ ├── webtalk_12628.backup.log │ │ │ ├── webtalk_12764.backup.jou │ │ │ ├── webtalk_12764.backup.log │ │ │ ├── webtalk_13232.backup.jou │ │ │ ├── webtalk_13232.backup.log │ │ │ ├── webtalk_13564.backup.jou │ │ │ ├── webtalk_13564.backup.log │ │ │ ├── webtalk_8632.backup.jou │ │ │ ├── webtalk_8632.backup.log │ │ │ ├── xelab.pb │ │ │ ├── xsim.dir │ │ │ ├── sim_behav │ │ │ │ ├── Compile_Options.txt │ │ │ │ ├── TempBreakPointFile.txt │ │ │ │ ├── obj │ │ │ │ │ ├── xsim_0.win64.obj │ │ │ │ │ ├── xsim_1.c │ │ │ │ │ └── xsim_1.win64.obj │ │ │ │ ├── webtalk │ │ │ │ │ ├── .xsim_webtallk.info │ │ │ │ │ ├── usage_statistics_ext_xsim.html │ │ │ │ │ └── usage_statistics_ext_xsim.xml │ │ │ │ ├── xsim.dbg │ │ │ │ ├── xsim.mem │ │ │ │ ├── xsim.reloc │ │ │ │ ├── xsim.rlx │ │ │ │ ├── xsim.rtti │ │ │ │ ├── xsim.svtype │ │ │ │ ├── xsim.type │ │ │ │ ├── xsim.xdbg │ │ │ │ ├── xsimSettings.ini │ │ │ │ ├── xsimcrash.log │ │ │ │ ├── xsimk.exe │ │ │ │ └── xsimkernel.log │ │ │ └── xil_defaultlib │ │ │ │ ├── @a@l@u.sdb │ │ │ │ ├── @adder.sdb │ │ │ │ ├── @c@p@u.sdb │ │ │ │ ├── @control@unit.sdb │ │ │ │ ├── @data@mem.sdb │ │ │ │ ├── @ins@mem.sdb │ │ │ │ ├── @ins@select.sdb │ │ │ │ ├── @p@c.sdb │ │ │ │ ├── @register@file.sdb │ │ │ │ ├── glbl.sdb │ │ │ │ ├── sign_zero_extend.sdb │ │ │ │ ├── sim.sdb │ │ │ │ └── xil_defaultlib.rlx │ │ │ ├── xsim.ini │ │ │ ├── xvlog.log │ │ │ └── xvlog.pb │ ├── SingleCPU.srcs │ │ ├── sim_1 │ │ │ └── new │ │ │ │ └── sim.v │ │ └── sources_1 │ │ │ └── new │ │ │ ├── ALU.v │ │ │ ├── Adder.v │ │ │ ├── Basy3.v │ │ │ ├── CPU.v │ │ │ ├── ControlUnit.v │ │ │ ├── DataMem.v │ │ │ ├── InsMem.v │ │ │ ├── InsSelect.v │ │ │ ├── PC.v │ │ │ ├── RegisterFile.v │ │ │ ├── Untitled-1.c │ │ │ ├── clk_show.v │ │ │ ├── display.v │ │ │ ├── remove_shake.v │ │ │ └── sign_zero_extend.v │ ├── SingleCPU.xpr │ ├── vivado.jou │ ├── vivado.log │ ├── vivado_11252.backup.jou │ ├── vivado_11252.backup.log │ ├── vivado_12564.backup.jou │ ├── vivado_12564.backup.log │ ├── vivado_2756.backup.jou │ ├── vivado_2756.backup.log │ ├── vivado_7748.backup.jou │ ├── vivado_7748.backup.log │ ├── vivado_8720.backup.jou │ └── vivado_8720.backup.log ├── 单周期CPU实验报告.doc └── 测试代码段.docx └── 多周期CPU ├── 18329015 郝裕玮 03 多周期CPU.pdf ├── 18329015-郝裕玮-多周期CPU.doc ├── Multiple-Cycle-CPU ├── Multiple-Cycle-CPU.cache │ └── wt │ │ ├── gui_handlers.wdf │ │ ├── java_command_handlers.wdf │ │ ├── project.wpc │ │ ├── synthesis.wdf │ │ ├── synthesis_details.wdf │ │ ├── webtalk_pa.xml │ │ └── xsim.wdf ├── Multiple-Cycle-CPU.hw │ ├── Multiple-Cycle-CPU.lpr │ └── hw_1 │ │ └── hw.xml ├── Multiple-Cycle-CPU.ip_user_files │ └── README.txt ├── Multiple-Cycle-CPU.runs │ ├── .jobs │ │ ├── vrs_config_1.xml │ │ ├── vrs_config_2.xml │ │ ├── vrs_config_3.xml │ │ ├── vrs_config_4.xml │ │ ├── vrs_config_5.xml │ │ ├── vrs_config_6.xml │ │ ├── vrs_config_7.xml │ │ └── vrs_config_8.xml │ ├── impl_1 │ │ ├── ISEWrap.js │ │ ├── ISEWrap.sh │ │ ├── TOP_CPU.tcl │ │ ├── gen_run.xml │ │ ├── htr.txt │ │ ├── project.wdf │ │ ├── rundef.js │ │ ├── runme.bat │ │ └── runme.sh │ └── synth_1 │ │ ├── .Vivado_Synthesis.queue.rst │ │ ├── .Xil │ │ └── Vivado-11840-LAPTOP-K6ETJT1R │ │ │ ├── .lpr │ │ │ ├── realtime │ │ │ ├── TOP_CPU.tcl │ │ │ └── dupFiles.rpt │ │ │ └── wt │ │ │ └── project.wpc │ │ ├── .vivado.begin.rst │ │ ├── .vivado.error.rst │ │ ├── ISEWrap.js │ │ ├── ISEWrap.sh │ │ ├── TOP_CPU.tcl │ │ ├── TOP_CPU.vds │ │ ├── __synthesis_is_running__ │ │ ├── gen_run.xml │ │ ├── htr.txt │ │ ├── rundef.js │ │ ├── runme.bat │ │ ├── runme.log │ │ ├── runme.sh │ │ ├── vivado.jou │ │ └── vivado.pb ├── Multiple-Cycle-CPU.sim │ └── sim_1 │ │ └── behav │ │ └── xsim │ │ ├── compile.bat │ │ ├── compile.log │ │ ├── elaborate.bat │ │ ├── elaborate.log │ │ ├── glbl.v │ │ ├── sim.tcl │ │ ├── sim_behav.wdb │ │ ├── sim_vlog.prj │ │ ├── simulate.bat │ │ ├── simulate.log │ │ ├── webtalk.jou │ │ ├── webtalk.log │ │ ├── webtalk_10220.backup.jou │ │ ├── webtalk_10220.backup.log │ │ ├── webtalk_11028.backup.jou │ │ ├── webtalk_11028.backup.log │ │ ├── webtalk_1860.backup.jou │ │ ├── webtalk_1860.backup.log │ │ ├── webtalk_7364.backup.jou │ │ ├── webtalk_7364.backup.log │ │ ├── xelab.pb │ │ ├── xsim.dir │ │ ├── sim_behav │ │ │ ├── Compile_Options.txt │ │ │ ├── TempBreakPointFile.txt │ │ │ ├── obj │ │ │ │ ├── xsim_0.win64.obj │ │ │ │ ├── xsim_1.c │ │ │ │ └── xsim_1.win64.obj │ │ │ ├── webtalk │ │ │ │ ├── .xsim_webtallk.info │ │ │ │ ├── usage_statistics_ext_xsim.html │ │ │ │ └── usage_statistics_ext_xsim.xml │ │ │ ├── xsim.dbg │ │ │ ├── xsim.mem │ │ │ ├── xsim.reloc │ │ │ ├── xsim.rlx │ │ │ ├── xsim.rtti │ │ │ ├── xsim.svtype │ │ │ ├── xsim.type │ │ │ ├── xsim.xdbg │ │ │ ├── xsimSettings.ini │ │ │ ├── xsimcrash.log │ │ │ ├── xsimk.exe │ │ │ └── xsimkernel.log │ │ └── xil_defaultlib │ │ │ ├── @a@l@u.sdb │ │ │ ├── @adder.sdb │ │ │ ├── @c@p@u.sdb │ │ │ ├── @control@unit.sdb │ │ │ ├── @data@mem.sdb │ │ │ ├── @ins@mem.sdb │ │ │ ├── @left@shift2.sdb │ │ │ ├── @mux2.sdb │ │ │ ├── @mux3.sdb │ │ │ ├── @mux4.sdb │ │ │ ├── @p@c.sdb │ │ │ ├── @register@file.sdb │ │ │ ├── @same@register.sdb │ │ │ ├── glbl.sdb │ │ │ ├── sign_zero_extend.sdb │ │ │ ├── sim.sdb │ │ │ └── xil_defaultlib.rlx │ │ ├── xsim.ini │ │ ├── xvlog.log │ │ └── xvlog.pb ├── Multiple-Cycle-CPU.srcs │ ├── constrs_1 │ │ └── new │ │ │ └── basy3Ports.xdc │ ├── sim_1 │ │ └── new │ │ │ └── sim.v │ └── sources_1 │ │ └── new │ │ ├── ALU.v │ │ ├── Adder.v │ │ ├── CPU.v │ │ ├── ControlUnit.v │ │ ├── DataMem.v │ │ ├── Extend.v │ │ ├── InsMem.v │ │ ├── LeftShift2.v │ │ ├── Mux2.v │ │ ├── Mux3.v │ │ ├── Mux4.v │ │ ├── PC.v │ │ ├── RegisterFile.v │ │ ├── SameRegister.v │ │ ├── TOP_CPU.v │ │ ├── clk_slow.v │ │ ├── display.v │ │ ├── remove_shake.v │ │ └── sign_zero_extend.v ├── Multiple-Cycle-CPU.xpr ├── vivado.jou ├── vivado.log ├── vivado_11744.backup.jou ├── vivado_11744.backup.log ├── vivado_14248.backup.jou ├── vivado_14248.backup.log ├── vivado_5412.backup.jou ├── vivado_5412.backup.log ├── vivado_8908.backup.jou ├── vivado_8908.backup.log ├── vivado_9608.backup.jou └── vivado_9608.backup.log ├── instruction.txt ├── 汇编器 ├── Compiler.cpp ├── Compiler.exe ├── instruction.txt └── test.asm └── 测试代码段.docx /MIPS汇编语言程序设计实验/18329015-郝裕玮-实验一.doc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ConstHall/Computer-Composition-Principle-Experiment/HEAD/MIPS汇编语言程序设计实验/18329015-郝裕玮-实验一.doc -------------------------------------------------------------------------------- /MIPS汇编语言程序设计实验/18329015-郝裕玮-实验一.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ConstHall/Computer-Composition-Principle-Experiment/HEAD/MIPS汇编语言程序设计实验/18329015-郝裕玮-实验一.pdf -------------------------------------------------------------------------------- /MIPS汇编语言程序设计实验/实验一.asm: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ConstHall/Computer-Composition-Principle-Experiment/HEAD/MIPS汇编语言程序设计实验/实验一.asm -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # Computer-Composition-Principle-Experiment 2 | ## 2020计算机组成原理实验 3 | 授课教师：陈志广
4 | 仅供参考，杜绝抄袭！
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