├── FinalProject_Report_CincottiMalhotraQuercetti.pdf ├── README.md ├── Comparing.v ├── dac_driver.ucf ├── header_LCD_driver_pm10to4.v ├── adc_driver.ucf ├── header_ADC_driver.v ├── module_counter_8_bit.v ├── module_lowPassFilter.v ├── Module_HighPassFilter.v ├── lcd_driver.ucf ├── header_DAC_driver.v ├── lowPassFilter.ucf ├── Module_HR_Detection.v ├── bin2bcd_8_bit.v ├── ECG_summary.html ├── ECG_main.v ├── module_chipStore.v ├── DAC_Driver.ngc ├── LCD_Driver_pm10to4.ngc ├── ECG.xise └── ADC_Driver.ngc /FinalProject_Report_CincottiMalhotraQuercetti.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CountingLogic/ECG-Verilog-FPGA/HEAD/FinalProject_Report_CincottiMalhotraQuercetti.pdf -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # ECG-Verilog-FPGA 2 | An accurate Electro Cardio Gram system, with peak detection and counting mechanism programmed in Verilog and implimented in Xilinx-FPGA. 3 | 4 | The entire code and the analogue steps involved in heart beat processing are explained in the Final Project report (the only pdf file in this repo) 5 | -------------------------------------------------------------------------------- /Comparing.v: -------------------------------------------------------------------------------- 1 | module Comparing ( qzt_clk, 2 | Vin, 3 | Thr, 4 | overthr); 5 | 6 | input qzt_clk; 7 | input [19:0] Vin; 8 | input [19:0] Thr; //threashold 9 | 10 | output overthr; 11 | 12 | reg overthr; 13 | 14 | 15 | always @(posedge qzt_clk) begin 16 | overthr= (Vin>Thr)? 1 : 0; 17 | end 18 | 19 | endmodule -------------------------------------------------------------------------------- /dac_driver.ucf: -------------------------------------------------------------------------------- 1 | NET "SPI_SCK" LOC = "AA20" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ; 2 | NET "SPI_MOSI" LOC = "AB14" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ; 3 | NET "DAC_CS" LOC = "W7" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ; 4 | NET "DAC_CLR" LOC = "AB13" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ; 5 | -------------------------------------------------------------------------------- /header_LCD_driver_pm10to4.v: -------------------------------------------------------------------------------- 1 | module LCD_Driver_pm10to4 ( qzt_clk, 2 | fourDigitInput, 3 | signFlag, 4 | dashFlag, 5 | 6 | lcd_flags, 7 | lcd_data); 8 | 9 | input qzt_clk; 10 | input [15:0] fourDigitInput; 11 | input signFlag; 12 | input dashFlag; 13 | 14 | output [1:0] lcd_flags; 15 | output [3:0] lcd_data; 16 | 17 | endmodule 18 | -------------------------------------------------------------------------------- /adc_driver.ucf: -------------------------------------------------------------------------------- 1 | NET "SPI_SCK" LOC = "AA20" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ; 2 | NET "SPI_MOSI" LOC = "AB14" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ; 3 | NET "ADC_OUT" LOC = "D16" | IOSTANDARD = LVCMOS33 ; # Private MISO for ADC 4 | NET "AMP_CS" LOC = "W6" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ; 5 | NET "AD_CONV" LOC = "Y6" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ; 6 | -------------------------------------------------------------------------------- /header_ADC_driver.v: -------------------------------------------------------------------------------- 1 | module ADC_Driver ( qzt_clk, 2 | SPI_SCK, 3 | enable, 4 | ADC_OUT, 5 | gainLabel, 6 | waitTime, 7 | 8 | AD_CONV, 9 | Va_Vb, 10 | AMP_CS, 11 | SPI_MOSI); 12 | 13 | input qzt_clk; 14 | input SPI_SCK; 15 | input enable; 16 | input ADC_OUT; 17 | input gainLabel; 18 | input [4:0] waitTime; 19 | 20 | output AD_CONV; 21 | output [27:0] Va_Vb; 22 | output AMP_CS; 23 | output SPI_MOSI; 24 | 25 | endmodule 26 | -------------------------------------------------------------------------------- /module_counter_8_bit.v: -------------------------------------------------------------------------------- 1 | module Module_Counter_8_bit ( clk_in, 2 | limit, 3 | 4 | out, 5 | carry); 6 | 7 | input clk_in; 8 | input [7:0] limit; 9 | 10 | output [7:0] out; 11 | output carry; 12 | 13 | reg [7:0] out; 14 | reg carry; 15 | 16 | always @(posedge clk_in) begin 17 | if (out >= (limit - 8'b00000001)) begin 18 | out = 0; 19 | carry = 1; 20 | end else if (out == 0) begin 21 | out = 1; 22 | carry = 0; 23 | end else 24 | out = out + 1; 25 | end 26 | 27 | endmodule 28 | -------------------------------------------------------------------------------- /module_lowPassFilter.v: -------------------------------------------------------------------------------- 1 | `define uni 25'b1111111111111111111111111 2 | module Module_LowPassFilter ( qzt_clk, 3 | clk_in, 4 | k, 5 | Vin, 6 | 7 | Vout); 8 | 9 | input qzt_clk; 10 | input clk_in; 11 | input [3:0] k; 12 | input [19:0] Vin; 13 | 14 | output [19:0] Vout; 15 | 16 | reg [19:0] Vout; 17 | reg [19:0] tmp; 18 | reg [19:0] old; 19 | reg clk_in_old; 20 | 21 | always @(posedge qzt_clk) begin 22 | if (clk_in & !clk_in_old) begin 23 | tmp<=Vin[19]? ({`uni,Vin}>>(k+1)): Vin>>(k+1); 24 | Vout<= old + tmp; 25 | old<= Vout + ~(Vout[19]? ({`uni,Vout}>>(k)): Vout>>(k))+1+ tmp; 26 | end 27 | clk_in_old <= clk_in; 28 | end 29 | endmodule 30 | -------------------------------------------------------------------------------- /Module_HighPassFilter.v: -------------------------------------------------------------------------------- 1 | `define uni 25'b1111111111111111111111111 2 | module Module_HighPassFilter ( qzt_clk, 3 | clk_in, 4 | k, 5 | Vin, 6 | 7 | Vout); 8 | 9 | input qzt_clk; 10 | input clk_in; 11 | input [3:0] k; 12 | input [19:0] Vin; 13 | 14 | output [19:0] Vout; 15 | 16 | reg [19:0] Vout; 17 | reg [19:0] tmp; 18 | reg [19:0] old; 19 | reg clk_in_old; 20 | 21 | always @(posedge qzt_clk) begin 22 | if (clk_in & !clk_in_old) begin 23 | tmp<=Vin + ~ (Vin[19]? ({`uni,Vin}>>(k+1)): Vin>>(k+1)) + 1; 24 | Vout<= old + Vin + ~ (Vin[19]? ({`uni,Vin}>>(k+1)): Vin>>(k+1)) + 1 + ~tmp+1; 25 | old<= Vout + ~ (Vout[19]? ({`uni,Vout}>>(k)): Vout>>(k)) + 1; 26 | end 27 | clk_in_old <= clk_in; 28 | end 29 | endmodule 30 | -------------------------------------------------------------------------------- /lcd_driver.ucf: -------------------------------------------------------------------------------- 1 | NET "LCD_DB<0>" LOC = "Y13" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ; 2 | NET "LCD_DB<1>" LOC = "AB18" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ; 3 | NET "LCD_DB<2>" LOC = "AB17" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ; 4 | NET "LCD_DB<3>" LOC = "AB12" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ; 5 | NET "LCD_DB<4>" LOC = "AA12" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ; 6 | NET "LCD_DB<5>" LOC = "Y16" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ; 7 | NET "LCD_DB<6>" LOC = "AB16" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ; 8 | NET "LCD_DB<7>" LOC = "Y15" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ; 9 | NET "LCD_E" LOC = "AB4" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ; 10 | NET "LCD_RS" LOC = "Y14" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ; 11 | NET "LCD_RW" LOC = "W13" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ; 12 | -------------------------------------------------------------------------------- /header_DAC_driver.v: -------------------------------------------------------------------------------- 1 | /**********************/ 2 | /* Timing description */ 3 | /**********************/ 4 | // clock period frequency note 5 | // CLK_50M 20 ns 50 MHz 6 | // SPI_SCK 160 ns 6.25 MHz generated from CLK_50M via Module_FrequencyDivider with period = 4 7 | // DAC_CS 5.28 us 189.394 kHz generated from SPI_SCK via DAC_Driver, that requires 33 clk cycles 8 | // for each of the two DACs (160 * 33 = 5.28 us) 9 | // Consequently each DAC is refreshed each 66 SPI_SCK cycles 10 | // 10.56 us 94.697 kHz 11 | 12 | /**************/ 13 | /* Conversion */ 14 | /**************/ 15 | // 16 | // Vout = 3.3 V * nDAC / 2^12 17 | 18 | module DAC_Driver ( CLK_50M, 19 | SPI_SCK, 20 | Va, Vb, 21 | startEnable, 22 | 23 | SPI_MOSI, DAC_CS, DAC_CLR, 24 | dacNumber 25 | ); 26 | 27 | input CLK_50M; 28 | input SPI_SCK; 29 | input [11:0] Va; 30 | input [11:0] Vb; 31 | input startEnable; 32 | 33 | output SPI_MOSI; 34 | output DAC_CS; 35 | output DAC_CLR; 36 | output dacNumber; 37 | 38 | endmodule 39 | -------------------------------------------------------------------------------- /lowPassFilter.ucf: -------------------------------------------------------------------------------- 1 | CONFIG VCCAUX = "3.3" ; 2 | CONFIG ENABLE_SUSPEND = "FILTERED" ; 3 | CONFIG POST_CRC = "DISABLE" ; 4 | 5 | NET "CLK_50M" LOC = "E12" | IOSTANDARD = LVCMOS33 | PERIOD = 20.000 ; 6 | OFFSET = IN 10.000 VALID 20.000 BEFORE "CLK_50M" ; 7 | OFFSET = OUT 20.000 AFTER "CLK_50M" ; 8 | 9 | 10 | ############################################ 11 | ############################################ 12 | # DO NOT MODIFY ANYTHING ABOVE THIS POINT!!! 13 | ############################################ 14 | ############################################ 15 | 16 | //NET "SW<0>" LOC = "V8" | IOSTANDARD = LVCMOS33 ; 17 | //NET "SW<1>" LOC = "U10" | IOSTANDARD = LVCMOS33 ; 18 | //NET "SW<2>" LOC = "U8" | IOSTANDARD = LVCMOS33 ; 19 | //NET "SW<3>" LOC = "T9" | IOSTANDARD = LVCMOS33 ; 20 | 21 | NET "LED<0>" LOC = "R20" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ; 22 | NET "LED<1>" LOC = "T19" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ; 23 | NET "LED<2>" LOC = "U20" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ; 24 | NET "LED<3>" LOC = "U19" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ; 25 | NET "LED<4>" LOC = "V19" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ; 26 | NET "LED<5>" LOC = "V20" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ; 27 | NET "LED<6>" LOC = "Y22" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ; 28 | NET "LED<7>" LOC = "W21" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ; 29 | -------------------------------------------------------------------------------- /Module_HR_Detection.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | `define minuto 16'b1110101001100000 3 | ////////////////////////////////////////////////////////////////////////////////// 4 | // Company: unitn 5 | // Engineer: Sagar M., Sara Q., Giancarlo C. 6 | // 7 | // Create Date: 17:01:32 01/31/2018 8 | // Design Name: 9 | // Module Name: Module_HR_Detection 10 | // Project Name: ECG 11 | // Target Devices: 12 | // Tool versions: 13 | // Description: the module operates a division to return a value of HR [bits/minute] 14 | // to print on a display. the division is: 15 | // 60seconds[in bits] / counter time [in bits] 16 | // it uses an algorithm fount on wikipedia to perform division 17 | // Dependencies: 18 | // 19 | // Revision: 20 | // Revision 0.01 - File Created 21 | // Additional Comments: 22 | // 23 | ////////////////////////////////////////////////////////////////////////////////// 24 | module Module_HR_Detection (qzt_clk, 25 | clk_in, 26 | counter, 27 | 28 | HR); 29 | 30 | input qzt_clk; 31 | input clk_in; 32 | input [15:0] counter; 33 | 34 | output [15:0] HR; 35 | 36 | reg [15:0] HR; 37 | reg [15:0] Q; 38 | reg [15:0] minute; 39 | reg count_flag; 40 | reg old_clk_in; 41 | 42 | always @ (posedge qzt_clk) begin 43 | if(clk_in & !old_clk_in) begin 44 | count_flag=1; 45 | Q=0; 46 | minute = `minuto; 47 | end 48 | if (count_flag) begin 49 | if(minute 4) 45 | bcd[3:0] = bcd[3:0] + 3; 46 | if(i < 7 && bcd[7:4] > 4) 47 | bcd[7:4] = bcd[7:4] + 3; 48 | if(i < 7 && bcd[11:8] > 4) 49 | bcd[11:8] = bcd[11:8] + 3; 50 | end 51 | end 52 | 53 | endmodule -------------------------------------------------------------------------------- /ECG_summary.html: -------------------------------------------------------------------------------- 1 | Xilinx Design Summary 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 35 | 36 | 37 | 38 | 39 | 40 | 41 | 42 | 43 | 44 | 45 | 46 | 47 | 48 |
ECG Project Status
Project File:ECG.xiseParser Errors: No Errors
Module Name:ECGImplementation State:New
Target Device:xc3s700an-4fgg484
  • Errors:
 
Product Version:ISE 14.7
  • Warnings:
 
Design Goal:Balanced
  • Routing Results:
 34 |  
Design Strategy:Xilinx Default (unlocked)
  • Timing Constraints:
 
Environment: 
  • Final Timing Score:
  
49 | 50 | 51 | 52 | 53 | 54 | 55 | 56 | 57 | 58 | 59 | 60 |  
61 | 62 | 63 | 64 | 65 | 66 | 67 | 68 | 69 | 70 | 71 |
Detailed Reports [-]
Report NameStatusGeneratedErrorsWarningsInfos
Synthesis Report     
Translation Report     
Map Report     
Place and Route Report     
Power Report     
Post-PAR Static Timing Report     
Bitgen Report     
72 |  
73 | 74 | 75 |
Secondary Reports [-]
Report NameStatusGenerated
76 | 77 | 78 |
Date Generated: 03/23/2018 - 14:00:04
79 | -------------------------------------------------------------------------------- /ECG_main.v: -------------------------------------------------------------------------------- 1 | `define t1millesimo 28'b0000000000000110000110101000 2 | 3 | module ECG ( CLK_50M, 4 | ADC_OUT, 5 | 6 | DAC_CS, 7 | DAC_CLR, 8 | SPI_SCK, 9 | AMP_CS, 10 | SPI_MOSI, 11 | AD_CONV, 12 | LED,LCD_DB, 13 | LCD_E, LCD_RS, LCD_RW); 14 | 15 | input CLK_50M; 16 | input ADC_OUT; 17 | 18 | output DAC_CS; 19 | output DAC_CLR; 20 | output SPI_SCK; 21 | output SPI_MOSI; 22 | output AMP_CS; 23 | output AD_CONV; 24 | output [7:0] LED; 25 | output [7:0] LCD_DB; 26 | output LCD_E; 27 | output LCD_RS; 28 | output LCD_RW; 29 | 30 | wire w_SPI_MOSI_preAmp; 31 | wire w_SPI_MOSI_DAC; 32 | wire w_dacNumber; 33 | wire overthr; 34 | wire monover; 35 | wire beat_period; 36 | wire clk_un_k; 37 | wire c_counter_1; 38 | wire [13:0] wb_Va; 39 | wire [13:0] wb_Vb; 40 | wire [19:0] wb_V_HPF; 41 | wire [19:0] wb_Va_filtered; 42 | wire [15:0] period_count; 43 | wire [15:0] b_period; 44 | wire [15:0] HR_show; 45 | wire [15:0] HR_to_conv; 46 | 47 | buf(SPI_MOSI, ((AMP_CS & w_SPI_MOSI_DAC)|(!AMP_CS & w_SPI_MOSI_preAmp))); 48 | 49 | buf(LCD_RW, 0); 50 | buf(LCD_DB[3:0], 4'b1111); 51 | 52 | 53 | 54 | 55 | Module_Counter_8_bit SPI_SCK_generator ( .clk_in(CLK_50M), 56 | .limit(30'd10), 57 | 58 | .carry(SPI_SCK)); 59 | 60 | Module_HighPassFilter HPF ( .qzt_clk(CLK_50M), 61 | .clk_in(~w_dacNumber), 62 | .k(4'b1011), 63 | .Vin({wb_Va,6'b000000}), 64 | .Vout(wb_V_HPF)); 65 | 66 | Module_LowPassFilter LPF ( .qzt_clk(CLK_50M), 67 | .clk_in(~w_dacNumber), 68 | .k(4'b1000), 69 | .Vin(wb_V_HPF), 70 | 71 | .Vout(wb_Va_filtered)); 72 | 73 | Comparing overt ( .qzt_clk(CLK_50M), 74 | .Vin({!wb_Va_filtered[19],wb_Va_filtered[18:0]}), 75 | .Thr({!wb_Vb[13], wb_Vb[12:0], 6'b000000}), 76 | 77 | .overthr(overthr)); 78 | 79 | Module_Monostable monov ( .clk_in(CLK_50M), 80 | .monostable_input(overthr), 81 | .N(28'b0000010011000100101101000000),//=5*10^6 ---> 100ms 82 | 83 | .monostable_output(monover)); 84 | 85 | 86 | Module_ToggleFlipFlop beat_toggle ( .clk_in(CLK_50M), 87 | .ff_input(monover), 88 | 89 | .ff_output(beat_period)); 90 | 91 | 92 | Module_FrequencyDivider Clock_1kHz ( .clk_in(CLK_50M), 93 | .period(`t1millesimo), 94 | 95 | .clk_out(clk_un_k)); 96 | 97 | 98 | 99 | Module_SynchroCounter_8_bit_SR counter_1 ( .qzt_clk(CLK_50M), 100 | .clk_in(clk_un_k & beat_period), 101 | .set(0), 102 | .reset(!monover & !beat_period), 103 | .presetValue(0), 104 | 105 | .out(period_count[7:0]), 106 | .carry(c_counter_1)); 107 | 108 | Module_SynchroCounter_8_bit_SR counter_2 ( .qzt_clk(CLK_50M), 109 | .clk_in(c_counter_1), 110 | .set(0), 111 | .reset(!monover & !beat_period), 112 | .presetValue(0), 113 | 114 | .out(period_count[15:8])); 115 | 116 | 117 | 118 | assign LED = period_count[9:2]; 119 | 120 | Module_Buffer_16bit_sync display_buff ( .qtz_clk(CLK_50M), 121 | .clk_in(!beat_period), 122 | .buff_input(period_count), 123 | 124 | .buff_output(b_period)); 125 | 126 | Module_HR_Detection frequency (.qzt_clk(CLK_50M), 127 | .clk_in(!beat_period), 128 | .counter(b_period), 129 | 130 | .HR(HR_to_conv)); 131 | 132 | bin2bcd_8_bit decimal_conv( .bin(HR_to_conv), 133 | .bcd(HR_show)); 134 | 135 | 136 | LCD_Driver_pm10to4 lcd_driver ( .qzt_clk(CLK_50M), 137 | .fourDigitInput(HR_show), 138 | .signFlag(0), 139 | .dashFlag(0), 140 | 141 | .lcd_flags({LCD_RS, LCD_E}), 142 | .lcd_data(LCD_DB[7:4])); 143 | 144 | 145 | 146 | ADC_Driver ADC_Driver ( .qzt_clk(CLK_50M), 147 | .SPI_SCK(SPI_SCK), 148 | .enable(1), 149 | .ADC_OUT(ADC_OUT), 150 | .gainLabel(0), 151 | .waitTime(5'b10000), 152 | 153 | .AD_CONV(AD_CONV), 154 | .Va_Vb({wb_Va, wb_Vb}), 155 | .AMP_CS(AMP_CS), 156 | .SPI_MOSI(w_SPI_MOSI_preAmp)); 157 | 158 | DAC_Driver DAC_Driver ( .CLK_50M(CLK_50M), 159 | .SPI_SCK(SPI_SCK), 160 | .Va({!wb_Va_filtered[19], wb_Va_filtered[18:8]}), 161 | .Vb({!wb_Vb[13], wb_Vb[12:2]}), 162 | .startEnable(AD_CONV), 163 | 164 | .SPI_MOSI(w_SPI_MOSI_DAC), 165 | .DAC_CS(DAC_CS), 166 | .DAC_CLR(DAC_CLR), 167 | .dacNumber(w_dacNumber)); 168 | 169 | 170 | 171 | endmodule 172 | -------------------------------------------------------------------------------- /module_chipStore.v: -------------------------------------------------------------------------------- 1 | /*******************************/ 2 | /*** Module_FrequencyDivider ***/ 3 | /*******************************/ 4 | 5 | module Module_FrequencyDivider ( clk_in, 6 | period, 7 | 8 | clk_out); 9 | 10 | input clk_in; 11 | input [29:0] period; 12 | 13 | output clk_out; 14 | 15 | reg clk_out; 16 | 17 | reg [29:0] counter; 18 | 19 | always @(posedge clk_in) begin 20 | if (counter >= (period - 1)) begin 21 | counter = 0; 22 | clk_out = ~clk_out; 23 | end else 24 | counter = counter + 1; 25 | end 26 | 27 | endmodule 28 | 29 | /**************************************/ 30 | /*** Module_SynchroCounter_8_bit_SR ***/ 31 | /**************************************/ 32 | 33 | module Module_SynchroCounter_8_bit_SR ( qzt_clk, 34 | clk_in, 35 | set, 36 | reset, 37 | presetValue, 38 | limit, 39 | 40 | out, 41 | carry); 42 | 43 | input qzt_clk; 44 | input clk_in; 45 | input set; 46 | input reset; 47 | input [7:0] presetValue; 48 | input [7:0] limit; 49 | 50 | output [7:0] out; 51 | output carry; 52 | 53 | reg [7:0] out; 54 | reg carry; 55 | 56 | reg clk_in_old; 57 | 58 | 59 | always @(posedge qzt_clk) begin 60 | if (reset) begin 61 | out = 0; 62 | carry = 0; 63 | end else if (set) begin 64 | out = presetValue; 65 | carry = 0; 66 | end else if (!clk_in_old & clk_in) begin 67 | if (out >= (limit - 8'b00000001)) begin 68 | out = 0; 69 | carry = 1; 70 | end else if (out == 0) begin 71 | out = 1; 72 | carry = 0; 73 | end else 74 | out = out + 1; 75 | end 76 | 77 | clk_in_old = clk_in; 78 | end 79 | 80 | endmodule 81 | 82 | /*********************************************/ 83 | /*** Module_Multiplexer_2_input_8_bit_sync ***/ 84 | /*********************************************/ 85 | 86 | module Module_Multiplexer_2_input_8_bit_sync ( clk_in, 87 | address, 88 | input_0, 89 | input_1, 90 | 91 | mux_output); 92 | 93 | input clk_in; 94 | input address; 95 | input [7:0] input_0; 96 | input [7:0] input_1; 97 | 98 | output [7:0] mux_output; 99 | 100 | reg [7:0] mux_output; 101 | 102 | always @(posedge clk_in) begin 103 | mux_output = (address)? input_1 : input_0; 104 | end 105 | 106 | endmodule 107 | 108 | /*****************************/ 109 | /*** Module_MonostableHold ***/ 110 | /*****************************/ 111 | 112 | `define defaultN 28'b111101000010010000 // 2.5 10^5 ===> 5 ms 113 | 114 | module Module_Monostable ( clk_in, 115 | monostable_input, 116 | N, 117 | 118 | monostable_output); 119 | 120 | input clk_in; 121 | input monostable_input; 122 | input [27:0] N; 123 | 124 | output monostable_output; 125 | 126 | reg monostable_output = 0; 127 | 128 | reg monostable_input_old = 0; 129 | reg [27:0] counter = 0; 130 | 131 | always @(posedge clk_in) begin 132 | if (counter == 0) begin 133 | if (!monostable_input_old & monostable_input) begin 134 | counter =((N)? N : `defaultN) - 1; 135 | monostable_output = 1; 136 | end else 137 | monostable_output = 0; 138 | end else 139 | counter = counter - 1; 140 | 141 | monostable_input_old = monostable_input; 142 | end 143 | 144 | endmodule 145 | 146 | /**********************************/ 147 | /*** Module_ToggleFlipFlop_sync ***/ 148 | /**********************************/ 149 | 150 | module Module_ToggleFlipFlop ( clk_in, 151 | ff_input, 152 | 153 | ff_output); 154 | 155 | input clk_in; 156 | input ff_input; 157 | 158 | output ff_output; 159 | 160 | reg ff_output; 161 | 162 | reg ff_input_previous; 163 | 164 | always @(posedge clk_in) begin 165 | if (!ff_input_previous & ff_input) begin 166 | ff_output = ~ff_output; 167 | end 168 | 169 | ff_input_previous = ff_input; 170 | end 171 | 172 | endmodule 173 | /**********************************/ 174 | /*** Module_Buffer_16bit_sync ***/ 175 | /**********************************/ 176 | 177 | module Module_Buffer_16bit_sync ( qtz_clk, 178 | clk_in, 179 | buff_input, 180 | 181 | buff_output); 182 | 183 | input qtz_clk; 184 | input clk_in; 185 | input [15:0] buff_input; 186 | 187 | output [15:0] buff_output; 188 | 189 | reg [15:0] buff_output; 190 | reg old_clk; 191 | 192 | always @(posedge qtz_clk) begin 193 | if (!old_clk & clk_in) begin 194 | buff_output <= buff_input; 195 | end 196 | 197 | old_clk<=clk_in; 198 | end 199 | 200 | endmodule 201 | 202 | /***************************/ 203 | /*** Module_Latch_16_bit ***/ 204 | /***************************/ 205 | 206 | module Module_Latch_16_bit ( clk_in, 207 | holdFlag, 208 | twoByteInput, 209 | 210 | twoByteOuput); 211 | 212 | input clk_in; 213 | input holdFlag; 214 | input [15:0] twoByteInput; 215 | 216 | output [15:0] twoByteOuput; 217 | 218 | reg [15:0] twoByteOuput; 219 | 220 | 221 | always @(posedge clk_in) begin 222 | if (!holdFlag) twoByteOuput = twoByteInput; 223 | end 224 | 225 | endmodule 226 | 227 | /***************************/ 228 | /*** Module_Counter_13_bit ***/ 229 | /***************************/ 230 | 231 | module Module_Counter_13_bit ( clk_in, 232 | limit, 233 | 234 | out, 235 | carry); 236 | 237 | input clk_in; 238 | input [12:0] limit; 239 | 240 | output [12:0] out; 241 | output carry; 242 | 243 | reg [12:0] out; 244 | reg carry; 245 | 246 | always @(posedge clk_in) begin 247 | if (out >= (limit - 13'b0000000000001)) begin 248 | out = 0; 249 | carry = 1; 250 | end else if (out == 0) begin 251 | out = 1; 252 | carry = 0; 253 | end else 254 | out = out + 1; 255 | end 256 | 257 | endmodule 258 | -------------------------------------------------------------------------------- /DAC_Driver.ngc: -------------------------------------------------------------------------------- 1 | XILINX-XDB 0.1 STUB 0.1 ASCII 2 | XILINX-XDM V1.6e 3 | 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