├── ALU ├── ALU.v ├── Add32.v ├── FullAdder.v └── HalfAdder.v ├── CPU.v ├── Computer.v ├── DMux32.v ├── Load_Length_Changer.v ├── Mem ├── RAM.v └── ROM.v ├── Mux.v ├── README.md ├── RISC-V_SIM ├── Reg ├── PC.v ├── Regfile.v ├── Regfile_2.v └── Register.v ├── SignExtender.v ├── SignExtender_bnc.v ├── SignExtender_jal.v ├── Simulation.v ├── Store_Length_Changer.v ├── UART ├── clk_gen.v ├── uart.v ├── uart_v2 │ └── uart_v2.v ├── uart_v3 │ └── uart_v3.v └── uart_v4 │ └── uart_v4.v ├── VGA ├── Mif3.mif ├── memory_map.v ├── memory_map_v2.v ├── vga_test.qpf ├── vga_test.v ├── vga_test_v2.qpf └── vga_test_v2.v ├── branchcontroller.v ├── controller.v └── wave.vcd /ALU/ALU.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Cra2yPierr0t/risc-v/HEAD/ALU/ALU.v -------------------------------------------------------------------------------- /ALU/Add32.v: -------------------------------------------------------------------------------- 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