├── .gitattributes ├── Lab1 ├── README.txt ├── alu.v └── test.v ├── Lab2 ├── ALU.v ├── ALU_output.v ├── CPU.v ├── CPUtest.v ├── CU.v ├── Data_holder.v ├── Data_memory.v ├── Extender.v ├── IR.v ├── Instruction_memory.v ├── MUX32.v ├── NPC.v ├── PC.v ├── PC_adder.v ├── PC_select.v ├── README.txt ├── Register_set.v ├── Writeback_Select.v ├── cutest.v ├── equal_control.v ├── pctest.v ├── test.v ├── test2.v └── tsst.v ├── Lab3 ├── ALU.v ├── ALU_output.v ├── CPU.v ├── CPU_top.v ├── CPU_top_test.v ├── CPUtest.v ├── CU.v ├── Conflict_Control_Unit.v ├── Data_holder.v ├── Data_memory.v ├── EX_MEM_Register.v ├── Equal_cond_holder.v ├── Extender.v ├── ID_EX_Register.v ├── IF_ID_Register.v ├── IR.v ├── Instruction_memory.v ├── MEM_WB_Register.v ├── MUX32.v ├── MUX3241.v ├── NPC.v ├── PC.v ├── PC_adder.v ├── PC_select.v ├── README.txt ├── Register_set.v ├── Writeback_Select.v ├── alu_test.v ├── cutest.v ├── equal_control.v ├── mux3241_test.v ├── pctest.v ├── test.v ├── test2.v └── tsst.v ├── Lab4 ├── README.txt ├── cache.v ├── cache_data.v ├── cache_tagv.v └── cache_tb.v └── README.md /.gitattributes: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/DARX1024/HITCCLab/HEAD/.gitattributes -------------------------------------------------------------------------------- /Lab1/README.txt: -------------------------------------------------------------------------------- 1 | 这个实验就是让大家熟悉熟悉verilog的语法，实在是没啥好说的…… 2 | 3 | 写不明白就去学咯，可以刷一点基础题 4 | https://hdlbits.01xz.net/wiki/Problem_sets#Getting_Started -------------------------------------------------------------------------------- /Lab1/alu.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/DARX1024/HITCCLab/HEAD/Lab1/alu.v -------------------------------------------------------------------------------- /Lab1/test.v: -------------------------------------------------------------------------------- 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