├── .gitattributes ├── Code ├── TOP.v ├── display_ctrl.v └── time_control.v ├── Digital_Clock.qpf ├── Digital_Clock.qsf ├── Digital_Clock.qws ├── Digital_Clock_nativelink_simulation.rpt ├── README.md ├── RTL.png ├── TestBench └── tb_TOP.v ├── db ├── Digital_Clock.(0).cnf.cdb ├── Digital_Clock.(0).cnf.hdb ├── Digital_Clock.(1).cnf.cdb ├── Digital_Clock.(1).cnf.hdb ├── Digital_Clock.(2).cnf.cdb ├── Digital_Clock.(2).cnf.hdb ├── Digital_Clock.ae.hdb ├── Digital_Clock.cbx.xml ├── Digital_Clock.cmp.rdb ├── Digital_Clock.db_info ├── Digital_Clock.hier_info ├── Digital_Clock.hif ├── Digital_Clock.lpc.html ├── Digital_Clock.lpc.rdb ├── Digital_Clock.lpc.txt ├── Digital_Clock.map.cdb ├── Digital_Clock.map.hdb ├── Digital_Clock.map.logdb ├── Digital_Clock.map.qmsg ├── Digital_Clock.map.rdb ├── Digital_Clock.npp.qmsg ├── Digital_Clock.pplq.rdb ├── Digital_Clock.pre_map.cdb ├── Digital_Clock.pre_map.hdb ├── Digital_Clock.root_partition.map.reg_db.cdb ├── Digital_Clock.rtlv.hdb ├── Digital_Clock.rtlv_sg.cdb ├── Digital_Clock.rtlv_sg_swap.cdb ├── Digital_Clock.sgate.nvd ├── Digital_Clock.sgate_sm.nvd ├── Digital_Clock.sld_design_entry.sci ├── Digital_Clock.sld_design_entry_dsc.sci ├── Digital_Clock.smart_action.txt ├── Digital_Clock.tis_db_list.ddb └── prev_cmp_Digital_Clock.qmsg ├── incremental_db ├── README └── compiled_partitions │ ├── Digital_Clock.db_info │ └── Digital_Clock.root_partition.map.kpt ├── output_files ├── Digital_Clock.done ├── Digital_Clock.flow.rpt ├── Digital_Clock.map.rpt └── Digital_Clock.map.summary ├── simulation └── modelsim │ ├── Digital_Clock_run_msim_rtl_verilog.do │ ├── Digital_Clock_run_msim_rtl_verilog.do.bak │ ├── Digital_Clock_run_msim_rtl_verilog.do.bak1 │ ├── Digital_Clock_run_msim_rtl_verilog.do.bak10 │ ├── Digital_Clock_run_msim_rtl_verilog.do.bak11 │ ├── Digital_Clock_run_msim_rtl_verilog.do.bak2 │ ├── Digital_Clock_run_msim_rtl_verilog.do.bak3 │ ├── Digital_Clock_run_msim_rtl_verilog.do.bak4 │ ├── Digital_Clock_run_msim_rtl_verilog.do.bak5 │ ├── Digital_Clock_run_msim_rtl_verilog.do.bak6 │ ├── Digital_Clock_run_msim_rtl_verilog.do.bak7 │ ├── Digital_Clock_run_msim_rtl_verilog.do.bak8 │ ├── Digital_Clock_run_msim_rtl_verilog.do.bak9 │ ├── modelsim.ini │ ├── msim_transcript │ ├── rtl_work │ ├── _info │ ├── _lib.qdb │ ├── _lib1_0.qdb │ ├── _lib1_0.qpg │ ├── _lib1_0.qtl │ └── _vmake │ ├── vish_stacktrace.vstf │ └── vsim.wlf ├── 仿真图1.png ├── 仿真图2.png └── 仿真图3.png /.gitattributes: -------------------------------------------------------------------------------- 1 | # Auto detect text files and perform LF normalization 2 | *.html linguist-language=Verilog 3 | * VHDL linguist-language=Verilog 4 | -------------------------------------------------------------------------------- /Code/TOP.v: -------------------------------------------------------------------------------- 1 | module TOP( 2 | input clk, 3 | input rst_n, 4 | 5 | input set_time_finish, //设置时间 6 | input [3:0] set_sec_ge, 7 | input [3:0] set_sec_shi, 8 | input [3:0] set_min_ge, 9 | input [3:0] set_min_shi, 10 | input [3:0] set_hour_ge, 11 | input [3:0] set_hour_shi, 12 | 13 | input clock_en, //闹钟开关，置“1”打开闹钟；置“0”关闭闹钟。 14 | input [3:0] clock_min_ge, 15 | input [3:0] clock_min_shi, 16 | input [3:0] clock_hour_ge, 17 | input [3:0] clock_hour_shi, 18 | output clock_out, 19 | 20 | output [3:0] sec_ge_r, 21 | output [3:0] sec_shi_r, 22 | output [3:0] min_ge_r, 23 | output [3:0] min_shi_r, 24 | output [3:0] hour_ge_r, 25 | output [3:0] hour_shi_r, 26 | 27 | output [7:0] data_out, //数码管输出 28 | output [7:0] select 29 | ); 30 | 31 | wire [3:0] sec_ge_rr; 32 | wire [3:0] sec_shi_rr; 33 | wire [3:0] min_ge_rr; 34 | wire [3:0] min_shi_rr; 35 | wire [3:0] hour_ge_rr; 36 | wire [3:0] hour_shi_rr; 37 | 38 | assign sec_ge_r = sec_ge_rr; 39 | assign sec_shi_r = sec_shi_rr; 40 | assign min_ge_r = min_ge_rr; 41 | assign min_shi_r = min_shi_rr; 42 | assign hour_ge_r = hour_ge_rr; 43 | assign hour_shi_r = hour_shi_rr; 44 | 45 | //------------------------------// 46 | time_control time_control_inst( 47 | .clk (clk), 48 | .rst_n (rst_n), 49 | 50 | .set_time_finish (set_time_finish), 51 | .set_sec_ge (set_sec_ge), 52 | .set_sec_shi (set_sec_shi), 53 | .set_min_ge (set_min_ge), 54 | .set_min_shi (set_min_shi), 55 | .set_hour_ge (set_hour_ge), 56 | .set_hour_shi (set_hour_shi), 57 | 58 | .clock_en (clock_en), 59 | .clock_min_ge (clock_min_ge), 60 | .clock_min_shi (clock_min_shi), 61 | .clock_hour_ge (clock_hour_ge), 62 | .clock_hour_shi (clock_hour_shi), 63 | .clock_out (clock_out), 64 | 65 | .sec_ge_r (sec_ge_rr), 66 | .sec_shi_r (sec_shi_rr), 67 | .min_ge_r (min_ge_rr), 68 | .min_shi_r (min_shi_rr), 69 | .hour_ge_r (hour_ge_rr), 70 | .hour_shi_r (hour_shi_rr) 71 | ); 72 | //-----------------------------// 73 | display_ctrl display_ctrl_inst( 74 | .clk (clk), 75 | .rst_n (rst_n), 76 | .sec_ge (sec_ge_rr), 77 | .sec_shi (sec_shi_rr), 78 | .min_ge (min_ge_rr), 79 | .min_shi (min_shi_rr), 80 | .hour_ge (hour_ge_rr), 81 | .hour_shi (hour_shi_rr), 82 | .data_out (data_out), 83 | .select (select) 84 | ); 85 | 86 | 87 | 88 | 89 | 90 | 91 | endmodule -------------------------------------------------------------------------------- /Code/display_ctrl.v: -------------------------------------------------------------------------------- 1 | module display_ctrl( 2 | input clk, 3 | input rst_n, 4 | input [3:0] sec_ge, 5 | input [3:0] sec_shi, 6 | input [3:0] min_ge, 7 | input [3:0] min_shi, 8 | input [3:0] hour_ge, 9 | input [3:0] hour_shi, 10 | output [7:0] data_out, 11 | output [7:0] select 12 | ); 13 | 14 | reg [7:0] data; //数码管段选信号 15 | reg [7:0] sel; //数码管位选信号 16 | reg [3:0] display_data=0; 17 | 18 | //============================数码管动态刷新============================// 19 | reg [10:0] m=0; 20 | 21 | always @ ( posedge clk or negedge rst_n) begin 22 | if(!rst_n) begin 23 | m <= 0; 24 | end 25 | else begin 26 | m <= m+1; 27 | end 28 | end 29 | 30 | //----------------数码管位选-------------------// 31 | always@( posedge clk) begin 32 | case(m[5:3]) 33 | 0: begin 34 | display_data<=4'b0000; 35 | sel<=8'b1111_1110; 36 | end 37 | 1: begin 38 | display_data<=4'b0000; 39 | sel<=8'b1111_1101; 40 | end 41 | 2: begin 42 | display_data<=hour_shi; 43 | sel<=8'b1111_1011; 44 | end 45 | 3: begin 46 | display_data<=hour_ge; 47 | sel<=8'b1111_0111; 48 | end 49 | 4: begin 50 | display_data<=min_shi; 51 | sel<=8'b1110_1111; 52 | end 53 | 5: begin 54 | display_data<=min_ge; 55 | sel<=8'b1101_1111; 56 | end 57 | 6: begin 58 | display_data<=sec_shi; 59 | sel<=8'b1011_1111; 60 | end 61 | 7: begin 62 | display_data<=sec_ge; 63 | sel<=8'b0111_1111; 64 | end 65 | default:begin 66 | data<=8'b0; 67 | sel<=8'b0; 68 | end 69 | endcase 70 | end 71 | 72 | //---------------数码管段选-----------------// 73 | always @(display_data) begin 74 | case(display_data) //七段译码 75 | 4'h0:data = 8'hc0;//显示0 76 | 4'h1:data = 8'hf9;//显示1 77 | 4'h2:data = 8'ha4;//显示2 78 | 4'h3:data = 8'hb0;//显示3 79 | 4'h4:data = 8'h99;//显示4 80 | 4'h5:data = 8'h92;//显示5 81 | 4'h6:data = 8'h82;//显示6 82 | 4'h7:data = 8'hf8;//显示7 83 | 4'h8:data = 8'h80;//显示8 84 | 4'h9:data = 8'h90;//显示9 85 | default data = data; 86 | endcase 87 | end 88 | //======================================================================// 89 | 90 | assign select = sel; 91 | assign data_out = data; 92 | 93 | endmodule -------------------------------------------------------------------------------- /Code/time_control.v: -------------------------------------------------------------------------------- 1 | module time_control( 2 | input clk, 3 | input rst_n, 4 | 5 | input set_time_finish, //设置时间 6 | input [3:0] set_sec_ge, 7 | input [3:0] set_sec_shi, 8 | input [3:0] set_min_ge, 9 | input [3:0] set_min_shi, 10 | input [3:0] set_hour_ge, 11 | input [3:0] set_hour_shi, 12 | 13 | input clock_en, //闹钟开关，置“1”打开闹钟；置“0”关闭闹钟。 14 | input [3:0] clock_min_ge, 15 | input [3:0] clock_min_shi, 16 | input [3:0] clock_hour_ge, 17 | input [3:0] clock_hour_shi, 18 | output reg clock_out, 19 | 20 | output [3:0] sec_ge_r, 21 | output [3:0] sec_shi_r, 22 | output [3:0] min_ge_r, 23 | output [3:0] min_shi_r, 24 | output [3:0] hour_ge_r, 25 | output [3:0] hour_shi_r 26 | ); 27 | 28 | //=================时钟模块====================// 29 | //---------1ms延时-------// 30 | reg [15:0] cnt_1ms; //1ms计数 31 | reg flag_1ms; //ms进位信号 32 | always @(posedge clk or negedge rst_n) begin 33 | if(!rst_n) begin 34 | cnt_1ms <= 0; 35 | flag_1ms <= 0; 36 | end 37 | else if(cnt_1ms == 16'd4) begin 38 | cnt_1ms <= 0; 39 | flag_1ms <= 1; 40 | end 41 | else begin 42 | cnt_1ms <= cnt_1ms + 1; 43 | flag_1ms <= 0; 44 | end 45 | end 46 | //--------1s延时--------// 47 | reg [11:0] cnt_1s; //1s计数 48 | reg flag_1s; //s进位信号 49 | always @(posedge clk or negedge rst_n) begin 50 | if(!rst_n) begin 51 | cnt_1s <= 0; 52 | flag_1s <= 0; 53 | end 54 | else if(flag_1ms) begin 55 | if(cnt_1s == 12'd4) begin 56 | cnt_1s <= 0; 57 | flag_1s <= 1; 58 | end 59 | else begin 60 | cnt_1s <= cnt_1s + 1; 61 | flag_1s <= 0; 62 | end 63 | end 64 | else begin 65 | cnt_1s <= cnt_1s; 66 | flag_1s <= 0; 67 | end 68 | end 69 | //============================================// 70 | 71 | //=================时钟模块====================// 72 | //---------秒钟个位、十位--------// 73 | reg [3:0] sec_ge; 74 | reg flag_sec_ge; //秒钟个位进位信号 75 | reg [2:0] sec_shi; 76 | reg flag_sec_shi; //秒钟十位进位信号 77 | 78 | always @(posedge clk or negedge rst_n) begin 79 | if(!rst_n) begin 80 | sec_ge <= 0; 81 | flag_sec_ge <= 0; 82 | end 83 | else if(set_time_finish) begin 84 | sec_ge <= set_sec_ge; 85 | flag_sec_ge <= 0; 86 | end 87 | else if(flag_1ms) begin 88 | if(sec_ge == 4'd9) begin 89 | sec_ge <= 0; 90 | flag_sec_ge <= 1; 91 | end 92 | else begin 93 | sec_ge <= sec_ge + 1; 94 | flag_sec_ge <= 0; 95 | end 96 | end 97 | else begin 98 | sec_ge <= sec_ge; 99 | flag_sec_ge <= 0; 100 | end 101 | end 102 | always @(posedge clk or negedge rst_n) begin 103 | if(!rst_n) begin 104 | sec_shi <= 0; 105 | flag_sec_shi <= 0; 106 | end 107 | else if(set_time_finish) begin 108 | sec_shi <= set_sec_shi; 109 | flag_sec_shi <= 0; 110 | end 111 | else if(flag_sec_ge) begin 112 | if(sec_shi == 3'd5)begin 113 | sec_shi <= 0; 114 | flag_sec_shi <= 1; 115 | end 116 | else begin 117 | sec_shi <= sec_shi + 1; 118 | flag_sec_shi <= 0; 119 | end 120 | end 121 | else begin 122 | sec_shi <= sec_shi; 123 | flag_sec_shi <= 0; 124 | end 125 | end 126 | 127 | //---------分钟个位、十位--------// 128 | reg [3:0] min_ge; 129 | reg flag_min_ge; //分钟个位进位信号 130 | reg [2:0] min_shi; 131 | reg flag_min_shi; //分钟十位进位信号 132 | 133 | always @(posedge clk or negedge rst_n) begin 134 | if(!rst_n) begin 135 | min_ge <= 0; 136 | flag_min_ge <= 0; 137 | end 138 | else if(set_time_finish) begin 139 | min_ge <= set_min_ge; 140 | flag_min_ge <= 0; 141 | end 142 | else if(flag_sec_shi) begin 143 | if(min_ge == 4'd9) begin 144 | min_ge <= 0; 145 | flag_min_ge <= 1; 146 | end 147 | else begin 148 | min_ge <= min_ge + 1; 149 | flag_min_ge <= 0; 150 | end 151 | end 152 | else begin 153 | min_ge <= min_ge; 154 | flag_min_ge <= 0; 155 | end 156 | end 157 | always @(posedge clk or negedge rst_n) begin 158 | if(!rst_n) begin 159 | min_shi <= 0; 160 | flag_min_shi <= 0; 161 | end 162 | else if(set_time_finish) begin 163 | min_shi <= set_min_shi; 164 | flag_min_shi <= 0; 165 | end 166 | else if(flag_min_ge) begin 167 | if(min_shi == 3'd5) begin 168 | min_shi <= 0; 169 | flag_min_shi <= 1; 170 | end 171 | else begin 172 | min_shi <= min_shi + 1; 173 | flag_min_shi <= 0; 174 | end 175 | end 176 | else begin 177 | min_shi <= min_shi; 178 | flag_min_shi <= 0; 179 | end 180 | end 181 | 182 | //---------时钟个位、十位--------// 183 | reg [3:0] hour_ge; 184 | reg flag_hour_ge; 185 | reg [1:0] hour_shi; 186 | reg flag_hour_shi; 187 | 188 | always @(posedge clk or negedge rst_n) begin 189 | if(!rst_n) begin 190 | hour_ge <= 0; 191 | flag_hour_ge <= 0; 192 | end 193 | else if(set_time_finish) begin 194 | hour_ge <= set_hour_ge; 195 | flag_hour_ge <= 0; 196 | end 197 | else if(flag_min_shi) begin 198 | if(hour_ge == 4'd9) begin 199 | hour_ge <= 0; 200 | flag_hour_ge <= 1; 201 | end 202 | else if((hour_shi == 3'd2) && (hour_ge == 4'd3)) begin 203 | hour_ge <= 0; 204 | flag_hour_ge <= 1; 205 | end 206 | else begin 207 | hour_ge <= hour_ge + 1; 208 | flag_hour_ge <= 0; 209 | end 210 | end 211 | else begin 212 | hour_ge <= hour_ge; 213 | flag_hour_ge <= 0; 214 | end 215 | end 216 | always @(posedge clk or negedge rst_n) begin 217 | if(!rst_n) begin 218 | hour_shi <= 0; 219 | flag_hour_shi <= 0; 220 | end 221 | else if(set_time_finish) begin 222 | hour_shi <= set_hour_shi; 223 | flag_hour_shi <= 0; 224 | end 225 | else if(flag_hour_ge) begin 226 | if(hour_shi == 3'd2) begin 227 | hour_shi <= 0; 228 | flag_hour_shi <= 1; 229 | end 230 | else begin 231 | hour_shi <= hour_shi + 1; 232 | flag_hour_shi <= 0; 233 | end 234 | end 235 | else begin 236 | hour_shi <= hour_shi; 237 | flag_hour_shi <= 0; 238 | end 239 | end 240 | //============================================// 241 | 242 | assign sec_ge_r = sec_ge; 243 | assign sec_shi_r = sec_shi; 244 | assign min_ge_r = min_ge; 245 | assign min_shi_r = min_shi; 246 | assign hour_ge_r = hour_ge; 247 | assign hour_shi_r = hour_shi; 248 | 249 | //=================闹钟设置===================// 250 | always @(posedge clk or negedge rst_n) begin 251 | if(!rst_n) begin 252 | clock_out <= 0; 253 | end 254 | else if(!clock_en) begin 255 | clock_out <= 0; 256 | end 257 | else if({hour_shi,hour_ge,min_shi,min_ge} == {clock_hour_shi,clock_hour_ge,clock_min_shi,clock_min_ge}) begin 258 | clock_out <= 1; 259 | end 260 | else begin 261 | clock_out <= clock_out; 262 | end 263 | end 264 | //============================================// 265 | 266 | 267 | 268 | endmodule 269 | 270 | 271 | -------------------------------------------------------------------------------- /Digital_Clock.qpf: -------------------------------------------------------------------------------- 1 | # -------------------------------------------------------------------------- # 2 | # 3 | # Copyright (C) 2017 Intel Corporation. All rights reserved. 4 | # Your use of Intel Corporation's design tools, logic functions 5 | # and other software and tools, and its AMPP partner logic 6 | # functions, and any output files from any of the foregoing 7 | # (including device programming or simulation files), and any 8 | # associated documentation or information are expressly subject 9 | # to the terms and conditions of the Intel Program License 10 | # Subscription Agreement, the Intel Quartus Prime License Agreement, 11 | # the Intel FPGA IP License Agreement, or other applicable license 12 | # agreement, including, without limitation, that your use is for 13 | # the sole purpose of programming logic devices manufactured by 14 | # Intel and sold by Intel or its authorized distributors. Please 15 | # refer to the applicable agreement for further details. 16 | # 17 | # -------------------------------------------------------------------------- # 18 | # 19 | # Quartus Prime 20 | # Version 17.1.0 Build 590 10/25/2017 SJ Standard Edition 21 | # Date created = 00:43:28 May 14, 2018 22 | # 23 | # -------------------------------------------------------------------------- # 24 | 25 | QUARTUS_VERSION = "17.1" 26 | DATE = "00:43:28 May 14, 2018" 27 | 28 | # Revisions 29 | 30 | PROJECT_REVISION = "Digital_Clock" 31 | -------------------------------------------------------------------------------- /Digital_Clock.qsf: -------------------------------------------------------------------------------- 1 | # -------------------------------------------------------------------------- # 2 | # 3 | # Copyright (C) 2017 Intel Corporation. All rights reserved. 4 | # Your use of Intel Corporation's design tools, logic functions 5 | # and other software and tools, and its AMPP partner logic 6 | # functions, and any output files from any of the foregoing 7 | # (including device programming or simulation files), and any 8 | # associated documentation or information are expressly subject 9 | # to the terms and conditions of the Intel Program License 10 | # Subscription Agreement, the Intel Quartus Prime License Agreement, 11 | # the Intel FPGA IP License Agreement, or other applicable license 12 | # agreement, including, without limitation, that your use is for 13 | # the sole purpose of programming logic devices manufactured by 14 | # Intel and sold by Intel or its authorized distributors. Please 15 | # refer to the applicable agreement for further details. 16 | # 17 | # -------------------------------------------------------------------------- # 18 | # 19 | # Quartus Prime 20 | # Version 17.1.0 Build 590 10/25/2017 SJ Standard Edition 21 | # Date created = 00:43:28 May 14, 2018 22 | # 23 | # -------------------------------------------------------------------------- # 24 | # 25 | # Notes: 26 | # 27 | # 1) The default values for assignments are stored in the file: 28 | # Digital_Clock_assignment_defaults.qdf 29 | # If this file doesn't exist, see file: 30 | # assignment_defaults.qdf 31 | # 32 | # 2) Altera recommends that you do not modify this file. This 33 | # file is updated automatically by the Quartus Prime software 34 | # and any changes you make may be lost or overwritten. 35 | # 36 | # -------------------------------------------------------------------------- # 37 | 38 | 39 | set_global_assignment -name FAMILY "MAX II" 40 | set_global_assignment -name DEVICE EPM2210F324C5 41 | set_global_assignment -name TOP_LEVEL_ENTITY TOP 42 | set_global_assignment -name ORIGINAL_QUARTUS_VERSION 17.1.0 43 | set_global_assignment -name PROJECT_CREATION_TIME_DATE "00:43:28 MAY 14, 2018" 44 | set_global_assignment -name LAST_QUARTUS_VERSION "17.1.0 Standard Edition" 45 | set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files 46 | set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 47 | set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 48 | set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR "-1" 49 | set_global_assignment -name POWER_EXT_SUPPLY_VOLTAGE_TO_REGULATOR 3.3V 50 | set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (Verilog)" 51 | set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation 52 | set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation 53 | set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "NO HEAT SINK WITH STILL AIR" 54 | set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS TEST_BENCH_MODE -section_id eda_simulation 55 | set_global_assignment -name EDA_NATIVELINK_SIMULATION_TEST_BENCH tb_TOP -section_id eda_simulation 56 | set_global_assignment -name EDA_TEST_BENCH_NAME tb_TOP -section_id eda_simulation 57 | set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id tb_TOP 58 | set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME tb_TOP -section_id tb_TOP 59 | set_global_assignment -name EDA_TEST_BENCH_FILE TestBench/tb_TOP.v -section_id tb_TOP 60 | set_global_assignment -name EDA_NATIVELINK_PORTABLE_FILE_PATHS ON -section_id eda_simulation 61 | set_global_assignment -name VERILOG_FILE Code/TOP.v 62 | set_global_assignment -name VERILOG_FILE Code/display_ctrl.v 63 | set_global_assignment -name VERILOG_FILE Code/time_control.v -------------------------------------------------------------------------------- /Digital_Clock.qws: -------------------------------------------------------------------------------- 1 | @(last_workspace -------------------------------------------------------------------------------- /Digital_Clock_nativelink_simulation.rpt: -------------------------------------------------------------------------------- 1 | Info: Start Nativelink Simulation process 2 | Info: NativeLink has detected Verilog design -- Verilog simulation models will be used 3 | 4 | ========= EDA Simulation Settings ===================== 5 | 6 | Sim Mode : RTL 7 | Family : maxii 8 | Quartus root : e:/softwares/quartus_17.1/quartus/bin64/ 9 | Quartus sim root : e:/softwares/quartus_17.1/quartus/eda/sim_lib 10 | Simulation Tool : modelsim-altera 11 | Simulation Language : verilog 12 | Simulation Mode : GUI 13 | Sim Output File : 14 | Sim SDF file : 15 | Sim dir : simulation\modelsim 16 | 17 | ======================================================= 18 | 19 | Info: Starting NativeLink simulation with ModelSim-Altera software 20 | Sourced NativeLink script e:/softwares/quartus_17.1/quartus/common/tcl/internal/nativelink/modelsim.tcl 21 | Warning: File Digital_Clock_run_msim_rtl_verilog.do already exists - backing up current file as Digital_Clock_run_msim_rtl_verilog.do.bak11 22 | Info: Spawning ModelSim-Altera Simulation software 23 | Info: NativeLink simulation flow was successful 24 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | ## 1. 说明： 2 | 3 | - 基于Verilog的数字时钟设计，仿真版本。 4 | 5 | ## 2. 平台： 6 | 7 | - Quartus 17.1 8 | - Modelsim仿真 9 | 10 | ## 3. 功能实现： 11 | 12 | - 数字时钟，具有时、分、秒显示； 13 | - 具有时间校准及闹钟功能； 14 | - 采用数码管显示时钟值（仿真中看不出数码管显示效果）。 15 | 16 | ## 4. 补充说明： 17 | 18 | - 模块说明： 19 | ``` 20 | TOP.v 顶层文件 21 | time_control.v 数字钟实现模块 22 | display_ctrl.v 数码管驱动模块 23 | tb_TOP.v 测试文件 24 | ``` 25 | 26 | - RTL结构图： 27 | 28 | ![RTL图](https://user-images.githubusercontent.com/29295862/40353222-88119fd2-5de3-11e8-8386-eee87dd0fbd3.png) 29 | 30 | - 仿真图： 31 | 32 | ![仿真图](https://user-images.githubusercontent.com/29295862/40353569-62f78832-5de4-11e8-9dfd-8950000d44f2.png) 33 | ![仿真图](https://user-images.githubusercontent.com/29295862/40353572-64ea39f0-5de4-11e8-8658-1fc40eef2632.png) 34 | ![仿真图](https://user-images.githubusercontent.com/29295862/40353576-66da9d40-5de4-11e8-8de2-431d39147bda.png) -------------------------------------------------------------------------------- /RTL.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/DOOKNET/Digital_Clock/c56f1dbf5b4fb8fe69f5c27d19749ed98fe408a7/RTL.png -------------------------------------------------------------------------------- /TestBench/tb_TOP.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns/1ps 2 | 3 | module tb_TOP(); 4 | 5 | reg sclk; 6 | reg rst_n; 7 | 8 | reg set_time_finish = 0; 9 | reg [3:0] set_sec_ge = 4'd0; 10 | reg [2:0] set_sec_shi = 3'd0; 11 | reg [3:0] set_min_ge = 4'd0; 12 | reg [2:0] set_min_shi = 3'd0; 13 | reg [3:0] set_hour_ge = 4'd0; 14 | reg [1:0] set_hour_shi = 2'd0; 15 | 16 | reg clock_en = 0; 17 | reg [3:0] clock_min_ge = 4'd0; 18 | reg [2:0] clock_min_shi = 3'd0; 19 | reg [3:0] clock_hour_ge = 4'd0; 20 | reg [1:0] clock_hour_shi = 2'd0; 21 | wire clock_out; 22 | 23 | wire [3:0] sec_ge; 24 | wire [2:0] sec_shi; 25 | wire [3:0] min_ge; 26 | wire [2:0] min_shi; 27 | wire [3:0] hour_ge; 28 | wire [1:0] hour_shi; 29 | 30 | wire [7:0] data_out; 31 | wire [7:0] select; 32 | 33 | initial sclk = 1; 34 | always #10 sclk = !sclk; 35 | 36 | initial begin 37 | rst_n = 0; 38 | #100 39 | rst_n = 1; 40 | end 41 | 42 | 43 | TOP TOP_inst( 44 | .clk (sclk), 45 | .rst_n (rst_n), 46 | 47 | .set_time_finish (set_time_finish), 48 | .set_sec_ge (set_sec_ge), 49 | .set_sec_shi (set_sec_shi), 50 | .set_min_ge (set_min_ge), 51 | .set_min_shi (set_min_shi), 52 | .set_hour_ge (set_hour_ge), 53 | .set_hour_shi (set_hour_shi), 54 | 55 | .clock_en (clock_en), 56 | .clock_min_ge (clock_min_ge), 57 | .clock_min_shi (clock_min_shi), 58 | .clock_hour_ge (clock_hour_ge), 59 | .clock_hour_shi (clock_hour_shi), 60 | .clock_out (clock_out), 61 | 62 | .sec_ge_r (sec_ge), 63 | .sec_shi_r (sec_shi), 64 | .min_ge_r (min_ge), 65 | .min_shi_r (min_shi), 66 | .hour_ge_r (hour_ge), 67 | .hour_shi_r (hour_shi), 68 | 69 | .data_out (data_out), 70 | .select (select) 71 | ); 72 | 73 | endmodule 74 | -------------------------------------------------------------------------------- /db/Digital_Clock.(0).cnf.cdb: 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-------------------------------------------------------------------------------- https://raw.githubusercontent.com/DOOKNET/Digital_Clock/c56f1dbf5b4fb8fe69f5c27d19749ed98fe408a7/db/Digital_Clock.ae.hdb -------------------------------------------------------------------------------- /db/Digital_Clock.cbx.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | -------------------------------------------------------------------------------- /db/Digital_Clock.cmp.rdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/DOOKNET/Digital_Clock/c56f1dbf5b4fb8fe69f5c27d19749ed98fe408a7/db/Digital_Clock.cmp.rdb -------------------------------------------------------------------------------- /db/Digital_Clock.db_info: -------------------------------------------------------------------------------- 1 | Quartus_Version = Version 17.1.0 Build 590 10/25/2017 SJ Standard Edition 2 | Version_Index = 453135872 3 | Creation_Time = Tue May 22 16:54:43 2018 4 | -------------------------------------------------------------------------------- /db/Digital_Clock.hier_info: -------------------------------------------------------------------------------- 1 | |TOP 2 | clk => clk.IN2 3 | rst_n => rst_n.IN2 4 | set_time_finish => set_time_finish.IN1 5 | set_sec_ge[0] => set_sec_ge[0].IN1 6 | set_sec_ge[1] => set_sec_ge[1].IN1 7 | set_sec_ge[2] => set_sec_ge[2].IN1 8 | set_sec_ge[3] => set_sec_ge[3].IN1 9 | set_sec_shi[0] => set_sec_shi[0].IN1 10 | set_sec_shi[1] => set_sec_shi[1].IN1 11 | set_sec_shi[2] => set_sec_shi[2].IN1 12 | set_sec_shi[3] => set_sec_shi[3].IN1 13 | set_min_ge[0] => set_min_ge[0].IN1 14 | set_min_ge[1] => set_min_ge[1].IN1 15 | set_min_ge[2] => set_min_ge[2].IN1 16 | set_min_ge[3] => set_min_ge[3].IN1 17 | set_min_shi[0] => set_min_shi[0].IN1 18 | set_min_shi[1] => set_min_shi[1].IN1 19 | set_min_shi[2] => set_min_shi[2].IN1 20 | set_min_shi[3] => set_min_shi[3].IN1 21 | set_hour_ge[0] => set_hour_ge[0].IN1 22 | set_hour_ge[1] => set_hour_ge[1].IN1 23 | set_hour_ge[2] => set_hour_ge[2].IN1 24 | set_hour_ge[3] => set_hour_ge[3].IN1 25 | set_hour_shi[0] => set_hour_shi[0].IN1 26 | set_hour_shi[1] => set_hour_shi[1].IN1 27 | set_hour_shi[2] => set_hour_shi[2].IN1 28 | set_hour_shi[3] => set_hour_shi[3].IN1 29 | clock_en => clock_en.IN1 30 | clock_min_ge[0] => clock_min_ge[0].IN1 31 | clock_min_ge[1] => clock_min_ge[1].IN1 32 | clock_min_ge[2] => clock_min_ge[2].IN1 33 | clock_min_ge[3] => clock_min_ge[3].IN1 34 | clock_min_shi[0] => clock_min_shi[0].IN1 35 | clock_min_shi[1] => clock_min_shi[1].IN1 36 | clock_min_shi[2] => clock_min_shi[2].IN1 37 | clock_min_shi[3] => clock_min_shi[3].IN1 38 | clock_hour_ge[0] => clock_hour_ge[0].IN1 39 | clock_hour_ge[1] => clock_hour_ge[1].IN1 40 | clock_hour_ge[2] => clock_hour_ge[2].IN1 41 | clock_hour_ge[3] => clock_hour_ge[3].IN1 42 | clock_hour_shi[0] => clock_hour_shi[0].IN1 43 | clock_hour_shi[1] => clock_hour_shi[1].IN1 44 | clock_hour_shi[2] => clock_hour_shi[2].IN1 45 | clock_hour_shi[3] => clock_hour_shi[3].IN1 46 | clock_out << time_control:time_control_inst.clock_out 47 | sec_ge_r[0] << sec_ge_rr[0].DB_MAX_OUTPUT_PORT_TYPE 48 | sec_ge_r[1] << sec_ge_rr[1].DB_MAX_OUTPUT_PORT_TYPE 49 | sec_ge_r[2] << sec_ge_rr[2].DB_MAX_OUTPUT_PORT_TYPE 50 | sec_ge_r[3] << sec_ge_rr[3].DB_MAX_OUTPUT_PORT_TYPE 51 | sec_shi_r[0] << sec_shi_rr[0].DB_MAX_OUTPUT_PORT_TYPE 52 | sec_shi_r[1] << sec_shi_rr[1].DB_MAX_OUTPUT_PORT_TYPE 53 | sec_shi_r[2] << sec_shi_rr[2].DB_MAX_OUTPUT_PORT_TYPE 54 | sec_shi_r[3] << sec_shi_rr[3].DB_MAX_OUTPUT_PORT_TYPE 55 | min_ge_r[0] << min_ge_rr[0].DB_MAX_OUTPUT_PORT_TYPE 56 | min_ge_r[1] << min_ge_rr[1].DB_MAX_OUTPUT_PORT_TYPE 57 | min_ge_r[2] << min_ge_rr[2].DB_MAX_OUTPUT_PORT_TYPE 58 | min_ge_r[3] << min_ge_rr[3].DB_MAX_OUTPUT_PORT_TYPE 59 | min_shi_r[0] << min_shi_rr[0].DB_MAX_OUTPUT_PORT_TYPE 60 | min_shi_r[1] << min_shi_rr[1].DB_MAX_OUTPUT_PORT_TYPE 61 | min_shi_r[2] << min_shi_rr[2].DB_MAX_OUTPUT_PORT_TYPE 62 | min_shi_r[3] << min_shi_rr[3].DB_MAX_OUTPUT_PORT_TYPE 63 | hour_ge_r[0] << hour_ge_rr[0].DB_MAX_OUTPUT_PORT_TYPE 64 | hour_ge_r[1] << hour_ge_rr[1].DB_MAX_OUTPUT_PORT_TYPE 65 | hour_ge_r[2] << hour_ge_rr[2].DB_MAX_OUTPUT_PORT_TYPE 66 | hour_ge_r[3] << hour_ge_rr[3].DB_MAX_OUTPUT_PORT_TYPE 67 | hour_shi_r[0] << hour_shi_rr[0].DB_MAX_OUTPUT_PORT_TYPE 68 | hour_shi_r[1] << hour_shi_rr[1].DB_MAX_OUTPUT_PORT_TYPE 69 | hour_shi_r[2] << hour_shi_rr[2].DB_MAX_OUTPUT_PORT_TYPE 70 | hour_shi_r[3] << hour_shi_rr[3].DB_MAX_OUTPUT_PORT_TYPE 71 | data_out[0] << display_ctrl:display_ctrl_inst.data_out 72 | data_out[1] << display_ctrl:display_ctrl_inst.data_out 73 | data_out[2] << display_ctrl:display_ctrl_inst.data_out 74 | data_out[3] << display_ctrl:display_ctrl_inst.data_out 75 | data_out[4] << display_ctrl:display_ctrl_inst.data_out 76 | data_out[5] << display_ctrl:display_ctrl_inst.data_out 77 | data_out[6] << display_ctrl:display_ctrl_inst.data_out 78 | data_out[7] << display_ctrl:display_ctrl_inst.data_out 79 | select[0] << display_ctrl:display_ctrl_inst.select 80 | select[1] << display_ctrl:display_ctrl_inst.select 81 | select[2] << display_ctrl:display_ctrl_inst.select 82 | select[3] << display_ctrl:display_ctrl_inst.select 83 | select[4] << display_ctrl:display_ctrl_inst.select 84 | select[5] << display_ctrl:display_ctrl_inst.select 85 | select[6] << display_ctrl:display_ctrl_inst.select 86 | select[7] << display_ctrl:display_ctrl_inst.select 87 | 88 | 89 | |TOP|time_control:time_control_inst 90 | clk => clock_out~reg0.CLK 91 | clk => hour_shi[0].CLK 92 | clk => hour_shi[1].CLK 93 | clk => flag_hour_ge.CLK 94 | clk => hour_ge[0].CLK 95 | clk => hour_ge[1].CLK 96 | clk => hour_ge[2].CLK 97 | clk => hour_ge[3].CLK 98 | clk => flag_min_shi.CLK 99 | clk => min_shi[0].CLK 100 | clk => min_shi[1].CLK 101 | clk => min_shi[2].CLK 102 | clk => flag_min_ge.CLK 103 | clk => min_ge[0].CLK 104 | clk => min_ge[1].CLK 105 | clk => min_ge[2].CLK 106 | clk => min_ge[3].CLK 107 | clk => flag_sec_shi.CLK 108 | clk => sec_shi[0].CLK 109 | clk => sec_shi[1].CLK 110 | clk => sec_shi[2].CLK 111 | clk => flag_sec_ge.CLK 112 | clk => sec_ge[0].CLK 113 | clk => sec_ge[1].CLK 114 | clk => sec_ge[2].CLK 115 | clk => sec_ge[3].CLK 116 | clk => flag_1ms.CLK 117 | clk => cnt_1ms[0].CLK 118 | clk => cnt_1ms[1].CLK 119 | clk => cnt_1ms[2].CLK 120 | clk => cnt_1ms[3].CLK 121 | clk => cnt_1ms[4].CLK 122 | clk => cnt_1ms[5].CLK 123 | clk => cnt_1ms[6].CLK 124 | clk => cnt_1ms[7].CLK 125 | clk => cnt_1ms[8].CLK 126 | clk => cnt_1ms[9].CLK 127 | clk => cnt_1ms[10].CLK 128 | clk => cnt_1ms[11].CLK 129 | clk => cnt_1ms[12].CLK 130 | clk => cnt_1ms[13].CLK 131 | clk => cnt_1ms[14].CLK 132 | clk => cnt_1ms[15].CLK 133 | rst_n => flag_sec_ge.ACLR 134 | rst_n => sec_ge[0].ACLR 135 | rst_n => sec_ge[1].ACLR 136 | rst_n => sec_ge[2].ACLR 137 | rst_n => sec_ge[3].ACLR 138 | rst_n => clock_out~reg0.ACLR 139 | rst_n => flag_sec_shi.ACLR 140 | rst_n => sec_shi[0].ACLR 141 | rst_n => sec_shi[1].ACLR 142 | rst_n => sec_shi[2].ACLR 143 | rst_n => flag_min_ge.ACLR 144 | rst_n => min_ge[0].ACLR 145 | rst_n => min_ge[1].ACLR 146 | rst_n => min_ge[2].ACLR 147 | rst_n => min_ge[3].ACLR 148 | rst_n => flag_min_shi.ACLR 149 | rst_n => min_shi[0].ACLR 150 | rst_n => min_shi[1].ACLR 151 | rst_n => min_shi[2].ACLR 152 | rst_n => flag_hour_ge.ACLR 153 | rst_n => hour_ge[0].ACLR 154 | rst_n => hour_ge[1].ACLR 155 | rst_n => hour_ge[2].ACLR 156 | rst_n => hour_ge[3].ACLR 157 | rst_n => hour_shi[0].ACLR 158 | rst_n => hour_shi[1].ACLR 159 | rst_n => flag_1ms.ACLR 160 | rst_n => cnt_1ms[0].ACLR 161 | rst_n => cnt_1ms[1].ACLR 162 | rst_n => cnt_1ms[2].ACLR 163 | rst_n => cnt_1ms[3].ACLR 164 | rst_n => cnt_1ms[4].ACLR 165 | rst_n => cnt_1ms[5].ACLR 166 | rst_n => cnt_1ms[6].ACLR 167 | rst_n => cnt_1ms[7].ACLR 168 | rst_n => cnt_1ms[8].ACLR 169 | rst_n => cnt_1ms[9].ACLR 170 | rst_n => cnt_1ms[10].ACLR 171 | rst_n => cnt_1ms[11].ACLR 172 | rst_n => cnt_1ms[12].ACLR 173 | rst_n => cnt_1ms[13].ACLR 174 | rst_n => cnt_1ms[14].ACLR 175 | rst_n => cnt_1ms[15].ACLR 176 | set_time_finish => sec_ge.OUTPUTSELECT 177 | set_time_finish => sec_ge.OUTPUTSELECT 178 | set_time_finish => sec_ge.OUTPUTSELECT 179 | set_time_finish => sec_ge.OUTPUTSELECT 180 | set_time_finish => flag_sec_ge.OUTPUTSELECT 181 | set_time_finish => sec_shi.OUTPUTSELECT 182 | set_time_finish => sec_shi.OUTPUTSELECT 183 | set_time_finish => sec_shi.OUTPUTSELECT 184 | set_time_finish => flag_sec_shi.OUTPUTSELECT 185 | set_time_finish => min_ge.OUTPUTSELECT 186 | set_time_finish => min_ge.OUTPUTSELECT 187 | set_time_finish => min_ge.OUTPUTSELECT 188 | set_time_finish => min_ge.OUTPUTSELECT 189 | set_time_finish => flag_min_ge.OUTPUTSELECT 190 | set_time_finish => min_shi.OUTPUTSELECT 191 | set_time_finish => min_shi.OUTPUTSELECT 192 | set_time_finish => min_shi.OUTPUTSELECT 193 | set_time_finish => flag_min_shi.OUTPUTSELECT 194 | set_time_finish => hour_ge.OUTPUTSELECT 195 | set_time_finish => hour_ge.OUTPUTSELECT 196 | set_time_finish => hour_ge.OUTPUTSELECT 197 | set_time_finish => hour_ge.OUTPUTSELECT 198 | set_time_finish => flag_hour_ge.OUTPUTSELECT 199 | set_time_finish => hour_shi.OUTPUTSELECT 200 | set_time_finish => hour_shi.OUTPUTSELECT 201 | set_sec_ge[0] => sec_ge.DATAB 202 | set_sec_ge[1] => sec_ge.DATAB 203 | set_sec_ge[2] => sec_ge.DATAB 204 | set_sec_ge[3] => sec_ge.DATAB 205 | set_sec_shi[0] => sec_shi.DATAB 206 | set_sec_shi[1] => sec_shi.DATAB 207 | set_sec_shi[2] => sec_shi.DATAB 208 | set_sec_shi[3] => ~NO_FANOUT~ 209 | set_min_ge[0] => min_ge.DATAB 210 | set_min_ge[1] => min_ge.DATAB 211 | set_min_ge[2] => min_ge.DATAB 212 | set_min_ge[3] => min_ge.DATAB 213 | set_min_shi[0] => min_shi.DATAB 214 | set_min_shi[1] => min_shi.DATAB 215 | set_min_shi[2] => min_shi.DATAB 216 | set_min_shi[3] => ~NO_FANOUT~ 217 | set_hour_ge[0] => hour_ge.DATAB 218 | set_hour_ge[1] => hour_ge.DATAB 219 | set_hour_ge[2] => hour_ge.DATAB 220 | set_hour_ge[3] => hour_ge.DATAB 221 | set_hour_shi[0] => hour_shi.DATAB 222 | set_hour_shi[1] => hour_shi.DATAB 223 | set_hour_shi[2] => ~NO_FANOUT~ 224 | set_hour_shi[3] => ~NO_FANOUT~ 225 | clock_en => clock_out.OUTPUTSELECT 226 | clock_min_ge[0] => Equal8.IN6 227 | clock_min_ge[1] => Equal8.IN5 228 | clock_min_ge[2] => Equal8.IN4 229 | clock_min_ge[3] => Equal8.IN3 230 | clock_min_shi[0] => Equal8.IN10 231 | clock_min_shi[1] => Equal8.IN9 232 | clock_min_shi[2] => Equal8.IN8 233 | clock_min_shi[3] => Equal8.IN7 234 | clock_hour_ge[0] => Equal8.IN14 235 | clock_hour_ge[1] => Equal8.IN13 236 | clock_hour_ge[2] => Equal8.IN12 237 | clock_hour_ge[3] => Equal8.IN11 238 | clock_hour_shi[0] => Equal8.IN18 239 | clock_hour_shi[1] => Equal8.IN17 240 | clock_hour_shi[2] => Equal8.IN16 241 | clock_hour_shi[3] => Equal8.IN15 242 | clock_out <= clock_out~reg0.DB_MAX_OUTPUT_PORT_TYPE 243 | sec_ge_r[0] <= sec_ge[0].DB_MAX_OUTPUT_PORT_TYPE 244 | sec_ge_r[1] <= sec_ge[1].DB_MAX_OUTPUT_PORT_TYPE 245 | sec_ge_r[2] <= sec_ge[2].DB_MAX_OUTPUT_PORT_TYPE 246 | sec_ge_r[3] <= sec_ge[3].DB_MAX_OUTPUT_PORT_TYPE 247 | sec_shi_r[0] <= sec_shi[0].DB_MAX_OUTPUT_PORT_TYPE 248 | sec_shi_r[1] <= sec_shi[1].DB_MAX_OUTPUT_PORT_TYPE 249 | sec_shi_r[2] <= sec_shi[2].DB_MAX_OUTPUT_PORT_TYPE 250 | sec_shi_r[3] <= 251 | min_ge_r[0] <= min_ge[0].DB_MAX_OUTPUT_PORT_TYPE 252 | min_ge_r[1] <= min_ge[1].DB_MAX_OUTPUT_PORT_TYPE 253 | min_ge_r[2] <= min_ge[2].DB_MAX_OUTPUT_PORT_TYPE 254 | min_ge_r[3] <= min_ge[3].DB_MAX_OUTPUT_PORT_TYPE 255 | min_shi_r[0] <= min_shi[0].DB_MAX_OUTPUT_PORT_TYPE 256 | min_shi_r[1] <= min_shi[1].DB_MAX_OUTPUT_PORT_TYPE 257 | min_shi_r[2] <= min_shi[2].DB_MAX_OUTPUT_PORT_TYPE 258 | min_shi_r[3] <= 259 | hour_ge_r[0] <= hour_ge[0].DB_MAX_OUTPUT_PORT_TYPE 260 | hour_ge_r[1] <= hour_ge[1].DB_MAX_OUTPUT_PORT_TYPE 261 | hour_ge_r[2] <= hour_ge[2].DB_MAX_OUTPUT_PORT_TYPE 262 | hour_ge_r[3] <= hour_ge[3].DB_MAX_OUTPUT_PORT_TYPE 263 | hour_shi_r[0] <= hour_shi[0].DB_MAX_OUTPUT_PORT_TYPE 264 | hour_shi_r[1] <= hour_shi[1].DB_MAX_OUTPUT_PORT_TYPE 265 | hour_shi_r[2] <= 266 | hour_shi_r[3] <= 267 | 268 | 269 | |TOP|display_ctrl:display_ctrl_inst 270 | clk => sel[0].CLK 271 | clk => sel[1].CLK 272 | clk => sel[2].CLK 273 | clk => sel[3].CLK 274 | clk => sel[4].CLK 275 | clk => sel[5].CLK 276 | clk => sel[6].CLK 277 | clk => sel[7].CLK 278 | clk => display_data[0].CLK 279 | clk => display_data[1].CLK 280 | clk => display_data[2].CLK 281 | clk => display_data[3].CLK 282 | clk => m[0].CLK 283 | clk => m[1].CLK 284 | clk => m[2].CLK 285 | clk => m[3].CLK 286 | clk => m[4].CLK 287 | clk => m[5].CLK 288 | clk => m[6].CLK 289 | clk => m[7].CLK 290 | clk => m[8].CLK 291 | clk => m[9].CLK 292 | clk => m[10].CLK 293 | rst_n => m[0].ACLR 294 | rst_n => m[1].ACLR 295 | rst_n => m[2].ACLR 296 | rst_n => m[3].ACLR 297 | rst_n => m[4].ACLR 298 | rst_n => m[5].ACLR 299 | rst_n => m[6].ACLR 300 | rst_n => m[7].ACLR 301 | rst_n => m[8].ACLR 302 | rst_n => m[9].ACLR 303 | rst_n => m[10].ACLR 304 | sec_ge[0] => Mux4.IN2 305 | sec_ge[1] => Mux3.IN2 306 | sec_ge[2] => Mux2.IN2 307 | sec_ge[3] => Mux1.IN2 308 | sec_shi[0] => Mux4.IN3 309 | sec_shi[1] => Mux3.IN3 310 | sec_shi[2] => Mux2.IN3 311 | sec_shi[3] => Mux1.IN3 312 | min_ge[0] => Mux4.IN4 313 | min_ge[1] => Mux3.IN4 314 | min_ge[2] => Mux2.IN4 315 | min_ge[3] => Mux1.IN4 316 | min_shi[0] => Mux4.IN5 317 | min_shi[1] => Mux3.IN5 318 | min_shi[2] => Mux2.IN5 319 | min_shi[3] => Mux1.IN5 320 | hour_ge[0] => Mux4.IN6 321 | hour_ge[1] => Mux3.IN6 322 | hour_ge[2] => Mux2.IN6 323 | hour_ge[3] => Mux1.IN6 324 | hour_shi[0] => Mux4.IN7 325 | hour_shi[1] => Mux3.IN7 326 | hour_shi[2] => Mux2.IN7 327 | hour_shi[3] => Mux1.IN7 328 | data_out[0] <= data[0].DB_MAX_OUTPUT_PORT_TYPE 329 | data_out[1] <= data[1].DB_MAX_OUTPUT_PORT_TYPE 330 | data_out[2] <= data[2].DB_MAX_OUTPUT_PORT_TYPE 331 | data_out[3] <= data[3].DB_MAX_OUTPUT_PORT_TYPE 332 | data_out[4] <= data[4].DB_MAX_OUTPUT_PORT_TYPE 333 | data_out[5] <= data[5].DB_MAX_OUTPUT_PORT_TYPE 334 | data_out[6] <= data[6].DB_MAX_OUTPUT_PORT_TYPE 335 | data_out[7] <= 336 | select[0] <= sel[0].DB_MAX_OUTPUT_PORT_TYPE 337 | select[1] <= sel[1].DB_MAX_OUTPUT_PORT_TYPE 338 | select[2] <= sel[2].DB_MAX_OUTPUT_PORT_TYPE 339 | select[3] <= sel[3].DB_MAX_OUTPUT_PORT_TYPE 340 | select[4] <= sel[4].DB_MAX_OUTPUT_PORT_TYPE 341 | select[5] <= sel[5].DB_MAX_OUTPUT_PORT_TYPE 342 | select[6] <= sel[6].DB_MAX_OUTPUT_PORT_TYPE 343 | select[7] <= sel[7].DB_MAX_OUTPUT_PORT_TYPE 344 | 345 | 346 | -------------------------------------------------------------------------------- /db/Digital_Clock.hif: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/DOOKNET/Digital_Clock/c56f1dbf5b4fb8fe69f5c27d19749ed98fe408a7/db/Digital_Clock.hif -------------------------------------------------------------------------------- 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HierarchyInputConstant InputUnused InputFloating InputOutputConstant OutputUnused OutputFloating OutputBidirConstant BidirUnused BidirInput only BidirOutput only Bidir
display_ctrl_inst261011611100000
time_control_inst444442544400000
51 | -------------------------------------------------------------------------------- /db/Digital_Clock.lpc.rdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/DOOKNET/Digital_Clock/c56f1dbf5b4fb8fe69f5c27d19749ed98fe408a7/db/Digital_Clock.lpc.rdb -------------------------------------------------------------------------------- /db/Digital_Clock.lpc.txt: -------------------------------------------------------------------------------- 1 | +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ 2 | ; Legal Partition Candidates ; 3 | +-------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ 4 | ; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ; 5 | +-------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ 6 | ; display_ctrl_inst ; 26 ; 1 ; 0 ; 1 ; 16 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 7 | ; time_control_inst ; 44 ; 4 ; 4 ; 4 ; 25 ; 4 ; 4 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 8 | +-------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ 9 | -------------------------------------------------------------------------------- /db/Digital_Clock.map.cdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/DOOKNET/Digital_Clock/c56f1dbf5b4fb8fe69f5c27d19749ed98fe408a7/db/Digital_Clock.map.cdb -------------------------------------------------------------------------------- /db/Digital_Clock.map.hdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/DOOKNET/Digital_Clock/c56f1dbf5b4fb8fe69f5c27d19749ed98fe408a7/db/Digital_Clock.map.hdb -------------------------------------------------------------------------------- /db/Digital_Clock.map.logdb: -------------------------------------------------------------------------------- 1 | v1 2 | -------------------------------------------------------------------------------- /db/Digital_Clock.map.qmsg: -------------------------------------------------------------------------------- 1 | { "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1526978045072 ""} 2 | { "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Elaboration Quartus Prime " "Running Quartus Prime Analysis & Elaboration" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 17.1.0 Build 590 10/25/2017 SJ Standard Edition " "Version 17.1.0 Build 590 10/25/2017 SJ Standard Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1526978045073 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue May 22 16:34:04 2018 " "Processing started: Tue May 22 16:34:04 2018" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1526978045073 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Design Software" 0 -1 1526978045073 ""} 3 | { "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off Digital_Clock -c Digital_Clock --analysis_and_elaboration " "Command: quartus_map --read_settings_files=on --write_settings_files=off Digital_Clock -c Digital_Clock --analysis_and_elaboration" { } { } 0 0 "Command: %1!s!" 0 0 "Design Software" 0 -1 1526978045073 ""} 4 | { "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Design Software" 0 -1 1526978045616 ""} 5 | { "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Design Software" 0 -1 1526978045616 ""} 6 | { "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "code/top.v 1 1 " "Found 1 design units, including 1 entities, in source file code/top.v" { { "Info" "ISGN_ENTITY_NAME" "1 TOP " "Found entity 1: TOP" { } { { "Code/TOP.v" "" { Text "E:/Workspace/Quartus_17.1/2018_5_9_Digital_Clock/Code/TOP.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1526978065023 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Design Software" 0 -1 1526978065023 ""} 7 | { "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "code/display_ctrl.v 1 1 " "Found 1 design units, including 1 entities, in source file code/display_ctrl.v" { { "Info" "ISGN_ENTITY_NAME" "1 display_ctrl " "Found entity 1: display_ctrl" { } { { "Code/display_ctrl.v" "" { Text "E:/Workspace/Quartus_17.1/2018_5_9_Digital_Clock/Code/display_ctrl.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1526978065029 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Design Software" 0 -1 1526978065029 ""} 8 | { "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "code/time_control.v 1 1 " "Found 1 design units, including 1 entities, in source file code/time_control.v" { { "Info" "ISGN_ENTITY_NAME" "1 time_control " "Found entity 1: time_control" { } { { "Code/time_control.v" "" { Text "E:/Workspace/Quartus_17.1/2018_5_9_Digital_Clock/Code/time_control.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1526978065033 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Design Software" 0 -1 1526978065033 ""} 9 | { "Info" "ISGN_START_ELABORATION_TOP" "TOP " "Elaborating entity \"TOP\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Design Software" 0 -1 1526978065106 ""} 10 | { "Info" "ISGN_START_ELABORATION_HIERARCHY" "time_control time_control:time_control_inst " "Elaborating entity \"time_control\" for hierarchy \"time_control:time_control_inst\"" { } { { "Code/TOP.v" "time_control_inst" { Text "E:/Workspace/Quartus_17.1/2018_5_9_Digital_Clock/Code/TOP.v" 71 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Design Software" 0 -1 1526978065114 ""} 11 | { "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "flag_1s time_control.v(48) " "Verilog HDL or VHDL warning at time_control.v(48): object \"flag_1s\" assigned a value but never read" { } { { "Code/time_control.v" "" { Text "E:/Workspace/Quartus_17.1/2018_5_9_Digital_Clock/Code/time_control.v" 48 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Analysis & Synthesis" 0 -1 1526978065117 "|TOP|time_control:time_control_inst"} 12 | { "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "flag_hour_shi time_control.v(186) " "Verilog HDL or VHDL warning at time_control.v(186): object \"flag_hour_shi\" assigned a value but never read" { } { { "Code/time_control.v" "" { Text "E:/Workspace/Quartus_17.1/2018_5_9_Digital_Clock/Code/time_control.v" 186 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Analysis & Synthesis" 0 -1 1526978065117 "|TOP|time_control:time_control_inst"} 13 | { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 time_control.v(42) " "Verilog HDL assignment warning at time_control.v(42): truncated value with size 32 to match size of target (16)" { } { { "Code/time_control.v" "" { Text "E:/Workspace/Quartus_17.1/2018_5_9_Digital_Clock/Code/time_control.v" 42 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1526978065117 "|TOP|time_control:time_control_inst"} 14 | { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 12 time_control.v(60) " "Verilog HDL assignment warning at time_control.v(60): truncated value with size 32 to match size of target (12)" { } { { "Code/time_control.v" "" { Text "E:/Workspace/Quartus_17.1/2018_5_9_Digital_Clock/Code/time_control.v" 60 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1526978065117 "|TOP|time_control:time_control_inst"} 15 | { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 time_control.v(93) " "Verilog HDL assignment warning at time_control.v(93): truncated value with size 32 to match size of target (4)" { } { { "Code/time_control.v" "" { Text "E:/Workspace/Quartus_17.1/2018_5_9_Digital_Clock/Code/time_control.v" 93 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1526978065117 "|TOP|time_control:time_control_inst"} 16 | { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "4 3 time_control.v(108) " "Verilog HDL assignment warning at time_control.v(108): truncated value with size 4 to match size of target (3)" { } { { "Code/time_control.v" "" { Text "E:/Workspace/Quartus_17.1/2018_5_9_Digital_Clock/Code/time_control.v" 108 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1526978065117 "|TOP|time_control:time_control_inst"} 17 | { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 time_control.v(117) " "Verilog HDL assignment warning at time_control.v(117): truncated value with size 32 to match size of target (3)" { } { { "Code/time_control.v" "" { Text "E:/Workspace/Quartus_17.1/2018_5_9_Digital_Clock/Code/time_control.v" 117 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1526978065117 "|TOP|time_control:time_control_inst"} 18 | { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 time_control.v(148) " "Verilog HDL assignment warning at time_control.v(148): truncated value with size 32 to match size of target (4)" { } { { "Code/time_control.v" "" { Text "E:/Workspace/Quartus_17.1/2018_5_9_Digital_Clock/Code/time_control.v" 148 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1526978065117 "|TOP|time_control:time_control_inst"} 19 | { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "4 3 time_control.v(163) " "Verilog HDL assignment warning at time_control.v(163): truncated value with size 4 to match size of target (3)" { } { { "Code/time_control.v" "" { Text "E:/Workspace/Quartus_17.1/2018_5_9_Digital_Clock/Code/time_control.v" 163 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1526978065118 "|TOP|time_control:time_control_inst"} 20 | { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 time_control.v(172) " "Verilog HDL assignment warning at time_control.v(172): truncated value with size 32 to match size of target (3)" { } { { "Code/time_control.v" "" { Text "E:/Workspace/Quartus_17.1/2018_5_9_Digital_Clock/Code/time_control.v" 172 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1526978065118 "|TOP|time_control:time_control_inst"} 21 | { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 time_control.v(207) " "Verilog HDL assignment warning at time_control.v(207): truncated value with size 32 to match size of target (4)" { } { { "Code/time_control.v" "" { Text "E:/Workspace/Quartus_17.1/2018_5_9_Digital_Clock/Code/time_control.v" 207 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1526978065118 "|TOP|time_control:time_control_inst"} 22 | { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "4 2 time_control.v(222) " "Verilog HDL assignment warning at time_control.v(222): truncated value with size 4 to match size of target (2)" { } { { "Code/time_control.v" "" { Text "E:/Workspace/Quartus_17.1/2018_5_9_Digital_Clock/Code/time_control.v" 222 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1526978065118 "|TOP|time_control:time_control_inst"} 23 | { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 2 time_control.v(231) " "Verilog HDL assignment warning at time_control.v(231): truncated value with size 32 to match size of target (2)" { } { { "Code/time_control.v" "" { Text "E:/Workspace/Quartus_17.1/2018_5_9_Digital_Clock/Code/time_control.v" 231 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1526978065118 "|TOP|time_control:time_control_inst"} 24 | { "Info" "ISGN_START_ELABORATION_HIERARCHY" "display_ctrl display_ctrl:display_ctrl_inst " "Elaborating entity \"display_ctrl\" for hierarchy \"display_ctrl:display_ctrl_inst\"" { } { { "Code/TOP.v" "display_ctrl_inst" { Text "E:/Workspace/Quartus_17.1/2018_5_9_Digital_Clock/Code/TOP.v" 84 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Design Software" 0 -1 1526978065120 ""} 25 | { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 11 display_ctrl.v(26) " "Verilog HDL assignment warning at display_ctrl.v(26): truncated value with size 32 to match size of target (11)" { } { { "Code/display_ctrl.v" "" { Text "E:/Workspace/Quartus_17.1/2018_5_9_Digital_Clock/Code/display_ctrl.v" 26 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Design Software" 0 -1 1526978065130 "|TOP|display_ctrl:display_ctrl_inst"} 26 | { "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "data display_ctrl.v(85) " "Verilog HDL Always Construct warning at display_ctrl.v(85): variable \"data\" is read inside the Always Construct but isn't in the Always Construct's Event Control" { } { { "Code/display_ctrl.v" "" { Text "E:/Workspace/Quartus_17.1/2018_5_9_Digital_Clock/Code/display_ctrl.v" 85 0 0 } } } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0 "Design Software" 0 -1 1526978065131 "|TOP|display_ctrl:display_ctrl_inst"} 27 | { "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "data display_ctrl.v(73) " "Verilog HDL Always Construct warning at display_ctrl.v(73): inferring latch(es) for variable \"data\", which holds its previous value in one or more paths through the always construct" { } { { "Code/display_ctrl.v" "" { Text "E:/Workspace/Quartus_17.1/2018_5_9_Digital_Clock/Code/display_ctrl.v" 73 0 0 } } } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Design Software" 0 -1 1526978065132 "|TOP|display_ctrl:display_ctrl_inst"} 28 | { "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "data\[0\] display_ctrl.v(73) " "Inferred latch for \"data\[0\]\" at display_ctrl.v(73)" { } { { "Code/display_ctrl.v" "" { Text "E:/Workspace/Quartus_17.1/2018_5_9_Digital_Clock/Code/display_ctrl.v" 73 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Design Software" 0 -1 1526978065133 "|TOP|display_ctrl:display_ctrl_inst"} 29 | { "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "data\[1\] display_ctrl.v(73) " "Inferred latch for \"data\[1\]\" at display_ctrl.v(73)" { } { { "Code/display_ctrl.v" "" { Text "E:/Workspace/Quartus_17.1/2018_5_9_Digital_Clock/Code/display_ctrl.v" 73 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Design Software" 0 -1 1526978065133 "|TOP|display_ctrl:display_ctrl_inst"} 30 | { "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "data\[2\] display_ctrl.v(73) " "Inferred latch for \"data\[2\]\" at display_ctrl.v(73)" { } { { "Code/display_ctrl.v" "" { Text "E:/Workspace/Quartus_17.1/2018_5_9_Digital_Clock/Code/display_ctrl.v" 73 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Design Software" 0 -1 1526978065133 "|TOP|display_ctrl:display_ctrl_inst"} 31 | { "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "data\[3\] display_ctrl.v(73) " "Inferred latch for \"data\[3\]\" at display_ctrl.v(73)" { } { { "Code/display_ctrl.v" "" { Text "E:/Workspace/Quartus_17.1/2018_5_9_Digital_Clock/Code/display_ctrl.v" 73 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Design Software" 0 -1 1526978065133 "|TOP|display_ctrl:display_ctrl_inst"} 32 | { "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "data\[4\] display_ctrl.v(73) " "Inferred latch for \"data\[4\]\" at display_ctrl.v(73)" { } { { "Code/display_ctrl.v" "" { Text "E:/Workspace/Quartus_17.1/2018_5_9_Digital_Clock/Code/display_ctrl.v" 73 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Design Software" 0 -1 1526978065133 "|TOP|display_ctrl:display_ctrl_inst"} 33 | { "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "data\[5\] display_ctrl.v(73) " "Inferred latch for \"data\[5\]\" at display_ctrl.v(73)" { } { { "Code/display_ctrl.v" "" { Text "E:/Workspace/Quartus_17.1/2018_5_9_Digital_Clock/Code/display_ctrl.v" 73 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Design Software" 0 -1 1526978065134 "|TOP|display_ctrl:display_ctrl_inst"} 34 | { "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "data\[6\] display_ctrl.v(73) " "Inferred latch for \"data\[6\]\" at display_ctrl.v(73)" { } { { "Code/display_ctrl.v" "" { Text "E:/Workspace/Quartus_17.1/2018_5_9_Digital_Clock/Code/display_ctrl.v" 73 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Design Software" 0 -1 1526978065134 "|TOP|display_ctrl:display_ctrl_inst"} 35 | { "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "data\[7\] display_ctrl.v(73) " "Inferred latch for \"data\[7\]\" at display_ctrl.v(73)" { } { { "Code/display_ctrl.v" "" { Text "E:/Workspace/Quartus_17.1/2018_5_9_Digital_Clock/Code/display_ctrl.v" 73 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Design Software" 0 -1 1526978065134 "|TOP|display_ctrl:display_ctrl_inst"} 36 | { "Info" "IQEXE_ERROR_COUNT" "Analysis & Elaboration 0 s 17 s Quartus Prime " "Quartus Prime Analysis & Elaboration was successful. 0 errors, 17 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4715 " "Peak virtual memory: 4715 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1526978065279 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue May 22 16:34:25 2018 " "Processing ended: Tue May 22 16:34:25 2018" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1526978065279 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:21 " "Elapsed time: 00:00:21" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1526978065279 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:48 " "Total CPU time (on all processors): 00:00:48" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1526978065279 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Design Software" 0 -1 1526978065279 ""} 37 | -------------------------------------------------------------------------------- /db/Digital_Clock.map.rdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/DOOKNET/Digital_Clock/c56f1dbf5b4fb8fe69f5c27d19749ed98fe408a7/db/Digital_Clock.map.rdb -------------------------------------------------------------------------------- /db/Digital_Clock.npp.qmsg: -------------------------------------------------------------------------------- 1 | { "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1526980143809 ""} 2 | { "Info" "IQEXE_START_BANNER_PRODUCT" "Netlist Viewers Preprocess Quartus Prime " "Running Quartus Prime Netlist Viewers Preprocess" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 17.1.0 Build 590 10/25/2017 SJ Standard Edition " "Version 17.1.0 Build 590 10/25/2017 SJ Standard Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1526980143816 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue May 22 17:09:03 2018 " "Processing started: Tue May 22 17:09:03 2018" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1526980143816 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Netlist Viewers Preprocess" 0 -1 1526980143816 ""} 3 | { "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_npp Digital_Clock -c Digital_Clock --netlist_type=sgate " "Command: quartus_npp Digital_Clock -c Digital_Clock --netlist_type=sgate" { } { } 0 0 "Command: %1!s!" 0 0 "Netlist Viewers Preprocess" 0 -1 1526980143816 ""} 4 | { "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Netlist Viewers Preprocess" 0 -1 1526980144064 ""} 5 | { "Info" "IQEXE_ERROR_COUNT" "Netlist Viewers Preprocess 0 s 1 Quartus Prime " "Quartus Prime Netlist Viewers Preprocess was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4563 " "Peak virtual memory: 4563 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1526980144097 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue May 22 17:09:04 2018 " "Processing ended: Tue May 22 17:09:04 2018" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1526980144097 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1526980144097 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 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/db/Digital_Clock.smart_action.txt: -------------------------------------------------------------------------------- 1 | SOURCE 2 | -------------------------------------------------------------------------------- /db/Digital_Clock.tis_db_list.ddb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/DOOKNET/Digital_Clock/c56f1dbf5b4fb8fe69f5c27d19749ed98fe408a7/db/Digital_Clock.tis_db_list.ddb -------------------------------------------------------------------------------- /db/prev_cmp_Digital_Clock.qmsg: -------------------------------------------------------------------------------- 1 | { "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1526977452807 ""} 2 | { "Info" "IQEXE_START_BANNER_PRODUCT" "Netlist Viewers Preprocess Quartus Prime " "Running Quartus Prime Netlist Viewers Preprocess" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 17.1.0 Build 590 10/25/2017 SJ Standard Edition " "Version 17.1.0 Build 590 10/25/2017 SJ Standard Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1526977452816 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue May 22 16:24:12 2018 " "Processing started: Tue May 22 16:24:12 2018" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1526977452816 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Netlist Viewers Preprocess" 0 -1 1526977452816 ""} 3 | { "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_npp Digital_Clock -c Digital_Clock --netlist_type=sgate " "Command: quartus_npp Digital_Clock -c Digital_Clock --netlist_type=sgate" { } { } 0 0 "Command: %1!s!" 0 0 "Netlist Viewers Preprocess" 0 -1 1526977452816 ""} 4 | { "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Netlist Viewers Preprocess" 0 -1 1526977453062 ""} 5 | { "Info" "IQEXE_ERROR_COUNT" "Netlist Viewers Preprocess 0 s 1 Quartus Prime " "Quartus Prime Netlist Viewers Preprocess was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4564 " "Peak virtual memory: 4564 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1526977453098 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue May 22 16:24:13 2018 " "Processing ended: Tue May 22 16:24:13 2018" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1526977453098 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1526977453098 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1526977453098 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Netlist Viewers Preprocess" 0 -1 1526977453098 ""} 6 | -------------------------------------------------------------------------------- /incremental_db/README: -------------------------------------------------------------------------------- 1 | This folder contains data for incremental compilation. 2 | 3 | The compiled_partitions sub-folder contains previous compilation results for each partition. 4 | As long as this folder is preserved, incremental compilation results from earlier compiles 5 | can be re-used. To perform a clean compilation from source files for all partitions, both 6 | the db and incremental_db folder should be removed. 7 | 8 | The imported_partitions sub-folder contains the last imported QXP for each imported partition. 9 | As long as this folder is preserved, imported partitions will be automatically re-imported 10 | when the db or incremental_db/compiled_partitions folders are removed. 11 | 12 | -------------------------------------------------------------------------------- /incremental_db/compiled_partitions/Digital_Clock.db_info: -------------------------------------------------------------------------------- 1 | Quartus_Version = Version 17.1.0 Build 590 10/25/2017 SJ Standard Edition 2 | Version_Index = 453135872 3 | Creation_Time = Mon May 14 04:15:35 2018 4 | -------------------------------------------------------------------------------- /incremental_db/compiled_partitions/Digital_Clock.root_partition.map.kpt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/DOOKNET/Digital_Clock/c56f1dbf5b4fb8fe69f5c27d19749ed98fe408a7/incremental_db/compiled_partitions/Digital_Clock.root_partition.map.kpt -------------------------------------------------------------------------------- /output_files/Digital_Clock.done: -------------------------------------------------------------------------------- 1 | Tue May 22 17:09:04 2018 2 | -------------------------------------------------------------------------------- /output_files/Digital_Clock.flow.rpt: -------------------------------------------------------------------------------- 1 | Flow report for Digital_Clock 2 | Tue May 22 16:34:25 2018 3 | Quartus Prime Version 17.1.0 Build 590 10/25/2017 SJ Standard Edition 4 | 5 | 6 | --------------------- 7 | ; Table of Contents ; 8 | --------------------- 9 | 1. Legal Notice 10 | 2. Flow Summary 11 | 3. Flow Settings 12 | 4. Flow Non-Default Global Settings 13 | 5. Flow Elapsed Time 14 | 6. Flow OS Summary 15 | 7. Flow Log 16 | 8. Flow Messages 17 | 9. Flow Suppressed Messages 18 | 19 | 20 | 21 | ---------------- 22 | ; Legal Notice ; 23 | ---------------- 24 | Copyright (C) 2017 Intel Corporation. All rights reserved. 25 | Your use of Intel Corporation's design tools, logic functions 26 | and other software and tools, and its AMPP partner logic 27 | functions, and any output files from any of the foregoing 28 | (including device programming or simulation files), and any 29 | associated documentation or information are expressly subject 30 | to the terms and conditions of the Intel Program License 31 | Subscription Agreement, the Intel Quartus Prime License Agreement, 32 | the Intel FPGA IP License Agreement, or other applicable license 33 | agreement, including, without limitation, that your use is for 34 | the sole purpose of programming logic devices manufactured by 35 | Intel and sold by Intel or its authorized distributors. Please 36 | refer to the applicable agreement for further details. 37 | 38 | 39 | 40 | +-------------------------------------------------------------------------+ 41 | ; Flow Summary ; 42 | +-----------------------+-------------------------------------------------+ 43 | ; Flow Status ; Successful - Tue May 22 16:34:25 2018 ; 44 | ; Quartus Prime Version ; 17.1.0 Build 590 10/25/2017 SJ Standard Edition ; 45 | ; Revision Name ; Digital_Clock ; 46 | ; Top-level Entity Name ; TOP ; 47 | ; Family ; MAX II ; 48 | ; Device ; EPM2210F324C5 ; 49 | ; Timing Models ; Final ; 50 | +-----------------------+-------------------------------------------------+ 51 | 52 | 53 | +-----------------------------------------+ 54 | ; Flow Settings ; 55 | +-------------------+---------------------+ 56 | ; Option ; Setting ; 57 | +-------------------+---------------------+ 58 | ; Start date & time ; 05/22/2018 16:34:05 ; 59 | ; Main task ; Compilation ; 60 | ; Revision Name ; Digital_Clock ; 61 | +-------------------+---------------------+ 62 | 63 | 64 | +------------------------------------------------------------------------------------------------------------------------+ 65 | ; Flow Non-Default Global Settings ; 66 | +---------------------------------------+---------------------------------+---------------+-------------+----------------+ 67 | ; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ; 68 | +---------------------------------------+---------------------------------+---------------+-------------+----------------+ 69 | ; COMPILER_SIGNATURE_ID ; 264390066597439.152697804513956 ; -- ; -- ; -- ; 70 | ; EDA_DESIGN_INSTANCE_NAME ; NA ; -- ; -- ; tb_TOP ; 71 | ; EDA_NATIVELINK_PORTABLE_FILE_PATHS ; On ; -- ; -- ; eda_simulation ; 72 | ; EDA_NATIVELINK_SIMULATION_TEST_BENCH ; tb_TOP ; -- ; -- ; eda_simulation ; 73 | ; EDA_OUTPUT_DATA_FORMAT ; Verilog Hdl ; -- ; -- ; eda_simulation ; 74 | ; EDA_SIMULATION_TOOL ; ModelSim-Altera (Verilog) ; ; -- ; -- ; 75 | ; EDA_TEST_BENCH_ENABLE_STATUS ; TEST_BENCH_MODE ; -- ; -- ; eda_simulation ; 76 | ; EDA_TEST_BENCH_FILE ; TestBench/tb_TOP.v ; -- ; -- ; tb_TOP ; 77 | ; EDA_TEST_BENCH_MODULE_NAME ; tb_TOP ; -- ; -- ; tb_TOP ; 78 | ; EDA_TEST_BENCH_NAME ; tb_TOP ; -- ; -- ; eda_simulation ; 79 | ; EDA_TIME_SCALE ; 1 ps ; -- ; -- ; eda_simulation ; 80 | ; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ; 81 | ; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ; 82 | ; POWER_EXT_SUPPLY_VOLTAGE_TO_REGULATOR ; 3.3V ; -- ; -- ; -- ; 83 | ; POWER_PRESET_COOLING_SOLUTION ; No Heat Sink With Still Air ; -- ; -- ; -- ; 84 | ; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ; 85 | ; TOP_LEVEL_ENTITY ; TOP ; Digital_Clock ; -- ; -- ; 86 | +---------------------------------------+---------------------------------+---------------+-------------+----------------+ 87 | 88 | 89 | +----------------------------------------------------------------------------------------------------------------------------+ 90 | ; Flow Elapsed Time ; 91 | +------------------------+--------------+-------------------------+---------------------+------------------------------------+ 92 | ; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ; 93 | +------------------------+--------------+-------------------------+---------------------+------------------------------------+ 94 | ; Analysis & Elaboration ; 00:00:21 ; 1.0 ; 4715 MB ; 00:00:48 ; 95 | ; Total ; 00:00:21 ; -- ; -- ; 00:00:48 ; 96 | +------------------------+--------------+-------------------------+---------------------+------------------------------------+ 97 | 98 | 99 | +--------------------------------------------------------------------------------------+ 100 | ; Flow OS Summary ; 101 | +------------------------+------------------+------------+------------+----------------+ 102 | ; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ; 103 | +------------------------+------------------+------------+------------+----------------+ 104 | ; Analysis & Elaboration ; DESKTOP-JC6NIF0 ; Windows 10 ; 10.0 ; x86_64 ; 105 | +------------------------+------------------+------------+------------+----------------+ 106 | 107 | 108 | ------------ 109 | ; Flow Log ; 110 | ------------ 111 | quartus_map --read_settings_files=on --write_settings_files=off Digital_Clock -c Digital_Clock --analysis_and_elaboration 112 | 113 | 114 | 115 | -------------------------------------------------------------------------------- /output_files/Digital_Clock.map.rpt: -------------------------------------------------------------------------------- 1 | Analysis & Elaboration report for Digital_Clock 2 | Tue May 22 16:34:25 2018 3 | Quartus Prime Version 17.1.0 Build 590 10/25/2017 SJ Standard Edition 4 | 5 | 6 | --------------------- 7 | ; Table of Contents ; 8 | --------------------- 9 | 1. Legal Notice 10 | 2. Analysis & Elaboration Summary 11 | 3. Parallel Compilation 12 | 4. Analysis & Elaboration Settings 13 | 5. Analysis & Elaboration Messages 14 | 15 | 16 | 17 | ---------------- 18 | ; Legal Notice ; 19 | ---------------- 20 | Copyright (C) 2017 Intel Corporation. All rights reserved. 21 | Your use of Intel Corporation's design tools, logic functions 22 | and other software and tools, and its AMPP partner logic 23 | functions, and any output files from any of the foregoing 24 | (including device programming or simulation files), and any 25 | associated documentation or information are expressly subject 26 | to the terms and conditions of the Intel Program License 27 | Subscription Agreement, the Intel Quartus Prime License Agreement, 28 | the Intel FPGA IP License Agreement, or other applicable license 29 | agreement, including, without limitation, that your use is for 30 | the sole purpose of programming logic devices manufactured by 31 | Intel and sold by Intel or its authorized distributors. Please 32 | refer to the applicable agreement for further details. 33 | 34 | 35 | 36 | +---------------------------------------------------------------------------------+ 37 | ; Analysis & Elaboration Summary ; 38 | +-------------------------------+-------------------------------------------------+ 39 | ; Analysis & Elaboration Status ; Successful - Tue May 22 16:34:25 2018 ; 40 | ; Quartus Prime Version ; 17.1.0 Build 590 10/25/2017 SJ Standard Edition ; 41 | ; Revision Name ; Digital_Clock ; 42 | ; Top-level Entity Name ; TOP ; 43 | ; Family ; MAX II ; 44 | +-------------------------------+-------------------------------------------------+ 45 | 46 | 47 | +------------------------------------------+ 48 | ; Parallel Compilation ; 49 | +----------------------------+-------------+ 50 | ; Processors ; Number ; 51 | +----------------------------+-------------+ 52 | ; Number detected on machine ; 4 ; 53 | ; Maximum allowed ; 2 ; 54 | ; ; ; 55 | ; Average used ; 1.00 ; 56 | ; Maximum used ; 1 ; 57 | ; ; ; 58 | ; Usage by Processor ; % Time Used ; 59 | ; Processor 1 ; 100.0% ; 60 | +----------------------------+-------------+ 61 | 62 | 63 | +----------------------------------------------------------------------------------------------------------------------+ 64 | ; Analysis & Elaboration Settings ; 65 | +----------------------------------------------------------------------------+--------------------+--------------------+ 66 | ; Option ; Setting ; Default Value ; 67 | +----------------------------------------------------------------------------+--------------------+--------------------+ 68 | ; Device ; EPM2210F324C5 ; ; 69 | ; Top-level entity name ; TOP ; Digital_Clock ; 70 | ; Family name ; MAX II ; Cyclone V ; 71 | ; Use smart compilation ; Off ; Off ; 72 | ; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ; 73 | ; Enable compact report table ; Off ; Off ; 74 | ; Restructure Multiplexers ; Auto ; Auto ; 75 | ; Create Debugging Nodes for IP Cores ; Off ; Off ; 76 | ; Preserve fewer node names ; On ; On ; 77 | ; Intel FPGA IP Evaluation Mode ; Enable ; Enable ; 78 | ; Verilog Version ; Verilog_2001 ; Verilog_2001 ; 79 | ; VHDL Version ; VHDL_1993 ; VHDL_1993 ; 80 | ; State Machine Processing ; Auto ; Auto ; 81 | ; Safe State Machine ; Off ; Off ; 82 | ; Extract Verilog State Machines ; On ; On ; 83 | ; Extract VHDL State Machines ; On ; On ; 84 | ; Ignore Verilog initial constructs ; Off ; Off ; 85 | ; Iteration limit for constant Verilog loops ; 5000 ; 5000 ; 86 | ; Iteration limit for non-constant Verilog loops ; 250 ; 250 ; 87 | ; Add Pass-Through Logic to Inferred RAMs ; On ; On ; 88 | ; Infer RAMs from Raw Logic ; On ; On ; 89 | ; Parallel Synthesis ; On ; On ; 90 | ; NOT Gate Push-Back ; On ; On ; 91 | ; Power-Up Don't Care ; On ; On ; 92 | ; Remove Redundant Logic Cells ; Off ; Off ; 93 | ; Remove Duplicate Registers ; On ; On ; 94 | ; Ignore CARRY Buffers ; Off ; Off ; 95 | ; Ignore CASCADE Buffers ; Off ; Off ; 96 | ; Ignore GLOBAL Buffers ; Off ; Off ; 97 | ; Ignore ROW GLOBAL Buffers ; Off ; Off ; 98 | ; Ignore LCELL Buffers ; Off ; Off ; 99 | ; Ignore SOFT Buffers ; On ; On ; 100 | ; Limit AHDL Integers to 32 Bits ; Off ; Off ; 101 | ; Optimization Technique ; Balanced ; Balanced ; 102 | ; Carry Chain Length ; 70 ; 70 ; 103 | ; Auto Carry Chains ; On ; On ; 104 | ; Auto Open-Drain Pins ; On ; On ; 105 | ; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ; 106 | ; Auto Shift Register Replacement ; Auto ; Auto ; 107 | ; Allow Shift Register Merging across Hierarchies ; Auto ; Auto ; 108 | ; Auto Clock Enable Replacement ; On ; On ; 109 | ; Allow Synchronous Control Signals ; On ; On ; 110 | ; Force Use of Synchronous Clear Signals ; Off ; Off ; 111 | ; Auto Resource Sharing ; Off ; Off ; 112 | ; Use LogicLock Constraints during Resource Balancing ; On ; On ; 113 | ; Ignore translate_off and synthesis_off directives ; Off ; Off ; 114 | ; Report Parameter Settings ; On ; On ; 115 | ; Report Source Assignments ; On ; On ; 116 | ; Report Connectivity Checks ; On ; On ; 117 | ; Ignore Maximum Fan-Out Assignments ; Off ; Off ; 118 | ; Synchronization Register Chain Length ; 2 ; 2 ; 119 | ; Power Optimization During Synthesis ; Normal compilation ; Normal compilation ; 120 | ; HDL message level ; Level2 ; Level2 ; 121 | ; Suppress Register Optimization Related Messages ; Off ; Off ; 122 | ; Number of Removed Registers Reported in Synthesis Report ; 5000 ; 5000 ; 123 | ; Number of Swept Nodes Reported in Synthesis Report ; 5000 ; 5000 ; 124 | ; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ; 125 | ; Clock MUX Protection ; On ; On ; 126 | ; Block Design Naming ; Auto ; Auto ; 127 | ; Synthesis Effort ; Auto ; Auto ; 128 | ; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ; 129 | ; Analysis & Synthesis Message Level ; Medium ; Medium ; 130 | ; Disable Register Merging Across Hierarchies ; Auto ; Auto ; 131 | +----------------------------------------------------------------------------+--------------------+--------------------+ 132 | 133 | 134 | +---------------------------------+ 135 | ; Analysis & Elaboration Messages ; 136 | +---------------------------------+ 137 | Info: ******************************************************************* 138 | Info: Running Quartus Prime Analysis & Elaboration 139 | Info: Version 17.1.0 Build 590 10/25/2017 SJ Standard Edition 140 | Info: Processing started: Tue May 22 16:34:04 2018 141 | Info: Command: quartus_map --read_settings_files=on --write_settings_files=off Digital_Clock -c Digital_Clock --analysis_and_elaboration 142 | Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. 143 | Info (20030): Parallel compilation is enabled and will use 2 of the 2 processors detected 144 | Info (12021): Found 1 design units, including 1 entities, in source file code/top.v 145 | Info (12023): Found entity 1: TOP File: E:/Workspace/Quartus_17.1/2018_5_9_Digital_Clock/Code/TOP.v Line: 1 146 | Info (12021): Found 1 design units, including 1 entities, in source file code/display_ctrl.v 147 | Info (12023): Found entity 1: display_ctrl File: E:/Workspace/Quartus_17.1/2018_5_9_Digital_Clock/Code/display_ctrl.v Line: 1 148 | Info (12021): Found 1 design units, including 1 entities, in source file code/time_control.v 149 | Info (12023): Found entity 1: time_control File: E:/Workspace/Quartus_17.1/2018_5_9_Digital_Clock/Code/time_control.v Line: 1 150 | Info (12127): Elaborating entity "TOP" for the top level hierarchy 151 | Info (12128): Elaborating entity "time_control" for hierarchy "time_control:time_control_inst" File: E:/Workspace/Quartus_17.1/2018_5_9_Digital_Clock/Code/TOP.v Line: 71 152 | Warning (10036): Verilog HDL or VHDL warning at time_control.v(48): object "flag_1s" assigned a value but never read File: E:/Workspace/Quartus_17.1/2018_5_9_Digital_Clock/Code/time_control.v Line: 48 153 | Warning (10036): Verilog HDL or VHDL warning at time_control.v(186): object "flag_hour_shi" assigned a value but never read File: E:/Workspace/Quartus_17.1/2018_5_9_Digital_Clock/Code/time_control.v Line: 186 154 | Warning (10230): Verilog HDL assignment warning at time_control.v(42): truncated value with size 32 to match size of target (16) File: E:/Workspace/Quartus_17.1/2018_5_9_Digital_Clock/Code/time_control.v Line: 42 155 | Warning (10230): Verilog HDL assignment warning at time_control.v(60): truncated value with size 32 to match size of target (12) File: E:/Workspace/Quartus_17.1/2018_5_9_Digital_Clock/Code/time_control.v Line: 60 156 | Warning (10230): Verilog HDL assignment warning at time_control.v(93): truncated value with size 32 to match size of target (4) File: E:/Workspace/Quartus_17.1/2018_5_9_Digital_Clock/Code/time_control.v Line: 93 157 | Warning (10230): Verilog HDL assignment warning at time_control.v(108): truncated value with size 4 to match size of target (3) File: E:/Workspace/Quartus_17.1/2018_5_9_Digital_Clock/Code/time_control.v Line: 108 158 | Warning (10230): Verilog HDL assignment warning at time_control.v(117): truncated value with size 32 to match size of target (3) File: E:/Workspace/Quartus_17.1/2018_5_9_Digital_Clock/Code/time_control.v Line: 117 159 | Warning (10230): Verilog HDL assignment warning at time_control.v(148): truncated value with size 32 to match size of target (4) File: E:/Workspace/Quartus_17.1/2018_5_9_Digital_Clock/Code/time_control.v Line: 148 160 | Warning (10230): Verilog HDL assignment warning at time_control.v(163): truncated value with size 4 to match size of target (3) File: E:/Workspace/Quartus_17.1/2018_5_9_Digital_Clock/Code/time_control.v Line: 163 161 | Warning (10230): Verilog HDL assignment warning at time_control.v(172): truncated value with size 32 to match size of target (3) File: E:/Workspace/Quartus_17.1/2018_5_9_Digital_Clock/Code/time_control.v Line: 172 162 | Warning (10230): Verilog HDL assignment warning at time_control.v(207): truncated value with size 32 to match size of target (4) File: E:/Workspace/Quartus_17.1/2018_5_9_Digital_Clock/Code/time_control.v Line: 207 163 | Warning (10230): Verilog HDL assignment warning at time_control.v(222): truncated value with size 4 to match size of target (2) File: E:/Workspace/Quartus_17.1/2018_5_9_Digital_Clock/Code/time_control.v Line: 222 164 | Warning (10230): Verilog HDL assignment warning at time_control.v(231): truncated value with size 32 to match size of target (2) File: E:/Workspace/Quartus_17.1/2018_5_9_Digital_Clock/Code/time_control.v Line: 231 165 | Info (12128): Elaborating entity "display_ctrl" for hierarchy "display_ctrl:display_ctrl_inst" File: E:/Workspace/Quartus_17.1/2018_5_9_Digital_Clock/Code/TOP.v Line: 84 166 | Warning (10230): Verilog HDL assignment warning at display_ctrl.v(26): truncated value with size 32 to match size of target (11) File: E:/Workspace/Quartus_17.1/2018_5_9_Digital_Clock/Code/display_ctrl.v Line: 26 167 | Warning (10235): Verilog HDL Always Construct warning at display_ctrl.v(85): variable "data" is read inside the Always Construct but isn't in the Always Construct's Event Control File: E:/Workspace/Quartus_17.1/2018_5_9_Digital_Clock/Code/display_ctrl.v Line: 85 168 | Warning (10240): Verilog HDL Always Construct warning at display_ctrl.v(73): inferring latch(es) for variable "data", which holds its previous value in one or more paths through the always construct File: E:/Workspace/Quartus_17.1/2018_5_9_Digital_Clock/Code/display_ctrl.v Line: 73 169 | Info (10041): Inferred latch for "data[0]" at display_ctrl.v(73) File: E:/Workspace/Quartus_17.1/2018_5_9_Digital_Clock/Code/display_ctrl.v Line: 73 170 | Info (10041): Inferred latch for "data[1]" at display_ctrl.v(73) File: E:/Workspace/Quartus_17.1/2018_5_9_Digital_Clock/Code/display_ctrl.v Line: 73 171 | Info (10041): Inferred latch for "data[2]" at display_ctrl.v(73) File: E:/Workspace/Quartus_17.1/2018_5_9_Digital_Clock/Code/display_ctrl.v Line: 73 172 | Info (10041): Inferred latch for "data[3]" at display_ctrl.v(73) File: E:/Workspace/Quartus_17.1/2018_5_9_Digital_Clock/Code/display_ctrl.v Line: 73 173 | Info (10041): Inferred latch for "data[4]" at display_ctrl.v(73) File: E:/Workspace/Quartus_17.1/2018_5_9_Digital_Clock/Code/display_ctrl.v Line: 73 174 | Info (10041): Inferred latch for "data[5]" at display_ctrl.v(73) File: E:/Workspace/Quartus_17.1/2018_5_9_Digital_Clock/Code/display_ctrl.v Line: 73 175 | Info (10041): Inferred latch for "data[6]" at display_ctrl.v(73) File: E:/Workspace/Quartus_17.1/2018_5_9_Digital_Clock/Code/display_ctrl.v Line: 73 176 | Info (10041): Inferred latch for "data[7]" at display_ctrl.v(73) File: E:/Workspace/Quartus_17.1/2018_5_9_Digital_Clock/Code/display_ctrl.v Line: 73 177 | Info: Quartus Prime Analysis & Elaboration was successful. 0 errors, 17 warnings 178 | Info: Peak virtual memory: 4715 megabytes 179 | Info: Processing ended: Tue May 22 16:34:25 2018 180 | Info: Elapsed time: 00:00:21 181 | Info: Total CPU time (on all processors): 00:00:48 182 | 183 | 184 | -------------------------------------------------------------------------------- /output_files/Digital_Clock.map.summary: -------------------------------------------------------------------------------- 1 | Analysis & Elaboration Status : Successful - Tue May 22 16:34:25 2018 2 | Quartus Prime Version : 17.1.0 Build 590 10/25/2017 SJ Standard Edition 3 | Revision Name : Digital_Clock 4 | Top-level Entity Name : TOP 5 | Family : MAX II 6 | -------------------------------------------------------------------------------- /simulation/modelsim/Digital_Clock_run_msim_rtl_verilog.do: -------------------------------------------------------------------------------- 1 | transcript on 2 | if {[file exists rtl_work]} { 3 | vdel -lib rtl_work -all 4 | } 5 | vlib rtl_work 6 | vmap work rtl_work 7 | 8 | vlog -vlog01compat -work work +incdir+E:/Workspace/Quartus_17.1/2018_5_9_Digital_Clock/Code {E:/Workspace/Quartus_17.1/2018_5_9_Digital_Clock/Code/TOP.v} 9 | vlog -vlog01compat -work work +incdir+E:/Workspace/Quartus_17.1/2018_5_9_Digital_Clock/Code {E:/Workspace/Quartus_17.1/2018_5_9_Digital_Clock/Code/display_ctrl.v} 10 | vlog -vlog01compat -work work +incdir+E:/Workspace/Quartus_17.1/2018_5_9_Digital_Clock/Code {E:/Workspace/Quartus_17.1/2018_5_9_Digital_Clock/Code/time_control.v} 11 | 12 | vlog -vlog01compat -work work +incdir+E:/Workspace/Quartus_17.1/2018_5_9_Digital_Clock/TestBench {E:/Workspace/Quartus_17.1/2018_5_9_Digital_Clock/TestBench/tb_TOP.v} 13 | 14 | vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L maxii_ver -L rtl_work -L work -voptargs="+acc" tb_TOP 15 | 16 | add wave * 17 | view structure 18 | view signals 19 | run -all 20 | -------------------------------------------------------------------------------- /simulation/modelsim/Digital_Clock_run_msim_rtl_verilog.do.bak: -------------------------------------------------------------------------------- 1 | transcript on 2 | if {[file exists rtl_work]} { 3 | vdel -lib rtl_work -all 4 | } 5 | vlib rtl_work 6 | vmap work rtl_work 7 | 8 | vlog -vlog01compat -work work +incdir+E:/Workspace/Quartus_17.1/2018_5_9_Digital_Clock/Code {E:/Workspace/Quartus_17.1/2018_5_9_Digital_Clock/Code/time_control.v} 9 | 10 | vlog -vlog01compat -work work +incdir+E:/Workspace/Quartus_17.1/2018_5_9_Digital_Clock/TestBench {E:/Workspace/Quartus_17.1/2018_5_9_Digital_Clock/TestBench/tb_TOP.v} 11 | 12 | vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L maxii_ver -L rtl_work -L work -voptargs="+acc" tb_TOP 13 | 14 | add wave * 15 | view structure 16 | view signals 17 | run -all 18 | -------------------------------------------------------------------------------- /simulation/modelsim/Digital_Clock_run_msim_rtl_verilog.do.bak1: -------------------------------------------------------------------------------- 1 | transcript on 2 | if {[file exists rtl_work]} { 3 | vdel -lib rtl_work -all 4 | } 5 | vlib rtl_work 6 | vmap work rtl_work 7 | 8 | vlog -vlog01compat -work work +incdir+E:/Workspace/Quartus_17.1/2018_5_9_Digital_Clock/Code {E:/Workspace/Quartus_17.1/2018_5_9_Digital_Clock/Code/time_control.v} 9 | 10 | vlog -vlog01compat -work work +incdir+E:/Workspace/Quartus_17.1/2018_5_9_Digital_Clock/TestBench {E:/Workspace/Quartus_17.1/2018_5_9_Digital_Clock/TestBench/tb_TOP.v} 11 | 12 | vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L maxii_ver -L rtl_work -L work -voptargs="+acc" tb_TOP 13 | 14 | add wave * 15 | view structure 16 | view signals 17 | run -all 18 | -------------------------------------------------------------------------------- /simulation/modelsim/Digital_Clock_run_msim_rtl_verilog.do.bak10: -------------------------------------------------------------------------------- 1 | transcript on 2 | if {[file exists rtl_work]} { 3 | vdel -lib rtl_work -all 4 | } 5 | vlib rtl_work 6 | vmap work rtl_work 7 | 8 | vlog -vlog01compat -work work +incdir+E:/Workspace/Quartus_17.1/2018_5_9_Digital_Clock/Code {E:/Workspace/Quartus_17.1/2018_5_9_Digital_Clock/Code/time_control.v} 9 | 10 | vlog -vlog01compat -work work +incdir+E:/Workspace/Quartus_17.1/2018_5_9_Digital_Clock/TestBench {E:/Workspace/Quartus_17.1/2018_5_9_Digital_Clock/TestBench/tb_TOP.v} 11 | 12 | vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L maxii_ver -L rtl_work -L work -voptargs="+acc" tb_TOP 13 | 14 | add wave * 15 | view structure 16 | view signals 17 | run -all 18 | -------------------------------------------------------------------------------- /simulation/modelsim/Digital_Clock_run_msim_rtl_verilog.do.bak11: -------------------------------------------------------------------------------- 1 | transcript on 2 | if {[file exists rtl_work]} { 3 | vdel -lib rtl_work -all 4 | } 5 | vlib rtl_work 6 | vmap work rtl_work 7 | 8 | vlog -vlog01compat -work work +incdir+E:/Workspace/Quartus_17.1/2018_5_9_Digital_Clock/Code {E:/Workspace/Quartus_17.1/2018_5_9_Digital_Clock/Code/TOP.v} 9 | vlog -vlog01compat -work work +incdir+E:/Workspace/Quartus_17.1/2018_5_9_Digital_Clock/Code {E:/Workspace/Quartus_17.1/2018_5_9_Digital_Clock/Code/display_ctrl.v} 10 | vlog -vlog01compat -work work +incdir+E:/Workspace/Quartus_17.1/2018_5_9_Digital_Clock/Code {E:/Workspace/Quartus_17.1/2018_5_9_Digital_Clock/Code/time_control.v} 11 | 12 | vlog -vlog01compat -work work +incdir+E:/Workspace/Quartus_17.1/2018_5_9_Digital_Clock/TestBench {E:/Workspace/Quartus_17.1/2018_5_9_Digital_Clock/TestBench/tb_TOP.v} 13 | 14 | vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L maxii_ver -L rtl_work -L work -voptargs="+acc" tb_TOP 15 | 16 | add wave * 17 | view structure 18 | view signals 19 | run -all 20 | -------------------------------------------------------------------------------- /simulation/modelsim/Digital_Clock_run_msim_rtl_verilog.do.bak2: -------------------------------------------------------------------------------- 1 | transcript on 2 | if {[file exists rtl_work]} { 3 | vdel -lib rtl_work -all 4 | } 5 | vlib rtl_work 6 | vmap work rtl_work 7 | 8 | vlog -vlog01compat -work work +incdir+E:/Workspace/Quartus_17.1/2018_5_9_Digital_Clock/Code {E:/Workspace/Quartus_17.1/2018_5_9_Digital_Clock/Code/time_control.v} 9 | 10 | vlog -vlog01compat -work work +incdir+E:/Workspace/Quartus_17.1/2018_5_9_Digital_Clock/TestBench {E:/Workspace/Quartus_17.1/2018_5_9_Digital_Clock/TestBench/tb_TOP.v} 11 | 12 | vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L maxii_ver -L rtl_work -L work -voptargs="+acc" tb_TOP 13 | 14 | add wave * 15 | view structure 16 | view signals 17 | run -all 18 | -------------------------------------------------------------------------------- /simulation/modelsim/Digital_Clock_run_msim_rtl_verilog.do.bak3: -------------------------------------------------------------------------------- 1 | transcript on 2 | if {[file exists rtl_work]} { 3 | vdel -lib rtl_work -all 4 | } 5 | vlib rtl_work 6 | vmap work rtl_work 7 | 8 | vlog -vlog01compat -work work +incdir+E:/Workspace/Quartus_17.1/2018_5_9_Digital_Clock/Code {E:/Workspace/Quartus_17.1/2018_5_9_Digital_Clock/Code/time_control.v} 9 | 10 | vlog -vlog01compat -work work +incdir+E:/Workspace/Quartus_17.1/2018_5_9_Digital_Clock/TestBench {E:/Workspace/Quartus_17.1/2018_5_9_Digital_Clock/TestBench/tb_TOP.v} 11 | 12 | vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L maxii_ver -L rtl_work -L work -voptargs="+acc" tb_TOP 13 | 14 | add wave * 15 | view structure 16 | view signals 17 | run -all 18 | -------------------------------------------------------------------------------- /simulation/modelsim/Digital_Clock_run_msim_rtl_verilog.do.bak4: -------------------------------------------------------------------------------- 1 | transcript on 2 | if {[file exists rtl_work]} { 3 | vdel -lib rtl_work -all 4 | } 5 | vlib rtl_work 6 | vmap work rtl_work 7 | 8 | vlog -vlog01compat -work work +incdir+E:/Workspace/Quartus_17.1/2018_5_9_Digital_Clock/Code {E:/Workspace/Quartus_17.1/2018_5_9_Digital_Clock/Code/time_control.v} 9 | 10 | vlog -vlog01compat -work work +incdir+E:/Workspace/Quartus_17.1/2018_5_9_Digital_Clock/TestBench {E:/Workspace/Quartus_17.1/2018_5_9_Digital_Clock/TestBench/tb_TOP.v} 11 | 12 | vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L maxii_ver -L rtl_work -L work -voptargs="+acc" tb_TOP 13 | 14 | add wave * 15 | view structure 16 | view signals 17 | run -all 18 | -------------------------------------------------------------------------------- /simulation/modelsim/Digital_Clock_run_msim_rtl_verilog.do.bak5: -------------------------------------------------------------------------------- 1 | transcript on 2 | if {[file exists rtl_work]} { 3 | vdel -lib rtl_work -all 4 | } 5 | vlib rtl_work 6 | vmap work rtl_work 7 | 8 | vlog -vlog01compat -work work +incdir+E:/Workspace/Quartus_17.1/2018_5_9_Digital_Clock/Code {E:/Workspace/Quartus_17.1/2018_5_9_Digital_Clock/Code/time_control.v} 9 | 10 | vlog -vlog01compat -work work +incdir+E:/Workspace/Quartus_17.1/2018_5_9_Digital_Clock/TestBench {E:/Workspace/Quartus_17.1/2018_5_9_Digital_Clock/TestBench/tb_TOP.v} 11 | 12 | vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L maxii_ver -L rtl_work -L work -voptargs="+acc" tb_TOP 13 | 14 | add wave * 15 | view structure 16 | view signals 17 | run -all 18 | -------------------------------------------------------------------------------- /simulation/modelsim/Digital_Clock_run_msim_rtl_verilog.do.bak6: -------------------------------------------------------------------------------- 1 | transcript on 2 | if {[file exists rtl_work]} { 3 | vdel -lib rtl_work -all 4 | } 5 | vlib rtl_work 6 | vmap work rtl_work 7 | 8 | vlog -vlog01compat -work work +incdir+E:/Workspace/Quartus_17.1/2018_5_9_Digital_Clock/Code {E:/Workspace/Quartus_17.1/2018_5_9_Digital_Clock/Code/time_control.v} 9 | 10 | vlog -vlog01compat -work work +incdir+E:/Workspace/Quartus_17.1/2018_5_9_Digital_Clock/TestBench {E:/Workspace/Quartus_17.1/2018_5_9_Digital_Clock/TestBench/tb_TOP.v} 11 | 12 | vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L maxii_ver -L rtl_work -L work -voptargs="+acc" tb_TOP 13 | 14 | add wave * 15 | view structure 16 | view signals 17 | run -all 18 | -------------------------------------------------------------------------------- /simulation/modelsim/Digital_Clock_run_msim_rtl_verilog.do.bak7: -------------------------------------------------------------------------------- 1 | transcript on 2 | if {[file exists rtl_work]} { 3 | vdel -lib rtl_work -all 4 | } 5 | vlib rtl_work 6 | vmap work rtl_work 7 | 8 | vlog -vlog01compat -work work +incdir+E:/Workspace/Quartus_17.1/2018_5_9_Digital_Clock/Code {E:/Workspace/Quartus_17.1/2018_5_9_Digital_Clock/Code/time_control.v} 9 | 10 | vlog -vlog01compat -work work +incdir+E:/Workspace/Quartus_17.1/2018_5_9_Digital_Clock/TestBench {E:/Workspace/Quartus_17.1/2018_5_9_Digital_Clock/TestBench/tb_TOP.v} 11 | 12 | vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L maxii_ver -L rtl_work -L work -voptargs="+acc" tb_TOP 13 | 14 | add wave * 15 | view structure 16 | view signals 17 | run -all 18 | -------------------------------------------------------------------------------- /simulation/modelsim/Digital_Clock_run_msim_rtl_verilog.do.bak8: -------------------------------------------------------------------------------- 1 | transcript on 2 | if {[file exists rtl_work]} { 3 | vdel -lib rtl_work -all 4 | } 5 | vlib rtl_work 6 | vmap work rtl_work 7 | 8 | vlog -vlog01compat -work work +incdir+E:/Workspace/Quartus_17.1/2018_5_9_Digital_Clock/Code {E:/Workspace/Quartus_17.1/2018_5_9_Digital_Clock/Code/time_control.v} 9 | 10 | vlog -vlog01compat -work work +incdir+E:/Workspace/Quartus_17.1/2018_5_9_Digital_Clock/TestBench {E:/Workspace/Quartus_17.1/2018_5_9_Digital_Clock/TestBench/tb_TOP.v} 11 | 12 | vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L maxii_ver -L rtl_work -L work -voptargs="+acc" tb_TOP 13 | 14 | add wave * 15 | view structure 16 | view signals 17 | run -all 18 | -------------------------------------------------------------------------------- /simulation/modelsim/Digital_Clock_run_msim_rtl_verilog.do.bak9: -------------------------------------------------------------------------------- 1 | transcript on 2 | if {[file exists rtl_work]} { 3 | vdel -lib rtl_work -all 4 | } 5 | vlib rtl_work 6 | vmap work rtl_work 7 | 8 | vlog -vlog01compat -work work +incdir+E:/Workspace/Quartus_17.1/2018_5_9_Digital_Clock/Code {E:/Workspace/Quartus_17.1/2018_5_9_Digital_Clock/Code/time_control.v} 9 | 10 | vlog -vlog01compat -work work +incdir+E:/Workspace/Quartus_17.1/2018_5_9_Digital_Clock/TestBench {E:/Workspace/Quartus_17.1/2018_5_9_Digital_Clock/TestBench/tb_TOP.v} 11 | 12 | vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L maxii_ver -L rtl_work -L work -voptargs="+acc" tb_TOP 13 | 14 | add wave * 15 | view structure 16 | view signals 17 | run -all 18 | -------------------------------------------------------------------------------- /simulation/modelsim/modelsim.ini: -------------------------------------------------------------------------------- 1 | ; Copyright 1991-2009 Mentor Graphics Corporation 2 | ; 3 | ; All Rights Reserved. 4 | ; 5 | ; THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF 6 | ; MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS. 7 | ; 8 | 9 | [Library] 10 | others = $MODEL_TECH/../modelsim.ini 11 | 12 | ; Altera Primitive libraries 13 | ; 14 | ; VHDL Section 15 | ; 16 | ; 17 | ; Verilog Section 18 | ; 19 | 20 | work = rtl_work 21 | [vcom] 22 | ; VHDL93 variable selects language version as the default. 23 | ; Default is VHDL-2002. 24 | ; Value of 0 or 1987 for VHDL-1987. 25 | ; Value of 1 or 1993 for VHDL-1993. 26 | ; Default or value of 2 or 2002 for VHDL-2002. 27 | ; Default or value of 3 or 2008 for VHDL-2008. 28 | VHDL93 = 2002 29 | 30 | ; Show source line containing error. Default is off. 31 | ; Show_source = 1 32 | 33 | ; Turn off unbound-component warnings. Default is on. 34 | ; Show_Warning1 = 0 35 | 36 | ; Turn off process-without-a-wait-statement warnings. Default is on. 37 | ; Show_Warning2 = 0 38 | 39 | ; Turn off null-range warnings. Default is on. 40 | ; Show_Warning3 = 0 41 | 42 | ; Turn off no-space-in-time-literal warnings. Default is on. 43 | ; Show_Warning4 = 0 44 | 45 | ; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on. 46 | ; Show_Warning5 = 0 47 | 48 | ; Turn off optimization for IEEE std_logic_1164 package. Default is on. 49 | ; Optimize_1164 = 0 50 | 51 | ; Turn on resolving of ambiguous function overloading in favor of the 52 | ; "explicit" function declaration (not the one automatically created by 53 | ; the compiler for each type declaration). Default is off. 54 | ; The .ini file has Explicit enabled so that std_logic_signed/unsigned 55 | ; will match the behavior of synthesis tools. 56 | Explicit = 1 57 | 58 | ; Turn off acceleration of the VITAL packages. Default is to accelerate. 59 | ; NoVital = 1 60 | 61 | ; Turn off VITAL compliance checking. Default is checking on. 62 | ; NoVitalCheck = 1 63 | 64 | ; Ignore VITAL compliance checking errors. Default is to not ignore. 65 | ; IgnoreVitalErrors = 1 66 | 67 | ; Turn off VITAL compliance checking warnings. Default is to show warnings. 68 | ; Show_VitalChecksWarnings = 0 69 | 70 | ; Keep silent about case statement static warnings. 71 | ; Default is to give a warning. 72 | ; NoCaseStaticError = 1 73 | 74 | ; Keep silent about warnings caused by aggregates that are not locally static. 75 | ; Default is to give a warning. 76 | ; NoOthersStaticError = 1 77 | 78 | ; Turn off inclusion of debugging info within design units. 79 | ; Default is to include debugging info. 80 | ; NoDebug = 1 81 | 82 | ; Turn off "Loading..." messages. Default is messages on. 83 | ; Quiet = 1 84 | 85 | ; Turn on some limited synthesis rule compliance checking. Checks only: 86 | ; -- signals used (read) by a process must be in the sensitivity list 87 | ; CheckSynthesis = 1 88 | 89 | ; Activate optimizations on expressions that do not involve signals, 90 | ; waits, or function/procedure/task invocations. Default is off. 91 | ; ScalarOpts = 1 92 | 93 | ; Require the user to specify a configuration for all bindings, 94 | ; and do not generate a compile time default binding for the 95 | ; component. This will result in an elaboration error of 96 | ; 'component not bound' if the user fails to do so. Avoids the rare 97 | ; issue of a false dependency upon the unused default binding. 98 | ; RequireConfigForAllDefaultBinding = 1 99 | 100 | ; Inhibit range checking on subscripts of arrays. Range checking on 101 | ; scalars defined with subtypes is inhibited by default. 102 | ; NoIndexCheck = 1 103 | 104 | ; Inhibit range checks on all (implicit and explicit) assignments to 105 | ; scalar objects defined with subtypes. 106 | ; NoRangeCheck = 1 107 | 108 | [vlog] 109 | 110 | ; Turn off inclusion of debugging info within design units. 111 | ; Default is to include debugging info. 112 | ; NoDebug = 1 113 | 114 | ; Turn off "loading..." messages. Default is messages on. 115 | ; Quiet = 1 116 | 117 | ; Turn on Verilog hazard checking (order-dependent accessing of global vars). 118 | ; Default is off. 119 | ; Hazard = 1 120 | 121 | ; Turn on converting regular Verilog identifiers to uppercase. Allows case 122 | ; insensitivity for module names. Default is no conversion. 123 | ; UpCase = 1 124 | 125 | ; Turn on incremental compilation of modules. Default is off. 126 | ; Incremental = 1 127 | 128 | ; Turns on lint-style checking. 129 | ; Show_Lint = 1 130 | 131 | [vsim] 132 | ; Simulator resolution 133 | ; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100. 134 | Resolution = ps 135 | 136 | ; User time unit for run commands 137 | ; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the 138 | ; unit specified for Resolution. For example, if Resolution is 100ps, 139 | ; then UserTimeUnit defaults to ps. 140 | ; Should generally be set to default. 141 | UserTimeUnit = default 142 | 143 | ; Default run length 144 | RunLength = 100 145 | 146 | ; Maximum iterations that can be run without advancing simulation time 147 | IterationLimit = 5000 148 | 149 | ; Directive to license manager: 150 | ; vhdl Immediately reserve a VHDL license 151 | ; vlog Immediately reserve a Verilog license 152 | ; plus Immediately reserve a VHDL and Verilog license 153 | ; nomgc Do not look for Mentor Graphics Licenses 154 | ; nomti Do not look for Model Technology Licenses 155 | ; noqueue Do not wait in the license queue when a license isn't available 156 | ; viewsim Try for viewer license but accept simulator license(s) instead 157 | ; of queuing for viewer license 158 | ; License = plus 159 | 160 | ; Stop the simulator after a VHDL/Verilog assertion message 161 | ; 0 = Note 1 = Warning 2 = Error 3 = Failure 4 = Fatal 162 | BreakOnAssertion = 3 163 | 164 | ; Assertion Message Format 165 | ; %S - Severity Level 166 | ; %R - Report Message 167 | ; %T - Time of assertion 168 | ; %D - Delta 169 | ; %I - Instance or Region pathname (if available) 170 | ; %% - print '%' character 171 | ; AssertionFormat = "** %S: %R\n Time: %T Iteration: %D%I\n" 172 | 173 | ; Assertion File - alternate file for storing VHDL/Verilog assertion messages 174 | ; AssertFile = assert.log 175 | 176 | ; Default radix for all windows and commands... 177 | ; Set to symbolic, ascii, binary, octal, decimal, hex, unsigned 178 | DefaultRadix = symbolic 179 | 180 | ; VSIM Startup command 181 | ; Startup = do startup.do 182 | 183 | ; File for saving command transcript 184 | TranscriptFile = transcript 185 | 186 | ; File for saving command history 187 | ; CommandHistory = cmdhist.log 188 | 189 | ; Specify whether paths in simulator commands should be described 190 | ; in VHDL or Verilog format. 191 | ; For VHDL, PathSeparator = / 192 | ; For Verilog, PathSeparator = . 193 | ; Must not be the same character as DatasetSeparator. 194 | PathSeparator = / 195 | 196 | ; Specify the dataset separator for fully rooted contexts. 197 | ; The default is ':'. For example, sim:/top 198 | ; Must not be the same character as PathSeparator. 199 | DatasetSeparator = : 200 | 201 | ; Disable VHDL assertion messages 202 | ; IgnoreNote = 1 203 | ; IgnoreWarning = 1 204 | ; IgnoreError = 1 205 | ; IgnoreFailure = 1 206 | 207 | ; Default force kind. May be freeze, drive, deposit, or default 208 | ; or in other terms, fixed, wired, or charged. 209 | ; A value of "default" will use the signal kind to determine the 210 | ; force kind, drive for resolved signals, freeze for unresolved signals 211 | ; DefaultForceKind = freeze 212 | 213 | ; If zero, open files when elaborated; otherwise, open files on 214 | ; first read or write. Default is 0. 215 | ; DelayFileOpen = 1 216 | 217 | ; Control VHDL files opened for write. 218 | ; 0 = Buffered, 1 = Unbuffered 219 | UnbufferedOutput = 0 220 | 221 | ; Control the number of VHDL files open concurrently. 222 | ; This number should always be less than the current ulimit 223 | ; setting for max file descriptors. 224 | ; 0 = unlimited 225 | ConcurrentFileLimit = 40 226 | 227 | ; Control the number of hierarchical regions displayed as 228 | ; part of a signal name shown in the Wave window. 229 | ; A value of zero tells VSIM to display the full name. 230 | ; The default is 0. 231 | ; WaveSignalNameWidth = 0 232 | 233 | ; Turn off warnings from the std_logic_arith, std_logic_unsigned 234 | ; and std_logic_signed packages. 235 | ; StdArithNoWarnings = 1 236 | 237 | ; Turn off warnings from the IEEE numeric_std and numeric_bit packages. 238 | ; NumericStdNoWarnings = 1 239 | 240 | ; Control the format of the (VHDL) FOR generate statement label 241 | ; for each iteration. Do not quote it. 242 | ; The format string here must contain the conversion codes %s and %d, 243 | ; in that order, and no other conversion codes. The %s represents 244 | ; the generate_label; the %d represents the generate parameter value 245 | ; at a particular generate iteration (this is the position number if 246 | ; the generate parameter is of an enumeration type). Embedded whitespace 247 | ; is allowed (but discouraged); leading and trailing whitespace is ignored. 248 | ; Application of the format must result in a unique scope name over all 249 | ; such names in the design so that name lookup can function properly. 250 | ; GenerateFormat = %s__%d 251 | 252 | ; Specify whether checkpoint files should be compressed. 253 | ; The default is 1 (compressed). 254 | ; CheckpointCompressMode = 0 255 | 256 | ; List of dynamically loaded objects for Verilog PLI applications 257 | ; Veriuser = veriuser.sl 258 | 259 | ; Specify default options for the restart command. Options can be one 260 | ; or more of: -force -nobreakpoint -nolist -nolog -nowave 261 | ; DefaultRestartOptions = -force 262 | 263 | ; HP-UX 10.20 ONLY - Enable memory locking to speed up large designs 264 | ; (> 500 megabyte memory footprint). Default is disabled. 265 | ; Specify number of megabytes to lock. 266 | ; LockedMemory = 1000 267 | 268 | ; Turn on (1) or off (0) WLF file compression. 269 | ; The default is 1 (compress WLF file). 270 | ; WLFCompress = 0 271 | 272 | ; Specify whether to save all design hierarchy (1) in the WLF file 273 | ; or only regions containing logged signals (0). 274 | ; The default is 0 (save only regions with logged signals). 275 | ; WLFSaveAllRegions = 1 276 | 277 | ; WLF file time limit. Limit WLF file by time, as closely as possible, 278 | ; to the specified amount of simulation time. When the limit is exceeded 279 | ; the earliest times get truncated from the file. 280 | ; If both time and size limits are specified the most restrictive is used. 281 | ; UserTimeUnits are used if time units are not specified. 282 | ; The default is 0 (no limit). Example: WLFTimeLimit = {100 ms} 283 | ; WLFTimeLimit = 0 284 | 285 | ; WLF file size limit. Limit WLF file size, as closely as possible, 286 | ; to the specified number of megabytes. If both time and size limits 287 | ; are specified then the most restrictive is used. 288 | ; The default is 0 (no limit). 289 | ; WLFSizeLimit = 1000 290 | 291 | ; Specify whether or not a WLF file should be deleted when the 292 | ; simulation ends. A value of 1 will cause the WLF file to be deleted. 293 | ; The default is 0 (do not delete WLF file when simulation ends). 294 | ; WLFDeleteOnQuit = 1 295 | 296 | ; Automatic SDF compilation 297 | ; Disables automatic compilation of SDF files in flows that support it. 298 | ; Default is on, uncomment to turn off. 299 | ; NoAutoSDFCompile = 1 300 | 301 | [lmc] 302 | 303 | [msg_system] 304 | ; Change a message severity or suppress a message. 305 | ; The format is: = [,...] 306 | ; Examples: 307 | ; note = 3009 308 | ; warning = 3033 309 | ; error = 3010,3016 310 | ; fatal = 3016,3033 311 | ; suppress = 3009,3016,3043 312 | ; The command verror can be used to get the complete 313 | ; description of a message. 314 | 315 | ; Control transcripting of elaboration/runtime messages. 316 | ; The default is to have messages appear in the transcript and 317 | ; recorded in the wlf file (messages that are recorded in the 318 | ; wlf file can be viewed in the MsgViewer). The other settings 319 | ; are to send messages only to the transcript or only to the 320 | ; wlf file. The valid values are 321 | ; both {default} 322 | ; tran {transcript only} 323 | ; wlf {wlf file only} 324 | ; msgmode = both 325 | -------------------------------------------------------------------------------- /simulation/modelsim/msim_transcript: -------------------------------------------------------------------------------- 1 | # Reading E:/Softwares/Quartus_17.1/modelsim_ase/tcl/vsim/pref.tcl 2 | # do Digital_Clock_run_msim_rtl_verilog.do 3 | # if {[file exists rtl_work]} { 4 | # vdel -lib rtl_work -all 5 | # } 6 | # vlib rtl_work 7 | # vmap work rtl_work 8 | # Model Technology ModelSim - Intel FPGA Edition vmap 10.5b Lib Mapping Utility 2016.10 Oct 5 2016 9 | # vmap work rtl_work 10 | # Copying E:/Softwares/Quartus_17.1/modelsim_ase/win32aloem/../modelsim.ini to modelsim.ini 11 | # Modifying modelsim.ini 12 | # 13 | # vlog -vlog01compat -work work +incdir+E:/Workspace/Quartus_17.1/2018_5_9_Digital_Clock/Code {E:/Workspace/Quartus_17.1/2018_5_9_Digital_Clock/Code/TOP.v} 14 | # Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 15 | # Start time: 17:15:35 on May 22,2018 16 | # vlog -reportprogress 300 -vlog01compat -work work "+incdir+E:/Workspace/Quartus_17.1/2018_5_9_Digital_Clock/Code" E:/Workspace/Quartus_17.1/2018_5_9_Digital_Clock/Code/TOP.v 17 | # -- Compiling module TOP 18 | # 19 | # Top level modules: 20 | # TOP 21 | # End time: 17:15:35 on May 22,2018, Elapsed time: 0:00:00 22 | # Errors: 0, Warnings: 0 23 | # vlog -vlog01compat -work work +incdir+E:/Workspace/Quartus_17.1/2018_5_9_Digital_Clock/Code {E:/Workspace/Quartus_17.1/2018_5_9_Digital_Clock/Code/display_ctrl.v} 24 | # Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 25 | # Start time: 17:15:35 on May 22,2018 26 | # vlog -reportprogress 300 -vlog01compat -work work "+incdir+E:/Workspace/Quartus_17.1/2018_5_9_Digital_Clock/Code" E:/Workspace/Quartus_17.1/2018_5_9_Digital_Clock/Code/display_ctrl.v 27 | # -- Compiling module display_ctrl 28 | # 29 | # Top level modules: 30 | # display_ctrl 31 | # End time: 17:15:35 on May 22,2018, Elapsed time: 0:00:00 32 | # Errors: 0, Warnings: 0 33 | # vlog -vlog01compat -work work +incdir+E:/Workspace/Quartus_17.1/2018_5_9_Digital_Clock/Code {E:/Workspace/Quartus_17.1/2018_5_9_Digital_Clock/Code/time_control.v} 34 | # Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 35 | # Start time: 17:15:36 on May 22,2018 36 | # vlog -reportprogress 300 -vlog01compat -work work "+incdir+E:/Workspace/Quartus_17.1/2018_5_9_Digital_Clock/Code" E:/Workspace/Quartus_17.1/2018_5_9_Digital_Clock/Code/time_control.v 37 | # -- Compiling module time_control 38 | # 39 | # Top level modules: 40 | # time_control 41 | # End time: 17:15:36 on May 22,2018, Elapsed time: 0:00:00 42 | # Errors: 0, Warnings: 0 43 | # 44 | # vlog -vlog01compat -work work +incdir+E:/Workspace/Quartus_17.1/2018_5_9_Digital_Clock/TestBench {E:/Workspace/Quartus_17.1/2018_5_9_Digital_Clock/TestBench/tb_TOP.v} 45 | # Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 46 | # Start time: 17:15:36 on May 22,2018 47 | # vlog -reportprogress 300 -vlog01compat -work work "+incdir+E:/Workspace/Quartus_17.1/2018_5_9_Digital_Clock/TestBench" E:/Workspace/Quartus_17.1/2018_5_9_Digital_Clock/TestBench/tb_TOP.v 48 | # -- Compiling module tb_TOP 49 | # 50 | # Top level modules: 51 | # tb_TOP 52 | # End time: 17:15:36 on May 22,2018, Elapsed time: 0:00:00 53 | # Errors: 0, Warnings: 0 54 | # 55 | # vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L maxii_ver -L rtl_work -L work -voptargs="+acc" tb_TOP 56 | # vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L maxii_ver -L rtl_work -L work -voptargs=""+acc"" tb_TOP 57 | # Start time: 17:15:36 on May 22,2018 58 | # Loading work.tb_TOP 59 | # Loading work.TOP 60 | # Loading work.time_control 61 | # Loading work.display_ctrl 62 | # ** Warning: (vsim-3015) E:/Workspace/Quartus_17.1/2018_5_9_Digital_Clock/TestBench/tb_TOP.v(43): [PCDPC] - Port size (4) does not match connection size (3) for port 'set_sec_shi'. The port definition is at: E:/Workspace/Quartus_17.1/2018_5_9_Digital_Clock/Code/TOP.v(7). 63 | # Time: 0 ps Iteration: 0 Instance: /tb_TOP/TOP_inst File: E:/Workspace/Quartus_17.1/2018_5_9_Digital_Clock/Code/TOP.v 64 | # ** Warning: (vsim-3015) E:/Workspace/Quartus_17.1/2018_5_9_Digital_Clock/TestBench/tb_TOP.v(43): [PCDPC] - Port size (4) does not match connection size (3) for port 'set_min_shi'. The port definition is at: E:/Workspace/Quartus_17.1/2018_5_9_Digital_Clock/Code/TOP.v(9). 65 | # Time: 0 ps Iteration: 0 Instance: /tb_TOP/TOP_inst File: E:/Workspace/Quartus_17.1/2018_5_9_Digital_Clock/Code/TOP.v 66 | # ** Warning: (vsim-3015) E:/Workspace/Quartus_17.1/2018_5_9_Digital_Clock/TestBench/tb_TOP.v(43): [PCDPC] - Port size (4) does not match connection size (2) for port 'set_hour_shi'. The port definition is at: E:/Workspace/Quartus_17.1/2018_5_9_Digital_Clock/Code/TOP.v(11). 67 | # Time: 0 ps Iteration: 0 Instance: /tb_TOP/TOP_inst File: E:/Workspace/Quartus_17.1/2018_5_9_Digital_Clock/Code/TOP.v 68 | # ** Warning: (vsim-3015) E:/Workspace/Quartus_17.1/2018_5_9_Digital_Clock/TestBench/tb_TOP.v(43): [PCDPC] - Port size (4) does not match connection size (3) for port 'clock_min_shi'. The port definition is at: E:/Workspace/Quartus_17.1/2018_5_9_Digital_Clock/Code/TOP.v(15). 69 | # Time: 0 ps Iteration: 0 Instance: /tb_TOP/TOP_inst File: E:/Workspace/Quartus_17.1/2018_5_9_Digital_Clock/Code/TOP.v 70 | # ** Warning: (vsim-3015) E:/Workspace/Quartus_17.1/2018_5_9_Digital_Clock/TestBench/tb_TOP.v(43): [PCDPC] - Port size (4) does not match connection size (2) for port 'clock_hour_shi'. The port definition is at: E:/Workspace/Quartus_17.1/2018_5_9_Digital_Clock/Code/TOP.v(17). 71 | # Time: 0 ps Iteration: 0 Instance: /tb_TOP/TOP_inst File: E:/Workspace/Quartus_17.1/2018_5_9_Digital_Clock/Code/TOP.v 72 | # ** Warning: (vsim-3015) E:/Workspace/Quartus_17.1/2018_5_9_Digital_Clock/TestBench/tb_TOP.v(43): [PCDPC] - Port size (4) does not match connection size (3) for port 'sec_shi_r'. The port definition is at: E:/Workspace/Quartus_17.1/2018_5_9_Digital_Clock/Code/TOP.v(21). 73 | # Time: 0 ps Iteration: 0 Instance: /tb_TOP/TOP_inst File: E:/Workspace/Quartus_17.1/2018_5_9_Digital_Clock/Code/TOP.v 74 | # ** Warning: (vsim-3015) E:/Workspace/Quartus_17.1/2018_5_9_Digital_Clock/TestBench/tb_TOP.v(43): [PCDPC] - Port size (4) does not match connection size (3) for port 'min_shi_r'. The port definition is at: E:/Workspace/Quartus_17.1/2018_5_9_Digital_Clock/Code/TOP.v(23). 75 | # Time: 0 ps Iteration: 0 Instance: /tb_TOP/TOP_inst File: E:/Workspace/Quartus_17.1/2018_5_9_Digital_Clock/Code/TOP.v 76 | # ** Warning: (vsim-3015) E:/Workspace/Quartus_17.1/2018_5_9_Digital_Clock/TestBench/tb_TOP.v(43): [PCDPC] - Port size (4) does not match connection size (2) for port 'hour_shi_r'. The port definition is at: E:/Workspace/Quartus_17.1/2018_5_9_Digital_Clock/Code/TOP.v(25). 77 | # Time: 0 ps Iteration: 0 Instance: /tb_TOP/TOP_inst File: E:/Workspace/Quartus_17.1/2018_5_9_Digital_Clock/Code/TOP.v 78 | # 79 | # add wave * 80 | # view structure 81 | # .main_pane.structure.interior.cs.body.struct 82 | # view signals 83 | # .main_pane.objects.interior.cs.body.tree 84 | # run -all 85 | # End time: 17:19:26 on May 22,2018, Elapsed time: 0:03:50 86 | # Errors: 0, Warnings: 8 87 | -------------------------------------------------------------------------------- /simulation/modelsim/rtl_work/_info: -------------------------------------------------------------------------------- 1 | m255 2 | K4 3 | z2 4 | 13 5 | !s112 1.1 6 | !i10d 8192 7 | !i10e 25 8 | !i10f 100 9 | cModel Technology 10 | Z0 dE:/Workspace/Quartus_17.1/2018_5_9_Digital_Clock/simulation/modelsim 11 | vdisplay_ctrl 12 | Z1 !s110 1526980535 13 | !i10b 1 14 | !s100 @WE[X7bO7WOWJ0C4LS73i0 15 | I[5haK08<8H^NEO34me9I<2 16 | Z2 VDg1SIo80bB@j0V0VzS_@n1 17 | R0 18 | w1526521865 19 | 8E:/Workspace/Quartus_17.1/2018_5_9_Digital_Clock/Code/display_ctrl.v 20 | FE:/Workspace/Quartus_17.1/2018_5_9_Digital_Clock/Code/display_ctrl.v 21 | L0 1 22 | Z3 OV;L;10.5b;63 23 | r1 24 | !s85 0 25 | 31 26 | Z4 !s108 1526980535.000000 27 | !s107 E:/Workspace/Quartus_17.1/2018_5_9_Digital_Clock/Code/display_ctrl.v| 28 | !s90 -reportprogress|300|-vlog01compat|-work|work|+incdir+E:/Workspace/Quartus_17.1/2018_5_9_Digital_Clock/Code|E:/Workspace/Quartus_17.1/2018_5_9_Digital_Clock/Code/display_ctrl.v| 29 | !i113 1 30 | Z5 o-vlog01compat -work work 31 | Z6 !s92 -vlog01compat -work work +incdir+E:/Workspace/Quartus_17.1/2018_5_9_Digital_Clock/Code 32 | Z7 tCvgOpt 0 33 | vtb_TOP 34 | Z8 !s110 1526980536 35 | !i10b 1 36 | !s100 QMM78eHzTlg0EboQY90Gf0 37 | IC7O2Z3B;fB;Fg52CamdY60 38 | R2 39 | R0 40 | w1526520175 41 | 8E:/Workspace/Quartus_17.1/2018_5_9_Digital_Clock/TestBench/tb_TOP.v 42 | FE:/Workspace/Quartus_17.1/2018_5_9_Digital_Clock/TestBench/tb_TOP.v 43 | L0 3 44 | R3 45 | r1 46 | !s85 0 47 | 31 48 | Z9 !s108 1526980536.000000 49 | !s107 E:/Workspace/Quartus_17.1/2018_5_9_Digital_Clock/TestBench/tb_TOP.v| 50 | !s90 -reportprogress|300|-vlog01compat|-work|work|+incdir+E:/Workspace/Quartus_17.1/2018_5_9_Digital_Clock/TestBench|E:/Workspace/Quartus_17.1/2018_5_9_Digital_Clock/TestBench/tb_TOP.v| 51 | !i113 1 52 | R5 53 | !s92 -vlog01compat -work work +incdir+E:/Workspace/Quartus_17.1/2018_5_9_Digital_Clock/TestBench 54 | R7 55 | ntb_@t@o@p 56 | vtime_control 57 | R8 58 | !i10b 1 59 | !s100 [>RRQfBIl0@e`Jl7oUj`g2 60 | IZD3eBgYSTnlaUTGMa8T@X1 61 | R2 62 | R0 63 | w1526519258 64 | 8E:/Workspace/Quartus_17.1/2018_5_9_Digital_Clock/Code/time_control.v 65 | FE:/Workspace/Quartus_17.1/2018_5_9_Digital_Clock/Code/time_control.v 66 | L0 1 67 | R3 68 | r1 69 | !s85 0 70 | 31 71 | R9 72 | !s107 E:/Workspace/Quartus_17.1/2018_5_9_Digital_Clock/Code/time_control.v| 73 | !s90 -reportprogress|300|-vlog01compat|-work|work|+incdir+E:/Workspace/Quartus_17.1/2018_5_9_Digital_Clock/Code|E:/Workspace/Quartus_17.1/2018_5_9_Digital_Clock/Code/time_control.v| 74 | !i113 1 75 | R5 76 | R6 77 | R7 78 | vTOP 79 | R1 80 | !i10b 1 81 | !s100 T^^d4kgF_?>;G?102kjAS2 82 | IGGoOnE=TP:RmDSVSg7^Wf3 83 | R2 84 | R0 85 | w1526520657 86 | 8E:/Workspace/Quartus_17.1/2018_5_9_Digital_Clock/Code/TOP.v 87 | FE:/Workspace/Quartus_17.1/2018_5_9_Digital_Clock/Code/TOP.v 88 | L0 1 89 | R3 90 | r1 91 | !s85 0 92 | 31 93 | R4 94 | !s107 E:/Workspace/Quartus_17.1/2018_5_9_Digital_Clock/Code/TOP.v| 95 | !s90 -reportprogress|300|-vlog01compat|-work|work|+incdir+E:/Workspace/Quartus_17.1/2018_5_9_Digital_Clock/Code|E:/Workspace/Quartus_17.1/2018_5_9_Digital_Clock/Code/TOP.v| 96 | !i113 1 97 | R5 98 | R6 99 | R7 100 | n@t@o@p 101 | -------------------------------------------------------------------------------- /simulation/modelsim/rtl_work/_lib.qdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/DOOKNET/Digital_Clock/c56f1dbf5b4fb8fe69f5c27d19749ed98fe408a7/simulation/modelsim/rtl_work/_lib.qdb -------------------------------------------------------------------------------- /simulation/modelsim/rtl_work/_lib1_0.qdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/DOOKNET/Digital_Clock/c56f1dbf5b4fb8fe69f5c27d19749ed98fe408a7/simulation/modelsim/rtl_work/_lib1_0.qdb -------------------------------------------------------------------------------- /simulation/modelsim/rtl_work/_lib1_0.qpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/DOOKNET/Digital_Clock/c56f1dbf5b4fb8fe69f5c27d19749ed98fe408a7/simulation/modelsim/rtl_work/_lib1_0.qpg -------------------------------------------------------------------------------- /simulation/modelsim/rtl_work/_lib1_0.qtl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/DOOKNET/Digital_Clock/c56f1dbf5b4fb8fe69f5c27d19749ed98fe408a7/simulation/modelsim/rtl_work/_lib1_0.qtl -------------------------------------------------------------------------------- /simulation/modelsim/rtl_work/_vmake: -------------------------------------------------------------------------------- 1 | m255 2 | K4 3 | z0 4 | cModel Technology 5 | -------------------------------------------------------------------------------- /simulation/modelsim/vish_stacktrace.vstf: -------------------------------------------------------------------------------- 1 | # Current time Mon May 14 11:39:05 2018 2 | # ModelSim - Intel FPGA Edition Stack Trace 3 | # Program = vish 4 | # Id = "10.5b" 5 | # Version = "2016.10" 6 | # Date = "Oct 5 2016" 7 | # Platform = win32pe 8 | 9 | Exception c0000005 has occurred at address 0065d4f5. Traceback: 10 | -------------------------------------------------------------------------------- /simulation/modelsim/vsim.wlf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/DOOKNET/Digital_Clock/c56f1dbf5b4fb8fe69f5c27d19749ed98fe408a7/simulation/modelsim/vsim.wlf -------------------------------------------------------------------------------- /仿真图1.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/DOOKNET/Digital_Clock/c56f1dbf5b4fb8fe69f5c27d19749ed98fe408a7/仿真图1.png -------------------------------------------------------------------------------- /仿真图2.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/DOOKNET/Digital_Clock/c56f1dbf5b4fb8fe69f5c27d19749ed98fe408a7/仿真图2.png -------------------------------------------------------------------------------- /仿真图3.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/DOOKNET/Digital_Clock/c56f1dbf5b4fb8fe69f5c27d19749ed98fe408a7/仿真图3.png --------------------------------------------------------------------------------