├── .Xil ├── Vivado-32765-eecs-digital-02 │ ├── CharactersROM │ │ └── CharactersROM.dcp │ └── clk_wiz_0 │ │ └── clk_wiz_0.dcp └── Vivado-3598-eecs-digital-02 │ ├── CharactersROM │ └── CharactersROM.dcp │ └── clk_wiz_0 │ └── clk_wiz_0.dcp ├── .gitignore ├── Oscilloscope_v1 ├── Oscilloscope_v1.hw │ ├── Oscilloscope_v1.lpr │ ├── hw_1 │ │ ├── hw.xml │ │ └── wave │ │ │ └── hw_ila_data_1 │ │ │ └── hw_ila_data_1.wcfg │ └── webtalk │ │ ├── .xsim_webtallk.info │ │ ├── labtool_webtalk.log │ │ ├── labtool_webtalk.tcl │ │ ├── usage_statistics_ext_labtool.html │ │ └── usage_statistics_ext_labtool.xml ├── Oscilloscope_v1.ip_user_files │ ├── README.txt │ ├── bd │ │ └── fft_mag │ │ │ ├── hdl │ │ │ └── fft_mag.v │ │ │ ├── ip │ │ │ ├── fft_mag_axis_register_slice_2_0 │ │ │ │ ├── fft_mag_axis_register_slice_2_0_sim_netlist.v │ │ │ │ └── sim │ │ │ │ │ └── fft_mag_axis_register_slice_2_0.v │ │ │ ├── fft_mag_c_addsub_0_0 │ │ │ │ ├── fft_mag_c_addsub_0_0_sim_netlist.v │ │ │ │ └── sim │ │ │ │ │ └── fft_mag_c_addsub_0_0.vhd │ │ │ ├── fft_mag_cordic_0_0 │ │ │ │ ├── fft_mag_cordic_0_0_sim_netlist.v │ │ │ │ └── sim │ │ │ │ │ └── fft_mag_cordic_0_0.vhd │ │ │ ├── fft_mag_mult_gen_0_0 │ │ │ │ ├── fft_mag_mult_gen_0_0_sim_netlist.v │ │ │ │ └── sim │ │ │ │ │ └── fft_mag_mult_gen_0_0.vhd │ │ │ ├── fft_mag_mult_gen_1_0 │ │ │ │ ├── fft_mag_mult_gen_1_0_sim_netlist.v │ │ │ │ └── sim │ │ │ │ │ └── fft_mag_mult_gen_1_0.vhd │ │ │ ├── fft_mag_xfft_0_0 │ │ │ │ ├── fft_mag_xfft_0_0_sim_netlist.v │ │ │ │ └── sim │ │ │ │ │ └── fft_mag_xfft_0_0.vhd │ │ │ ├── fft_mag_xlconcat_0_0 │ │ │ │ ├── fft_mag_xlconcat_0_0_sim_netlist.v │ │ │ │ └── sim │ │ │ │ │ └── fft_mag_xlconcat_0_0.v │ │ │ ├── fft_mag_xlconstant_0_0 │ │ │ │ ├── fft_mag_xlconstant_0_0_sim_netlist.v │ │ │ │ └── sim │ │ │ │ │ └── fft_mag_xlconstant_0_0.v │ │ │ ├── fft_mag_xlconstant_1_0 │ │ │ │ ├── fft_mag_xlconstant_1_0_sim_netlist.v │ │ │ │ └── sim │ │ │ │ │ └── fft_mag_xlconstant_1_0.v │ │ │ ├── fft_mag_xlconstant_2_0 │ │ │ │ ├── fft_mag_xlconstant_2_0_sim_netlist.v │ │ │ │ └── sim │ │ │ │ │ └── fft_mag_xlconstant_2_0.v │ │ │ ├── fft_mag_xlslice_0_0 │ │ │ │ ├── fft_mag_xlslice_0_0_sim_netlist.v │ │ │ │ └── sim │ │ │ │ │ └── fft_mag_xlslice_0_0.v │ │ │ └── fft_mag_xlslice_1_0 │ │ │ │ ├── fft_mag_xlslice_1_0_sim_netlist.v │ │ │ │ └── sim │ │ │ │ └── fft_mag_xlslice_1_0.v │ │ │ └── ipshared │ │ │ └── xilinx.com │ │ │ ├── xlconcat_v2_1 │ │ │ └── xlconcat.v │ │ │ ├── xlconstant_v1_1 │ │ │ └── xlconstant.v │ │ │ └── xlslice_v1_0 │ │ │ └── xlslice.v │ ├── ip │ │ ├── CharactersROM │ │ │ ├── CharactersROM_sim_netlist.v │ │ │ ├── CharactersROM_stub.v │ │ │ └── sim │ │ │ │ └── CharactersROM.v │ │ ├── blk_mem_fft │ │ │ ├── blk_mem_fft_sim_netlist.v │ │ │ ├── blk_mem_fft_stub.v │ │ │ └── sim │ │ │ │ └── blk_mem_fft.v │ │ ├── blk_mem_gen_0 │ │ │ ├── blk_mem_gen_0.veo │ │ │ ├── blk_mem_gen_0.vho │ │ │ ├── blk_mem_gen_0_stub.v │ │ │ └── blk_mem_gen_0_stub.vhdl │ │ ├── characterBRAM2 │ │ │ ├── characterBRAM2_sim_netlist.v │ │ │ ├── characterBRAM2_stub.v │ │ │ └── sim │ │ │ │ └── characterBRAM2.v │ │ ├── clk_wiz_0 │ │ │ ├── clk_wiz_0.v │ │ │ ├── clk_wiz_0.veo │ │ │ ├── clk_wiz_0_clk_wiz.v │ │ │ ├── clk_wiz_0_sim_netlist.v │ │ │ ├── clk_wiz_0_stub.v │ │ │ └── clk_wiz_0_stub.vhdl │ │ ├── shift_ram_4cycledelay │ │ │ ├── shift_ram_4cycledelay_sim_netlist.v │ │ │ ├── shift_ram_4cycledelay_stub.v │ │ │ └── sim │ │ │ │ └── shift_ram_4cycledelay.vhd │ │ ├── xadc_wiz_1 │ │ │ ├── xadc_wiz_1.v │ │ │ ├── xadc_wiz_1_sim_netlist.v │ │ │ └── xadc_wiz_1_stub.v │ │ └── xadc_wiz_2 │ │ │ ├── xadc_wiz_2.v │ │ │ ├── xadc_wiz_2_sim_netlist.v │ │ │ └── xadc_wiz_2_stub.v │ ├── ipstatic │ │ ├── axi_utils_v2_0_2 │ │ │ └── hdl │ │ │ │ └── axi_utils_v2_0_vh_rfs.vhd │ │ ├── blk_mem_gen_v8_3_3 │ │ │ └── simulation │ │ │ │ └── blk_mem_gen_v8_3.v │ │ ├── c_mux_bit_v12_0_2 │ │ │ └── hdl │ │ │ │ ├── c_mux_bit_v12_0.vhd │ │ │ │ └── c_mux_bit_v12_0_vh_rfs.vhd │ │ ├── c_reg_fd_v12_0_2 │ │ │ └── hdl │ │ │ │ ├── c_reg_fd_v12_0.vhd │ │ │ │ └── c_reg_fd_v12_0_vh_rfs.vhd │ │ ├── c_shift_ram_v12_0_9 │ │ │ └── hdl │ │ │ │ ├── c_shift_ram_v12_0.vhd │ │ │ │ └── c_shift_ram_v12_0_vh_rfs.vhd │ │ ├── clk_wiz_v5_3_1 │ │ │ ├── mmcm_pll_drp_func_7s_mmcm.vh │ │ │ ├── mmcm_pll_drp_func_7s_pll.vh │ │ │ ├── mmcm_pll_drp_func_us_mmcm.vh │ │ │ └── mmcm_pll_drp_func_us_pll.vh │ │ ├── div_gen_v5_1_10 │ │ │ └── hdl │ │ │ │ ├── div_gen_v5_1.vhd │ │ │ │ └── div_gen_v5_1_vh_rfs.vhd │ │ ├── floating_point_v7_0_12 │ │ │ └── hdl │ │ │ │ └── floating_point_v7_0_vh_rfs.vhd │ │ ├── mult_gen_v12_0_11 │ │ │ └── hdl │ │ │ │ ├── mult_gen_v12_0.vhd │ │ │ │ └── mult_gen_v12_0_vh_rfs.vhd │ │ ├── xbip_bram18k_v3_0_2 │ │ │ └── hdl │ │ │ │ ├── xbip_bram18k_v3_0.vhd │ │ │ │ └── xbip_bram18k_v3_0_vh_rfs.vhd │ │ ├── xbip_dsp48_addsub_v3_0_2 │ │ │ └── hdl │ │ │ │ ├── xbip_dsp48_addsub_v3_0.vhd │ │ │ │ └── xbip_dsp48_addsub_v3_0_vh_rfs.vhd │ │ ├── xbip_dsp48_mult_v3_0_2 │ │ │ └── hdl │ │ │ │ ├── xbip_dsp48_mult_v3_0.vhd │ │ │ │ └── xbip_dsp48_mult_v3_0_vh_rfs.vhd │ │ ├── xbip_dsp48_multadd_v3_0_2 │ │ │ └── hdl │ │ │ │ ├── xbip_dsp48_multadd_v3_0.vhd │ │ │ │ └── xbip_dsp48_multadd_v3_0_vh_rfs.vhd │ │ ├── xbip_dsp48_wrapper_v3_0_4 │ │ │ └── hdl │ │ │ │ └── xbip_dsp48_wrapper_v3_0_vh_rfs.vhd │ │ ├── xbip_pipe_v3_0_2 │ │ │ └── hdl │ │ │ │ ├── xbip_pipe_v3_0.vhd │ │ │ │ └── xbip_pipe_v3_0_vh_rfs.vhd │ │ └── xbip_utils_v3_0_6 │ │ │ └── hdl │ │ │ └── xbip_utils_v3_0_vh_rfs.vhd │ ├── mem_init_files │ │ ├── character32x32.coe │ │ ├── design.txt │ │ └── summary.log │ └── sim_scripts │ │ ├── CharactersROM │ │ ├── README.txt │ │ ├── activehdl │ │ │ ├── README.txt │ │ │ ├── character32x32.coe │ │ │ ├── file_info.txt │ │ │ └── glbl.v │ │ ├── ies │ │ │ ├── README.txt │ │ │ ├── character32x32.coe │ │ │ ├── file_info.txt │ │ │ └── glbl.v │ │ ├── modelsim │ │ │ ├── README.txt │ │ │ ├── character32x32.coe │ │ │ ├── file_info.txt │ │ │ └── glbl.v │ │ ├── questa │ │ │ ├── README.txt │ │ │ ├── character32x32.coe │ │ │ ├── file_info.txt │ │ │ └── glbl.v │ │ ├── riviera │ │ │ ├── README.txt │ │ │ ├── character32x32.coe │ │ │ ├── file_info.txt │ │ │ └── glbl.v │ │ ├── vcs │ │ │ ├── README.txt │ │ │ ├── character32x32.coe │ │ │ ├── file_info.txt │ │ │ └── glbl.v │ │ └── xsim │ │ │ ├── README.txt │ │ │ ├── character32x32.coe │ │ │ ├── cmd.tcl │ │ │ ├── file_info.txt │ │ │ ├── glbl.v │ │ │ ├── vhdl.prj │ │ │ └── vlog.prj │ │ ├── blk_mem_gen_0 │ │ ├── README.txt │ │ ├── activehdl │ │ │ ├── README.txt │ │ │ ├── blk_mem_gen_0.sh │ │ │ ├── blk_mem_gen_0.udo │ │ │ ├── compile.do │ │ │ ├── file_info.txt │ │ │ ├── glbl.v │ │ │ ├── simulate.do │ │ │ ├── summary.log │ │ │ └── wave.do │ │ ├── ies │ │ │ ├── README.txt │ │ │ ├── blk_mem_gen_0.sh │ │ │ ├── file_info.txt │ │ │ ├── glbl.v │ │ │ ├── run.f │ │ │ └── summary.log │ │ ├── modelsim │ │ │ ├── README.txt │ │ │ ├── blk_mem_gen_0.sh │ │ │ ├── blk_mem_gen_0.udo │ │ │ ├── compile.do │ │ │ ├── file_info.txt │ │ │ ├── glbl.v │ │ │ ├── simulate.do │ │ │ ├── summary.log │ │ │ └── wave.do │ │ ├── questa │ │ │ ├── README.txt │ │ │ ├── blk_mem_gen_0.sh │ │ │ ├── blk_mem_gen_0.udo │ │ │ ├── compile.do │ │ │ ├── elaborate.do │ │ │ ├── file_info.txt │ │ │ ├── glbl.v │ │ │ ├── simulate.do │ │ │ ├── summary.log │ │ │ └── wave.do │ │ ├── riviera │ │ │ ├── README.txt │ │ │ ├── blk_mem_gen_0.sh │ │ │ ├── blk_mem_gen_0.udo │ │ │ ├── compile.do │ │ │ ├── file_info.txt │ │ │ ├── glbl.v │ │ │ ├── simulate.do │ │ │ ├── summary.log │ │ │ └── wave.do │ │ ├── vcs │ │ │ ├── README.txt │ │ │ ├── blk_mem_gen_0.sh │ │ │ ├── file_info.txt │ │ │ ├── glbl.v │ │ │ ├── simulate.do │ │ │ └── summary.log │ │ └── xsim │ │ │ ├── README.txt │ │ │ ├── blk_mem_gen_0.sh │ │ │ ├── cmd.tcl │ │ │ ├── file_info.txt │ │ │ ├── glbl.v │ │ │ ├── summary.log │ │ │ ├── vhdl.prj │ │ │ ├── vlog.prj │ │ │ └── xsim.ini │ │ ├── characterBRAM2 │ │ ├── README.txt │ │ ├── activehdl │ │ │ ├── README.txt │ │ │ ├── character32x32.coe │ │ │ ├── file_info.txt │ │ │ └── glbl.v │ │ ├── ies │ │ │ ├── README.txt │ │ │ ├── character32x32.coe │ │ │ ├── file_info.txt │ │ │ └── glbl.v │ │ ├── modelsim │ │ │ ├── README.txt │ │ │ ├── character32x32.coe │ │ │ ├── file_info.txt │ │ │ └── glbl.v │ │ ├── questa │ │ │ ├── README.txt │ │ │ ├── character32x32.coe │ │ │ ├── file_info.txt │ │ │ └── glbl.v │ │ ├── riviera │ │ │ ├── README.txt │ │ │ ├── character32x32.coe │ │ │ ├── file_info.txt │ │ │ └── glbl.v │ │ ├── vcs │ │ │ ├── README.txt │ │ │ ├── character32x32.coe │ │ │ ├── file_info.txt │ │ │ └── glbl.v │ │ └── xsim │ │ │ ├── README.txt │ │ │ ├── character32x32.coe │ │ │ ├── cmd.tcl │ │ │ ├── file_info.txt │ │ │ ├── glbl.v │ │ │ ├── vhdl.prj │ │ │ └── vlog.prj │ │ ├── clk_wiz_0 │ │ ├── README.txt │ │ ├── activehdl │ │ │ ├── README.txt │ │ │ ├── clk_wiz_0.sh │ │ │ ├── clk_wiz_0.udo │ │ │ ├── compile.do │ │ │ ├── file_info.txt │ │ │ ├── glbl.v │ │ │ ├── simulate.do │ │ │ └── wave.do │ │ ├── ies │ │ │ ├── README.txt │ │ │ ├── clk_wiz_0.sh │ │ │ ├── file_info.txt │ │ │ ├── glbl.v │ │ │ └── run.f │ │ ├── modelsim │ │ │ ├── README.txt │ │ │ ├── clk_wiz_0.sh │ │ │ ├── clk_wiz_0.udo │ │ │ ├── compile.do │ │ │ ├── file_info.txt │ │ │ ├── glbl.v │ │ │ ├── simulate.do │ │ │ └── wave.do │ │ ├── questa │ │ │ ├── README.txt │ │ │ ├── clk_wiz_0.sh │ │ │ ├── clk_wiz_0.udo │ │ │ ├── compile.do │ │ │ ├── elaborate.do │ │ │ ├── file_info.txt │ │ │ ├── glbl.v │ │ │ ├── simulate.do │ │ │ └── wave.do │ │ ├── riviera │ │ │ ├── README.txt │ │ │ ├── clk_wiz_0.sh │ │ │ ├── clk_wiz_0.udo │ │ │ ├── compile.do │ │ │ ├── file_info.txt │ │ │ ├── glbl.v │ │ │ ├── simulate.do │ │ │ └── wave.do │ │ ├── vcs │ │ │ ├── README.txt │ │ │ ├── clk_wiz_0.sh │ │ │ ├── file_info.txt │ │ │ ├── glbl.v │ │ │ └── simulate.do │ │ └── xsim │ │ │ ├── README.txt │ │ │ ├── clk_wiz_0.sh │ │ │ ├── cmd.tcl │ │ │ ├── file_info.txt │ │ │ ├── glbl.v │ │ │ ├── vhdl.prj │ │ │ ├── vlog.prj │ │ │ └── xsim.ini │ │ ├── shift_ram_4cycledelay │ │ ├── README.txt │ │ ├── activehdl │ │ │ ├── README.txt │ │ │ ├── file_info.txt │ │ │ └── glbl.v │ │ ├── ies │ │ │ ├── README.txt │ │ │ ├── file_info.txt │ │ │ └── glbl.v │ │ ├── modelsim │ │ │ ├── README.txt │ │ │ ├── file_info.txt │ │ │ └── glbl.v │ │ ├── questa │ │ │ ├── README.txt │ │ │ ├── file_info.txt │ │ │ └── glbl.v │ │ ├── riviera │ │ │ ├── README.txt │ │ │ ├── file_info.txt │ │ │ └── glbl.v │ │ ├── vcs │ │ │ ├── README.txt │ │ │ ├── file_info.txt │ │ │ └── glbl.v │ │ └── xsim │ │ │ ├── README.txt │ │ │ ├── cmd.tcl │ │ │ ├── file_info.txt │ │ │ ├── glbl.v │ │ │ ├── vhdl.prj │ │ │ └── vlog.prj │ │ ├── xadc_wiz_1 │ │ ├── README.txt │ │ ├── activehdl │ │ │ ├── README.txt │ │ │ ├── design.txt │ │ │ ├── file_info.txt │ │ │ └── glbl.v │ │ ├── ies │ │ │ ├── README.txt │ │ │ ├── design.txt │ │ │ ├── file_info.txt │ │ │ └── glbl.v │ │ ├── modelsim │ │ │ ├── README.txt │ │ │ ├── design.txt │ │ │ ├── file_info.txt │ │ │ └── glbl.v │ │ ├── questa │ │ │ ├── README.txt │ │ │ ├── design.txt │ │ │ ├── file_info.txt │ │ │ └── glbl.v │ │ ├── riviera │ │ │ ├── README.txt │ │ │ ├── design.txt │ │ │ ├── file_info.txt │ │ │ └── glbl.v │ │ ├── vcs │ │ │ ├── README.txt │ │ │ ├── design.txt │ │ │ ├── file_info.txt │ │ │ └── glbl.v │ │ └── xsim │ │ │ ├── README.txt │ │ │ ├── cmd.tcl │ │ │ ├── design.txt │ │ │ ├── file_info.txt │ │ │ ├── glbl.v │ │ │ ├── vhdl.prj │ │ │ └── vlog.prj │ │ └── xadc_wiz_2 │ │ ├── README.txt │ │ ├── activehdl │ │ ├── README.txt │ │ ├── design.txt │ │ ├── file_info.txt │ │ └── glbl.v │ │ ├── ies │ │ ├── README.txt │ │ ├── design.txt │ │ ├── file_info.txt │ │ └── glbl.v │ │ ├── modelsim │ │ ├── README.txt │ │ ├── design.txt │ │ ├── file_info.txt │ │ └── glbl.v │ │ ├── questa │ │ ├── README.txt │ │ ├── design.txt │ │ ├── file_info.txt │ │ └── glbl.v │ │ ├── riviera │ │ ├── README.txt │ │ ├── design.txt │ │ ├── file_info.txt │ │ └── glbl.v │ │ ├── vcs │ │ ├── README.txt │ │ ├── design.txt │ │ ├── file_info.txt │ │ └── glbl.v │ │ └── xsim │ │ ├── README.txt │ │ ├── cmd.tcl │ │ ├── design.txt │ │ ├── file_info.txt │ │ ├── glbl.v │ │ ├── vhdl.prj │ │ └── vlog.prj ├── Oscilloscope_v1.sim │ └── sim_1 │ │ ├── behav │ │ ├── character32x32.coe │ │ ├── glbl.v │ │ ├── test_vhdl.prj │ │ ├── test_vlog.prj │ │ ├── xvhdl.pb │ │ └── xvlog.pb │ │ └── synth │ │ └── func │ │ ├── ToggleChannels_func_synth.v │ │ ├── ToggleChannels_vlog.prj │ │ ├── character32x32.coe │ │ └── xvlog.pb ├── Oscilloscope_v1.srcs │ ├── constrs_1 │ │ └── imports │ │ │ └── constraints │ │ │ └── Nexys4DDR_Master.xdc │ ├── sim_1 │ │ └── new │ │ │ └── test.v │ └── sources_1 │ │ ├── bd │ │ └── fft_mag │ │ │ ├── fft_mag.bd │ │ │ ├── fft_mag.bxml │ │ │ ├── fft_mag_ooc.xdc │ │ │ ├── hdl │ │ │ ├── fft_mag.v │ │ │ └── fft_mag_wrapper.v │ │ │ ├── hw_handoff │ │ │ └── fft_mag_bd.tcl │ │ │ ├── ip │ │ │ ├── fft_mag_axis_register_slice_2_0 │ │ │ │ ├── fft_mag_axis_register_slice_2_0.dcp │ │ │ │ ├── fft_mag_axis_register_slice_2_0.xci │ │ │ │ ├── fft_mag_axis_register_slice_2_0_ooc.xdc │ │ │ │ ├── fft_mag_axis_register_slice_2_0_sim_netlist.v │ │ │ │ ├── fft_mag_axis_register_slice_2_0_stub.v │ │ │ │ ├── sim │ │ │ │ │ └── fft_mag_axis_register_slice_2_0.v │ │ │ │ └── synth │ │ │ │ │ └── fft_mag_axis_register_slice_2_0.v │ │ │ ├── fft_mag_c_addsub_0_0 │ │ │ │ ├── fft_mag_c_addsub_0_0.dcp │ │ │ │ ├── fft_mag_c_addsub_0_0.xci │ │ │ │ ├── fft_mag_c_addsub_0_0_sim_netlist.v │ │ │ │ ├── fft_mag_c_addsub_0_0_stub.v │ │ │ │ ├── sim │ │ │ │ │ └── fft_mag_c_addsub_0_0.vhd │ │ │ │ └── synth │ │ │ │ │ └── fft_mag_c_addsub_0_0.vhd │ │ │ ├── fft_mag_cordic_0_0 │ │ │ │ ├── fft_mag_cordic_0_0.dcp │ │ │ │ ├── fft_mag_cordic_0_0.xci │ │ │ │ ├── fft_mag_cordic_0_0_ooc.xdc │ │ │ │ ├── fft_mag_cordic_0_0_sim_netlist.v │ │ │ │ ├── fft_mag_cordic_0_0_stub.v │ │ │ │ ├── sim │ │ │ │ │ └── fft_mag_cordic_0_0.vhd │ │ │ │ └── synth │ │ │ │ │ └── fft_mag_cordic_0_0.vhd │ │ │ ├── fft_mag_mult_gen_0_0 │ │ │ │ ├── fft_mag_mult_gen_0_0.dcp │ │ │ │ ├── fft_mag_mult_gen_0_0.xci │ │ │ │ ├── fft_mag_mult_gen_0_0_ooc.xdc │ │ │ │ ├── fft_mag_mult_gen_0_0_sim_netlist.v │ │ │ │ ├── fft_mag_mult_gen_0_0_stub.v │ │ │ │ ├── sim │ │ │ │ │ └── fft_mag_mult_gen_0_0.vhd │ │ │ │ └── synth │ │ │ │ │ └── fft_mag_mult_gen_0_0.vhd │ │ │ ├── fft_mag_mult_gen_1_0 │ │ │ │ ├── fft_mag_mult_gen_1_0.dcp │ │ │ │ ├── fft_mag_mult_gen_1_0.xci │ │ │ │ ├── fft_mag_mult_gen_1_0_ooc.xdc │ │ │ │ ├── fft_mag_mult_gen_1_0_sim_netlist.v │ │ │ │ ├── fft_mag_mult_gen_1_0_stub.v │ │ │ │ ├── sim │ │ │ │ │ └── fft_mag_mult_gen_1_0.vhd │ │ │ │ └── synth │ │ │ │ │ └── fft_mag_mult_gen_1_0.vhd │ │ │ ├── fft_mag_xfft_0_0 │ │ │ │ ├── fft_mag_xfft_0_0.dcp │ │ │ │ ├── fft_mag_xfft_0_0.xci │ │ │ │ ├── fft_mag_xfft_0_0_ooc.xdc │ │ │ │ ├── fft_mag_xfft_0_0_sim_netlist.v │ │ │ │ ├── fft_mag_xfft_0_0_stub.v │ │ │ │ ├── sim │ │ │ │ │ └── fft_mag_xfft_0_0.vhd │ │ │ │ └── synth │ │ │ │ │ └── fft_mag_xfft_0_0.vhd │ │ │ ├── fft_mag_xlconcat_0_0 │ │ │ │ ├── fft_mag_xlconcat_0_0.dcp │ │ │ │ ├── fft_mag_xlconcat_0_0.xci │ │ │ │ ├── fft_mag_xlconcat_0_0_sim_netlist.v │ │ │ │ ├── fft_mag_xlconcat_0_0_stub.v │ │ │ │ ├── sim │ │ │ │ │ └── fft_mag_xlconcat_0_0.v │ │ │ │ └── synth │ │ │ │ │ └── fft_mag_xlconcat_0_0.v │ │ │ ├── fft_mag_xlconstant_0_0 │ │ │ │ ├── fft_mag_xlconstant_0_0.dcp │ │ │ │ ├── fft_mag_xlconstant_0_0.xci │ │ │ │ ├── fft_mag_xlconstant_0_0_sim_netlist.v │ │ │ │ ├── fft_mag_xlconstant_0_0_stub.v │ │ │ │ └── sim │ │ │ │ │ └── fft_mag_xlconstant_0_0.v │ │ │ ├── fft_mag_xlconstant_1_0 │ │ │ │ ├── fft_mag_xlconstant_1_0.dcp │ │ │ │ ├── fft_mag_xlconstant_1_0.xci │ │ │ │ ├── fft_mag_xlconstant_1_0_sim_netlist.v │ │ │ │ ├── fft_mag_xlconstant_1_0_stub.v │ │ │ │ └── sim │ │ │ │ │ └── fft_mag_xlconstant_1_0.v │ │ │ ├── fft_mag_xlconstant_2_0 │ │ │ │ ├── fft_mag_xlconstant_2_0.dcp │ │ │ │ ├── fft_mag_xlconstant_2_0.xci │ │ │ │ ├── fft_mag_xlconstant_2_0_sim_netlist.v │ │ │ │ ├── fft_mag_xlconstant_2_0_stub.v │ │ │ │ └── sim │ │ │ │ │ └── fft_mag_xlconstant_2_0.v │ │ │ ├── fft_mag_xlslice_0_0 │ │ │ │ ├── fft_mag_xlslice_0_0.dcp │ │ │ │ ├── fft_mag_xlslice_0_0.xci │ │ │ │ ├── fft_mag_xlslice_0_0_sim_netlist.v │ │ │ │ ├── fft_mag_xlslice_0_0_stub.v │ │ │ │ ├── sim │ │ │ │ │ └── fft_mag_xlslice_0_0.v │ │ │ │ └── synth │ │ │ │ │ └── fft_mag_xlslice_0_0.v │ │ │ └── fft_mag_xlslice_1_0 │ │ │ │ ├── fft_mag_xlslice_1_0.dcp │ │ │ │ ├── fft_mag_xlslice_1_0.xci │ │ │ │ ├── fft_mag_xlslice_1_0_sim_netlist.v │ │ │ │ ├── fft_mag_xlslice_1_0_stub.v │ │ │ │ ├── sim │ │ │ │ └── fft_mag_xlslice_1_0.v │ │ │ │ └── synth │ │ │ │ └── fft_mag_xlslice_1_0.v │ │ │ ├── ipshared │ │ │ └── xilinx.com │ │ │ │ ├── axi_utils_v2_0 │ │ │ │ └── hdl │ │ │ │ │ └── axi_utils_v2_0_vh_rfs.vhd │ │ │ │ ├── axis_infrastructure_v1_1 │ │ │ │ └── hdl │ │ │ │ │ └── verilog │ │ │ │ │ ├── axis_infrastructure_v1_1_cdc_handshake.v │ │ │ │ │ ├── axis_infrastructure_v1_1_clock_synchronizer.v │ │ │ │ │ ├── axis_infrastructure_v1_1_mux_enc.v │ │ │ │ │ ├── axis_infrastructure_v1_1_util_aclken_converter.v │ │ │ │ │ ├── axis_infrastructure_v1_1_util_aclken_converter_wrapper.v │ │ │ │ │ ├── axis_infrastructure_v1_1_util_axis2vector.v │ │ │ │ │ └── axis_infrastructure_v1_1_util_vector2axis.v │ │ │ │ ├── axis_register_slice_v1_1 │ │ │ │ └── hdl │ │ │ │ │ └── verilog │ │ │ │ │ ├── axis_register_slice_v1_1_axis_register_slice.v │ │ │ │ │ └── axis_register_slice_v1_1_axisc_register_slice.v │ │ │ │ ├── c_addsub_v12_0 │ │ │ │ └── hdl │ │ │ │ │ ├── c_addsub_v12_0.vhd │ │ │ │ │ └── c_addsub_v12_0_vh_rfs.vhd │ │ │ │ ├── c_mux_bit_v12_0 │ │ │ │ └── hdl │ │ │ │ │ ├── c_mux_bit_v12_0.vhd │ │ │ │ │ └── c_mux_bit_v12_0_vh_rfs.vhd │ │ │ │ ├── c_reg_fd_v12_0 │ │ │ │ └── hdl │ │ │ │ │ ├── c_reg_fd_v12_0.vhd │ │ │ │ │ └── c_reg_fd_v12_0_vh_rfs.vhd │ │ │ │ ├── c_shift_ram_v12_0 │ │ │ │ └── hdl │ │ │ │ │ ├── c_shift_ram_v12_0.vhd │ │ │ │ │ └── c_shift_ram_v12_0_vh_rfs.vhd │ │ │ │ ├── cmpy_v6_0 │ │ │ │ └── hdl │ │ │ │ │ ├── cmpy_v6_0.vhd │ │ │ │ │ └── cmpy_v6_0_vh_rfs.vhd │ │ │ │ ├── cordic_v6_0 │ │ │ │ └── hdl │ │ │ │ │ ├── cordic_v6_0.vhd │ │ │ │ │ └── cordic_v6_0_vh_rfs.vhd │ │ │ │ ├── floating_point_v7_0 │ │ │ │ └── hdl │ │ │ │ │ └── floating_point_v7_0_vh_rfs.vhd │ │ │ │ ├── mult_gen_v12_0 │ │ │ │ └── hdl │ │ │ │ │ ├── mult_gen_v12_0.vhd │ │ │ │ │ └── mult_gen_v12_0_vh_rfs.vhd │ │ │ │ ├── xbip_addsub_v3_0 │ │ │ │ └── hdl │ │ │ │ │ ├── xbip_addsub_v3_0.vhd │ │ │ │ │ └── xbip_addsub_v3_0_vh_rfs.vhd │ │ │ │ ├── xbip_bram18k_v3_0 │ │ │ │ └── hdl │ │ │ │ │ ├── xbip_bram18k_v3_0.vhd │ │ │ │ │ └── xbip_bram18k_v3_0_vh_rfs.vhd │ │ │ │ ├── xbip_dsp48_addsub_v3_0 │ │ │ │ └── hdl │ │ │ │ │ ├── xbip_dsp48_addsub_v3_0.vhd │ │ │ │ │ └── xbip_dsp48_addsub_v3_0_vh_rfs.vhd │ │ │ │ ├── xbip_dsp48_wrapper_v3_0 │ │ │ │ └── hdl │ │ │ │ │ └── xbip_dsp48_wrapper_v3_0_vh_rfs.vhd │ │ │ │ ├── xbip_pipe_v3_0 │ │ │ │ └── hdl │ │ │ │ │ ├── xbip_pipe_v3_0.vhd │ │ │ │ │ └── xbip_pipe_v3_0_vh_rfs.vhd │ │ │ │ ├── xbip_utils_v3_0 │ │ │ │ └── hdl │ │ │ │ │ └── xbip_utils_v3_0_vh_rfs.vhd │ │ │ │ ├── xfft_v9_0 │ │ │ │ └── hdl │ │ │ │ │ ├── xfft_v9_0.vhd │ │ │ │ │ └── xfft_v9_0_vh_rfs.vhd │ │ │ │ ├── xlconcat_v2_1 │ │ │ │ └── xlconcat.v │ │ │ │ ├── xlconstant_v1_1 │ │ │ │ └── xlconstant.v │ │ │ │ └── xlslice_v1_0 │ │ │ │ └── xlslice.v │ │ │ └── ui │ │ │ └── bd_1adb83c8.ui │ │ ├── imports │ │ ├── 6.111-Final-Project │ │ │ ├── jorge │ │ │ │ └── oscilloscope │ │ │ │ │ └── oscilloscope.srcs │ │ │ │ │ └── sources_1 │ │ │ │ │ └── new │ │ │ │ │ └── TriggerRisingEdge.v │ │ │ └── project_xadc │ │ │ │ ├── proj │ │ │ │ └── XADC_Demo.srcs │ │ │ │ │ └── sources_1 │ │ │ │ │ └── new │ │ │ │ │ └── ADCController.v │ │ │ │ └── src │ │ │ │ └── hdl │ │ │ │ ├── DigitToSeg.v │ │ │ │ ├── buffer.v │ │ │ │ └── xvga.v │ │ ├── Downloads │ │ │ └── debounce.v │ │ ├── ddr │ │ │ ├── EdgeTypeDetector.v │ │ │ └── SampleAverager.v │ │ └── tmp │ │ │ └── EdgeTypeDetector.v │ │ ├── ip │ │ ├── .Xil │ │ │ └── .xadc_wiz_0.xcix.lock │ │ ├── CharactersROM.xcix │ │ ├── blk_mem_gen_0 │ │ │ ├── blk_mem_gen_0.dcp │ │ │ ├── blk_mem_gen_0.veo │ │ │ ├── blk_mem_gen_0.vho │ │ │ ├── blk_mem_gen_0.xci │ │ │ ├── blk_mem_gen_0.xml │ │ │ ├── blk_mem_gen_0_ooc.xdc │ │ │ ├── blk_mem_gen_0_sim_netlist.v │ │ │ ├── blk_mem_gen_0_sim_netlist.vhdl │ │ │ ├── blk_mem_gen_0_stub.v │ │ │ ├── blk_mem_gen_0_stub.vhdl │ │ │ ├── blk_mem_gen_v8_3_3 │ │ │ │ ├── hdl │ │ │ │ │ ├── blk_mem_gen_v8_3.vhd │ │ │ │ │ └── blk_mem_gen_v8_3_vhsyn_rfs.vhd │ │ │ │ └── simulation │ │ │ │ │ └── blk_mem_gen_v8_3.v │ │ │ ├── doc │ │ │ │ └── blk_mem_gen_v8_3_changelog.txt │ │ │ ├── misc │ │ │ │ └── blk_mem_gen_v8_3.vhd │ │ │ ├── sim │ │ │ │ └── blk_mem_gen_0.v │ │ │ ├── summary.log │ │ │ └── synth │ │ │ │ └── blk_mem_gen_0.vhd │ │ ├── character32x32.coe │ │ └── xadc_wiz_0.xcix │ │ └── new │ │ ├── BufferSelector.v │ │ ├── ButtonSinglePulse.v │ │ ├── ConvertBCD.v │ │ ├── Curve.v │ │ ├── CurveFFT.v │ │ ├── DecimalToROMLocation.v │ │ ├── GetVerticalScaleExponents.v │ │ ├── Grid.v │ │ ├── MeasureSignal.v │ │ ├── Oscilloscope_v1.v │ │ ├── SamplePeriodToTimePerDivision.v │ │ ├── ScopeSettings.v │ │ ├── SelectChannelData.v │ │ ├── SignalFFT.v │ │ ├── SignalToVoltage.v │ │ ├── SimultaneousSamplingXADC.v │ │ ├── Text.v │ │ ├── Text30Characters.v │ │ ├── ToggleChannels.v │ │ ├── TriggerLevelSprite.v │ │ ├── VerticalScaler.vh │ │ ├── XYCurve.v │ │ ├── YPixelToVoltage.v │ │ └── debounce.v ├── Oscilloscope_v1.xpr ├── Oscilloscope_v1_videodemo2048fft.bit ├── character32x32.coe ├── ip_upgrade.log ├── vivado.jou └── webtalk.jou ├── README.md ├── buffer-sim └── buffer.v ├── jorge ├── oscilloscope │ ├── oscilloscope.cache │ │ └── wt │ │ │ ├── java_command_handlers.wdf │ │ │ ├── project.wpc │ │ │ ├── synthesis.wdf │ │ │ └── webtalk_pa.xml │ ├── oscilloscope.hw │ │ ├── oscilloscope.lpr │ │ └── webtalk │ │ │ ├── .xsim_webtallk.info │ │ │ ├── labtool_webtalk.log │ │ │ ├── usage_statistics_ext_labtool.html │ │ │ └── usage_statistics_ext_labtool.xml │ ├── oscilloscope.ip_user_files │ │ ├── README.txt │ │ ├── ip │ │ │ └── blk_mem_gen_0 │ │ │ │ ├── blk_mem_gen_0.veo │ │ │ │ ├── blk_mem_gen_0.vho │ │ │ │ ├── blk_mem_gen_0_stub.v │ │ │ │ └── blk_mem_gen_0_stub.vhdl │ │ ├── ipstatic │ │ │ └── blk_mem_gen_v8_3_3 │ │ │ │ └── simulation │ │ │ │ └── blk_mem_gen_v8_3.v │ │ ├── mem_init_files │ │ │ └── summary.log │ │ └── sim_scripts │ │ │ └── blk_mem_gen_0 │ │ │ ├── README.txt │ │ │ ├── activehdl │ │ │ ├── README.txt │ │ │ ├── blk_mem_gen_0.sh │ │ │ ├── blk_mem_gen_0.udo │ │ │ ├── compile.do │ │ │ ├── file_info.txt │ │ │ ├── glbl.v │ │ │ ├── simulate.do │ │ │ ├── summary.log │ │ │ └── wave.do │ │ │ ├── ies │ │ │ ├── README.txt │ │ │ ├── blk_mem_gen_0.sh │ │ │ ├── file_info.txt │ │ │ ├── glbl.v │ │ │ ├── run.f │ │ │ └── summary.log │ │ │ ├── modelsim │ │ │ ├── README.txt │ │ │ ├── blk_mem_gen_0.sh │ │ │ ├── blk_mem_gen_0.udo │ │ │ ├── compile.do │ │ │ ├── file_info.txt │ │ │ ├── glbl.v │ │ │ ├── simulate.do │ │ │ ├── summary.log │ │ │ └── wave.do │ │ │ ├── questa │ │ │ ├── README.txt │ │ │ ├── blk_mem_gen_0.sh │ │ │ ├── blk_mem_gen_0.udo │ │ │ ├── compile.do │ │ │ ├── elaborate.do │ │ │ ├── file_info.txt │ │ │ ├── glbl.v │ │ │ ├── simulate.do │ │ │ ├── summary.log │ │ │ └── wave.do │ │ │ ├── riviera │ │ │ ├── README.txt │ │ │ ├── blk_mem_gen_0.sh │ │ │ ├── blk_mem_gen_0.udo │ │ │ ├── compile.do │ │ │ ├── file_info.txt │ │ │ ├── glbl.v │ │ │ ├── simulate.do │ │ │ ├── summary.log │ │ │ └── wave.do │ │ │ ├── vcs │ │ │ ├── README.txt │ │ │ ├── blk_mem_gen_0.sh │ │ │ ├── file_info.txt │ │ │ ├── glbl.v │ │ │ ├── simulate.do │ │ │ └── summary.log │ │ │ └── xsim │ │ │ ├── README.txt │ │ │ ├── blk_mem_gen_0.sh │ │ │ ├── cmd.tcl │ │ │ ├── file_info.txt │ │ │ ├── glbl.v │ │ │ ├── summary.log │ │ │ ├── vhdl.prj │ │ │ ├── vlog.prj │ │ │ └── xsim.ini │ ├── oscilloscope.runs │ │ ├── .jobs │ │ │ └── vrs_config_1.xml │ │ └── blk_mem_gen_0_synth_1 │ │ │ ├── .Vivado_Synthesis.queue.rst │ │ │ ├── .vivado.begin.rst │ │ │ ├── .vivado.end.rst │ │ │ ├── ISEWrap.js │ │ │ ├── ISEWrap.sh │ │ │ ├── blk_mem_gen_0.dcp │ │ │ ├── blk_mem_gen_0.tcl │ │ │ ├── blk_mem_gen_0.vds │ │ │ ├── blk_mem_gen_0_utilization_synth.pb │ │ │ ├── blk_mem_gen_0_utilization_synth.rpt │ │ │ ├── dont_touch.xdc │ │ │ ├── gen_run.xml │ │ │ ├── htr.txt │ │ │ ├── project.wdf │ │ │ ├── rundef.js │ │ │ ├── runme.bat │ │ │ ├── runme.log │ │ │ ├── runme.sh │ │ │ ├── vivado.jou │ │ │ └── vivado.pb │ ├── oscilloscope.srcs │ │ └── sources_1 │ │ │ ├── ip │ │ │ └── blk_mem_gen_0 │ │ │ │ ├── blk_mem_gen_0.dcp │ │ │ │ ├── blk_mem_gen_0.veo │ │ │ │ ├── blk_mem_gen_0.vho │ │ │ │ ├── blk_mem_gen_0.xci │ │ │ │ ├── blk_mem_gen_0.xml │ │ │ │ ├── blk_mem_gen_0_ooc.xdc │ │ │ │ ├── blk_mem_gen_0_sim_netlist.v │ │ │ │ ├── blk_mem_gen_0_sim_netlist.vhdl │ │ │ │ ├── blk_mem_gen_0_stub.v │ │ │ │ ├── blk_mem_gen_0_stub.vhdl │ │ │ │ ├── blk_mem_gen_v8_3_3 │ │ │ │ ├── hdl │ │ │ │ │ ├── blk_mem_gen_v8_3.vhd │ │ │ │ │ └── blk_mem_gen_v8_3_vhsyn_rfs.vhd │ │ │ │ └── simulation │ │ │ │ │ └── blk_mem_gen_v8_3.v │ │ │ │ ├── doc │ │ │ │ └── blk_mem_gen_v8_3_changelog.txt │ │ │ │ ├── misc │ │ │ │ └── blk_mem_gen_v8_3.vhd │ │ │ │ ├── sim │ │ │ │ └── blk_mem_gen_0.v │ │ │ │ ├── summary.log │ │ │ │ └── synth │ │ │ │ └── blk_mem_gen_0.vhd │ │ │ └── new │ │ │ ├── Buffer.v │ │ │ ├── Curve.v │ │ │ ├── GenerateWave.v │ │ │ ├── Trigger.v │ │ │ └── TriggerRisingEdge.v │ └── oscilloscope.xpr └── oscilloscopeISE │ ├── .lso │ ├── GenerateWave.prj │ ├── GenerateWave.stx │ ├── GenerateWave.v │ ├── GenerateWave.xst │ ├── GenerateWave_tb.fdo │ ├── GenerateWave_tb.udo │ ├── GenerateWave_tb.v │ ├── GenerateWave_tb_wave.fdo │ ├── Trigger.cmd_log │ ├── Trigger.lso │ ├── Trigger.ngc │ ├── Trigger.ngr │ ├── Trigger.prj │ ├── Trigger.stx │ ├── Trigger.syr │ ├── Trigger.v │ ├── Trigger.xst │ ├── Trigger_summary.html │ ├── Trigger_tb.udo │ ├── Trigger_tb.v │ ├── Trigger_tb_wave.fdo │ ├── Trigger_xst.xrpt │ ├── _xmsgs │ └── xst.xmsgs │ ├── oscilloscopeISE.ise │ ├── oscilloscopeISE.ntrc_log │ ├── oscilloscopeISE.restore │ ├── oscilloscopeISE_xdb │ └── tmp │ │ ├── ise.lock │ │ └── ise │ │ ├── __OBJSTORE__ │ │ ├── HierarchicalDesign │ │ │ ├── HDProject │ │ │ │ ├── HDProject │ │ │ │ └── HDProject_StrTbl │ │ │ └── __stored_object_table__ │ │ ├── PnAutoRun │ │ │ └── Scripts │ │ │ │ ├── RunOnce_tcl │ │ │ │ └── RunOnce_tcl_StrTbl │ │ ├── ProjectNavigator │ │ │ ├── __stored_object_table__ │ │ │ ├── __stored_objects__ │ │ │ ├── __stored_objects___StrTbl │ │ │ └── dpm_project_main │ │ │ │ ├── NameMap │ │ │ │ ├── NameMap_StrTbl │ │ │ │ ├── dpm_project_main │ │ │ │ └── dpm_project_main_StrTbl │ │ ├── ProjectNavigatorGui │ │ │ ├── GuiProjectData │ │ │ └── GuiProjectData_StrTbl │ │ └── xreport │ │ │ ├── Gc_RvReportViewer-Current-Module │ │ │ ├── Gc_RvReportViewer-Current-Module_StrTbl │ │ │ ├── Gc_RvReportViewer-Module-Data-Trigger │ │ │ ├── Gc_RvReportViewer-Module-Data-Trigger_StrTbl │ │ │ ├── Gc_RvReportViewer-Module-DataFactory-Default │ │ │ └── Gc_RvReportViewer-Module-DataFactory-Default_StrTbl │ │ ├── __REGISTRY__ │ │ ├── Autonym │ │ │ └── regkeys │ │ ├── HierarchicalDesign │ │ │ ├── HDProject │ │ │ │ └── regkeys │ │ │ └── regkeys │ │ ├── ProjectNavigator │ │ │ └── regkeys │ │ ├── ProjectNavigatorGui │ │ │ └── regkeys │ │ ├── ProjectSeedData │ │ │ ├── ProcessProperties │ │ │ │ └── regkeys │ │ │ ├── ProjectProperties │ │ │ │ └── regkeys │ │ │ ├── UserLibraries │ │ │ │ └── regkeys │ │ │ ├── UserPartitions │ │ │ │ └── regkeys │ │ │ ├── UserSourceFiles │ │ │ │ └── regkeys │ │ │ └── regkeys │ │ ├── STE │ │ │ ├── regkeys │ │ │ └── xst │ │ │ │ └── regkeys │ │ ├── SrcCtrl │ │ │ └── regkeys │ │ ├── XSLTProcess │ │ │ └── regkeys │ │ ├── _ProjRepoInternal_ │ │ │ └── regkeys │ │ ├── bitgen │ │ │ └── regkeys │ │ ├── common │ │ │ └── regkeys │ │ ├── cpldfit │ │ │ └── regkeys │ │ ├── dumpngdio │ │ │ └── regkeys │ │ ├── fuse │ │ │ └── regkeys │ │ ├── hprep6 │ │ │ └── regkeys │ │ ├── idem │ │ │ └── regkeys │ │ ├── map │ │ │ └── regkeys │ │ ├── netgen │ │ │ └── regkeys │ │ ├── ngc2edif │ │ │ └── regkeys │ │ ├── ngcbuild │ │ │ └── regkeys │ │ ├── ngdbuild │ │ │ └── regkeys │ │ ├── par │ │ │ └── regkeys │ │ ├── runner │ │ │ └── regkeys │ │ ├── taengine │ │ │ └── regkeys │ │ ├── trce │ │ │ └── regkeys │ │ ├── tsim │ │ │ └── regkeys │ │ ├── vhpcomp │ │ │ └── regkeys │ │ ├── vlogcomp │ │ │ └── regkeys │ │ ├── xpwr │ │ │ └── regkeys │ │ ├── xreport │ │ │ └── regkeys │ │ └── xst │ │ │ └── regkeys │ │ └── version │ ├── transcript │ ├── vsim.wlf │ ├── wlft2xeQvm │ ├── wlft4h8acV │ ├── wlftDjE2TP │ ├── wlftJv4zxd │ ├── wlftM5egcy │ ├── wlftawKRuS │ ├── wlfthn9DpD │ ├── wlftk5YPg7 │ ├── work │ ├── @generate@wave │ │ ├── _primary.dat │ │ ├── _primary.dbs │ │ └── _primary.vhd │ ├── @generate@wave_tb │ │ ├── _primary.dat │ │ ├── _primary.dbs │ │ └── _primary.vhd │ ├── @trigger │ │ ├── _primary.dat │ │ ├── _primary.dbs │ │ └── _primary.vhd │ ├── @trigger_tb │ │ ├── _primary.dat │ │ ├── _primary.dbs │ │ └── _primary.vhd │ ├── _info │ ├── _opt │ │ ├── _deps │ │ ├── vopt039maj │ │ ├── vopt0z7a00 │ │ ├── vopt1mvf68 │ │ ├── vopt6218e0 │ │ ├── vopt6ib78w │ │ ├── vopt6z5z9n │ │ ├── vopta6xbch │ │ ├── voptc58346 │ │ ├── voptd1m5qk │ │ ├── voptd8ed5i │ │ ├── voptdybyq0 │ │ ├── voptej2nys │ │ ├── voptff7yyy │ │ ├── voptqy033e │ │ ├── voptrvvfgb │ │ ├── voptsds8rb │ │ ├── voptxw6ewc │ │ ├── vopty3k9w1 │ │ └── voptytgmn1 │ ├── _opt1 │ │ ├── _deps │ │ ├── vopt02n6w9 │ │ ├── vopt3tf3vr │ │ ├── vopt4w2rqv │ │ ├── vopt62biek │ │ ├── vopt63q4hv │ │ ├── vopt6cca90 │ │ ├── vopt7c5iz8 │ │ ├── vopt8ngi12 │ │ ├── voptars7a3 │ │ ├── voptd91xvq │ │ ├── voptdcm6ke │ │ ├── voptfg54ew │ │ ├── voptfs910t │ │ ├── voptgi5ni4 │ │ ├── voptjgdyhw │ │ ├── voptkqw095 │ │ ├── voptn4gbcv │ │ ├── voptt73043 │ │ └── vopty8ba5r │ ├── _opt2 │ │ ├── _deps │ │ ├── vopt4jkea1 │ │ ├── vopt5f610q │ │ ├── vopt6nf3g2 │ │ ├── vopta0zj6z │ │ ├── vopta9q6xt │ │ ├── voptcywqjw │ │ ├── voptey1wj6 │ │ ├── voptfmqwmr │ │ ├── vopthresxk │ │ ├── voptm3qagg │ │ ├── voptr15rqt │ │ ├── voptr8ma02 │ │ ├── voptsy333k │ │ ├── voptt0zw4j │ │ ├── voptty7j8i │ │ ├── voptxhmeyj │ │ ├── vopty2vkb6 │ │ ├── vopty9t41b │ │ └── voptygzyjb │ ├── _opt2__lock │ ├── _opt__lock │ ├── _temp │ │ ├── vlog0n5neI │ │ ├── vlog4ejZr6 │ │ ├── vlogO23DWc │ │ ├── vlogO4OU3f │ │ ├── vlogWK3kUk │ │ └── vlogu8VVjQ │ ├── _vmake │ └── glbl │ │ ├── _primary.dat │ │ ├── _primary.dbs │ │ └── _primary.vhd │ └── xst │ ├── dump.xst │ └── Trigger.prj │ │ └── ntrc.scr │ └── work │ ├── hdllib.ref │ ├── vlg2C │ └── _trigger.bin │ └── vlg66 │ └── _generate_wave.bin ├── project_buffer_test ├── project_xvga_disp.cache │ └── wt │ │ └── webtalk_pa.xml ├── project_xvga_disp.hw │ ├── hw_1 │ │ └── hw.xml │ └── webtalk │ │ ├── labtool_webtalk.tcl │ │ └── usage_statistics_ext_labtool.xml ├── project_xvga_disp.ip_user_files │ ├── README.txt │ ├── ip │ │ └── clk_wiz_0 │ │ │ └── clk_wiz_0_stub.v │ ├── ipstatic │ │ └── blk_mem_gen_v8_3_3 │ │ │ └── simulation │ │ │ └── blk_mem_gen_v8_3.v │ └── sim_scripts │ │ ├── blk_mem_gen_0 │ │ ├── README.txt │ │ ├── activehdl │ │ │ ├── README.txt │ │ │ ├── file_info.txt │ │ │ └── glbl.v │ │ ├── ies │ │ │ ├── README.txt │ │ │ ├── file_info.txt │ │ │ └── glbl.v │ │ ├── modelsim │ │ │ ├── README.txt │ │ │ ├── file_info.txt │ │ │ └── glbl.v │ │ ├── questa │ │ │ ├── README.txt │ │ │ ├── file_info.txt │ │ │ └── glbl.v │ │ ├── riviera │ │ │ ├── README.txt │ │ │ ├── file_info.txt │ │ │ └── glbl.v │ │ ├── vcs │ │ │ ├── README.txt │ │ │ ├── file_info.txt │ │ │ └── glbl.v │ │ └── xsim │ │ │ ├── README.txt │ │ │ ├── cmd.tcl │ │ │ ├── file_info.txt │ │ │ ├── glbl.v │ │ │ ├── vhdl.prj │ │ │ └── vlog.prj │ │ ├── blk_mem_gen_1 │ │ ├── README.txt │ │ ├── activehdl │ │ │ ├── README.txt │ │ │ ├── file_info.txt │ │ │ └── glbl.v │ │ ├── ies │ │ │ ├── README.txt │ │ │ ├── file_info.txt │ │ │ └── glbl.v │ │ ├── modelsim │ │ │ ├── README.txt │ │ │ ├── file_info.txt │ │ │ └── glbl.v │ │ ├── questa │ │ │ ├── README.txt │ │ │ ├── file_info.txt │ │ │ └── glbl.v │ │ ├── riviera │ │ │ ├── README.txt │ │ │ ├── file_info.txt │ │ │ └── glbl.v │ │ ├── vcs │ │ │ ├── README.txt │ │ │ ├── file_info.txt │ │ │ └── glbl.v │ │ └── xsim │ │ │ ├── README.txt │ │ │ ├── cmd.tcl │ │ │ ├── file_info.txt │ │ │ ├── glbl.v │ │ │ ├── vhdl.prj │ │ │ └── vlog.prj │ │ └── clk_wiz_0 │ │ ├── README.txt │ │ ├── activehdl │ │ ├── README.txt │ │ ├── file_info.txt │ │ └── glbl.v │ │ ├── ies │ │ ├── README.txt │ │ ├── file_info.txt │ │ └── glbl.v │ │ ├── modelsim │ │ ├── README.txt │ │ ├── file_info.txt │ │ └── glbl.v │ │ ├── questa │ │ ├── README.txt │ │ ├── file_info.txt │ │ └── glbl.v │ │ ├── riviera │ │ ├── README.txt │ │ ├── file_info.txt │ │ └── glbl.v │ │ ├── vcs │ │ ├── README.txt │ │ ├── file_info.txt │ │ └── glbl.v │ │ └── xsim │ │ ├── README.txt │ │ ├── cmd.tcl │ │ ├── file_info.txt │ │ ├── glbl.v │ │ ├── vhdl.prj │ │ └── vlog.prj ├── project_xvga_disp.runs │ ├── .jobs │ │ ├── vrs_config_1.xml │ │ ├── vrs_config_10.xml │ │ ├── vrs_config_11.xml │ │ ├── vrs_config_12.xml │ │ ├── vrs_config_13.xml │ │ ├── vrs_config_14.xml │ │ ├── vrs_config_15.xml │ │ ├── vrs_config_16.xml │ │ ├── vrs_config_17.xml │ │ ├── vrs_config_18.xml │ │ ├── vrs_config_19.xml │ │ ├── vrs_config_2.xml │ │ ├── vrs_config_20.xml │ │ ├── vrs_config_21.xml │ │ ├── vrs_config_22.xml │ │ ├── vrs_config_23.xml │ │ ├── vrs_config_24.xml │ │ ├── vrs_config_25.xml │ │ ├── vrs_config_26.xml │ │ ├── vrs_config_3.xml │ │ ├── vrs_config_4.xml │ │ ├── vrs_config_5.xml │ │ ├── vrs_config_6.xml │ │ ├── vrs_config_7.xml │ │ ├── vrs_config_8.xml │ │ └── vrs_config_9.xml │ ├── clk_wiz_0_synth_1 │ │ ├── .Xil │ │ │ └── clk_wiz_0_propImpl.xdc │ │ ├── clk_wiz_0.dcp │ │ ├── clk_wiz_0.tcl │ │ ├── clk_wiz_0.vds │ │ ├── clk_wiz_0_utilization_synth.pb │ │ ├── clk_wiz_0_utilization_synth.rpt │ │ ├── dont_touch.xdc │ │ ├── gen_run.xml │ │ ├── htr.txt │ │ ├── vivado.jou │ │ └── vivado.pb │ ├── impl_1 │ │ ├── XADCdemo.tcl │ │ ├── XADCdemo.vdi │ │ ├── XADCdemo_clock_utilization_routed.rpt │ │ ├── XADCdemo_control_sets_placed.rpt │ │ ├── XADCdemo_drc_opted.rpt │ │ ├── XADCdemo_drc_routed.pb │ │ ├── XADCdemo_drc_routed.rpt │ │ ├── XADCdemo_io_placed.rpt │ │ ├── XADCdemo_opt.dcp │ │ ├── XADCdemo_placed.dcp │ │ ├── XADCdemo_power_routed.rpt │ │ ├── XADCdemo_power_summary_routed.pb │ │ ├── XADCdemo_route_status.pb │ │ ├── XADCdemo_route_status.rpt │ │ ├── XADCdemo_routed.dcp │ │ ├── XADCdemo_timing_summary_routed.rpt │ │ ├── XADCdemo_utilization_placed.pb │ │ ├── XADCdemo_utilization_placed.rpt │ │ ├── gen_run.xml │ │ ├── htr.txt │ │ ├── init_design.pb │ │ ├── opt_design.pb │ │ ├── place_design.pb │ │ ├── route_design.pb │ │ ├── usage_statistics_webtalk.xml │ │ ├── vivado.jou │ │ ├── vivado.pb │ │ ├── vivado_11906.backup.jou │ │ ├── vivado_32034.backup.jou │ │ └── write_bitstream.pb │ └── synth_1 │ │ ├── .Xil │ │ └── XADCdemo_propImpl.xdc │ │ ├── XADCdemo.dcp │ │ ├── XADCdemo.tcl │ │ ├── XADCdemo.vds │ │ ├── XADCdemo_utilization_synth.pb │ │ ├── XADCdemo_utilization_synth.rpt │ │ ├── dont_touch.xdc │ │ ├── gen_run.xml │ │ ├── htr.txt │ │ ├── vivado.jou │ │ └── vivado.pb ├── project_xvga_disp.srcs │ ├── constrs_1 │ │ └── imports │ │ │ └── tmp │ │ │ └── Nexys4DDR_Master.xdc │ └── sources_1 │ │ ├── imports │ │ └── hdl │ │ │ ├── DigitToSeg.v │ │ │ ├── XADCdemo.v │ │ │ ├── buffer.v │ │ │ ├── counter3bit.v │ │ │ ├── decoder3_8.v │ │ │ ├── mux4_4bus.v │ │ │ ├── segClkDevider.v │ │ │ ├── sevensegdecoder.v │ │ │ └── xvga.v │ │ ├── ip │ │ ├── blk_mem_gen_0 │ │ │ ├── blk_mem_gen_0.dcp │ │ │ ├── blk_mem_gen_0.xci │ │ │ ├── blk_mem_gen_0.xml │ │ │ ├── blk_mem_gen_0_ooc.xdc │ │ │ ├── blk_mem_gen_0_sim_netlist.v │ │ │ ├── blk_mem_gen_0_stub.v │ │ │ ├── blk_mem_gen_v8_3_3 │ │ │ │ ├── hdl │ │ │ │ │ ├── blk_mem_gen_v8_3.vhd │ │ │ │ │ └── blk_mem_gen_v8_3_vhsyn_rfs.vhd │ │ │ │ └── simulation │ │ │ │ │ └── blk_mem_gen_v8_3.v │ │ │ ├── doc │ │ │ │ └── blk_mem_gen_v8_3_changelog.txt │ │ │ ├── misc │ │ │ │ └── blk_mem_gen_v8_3.vhd │ │ │ ├── sim │ │ │ │ └── blk_mem_gen_0.v │ │ │ └── synth │ │ │ │ └── blk_mem_gen_0.vhd │ │ ├── blk_mem_gen_1 │ │ │ ├── blk_mem_gen_1.dcp │ │ │ ├── blk_mem_gen_1.xci │ │ │ ├── blk_mem_gen_1.xml │ │ │ ├── blk_mem_gen_1_ooc.xdc │ │ │ ├── blk_mem_gen_1_sim_netlist.v │ │ │ ├── blk_mem_gen_1_stub.v │ │ │ ├── blk_mem_gen_v8_3_3 │ │ │ │ ├── hdl │ │ │ │ │ ├── blk_mem_gen_v8_3.vhd │ │ │ │ │ └── blk_mem_gen_v8_3_vhsyn_rfs.vhd │ │ │ │ └── simulation │ │ │ │ │ └── blk_mem_gen_v8_3.v │ │ │ ├── doc │ │ │ │ └── blk_mem_gen_v8_3_changelog.txt │ │ │ ├── misc │ │ │ │ └── blk_mem_gen_v8_3.vhd │ │ │ ├── sim │ │ │ │ └── blk_mem_gen_1.v │ │ │ └── synth │ │ │ │ └── blk_mem_gen_1.vhd │ │ └── clk_wiz_0 │ │ │ ├── clk_wiz_0.dcp │ │ │ ├── clk_wiz_0.v │ │ │ ├── clk_wiz_0.xci │ │ │ ├── clk_wiz_0.xdc │ │ │ ├── clk_wiz_0.xml │ │ │ ├── clk_wiz_0_board.xdc │ │ │ ├── clk_wiz_0_clk_wiz.v │ │ │ ├── clk_wiz_0_ooc.xdc │ │ │ ├── clk_wiz_0_sim_netlist.v │ │ │ ├── clk_wiz_0_stub.v │ │ │ └── doc │ │ │ └── clk_wiz_v5_3_changelog.txt │ │ └── new │ │ ├── buffer_simple.v │ │ └── disp.v └── project_xvga_disp.xpr ├── project_xadc ├── proj │ ├── XADC_Demo.cache │ │ └── wt │ │ │ ├── java_command_handlers.wdf │ │ │ ├── project.wpc │ │ │ ├── synthesis.wdf │ │ │ ├── synthesis_details.wdf │ │ │ └── webtalk_pa.xml │ ├── XADC_Demo.hw │ │ ├── XADC_Demo.lpr │ │ ├── hw_1 │ │ │ └── hw.xml │ │ └── webtalk │ │ │ ├── .xsim_webtallk.info │ │ │ ├── labtool_webtalk.log │ │ │ ├── labtool_webtalk.tcl │ │ │ ├── usage_statistics_ext_labtool.html │ │ │ └── usage_statistics_ext_labtool.xml │ ├── XADC_Demo.ip_user_files │ │ ├── README.txt │ │ ├── ip │ │ │ ├── blk_mem_gen_0 │ │ │ │ ├── blk_mem_gen_0.veo │ │ │ │ ├── blk_mem_gen_0.vho │ │ │ │ ├── blk_mem_gen_0_stub.v │ │ │ │ └── blk_mem_gen_0_stub.vhdl │ │ │ ├── clk_wiz_0 │ │ │ │ ├── clk_wiz_0.vho │ │ │ │ ├── clk_wiz_0_stub.v │ │ │ │ └── clk_wiz_0_stub.vhdl │ │ │ └── xadc_wiz_0 │ │ │ │ ├── xadc_wiz_0.veo │ │ │ │ ├── xadc_wiz_0.vho │ │ │ │ ├── xadc_wiz_0_stub.v │ │ │ │ └── xadc_wiz_0_stub.vhdl │ │ ├── ipstatic │ │ │ ├── blk_mem_gen_v8_3_3 │ │ │ │ └── simulation │ │ │ │ │ └── blk_mem_gen_v8_3.v │ │ │ └── clk_wiz_v5_3_1 │ │ │ │ ├── mmcm_pll_drp_func_7s_mmcm.vh │ │ │ │ ├── mmcm_pll_drp_func_7s_pll.vh │ │ │ │ ├── mmcm_pll_drp_func_us_mmcm.vh │ │ │ │ └── mmcm_pll_drp_func_us_pll.vh │ │ ├── mem_init_files │ │ │ ├── design.txt │ │ │ └── summary.log │ │ └── sim_scripts │ │ │ ├── blk_mem_gen_0 │ │ │ ├── README.txt │ │ │ ├── activehdl │ │ │ │ ├── README.txt │ │ │ │ ├── blk_mem_gen_0.sh │ │ │ │ ├── blk_mem_gen_0.udo │ │ │ │ ├── compile.do │ │ │ │ ├── file_info.txt │ │ │ │ ├── glbl.v │ │ │ │ ├── simulate.do │ │ │ │ ├── summary.log │ │ │ │ └── wave.do │ │ │ ├── ies │ │ │ │ ├── README.txt │ │ │ │ ├── blk_mem_gen_0.sh │ │ │ │ ├── file_info.txt │ │ │ │ ├── glbl.v │ │ │ │ ├── run.f │ │ │ │ └── summary.log │ │ │ ├── modelsim │ │ │ │ ├── README.txt │ │ │ │ ├── blk_mem_gen_0.sh │ │ │ │ ├── blk_mem_gen_0.udo │ │ │ │ ├── compile.do │ │ │ │ ├── file_info.txt │ │ │ │ ├── glbl.v │ │ │ │ ├── simulate.do │ │ │ │ ├── summary.log │ │ │ │ └── wave.do │ │ │ ├── questa │ │ │ │ ├── README.txt │ │ │ │ ├── blk_mem_gen_0.sh │ │ │ │ ├── blk_mem_gen_0.udo │ │ │ │ ├── compile.do │ │ │ │ ├── elaborate.do │ │ │ │ ├── file_info.txt │ │ │ │ ├── glbl.v │ │ │ │ ├── simulate.do │ │ │ │ ├── summary.log │ │ │ │ └── wave.do │ │ │ ├── riviera │ │ │ │ ├── README.txt │ │ │ │ ├── blk_mem_gen_0.sh │ │ │ │ ├── blk_mem_gen_0.udo │ │ │ │ ├── compile.do │ │ │ │ ├── file_info.txt │ │ │ │ ├── glbl.v │ │ │ │ ├── simulate.do │ │ │ │ ├── summary.log │ │ │ │ └── wave.do │ │ │ ├── vcs │ │ │ │ ├── README.txt │ │ │ │ ├── blk_mem_gen_0.sh │ │ │ │ ├── file_info.txt │ │ │ │ ├── glbl.v │ │ │ │ ├── simulate.do │ │ │ │ └── summary.log │ │ │ └── xsim │ │ │ │ ├── README.txt │ │ │ │ ├── blk_mem_gen_0.sh │ │ │ │ ├── cmd.tcl │ │ │ │ ├── file_info.txt │ │ │ │ ├── glbl.v │ │ │ │ ├── summary.log │ │ │ │ ├── vhdl.prj │ │ │ │ ├── vlog.prj │ │ │ │ └── xsim.ini │ │ │ ├── clk_wiz_0 │ │ │ ├── README.txt │ │ │ ├── activehdl │ │ │ │ ├── README.txt │ │ │ │ ├── clk_wiz_0.sh │ │ │ │ ├── clk_wiz_0.udo │ │ │ │ ├── compile.do │ │ │ │ ├── file_info.txt │ │ │ │ ├── glbl.v │ │ │ │ ├── simulate.do │ │ │ │ └── wave.do │ │ │ ├── ies │ │ │ │ ├── README.txt │ │ │ │ ├── clk_wiz_0.sh │ │ │ │ ├── file_info.txt │ │ │ │ ├── glbl.v │ │ │ │ └── run.f │ │ │ ├── modelsim │ │ │ │ ├── README.txt │ │ │ │ ├── clk_wiz_0.sh │ │ │ │ ├── clk_wiz_0.udo │ │ │ │ ├── compile.do │ │ │ │ ├── file_info.txt │ │ │ │ ├── glbl.v │ │ │ │ ├── simulate.do │ │ │ │ └── wave.do │ │ │ ├── questa │ │ │ │ ├── README.txt │ │ │ │ ├── clk_wiz_0.sh │ │ │ │ ├── clk_wiz_0.udo │ │ │ │ ├── compile.do │ │ │ │ ├── elaborate.do │ │ │ │ ├── file_info.txt │ │ │ │ ├── glbl.v │ │ │ │ ├── simulate.do │ │ │ │ └── wave.do │ │ │ ├── riviera │ │ │ │ ├── README.txt │ │ │ │ ├── clk_wiz_0.sh │ │ │ │ ├── clk_wiz_0.udo │ │ │ │ ├── compile.do │ │ │ │ ├── file_info.txt │ │ │ │ ├── glbl.v │ │ │ │ ├── simulate.do │ │ │ │ └── wave.do │ │ │ ├── vcs │ │ │ │ ├── README.txt │ │ │ │ ├── clk_wiz_0.sh │ │ │ │ ├── file_info.txt │ │ │ │ ├── glbl.v │ │ │ │ └── simulate.do │ │ │ └── xsim │ │ │ │ ├── README.txt │ │ │ │ ├── clk_wiz_0.sh │ │ │ │ ├── cmd.tcl │ │ │ │ ├── file_info.txt │ │ │ │ ├── glbl.v │ │ │ │ ├── vhdl.prj │ │ │ │ ├── vlog.prj │ │ │ │ └── xsim.ini │ │ │ └── xadc_wiz_0 │ │ │ ├── README.txt │ │ │ ├── activehdl │ │ │ ├── README.txt │ │ │ ├── compile.do │ │ │ ├── design.txt │ │ │ ├── file_info.txt │ │ │ ├── simulate.do │ │ │ ├── wave.do │ │ │ ├── xadc_wiz_0.sh │ │ │ └── xadc_wiz_0.udo │ │ │ ├── ies │ │ │ ├── README.txt │ │ │ ├── design.txt │ │ │ ├── file_info.txt │ │ │ ├── run.f │ │ │ └── xadc_wiz_0.sh │ │ │ ├── modelsim │ │ │ ├── README.txt │ │ │ ├── compile.do │ │ │ ├── design.txt │ │ │ ├── file_info.txt │ │ │ ├── simulate.do │ │ │ ├── wave.do │ │ │ ├── xadc_wiz_0.sh │ │ │ └── xadc_wiz_0.udo │ │ │ ├── questa │ │ │ ├── README.txt │ │ │ ├── compile.do │ │ │ ├── design.txt │ │ │ ├── elaborate.do │ │ │ ├── file_info.txt │ │ │ ├── simulate.do │ │ │ ├── wave.do │ │ │ ├── xadc_wiz_0.sh │ │ │ └── xadc_wiz_0.udo │ │ │ ├── riviera │ │ │ ├── README.txt │ │ │ ├── compile.do │ │ │ ├── design.txt │ │ │ ├── file_info.txt │ │ │ ├── simulate.do │ │ │ ├── wave.do │ │ │ ├── xadc_wiz_0.sh │ │ │ └── xadc_wiz_0.udo │ │ │ ├── vcs │ │ │ ├── README.txt │ │ │ ├── design.txt │ │ │ ├── file_info.txt │ │ │ ├── simulate.do │ │ │ └── xadc_wiz_0.sh │ │ │ └── xsim │ │ │ ├── README.txt │ │ │ ├── cmd.tcl │ │ │ ├── design.txt │ │ │ ├── file_info.txt │ │ │ ├── vhdl.prj │ │ │ ├── xadc_wiz_0.sh │ │ │ └── xsim.ini │ ├── XADC_Demo.runs │ │ ├── .jobs │ │ │ ├── vrs_config_1.xml │ │ │ ├── vrs_config_10.xml │ │ │ ├── vrs_config_11.xml │ │ │ ├── vrs_config_12.xml │ │ │ ├── vrs_config_13.xml │ │ │ ├── vrs_config_14.xml │ │ │ ├── vrs_config_2.xml │ │ │ ├── vrs_config_3.xml │ │ │ ├── vrs_config_4.xml │ │ │ ├── vrs_config_5.xml │ │ │ ├── vrs_config_6.xml │ │ │ ├── vrs_config_7.xml │ │ │ ├── vrs_config_8.xml │ │ │ └── vrs_config_9.xml │ │ ├── blk_mem_gen_0_synth_1 │ │ │ ├── .Vivado_Synthesis.queue.rst │ │ │ ├── .vivado.begin.rst │ │ │ ├── .vivado.end.rst │ │ │ ├── ISEWrap.js │ │ │ ├── ISEWrap.sh │ │ │ ├── blk_mem_gen_0.dcp │ │ │ ├── blk_mem_gen_0.tcl │ │ │ ├── blk_mem_gen_0.vds │ │ │ ├── blk_mem_gen_0_utilization_synth.pb │ │ │ ├── blk_mem_gen_0_utilization_synth.rpt │ │ │ ├── dont_touch.xdc │ │ │ ├── gen_run.xml │ │ │ ├── htr.txt │ │ │ ├── project.wdf │ │ │ ├── rundef.js │ │ │ ├── runme.bat │ │ │ ├── runme.log │ │ │ ├── runme.sh │ │ │ ├── vivado.jou │ │ │ └── vivado.pb │ │ ├── clk_wiz_0_synth_1 │ │ │ ├── .Vivado_Synthesis.queue.rst │ │ │ ├── .Xil │ │ │ │ └── clk_wiz_0_propImpl.xdc │ │ │ ├── .vivado.begin.rst │ │ │ ├── .vivado.end.rst │ │ │ ├── ISEWrap.js │ │ │ ├── ISEWrap.sh │ │ │ ├── clk_wiz_0.dcp │ │ │ ├── clk_wiz_0.tcl │ │ │ ├── clk_wiz_0.vds │ │ │ ├── clk_wiz_0_utilization_synth.pb │ │ │ ├── clk_wiz_0_utilization_synth.rpt │ │ │ ├── dont_touch.xdc │ │ │ ├── gen_run.xml │ │ │ ├── htr.txt │ │ │ ├── project.wdf │ │ │ ├── rundef.js │ │ │ ├── runme.bat │ │ │ ├── runme.log │ │ │ ├── runme.sh │ │ │ ├── vivado.jou │ │ │ └── vivado.pb │ │ ├── impl_1 │ │ │ ├── XADCdemo_2362.backup.vdi │ │ │ └── vivado_2362.backup.jou │ │ ├── synth_1 │ │ │ ├── .Vivado_Synthesis.queue.rst │ │ │ ├── .Xil │ │ │ │ └── XADCdemo_propImpl.xdc │ │ │ ├── .vivado.begin.rst │ │ │ ├── .vivado.end.rst │ │ │ ├── ISEWrap.js │ │ │ ├── ISEWrap.sh │ │ │ ├── XADCdemo.dcp │ │ │ ├── XADCdemo.tcl │ │ │ ├── XADCdemo.vds │ │ │ ├── XADCdemo_utilization_synth.pb │ │ │ ├── XADCdemo_utilization_synth.rpt │ │ │ ├── gen_run.xml │ │ │ ├── htr.txt │ │ │ ├── project.wdf │ │ │ ├── rundef.js │ │ │ ├── runme.bat │ │ │ ├── runme.log │ │ │ ├── runme.sh │ │ │ ├── vivado.jou │ │ │ └── vivado.pb │ │ └── xadc_wiz_0_synth_1 │ │ │ ├── .Vivado_Synthesis.queue.rst │ │ │ ├── .vivado.begin.rst │ │ │ ├── .vivado.end.rst │ │ │ ├── ISEWrap.js │ │ │ ├── ISEWrap.sh │ │ │ ├── dont_touch.xdc │ │ │ ├── gen_run.xml │ │ │ ├── htr.txt │ │ │ ├── project.wdf │ │ │ ├── rundef.js │ │ │ ├── runme.bat │ │ │ ├── runme.log │ │ │ ├── runme.sh │ │ │ ├── vivado.jou │ │ │ ├── vivado.pb │ │ │ ├── xadc_wiz_0.dcp │ │ │ ├── xadc_wiz_0.tcl │ │ │ ├── xadc_wiz_0.vds │ │ │ ├── xadc_wiz_0_utilization_synth.pb │ │ │ └── xadc_wiz_0_utilization_synth.rpt │ ├── XADC_Demo.srcs │ │ └── sources_1 │ │ │ ├── ip │ │ │ ├── blk_mem_gen_0 │ │ │ │ ├── .Xil │ │ │ │ │ └── Vivado-32338-eecs-digital-22 │ │ │ │ │ │ └── ss32338.287432800.log │ │ │ │ ├── blk_mem_gen_0.dcp │ │ │ │ ├── blk_mem_gen_0.veo │ │ │ │ ├── blk_mem_gen_0.vho │ │ │ │ ├── blk_mem_gen_0.xci │ │ │ │ ├── blk_mem_gen_0.xml │ │ │ │ ├── blk_mem_gen_0_ooc.xdc │ │ │ │ ├── blk_mem_gen_0_sim_netlist.v │ │ │ │ ├── blk_mem_gen_0_sim_netlist.vhdl │ │ │ │ ├── blk_mem_gen_0_stub.v │ │ │ │ ├── blk_mem_gen_0_stub.vhdl │ │ │ │ ├── blk_mem_gen_v8_3_3 │ │ │ │ │ ├── hdl │ │ │ │ │ │ ├── blk_mem_gen_v8_3.vhd │ │ │ │ │ │ └── blk_mem_gen_v8_3_vhsyn_rfs.vhd │ │ │ │ │ └── simulation │ │ │ │ │ │ └── blk_mem_gen_v8_3.v │ │ │ │ ├── doc │ │ │ │ │ └── blk_mem_gen_v8_3_changelog.txt │ │ │ │ ├── misc │ │ │ │ │ └── blk_mem_gen_v8_3.vhd │ │ │ │ ├── sim │ │ │ │ │ └── blk_mem_gen_0.v │ │ │ │ ├── summary.log │ │ │ │ └── synth │ │ │ │ │ └── blk_mem_gen_0.vhd │ │ │ └── clk_wiz_0 │ │ │ │ ├── clk_wiz_0.dcp │ │ │ │ ├── clk_wiz_0.v │ │ │ │ ├── clk_wiz_0.vho │ │ │ │ ├── clk_wiz_0.xci │ │ │ │ ├── clk_wiz_0.xdc │ │ │ │ ├── clk_wiz_0.xml │ │ │ │ ├── clk_wiz_0_board.xdc │ │ │ │ ├── clk_wiz_0_clk_wiz.v │ │ │ │ ├── clk_wiz_0_ooc.xdc │ │ │ │ ├── clk_wiz_0_sim_netlist.v │ │ │ │ ├── clk_wiz_0_sim_netlist.vhdl │ │ │ │ ├── clk_wiz_0_stub.v │ │ │ │ ├── clk_wiz_0_stub.vhdl │ │ │ │ ├── clk_wiz_v5_3_1 │ │ │ │ ├── mmcm_pll_drp_func_7s_mmcm.vh │ │ │ │ ├── mmcm_pll_drp_func_7s_pll.vh │ │ │ │ ├── mmcm_pll_drp_func_us_mmcm.vh │ │ │ │ └── mmcm_pll_drp_func_us_pll.vh │ │ │ │ └── doc │ │ │ │ └── clk_wiz_v5_3_changelog.txt │ │ │ └── new │ │ │ └── ADCController.v │ ├── XADC_Demo.xpr │ ├── _READ_ME_.txt │ ├── cleanup.cmd │ ├── cleanup.sh │ ├── create_project.tcl │ └── ip_upgrade.log └── src │ ├── constraints │ └── Nexys4DDR_Master.xdc │ ├── hdl │ ├── DigitToSeg.v │ ├── UART_TX_CTRL.vhd │ ├── XADCdemo.v │ ├── buffer.v │ ├── counter3bit.v │ ├── decoder3_8.v │ ├── mux4_4bus.v │ ├── segClkDevider.v │ ├── sevensegdecoder.v │ └── xvga.v │ └── ip │ └── xadc_wiz_0 │ ├── design.txt │ ├── doc │ └── xadc_wiz_v3_3_changelog.txt │ ├── xadc_wiz_0.dcp │ ├── xadc_wiz_0.upgrade_log │ ├── xadc_wiz_0.veo │ ├── xadc_wiz_0.vhd │ ├── xadc_wiz_0.vho │ ├── xadc_wiz_0.xci │ ├── xadc_wiz_0.xdc │ ├── xadc_wiz_0.xml │ ├── xadc_wiz_0 │ └── simulation │ │ └── timing │ │ └── design.txt │ ├── xadc_wiz_0_ooc.xdc │ ├── xadc_wiz_0_sim_netlist.v │ ├── xadc_wiz_0_sim_netlist.vhdl │ ├── xadc_wiz_0_stub.v │ └── xadc_wiz_0_stub.vhdl ├── project_xvga_disp ├── project_xvga_disp.cache │ └── wt │ │ ├── java_command_handlers.wdf │ │ ├── project.wpc │ │ ├── synthesis.wdf │ │ ├── synthesis_details.wdf │ │ └── webtalk_pa.xml ├── project_xvga_disp.hw │ ├── hw_1 │ │ └── hw.xml │ ├── project_xvga_disp.lpr │ └── webtalk │ │ ├── .xsim_webtallk.info │ │ ├── labtool_webtalk.log │ │ ├── labtool_webtalk.tcl │ │ ├── usage_statistics_ext_labtool.html │ │ ├── usage_statistics_ext_labtool.wdm │ │ └── usage_statistics_ext_labtool.xml ├── project_xvga_disp.ip_user_files │ ├── README.txt │ ├── ip │ │ └── clk_wiz_0 │ │ │ ├── clk_wiz_0.veo │ │ │ ├── clk_wiz_0_stub.v │ │ │ └── clk_wiz_0_stub.vhdl │ ├── ipstatic │ │ └── clk_wiz_v5_3_1 │ │ │ ├── mmcm_pll_drp_func_7s_mmcm.vh │ │ │ ├── mmcm_pll_drp_func_7s_pll.vh │ │ │ ├── mmcm_pll_drp_func_us_mmcm.vh │ │ │ └── mmcm_pll_drp_func_us_pll.vh │ └── sim_scripts │ │ └── clk_wiz_0 │ │ ├── README.txt │ │ ├── activehdl │ │ ├── README.txt │ │ ├── clk_wiz_0.sh │ │ ├── clk_wiz_0.udo │ │ ├── compile.do │ │ ├── file_info.txt │ │ ├── glbl.v │ │ ├── simulate.do │ │ └── wave.do │ │ ├── ies │ │ ├── README.txt │ │ ├── clk_wiz_0.sh │ │ ├── file_info.txt │ │ ├── glbl.v │ │ └── run.f │ │ ├── modelsim │ │ ├── README.txt │ │ ├── clk_wiz_0.sh │ │ ├── clk_wiz_0.udo │ │ ├── compile.do │ │ ├── file_info.txt │ │ ├── glbl.v │ │ ├── simulate.do │ │ └── wave.do │ │ ├── questa │ │ ├── README.txt │ │ ├── clk_wiz_0.sh │ │ ├── clk_wiz_0.udo │ │ ├── compile.do │ │ ├── elaborate.do │ │ ├── file_info.txt │ │ ├── glbl.v │ │ ├── simulate.do │ │ └── wave.do │ │ ├── riviera │ │ ├── README.txt │ │ ├── clk_wiz_0.sh │ │ ├── clk_wiz_0.udo │ │ ├── compile.do │ │ ├── file_info.txt │ │ ├── glbl.v │ │ ├── simulate.do │ │ └── wave.do │ │ ├── vcs │ │ ├── README.txt │ │ ├── clk_wiz_0.sh │ │ ├── file_info.txt │ │ ├── glbl.v │ │ └── simulate.do │ │ └── xsim │ │ ├── README.txt │ │ ├── clk_wiz_0.sh │ │ ├── cmd.tcl │ │ ├── file_info.txt │ │ ├── glbl.v │ │ ├── vhdl.prj │ │ ├── vlog.prj │ │ └── xsim.ini ├── project_xvga_disp.runs │ ├── .jobs │ │ ├── vrs_config_1.xml │ │ ├── vrs_config_2.xml │ │ ├── vrs_config_3.xml │ │ ├── vrs_config_4.xml │ │ ├── vrs_config_5.xml │ │ └── vrs_config_6.xml │ ├── clk_wiz_0_synth_1 │ │ ├── .Vivado_Synthesis.queue.rst │ │ ├── .Xil │ │ │ └── clk_wiz_0_propImpl.xdc │ │ ├── .vivado.begin.rst │ │ ├── .vivado.end.rst │ │ ├── ISEWrap.js │ │ ├── ISEWrap.sh │ │ ├── clk_wiz_0.dcp │ │ ├── clk_wiz_0.tcl │ │ ├── clk_wiz_0.vds │ │ ├── clk_wiz_0_utilization_synth.pb │ │ ├── clk_wiz_0_utilization_synth.rpt │ │ ├── dont_touch.xdc │ │ ├── gen_run.xml │ │ ├── htr.txt │ │ ├── project.wdf │ │ ├── rundef.js │ │ ├── runme.bat │ │ ├── runme.log │ │ ├── runme.sh │ │ ├── vivado.jou │ │ └── vivado.pb │ ├── impl_1 │ │ ├── .Vivado_Implementation.queue.rst │ │ ├── .init_design.begin.rst │ │ ├── .init_design.end.rst │ │ ├── .opt_design.begin.rst │ │ ├── .opt_design.end.rst │ │ ├── .place_design.begin.rst │ │ ├── .place_design.end.rst │ │ ├── .route_design.begin.rst │ │ ├── .route_design.end.rst │ │ ├── .vivado.begin.rst │ │ ├── .vivado.end.rst │ │ ├── .write_bitstream.begin.rst │ │ ├── .write_bitstream.end.rst │ │ ├── ISEWrap.js │ │ ├── ISEWrap.sh │ │ ├── XADCdemo.bit │ │ ├── XADCdemo.tcl │ │ ├── XADCdemo.vdi │ │ ├── XADCdemo_clock_utilization_routed.rpt │ │ ├── XADCdemo_control_sets_placed.rpt │ │ ├── XADCdemo_drc_opted.rpt │ │ ├── XADCdemo_drc_routed.pb │ │ ├── XADCdemo_drc_routed.rpt │ │ ├── XADCdemo_io_placed.rpt │ │ ├── XADCdemo_opt.dcp │ │ ├── XADCdemo_placed.dcp │ │ ├── XADCdemo_power_routed.rpt │ │ ├── XADCdemo_power_routed.rpx │ │ ├── XADCdemo_power_summary_routed.pb │ │ ├── XADCdemo_route_status.pb │ │ ├── XADCdemo_route_status.rpt │ │ ├── XADCdemo_routed.dcp │ │ ├── XADCdemo_timing_summary_routed.rpt │ │ ├── XADCdemo_timing_summary_routed.rpx │ │ ├── XADCdemo_utilization_placed.pb │ │ ├── XADCdemo_utilization_placed.rpt │ │ ├── gen_run.xml │ │ ├── htr.txt │ │ ├── init_design.pb │ │ ├── opt_design.pb │ │ ├── place_design.pb │ │ ├── project.wdf │ │ ├── route_design.pb │ │ ├── rundef.js │ │ ├── runme.bat │ │ ├── runme.log │ │ ├── runme.sh │ │ ├── usage_statistics_webtalk.html │ │ ├── usage_statistics_webtalk.xml │ │ ├── vivado.jou │ │ ├── vivado.pb │ │ └── write_bitstream.pb │ └── synth_1 │ │ ├── .Vivado_Synthesis.queue.rst │ │ ├── .Xil │ │ └── XADCdemo_propImpl.xdc │ │ ├── .vivado.begin.rst │ │ ├── .vivado.end.rst │ │ ├── ISEWrap.js │ │ ├── ISEWrap.sh │ │ ├── XADCdemo.dcp │ │ ├── XADCdemo.tcl │ │ ├── XADCdemo.vds │ │ ├── XADCdemo_utilization_synth.pb │ │ ├── XADCdemo_utilization_synth.rpt │ │ ├── gen_run.xml │ │ ├── htr.txt │ │ ├── rundef.js │ │ ├── runme.bat │ │ ├── runme.log │ │ ├── runme.sh │ │ ├── vivado.jou │ │ └── vivado.pb ├── project_xvga_disp.srcs │ ├── constrs_1 │ │ └── imports │ │ │ └── tmp │ │ │ └── Nexys4DDR_Master.xdc │ └── sources_1 │ │ ├── imports │ │ └── hdl │ │ │ ├── XADCdemo.v │ │ │ └── xvga.v │ │ ├── ip │ │ └── clk_wiz_0 │ │ │ ├── clk_wiz_0.dcp │ │ │ ├── clk_wiz_0.v │ │ │ ├── clk_wiz_0.veo │ │ │ ├── clk_wiz_0.xci │ │ │ ├── clk_wiz_0.xdc │ │ │ ├── clk_wiz_0.xml │ │ │ ├── clk_wiz_0_board.xdc │ │ │ ├── clk_wiz_0_clk_wiz.v │ │ │ ├── clk_wiz_0_ooc.xdc │ │ │ ├── clk_wiz_0_sim_netlist.v │ │ │ ├── clk_wiz_0_sim_netlist.vhdl │ │ │ ├── clk_wiz_0_stub.v │ │ │ ├── clk_wiz_0_stub.vhdl │ │ │ ├── clk_wiz_v5_3_1 │ │ │ ├── mmcm_pll_drp_func_7s_mmcm.vh │ │ │ ├── mmcm_pll_drp_func_7s_pll.vh │ │ │ ├── mmcm_pll_drp_func_us_mmcm.vh │ │ │ └── mmcm_pll_drp_func_us_pll.vh │ │ │ └── doc │ │ │ └── clk_wiz_v5_3_changelog.txt │ │ └── new │ │ └── disp.v └── project_xvga_disp.xpr ├── vivado.jou ├── vivado.log └── vivado_14858.backup.jou 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