├── DOC ├── 802.3-2015 │ ├── 802.3-2015_SECTION1.pdf │ ├── 802.3-2015_SECTION2.pdf │ ├── 802.3-2015_SECTION3.pdf │ ├── 802.3-2015_SECTION4.pdf │ ├── 802.3-2015_SECTION5.pdf │ └── 802.3-2015_SECTION6.pdf └── 传输测试结果 │ ├── UDP解决最后一byte.png │ └── UDP调试传输通过.png ├── git地址.txt ├── proj ├── db │ ├── altsyncram_cr14.tdf │ ├── altsyncram_er14.tdf │ ├── cmpr_ngc.tdf │ ├── cmpr_pgc.tdf │ ├── cmpr_rgc.tdf │ ├── cntr_23j.tdf │ ├── cntr_hgi.tdf │ ├── cntr_l6j.tdf │ ├── cntr_sei.tdf │ ├── cntr_tei.tdf │ ├── decode_dvf.tdf │ ├── eth.(0).cnf.cdb │ ├── eth.(0).cnf.hdb │ ├── eth.(1).cnf.cdb │ ├── eth.(1).cnf.hdb │ ├── eth.(10).cnf.cdb │ ├── eth.(10).cnf.hdb │ ├── eth.(100).cnf.cdb │ ├── eth.(100).cnf.hdb │ ├── eth.(101).cnf.cdb │ ├── eth.(101).cnf.hdb │ ├── eth.(102).cnf.cdb │ ├── eth.(102).cnf.hdb │ ├── eth.(103).cnf.cdb │ ├── eth.(103).cnf.hdb │ ├── eth.(104).cnf.cdb │ ├── eth.(104).cnf.hdb │ ├── eth.(105).cnf.cdb │ ├── eth.(105).cnf.hdb │ ├── eth.(106).cnf.cdb │ ├── eth.(106).cnf.hdb │ ├── eth.(107).cnf.cdb │ ├── eth.(107).cnf.hdb │ ├── eth.(108).cnf.cdb │ ├── eth.(108).cnf.hdb │ ├── eth.(109).cnf.cdb │ ├── eth.(109).cnf.hdb │ ├── eth.(11).cnf.cdb │ ├── eth.(11).cnf.hdb │ ├── eth.(110).cnf.cdb │ ├── eth.(110).cnf.hdb │ ├── eth.(111).cnf.cdb │ ├── eth.(111).cnf.hdb │ ├── eth.(112).cnf.cdb │ ├── eth.(112).cnf.hdb │ ├── eth.(113).cnf.cdb │ ├── eth.(113).cnf.hdb │ ├── eth.(114).cnf.cdb │ ├── eth.(114).cnf.hdb │ ├── eth.(115).cnf.cdb │ ├── eth.(115).cnf.hdb │ ├── eth.(116).cnf.cdb │ ├── eth.(116).cnf.hdb │ ├── eth.(117).cnf.cdb │ ├── eth.(117).cnf.hdb │ ├── eth.(118).cnf.cdb │ ├── eth.(118).cnf.hdb │ ├── eth.(119).cnf.cdb │ ├── eth.(119).cnf.hdb │ ├── eth.(12).cnf.cdb │ ├── eth.(12).cnf.hdb │ ├── eth.(120).cnf.cdb │ ├── eth.(120).cnf.hdb │ ├── eth.(121).cnf.cdb │ ├── eth.(121).cnf.hdb │ ├── eth.(122).cnf.cdb │ ├── eth.(122).cnf.hdb │ ├── eth.(123).cnf.cdb │ ├── eth.(123).cnf.hdb │ ├── eth.(124).cnf.cdb │ ├── eth.(124).cnf.hdb │ ├── eth.(125).cnf.cdb │ ├── eth.(125).cnf.hdb │ ├── eth.(126).cnf.cdb │ ├── eth.(126).cnf.hdb │ ├── eth.(127).cnf.cdb │ ├── eth.(127).cnf.hdb │ ├── eth.(128).cnf.cdb │ ├── eth.(128).cnf.hdb │ ├── eth.(129).cnf.cdb │ ├── eth.(129).cnf.hdb │ ├── eth.(13).cnf.cdb │ ├── eth.(13).cnf.hdb │ ├── eth.(130).cnf.cdb │ ├── eth.(130).cnf.hdb │ ├── eth.(131).cnf.cdb │ ├── eth.(131).cnf.hdb │ ├── eth.(132).cnf.cdb │ ├── eth.(132).cnf.hdb │ ├── eth.(133).cnf.cdb │ ├── eth.(133).cnf.hdb │ ├── eth.(134).cnf.cdb │ ├── eth.(134).cnf.hdb │ ├── eth.(135).cnf.cdb │ ├── eth.(135).cnf.hdb │ ├── eth.(136).cnf.cdb │ ├── eth.(136).cnf.hdb │ ├── eth.(137).cnf.cdb │ ├── eth.(137).cnf.hdb │ ├── eth.(138).cnf.cdb │ ├── eth.(138).cnf.hdb │ ├── eth.(139).cnf.cdb │ ├── eth.(139).cnf.hdb │ ├── eth.(14).cnf.cdb │ ├── eth.(14).cnf.hdb │ ├── eth.(140).cnf.cdb │ ├── eth.(140).cnf.hdb │ ├── eth.(141).cnf.cdb │ ├── eth.(141).cnf.hdb │ ├── eth.(142).cnf.cdb │ ├── eth.(142).cnf.hdb │ ├── eth.(143).cnf.cdb │ ├── eth.(143).cnf.hdb │ ├── eth.(144).cnf.cdb │ ├── eth.(144).cnf.hdb │ ├── eth.(145).cnf.cdb │ ├── eth.(145).cnf.hdb │ ├── eth.(146).cnf.cdb │ ├── eth.(146).cnf.hdb │ ├── eth.(147).cnf.cdb │ ├── eth.(147).cnf.hdb │ ├── eth.(148).cnf.cdb │ ├── eth.(148).cnf.hdb │ ├── eth.(149).cnf.cdb │ ├── eth.(149).cnf.hdb │ ├── eth.(15).cnf.cdb │ ├── eth.(15).cnf.hdb │ ├── eth.(150).cnf.cdb │ ├── eth.(150).cnf.hdb │ ├── eth.(151).cnf.cdb │ ├── eth.(151).cnf.hdb │ ├── eth.(152).cnf.cdb │ ├── eth.(152).cnf.hdb │ ├── eth.(153).cnf.cdb │ ├── eth.(153).cnf.hdb │ ├── eth.(154).cnf.cdb │ ├── eth.(154).cnf.hdb │ ├── eth.(155).cnf.cdb │ ├── eth.(155).cnf.hdb │ ├── eth.(156).cnf.cdb │ ├── eth.(156).cnf.hdb │ ├── eth.(157).cnf.cdb │ ├── eth.(157).cnf.hdb │ ├── eth.(158).cnf.cdb │ ├── eth.(158).cnf.hdb │ ├── eth.(159).cnf.cdb │ ├── eth.(159).cnf.hdb │ ├── eth.(16).cnf.cdb │ ├── eth.(16).cnf.hdb │ ├── eth.(160).cnf.cdb │ ├── eth.(160).cnf.hdb │ ├── eth.(161).cnf.cdb │ ├── eth.(161).cnf.hdb │ ├── eth.(162).cnf.cdb │ ├── eth.(162).cnf.hdb │ ├── eth.(163).cnf.cdb │ ├── eth.(163).cnf.hdb │ ├── eth.(164).cnf.cdb │ ├── eth.(164).cnf.hdb │ ├── eth.(165).cnf.cdb │ ├── eth.(165).cnf.hdb │ ├── eth.(166).cnf.cdb │ ├── eth.(166).cnf.hdb │ ├── eth.(167).cnf.cdb │ ├── eth.(167).cnf.hdb │ ├── eth.(17).cnf.cdb │ ├── eth.(17).cnf.hdb │ ├── eth.(18).cnf.cdb │ ├── eth.(18).cnf.hdb │ ├── eth.(19).cnf.cdb │ ├── eth.(19).cnf.hdb │ ├── eth.(2).cnf.cdb │ ├── eth.(2).cnf.hdb │ ├── eth.(20).cnf.cdb │ ├── eth.(20).cnf.hdb │ ├── eth.(21).cnf.cdb │ ├── eth.(21).cnf.hdb │ ├── eth.(22).cnf.cdb │ ├── eth.(22).cnf.hdb │ ├── eth.(23).cnf.cdb │ ├── eth.(23).cnf.hdb │ ├── eth.(24).cnf.cdb │ ├── eth.(24).cnf.hdb │ ├── eth.(25).cnf.cdb │ ├── eth.(25).cnf.hdb │ ├── eth.(26).cnf.cdb │ ├── eth.(26).cnf.hdb │ ├── eth.(27).cnf.cdb │ ├── eth.(27).cnf.hdb │ ├── eth.(28).cnf.cdb │ ├── eth.(28).cnf.hdb │ ├── eth.(29).cnf.cdb │ ├── eth.(29).cnf.hdb │ ├── eth.(3).cnf.cdb │ ├── eth.(3).cnf.hdb │ ├── eth.(30).cnf.cdb │ ├── eth.(30).cnf.hdb │ ├── eth.(31).cnf.cdb │ ├── eth.(31).cnf.hdb │ ├── eth.(32).cnf.cdb │ ├── eth.(32).cnf.hdb │ ├── eth.(33).cnf.cdb │ ├── eth.(33).cnf.hdb │ ├── eth.(34).cnf.cdb │ ├── eth.(34).cnf.hdb │ ├── eth.(35).cnf.cdb │ ├── eth.(35).cnf.hdb │ ├── eth.(36).cnf.cdb │ ├── eth.(36).cnf.hdb │ ├── eth.(37).cnf.cdb │ ├── eth.(37).cnf.hdb │ ├── eth.(38).cnf.cdb │ ├── eth.(38).cnf.hdb │ ├── eth.(39).cnf.cdb │ ├── eth.(39).cnf.hdb │ ├── eth.(4).cnf.cdb │ ├── eth.(4).cnf.hdb │ ├── eth.(40).cnf.cdb │ ├── eth.(40).cnf.hdb │ ├── eth.(41).cnf.cdb │ ├── eth.(41).cnf.hdb │ ├── eth.(42).cnf.cdb │ ├── eth.(42).cnf.hdb │ ├── eth.(43).cnf.cdb │ ├── eth.(43).cnf.hdb │ ├── eth.(44).cnf.cdb │ ├── eth.(44).cnf.hdb │ ├── eth.(45).cnf.cdb │ ├── eth.(45).cnf.hdb │ ├── eth.(46).cnf.cdb │ ├── eth.(46).cnf.hdb │ ├── eth.(47).cnf.cdb │ ├── eth.(47).cnf.hdb │ ├── eth.(48).cnf.cdb │ ├── eth.(48).cnf.hdb │ ├── eth.(49).cnf.cdb │ ├── eth.(49).cnf.hdb │ ├── eth.(5).cnf.cdb │ ├── eth.(5).cnf.hdb │ ├── eth.(50).cnf.cdb │ ├── eth.(50).cnf.hdb │ ├── eth.(51).cnf.cdb │ ├── eth.(51).cnf.hdb │ ├── eth.(52).cnf.cdb │ ├── eth.(52).cnf.hdb │ ├── eth.(53).cnf.cdb │ ├── eth.(53).cnf.hdb │ ├── eth.(54).cnf.cdb │ ├── eth.(54).cnf.hdb │ ├── eth.(55).cnf.cdb │ ├── eth.(55).cnf.hdb │ ├── eth.(56).cnf.cdb │ ├── eth.(56).cnf.hdb │ ├── eth.(57).cnf.cdb │ ├── eth.(57).cnf.hdb │ ├── eth.(58).cnf.cdb │ ├── eth.(58).cnf.hdb │ ├── eth.(59).cnf.cdb │ ├── eth.(59).cnf.hdb │ ├── eth.(6).cnf.cdb │ ├── eth.(6).cnf.hdb │ ├── eth.(60).cnf.cdb │ ├── eth.(60).cnf.hdb │ ├── eth.(61).cnf.cdb │ ├── eth.(61).cnf.hdb │ ├── eth.(62).cnf.cdb │ ├── eth.(62).cnf.hdb │ ├── eth.(63).cnf.cdb │ ├── eth.(63).cnf.hdb │ ├── eth.(64).cnf.cdb │ ├── eth.(64).cnf.hdb │ ├── eth.(65).cnf.cdb │ ├── eth.(65).cnf.hdb │ ├── eth.(66).cnf.cdb │ ├── eth.(66).cnf.hdb │ ├── eth.(67).cnf.cdb │ ├── eth.(67).cnf.hdb │ ├── eth.(68).cnf.cdb │ ├── eth.(68).cnf.hdb │ ├── eth.(69).cnf.cdb │ ├── eth.(69).cnf.hdb │ ├── eth.(7).cnf.cdb │ ├── eth.(7).cnf.hdb │ ├── eth.(70).cnf.cdb │ ├── eth.(70).cnf.hdb │ ├── eth.(71).cnf.cdb │ ├── eth.(71).cnf.hdb │ ├── eth.(72).cnf.cdb │ ├── eth.(72).cnf.hdb │ ├── eth.(73).cnf.cdb │ ├── eth.(73).cnf.hdb │ ├── eth.(74).cnf.cdb │ ├── eth.(74).cnf.hdb │ ├── eth.(75).cnf.cdb │ ├── eth.(75).cnf.hdb │ ├── eth.(76).cnf.cdb │ ├── eth.(76).cnf.hdb │ ├── eth.(77).cnf.cdb │ ├── eth.(77).cnf.hdb │ ├── eth.(78).cnf.cdb │ ├── eth.(78).cnf.hdb │ ├── eth.(79).cnf.cdb │ ├── eth.(79).cnf.hdb │ ├── eth.(8).cnf.cdb │ ├── eth.(8).cnf.hdb │ ├── eth.(80).cnf.cdb │ ├── eth.(80).cnf.hdb │ ├── eth.(81).cnf.cdb │ ├── eth.(81).cnf.hdb │ ├── eth.(82).cnf.cdb │ ├── eth.(82).cnf.hdb │ ├── eth.(83).cnf.cdb │ ├── eth.(83).cnf.hdb │ ├── eth.(84).cnf.cdb │ ├── eth.(84).cnf.hdb │ ├── eth.(85).cnf.cdb │ ├── eth.(85).cnf.hdb │ ├── eth.(86).cnf.cdb │ ├── eth.(86).cnf.hdb │ ├── eth.(87).cnf.cdb │ ├── eth.(87).cnf.hdb │ ├── eth.(88).cnf.cdb │ ├── eth.(88).cnf.hdb │ ├── eth.(89).cnf.cdb │ ├── eth.(89).cnf.hdb │ ├── eth.(9).cnf.cdb │ ├── eth.(9).cnf.hdb │ ├── eth.(90).cnf.cdb │ ├── eth.(90).cnf.hdb │ ├── eth.(91).cnf.cdb │ ├── eth.(91).cnf.hdb │ ├── eth.(92).cnf.cdb │ ├── eth.(92).cnf.hdb │ ├── eth.(93).cnf.cdb │ ├── eth.(93).cnf.hdb │ ├── eth.(94).cnf.cdb │ ├── eth.(94).cnf.hdb │ ├── eth.(95).cnf.cdb │ ├── eth.(95).cnf.hdb │ ├── eth.(96).cnf.cdb │ ├── eth.(96).cnf.hdb │ ├── eth.(97).cnf.cdb │ ├── eth.(97).cnf.hdb │ ├── eth.(98).cnf.cdb │ ├── eth.(98).cnf.hdb │ ├── eth.(99).cnf.cdb │ ├── eth.(99).cnf.hdb │ ├── eth.0.cmp.rdb │ ├── eth.1.cmp.rdb │ ├── eth.2.cmp.rdb │ ├── eth.asm.qmsg │ ├── eth.asm.rdb │ ├── eth.asm_labs.ddb │ ├── eth.autoh_e40e1.map.reg_db.cdb │ ├── eth.autoh_e40e1.qmsg │ ├── eth.autos_3e921.map.reg_db.cdb │ ├── eth.autos_3e921.qmsg │ ├── eth.cbx.xml │ ├── eth.cmp.bpm │ ├── eth.cmp.cdb │ ├── eth.cmp.hdb │ ├── eth.cmp.idb │ ├── eth.cmp.kpt │ ├── eth.cmp.logdb │ ├── eth.cmp.rdb │ ├── eth.cmp_merge.kpt │ ├── eth.cycloneive_io_sim_cache.45um_ff_1200mv_0c_fast.hsd │ ├── eth.cycloneive_io_sim_cache.45um_ss_1200mv_0c_slow.hsd │ ├── eth.cycloneive_io_sim_cache.45um_ss_1200mv_85c_slow.hsd │ ├── eth.db_info │ ├── eth.eda.qmsg │ ├── eth.fit.qmsg │ ├── eth.hier_info │ ├── eth.hif │ ├── eth.ipinfo │ ├── eth.lpc.html │ ├── eth.lpc.rdb │ ├── eth.lpc.txt │ ├── eth.main.hdb │ ├── eth.map.ammdb │ ├── eth.map.bpm │ ├── eth.map.cdb │ ├── eth.map.hdb │ ├── eth.map.kpt │ ├── eth.map.logdb │ ├── eth.map.qmsg │ ├── eth.map.rcfdb │ ├── eth.map.rdb │ ├── eth.map_bb.cdb │ ├── eth.map_bb.hdb │ ├── eth.map_bb.logdb │ ├── eth.merge.qmsg │ ├── eth.pplq.rdb │ ├── eth.pre_map.hdb │ ├── eth.pti_db_list.ddb │ ├── eth.root_partition.map.reg_db.cdb │ ├── eth.root_partition.qmsg │ ├── eth.routing.rdb │ ├── eth.rtlv.hdb │ ├── eth.rtlv_sg.cdb │ ├── eth.rtlv_sg_swap.cdb │ ├── eth.sgdiff.cdb │ ├── eth.sgdiff.hdb │ ├── eth.sld_design_entry.sci │ ├── eth.sld_design_entry_dsc.sci │ ├── eth.smart_action.txt │ ├── eth.sta.qmsg │ ├── eth.sta.rdb │ ├── eth.sta_cmp.8_slow_1200mv_85c.tdb │ ├── eth.syn_hier_info │ ├── eth.tis_db_list.ddb │ ├── eth.tiscmp.fast_1200mv_0c.ddb │ ├── eth.tiscmp.fastest_slow_1200mv_0c.ddb │ ├── eth.tiscmp.fastest_slow_1200mv_85c.ddb │ ├── eth.tiscmp.slow_1200mv_0c.ddb │ ├── eth.tiscmp.slow_1200mv_85c.ddb │ ├── eth.vpr.ammdb │ ├── logic_util_heursitic.dat │ ├── mux_usc.tdf │ └── prev_cmp_eth.qmsg ├── eth.qpf ├── eth.qsf ├── eth.qsf.bak ├── eth.qws ├── eth.sdc ├── eth_nativelink_simulation.rpt ├── incremental_db │ ├── README │ └── compiled_partitions │ │ ├── eth.autoh_e40e1.map.cdb │ │ ├── eth.autoh_e40e1.map.dpi │ │ ├── eth.autoh_e40e1.map.hdb │ │ ├── eth.autoh_e40e1.map.kpt │ │ ├── eth.autoh_e40e1.map.logdb │ │ ├── eth.autos_3e921.map.cdb │ │ ├── eth.autos_3e921.map.dpi │ │ ├── eth.autos_3e921.map.hdb │ │ ├── eth.autos_3e921.map.kpt │ │ ├── eth.autos_3e921.map.logdb │ │ ├── eth.db_info │ │ ├── eth.root_partition.cmp.ammdb │ │ ├── eth.root_partition.cmp.cdb │ │ ├── eth.root_partition.cmp.dfp │ │ ├── eth.root_partition.cmp.hdb │ │ ├── eth.root_partition.cmp.kpt │ │ ├── eth.root_partition.cmp.logdb │ │ ├── eth.root_partition.cmp.rcfdb │ │ ├── eth.root_partition.map.cdb │ │ ├── eth.root_partition.map.dpi │ │ ├── eth.root_partition.map.hbdb.cdb │ │ ├── eth.root_partition.map.hbdb.hb_info │ │ ├── eth.root_partition.map.hbdb.hdb │ │ ├── eth.root_partition.map.hbdb.sig │ │ ├── eth.root_partition.map.hdb │ │ └── eth.root_partition.map.kpt ├── ip_proto_test.v.bak ├── output_files │ ├── eth.asm.rpt │ ├── eth.cdf │ ├── eth.done │ ├── eth.eda.rpt │ ├── eth.fit.rpt │ ├── eth.fit.smsg │ ├── eth.fit.summary │ ├── eth.flow.rpt │ ├── eth.jdi │ ├── eth.map.rpt │ ├── eth.map.smsg │ ├── eth.map.summary │ ├── eth.merge.rpt │ ├── eth.merge.summary │ ├── eth.pin │ ├── eth.sof │ ├── eth.sta.rpt │ ├── eth.sta.summary │ ├── stp1.stp │ └── stp1_auto_stripped.stp └── simulation │ └── modelsim │ ├── eth.sft │ ├── eth.vo │ ├── eth_8_1200mv_0c_slow.vo │ ├── eth_8_1200mv_0c_v_slow.sdo │ ├── eth_8_1200mv_85c_slow.vo │ ├── eth_8_1200mv_85c_v_slow.sdo │ ├── eth_min_1200mv_0c_fast.vo │ ├── eth_min_1200mv_0c_v_fast.sdo │ ├── eth_modelsim.xrf │ ├── eth_run_msim_gate_verilog.do │ ├── eth_run_msim_rtl_verilog.do │ ├── eth_run_msim_rtl_verilog.do.bak │ ├── eth_run_msim_rtl_verilog.do.bak1 │ ├── eth_run_msim_rtl_verilog.do.bak2 │ ├── eth_run_msim_rtl_verilog.do.bak3 │ ├── eth_run_msim_rtl_verilog.do.bak4 │ ├── eth_run_msim_rtl_verilog.do.bak5 │ ├── eth_run_msim_rtl_verilog.do.bak6 │ ├── eth_run_msim_rtl_verilog.do.bak7 │ ├── eth_run_msim_rtl_verilog.do.bak8 │ ├── eth_v.sdo │ ├── gate_work │ ├── _info │ ├── _vmake │ ├── check_sum │ │ ├── _primary.dat │ │ ├── _primary.dbs │ │ ├── _primary.vhd │ │ ├── verilog.prw │ │ └── verilog.psm │ └── check_sum_tb │ │ ├── _primary.dat │ │ ├── _primary.dbs │ │ ├── _primary.vhd │ │ ├── verilog.prw │ │ └── verilog.psm │ ├── modelsim.ini │ ├── msim_transcript │ ├── rtl_work │ ├── _info │ ├── _vmake │ ├── check_sum │ │ ├── _primary.dat │ │ ├── _primary.dbs │ │ ├── _primary.vhd │ │ ├── verilog.prw │ │ └── verilog.psm │ ├── crc32_d4 │ │ ├── _primary.dat │ │ ├── _primary.dbs │ │ ├── _primary.vhd │ │ ├── verilog.prw │ │ └── verilog.psm │ ├── eth │ │ ├── _primary.dat │ │ ├── _primary.dbs │ │ ├── _primary.vhd │ │ ├── verilog.prw │ │ └── verilog.psm │ ├── eth_mac │ │ ├── _primary.dat │ │ ├── _primary.dbs │ │ ├── _primary.vhd │ │ ├── verilog.prw │ │ └── verilog.psm │ ├── ip_proto_test │ │ ├── _primary.dat │ │ ├── _primary.dbs │ │ ├── _primary.vhd │ │ ├── verilog.prw │ │ └── verilog.psm │ ├── ip_protocol │ │ ├── _primary.dat │ │ ├── _primary.dbs │ │ ├── _primary.vhd │ │ ├── verilog.prw │ │ └── verilog.psm │ ├── udp_proto_test │ │ ├── _primary.dat │ │ ├── _primary.dbs │ │ ├── _primary.vhd │ │ ├── verilog.prw │ │ └── verilog.psm │ ├── udp_proto_test_tb │ │ ├── _primary.dat │ │ ├── _primary.dbs │ │ ├── _primary.vhd │ │ ├── verilog.prw │ │ └── verilog.psm │ └── udp_protocol │ │ ├── _primary.dat │ │ ├── _primary.dbs │ │ ├── _primary.vhd │ │ ├── verilog.prw │ │ └── verilog.psm │ └── vsim.wlf ├── rtl ├── PIN_LOC_100METH.txt ├── check_sum.v ├── check_sum.v.bak ├── crc32_d4.v ├── eth.v ├── eth.v.bak ├── eth_mac.v ├── eth_mac.v.bak ├── ip_proto_test.v ├── ip_proto_test.v.bak ├── ip_protocol.v ├── ip_protocol.v.bak ├── udp_proto_test.v ├── udp_proto_test.v.bak ├── udp_protocol.v └── udp_protocol.v.bak ├── tb ├── check_sum_tb.v ├── check_sum_tb.v.bak ├── eth_mac_tb.v ├── eth_mac_tb.v.bak ├── eth_tb.v ├── eth_tb.v.bak ├── ip_proto_test_tb.v ├── ip_proto_test_tb.v.bak ├── ip_protocol_tb.v ├── ip_protocol_tb.v.bak ├── udp_proto_test_tb.v └── udp_proto_test_tb.v.bak └── tool ├── CRC_Calc+v0.1.exe ├── arp_pak_192.168.137.1.txt ├── pkt_cap_while_snd.pcap ├── profile.ini ├── udp.txt ├── udp——192.168.137.1.txt └── xb_ether_tester.exe /DOC/802.3-2015/802.3-2015_SECTION1.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/DeamonYang/FPGA_100M_ETH/1caa878e38527286618d0852fc647df305cdd282/DOC/802.3-2015/802.3-2015_SECTION1.pdf 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-------------------------------------------------------------------------------- https://raw.githubusercontent.com/DeamonYang/FPGA_100M_ETH/1caa878e38527286618d0852fc647df305cdd282/DOC/传输测试结果/UDP解决最后一byte.png -------------------------------------------------------------------------------- /DOC/传输测试结果/UDP调试传输通过.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/DeamonYang/FPGA_100M_ETH/1caa878e38527286618d0852fc647df305cdd282/DOC/传输测试结果/UDP调试传输通过.png -------------------------------------------------------------------------------- /git地址.txt: -------------------------------------------------------------------------------- 1 | https://github.com/DeamonYang/FPGA_100M_ETH.git -------------------------------------------------------------------------------- /proj/db/cmpr_ngc.tdf: -------------------------------------------------------------------------------- 1 | --lpm_compare CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone IV E" LPM_WIDTH=1 ONE_INPUT_IS_CONSTANT="YES" aeb dataa datab 2 | --VERSION_BEGIN 13.0 cbx_cycloneii 2013:04:24:18:08:47:SJ cbx_lpm_add_sub 2013:04:24:18:08:47:SJ cbx_lpm_compare 2013:04:24:18:08:47:SJ cbx_mgl 2013:04:24:18:11:10:SJ cbx_stratix 2013:04:24:18:08:47:SJ cbx_stratixii 2013:04:24:18:08:47:SJ VERSION_END 3 | 4 | 5 | -- Copyright (C) 1991-2013 Altera Corporation 6 | -- Your use of Altera Corporation's design tools, logic functions 7 | -- and other software and tools, and its AMPP partner logic 8 | -- functions, and any output files from any of the foregoing 9 | -- (including device programming or simulation files), and any 10 | -- associated documentation or information are expressly subject 11 | -- to the terms and conditions of the Altera Program License 12 | -- Subscription Agreement, Altera MegaCore Function License 13 | -- Agreement, or other applicable license agreement, including, 14 | -- without limitation, that your use is for the sole purpose of 15 | -- programming logic devices manufactured by Altera and sold by 16 | -- Altera or its authorized distributors. Please refer to the 17 | -- applicable agreement for further details. 18 | 19 | 20 | 21 | --synthesis_resources = 22 | SUBDESIGN cmpr_ngc 23 | ( 24 | aeb : output; 25 | dataa[0..0] : input; 26 | datab[0..0] : input; 27 | ) 28 | VARIABLE 29 | aeb_result_wire[0..0] : WIRE; 30 | aneb_result_wire[0..0] : WIRE; 31 | data_wire[1..0] : WIRE; 32 | eq_wire : WIRE; 33 | 34 | BEGIN 35 | aeb = eq_wire; 36 | aeb_result_wire[] = (! aneb_result_wire[]); 37 | aneb_result_wire[] = (data_wire[0..0] $ data_wire[1..1]); 38 | data_wire[] = ( datab[0..0], dataa[0..0]); 39 | eq_wire = aeb_result_wire[]; 40 | END; 41 | --VALID FILE 42 | -------------------------------------------------------------------------------- /proj/db/cmpr_pgc.tdf: -------------------------------------------------------------------------------- 1 | --lpm_compare CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone IV E" LPM_WIDTH=3 ONE_INPUT_IS_CONSTANT="YES" aeb dataa datab 2 | --VERSION_BEGIN 13.0 cbx_cycloneii 2013:04:24:18:08:47:SJ cbx_lpm_add_sub 2013:04:24:18:08:47:SJ cbx_lpm_compare 2013:04:24:18:08:47:SJ cbx_mgl 2013:04:24:18:11:10:SJ cbx_stratix 2013:04:24:18:08:47:SJ cbx_stratixii 2013:04:24:18:08:47:SJ VERSION_END 3 | 4 | 5 | -- Copyright (C) 1991-2013 Altera Corporation 6 | -- Your use of Altera Corporation's design tools, logic functions 7 | -- and other software and tools, and its AMPP partner logic 8 | -- functions, and any output files from any of the foregoing 9 | -- (including device programming or simulation files), and any 10 | -- associated documentation or information are expressly subject 11 | -- to the terms and conditions of the Altera Program License 12 | -- Subscription Agreement, Altera MegaCore Function License 13 | -- Agreement, or other applicable license agreement, including, 14 | -- without limitation, that your use is for the sole purpose of 15 | -- programming logic devices manufactured by Altera and sold by 16 | -- Altera or its authorized distributors. Please refer to the 17 | -- applicable agreement for further details. 18 | 19 | 20 | 21 | --synthesis_resources = 22 | SUBDESIGN cmpr_pgc 23 | ( 24 | aeb : output; 25 | dataa[2..0] : input; 26 | datab[2..0] : input; 27 | ) 28 | VARIABLE 29 | aeb_result_wire[0..0] : WIRE; 30 | aneb_result_wire[0..0] : WIRE; 31 | data_wire[7..0] : WIRE; 32 | eq_wire : WIRE; 33 | 34 | BEGIN 35 | aeb = eq_wire; 36 | aeb_result_wire[] = (! aneb_result_wire[]); 37 | aneb_result_wire[] = (data_wire[0..0] # data_wire[1..1]); 38 | data_wire[] = ( datab[2..2], dataa[2..2], datab[1..1], dataa[1..1], datab[0..0], dataa[0..0], (data_wire[6..6] $ data_wire[7..7]), ((data_wire[2..2] $ data_wire[3..3]) # (data_wire[4..4] $ data_wire[5..5]))); 39 | eq_wire = aeb_result_wire[]; 40 | END; 41 | --VALID FILE 42 | -------------------------------------------------------------------------------- /proj/db/cmpr_rgc.tdf: -------------------------------------------------------------------------------- 1 | --lpm_compare CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone IV E" LPM_WIDTH=5 ONE_INPUT_IS_CONSTANT="YES" aeb dataa datab 2 | --VERSION_BEGIN 13.0 cbx_cycloneii 2013:04:24:18:08:47:SJ cbx_lpm_add_sub 2013:04:24:18:08:47:SJ cbx_lpm_compare 2013:04:24:18:08:47:SJ cbx_mgl 2013:04:24:18:11:10:SJ cbx_stratix 2013:04:24:18:08:47:SJ cbx_stratixii 2013:04:24:18:08:47:SJ VERSION_END 3 | 4 | 5 | -- Copyright (C) 1991-2013 Altera Corporation 6 | -- Your use of Altera Corporation's design tools, logic functions 7 | -- and other software and tools, and its AMPP partner logic 8 | -- functions, and any output files from any of the foregoing 9 | -- (including device programming or simulation files), and any 10 | -- associated documentation or information are expressly subject 11 | -- to the terms and conditions of the Altera Program License 12 | -- Subscription Agreement, Altera MegaCore Function License 13 | -- Agreement, or other applicable license agreement, including, 14 | -- without limitation, that your use is for the sole purpose of 15 | -- programming logic devices manufactured by Altera and sold by 16 | -- Altera or its authorized distributors. Please refer to the 17 | -- applicable agreement for further details. 18 | 19 | 20 | 21 | --synthesis_resources = 22 | SUBDESIGN cmpr_rgc 23 | ( 24 | aeb : output; 25 | dataa[4..0] : input; 26 | datab[4..0] : input; 27 | ) 28 | VARIABLE 29 | aeb_result_wire[0..0] : WIRE; 30 | aneb_result_wire[0..0] : WIRE; 31 | data_wire[12..0] : WIRE; 32 | eq_wire : WIRE; 33 | 34 | BEGIN 35 | aeb = eq_wire; 36 | aeb_result_wire[] = (! aneb_result_wire[]); 37 | aneb_result_wire[] = ((data_wire[0..0] # data_wire[1..1]) # data_wire[2..2]); 38 | data_wire[] = ( datab[4..4], dataa[4..4], datab[3..3], dataa[3..3], datab[2..2], dataa[2..2], datab[1..1], dataa[1..1], datab[0..0], dataa[0..0], (data_wire[11..11] $ data_wire[12..12]), ((data_wire[7..7] $ data_wire[8..8]) # (data_wire[9..9] $ data_wire[10..10])), ((data_wire[3..3] $ data_wire[4..4]) # (data_wire[5..5] $ data_wire[6..6]))); 39 | eq_wire = aeb_result_wire[]; 40 | END; 41 | --VALID FILE 42 | -------------------------------------------------------------------------------- /proj/db/decode_dvf.tdf: -------------------------------------------------------------------------------- 1 | --lpm_decode CASCADE_CHAIN="MANUAL" DEVICE_FAMILY="Cyclone IV E" IGNORE_CASCADE_BUFFERS="OFF" LPM_DECODES=2 LPM_WIDTH=1 data enable eq CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 2 | --VERSION_BEGIN 13.0 cbx_cycloneii 2013:04:24:18:08:47:SJ cbx_lpm_add_sub 2013:04:24:18:08:47:SJ cbx_lpm_compare 2013:04:24:18:08:47:SJ cbx_lpm_decode 2013:04:24:18:08:47:SJ cbx_mgl 2013:04:24:18:11:10:SJ cbx_stratix 2013:04:24:18:08:47:SJ cbx_stratixii 2013:04:24:18:08:47:SJ VERSION_END 3 | 4 | 5 | -- Copyright (C) 1991-2013 Altera Corporation 6 | -- Your use of Altera Corporation's design tools, logic functions 7 | -- and other software and tools, and its AMPP partner logic 8 | -- functions, and any output files from any of the foregoing 9 | -- (including device programming or simulation files), and any 10 | -- associated documentation or information are expressly subject 11 | -- to the terms and conditions of the Altera Program License 12 | -- Subscription Agreement, Altera MegaCore Function License 13 | -- Agreement, or other applicable license agreement, including, 14 | -- without limitation, that your use is for the sole purpose of 15 | -- programming logic devices manufactured by Altera and sold by 16 | -- Altera or its authorized distributors. Please refer to the 17 | -- applicable agreement for further details. 18 | 19 | 20 | 21 | --synthesis_resources = lut 1 22 | SUBDESIGN decode_dvf 23 | ( 24 | data[0..0] : input; 25 | enable : input; 26 | eq[1..0] : output; 27 | ) 28 | VARIABLE 29 | eq_node[1..0] : WIRE; 30 | 31 | BEGIN 32 | eq[] = eq_node[]; 33 | eq_node[] = ( (data[] & enable), ((! data[]) & enable)); 34 | END; 35 | --VALID FILE 36 | -------------------------------------------------------------------------------- /proj/db/eth.(0).cnf.cdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/DeamonYang/FPGA_100M_ETH/1caa878e38527286618d0852fc647df305cdd282/proj/db/eth.(0).cnf.cdb -------------------------------------------------------------------------------- /proj/db/eth.(0).cnf.hdb: -------------------------------------------------------------------------------- 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device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1550914389399 ""} 6 | { "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 64-Bit " "Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4576 " "Peak virtual memory: 4576 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1550914389619 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat Feb 23 17:33:09 2019 " "Processing ended: Sat Feb 23 17:33:09 2019" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1550914389619 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1550914389619 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1550914389619 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1550914389619 ""} 7 | -------------------------------------------------------------------------------- /proj/db/eth.asm.rdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/DeamonYang/FPGA_100M_ETH/1caa878e38527286618d0852fc647df305cdd282/proj/db/eth.asm.rdb -------------------------------------------------------------------------------- /proj/db/eth.asm_labs.ddb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/DeamonYang/FPGA_100M_ETH/1caa878e38527286618d0852fc647df305cdd282/proj/db/eth.asm_labs.ddb -------------------------------------------------------------------------------- /proj/db/eth.autoh_e40e1.map.reg_db.cdb: -------------------------------------------------------------------------------- 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https://raw.githubusercontent.com/DeamonYang/FPGA_100M_ETH/1caa878e38527286618d0852fc647df305cdd282/proj/db/eth.ipinfo -------------------------------------------------------------------------------- /proj/db/eth.lpc.html: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 | 39 | 40 | 41 | 42 | 43 | 44 | 45 | 46 | 47 | 48 | 49 | 50 | 51 | 52 | 53 | 54 | 55 | 56 | 57 | 58 | 59 | 60 | 61 | 62 | 63 | 64 | 65 | 66 | 67 | 68 | 69 | 70 | 71 | 72 | 73 | 74 | 75 | 76 | 77 | 78 | 79 | 80 | 81 | 82 | 83 | 84 | 85 | 86 | 87 | 88 | 89 | 90 | 91 | 92 | 93 | 94 | 95 | 96 | 97 | 98 |
HierarchyInputConstant InputUnused InputFloating InputOutputConstant OutputUnused OutputFloating OutputBidirConstant BidirUnused BidirInput only BidirOutput only Bidir
udp_protocol_u0|ip_protocol_u3|cksum_u7144640641664646400000
udp_protocol_u0|ip_protocol_u3|eth_mac_u01631140114811411411400000
udp_protocol_u0|ip_protocol_u3|crc_u180003200000000
udp_protocol_u0|ip_protocol_u320101711100000
udp_protocol_u07164064864646400000
99 | -------------------------------------------------------------------------------- /proj/db/eth.lpc.rdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/DeamonYang/FPGA_100M_ETH/1caa878e38527286618d0852fc647df305cdd282/proj/db/eth.lpc.rdb -------------------------------------------------------------------------------- /proj/db/eth.lpc.txt: -------------------------------------------------------------------------------- 1 | +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ 2 | ; Legal Partition Candidates ; 3 | +-------------------------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ 4 | ; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ; 5 | +-------------------------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ 6 | ; udp_protocol_u0|ip_protocol_u3|cksum_u7 ; 144 ; 64 ; 0 ; 64 ; 16 ; 64 ; 64 ; 64 ; 0 ; 0 ; 0 ; 0 ; 0 ; 7 | ; udp_protocol_u0|ip_protocol_u3|eth_mac_u0 ; 163 ; 114 ; 0 ; 114 ; 8 ; 114 ; 114 ; 114 ; 0 ; 0 ; 0 ; 0 ; 0 ; 8 | ; udp_protocol_u0|ip_protocol_u3|crc_u1 ; 8 ; 0 ; 0 ; 0 ; 32 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 9 | ; udp_protocol_u0|ip_protocol_u3 ; 20 ; 1 ; 0 ; 1 ; 7 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 10 | ; udp_protocol_u0 ; 71 ; 64 ; 0 ; 64 ; 8 ; 64 ; 64 ; 64 ; 0 ; 0 ; 0 ; 0 ; 0 ; 11 | +-------------------------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ 12 | -------------------------------------------------------------------------------- /proj/db/eth.main.hdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/DeamonYang/FPGA_100M_ETH/1caa878e38527286618d0852fc647df305cdd282/proj/db/eth.main.hdb -------------------------------------------------------------------------------- /proj/db/eth.map.ammdb: -------------------------------------------------------------------------------- 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2 | { "Info" "IMLS_MLS_PRESET_POWER_UP" "" "Registers with preset signals will power-up high" { } { { "../rtl/crc32_d4.v" "" { Text "L:/FPWG_WORK/FPGA_100ETH/rtl/crc32_d4.v" 61 -1 0 } } } 0 13000 "Registers with preset signals will power-up high" 0 0 "Quartus II" 0 0 1550914377904 ""} 3 | { "Info" "IMLS_MLS_DEV_CLRN_SETS_REGISTERS" "" "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" { } { } 0 13003 "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" 0 0 "Quartus II" 0 0 1550914377904 ""} 4 | { "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "mii_tx_er GND " "Pin \"mii_tx_er\" is stuck at GND" { } { { "../rtl/udp_proto_test.v" "" { Text "L:/FPWG_WORK/FPGA_100ETH/rtl/udp_proto_test.v" 23 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 0 1550914378124 "|udp_proto_test|mii_tx_er"} { "Warning" "WMLS_MLS_STUCK_PIN" "phy_rst_n VCC " "Pin \"phy_rst_n\" is stuck at VCC" { } { { "../rtl/udp_proto_test.v" "" { Text "L:/FPWG_WORK/FPGA_100ETH/rtl/udp_proto_test.v" 25 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 0 1550914378124 "|udp_proto_test|phy_rst_n"} } { } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Quartus II" 0 0 1550914378124 ""} 5 | { "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING_ON_PARTITION" "Top " "Timing-Driven Synthesis is running on partition \"Top\"" { } { } 0 286031 "Timing-Driven Synthesis is running on partition \"%1!s!\"" 0 0 "Quartus II" 0 0 1550914378236 ""} 6 | { "Info" "ICUT_CUT_TM_SUMMARY" "374 " "Implemented 374 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "9 " "Implemented 9 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 0 1550914378701 ""} { "Info" "ICUT_CUT_TM_OPINS" "7 " "Implemented 7 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 0 1550914378701 ""} { "Info" "ICUT_CUT_TM_LCELLS" "358 " "Implemented 358 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 0 1550914378701 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 0 1550914378701 ""} 7 | { "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 3 s Quartus II 64-Bit " "Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4601 " "Peak virtual memory: 4601 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 0 1550914378752 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat Feb 23 17:32:58 2019 " "Processing ended: Sat Feb 23 17:32:58 2019" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 0 1550914378752 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 0 1550914378752 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Total CPU time (on all processors): 00:00:03" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 0 1550914378752 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 0 1550914378752 ""} 8 | -------------------------------------------------------------------------------- /proj/db/eth.routing.rdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/DeamonYang/FPGA_100M_ETH/1caa878e38527286618d0852fc647df305cdd282/proj/db/eth.routing.rdb -------------------------------------------------------------------------------- /proj/db/eth.rtlv.hdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/DeamonYang/FPGA_100M_ETH/1caa878e38527286618d0852fc647df305cdd282/proj/db/eth.rtlv.hdb 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-------------------------------------------------------------------------------- /proj/eth.qpf: -------------------------------------------------------------------------------- 1 | # -------------------------------------------------------------------------- # 2 | # 3 | # Copyright (C) 1991-2013 Altera Corporation 4 | # Your use of Altera Corporation's design tools, logic functions 5 | # and other software and tools, and its AMPP partner logic 6 | # functions, and any output files from any of the foregoing 7 | # (including device programming or simulation files), and any 8 | # associated documentation or information are expressly subject 9 | # to the terms and conditions of the Altera Program License 10 | # Subscription Agreement, Altera MegaCore Function License 11 | # Agreement, or other applicable license agreement, including, 12 | # without limitation, that your use is for the sole purpose of 13 | # programming logic devices manufactured by Altera and sold by 14 | # Altera or its authorized distributors. Please refer to the 15 | # applicable agreement for further details. 16 | # 17 | # -------------------------------------------------------------------------- # 18 | # 19 | # Quartus II 64-Bit 20 | # Version 13.0.0 Build 156 04/24/2013 SJ Full Version 21 | # Date created = 20:34:25 February 21, 2019 22 | # 23 | # -------------------------------------------------------------------------- # 24 | 25 | QUARTUS_VERSION = "13.0" 26 | DATE = "20:34:25 February 21, 2019" 27 | 28 | # Revisions 29 | 30 | PROJECT_REVISION = "eth" 31 | -------------------------------------------------------------------------------- /proj/eth.qws: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/DeamonYang/FPGA_100M_ETH/1caa878e38527286618d0852fc647df305cdd282/proj/eth.qws -------------------------------------------------------------------------------- /proj/eth.sdc: -------------------------------------------------------------------------------- 1 | #************************************************************ 2 | # THIS IS A WIZARD-GENERATED FILE. 3 | # 4 | # Version 13.0.0 Build 156 04/24/2013 SJ Full Version 5 | # 6 | #************************************************************ 7 | 8 | # Copyright (C) 1991-2013 Altera Corporation 9 | # Your use of Altera Corporation's design tools, logic functions 10 | # and other software and tools, and its AMPP partner logic 11 | # functions, and any output files from any of the foregoing 12 | # (including device programming or simulation files), and any 13 | # associated documentation or information are expressly subject 14 | # to the terms and conditions of the Altera Program License 15 | # Subscription Agreement, Altera MegaCore Function License 16 | # Agreement, or other applicable license agreement, including, 17 | # without limitation, that your use is for the sole purpose of 18 | # programming logic devices manufactured by Altera and sold by 19 | # Altera or its authorized distributors. Please refer to the 20 | # applicable agreement for further details. 21 | 22 | 23 | 24 | # Clock constraints 25 | 26 | create_clock -name "mii_tx_clk" -period 40.000ns [get_ports {mii_tx_clk}] 27 | 28 | 29 | # Automatically constrain PLL and other generated clocks 30 | derive_pll_clocks -create_base_clocks 31 | 32 | # Automatically calculate clock uncertainty to jitter and other effects. 33 | derive_clock_uncertainty 34 | 35 | # tsu/th constraints 36 | 37 | # tco constraints 38 | 39 | # tpd constraints 40 | 41 | -------------------------------------------------------------------------------- /proj/eth_nativelink_simulation.rpt: -------------------------------------------------------------------------------- 1 | Info: Start Nativelink Simulation process 2 | Info: NativeLink has detected Verilog design -- Verilog simulation models will be used 3 | 4 | ========= EDA Simulation Settings ===================== 5 | 6 | Sim Mode : RTL 7 | Family : cycloneive 8 | Quartus root : d:/major_soft/soft/quartus13/quartus/bin64/ 9 | Quartus sim root : d:/major_soft/soft/quartus13/quartus/eda/sim_lib 10 | Simulation Tool : modelsim-altera 11 | Simulation Language : verilog 12 | Simulation Mode : GUI 13 | Sim Output File : 14 | Sim SDF file : 15 | Sim dir : simulation\modelsim 16 | 17 | ======================================================= 18 | 19 | Info: Starting NativeLink simulation with ModelSim-Altera software 20 | Sourced NativeLink script d:/major_soft/soft/quartus13/quartus/common/tcl/internal/nativelink/modelsim.tcl 21 | Warning: File eth_run_msim_rtl_verilog.do already exists - backing up current file as eth_run_msim_rtl_verilog.do.bak8 22 | Info: Spawning ModelSim-Altera Simulation software 23 | -------------------------------------------------------------------------------- /proj/incremental_db/README: -------------------------------------------------------------------------------- 1 | This folder contains data for incremental compilation. 2 | 3 | The compiled_partitions sub-folder contains previous compilation results for each partition. 4 | As long as this folder is preserved, incremental compilation results from earlier compiles 5 | can be re-used. To perform a clean compilation from source files for all partitions, both 6 | the db and incremental_db folder should be removed. 7 | 8 | The imported_partitions sub-folder contains the last imported QXP for each imported partition. 9 | As long as this folder is preserved, imported partitions will be automatically re-imported 10 | when the db or incremental_db/compiled_partitions folders are removed. 11 | 12 | -------------------------------------------------------------------------------- /proj/incremental_db/compiled_partitions/eth.autoh_e40e1.map.cdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/DeamonYang/FPGA_100M_ETH/1caa878e38527286618d0852fc647df305cdd282/proj/incremental_db/compiled_partitions/eth.autoh_e40e1.map.cdb -------------------------------------------------------------------------------- /proj/incremental_db/compiled_partitions/eth.autoh_e40e1.map.dpi: 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/proj/ip_proto_test.v.bak: -------------------------------------------------------------------------------- 1 | module ip_proto_test( 2 | rst_n , 3 | 4 | mii_tx_clk , 5 | mii_tx_en , 6 | mii_tx_er , 7 | mii_tx_da , 8 | 9 | mii_rx_clk , 10 | mii_rx_dv , 11 | mii_rx_er , 12 | mii_rx_da , 13 | 14 | phy_rst_n 15 | ); 16 | 17 | 18 | input rst_n; 19 | 20 | //MII 接口信号 21 | input mii_tx_clk; //MII接口发送时钟，由PHY芯片产生，25MHz 22 | output mii_tx_en; //MII接口发送数据使能信号，高电平有效 23 | output mii_tx_er; //发送错误，用以破坏数据包发送 24 | output [3:0]mii_tx_da; //MII接口发送数据线，FPGA通过该数据线将需要发送的数据依次送给PHY芯片 25 | output phy_rst_n; // PHY 复位信号 26 | 27 | input mii_rx_clk; //MII接口接收时钟，由PHY芯片产生，25MHz 28 | input mii_rx_dv; //MII接口接收数据有效信号，高电平有效 29 | input mii_rx_er; //接收错误，本实例中暂时忽略该信号 30 | input [3:0]mii_rx_da; //MII接口数据总线，FPGA通过该数据线读取PHY芯片接收到的以太网数据 31 | 32 | 33 | assign phy_rst_n = 1'b1; 34 | 35 | reg [10:0]data_cnt; 36 | wire [31:0]crc_result; 37 | parameter CRC = 32'hB1E85F40; //整个数据包CRC校验值，本例中使用CRC计算软件计算得出。 38 | 39 | assign crc_result = {CRC[7:0],CRC[15:8],CRC[23:16],CRC[31:24]}; 40 | 41 | wire fifo_ck; 42 | wire fifo_rq; 43 | reg[3:0] fifo_da; 44 | 45 | wire[3:0]crc_res; 46 | wire crc_en; 47 | 48 | ip_protocol ui( 49 | .rst_n (rst_n), 50 | .tx_go (tx_go) , 51 | .data_len (12'd20) , 52 | 53 | .fifo_rq (fifo_rq ), 54 | .fifo_ck (fifo_ck ), 55 | .fifo_da (fifo_da ), 56 | 57 | 58 | .mii_tx_clk (mii_tx_clk ), 59 | .mii_tx_en (mii_tx_en ), 60 | .mii_tx_er (mii_tx_er ), 61 | .mii_tx_da (mii_tx_da ) 62 | 63 | ); 64 | 65 | 66 | 67 | 68 | 69 | endmodule 70 | -------------------------------------------------------------------------------- /proj/output_files/eth.cdf: -------------------------------------------------------------------------------- 1 | /* Quartus II 64-Bit Version 13.0.0 Build 156 04/24/2013 SJ Full Version */ 2 | JedecChain; 3 | FileRevision(JESD32A); 4 | DefaultMfr(6E); 5 | 6 | P ActionCode(Cfg) 7 | Device PartName(EP4CE10F17) Path("L:/FPWG_WORK/FPGA_100ETH/proj/output_files/") File("eth.sof") MfrSpec(OpMask(1)); 8 | 9 | ChainEnd; 10 | 11 | AlteraBegin; 12 | ChainType(JTAG); 13 | AlteraEnd; 14 | -------------------------------------------------------------------------------- /proj/output_files/eth.done: -------------------------------------------------------------------------------- 1 | Sat Feb 23 17:33:16 2019 2 | -------------------------------------------------------------------------------- /proj/output_files/eth.fit.rpt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/DeamonYang/FPGA_100M_ETH/1caa878e38527286618d0852fc647df305cdd282/proj/output_files/eth.fit.rpt -------------------------------------------------------------------------------- /proj/output_files/eth.fit.smsg: -------------------------------------------------------------------------------- 1 | Extra Info (176273): Performing register packing on registers with non-logic cell location assignments 2 | Extra Info (176274): Completed register packing on registers with non-logic cell location assignments 3 | Extra Info (176236): Started Fast Input/Output/OE register processing 4 | Extra Info (176237): Finished Fast Input/Output/OE register processing 5 | Extra Info (176238): Start inferring scan chains for DSP blocks 6 | Extra Info (176239): Inferring scan chains for DSP blocks is complete 7 | Extra Info (176248): Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density 8 | Extra Info (176249): Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks 9 | -------------------------------------------------------------------------------- /proj/output_files/eth.fit.summary: -------------------------------------------------------------------------------- 1 | Fitter Status : Successful - Sat Feb 23 17:33:07 2019 2 | Quartus II 64-Bit Version : 13.0.0 Build 156 04/24/2013 SJ Full Version 3 | Revision Name : eth 4 | Top-level Entity Name : udp_proto_test 5 | Family : Cyclone IV E 6 | Device : EP4CE10F17C8 7 | Timing Models : Final 8 | Total logic elements : 901 / 10,320 ( 9 % ) 9 | Total combinational functions : 707 / 10,320 ( 7 % ) 10 | Dedicated logic registers : 605 / 10,320 ( 6 % ) 11 | Total registers : 605 12 | Total pins : 16 / 180 ( 9 % ) 13 | Total virtual pins : 0 14 | Total memory bits : 1,536 / 423,936 ( < 1 % ) 15 | Embedded Multiplier 9-bit elements : 0 / 46 ( 0 % ) 16 | Total PLLs : 0 / 2 ( 0 % ) 17 | -------------------------------------------------------------------------------- /proj/output_files/eth.map.smsg: -------------------------------------------------------------------------------- 1 | Warning (10268): Verilog HDL information at ip_proto_test.v(74): always construct contains both blocking and non-blocking assignments 2 | Warning (10268): Verilog HDL information at eth.v(89): always construct contains both blocking and non-blocking assignments 3 | Warning (10268): Verilog HDL information at udp_proto_test.v(76): always construct contains both blocking and non-blocking assignments 4 | -------------------------------------------------------------------------------- /proj/output_files/eth.map.summary: -------------------------------------------------------------------------------- 1 | Analysis & Synthesis Status : Successful - Sat Feb 23 17:32:59 2019 2 | Quartus II 64-Bit Version : 13.0.0 Build 156 04/24/2013 SJ Full Version 3 | Revision Name : eth 4 | Top-level Entity Name : udp_proto_test 5 | Family : Cyclone IV E 6 | Total logic elements : N/A until Partition Merge 7 | Total combinational functions : N/A until Partition Merge 8 | Dedicated logic registers : N/A until Partition Merge 9 | Total registers : N/A until Partition Merge 10 | Total pins : N/A until Partition Merge 11 | Total virtual pins : N/A until Partition Merge 12 | Total memory bits : N/A until Partition Merge 13 | Embedded Multiplier 9-bit elements : N/A until Partition Merge 14 | Total PLLs : N/A until Partition Merge 15 | -------------------------------------------------------------------------------- /proj/output_files/eth.merge.summary: -------------------------------------------------------------------------------- 1 | Partition Merge Status : Successful - Sat Feb 23 17:33:01 2019 2 | Quartus II 64-Bit Version : 13.0.0 Build 156 04/24/2013 SJ Full Version 3 | Revision Name : eth 4 | Top-level Entity Name : udp_proto_test 5 | Family : Cyclone IV E 6 | Total logic elements : 944 7 | Total combinational functions : 705 8 | Dedicated logic registers : 605 9 | Total registers : 605 10 | Total pins : 16 11 | Total virtual pins : 0 12 | Total memory bits : 1,536 13 | Embedded Multiplier 9-bit elements : 0 14 | Total PLLs : 0 15 | -------------------------------------------------------------------------------- /proj/output_files/eth.sof: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/DeamonYang/FPGA_100M_ETH/1caa878e38527286618d0852fc647df305cdd282/proj/output_files/eth.sof -------------------------------------------------------------------------------- /proj/output_files/eth.sta.summary: -------------------------------------------------------------------------------- 1 | ------------------------------------------------------------ 2 | TimeQuest Timing Analyzer Summary 3 | ------------------------------------------------------------ 4 | 5 | Type : Slow 1200mV 85C Model Setup 'mii_tx_clk' 6 | Slack : 33.304 7 | TNS : 0.000 8 | 9 | Type : Slow 1200mV 85C Model Setup 'altera_reserved_tck' 10 | Slack : 41.971 11 | TNS : 0.000 12 | 13 | Type : Slow 1200mV 85C Model Hold 'altera_reserved_tck' 14 | Slack : 0.452 15 | TNS : 0.000 16 | 17 | Type : Slow 1200mV 85C Model Hold 'mii_tx_clk' 18 | Slack : 0.485 19 | TNS : 0.000 20 | 21 | Type : Slow 1200mV 85C Model Recovery 'altera_reserved_tck' 22 | Slack : 48.080 23 | TNS : 0.000 24 | 25 | Type : Slow 1200mV 85C Model Removal 'altera_reserved_tck' 26 | Slack : 1.128 27 | TNS : 0.000 28 | 29 | Type : Slow 1200mV 85C Model Minimum Pulse Width 'mii_tx_clk' 30 | Slack : 19.635 31 | TNS : 0.000 32 | 33 | Type : Slow 1200mV 85C Model Minimum Pulse Width 'altera_reserved_tck' 34 | Slack : 49.456 35 | TNS : 0.000 36 | 37 | Type : Slow 1200mV 0C Model Setup 'mii_tx_clk' 38 | Slack : 33.701 39 | TNS : 0.000 40 | 41 | Type : Slow 1200mV 0C Model Setup 'altera_reserved_tck' 42 | Slack : 42.505 43 | TNS : 0.000 44 | 45 | Type : Slow 1200mV 0C Model Hold 'altera_reserved_tck' 46 | Slack : 0.401 47 | TNS : 0.000 48 | 49 | Type : Slow 1200mV 0C Model Hold 'mii_tx_clk' 50 | Slack : 0.430 51 | TNS : 0.000 52 | 53 | Type : Slow 1200mV 0C Model Recovery 'altera_reserved_tck' 54 | Slack : 48.369 55 | TNS : 0.000 56 | 57 | Type : Slow 1200mV 0C Model Removal 'altera_reserved_tck' 58 | Slack : 1.029 59 | TNS : 0.000 60 | 61 | Type : Slow 1200mV 0C Model Minimum Pulse Width 'mii_tx_clk' 62 | Slack : 19.530 63 | TNS : 0.000 64 | 65 | Type : Slow 1200mV 0C Model Minimum Pulse Width 'altera_reserved_tck' 66 | Slack : 49.305 67 | TNS : 0.000 68 | 69 | Type : Fast 1200mV 0C Model Setup 'mii_tx_clk' 70 | Slack : 37.082 71 | TNS : 0.000 72 | 73 | Type : Fast 1200mV 0C Model Setup 'altera_reserved_tck' 74 | Slack : 46.588 75 | TNS : 0.000 76 | 77 | Type : Fast 1200mV 0C Model Hold 'altera_reserved_tck' 78 | Slack : 0.186 79 | TNS : 0.000 80 | 81 | Type : Fast 1200mV 0C Model Hold 'mii_tx_clk' 82 | Slack : 0.201 83 | TNS : 0.000 84 | 85 | Type : Fast 1200mV 0C Model Recovery 'altera_reserved_tck' 86 | Slack : 49.313 87 | TNS : 0.000 88 | 89 | Type : Fast 1200mV 0C Model Removal 'altera_reserved_tck' 90 | Slack : 0.492 91 | TNS : 0.000 92 | 93 | Type : Fast 1200mV 0C Model Minimum Pulse Width 'mii_tx_clk' 94 | Slack : 19.375 95 | TNS : 0.000 96 | 97 | Type : Fast 1200mV 0C Model Minimum Pulse Width 'altera_reserved_tck' 98 | Slack : 49.450 99 | TNS : 0.000 100 | 101 | ------------------------------------------------------------ 102 | -------------------------------------------------------------------------------- /proj/simulation/modelsim/eth.sft: -------------------------------------------------------------------------------- 1 | set tool_name "ModelSim-Altera (Verilog)" 2 | set corner_file_list { 3 | {{"Slow -8 1.2V 85 Model"} {eth_8_1200mv_85c_slow.vo eth_8_1200mv_85c_v_slow.sdo}} 4 | {{"Slow -8 1.2V 0 Model"} {eth_8_1200mv_0c_slow.vo eth_8_1200mv_0c_v_slow.sdo}} 5 | {{"Fast -M 1.2V 0 Model"} {eth_min_1200mv_0c_fast.vo eth_min_1200mv_0c_v_fast.sdo}} 6 | } 7 | -------------------------------------------------------------------------------- /proj/simulation/modelsim/eth_run_msim_gate_verilog.do: -------------------------------------------------------------------------------- 1 | transcript on 2 | if {[file exists gate_work]} { 3 | vdel -lib gate_work -all 4 | } 5 | vlib gate_work 6 | vmap work gate_work 7 | 8 | vlog -vlog01compat -work work +incdir+. {eth_8_1200mv_85c_slow.vo} 9 | 10 | vlog -vlog01compat -work work +incdir+L:/FPWG_WORK/FPGA_100ETH/proj/../tb {L:/FPWG_WORK/FPGA_100ETH/proj/../tb/check_sum_tb.v} 11 | vlog -vlog01compat -work work +incdir+L:/FPWG_WORK/FPGA_100ETH/proj/../rtl {L:/FPWG_WORK/FPGA_100ETH/proj/../rtl/check_sum.v} 12 | 13 | vsim -t 1ps +transport_int_delays +transport_path_delays -L altera_ver -L cycloneive_ver -L gate_work -L work -voptargs="+acc" check_sum_tb 14 | 15 | add wave * 16 | view structure 17 | view signals 18 | run -all 19 | -------------------------------------------------------------------------------- /proj/simulation/modelsim/eth_run_msim_rtl_verilog.do: -------------------------------------------------------------------------------- 1 | transcript on 2 | if {[file exists rtl_work]} { 3 | vdel -lib rtl_work -all 4 | } 5 | vlib rtl_work 6 | vmap work rtl_work 7 | 8 | vlog -vlog01compat -work work +incdir+L:/FPWG_WORK/FPGA_100ETH/rtl {L:/FPWG_WORK/FPGA_100ETH/rtl/ip_protocol.v} 9 | vlog -vlog01compat -work work +incdir+L:/FPWG_WORK/FPGA_100ETH/rtl {L:/FPWG_WORK/FPGA_100ETH/rtl/crc32_d4.v} 10 | vlog -vlog01compat -work work +incdir+L:/FPWG_WORK/FPGA_100ETH/rtl {L:/FPWG_WORK/FPGA_100ETH/rtl/eth_mac.v} 11 | vlog -vlog01compat -work work +incdir+L:/FPWG_WORK/FPGA_100ETH/rtl {L:/FPWG_WORK/FPGA_100ETH/rtl/check_sum.v} 12 | vlog -vlog01compat -work work +incdir+L:/FPWG_WORK/FPGA_100ETH/rtl {L:/FPWG_WORK/FPGA_100ETH/rtl/udp_protocol.v} 13 | vlog -vlog01compat -work work +incdir+L:/FPWG_WORK/FPGA_100ETH/rtl {L:/FPWG_WORK/FPGA_100ETH/rtl/udp_proto_test.v} 14 | 15 | vlog -vlog01compat -work work +incdir+L:/FPWG_WORK/FPGA_100ETH/proj/../tb {L:/FPWG_WORK/FPGA_100ETH/proj/../tb/udp_proto_test_tb.v} 16 | vlog -vlog01compat -work work +incdir+L:/FPWG_WORK/FPGA_100ETH/proj/../rtl {L:/FPWG_WORK/FPGA_100ETH/proj/../rtl/check_sum.v} 17 | vlog -vlog01compat -work work +incdir+L:/FPWG_WORK/FPGA_100ETH/proj/../rtl {L:/FPWG_WORK/FPGA_100ETH/proj/../rtl/eth_mac.v} 18 | vlog -vlog01compat -work work +incdir+L:/FPWG_WORK/FPGA_100ETH/proj/../rtl {L:/FPWG_WORK/FPGA_100ETH/proj/../rtl/crc32_d4.v} 19 | vlog -vlog01compat -work work +incdir+L:/FPWG_WORK/FPGA_100ETH/proj/../rtl {L:/FPWG_WORK/FPGA_100ETH/proj/../rtl/udp_protocol.v} 20 | vlog -vlog01compat -work work +incdir+L:/FPWG_WORK/FPGA_100ETH/proj/../rtl {L:/FPWG_WORK/FPGA_100ETH/proj/../rtl/eth.v} 21 | vlog -vlog01compat -work work +incdir+L:/FPWG_WORK/FPGA_100ETH/proj/../rtl {L:/FPWG_WORK/FPGA_100ETH/proj/../rtl/ip_proto_test.v} 22 | vlog -vlog01compat -work work +incdir+L:/FPWG_WORK/FPGA_100ETH/proj/../rtl {L:/FPWG_WORK/FPGA_100ETH/proj/../rtl/udp_proto_test.v} 23 | vlog -vlog01compat -work work +incdir+L:/FPWG_WORK/FPGA_100ETH/proj/../rtl {L:/FPWG_WORK/FPGA_100ETH/proj/../rtl/ip_protocol.v} 24 | 25 | vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cycloneive_ver -L rtl_work -L work -voptargs="+acc" udp_proto_test_tb 26 | 27 | add wave * 28 | view structure 29 | view signals 30 | run -all 31 | -------------------------------------------------------------------------------- /proj/simulation/modelsim/eth_run_msim_rtl_verilog.do.bak: -------------------------------------------------------------------------------- 1 | transcript on 2 | if {[file exists rtl_work]} { 3 | vdel -lib rtl_work -all 4 | } 5 | vlib rtl_work 6 | vmap work rtl_work 7 | 8 | vlog -vlog01compat -work work +incdir+L:/FPWG_WORK/FPGA_100ETH/rtl {L:/FPWG_WORK/FPGA_100ETH/rtl/eth_mac.v} 9 | 10 | vlog -vlog01compat -work work +incdir+L:/FPWG_WORK/FPGA_100ETH/proj/../tb {L:/FPWG_WORK/FPGA_100ETH/proj/../tb/eth_mac_tb.v} 11 | vlog -vlog01compat -work work +incdir+L:/FPWG_WORK/FPGA_100ETH/proj/../rtl {L:/FPWG_WORK/FPGA_100ETH/proj/../rtl/eth_mac.v} 12 | vlog -vlog01compat -work work +incdir+L:/FPWG_WORK/FPGA_100ETH/proj/../rtl {L:/FPWG_WORK/FPGA_100ETH/proj/../rtl/eth.v} 13 | 14 | vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cycloneive_ver -L rtl_work -L work -voptargs="+acc" eth_mac_tb 15 | 16 | add wave * 17 | view structure 18 | view signals 19 | run -all 20 | -------------------------------------------------------------------------------- /proj/simulation/modelsim/eth_run_msim_rtl_verilog.do.bak1: -------------------------------------------------------------------------------- 1 | transcript on 2 | if {[file exists rtl_work]} { 3 | vdel -lib rtl_work -all 4 | } 5 | vlib rtl_work 6 | vmap work rtl_work 7 | 8 | vlog -vlog01compat -work work +incdir+L:/FPWG_WORK/FPGA_100ETH/rtl {L:/FPWG_WORK/FPGA_100ETH/rtl/eth_mac.v} 9 | vlog -vlog01compat -work work +incdir+L:/FPWG_WORK/FPGA_100ETH/rtl {L:/FPWG_WORK/FPGA_100ETH/rtl/eth.v} 10 | 11 | vlog -vlog01compat -work work +incdir+L:/FPWG_WORK/FPGA_100ETH/proj/../tb {L:/FPWG_WORK/FPGA_100ETH/proj/../tb/eth_mac_tb.v} 12 | vlog -vlog01compat -work work +incdir+L:/FPWG_WORK/FPGA_100ETH/proj/../rtl {L:/FPWG_WORK/FPGA_100ETH/proj/../rtl/eth_mac.v} 13 | vlog -vlog01compat -work work +incdir+L:/FPWG_WORK/FPGA_100ETH/proj/../rtl {L:/FPWG_WORK/FPGA_100ETH/proj/../rtl/eth.v} 14 | 15 | vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cycloneive_ver -L rtl_work -L work -voptargs="+acc" eth_mac_tb 16 | 17 | add wave * 18 | view structure 19 | view signals 20 | run -all 21 | -------------------------------------------------------------------------------- /proj/simulation/modelsim/eth_run_msim_rtl_verilog.do.bak2: -------------------------------------------------------------------------------- 1 | transcript on 2 | if {[file exists rtl_work]} { 3 | vdel -lib rtl_work -all 4 | } 5 | vlib rtl_work 6 | vmap work rtl_work 7 | 8 | vlog -vlog01compat -work work +incdir+L:/FPWG_WORK/FPGA_100ETH/rtl {L:/FPWG_WORK/FPGA_100ETH/rtl/eth_mac.v} 9 | vlog -vlog01compat -work work +incdir+L:/FPWG_WORK/FPGA_100ETH/rtl {L:/FPWG_WORK/FPGA_100ETH/rtl/eth.v} 10 | 11 | vlog -vlog01compat -work work +incdir+L:/FPWG_WORK/FPGA_100ETH/proj/../tb {L:/FPWG_WORK/FPGA_100ETH/proj/../tb/eth_tb.v} 12 | vlog -vlog01compat -work work +incdir+L:/FPWG_WORK/FPGA_100ETH/proj/../rtl {L:/FPWG_WORK/FPGA_100ETH/proj/../rtl/eth_mac.v} 13 | vlog -vlog01compat -work work +incdir+L:/FPWG_WORK/FPGA_100ETH/proj/../rtl {L:/FPWG_WORK/FPGA_100ETH/proj/../rtl/eth.v} 14 | 15 | vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cycloneive_ver -L rtl_work -L work -voptargs="+acc" eth_tb 16 | 17 | add wave * 18 | view structure 19 | view signals 20 | run -all 21 | -------------------------------------------------------------------------------- /proj/simulation/modelsim/eth_run_msim_rtl_verilog.do.bak3: -------------------------------------------------------------------------------- 1 | transcript on 2 | if {[file exists rtl_work]} { 3 | vdel -lib rtl_work -all 4 | } 5 | vlib rtl_work 6 | vmap work rtl_work 7 | 8 | vlog -vlog01compat -work work +incdir+L:/FPWG_WORK/FPGA_100ETH/rtl {L:/FPWG_WORK/FPGA_100ETH/rtl/crc32_d4.v} 9 | vlog -vlog01compat -work work +incdir+L:/FPWG_WORK/FPGA_100ETH/rtl {L:/FPWG_WORK/FPGA_100ETH/rtl/eth_mac.v} 10 | vlog -vlog01compat -work work +incdir+L:/FPWG_WORK/FPGA_100ETH/rtl {L:/FPWG_WORK/FPGA_100ETH/rtl/eth.v} 11 | 12 | vlog -vlog01compat -work work +incdir+L:/FPWG_WORK/FPGA_100ETH/proj/../tb {L:/FPWG_WORK/FPGA_100ETH/proj/../tb/check_sum_tb.v} 13 | vlog -vlog01compat -work work +incdir+L:/FPWG_WORK/FPGA_100ETH/proj/../rtl {L:/FPWG_WORK/FPGA_100ETH/proj/../rtl/check_sum.v} 14 | 15 | vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cycloneive_ver -L rtl_work -L work -voptargs="+acc" check_sum_tb 16 | 17 | add wave * 18 | view structure 19 | view signals 20 | run -all 21 | -------------------------------------------------------------------------------- /proj/simulation/modelsim/eth_run_msim_rtl_verilog.do.bak4: -------------------------------------------------------------------------------- 1 | transcript on 2 | if {[file exists rtl_work]} { 3 | vdel -lib rtl_work -all 4 | } 5 | vlib rtl_work 6 | vmap work rtl_work 7 | 8 | vlog -vlog01compat -work work +incdir+L:/FPWG_WORK/FPGA_100ETH/rtl {L:/FPWG_WORK/FPGA_100ETH/rtl/check_sum.v} 9 | 10 | vlog -vlog01compat -work work +incdir+L:/FPWG_WORK/FPGA_100ETH/proj/../tb {L:/FPWG_WORK/FPGA_100ETH/proj/../tb/check_sum_tb.v} 11 | vlog -vlog01compat -work work +incdir+L:/FPWG_WORK/FPGA_100ETH/proj/../rtl {L:/FPWG_WORK/FPGA_100ETH/proj/../rtl/check_sum.v} 12 | 13 | vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cycloneive_ver -L rtl_work -L work -voptargs="+acc" check_sum_tb 14 | 15 | add wave * 16 | view structure 17 | view signals 18 | run -all 19 | -------------------------------------------------------------------------------- /proj/simulation/modelsim/eth_run_msim_rtl_verilog.do.bak5: -------------------------------------------------------------------------------- 1 | transcript on 2 | if {[file exists rtl_work]} { 3 | vdel -lib rtl_work -all 4 | } 5 | vlib rtl_work 6 | vmap work rtl_work 7 | 8 | vlog -vlog01compat -work work +incdir+L:/FPWG_WORK/FPGA_100ETH/rtl {L:/FPWG_WORK/FPGA_100ETH/rtl/ip_protocol.v} 9 | vlog -vlog01compat -work work +incdir+L:/FPWG_WORK/FPGA_100ETH/rtl {L:/FPWG_WORK/FPGA_100ETH/rtl/crc32_d4.v} 10 | vlog -vlog01compat -work work +incdir+L:/FPWG_WORK/FPGA_100ETH/rtl {L:/FPWG_WORK/FPGA_100ETH/rtl/eth_mac.v} 11 | vlog -vlog01compat -work work +incdir+L:/FPWG_WORK/FPGA_100ETH/rtl {L:/FPWG_WORK/FPGA_100ETH/rtl/check_sum.v} 12 | 13 | vlog -vlog01compat -work work +incdir+L:/FPWG_WORK/FPGA_100ETH/proj/../tb {L:/FPWG_WORK/FPGA_100ETH/proj/../tb/ip_protocol_tb.v} 14 | vlog -vlog01compat -work work +incdir+L:/FPWG_WORK/FPGA_100ETH/proj/../rtl {L:/FPWG_WORK/FPGA_100ETH/proj/../rtl/eth_mac.v} 15 | vlog -vlog01compat -work work +incdir+L:/FPWG_WORK/FPGA_100ETH/proj/../rtl {L:/FPWG_WORK/FPGA_100ETH/proj/../rtl/crc32_d4.v} 16 | vlog -vlog01compat -work work +incdir+L:/FPWG_WORK/FPGA_100ETH/proj/../rtl {L:/FPWG_WORK/FPGA_100ETH/proj/../rtl/eth.v} 17 | vlog -vlog01compat -work work +incdir+L:/FPWG_WORK/FPGA_100ETH/proj/../rtl {L:/FPWG_WORK/FPGA_100ETH/proj/../rtl/check_sum.v} 18 | vlog -vlog01compat -work work +incdir+L:/FPWG_WORK/FPGA_100ETH/proj/../rtl {L:/FPWG_WORK/FPGA_100ETH/proj/../rtl/ip_protocol.v} 19 | 20 | vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cycloneive_ver -L rtl_work -L work -voptargs="+acc" ip_protocol_tb 21 | 22 | add wave * 23 | view structure 24 | view signals 25 | run -all 26 | -------------------------------------------------------------------------------- /proj/simulation/modelsim/eth_run_msim_rtl_verilog.do.bak6: -------------------------------------------------------------------------------- 1 | transcript on 2 | if {[file exists rtl_work]} { 3 | vdel -lib rtl_work -all 4 | } 5 | vlib rtl_work 6 | vmap work rtl_work 7 | 8 | vlog -vlog01compat -work work +incdir+L:/FPWG_WORK/FPGA_100ETH/rtl {L:/FPWG_WORK/FPGA_100ETH/rtl/ip_proto_test.v} 9 | vlog -vlog01compat -work work +incdir+L:/FPWG_WORK/FPGA_100ETH/rtl {L:/FPWG_WORK/FPGA_100ETH/rtl/ip_protocol.v} 10 | vlog -vlog01compat -work work +incdir+L:/FPWG_WORK/FPGA_100ETH/rtl {L:/FPWG_WORK/FPGA_100ETH/rtl/crc32_d4.v} 11 | vlog -vlog01compat -work work +incdir+L:/FPWG_WORK/FPGA_100ETH/rtl {L:/FPWG_WORK/FPGA_100ETH/rtl/eth_mac.v} 12 | vlog -vlog01compat -work work +incdir+L:/FPWG_WORK/FPGA_100ETH/rtl {L:/FPWG_WORK/FPGA_100ETH/rtl/check_sum.v} 13 | 14 | vlog -vlog01compat -work work +incdir+L:/FPWG_WORK/FPGA_100ETH/proj/../tb {L:/FPWG_WORK/FPGA_100ETH/proj/../tb/ip_proto_test_tb.v} 15 | vlog -vlog01compat -work work +incdir+L:/FPWG_WORK/FPGA_100ETH/proj/../rtl {L:/FPWG_WORK/FPGA_100ETH/proj/../rtl/eth_mac.v} 16 | vlog -vlog01compat -work work +incdir+L:/FPWG_WORK/FPGA_100ETH/proj/../rtl {L:/FPWG_WORK/FPGA_100ETH/proj/../rtl/crc32_d4.v} 17 | vlog -vlog01compat -work work +incdir+L:/FPWG_WORK/FPGA_100ETH/proj/../rtl {L:/FPWG_WORK/FPGA_100ETH/proj/../rtl/eth.v} 18 | vlog -vlog01compat -work work +incdir+L:/FPWG_WORK/FPGA_100ETH/proj/../rtl {L:/FPWG_WORK/FPGA_100ETH/proj/../rtl/check_sum.v} 19 | vlog -vlog01compat -work work +incdir+L:/FPWG_WORK/FPGA_100ETH/proj/../rtl {L:/FPWG_WORK/FPGA_100ETH/proj/../rtl/ip_protocol.v} 20 | vlog -vlog01compat -work work +incdir+L:/FPWG_WORK/FPGA_100ETH/proj/../rtl {L:/FPWG_WORK/FPGA_100ETH/proj/../rtl/ip_proto_test.v} 21 | 22 | vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cycloneive_ver -L rtl_work -L work -voptargs="+acc" ip_proto_test_tb 23 | 24 | add wave * 25 | view structure 26 | view signals 27 | run -all 28 | -------------------------------------------------------------------------------- /proj/simulation/modelsim/eth_run_msim_rtl_verilog.do.bak7: -------------------------------------------------------------------------------- 1 | transcript on 2 | if {[file exists rtl_work]} { 3 | vdel -lib rtl_work -all 4 | } 5 | vlib rtl_work 6 | vmap work rtl_work 7 | 8 | vlog -vlog01compat -work work +incdir+L:/FPWG_WORK/FPGA_100ETH/rtl {L:/FPWG_WORK/FPGA_100ETH/rtl/ip_proto_test.v} 9 | vlog -vlog01compat -work work +incdir+L:/FPWG_WORK/FPGA_100ETH/rtl {L:/FPWG_WORK/FPGA_100ETH/rtl/ip_protocol.v} 10 | vlog -vlog01compat -work work +incdir+L:/FPWG_WORK/FPGA_100ETH/rtl {L:/FPWG_WORK/FPGA_100ETH/rtl/crc32_d4.v} 11 | vlog -vlog01compat -work work +incdir+L:/FPWG_WORK/FPGA_100ETH/rtl {L:/FPWG_WORK/FPGA_100ETH/rtl/eth_mac.v} 12 | vlog -vlog01compat -work work +incdir+L:/FPWG_WORK/FPGA_100ETH/rtl {L:/FPWG_WORK/FPGA_100ETH/rtl/check_sum.v} 13 | 14 | vlog -vlog01compat -work work +incdir+L:/FPWG_WORK/FPGA_100ETH/proj/../tb {L:/FPWG_WORK/FPGA_100ETH/proj/../tb/ip_proto_test_tb.v} 15 | vlog -vlog01compat -work work +incdir+L:/FPWG_WORK/FPGA_100ETH/proj/../rtl {L:/FPWG_WORK/FPGA_100ETH/proj/../rtl/eth_mac.v} 16 | vlog -vlog01compat -work work +incdir+L:/FPWG_WORK/FPGA_100ETH/proj/../rtl {L:/FPWG_WORK/FPGA_100ETH/proj/../rtl/crc32_d4.v} 17 | vlog -vlog01compat -work work +incdir+L:/FPWG_WORK/FPGA_100ETH/proj/../rtl {L:/FPWG_WORK/FPGA_100ETH/proj/../rtl/eth.v} 18 | vlog -vlog01compat -work work +incdir+L:/FPWG_WORK/FPGA_100ETH/proj/../rtl {L:/FPWG_WORK/FPGA_100ETH/proj/../rtl/check_sum.v} 19 | vlog -vlog01compat -work work +incdir+L:/FPWG_WORK/FPGA_100ETH/proj/../rtl {L:/FPWG_WORK/FPGA_100ETH/proj/../rtl/ip_protocol.v} 20 | vlog -vlog01compat -work work +incdir+L:/FPWG_WORK/FPGA_100ETH/proj/../rtl {L:/FPWG_WORK/FPGA_100ETH/proj/../rtl/ip_proto_test.v} 21 | 22 | vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cycloneive_ver -L rtl_work -L work -voptargs="+acc" ip_proto_test_tb 23 | 24 | add wave * 25 | view structure 26 | view signals 27 | run -all 28 | -------------------------------------------------------------------------------- /proj/simulation/modelsim/eth_run_msim_rtl_verilog.do.bak8: -------------------------------------------------------------------------------- 1 | transcript on 2 | if {[file exists rtl_work]} { 3 | vdel -lib rtl_work -all 4 | } 5 | vlib rtl_work 6 | vmap work rtl_work 7 | 8 | vlog -vlog01compat -work work +incdir+L:/FPWG_WORK/FPGA_100ETH/rtl {L:/FPWG_WORK/FPGA_100ETH/rtl/ip_protocol.v} 9 | vlog -vlog01compat -work work +incdir+L:/FPWG_WORK/FPGA_100ETH/rtl {L:/FPWG_WORK/FPGA_100ETH/rtl/crc32_d4.v} 10 | vlog -vlog01compat -work work +incdir+L:/FPWG_WORK/FPGA_100ETH/rtl {L:/FPWG_WORK/FPGA_100ETH/rtl/eth_mac.v} 11 | vlog -vlog01compat -work work +incdir+L:/FPWG_WORK/FPGA_100ETH/rtl {L:/FPWG_WORK/FPGA_100ETH/rtl/check_sum.v} 12 | vlog -vlog01compat -work work +incdir+L:/FPWG_WORK/FPGA_100ETH/rtl {L:/FPWG_WORK/FPGA_100ETH/rtl/udp_protocol.v} 13 | vlog -vlog01compat -work work +incdir+L:/FPWG_WORK/FPGA_100ETH/rtl {L:/FPWG_WORK/FPGA_100ETH/rtl/udp_proto_test.v} 14 | 15 | vlog -vlog01compat -work work +incdir+L:/FPWG_WORK/FPGA_100ETH/proj/../tb {L:/FPWG_WORK/FPGA_100ETH/proj/../tb/udp_proto_test_tb.v} 16 | vlog -vlog01compat -work work +incdir+L:/FPWG_WORK/FPGA_100ETH/proj/../rtl {L:/FPWG_WORK/FPGA_100ETH/proj/../rtl/check_sum.v} 17 | vlog -vlog01compat -work work +incdir+L:/FPWG_WORK/FPGA_100ETH/proj/../rtl {L:/FPWG_WORK/FPGA_100ETH/proj/../rtl/eth_mac.v} 18 | vlog -vlog01compat -work work +incdir+L:/FPWG_WORK/FPGA_100ETH/proj/../rtl {L:/FPWG_WORK/FPGA_100ETH/proj/../rtl/crc32_d4.v} 19 | vlog -vlog01compat -work work +incdir+L:/FPWG_WORK/FPGA_100ETH/proj/../rtl {L:/FPWG_WORK/FPGA_100ETH/proj/../rtl/udp_protocol.v} 20 | vlog -vlog01compat -work work +incdir+L:/FPWG_WORK/FPGA_100ETH/proj/../rtl {L:/FPWG_WORK/FPGA_100ETH/proj/../rtl/eth.v} 21 | vlog -vlog01compat -work work +incdir+L:/FPWG_WORK/FPGA_100ETH/proj/../rtl {L:/FPWG_WORK/FPGA_100ETH/proj/../rtl/ip_proto_test.v} 22 | vlog -vlog01compat -work work +incdir+L:/FPWG_WORK/FPGA_100ETH/proj/../rtl {L:/FPWG_WORK/FPGA_100ETH/proj/../rtl/udp_proto_test.v} 23 | vlog -vlog01compat -work work +incdir+L:/FPWG_WORK/FPGA_100ETH/proj/../rtl {L:/FPWG_WORK/FPGA_100ETH/proj/../rtl/ip_protocol.v} 24 | 25 | vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cycloneive_ver -L rtl_work -L work -voptargs="+acc" udp_proto_test_tb 26 | 27 | add wave * 28 | view structure 29 | view signals 30 | run -all 31 | -------------------------------------------------------------------------------- /proj/simulation/modelsim/gate_work/_info: -------------------------------------------------------------------------------- 1 | m255 2 | K3 3 | 13 4 | cModel Technology 5 | Z0 dL:\FPWG_WORK\FPGA_100ETH\proj\simulation\modelsim 6 | vcheck_sum 7 | !i10b 1 8 | !s100 Y0_Uk<;G7hz[Hj16GYZP]0 9 | I1BnRXH8?Sd3IPj>^kcRL?3 10 | VTJFbP>6`Q?]JSbb8TR^Yk2 11 | Z1 dL:\FPWG_WORK\FPGA_100ETH\proj\simulation\modelsim 12 | w1550823367 13 | 8L:/FPWG_WORK/FPGA_100ETH/proj/../rtl/check_sum.v 14 | FL:/FPWG_WORK/FPGA_100ETH/proj/../rtl/check_sum.v 15 | L0 1 16 | Z2 OV;L;10.1d;51 17 | r1 18 | !s85 0 19 | 31 20 | !s108 1550824007.537000 21 | !s107 L:/FPWG_WORK/FPGA_100ETH/proj/../rtl/check_sum.v| 22 | !s90 -reportprogress|300|-vlog01compat|-work|work|+incdir+L:/FPWG_WORK/FPGA_100ETH/proj/../rtl|L:/FPWG_WORK/FPGA_100ETH/proj/../rtl/check_sum.v| 23 | !s101 -O0 24 | Z3 o-vlog01compat -work work -O0 25 | !s92 -vlog01compat -work work +incdir+L:/FPWG_WORK/FPGA_100ETH/proj/../rtl -O0 26 | vcheck_sum_tb 27 | I_noAbYm[f=nYf8zYCIE<^3 28 | VS1UmFe59DHPH:kFj>YG[01 29 | R1 30 | w1550823835 31 | 8L:/FPWG_WORK/FPGA_100ETH/proj/../tb/check_sum_tb.v 32 | FL:/FPWG_WORK/FPGA_100ETH/proj/../tb/check_sum_tb.v 33 | L0 2 34 | R2 35 | r1 36 | 31 37 | R3 38 | !i10b 1 39 | !s100 _Z1PMQhfke= 7'd15) && (data_cnt > 0); 49 | assign ip_totlen_byte = data_len + 8; 50 | 51 | 52 | 53 | 54 | assign fifo_ck = mii_tx_clk; 55 | 56 | 57 | ip_protocol ip_protocol_u3( 58 | .rst_n (rst_n ), 59 | .tx_go (tx_go ), 60 | .data_len (tot_data_len_byte ), 61 | 62 | .fifo_rq (ip_rq), 63 | .fifo_ck ( ), 64 | .fifo_da (ip_data), 65 | 66 | .mii_tx_clk (mii_tx_clk ), 67 | .mii_tx_en (mii_tx_en ), 68 | .mii_tx_er (mii_tx_er ), 69 | .mii_tx_da (mii_tx_da ) 70 | 71 | ); 72 | 73 | 74 | 75 | 76 | 77 | always@(posedge mii_tx_clk or negedge rst_n) 78 | if(!rst_n) 79 | data_cnt <= 12'd0; 80 | else if(cnt == 7'd1) 81 | data_cnt <= (data_len << 1); 82 | else if(cnt >= 7'd15 & data_cnt > 0) 83 | data_cnt <= data_cnt - 1'b1; 84 | 85 | 86 | 87 | always @(posedge mii_tx_clk or negedge rst_n) 88 | if(!rst_n) 89 | cnt <= 7'd0; 90 | else if(ip_rq)begin 91 | if(cnt > 7'd15 && data_cnt > 12'd0) 92 | cnt <= cnt; 93 | else 94 | cnt <= cnt + 1'b1; 95 | end else 96 | cnt <= 7'd0; 97 | 98 | 99 | 100 | always @(posedge mii_tx_clk or negedge rst_n ) 101 | if(!rst_n) 102 | ip_data <= 4'd0; 103 | else begin 104 | case (cnt) 105 | 00 : ip_data <= sour_port[11:8]; 106 | 01 : ip_data <= sour_port[15:12]; 107 | 02 : ip_data <= sour_port[3:0]; 108 | 03 : ip_data <= sour_port[7:4]; 109 | 110 | 04 : ip_data <= dest_port[11:8];//totlen 111 | 05 : ip_data <= dest_port[15:12]; 112 | 06 : ip_data <= dest_port[3:0]; 113 | 07 : ip_data <= dest_port[7:4]; 114 | 115 | 08 : ip_data <= tot_data_len_byte[11:8]; 116 | 09 : ip_data <= tot_data_len_byte[15:12]; 117 | 10 : ip_data <= tot_data_len_byte[3:0]; 118 | 11 : ip_data <= tot_data_len_byte[7:4]; 119 | 120 | 12 : ip_data <= udp_ck_sum[11:8]; 121 | 13 : ip_data <= udp_ck_sum[15:12]; 122 | 14 : ip_data <= udp_ck_sum[3:0]; 123 | 15 : ip_data <= udp_ck_sum[7:4]; 124 | 125 | 16 : ip_data <= fifo_da; 126 | 127 | 128 | default:ip_data <= 4'd0; 129 | endcase 130 | end 131 | 132 | 133 | 134 | 135 | 136 | endmodule 137 | 138 | -------------------------------------------------------------------------------- /rtl/udp_protocol.v.bak: -------------------------------------------------------------------------------- 1 | module udp_protocol(); 2 | 3 | 4 | 5 | endmodule 6 | 7 | -------------------------------------------------------------------------------- /tb/check_sum_tb.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns/1ns 2 | module check_sum_tb; 3 | 4 | 5 | reg [3:0]ver ; 6 | reg [3:0]hdr_len ; 7 | reg [7:0]tos ; 8 | reg [15:0]tot_len ; 9 | reg [15:0]id ; 10 | reg [15:0]offset ; 11 | reg [7:0]ttl ; 12 | reg [7:0]protocol ; 13 | reg [31:0]src_ip ; 14 | reg [31:0]dst_ip ; 15 | 16 | wire[15:0]res_check_sum; 17 | 18 | 19 | 20 | check_sum ck_sum_u2( 21 | .ver (ver ), 22 | .hdr_len (hdr_len ), 23 | .tos (tos ), 24 | .tot_len (tot_len ), 25 | .id (id ), 26 | .offset (offset ), 27 | .ttl (ttl ), 28 | .protocol (protocol ), 29 | .src_ip (src_ip ), 30 | .dst_ip (dst_ip ), 31 | .res_check_sum(res_check_sum) 32 | ); 33 | 34 | initial begin 35 | ver = 0; 36 | hdr_len = 0; 37 | tos = 0; 38 | tot_len = 0; 39 | id = 0; 40 | offset = 0; 41 | ttl = 0; 42 | protocol = 0; 43 | src_ip = 0; 44 | dst_ip = 0; 45 | #200; 46 | 47 | 48 | ver = 4'h4; 49 | hdr_len = 4'h5; 50 | tos = 8'h0; 51 | tot_len = 16'h0032; 52 | id = 16'h0000; 53 | offset = 16'h0000; 54 | ttl = 8'h40; 55 | protocol = 8'h11; 56 | src_ip = 32'hc0a80002; 57 | dst_ip = 32'hc0a80003; 58 | #300; 59 | 60 | 61 | ver = 4'h4; 62 | hdr_len = 4'h5; 63 | tos = 8'h0; 64 | tot_len = 16'h0032; 65 | id = 16'h0000; 66 | offset = 16'h0000; 67 | ttl = 8'h40; 68 | protocol = 8'h11; 69 | src_ip = 32'hc0a80005; 70 | dst_ip = 32'hc0a80008; 71 | #300; 72 | 73 | 74 | ver = 4'h4; 75 | hdr_len = 4'h5; 76 | tos = 8'h0; 77 | tot_len = 16'h0032; 78 | id = 16'h0000; 79 | offset = 16'h0000; 80 | ttl = 8'h40; 81 | protocol = 8'h11; 82 | src_ip = 32'hc0a80105; 83 | dst_ip = 32'hc0a80108; 84 | #300; 85 | 86 | $stop; 87 | end 88 | 89 | 90 | 91 | 92 | 93 | endmodule 94 | -------------------------------------------------------------------------------- /tb/check_sum_tb.v.bak: -------------------------------------------------------------------------------- 1 | module check_sum_tb; 2 | 3 | 4 | endmodule 5 | -------------------------------------------------------------------------------- /tb/eth_mac_tb.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns/1ns 2 | module eth_mac_tb; 3 | 4 | reg rst_n ; 5 | reg tx_go ; 6 | reg [10:0]data_len ; 7 | reg [47:0]des_mac ; 8 | reg [47:0]src_mac ; 9 | reg [31:0]crc_res ; 10 | reg [15:0]len_type ; 11 | reg [3:0]fifo_da ; 12 | reg mii_tx_clk ; 13 | 14 | wire fifo_rq ; 15 | wire fifo_ck ; 16 | 17 | wire mii_tx_en ; 18 | wire mii_tx_er ; 19 | wire [3:0]mii_tx_da ; 20 | 21 | 22 | 23 | 24 | eth_mac mac( 25 | .rst_n (rst_n ), 26 | .tx_go (tx_go ), 27 | .data_len (data_len ), 28 | .des_mac (des_mac ), 29 | .src_mac (src_mac ), 30 | .crc_res (crc_res ), 31 | .len_type (len_type ), 32 | .fifo_rq (fifo_rq ), 33 | .fifo_ck (fifo_ck ), 34 | .fifo_da (fifo_da ), 35 | .mii_tx_clk (mii_tx_clk ), 36 | .mii_tx_en (mii_tx_en ), 37 | .mii_tx_er (mii_tx_er ), 38 | .mii_tx_da (mii_tx_da ) 39 | ); 40 | 41 | initial begin 42 | mii_tx_clk = 0; 43 | rst_n = 0; 44 | tx_go = 0; 45 | data_len = 100; 46 | des_mac = 48'h84_7b_eb_48_94_13; 47 | src_mac = 48'h00_0a_35_01_fe_c0; 48 | len_type = 16'h08_00; 49 | crc_res = 32'h12_34_56_78; 50 | #201; 51 | rst_n = 1; 52 | #200; 53 | tx_go = 1; //启动一次发送 54 | #40; 55 | tx_go = 0; 56 | #40000; 57 | 58 | data_len = 10; 59 | des_mac = 48'h84_7b_eb_48_94_13; 60 | src_mac = 48'h00_0a_35_01_fe_c0; 61 | len_type = 16'h08_00; 62 | crc_res = 32'h12_34_56_78; 63 | #200; 64 | tx_go = 1; //启动一次发送 65 | #40; 66 | tx_go = 0; 67 | #40000; 68 | 69 | $stop; 70 | end 71 | 72 | 73 | always #20 mii_tx_clk = ~mii_tx_clk; 74 | 75 | 76 | always@(posedge mii_tx_clk or negedge rst_n) 77 | if(!rst_n) 78 | fifo_da <= 4'd0; 79 | else if(fifo_rq) 80 | fifo_da <= fifo_da + 1'b1; 81 | 82 | 83 | endmodule 84 | -------------------------------------------------------------------------------- /tb/eth_mac_tb.v.bak: -------------------------------------------------------------------------------- 1 | module eth_mac_tb; 2 | 3 | 4 | eth_mac( 5 | rst_n , 6 | tx_go , 7 | data_len , 8 | des_mac , 9 | src_mac , 10 | crc_res , 11 | len_type , 12 | 13 | fifo_rq , 14 | fifo_ck , 15 | fifo_da , 16 | 17 | /*mii 接口*/ 18 | mii_tx_clk , 19 | mii_tx_en , 20 | mii_tx_er , 21 | mii_tx_da , 22 | ); 23 | 24 | 25 | 26 | endmodule 27 | -------------------------------------------------------------------------------- /tb/eth_tb.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns/1ns 2 | module eth_tb; 3 | 4 | reg rst_n; 5 | reg mii_tx_clk; //MII接口发送时钟，由PHY芯片产生，25MHz 6 | wire mii_tx_en; //MII接口发送数据使能信号，高电平有效 7 | wire mii_tx_er; //发送错误，用以破坏数据包发送 8 | wire [3:0]mii_tx_da; //MII接口发送数据线，FPGA通过该数据线将需要发送的数据依次送给PHY芯片 9 | wire phy_rst_n; // PHY 复位信号 10 | 11 | reg mii_rx_clk; //MII接口接收时钟，由PHY芯片产生，25MHz 12 | reg mii_rx_dv; //MII接口接收数据有效信号，高电平有效 13 | reg mii_rx_er; //接收错误，本实例中暂时忽略该信号 14 | reg [3:0]mii_rx_da; //MII接口数据总线，FPGA通过该数据线读取PHY芯片接收到的以太网数据 15 | 16 | eth eth_u0( 17 | .rst_n (rst_n ), 18 | .mii_tx_clk (mii_tx_clk ), 19 | .mii_tx_en (mii_tx_en ), 20 | .mii_tx_er (mii_tx_er ), 21 | .mii_tx_da (mii_tx_da ), 22 | .mii_rx_clk (mii_rx_clk ), 23 | .mii_rx_dv (mii_rx_dv ), 24 | .mii_rx_er (mii_rx_er ), 25 | .mii_rx_da (mii_rx_da ), 26 | .phy_rst_n (phy_rst_n ) 27 | ); 28 | 29 | 30 | 31 | initial begin 32 | rst_n = 0; 33 | mii_tx_clk = 0; //MII接口发送时钟，由PHY芯片产生，25MHz 34 | #2000; 35 | rst_n = 1; 36 | #40000; 37 | $stop; 38 | end 39 | 40 | 41 | always #20 mii_tx_clk = ~mii_tx_clk; 42 | 43 | 44 | 45 | endmodule 46 | -------------------------------------------------------------------------------- /tb/eth_tb.v.bak: -------------------------------------------------------------------------------- 1 | module eth_tb; 2 | 3 | 4 | 5 | 6 | endmodule 7 | -------------------------------------------------------------------------------- /tb/ip_proto_test_tb.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns/1ns 2 | module ip_proto_test_tb; 3 | 4 | reg rst_n; 5 | 6 | //MII 接口信号 7 | reg mii_tx_clk; //MII接口发送时钟，由PHY芯片产生，25MHz 8 | wire mii_tx_en; //MII接口发送数据使能信号，高电平有效 9 | wire mii_tx_er; //发送错误，用以破坏数据包发送 10 | wire [3:0]mii_tx_da; //MII接口发送数据线，FPGA通过该数据线将需要发送的数据依次送给PHY芯片 11 | wire phy_rst_n; // PHY 复位信号 12 | 13 | reg mii_rx_clk; //MII接口接收时钟，由PHY芯片产生，25MHz 14 | reg mii_rx_dv; //MII接口接收数据有效信号，高电平有效 15 | reg mii_rx_er; //接收错误，本实例中暂时忽略该信号 16 | reg [3:0]mii_rx_da; //MII接口数据总线，FPGA通过该数据线读取PHY芯片接收到的以太网数据 17 | 18 | 19 | 20 | ip_proto_test ue8( 21 | .rst_n (rst_n ), 22 | .mii_tx_clk (mii_tx_clk ), 23 | .mii_tx_en (mii_tx_en ), 24 | .mii_tx_er (mii_tx_er ), 25 | .mii_tx_da (mii_tx_da ), 26 | .mii_rx_clk (mii_rx_clk ), 27 | .mii_rx_dv (mii_rx_dv ), 28 | .mii_rx_er (mii_rx_er ), 29 | .mii_rx_da (mii_rx_da ), 30 | .phy_rst_n(phy_rst_n) 31 | ); 32 | 33 | 34 | always #40 mii_tx_clk = ~mii_tx_clk; 35 | initial begin 36 | rst_n = 0; 37 | mii_tx_clk = 0; 38 | #2000; 39 | rst_n = 1; 40 | #40000; 41 | $stop; 42 | 43 | 44 | end 45 | 46 | 47 | 48 | 49 | endmodule 50 | -------------------------------------------------------------------------------- /tb/ip_proto_test_tb.v.bak: -------------------------------------------------------------------------------- 1 | `timescale 1ns/1ns 2 | module ip_proto_test_tb; 3 | 4 | ip_proto_test( 5 | rst_n , 6 | 7 | mii_tx_clk , 8 | mii_tx_en , 9 | mii_tx_er , 10 | mii_tx_da , 11 | 12 | mii_rx_clk , 13 | mii_rx_dv , 14 | mii_rx_er , 15 | mii_rx_da , 16 | 17 | phy_rst_n 18 | ); 19 | 20 | 21 | endmodule 22 | -------------------------------------------------------------------------------- /tb/ip_protocol_tb.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns/1ns 2 | 3 | module ip_protocol_tb; 4 | 5 | reg rst_n ; 6 | reg tx_go ; 7 | reg[11:0]data_len ; 8 | reg[4:0] fifo_da; 9 | reg mii_tx_clk ; 10 | 11 | 12 | wire fifo_rq ; 13 | wire fifo_ck ; 14 | wire mii_tx_en ; 15 | wire mii_tx_er ; 16 | wire [3:0]mii_tx_da ; 17 | 18 | ip_protocol ip_pro_u4( 19 | .rst_n (rst_n ), 20 | .tx_go (tx_go ), 21 | .data_len (data_len ), 22 | .fifo_rq (fifo_rq ), 23 | .fifo_ck (fifo_ck ), 24 | .fifo_da (fifo_da ), 25 | .mii_tx_clk (mii_tx_clk ), 26 | .mii_tx_en (mii_tx_en ), 27 | .mii_tx_er (mii_tx_er ), 28 | .mii_tx_da (mii_tx_da ) 29 | ); 30 | 31 | 32 | always #40 mii_tx_clk =~mii_tx_clk; 33 | 34 | initial begin 35 | rst_n = 0 ; 36 | tx_go = 0 ; 37 | data_len = 28 ; 38 | mii_tx_clk = 0; 39 | #2000; 40 | tx_go = 1; 41 | rst_n = 1; 42 | fifo_da = 4'hd; 43 | #50; 44 | tx_go = 0; 45 | #20000; 46 | $stop; 47 | end 48 | 49 | 50 | always@(posedge mii_tx_clk or negedge rst_n) 51 | if(!rst_n) 52 | fifo_da <= 4'd0; 53 | else if(fifo_rq) 54 | fifo_da <= fifo_da + 1'b1; 55 | 56 | 57 | endmodule 58 | -------------------------------------------------------------------------------- /tb/ip_protocol_tb.v.bak: -------------------------------------------------------------------------------- 1 | module ip_protocol_tb; 2 | 3 | 4 | ip_protocol( 5 | rst_n , 6 | clk , 7 | tx_go , 8 | data_len , 9 | 10 | fifo_rq , 11 | fifo_ck , 12 | fifo_da , 13 | 14 | 15 | mii_tx_clk , 16 | mii_tx_en , 17 | mii_tx_er , 18 | mii_tx_da 19 | 20 | ); 21 | 22 | 23 | endmodule 24 | -------------------------------------------------------------------------------- /tb/udp_proto_test_tb.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns/1ns 2 | module udp_proto_test_tb; 3 | 4 | 5 | reg rst_n; 6 | 7 | //MII 接口信号 8 | reg mii_tx_clk; //MII接口发送时钟，由PHY芯片产生，25MHz 9 | wire mii_tx_en; //MII接口发送数据使能信号，高电平有效 10 | wire mii_tx_er; //发送错误，用以破坏数据包发送 11 | wire [3:0]mii_tx_da; //MII接口发送数据线，FPGA通过该数据线将需要发送的数据依次送给PHY芯片 12 | wire phy_rst_n; // PHY 复位信号 13 | 14 | reg mii_rx_clk; //MII接口接收时钟，由PHY芯片产生，25MHz 15 | reg mii_rx_dv; //MII接口接收数据有效信号，高电平有效 16 | reg mii_rx_er; //接收错误，本实例中暂时忽略该信号 17 | reg [3:0]mii_rx_da; //MII接口数据总线，FPGA通过该数据线读取PHY芯片接收到的以太网数据 18 | 19 | 20 | 21 | udp_proto_test udp_proto_test_ue8( 22 | .rst_n (rst_n ), 23 | .mii_tx_clk (mii_tx_clk ), 24 | .mii_tx_en (mii_tx_en ), 25 | .mii_tx_er (mii_tx_er ), 26 | .mii_tx_da (mii_tx_da ), 27 | .mii_rx_clk (mii_rx_clk ), 28 | .mii_rx_dv (mii_rx_dv ), 29 | .mii_rx_er (mii_rx_er ), 30 | .mii_rx_da (mii_rx_da ), 31 | .phy_rst_n(phy_rst_n) 32 | ); 33 | 34 | always #40 mii_tx_clk = ~mii_tx_clk; 35 | initial begin 36 | rst_n = 0; 37 | mii_tx_clk = 0; 38 | #2000; 39 | rst_n = 1; 40 | #40000; 41 | $stop; 42 | 43 | 44 | end 45 | 46 | endmodule 47 | -------------------------------------------------------------------------------- /tb/udp_proto_test_tb.v.bak: -------------------------------------------------------------------------------- 1 | `timescale 1ns/1ns 2 | module udp_proto_test_tb; 3 | 4 | 5 | reg rst_n; 6 | 7 | //MII 接口信号 8 | reg mii_tx_clk; //MII接口发送时钟，由PHY芯片产生，25MHz 9 | wire mii_tx_en; //MII接口发送数据使能信号，高电平有效 10 | wire mii_tx_er; //发送错误，用以破坏数据包发送 11 | wire [3:0]mii_tx_da; //MII接口发送数据线，FPGA通过该数据线将需要发送的数据依次送给PHY芯片 12 | wire phy_rst_n; // PHY 复位信号 13 | 14 | reg mii_rx_clk; //MII接口接收时钟，由PHY芯片产生，25MHz 15 | reg mii_rx_dv; //MII接口接收数据有效信号，高电平有效 16 | reg mii_rx_er; //接收错误，本实例中暂时忽略该信号 17 | reg [3:0]mii_rx_da; //MII接口数据总线，FPGA通过该数据线读取PHY芯片接收到的以太网数据 18 | 19 | 20 | 21 | ip_proto_test ue8( 22 | .rst_n (rst_n ), 23 | .mii_tx_clk (mii_tx_clk ), 24 | .mii_tx_en (mii_tx_en ), 25 | .mii_tx_er (mii_tx_er ), 26 | .mii_tx_da (mii_tx_da ), 27 | .mii_rx_clk (mii_rx_clk ), 28 | .mii_rx_dv (mii_rx_dv ), 29 | .mii_rx_er (mii_rx_er ), 30 | .mii_rx_da (mii_rx_da ), 31 | .phy_rst_n(phy_rst_n) 32 | ); 33 | 34 | 35 | always #40 mii_tx_clk = ~mii_tx_clk; 36 | initial begin 37 | rst_n = 0; 38 | mii_tx_clk = 0; 39 | #2000; 40 | rst_n = 1; 41 | #40000; 42 | $stop; 43 | 44 | 45 | end 46 | 47 | endmodule 48 | -------------------------------------------------------------------------------- /tool/CRC_Calc+v0.1.exe: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/DeamonYang/FPGA_100M_ETH/1caa878e38527286618d0852fc647df305cdd282/tool/CRC_Calc+v0.1.exe -------------------------------------------------------------------------------- /tool/arp_pak_192.168.137.1.txt: -------------------------------------------------------------------------------- 1 | 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0x0a, 0x35, 0x01, 0xfe, 0xc0, 0x08, 0x06, 0x00, 0x01, 2 | 0x08, 0x00, 0x06, 0x04, 0x00, 0x01, 0x00, 0x21, 0x85, 0xc5, 0x2b, 0x8f, 0xc0, 0xa8, 0x89, 0x58, 3 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xa8, 0x89, 0x01, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 4 | 0xff, 0xff, 0x00, 0x23, 0xcd, 0x76, 0x63, 0x1a, 0x08, 0x06, 0x00, 0x01, -------------------------------------------------------------------------------- /tool/pkt_cap_while_snd.pcap: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/DeamonYang/FPGA_100M_ETH/1caa878e38527286618d0852fc647df305cdd282/tool/pkt_cap_while_snd.pcap -------------------------------------------------------------------------------- /tool/profile.ini: -------------------------------------------------------------------------------- 1 | [last_nic] 2 | name=rpcap://\Device\NPF_{EC9E5F8C-7FD7-4A32-9E17-BC81EC48C961} 3 | -------------------------------------------------------------------------------- /tool/udp.txt: -------------------------------------------------------------------------------- 1 | 0x00, 0x23, 0xcd, 0x76, 0x63, 0x1a, 0x00, 0x21, 0x85, 0xc5, 0x2b, 0x8f, 0x08, 0x00, 0x45, 0x00, 2 | 0x00, 0x30, 0x21, 0xb3, 0x00, 0x00, 0x40, 0x11, 0x9d, 0x6f, 0xc0, 0xa8, 0x01, 0x64, 0xde, 0x49, 3 | 0x1b, 0x45, 0x05, 0x21, 0x27, 0x15, 0x00, 0x1c, 0x60, 0x7b, 0x68, 0x65, 0x6c, 0x6c, 0x6f, 0x2c, 4 | 0x49, 0x6d, 0x20, 0x44, 0x65, 0x61, 0x6d, 0x6f, 0x6e, 0x59, 0x61, 0x6e, 0x67, 0x21, -------------------------------------------------------------------------------- /tool/udp——192.168.137.1.txt: -------------------------------------------------------------------------------- 1 | 0x98, 0xee, 0xcb, 0x91, 0xf7, 0xcb, 0x00, 0x0a, 0x35, 0x01, 0xfe, 0xc0, 0x08, 0x00, 0x45, 0x00, 2 | 0x00, 0x30, 0x21, 0xb3, 0x00, 0x00, 0x40, 0x11, 0xc5, 0x5f, 0xc0, 0xa8, 0x89, 0x58, 0xc0, 0xa8, 3 | 0x89, 0x01, 0x05, 0x21, 0x27, 0x15, 0x00, 0x1c, 0x88, 0x6b, 0x68, 0x65, 0x6c, 0x6c, 0x6f, 0x2c, 4 | 0x49, 0x6d, 0x20, 0x44, 0x65, 0x61, 0x6d, 0x6f, 0x6e, 0x59, 0x61, 0x6e, 0x67, 0x21, -------------------------------------------------------------------------------- /tool/xb_ether_tester.exe: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/DeamonYang/FPGA_100M_ETH/1caa878e38527286618d0852fc647df305cdd282/tool/xb_ether_tester.exe --------------------------------------------------------------------------------