├── FPGA_WORK ├── ip │ ├── ram128.qip │ ├── ram128.v │ ├── ram128_bb.v │ ├── ram128_inst.v │ ├── wnp.qip │ ├── wnp.v │ ├── wnp64relimg88.mif │ ├── wnp_bb.v │ └── wnp_inst.v ├── proj │ ├── add889.qip │ ├── db │ │ ├── altsyncram_9p91.tdf │ │ ├── altsyncram_j6g1.tdf │ │ ├── altsyncram_kt91.tdf │ │ ├── altsyncram_ufa1.tdf │ │ ├── altsyncram_uff1.tdf │ │ ├── fft.db_info │ │ ├── fft.sld_design_entry.sci │ │ ├── logic_util_heursitic.dat │ │ ├── mult_73t.tdf │ │ ├── mult_aat.tdf │ │ ├── mult_b3t.tdf │ │ └── prev_cmp_fft.qmsg │ ├── fft.qpf │ ├── fft.qsf │ ├── fft.qws │ ├── fft_assignment_defaults.qdf │ ├── fft_nativelink_simulation.rpt │ ├── greybox_tmp │ │ └── cbx_args.txt │ ├── incremental_db │ │ ├── README │ │ └── compiled_partitions │ │ │ ├── fft.db_info │ │ │ ├── fft.root_partition.cmp.dfp │ │ │ ├── fft.root_partition.cmp.kpt │ │ │ ├── fft.root_partition.cmp.logdb │ │ │ ├── fft.root_partition.map.dpi │ │ │ └── fft.root_partition.map.kpt │ ├── output_files │ │ ├── fft.asm.rpt │ │ ├── fft.done │ │ ├── fft.eda.rpt │ │ ├── fft.fit.rpt │ │ ├── fft.fit.smsg │ │ ├── fft.fit.summary │ │ ├── fft.flow.rpt │ │ ├── fft.jdi │ │ ├── fft.map.rpt │ │ ├── fft.map.smsg │ │ ├── fft.map.summary │ │ ├── fft.pin │ │ ├── fft.sof │ │ ├── fft.sta.rpt │ │ └── fft.sta.summary │ ├── ram128.qip │ ├── simulation │ │ └── modelsim │ │ │ ├── fft.sft │ │ │ ├── fft.vo │ │ │ ├── fft_8_1200mv_0c_slow.vo │ │ │ ├── fft_8_1200mv_0c_v_slow.sdo │ │ │ ├── fft_8_1200mv_85c_slow.vo │ │ │ ├── fft_8_1200mv_85c_v_slow.sdo │ │ │ ├── fft_min_1200mv_0c_fast.vo │ │ │ ├── fft_min_1200mv_0c_v_fast.sdo │ │ │ ├── fft_modelsim.xrf │ │ │ ├── fft_run_msim_rtl_verilog.do │ │ │ ├── fft_run_msim_rtl_verilog.do.bak │ │ │ ├── fft_run_msim_rtl_verilog.do.bak1 │ │ │ ├── fft_run_msim_rtl_verilog.do.bak10 │ │ │ ├── fft_run_msim_rtl_verilog.do.bak11 │ │ │ ├── fft_run_msim_rtl_verilog.do.bak2 │ │ │ ├── fft_run_msim_rtl_verilog.do.bak3 │ │ │ ├── fft_run_msim_rtl_verilog.do.bak4 │ │ │ ├── fft_run_msim_rtl_verilog.do.bak5 │ │ │ ├── fft_run_msim_rtl_verilog.do.bak6 │ │ │ ├── fft_run_msim_rtl_verilog.do.bak7 │ │ │ ├── fft_run_msim_rtl_verilog.do.bak8 │ │ │ ├── fft_run_msim_rtl_verilog.do.bak9 │ │ │ ├── fft_v.sdo │ │ │ ├── modelsim.ini │ │ │ ├── msim_transcript │ │ │ ├── rtl_work │ │ │ ├── _info │ │ │ ├── _vmake │ │ │ ├── butterfly_ra2 │ │ │ │ ├── _primary.dat │ │ │ │ ├── _primary.dbs │ │ │ │ ├── _primary.vhd │ │ │ │ ├── verilog.prw │ │ │ │ └── verilog.psm │ │ │ ├── butterfly_ra2_seri │ │ │ │ ├── _primary.dat │ │ │ │ ├── _primary.dbs │ │ │ │ ├── _primary.vhd │ │ │ │ ├── verilog.prw │ │ │ │ └── verilog.psm │ │ │ ├── fft │ │ │ │ ├── _primary.dat │ │ │ │ ├── _primary.dbs │ │ │ │ ├── _primary.vhd │ │ │ │ ├── verilog.prw │ │ │ │ └── verilog.psm │ │ │ ├── fft_tb │ │ │ │ ├── _primary.dat │ │ │ │ ├── _primary.dbs │ │ │ │ ├── _primary.vhd │ │ │ │ ├── verilog.prw │ │ │ │ └── verilog.psm │ │ │ ├── ram128 │ │ │ │ ├── _primary.dat │ │ │ │ ├── _primary.dbs │ │ │ │ ├── _primary.vhd │ │ │ │ ├── verilog.prw │ │ │ │ └── verilog.psm │ │ │ └── wnp │ │ │ │ ├── _primary.dat │ │ │ │ ├── _primary.dbs │ │ │ │ ├── _primary.vhd │ │ │ │ ├── verilog.prw │ │ │ │ └── verilog.psm │ │ │ ├── tcl_stacktrace.txt │ │ │ ├── vsim.wlf │ │ │ ├── wlft0591iw │ │ │ ├── wlft0sa19h │ │ │ ├── wlft3aybhq │ │ │ ├── wlft3ks94y │ │ │ ├── wlftabndgf │ │ │ ├── wlftb7yakq │ │ │ ├── wlftbhwxvm │ │ │ ├── wlftdicq3g │ │ │ ├── wlftexa9m4 │ │ │ ├── wlftgc9mvy │ │ │ ├── wlftms6rfq │ │ │ ├── wlftsddwz9 │ │ │ ├── wlfttgz7y5 │ │ │ ├── wlfttnyyyj │ │ │ ├── wlftw9qnts │ │ │ ├── wlftx365ss │ │ │ ├── wnp64relimg88.mif │ │ │ └── wnp64relimg88.ver │ ├── wnp.qip │ └── wnp64relimg88.mif ├── rtl │ ├── butterfly_ra2.v │ ├── butterfly_ra2.v.bak │ ├── butterfly_ra2_seri.v │ ├── butterfly_ra2_seri.v.bak │ ├── fft.v │ ├── fft.v.bak │ ├── fftbkbkb.v │ ├── greybox_tmp │ │ └── cbx_args.txt │ └── ram128.qip └── testbench │ ├── address_gererate_tb.v │ ├── address_gererate_tb.v.bak │ ├── butterfly_ra2_seri_tb.v │ ├── butterfly_ra2_seri_tb.v.bak │ ├── butterfly_ra2_tb.v │ ├── butterfly_ra2_tb.v.bak │ ├── fft_mult_tb.v │ ├── fft_mult_tb.v.bak │ ├── fft_tb.v │ └── fft_tb.v.bak ├── README.md └── VC_PROJ ├── main.c ├── myfft.c └── myfft.h /FPGA_WORK/ip/ram128.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "RAM: 1-PORT" 2 | set_global_assignment -name IP_TOOL_VERSION "13.0" 3 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "ram128.v"] 4 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "ram128_inst.v"] 5 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "ram128_bb.v"] 6 | -------------------------------------------------------------------------------- /FPGA_WORK/ip/ram128.v: -------------------------------------------------------------------------------- 1 | // megafunction wizard: %RAM: 1-PORT% 2 | // GENERATION: STANDARD 3 | // VERSION: WM1.0 4 | // MODULE: altsyncram 5 | 6 | // ============================================================ 7 | // File Name: ram128.v 8 | // Megafunction Name(s): 9 | // altsyncram 10 | // 11 | // Simulation Library Files(s): 12 | // altera_mf 13 | // ============================================================ 14 | // ************************************************************ 15 | // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! 16 | // 17 | // 13.0.0 Build 156 04/24/2013 SJ Full Version 18 | // ************************************************************ 19 | 20 | 21 | //Copyright (C) 1991-2013 Altera Corporation 22 | //Your use of Altera Corporation's design tools, logic functions 23 | //and other software and tools, and its AMPP partner logic 24 | //functions, and any output files from any of the foregoing 25 | //(including device programming or simulation files), and any 26 | //associated documentation or information are expressly subject 27 | //to the terms and conditions of the Altera Program License 28 | //Subscription Agreement, Altera MegaCore Function License 29 | //Agreement, or other applicable license agreement, including, 30 | //without limitation, that your use is for the sole purpose of 31 | //programming logic devices manufactured by Altera and sold by 32 | //Altera or its authorized distributors. Please refer to the 33 | //applicable agreement for further details. 34 | 35 | 36 | // synopsys translate_off 37 | `timescale 1 ps / 1 ps 38 | // synopsys translate_on 39 | module ram128 ( 40 | address, 41 | clock, 42 | data, 43 | wren, 44 | q); 45 | 46 | input [6:0] address; 47 | input clock; 48 | input [15:0] data; 49 | input wren; 50 | output [15:0] q; 51 | `ifndef ALTERA_RESERVED_QIS 52 | // synopsys translate_off 53 | `endif 54 | tri1 clock; 55 | `ifndef ALTERA_RESERVED_QIS 56 | // synopsys translate_on 57 | `endif 58 | 59 | wire [15:0] sub_wire0; 60 | wire [15:0] q = sub_wire0[15:0]; 61 | 62 | altsyncram altsyncram_component ( 63 | .address_a (address), 64 | .clock0 (clock), 65 | .data_a (data), 66 | .wren_a (wren), 67 | .q_a (sub_wire0), 68 | .aclr0 (1'b0), 69 | .aclr1 (1'b0), 70 | .address_b (1'b1), 71 | .addressstall_a (1'b0), 72 | .addressstall_b (1'b0), 73 | .byteena_a (1'b1), 74 | .byteena_b (1'b1), 75 | .clock1 (1'b1), 76 | .clocken0 (1'b1), 77 | .clocken1 (1'b1), 78 | .clocken2 (1'b1), 79 | .clocken3 (1'b1), 80 | .data_b (1'b1), 81 | .eccstatus (), 82 | .q_b (), 83 | .rden_a (1'b1), 84 | .rden_b (1'b1), 85 | .wren_b (1'b0)); 86 | defparam 87 | altsyncram_component.clock_enable_input_a = "BYPASS", 88 | altsyncram_component.clock_enable_output_a = "BYPASS", 89 | altsyncram_component.intended_device_family = "Cyclone IV E", 90 | altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO", 91 | altsyncram_component.lpm_type = "altsyncram", 92 | altsyncram_component.numwords_a = 128, 93 | altsyncram_component.operation_mode = "SINGLE_PORT", 94 | altsyncram_component.outdata_aclr_a = "NONE", 95 | altsyncram_component.outdata_reg_a = "UNREGISTERED", 96 | altsyncram_component.power_up_uninitialized = "FALSE", 97 | altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ", 98 | altsyncram_component.widthad_a = 7, 99 | altsyncram_component.width_a = 16, 100 | altsyncram_component.width_byteena_a = 1; 101 | 102 | 103 | endmodule 104 | 105 | // ============================================================ 106 | // CNX file retrieval info 107 | // ============================================================ 108 | // Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" 109 | // Retrieval info: PRIVATE: AclrAddr NUMERIC "0" 110 | // Retrieval info: PRIVATE: AclrByte NUMERIC "0" 111 | // Retrieval info: PRIVATE: AclrData NUMERIC "0" 112 | // Retrieval info: PRIVATE: AclrOutput NUMERIC "0" 113 | // Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0" 114 | // Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" 115 | // Retrieval info: PRIVATE: BlankMemory NUMERIC "1" 116 | // Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" 117 | // Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" 118 | // Retrieval info: PRIVATE: Clken NUMERIC "0" 119 | // Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1" 120 | // Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" 121 | // Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" 122 | // Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" 123 | // Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" 124 | // Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" 125 | // Retrieval info: PRIVATE: JTAG_ID STRING "NONE" 126 | // Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" 127 | // Retrieval info: PRIVATE: MIFfilename STRING "" 128 | // Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "128" 129 | // Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" 130 | // Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3" 131 | // Retrieval info: PRIVATE: RegAddr NUMERIC "1" 132 | // Retrieval info: PRIVATE: RegData NUMERIC "1" 133 | // Retrieval info: PRIVATE: RegOutput NUMERIC "0" 134 | // Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" 135 | // Retrieval info: PRIVATE: SingleClock NUMERIC "1" 136 | // Retrieval info: PRIVATE: UseDQRAM NUMERIC "1" 137 | // Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0" 138 | // Retrieval info: PRIVATE: WidthAddr NUMERIC "7" 139 | // Retrieval info: PRIVATE: WidthData NUMERIC "16" 140 | // Retrieval info: PRIVATE: rden NUMERIC "0" 141 | // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all 142 | // Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" 143 | // Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" 144 | // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" 145 | // Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO" 146 | // Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" 147 | // Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "128" 148 | // Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT" 149 | // Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" 150 | // Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED" 151 | // Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE" 152 | // Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ" 153 | // Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "7" 154 | // Retrieval info: CONSTANT: WIDTH_A NUMERIC "16" 155 | // Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" 156 | // Retrieval info: USED_PORT: address 0 0 7 0 INPUT NODEFVAL "address[6..0]" 157 | // Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" 158 | // Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL "data[15..0]" 159 | // Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL "q[15..0]" 160 | // Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren" 161 | // Retrieval info: CONNECT: @address_a 0 0 7 0 address 0 0 7 0 162 | // Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 163 | // Retrieval info: CONNECT: @data_a 0 0 16 0 data 0 0 16 0 164 | // Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0 165 | // Retrieval info: CONNECT: q 0 0 16 0 @q_a 0 0 16 0 166 | // Retrieval info: GEN_FILE: TYPE_NORMAL ram128.v TRUE 167 | // Retrieval info: GEN_FILE: TYPE_NORMAL ram128.inc FALSE 168 | // Retrieval info: GEN_FILE: TYPE_NORMAL ram128.cmp FALSE 169 | // Retrieval info: GEN_FILE: TYPE_NORMAL ram128.bsf FALSE 170 | // Retrieval info: GEN_FILE: TYPE_NORMAL ram128_inst.v TRUE 171 | // Retrieval info: GEN_FILE: TYPE_NORMAL ram128_bb.v TRUE 172 | // Retrieval info: LIB_FILE: altera_mf 173 | -------------------------------------------------------------------------------- /FPGA_WORK/ip/ram128_bb.v: -------------------------------------------------------------------------------- 1 | // megafunction wizard: %RAM: 1-PORT%VBB% 2 | // GENERATION: STANDARD 3 | // VERSION: WM1.0 4 | // MODULE: altsyncram 5 | 6 | // ============================================================ 7 | // File Name: ram128.v 8 | // Megafunction Name(s): 9 | // altsyncram 10 | // 11 | // Simulation Library Files(s): 12 | // altera_mf 13 | // ============================================================ 14 | // ************************************************************ 15 | // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! 16 | // 17 | // 13.0.0 Build 156 04/24/2013 SJ Full Version 18 | // ************************************************************ 19 | 20 | //Copyright (C) 1991-2013 Altera Corporation 21 | //Your use of Altera Corporation's design tools, logic functions 22 | //and other software and tools, and its AMPP partner logic 23 | //functions, and any output files from any of the foregoing 24 | //(including device programming or simulation files), and any 25 | //associated documentation or information are expressly subject 26 | //to the terms and conditions of the Altera Program License 27 | //Subscription Agreement, Altera MegaCore Function License 28 | //Agreement, or other applicable license agreement, including, 29 | //without limitation, that your use is for the sole purpose of 30 | //programming logic devices manufactured by Altera and sold by 31 | //Altera or its authorized distributors. Please refer to the 32 | //applicable agreement for further details. 33 | 34 | module ram128 ( 35 | address, 36 | clock, 37 | data, 38 | wren, 39 | q); 40 | 41 | input [6:0] address; 42 | input clock; 43 | input [15:0] data; 44 | input wren; 45 | output [15:0] q; 46 | `ifndef ALTERA_RESERVED_QIS 47 | // synopsys translate_off 48 | `endif 49 | tri1 clock; 50 | `ifndef ALTERA_RESERVED_QIS 51 | // synopsys translate_on 52 | `endif 53 | 54 | endmodule 55 | 56 | // ============================================================ 57 | // CNX file retrieval info 58 | // ============================================================ 59 | // Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" 60 | // Retrieval info: PRIVATE: AclrAddr NUMERIC "0" 61 | // Retrieval info: PRIVATE: AclrByte NUMERIC "0" 62 | // Retrieval info: PRIVATE: AclrData NUMERIC "0" 63 | // Retrieval info: PRIVATE: AclrOutput NUMERIC "0" 64 | // Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0" 65 | // Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" 66 | // Retrieval info: PRIVATE: BlankMemory NUMERIC "1" 67 | // Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" 68 | // Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" 69 | // Retrieval info: PRIVATE: Clken NUMERIC "0" 70 | // Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1" 71 | // Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" 72 | // Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" 73 | // Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" 74 | // Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" 75 | // Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" 76 | // Retrieval info: PRIVATE: JTAG_ID STRING "NONE" 77 | // Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" 78 | // Retrieval info: PRIVATE: MIFfilename STRING "" 79 | // Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "128" 80 | // Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" 81 | // Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3" 82 | // Retrieval info: PRIVATE: RegAddr NUMERIC "1" 83 | // Retrieval info: PRIVATE: RegData NUMERIC "1" 84 | // Retrieval info: PRIVATE: RegOutput NUMERIC "0" 85 | // Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" 86 | // Retrieval info: PRIVATE: SingleClock NUMERIC "1" 87 | // Retrieval info: PRIVATE: UseDQRAM NUMERIC "1" 88 | // Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0" 89 | // Retrieval info: PRIVATE: WidthAddr NUMERIC "7" 90 | // Retrieval info: PRIVATE: WidthData NUMERIC "16" 91 | // Retrieval info: PRIVATE: rden NUMERIC "0" 92 | // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all 93 | // Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" 94 | // Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" 95 | // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" 96 | // Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO" 97 | // Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" 98 | // Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "128" 99 | // Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT" 100 | // Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" 101 | // Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED" 102 | // Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE" 103 | // Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ" 104 | // Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "7" 105 | // Retrieval info: CONSTANT: WIDTH_A NUMERIC "16" 106 | // Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" 107 | // Retrieval info: USED_PORT: address 0 0 7 0 INPUT NODEFVAL "address[6..0]" 108 | // Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" 109 | // Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL "data[15..0]" 110 | // Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL "q[15..0]" 111 | // Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren" 112 | // Retrieval info: CONNECT: @address_a 0 0 7 0 address 0 0 7 0 113 | // Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 114 | // Retrieval info: CONNECT: @data_a 0 0 16 0 data 0 0 16 0 115 | // Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0 116 | // Retrieval info: CONNECT: q 0 0 16 0 @q_a 0 0 16 0 117 | // Retrieval info: GEN_FILE: TYPE_NORMAL ram128.v TRUE 118 | // Retrieval info: GEN_FILE: TYPE_NORMAL ram128.inc FALSE 119 | // Retrieval info: GEN_FILE: TYPE_NORMAL ram128.cmp FALSE 120 | // Retrieval info: GEN_FILE: TYPE_NORMAL ram128.bsf FALSE 121 | // Retrieval info: GEN_FILE: TYPE_NORMAL ram128_inst.v TRUE 122 | // Retrieval info: GEN_FILE: TYPE_NORMAL ram128_bb.v TRUE 123 | // Retrieval info: LIB_FILE: altera_mf 124 | -------------------------------------------------------------------------------- /FPGA_WORK/ip/ram128_inst.v: -------------------------------------------------------------------------------- 1 | ram128 ram128_inst ( 2 | .address ( address_sig ), 3 | .clock ( clock_sig ), 4 | .data ( data_sig ), 5 | .wren ( wren_sig ), 6 | .q ( q_sig ) 7 | ); 8 | -------------------------------------------------------------------------------- /FPGA_WORK/ip/wnp.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "ROM: 1-PORT" 2 | set_global_assignment -name IP_TOOL_VERSION "13.0" 3 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "wnp.v"] 4 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "wnp_inst.v"] 5 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "wnp_bb.v"] 6 | -------------------------------------------------------------------------------- /FPGA_WORK/ip/wnp.v: -------------------------------------------------------------------------------- 1 | // megafunction wizard: %ROM: 1-PORT% 2 | // GENERATION: STANDARD 3 | // VERSION: WM1.0 4 | // MODULE: altsyncram 5 | 6 | // ============================================================ 7 | // File Name: wnp.v 8 | // Megafunction Name(s): 9 | // altsyncram 10 | // 11 | // Simulation Library Files(s): 12 | // altera_mf 13 | // ============================================================ 14 | // ************************************************************ 15 | // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! 16 | // 17 | // 13.0.0 Build 156 04/24/2013 SJ Full Version 18 | // ************************************************************ 19 | 20 | 21 | //Copyright (C) 1991-2013 Altera Corporation 22 | //Your use of Altera Corporation's design tools, logic functions 23 | //and other software and tools, and its AMPP partner logic 24 | //functions, and any output files from any of the foregoing 25 | //(including device programming or simulation files), and any 26 | //associated documentation or information are expressly subject 27 | //to the terms and conditions of the Altera Program License 28 | //Subscription Agreement, Altera MegaCore Function License 29 | //Agreement, or other applicable license agreement, including, 30 | //without limitation, that your use is for the sole purpose of 31 | //programming logic devices manufactured by Altera and sold by 32 | //Altera or its authorized distributors. Please refer to the 33 | //applicable agreement for further details. 34 | 35 | 36 | // synopsys translate_off 37 | `timescale 1 ps / 1 ps 38 | // synopsys translate_on 39 | module wnp ( 40 | address, 41 | clock, 42 | q); 43 | 44 | input [5:0] address; 45 | input clock; 46 | output [15:0] q; 47 | `ifndef ALTERA_RESERVED_QIS 48 | // synopsys translate_off 49 | `endif 50 | tri1 clock; 51 | `ifndef ALTERA_RESERVED_QIS 52 | // synopsys translate_on 53 | `endif 54 | 55 | wire [15:0] sub_wire0; 56 | wire [15:0] q = sub_wire0[15:0]; 57 | 58 | altsyncram altsyncram_component ( 59 | .address_a (address), 60 | .clock0 (clock), 61 | .q_a (sub_wire0), 62 | .aclr0 (1'b0), 63 | .aclr1 (1'b0), 64 | .address_b (1'b1), 65 | .addressstall_a (1'b0), 66 | .addressstall_b (1'b0), 67 | .byteena_a (1'b1), 68 | .byteena_b (1'b1), 69 | .clock1 (1'b1), 70 | .clocken0 (1'b1), 71 | .clocken1 (1'b1), 72 | .clocken2 (1'b1), 73 | .clocken3 (1'b1), 74 | .data_a ({16{1'b1}}), 75 | .data_b (1'b1), 76 | .eccstatus (), 77 | .q_b (), 78 | .rden_a (1'b1), 79 | .rden_b (1'b1), 80 | .wren_a (1'b0), 81 | .wren_b (1'b0)); 82 | defparam 83 | altsyncram_component.address_aclr_a = "NONE", 84 | altsyncram_component.clock_enable_input_a = "BYPASS", 85 | altsyncram_component.clock_enable_output_a = "BYPASS", 86 | altsyncram_component.init_file = "wnp64relimg88.mif", 87 | altsyncram_component.intended_device_family = "Cyclone IV E", 88 | altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO", 89 | altsyncram_component.lpm_type = "altsyncram", 90 | altsyncram_component.numwords_a = 64, 91 | altsyncram_component.operation_mode = "ROM", 92 | altsyncram_component.outdata_aclr_a = "NONE", 93 | altsyncram_component.outdata_reg_a = "UNREGISTERED", 94 | altsyncram_component.widthad_a = 6, 95 | altsyncram_component.width_a = 16, 96 | altsyncram_component.width_byteena_a = 1; 97 | 98 | 99 | endmodule 100 | 101 | // ============================================================ 102 | // CNX file retrieval info 103 | // ============================================================ 104 | // Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" 105 | // Retrieval info: PRIVATE: AclrAddr NUMERIC "0" 106 | // Retrieval info: PRIVATE: AclrByte NUMERIC "0" 107 | // Retrieval info: PRIVATE: AclrOutput NUMERIC "0" 108 | // Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0" 109 | // Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" 110 | // Retrieval info: PRIVATE: BlankMemory NUMERIC "0" 111 | // Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" 112 | // Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" 113 | // Retrieval info: PRIVATE: Clken NUMERIC "0" 114 | // Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" 115 | // Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" 116 | // Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" 117 | // Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" 118 | // Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" 119 | // Retrieval info: PRIVATE: JTAG_ID STRING "NONE" 120 | // Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" 121 | // Retrieval info: PRIVATE: MIFfilename STRING "wnp64relimg88.mif" 122 | // Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "64" 123 | // Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" 124 | // Retrieval info: PRIVATE: RegAddr NUMERIC "1" 125 | // Retrieval info: PRIVATE: RegOutput NUMERIC "0" 126 | // Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" 127 | // Retrieval info: PRIVATE: SingleClock NUMERIC "1" 128 | // Retrieval info: PRIVATE: UseDQRAM NUMERIC "0" 129 | // Retrieval info: PRIVATE: WidthAddr NUMERIC "6" 130 | // Retrieval info: PRIVATE: WidthData NUMERIC "16" 131 | // Retrieval info: PRIVATE: rden NUMERIC "0" 132 | // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all 133 | // Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE" 134 | // Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" 135 | // Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" 136 | // Retrieval info: CONSTANT: INIT_FILE STRING "wnp64relimg88.mif" 137 | // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" 138 | // Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO" 139 | // Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" 140 | // Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "64" 141 | // Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM" 142 | // Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" 143 | // Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED" 144 | // Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "6" 145 | // Retrieval info: CONSTANT: WIDTH_A NUMERIC "16" 146 | // Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" 147 | // Retrieval info: USED_PORT: address 0 0 6 0 INPUT NODEFVAL "address[5..0]" 148 | // Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" 149 | // Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL "q[15..0]" 150 | // Retrieval info: CONNECT: @address_a 0 0 6 0 address 0 0 6 0 151 | // Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 152 | // Retrieval info: CONNECT: q 0 0 16 0 @q_a 0 0 16 0 153 | // Retrieval info: GEN_FILE: TYPE_NORMAL wnp.v TRUE 154 | // Retrieval info: GEN_FILE: TYPE_NORMAL wnp.inc FALSE 155 | // Retrieval info: GEN_FILE: TYPE_NORMAL wnp.cmp FALSE 156 | // Retrieval info: GEN_FILE: TYPE_NORMAL wnp.bsf FALSE 157 | // Retrieval info: GEN_FILE: TYPE_NORMAL wnp_inst.v TRUE 158 | // Retrieval info: GEN_FILE: TYPE_NORMAL wnp_bb.v TRUE 159 | // Retrieval info: LIB_FILE: altera_mf 160 | -------------------------------------------------------------------------------- /FPGA_WORK/ip/wnp64relimg88.mif: -------------------------------------------------------------------------------- 1 | WIDTH=16; 2 | DEPTH=64; 3 | 4 | ADDRESS_RADIX=UNS; 5 | DATA_RADIX=HEX; 6 | 7 | CONTENT BEGIN 8 | 0 : 7f00; 9 | 1 : 7ef4; 10 | 2 : 7de7; 11 | 3 : 7adb; 12 | 4 : 75cf; 13 | 5 : 70c4; 14 | 6 : 6ab9; 15 | 7 : 62af; 16 | 8 : 5aa6; 17 | 9 : 519e; 18 | 10 : 4796; 19 | 11 : 3c90; 20 | 12 : 318b; 21 | 13 : 2586; 22 | 14 : 1983; 23 | 15 : 0c82; 24 | 16 : 0081; 25 | 17 : f482; 26 | 18 : e783; 27 | 19 : db86; 28 | 20 : cf8b; 29 | 21 : c490; 30 | 22 : b996; 31 | 23 : af9e; 32 | 24 : a6a6; 33 | 25 : 9eaf; 34 | 26 : 96b9; 35 | 27 : 90c4; 36 | 28 : 8bcf; 37 | 29 : 86db; 38 | 30 : 83e7; 39 | 31 : 82f4; 40 | 32 : 8100; 41 | 33 : 820c; 42 | 34 : 8319; 43 | 35 : 8625; 44 | 36 : 8b31; 45 | 37 : 903c; 46 | 38 : 9647; 47 | 39 : 9e51; 48 | 40 : a65a; 49 | 41 : af62; 50 | 42 : b96a; 51 | 43 : c470; 52 | 44 : cf75; 53 | 45 : db7a; 54 | 46 : e77d; 55 | 47 : f47e; 56 | 48 : 007f; 57 | 49 : 0c7e; 58 | 50 : 197d; 59 | 51 : 257a; 60 | 52 : 3175; 61 | 53 : 3c70; 62 | 54 : 476a; 63 | 55 : 5162; 64 | 56 : 5a5a; 65 | 57 : 6251; 66 | 58 : 6a47; 67 | 59 : 703c; 68 | 60 : 7531; 69 | 61 : 7a25; 70 | 62 : 7d19; 71 | 63 : 7e0c; 72 | END; 73 | -------------------------------------------------------------------------------- /FPGA_WORK/ip/wnp_bb.v: -------------------------------------------------------------------------------- 1 | // megafunction wizard: %ROM: 1-PORT%VBB% 2 | // GENERATION: STANDARD 3 | // VERSION: WM1.0 4 | // MODULE: altsyncram 5 | 6 | // ============================================================ 7 | // File Name: wnp.v 8 | // Megafunction Name(s): 9 | // altsyncram 10 | // 11 | // Simulation Library Files(s): 12 | // altera_mf 13 | // ============================================================ 14 | // ************************************************************ 15 | // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! 16 | // 17 | // 13.0.0 Build 156 04/24/2013 SJ Full Version 18 | // ************************************************************ 19 | 20 | //Copyright (C) 1991-2013 Altera Corporation 21 | //Your use of Altera Corporation's design tools, logic functions 22 | //and other software and tools, and its AMPP partner logic 23 | //functions, and any output files from any of the foregoing 24 | //(including device programming or simulation files), and any 25 | //associated documentation or information are expressly subject 26 | //to the terms and conditions of the Altera Program License 27 | //Subscription Agreement, Altera MegaCore Function License 28 | //Agreement, or other applicable license agreement, including, 29 | //without limitation, that your use is for the sole purpose of 30 | //programming logic devices manufactured by Altera and sold by 31 | //Altera or its authorized distributors. Please refer to the 32 | //applicable agreement for further details. 33 | 34 | module wnp ( 35 | address, 36 | clock, 37 | q); 38 | 39 | input [5:0] address; 40 | input clock; 41 | output [15:0] q; 42 | `ifndef ALTERA_RESERVED_QIS 43 | // synopsys translate_off 44 | `endif 45 | tri1 clock; 46 | `ifndef ALTERA_RESERVED_QIS 47 | // synopsys translate_on 48 | `endif 49 | 50 | endmodule 51 | 52 | // ============================================================ 53 | // CNX file retrieval info 54 | // ============================================================ 55 | // Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" 56 | // Retrieval info: PRIVATE: AclrAddr NUMERIC "0" 57 | // Retrieval info: PRIVATE: AclrByte NUMERIC "0" 58 | // Retrieval info: PRIVATE: AclrOutput NUMERIC "0" 59 | // Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0" 60 | // Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" 61 | // Retrieval info: PRIVATE: BlankMemory NUMERIC "0" 62 | // Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" 63 | // Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" 64 | // Retrieval info: PRIVATE: Clken NUMERIC "0" 65 | // Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" 66 | // Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" 67 | // Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" 68 | // Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" 69 | // Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" 70 | // Retrieval info: PRIVATE: JTAG_ID STRING "NONE" 71 | // Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" 72 | // Retrieval info: PRIVATE: MIFfilename STRING "wnp64relimg88.mif" 73 | // Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "64" 74 | // Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" 75 | // Retrieval info: PRIVATE: RegAddr NUMERIC "1" 76 | // Retrieval info: PRIVATE: RegOutput NUMERIC "0" 77 | // Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" 78 | // Retrieval info: PRIVATE: SingleClock NUMERIC "1" 79 | // Retrieval info: PRIVATE: UseDQRAM NUMERIC "0" 80 | // Retrieval info: PRIVATE: WidthAddr NUMERIC "6" 81 | // Retrieval info: PRIVATE: WidthData NUMERIC "16" 82 | // Retrieval info: PRIVATE: rden NUMERIC "0" 83 | // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all 84 | // Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE" 85 | // Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" 86 | // Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" 87 | // Retrieval info: CONSTANT: INIT_FILE STRING "wnp64relimg88.mif" 88 | // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" 89 | // Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO" 90 | // Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" 91 | // Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "64" 92 | // Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM" 93 | // Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" 94 | // Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED" 95 | // Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "6" 96 | // Retrieval info: CONSTANT: WIDTH_A NUMERIC "16" 97 | // Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" 98 | // Retrieval info: USED_PORT: address 0 0 6 0 INPUT NODEFVAL "address[5..0]" 99 | // Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" 100 | // Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL "q[15..0]" 101 | // Retrieval info: CONNECT: @address_a 0 0 6 0 address 0 0 6 0 102 | // Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 103 | // Retrieval info: CONNECT: q 0 0 16 0 @q_a 0 0 16 0 104 | // Retrieval info: GEN_FILE: TYPE_NORMAL wnp.v TRUE 105 | // Retrieval info: GEN_FILE: TYPE_NORMAL wnp.inc FALSE 106 | // Retrieval info: GEN_FILE: TYPE_NORMAL wnp.cmp FALSE 107 | // Retrieval info: GEN_FILE: TYPE_NORMAL wnp.bsf FALSE 108 | // Retrieval info: GEN_FILE: TYPE_NORMAL wnp_inst.v TRUE 109 | // Retrieval info: GEN_FILE: TYPE_NORMAL wnp_bb.v TRUE 110 | // Retrieval info: LIB_FILE: altera_mf 111 | -------------------------------------------------------------------------------- /FPGA_WORK/ip/wnp_inst.v: -------------------------------------------------------------------------------- 1 | wnp wnp_inst ( 2 | .address ( address_sig ), 3 | .clock ( clock_sig ), 4 | .q ( q_sig ) 5 | ); 6 | -------------------------------------------------------------------------------- /FPGA_WORK/proj/add889.qip: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/DeamonYang/FPGA_FFT/fa3b99e23651234b410932c9e37d66598745853f/FPGA_WORK/proj/add889.qip -------------------------------------------------------------------------------- /FPGA_WORK/proj/db/altsyncram_9p91.tdf: -------------------------------------------------------------------------------- 1 | --altsyncram ADDRESS_ACLR_A="NONE" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CLOCK_ENABLE_INPUT_A="BYPASS" CLOCK_ENABLE_OUTPUT_A="BYPASS" CYCLONEII_M4K_COMPATIBILITY="ON" DEVICE_FAMILY="Cyclone IV E" ENABLE_RUNTIME_MOD="NO" INIT_FILE="wnp64relimg88.mif" LOW_POWER_MODE="AUTO" NUMWORDS_A=64 OPERATION_MODE="ROM" OUTDATA_ACLR_A="NONE" OUTDATA_REG_A="CLOCK0" WIDTH_A=16 WIDTH_BYTEENA_A=1 WIDTHAD_A=6 address_a clock0 q_a CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 2 | --VERSION_BEGIN 13.0 cbx_altsyncram 2013:04:24:18:08:47:SJ cbx_cycloneii 2013:04:24:18:08:47:SJ cbx_lpm_add_sub 2013:04:24:18:08:47:SJ cbx_lpm_compare 2013:04:24:18:08:47:SJ cbx_lpm_decode 2013:04:24:18:08:47:SJ cbx_lpm_mux 2013:04:24:18:08:47:SJ cbx_mgl 2013:04:24:18:11:10:SJ cbx_stratix 2013:04:24:18:08:47:SJ cbx_stratixii 2013:04:24:18:08:47:SJ cbx_stratixiii 2013:04:24:18:08:47:SJ cbx_stratixv 2013:04:24:18:08:47:SJ cbx_util_mgl 2013:04:24:18:08:47:SJ VERSION_END 3 | 4 | 5 | -- Copyright (C) 1991-2013 Altera Corporation 6 | -- Your use of Altera Corporation's design tools, logic functions 7 | -- and other software and tools, and its AMPP partner logic 8 | -- functions, and any output files from any of the foregoing 9 | -- (including device programming or simulation files), and any 10 | -- associated documentation or information are expressly subject 11 | -- to the terms and conditions of the Altera Program License 12 | -- Subscription Agreement, Altera MegaCore Function License 13 | -- Agreement, or other applicable license agreement, including, 14 | -- without limitation, that your use is for the sole purpose of 15 | -- programming logic devices manufactured by Altera and sold by 16 | -- Altera or its authorized distributors. Please refer to the 17 | -- applicable agreement for further details. 18 | 19 | 20 | FUNCTION cycloneive_ram_block (clk0, clk1, clr0, clr1, ena0, ena1, ena2, ena3, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portaaddrstall, portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portare, portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbaddrstall, portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbre, portbwe) 21 | WITH ( CLK0_CORE_CLOCK_ENABLE, CLK0_INPUT_CLOCK_ENABLE, CLK0_OUTPUT_CLOCK_ENABLE, CLK1_CORE_CLOCK_ENABLE, CLK1_INPUT_CLOCK_ENABLE, CLK1_OUTPUT_CLOCK_ENABLE, CONNECTIVITY_CHECKING, DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS, DONT_POWER_OPTIMIZE, INIT_FILE, INIT_FILE_LAYOUT, init_file_restructured, LOGICAL_RAM_NAME, mem_init0, mem_init1, mem_init2, mem_init3, mem_init4, MIXED_PORT_FEED_THROUGH_MODE, OPERATION_MODE, PORT_A_ADDRESS_CLEAR, PORT_A_ADDRESS_WIDTH = 1, PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, PORT_A_BYTE_SIZE, PORT_A_DATA_OUT_CLEAR, PORT_A_DATA_OUT_CLOCK, PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS, PORT_A_FIRST_BIT_NUMBER, PORT_A_LAST_ADDRESS, PORT_A_LOGICAL_RAM_DEPTH, PORT_A_LOGICAL_RAM_WIDTH, PORT_A_READ_DURING_WRITE_MODE, PORT_B_ADDRESS_CLEAR, PORT_B_ADDRESS_CLOCK, PORT_B_ADDRESS_WIDTH = 1, PORT_B_BYTE_ENABLE_CLOCK, PORT_B_BYTE_ENABLE_MASK_WIDTH = 1, PORT_B_BYTE_SIZE, PORT_B_DATA_IN_CLOCK, PORT_B_DATA_OUT_CLEAR, PORT_B_DATA_OUT_CLOCK, PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS, PORT_B_FIRST_BIT_NUMBER, PORT_B_LAST_ADDRESS, PORT_B_LOGICAL_RAM_DEPTH, PORT_B_LOGICAL_RAM_WIDTH, PORT_B_READ_DURING_WRITE_MODE, PORT_B_READ_ENABLE_CLOCK, PORT_B_WRITE_ENABLE_CLOCK, POWER_UP_UNINITIALIZED, RAM_BLOCK_TYPE, SAFE_WRITE, WIDTH_ECCSTATUS) 22 | RETURNS ( portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]); 23 | 24 | --synthesis_resources = M9K 1 25 | OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION"; 26 | 27 | SUBDESIGN altsyncram_9p91 28 | ( 29 | address_a[5..0] : input; 30 | clock0 : input; 31 | q_a[15..0] : output; 32 | ) 33 | VARIABLE 34 | ram_block1a0 : cycloneive_ram_block 35 | WITH ( 36 | CLK0_CORE_CLOCK_ENABLE = "none", 37 | CLK0_INPUT_CLOCK_ENABLE = "none", 38 | CLK0_OUTPUT_CLOCK_ENABLE = "none", 39 | CONNECTIVITY_CHECKING = "OFF", 40 | INIT_FILE = "wnp64relimg88.mif", 41 | INIT_FILE_LAYOUT = "port_a", 42 | LOGICAL_RAM_NAME = "ALTSYNCRAM", 43 | OPERATION_MODE = "rom", 44 | PORT_A_ADDRESS_CLEAR = "none", 45 | PORT_A_ADDRESS_WIDTH = 6, 46 | PORT_A_DATA_OUT_CLEAR = "none", 47 | PORT_A_DATA_OUT_CLOCK = "clock0", 48 | PORT_A_DATA_WIDTH = 1, 49 | PORT_A_FIRST_ADDRESS = 0, 50 | PORT_A_FIRST_BIT_NUMBER = 0, 51 | PORT_A_LAST_ADDRESS = 63, 52 | PORT_A_LOGICAL_RAM_DEPTH = 64, 53 | PORT_A_LOGICAL_RAM_WIDTH = 16, 54 | RAM_BLOCK_TYPE = "AUTO" 55 | ); 56 | ram_block1a1 : cycloneive_ram_block 57 | WITH ( 58 | CLK0_CORE_CLOCK_ENABLE = "none", 59 | CLK0_INPUT_CLOCK_ENABLE = "none", 60 | CLK0_OUTPUT_CLOCK_ENABLE = "none", 61 | CONNECTIVITY_CHECKING = "OFF", 62 | INIT_FILE = "wnp64relimg88.mif", 63 | INIT_FILE_LAYOUT = "port_a", 64 | LOGICAL_RAM_NAME = "ALTSYNCRAM", 65 | OPERATION_MODE = "rom", 66 | PORT_A_ADDRESS_CLEAR = "none", 67 | PORT_A_ADDRESS_WIDTH = 6, 68 | PORT_A_DATA_OUT_CLEAR = "none", 69 | PORT_A_DATA_OUT_CLOCK = "clock0", 70 | PORT_A_DATA_WIDTH = 1, 71 | PORT_A_FIRST_ADDRESS = 0, 72 | PORT_A_FIRST_BIT_NUMBER = 1, 73 | PORT_A_LAST_ADDRESS = 63, 74 | PORT_A_LOGICAL_RAM_DEPTH = 64, 75 | PORT_A_LOGICAL_RAM_WIDTH = 16, 76 | RAM_BLOCK_TYPE = "AUTO" 77 | ); 78 | ram_block1a2 : cycloneive_ram_block 79 | WITH ( 80 | CLK0_CORE_CLOCK_ENABLE = "none", 81 | CLK0_INPUT_CLOCK_ENABLE = "none", 82 | CLK0_OUTPUT_CLOCK_ENABLE = "none", 83 | CONNECTIVITY_CHECKING = "OFF", 84 | INIT_FILE = "wnp64relimg88.mif", 85 | INIT_FILE_LAYOUT = "port_a", 86 | LOGICAL_RAM_NAME = "ALTSYNCRAM", 87 | OPERATION_MODE = "rom", 88 | PORT_A_ADDRESS_CLEAR = "none", 89 | PORT_A_ADDRESS_WIDTH = 6, 90 | PORT_A_DATA_OUT_CLEAR = "none", 91 | PORT_A_DATA_OUT_CLOCK = "clock0", 92 | PORT_A_DATA_WIDTH = 1, 93 | PORT_A_FIRST_ADDRESS = 0, 94 | PORT_A_FIRST_BIT_NUMBER = 2, 95 | PORT_A_LAST_ADDRESS = 63, 96 | PORT_A_LOGICAL_RAM_DEPTH = 64, 97 | PORT_A_LOGICAL_RAM_WIDTH = 16, 98 | RAM_BLOCK_TYPE = "AUTO" 99 | ); 100 | ram_block1a3 : cycloneive_ram_block 101 | WITH ( 102 | CLK0_CORE_CLOCK_ENABLE = "none", 103 | CLK0_INPUT_CLOCK_ENABLE = "none", 104 | CLK0_OUTPUT_CLOCK_ENABLE = "none", 105 | CONNECTIVITY_CHECKING = "OFF", 106 | INIT_FILE = "wnp64relimg88.mif", 107 | INIT_FILE_LAYOUT = "port_a", 108 | LOGICAL_RAM_NAME = "ALTSYNCRAM", 109 | OPERATION_MODE = "rom", 110 | PORT_A_ADDRESS_CLEAR = "none", 111 | PORT_A_ADDRESS_WIDTH = 6, 112 | PORT_A_DATA_OUT_CLEAR = "none", 113 | PORT_A_DATA_OUT_CLOCK = "clock0", 114 | PORT_A_DATA_WIDTH = 1, 115 | PORT_A_FIRST_ADDRESS = 0, 116 | PORT_A_FIRST_BIT_NUMBER = 3, 117 | PORT_A_LAST_ADDRESS = 63, 118 | PORT_A_LOGICAL_RAM_DEPTH = 64, 119 | PORT_A_LOGICAL_RAM_WIDTH = 16, 120 | RAM_BLOCK_TYPE = "AUTO" 121 | ); 122 | ram_block1a4 : cycloneive_ram_block 123 | WITH ( 124 | CLK0_CORE_CLOCK_ENABLE = "none", 125 | CLK0_INPUT_CLOCK_ENABLE = "none", 126 | CLK0_OUTPUT_CLOCK_ENABLE = "none", 127 | CONNECTIVITY_CHECKING = "OFF", 128 | INIT_FILE = "wnp64relimg88.mif", 129 | INIT_FILE_LAYOUT = "port_a", 130 | LOGICAL_RAM_NAME = "ALTSYNCRAM", 131 | OPERATION_MODE = "rom", 132 | PORT_A_ADDRESS_CLEAR = "none", 133 | PORT_A_ADDRESS_WIDTH = 6, 134 | PORT_A_DATA_OUT_CLEAR = "none", 135 | PORT_A_DATA_OUT_CLOCK = "clock0", 136 | PORT_A_DATA_WIDTH = 1, 137 | PORT_A_FIRST_ADDRESS = 0, 138 | PORT_A_FIRST_BIT_NUMBER = 4, 139 | PORT_A_LAST_ADDRESS = 63, 140 | PORT_A_LOGICAL_RAM_DEPTH = 64, 141 | PORT_A_LOGICAL_RAM_WIDTH = 16, 142 | RAM_BLOCK_TYPE = "AUTO" 143 | ); 144 | ram_block1a5 : cycloneive_ram_block 145 | WITH ( 146 | CLK0_CORE_CLOCK_ENABLE = "none", 147 | CLK0_INPUT_CLOCK_ENABLE = "none", 148 | CLK0_OUTPUT_CLOCK_ENABLE = "none", 149 | CONNECTIVITY_CHECKING = "OFF", 150 | INIT_FILE = "wnp64relimg88.mif", 151 | INIT_FILE_LAYOUT = "port_a", 152 | LOGICAL_RAM_NAME = "ALTSYNCRAM", 153 | OPERATION_MODE = "rom", 154 | PORT_A_ADDRESS_CLEAR = "none", 155 | PORT_A_ADDRESS_WIDTH = 6, 156 | PORT_A_DATA_OUT_CLEAR = "none", 157 | PORT_A_DATA_OUT_CLOCK = "clock0", 158 | PORT_A_DATA_WIDTH = 1, 159 | PORT_A_FIRST_ADDRESS = 0, 160 | PORT_A_FIRST_BIT_NUMBER = 5, 161 | PORT_A_LAST_ADDRESS = 63, 162 | PORT_A_LOGICAL_RAM_DEPTH = 64, 163 | PORT_A_LOGICAL_RAM_WIDTH = 16, 164 | RAM_BLOCK_TYPE = "AUTO" 165 | ); 166 | ram_block1a6 : cycloneive_ram_block 167 | WITH ( 168 | CLK0_CORE_CLOCK_ENABLE = "none", 169 | CLK0_INPUT_CLOCK_ENABLE = "none", 170 | CLK0_OUTPUT_CLOCK_ENABLE = "none", 171 | CONNECTIVITY_CHECKING = "OFF", 172 | INIT_FILE = "wnp64relimg88.mif", 173 | INIT_FILE_LAYOUT = "port_a", 174 | LOGICAL_RAM_NAME = "ALTSYNCRAM", 175 | OPERATION_MODE = "rom", 176 | PORT_A_ADDRESS_CLEAR = "none", 177 | PORT_A_ADDRESS_WIDTH = 6, 178 | PORT_A_DATA_OUT_CLEAR = "none", 179 | PORT_A_DATA_OUT_CLOCK = "clock0", 180 | PORT_A_DATA_WIDTH = 1, 181 | PORT_A_FIRST_ADDRESS = 0, 182 | PORT_A_FIRST_BIT_NUMBER = 6, 183 | PORT_A_LAST_ADDRESS = 63, 184 | PORT_A_LOGICAL_RAM_DEPTH = 64, 185 | PORT_A_LOGICAL_RAM_WIDTH = 16, 186 | RAM_BLOCK_TYPE = "AUTO" 187 | ); 188 | ram_block1a7 : cycloneive_ram_block 189 | WITH ( 190 | CLK0_CORE_CLOCK_ENABLE = "none", 191 | CLK0_INPUT_CLOCK_ENABLE = "none", 192 | CLK0_OUTPUT_CLOCK_ENABLE = "none", 193 | CONNECTIVITY_CHECKING = "OFF", 194 | INIT_FILE = "wnp64relimg88.mif", 195 | INIT_FILE_LAYOUT = "port_a", 196 | LOGICAL_RAM_NAME = "ALTSYNCRAM", 197 | OPERATION_MODE = "rom", 198 | PORT_A_ADDRESS_CLEAR = "none", 199 | PORT_A_ADDRESS_WIDTH = 6, 200 | PORT_A_DATA_OUT_CLEAR = "none", 201 | PORT_A_DATA_OUT_CLOCK = "clock0", 202 | PORT_A_DATA_WIDTH = 1, 203 | PORT_A_FIRST_ADDRESS = 0, 204 | PORT_A_FIRST_BIT_NUMBER = 7, 205 | PORT_A_LAST_ADDRESS = 63, 206 | PORT_A_LOGICAL_RAM_DEPTH = 64, 207 | PORT_A_LOGICAL_RAM_WIDTH = 16, 208 | RAM_BLOCK_TYPE = "AUTO" 209 | ); 210 | ram_block1a8 : cycloneive_ram_block 211 | WITH ( 212 | CLK0_CORE_CLOCK_ENABLE = "none", 213 | CLK0_INPUT_CLOCK_ENABLE = "none", 214 | CLK0_OUTPUT_CLOCK_ENABLE = "none", 215 | CONNECTIVITY_CHECKING = "OFF", 216 | INIT_FILE = "wnp64relimg88.mif", 217 | INIT_FILE_LAYOUT = "port_a", 218 | LOGICAL_RAM_NAME = "ALTSYNCRAM", 219 | OPERATION_MODE = "rom", 220 | PORT_A_ADDRESS_CLEAR = "none", 221 | PORT_A_ADDRESS_WIDTH = 6, 222 | PORT_A_DATA_OUT_CLEAR = "none", 223 | PORT_A_DATA_OUT_CLOCK = "clock0", 224 | PORT_A_DATA_WIDTH = 1, 225 | PORT_A_FIRST_ADDRESS = 0, 226 | PORT_A_FIRST_BIT_NUMBER = 8, 227 | PORT_A_LAST_ADDRESS = 63, 228 | PORT_A_LOGICAL_RAM_DEPTH = 64, 229 | PORT_A_LOGICAL_RAM_WIDTH = 16, 230 | RAM_BLOCK_TYPE = "AUTO" 231 | ); 232 | ram_block1a9 : cycloneive_ram_block 233 | WITH ( 234 | CLK0_CORE_CLOCK_ENABLE = "none", 235 | CLK0_INPUT_CLOCK_ENABLE = "none", 236 | CLK0_OUTPUT_CLOCK_ENABLE = "none", 237 | CONNECTIVITY_CHECKING = "OFF", 238 | INIT_FILE = "wnp64relimg88.mif", 239 | INIT_FILE_LAYOUT = "port_a", 240 | LOGICAL_RAM_NAME = "ALTSYNCRAM", 241 | OPERATION_MODE = "rom", 242 | PORT_A_ADDRESS_CLEAR = "none", 243 | PORT_A_ADDRESS_WIDTH = 6, 244 | PORT_A_DATA_OUT_CLEAR = "none", 245 | PORT_A_DATA_OUT_CLOCK = "clock0", 246 | PORT_A_DATA_WIDTH = 1, 247 | PORT_A_FIRST_ADDRESS = 0, 248 | PORT_A_FIRST_BIT_NUMBER = 9, 249 | PORT_A_LAST_ADDRESS = 63, 250 | PORT_A_LOGICAL_RAM_DEPTH = 64, 251 | PORT_A_LOGICAL_RAM_WIDTH = 16, 252 | RAM_BLOCK_TYPE = "AUTO" 253 | ); 254 | ram_block1a10 : cycloneive_ram_block 255 | WITH ( 256 | CLK0_CORE_CLOCK_ENABLE = "none", 257 | CLK0_INPUT_CLOCK_ENABLE = "none", 258 | CLK0_OUTPUT_CLOCK_ENABLE = "none", 259 | CONNECTIVITY_CHECKING = "OFF", 260 | INIT_FILE = "wnp64relimg88.mif", 261 | INIT_FILE_LAYOUT = "port_a", 262 | LOGICAL_RAM_NAME = "ALTSYNCRAM", 263 | OPERATION_MODE = "rom", 264 | PORT_A_ADDRESS_CLEAR = "none", 265 | PORT_A_ADDRESS_WIDTH = 6, 266 | PORT_A_DATA_OUT_CLEAR = "none", 267 | PORT_A_DATA_OUT_CLOCK = "clock0", 268 | PORT_A_DATA_WIDTH = 1, 269 | PORT_A_FIRST_ADDRESS = 0, 270 | PORT_A_FIRST_BIT_NUMBER = 10, 271 | PORT_A_LAST_ADDRESS = 63, 272 | PORT_A_LOGICAL_RAM_DEPTH = 64, 273 | PORT_A_LOGICAL_RAM_WIDTH = 16, 274 | RAM_BLOCK_TYPE = "AUTO" 275 | ); 276 | ram_block1a11 : cycloneive_ram_block 277 | WITH ( 278 | CLK0_CORE_CLOCK_ENABLE = "none", 279 | CLK0_INPUT_CLOCK_ENABLE = "none", 280 | CLK0_OUTPUT_CLOCK_ENABLE = "none", 281 | CONNECTIVITY_CHECKING = "OFF", 282 | INIT_FILE = "wnp64relimg88.mif", 283 | INIT_FILE_LAYOUT = "port_a", 284 | LOGICAL_RAM_NAME = "ALTSYNCRAM", 285 | OPERATION_MODE = "rom", 286 | PORT_A_ADDRESS_CLEAR = "none", 287 | PORT_A_ADDRESS_WIDTH = 6, 288 | PORT_A_DATA_OUT_CLEAR = "none", 289 | PORT_A_DATA_OUT_CLOCK = "clock0", 290 | PORT_A_DATA_WIDTH = 1, 291 | PORT_A_FIRST_ADDRESS = 0, 292 | PORT_A_FIRST_BIT_NUMBER = 11, 293 | PORT_A_LAST_ADDRESS = 63, 294 | PORT_A_LOGICAL_RAM_DEPTH = 64, 295 | PORT_A_LOGICAL_RAM_WIDTH = 16, 296 | RAM_BLOCK_TYPE = "AUTO" 297 | ); 298 | ram_block1a12 : cycloneive_ram_block 299 | WITH ( 300 | CLK0_CORE_CLOCK_ENABLE = "none", 301 | CLK0_INPUT_CLOCK_ENABLE = "none", 302 | CLK0_OUTPUT_CLOCK_ENABLE = "none", 303 | CONNECTIVITY_CHECKING = "OFF", 304 | INIT_FILE = "wnp64relimg88.mif", 305 | INIT_FILE_LAYOUT = "port_a", 306 | LOGICAL_RAM_NAME = "ALTSYNCRAM", 307 | OPERATION_MODE = "rom", 308 | PORT_A_ADDRESS_CLEAR = "none", 309 | PORT_A_ADDRESS_WIDTH = 6, 310 | PORT_A_DATA_OUT_CLEAR = "none", 311 | PORT_A_DATA_OUT_CLOCK = "clock0", 312 | PORT_A_DATA_WIDTH = 1, 313 | PORT_A_FIRST_ADDRESS = 0, 314 | PORT_A_FIRST_BIT_NUMBER = 12, 315 | PORT_A_LAST_ADDRESS = 63, 316 | PORT_A_LOGICAL_RAM_DEPTH = 64, 317 | PORT_A_LOGICAL_RAM_WIDTH = 16, 318 | RAM_BLOCK_TYPE = "AUTO" 319 | ); 320 | ram_block1a13 : cycloneive_ram_block 321 | WITH ( 322 | CLK0_CORE_CLOCK_ENABLE = "none", 323 | CLK0_INPUT_CLOCK_ENABLE = "none", 324 | CLK0_OUTPUT_CLOCK_ENABLE = "none", 325 | CONNECTIVITY_CHECKING = "OFF", 326 | INIT_FILE = "wnp64relimg88.mif", 327 | INIT_FILE_LAYOUT = "port_a", 328 | LOGICAL_RAM_NAME = "ALTSYNCRAM", 329 | OPERATION_MODE = "rom", 330 | PORT_A_ADDRESS_CLEAR = "none", 331 | PORT_A_ADDRESS_WIDTH = 6, 332 | PORT_A_DATA_OUT_CLEAR = "none", 333 | PORT_A_DATA_OUT_CLOCK = "clock0", 334 | PORT_A_DATA_WIDTH = 1, 335 | PORT_A_FIRST_ADDRESS = 0, 336 | PORT_A_FIRST_BIT_NUMBER = 13, 337 | PORT_A_LAST_ADDRESS = 63, 338 | PORT_A_LOGICAL_RAM_DEPTH = 64, 339 | PORT_A_LOGICAL_RAM_WIDTH = 16, 340 | RAM_BLOCK_TYPE = "AUTO" 341 | ); 342 | ram_block1a14 : cycloneive_ram_block 343 | WITH ( 344 | CLK0_CORE_CLOCK_ENABLE = "none", 345 | CLK0_INPUT_CLOCK_ENABLE = "none", 346 | CLK0_OUTPUT_CLOCK_ENABLE = "none", 347 | CONNECTIVITY_CHECKING = "OFF", 348 | INIT_FILE = "wnp64relimg88.mif", 349 | INIT_FILE_LAYOUT = "port_a", 350 | LOGICAL_RAM_NAME = "ALTSYNCRAM", 351 | OPERATION_MODE = "rom", 352 | PORT_A_ADDRESS_CLEAR = "none", 353 | PORT_A_ADDRESS_WIDTH = 6, 354 | PORT_A_DATA_OUT_CLEAR = "none", 355 | PORT_A_DATA_OUT_CLOCK = "clock0", 356 | PORT_A_DATA_WIDTH = 1, 357 | PORT_A_FIRST_ADDRESS = 0, 358 | PORT_A_FIRST_BIT_NUMBER = 14, 359 | PORT_A_LAST_ADDRESS = 63, 360 | PORT_A_LOGICAL_RAM_DEPTH = 64, 361 | PORT_A_LOGICAL_RAM_WIDTH = 16, 362 | RAM_BLOCK_TYPE = "AUTO" 363 | ); 364 | ram_block1a15 : cycloneive_ram_block 365 | WITH ( 366 | CLK0_CORE_CLOCK_ENABLE = "none", 367 | CLK0_INPUT_CLOCK_ENABLE = "none", 368 | CLK0_OUTPUT_CLOCK_ENABLE = "none", 369 | CONNECTIVITY_CHECKING = "OFF", 370 | INIT_FILE = "wnp64relimg88.mif", 371 | INIT_FILE_LAYOUT = "port_a", 372 | LOGICAL_RAM_NAME = "ALTSYNCRAM", 373 | OPERATION_MODE = "rom", 374 | PORT_A_ADDRESS_CLEAR = "none", 375 | PORT_A_ADDRESS_WIDTH = 6, 376 | PORT_A_DATA_OUT_CLEAR = "none", 377 | PORT_A_DATA_OUT_CLOCK = "clock0", 378 | PORT_A_DATA_WIDTH = 1, 379 | PORT_A_FIRST_ADDRESS = 0, 380 | PORT_A_FIRST_BIT_NUMBER = 15, 381 | PORT_A_LAST_ADDRESS = 63, 382 | PORT_A_LOGICAL_RAM_DEPTH = 64, 383 | PORT_A_LOGICAL_RAM_WIDTH = 16, 384 | RAM_BLOCK_TYPE = "AUTO" 385 | ); 386 | address_a_wire[5..0] : WIRE; 387 | 388 | BEGIN 389 | ram_block1a[15..0].clk0 = clock0; 390 | ram_block1a[15..0].portaaddr[] = ( address_a_wire[5..0]); 391 | ram_block1a[15..0].portare = B"1111111111111111"; 392 | address_a_wire[] = address_a[]; 393 | q_a[] = ( ram_block1a[15..0].portadataout[0..0]); 394 | END; 395 | --VALID FILE 396 | -------------------------------------------------------------------------------- /FPGA_WORK/proj/db/altsyncram_j6g1.tdf: -------------------------------------------------------------------------------- 1 | --altsyncram CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CLOCK_ENABLE_INPUT_A="BYPASS" CLOCK_ENABLE_OUTPUT_A="BYPASS" CYCLONEII_M4K_COMPATIBILITY="ON" DEVICE_FAMILY="Cyclone IV E" ENABLE_RUNTIME_MOD="NO" LOW_POWER_MODE="AUTO" NUMWORDS_A=128 OPERATION_MODE="SINGLE_PORT" OUTDATA_ACLR_A="NONE" OUTDATA_REG_A="UNREGISTERED" POWER_UP_UNINITIALIZED="FALSE" read_during_write_mode_port_a="NEW_DATA_NO_NBE_READ" WIDTH_A=16 WIDTH_BYTEENA_A=1 WIDTHAD_A=7 address_a clock0 data_a q_a wren_a CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 2 | --VERSION_BEGIN 13.0 cbx_altsyncram 2013:04:24:18:08:47:SJ cbx_cycloneii 2013:04:24:18:08:47:SJ cbx_lpm_add_sub 2013:04:24:18:08:47:SJ cbx_lpm_compare 2013:04:24:18:08:47:SJ cbx_lpm_decode 2013:04:24:18:08:47:SJ cbx_lpm_mux 2013:04:24:18:08:47:SJ cbx_mgl 2013:04:24:18:11:10:SJ cbx_stratix 2013:04:24:18:08:47:SJ cbx_stratixii 2013:04:24:18:08:47:SJ cbx_stratixiii 2013:04:24:18:08:47:SJ cbx_stratixv 2013:04:24:18:08:47:SJ cbx_util_mgl 2013:04:24:18:08:47:SJ VERSION_END 3 | 4 | 5 | -- Copyright (C) 1991-2013 Altera Corporation 6 | -- Your use of Altera Corporation's design tools, logic functions 7 | -- and other software and tools, and its AMPP partner logic 8 | -- functions, and any output files from any of the foregoing 9 | -- (including device programming or simulation files), and any 10 | -- associated documentation or information are expressly subject 11 | -- to the terms and conditions of the Altera Program License 12 | -- Subscription Agreement, Altera MegaCore Function License 13 | -- Agreement, or other applicable license agreement, including, 14 | -- without limitation, that your use is for the sole purpose of 15 | -- programming logic devices manufactured by Altera and sold by 16 | -- Altera or its authorized distributors. Please refer to the 17 | -- applicable agreement for further details. 18 | 19 | 20 | FUNCTION cycloneive_ram_block (clk0, clk1, clr0, clr1, ena0, ena1, ena2, ena3, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portaaddrstall, portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portare, portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbaddrstall, portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbre, portbwe) 21 | WITH ( CLK0_CORE_CLOCK_ENABLE, CLK0_INPUT_CLOCK_ENABLE, CLK0_OUTPUT_CLOCK_ENABLE, CLK1_CORE_CLOCK_ENABLE, CLK1_INPUT_CLOCK_ENABLE, CLK1_OUTPUT_CLOCK_ENABLE, CONNECTIVITY_CHECKING, DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS, DONT_POWER_OPTIMIZE, INIT_FILE, INIT_FILE_LAYOUT, init_file_restructured, LOGICAL_RAM_NAME, mem_init0, mem_init1, mem_init2, mem_init3, mem_init4, MIXED_PORT_FEED_THROUGH_MODE, OPERATION_MODE, PORT_A_ADDRESS_CLEAR, PORT_A_ADDRESS_WIDTH = 1, PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, PORT_A_BYTE_SIZE, PORT_A_DATA_OUT_CLEAR, PORT_A_DATA_OUT_CLOCK, PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS, PORT_A_FIRST_BIT_NUMBER, PORT_A_LAST_ADDRESS, PORT_A_LOGICAL_RAM_DEPTH, PORT_A_LOGICAL_RAM_WIDTH, PORT_A_READ_DURING_WRITE_MODE, PORT_B_ADDRESS_CLEAR, PORT_B_ADDRESS_CLOCK, PORT_B_ADDRESS_WIDTH = 1, PORT_B_BYTE_ENABLE_CLOCK, PORT_B_BYTE_ENABLE_MASK_WIDTH = 1, PORT_B_BYTE_SIZE, PORT_B_DATA_IN_CLOCK, PORT_B_DATA_OUT_CLEAR, PORT_B_DATA_OUT_CLOCK, PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS, PORT_B_FIRST_BIT_NUMBER, PORT_B_LAST_ADDRESS, PORT_B_LOGICAL_RAM_DEPTH, PORT_B_LOGICAL_RAM_WIDTH, PORT_B_READ_DURING_WRITE_MODE, PORT_B_READ_ENABLE_CLOCK, PORT_B_WRITE_ENABLE_CLOCK, POWER_UP_UNINITIALIZED, RAM_BLOCK_TYPE, SAFE_WRITE, WIDTH_ECCSTATUS) 22 | RETURNS ( portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]); 23 | 24 | --synthesis_resources = M9K 1 25 | OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION"; 26 | 27 | SUBDESIGN altsyncram_j6g1 28 | ( 29 | address_a[6..0] : input; 30 | clock0 : input; 31 | data_a[15..0] : input; 32 | q_a[15..0] : output; 33 | wren_a : input; 34 | ) 35 | VARIABLE 36 | ram_block1a0 : cycloneive_ram_block 37 | WITH ( 38 | CLK0_CORE_CLOCK_ENABLE = "none", 39 | CLK0_INPUT_CLOCK_ENABLE = "none", 40 | CONNECTIVITY_CHECKING = "OFF", 41 | LOGICAL_RAM_NAME = "ALTSYNCRAM", 42 | OPERATION_MODE = "single_port", 43 | PORT_A_ADDRESS_WIDTH = 7, 44 | PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, 45 | PORT_A_BYTE_SIZE = 1, 46 | PORT_A_DATA_OUT_CLEAR = "none", 47 | PORT_A_DATA_OUT_CLOCK = "none", 48 | PORT_A_DATA_WIDTH = 1, 49 | PORT_A_FIRST_ADDRESS = 0, 50 | PORT_A_FIRST_BIT_NUMBER = 0, 51 | PORT_A_LAST_ADDRESS = 127, 52 | PORT_A_LOGICAL_RAM_DEPTH = 128, 53 | PORT_A_LOGICAL_RAM_WIDTH = 16, 54 | PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", 55 | POWER_UP_UNINITIALIZED = "false", 56 | RAM_BLOCK_TYPE = "AUTO" 57 | ); 58 | ram_block1a1 : cycloneive_ram_block 59 | WITH ( 60 | CLK0_CORE_CLOCK_ENABLE = "none", 61 | CLK0_INPUT_CLOCK_ENABLE = "none", 62 | CONNECTIVITY_CHECKING = "OFF", 63 | LOGICAL_RAM_NAME = "ALTSYNCRAM", 64 | OPERATION_MODE = "single_port", 65 | PORT_A_ADDRESS_WIDTH = 7, 66 | PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, 67 | PORT_A_BYTE_SIZE = 1, 68 | PORT_A_DATA_OUT_CLEAR = "none", 69 | PORT_A_DATA_OUT_CLOCK = "none", 70 | PORT_A_DATA_WIDTH = 1, 71 | PORT_A_FIRST_ADDRESS = 0, 72 | PORT_A_FIRST_BIT_NUMBER = 1, 73 | PORT_A_LAST_ADDRESS = 127, 74 | PORT_A_LOGICAL_RAM_DEPTH = 128, 75 | PORT_A_LOGICAL_RAM_WIDTH = 16, 76 | PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", 77 | POWER_UP_UNINITIALIZED = "false", 78 | RAM_BLOCK_TYPE = "AUTO" 79 | ); 80 | ram_block1a2 : cycloneive_ram_block 81 | WITH ( 82 | CLK0_CORE_CLOCK_ENABLE = "none", 83 | CLK0_INPUT_CLOCK_ENABLE = "none", 84 | CONNECTIVITY_CHECKING = "OFF", 85 | LOGICAL_RAM_NAME = "ALTSYNCRAM", 86 | OPERATION_MODE = "single_port", 87 | PORT_A_ADDRESS_WIDTH = 7, 88 | PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, 89 | PORT_A_BYTE_SIZE = 1, 90 | PORT_A_DATA_OUT_CLEAR = "none", 91 | PORT_A_DATA_OUT_CLOCK = "none", 92 | PORT_A_DATA_WIDTH = 1, 93 | PORT_A_FIRST_ADDRESS = 0, 94 | PORT_A_FIRST_BIT_NUMBER = 2, 95 | PORT_A_LAST_ADDRESS = 127, 96 | PORT_A_LOGICAL_RAM_DEPTH = 128, 97 | PORT_A_LOGICAL_RAM_WIDTH = 16, 98 | PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", 99 | POWER_UP_UNINITIALIZED = "false", 100 | RAM_BLOCK_TYPE = "AUTO" 101 | ); 102 | ram_block1a3 : cycloneive_ram_block 103 | WITH ( 104 | CLK0_CORE_CLOCK_ENABLE = "none", 105 | CLK0_INPUT_CLOCK_ENABLE = "none", 106 | CONNECTIVITY_CHECKING = "OFF", 107 | LOGICAL_RAM_NAME = "ALTSYNCRAM", 108 | OPERATION_MODE = "single_port", 109 | PORT_A_ADDRESS_WIDTH = 7, 110 | PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, 111 | PORT_A_BYTE_SIZE = 1, 112 | PORT_A_DATA_OUT_CLEAR = "none", 113 | PORT_A_DATA_OUT_CLOCK = "none", 114 | PORT_A_DATA_WIDTH = 1, 115 | PORT_A_FIRST_ADDRESS = 0, 116 | PORT_A_FIRST_BIT_NUMBER = 3, 117 | PORT_A_LAST_ADDRESS = 127, 118 | PORT_A_LOGICAL_RAM_DEPTH = 128, 119 | PORT_A_LOGICAL_RAM_WIDTH = 16, 120 | PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", 121 | POWER_UP_UNINITIALIZED = "false", 122 | RAM_BLOCK_TYPE = "AUTO" 123 | ); 124 | ram_block1a4 : cycloneive_ram_block 125 | WITH ( 126 | CLK0_CORE_CLOCK_ENABLE = "none", 127 | CLK0_INPUT_CLOCK_ENABLE = "none", 128 | CONNECTIVITY_CHECKING = "OFF", 129 | LOGICAL_RAM_NAME = "ALTSYNCRAM", 130 | OPERATION_MODE = "single_port", 131 | PORT_A_ADDRESS_WIDTH = 7, 132 | PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, 133 | PORT_A_BYTE_SIZE = 1, 134 | PORT_A_DATA_OUT_CLEAR = "none", 135 | PORT_A_DATA_OUT_CLOCK = "none", 136 | PORT_A_DATA_WIDTH = 1, 137 | PORT_A_FIRST_ADDRESS = 0, 138 | PORT_A_FIRST_BIT_NUMBER = 4, 139 | PORT_A_LAST_ADDRESS = 127, 140 | PORT_A_LOGICAL_RAM_DEPTH = 128, 141 | PORT_A_LOGICAL_RAM_WIDTH = 16, 142 | PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", 143 | POWER_UP_UNINITIALIZED = "false", 144 | RAM_BLOCK_TYPE = "AUTO" 145 | ); 146 | ram_block1a5 : cycloneive_ram_block 147 | WITH ( 148 | CLK0_CORE_CLOCK_ENABLE = "none", 149 | CLK0_INPUT_CLOCK_ENABLE = "none", 150 | CONNECTIVITY_CHECKING = "OFF", 151 | LOGICAL_RAM_NAME = "ALTSYNCRAM", 152 | OPERATION_MODE = "single_port", 153 | PORT_A_ADDRESS_WIDTH = 7, 154 | PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, 155 | PORT_A_BYTE_SIZE = 1, 156 | PORT_A_DATA_OUT_CLEAR = "none", 157 | PORT_A_DATA_OUT_CLOCK = "none", 158 | PORT_A_DATA_WIDTH = 1, 159 | PORT_A_FIRST_ADDRESS = 0, 160 | PORT_A_FIRST_BIT_NUMBER = 5, 161 | PORT_A_LAST_ADDRESS = 127, 162 | PORT_A_LOGICAL_RAM_DEPTH = 128, 163 | PORT_A_LOGICAL_RAM_WIDTH = 16, 164 | PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", 165 | POWER_UP_UNINITIALIZED = "false", 166 | RAM_BLOCK_TYPE = "AUTO" 167 | ); 168 | ram_block1a6 : cycloneive_ram_block 169 | WITH ( 170 | CLK0_CORE_CLOCK_ENABLE = "none", 171 | CLK0_INPUT_CLOCK_ENABLE = "none", 172 | CONNECTIVITY_CHECKING = "OFF", 173 | LOGICAL_RAM_NAME = "ALTSYNCRAM", 174 | OPERATION_MODE = "single_port", 175 | PORT_A_ADDRESS_WIDTH = 7, 176 | PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, 177 | PORT_A_BYTE_SIZE = 1, 178 | PORT_A_DATA_OUT_CLEAR = "none", 179 | PORT_A_DATA_OUT_CLOCK = "none", 180 | PORT_A_DATA_WIDTH = 1, 181 | PORT_A_FIRST_ADDRESS = 0, 182 | PORT_A_FIRST_BIT_NUMBER = 6, 183 | PORT_A_LAST_ADDRESS = 127, 184 | PORT_A_LOGICAL_RAM_DEPTH = 128, 185 | PORT_A_LOGICAL_RAM_WIDTH = 16, 186 | PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", 187 | POWER_UP_UNINITIALIZED = "false", 188 | RAM_BLOCK_TYPE = "AUTO" 189 | ); 190 | ram_block1a7 : cycloneive_ram_block 191 | WITH ( 192 | CLK0_CORE_CLOCK_ENABLE = "none", 193 | CLK0_INPUT_CLOCK_ENABLE = "none", 194 | CONNECTIVITY_CHECKING = "OFF", 195 | LOGICAL_RAM_NAME = "ALTSYNCRAM", 196 | OPERATION_MODE = "single_port", 197 | PORT_A_ADDRESS_WIDTH = 7, 198 | PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, 199 | PORT_A_BYTE_SIZE = 1, 200 | PORT_A_DATA_OUT_CLEAR = "none", 201 | PORT_A_DATA_OUT_CLOCK = "none", 202 | PORT_A_DATA_WIDTH = 1, 203 | PORT_A_FIRST_ADDRESS = 0, 204 | PORT_A_FIRST_BIT_NUMBER = 7, 205 | PORT_A_LAST_ADDRESS = 127, 206 | PORT_A_LOGICAL_RAM_DEPTH = 128, 207 | PORT_A_LOGICAL_RAM_WIDTH = 16, 208 | PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", 209 | POWER_UP_UNINITIALIZED = "false", 210 | RAM_BLOCK_TYPE = "AUTO" 211 | ); 212 | ram_block1a8 : cycloneive_ram_block 213 | WITH ( 214 | CLK0_CORE_CLOCK_ENABLE = "none", 215 | CLK0_INPUT_CLOCK_ENABLE = "none", 216 | CONNECTIVITY_CHECKING = "OFF", 217 | LOGICAL_RAM_NAME = "ALTSYNCRAM", 218 | OPERATION_MODE = "single_port", 219 | PORT_A_ADDRESS_WIDTH = 7, 220 | PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, 221 | PORT_A_BYTE_SIZE = 1, 222 | PORT_A_DATA_OUT_CLEAR = "none", 223 | PORT_A_DATA_OUT_CLOCK = "none", 224 | PORT_A_DATA_WIDTH = 1, 225 | PORT_A_FIRST_ADDRESS = 0, 226 | PORT_A_FIRST_BIT_NUMBER = 8, 227 | PORT_A_LAST_ADDRESS = 127, 228 | PORT_A_LOGICAL_RAM_DEPTH = 128, 229 | PORT_A_LOGICAL_RAM_WIDTH = 16, 230 | PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", 231 | POWER_UP_UNINITIALIZED = "false", 232 | RAM_BLOCK_TYPE = "AUTO" 233 | ); 234 | ram_block1a9 : cycloneive_ram_block 235 | WITH ( 236 | CLK0_CORE_CLOCK_ENABLE = "none", 237 | CLK0_INPUT_CLOCK_ENABLE = "none", 238 | CONNECTIVITY_CHECKING = "OFF", 239 | LOGICAL_RAM_NAME = "ALTSYNCRAM", 240 | OPERATION_MODE = "single_port", 241 | PORT_A_ADDRESS_WIDTH = 7, 242 | PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, 243 | PORT_A_BYTE_SIZE = 1, 244 | PORT_A_DATA_OUT_CLEAR = "none", 245 | PORT_A_DATA_OUT_CLOCK = "none", 246 | PORT_A_DATA_WIDTH = 1, 247 | PORT_A_FIRST_ADDRESS = 0, 248 | PORT_A_FIRST_BIT_NUMBER = 9, 249 | PORT_A_LAST_ADDRESS = 127, 250 | PORT_A_LOGICAL_RAM_DEPTH = 128, 251 | PORT_A_LOGICAL_RAM_WIDTH = 16, 252 | PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", 253 | POWER_UP_UNINITIALIZED = "false", 254 | RAM_BLOCK_TYPE = "AUTO" 255 | ); 256 | ram_block1a10 : cycloneive_ram_block 257 | WITH ( 258 | CLK0_CORE_CLOCK_ENABLE = "none", 259 | CLK0_INPUT_CLOCK_ENABLE = "none", 260 | CONNECTIVITY_CHECKING = "OFF", 261 | LOGICAL_RAM_NAME = "ALTSYNCRAM", 262 | OPERATION_MODE = "single_port", 263 | PORT_A_ADDRESS_WIDTH = 7, 264 | PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, 265 | PORT_A_BYTE_SIZE = 1, 266 | PORT_A_DATA_OUT_CLEAR = "none", 267 | PORT_A_DATA_OUT_CLOCK = "none", 268 | PORT_A_DATA_WIDTH = 1, 269 | PORT_A_FIRST_ADDRESS = 0, 270 | PORT_A_FIRST_BIT_NUMBER = 10, 271 | PORT_A_LAST_ADDRESS = 127, 272 | PORT_A_LOGICAL_RAM_DEPTH = 128, 273 | PORT_A_LOGICAL_RAM_WIDTH = 16, 274 | PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", 275 | POWER_UP_UNINITIALIZED = "false", 276 | RAM_BLOCK_TYPE = "AUTO" 277 | ); 278 | ram_block1a11 : cycloneive_ram_block 279 | WITH ( 280 | CLK0_CORE_CLOCK_ENABLE = "none", 281 | CLK0_INPUT_CLOCK_ENABLE = "none", 282 | CONNECTIVITY_CHECKING = "OFF", 283 | LOGICAL_RAM_NAME = "ALTSYNCRAM", 284 | OPERATION_MODE = "single_port", 285 | PORT_A_ADDRESS_WIDTH = 7, 286 | PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, 287 | PORT_A_BYTE_SIZE = 1, 288 | PORT_A_DATA_OUT_CLEAR = "none", 289 | PORT_A_DATA_OUT_CLOCK = "none", 290 | PORT_A_DATA_WIDTH = 1, 291 | PORT_A_FIRST_ADDRESS = 0, 292 | PORT_A_FIRST_BIT_NUMBER = 11, 293 | PORT_A_LAST_ADDRESS = 127, 294 | PORT_A_LOGICAL_RAM_DEPTH = 128, 295 | PORT_A_LOGICAL_RAM_WIDTH = 16, 296 | PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", 297 | POWER_UP_UNINITIALIZED = "false", 298 | RAM_BLOCK_TYPE = "AUTO" 299 | ); 300 | ram_block1a12 : cycloneive_ram_block 301 | WITH ( 302 | CLK0_CORE_CLOCK_ENABLE = "none", 303 | CLK0_INPUT_CLOCK_ENABLE = "none", 304 | CONNECTIVITY_CHECKING = "OFF", 305 | LOGICAL_RAM_NAME = "ALTSYNCRAM", 306 | OPERATION_MODE = "single_port", 307 | PORT_A_ADDRESS_WIDTH = 7, 308 | PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, 309 | PORT_A_BYTE_SIZE = 1, 310 | PORT_A_DATA_OUT_CLEAR = "none", 311 | PORT_A_DATA_OUT_CLOCK = "none", 312 | PORT_A_DATA_WIDTH = 1, 313 | PORT_A_FIRST_ADDRESS = 0, 314 | PORT_A_FIRST_BIT_NUMBER = 12, 315 | PORT_A_LAST_ADDRESS = 127, 316 | PORT_A_LOGICAL_RAM_DEPTH = 128, 317 | PORT_A_LOGICAL_RAM_WIDTH = 16, 318 | PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", 319 | POWER_UP_UNINITIALIZED = "false", 320 | RAM_BLOCK_TYPE = "AUTO" 321 | ); 322 | ram_block1a13 : cycloneive_ram_block 323 | WITH ( 324 | CLK0_CORE_CLOCK_ENABLE = "none", 325 | CLK0_INPUT_CLOCK_ENABLE = "none", 326 | CONNECTIVITY_CHECKING = "OFF", 327 | LOGICAL_RAM_NAME = "ALTSYNCRAM", 328 | OPERATION_MODE = "single_port", 329 | PORT_A_ADDRESS_WIDTH = 7, 330 | PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, 331 | PORT_A_BYTE_SIZE = 1, 332 | PORT_A_DATA_OUT_CLEAR = "none", 333 | PORT_A_DATA_OUT_CLOCK = "none", 334 | PORT_A_DATA_WIDTH = 1, 335 | PORT_A_FIRST_ADDRESS = 0, 336 | PORT_A_FIRST_BIT_NUMBER = 13, 337 | PORT_A_LAST_ADDRESS = 127, 338 | PORT_A_LOGICAL_RAM_DEPTH = 128, 339 | PORT_A_LOGICAL_RAM_WIDTH = 16, 340 | PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", 341 | POWER_UP_UNINITIALIZED = "false", 342 | RAM_BLOCK_TYPE = "AUTO" 343 | ); 344 | ram_block1a14 : cycloneive_ram_block 345 | WITH ( 346 | CLK0_CORE_CLOCK_ENABLE = "none", 347 | CLK0_INPUT_CLOCK_ENABLE = "none", 348 | CONNECTIVITY_CHECKING = "OFF", 349 | LOGICAL_RAM_NAME = "ALTSYNCRAM", 350 | OPERATION_MODE = "single_port", 351 | PORT_A_ADDRESS_WIDTH = 7, 352 | PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, 353 | PORT_A_BYTE_SIZE = 1, 354 | PORT_A_DATA_OUT_CLEAR = "none", 355 | PORT_A_DATA_OUT_CLOCK = "none", 356 | PORT_A_DATA_WIDTH = 1, 357 | PORT_A_FIRST_ADDRESS = 0, 358 | PORT_A_FIRST_BIT_NUMBER = 14, 359 | PORT_A_LAST_ADDRESS = 127, 360 | PORT_A_LOGICAL_RAM_DEPTH = 128, 361 | PORT_A_LOGICAL_RAM_WIDTH = 16, 362 | PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", 363 | POWER_UP_UNINITIALIZED = "false", 364 | RAM_BLOCK_TYPE = "AUTO" 365 | ); 366 | ram_block1a15 : cycloneive_ram_block 367 | WITH ( 368 | CLK0_CORE_CLOCK_ENABLE = "none", 369 | CLK0_INPUT_CLOCK_ENABLE = "none", 370 | CONNECTIVITY_CHECKING = "OFF", 371 | LOGICAL_RAM_NAME = "ALTSYNCRAM", 372 | OPERATION_MODE = "single_port", 373 | PORT_A_ADDRESS_WIDTH = 7, 374 | PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, 375 | PORT_A_BYTE_SIZE = 1, 376 | PORT_A_DATA_OUT_CLEAR = "none", 377 | PORT_A_DATA_OUT_CLOCK = "none", 378 | PORT_A_DATA_WIDTH = 1, 379 | PORT_A_FIRST_ADDRESS = 0, 380 | PORT_A_FIRST_BIT_NUMBER = 15, 381 | PORT_A_LAST_ADDRESS = 127, 382 | PORT_A_LOGICAL_RAM_DEPTH = 128, 383 | PORT_A_LOGICAL_RAM_WIDTH = 16, 384 | PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", 385 | POWER_UP_UNINITIALIZED = "false", 386 | RAM_BLOCK_TYPE = "AUTO" 387 | ); 388 | address_a_wire[6..0] : WIRE; 389 | 390 | BEGIN 391 | ram_block1a[15..0].clk0 = clock0; 392 | ram_block1a[15..0].portaaddr[] = ( address_a_wire[6..0]); 393 | ram_block1a[0].portadatain[] = ( data_a[0..0]); 394 | ram_block1a[1].portadatain[] = ( data_a[1..1]); 395 | ram_block1a[2].portadatain[] = ( data_a[2..2]); 396 | ram_block1a[3].portadatain[] = ( data_a[3..3]); 397 | ram_block1a[4].portadatain[] = ( data_a[4..4]); 398 | ram_block1a[5].portadatain[] = ( data_a[5..5]); 399 | ram_block1a[6].portadatain[] = ( data_a[6..6]); 400 | ram_block1a[7].portadatain[] = ( data_a[7..7]); 401 | ram_block1a[8].portadatain[] = ( data_a[8..8]); 402 | ram_block1a[9].portadatain[] = ( data_a[9..9]); 403 | ram_block1a[10].portadatain[] = ( data_a[10..10]); 404 | ram_block1a[11].portadatain[] = ( data_a[11..11]); 405 | ram_block1a[12].portadatain[] = ( data_a[12..12]); 406 | ram_block1a[13].portadatain[] = ( data_a[13..13]); 407 | ram_block1a[14].portadatain[] = ( data_a[14..14]); 408 | ram_block1a[15].portadatain[] = ( data_a[15..15]); 409 | ram_block1a[15..0].portare = B"1111111111111111"; 410 | ram_block1a[15..0].portawe = wren_a; 411 | address_a_wire[] = address_a[]; 412 | q_a[] = ( ram_block1a[15..0].portadataout[0..0]); 413 | END; 414 | --VALID FILE 415 | -------------------------------------------------------------------------------- /FPGA_WORK/proj/db/altsyncram_kt91.tdf: -------------------------------------------------------------------------------- 1 | --altsyncram ADDRESS_ACLR_A="NONE" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CLOCK_ENABLE_INPUT_A="BYPASS" CLOCK_ENABLE_OUTPUT_A="BYPASS" CYCLONEII_M4K_COMPATIBILITY="ON" DEVICE_FAMILY="Cyclone IV E" ENABLE_RUNTIME_MOD="NO" INIT_FILE="../wnp64relimg88.mif" LOW_POWER_MODE="AUTO" NUMWORDS_A=64 OPERATION_MODE="ROM" OUTDATA_ACLR_A="NONE" OUTDATA_REG_A="CLOCK0" WIDTH_A=16 WIDTH_BYTEENA_A=1 WIDTHAD_A=6 address_a clock0 q_a CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 2 | --VERSION_BEGIN 13.0 cbx_altsyncram 2013:04:24:18:08:47:SJ cbx_cycloneii 2013:04:24:18:08:47:SJ cbx_lpm_add_sub 2013:04:24:18:08:47:SJ cbx_lpm_compare 2013:04:24:18:08:47:SJ cbx_lpm_decode 2013:04:24:18:08:47:SJ cbx_lpm_mux 2013:04:24:18:08:47:SJ cbx_mgl 2013:04:24:18:11:10:SJ cbx_stratix 2013:04:24:18:08:47:SJ cbx_stratixii 2013:04:24:18:08:47:SJ cbx_stratixiii 2013:04:24:18:08:47:SJ cbx_stratixv 2013:04:24:18:08:47:SJ cbx_util_mgl 2013:04:24:18:08:47:SJ VERSION_END 3 | 4 | 5 | -- Copyright (C) 1991-2013 Altera Corporation 6 | -- Your use of Altera Corporation's design tools, logic functions 7 | -- and other software and tools, and its AMPP partner logic 8 | -- functions, and any output files from any of the foregoing 9 | -- (including device programming or simulation files), and any 10 | -- associated documentation or information are expressly subject 11 | -- to the terms and conditions of the Altera Program License 12 | -- Subscription Agreement, Altera MegaCore Function License 13 | -- Agreement, or other applicable license agreement, including, 14 | -- without limitation, that your use is for the sole purpose of 15 | -- programming logic devices manufactured by Altera and sold by 16 | -- Altera or its authorized distributors. Please refer to the 17 | -- applicable agreement for further details. 18 | 19 | 20 | FUNCTION cycloneive_ram_block (clk0, clk1, clr0, clr1, ena0, ena1, ena2, ena3, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portaaddrstall, portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portare, portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbaddrstall, portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbre, portbwe) 21 | WITH ( CLK0_CORE_CLOCK_ENABLE, CLK0_INPUT_CLOCK_ENABLE, CLK0_OUTPUT_CLOCK_ENABLE, CLK1_CORE_CLOCK_ENABLE, CLK1_INPUT_CLOCK_ENABLE, CLK1_OUTPUT_CLOCK_ENABLE, CONNECTIVITY_CHECKING, DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS, DONT_POWER_OPTIMIZE, INIT_FILE, INIT_FILE_LAYOUT, init_file_restructured, LOGICAL_RAM_NAME, mem_init0, mem_init1, mem_init2, mem_init3, mem_init4, MIXED_PORT_FEED_THROUGH_MODE, OPERATION_MODE, PORT_A_ADDRESS_CLEAR, PORT_A_ADDRESS_WIDTH = 1, PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, PORT_A_BYTE_SIZE, PORT_A_DATA_OUT_CLEAR, PORT_A_DATA_OUT_CLOCK, PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS, PORT_A_FIRST_BIT_NUMBER, PORT_A_LAST_ADDRESS, PORT_A_LOGICAL_RAM_DEPTH, PORT_A_LOGICAL_RAM_WIDTH, PORT_A_READ_DURING_WRITE_MODE, PORT_B_ADDRESS_CLEAR, PORT_B_ADDRESS_CLOCK, PORT_B_ADDRESS_WIDTH = 1, PORT_B_BYTE_ENABLE_CLOCK, PORT_B_BYTE_ENABLE_MASK_WIDTH = 1, PORT_B_BYTE_SIZE, PORT_B_DATA_IN_CLOCK, PORT_B_DATA_OUT_CLEAR, PORT_B_DATA_OUT_CLOCK, PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS, PORT_B_FIRST_BIT_NUMBER, PORT_B_LAST_ADDRESS, PORT_B_LOGICAL_RAM_DEPTH, PORT_B_LOGICAL_RAM_WIDTH, PORT_B_READ_DURING_WRITE_MODE, PORT_B_READ_ENABLE_CLOCK, PORT_B_WRITE_ENABLE_CLOCK, POWER_UP_UNINITIALIZED, RAM_BLOCK_TYPE, SAFE_WRITE, WIDTH_ECCSTATUS) 22 | RETURNS ( portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]); 23 | 24 | --synthesis_resources = M9K 1 25 | OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION"; 26 | 27 | SUBDESIGN altsyncram_kt91 28 | ( 29 | address_a[5..0] : input; 30 | clock0 : input; 31 | q_a[15..0] : output; 32 | ) 33 | VARIABLE 34 | ram_block1a0 : cycloneive_ram_block 35 | WITH ( 36 | CLK0_CORE_CLOCK_ENABLE = "none", 37 | CLK0_INPUT_CLOCK_ENABLE = "none", 38 | CLK0_OUTPUT_CLOCK_ENABLE = "none", 39 | CONNECTIVITY_CHECKING = "OFF", 40 | INIT_FILE = "../wnp64relimg88.mif", 41 | INIT_FILE_LAYOUT = "port_a", 42 | LOGICAL_RAM_NAME = "ALTSYNCRAM", 43 | OPERATION_MODE = "rom", 44 | PORT_A_ADDRESS_CLEAR = "none", 45 | PORT_A_ADDRESS_WIDTH = 6, 46 | PORT_A_DATA_OUT_CLEAR = "none", 47 | PORT_A_DATA_OUT_CLOCK = "clock0", 48 | PORT_A_DATA_WIDTH = 1, 49 | PORT_A_FIRST_ADDRESS = 0, 50 | PORT_A_FIRST_BIT_NUMBER = 0, 51 | PORT_A_LAST_ADDRESS = 63, 52 | PORT_A_LOGICAL_RAM_DEPTH = 64, 53 | PORT_A_LOGICAL_RAM_WIDTH = 16, 54 | RAM_BLOCK_TYPE = "AUTO" 55 | ); 56 | ram_block1a1 : cycloneive_ram_block 57 | WITH ( 58 | CLK0_CORE_CLOCK_ENABLE = "none", 59 | CLK0_INPUT_CLOCK_ENABLE = "none", 60 | CLK0_OUTPUT_CLOCK_ENABLE = "none", 61 | CONNECTIVITY_CHECKING = "OFF", 62 | INIT_FILE = "../wnp64relimg88.mif", 63 | INIT_FILE_LAYOUT = "port_a", 64 | LOGICAL_RAM_NAME = "ALTSYNCRAM", 65 | OPERATION_MODE = "rom", 66 | PORT_A_ADDRESS_CLEAR = "none", 67 | PORT_A_ADDRESS_WIDTH = 6, 68 | PORT_A_DATA_OUT_CLEAR = "none", 69 | PORT_A_DATA_OUT_CLOCK = "clock0", 70 | PORT_A_DATA_WIDTH = 1, 71 | PORT_A_FIRST_ADDRESS = 0, 72 | PORT_A_FIRST_BIT_NUMBER = 1, 73 | PORT_A_LAST_ADDRESS = 63, 74 | PORT_A_LOGICAL_RAM_DEPTH = 64, 75 | PORT_A_LOGICAL_RAM_WIDTH = 16, 76 | RAM_BLOCK_TYPE = "AUTO" 77 | ); 78 | ram_block1a2 : cycloneive_ram_block 79 | WITH ( 80 | CLK0_CORE_CLOCK_ENABLE = "none", 81 | CLK0_INPUT_CLOCK_ENABLE = "none", 82 | CLK0_OUTPUT_CLOCK_ENABLE = "none", 83 | CONNECTIVITY_CHECKING = "OFF", 84 | INIT_FILE = "../wnp64relimg88.mif", 85 | INIT_FILE_LAYOUT = "port_a", 86 | LOGICAL_RAM_NAME = "ALTSYNCRAM", 87 | OPERATION_MODE = "rom", 88 | PORT_A_ADDRESS_CLEAR = "none", 89 | PORT_A_ADDRESS_WIDTH = 6, 90 | PORT_A_DATA_OUT_CLEAR = "none", 91 | PORT_A_DATA_OUT_CLOCK = "clock0", 92 | PORT_A_DATA_WIDTH = 1, 93 | PORT_A_FIRST_ADDRESS = 0, 94 | PORT_A_FIRST_BIT_NUMBER = 2, 95 | PORT_A_LAST_ADDRESS = 63, 96 | PORT_A_LOGICAL_RAM_DEPTH = 64, 97 | PORT_A_LOGICAL_RAM_WIDTH = 16, 98 | RAM_BLOCK_TYPE = "AUTO" 99 | ); 100 | ram_block1a3 : cycloneive_ram_block 101 | WITH ( 102 | CLK0_CORE_CLOCK_ENABLE = "none", 103 | CLK0_INPUT_CLOCK_ENABLE = "none", 104 | CLK0_OUTPUT_CLOCK_ENABLE = "none", 105 | CONNECTIVITY_CHECKING = "OFF", 106 | INIT_FILE = "../wnp64relimg88.mif", 107 | INIT_FILE_LAYOUT = "port_a", 108 | LOGICAL_RAM_NAME = "ALTSYNCRAM", 109 | OPERATION_MODE = "rom", 110 | PORT_A_ADDRESS_CLEAR = "none", 111 | PORT_A_ADDRESS_WIDTH = 6, 112 | PORT_A_DATA_OUT_CLEAR = "none", 113 | PORT_A_DATA_OUT_CLOCK = "clock0", 114 | PORT_A_DATA_WIDTH = 1, 115 | PORT_A_FIRST_ADDRESS = 0, 116 | PORT_A_FIRST_BIT_NUMBER = 3, 117 | PORT_A_LAST_ADDRESS = 63, 118 | PORT_A_LOGICAL_RAM_DEPTH = 64, 119 | PORT_A_LOGICAL_RAM_WIDTH = 16, 120 | RAM_BLOCK_TYPE = "AUTO" 121 | ); 122 | ram_block1a4 : cycloneive_ram_block 123 | WITH ( 124 | CLK0_CORE_CLOCK_ENABLE = "none", 125 | CLK0_INPUT_CLOCK_ENABLE = "none", 126 | CLK0_OUTPUT_CLOCK_ENABLE = "none", 127 | CONNECTIVITY_CHECKING = "OFF", 128 | INIT_FILE = "../wnp64relimg88.mif", 129 | INIT_FILE_LAYOUT = "port_a", 130 | LOGICAL_RAM_NAME = "ALTSYNCRAM", 131 | OPERATION_MODE = "rom", 132 | PORT_A_ADDRESS_CLEAR = "none", 133 | PORT_A_ADDRESS_WIDTH = 6, 134 | PORT_A_DATA_OUT_CLEAR = "none", 135 | PORT_A_DATA_OUT_CLOCK = "clock0", 136 | PORT_A_DATA_WIDTH = 1, 137 | PORT_A_FIRST_ADDRESS = 0, 138 | PORT_A_FIRST_BIT_NUMBER = 4, 139 | PORT_A_LAST_ADDRESS = 63, 140 | PORT_A_LOGICAL_RAM_DEPTH = 64, 141 | PORT_A_LOGICAL_RAM_WIDTH = 16, 142 | RAM_BLOCK_TYPE = "AUTO" 143 | ); 144 | ram_block1a5 : cycloneive_ram_block 145 | WITH ( 146 | CLK0_CORE_CLOCK_ENABLE = "none", 147 | CLK0_INPUT_CLOCK_ENABLE = "none", 148 | CLK0_OUTPUT_CLOCK_ENABLE = "none", 149 | CONNECTIVITY_CHECKING = "OFF", 150 | INIT_FILE = "../wnp64relimg88.mif", 151 | INIT_FILE_LAYOUT = "port_a", 152 | LOGICAL_RAM_NAME = "ALTSYNCRAM", 153 | OPERATION_MODE = "rom", 154 | PORT_A_ADDRESS_CLEAR = "none", 155 | PORT_A_ADDRESS_WIDTH = 6, 156 | PORT_A_DATA_OUT_CLEAR = "none", 157 | PORT_A_DATA_OUT_CLOCK = "clock0", 158 | PORT_A_DATA_WIDTH = 1, 159 | PORT_A_FIRST_ADDRESS = 0, 160 | PORT_A_FIRST_BIT_NUMBER = 5, 161 | PORT_A_LAST_ADDRESS = 63, 162 | PORT_A_LOGICAL_RAM_DEPTH = 64, 163 | PORT_A_LOGICAL_RAM_WIDTH = 16, 164 | RAM_BLOCK_TYPE = "AUTO" 165 | ); 166 | ram_block1a6 : cycloneive_ram_block 167 | WITH ( 168 | CLK0_CORE_CLOCK_ENABLE = "none", 169 | CLK0_INPUT_CLOCK_ENABLE = "none", 170 | CLK0_OUTPUT_CLOCK_ENABLE = "none", 171 | CONNECTIVITY_CHECKING = "OFF", 172 | INIT_FILE = "../wnp64relimg88.mif", 173 | INIT_FILE_LAYOUT = "port_a", 174 | LOGICAL_RAM_NAME = "ALTSYNCRAM", 175 | OPERATION_MODE = "rom", 176 | PORT_A_ADDRESS_CLEAR = "none", 177 | PORT_A_ADDRESS_WIDTH = 6, 178 | PORT_A_DATA_OUT_CLEAR = "none", 179 | PORT_A_DATA_OUT_CLOCK = "clock0", 180 | PORT_A_DATA_WIDTH = 1, 181 | PORT_A_FIRST_ADDRESS = 0, 182 | PORT_A_FIRST_BIT_NUMBER = 6, 183 | PORT_A_LAST_ADDRESS = 63, 184 | PORT_A_LOGICAL_RAM_DEPTH = 64, 185 | PORT_A_LOGICAL_RAM_WIDTH = 16, 186 | RAM_BLOCK_TYPE = "AUTO" 187 | ); 188 | ram_block1a7 : cycloneive_ram_block 189 | WITH ( 190 | CLK0_CORE_CLOCK_ENABLE = "none", 191 | CLK0_INPUT_CLOCK_ENABLE = "none", 192 | CLK0_OUTPUT_CLOCK_ENABLE = "none", 193 | CONNECTIVITY_CHECKING = "OFF", 194 | INIT_FILE = "../wnp64relimg88.mif", 195 | INIT_FILE_LAYOUT = "port_a", 196 | LOGICAL_RAM_NAME = "ALTSYNCRAM", 197 | OPERATION_MODE = "rom", 198 | PORT_A_ADDRESS_CLEAR = "none", 199 | PORT_A_ADDRESS_WIDTH = 6, 200 | PORT_A_DATA_OUT_CLEAR = "none", 201 | PORT_A_DATA_OUT_CLOCK = "clock0", 202 | PORT_A_DATA_WIDTH = 1, 203 | PORT_A_FIRST_ADDRESS = 0, 204 | PORT_A_FIRST_BIT_NUMBER = 7, 205 | PORT_A_LAST_ADDRESS = 63, 206 | PORT_A_LOGICAL_RAM_DEPTH = 64, 207 | PORT_A_LOGICAL_RAM_WIDTH = 16, 208 | RAM_BLOCK_TYPE = "AUTO" 209 | ); 210 | ram_block1a8 : cycloneive_ram_block 211 | WITH ( 212 | CLK0_CORE_CLOCK_ENABLE = "none", 213 | CLK0_INPUT_CLOCK_ENABLE = "none", 214 | CLK0_OUTPUT_CLOCK_ENABLE = "none", 215 | CONNECTIVITY_CHECKING = "OFF", 216 | INIT_FILE = "../wnp64relimg88.mif", 217 | INIT_FILE_LAYOUT = "port_a", 218 | LOGICAL_RAM_NAME = "ALTSYNCRAM", 219 | OPERATION_MODE = "rom", 220 | PORT_A_ADDRESS_CLEAR = "none", 221 | PORT_A_ADDRESS_WIDTH = 6, 222 | PORT_A_DATA_OUT_CLEAR = "none", 223 | PORT_A_DATA_OUT_CLOCK = "clock0", 224 | PORT_A_DATA_WIDTH = 1, 225 | PORT_A_FIRST_ADDRESS = 0, 226 | PORT_A_FIRST_BIT_NUMBER = 8, 227 | PORT_A_LAST_ADDRESS = 63, 228 | PORT_A_LOGICAL_RAM_DEPTH = 64, 229 | PORT_A_LOGICAL_RAM_WIDTH = 16, 230 | RAM_BLOCK_TYPE = "AUTO" 231 | ); 232 | ram_block1a9 : cycloneive_ram_block 233 | WITH ( 234 | CLK0_CORE_CLOCK_ENABLE = "none", 235 | CLK0_INPUT_CLOCK_ENABLE = "none", 236 | CLK0_OUTPUT_CLOCK_ENABLE = "none", 237 | CONNECTIVITY_CHECKING = "OFF", 238 | INIT_FILE = "../wnp64relimg88.mif", 239 | INIT_FILE_LAYOUT = "port_a", 240 | LOGICAL_RAM_NAME = "ALTSYNCRAM", 241 | OPERATION_MODE = "rom", 242 | PORT_A_ADDRESS_CLEAR = "none", 243 | PORT_A_ADDRESS_WIDTH = 6, 244 | PORT_A_DATA_OUT_CLEAR = "none", 245 | PORT_A_DATA_OUT_CLOCK = "clock0", 246 | PORT_A_DATA_WIDTH = 1, 247 | PORT_A_FIRST_ADDRESS = 0, 248 | PORT_A_FIRST_BIT_NUMBER = 9, 249 | PORT_A_LAST_ADDRESS = 63, 250 | PORT_A_LOGICAL_RAM_DEPTH = 64, 251 | PORT_A_LOGICAL_RAM_WIDTH = 16, 252 | RAM_BLOCK_TYPE = "AUTO" 253 | ); 254 | ram_block1a10 : cycloneive_ram_block 255 | WITH ( 256 | CLK0_CORE_CLOCK_ENABLE = "none", 257 | CLK0_INPUT_CLOCK_ENABLE = "none", 258 | CLK0_OUTPUT_CLOCK_ENABLE = "none", 259 | CONNECTIVITY_CHECKING = "OFF", 260 | INIT_FILE = "../wnp64relimg88.mif", 261 | INIT_FILE_LAYOUT = "port_a", 262 | LOGICAL_RAM_NAME = "ALTSYNCRAM", 263 | OPERATION_MODE = "rom", 264 | PORT_A_ADDRESS_CLEAR = "none", 265 | PORT_A_ADDRESS_WIDTH = 6, 266 | PORT_A_DATA_OUT_CLEAR = "none", 267 | PORT_A_DATA_OUT_CLOCK = "clock0", 268 | PORT_A_DATA_WIDTH = 1, 269 | PORT_A_FIRST_ADDRESS = 0, 270 | PORT_A_FIRST_BIT_NUMBER = 10, 271 | PORT_A_LAST_ADDRESS = 63, 272 | PORT_A_LOGICAL_RAM_DEPTH = 64, 273 | PORT_A_LOGICAL_RAM_WIDTH = 16, 274 | RAM_BLOCK_TYPE = "AUTO" 275 | ); 276 | ram_block1a11 : cycloneive_ram_block 277 | WITH ( 278 | CLK0_CORE_CLOCK_ENABLE = "none", 279 | CLK0_INPUT_CLOCK_ENABLE = "none", 280 | CLK0_OUTPUT_CLOCK_ENABLE = "none", 281 | CONNECTIVITY_CHECKING = "OFF", 282 | INIT_FILE = "../wnp64relimg88.mif", 283 | INIT_FILE_LAYOUT = "port_a", 284 | LOGICAL_RAM_NAME = "ALTSYNCRAM", 285 | OPERATION_MODE = "rom", 286 | PORT_A_ADDRESS_CLEAR = "none", 287 | PORT_A_ADDRESS_WIDTH = 6, 288 | PORT_A_DATA_OUT_CLEAR = "none", 289 | PORT_A_DATA_OUT_CLOCK = "clock0", 290 | PORT_A_DATA_WIDTH = 1, 291 | PORT_A_FIRST_ADDRESS = 0, 292 | PORT_A_FIRST_BIT_NUMBER = 11, 293 | PORT_A_LAST_ADDRESS = 63, 294 | PORT_A_LOGICAL_RAM_DEPTH = 64, 295 | PORT_A_LOGICAL_RAM_WIDTH = 16, 296 | RAM_BLOCK_TYPE = "AUTO" 297 | ); 298 | ram_block1a12 : cycloneive_ram_block 299 | WITH ( 300 | CLK0_CORE_CLOCK_ENABLE = "none", 301 | CLK0_INPUT_CLOCK_ENABLE = "none", 302 | CLK0_OUTPUT_CLOCK_ENABLE = "none", 303 | CONNECTIVITY_CHECKING = "OFF", 304 | INIT_FILE = "../wnp64relimg88.mif", 305 | INIT_FILE_LAYOUT = "port_a", 306 | LOGICAL_RAM_NAME = "ALTSYNCRAM", 307 | OPERATION_MODE = "rom", 308 | PORT_A_ADDRESS_CLEAR = "none", 309 | PORT_A_ADDRESS_WIDTH = 6, 310 | PORT_A_DATA_OUT_CLEAR = "none", 311 | PORT_A_DATA_OUT_CLOCK = "clock0", 312 | PORT_A_DATA_WIDTH = 1, 313 | PORT_A_FIRST_ADDRESS = 0, 314 | PORT_A_FIRST_BIT_NUMBER = 12, 315 | PORT_A_LAST_ADDRESS = 63, 316 | PORT_A_LOGICAL_RAM_DEPTH = 64, 317 | PORT_A_LOGICAL_RAM_WIDTH = 16, 318 | RAM_BLOCK_TYPE = "AUTO" 319 | ); 320 | ram_block1a13 : cycloneive_ram_block 321 | WITH ( 322 | CLK0_CORE_CLOCK_ENABLE = "none", 323 | CLK0_INPUT_CLOCK_ENABLE = "none", 324 | CLK0_OUTPUT_CLOCK_ENABLE = "none", 325 | CONNECTIVITY_CHECKING = "OFF", 326 | INIT_FILE = "../wnp64relimg88.mif", 327 | INIT_FILE_LAYOUT = "port_a", 328 | LOGICAL_RAM_NAME = "ALTSYNCRAM", 329 | OPERATION_MODE = "rom", 330 | PORT_A_ADDRESS_CLEAR = "none", 331 | PORT_A_ADDRESS_WIDTH = 6, 332 | PORT_A_DATA_OUT_CLEAR = "none", 333 | PORT_A_DATA_OUT_CLOCK = "clock0", 334 | PORT_A_DATA_WIDTH = 1, 335 | PORT_A_FIRST_ADDRESS = 0, 336 | PORT_A_FIRST_BIT_NUMBER = 13, 337 | PORT_A_LAST_ADDRESS = 63, 338 | PORT_A_LOGICAL_RAM_DEPTH = 64, 339 | PORT_A_LOGICAL_RAM_WIDTH = 16, 340 | RAM_BLOCK_TYPE = "AUTO" 341 | ); 342 | ram_block1a14 : cycloneive_ram_block 343 | WITH ( 344 | CLK0_CORE_CLOCK_ENABLE = "none", 345 | CLK0_INPUT_CLOCK_ENABLE = "none", 346 | CLK0_OUTPUT_CLOCK_ENABLE = "none", 347 | CONNECTIVITY_CHECKING = "OFF", 348 | INIT_FILE = "../wnp64relimg88.mif", 349 | INIT_FILE_LAYOUT = "port_a", 350 | LOGICAL_RAM_NAME = "ALTSYNCRAM", 351 | OPERATION_MODE = "rom", 352 | PORT_A_ADDRESS_CLEAR = "none", 353 | PORT_A_ADDRESS_WIDTH = 6, 354 | PORT_A_DATA_OUT_CLEAR = "none", 355 | PORT_A_DATA_OUT_CLOCK = "clock0", 356 | PORT_A_DATA_WIDTH = 1, 357 | PORT_A_FIRST_ADDRESS = 0, 358 | PORT_A_FIRST_BIT_NUMBER = 14, 359 | PORT_A_LAST_ADDRESS = 63, 360 | PORT_A_LOGICAL_RAM_DEPTH = 64, 361 | PORT_A_LOGICAL_RAM_WIDTH = 16, 362 | RAM_BLOCK_TYPE = "AUTO" 363 | ); 364 | ram_block1a15 : cycloneive_ram_block 365 | WITH ( 366 | CLK0_CORE_CLOCK_ENABLE = "none", 367 | CLK0_INPUT_CLOCK_ENABLE = "none", 368 | CLK0_OUTPUT_CLOCK_ENABLE = "none", 369 | CONNECTIVITY_CHECKING = "OFF", 370 | INIT_FILE = "../wnp64relimg88.mif", 371 | INIT_FILE_LAYOUT = "port_a", 372 | LOGICAL_RAM_NAME = "ALTSYNCRAM", 373 | OPERATION_MODE = "rom", 374 | PORT_A_ADDRESS_CLEAR = "none", 375 | PORT_A_ADDRESS_WIDTH = 6, 376 | PORT_A_DATA_OUT_CLEAR = "none", 377 | PORT_A_DATA_OUT_CLOCK = "clock0", 378 | PORT_A_DATA_WIDTH = 1, 379 | PORT_A_FIRST_ADDRESS = 0, 380 | PORT_A_FIRST_BIT_NUMBER = 15, 381 | PORT_A_LAST_ADDRESS = 63, 382 | PORT_A_LOGICAL_RAM_DEPTH = 64, 383 | PORT_A_LOGICAL_RAM_WIDTH = 16, 384 | RAM_BLOCK_TYPE = "AUTO" 385 | ); 386 | address_a_wire[5..0] : WIRE; 387 | 388 | BEGIN 389 | ram_block1a[15..0].clk0 = clock0; 390 | ram_block1a[15..0].portaaddr[] = ( address_a_wire[5..0]); 391 | ram_block1a[15..0].portare = B"1111111111111111"; 392 | address_a_wire[] = address_a[]; 393 | q_a[] = ( ram_block1a[15..0].portadataout[0..0]); 394 | END; 395 | --VALID FILE 396 | -------------------------------------------------------------------------------- /FPGA_WORK/proj/db/altsyncram_ufa1.tdf: -------------------------------------------------------------------------------- 1 | --altsyncram ADDRESS_ACLR_A="NONE" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CLOCK_ENABLE_INPUT_A="BYPASS" CLOCK_ENABLE_OUTPUT_A="BYPASS" CYCLONEII_M4K_COMPATIBILITY="ON" DEVICE_FAMILY="Cyclone IV E" ENABLE_RUNTIME_MOD="NO" INIT_FILE="wnp64relimg88.mif" LOW_POWER_MODE="AUTO" NUMWORDS_A=64 OPERATION_MODE="ROM" OUTDATA_ACLR_A="NONE" OUTDATA_REG_A="UNREGISTERED" WIDTH_A=16 WIDTH_BYTEENA_A=1 WIDTHAD_A=6 address_a clock0 q_a CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 2 | --VERSION_BEGIN 13.0 cbx_altsyncram 2013:04:24:18:08:47:SJ cbx_cycloneii 2013:04:24:18:08:47:SJ cbx_lpm_add_sub 2013:04:24:18:08:47:SJ cbx_lpm_compare 2013:04:24:18:08:47:SJ cbx_lpm_decode 2013:04:24:18:08:47:SJ cbx_lpm_mux 2013:04:24:18:08:47:SJ cbx_mgl 2013:04:24:18:11:10:SJ cbx_stratix 2013:04:24:18:08:47:SJ cbx_stratixii 2013:04:24:18:08:47:SJ cbx_stratixiii 2013:04:24:18:08:47:SJ cbx_stratixv 2013:04:24:18:08:47:SJ cbx_util_mgl 2013:04:24:18:08:47:SJ VERSION_END 3 | 4 | 5 | -- Copyright (C) 1991-2013 Altera Corporation 6 | -- Your use of Altera Corporation's design tools, logic functions 7 | -- and other software and tools, and its AMPP partner logic 8 | -- functions, and any output files from any of the foregoing 9 | -- (including device programming or simulation files), and any 10 | -- associated documentation or information are expressly subject 11 | -- to the terms and conditions of the Altera Program License 12 | -- Subscription Agreement, Altera MegaCore Function License 13 | -- Agreement, or other applicable license agreement, including, 14 | -- without limitation, that your use is for the sole purpose of 15 | -- programming logic devices manufactured by Altera and sold by 16 | -- Altera or its authorized distributors. Please refer to the 17 | -- applicable agreement for further details. 18 | 19 | 20 | FUNCTION cycloneive_ram_block (clk0, clk1, clr0, clr1, ena0, ena1, ena2, ena3, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portaaddrstall, portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portare, portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbaddrstall, portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbre, portbwe) 21 | WITH ( CLK0_CORE_CLOCK_ENABLE, CLK0_INPUT_CLOCK_ENABLE, CLK0_OUTPUT_CLOCK_ENABLE, CLK1_CORE_CLOCK_ENABLE, CLK1_INPUT_CLOCK_ENABLE, CLK1_OUTPUT_CLOCK_ENABLE, CONNECTIVITY_CHECKING, DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS, DONT_POWER_OPTIMIZE, INIT_FILE, INIT_FILE_LAYOUT, init_file_restructured, LOGICAL_RAM_NAME, mem_init0, mem_init1, mem_init2, mem_init3, mem_init4, MIXED_PORT_FEED_THROUGH_MODE, OPERATION_MODE, PORT_A_ADDRESS_CLEAR, PORT_A_ADDRESS_WIDTH = 1, PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, PORT_A_BYTE_SIZE, PORT_A_DATA_OUT_CLEAR, PORT_A_DATA_OUT_CLOCK, PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS, PORT_A_FIRST_BIT_NUMBER, PORT_A_LAST_ADDRESS, PORT_A_LOGICAL_RAM_DEPTH, PORT_A_LOGICAL_RAM_WIDTH, PORT_A_READ_DURING_WRITE_MODE, PORT_B_ADDRESS_CLEAR, PORT_B_ADDRESS_CLOCK, PORT_B_ADDRESS_WIDTH = 1, PORT_B_BYTE_ENABLE_CLOCK, PORT_B_BYTE_ENABLE_MASK_WIDTH = 1, PORT_B_BYTE_SIZE, PORT_B_DATA_IN_CLOCK, PORT_B_DATA_OUT_CLEAR, PORT_B_DATA_OUT_CLOCK, PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS, PORT_B_FIRST_BIT_NUMBER, PORT_B_LAST_ADDRESS, PORT_B_LOGICAL_RAM_DEPTH, PORT_B_LOGICAL_RAM_WIDTH, PORT_B_READ_DURING_WRITE_MODE, PORT_B_READ_ENABLE_CLOCK, PORT_B_WRITE_ENABLE_CLOCK, POWER_UP_UNINITIALIZED, RAM_BLOCK_TYPE, SAFE_WRITE, WIDTH_ECCSTATUS) 22 | RETURNS ( portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]); 23 | 24 | --synthesis_resources = M9K 1 25 | OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION"; 26 | 27 | SUBDESIGN altsyncram_ufa1 28 | ( 29 | address_a[5..0] : input; 30 | clock0 : input; 31 | q_a[15..0] : output; 32 | ) 33 | VARIABLE 34 | ram_block1a0 : cycloneive_ram_block 35 | WITH ( 36 | CLK0_CORE_CLOCK_ENABLE = "none", 37 | CLK0_INPUT_CLOCK_ENABLE = "none", 38 | CONNECTIVITY_CHECKING = "OFF", 39 | INIT_FILE = "wnp64relimg88.mif", 40 | INIT_FILE_LAYOUT = "port_a", 41 | LOGICAL_RAM_NAME = "ALTSYNCRAM", 42 | OPERATION_MODE = "rom", 43 | PORT_A_ADDRESS_CLEAR = "none", 44 | PORT_A_ADDRESS_WIDTH = 6, 45 | PORT_A_DATA_OUT_CLEAR = "none", 46 | PORT_A_DATA_OUT_CLOCK = "none", 47 | PORT_A_DATA_WIDTH = 1, 48 | PORT_A_FIRST_ADDRESS = 0, 49 | PORT_A_FIRST_BIT_NUMBER = 0, 50 | PORT_A_LAST_ADDRESS = 63, 51 | PORT_A_LOGICAL_RAM_DEPTH = 64, 52 | PORT_A_LOGICAL_RAM_WIDTH = 16, 53 | RAM_BLOCK_TYPE = "AUTO" 54 | ); 55 | ram_block1a1 : cycloneive_ram_block 56 | WITH ( 57 | CLK0_CORE_CLOCK_ENABLE = "none", 58 | CLK0_INPUT_CLOCK_ENABLE = "none", 59 | CONNECTIVITY_CHECKING = "OFF", 60 | INIT_FILE = "wnp64relimg88.mif", 61 | INIT_FILE_LAYOUT = "port_a", 62 | LOGICAL_RAM_NAME = "ALTSYNCRAM", 63 | OPERATION_MODE = "rom", 64 | PORT_A_ADDRESS_CLEAR = "none", 65 | PORT_A_ADDRESS_WIDTH = 6, 66 | PORT_A_DATA_OUT_CLEAR = "none", 67 | PORT_A_DATA_OUT_CLOCK = "none", 68 | PORT_A_DATA_WIDTH = 1, 69 | PORT_A_FIRST_ADDRESS = 0, 70 | PORT_A_FIRST_BIT_NUMBER = 1, 71 | PORT_A_LAST_ADDRESS = 63, 72 | PORT_A_LOGICAL_RAM_DEPTH = 64, 73 | PORT_A_LOGICAL_RAM_WIDTH = 16, 74 | RAM_BLOCK_TYPE = "AUTO" 75 | ); 76 | ram_block1a2 : cycloneive_ram_block 77 | WITH ( 78 | CLK0_CORE_CLOCK_ENABLE = "none", 79 | CLK0_INPUT_CLOCK_ENABLE = "none", 80 | CONNECTIVITY_CHECKING = "OFF", 81 | INIT_FILE = "wnp64relimg88.mif", 82 | INIT_FILE_LAYOUT = "port_a", 83 | LOGICAL_RAM_NAME = "ALTSYNCRAM", 84 | OPERATION_MODE = "rom", 85 | PORT_A_ADDRESS_CLEAR = "none", 86 | PORT_A_ADDRESS_WIDTH = 6, 87 | PORT_A_DATA_OUT_CLEAR = "none", 88 | PORT_A_DATA_OUT_CLOCK = "none", 89 | PORT_A_DATA_WIDTH = 1, 90 | PORT_A_FIRST_ADDRESS = 0, 91 | PORT_A_FIRST_BIT_NUMBER = 2, 92 | PORT_A_LAST_ADDRESS = 63, 93 | PORT_A_LOGICAL_RAM_DEPTH = 64, 94 | PORT_A_LOGICAL_RAM_WIDTH = 16, 95 | RAM_BLOCK_TYPE = "AUTO" 96 | ); 97 | ram_block1a3 : cycloneive_ram_block 98 | WITH ( 99 | CLK0_CORE_CLOCK_ENABLE = "none", 100 | CLK0_INPUT_CLOCK_ENABLE = "none", 101 | CONNECTIVITY_CHECKING = "OFF", 102 | INIT_FILE = "wnp64relimg88.mif", 103 | INIT_FILE_LAYOUT = "port_a", 104 | LOGICAL_RAM_NAME = "ALTSYNCRAM", 105 | OPERATION_MODE = "rom", 106 | PORT_A_ADDRESS_CLEAR = "none", 107 | PORT_A_ADDRESS_WIDTH = 6, 108 | PORT_A_DATA_OUT_CLEAR = "none", 109 | PORT_A_DATA_OUT_CLOCK = "none", 110 | PORT_A_DATA_WIDTH = 1, 111 | PORT_A_FIRST_ADDRESS = 0, 112 | PORT_A_FIRST_BIT_NUMBER = 3, 113 | PORT_A_LAST_ADDRESS = 63, 114 | PORT_A_LOGICAL_RAM_DEPTH = 64, 115 | PORT_A_LOGICAL_RAM_WIDTH = 16, 116 | RAM_BLOCK_TYPE = "AUTO" 117 | ); 118 | ram_block1a4 : cycloneive_ram_block 119 | WITH ( 120 | CLK0_CORE_CLOCK_ENABLE = "none", 121 | CLK0_INPUT_CLOCK_ENABLE = "none", 122 | CONNECTIVITY_CHECKING = "OFF", 123 | INIT_FILE = "wnp64relimg88.mif", 124 | INIT_FILE_LAYOUT = "port_a", 125 | LOGICAL_RAM_NAME = "ALTSYNCRAM", 126 | OPERATION_MODE = "rom", 127 | PORT_A_ADDRESS_CLEAR = "none", 128 | PORT_A_ADDRESS_WIDTH = 6, 129 | PORT_A_DATA_OUT_CLEAR = "none", 130 | PORT_A_DATA_OUT_CLOCK = "none", 131 | PORT_A_DATA_WIDTH = 1, 132 | PORT_A_FIRST_ADDRESS = 0, 133 | PORT_A_FIRST_BIT_NUMBER = 4, 134 | PORT_A_LAST_ADDRESS = 63, 135 | PORT_A_LOGICAL_RAM_DEPTH = 64, 136 | PORT_A_LOGICAL_RAM_WIDTH = 16, 137 | RAM_BLOCK_TYPE = "AUTO" 138 | ); 139 | ram_block1a5 : cycloneive_ram_block 140 | WITH ( 141 | CLK0_CORE_CLOCK_ENABLE = "none", 142 | CLK0_INPUT_CLOCK_ENABLE = "none", 143 | CONNECTIVITY_CHECKING = "OFF", 144 | INIT_FILE = "wnp64relimg88.mif", 145 | INIT_FILE_LAYOUT = "port_a", 146 | LOGICAL_RAM_NAME = "ALTSYNCRAM", 147 | OPERATION_MODE = "rom", 148 | PORT_A_ADDRESS_CLEAR = "none", 149 | PORT_A_ADDRESS_WIDTH = 6, 150 | PORT_A_DATA_OUT_CLEAR = "none", 151 | PORT_A_DATA_OUT_CLOCK = "none", 152 | PORT_A_DATA_WIDTH = 1, 153 | PORT_A_FIRST_ADDRESS = 0, 154 | PORT_A_FIRST_BIT_NUMBER = 5, 155 | PORT_A_LAST_ADDRESS = 63, 156 | PORT_A_LOGICAL_RAM_DEPTH = 64, 157 | PORT_A_LOGICAL_RAM_WIDTH = 16, 158 | RAM_BLOCK_TYPE = "AUTO" 159 | ); 160 | ram_block1a6 : cycloneive_ram_block 161 | WITH ( 162 | CLK0_CORE_CLOCK_ENABLE = "none", 163 | CLK0_INPUT_CLOCK_ENABLE = "none", 164 | CONNECTIVITY_CHECKING = "OFF", 165 | INIT_FILE = "wnp64relimg88.mif", 166 | INIT_FILE_LAYOUT = "port_a", 167 | LOGICAL_RAM_NAME = "ALTSYNCRAM", 168 | OPERATION_MODE = "rom", 169 | PORT_A_ADDRESS_CLEAR = "none", 170 | PORT_A_ADDRESS_WIDTH = 6, 171 | PORT_A_DATA_OUT_CLEAR = "none", 172 | PORT_A_DATA_OUT_CLOCK = "none", 173 | PORT_A_DATA_WIDTH = 1, 174 | PORT_A_FIRST_ADDRESS = 0, 175 | PORT_A_FIRST_BIT_NUMBER = 6, 176 | PORT_A_LAST_ADDRESS = 63, 177 | PORT_A_LOGICAL_RAM_DEPTH = 64, 178 | PORT_A_LOGICAL_RAM_WIDTH = 16, 179 | RAM_BLOCK_TYPE = "AUTO" 180 | ); 181 | ram_block1a7 : cycloneive_ram_block 182 | WITH ( 183 | CLK0_CORE_CLOCK_ENABLE = "none", 184 | CLK0_INPUT_CLOCK_ENABLE = "none", 185 | CONNECTIVITY_CHECKING = "OFF", 186 | INIT_FILE = "wnp64relimg88.mif", 187 | INIT_FILE_LAYOUT = "port_a", 188 | LOGICAL_RAM_NAME = "ALTSYNCRAM", 189 | OPERATION_MODE = "rom", 190 | PORT_A_ADDRESS_CLEAR = "none", 191 | PORT_A_ADDRESS_WIDTH = 6, 192 | PORT_A_DATA_OUT_CLEAR = "none", 193 | PORT_A_DATA_OUT_CLOCK = "none", 194 | PORT_A_DATA_WIDTH = 1, 195 | PORT_A_FIRST_ADDRESS = 0, 196 | PORT_A_FIRST_BIT_NUMBER = 7, 197 | PORT_A_LAST_ADDRESS = 63, 198 | PORT_A_LOGICAL_RAM_DEPTH = 64, 199 | PORT_A_LOGICAL_RAM_WIDTH = 16, 200 | RAM_BLOCK_TYPE = "AUTO" 201 | ); 202 | ram_block1a8 : cycloneive_ram_block 203 | WITH ( 204 | CLK0_CORE_CLOCK_ENABLE = "none", 205 | CLK0_INPUT_CLOCK_ENABLE = "none", 206 | CONNECTIVITY_CHECKING = "OFF", 207 | INIT_FILE = "wnp64relimg88.mif", 208 | INIT_FILE_LAYOUT = "port_a", 209 | LOGICAL_RAM_NAME = "ALTSYNCRAM", 210 | OPERATION_MODE = "rom", 211 | PORT_A_ADDRESS_CLEAR = "none", 212 | PORT_A_ADDRESS_WIDTH = 6, 213 | PORT_A_DATA_OUT_CLEAR = "none", 214 | PORT_A_DATA_OUT_CLOCK = "none", 215 | PORT_A_DATA_WIDTH = 1, 216 | PORT_A_FIRST_ADDRESS = 0, 217 | PORT_A_FIRST_BIT_NUMBER = 8, 218 | PORT_A_LAST_ADDRESS = 63, 219 | PORT_A_LOGICAL_RAM_DEPTH = 64, 220 | PORT_A_LOGICAL_RAM_WIDTH = 16, 221 | RAM_BLOCK_TYPE = "AUTO" 222 | ); 223 | ram_block1a9 : cycloneive_ram_block 224 | WITH ( 225 | CLK0_CORE_CLOCK_ENABLE = "none", 226 | CLK0_INPUT_CLOCK_ENABLE = "none", 227 | CONNECTIVITY_CHECKING = "OFF", 228 | INIT_FILE = "wnp64relimg88.mif", 229 | INIT_FILE_LAYOUT = "port_a", 230 | LOGICAL_RAM_NAME = "ALTSYNCRAM", 231 | OPERATION_MODE = "rom", 232 | PORT_A_ADDRESS_CLEAR = "none", 233 | PORT_A_ADDRESS_WIDTH = 6, 234 | PORT_A_DATA_OUT_CLEAR = "none", 235 | PORT_A_DATA_OUT_CLOCK = "none", 236 | PORT_A_DATA_WIDTH = 1, 237 | PORT_A_FIRST_ADDRESS = 0, 238 | PORT_A_FIRST_BIT_NUMBER = 9, 239 | PORT_A_LAST_ADDRESS = 63, 240 | PORT_A_LOGICAL_RAM_DEPTH = 64, 241 | PORT_A_LOGICAL_RAM_WIDTH = 16, 242 | RAM_BLOCK_TYPE = "AUTO" 243 | ); 244 | ram_block1a10 : cycloneive_ram_block 245 | WITH ( 246 | CLK0_CORE_CLOCK_ENABLE = "none", 247 | CLK0_INPUT_CLOCK_ENABLE = "none", 248 | CONNECTIVITY_CHECKING = "OFF", 249 | INIT_FILE = "wnp64relimg88.mif", 250 | INIT_FILE_LAYOUT = "port_a", 251 | LOGICAL_RAM_NAME = "ALTSYNCRAM", 252 | OPERATION_MODE = "rom", 253 | PORT_A_ADDRESS_CLEAR = "none", 254 | PORT_A_ADDRESS_WIDTH = 6, 255 | PORT_A_DATA_OUT_CLEAR = "none", 256 | PORT_A_DATA_OUT_CLOCK = "none", 257 | PORT_A_DATA_WIDTH = 1, 258 | PORT_A_FIRST_ADDRESS = 0, 259 | PORT_A_FIRST_BIT_NUMBER = 10, 260 | PORT_A_LAST_ADDRESS = 63, 261 | PORT_A_LOGICAL_RAM_DEPTH = 64, 262 | PORT_A_LOGICAL_RAM_WIDTH = 16, 263 | RAM_BLOCK_TYPE = "AUTO" 264 | ); 265 | ram_block1a11 : cycloneive_ram_block 266 | WITH ( 267 | CLK0_CORE_CLOCK_ENABLE = "none", 268 | CLK0_INPUT_CLOCK_ENABLE = "none", 269 | CONNECTIVITY_CHECKING = "OFF", 270 | INIT_FILE = "wnp64relimg88.mif", 271 | INIT_FILE_LAYOUT = "port_a", 272 | LOGICAL_RAM_NAME = "ALTSYNCRAM", 273 | OPERATION_MODE = "rom", 274 | PORT_A_ADDRESS_CLEAR = "none", 275 | PORT_A_ADDRESS_WIDTH = 6, 276 | PORT_A_DATA_OUT_CLEAR = "none", 277 | PORT_A_DATA_OUT_CLOCK = "none", 278 | PORT_A_DATA_WIDTH = 1, 279 | PORT_A_FIRST_ADDRESS = 0, 280 | PORT_A_FIRST_BIT_NUMBER = 11, 281 | PORT_A_LAST_ADDRESS = 63, 282 | PORT_A_LOGICAL_RAM_DEPTH = 64, 283 | PORT_A_LOGICAL_RAM_WIDTH = 16, 284 | RAM_BLOCK_TYPE = "AUTO" 285 | ); 286 | ram_block1a12 : cycloneive_ram_block 287 | WITH ( 288 | CLK0_CORE_CLOCK_ENABLE = "none", 289 | CLK0_INPUT_CLOCK_ENABLE = "none", 290 | CONNECTIVITY_CHECKING = "OFF", 291 | INIT_FILE = "wnp64relimg88.mif", 292 | INIT_FILE_LAYOUT = "port_a", 293 | LOGICAL_RAM_NAME = "ALTSYNCRAM", 294 | OPERATION_MODE = "rom", 295 | PORT_A_ADDRESS_CLEAR = "none", 296 | PORT_A_ADDRESS_WIDTH = 6, 297 | PORT_A_DATA_OUT_CLEAR = "none", 298 | PORT_A_DATA_OUT_CLOCK = "none", 299 | PORT_A_DATA_WIDTH = 1, 300 | PORT_A_FIRST_ADDRESS = 0, 301 | PORT_A_FIRST_BIT_NUMBER = 12, 302 | PORT_A_LAST_ADDRESS = 63, 303 | PORT_A_LOGICAL_RAM_DEPTH = 64, 304 | PORT_A_LOGICAL_RAM_WIDTH = 16, 305 | RAM_BLOCK_TYPE = "AUTO" 306 | ); 307 | ram_block1a13 : cycloneive_ram_block 308 | WITH ( 309 | CLK0_CORE_CLOCK_ENABLE = "none", 310 | CLK0_INPUT_CLOCK_ENABLE = "none", 311 | CONNECTIVITY_CHECKING = "OFF", 312 | INIT_FILE = "wnp64relimg88.mif", 313 | INIT_FILE_LAYOUT = "port_a", 314 | LOGICAL_RAM_NAME = "ALTSYNCRAM", 315 | OPERATION_MODE = "rom", 316 | PORT_A_ADDRESS_CLEAR = "none", 317 | PORT_A_ADDRESS_WIDTH = 6, 318 | PORT_A_DATA_OUT_CLEAR = "none", 319 | PORT_A_DATA_OUT_CLOCK = "none", 320 | PORT_A_DATA_WIDTH = 1, 321 | PORT_A_FIRST_ADDRESS = 0, 322 | PORT_A_FIRST_BIT_NUMBER = 13, 323 | PORT_A_LAST_ADDRESS = 63, 324 | PORT_A_LOGICAL_RAM_DEPTH = 64, 325 | PORT_A_LOGICAL_RAM_WIDTH = 16, 326 | RAM_BLOCK_TYPE = "AUTO" 327 | ); 328 | ram_block1a14 : cycloneive_ram_block 329 | WITH ( 330 | CLK0_CORE_CLOCK_ENABLE = "none", 331 | CLK0_INPUT_CLOCK_ENABLE = "none", 332 | CONNECTIVITY_CHECKING = "OFF", 333 | INIT_FILE = "wnp64relimg88.mif", 334 | INIT_FILE_LAYOUT = "port_a", 335 | LOGICAL_RAM_NAME = "ALTSYNCRAM", 336 | OPERATION_MODE = "rom", 337 | PORT_A_ADDRESS_CLEAR = "none", 338 | PORT_A_ADDRESS_WIDTH = 6, 339 | PORT_A_DATA_OUT_CLEAR = "none", 340 | PORT_A_DATA_OUT_CLOCK = "none", 341 | PORT_A_DATA_WIDTH = 1, 342 | PORT_A_FIRST_ADDRESS = 0, 343 | PORT_A_FIRST_BIT_NUMBER = 14, 344 | PORT_A_LAST_ADDRESS = 63, 345 | PORT_A_LOGICAL_RAM_DEPTH = 64, 346 | PORT_A_LOGICAL_RAM_WIDTH = 16, 347 | RAM_BLOCK_TYPE = "AUTO" 348 | ); 349 | ram_block1a15 : cycloneive_ram_block 350 | WITH ( 351 | CLK0_CORE_CLOCK_ENABLE = "none", 352 | CLK0_INPUT_CLOCK_ENABLE = "none", 353 | CONNECTIVITY_CHECKING = "OFF", 354 | INIT_FILE = "wnp64relimg88.mif", 355 | INIT_FILE_LAYOUT = "port_a", 356 | LOGICAL_RAM_NAME = "ALTSYNCRAM", 357 | OPERATION_MODE = "rom", 358 | PORT_A_ADDRESS_CLEAR = "none", 359 | PORT_A_ADDRESS_WIDTH = 6, 360 | PORT_A_DATA_OUT_CLEAR = "none", 361 | PORT_A_DATA_OUT_CLOCK = "none", 362 | PORT_A_DATA_WIDTH = 1, 363 | PORT_A_FIRST_ADDRESS = 0, 364 | PORT_A_FIRST_BIT_NUMBER = 15, 365 | PORT_A_LAST_ADDRESS = 63, 366 | PORT_A_LOGICAL_RAM_DEPTH = 64, 367 | PORT_A_LOGICAL_RAM_WIDTH = 16, 368 | RAM_BLOCK_TYPE = "AUTO" 369 | ); 370 | address_a_wire[5..0] : WIRE; 371 | 372 | BEGIN 373 | ram_block1a[15..0].clk0 = clock0; 374 | ram_block1a[15..0].portaaddr[] = ( address_a_wire[5..0]); 375 | ram_block1a[15..0].portare = B"1111111111111111"; 376 | address_a_wire[] = address_a[]; 377 | q_a[] = ( ram_block1a[15..0].portadataout[0..0]); 378 | END; 379 | --VALID FILE 380 | -------------------------------------------------------------------------------- /FPGA_WORK/proj/db/fft.db_info: -------------------------------------------------------------------------------- 1 | Quartus_Version = Version 17.1.0 Build 590 10/25/2017 SJ Standard Edition 2 | Version_Index = 453135872 3 | Creation_Time = Mon Feb 18 16:36:53 2019 4 | -------------------------------------------------------------------------------- /FPGA_WORK/proj/db/fft.sld_design_entry.sci: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/DeamonYang/FPGA_FFT/fa3b99e23651234b410932c9e37d66598745853f/FPGA_WORK/proj/db/fft.sld_design_entry.sci -------------------------------------------------------------------------------- /FPGA_WORK/proj/db/logic_util_heursitic.dat: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/DeamonYang/FPGA_FFT/fa3b99e23651234b410932c9e37d66598745853f/FPGA_WORK/proj/db/logic_util_heursitic.dat -------------------------------------------------------------------------------- /FPGA_WORK/proj/db/mult_73t.tdf: -------------------------------------------------------------------------------- 1 | --lpm_mult CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone IV E" DSP_BLOCK_BALANCING="Auto" INPUT_A_IS_CONSTANT="NO" INPUT_B_IS_CONSTANT="NO" LPM_REPRESENTATION="SIGNED" LPM_WIDTHA=8 LPM_WIDTHB=8 LPM_WIDTHP=16 LPM_WIDTHS=1 MAXIMIZE_SPEED=5 dataa datab result CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 2 | --VERSION_BEGIN 13.0 cbx_cycloneii 2013:04:24:18:08:47:SJ cbx_lpm_add_sub 2013:04:24:18:08:47:SJ cbx_lpm_mult 2013:04:24:18:08:47:SJ cbx_mgl 2013:04:24:18:11:10:SJ cbx_padd 2013:04:24:18:08:47:SJ cbx_stratix 2013:04:24:18:08:47:SJ cbx_stratixii 2013:04:24:18:08:47:SJ cbx_util_mgl 2013:04:24:18:08:47:SJ VERSION_END 3 | 4 | 5 | -- Copyright (C) 1991-2013 Altera Corporation 6 | -- Your use of Altera Corporation's design tools, logic functions 7 | -- and other software and tools, and its AMPP partner logic 8 | -- functions, and any output files from any of the foregoing 9 | -- (including device programming or simulation files), and any 10 | -- associated documentation or information are expressly subject 11 | -- to the terms and conditions of the Altera Program License 12 | -- Subscription Agreement, Altera MegaCore Function License 13 | -- Agreement, or other applicable license agreement, including, 14 | -- without limitation, that your use is for the sole purpose of 15 | -- programming logic devices manufactured by Altera and sold by 16 | -- Altera or its authorized distributors. Please refer to the 17 | -- applicable agreement for further details. 18 | 19 | 20 | FUNCTION cycloneive_mac_mult (aclr, clk, dataa[dataa_width-1..0], datab[datab_width-1..0], ena, signa, signb) 21 | WITH ( dataa_clock, dataa_width, datab_clock, datab_width, signa_clock, signb_clock) 22 | RETURNS ( dataout[dataa_width+datab_width-1..0]); 23 | FUNCTION cycloneive_mac_out (aclr, clk, dataa[dataa_width-1..0], ena) 24 | WITH ( dataa_width = 0, output_clock) 25 | RETURNS ( dataout[dataa_width-1..0]); 26 | 27 | --synthesis_resources = dsp_9bit 1 28 | SUBDESIGN mult_73t 29 | ( 30 | dataa[7..0] : input; 31 | datab[7..0] : input; 32 | result[15..0] : output; 33 | ) 34 | VARIABLE 35 | mac_mult1 : cycloneive_mac_mult 36 | WITH ( 37 | dataa_clock = "none", 38 | dataa_width = 8, 39 | datab_clock = "none", 40 | datab_width = 8, 41 | signa_clock = "none", 42 | signb_clock = "none" 43 | ); 44 | mac_out2 : cycloneive_mac_out 45 | WITH ( 46 | dataa_width = 16, 47 | output_clock = "none" 48 | ); 49 | 50 | BEGIN 51 | mac_mult1.dataa[] = ( dataa[]); 52 | mac_mult1.datab[] = ( datab[]); 53 | mac_mult1.signa = B"1"; 54 | mac_mult1.signb = B"1"; 55 | mac_out2.dataa[] = mac_mult1.dataout[]; 56 | result[15..0] = mac_out2.dataout[15..0]; 57 | END; 58 | --VALID FILE 59 | -------------------------------------------------------------------------------- /FPGA_WORK/proj/db/mult_aat.tdf: -------------------------------------------------------------------------------- 1 | --lpm_mult CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone IV E" DSP_BLOCK_BALANCING="Auto" INPUT_A_IS_CONSTANT="NO" INPUT_B_IS_CONSTANT="NO" LPM_REPRESENTATION="UNSIGNED" LPM_WIDTHA=8 LPM_WIDTHB=8 LPM_WIDTHP=16 LPM_WIDTHS=1 MAXIMIZE_SPEED=5 dataa datab result CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 2 | --VERSION_BEGIN 13.0 cbx_cycloneii 2013:04:24:18:08:47:SJ cbx_lpm_add_sub 2013:04:24:18:08:47:SJ cbx_lpm_mult 2013:04:24:18:08:47:SJ cbx_mgl 2013:04:24:18:11:10:SJ cbx_padd 2013:04:24:18:08:47:SJ cbx_stratix 2013:04:24:18:08:47:SJ cbx_stratixii 2013:04:24:18:08:47:SJ cbx_util_mgl 2013:04:24:18:08:47:SJ VERSION_END 3 | 4 | 5 | -- Copyright (C) 1991-2013 Altera Corporation 6 | -- Your use of Altera Corporation's design tools, logic functions 7 | -- and other software and tools, and its AMPP partner logic 8 | -- functions, and any output files from any of the foregoing 9 | -- (including device programming or simulation files), and any 10 | -- associated documentation or information are expressly subject 11 | -- to the terms and conditions of the Altera Program License 12 | -- Subscription Agreement, Altera MegaCore Function License 13 | -- Agreement, or other applicable license agreement, including, 14 | -- without limitation, that your use is for the sole purpose of 15 | -- programming logic devices manufactured by Altera and sold by 16 | -- Altera or its authorized distributors. Please refer to the 17 | -- applicable agreement for further details. 18 | 19 | 20 | FUNCTION cycloneive_mac_mult (aclr, clk, dataa[dataa_width-1..0], datab[datab_width-1..0], ena, signa, signb) 21 | WITH ( dataa_clock, dataa_width, datab_clock, datab_width, signa_clock, signb_clock) 22 | RETURNS ( dataout[dataa_width+datab_width-1..0]); 23 | FUNCTION cycloneive_mac_out (aclr, clk, dataa[dataa_width-1..0], ena) 24 | WITH ( dataa_width = 0, output_clock) 25 | RETURNS ( dataout[dataa_width-1..0]); 26 | 27 | --synthesis_resources = dsp_9bit 1 28 | SUBDESIGN mult_aat 29 | ( 30 | dataa[7..0] : input; 31 | datab[7..0] : input; 32 | result[15..0] : output; 33 | ) 34 | VARIABLE 35 | mac_mult1 : cycloneive_mac_mult 36 | WITH ( 37 | dataa_clock = "none", 38 | dataa_width = 8, 39 | datab_clock = "none", 40 | datab_width = 8, 41 | signa_clock = "none", 42 | signb_clock = "none" 43 | ); 44 | mac_out2 : cycloneive_mac_out 45 | WITH ( 46 | dataa_width = 16, 47 | output_clock = "none" 48 | ); 49 | 50 | BEGIN 51 | mac_mult1.dataa[] = ( dataa[]); 52 | mac_mult1.datab[] = ( datab[]); 53 | mac_mult1.signa = B"0"; 54 | mac_mult1.signb = B"0"; 55 | mac_out2.dataa[] = mac_mult1.dataout[]; 56 | result[15..0] = mac_out2.dataout[15..0]; 57 | END; 58 | --VALID FILE 59 | -------------------------------------------------------------------------------- /FPGA_WORK/proj/db/mult_b3t.tdf: -------------------------------------------------------------------------------- 1 | --lpm_mult CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone IV E" DSP_BLOCK_BALANCING="Auto" INPUT_A_IS_CONSTANT="NO" INPUT_B_IS_CONSTANT="NO" LPM_REPRESENTATION="SIGNED" LPM_WIDTHA=9 LPM_WIDTHB=9 LPM_WIDTHP=18 LPM_WIDTHS=1 MAXIMIZE_SPEED=5 dataa datab result CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 2 | --VERSION_BEGIN 13.0 cbx_cycloneii 2013:04:24:18:08:47:SJ cbx_lpm_add_sub 2013:04:24:18:08:47:SJ cbx_lpm_mult 2013:04:24:18:08:47:SJ cbx_mgl 2013:04:24:18:11:10:SJ cbx_padd 2013:04:24:18:08:47:SJ cbx_stratix 2013:04:24:18:08:47:SJ cbx_stratixii 2013:04:24:18:08:47:SJ cbx_util_mgl 2013:04:24:18:08:47:SJ VERSION_END 3 | 4 | 5 | -- Copyright (C) 1991-2013 Altera Corporation 6 | -- Your use of Altera Corporation's design tools, logic functions 7 | -- and other software and tools, and its AMPP partner logic 8 | -- functions, and any output files from any of the foregoing 9 | -- (including device programming or simulation files), and any 10 | -- associated documentation or information are expressly subject 11 | -- to the terms and conditions of the Altera Program License 12 | -- Subscription Agreement, Altera MegaCore Function License 13 | -- Agreement, or other applicable license agreement, including, 14 | -- without limitation, that your use is for the sole purpose of 15 | -- programming logic devices manufactured by Altera and sold by 16 | -- Altera or its authorized distributors. Please refer to the 17 | -- applicable agreement for further details. 18 | 19 | 20 | FUNCTION cycloneive_mac_mult (aclr, clk, dataa[dataa_width-1..0], datab[datab_width-1..0], ena, signa, signb) 21 | WITH ( dataa_clock, dataa_width, datab_clock, datab_width, signa_clock, signb_clock) 22 | RETURNS ( dataout[dataa_width+datab_width-1..0]); 23 | FUNCTION cycloneive_mac_out (aclr, clk, dataa[dataa_width-1..0], ena) 24 | WITH ( dataa_width = 0, output_clock) 25 | RETURNS ( dataout[dataa_width-1..0]); 26 | 27 | --synthesis_resources = dsp_9bit 1 28 | SUBDESIGN mult_b3t 29 | ( 30 | dataa[8..0] : input; 31 | datab[8..0] : input; 32 | result[17..0] : output; 33 | ) 34 | VARIABLE 35 | mac_mult1 : cycloneive_mac_mult 36 | WITH ( 37 | dataa_clock = "none", 38 | dataa_width = 9, 39 | datab_clock = "none", 40 | datab_width = 9, 41 | signa_clock = "none", 42 | signb_clock = "none" 43 | ); 44 | mac_out2 : cycloneive_mac_out 45 | WITH ( 46 | dataa_width = 18, 47 | output_clock = "none" 48 | ); 49 | 50 | BEGIN 51 | mac_mult1.dataa[] = ( dataa[]); 52 | mac_mult1.datab[] = ( datab[]); 53 | mac_mult1.signa = B"1"; 54 | mac_mult1.signb = B"1"; 55 | mac_out2.dataa[] = mac_mult1.dataout[]; 56 | result[17..0] = mac_out2.dataout[17..0]; 57 | END; 58 | --VALID FILE 59 | -------------------------------------------------------------------------------- /FPGA_WORK/proj/fft.qpf: -------------------------------------------------------------------------------- 1 | # -------------------------------------------------------------------------- # 2 | # 3 | # Copyright (C) 1991-2013 Altera Corporation 4 | # Your use of Altera Corporation's design tools, logic functions 5 | # and other software and tools, and its AMPP partner logic 6 | # functions, and any output files from any of the foregoing 7 | # (including device programming or simulation files), and any 8 | # associated documentation or information are expressly subject 9 | # to the terms and conditions of the Altera Program License 10 | # Subscription Agreement, Altera MegaCore Function License 11 | # Agreement, or other applicable license agreement, including, 12 | # without limitation, that your use is for the sole purpose of 13 | # programming logic devices manufactured by Altera and sold by 14 | # Altera or its authorized distributors. Please refer to the 15 | # applicable agreement for further details. 16 | # 17 | # -------------------------------------------------------------------------- # 18 | # 19 | # Quartus II 64-Bit 20 | # Version 13.0.0 Build 156 04/24/2013 SJ Full Version 21 | # Date created = 10:26:31 September 19, 2018 22 | # 23 | # -------------------------------------------------------------------------- # 24 | 25 | QUARTUS_VERSION = "13.0" 26 | DATE = "10:26:31 September 19, 2018" 27 | 28 | # Revisions 29 | 30 | PROJECT_REVISION = "fft" 31 | -------------------------------------------------------------------------------- /FPGA_WORK/proj/fft.qsf: -------------------------------------------------------------------------------- 1 | # -------------------------------------------------------------------------- # 2 | # 3 | # Copyright (C) 1991-2013 Altera Corporation 4 | # Your use of Altera Corporation's design tools, logic functions 5 | # and other software and tools, and its AMPP partner logic 6 | # functions, and any output files from any of the foregoing 7 | # (including device programming or simulation files), and any 8 | # associated documentation or information are expressly subject 9 | # to the terms and conditions of the Altera Program License 10 | # Subscription Agreement, Altera MegaCore Function License 11 | # Agreement, or other applicable license agreement, including, 12 | # without limitation, that your use is for the sole purpose of 13 | # programming logic devices manufactured by Altera and sold by 14 | # Altera or its authorized distributors. Please refer to the 15 | # applicable agreement for further details. 16 | # 17 | # -------------------------------------------------------------------------- # 18 | # 19 | # Quartus II 64-Bit 20 | # Version 13.0.0 Build 156 04/24/2013 SJ Full Version 21 | # Date created = 10:26:31 September 19, 2018 22 | # 23 | # -------------------------------------------------------------------------- # 24 | # 25 | # Notes: 26 | # 27 | # 1) The default values for assignments are stored in the file: 28 | # fft_assignment_defaults.qdf 29 | # If this file doesn't exist, see file: 30 | # assignment_defaults.qdf 31 | # 32 | # 2) Altera recommends that you do not modify this file. This 33 | # file is updated automatically by the Quartus II software 34 | # and any changes you make may be lost or overwritten. 35 | # 36 | # -------------------------------------------------------------------------- # 37 | 38 | 39 | set_global_assignment -name FAMILY "Cyclone IV E" 40 | set_global_assignment -name DEVICE EP4CE10F17C8 41 | set_global_assignment -name TOP_LEVEL_ENTITY fft 42 | set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.0 43 | set_global_assignment -name PROJECT_CREATION_TIME_DATE "10:26:31 SEPTEMBER 19, 2018" 44 | set_global_assignment -name LAST_QUARTUS_VERSION "17.1.0 Standard Edition" 45 | set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files 46 | set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 47 | set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 48 | set_global_assignment -name DEVICE_FILTER_PIN_COUNT 256 49 | set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8 50 | set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 51 | set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V 52 | set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (Verilog)" 53 | set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation 54 | set_global_assignment -name VERILOG_FILE ../rtl/fft.v 55 | set_global_assignment -name VERILOG_FILE ../testbench/fft_mult_tb.v 56 | set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation 57 | set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS TEST_BENCH_MODE -section_id eda_simulation 58 | set_global_assignment -name EDA_NATIVELINK_SIMULATION_TEST_BENCH fft_tb -section_id eda_simulation 59 | set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" 60 | set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" 61 | set_global_assignment -name VERILOG_FILE ../rtl/butterfly_ra2.v 62 | set_global_assignment -name VERILOG_FILE ../testbench/butterfly_ra2_tb.v 63 | set_global_assignment -name QIP_FILE ../ip/ram128.qip 64 | set_global_assignment -name VERILOG_FILE ../rtl/butterfly_ra2_seri.v 65 | set_global_assignment -name VERILOG_FILE ../testbench/butterfly_ra2_seri_tb.v 66 | set_global_assignment -name VERILOG_FILE ../testbench/address_gererate_tb.v 67 | set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top 68 | set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top 69 | set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top 70 | set_global_assignment -name VERILOG_FILE ../testbench/fft_tb.v 71 | set_global_assignment -name EDA_TEST_BENCH_NAME fft_tb -section_id eda_simulation 72 | set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id fft_tb 73 | set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME fft_tb -section_id fft_tb 74 | set_global_assignment -name EDA_TEST_BENCH_FILE ../testbench/fft_tb.v -section_id fft_tb 75 | set_global_assignment -name QIP_FILE ../ip/wnp.qip 76 | set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top -------------------------------------------------------------------------------- /FPGA_WORK/proj/fft.qws: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/DeamonYang/FPGA_FFT/fa3b99e23651234b410932c9e37d66598745853f/FPGA_WORK/proj/fft.qws -------------------------------------------------------------------------------- /FPGA_WORK/proj/fft_nativelink_simulation.rpt: -------------------------------------------------------------------------------- 1 | Info: Start Nativelink Simulation process 2 | Info: NativeLink has detected Verilog design -- Verilog simulation models will be used 3 | 4 | ========= EDA Simulation Settings ===================== 5 | 6 | Sim Mode : RTL 7 | Family : cycloneive 8 | Quartus root : d:/majorsoft/soft/quartus13/quartus/bin/ 9 | Quartus sim root : d:/majorsoft/soft/quartus13/quartus/eda/sim_lib 10 | Simulation Tool : modelsim-altera 11 | Simulation Language : verilog 12 | Simulation Mode : GUI 13 | Sim Output File : 14 | Sim SDF file : 15 | Sim dir : simulation\modelsim 16 | 17 | ======================================================= 18 | 19 | Info: Starting NativeLink simulation with ModelSim-Altera software 20 | Sourced NativeLink script d:/majorsoft/soft/quartus13/quartus/common/tcl/internal/nativelink/modelsim.tcl 21 | Warning: File fft_run_msim_rtl_verilog.do already exists - backing up current file as fft_run_msim_rtl_verilog.do.bak11 22 | Info: Spawning ModelSim-Altera Simulation software 23 | -------------------------------------------------------------------------------- /FPGA_WORK/proj/greybox_tmp/cbx_args.txt: -------------------------------------------------------------------------------- 1 | MSW_SUBTRACT=NO 2 | PIPELINE=0 3 | REPRESENTATION=UNSIGNED 4 | RESULT_ALIGNMENT=LSB 5 | SHIFT=0 6 | SIZE=8 7 | WIDTH=8 8 | WIDTHR=11 9 | DEVICE_FAMILY="Cyclone IV E" 10 | data 11 | data 12 | data 13 | data 14 | data 15 | data 16 | data 17 | data 18 | result 19 | -------------------------------------------------------------------------------- /FPGA_WORK/proj/incremental_db/README: -------------------------------------------------------------------------------- 1 | This folder contains data for incremental compilation. 2 | 3 | The compiled_partitions sub-folder contains previous compilation results for each partition. 4 | As long as this folder is preserved, incremental compilation results from earlier compiles 5 | can be re-used. To perform a clean compilation from source files for all partitions, both 6 | the db and incremental_db folder should be removed. 7 | 8 | The imported_partitions sub-folder contains the last imported QXP for each imported partition. 9 | As long as this folder is preserved, imported partitions will be automatically re-imported 10 | when the db or incremental_db/compiled_partitions folders are removed. 11 | 12 | -------------------------------------------------------------------------------- /FPGA_WORK/proj/incremental_db/compiled_partitions/fft.db_info: -------------------------------------------------------------------------------- 1 | Quartus_Version = Version 17.1.0 Build 590 10/25/2017 SJ Standard Edition 2 | Version_Index = 453135872 3 | Creation_Time = Mon Feb 18 16:36:53 2019 4 | -------------------------------------------------------------------------------- /FPGA_WORK/proj/incremental_db/compiled_partitions/fft.root_partition.cmp.dfp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/DeamonYang/FPGA_FFT/fa3b99e23651234b410932c9e37d66598745853f/FPGA_WORK/proj/incremental_db/compiled_partitions/fft.root_partition.cmp.dfp -------------------------------------------------------------------------------- /FPGA_WORK/proj/incremental_db/compiled_partitions/fft.root_partition.cmp.kpt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/DeamonYang/FPGA_FFT/fa3b99e23651234b410932c9e37d66598745853f/FPGA_WORK/proj/incremental_db/compiled_partitions/fft.root_partition.cmp.kpt -------------------------------------------------------------------------------- /FPGA_WORK/proj/incremental_db/compiled_partitions/fft.root_partition.cmp.logdb: -------------------------------------------------------------------------------- 1 | v1 2 | DSP_BALANCING_IMPLEMENTATION,DSP_BLOCKS,butterfly_ra2_seri:bfcalc|butterfly_ra2:bflab1|lpm_mult:Mult0|mult_73t:auto_generated|mac_out2, 3 | DSP_BALANCING_IMPLEMENTATION,DSP_BLOCKS,butterfly_ra2_seri:bfcalc|butterfly_ra2:bflab1|lpm_mult:Mult1|mult_73t:auto_generated|mac_out2, 4 | DSP_BALANCING_IMPLEMENTATION,DSP_BLOCKS,butterfly_ra2_seri:bfcalc|butterfly_ra2:bflab1|lpm_mult:Mult2|mult_73t:auto_generated|mac_out2, 5 | DSP_BALANCING_IMPLEMENTATION,DSP_BLOCKS,butterfly_ra2_seri:bfcalc|butterfly_ra2:bflab1|lpm_mult:Mult3|mult_73t:auto_generated|mac_out2, 6 | PORT_SWAPPING,PORT_SWAPPING_FINISHED,butterfly_ra2_seri:bfcalc|butterfly_ra2:bflab1|lpm_mult:Mult3|mult_73t:auto_generated|mac_mult1, 7 | -------------------------------------------------------------------------------- /FPGA_WORK/proj/incremental_db/compiled_partitions/fft.root_partition.map.dpi: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/DeamonYang/FPGA_FFT/fa3b99e23651234b410932c9e37d66598745853f/FPGA_WORK/proj/incremental_db/compiled_partitions/fft.root_partition.map.dpi -------------------------------------------------------------------------------- /FPGA_WORK/proj/incremental_db/compiled_partitions/fft.root_partition.map.kpt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/DeamonYang/FPGA_FFT/fa3b99e23651234b410932c9e37d66598745853f/FPGA_WORK/proj/incremental_db/compiled_partitions/fft.root_partition.map.kpt -------------------------------------------------------------------------------- /FPGA_WORK/proj/output_files/fft.asm.rpt: -------------------------------------------------------------------------------- 1 | Assembler report for fft 2 | Sat Sep 22 20:13:00 2018 3 | Quartus II 64-Bit Version 13.0.0 Build 156 04/24/2013 SJ Full Version 4 | 5 | 6 | --------------------- 7 | ; Table of Contents ; 8 | --------------------- 9 | 1. Legal Notice 10 | 2. Assembler Summary 11 | 3. Assembler Settings 12 | 4. Assembler Generated Files 13 | 5. Assembler Device Options: G:/FPWG_WORK/FPGA_W/FFT_S1/FFT_20180922/proj/output_files/fft.sof 14 | 6. Assembler Messages 15 | 16 | 17 | 18 | ---------------- 19 | ; Legal Notice ; 20 | ---------------- 21 | Copyright (C) 1991-2013 Altera Corporation 22 | Your use of Altera Corporation's design tools, logic functions 23 | and other software and tools, and its AMPP partner logic 24 | functions, and any output files from any of the foregoing 25 | (including device programming or simulation files), and any 26 | associated documentation or information are expressly subject 27 | to the terms and conditions of the Altera Program License 28 | Subscription Agreement, Altera MegaCore Function License 29 | Agreement, or other applicable license agreement, including, 30 | without limitation, that your use is for the sole purpose of 31 | programming logic devices manufactured by Altera and sold by 32 | Altera or its authorized distributors. Please refer to the 33 | applicable agreement for further details. 34 | 35 | 36 | 37 | +---------------------------------------------------------------+ 38 | ; Assembler Summary ; 39 | +-----------------------+---------------------------------------+ 40 | ; Assembler Status ; Successful - Sat Sep 22 20:13:00 2018 ; 41 | ; Revision Name ; fft ; 42 | ; Top-level Entity Name ; fft ; 43 | ; Family ; Cyclone IV E ; 44 | ; Device ; EP4CE10F17C8 ; 45 | +-----------------------+---------------------------------------+ 46 | 47 | 48 | +--------------------------------------------------------------------------------------------------------+ 49 | ; Assembler Settings ; 50 | +-----------------------------------------------------------------------------+----------+---------------+ 51 | ; Option ; Setting ; Default Value ; 52 | +-----------------------------------------------------------------------------+----------+---------------+ 53 | ; Use smart compilation ; Off ; Off ; 54 | ; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ; 55 | ; Enable compact report table ; Off ; Off ; 56 | ; Generate compressed bitstreams ; On ; On ; 57 | ; Compression mode ; Off ; Off ; 58 | ; Clock source for configuration device ; Internal ; Internal ; 59 | ; Clock frequency of the configuration device ; 10 MHZ ; 10 MHz ; 60 | ; Divide clock frequency by ; 1 ; 1 ; 61 | ; Auto user code ; On ; On ; 62 | ; Use configuration device ; Off ; Off ; 63 | ; Configuration device ; Auto ; Auto ; 64 | ; Configuration device auto user code ; Off ; Off ; 65 | ; Generate Tabular Text File (.ttf) For Target Device ; Off ; Off ; 66 | ; Generate Raw Binary File (.rbf) For Target Device ; Off ; Off ; 67 | ; Generate Hexadecimal (Intel-Format) Output File (.hexout) for Target Device ; Off ; Off ; 68 | ; Hexadecimal Output File start address ; 0 ; 0 ; 69 | ; Hexadecimal Output File count direction ; Up ; Up ; 70 | ; Release clears before tri-states ; Off ; Off ; 71 | ; Auto-restart configuration after error ; On ; On ; 72 | ; Enable OCT_DONE ; Off ; Off ; 73 | ; Generate Serial Vector Format File (.svf) for Target Device ; Off ; Off ; 74 | ; Generate a JEDEC STAPL Format File (.jam) for Target Device ; Off ; Off ; 75 | ; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; Off ; Off ; 76 | ; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; On ; On ; 77 | +-----------------------------------------------------------------------------+----------+---------------+ 78 | 79 | 80 | +-------------------------------------------------------------------+ 81 | ; Assembler Generated Files ; 82 | +-------------------------------------------------------------------+ 83 | ; File Name ; 84 | +-------------------------------------------------------------------+ 85 | ; G:/FPWG_WORK/FPGA_W/FFT_S1/FFT_20180922/proj/output_files/fft.sof ; 86 | +-------------------------------------------------------------------+ 87 | 88 | 89 | +---------------------------------------------------------------------------------------------+ 90 | ; Assembler Device Options: G:/FPWG_WORK/FPGA_W/FFT_S1/FFT_20180922/proj/output_files/fft.sof ; 91 | +----------------+----------------------------------------------------------------------------+ 92 | ; Option ; Setting ; 93 | +----------------+----------------------------------------------------------------------------+ 94 | ; Device ; EP4CE10F17C8 ; 95 | ; JTAG usercode ; 0x000BA646 ; 96 | ; Checksum ; 0x000BA646 ; 97 | +----------------+----------------------------------------------------------------------------+ 98 | 99 | 100 | +--------------------+ 101 | ; Assembler Messages ; 102 | +--------------------+ 103 | Info: ******************************************************************* 104 | Info: Running Quartus II 64-Bit Assembler 105 | Info: Version 13.0.0 Build 156 04/24/2013 SJ Full Version 106 | Info: Processing started: Sat Sep 22 20:12:57 2018 107 | Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off fft -c fft 108 | Info (115031): Writing out detailed assembly data for power analysis 109 | Info (115030): Assembler is generating device programming files 110 | Info: Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings 111 | Info: Peak virtual memory: 4567 megabytes 112 | Info: Processing ended: Sat Sep 22 20:13:00 2018 113 | Info: Elapsed time: 00:00:03 114 | Info: Total CPU time (on all processors): 00:00:02 115 | 116 | 117 | -------------------------------------------------------------------------------- /FPGA_WORK/proj/output_files/fft.done: -------------------------------------------------------------------------------- 1 | Sat Sep 22 20:13:21 2018 2 | -------------------------------------------------------------------------------- /FPGA_WORK/proj/output_files/fft.eda.rpt: -------------------------------------------------------------------------------- 1 | EDA Netlist Writer report for fft 2 | Sat Sep 22 20:13:11 2018 3 | Quartus II 64-Bit Version 13.0.0 Build 156 04/24/2013 SJ Full Version 4 | 5 | 6 | --------------------- 7 | ; Table of Contents ; 8 | --------------------- 9 | 1. Legal Notice 10 | 2. EDA Netlist Writer Summary 11 | 3. Simulation Settings 12 | 4. Simulation Generated Files 13 | 5. EDA Netlist Writer Messages 14 | 15 | 16 | 17 | ---------------- 18 | ; Legal Notice ; 19 | ---------------- 20 | Copyright (C) 1991-2013 Altera Corporation 21 | Your use of Altera Corporation's design tools, logic functions 22 | and other software and tools, and its AMPP partner logic 23 | functions, and any output files from any of the foregoing 24 | (including device programming or simulation files), and any 25 | associated documentation or information are expressly subject 26 | to the terms and conditions of the Altera Program License 27 | Subscription Agreement, Altera MegaCore Function License 28 | Agreement, or other applicable license agreement, including, 29 | without limitation, that your use is for the sole purpose of 30 | programming logic devices manufactured by Altera and sold by 31 | Altera or its authorized distributors. Please refer to the 32 | applicable agreement for further details. 33 | 34 | 35 | 36 | +-------------------------------------------------------------------+ 37 | ; EDA Netlist Writer Summary ; 38 | +---------------------------+---------------------------------------+ 39 | ; EDA Netlist Writer Status ; Successful - Sat Sep 22 20:13:10 2018 ; 40 | ; Revision Name ; fft ; 41 | ; Top-level Entity Name ; fft ; 42 | ; Family ; Cyclone IV E ; 43 | ; Simulation Files Creation ; Successful ; 44 | +---------------------------+---------------------------------------+ 45 | 46 | 47 | +-------------------------------------------------------------------------------------------------------------------------------+ 48 | ; Simulation Settings ; 49 | +---------------------------------------------------------------------------------------------------+---------------------------+ 50 | ; Option ; Setting ; 51 | +---------------------------------------------------------------------------------------------------+---------------------------+ 52 | ; Tool Name ; ModelSim-Altera (Verilog) ; 53 | ; Generate netlist for functional simulation only ; Off ; 54 | ; Time scale ; 1 ps ; 55 | ; Truncate long hierarchy paths ; Off ; 56 | ; Map illegal HDL characters ; Off ; 57 | ; Flatten buses into individual nodes ; Off ; 58 | ; Maintain hierarchy ; Off ; 59 | ; Bring out device-wide set/reset signals as ports ; Off ; 60 | ; Enable glitch filtering ; Off ; 61 | ; Do not write top level VHDL entity ; Off ; 62 | ; Disable detection of setup and hold time violations in the input registers of bi-directional pins ; Off ; 63 | ; Architecture name in VHDL output netlist ; structure ; 64 | ; Generate third-party EDA tool command script for RTL functional simulation ; Off ; 65 | ; Generate third-party EDA tool command script for gate-level simulation ; Off ; 66 | +---------------------------------------------------------------------------------------------------+---------------------------+ 67 | 68 | 69 | +-----------------------------------------------------------------------------------------------+ 70 | ; Simulation Generated Files ; 71 | +-----------------------------------------------------------------------------------------------+ 72 | ; Generated Files ; 73 | +-----------------------------------------------------------------------------------------------+ 74 | ; G:/FPWG_WORK/FPGA_W/FFT_S1/FFT_20180922/proj/simulation/modelsim/fft_8_1200mv_85c_slow.vo ; 75 | ; G:/FPWG_WORK/FPGA_W/FFT_S1/FFT_20180922/proj/simulation/modelsim/fft_8_1200mv_0c_slow.vo ; 76 | ; G:/FPWG_WORK/FPGA_W/FFT_S1/FFT_20180922/proj/simulation/modelsim/fft_min_1200mv_0c_fast.vo ; 77 | ; G:/FPWG_WORK/FPGA_W/FFT_S1/FFT_20180922/proj/simulation/modelsim/fft.vo ; 78 | ; G:/FPWG_WORK/FPGA_W/FFT_S1/FFT_20180922/proj/simulation/modelsim/fft_8_1200mv_85c_v_slow.sdo ; 79 | ; G:/FPWG_WORK/FPGA_W/FFT_S1/FFT_20180922/proj/simulation/modelsim/fft_8_1200mv_0c_v_slow.sdo ; 80 | ; G:/FPWG_WORK/FPGA_W/FFT_S1/FFT_20180922/proj/simulation/modelsim/fft_min_1200mv_0c_v_fast.sdo ; 81 | ; G:/FPWG_WORK/FPGA_W/FFT_S1/FFT_20180922/proj/simulation/modelsim/fft_v.sdo ; 82 | +-----------------------------------------------------------------------------------------------+ 83 | 84 | 85 | +-----------------------------+ 86 | ; EDA Netlist Writer Messages ; 87 | +-----------------------------+ 88 | Info: ******************************************************************* 89 | Info: Running Quartus II 64-Bit EDA Netlist Writer 90 | Info: Version 13.0.0 Build 156 04/24/2013 SJ Full Version 91 | Info: Processing started: Sat Sep 22 20:13:08 2018 92 | Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off fft -c fft 93 | Info (204019): Generated file fft_8_1200mv_85c_slow.vo in folder "G:/FPWG_WORK/FPGA_W/FFT_S1/FFT_20180922/proj/simulation/modelsim/" for EDA simulation tool 94 | Info (204019): Generated file fft_8_1200mv_0c_slow.vo in folder "G:/FPWG_WORK/FPGA_W/FFT_S1/FFT_20180922/proj/simulation/modelsim/" for EDA simulation tool 95 | Info (204019): Generated file fft_min_1200mv_0c_fast.vo in folder "G:/FPWG_WORK/FPGA_W/FFT_S1/FFT_20180922/proj/simulation/modelsim/" for EDA simulation tool 96 | Info (204019): Generated file fft.vo in folder "G:/FPWG_WORK/FPGA_W/FFT_S1/FFT_20180922/proj/simulation/modelsim/" for EDA simulation tool 97 | Info (204019): Generated file fft_8_1200mv_85c_v_slow.sdo in folder "G:/FPWG_WORK/FPGA_W/FFT_S1/FFT_20180922/proj/simulation/modelsim/" for EDA simulation tool 98 | Info (204019): Generated file fft_8_1200mv_0c_v_slow.sdo in folder "G:/FPWG_WORK/FPGA_W/FFT_S1/FFT_20180922/proj/simulation/modelsim/" for EDA simulation tool 99 | Info (204019): Generated file fft_min_1200mv_0c_v_fast.sdo in folder "G:/FPWG_WORK/FPGA_W/FFT_S1/FFT_20180922/proj/simulation/modelsim/" for EDA simulation tool 100 | Info (204019): Generated file fft_v.sdo in folder "G:/FPWG_WORK/FPGA_W/FFT_S1/FFT_20180922/proj/simulation/modelsim/" for EDA simulation tool 101 | Info: Quartus II 64-Bit EDA Netlist Writer was successful. 0 errors, 0 warnings 102 | Info: Peak virtual memory: 4550 megabytes 103 | Info: Processing ended: Sat Sep 22 20:13:11 2018 104 | Info: Elapsed time: 00:00:03 105 | Info: Total CPU time (on all processors): 00:00:02 106 | 107 | 108 | -------------------------------------------------------------------------------- /FPGA_WORK/proj/output_files/fft.fit.rpt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/DeamonYang/FPGA_FFT/fa3b99e23651234b410932c9e37d66598745853f/FPGA_WORK/proj/output_files/fft.fit.rpt -------------------------------------------------------------------------------- /FPGA_WORK/proj/output_files/fft.fit.smsg: -------------------------------------------------------------------------------- 1 | Extra Info (176273): Performing register packing on registers with non-logic cell location assignments 2 | Extra Info (176274): Completed register packing on registers with non-logic cell location assignments 3 | Extra Info (176236): Started Fast Input/Output/OE register processing 4 | Extra Info (176237): Finished Fast Input/Output/OE register processing 5 | Extra Info (176248): Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density 6 | Extra Info (176249): Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks 7 | -------------------------------------------------------------------------------- /FPGA_WORK/proj/output_files/fft.fit.summary: -------------------------------------------------------------------------------- 1 | Fitter Status : Successful - Sat Sep 22 20:12:54 2018 2 | Quartus II 64-Bit Version : 13.0.0 Build 156 04/24/2013 SJ Full Version 3 | Revision Name : fft 4 | Top-level Entity Name : fft 5 | Family : Cyclone IV E 6 | Device : EP4CE10F17C8 7 | Timing Models : Final 8 | Total logic elements : 300 / 10,320 ( 3 % ) 9 | Total combinational functions : 264 / 10,320 ( 3 % ) 10 | Dedicated logic registers : 188 / 10,320 ( 2 % ) 11 | Total registers : 188 12 | Total pins : 28 / 180 ( 16 % ) 13 | Total virtual pins : 0 14 | Total memory bits : 3,072 / 423,936 ( < 1 % ) 15 | Embedded Multiplier 9-bit elements : 4 / 46 ( 9 % ) 16 | Total PLLs : 0 / 2 ( 0 % ) 17 | -------------------------------------------------------------------------------- /FPGA_WORK/proj/output_files/fft.flow.rpt: -------------------------------------------------------------------------------- 1 | Flow report for fft 2 | Sat Sep 22 20:13:11 2018 3 | Quartus II 64-Bit Version 13.0.0 Build 156 04/24/2013 SJ Full Version 4 | 5 | 6 | --------------------- 7 | ; Table of Contents ; 8 | --------------------- 9 | 1. Legal Notice 10 | 2. Flow Summary 11 | 3. Flow Settings 12 | 4. Flow Non-Default Global Settings 13 | 5. Flow Elapsed Time 14 | 6. Flow OS Summary 15 | 7. Flow Log 16 | 8. Flow Messages 17 | 9. Flow Suppressed Messages 18 | 19 | 20 | 21 | ---------------- 22 | ; Legal Notice ; 23 | ---------------- 24 | Copyright (C) 1991-2013 Altera Corporation 25 | Your use of Altera Corporation's design tools, logic functions 26 | and other software and tools, and its AMPP partner logic 27 | functions, and any output files from any of the foregoing 28 | (including device programming or simulation files), and any 29 | associated documentation or information are expressly subject 30 | to the terms and conditions of the Altera Program License 31 | Subscription Agreement, Altera MegaCore Function License 32 | Agreement, or other applicable license agreement, including, 33 | without limitation, that your use is for the sole purpose of 34 | programming logic devices manufactured by Altera and sold by 35 | Altera or its authorized distributors. Please refer to the 36 | applicable agreement for further details. 37 | 38 | 39 | 40 | +----------------------------------------------------------------------------------+ 41 | ; Flow Summary ; 42 | +------------------------------------+---------------------------------------------+ 43 | ; Flow Status ; Successful - Sat Sep 22 20:13:10 2018 ; 44 | ; Quartus II 64-Bit Version ; 13.0.0 Build 156 04/24/2013 SJ Full Version ; 45 | ; Revision Name ; fft ; 46 | ; Top-level Entity Name ; fft ; 47 | ; Family ; Cyclone IV E ; 48 | ; Device ; EP4CE10F17C8 ; 49 | ; Timing Models ; Final ; 50 | ; Total logic elements ; 300 / 10,320 ( 3 % ) ; 51 | ; Total combinational functions ; 264 / 10,320 ( 3 % ) ; 52 | ; Dedicated logic registers ; 188 / 10,320 ( 2 % ) ; 53 | ; Total registers ; 188 ; 54 | ; Total pins ; 28 / 180 ( 16 % ) ; 55 | ; Total virtual pins ; 0 ; 56 | ; Total memory bits ; 3,072 / 423,936 ( < 1 % ) ; 57 | ; Embedded Multiplier 9-bit elements ; 4 / 46 ( 9 % ) ; 58 | ; Total PLLs ; 0 / 2 ( 0 % ) ; 59 | +------------------------------------+---------------------------------------------+ 60 | 61 | 62 | +-----------------------------------------+ 63 | ; Flow Settings ; 64 | +-------------------+---------------------+ 65 | ; Option ; Setting ; 66 | +-------------------+---------------------+ 67 | ; Start date & time ; 09/22/2018 20:12:32 ; 68 | ; Main task ; Compilation ; 69 | ; Revision Name ; fft ; 70 | +-------------------+---------------------+ 71 | 72 | 73 | +-----------------------------------------------------------------------------------------------------------------------------+ 74 | ; Flow Non-Default Global Settings ; 75 | +--------------------------------------+---------------------------------------+---------------+-------------+----------------+ 76 | ; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ; 77 | +--------------------------------------+---------------------------------------+---------------+-------------+----------------+ 78 | ; COMPILER_SIGNATURE_ID ; 345052807169.153761835224008 ; -- ; -- ; -- ; 79 | ; EDA_DESIGN_INSTANCE_NAME ; NA ; -- ; -- ; fft_tb ; 80 | ; EDA_NATIVELINK_SIMULATION_TEST_BENCH ; fft_tb ; -- ; -- ; eda_simulation ; 81 | ; EDA_OUTPUT_DATA_FORMAT ; Verilog Hdl ; -- ; -- ; eda_simulation ; 82 | ; EDA_SIMULATION_TOOL ; ModelSim-Altera (Verilog) ; ; -- ; -- ; 83 | ; EDA_TEST_BENCH_ENABLE_STATUS ; TEST_BENCH_MODE ; -- ; -- ; eda_simulation ; 84 | ; EDA_TEST_BENCH_FILE ; ../testbench/fft_tb.v ; -- ; -- ; fft_tb ; 85 | ; EDA_TEST_BENCH_MODULE_NAME ; fft_tb ; -- ; -- ; fft_tb ; 86 | ; EDA_TEST_BENCH_NAME ; fft_tb ; -- ; -- ; eda_simulation ; 87 | ; EDA_TIME_SCALE ; 1 ps ; -- ; -- ; eda_simulation ; 88 | ; IP_TOOL_NAME ; RAM: 1-PORT ; -- ; -- ; -- ; 89 | ; IP_TOOL_NAME ; ROM: 1-PORT ; -- ; -- ; -- ; 90 | ; IP_TOOL_VERSION ; 13.0 ; -- ; -- ; -- ; 91 | ; IP_TOOL_VERSION ; 13.0 ; -- ; -- ; -- ; 92 | ; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ; 93 | ; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ; 94 | ; MISC_FILE ; ../ip/ram128_inst.v ; -- ; -- ; -- ; 95 | ; MISC_FILE ; ../ip/ram128_bb.v ; -- ; -- ; -- ; 96 | ; MISC_FILE ; ../ip/wnp_inst.v ; -- ; -- ; -- ; 97 | ; MISC_FILE ; ../ip/wnp_bb.v ; -- ; -- ; -- ; 98 | ; NOMINAL_CORE_SUPPLY_VOLTAGE ; 1.2V ; -- ; -- ; -- ; 99 | ; PARTITION_COLOR ; 16764057 ; -- ; -- ; Top ; 100 | ; PARTITION_FITTER_PRESERVATION_LEVEL ; PLACEMENT_AND_ROUTING ; -- ; -- ; Top ; 101 | ; PARTITION_NETLIST_TYPE ; SOURCE ; -- ; -- ; Top ; 102 | ; POWER_BOARD_THERMAL_MODEL ; None (CONSERVATIVE) ; -- ; -- ; -- ; 103 | ; POWER_PRESET_COOLING_SOLUTION ; 23 MM HEAT SINK WITH 200 LFPM AIRFLOW ; -- ; -- ; -- ; 104 | ; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ; 105 | +--------------------------------------+---------------------------------------+---------------+-------------+----------------+ 106 | 107 | 108 | +-------------------------------------------------------------------------------------------------------------------------------+ 109 | ; Flow Elapsed Time ; 110 | +---------------------------+--------------+-------------------------+---------------------+------------------------------------+ 111 | ; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ; 112 | +---------------------------+--------------+-------------------------+---------------------+------------------------------------+ 113 | ; Analysis & Synthesis ; 00:00:05 ; 1.0 ; 4646 MB ; 00:00:05 ; 114 | ; Fitter ; 00:00:16 ; 1.5 ; 5351 MB ; 00:00:16 ; 115 | ; Assembler ; 00:00:03 ; 1.0 ; 4567 MB ; 00:00:02 ; 116 | ; TimeQuest Timing Analyzer ; 00:00:06 ; 1.0 ; 4645 MB ; 00:00:05 ; 117 | ; EDA Netlist Writer ; 00:00:02 ; 1.0 ; 4538 MB ; 00:00:02 ; 118 | ; Total ; 00:00:32 ; -- ; -- ; 00:00:30 ; 119 | +---------------------------+--------------+-------------------------+---------------------+------------------------------------+ 120 | 121 | 122 | +----------------------------------------------------------------------------------------+ 123 | ; Flow OS Summary ; 124 | +---------------------------+------------------+-----------+------------+----------------+ 125 | ; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ; 126 | +---------------------------+------------------+-----------+------------+----------------+ 127 | ; Analysis & Synthesis ; DESKTOP-V0SMT60 ; Windows 7 ; 6.2 ; x86_64 ; 128 | ; Fitter ; DESKTOP-V0SMT60 ; Windows 7 ; 6.2 ; x86_64 ; 129 | ; Assembler ; DESKTOP-V0SMT60 ; Windows 7 ; 6.2 ; x86_64 ; 130 | ; TimeQuest Timing Analyzer ; DESKTOP-V0SMT60 ; Windows 7 ; 6.2 ; x86_64 ; 131 | ; EDA Netlist Writer ; DESKTOP-V0SMT60 ; Windows 7 ; 6.2 ; x86_64 ; 132 | +---------------------------+------------------+-----------+------------+----------------+ 133 | 134 | 135 | ------------ 136 | ; Flow Log ; 137 | ------------ 138 | quartus_map --read_settings_files=on --write_settings_files=off fft -c fft 139 | quartus_fit --read_settings_files=off --write_settings_files=off fft -c fft 140 | quartus_asm --read_settings_files=off --write_settings_files=off fft -c fft 141 | quartus_sta fft -c fft 142 | quartus_eda --read_settings_files=off --write_settings_files=off fft -c fft 143 | 144 | 145 | 146 | -------------------------------------------------------------------------------- /FPGA_WORK/proj/output_files/fft.jdi: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | -------------------------------------------------------------------------------- /FPGA_WORK/proj/output_files/fft.map.smsg: -------------------------------------------------------------------------------- 1 | Warning (10268): Verilog HDL information at butterfly_ra2.v(59): always construct contains both blocking and non-blocking assignments 2 | -------------------------------------------------------------------------------- /FPGA_WORK/proj/output_files/fft.map.summary: -------------------------------------------------------------------------------- 1 | Analysis & Synthesis Status : Successful - Sat Sep 22 20:12:37 2018 2 | Quartus II 64-Bit Version : 13.0.0 Build 156 04/24/2013 SJ Full Version 3 | Revision Name : fft 4 | Top-level Entity Name : fft 5 | Family : Cyclone IV E 6 | Total logic elements : 404 7 | Total combinational functions : 264 8 | Dedicated logic registers : 268 9 | Total registers : 268 10 | Total pins : 28 11 | Total virtual pins : 0 12 | Total memory bits : 3,072 13 | Embedded Multiplier 9-bit elements : 4 14 | Total PLLs : 0 15 | -------------------------------------------------------------------------------- /FPGA_WORK/proj/output_files/fft.sof: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/DeamonYang/FPGA_FFT/fa3b99e23651234b410932c9e37d66598745853f/FPGA_WORK/proj/output_files/fft.sof -------------------------------------------------------------------------------- /FPGA_WORK/proj/output_files/fft.sta.summary: -------------------------------------------------------------------------------- 1 | ------------------------------------------------------------ 2 | TimeQuest Timing Analyzer Summary 3 | ------------------------------------------------------------ 4 | 5 | Type : Slow 1200mV 85C Model Setup 'clk' 6 | Slack : -5.182 7 | TNS : -835.119 8 | 9 | Type : Slow 1200mV 85C Model Hold 'clk' 10 | Slack : 0.421 11 | TNS : 0.000 12 | 13 | Type : Slow 1200mV 85C Model Minimum Pulse Width 'clk' 14 | Slack : -3.201 15 | TNS : -346.576 16 | 17 | Type : Slow 1200mV 0C Model Setup 'clk' 18 | Slack : -4.727 19 | TNS : -754.470 20 | 21 | Type : Slow 1200mV 0C Model Hold 'clk' 22 | Slack : 0.381 23 | TNS : 0.000 24 | 25 | Type : Slow 1200mV 0C Model Minimum Pulse Width 'clk' 26 | Slack : -3.201 27 | TNS : -346.576 28 | 29 | Type : Fast 1200mV 0C Model Setup 'clk' 30 | Slack : -1.770 31 | TNS : -211.091 32 | 33 | Type : Fast 1200mV 0C Model Hold 'clk' 34 | Slack : 0.147 35 | TNS : 0.000 36 | 37 | Type : Fast 1200mV 0C Model Minimum Pulse Width 'clk' 38 | Slack : -3.000 39 | TNS : -231.690 40 | 41 | ------------------------------------------------------------ 42 | -------------------------------------------------------------------------------- /FPGA_WORK/proj/ram128.qip: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/DeamonYang/FPGA_FFT/fa3b99e23651234b410932c9e37d66598745853f/FPGA_WORK/proj/ram128.qip -------------------------------------------------------------------------------- /FPGA_WORK/proj/simulation/modelsim/fft.sft: -------------------------------------------------------------------------------- 1 | set tool_name "ModelSim-Altera (Verilog)" 2 | set corner_file_list { 3 | {{"Slow -8 1.2V 85 Model"} {fft_8_1200mv_85c_slow.vo fft_8_1200mv_85c_v_slow.sdo}} 4 | {{"Slow -8 1.2V 0 Model"} {fft_8_1200mv_0c_slow.vo fft_8_1200mv_0c_v_slow.sdo}} 5 | {{"Fast -M 1.2V 0 Model"} {fft_min_1200mv_0c_fast.vo fft_min_1200mv_0c_v_fast.sdo}} 6 | } 7 | -------------------------------------------------------------------------------- /FPGA_WORK/proj/simulation/modelsim/fft_run_msim_rtl_verilog.do: -------------------------------------------------------------------------------- 1 | transcript on 2 | if {[file exists rtl_work]} { 3 | vdel -lib rtl_work -all 4 | } 5 | vlib rtl_work 6 | vmap work rtl_work 7 | 8 | vlog -vlog01compat -work work +incdir+G:/FPWG_WORK/FPGA_W/FFT_S1/FFT_20180922/rtl {G:/FPWG_WORK/FPGA_W/FFT_S1/FFT_20180922/rtl/fft.v} 9 | vlog -vlog01compat -work work +incdir+G:/FPWG_WORK/FPGA_W/FFT_S1/FFT_20180922/rtl {G:/FPWG_WORK/FPGA_W/FFT_S1/FFT_20180922/rtl/butterfly_ra2.v} 10 | vlog -vlog01compat -work work +incdir+G:/FPWG_WORK/FPGA_W/FFT_S1/FFT_20180922/ip {G:/FPWG_WORK/FPGA_W/FFT_S1/FFT_20180922/ip/ram128.v} 11 | vlog -vlog01compat -work work +incdir+G:/FPWG_WORK/FPGA_W/FFT_S1/FFT_20180922/rtl {G:/FPWG_WORK/FPGA_W/FFT_S1/FFT_20180922/rtl/butterfly_ra2_seri.v} 12 | vlog -vlog01compat -work work +incdir+G:/FPWG_WORK/FPGA_W/FFT_S1/FFT_20180922/ip {G:/FPWG_WORK/FPGA_W/FFT_S1/FFT_20180922/ip/wnp.v} 13 | 14 | vlog -vlog01compat -work work +incdir+G:/FPWG_WORK/FPGA_W/FFT_S1/FFT_20180922/proj/../testbench {G:/FPWG_WORK/FPGA_W/FFT_S1/FFT_20180922/proj/../testbench/fft_tb.v} 15 | 16 | vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cycloneive_ver -L rtl_work -L work -voptargs="+acc" fft_tb 17 | 18 | add wave * 19 | view structure 20 | view signals 21 | run -all 22 | -------------------------------------------------------------------------------- /FPGA_WORK/proj/simulation/modelsim/fft_run_msim_rtl_verilog.do.bak: -------------------------------------------------------------------------------- 1 | transcript on 2 | if {[file exists rtl_work]} { 3 | vdel -lib rtl_work -all 4 | } 5 | vlib rtl_work 6 | vmap work rtl_work 7 | 8 | vlog -vlog01compat -work work +incdir+G:/FPWG_WORK/FPGA_W/FFT_S1/rtl {G:/FPWG_WORK/FPGA_W/FFT_S1/rtl/fft.v} 9 | vlog -vlog01compat -work work +incdir+G:/FPWG_WORK/FPGA_W/FFT_S1/rtl {G:/FPWG_WORK/FPGA_W/FFT_S1/rtl/butterfly_ra2.v} 10 | vlog -vlog01compat -work work +incdir+G:/FPWG_WORK/FPGA_W/FFT_S1/ip {G:/FPWG_WORK/FPGA_W/FFT_S1/ip/ram128.v} 11 | vlog -vlog01compat -work work +incdir+G:/FPWG_WORK/FPGA_W/FFT_S1/rtl {G:/FPWG_WORK/FPGA_W/FFT_S1/rtl/butterfly_ra2_seri.v} 12 | vlog -vlog01compat -work work +incdir+G:/FPWG_WORK/FPGA_W/FFT_S1/ip {G:/FPWG_WORK/FPGA_W/FFT_S1/ip/wnp.v} 13 | 14 | vlog -vlog01compat -work work +incdir+G:/FPWG_WORK/FPGA_W/FFT_S1/proj/../testbench {G:/FPWG_WORK/FPGA_W/FFT_S1/proj/../testbench/fft_tb.v} 15 | 16 | vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cycloneive_ver -L rtl_work -L work -voptargs="+acc" fft_tb 17 | 18 | add wave * 19 | view structure 20 | view signals 21 | run -all 22 | -------------------------------------------------------------------------------- /FPGA_WORK/proj/simulation/modelsim/fft_run_msim_rtl_verilog.do.bak1: -------------------------------------------------------------------------------- 1 | transcript on 2 | if {[file exists rtl_work]} { 3 | vdel -lib rtl_work -all 4 | } 5 | vlib rtl_work 6 | vmap work rtl_work 7 | 8 | vlog -vlog01compat -work work +incdir+E:/FPGA/FFT_S1/rtl {E:/FPGA/FFT_S1/rtl/butterfly_ra2.v} 9 | 10 | vlog -vlog01compat -work work +incdir+E:/FPGA/FFT_S1/proj/../testbench {E:/FPGA/FFT_S1/proj/../testbench/butterfly_ra2_tb.v} 11 | 12 | vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cycloneive_ver -L rtl_work -L work -voptargs="+acc" butterfly_ra2_tb 13 | 14 | add wave * 15 | view structure 16 | view signals 17 | run -all 18 | -------------------------------------------------------------------------------- /FPGA_WORK/proj/simulation/modelsim/fft_run_msim_rtl_verilog.do.bak10: -------------------------------------------------------------------------------- 1 | transcript on 2 | if {[file exists rtl_work]} { 3 | vdel -lib rtl_work -all 4 | } 5 | vlib rtl_work 6 | vmap work rtl_work 7 | 8 | vlog -vlog01compat -work work +incdir+E:/FPGA/FFT_S1/rtl {E:/FPGA/FFT_S1/rtl/butterfly_ra2.v} 9 | 10 | vlog -vlog01compat -work work +incdir+E:/FPGA/FFT_S1/proj/../testbench {E:/FPGA/FFT_S1/proj/../testbench/address_gererate_tb.v} 11 | 12 | vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cycloneive_ver -L rtl_work -L work -voptargs="+acc" address_gererate_tb 13 | 14 | add wave * 15 | view structure 16 | view signals 17 | run -all 18 | -------------------------------------------------------------------------------- /FPGA_WORK/proj/simulation/modelsim/fft_run_msim_rtl_verilog.do.bak11: -------------------------------------------------------------------------------- 1 | transcript on 2 | if {[file exists rtl_work]} { 3 | vdel -lib rtl_work -all 4 | } 5 | vlib rtl_work 6 | vmap work rtl_work 7 | 8 | vlog -vlog01compat -work work +incdir+E:/FPGA/FFT/FFT_20180921/rtl {E:/FPGA/FFT/FFT_20180921/rtl/fft.v} 9 | vlog -vlog01compat -work work +incdir+E:/FPGA/FFT/FFT_20180921/rtl {E:/FPGA/FFT/FFT_20180921/rtl/butterfly_ra2.v} 10 | vlog -vlog01compat -work work +incdir+E:/FPGA/FFT/FFT_20180921/ip {E:/FPGA/FFT/FFT_20180921/ip/ram128.v} 11 | vlog -vlog01compat -work work +incdir+E:/FPGA/FFT/FFT_20180921/rtl {E:/FPGA/FFT/FFT_20180921/rtl/butterfly_ra2_seri.v} 12 | vlog -vlog01compat -work work +incdir+E:/FPGA/FFT/FFT_20180921/ip {E:/FPGA/FFT/FFT_20180921/ip/wnp.v} 13 | 14 | vlog -vlog01compat -work work +incdir+E:/FPGA/FFT/FFT_20180921/proj/../testbench {E:/FPGA/FFT/FFT_20180921/proj/../testbench/fft_tb.v} 15 | 16 | vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cycloneive_ver -L rtl_work -L work -voptargs="+acc" fft_tb 17 | 18 | add wave * 19 | view structure 20 | view signals 21 | run -all 22 | -------------------------------------------------------------------------------- /FPGA_WORK/proj/simulation/modelsim/fft_run_msim_rtl_verilog.do.bak2: -------------------------------------------------------------------------------- 1 | transcript on 2 | if {[file exists rtl_work]} { 3 | vdel -lib rtl_work -all 4 | } 5 | vlib rtl_work 6 | vmap work rtl_work 7 | 8 | vlog -vlog01compat -work work +incdir+E:/FPGA/FFT_S1/rtl {E:/FPGA/FFT_S1/rtl/butterfly_ra2.v} 9 | 10 | vlog -vlog01compat -work work +incdir+E:/FPGA/FFT_S1/proj/../testbench {E:/FPGA/FFT_S1/proj/../testbench/butterfly_ra2_seri_tb.v} 11 | 12 | vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cycloneive_ver -L rtl_work -L work -voptargs="+acc" butterfly_ra2_seri_tb 13 | 14 | add wave * 15 | view structure 16 | view signals 17 | run -all 18 | -------------------------------------------------------------------------------- /FPGA_WORK/proj/simulation/modelsim/fft_run_msim_rtl_verilog.do.bak3: -------------------------------------------------------------------------------- 1 | transcript on 2 | if {[file exists rtl_work]} { 3 | vdel -lib rtl_work -all 4 | } 5 | vlib rtl_work 6 | vmap work rtl_work 7 | 8 | vlog -vlog01compat -work work +incdir+E:/FPGA/FFT_S1/rtl {E:/FPGA/FFT_S1/rtl/butterfly_ra2.v} 9 | vlog -vlog01compat -work work +incdir+E:/FPGA/FFT_S1/rtl {E:/FPGA/FFT_S1/rtl/butterfly_ra2_seri.v} 10 | 11 | vlog -vlog01compat -work work +incdir+E:/FPGA/FFT_S1/proj/../testbench {E:/FPGA/FFT_S1/proj/../testbench/butterfly_ra2_seri_tb.v} 12 | 13 | vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cycloneive_ver -L rtl_work -L work -voptargs="+acc" butterfly_ra2_seri_tb 14 | 15 | add wave * 16 | view structure 17 | view signals 18 | run -all 19 | -------------------------------------------------------------------------------- /FPGA_WORK/proj/simulation/modelsim/fft_run_msim_rtl_verilog.do.bak4: -------------------------------------------------------------------------------- 1 | transcript on 2 | if {[file exists rtl_work]} { 3 | vdel -lib rtl_work -all 4 | } 5 | vlib rtl_work 6 | vmap work rtl_work 7 | 8 | vlog -vlog01compat -work work +incdir+E:/FPGA/FFT_S1/rtl {E:/FPGA/FFT_S1/rtl/butterfly_ra2.v} 9 | vlog -vlog01compat -work work +incdir+E:/FPGA/FFT_S1/rtl {E:/FPGA/FFT_S1/rtl/butterfly_ra2_seri.v} 10 | 11 | vlog -vlog01compat -work work +incdir+E:/FPGA/FFT_S1/proj/../testbench {E:/FPGA/FFT_S1/proj/../testbench/butterfly_ra2_seri_tb.v} 12 | 13 | vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cycloneive_ver -L rtl_work -L work -voptargs="+acc" butterfly_ra2_seri_tb 14 | 15 | add wave * 16 | view structure 17 | view signals 18 | run -all 19 | -------------------------------------------------------------------------------- /FPGA_WORK/proj/simulation/modelsim/fft_run_msim_rtl_verilog.do.bak5: -------------------------------------------------------------------------------- 1 | transcript on 2 | if {[file exists rtl_work]} { 3 | vdel -lib rtl_work -all 4 | } 5 | vlib rtl_work 6 | vmap work rtl_work 7 | 8 | vlog -vlog01compat -work work +incdir+E:/FPGA/FFT_S1/rtl {E:/FPGA/FFT_S1/rtl/butterfly_ra2.v} 9 | vlog -vlog01compat -work work +incdir+E:/FPGA/FFT_S1/rtl {E:/FPGA/FFT_S1/rtl/butterfly_ra2_seri.v} 10 | 11 | vlog -vlog01compat -work work +incdir+E:/FPGA/FFT_S1/proj/../testbench {E:/FPGA/FFT_S1/proj/../testbench/butterfly_ra2_seri_tb.v} 12 | 13 | vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cycloneive_ver -L rtl_work -L work -voptargs="+acc" butterfly_ra2_seri_tb 14 | 15 | add wave * 16 | view structure 17 | view signals 18 | run -all 19 | -------------------------------------------------------------------------------- /FPGA_WORK/proj/simulation/modelsim/fft_run_msim_rtl_verilog.do.bak6: -------------------------------------------------------------------------------- 1 | transcript on 2 | if {[file exists rtl_work]} { 3 | vdel -lib rtl_work -all 4 | } 5 | vlib rtl_work 6 | vmap work rtl_work 7 | 8 | vlog -vlog01compat -work work +incdir+E:/FPGA/FFT_S1/rtl {E:/FPGA/FFT_S1/rtl/butterfly_ra2.v} 9 | vlog -vlog01compat -work work +incdir+E:/FPGA/FFT_S1/rtl {E:/FPGA/FFT_S1/rtl/butterfly_ra2_seri.v} 10 | 11 | vlog -vlog01compat -work work +incdir+E:/FPGA/FFT_S1/proj/../testbench {E:/FPGA/FFT_S1/proj/../testbench/address_gererate_tb.v} 12 | 13 | vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cycloneive_ver -L rtl_work -L work -voptargs="+acc" address_gererate_tb 14 | 15 | add wave * 16 | view structure 17 | view signals 18 | run -all 19 | -------------------------------------------------------------------------------- /FPGA_WORK/proj/simulation/modelsim/fft_run_msim_rtl_verilog.do.bak7: -------------------------------------------------------------------------------- 1 | transcript on 2 | if {[file exists rtl_work]} { 3 | vdel -lib rtl_work -all 4 | } 5 | vlib rtl_work 6 | vmap work rtl_work 7 | 8 | vlog -vlog01compat -work work +incdir+E:/FPGA/FFT_S1/rtl {E:/FPGA/FFT_S1/rtl/butterfly_ra2.v} 9 | vlog -vlog01compat -work work +incdir+E:/FPGA/FFT_S1/rtl {E:/FPGA/FFT_S1/rtl/butterfly_ra2_seri.v} 10 | 11 | vlog -vlog01compat -work work +incdir+E:/FPGA/FFT_S1/proj/../testbench {E:/FPGA/FFT_S1/proj/../testbench/address_gererate_tb.v} 12 | 13 | vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cycloneive_ver -L rtl_work -L work -voptargs="+acc" address_gererate_tb 14 | 15 | add wave * 16 | view structure 17 | view signals 18 | run -all 19 | -------------------------------------------------------------------------------- /FPGA_WORK/proj/simulation/modelsim/fft_run_msim_rtl_verilog.do.bak8: -------------------------------------------------------------------------------- 1 | transcript on 2 | if {[file exists rtl_work]} { 3 | vdel -lib rtl_work -all 4 | } 5 | vlib rtl_work 6 | vmap work rtl_work 7 | 8 | vlog -vlog01compat -work work +incdir+E:/FPGA/FFT_S1/rtl {E:/FPGA/FFT_S1/rtl/butterfly_ra2.v} 9 | vlog -vlog01compat -work work +incdir+E:/FPGA/FFT_S1/rtl {E:/FPGA/FFT_S1/rtl/butterfly_ra2_seri.v} 10 | 11 | vlog -vlog01compat -work work +incdir+E:/FPGA/FFT_S1/proj/../testbench {E:/FPGA/FFT_S1/proj/../testbench/address_gererate_tb.v} 12 | 13 | vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cycloneive_ver -L rtl_work -L work -voptargs="+acc" address_gererate_tb 14 | 15 | add wave * 16 | view structure 17 | view signals 18 | run -all 19 | -------------------------------------------------------------------------------- /FPGA_WORK/proj/simulation/modelsim/fft_run_msim_rtl_verilog.do.bak9: -------------------------------------------------------------------------------- 1 | transcript on 2 | if {[file exists rtl_work]} { 3 | vdel -lib rtl_work -all 4 | } 5 | vlib rtl_work 6 | vmap work rtl_work 7 | 8 | vlog -vlog01compat -work work +incdir+E:/FPGA/FFT_S1/rtl {E:/FPGA/FFT_S1/rtl/butterfly_ra2.v} 9 | 10 | vlog -vlog01compat -work work +incdir+E:/FPGA/FFT_S1/proj/../testbench {E:/FPGA/FFT_S1/proj/../testbench/address_gererate_tb.v} 11 | 12 | vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cycloneive_ver -L rtl_work -L work -voptargs="+acc" address_gererate_tb 13 | 14 | add wave * 15 | view structure 16 | view signals 17 | run -all 18 | -------------------------------------------------------------------------------- /FPGA_WORK/proj/simulation/modelsim/modelsim.ini: -------------------------------------------------------------------------------- 1 | ; Copyright 1991-2009 Mentor Graphics Corporation 2 | ; 3 | ; All Rights Reserved. 4 | ; 5 | ; THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF 6 | ; MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS. 7 | ; 8 | 9 | [Library] 10 | others = $MODEL_TECH/../modelsim.ini 11 | 12 | ; Altera Primitive libraries 13 | ; 14 | ; VHDL Section 15 | ; 16 | ; 17 | ; Verilog Section 18 | ; 19 | 20 | work = rtl_work 21 | [vcom] 22 | ; VHDL93 variable selects language version as the default. 23 | ; Default is VHDL-2002. 24 | ; Value of 0 or 1987 for VHDL-1987. 25 | ; Value of 1 or 1993 for VHDL-1993. 26 | ; Default or value of 2 or 2002 for VHDL-2002. 27 | ; Default or value of 3 or 2008 for VHDL-2008. 28 | VHDL93 = 2002 29 | 30 | ; Show source line containing error. Default is off. 31 | ; Show_source = 1 32 | 33 | ; Turn off unbound-component warnings. Default is on. 34 | ; Show_Warning1 = 0 35 | 36 | ; Turn off process-without-a-wait-statement warnings. Default is on. 37 | ; Show_Warning2 = 0 38 | 39 | ; Turn off null-range warnings. Default is on. 40 | ; Show_Warning3 = 0 41 | 42 | ; Turn off no-space-in-time-literal warnings. Default is on. 43 | ; Show_Warning4 = 0 44 | 45 | ; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on. 46 | ; Show_Warning5 = 0 47 | 48 | ; Turn off optimization for IEEE std_logic_1164 package. Default is on. 49 | ; Optimize_1164 = 0 50 | 51 | ; Turn on resolving of ambiguous function overloading in favor of the 52 | ; "explicit" function declaration (not the one automatically created by 53 | ; the compiler for each type declaration). Default is off. 54 | ; The .ini file has Explicit enabled so that std_logic_signed/unsigned 55 | ; will match the behavior of synthesis tools. 56 | Explicit = 1 57 | 58 | ; Turn off acceleration of the VITAL packages. Default is to accelerate. 59 | ; NoVital = 1 60 | 61 | ; Turn off VITAL compliance checking. Default is checking on. 62 | ; NoVitalCheck = 1 63 | 64 | ; Ignore VITAL compliance checking errors. Default is to not ignore. 65 | ; IgnoreVitalErrors = 1 66 | 67 | ; Turn off VITAL compliance checking warnings. Default is to show warnings. 68 | ; Show_VitalChecksWarnings = 0 69 | 70 | ; Keep silent about case statement static warnings. 71 | ; Default is to give a warning. 72 | ; NoCaseStaticError = 1 73 | 74 | ; Keep silent about warnings caused by aggregates that are not locally static. 75 | ; Default is to give a warning. 76 | ; NoOthersStaticError = 1 77 | 78 | ; Turn off inclusion of debugging info within design units. 79 | ; Default is to include debugging info. 80 | ; NoDebug = 1 81 | 82 | ; Turn off "Loading..." messages. Default is messages on. 83 | ; Quiet = 1 84 | 85 | ; Turn on some limited synthesis rule compliance checking. Checks only: 86 | ; -- signals used (read) by a process must be in the sensitivity list 87 | ; CheckSynthesis = 1 88 | 89 | ; Activate optimizations on expressions that do not involve signals, 90 | ; waits, or function/procedure/task invocations. Default is off. 91 | ; ScalarOpts = 1 92 | 93 | ; Require the user to specify a configuration for all bindings, 94 | ; and do not generate a compile time default binding for the 95 | ; component. This will result in an elaboration error of 96 | ; 'component not bound' if the user fails to do so. Avoids the rare 97 | ; issue of a false dependency upon the unused default binding. 98 | ; RequireConfigForAllDefaultBinding = 1 99 | 100 | ; Inhibit range checking on subscripts of arrays. Range checking on 101 | ; scalars defined with subtypes is inhibited by default. 102 | ; NoIndexCheck = 1 103 | 104 | ; Inhibit range checks on all (implicit and explicit) assignments to 105 | ; scalar objects defined with subtypes. 106 | ; NoRangeCheck = 1 107 | 108 | [vlog] 109 | 110 | ; Turn off inclusion of debugging info within design units. 111 | ; Default is to include debugging info. 112 | ; NoDebug = 1 113 | 114 | ; Turn off "loading..." messages. Default is messages on. 115 | ; Quiet = 1 116 | 117 | ; Turn on Verilog hazard checking (order-dependent accessing of global vars). 118 | ; Default is off. 119 | ; Hazard = 1 120 | 121 | ; Turn on converting regular Verilog identifiers to uppercase. Allows case 122 | ; insensitivity for module names. Default is no conversion. 123 | ; UpCase = 1 124 | 125 | ; Turn on incremental compilation of modules. Default is off. 126 | ; Incremental = 1 127 | 128 | ; Turns on lint-style checking. 129 | ; Show_Lint = 1 130 | 131 | [vsim] 132 | ; Simulator resolution 133 | ; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100. 134 | Resolution = ps 135 | 136 | ; User time unit for run commands 137 | ; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the 138 | ; unit specified for Resolution. For example, if Resolution is 100ps, 139 | ; then UserTimeUnit defaults to ps. 140 | ; Should generally be set to default. 141 | UserTimeUnit = default 142 | 143 | ; Default run length 144 | RunLength = 100 145 | 146 | ; Maximum iterations that can be run without advancing simulation time 147 | IterationLimit = 5000 148 | 149 | ; Directive to license manager: 150 | ; vhdl Immediately reserve a VHDL license 151 | ; vlog Immediately reserve a Verilog license 152 | ; plus Immediately reserve a VHDL and Verilog license 153 | ; nomgc Do not look for Mentor Graphics Licenses 154 | ; nomti Do not look for Model Technology Licenses 155 | ; noqueue Do not wait in the license queue when a license isn't available 156 | ; viewsim Try for viewer license but accept simulator license(s) instead 157 | ; of queuing for viewer license 158 | ; License = plus 159 | 160 | ; Stop the simulator after a VHDL/Verilog assertion message 161 | ; 0 = Note 1 = Warning 2 = Error 3 = Failure 4 = Fatal 162 | BreakOnAssertion = 3 163 | 164 | ; Assertion Message Format 165 | ; %S - Severity Level 166 | ; %R - Report Message 167 | ; %T - Time of assertion 168 | ; %D - Delta 169 | ; %I - Instance or Region pathname (if available) 170 | ; %% - print '%' character 171 | ; AssertionFormat = "** %S: %R\n Time: %T Iteration: %D%I\n" 172 | 173 | ; Assertion File - alternate file for storing VHDL/Verilog assertion messages 174 | ; AssertFile = assert.log 175 | 176 | ; Default radix for all windows and commands... 177 | ; Set to symbolic, ascii, binary, octal, decimal, hex, unsigned 178 | DefaultRadix = symbolic 179 | 180 | ; VSIM Startup command 181 | ; Startup = do startup.do 182 | 183 | ; File for saving command transcript 184 | TranscriptFile = transcript 185 | 186 | ; File for saving command history 187 | ; CommandHistory = cmdhist.log 188 | 189 | ; Specify whether paths in simulator commands should be described 190 | ; in VHDL or Verilog format. 191 | ; For VHDL, PathSeparator = / 192 | ; For Verilog, PathSeparator = . 193 | ; Must not be the same character as DatasetSeparator. 194 | PathSeparator = / 195 | 196 | ; Specify the dataset separator for fully rooted contexts. 197 | ; The default is ':'. For example, sim:/top 198 | ; Must not be the same character as PathSeparator. 199 | DatasetSeparator = : 200 | 201 | ; Disable VHDL assertion messages 202 | ; IgnoreNote = 1 203 | ; IgnoreWarning = 1 204 | ; IgnoreError = 1 205 | ; IgnoreFailure = 1 206 | 207 | ; Default force kind. May be freeze, drive, deposit, or default 208 | ; or in other terms, fixed, wired, or charged. 209 | ; A value of "default" will use the signal kind to determine the 210 | ; force kind, drive for resolved signals, freeze for unresolved signals 211 | ; DefaultForceKind = freeze 212 | 213 | ; If zero, open files when elaborated; otherwise, open files on 214 | ; first read or write. Default is 0. 215 | ; DelayFileOpen = 1 216 | 217 | ; Control VHDL files opened for write. 218 | ; 0 = Buffered, 1 = Unbuffered 219 | UnbufferedOutput = 0 220 | 221 | ; Control the number of VHDL files open concurrently. 222 | ; This number should always be less than the current ulimit 223 | ; setting for max file descriptors. 224 | ; 0 = unlimited 225 | ConcurrentFileLimit = 40 226 | 227 | ; Control the number of hierarchical regions displayed as 228 | ; part of a signal name shown in the Wave window. 229 | ; A value of zero tells VSIM to display the full name. 230 | ; The default is 0. 231 | ; WaveSignalNameWidth = 0 232 | 233 | ; Turn off warnings from the std_logic_arith, std_logic_unsigned 234 | ; and std_logic_signed packages. 235 | ; StdArithNoWarnings = 1 236 | 237 | ; Turn off warnings from the IEEE numeric_std and numeric_bit packages. 238 | ; NumericStdNoWarnings = 1 239 | 240 | ; Control the format of the (VHDL) FOR generate statement label 241 | ; for each iteration. Do not quote it. 242 | ; The format string here must contain the conversion codes %s and %d, 243 | ; in that order, and no other conversion codes. The %s represents 244 | ; the generate_label; the %d represents the generate parameter value 245 | ; at a particular generate iteration (this is the position number if 246 | ; the generate parameter is of an enumeration type). Embedded whitespace 247 | ; is allowed (but discouraged); leading and trailing whitespace is ignored. 248 | ; Application of the format must result in a unique scope name over all 249 | ; such names in the design so that name lookup can function properly. 250 | ; GenerateFormat = %s__%d 251 | 252 | ; Specify whether checkpoint files should be compressed. 253 | ; The default is 1 (compressed). 254 | ; CheckpointCompressMode = 0 255 | 256 | ; List of dynamically loaded objects for Verilog PLI applications 257 | ; Veriuser = veriuser.sl 258 | 259 | ; Specify default options for the restart command. Options can be one 260 | ; or more of: -force -nobreakpoint -nolist -nolog -nowave 261 | ; DefaultRestartOptions = -force 262 | 263 | ; HP-UX 10.20 ONLY - Enable memory locking to speed up large designs 264 | ; (> 500 megabyte memory footprint). Default is disabled. 265 | ; Specify number of megabytes to lock. 266 | ; LockedMemory = 1000 267 | 268 | ; Turn on (1) or off (0) WLF file compression. 269 | ; The default is 1 (compress WLF file). 270 | ; WLFCompress = 0 271 | 272 | ; Specify whether to save all design hierarchy (1) in the WLF file 273 | ; or only regions containing logged signals (0). 274 | ; The default is 0 (save only regions with logged signals). 275 | ; WLFSaveAllRegions = 1 276 | 277 | ; WLF file time limit. Limit WLF file by time, as closely as possible, 278 | ; to the specified amount of simulation time. When the limit is exceeded 279 | ; the earliest times get truncated from the file. 280 | ; If both time and size limits are specified the most restrictive is used. 281 | ; UserTimeUnits are used if time units are not specified. 282 | ; The default is 0 (no limit). Example: WLFTimeLimit = {100 ms} 283 | ; WLFTimeLimit = 0 284 | 285 | ; WLF file size limit. Limit WLF file size, as closely as possible, 286 | ; to the specified number of megabytes. If both time and size limits 287 | ; are specified then the most restrictive is used. 288 | ; The default is 0 (no limit). 289 | ; WLFSizeLimit = 1000 290 | 291 | ; Specify whether or not a WLF file should be deleted when the 292 | ; simulation ends. A value of 1 will cause the WLF file to be deleted. 293 | ; The default is 0 (do not delete WLF file when simulation ends). 294 | ; WLFDeleteOnQuit = 1 295 | 296 | ; Automatic SDF compilation 297 | ; Disables automatic compilation of SDF files in flows that support it. 298 | ; Default is on, uncomment to turn off. 299 | ; NoAutoSDFCompile = 1 300 | 301 | [lmc] 302 | 303 | [msg_system] 304 | ; Change a message severity or suppress a message. 305 | ; The format is: = [,...] 306 | ; Examples: 307 | ; note = 3009 308 | ; warning = 3033 309 | ; error = 3010,3016 310 | ; fatal = 3016,3033 311 | ; suppress = 3009,3016,3043 312 | ; The command verror can be used to get the complete 313 | ; description of a message. 314 | 315 | ; Control transcripting of elaboration/runtime messages. 316 | ; The default is to have messages appear in the transcript and 317 | ; recorded in the wlf file (messages that are recorded in the 318 | ; wlf file can be viewed in the MsgViewer). The other settings 319 | ; are to send messages only to the transcript or only to the 320 | ; wlf file. The valid values are 321 | ; both {default} 322 | ; tran {transcript only} 323 | ; wlf {wlf file only} 324 | ; msgmode = both 325 | -------------------------------------------------------------------------------- /FPGA_WORK/proj/simulation/modelsim/rtl_work/_info: -------------------------------------------------------------------------------- 1 | m255 2 | K3 3 | 13 4 | cModel Technology 5 | Z0 dG:\FPWG_WORK\FPGA_W\FFT_S1\FFT_20180922\proj\simulation\modelsim 6 | vbutterfly_ra2 7 | IC@T=CGU=IL1Vh1l;@H40:0 8 | VIgK^Jbz07l1S>aMogLH^C0 9 | Z1 dG:\FPWG_WORK\FPGA_W\FFT_S1\FFT_20180922\proj\simulation\modelsim 10 | w1537616616 11 | 8G:/FPWG_WORK/FPGA_W/FFT_S1/FFT_20180922/rtl/butterfly_ra2.v 12 | FG:/FPWG_WORK/FPGA_W/FFT_S1/FFT_20180922/rtl/butterfly_ra2.v 13 | L0 2 14 | Z2 OV;L;10.1d;51 15 | r1 16 | 31 17 | Z3 o-vlog01compat -work work -O0 18 | Z4 !s92 -vlog01compat -work work +incdir+G:/FPWG_WORK/FPGA_W/FFT_S1/FFT_20180922/rtl -O0 19 | !i10b 1 20 | !s100 [BcW=gb1:CnjFE_5Taze@0 21 | !s85 0 22 | !s108 1537617487.692000 23 | !s107 G:/FPWG_WORK/FPGA_W/FFT_S1/FFT_20180922/rtl/butterfly_ra2.v| 24 | !s90 -reportprogress|300|-vlog01compat|-work|work|+incdir+G:/FPWG_WORK/FPGA_W/FFT_S1/FFT_20180922/rtl|-O0|G:/FPWG_WORK/FPGA_W/FFT_S1/FFT_20180922/rtl/butterfly_ra2.v| 25 | !s101 -O0 26 | vbutterfly_ra2_seri 27 | ICW=7QA__k=PDafEGL911D3 28 | Vg;_fV>_PF8QF;ahiJh]4N3 29 | R1 30 | w1537500617 31 | 8G:/FPWG_WORK/FPGA_W/FFT_S1/FFT_20180922/rtl/butterfly_ra2_seri.v 32 | FG:/FPWG_WORK/FPGA_W/FFT_S1/FFT_20180922/rtl/butterfly_ra2_seri.v 33 | L0 2 34 | R2 35 | r1 36 | 31 37 | R3 38 | R4 39 | !i10b 1 40 | !s100 SgB]VmIKjkj>_QbLA3 68 | VM>QD0DEjXP9k7SCizfzFE3 69 | R1 70 | w1537597495 71 | 8G:/FPWG_WORK/FPGA_W/FFT_S1/FFT_20180922/testbench/fft_tb.v 72 | FG:/FPWG_WORK/FPGA_W/FFT_S1/FFT_20180922/testbench/fft_tb.v 73 | L0 2 74 | R2 75 | r1 76 | 31 77 | R3 78 | !i10b 1 79 | !s100 83U@Oe]Bz0XQgj`_87=VJ0 80 | !s85 0 81 | !s108 1537617488.495000 82 | !s107 G:/FPWG_WORK/FPGA_W/FFT_S1/FFT_20180922/testbench/fft_tb.v| 83 | !s90 -reportprogress|300|-vlog01compat|-work|work|+incdir+G:/FPWG_WORK/FPGA_W/FFT_S1/FFT_20180922/proj/../testbench|-O0|G:/FPWG_WORK/FPGA_W/FFT_S1/FFT_20180922/testbench/fft_tb.v| 84 | !s101 -O0 85 | !s92 -vlog01compat -work work +incdir+G:/FPWG_WORK/FPGA_W/FFT_S1/FFT_20180922/proj/../testbench -O0 86 | vram128 87 | IBnNeYVg=nCT]RfH6BVlQU0 88 | V2ohd8XPL3g4^>h01 110 | V[hSC7H:FFNGnadlA9PPZ50 111 | R1 112 | w1537608555 113 | 8G:/FPWG_WORK/FPGA_W/FFT_S1/FFT_20180922/ip/wnp.v 114 | FG:/FPWG_WORK/FPGA_W/FFT_S1/FFT_20180922/ip/wnp.v 115 | L0 39 116 | R2 117 | r1 118 | !s85 0 119 | 31 120 | !s108 1537617489.170000 121 | !s107 G:/FPWG_WORK/FPGA_W/FFT_S1/FFT_20180922/ip/wnp.v| 122 | !s90 -reportprogress|300|-vlog01compat|-work|work|+incdir+G:/FPWG_WORK/FPGA_W/FFT_S1/FFT_20180922/ip|-O0|G:/FPWG_WORK/FPGA_W/FFT_S1/FFT_20180922/ip/wnp.v| 123 | !s101 -O0 124 | R3 125 | R5 126 | -------------------------------------------------------------------------------- /FPGA_WORK/proj/simulation/modelsim/rtl_work/_vmake: -------------------------------------------------------------------------------- 1 | m255 2 | K3 3 | cModel Technology 4 | -------------------------------------------------------------------------------- /FPGA_WORK/proj/simulation/modelsim/rtl_work/butterfly_ra2/_primary.dat: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/DeamonYang/FPGA_FFT/fa3b99e23651234b410932c9e37d66598745853f/FPGA_WORK/proj/simulation/modelsim/rtl_work/butterfly_ra2/_primary.dat -------------------------------------------------------------------------------- /FPGA_WORK/proj/simulation/modelsim/rtl_work/butterfly_ra2/_primary.dbs: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/DeamonYang/FPGA_FFT/fa3b99e23651234b410932c9e37d66598745853f/FPGA_WORK/proj/simulation/modelsim/rtl_work/butterfly_ra2/_primary.dbs -------------------------------------------------------------------------------- /FPGA_WORK/proj/simulation/modelsim/rtl_work/butterfly_ra2/_primary.vhd: -------------------------------------------------------------------------------- 1 | library verilog; 2 | use verilog.vl_types.all; 3 | entity butterfly_ra2 is 4 | port( 5 | rst_n : in vl_logic; 6 | clk : in vl_logic; 7 | bf_go : in vl_logic; 8 | bf_done : out vl_logic; 9 | wx : in vl_logic_vector(7 downto 0); 10 | wy : in vl_logic_vector(7 downto 0); 11 | x1 : in vl_logic_vector(7 downto 0); 12 | y1 : in vl_logic_vector(7 downto 0); 13 | x2 : in vl_logic_vector(7 downto 0); 14 | y2 : in vl_logic_vector(7 downto 0); 15 | bfx1 : out vl_logic_vector(8 downto 0); 16 | bfy1 : out vl_logic_vector(8 downto 0); 17 | bfx2 : out vl_logic_vector(8 downto 0); 18 | bfy2 : out vl_logic_vector(8 downto 0) 19 | ); 20 | end butterfly_ra2; 21 | -------------------------------------------------------------------------------- /FPGA_WORK/proj/simulation/modelsim/rtl_work/butterfly_ra2/verilog.prw: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/DeamonYang/FPGA_FFT/fa3b99e23651234b410932c9e37d66598745853f/FPGA_WORK/proj/simulation/modelsim/rtl_work/butterfly_ra2/verilog.prw -------------------------------------------------------------------------------- /FPGA_WORK/proj/simulation/modelsim/rtl_work/butterfly_ra2/verilog.psm: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/DeamonYang/FPGA_FFT/fa3b99e23651234b410932c9e37d66598745853f/FPGA_WORK/proj/simulation/modelsim/rtl_work/butterfly_ra2/verilog.psm -------------------------------------------------------------------------------- /FPGA_WORK/proj/simulation/modelsim/rtl_work/butterfly_ra2_seri/_primary.dat: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/DeamonYang/FPGA_FFT/fa3b99e23651234b410932c9e37d66598745853f/FPGA_WORK/proj/simulation/modelsim/rtl_work/butterfly_ra2_seri/_primary.dat -------------------------------------------------------------------------------- /FPGA_WORK/proj/simulation/modelsim/rtl_work/butterfly_ra2_seri/_primary.dbs: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/DeamonYang/FPGA_FFT/fa3b99e23651234b410932c9e37d66598745853f/FPGA_WORK/proj/simulation/modelsim/rtl_work/butterfly_ra2_seri/_primary.dbs -------------------------------------------------------------------------------- /FPGA_WORK/proj/simulation/modelsim/rtl_work/butterfly_ra2_seri/_primary.vhd: -------------------------------------------------------------------------------- 1 | library verilog; 2 | use verilog.vl_types.all; 3 | entity butterfly_ra2_seri is 4 | port( 5 | rst_n : in vl_logic; 6 | clk : in vl_logic; 7 | bf_go : in vl_logic; 8 | bf_done : out vl_logic; 9 | datax : in vl_logic_vector(7 downto 0); 10 | datay : in vl_logic_vector(7 downto 0); 11 | wx : in vl_logic_vector(7 downto 0); 12 | wy : in vl_logic_vector(7 downto 0); 13 | wren : out vl_logic; 14 | bfx : out vl_logic_vector(7 downto 0); 15 | bfy : out vl_logic_vector(7 downto 0) 16 | ); 17 | end butterfly_ra2_seri; 18 | -------------------------------------------------------------------------------- /FPGA_WORK/proj/simulation/modelsim/rtl_work/butterfly_ra2_seri/verilog.prw: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/DeamonYang/FPGA_FFT/fa3b99e23651234b410932c9e37d66598745853f/FPGA_WORK/proj/simulation/modelsim/rtl_work/butterfly_ra2_seri/verilog.prw -------------------------------------------------------------------------------- /FPGA_WORK/proj/simulation/modelsim/rtl_work/butterfly_ra2_seri/verilog.psm: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/DeamonYang/FPGA_FFT/fa3b99e23651234b410932c9e37d66598745853f/FPGA_WORK/proj/simulation/modelsim/rtl_work/butterfly_ra2_seri/verilog.psm -------------------------------------------------------------------------------- /FPGA_WORK/proj/simulation/modelsim/rtl_work/fft/_primary.dat: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/DeamonYang/FPGA_FFT/fa3b99e23651234b410932c9e37d66598745853f/FPGA_WORK/proj/simulation/modelsim/rtl_work/fft/_primary.dat -------------------------------------------------------------------------------- /FPGA_WORK/proj/simulation/modelsim/rtl_work/fft/_primary.dbs: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/DeamonYang/FPGA_FFT/fa3b99e23651234b410932c9e37d66598745853f/FPGA_WORK/proj/simulation/modelsim/rtl_work/fft/_primary.dbs -------------------------------------------------------------------------------- /FPGA_WORK/proj/simulation/modelsim/rtl_work/fft/_primary.vhd: -------------------------------------------------------------------------------- 1 | library verilog; 2 | use verilog.vl_types.all; 3 | entity fft is 4 | port( 5 | rst_n : in vl_logic; 6 | clk : in vl_logic; 7 | data1 : in vl_logic_vector(7 downto 0); 8 | fft_go : in vl_logic; 9 | fft_done : out vl_logic; 10 | fft_res : out vl_logic_vector(15 downto 0) 11 | ); 12 | end fft; 13 | -------------------------------------------------------------------------------- /FPGA_WORK/proj/simulation/modelsim/rtl_work/fft/verilog.prw: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/DeamonYang/FPGA_FFT/fa3b99e23651234b410932c9e37d66598745853f/FPGA_WORK/proj/simulation/modelsim/rtl_work/fft/verilog.prw -------------------------------------------------------------------------------- /FPGA_WORK/proj/simulation/modelsim/rtl_work/fft/verilog.psm: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/DeamonYang/FPGA_FFT/fa3b99e23651234b410932c9e37d66598745853f/FPGA_WORK/proj/simulation/modelsim/rtl_work/fft/verilog.psm -------------------------------------------------------------------------------- /FPGA_WORK/proj/simulation/modelsim/rtl_work/fft_tb/_primary.dat: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/DeamonYang/FPGA_FFT/fa3b99e23651234b410932c9e37d66598745853f/FPGA_WORK/proj/simulation/modelsim/rtl_work/fft_tb/_primary.dat -------------------------------------------------------------------------------- /FPGA_WORK/proj/simulation/modelsim/rtl_work/fft_tb/_primary.dbs: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/DeamonYang/FPGA_FFT/fa3b99e23651234b410932c9e37d66598745853f/FPGA_WORK/proj/simulation/modelsim/rtl_work/fft_tb/_primary.dbs -------------------------------------------------------------------------------- /FPGA_WORK/proj/simulation/modelsim/rtl_work/fft_tb/_primary.vhd: -------------------------------------------------------------------------------- 1 | library verilog; 2 | use verilog.vl_types.all; 3 | entity fft_tb is 4 | end fft_tb; 5 | -------------------------------------------------------------------------------- /FPGA_WORK/proj/simulation/modelsim/rtl_work/fft_tb/verilog.prw: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/DeamonYang/FPGA_FFT/fa3b99e23651234b410932c9e37d66598745853f/FPGA_WORK/proj/simulation/modelsim/rtl_work/fft_tb/verilog.prw -------------------------------------------------------------------------------- /FPGA_WORK/proj/simulation/modelsim/rtl_work/fft_tb/verilog.psm: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/DeamonYang/FPGA_FFT/fa3b99e23651234b410932c9e37d66598745853f/FPGA_WORK/proj/simulation/modelsim/rtl_work/fft_tb/verilog.psm -------------------------------------------------------------------------------- /FPGA_WORK/proj/simulation/modelsim/rtl_work/ram128/_primary.dat: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/DeamonYang/FPGA_FFT/fa3b99e23651234b410932c9e37d66598745853f/FPGA_WORK/proj/simulation/modelsim/rtl_work/ram128/_primary.dat -------------------------------------------------------------------------------- /FPGA_WORK/proj/simulation/modelsim/rtl_work/ram128/_primary.dbs: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/DeamonYang/FPGA_FFT/fa3b99e23651234b410932c9e37d66598745853f/FPGA_WORK/proj/simulation/modelsim/rtl_work/ram128/_primary.dbs -------------------------------------------------------------------------------- /FPGA_WORK/proj/simulation/modelsim/rtl_work/ram128/_primary.vhd: -------------------------------------------------------------------------------- 1 | library verilog; 2 | use verilog.vl_types.all; 3 | entity ram128 is 4 | port( 5 | address : in vl_logic_vector(6 downto 0); 6 | clock : in vl_logic; 7 | data : in vl_logic_vector(15 downto 0); 8 | wren : in vl_logic; 9 | q : out vl_logic_vector(15 downto 0) 10 | ); 11 | end ram128; 12 | -------------------------------------------------------------------------------- /FPGA_WORK/proj/simulation/modelsim/rtl_work/ram128/verilog.prw: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/DeamonYang/FPGA_FFT/fa3b99e23651234b410932c9e37d66598745853f/FPGA_WORK/proj/simulation/modelsim/rtl_work/ram128/verilog.prw -------------------------------------------------------------------------------- /FPGA_WORK/proj/simulation/modelsim/rtl_work/ram128/verilog.psm: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/DeamonYang/FPGA_FFT/fa3b99e23651234b410932c9e37d66598745853f/FPGA_WORK/proj/simulation/modelsim/rtl_work/ram128/verilog.psm -------------------------------------------------------------------------------- /FPGA_WORK/proj/simulation/modelsim/rtl_work/wnp/_primary.dat: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/DeamonYang/FPGA_FFT/fa3b99e23651234b410932c9e37d66598745853f/FPGA_WORK/proj/simulation/modelsim/rtl_work/wnp/_primary.dat -------------------------------------------------------------------------------- /FPGA_WORK/proj/simulation/modelsim/rtl_work/wnp/_primary.dbs: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/DeamonYang/FPGA_FFT/fa3b99e23651234b410932c9e37d66598745853f/FPGA_WORK/proj/simulation/modelsim/rtl_work/wnp/_primary.dbs -------------------------------------------------------------------------------- /FPGA_WORK/proj/simulation/modelsim/rtl_work/wnp/_primary.vhd: -------------------------------------------------------------------------------- 1 | library verilog; 2 | use verilog.vl_types.all; 3 | entity wnp is 4 | port( 5 | address : in vl_logic_vector(5 downto 0); 6 | clock : in vl_logic; 7 | q : out vl_logic_vector(15 downto 0) 8 | ); 9 | end wnp; 10 | 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?????? 2018 2 | Trace back: wrong # args: should be "mti_popupinternal menu w" 3 | while executing 4 | "mti_popupinternal .librarypopup_popup " 5 | ("after" script) 6 | <2: ::tkerror {wrong # args: should be "mti_popupinternal menu w"} 7 | <1: ::bgerror {wrong # args: should be "mti_popupinternal menu w"} 8 | Fri Sep 21 21:40:13 ?????? 2018 9 | Trace back: wrong # args: should be "mti_popupinternal menu w" 10 | while executing 11 | "mti_popupinternal .librarypopup_popup " 12 | ("after" script) 13 | <2: ::tkerror {wrong # args: should be "mti_popupinternal menu w"} 14 | <1: ::bgerror {wrong # args: should be "mti_popupinternal menu w"} 15 | -------------------------------------------------------------------------------- /FPGA_WORK/proj/simulation/modelsim/vsim.wlf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/DeamonYang/FPGA_FFT/fa3b99e23651234b410932c9e37d66598745853f/FPGA_WORK/proj/simulation/modelsim/vsim.wlf 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-------------------------------------------------------------------------------- /FPGA_WORK/proj/simulation/modelsim/wnp64relimg88.mif: -------------------------------------------------------------------------------- 1 | WIDTH=16; 2 | DEPTH=64; 3 | 4 | ADDRESS_RADIX=UNS; 5 | DATA_RADIX=HEX; 6 | 7 | CONTENT BEGIN 8 | 0 : 7f00; 9 | 1 : 7ef4; 10 | 2 : 7de7; 11 | 3 : 7adb; 12 | 4 : 75cf; 13 | 5 : 70c4; 14 | 6 : 6ab9; 15 | 7 : 62af; 16 | 8 : 5aa6; 17 | 9 : 519e; 18 | 10 : 4796; 19 | 11 : 3c90; 20 | 12 : 318b; 21 | 13 : 2586; 22 | 14 : 1983; 23 | 15 : 0c82; 24 | 16 : 0081; 25 | 17 : f482; 26 | 18 : e783; 27 | 19 : db86; 28 | 20 : cf8b; 29 | 21 : c490; 30 | 22 : b996; 31 | 23 : af9e; 32 | 24 : a6a6; 33 | 25 : 9eaf; 34 | 26 : 96b9; 35 | 27 : 90c4; 36 | 28 : 8bcf; 37 | 29 : 86db; 38 | 30 : 83e7; 39 | 31 : 82f4; 40 | 32 : 8100; 41 | 33 : 820c; 42 | 34 : 8319; 43 | 35 : 8625; 44 | 36 : 8b31; 45 | 37 : 903c; 46 | 38 : 9647; 47 | 39 : 9e51; 48 | 40 : a65a; 49 | 41 : af62; 50 | 42 : b96a; 51 | 43 : c470; 52 | 44 : cf75; 53 | 45 : db7a; 54 | 46 : e77d; 55 | 47 : f47e; 56 | 48 : 007f; 57 | 49 : 0c7e; 58 | 50 : 197d; 59 | 51 : 257a; 60 | 52 : 3175; 61 | 53 : 3c70; 62 | 54 : 476a; 63 | 55 : 5162; 64 | 56 : 5a5a; 65 | 57 : 6251; 66 | 58 : 6a47; 67 | 59 : 703c; 68 | 60 : 7531; 69 | 61 : 7a25; 70 | 62 : 7d19; 71 | 63 : 7e0c; 72 | END; 73 | -------------------------------------------------------------------------------- /FPGA_WORK/proj/simulation/modelsim/wnp64relimg88.ver: -------------------------------------------------------------------------------- 1 | @0 2 | 7f00 3 | @1 4 | 7ef4 5 | @2 6 | 7de7 7 | @3 8 | 7adb 9 | @4 10 | 75cf 11 | @5 12 | 70c4 13 | @6 14 | 6ab9 15 | @7 16 | 62af 17 | @8 18 | 5aa6 19 | @9 20 | 519e 21 | @a 22 | 4796 23 | @b 24 | 3c90 25 | @c 26 | 318b 27 | @d 28 | 2586 29 | @e 30 | 1983 31 | @f 32 | 0c82 33 | @10 34 | 0081 35 | @11 36 | f482 37 | @12 38 | e783 39 | @13 40 | db86 41 | @14 42 | cf8b 43 | @15 44 | c490 45 | @16 46 | b996 47 | @17 48 | af9e 49 | @18 50 | a6a6 51 | @19 52 | 9eaf 53 | @1a 54 | 96b9 55 | @1b 56 | 90c4 57 | @1c 58 | 8bcf 59 | @1d 60 | 86db 61 | @1e 62 | 83e7 63 | @1f 64 | 82f4 65 | @20 66 | 8100 67 | @21 68 | 820c 69 | @22 70 | 8319 71 | @23 72 | 8625 73 | @24 74 | 8b31 75 | @25 76 | 903c 77 | @26 78 | 9647 79 | @27 80 | 9e51 81 | @28 82 | a65a 83 | @29 84 | af62 85 | @2a 86 | b96a 87 | @2b 88 | c470 89 | @2c 90 | cf75 91 | @2d 92 | db7a 93 | @2e 94 | e77d 95 | @2f 96 | f47e 97 | @30 98 | 007f 99 | @31 100 | 0c7e 101 | @32 102 | 197d 103 | @33 104 | 257a 105 | @34 106 | 3175 107 | @35 108 | 3c70 109 | @36 110 | 476a 111 | @37 112 | 5162 113 | @38 114 | 5a5a 115 | @39 116 | 6251 117 | @3a 118 | 6a47 119 | @3b 120 | 703c 121 | @3c 122 | 7531 123 | @3d 124 | 7a25 125 | @3e 126 | 7d19 127 | @3f 128 | 7e0c 129 | -------------------------------------------------------------------------------- /FPGA_WORK/proj/wnp.qip: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/DeamonYang/FPGA_FFT/fa3b99e23651234b410932c9e37d66598745853f/FPGA_WORK/proj/wnp.qip -------------------------------------------------------------------------------- /FPGA_WORK/proj/wnp64relimg88.mif: -------------------------------------------------------------------------------- 1 | WIDTH=16; 2 | DEPTH=64; 3 | 4 | ADDRESS_RADIX=UNS; 5 | DATA_RADIX=HEX; 6 | 7 | CONTENT BEGIN 8 | 0 : 7f00; 9 | 1 : 7ef4; 10 | 2 : 7de7; 11 | 3 : 7adb; 12 | 4 : 75cf; 13 | 5 : 70c4; 14 | 6 : 6ab9; 15 | 7 : 62af; 16 | 8 : 5aa6; 17 | 9 : 519e; 18 | 10 : 4796; 19 | 11 : 3c90; 20 | 12 : 318b; 21 | 13 : 2586; 22 | 14 : 1983; 23 | 15 : 0c82; 24 | 16 : 0081; 25 | 17 : f482; 26 | 18 : e783; 27 | 19 : db86; 28 | 20 : cf8b; 29 | 21 : c490; 30 | 22 : b996; 31 | 23 : af9e; 32 | 24 : a6a6; 33 | 25 : 9eaf; 34 | 26 : 96b9; 35 | 27 : 90c4; 36 | 28 : 8bcf; 37 | 29 : 86db; 38 | 30 : 83e7; 39 | 31 : 82f4; 40 | 32 : 8100; 41 | 33 : 820c; 42 | 34 : 8319; 43 | 35 : 8625; 44 | 36 : 8b31; 45 | 37 : 903c; 46 | 38 : 9647; 47 | 39 : 9e51; 48 | 40 : a65a; 49 | 41 : af62; 50 | 42 : b96a; 51 | 43 : c470; 52 | 44 : cf75; 53 | 45 : db7a; 54 | 46 : e77d; 55 | 47 : f47e; 56 | 48 : 007f; 57 | 49 : 0c7e; 58 | 50 : 197d; 59 | 51 : 257a; 60 | 52 : 3175; 61 | 53 : 3c70; 62 | 54 : 476a; 63 | 55 : 5162; 64 | 56 : 5a5a; 65 | 57 : 6251; 66 | 58 : 6a47; 67 | 59 : 703c; 68 | 60 : 7531; 69 | 61 : 7a25; 70 | 62 : 7d19; 71 | 63 : 7e0c; 72 | END; 73 | -------------------------------------------------------------------------------- /FPGA_WORK/rtl/butterfly_ra2.v: -------------------------------------------------------------------------------- 1 | //基2 蝶形变换 2 | module butterfly_ra2 3 | ( 4 | rst_n, 5 | clk, 6 | bf_go, 7 | bf_done, 8 | wx, 9 | wy, 10 | x1, 11 | y1, 12 | x2, 13 | y2, 14 | bfx1, 15 | bfy1, 16 | bfx2, 17 | bfy2 18 | ); 19 | 20 | input rst_n; 21 | input clk; 22 | input bf_go; 23 | output reg bf_done; 24 | input signed[7:0]wx; 25 | input signed[7:0]wy; 26 | input signed[7:0]x1; 27 | input signed[7:0]y1; 28 | input signed[7:0]x2; 29 | input signed[7:0]y2; 30 | output reg signed[8:0]bfx1; 31 | output reg signed[8:0]bfy1; 32 | output reg signed[8:0]bfx2; 33 | output reg signed[8:0]bfy2; 34 | reg [1:0]cnt; 35 | reg clc_en; 36 | reg signed [15:0]a; 37 | reg signed [15:0]b; 38 | reg signed [15:0]c; 39 | reg signed [15:0]d; 40 | 41 | reg signed[7:0]r_x1; 42 | reg signed[7:0]r_y1; 43 | 44 | 45 | reg signed[15:0]rel; 46 | reg signed[15:0]img; 47 | 48 | 49 | /*计算使能*/ 50 | always@(posedge clk or negedge rst_n) 51 | if(!rst_n) 52 | clc_en <= 1'd0; 53 | else if(bf_go) 54 | clc_en <= 1'd1; 55 | else if(cnt == 2'b11) 56 | clc_en <= 1'd0; 57 | 58 | /*寄存初始值防止计算过程中数据发生变化*/ 59 | always@(posedge clk or negedge rst_n) 60 | if(!rst_n)begin 61 | 62 | r_x1 = 8'd0; 63 | r_y1 = 8'd0; 64 | 65 | end 66 | else if(bf_go)begin 67 | 68 | r_x1 <= x1; 69 | r_y1 <= y1; 70 | end 71 | 72 | 73 | /*分3步完成计算*/ 74 | always@(posedge clk or negedge rst_n) 75 | if(!rst_n) 76 | cnt <= 2'd0; 77 | else if(bf_go) 78 | cnt <= 2'd1; 79 | else if(clc_en) 80 | cnt <= cnt + 1'b1; 81 | 82 | always@(posedge clk or negedge rst_n) 83 | if(!rst_n)begin 84 | bfx1 <= 9'd0; 85 | bfy1 <= 9'd0; 86 | bfx2 <= 9'd0; 87 | bfy2 <= 9'd0; 88 | rel <=15'd0; 89 | img <=15'd0; 90 | end else if(bf_go | clc_en ) 91 | case(cnt) 92 | 1: 93 | begin 94 | a <= x2*wx; 95 | b <= y2*wy; 96 | c <= y2*wx; 97 | d <= x2*wy; 98 | end 99 | 2: 100 | begin 101 | rel <= (a - b); 102 | img <= (c + d); 103 | end 104 | 3: 105 | begin 106 | bfx1 <= {r_x1[7],r_x1} + {rel[15],rel[15:8]}; 107 | bfy1 <= {r_y1[7],r_y1} + {img[15],img[15:8]}; 108 | bfx2 <= {r_x1[7],r_x1} - {rel[15],rel[15:8]}; 109 | bfy2 <= {r_y1[7],r_y1} - {img[15],img[15:8]}; 110 | end 111 | default:; 112 | 113 | endcase 114 | 115 | always @(posedge clk or negedge rst_n) 116 | if(!rst_n) 117 | bf_done <= 1'b0; 118 | else if(cnt == 2'd3) 119 | bf_done <= 1'b1; 120 | else 121 | bf_done <= 1'b0; 122 | 123 | 124 | 125 | endmodule 126 | 127 | 128 | 129 | 130 | 131 | 132 | 133 | -------------------------------------------------------------------------------- /FPGA_WORK/rtl/butterfly_ra2.v.bak: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /FPGA_WORK/rtl/butterfly_ra2_seri.v: -------------------------------------------------------------------------------- 1 | //将并行读写数据的蝶形变换转化为串行读写 2 | module butterfly_ra2_seri 3 | ( 4 | rst_n, 5 | clk, 6 | bf_go, 7 | bf_done, //两组数据 持续一个时钟周期 8 | 9 | datax, 10 | datay, 11 | 12 | wx,//第一个时钟周期读取旋转因子 13 | wy, 14 | 15 | wren,//写数据使能 16 | bfx, 17 | bfy 18 | ); 19 | 20 | 21 | input rst_n; 22 | input clk; 23 | input bf_go; 24 | output reg bf_done; 25 | 26 | input[7:0]datax; 27 | input[7:0]datay; 28 | 29 | input[7:0]wx;//第一个时钟周期读取旋转因子 30 | input[7:0]wy; 31 | 32 | output reg[7:0]bfx; 33 | output reg[7:0]bfy; 34 | output reg wren; 35 | // output reg num;//读取第一个数为低读取第二个为高电平 36 | 37 | reg signed[7:0]r_wx; 38 | reg signed[7:0]r_wy; 39 | reg signed[7:0]x1; 40 | reg signed[7:0]y1; 41 | reg signed[7:0]x2; 42 | reg signed[7:0]y2; 43 | wire signed[8:0]bfx1; 44 | wire signed[8:0]bfy1; 45 | wire signed[8:0]bfx2; 46 | wire signed[8:0]bfy2; 47 | wire bbf_done; 48 | 49 | // reg signed[8:0]r_bfx1; 50 | // reg signed[8:0]r_bfy1; 51 | // reg signed[8:0]r_bfx2; 52 | // reg signed[8:0]r_bfy2; 53 | 54 | reg r_bbf_go; 55 | 56 | 57 | reg[3:0]cnt; 58 | reg cnt_en; 59 | 60 | always@(posedge clk or negedge rst_n) 61 | if(!rst_n) 62 | cnt_en <= 1'd0; 63 | else if(bf_go) 64 | cnt_en <= 1'b1; 65 | else if(cnt >= 4'd7) 66 | cnt_en <= 1'd0; 67 | 68 | 69 | always@(posedge clk or negedge rst_n) 70 | if(!rst_n) 71 | cnt <= 'd0; 72 | else if(cnt_en) 73 | cnt <= cnt + 1'b1; 74 | else 75 | cnt <= 'd0; 76 | 77 | always@(posedge clk or negedge rst_n) 78 | if(!rst_n)begin 79 | r_bbf_go <= 1'b0; 80 | bf_done <= 1'b0; 81 | bfx <= 8'd0; 82 | bfy <= 8'd0; 83 | wren <= 1'b0; 84 | end 85 | else //if(cnt_en) 86 | case(cnt) 87 | 0:begin 88 | x1 <= datax; 89 | y1 <= datay; 90 | r_wx <= wx; 91 | r_wy <= wy; 92 | wren <= 1'b00; 93 | bf_done <= 1'b0; 94 | end 95 | 96 | 1:begin 97 | x2 <= datax; 98 | y2 <= datay; 99 | r_bbf_go <= 1'd1; 100 | end 101 | //开始计算 102 | 2:begin 103 | r_bbf_go <= 1'd0; 104 | end 105 | 106 | 107 | 108 | 6:begin 109 | 110 | bfx <= bfx1[8:1]; 111 | bfy <= bfy1[8:1]; 112 | wren <= 1'b1; 113 | end 114 | 7:begin 115 | bfx <= bfx2[8:1]; 116 | bfy <= bfy2[8:1]; 117 | wren <= 1'b1; 118 | bf_done <= 1'b1; 119 | end 120 | 121 | 8:begin 122 | wren <= 1'b00; 123 | bf_done <= 1'b0; 124 | end 125 | 126 | default:; 127 | 128 | endcase 129 | 130 | 131 | butterfly_ra2 bflab1( 132 | .rst_n(rst_n), 133 | .clk(clk), 134 | .bf_go(r_bbf_go), 135 | .bf_done(bbf_done), 136 | .wx(r_wx), 137 | .wy(r_wy), 138 | .x1(x1), 139 | .y1(y1), 140 | .x2(x2), 141 | .y2(y2), 142 | .bfx1(bfx1), 143 | .bfy1(bfy1), 144 | .bfx2(bfx2), 145 | .bfy2(bfy2) 146 | ); 147 | 148 | 149 | endmodule 150 | 151 | 152 | 153 | 154 | 155 | 156 | 157 | 158 | 159 | 160 | 161 | 162 | 163 | 164 | 165 | 166 | 167 | 168 | 169 | 170 | 171 | 172 | 173 | -------------------------------------------------------------------------------- /FPGA_WORK/rtl/butterfly_ra2_seri.v.bak: -------------------------------------------------------------------------------- 1 | module butterfly_ra2_seri 2 | ( 3 | rst_n, 4 | clk, 5 | bf_go, 6 | bf_done, 7 | wx, 8 | wy, 9 | x1, 10 | y1, 11 | x2, 12 | y2, 13 | bfx1, 14 | bfy1, 15 | bfx2, 16 | bfy2, 17 | ); 18 | 19 | endmodule 20 | 21 | -------------------------------------------------------------------------------- /FPGA_WORK/rtl/fft.v: -------------------------------------------------------------------------------- 1 | //128点FFT 2 | module fft( 3 | rst_n, 4 | clk, 5 | data1, 6 | 7 | fft_go, 8 | fft_done, 9 | fft_res 10 | ); 11 | input rst_n; 12 | input clk; 13 | input signed[7:0]data1; 14 | input fft_go; 15 | output reg fft_done; 16 | output [15:0]fft_res; 17 | 18 | reg[7:0]current_state; 19 | reg[7:0]next_state; 20 | reg rad_data_en;//读取外部数据使能 21 | reg[6:0]rd_cnt; 22 | reg[6:0]ot_cnt; 23 | reg unsigned[6:0]rd_data_add;//RAM 从外部读取数据线 24 | reg r_wren; 25 | reg [3:0]lay_cnt; //级数计数器 2^7 = 128 共7 级 26 | reg [6:0]r_lay_cnt;//级数计数器 2^7 = 128 共7 级 采用移位计数方式 27 | reg [6:0]bf_cnt; //每级FFT 进行 蝶形变换的数目 28 | wire bf_done; //一级蝶形变换计算完毕信号 单时钟周期 29 | reg unsigned [6:0]bstep; 30 | reg[5:0]rom_wn; 31 | reg[3:0]bf_clc_cnt; 32 | reg bf_go; 33 | wire[15:0]ram_out; 34 | wire[15:0]ram_data_in; 35 | wire[15:0]bf_data_out; 36 | wire[15:0]w_wnp; 37 | wire[15:0]fft_data_out; 38 | reg[6:0]ram_add_prv; 39 | // assign rd_data_add = 7'b{rd_cnt[0]},{rd_cnt[1]},{rd_cnt[2]},{rd_cnt[3]},{rd_cnt[4]},{rd_cnt[5]},{rd_cnt[6]}; 40 | 41 | 42 | localparam[7:0] 43 | IDEL = 8'b0000_0001, 44 | RADDAT= 8'b0000_0010, 45 | FBKSEQ= 8'b0000_0100, 46 | // FFTRDD= 8'b0000_1000; 47 | FFTCLC= 8'b0001_0000, 48 | // FFTSVD= 8'b0010_0000; 49 | FFTOUT= 8'b0100_0000; 50 | 51 | // /*读数据使能信号*/ 52 | // always@(posedge clk or negedge rst_n ) 53 | // if(!rst_n) 54 | // rad_data_en <= 1'b0; 55 | // else if(fft_go) 56 | // rad_data_en <= 1'd1; 57 | // else if(rd_cnt == 7'd111_1110) 58 | // rad_data_en <= 1'd0; 59 | 60 | 61 | ram128 ram_rel( 62 | .address(rd_data_add), 63 | .clock(clk), 64 | .data(ram_data_in), 65 | .wren(r_wren), 66 | .q(ram_out)); 67 | 68 | /*旋转因子 ROM表 地址5:0 数据 15:0 代表 rel + i*img 分别为 bits 88*/ 69 | wnp wnp_tab( 70 | .address(rom_wn), 71 | .clock(clk), 72 | .q(w_wnp)); 73 | 74 | 75 | 76 | always@(posedge clk or negedge rst_n ) 77 | if(!rst_n) 78 | lay_cnt <= 4'b0; 79 | else if((current_state == FFTCLC)&(bf_cnt == 7'd64)&(bf_clc_cnt == 4'd9)) 80 | lay_cnt <= lay_cnt + 1'd1; 81 | 82 | /*级数 计数器 采用移位计数方式 L */ 83 | always@(posedge clk or negedge rst_n ) 84 | if(!rst_n) 85 | r_lay_cnt <= 1'b0; 86 | else 87 | r_lay_cnt <= 1'b1 << lay_cnt; 88 | 89 | 90 | /*每层蝶形变换计数器 */ 91 | always@(posedge clk or negedge rst_n) 92 | if(!rst_n) 93 | bf_cnt <= 7'b0; 94 | else if((current_state == FFTCLC)&(bf_clc_cnt == 4'd0)&(r_wren == 1'b1)) 95 | if(bf_cnt < 7'd64) 96 | bf_cnt <= bf_cnt + 1'd1; 97 | else 98 | bf_cnt <= 7'd1; 99 | 100 | /*每个蝶形的两个输入数据的步距*/ 101 | always@(posedge clk or negedge rst_n) 102 | if(!rst_n) 103 | bstep <= 7'b0; 104 | else 105 | bstep <= 7'b1<<(lay_cnt ); 106 | 107 | /*蝶形变化计算 计数器*/ 108 | always@(posedge clk or negedge rst_n) 109 | if(!rst_n) 110 | bf_clc_cnt <= 4'b0; 111 | else 112 | if((current_state == FFTCLC)&(bf_clc_cnt < 4'd9)) 113 | bf_clc_cnt <= bf_clc_cnt + 1'd1; 114 | else 115 | bf_clc_cnt <= 4'd0; 116 | 117 | 118 | 119 | /*RAM 数据读写地址生成*/ 120 | always@(posedge clk or negedge rst_n) 121 | if(!rst_n)begin 122 | rd_data_add <= 7'd0; 123 | r_wren <= 1'd0; 124 | bf_go <= 1'd0; 125 | ram_add_prv <='d0; 126 | rom_wn <= 6'd0; 127 | end 128 | else case(current_state) 129 | RADDAT :begin 130 | r_wren <= 1'd1; 131 | rd_data_add <= {rd_cnt[0],rd_cnt[1],rd_cnt[2],rd_cnt[3],rd_cnt[4],rd_cnt[5],rd_cnt[6]};//rd_cnt[0:6];//输入数据倒序 132 | end 133 | 134 | /*计算蝶形变换 一次蝶形变换分为 读取RAN 和存储 RAM*/ 135 | FFTCLC : 136 | case(bf_clc_cnt) 137 | 0:begin 138 | bf_go <= 1'd1;//下一个时钟开始读取数据 139 | r_wren <= 1'd0; 140 | /*每次蝶形变换的RAM 数据读取的地址*/ 141 | rd_data_add[0] <= (r_lay_cnt[6]|r_lay_cnt[5]|r_lay_cnt[4]|r_lay_cnt[3]|r_lay_cnt[2]|r_lay_cnt[1])&(bf_cnt[0]) ; 142 | rd_data_add[1] <= (r_lay_cnt[6]|r_lay_cnt[5]|r_lay_cnt[4]|r_lay_cnt[3]|r_lay_cnt[2])&(bf_cnt[1])|(r_lay_cnt[0])&bf_cnt[0]; 143 | rd_data_add[2] <= (r_lay_cnt[6]|r_lay_cnt[5]|r_lay_cnt[4]|r_lay_cnt[3])&(bf_cnt[2])|(r_lay_cnt[1]|r_lay_cnt[0])&bf_cnt[1]; 144 | rd_data_add[3] <= (r_lay_cnt[6]|r_lay_cnt[5]|r_lay_cnt[4])&(bf_cnt[3])|(r_lay_cnt[2]|r_lay_cnt[1]|r_lay_cnt[0])&bf_cnt[2]; 145 | rd_data_add[4] <= (r_lay_cnt[6]|r_lay_cnt[5])&(bf_cnt[4])|(r_lay_cnt[3]|r_lay_cnt[2]|r_lay_cnt[1]|r_lay_cnt[0])&bf_cnt[3]; 146 | rd_data_add[5] <= (r_lay_cnt[6])&(bf_cnt[5])|(r_lay_cnt[4]|r_lay_cnt[3]|r_lay_cnt[2]|r_lay_cnt[1]|r_lay_cnt[0])&bf_cnt[4]; 147 | rd_data_add[6] <= (r_lay_cnt[5]|r_lay_cnt[4]|r_lay_cnt[3]|r_lay_cnt[2]|r_lay_cnt[1]|r_lay_cnt[0])&bf_cnt[5]; 148 | 149 | /*每次蝶形变换的 旋转因子的地址*/ 150 | rom_wn <={r_lay_cnt[6],r_lay_cnt[6],r_lay_cnt[6],r_lay_cnt[6],r_lay_cnt[6],r_lay_cnt[6]}&{bf_cnt[5],bf_cnt[4],bf_cnt[3],bf_cnt[2],bf_cnt[1],bf_cnt[0]}| 151 | {r_lay_cnt[5],r_lay_cnt[5],r_lay_cnt[5],r_lay_cnt[5],r_lay_cnt[5],r_lay_cnt[5]}&{bf_cnt[4],bf_cnt[3],bf_cnt[2],bf_cnt[1],bf_cnt[0],1'b0}| 152 | {r_lay_cnt[4],r_lay_cnt[4],r_lay_cnt[4],r_lay_cnt[4],r_lay_cnt[4],r_lay_cnt[4]}&{bf_cnt[3],bf_cnt[2],bf_cnt[1],bf_cnt[0],1'b0,1'b0}| 153 | {r_lay_cnt[3],r_lay_cnt[3],r_lay_cnt[3],r_lay_cnt[3],r_lay_cnt[3],r_lay_cnt[3]}&{bf_cnt[2],bf_cnt[1],bf_cnt[0],1'b0,1'b0,1'b0}| 154 | {r_lay_cnt[2],r_lay_cnt[2],r_lay_cnt[2],r_lay_cnt[2],r_lay_cnt[2],r_lay_cnt[2]}&{bf_cnt[1],bf_cnt[0],1'b0,1'b0,1'b0,1'b0}| 155 | {r_lay_cnt[1],r_lay_cnt[1],r_lay_cnt[1],r_lay_cnt[1],r_lay_cnt[1],r_lay_cnt[1]}&{bf_cnt[0],1'b0,1'b0,1'b0,1'b0,1'b0}| 156 | {r_lay_cnt[0],r_lay_cnt[0],r_lay_cnt[0],r_lay_cnt[0],r_lay_cnt[0],r_lay_cnt[0]}&{1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}; 157 | end 158 | 159 | 1:begin 160 | bf_go <= 1'd0; 161 | ram_add_prv <= rd_data_add; 162 | rd_data_add <= rd_data_add + bstep; //蝶形变换第二组数据输入 163 | end 164 | 165 | 8:begin 166 | r_wren <= 1'd1; 167 | rd_data_add <= ram_add_prv; //原位数据写入 168 | end 169 | 170 | 9:begin 171 | rd_data_add <= rd_data_add + bstep; 172 | end 173 | 174 | default:; 175 | 176 | 177 | endcase 178 | 179 | FFTOUT:begin 180 | rd_data_add <= ot_cnt; 181 | 182 | end 183 | 184 | 185 | default:begin 186 | r_wren <= 1'b0; 187 | 188 | 189 | end 190 | 191 | endcase 192 | 193 | // /*读取数据 计数器 */ 194 | // always@(posedge clk or negedge rst_n ) 195 | // if(!rst_n) 196 | // rd_cnt <= 1'b0; 197 | // else if(current_state == RADDAT) 198 | // rd_cnt <= rd_cnt + 1'd1; 199 | 200 | /*将外部数据读取到RAM*/ 201 | always@(posedge clk or negedge rst_n ) 202 | if(!rst_n) 203 | rd_cnt <= 1'b0; 204 | else if(current_state == RADDAT) 205 | rd_cnt <= rd_cnt + 1'd1; 206 | 207 | /*将RAM数据输出计数器*/ 208 | always@(posedge clk or negedge rst_n) 209 | if(!rst_n) 210 | ot_cnt <= 7'd0; 211 | else if(current_state == FFTOUT) 212 | ot_cnt <= ot_cnt + 1'b1; 213 | else 214 | ot_cnt <= 7'd0; 215 | 216 | /*数据运算结束指示*/ 217 | always@(posedge clk or negedge rst_n ) 218 | if(!rst_n) 219 | fft_done <= 1'b0; 220 | else if(current_state == FFTOUT) 221 | fft_done <= 1'd1; 222 | else 223 | fft_done <= 1'b0; 224 | 225 | /*状态机*/ 226 | always@(posedge clk or negedge rst_n ) 227 | if(!rst_n) 228 | current_state <= IDEL; 229 | else 230 | current_state <= next_state; 231 | 232 | 233 | 234 | always@(posedge clk or negedge rst_n ) 235 | if(!rst_n) 236 | next_state <= IDEL; 237 | else case(current_state) 238 | IDEL :begin 239 | if(fft_go) 240 | next_state <= RADDAT; 241 | end 242 | 243 | RADDAT:begin 244 | if(rd_cnt == 7'b111_1111) 245 | next_state <= FFTCLC; 246 | end 247 | FFTCLC:begin 248 | if((lay_cnt == 4'd7) &(bf_cnt == 7'b100_0000 )) 249 | next_state <= FFTOUT; 250 | 251 | 252 | end 253 | 254 | FFTOUT:begin 255 | if(ot_cnt == 7'b111_1110) 256 | next_state <= IDEL; 257 | end 258 | 259 | endcase 260 | 261 | 262 | 263 | butterfly_ra2_seri bfcalc( 264 | .rst_n(rst_n), 265 | .clk(clk), 266 | .bf_go(bf_go), 267 | .bf_done(bf_done), //两组数据 持续一个时钟周期 268 | .datax(ram_out[15:8]), //高位存储实部 269 | .datay(ram_out[7:0]), //地位存储虚部 270 | .wx(w_wnp[15:8]),//第一个时钟周期读取旋转因子 271 | .wy(w_wnp[7:0]), 272 | // .wx(8'd120),//第一个时钟周期读取旋转因子 273 | // .wy(8'd35), 274 | .wren(),//写数据使能 275 | .bfx(bf_data_out[15:8]), 276 | .bfy(bf_data_out[7:0])); 277 | 278 | /*RAM 数据多路选择器*/ 279 | 280 | // always@(*)begin 281 | // case(current_state) 282 | // FFTOUT: 283 | // ram_data_in = {data1,8'd0}; 284 | // FFTCLC: 285 | // ram_data_in = bf_data_out; 286 | // endcase 287 | // end 288 | assign fft_res = (current_state == FFTOUT)?ram_out:16'd0; 289 | 290 | // assign ram_data_in = (current_state == FFTCLC)?bf_data_out:{data1,8'd0}; 291 | assign ram_data_in = (current_state == FFTCLC)?bf_data_out:{(rd_cnt - 1'd1),8'd0};//测试使用 292 | endmodule 293 | 294 | 295 | 296 | 297 | 298 | 299 | 300 | 301 | 302 | 303 | 304 | 305 | 306 | 307 | 308 | 309 | 310 | 311 | 312 | 313 | 314 | 315 | 316 | 317 | 318 | 319 | 320 | -------------------------------------------------------------------------------- /FPGA_WORK/rtl/fft.v.bak: -------------------------------------------------------------------------------- 1 | module fft( 2 | rst_n, 3 | clk, 4 | data1, 5 | data2, 6 | res, 7 | ); 8 | reg rst_n, 9 | reg clk, 10 | input[7:0]data1, 11 | input[7:0]data2, 12 | output reg [8:0]res, 13 | 14 | always@(posedge clk or negedge rst_n ) 15 | if(!rst_n) 16 | res <= 9'd0; 17 | else 18 | res <= data1*data2; 19 | 20 | 21 | 22 | 23 | endmodule 24 | -------------------------------------------------------------------------------- /FPGA_WORK/rtl/fftbkbkb.v: -------------------------------------------------------------------------------- 1 | //128点FFT 2 | module fft( 3 | rst_n, 4 | clk, 5 | data1, 6 | 7 | fft_go, 8 | fft_done, 9 | fft_res 10 | ); 11 | input rst_n; 12 | input clk; 13 | input signed[7:0]data1; 14 | input fft_go; 15 | output reg fft_done; 16 | output reg signed[815:0]fft_res; 17 | 18 | reg[4:0]current_state; 19 | reg[4:0]next_state; 20 | reg rad_data_en;//读取外部数据使能 21 | reg[6:0]rd_cnt; 22 | reg[6:0]rd_data_add;//RAM 从外部读取数据线 23 | 24 | // assign rd_data_add = 7'b{rd_cnt[0]},{rd_cnt[1]},{rd_cnt[2]},{rd_cnt[3]},{rd_cnt[4]},{rd_cnt[5]},{rd_cnt[6]}; 25 | 26 | 27 | localparam[4:0] 28 | IDEL = 5'd0_0001, 29 | RADDAT= 5'd0_0010, 30 | FBKSEQ= 5'd0_0100, 31 | FFTCLC= 5'd0_1000, 32 | FFTOUT= 5'd1_0000; 33 | 34 | // /*读数据使能信号*/ 35 | // always@(posedge clk or negedge rst_n ) 36 | // if(!rst_n) 37 | // rad_data_en <= 1'b0; 38 | // else if(fft_go) 39 | // rad_data_en <= 1'd1; 40 | // else if(rd_cnt == 7'd111_1110) 41 | // rad_data_en <= 1'd0; 42 | 43 | 44 | ram128 ram_rel( 45 | .address(rd_data_add), 46 | .clock(clk), 47 | .data(data1), 48 | .wren(), 49 | .q()); 50 | 51 | 52 | /*RAM 数据读取地址生成*/ 53 | always@(posedge clk or negedge rst_n) 54 | if(!rst_n) 55 | rd_data_add <= 7'd0; 56 | else case() 57 | 58 | /*读取数据 计数器 */ 59 | always@(posedge clk or negedge rst_n ) 60 | if(!rst_n) 61 | rd_cnt <= 1'b0; 62 | else if(current_state == RADDAT) 63 | rd_cnt <= rd_cnt + 1'd1; 64 | 65 | /*将外部数据读取到RAM*/ 66 | always@(posedge clk or negedge rst_n ) 67 | if(!rst_n) 68 | rd_cnt <= 1'b0; 69 | else if(current_state == RADDAT) 70 | rd_cnt <= rd_cnt + 1'd1; 71 | 72 | 73 | 74 | /*状态机*/ 75 | always@(posedge clk or negedge rst_n ) 76 | if(!rst_n) 77 | current_state <= IDEL; 78 | else 79 | current_state <= next_state; 80 | 81 | 82 | 83 | always@(posedge clk or negedge rst_n ) 84 | if(!rst_n) 85 | next_state <= IDEL; 86 | else case(current_state) 87 | IDEL :begin 88 | if(fft_go) 89 | next_state <= RADDAT; 90 | end 91 | 92 | RADDAT:begin 93 | if(rd_cnt == 7'd111_1110) 94 | next_state <= FBKSEQ; 95 | end 96 | FBKSEQ:begin 97 | 98 | 99 | end 100 | 101 | 102 | endmodule 103 | 104 | 105 | 106 | 107 | 108 | 109 | 110 | 111 | 112 | 113 | 114 | 115 | 116 | 117 | 118 | 119 | 120 | 121 | 122 | 123 | 124 | 125 | 126 | 127 | 128 | 129 | 130 | -------------------------------------------------------------------------------- /FPGA_WORK/rtl/greybox_tmp/cbx_args.txt: -------------------------------------------------------------------------------- 1 | CLOCK_ENABLE_INPUT_A=BYPASS 2 | CLOCK_ENABLE_OUTPUT_A=BYPASS 3 | INTENDED_DEVICE_FAMILY="Cyclone IV E" 4 | NUMWORDS_A=128 5 | OPERATION_MODE=SINGLE_PORT 6 | OUTDATA_ACLR_A=NONE 7 | OUTDATA_REG_A=CLOCK0 8 | POWER_UP_UNINITIALIZED=FALSE 9 | READ_DURING_WRITE_MODE_PORT_A=NEW_DATA_NO_NBE_READ 10 | WIDTHAD_A=7 11 | WIDTH_A=16 12 | WIDTH_BYTEENA_A=1 13 | DEVICE_FAMILY="Cyclone IV E" 14 | address_a 15 | clock0 16 | q_a 17 | -------------------------------------------------------------------------------- /FPGA_WORK/rtl/ram128.qip: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/DeamonYang/FPGA_FFT/fa3b99e23651234b410932c9e37d66598745853f/FPGA_WORK/rtl/ram128.qip -------------------------------------------------------------------------------- /FPGA_WORK/testbench/address_gererate_tb.v: -------------------------------------------------------------------------------- 1 | module address_gererate_tb; 2 | 3 | reg[6:0]rd_data_add; 4 | reg[6:0]r_lay_cnt; 5 | reg[5:0]bf_cnt; 6 | reg[2:0]lay_cnt; 7 | reg[5:0]rom_wn; 8 | reg clk; 9 | 10 | initial clk = 0; 11 | always #20 clk = ~clk; 12 | 13 | initial begin 14 | r_lay_cnt = 1; 15 | forever begin 16 | #2560; 17 | r_lay_cnt = 6'd1 << lay_cnt + 1; 18 | end 19 | end 20 | 21 | 22 | initial begin 23 | lay_cnt = 0; 24 | forever begin 25 | 26 | #2560; 27 | lay_cnt = lay_cnt + 1; 28 | 29 | end 30 | end 31 | 32 | 33 | 34 | 35 | initial bf_cnt = 0; 36 | always #40 bf_cnt = bf_cnt + 1; 37 | 38 | 39 | initial begin 40 | #40000; 41 | $stop; 42 | 43 | end 44 | 45 | initial 46 | forever begin 47 | 48 | /*每次蝶形变换的RAM 数据读取的地址*/ 49 | rd_data_add[0] <= (r_lay_cnt[6]|r_lay_cnt[5]|r_lay_cnt[4]|r_lay_cnt[3]|r_lay_cnt[2]|r_lay_cnt[1])&(bf_cnt[0]) ; 50 | rd_data_add[1] <= (r_lay_cnt[6]|r_lay_cnt[5]|r_lay_cnt[4]|r_lay_cnt[3]|r_lay_cnt[2])&(bf_cnt[1])|(r_lay_cnt[0])&bf_cnt[0]; 51 | rd_data_add[2] <= (r_lay_cnt[6]|r_lay_cnt[5]|r_lay_cnt[4]|r_lay_cnt[3])&(bf_cnt[2])|(r_lay_cnt[1]|r_lay_cnt[0])&bf_cnt[1]; 52 | rd_data_add[3] <= (r_lay_cnt[6]|r_lay_cnt[5]|r_lay_cnt[4])&(bf_cnt[3])|(r_lay_cnt[2]|r_lay_cnt[1]|r_lay_cnt[0])&bf_cnt[2]; 53 | rd_data_add[4] <= (r_lay_cnt[6]|r_lay_cnt[5])&(bf_cnt[4])|(r_lay_cnt[3]|r_lay_cnt[2]|r_lay_cnt[1]|r_lay_cnt[0])&bf_cnt[3]; 54 | rd_data_add[5] <= (r_lay_cnt[6])&(bf_cnt[5])|(r_lay_cnt[4]|r_lay_cnt[3]|r_lay_cnt[2]|r_lay_cnt[1]|r_lay_cnt[0])&bf_cnt[4]; 55 | rd_data_add[6] <= (r_lay_cnt[5]|r_lay_cnt[4]|r_lay_cnt[3]|r_lay_cnt[2]|r_lay_cnt[1]|r_lay_cnt[0])&bf_cnt[5]; 56 | 57 | /*每次蝶形变换的 旋转因子的地址*/ 58 | rom_wn <={r_lay_cnt[6],r_lay_cnt[6],r_lay_cnt[6],r_lay_cnt[6],r_lay_cnt[6],r_lay_cnt[6]}&{bf_cnt[5],bf_cnt[4],bf_cnt[3],bf_cnt[2],bf_cnt[1],bf_cnt[0]}| 59 | {r_lay_cnt[5],r_lay_cnt[5],r_lay_cnt[5],r_lay_cnt[5],r_lay_cnt[5],r_lay_cnt[5]}&{bf_cnt[4],bf_cnt[3],bf_cnt[2],bf_cnt[1],bf_cnt[0],1'b0}| 60 | {r_lay_cnt[4],r_lay_cnt[4],r_lay_cnt[4],r_lay_cnt[4],r_lay_cnt[4],r_lay_cnt[4]}&{bf_cnt[3],bf_cnt[2],bf_cnt[1],bf_cnt[0],1'b0,1'b0}| 61 | {r_lay_cnt[3],r_lay_cnt[3],r_lay_cnt[3],r_lay_cnt[3],r_lay_cnt[3],r_lay_cnt[3]}&{bf_cnt[2],bf_cnt[1],bf_cnt[0],1'b0,1'b0,1'b0}| 62 | {r_lay_cnt[2],r_lay_cnt[2],r_lay_cnt[2],r_lay_cnt[2],r_lay_cnt[2],r_lay_cnt[2]}&{bf_cnt[1],bf_cnt[0],1'b0,1'b0,1'b0,1'b0}| 63 | {r_lay_cnt[1],r_lay_cnt[1],r_lay_cnt[1],r_lay_cnt[1],r_lay_cnt[1],r_lay_cnt[1]}&{bf_cnt[0],1'b0,1'b0,1'b0,1'b0,1'b0}| 64 | {r_lay_cnt[0],r_lay_cnt[0],r_lay_cnt[0],r_lay_cnt[0],r_lay_cnt[0],r_lay_cnt[0]}&{1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}; 65 | 66 | #40; 67 | end 68 | 69 | endmodule 70 | 71 | 72 | 73 | 74 | 75 | 76 | 77 | 78 | 79 | 80 | 81 | 82 | 83 | 84 | 85 | 86 | 87 | 88 | 89 | 90 | 91 | 92 | 93 | 94 | 95 | 96 | 97 | 98 | 99 | 100 | 101 | -------------------------------------------------------------------------------- /FPGA_WORK/testbench/address_gererate_tb.v.bak: -------------------------------------------------------------------------------- 1 | module address_gererate_tb; 2 | 3 | reg[6:0]rd_data_add; 4 | reg[6:0]r_lay_cnt; 5 | reg[5:0]bf_cnt; 6 | reg clk; 7 | 8 | 9 | 10 | rd_data_add[0] <= (r_lay_cnt[6]|r_lay_cnt[5]|r_lay_cnt[4]|r_lay_cnt[3]|r_lay_cnt[2]|r_lay_cnt[1])&(bf_cnt[0]) ; 11 | rd_data_add[1] <= (r_lay_cnt[6]|r_lay_cnt[5]|r_lay_cnt[4]|r_lay_cnt[3]|r_lay_cnt[2])&(bf_cnt[1])|(r_lay_cnt[0])&bf_cnt[0]; 12 | rd_data_add[2] <= (r_lay_cnt[6]|r_lay_cnt[5]|r_lay_cnt[4]|r_lay_cnt[3])&(bf_cnt[2])|(r_lay_cnt[1]|r_lay_cnt[0])&bf_cnt[1]; 13 | rd_data_add[3] <= (r_lay_cnt[6]|r_lay_cnt[5]|r_lay_cnt[4])&(bf_cnt[3])|(r_lay_cnt[2]|r_lay_cnt[1]|r_lay_cnt[0])&bf_cnt[2]; 14 | rd_data_add[4] <= (r_lay_cnt[6]|r_lay_cnt[5])&(bf_cnt[4])|(r_lay_cnt[3]|r_lay_cnt[2]|r_lay_cnt[1]|r_lay_cnt[0])&bf_cnt[3]; 15 | rd_data_add[5] <= (r_lay_cnt[6])&(bf_cnt[5])|(r_lay_cnt[4]|r_lay_cnt[3]|r_lay_cnt[2]|r_lay_cnt[1]|r_lay_cnt[0])&bf_cnt[4]; 16 | rd_data_add[6] <= (r_lay_cnt[5]|r_lay_cnt[4]|r_lay_cnt[3]|r_lay_cnt[2]|r_lay_cnt[1]|r_lay_cnt[0])&bf_cnt[5]; 17 | 18 | 19 | endmodule 20 | 21 | 22 | -------------------------------------------------------------------------------- /FPGA_WORK/testbench/butterfly_ra2_seri_tb.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns/1ps 2 | module butterfly_ra2_seri_tb; 3 | 4 | 5 | reg rst_n; 6 | reg clk; 7 | reg bf_go; 8 | wire bf_done; 9 | 10 | reg[7:0]datax; 11 | reg[7:0]datay; 12 | reg[7:0]wx;//第一个时钟周期读取旋转因子 13 | reg[7:0]wy; 14 | 15 | wire[7:0]bfx; 16 | wire[7:0]bfy; 17 | wire wren; 18 | 19 | butterfly_ra2_seri bs( 20 | rst_n, 21 | clk, 22 | bf_go, 23 | bf_done, 24 | 25 | datax, 26 | datay, 27 | 28 | wx,//第一个时钟周期读取旋转因子 29 | wy, 30 | 31 | wren,//写数据使能 32 | bfx, 33 | bfy); 34 | 35 | 36 | initial clk = 0; 37 | always #20 clk = ~clk; 38 | 39 | initial begin 40 | rst_n = 0; 41 | #1000; 42 | rst_n = 1; 43 | 44 | 45 | #4000; 46 | $stop; 47 | 48 | end 49 | 50 | 51 | 52 | 53 | initial begin 54 | datax = 128; 55 | datay = 100; 56 | wx = 20; 57 | wy = 35; 58 | forever begin 59 | datax = datax + 5; 60 | datay = datay - 5; 61 | bf_go = 1; 62 | #40; 63 | bf_go = 0; 64 | #320; 65 | end 66 | 67 | 68 | 69 | end 70 | 71 | 72 | 73 | endmodule 74 | 75 | 76 | -------------------------------------------------------------------------------- /FPGA_WORK/testbench/butterfly_ra2_seri_tb.v.bak: -------------------------------------------------------------------------------- 1 | module butterfly_ra2_seri_tb; 2 | 3 | butterfly_ra2_seri 4 | ( 5 | rst_n, 6 | clk, 7 | bf_go, 8 | bf_done, 9 | 10 | datax, 11 | datay, 12 | 13 | wx,//第一个时钟周期读取旋转因子 14 | wy, 15 | 16 | bfx, 17 | bfy, 18 | ); 19 | 20 | 21 | 22 | 23 | endmodule 24 | 25 | 26 | -------------------------------------------------------------------------------- /FPGA_WORK/testbench/butterfly_ra2_tb.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns/1ps 2 | 3 | 4 | module butterfly_ra2_tb; 5 | 6 | 7 | 8 | reg rst_n; 9 | reg clk; 10 | reg bf_go; 11 | wire bf_done; 12 | reg signed[7:0]wx; 13 | reg signed[7:0]wy; 14 | reg signed[7:0]x1; 15 | reg signed[7:0]y1; 16 | reg signed[7:0]x2; 17 | reg signed[7:0]y2; 18 | wire signed[8:0]bfx1; 19 | wire signed[8:0]bfy1; 20 | wire signed[8:0]bfx2; 21 | wire signed[8:0]bfy2; 22 | 23 | 24 | 25 | butterfly_ra2 butterfly_ra2_lab1( 26 | rst_n, 27 | clk, 28 | bf_go, 29 | bf_done, 30 | wx, 31 | wy, 32 | x1, 33 | y1, 34 | x2, 35 | y2, 36 | bfx1, 37 | bfy1, 38 | bfx2, 39 | bfy2 40 | ); 41 | 42 | 43 | initial begin 44 | rst_n = 0; 45 | 46 | #210; 47 | rst_n = 1; 48 | 49 | #40000; 50 | $stop; 51 | end 52 | 53 | 54 | 55 | 56 | 57 | initial clk = 0; 58 | always #20 clk = ~clk; 59 | 60 | initial begin 61 | wx = 8'd1; 62 | wy = 8'd1; 63 | x1 = 8'd1; 64 | y1 = 8'd1; 65 | x2 = 8'd1; 66 | y2 = 8'd1; 67 | bf_go = 0; 68 | #210; 69 | forever begin 70 | wx = wx + 10; 71 | wy = wy + 20; 72 | x1 = x1 + 30; 73 | y1 = y1 + 40; 74 | x2 = x2 + 50; 75 | y2 = y2 + 60; 76 | bf_go = 1; 77 | #40; 78 | bf_go = 0; 79 | #80; 80 | 81 | end 82 | end 83 | 84 | 85 | 86 | 87 | endmodule 88 | -------------------------------------------------------------------------------- /FPGA_WORK/testbench/butterfly_ra2_tb.v.bak: -------------------------------------------------------------------------------- 1 | `timescale 1ns/1ps 2 | 3 | 4 | module butterfly_ra2_tb; 5 | 6 | 7 | 8 | input rst_n; 9 | input clk; 10 | input bf_go; 11 | output reg bf_done; 12 | input signed[8:0]wx; 13 | input signed[8:0]wy; 14 | input signed[8:0]x1; 15 | input signed[8:0]y1; 16 | input signed[8:0]x2; 17 | input signed[8:0]y2; 18 | output reg signed[9:0]bfx1; 19 | output reg signed[9:0]bfy1; 20 | output reg signed[9:0]bfx2; 21 | output reg signed[9:0]bfy2; 22 | 23 | 24 | 25 | butterfly_ra2 butterfly_ra2_lab1( 26 | rst_n, 27 | clk, 28 | bf_go, 29 | bf_done, 30 | wx, 31 | wy, 32 | x1, 33 | y1, 34 | x2, 35 | y2, 36 | bfx1, 37 | bfy1, 38 | bfx2, 39 | bfy2, 40 | ); 41 | 42 | 43 | 44 | endmodule 45 | -------------------------------------------------------------------------------- /FPGA_WORK/testbench/fft_mult_tb.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns/1ps 2 | module fft_mult_tb; 3 | 4 | 5 | reg rst_n; 6 | reg clk; 7 | reg[7:0]data1; 8 | reg[7:0]data2; 9 | wire [15:0]res; 10 | 11 | 12 | fft fft_lab1( 13 | .rst_n(rst_n), 14 | .clk(clk), 15 | .data1(data1), 16 | .data2(data2), 17 | .res(res) 18 | ); 19 | 20 | initial begin 21 | rst_n = 0; 22 | #100; 23 | rst_n = 1; 24 | 25 | 26 | #40000; 27 | $stop; 28 | 29 | end 30 | 31 | initial clk = 0; 32 | always #20 clk = ~clk; 33 | 34 | initial begin 35 | data1 = 0; 36 | data2 = 8'hff; 37 | 38 | forever begin 39 | data1 = data1 + 1'b1; 40 | data2 = data2 - 1'b1; 41 | #40; 42 | 43 | end 44 | 45 | end 46 | 47 | 48 | 49 | endmodule 50 | 51 | 52 | -------------------------------------------------------------------------------- /FPGA_WORK/testbench/fft_mult_tb.v.bak: -------------------------------------------------------------------------------- 1 | `timescale 1ns/1ps 2 | module fft_mult_tb; 3 | 4 | 5 | reg rst_n; 6 | reg clk; 7 | reg[7:0]data1; 8 | reg[7:0]data2; 9 | wire [8:0]res; 10 | 11 | 12 | fft fft_lab1( 13 | .rst_n(rst_n), 14 | .clk(ckl), 15 | .data1(data1), 16 | .data2(data2), 17 | .res(res) 18 | ); 19 | 20 | 21 | 22 | 23 | 24 | endmodule 25 | 26 | 27 | -------------------------------------------------------------------------------- /FPGA_WORK/testbench/fft_tb.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns/1ps 2 | module fft_tb; 3 | 4 | 5 | 6 | reg rst_n; 7 | reg clk; 8 | reg signed[7:0]data1; 9 | reg fft_go; 10 | wire fft_done; 11 | wire [7:0]fft_res_rel; 12 | wire [7:0]fft_res_img; 13 | 14 | reg [6:0]test_ram_add; 15 | wire [15:0] test_data; 16 | reg test_wren; 17 | wire [15:0] test_q; 18 | 19 | fft fft_lab1( 20 | .rst_n(rst_n), 21 | .clk(clk), 22 | .data1(data1), 23 | .fft_go(fft_go), 24 | .fft_done(fft_done), 25 | .fft_res({fft_res_rel,fft_res_img}) 26 | ); 27 | 28 | assign test_data = {8'd0,test_ram_add}; 29 | ram128 ram_test( 30 | .address(test_ram_add), 31 | .clock(clk), 32 | .data(test_data), 33 | .wren(test_wren), 34 | .q(test_q)); 35 | 36 | initial begin 37 | test_ram_add = 0; 38 | test_wren = 1; 39 | #5120 40 | test_wren = 0; 41 | end 42 | 43 | always #40 test_ram_add = test_ram_add + 1; 44 | 45 | 46 | 47 | 48 | initial begin 49 | rst_n = 0; 50 | fft_go = 0; 51 | #1000; 52 | rst_n = 1; 53 | #100; 54 | fft_go = 1; 55 | #40; 56 | fft_go = 0; 57 | 58 | #240000; 59 | $stop; 60 | 61 | 62 | end 63 | 64 | initial clk = 0; 65 | always #20 clk = ~clk; 66 | 67 | 68 | initial begin 69 | data1 = 0; 70 | #1000; 71 | forever begin 72 | 73 | data1 = data1 + 1; 74 | #20; 75 | 76 | end 77 | 78 | 79 | 80 | end 81 | 82 | endmodule 83 | 84 | 85 | 86 | 87 | -------------------------------------------------------------------------------- /FPGA_WORK/testbench/fft_tb.v.bak: -------------------------------------------------------------------------------- 1 | `timescale 1ns/1ps 2 | module fft_tb 3 | 4 | 5 | 6 | end module 7 | 8 | 9 | 10 | 11 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | 本工程实现了在FPGA上的FFT 主要难点有蝶形变换与操作RAM地址实现计算 2 | 结果与数据的存取（地址生成） 3 | FPGA_WORK FPGA FFT 工程 4 | VC_PROJ C语言FFT工程，用于验证计算结果是否正确 -------------------------------------------------------------------------------- /VC_PROJ/main.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/DeamonYang/FPGA_FFT/fa3b99e23651234b410932c9e37d66598745853f/VC_PROJ/main.c -------------------------------------------------------------------------------- /VC_PROJ/myfft.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/DeamonYang/FPGA_FFT/fa3b99e23651234b410932c9e37d66598745853f/VC_PROJ/myfft.c -------------------------------------------------------------------------------- /VC_PROJ/myfft.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/DeamonYang/FPGA_FFT/fa3b99e23651234b410932c9e37d66598745853f/VC_PROJ/myfft.h --------------------------------------------------------------------------------