├── .gitattributes ├── .gitignore ├── Projects ├── Abacus │ ├── proj │ │ ├── _READ_ME_.txt │ │ ├── cleanup.cmd │ │ ├── cleanup.sh │ │ └── create_project.tcl │ └── src │ │ ├── constraints │ │ └── Basys3_Master.xdc │ │ └── hdl │ │ ├── Adder_Subtractor.v │ │ ├── Basys3_Abacus_Top.v │ │ ├── Binary_to_BCD_B1_bcdout1.v │ │ ├── Binary_to_BCD_B2_bcdout2.v │ │ ├── Binary_to_BCD_B_bcdout.v │ │ ├── Display_QU.v │ │ ├── Display_REM.v │ │ ├── Divider.v │ │ ├── Seg_7_Display.v │ │ ├── Segment_Scroll.v │ │ ├── multi_4_4_pp0.v │ │ ├── multi_4_4_pp1.v │ │ ├── multi_4_4_pp2.v │ │ └── multi_4_4_pp3.v ├── GPIO │ ├── proj │ │ ├── _READ_ME_.txt │ │ ├── cleanup.cmd │ │ ├── cleanup.sh │ │ └── create_project.tcl │ └── src │ │ ├── constraints │ │ └── Basys3_Master.xdc │ │ └── hdl │ │ ├── GPIO_Demo.vhd │ │ ├── MouseCtl.vhd │ │ ├── MouseDisplay.vhd │ │ ├── Ps2Interface.vhd │ │ ├── UART_TX_CTRL.vhd │ │ ├── clk_wiz_0.vhd │ │ ├── clk_wiz_0_clk_wiz.vhd │ │ ├── debouncer.vhd │ │ └── vga_ctrl.vhd ├── Keyboard │ ├── proj │ │ ├── _READ_ME_.txt │ │ ├── cleanup.cmd │ │ ├── cleanup.sh │ │ └── create_project.tcl │ └── src │ │ ├── constraints │ │ └── Basys3_Master.xdc │ │ └── hdl │ │ ├── PS2Receiver.v │ │ ├── bin2ascii.v │ │ ├── debouncer.v │ │ ├── top.v │ │ ├── uart_buf_con.v │ │ └── uart_tx.v └── XADC_Demo │ ├── proj │ ├── _READ_ME_.txt │ ├── cleanup.cmd │ ├── cleanup.sh │ └── create_project.tcl │ └── src │ ├── constraints │ └── Basys3_Master.xdc │ ├── hdl │ ├── DigitToSeg.v │ ├── UART_TX_CTRL.vhd │ ├── XADCdemo.v │ ├── counter3bit.v │ ├── decoder3_8.v │ ├── mux4_4bus.v │ ├── segClkDevider.v │ └── sevensegdecoder.v │ └── ip │ └── xadc_wiz_0_1 │ ├── xadc_wiz_0.dcp │ ├── xadc_wiz_0.upgrade_log │ ├── xadc_wiz_0.vhd │ ├── xadc_wiz_0.xci │ ├── xadc_wiz_0.xdc │ ├── xadc_wiz_0.xml │ ├── xadc_wiz_0_funcsim.v │ ├── xadc_wiz_0_funcsim.vhdl │ ├── xadc_wiz_0_ooc.xdc │ ├── xadc_wiz_0_stub.v │ └── xadc_wiz_0_stub.vhdl └── Resources └── XDC └── Basys3_Master.xdc /.gitattributes: -------------------------------------------------------------------------------- 1 | # Auto detect text files and perform LF normalization 2 | * text=auto 3 | 4 | # Custom for Visual Studio 5 | *.cs diff=csharp 6 | 7 | # Standard to msysgit 8 | *.doc diff=astextplain 9 | *.DOC diff=astextplain 10 | *.docx diff=astextplain 11 | *.DOCX diff=astextplain 12 | *.dot diff=astextplain 13 | *.DOT diff=astextplain 14 | *.pdf diff=astextplain 15 | *.PDF diff=astextplain 16 | *.rtf diff=astextplain 17 | *.RTF diff=astextplain 18 | -------------------------------------------------------------------------------- /.gitignore: -------------------------------------------------------------------------------- 1 | # Windows image file caches 2 | Thumbs.db 3 | ehthumbs.db 4 | 5 | # Folder config file 6 | Desktop.ini 7 | 8 | # Recycle Bin used on file shares 9 | $RECYCLE.BIN/ 10 | 11 | # Windows Installer files 12 | *.cab 13 | *.msi 14 | *.msm 15 | *.msp 16 | 17 | # Windows shortcuts 18 | *.lnk 19 | 20 | # ========================= 21 | # Operating System Files 22 | # ========================= 23 | 24 | # OSX 25 | # ========================= 26 | 27 | .DS_Store 28 | .AppleDouble 29 | .LSOverride 30 | 31 | # Thumbnails 32 | ._* 33 | 34 | # Files that might appear on external disk 35 | .Spotlight-V100 36 | .Trashes 37 | 38 | # Directories potentially created on remote AFP share 39 | .AppleDB 40 | .AppleDesktop 41 | Network Trash Folder 42 | Temporary Items 43 | .apdisk 44 | -------------------------------------------------------------------------------- /Projects/Abacus/proj/_READ_ME_.txt: -------------------------------------------------------------------------------- 1 | In order to run the create_project script successfully, the folder must be in its initial state 2 | containing only the cleanup, create_project scripts, and this document. 3 | 4 | To restore the folder to its initial state, double-click the cleanup Windows Command Script. 5 | 6 | !!!!CAUTION!!!! 7 | 8 | Moving or copying the cleanup Windows Command Script can result in unintentional loss of data on your 9 | system. The script contains a short list of specific files to ignore once it is run, all other files 10 | and folders within its directory location will be ERASED. Use this only within the project folder as 11 | instructed. 12 | 13 | See material on the usage of demo projects at reference.digilentinc.com -------------------------------------------------------------------------------- /Projects/Abacus/proj/cleanup.cmd: -------------------------------------------------------------------------------- 1 | @echo off 2 | rem delete all files from subfolders 3 | for /d /r %%i in (*) do del /f /q %%i\* 4 | rem delete all subfolders 5 | for /d %%i in (*) do rd /S /Q %%i 6 | 7 | rem unmark read only from all files 8 | attrib -R .\* /S 9 | 10 | rem mark read only those we wish to keep 11 | attrib +R .\create_project.tcl 12 | attrib +R .\cleanup.sh 13 | attrib +R .\cleanup.cmd 14 | attrib +R .\.gitignore 15 | attrib +R .\_READ_ME_.txt 16 | 17 | rem delete all non read-only 18 | del /Q /A:-R .\* 19 | 20 | rem unmark read-only 21 | attrib -R .\* 22 | -------------------------------------------------------------------------------- /Projects/Abacus/proj/cleanup.sh: -------------------------------------------------------------------------------- 1 | # This script is useful for cleaning up the 'project' 2 | # directory of a Digilent Vivado-project git repository 3 | ### 4 | # Run the following command to change permissions of 5 | # this 'cleanup' file if needed: 6 | # chmod u+x cleanup.sh 7 | ### 8 | # Remove directories/subdirectories 9 | find . -mindepth 1 -type d -exec rm -rf {} + 10 | # Remove any other files than: 11 | find . -type f ! -name 'cleanup.sh' \ 12 | ! -name 'cleanup.cmd' \ 13 | ! -name 'create_project.tcl' \ 14 | ! -name '.gitignore' \ 15 | -exec rm -rf {} + 16 | -------------------------------------------------------------------------------- /Projects/Abacus/proj/create_project.tcl: -------------------------------------------------------------------------------- 1 | # Run this script to create the Vivado project files in the WORKING DIRECTORY 2 | # If ::create_path global variable is set, the project is created under that path instead of the working dir 3 | 4 | if {[info exists ::create_path]} { 5 | set dest_dir $::create_path 6 | } else { 7 | set dest_dir [pwd] 8 | } 9 | puts "INFO: Creating new project in $dest_dir" 10 | 11 | # Set the reference directory for source file relative paths (by default the value is script directory path) 12 | set proj_name "Abacus" 13 | 14 | # Set the reference directory for source file relative paths (by default the value is script directory path) 15 | set origin_dir ".." 16 | 17 | # Set the directory path for the original project from where this script was exported 18 | set orig_proj_dir "[file normalize "$origin_dir/proj"]" 19 | 20 | set src_dir $origin_dir/src 21 | set repo_dir $origin_dir/repo 22 | 23 | # Set the board part number 24 | set part_num "xc7a35tcpg236-1" 25 | 26 | # Create project 27 | create_project $proj_name $dest_dir 28 | 29 | # Set the directory path for the new project 30 | set proj_dir [get_property directory [current_project]] 31 | 32 | # Set project properties 33 | set obj [get_projects $proj_name] 34 | set_property "default_lib" "xil_defaultlib" $obj 35 | set_property "part" "$part_num" $obj 36 | set_property "simulator_language" "Mixed" $obj 37 | set_property "target_language" "VHDL" $obj 38 | 39 | # Create 'sources_1' fileset (if not found) 40 | if {[string equal [get_filesets -quiet sources_1] ""]} { 41 | create_fileset -srcset sources_1 42 | } 43 | 44 | # Create 'constrs_1' fileset (if not found) 45 | if {[string equal [get_filesets -quiet constrs_1] ""]} { 46 | create_fileset -constrset constrs_1 47 | } 48 | 49 | # Set IP repository paths 50 | set obj [get_filesets sources_1] 51 | set_property "ip_repo_paths" "[file normalize $repo_dir]" $obj 52 | 53 | # Add conventional sources 54 | add_files -quiet $src_dir/hdl 55 | 56 | # Add IPs 57 | add_files -quiet [glob -nocomplain ../src/ip/*/*.xci] 58 | 59 | # Add constraints 60 | add_files -fileset constrs_1 -quiet $src_dir/constraints 61 | 62 | # Refresh IP Repositories 63 | #update_ip_catalog 64 | 65 | # Create 'synth_1' run (if not found) 66 | if {[string equal [get_runs -quiet synth_1] ""]} { 67 | create_run -name synth_1 -part $part_num -flow {Vivado Synthesis 2014} -strategy "Flow_PerfOptimized_High" -constrset constrs_1 68 | } else { 69 | set_property strategy "Flow_PerfOptimized_High" [get_runs synth_1] 70 | set_property flow "Vivado Synthesis 2014" [get_runs synth_1] 71 | } 72 | set obj [get_runs synth_1] 73 | set_property "part" "$part_num" $obj 74 | set_property "steps.synth_design.args.fanout_limit" "400" $obj 75 | set_property "steps.synth_design.args.fsm_extraction" "one_hot" $obj 76 | set_property "steps.synth_design.args.keep_equivalent_registers" "1" $obj 77 | set_property "steps.synth_design.args.resource_sharing" "off" $obj 78 | set_property "steps.synth_design.args.no_lc" "1" $obj 79 | set_property "steps.synth_design.args.shreg_min_size" "5" $obj 80 | 81 | # set the current synth run 82 | current_run -synthesis [get_runs synth_1] 83 | 84 | # Create 'impl_1' run (if not found) 85 | if {[string equal [get_runs -quiet impl_1] ""]} { 86 | create_run -name impl_1 -part $part_num -flow {Vivado Implementation 2014} -strategy "Vivado Implementation Defaults" -constrset constrs_1 -parent_run synth_1 87 | } else { 88 | set_property strategy "Vivado Implementation Defaults" [get_runs impl_1] 89 | set_property flow "Vivado Implementation 2014" [get_runs impl_1] 90 | } 91 | set obj [get_runs impl_1] 92 | set_property "part" "$part_num" $obj 93 | set_property "steps.write_bitstream.args.bin_file" "1" $obj 94 | 95 | # set the current impl run 96 | current_run -implementation [get_runs impl_1] 97 | 98 | #puts "INFO: Project created:$proj_name" 99 | 100 | # Comment the following section, if there is no block design 101 | # Create block design 102 | #source $origin_dir/src/bd/bt_gpio.tcl 103 | 104 | # Generate the wrapper 105 | #set design_name [get_bd_designs] 106 | #make_wrapper -files [get_files $design_name.bd] -top -import 107 | 108 | #set obj [get_filesets sources_1] 109 | #set_property "top" "bt_gpio_top" $obj 110 | 111 | #puts "INFO: Block design created: $design_name.bd" 112 | -------------------------------------------------------------------------------- /Projects/Abacus/src/constraints/Basys3_Master.xdc: -------------------------------------------------------------------------------- 1 | ## This file is a general .xdc for the Basys3 rev B board 2 | ## To use it in a project: 3 | ## - uncomment the lines corresponding to used pins 4 | ## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project 5 | 6 | ## Clock signal 7 | set_property PACKAGE_PIN W5 [get_ports clk] 8 | set_property IOSTANDARD LVCMOS33 [get_ports clk] 9 | create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports clk] 10 | 11 | ## Switches 12 | set_property PACKAGE_PIN V17 [get_ports {sw[0]}] 13 | set_property IOSTANDARD LVCMOS33 [get_ports {sw[0]}] 14 | set_property PACKAGE_PIN V16 [get_ports {sw[1]}] 15 | set_property IOSTANDARD LVCMOS33 [get_ports {sw[1]}] 16 | set_property PACKAGE_PIN W16 [get_ports {sw[2]}] 17 | set_property IOSTANDARD LVCMOS33 [get_ports {sw[2]}] 18 | set_property PACKAGE_PIN W17 [get_ports {sw[3]}] 19 | set_property IOSTANDARD LVCMOS33 [get_ports {sw[3]}] 20 | set_property PACKAGE_PIN W15 [get_ports {sw[4]}] 21 | set_property IOSTANDARD LVCMOS33 [get_ports {sw[4]}] 22 | set_property PACKAGE_PIN V15 [get_ports {sw[5]}] 23 | set_property IOSTANDARD LVCMOS33 [get_ports {sw[5]}] 24 | set_property PACKAGE_PIN W14 [get_ports {sw[6]}] 25 | set_property IOSTANDARD LVCMOS33 [get_ports {sw[6]}] 26 | set_property PACKAGE_PIN W13 [get_ports {sw[7]}] 27 | set_property IOSTANDARD LVCMOS33 [get_ports {sw[7]}] 28 | set_property PACKAGE_PIN V2 [get_ports {sw[8]}] 29 | set_property IOSTANDARD LVCMOS33 [get_ports {sw[8]}] 30 | set_property PACKAGE_PIN T3 [get_ports {sw[9]}] 31 | set_property IOSTANDARD LVCMOS33 [get_ports {sw[9]}] 32 | set_property PACKAGE_PIN T2 [get_ports {sw[10]}] 33 | set_property IOSTANDARD LVCMOS33 [get_ports {sw[10]}] 34 | set_property PACKAGE_PIN R3 [get_ports {sw[11]}] 35 | set_property IOSTANDARD LVCMOS33 [get_ports {sw[11]}] 36 | set_property PACKAGE_PIN W2 [get_ports {sw[12]}] 37 | set_property IOSTANDARD LVCMOS33 [get_ports {sw[12]}] 38 | set_property PACKAGE_PIN U1 [get_ports {sw[13]}] 39 | set_property IOSTANDARD LVCMOS33 [get_ports {sw[13]}] 40 | set_property PACKAGE_PIN T1 [get_ports {sw[14]}] 41 | set_property IOSTANDARD LVCMOS33 [get_ports {sw[14]}] 42 | set_property PACKAGE_PIN R2 [get_ports {sw[15]}] 43 | set_property IOSTANDARD LVCMOS33 [get_ports {sw[15]}] 44 | 45 | 46 | ## LEDs 47 | set_property PACKAGE_PIN U16 [get_ports {led[0]}] 48 | set_property IOSTANDARD LVCMOS33 [get_ports {led[0]}] 49 | set_property PACKAGE_PIN E19 [get_ports {led[1]}] 50 | set_property IOSTANDARD LVCMOS33 [get_ports {led[1]}] 51 | set_property PACKAGE_PIN U19 [get_ports {led[2]}] 52 | set_property IOSTANDARD LVCMOS33 [get_ports {led[2]}] 53 | set_property PACKAGE_PIN V19 [get_ports {led[3]}] 54 | set_property IOSTANDARD LVCMOS33 [get_ports {led[3]}] 55 | set_property PACKAGE_PIN W18 [get_ports {led[4]}] 56 | set_property IOSTANDARD LVCMOS33 [get_ports {led[4]}] 57 | set_property PACKAGE_PIN U15 [get_ports {led[5]}] 58 | set_property IOSTANDARD LVCMOS33 [get_ports {led[5]}] 59 | set_property PACKAGE_PIN U14 [get_ports {led[6]}] 60 | set_property IOSTANDARD LVCMOS33 [get_ports {led[6]}] 61 | set_property PACKAGE_PIN V14 [get_ports {led[7]}] 62 | set_property IOSTANDARD LVCMOS33 [get_ports {led[7]}] 63 | set_property PACKAGE_PIN V13 [get_ports {led[8]}] 64 | set_property IOSTANDARD LVCMOS33 [get_ports {led[8]}] 65 | set_property PACKAGE_PIN V3 [get_ports {led[9]}] 66 | set_property IOSTANDARD LVCMOS33 [get_ports {led[9]}] 67 | set_property PACKAGE_PIN W3 [get_ports {led[10]}] 68 | set_property IOSTANDARD LVCMOS33 [get_ports {led[10]}] 69 | set_property PACKAGE_PIN U3 [get_ports {led[11]}] 70 | set_property IOSTANDARD LVCMOS33 [get_ports {led[11]}] 71 | set_property PACKAGE_PIN P3 [get_ports {led[12]}] 72 | set_property IOSTANDARD LVCMOS33 [get_ports {led[12]}] 73 | set_property PACKAGE_PIN N3 [get_ports {led[13]}] 74 | set_property IOSTANDARD LVCMOS33 [get_ports {led[13]}] 75 | set_property PACKAGE_PIN P1 [get_ports {led[14]}] 76 | set_property IOSTANDARD LVCMOS33 [get_ports {led[14]}] 77 | set_property PACKAGE_PIN L1 [get_ports {led[15]}] 78 | set_property IOSTANDARD LVCMOS33 [get_ports {led[15]}] 79 | 80 | 81 | ##7 segment display 82 | set_property PACKAGE_PIN W7 [get_ports {seg[0]}] 83 | set_property IOSTANDARD LVCMOS33 [get_ports {seg[0]}] 84 | set_property PACKAGE_PIN W6 [get_ports {seg[1]}] 85 | set_property IOSTANDARD LVCMOS33 [get_ports {seg[1]}] 86 | set_property PACKAGE_PIN U8 [get_ports {seg[2]}] 87 | set_property IOSTANDARD LVCMOS33 [get_ports {seg[2]}] 88 | set_property PACKAGE_PIN V8 [get_ports {seg[3]}] 89 | set_property IOSTANDARD LVCMOS33 [get_ports {seg[3]}] 90 | set_property PACKAGE_PIN U5 [get_ports {seg[4]}] 91 | set_property IOSTANDARD LVCMOS33 [get_ports {seg[4]}] 92 | set_property PACKAGE_PIN V5 [get_ports {seg[5]}] 93 | set_property IOSTANDARD LVCMOS33 [get_ports {seg[5]}] 94 | set_property PACKAGE_PIN U7 [get_ports {seg[6]}] 95 | set_property IOSTANDARD LVCMOS33 [get_ports {seg[6]}] 96 | 97 | set_property PACKAGE_PIN V7 [get_ports dp] 98 | set_property IOSTANDARD LVCMOS33 [get_ports dp] 99 | 100 | set_property PACKAGE_PIN U2 [get_ports {an[0]}] 101 | set_property IOSTANDARD LVCMOS33 [get_ports {an[0]}] 102 | set_property PACKAGE_PIN U4 [get_ports {an[1]}] 103 | set_property IOSTANDARD LVCMOS33 [get_ports {an[1]}] 104 | set_property PACKAGE_PIN V4 [get_ports {an[2]}] 105 | set_property IOSTANDARD LVCMOS33 [get_ports {an[2]}] 106 | set_property PACKAGE_PIN W4 [get_ports {an[3]}] 107 | set_property IOSTANDARD LVCMOS33 [get_ports {an[3]}] 108 | 109 | 110 | ##Buttons 111 | set_property PACKAGE_PIN U18 [get_ports btnC] 112 | set_property IOSTANDARD LVCMOS33 [get_ports btnC] 113 | set_property PACKAGE_PIN T18 [get_ports btnU] 114 | set_property IOSTANDARD LVCMOS33 [get_ports btnU] 115 | set_property PACKAGE_PIN W19 [get_ports btnL] 116 | set_property IOSTANDARD LVCMOS33 [get_ports btnL] 117 | set_property PACKAGE_PIN T17 [get_ports btnR] 118 | set_property IOSTANDARD LVCMOS33 [get_ports btnR] 119 | set_property PACKAGE_PIN U17 [get_ports btnD] 120 | set_property IOSTANDARD LVCMOS33 [get_ports btnD] 121 | 122 | 123 | 124 | ##Pmod Header JA 125 | ##Sch name = JA1 126 | #set_property PACKAGE_PIN J1 [get_ports {JA[0]}] 127 | #set_property IOSTANDARD LVCMOS33 [get_ports {JA[0]}] 128 | ##Sch name = JA2 129 | #set_property PACKAGE_PIN L2 [get_ports {JA[1]}] 130 | #set_property IOSTANDARD LVCMOS33 [get_ports {JA[1]}] 131 | ##Sch name = JA3 132 | #set_property PACKAGE_PIN J2 [get_ports {JA[2]}] 133 | #set_property IOSTANDARD LVCMOS33 [get_ports {JA[2]}] 134 | ##Sch name = JA4 135 | #set_property PACKAGE_PIN G2 [get_ports {JA[3]}] 136 | #set_property IOSTANDARD LVCMOS33 [get_ports {JA[3]}] 137 | ##Sch name = JA7 138 | #set_property PACKAGE_PIN H1 [get_ports {JA[4]}] 139 | #set_property IOSTANDARD LVCMOS33 [get_ports {JA[4]}] 140 | ##Sch name = JA8 141 | #set_property PACKAGE_PIN K2 [get_ports {JA[5]}] 142 | #set_property IOSTANDARD LVCMOS33 [get_ports {JA[5]}] 143 | ##Sch name = JA9 144 | #set_property PACKAGE_PIN H2 [get_ports {JA[6]}] 145 | #set_property IOSTANDARD LVCMOS33 [get_ports {JA[6]}] 146 | ##Sch name = JA10 147 | #set_property PACKAGE_PIN G3 [get_ports {JA[7]}] 148 | #set_property IOSTANDARD LVCMOS33 [get_ports {JA[7]}] 149 | 150 | 151 | 152 | ##Pmod Header JB 153 | ##Sch name = JB1 154 | #set_property PACKAGE_PIN A14 [get_ports {JB[0]}] 155 | #set_property IOSTANDARD LVCMOS33 [get_ports {JB[0]}] 156 | ##Sch name = JB2 157 | #set_property PACKAGE_PIN A16 [get_ports {JB[1]}] 158 | #set_property IOSTANDARD LVCMOS33 [get_ports {JB[1]}] 159 | ##Sch name = JB3 160 | #set_property PACKAGE_PIN B15 [get_ports {JB[2]}] 161 | #set_property IOSTANDARD LVCMOS33 [get_ports {JB[2]}] 162 | ##Sch name = JB4 163 | #set_property PACKAGE_PIN B16 [get_ports {JB[3]}] 164 | #set_property IOSTANDARD LVCMOS33 [get_ports {JB[3]}] 165 | ##Sch name = JB7 166 | #set_property PACKAGE_PIN A15 [get_ports {JB[4]}] 167 | #set_property IOSTANDARD LVCMOS33 [get_ports {JB[4]}] 168 | ##Sch name = JB8 169 | #set_property PACKAGE_PIN A17 [get_ports {JB[5]}] 170 | #set_property IOSTANDARD LVCMOS33 [get_ports {JB[5]}] 171 | ##Sch name = JB9 172 | #set_property PACKAGE_PIN C15 [get_ports {JB[6]}] 173 | #set_property IOSTANDARD LVCMOS33 [get_ports {JB[6]}] 174 | ##Sch name = JB10 175 | #set_property PACKAGE_PIN C16 [get_ports {JB[7]}] 176 | #set_property IOSTANDARD LVCMOS33 [get_ports {JB[7]}] 177 | 178 | 179 | 180 | ##Pmod Header JC 181 | ##Sch name = JC1 182 | #set_property PACKAGE_PIN K17 [get_ports {JC[0]}] 183 | #set_property IOSTANDARD LVCMOS33 [get_ports {JC[0]}] 184 | ##Sch name = JC2 185 | #set_property PACKAGE_PIN M18 [get_ports {JC[1]}] 186 | #set_property IOSTANDARD LVCMOS33 [get_ports {JC[1]}] 187 | ##Sch name = JC3 188 | #set_property PACKAGE_PIN N17 [get_ports {JC[2]}] 189 | #set_property IOSTANDARD LVCMOS33 [get_ports {JC[2]}] 190 | ##Sch name = JC4 191 | #set_property PACKAGE_PIN P18 [get_ports {JC[3]}] 192 | #set_property IOSTANDARD LVCMOS33 [get_ports {JC[3]}] 193 | ##Sch name = JC7 194 | #set_property PACKAGE_PIN L17 [get_ports {JC[4]}] 195 | #set_property IOSTANDARD LVCMOS33 [get_ports {JC[4]}] 196 | ##Sch name = JC8 197 | #set_property PACKAGE_PIN M19 [get_ports {JC[5]}] 198 | #set_property IOSTANDARD LVCMOS33 [get_ports {JC[5]}] 199 | ##Sch name = JC9 200 | #set_property PACKAGE_PIN P17 [get_ports {JC[6]}] 201 | #set_property IOSTANDARD LVCMOS33 [get_ports {JC[6]}] 202 | ##Sch name = JC10 203 | #set_property PACKAGE_PIN R18 [get_ports {JC[7]}] 204 | #set_property IOSTANDARD LVCMOS33 [get_ports {JC[7]}] 205 | 206 | 207 | ##Pmod Header JXADC 208 | ##Sch name = XA1_P 209 | #set_property PACKAGE_PIN J3 [get_ports {JXADC[0]}] 210 | #set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[0]}] 211 | ##Sch name = XA2_P 212 | #set_property PACKAGE_PIN L3 [get_ports {JXADC[1]}] 213 | #set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[1]}] 214 | ##Sch name = XA3_P 215 | #set_property PACKAGE_PIN M2 [get_ports {JXADC[2]}] 216 | #set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[2]}] 217 | ##Sch name = XA4_P 218 | #set_property PACKAGE_PIN N2 [get_ports {JXADC[3]}] 219 | #set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[3]}] 220 | ##Sch name = XA1_N 221 | #set_property PACKAGE_PIN K3 [get_ports {JXADC[4]}] 222 | #set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[4]}] 223 | ##Sch name = XA2_N 224 | #set_property PACKAGE_PIN M3 [get_ports {JXADC[5]}] 225 | #set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[5]}] 226 | ##Sch name = XA3_N 227 | #set_property PACKAGE_PIN M1 [get_ports {JXADC[6]}] 228 | #set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[6]}] 229 | ##Sch name = XA4_N 230 | #set_property PACKAGE_PIN N1 [get_ports {JXADC[7]}] 231 | #set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[7]}] 232 | 233 | 234 | 235 | ##VGA Connector 236 | #set_property PACKAGE_PIN G19 [get_ports {vgaRed[0]}] 237 | #set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[0]}] 238 | #set_property PACKAGE_PIN H19 [get_ports {vgaRed[1]}] 239 | #set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[1]}] 240 | #set_property PACKAGE_PIN J19 [get_ports {vgaRed[2]}] 241 | #set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[2]}] 242 | #set_property PACKAGE_PIN N19 [get_ports {vgaRed[3]}] 243 | #set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[3]}] 244 | #set_property PACKAGE_PIN N18 [get_ports {vgaBlue[0]}] 245 | #set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[0]}] 246 | #set_property PACKAGE_PIN L18 [get_ports {vgaBlue[1]}] 247 | #set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[1]}] 248 | #set_property PACKAGE_PIN K18 [get_ports {vgaBlue[2]}] 249 | #set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[2]}] 250 | #set_property PACKAGE_PIN J18 [get_ports {vgaBlue[3]}] 251 | #set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[3]}] 252 | #set_property PACKAGE_PIN J17 [get_ports {vgaGreen[0]}] 253 | #set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[0]}] 254 | #set_property PACKAGE_PIN H17 [get_ports {vgaGreen[1]}] 255 | #set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[1]}] 256 | #set_property PACKAGE_PIN G17 [get_ports {vgaGreen[2]}] 257 | #set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[2]}] 258 | #set_property PACKAGE_PIN D17 [get_ports {vgaGreen[3]}] 259 | #set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[3]}] 260 | #set_property PACKAGE_PIN P19 [get_ports Hsync] 261 | #set_property IOSTANDARD LVCMOS33 [get_ports Hsync] 262 | #set_property PACKAGE_PIN R19 [get_ports Vsync] 263 | #set_property IOSTANDARD LVCMOS33 [get_ports Vsync] 264 | 265 | 266 | ##USB-RS232 Interface 267 | #set_property PACKAGE_PIN B18 [get_ports RsRx] 268 | #set_property IOSTANDARD LVCMOS33 [get_ports RsRx] 269 | #set_property PACKAGE_PIN A18 [get_ports RsTx] 270 | #set_property IOSTANDARD LVCMOS33 [get_ports RsTx] 271 | 272 | 273 | ##USB HID (PS/2) 274 | #set_property PACKAGE_PIN C17 [get_ports PS2Clk] 275 | #set_property IOSTANDARD LVCMOS33 [get_ports PS2Clk] 276 | #set_property PULLUP true [get_ports PS2Clk] 277 | #set_property PACKAGE_PIN B17 [get_ports PS2Data] 278 | #set_property IOSTANDARD LVCMOS33 [get_ports PS2Data] 279 | #set_property PULLUP true [get_ports PS2Data] 280 | 281 | 282 | ##Quad SPI Flash 283 | ##Note that CCLK_0 cannot be placed in 7 series devices. You can access it using the 284 | ##STARTUPE2 primitive. 285 | #set_property PACKAGE_PIN D18 [get_ports {QspiDB[0]}] 286 | #set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[0]}] 287 | #set_property PACKAGE_PIN D19 [get_ports {QspiDB[1]}] 288 | #set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[1]}] 289 | #set_property PACKAGE_PIN G18 [get_ports {QspiDB[2]}] 290 | #set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[2]}] 291 | #set_property PACKAGE_PIN F18 [get_ports {QspiDB[3]}] 292 | #set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[3]}] 293 | #set_property PACKAGE_PIN K19 [get_ports QspiCSn] 294 | #set_property IOSTANDARD LVCMOS33 [get_ports QspiCSn] 295 | 296 | -------------------------------------------------------------------------------- /Projects/Abacus/src/hdl/Adder_Subtractor.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 15:07:48 06/12/2014 7 | // Design Name: 8 | // Module Name: adder 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module adder( 22 | input [7:0] a, 23 | input [7:0] b, 24 | input clk, 25 | input cin, 26 | output reg [7:0] sum, 27 | output reg [7:0] diff, 28 | output reg cout 29 | 30 | ); 31 | 32 | reg [8:0] c; 33 | integer i; 34 | always @ (posedge clk)//a or b or cin) 35 | begin 36 | c[0]=cin; 37 | if (cin == 0) begin// addition 38 | for ( i=0; i<=7 ; i=i+1) 39 | begin 40 | sum[i]= a[i]^b[i]^c[i]; 41 | c[i+1]= (a[i]&b[i])|(a[i]&c[i])|(b[i]&c[i]); 42 | end 43 | end 44 | else if (cin == 1) begin// subtraction 45 | for ( i=0; i<8 ; i=i+1) 46 | begin 47 | diff[i]= a[i]^(~ b[i])^c[i]; 48 | c[i+1]= (a[i]&(~b[i]))|(a[i]&c[i])|((~b[i])&c[i]); 49 | end 50 | end 51 | cout=c[8]; 52 | end 53 | 54 | endmodule 55 | 56 | -------------------------------------------------------------------------------- /Projects/Abacus/src/hdl/Basys3_Abacus_Top.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: Digilent Inc. 4 | // Engineer: Varun Kondagunturi 5 | // 6 | // Create Date: 17:08:26 06/12/2014 7 | // Design Name: 8 | // Module Name: Abacus_Top_Module 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // 13 | // 14 | // Description: 15 | //This is the Top-Level Source file for the Abacus Project. 16 | //Slide switches provide two 8-bit binary inputs A and B. 17 | //Slide Switches [15 down to 8] is input A. 18 | //Slide Switches [7 down to 0] is input B. 19 | //Inputs from the Push Buttons ( btnU, btnD, btnR, btnL) will allow the user to select different arithmetic operations that will be computed on the inputs A and B. 20 | //btnU: Subtraction/Difference. Result will Scroll 21 | //When A>B, difference is positive. 22 | //When A 4) 42 | z[19:16] = z[19:16] + 3; 43 | if(z[23:20] > 4) 44 | z[23:20] = z[23:20] + 3; 45 | if(z[27:24] > 4) 46 | z[27:24] = z[27:24] + 3; 47 | if(z[31:28] > 4) 48 | z[31:28] = z[31:28] + 3; 49 | if(z[35:32] > 4) 50 | z[35:32] = z[35:32] + 3; 51 | 52 | z[35:1] = z[34:0]; 53 | 54 | //z[34:2] = z[33:1]; 55 | end 56 | bcdout1 = z[35:16];//20 bits 57 | end 58 | 59 | endmodule -------------------------------------------------------------------------------- /Projects/Abacus/src/hdl/Binary_to_BCD_B2_bcdout2.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 07/27/2014 11:48:22 PM 7 | // Design Name: 8 | // Module Name: BIN_DEC2 9 | // Project Name: 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | 23 | module BIN_DEC2( 24 | 25 | input [15:0] B2, 26 | output reg [19:0] bcdout2 27 | ); 28 | 29 | reg [35:0] z; 30 | integer i; 31 | 32 | always @(*) 33 | begin 34 | for(i = 0; i <= 35; i = i+1) 35 | z[i] = 0; 36 | z[18:3] = B2; // shift b 3 places left 37 | 38 | //for(i = 0; i <= 12; i = i+1) 39 | repeat(13) 40 | begin 41 | if(z[19:16] > 4) 42 | z[19:16] = z[19:16] + 3; 43 | if(z[23:20] > 4) 44 | z[23:20] = z[23:20] + 3; 45 | if(z[27:24] > 4) 46 | z[27:24] = z[27:24] + 3; 47 | if(z[31:28] > 4) 48 | z[31:28] = z[31:28] + 3; 49 | if(z[35:32] > 4) 50 | z[35:32] = z[35:32] + 3; 51 | 52 | z[35:1] = z[34:0]; 53 | 54 | //z[34:2] = z[33:1]; 55 | end 56 | bcdout2 = z[35:16];//20 bits 57 | end 58 | 59 | endmodule -------------------------------------------------------------------------------- /Projects/Abacus/src/hdl/Binary_to_BCD_B_bcdout.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 18:33:23 06/15/2014 7 | // Design Name: 8 | // Module Name: bin_to_decimal 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module bin_to_decimal( 22 | 23 | input [15:0] B, 24 | output reg [19:0] bcdout 25 | ); 26 | 27 | reg [35:0] z; 28 | integer i; 29 | 30 | always @(*) 31 | begin 32 | for(i = 0; i <= 35; i = i+1) 33 | z[i] = 0; 34 | z[18:3] = B; // shift b 3 places left 35 | 36 | //for(i = 0; i <= 12; i = i+1) 37 | repeat(13) 38 | begin 39 | if(z[19:16] > 4) 40 | z[19:16] = z[19:16] + 3; 41 | if(z[23:20] > 4) 42 | z[23:20] = z[23:20] + 3; 43 | if(z[27:24] > 4) 44 | z[27:24] = z[27:24] + 3; 45 | if(z[31:28] > 4) 46 | z[31:28] = z[31:28] + 3; 47 | if(z[35:32] > 4) 48 | z[35:32] = z[35:32] + 3; 49 | 50 | z[35:1] = z[34:0]; 51 | 52 | //z[34:2] = z[33:1]; 53 | end 54 | bcdout = z[35:16];//20 bits 55 | end 56 | 57 | endmodule 58 | -------------------------------------------------------------------------------- /Projects/Abacus/src/hdl/Display_QU.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 08/06/2014 01:08:23 PM 7 | // Design Name: 8 | // Module Name: seg_scroll_QU 9 | // Project Name: 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | 23 | module Seg_Scroll_QU( 24 | input clk, 25 | input clr, 26 | input [19:0] scroll_datain_QU, 27 | output [15:0] scroll_dataout_QU 28 | ); 29 | 30 | 31 | reg [26:0] q; 32 | reg [23:0] msg_array; 33 | 34 | always @(posedge clk_3 or posedge clr) 35 | 36 | begin 37 | 38 | if(clr==1) 39 | begin 40 | msg_array [19:0] <= scroll_datain_QU[19:0]; 41 | msg_array [23:20] <= 'hC; 42 | end 43 | else 44 | begin 45 | msg_array [19:0] <= msg_array[23:4]; 46 | msg_array [23:20] <= msg_array[3:0]; 47 | end 48 | end 49 | 50 | assign scroll_dataout_QU[15:0] = msg_array[15:0]; 51 | 52 | // 3 Hz scroll clk generator 53 | 54 | always @(posedge clk or posedge clr) 55 | begin 56 | if(clr==1) 57 | q<=0; 58 | else 59 | q<=q+1; 60 | end 61 | assign clk_3 = q[26]; 62 | 63 | 64 | 65 | endmodule -------------------------------------------------------------------------------- /Projects/Abacus/src/hdl/Display_REM.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 08/06/2014 01:08:09 PM 7 | // Design Name: 8 | // Module Name: seg_scroll_REM 9 | // Project Name: 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | 23 | module Seg_Scroll_REM( 24 | input clk, 25 | input clr, 26 | input [19:0] scroll_datain_REM, 27 | output [15:0] scroll_dataout_REM 28 | ); 29 | 30 | 31 | reg [26:0] q; 32 | reg [23:0] msg_array; 33 | 34 | always @(posedge clk_3 or posedge clr) 35 | 36 | begin 37 | 38 | if(clr==1) 39 | begin 40 | msg_array [19:0] <= scroll_datain_REM[19:0]; 41 | msg_array [23:20] <= 'hC; 42 | end 43 | else 44 | begin 45 | msg_array [19:0] <= msg_array[23:4]; 46 | msg_array [23:20] <= msg_array[3:0]; 47 | end 48 | end 49 | 50 | assign scroll_dataout_REM[15:0] = msg_array[15:0]; 51 | 52 | // 3 Hz scroll clk generator 53 | 54 | always @(posedge clk or posedge clr) 55 | begin 56 | if(clr==1) 57 | q<=0; 58 | else 59 | q<=q+1; 60 | end 61 | assign clk_3 = q[26]; 62 | 63 | 64 | 65 | endmodule -------------------------------------------------------------------------------- /Projects/Abacus/src/hdl/Divider.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 15:50:04 07/21/2014 7 | // Design Name: 8 | // Module Name: divider 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module divider( 22 | 23 | input [7:0] div, // dividend switch [15:8] 24 | input [7:0] dvr, // divisor switch [7:0] 25 | input clk, 26 | 27 | output [7:0] quotient, // quotient 28 | output [7:0] remainder // remainder 29 | 30 | ); 31 | 32 | integer i; 33 | //reg [7:0] r_d_diff; 34 | reg [7:0] diff; // remainder - divisor diff result 35 | //reg [8:0] c0; 36 | 37 | reg [7:0] qu;// quotient 38 | reg [7:0] rem;// remainder 39 | 40 | 41 | always @(posedge clk) begin 42 | 43 | //c0[0] = 1'b1; 44 | rem [7:0] = 8'b0; // assign reminader to all zeros initially 45 | qu [7:0] = div[7:0]; // place dividend in Quotient 46 | 47 | for (i=0;i<=7;i=i+1) begin 48 | //repeat (8) 49 | 50 | rem = rem<<1;// first iteration shift 51 | rem[0] = qu[7];// first iteration shift 52 | qu = qu<<1;// first iteration shift 53 | qu[0] = 1'b0;// first iteration shift 54 | 55 | if ( rem >= dvr) begin 56 | 57 | rem = rem-dvr; 58 | qu[0] = 1'b1; 59 | 60 | end 61 | 62 | 63 | end 64 | 65 | end 66 | 67 | assign remainder [7:0] = rem[7:0]; 68 | assign quotient [7:0] = qu[7:0]; 69 | 70 | 71 | endmodule 72 | -------------------------------------------------------------------------------- /Projects/Abacus/src/hdl/Seg_7_Display.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 16:52:53 06/12/2014 7 | // Design Name: 8 | // Module Name: seg7decimal 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module seg7decimal( 22 | 23 | input [15:0] x, 24 | input clk, 25 | input clr, 26 | output reg [6:0] a_to_g, 27 | output reg [3:0] an, 28 | output wire dp 29 | ); 30 | 31 | 32 | wire [1:0] s; 33 | reg [3:0] digit; 34 | wire [3:0] aen; 35 | reg [19:0] clkdiv; 36 | 37 | assign dp = 1; 38 | assign s = clkdiv[19:18]; 39 | assign aen = 4'b1111; // all turned off initially 40 | 41 | // quad 4to1 MUX. 42 | 43 | 44 | always @(posedge clk)// or posedge clr) 45 | 46 | case(s) 47 | 0:digit = x[3:0]; // s is 00 -->0 ; digit gets assigned 4 bit value assigned to x[3:0] 48 | 1:digit = x[7:4]; // s is 01 -->1 ; digit gets assigned 4 bit value assigned to x[7:4] 49 | 2:digit = x[11:8]; // s is 10 -->2 ; digit gets assigned 4 bit value assigned to x[11:8 50 | 3:digit = x[15:12]; // s is 11 -->3 ; digit gets assigned 4 bit value assigned to x[15:12] 51 | 52 | default:digit = x[3:0]; 53 | 54 | endcase 55 | 56 | //decoder or truth-table for 7a_to_g display values 57 | always @(*) 58 | 59 | case(digit) 60 | 61 | 62 | //////////<---MSB-LSB<--- 63 | //////////////gfedcba//////////////////////////////////////////// a 64 | 0:a_to_g = 7'b1000000;////0000 __ 65 | 1:a_to_g = 7'b1111001;////0001 f/ /b 66 | 2:a_to_g = 7'b0100100;////0010 g 67 | // __ 68 | 3:a_to_g = 7'b0110000;////0011 e / /c 69 | 4:a_to_g = 7'b0011001;////0100 __ 70 | 5:a_to_g = 7'b0010010;////0101 d 71 | 6:a_to_g = 7'b0000010;////0110 72 | 7:a_to_g = 7'b1111000;////0111 73 | 8:a_to_g = 7'b0000000;////1000 74 | 9:a_to_g = 7'b0010000;////1001 75 | 'hA:a_to_g = 7'b0111111; // dash-(g) 76 | 'hB:a_to_g = 7'b1111111; // all turned off 77 | 'hC:a_to_g = 7'b1110111; 78 | 79 | default: a_to_g = 7'b0000000; // U 80 | 81 | endcase 82 | 83 | 84 | always @(*)begin 85 | an=4'b1111; 86 | if(aen[s] == 1) 87 | an[s] = 0; 88 | end 89 | 90 | 91 | //clkdiv 92 | 93 | always @(posedge clk or posedge clr) begin 94 | if ( clr == 1) 95 | clkdiv <= 0; 96 | else 97 | clkdiv <= clkdiv+1; 98 | end 99 | 100 | 101 | endmodule 102 | -------------------------------------------------------------------------------- /Projects/Abacus/src/hdl/Segment_Scroll.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 14:41:32 06/24/2014 7 | // Design Name: 8 | // Module Name: seg_scroll 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | module seg_scroll( 23 | input clk, 24 | input clr, 25 | input [19:0] scroll_datain, 26 | output [15:0] scroll_dataout 27 | ); 28 | 29 | 30 | reg [26:0] q; 31 | reg [23:0] msg_array; 32 | 33 | always @(posedge clk_3 or posedge clr) 34 | 35 | begin 36 | 37 | if(clr==1) 38 | begin 39 | msg_array [19:0] <= scroll_datain[19:0]; 40 | msg_array [23:20] <= 'hC; 41 | end 42 | else 43 | begin 44 | msg_array [19:0] <= msg_array[23:4]; 45 | msg_array [23:20] <= msg_array[3:0]; 46 | end 47 | end 48 | 49 | assign scroll_dataout[15:0] = msg_array[15:0]; 50 | 51 | // 3 Hz scroll clk generator 52 | 53 | always @(posedge clk or posedge clr) 54 | begin 55 | if(clr==1) 56 | q<=0; 57 | else 58 | q<=q+1; 59 | end 60 | assign clk_3 = q[26]; 61 | 62 | 63 | 64 | endmodule 65 | -------------------------------------------------------------------------------- /Projects/Abacus/src/hdl/multi_4_4_pp0.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 10:38:22 06/26/2014 7 | // Design Name: 8 | // Module Name: multi_4_4 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module multi_4_4_pp0( 22 | input clk, 23 | //input clr, 24 | input [3:0] A0_3, 25 | input [3:0] B0_3, 26 | output reg [7:0] pp0 27 | ); 28 | 29 | reg [7:0] pv; 30 | reg [7:0] bp; 31 | integer i; 32 | 33 | 34 | always @(posedge clk)// or posedge clr) 35 | begin 36 | pv = 8'b00000000; 37 | bp = {4'b0000,B0_3}; 38 | for (i = 0; i<=3; i=i+1) 39 | begin 40 | if (A0_3[i] == 1) 41 | pv = pv+bp; 42 | bp={bp[6:0], 1'b0}; 43 | end 44 | pp0=pv; 45 | end 46 | 47 | endmodule 48 | -------------------------------------------------------------------------------- /Projects/Abacus/src/hdl/multi_4_4_pp1.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 12:01:33 06/26/2014 7 | // Design Name: 8 | // Module Name: multi_4_4_pp1 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module multi_4_4_pp1( 22 | input clk, 23 | //input clr, 24 | input [3:0] A4_7, 25 | input [3:0] B0_3, 26 | output reg [7:0] pp1 27 | ); 28 | 29 | reg [7:0] pv; 30 | reg [7:0] bp; 31 | integer i; 32 | 33 | always @(posedge clk)// or posedge clr) 34 | begin 35 | pv = 8'b00000000; 36 | bp = {4'b0000,B0_3}; 37 | for (i = 0; i<=3; i=i+1) 38 | begin 39 | if (A4_7[i] == 1) 40 | pv = pv+bp; 41 | bp={bp[6:0], 1'b0}; 42 | end 43 | pp1=pv; 44 | end 45 | 46 | 47 | endmodule 48 | -------------------------------------------------------------------------------- /Projects/Abacus/src/hdl/multi_4_4_pp2.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 12:03:40 06/26/2014 7 | // Design Name: 8 | // Module Name: multi_4_4_pp2 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module multi_4_4_pp2( 22 | input clk, 23 | //input clr, 24 | input [3:0] A0_3, 25 | input [3:0] B4_7, 26 | output reg [7:0] pp2 27 | ); 28 | 29 | reg [7:0] pv; 30 | reg [7:0] bp; 31 | integer i; 32 | 33 | always @(posedge clk)// or posedge clr) 34 | begin 35 | pv = 8'b00000000; 36 | bp = {4'b0000,B4_7}; 37 | for (i = 0; i<=3; i=i+1) 38 | begin 39 | if (A0_3[i] == 1) 40 | pv = pv+bp; 41 | bp={bp[6:0], 1'b0}; 42 | end 43 | pp2=pv; 44 | end 45 | 46 | 47 | endmodule 48 | 49 | -------------------------------------------------------------------------------- /Projects/Abacus/src/hdl/multi_4_4_pp3.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 12:14:47 06/26/2014 7 | // Design Name: 8 | // Module Name: multi_4_4_pp3 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module multi_4_4_pp3( 22 | input clk, 23 | //input clr, 24 | input [3:0] A4_7, 25 | input [3:0] B4_7, 26 | output reg [7:0] pp3 27 | ); 28 | 29 | reg [7:0] pv; 30 | reg [7:0] bp; 31 | integer i; 32 | 33 | always @(posedge clk)// or posedge clr) 34 | begin 35 | pv = 8'b00000000; 36 | bp = {4'b0000,B4_7}; 37 | for (i = 0; i<=3; i=i+1) 38 | begin 39 | if (A4_7[i] == 1) 40 | pv = pv+bp; 41 | bp={bp[6:0], 1'b0}; 42 | end 43 | pp3=pv; 44 | end 45 | 46 | 47 | endmodule 48 | -------------------------------------------------------------------------------- /Projects/GPIO/proj/_READ_ME_.txt: -------------------------------------------------------------------------------- 1 | In order to run the create_project script successfully, the folder must be in its initial state 2 | containing only the cleanup, create_project scripts, and this document. 3 | 4 | To restore the folder to its initial state, double-click the cleanup Windows Command Script. 5 | 6 | !!!!CAUTION!!!! 7 | 8 | Moving or copying the cleanup Windows Command Script can result in unintentional loss of data on your 9 | system. The script contains a short list of specific files to ignore once it is run, all other files 10 | and folders within its directory location will be ERASED. Use this only within the project folder as 11 | instructed. 12 | 13 | See material on the usage of demo projects at reference.digilentinc.com -------------------------------------------------------------------------------- /Projects/GPIO/proj/cleanup.cmd: -------------------------------------------------------------------------------- 1 | @echo off 2 | rem delete all files from subfolders 3 | for /d /r %%i in (*) do del /f /q %%i\* 4 | rem delete all subfolders 5 | for /d %%i in (*) do rd /S /Q %%i 6 | 7 | rem unmark read only from all files 8 | attrib -R .\* /S 9 | 10 | rem mark read only those we wish to keep 11 | attrib +R .\create_project.tcl 12 | attrib +R .\cleanup.sh 13 | attrib +R .\cleanup.cmd 14 | attrib +R .\.gitignore 15 | attrib +R .\_READ_ME_.txt 16 | 17 | rem delete all non read-only 18 | del /Q /A:-R .\* 19 | 20 | rem unmark read-only 21 | attrib -R .\* 22 | -------------------------------------------------------------------------------- /Projects/GPIO/proj/cleanup.sh: -------------------------------------------------------------------------------- 1 | # This script is useful for cleaning up the 'project' 2 | # directory of a Digilent Vivado-project git repository 3 | ### 4 | # Run the following command to change permissions of 5 | # this 'cleanup' file if needed: 6 | # chmod u+x cleanup.sh 7 | ### 8 | # Remove directories/subdirectories 9 | find . -mindepth 1 -type d -exec rm -rf {} + 10 | # Remove any other files than: 11 | find . -type f ! -name 'cleanup.sh' \ 12 | ! -name 'cleanup.cmd' \ 13 | ! -name 'create_project.tcl' \ 14 | ! -name '.gitignore' \ 15 | -exec rm -rf {} + 16 | -------------------------------------------------------------------------------- /Projects/GPIO/proj/create_project.tcl: -------------------------------------------------------------------------------- 1 | # Run this script to create the Vivado project files in the WORKING DIRECTORY 2 | # If ::create_path global variable is set, the project is created under that path instead of the working dir 3 | 4 | if {[info exists ::create_path]} { 5 | set dest_dir $::create_path 6 | } else { 7 | set dest_dir [pwd] 8 | } 9 | puts "INFO: Creating new project in $dest_dir" 10 | 11 | # Set the reference directory for source file relative paths (by default the value is script directory path) 12 | set proj_name "GPIO" 13 | 14 | # Set the reference directory for source file relative paths (by default the value is script directory path) 15 | set origin_dir ".." 16 | 17 | # Set the directory path for the original project from where this script was exported 18 | set orig_proj_dir "[file normalize "$origin_dir/proj"]" 19 | 20 | set src_dir $origin_dir/src 21 | set repo_dir $origin_dir/repo 22 | 23 | # Set the board part number 24 | set part_num "xc7a35tcpg236-1" 25 | 26 | # Create project 27 | create_project $proj_name $dest_dir 28 | 29 | # Set the directory path for the new project 30 | set proj_dir [get_property directory [current_project]] 31 | 32 | # Set project properties 33 | set obj [get_projects $proj_name] 34 | set_property "default_lib" "xil_defaultlib" $obj 35 | set_property "part" "$part_num" $obj 36 | set_property "simulator_language" "Mixed" $obj 37 | set_property "target_language" "VHDL" $obj 38 | 39 | # Create 'sources_1' fileset (if not found) 40 | if {[string equal [get_filesets -quiet sources_1] ""]} { 41 | create_fileset -srcset sources_1 42 | } 43 | 44 | # Create 'constrs_1' fileset (if not found) 45 | if {[string equal [get_filesets -quiet constrs_1] ""]} { 46 | create_fileset -constrset constrs_1 47 | } 48 | 49 | # Set IP repository paths 50 | set obj [get_filesets sources_1] 51 | set_property "ip_repo_paths" "[file normalize $repo_dir]" $obj 52 | 53 | # Add conventional sources 54 | add_files -quiet $src_dir/hdl 55 | 56 | # Add IPs 57 | add_files -quiet [glob -nocomplain ../src/ip/*/*.xci] 58 | 59 | # Add constraints 60 | add_files -fileset constrs_1 -quiet $src_dir/constraints 61 | 62 | # Refresh IP Repositories 63 | #update_ip_catalog 64 | 65 | # Create 'synth_1' run (if not found) 66 | if {[string equal [get_runs -quiet synth_1] ""]} { 67 | create_run -name synth_1 -part $part_num -flow {Vivado Synthesis 2014} -strategy "Flow_PerfOptimized_High" -constrset constrs_1 68 | } else { 69 | set_property strategy "Flow_PerfOptimized_High" [get_runs synth_1] 70 | set_property flow "Vivado Synthesis 2014" [get_runs synth_1] 71 | } 72 | set obj [get_runs synth_1] 73 | set_property "part" "$part_num" $obj 74 | set_property "steps.synth_design.args.fanout_limit" "400" $obj 75 | set_property "steps.synth_design.args.fsm_extraction" "one_hot" $obj 76 | set_property "steps.synth_design.args.keep_equivalent_registers" "1" $obj 77 | set_property "steps.synth_design.args.resource_sharing" "off" $obj 78 | set_property "steps.synth_design.args.no_lc" "1" $obj 79 | set_property "steps.synth_design.args.shreg_min_size" "5" $obj 80 | 81 | # set the current synth run 82 | current_run -synthesis [get_runs synth_1] 83 | 84 | # Create 'impl_1' run (if not found) 85 | if {[string equal [get_runs -quiet impl_1] ""]} { 86 | create_run -name impl_1 -part $part_num -flow {Vivado Implementation 2014} -strategy "Vivado Implementation Defaults" -constrset constrs_1 -parent_run synth_1 87 | } else { 88 | set_property strategy "Vivado Implementation Defaults" [get_runs impl_1] 89 | set_property flow "Vivado Implementation 2014" [get_runs impl_1] 90 | } 91 | set obj [get_runs impl_1] 92 | set_property "part" "$part_num" $obj 93 | set_property "steps.write_bitstream.args.bin_file" "1" $obj 94 | 95 | # set the current impl run 96 | current_run -implementation [get_runs impl_1] 97 | 98 | #puts "INFO: Project created:$proj_name" 99 | 100 | # Comment the following section, if there is no block design 101 | # Create block design 102 | #source $origin_dir/src/bd/bt_gpio.tcl 103 | 104 | # Generate the wrapper 105 | #set design_name [get_bd_designs] 106 | #make_wrapper -files [get_files $design_name.bd] -top -import 107 | 108 | #set obj [get_filesets sources_1] 109 | #set_property "top" "bt_gpio_top" $obj 110 | 111 | #puts "INFO: Block design created: $design_name.bd" 112 | -------------------------------------------------------------------------------- /Projects/GPIO/src/hdl/MouseCtl.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Digilent/Basys3/97c14a4f2f6d22047432c8752325a9aff83fa210/Projects/GPIO/src/hdl/MouseCtl.vhd -------------------------------------------------------------------------------- /Projects/GPIO/src/hdl/MouseDisplay.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Digilent/Basys3/97c14a4f2f6d22047432c8752325a9aff83fa210/Projects/GPIO/src/hdl/MouseDisplay.vhd -------------------------------------------------------------------------------- /Projects/GPIO/src/hdl/Ps2Interface.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Digilent/Basys3/97c14a4f2f6d22047432c8752325a9aff83fa210/Projects/GPIO/src/hdl/Ps2Interface.vhd -------------------------------------------------------------------------------- /Projects/GPIO/src/hdl/UART_TX_CTRL.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------------------- 2 | -- UART_TX_CTRL.vhd -- UART Data Transfer Component 3 | ---------------------------------------------------------------------------- 4 | -- Author: Sam Bobrowicz 5 | -- Copyright 2011 Digilent, Inc. 6 | ---------------------------------------------------------------------------- 7 | -- 8 | ---------------------------------------------------------------------------- 9 | -- This component may be used to transfer data over a UART device. It will 10 | -- serialize a byte of data and transmit it over a TXD line. The serialized 11 | -- data has the following characteristics: 12 | -- *9600 Baud Rate 13 | -- *8 data bits, LSB first 14 | -- *1 stop bit 15 | -- *no parity 16 | -- 17 | -- Port Descriptions: 18 | -- 19 | -- SEND - Used to trigger a send operation. The upper layer logic should 20 | -- set this signal high for a single clock cycle to trigger a 21 | -- send. When this signal is set high DATA must be valid . Should 22 | -- not be asserted unless READY is high. 23 | -- DATA - The parallel data to be sent. Must be valid the clock cycle 24 | -- that SEND has gone high. 25 | -- CLK - A 100 MHz clock is expected 26 | -- READY - This signal goes low once a send operation has begun and 27 | -- remains low until it has completed and the module is ready to 28 | -- send another byte. 29 | -- UART_TX - This signal should be routed to the appropriate TX pin of the 30 | -- external UART device. 31 | -- 32 | ---------------------------------------------------------------------------- 33 | -- 34 | ---------------------------------------------------------------------------- 35 | -- Revision History: 36 | -- 08/08/2011(SamB): Created using Xilinx Tools 13.2 37 | ---------------------------------------------------------------------------- 38 | library IEEE; 39 | use IEEE.STD_LOGIC_1164.ALL; 40 | use IEEE.std_logic_unsigned.all; 41 | 42 | entity UART_TX_CTRL is 43 | Port ( SEND : in STD_LOGIC; 44 | DATA : in STD_LOGIC_VECTOR (7 downto 0); 45 | CLK : in STD_LOGIC; 46 | READY : out STD_LOGIC; 47 | UART_TX : out STD_LOGIC); 48 | end UART_TX_CTRL; 49 | 50 | architecture Behavioral of UART_TX_CTRL is 51 | 52 | type TX_STATE_TYPE is (RDY, LOAD_BIT, SEND_BIT); 53 | 54 | constant BIT_TMR_MAX : std_logic_vector(13 downto 0) := "10100010110000"; --10416 = (round(100MHz / 9600)) - 1 55 | constant BIT_INDEX_MAX : natural := 10; 56 | 57 | --Counter that keeps track of the number of clock cycles the current bit has been held stable over the 58 | --UART TX line. It is used to signal when the ne 59 | signal bitTmr : std_logic_vector(13 downto 0) := (others => '0'); 60 | 61 | --combinatorial logic that goes high when bitTmr has counted to the proper value to ensure 62 | --a 9600 baud rate 63 | signal bitDone : std_logic; 64 | 65 | --Contains the index of the next bit in txData that needs to be transferred 66 | signal bitIndex : natural; 67 | 68 | --a register that holds the current data being sent over the UART TX line 69 | signal txBit : std_logic := '1'; 70 | 71 | --A register that contains the whole data packet to be sent, including start and stop bits. 72 | signal txData : std_logic_vector(9 downto 0); 73 | 74 | signal txState : TX_STATE_TYPE := RDY; 75 | 76 | begin 77 | 78 | --Next state logic 79 | next_txState_process : process (CLK) 80 | begin 81 | if (rising_edge(CLK)) then 82 | case txState is 83 | when RDY => 84 | if (SEND = '1') then 85 | txState <= LOAD_BIT; 86 | end if; 87 | when LOAD_BIT => 88 | txState <= SEND_BIT; 89 | when SEND_BIT => 90 | if (bitDone = '1') then 91 | if (bitIndex = BIT_INDEX_MAX) then 92 | txState <= RDY; 93 | else 94 | txState <= LOAD_BIT; 95 | end if; 96 | end if; 97 | when others=> --should never be reached 98 | txState <= RDY; 99 | end case; 100 | end if; 101 | end process; 102 | 103 | bit_timing_process : process (CLK) 104 | begin 105 | if (rising_edge(CLK)) then 106 | if (txState = RDY) then 107 | bitTmr <= (others => '0'); 108 | else 109 | if (bitDone = '1') then 110 | bitTmr <= (others => '0'); 111 | else 112 | bitTmr <= bitTmr + 1; 113 | end if; 114 | end if; 115 | end if; 116 | end process; 117 | 118 | bitDone <= '1' when (bitTmr = BIT_TMR_MAX) else 119 | '0'; 120 | 121 | bit_counting_process : process (CLK) 122 | begin 123 | if (rising_edge(CLK)) then 124 | if (txState = RDY) then 125 | bitIndex <= 0; 126 | elsif (txState = LOAD_BIT) then 127 | bitIndex <= bitIndex + 1; 128 | end if; 129 | end if; 130 | end process; 131 | 132 | tx_data_latch_process : process (CLK) 133 | begin 134 | if (rising_edge(CLK)) then 135 | if (SEND = '1') then 136 | txData <= '1' & DATA & '0'; 137 | end if; 138 | end if; 139 | end process; 140 | 141 | tx_bit_process : process (CLK) 142 | begin 143 | if (rising_edge(CLK)) then 144 | if (txState = RDY) then 145 | txBit <= '1'; 146 | elsif (txState = LOAD_BIT) then 147 | txBit <= txData(bitIndex); 148 | end if; 149 | end if; 150 | end process; 151 | 152 | UART_TX <= txBit; 153 | READY <= '1' when (txState = RDY) else 154 | '0'; 155 | 156 | end Behavioral; 157 | 158 | -------------------------------------------------------------------------------- /Projects/GPIO/src/hdl/clk_wiz_0.vhd: -------------------------------------------------------------------------------- 1 | -- file: clk_wiz_0.vhd 2 | -- 3 | -- (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. 4 | -- 5 | -- This file contains confidential and proprietary information 6 | -- of Xilinx, Inc. and is protected under U.S. and 7 | -- international copyright and other intellectual property 8 | -- laws. 9 | -- 10 | -- DISCLAIMER 11 | -- This disclaimer is not a license and does not grant any 12 | -- rights to the materials distributed herewith. Except as 13 | -- otherwise provided in a valid license issued to you by 14 | -- Xilinx, and to the maximum extent permitted by applicable 15 | -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 16 | -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 17 | -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 18 | -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 19 | -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 20 | -- (2) Xilinx shall not be liable (whether in contract or tort, 21 | -- including negligence, or under any other theory of 22 | -- liability) for any loss or damage of any kind or nature 23 | -- related to, arising under or in connection with these 24 | -- materials, including for any direct, or any indirect, 25 | -- special, incidental, or consequential loss or damage 26 | -- (including loss of data, profits, goodwill, or any type of 27 | -- loss or damage suffered as a result of any action brought 28 | -- by a third party) even if such damage or loss was 29 | -- reasonably foreseeable or Xilinx had been advised of the 30 | -- possibility of the same. 31 | -- 32 | -- CRITICAL APPLICATIONS 33 | -- Xilinx products are not designed or intended to be fail- 34 | -- safe, or for use in any application requiring fail-safe 35 | -- performance, such as life-support or safety devices or 36 | -- systems, Class III medical devices, nuclear facilities, 37 | -- applications related to the deployment of airbags, or any 38 | -- other applications that could lead to death, personal 39 | -- injury, or severe property or environmental damage 40 | -- (individually and collectively, "Critical 41 | -- Applications"). Customer assumes the sole risk and 42 | -- liability of any use of Xilinx products in Critical 43 | -- Applications, subject only to applicable laws and 44 | -- regulations governing limitations on product liability. 45 | -- 46 | -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 47 | -- PART OF THIS FILE AT ALL TIMES. 48 | -- 49 | ------------------------------------------------------------------------------ 50 | -- User entered comments 51 | ------------------------------------------------------------------------------ 52 | -- None 53 | -- 54 | ------------------------------------------------------------------------------ 55 | -- Output Output Phase Duty Cycle Pk-to-Pk Phase 56 | -- Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) 57 | ------------------------------------------------------------------------------ 58 | -- CLK_OUT1___108.000______0.000______50.0______127.691_____97.646 59 | -- 60 | ------------------------------------------------------------------------------ 61 | -- Input Clock Freq (MHz) Input Jitter (UI) 62 | ------------------------------------------------------------------------------ 63 | -- __primary_________100.000____________0.010 64 | 65 | library ieee; 66 | use ieee.std_logic_1164.all; 67 | use ieee.std_logic_unsigned.all; 68 | use ieee.std_logic_arith.all; 69 | use ieee.numeric_std.all; 70 | 71 | library unisim; 72 | use unisim.vcomponents.all; 73 | 74 | entity clk_wiz_0 is 75 | port 76 | (-- Clock in ports 77 | clk_in1 : in std_logic; 78 | -- Clock out ports 79 | clk_out1 : out std_logic 80 | ); 81 | end clk_wiz_0; 82 | 83 | architecture xilinx of clk_wiz_0 is 84 | attribute CORE_GENERATION_INFO : string; 85 | attribute CORE_GENERATION_INFO of xilinx : architecture is "clk_wiz_0,clk_wiz_v5_1,{component_name=clk_wiz_0,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=1,clkin1_period=10.0,clkin2_period=10.0,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}"; 86 | 87 | component clk_wiz_0_clk_wiz 88 | port 89 | (-- Clock in ports 90 | clk_in1 : in std_logic; 91 | -- Clock out ports 92 | clk_out1 : out std_logic 93 | ); 94 | end component; 95 | 96 | begin 97 | 98 | U0: clk_wiz_0_clk_wiz 99 | port map ( 100 | 101 | -- Clock in ports 102 | clk_in1 => clk_in1, 103 | -- Clock out ports 104 | clk_out1 => clk_out1 105 | ); 106 | 107 | end xilinx; 108 | 109 | -------------------------------------------------------------------------------- /Projects/GPIO/src/hdl/clk_wiz_0_clk_wiz.vhd: -------------------------------------------------------------------------------- 1 | -- file: clk_wiz_0_clk_wiz.vhd 2 | -- 3 | -- (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. 4 | -- 5 | -- This file contains confidential and proprietary information 6 | -- of Xilinx, Inc. and is protected under U.S. and 7 | -- international copyright and other intellectual property 8 | -- laws. 9 | -- 10 | -- DISCLAIMER 11 | -- This disclaimer is not a license and does not grant any 12 | -- rights to the materials distributed herewith. Except as 13 | -- otherwise provided in a valid license issued to you by 14 | -- Xilinx, and to the maximum extent permitted by applicable 15 | -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 16 | -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 17 | -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 18 | -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 19 | -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 20 | -- (2) Xilinx shall not be liable (whether in contract or tort, 21 | -- including negligence, or under any other theory of 22 | -- liability) for any loss or damage of any kind or nature 23 | -- related to, arising under or in connection with these 24 | -- materials, including for any direct, or any indirect, 25 | -- special, incidental, or consequential loss or damage 26 | -- (including loss of data, profits, goodwill, or any type of 27 | -- loss or damage suffered as a result of any action brought 28 | -- by a third party) even if such damage or loss was 29 | -- reasonably foreseeable or Xilinx had been advised of the 30 | -- possibility of the same. 31 | -- 32 | -- CRITICAL APPLICATIONS 33 | -- Xilinx products are not designed or intended to be fail- 34 | -- safe, or for use in any application requiring fail-safe 35 | -- performance, such as life-support or safety devices or 36 | -- systems, Class III medical devices, nuclear facilities, 37 | -- applications related to the deployment of airbags, or any 38 | -- other applications that could lead to death, personal 39 | -- injury, or severe property or environmental damage 40 | -- (individually and collectively, "Critical 41 | -- Applications"). Customer assumes the sole risk and 42 | -- liability of any use of Xilinx products in Critical 43 | -- Applications, subject only to applicable laws and 44 | -- regulations governing limitations on product liability. 45 | -- 46 | -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 47 | -- PART OF THIS FILE AT ALL TIMES. 48 | -- 49 | ------------------------------------------------------------------------------ 50 | -- User entered comments 51 | ------------------------------------------------------------------------------ 52 | -- None 53 | -- 54 | ------------------------------------------------------------------------------ 55 | -- Output Output Phase Duty Cycle Pk-to-Pk Phase 56 | -- Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) 57 | ------------------------------------------------------------------------------ 58 | -- CLK_OUT1___108.000______0.000______50.0______127.691_____97.646 59 | -- 60 | ------------------------------------------------------------------------------ 61 | -- Input Clock Freq (MHz) Input Jitter (UI) 62 | ------------------------------------------------------------------------------ 63 | -- __primary_________100.000____________0.010 64 | 65 | library ieee; 66 | use ieee.std_logic_1164.all; 67 | use ieee.std_logic_unsigned.all; 68 | use ieee.std_logic_arith.all; 69 | use ieee.numeric_std.all; 70 | 71 | library unisim; 72 | use unisim.vcomponents.all; 73 | 74 | entity clk_wiz_0_clk_wiz is 75 | port 76 | (-- Clock in ports 77 | clk_in1 : in std_logic; 78 | -- Clock out ports 79 | clk_out1 : out std_logic 80 | ); 81 | end clk_wiz_0_clk_wiz; 82 | 83 | architecture xilinx of clk_wiz_0_clk_wiz is 84 | -- Input clock buffering / unused connectors 85 | signal clk_in1_clk_wiz_0 : std_logic; 86 | -- Output clock buffering / unused connectors 87 | signal clkfbout_clk_wiz_0 : std_logic; 88 | signal clkfbout_buf_clk_wiz_0 : std_logic; 89 | signal clkfboutb_unused : std_logic; 90 | signal clk_out1_clk_wiz_0 : std_logic; 91 | signal clkout0b_unused : std_logic; 92 | signal clkout1_unused : std_logic; 93 | signal clkout1b_unused : std_logic; 94 | signal clkout2_unused : std_logic; 95 | signal clkout2b_unused : std_logic; 96 | signal clkout3_unused : std_logic; 97 | signal clkout3b_unused : std_logic; 98 | signal clkout4_unused : std_logic; 99 | signal clkout5_unused : std_logic; 100 | signal clkout6_unused : std_logic; 101 | -- Dynamic programming unused signals 102 | signal do_unused : std_logic_vector(15 downto 0); 103 | signal drdy_unused : std_logic; 104 | -- Dynamic phase shift unused signals 105 | signal psdone_unused : std_logic; 106 | signal locked_int : std_logic; 107 | -- Unused status signals 108 | signal clkfbstopped_unused : std_logic; 109 | signal clkinstopped_unused : std_logic; 110 | 111 | begin 112 | 113 | 114 | -- Input buffering 115 | -------------------------------------- 116 | clk_in1_clk_wiz_0 <= clk_in1; 117 | 118 | 119 | 120 | -- Clocking PRIMITIVE 121 | -------------------------------------- 122 | -- Instantiation of the MMCM PRIMITIVE 123 | -- * Unused inputs are tied off 124 | -- * Unused outputs are labeled unused 125 | mmcm_adv_inst : MMCME2_ADV 126 | generic map 127 | (BANDWIDTH => "OPTIMIZED", 128 | CLKOUT4_CASCADE => FALSE, 129 | COMPENSATION => "ZHOLD", 130 | STARTUP_WAIT => FALSE, 131 | DIVCLK_DIVIDE => 1, 132 | CLKFBOUT_MULT_F => 10.125, 133 | CLKFBOUT_PHASE => 0.000, 134 | CLKFBOUT_USE_FINE_PS => FALSE, 135 | CLKOUT0_DIVIDE_F => 9.375, 136 | CLKOUT0_PHASE => 0.000, 137 | CLKOUT0_DUTY_CYCLE => 0.500, 138 | CLKOUT0_USE_FINE_PS => FALSE, 139 | CLKIN1_PERIOD => 10.0, 140 | REF_JITTER1 => 0.010) 141 | port map 142 | -- Output clocks 143 | ( 144 | CLKFBOUT => clkfbout_clk_wiz_0, 145 | CLKFBOUTB => clkfboutb_unused, 146 | CLKOUT0 => clk_out1_clk_wiz_0, 147 | CLKOUT0B => clkout0b_unused, 148 | CLKOUT1 => clkout1_unused, 149 | CLKOUT1B => clkout1b_unused, 150 | CLKOUT2 => clkout2_unused, 151 | CLKOUT2B => clkout2b_unused, 152 | CLKOUT3 => clkout3_unused, 153 | CLKOUT3B => clkout3b_unused, 154 | CLKOUT4 => clkout4_unused, 155 | CLKOUT5 => clkout5_unused, 156 | CLKOUT6 => clkout6_unused, 157 | -- Input clock control 158 | CLKFBIN => clkfbout_buf_clk_wiz_0, 159 | CLKIN1 => clk_in1_clk_wiz_0, 160 | CLKIN2 => '0', 161 | -- Tied to always select the primary input clock 162 | CLKINSEL => '1', 163 | -- Ports for dynamic reconfiguration 164 | DADDR => (others => '0'), 165 | DCLK => '0', 166 | DEN => '0', 167 | DI => (others => '0'), 168 | DO => do_unused, 169 | DRDY => drdy_unused, 170 | DWE => '0', 171 | -- Ports for dynamic phase shift 172 | PSCLK => '0', 173 | PSEN => '0', 174 | PSINCDEC => '0', 175 | PSDONE => psdone_unused, 176 | -- Other control and status signals 177 | LOCKED => locked_int, 178 | CLKINSTOPPED => clkinstopped_unused, 179 | CLKFBSTOPPED => clkfbstopped_unused, 180 | PWRDWN => '0', 181 | RST => '0'); 182 | 183 | 184 | -- Output buffering 185 | ------------------------------------- 186 | 187 | clkf_buf : BUFG 188 | port map 189 | (O => clkfbout_buf_clk_wiz_0, 190 | I => clkfbout_clk_wiz_0); 191 | 192 | 193 | 194 | clkout1_buf : BUFG 195 | port map 196 | (O => clk_out1, 197 | I => clk_out1_clk_wiz_0); 198 | 199 | 200 | 201 | end xilinx; 202 | -------------------------------------------------------------------------------- /Projects/GPIO/src/hdl/debouncer.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------------------- 2 | -- debouncer.vhd -- Signal Debouncer 3 | ---------------------------------------------------------------------------- 4 | -- Author: Sam Bobrowicz 5 | -- Copyright 2011 Digilent, Inc. 6 | ---------------------------------------------------------------------------- 7 | -- 8 | ---------------------------------------------------------------------------- 9 | -- This component is used to debounce signals. It is designed to 10 | -- independently debounce a variable number of signals, the number of which 11 | -- are set using the PORT_WIDTH generic. Debouncing is done by only 12 | -- registering a change in a button state if it remains constant for 13 | -- the number of clocks determined by the DEBNC_CLOCKS generic. 14 | -- 15 | -- Generic Descriptions: 16 | -- 17 | -- PORT_WIDTH - The number of signals to debounce. determines the width 18 | -- of the SIGNAL_I and SIGNAL_O std_logic_vectors 19 | -- DEBNC_CLOCKS - The number of clocks (CLK_I) to wait before registering 20 | -- a change. 21 | -- 22 | -- Port Descriptions: 23 | -- 24 | -- SIGNAL_I - The input signals. A vector of width equal to PORT_WIDTH 25 | -- CLK_I - Input clock 26 | -- SIGNAL_O - The debounced signals. A vector of width equal to PORT_WIDTH 27 | -- 28 | ---------------------------------------------------------------------------- 29 | -- 30 | ---------------------------------------------------------------------------- 31 | -- Revision History: 32 | -- 08/08/2011(SamB): Created using Xilinx Tools 13.2 33 | -- 08/29/2013(SamB): Improved reuseability by using generics 34 | ---------------------------------------------------------------------------- 35 | 36 | library IEEE; 37 | use IEEE.STD_LOGIC_1164.ALL; 38 | use IEEE.std_logic_unsigned.all; 39 | USE IEEE.NUMERIC_STD.ALL; 40 | use IEEE.math_real.all; 41 | 42 | entity debouncer is 43 | Generic ( DEBNC_CLOCKS : INTEGER range 2 to (INTEGER'high) := 2**16; 44 | PORT_WIDTH : INTEGER range 1 to (INTEGER'high) := 5); 45 | Port ( SIGNAL_I : in STD_LOGIC_VECTOR ((PORT_WIDTH - 1) downto 0); 46 | CLK_I : in STD_LOGIC; 47 | SIGNAL_O : out STD_LOGIC_VECTOR ((PORT_WIDTH - 1) downto 0)); 48 | end debouncer; 49 | 50 | architecture Behavioral of debouncer is 51 | 52 | constant CNTR_WIDTH : integer := natural(ceil(LOG2(real(DEBNC_CLOCKS)))); 53 | constant CNTR_MAX : std_logic_vector((CNTR_WIDTH - 1) downto 0) := std_logic_vector(to_unsigned((DEBNC_CLOCKS - 1), CNTR_WIDTH)); 54 | type VECTOR_ARRAY_TYPE is array (integer range <>) of std_logic_vector((CNTR_WIDTH - 1) downto 0); 55 | 56 | signal sig_cntrs_ary : VECTOR_ARRAY_TYPE (0 to (PORT_WIDTH - 1)) := (others=>(others=>'0')); 57 | 58 | signal sig_out_reg : std_logic_vector((PORT_WIDTH - 1) downto 0) := (others => '0'); 59 | 60 | begin 61 | 62 | debounce_process : process (CLK_I) 63 | begin 64 | if (rising_edge(CLK_I)) then 65 | for index in 0 to (PORT_WIDTH - 1) loop 66 | if (sig_cntrs_ary(index) = CNTR_MAX) then 67 | sig_out_reg(index) <= not(sig_out_reg(index)); 68 | end if; 69 | end loop; 70 | end if; 71 | end process; 72 | 73 | counter_process : process (CLK_I) 74 | begin 75 | if (rising_edge(CLK_I)) then 76 | for index in 0 to (PORT_WIDTH - 1) loop 77 | 78 | if ((sig_out_reg(index) = '1') xor (SIGNAL_I(index) = '1')) then 79 | if (sig_cntrs_ary(index) = CNTR_MAX) then 80 | sig_cntrs_ary(index) <= (others => '0'); 81 | else 82 | sig_cntrs_ary(index) <= sig_cntrs_ary(index) + 1; 83 | end if; 84 | else 85 | sig_cntrs_ary(index) <= (others => '0'); 86 | end if; 87 | 88 | end loop; 89 | end if; 90 | end process; 91 | 92 | SIGNAL_O <= sig_out_reg; 93 | 94 | end Behavioral; 95 | 96 | -------------------------------------------------------------------------------- /Projects/GPIO/src/hdl/vga_ctrl.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------------------------- 2 | -- Company: 3 | -- Engineer: 4 | -- 5 | -- Create Date: 04/25/2014 02:10:40 PM 6 | -- Design Name: 7 | -- Module Name: vga_ctrl - Behavioral 8 | -- Project Name: 9 | -- Target Devices: 10 | -- Tool Versions: 11 | -- Description: 12 | -- 13 | -- Dependencies: 14 | -- 15 | -- Revision: 16 | -- Revision 0.01 - File Created 17 | -- Additional Comments: 18 | -- 19 | ---------------------------------------------------------------------------------- 20 | 21 | 22 | library IEEE; 23 | use IEEE.STD_LOGIC_1164.ALL; 24 | use IEEE.STD_LOGIC_ARITH.ALL; 25 | use IEEE.std_logic_unsigned.all; 26 | use ieee.math_real.all; 27 | 28 | 29 | -- Uncomment the following library declaration if using 30 | -- arithmetic functions with Signed or Unsigned values 31 | --use IEEE.NUMERIC_STD.ALL; 32 | 33 | -- Uncomment the following library declaration if instantiating 34 | -- any Xilinx leaf cells in this code. 35 | --library UNISIM; 36 | --use UNISIM.VComponents.all; 37 | 38 | entity vga_ctrl is 39 | Port ( CLK_I : in STD_LOGIC; 40 | VGA_HS_O : out STD_LOGIC; 41 | VGA_VS_O : out STD_LOGIC; 42 | VGA_RED_O : out STD_LOGIC_VECTOR (3 downto 0); 43 | VGA_BLUE_O : out STD_LOGIC_VECTOR (3 downto 0); 44 | VGA_GREEN_O : out STD_LOGIC_VECTOR (3 downto 0); 45 | PS2_CLK : inout STD_LOGIC; 46 | PS2_DATA : inout STD_LOGIC 47 | ); 48 | end vga_ctrl; 49 | 50 | architecture Behavioral of vga_ctrl is 51 | 52 | COMPONENT MouseCtl 53 | GENERIC 54 | ( 55 | SYSCLK_FREQUENCY_HZ : integer := 100000000; 56 | CHECK_PERIOD_MS : integer := 500; 57 | TIMEOUT_PERIOD_MS : integer := 100 58 | ); 59 | PORT( 60 | clk : IN std_logic; 61 | rst : IN std_logic; 62 | value : IN std_logic_vector(11 downto 0); 63 | setx : IN std_logic; 64 | sety : IN std_logic; 65 | setmax_x : IN std_logic; 66 | setmax_y : IN std_logic; 67 | ps2_clk : INOUT std_logic; 68 | ps2_data : INOUT std_logic; 69 | xpos : OUT std_logic_vector(11 downto 0); 70 | ypos : OUT std_logic_vector(11 downto 0); 71 | zpos : OUT std_logic_vector(3 downto 0); 72 | left : OUT std_logic; 73 | middle : OUT std_logic; 74 | right : OUT std_logic; 75 | new_event : OUT std_logic 76 | ); 77 | END COMPONENT; 78 | 79 | COMPONENT MouseDisplay 80 | PORT( 81 | pixel_clk : IN std_logic; 82 | xpos : IN std_logic_vector(11 downto 0); 83 | ypos : IN std_logic_vector(11 downto 0); 84 | hcount : IN std_logic_vector(11 downto 0); 85 | vcount : IN std_logic_vector(11 downto 0); 86 | enable_mouse_display_out : OUT std_logic; 87 | red_out : OUT std_logic_vector(3 downto 0); 88 | green_out : OUT std_logic_vector(3 downto 0); 89 | blue_out : OUT std_logic_vector(3 downto 0) 90 | ); 91 | END COMPONENT; 92 | 93 | component clk_wiz_0 94 | port 95 | (-- Clock in ports 96 | clk_in1 : in std_logic; 97 | -- Clock out ports 98 | clk_out1 : out std_logic 99 | ); 100 | end component; 101 | 102 | --***1280x1024@60Hz***-- 103 | constant FRAME_WIDTH : natural := 1280; 104 | constant FRAME_HEIGHT : natural := 1024; 105 | 106 | constant H_FP : natural := 48; --H front porch width (pixels) 107 | constant H_PW : natural := 112; --H sync pulse width (pixels) 108 | constant H_MAX : natural := 1688; --H total period (pixels) 109 | 110 | constant V_FP : natural := 1; --V front porch width (lines) 111 | constant V_PW : natural := 3; --V sync pulse width (lines) 112 | constant V_MAX : natural := 1066; --V total period (lines) 113 | 114 | constant H_POL : std_logic := '1'; 115 | constant V_POL : std_logic := '1'; 116 | 117 | ------------------------------------------------------------------------- 118 | 119 | -- VGA Controller specific signals: Counters, Sync, R, G, B 120 | 121 | ------------------------------------------------------------------------- 122 | -- Pixel clock, in this case 108 MHz 123 | signal pxl_clk : std_logic; 124 | -- The active signal is used to signal the active region of the screen (when not blank) 125 | signal active : std_logic; 126 | 127 | -- Horizontal and Vertical counters 128 | signal h_cntr_reg : std_logic_vector(11 downto 0) := (others =>'0'); 129 | signal v_cntr_reg : std_logic_vector(11 downto 0) := (others =>'0'); 130 | 131 | -- Pipe Horizontal and Vertical Counters 132 | signal h_cntr_reg_dly : std_logic_vector(11 downto 0) := (others => '0'); 133 | signal v_cntr_reg_dly : std_logic_vector(11 downto 0) := (others => '0'); 134 | 135 | -- Horizontal and Vertical Sync 136 | signal h_sync_reg : std_logic := not(H_POL); 137 | signal v_sync_reg : std_logic := not(V_POL); 138 | -- Pipe Horizontal and Vertical Sync 139 | signal h_sync_reg_dly : std_logic := not(H_POL); 140 | signal v_sync_reg_dly : std_logic := not(V_POL); 141 | 142 | -- VGA R, G and B signals coming from the main multiplexers 143 | signal vga_red_cmb : std_logic_vector(3 downto 0); 144 | signal vga_green_cmb : std_logic_vector(3 downto 0); 145 | signal vga_blue_cmb : std_logic_vector(3 downto 0); 146 | --The main VGA R, G and B signals, validated by active 147 | signal vga_red : std_logic_vector(3 downto 0); 148 | signal vga_green : std_logic_vector(3 downto 0); 149 | signal vga_blue : std_logic_vector(3 downto 0); 150 | -- Register VGA R, G and B signals 151 | signal vga_red_reg : std_logic_vector(3 downto 0) := (others =>'0'); 152 | signal vga_green_reg : std_logic_vector(3 downto 0) := (others =>'0'); 153 | signal vga_blue_reg : std_logic_vector(3 downto 0) := (others =>'0'); 154 | 155 | ------------------------------------------------------------------------- 156 | --Mouse pointer signals 157 | ------------------------------------------------------------------------- 158 | 159 | -- Mouse data signals 160 | signal MOUSE_X_POS: std_logic_vector (11 downto 0); 161 | signal MOUSE_Y_POS: std_logic_vector (11 downto 0); 162 | signal MOUSE_X_POS_REG: std_logic_vector (11 downto 0); 163 | signal MOUSE_Y_POS_REG: std_logic_vector (11 downto 0); 164 | 165 | -- Mouse cursor display signals 166 | signal mouse_cursor_red : std_logic_vector (3 downto 0) := (others => '0'); 167 | signal mouse_cursor_blue : std_logic_vector (3 downto 0) := (others => '0'); 168 | signal mouse_cursor_green : std_logic_vector (3 downto 0) := (others => '0'); 169 | -- Mouse cursor enable display signals 170 | signal enable_mouse_display: std_logic; 171 | -- Registered Mouse cursor display signals 172 | signal mouse_cursor_red_dly : std_logic_vector (3 downto 0) := (others => '0'); 173 | signal mouse_cursor_blue_dly : std_logic_vector (3 downto 0) := (others => '0'); 174 | signal mouse_cursor_green_dly : std_logic_vector (3 downto 0) := (others => '0'); 175 | -- Registered Mouse cursor enable display signals 176 | signal enable_mouse_display_dly : std_logic; 177 | 178 | ----------------------------------------------------------- 179 | -- Signals for generating the background (moving colorbar) 180 | ----------------------------------------------------------- 181 | signal cntDyn : integer range 0 to 2**28-1; -- counter for generating the colorbar 182 | signal intHcnt : integer range 0 to H_MAX - 1; 183 | signal intVcnt : integer range 0 to V_MAX - 1; 184 | -- Colorbar red, greeen and blue signals 185 | signal bg_red : std_logic_vector(3 downto 0); 186 | signal bg_blue : std_logic_vector(3 downto 0); 187 | signal bg_green : std_logic_vector(3 downto 0); 188 | -- Pipe the colorbar red, green and blue signals 189 | signal bg_red_dly : std_logic_vector(3 downto 0) := (others => '0'); 190 | signal bg_green_dly : std_logic_vector(3 downto 0) := (others => '0'); 191 | signal bg_blue_dly : std_logic_vector(3 downto 0) := (others => '0'); 192 | 193 | 194 | begin 195 | 196 | 197 | clk_wiz_0_inst : clk_wiz_0 198 | port map 199 | ( 200 | clk_in1 => CLK_I, 201 | clk_out1 => pxl_clk); 202 | 203 | 204 | ---------------------------------------------------------------------------------- 205 | -- Mouse Controller 206 | ---------------------------------------------------------------------------------- 207 | Inst_MouseCtl: MouseCtl 208 | GENERIC MAP 209 | ( 210 | SYSCLK_FREQUENCY_HZ => 108000000, 211 | CHECK_PERIOD_MS => 500, 212 | TIMEOUT_PERIOD_MS => 100 213 | ) 214 | PORT MAP 215 | ( 216 | clk => pxl_clk, 217 | rst => '0', 218 | xpos => MOUSE_X_POS, 219 | ypos => MOUSE_Y_POS, 220 | zpos => open, 221 | left => open, 222 | middle => open, 223 | right => open, 224 | new_event => open, 225 | value => x"000", 226 | setx => '0', 227 | sety => '0', 228 | setmax_x => '0', 229 | setmax_y => '0', 230 | ps2_clk => PS2_CLK, 231 | ps2_data => PS2_DATA 232 | ); 233 | 234 | --------------------------------------------------------------- 235 | 236 | -- Generate Horizontal, Vertical counters and the Sync signals 237 | 238 | --------------------------------------------------------------- 239 | -- Horizontal counter 240 | process (pxl_clk) 241 | begin 242 | if (rising_edge(pxl_clk)) then 243 | if (h_cntr_reg = (H_MAX - 1)) then 244 | h_cntr_reg <= (others =>'0'); 245 | else 246 | h_cntr_reg <= h_cntr_reg + 1; 247 | end if; 248 | end if; 249 | end process; 250 | -- Vertical counter 251 | process (pxl_clk) 252 | begin 253 | if (rising_edge(pxl_clk)) then 254 | if ((h_cntr_reg = (H_MAX - 1)) and (v_cntr_reg = (V_MAX - 1))) then 255 | v_cntr_reg <= (others =>'0'); 256 | elsif (h_cntr_reg = (H_MAX - 1)) then 257 | v_cntr_reg <= v_cntr_reg + 1; 258 | end if; 259 | end if; 260 | end process; 261 | -- Horizontal sync 262 | process (pxl_clk) 263 | begin 264 | if (rising_edge(pxl_clk)) then 265 | if (h_cntr_reg >= (H_FP + FRAME_WIDTH - 1)) and (h_cntr_reg < (H_FP + FRAME_WIDTH + H_PW - 1)) then 266 | h_sync_reg <= H_POL; 267 | else 268 | h_sync_reg <= not(H_POL); 269 | end if; 270 | end if; 271 | end process; 272 | -- Vertical sync 273 | process (pxl_clk) 274 | begin 275 | if (rising_edge(pxl_clk)) then 276 | if (v_cntr_reg >= (V_FP + FRAME_HEIGHT - 1)) and (v_cntr_reg < (V_FP + FRAME_HEIGHT + V_PW - 1)) then 277 | v_sync_reg <= V_POL; 278 | else 279 | v_sync_reg <= not(V_POL); 280 | end if; 281 | end if; 282 | end process; 283 | 284 | -------------------- 285 | 286 | -- The active 287 | 288 | -------------------- 289 | -- active signal 290 | active <= '1' when h_cntr_reg_dly < FRAME_WIDTH and v_cntr_reg_dly < FRAME_HEIGHT 291 | else '0'; 292 | 293 | 294 | -------------------- 295 | 296 | -- Register Inputs 297 | 298 | -------------------- 299 | register_inputs: process (pxl_clk) 300 | begin 301 | if (rising_edge(pxl_clk)) then 302 | if v_sync_reg = V_POL then 303 | MOUSE_X_POS_REG <= MOUSE_X_POS; 304 | MOUSE_Y_POS_REG <= MOUSE_Y_POS; 305 | end if; 306 | end if; 307 | end process register_inputs; 308 | --------------------------------------- 309 | 310 | -- Generate moving colorbar background 311 | 312 | --------------------------------------- 313 | 314 | process(pxl_clk) 315 | begin 316 | if(rising_edge(pxl_clk)) then 317 | cntdyn <= cntdyn + 1; 318 | end if; 319 | end process; 320 | 321 | intHcnt <= conv_integer(h_cntr_reg); 322 | intVcnt <= conv_integer(v_cntr_reg); 323 | 324 | bg_red <= conv_std_logic_vector((-intvcnt - inthcnt - cntDyn/2**20),8)(7 downto 4); 325 | bg_green <= conv_std_logic_vector((inthcnt - cntDyn/2**20),8)(7 downto 4); 326 | bg_blue <= conv_std_logic_vector((intvcnt - cntDyn/2**20),8)(7 downto 4); 327 | 328 | 329 | ---------------------------------- 330 | 331 | -- Mouse Cursor display instance 332 | 333 | ---------------------------------- 334 | Inst_MouseDisplay: MouseDisplay 335 | PORT MAP 336 | ( 337 | pixel_clk => pxl_clk, 338 | xpos => MOUSE_X_POS_REG, 339 | ypos => MOUSE_Y_POS_REG, 340 | hcount => h_cntr_reg, 341 | vcount => v_cntr_reg, 342 | enable_mouse_display_out => enable_mouse_display, 343 | red_out => mouse_cursor_red, 344 | green_out => mouse_cursor_green, 345 | blue_out => mouse_cursor_blue 346 | ); 347 | 348 | --------------------------------------------------------------------------------------------------- 349 | 350 | -- Register Outputs coming from the displaying components and the horizontal and vertical counters 351 | 352 | --------------------------------------------------------------------------------------------------- 353 | process (pxl_clk) 354 | begin 355 | if (rising_edge(pxl_clk)) then 356 | 357 | bg_red_dly <= bg_red; 358 | bg_green_dly <= bg_green; 359 | bg_blue_dly <= bg_blue; 360 | 361 | mouse_cursor_red_dly <= mouse_cursor_red; 362 | mouse_cursor_blue_dly <= mouse_cursor_blue; 363 | mouse_cursor_green_dly <= mouse_cursor_green; 364 | 365 | enable_mouse_display_dly <= enable_mouse_display; 366 | 367 | h_cntr_reg_dly <= h_cntr_reg; 368 | v_cntr_reg_dly <= v_cntr_reg; 369 | 370 | end if; 371 | end process; 372 | 373 | ---------------------------------- 374 | 375 | -- VGA Output Muxing 376 | 377 | ---------------------------------- 378 | 379 | vga_red <= mouse_cursor_red_dly when enable_mouse_display_dly = '1' else 380 | bg_red_dly; 381 | vga_green <= mouse_cursor_green_dly when enable_mouse_display_dly = '1' else 382 | bg_green_dly; 383 | vga_blue <= mouse_cursor_blue_dly when enable_mouse_display_dly = '1' else 384 | bg_blue_dly; 385 | 386 | ------------------------------------------------------------ 387 | -- Turn Off VGA RBG Signals if outside of the active screen 388 | -- Make a 4-bit AND logic with the R, G and B signals 389 | ------------------------------------------------------------ 390 | vga_red_cmb <= (active & active & active & active) and vga_red; 391 | vga_green_cmb <= (active & active & active & active) and vga_green; 392 | vga_blue_cmb <= (active & active & active & active) and vga_blue; 393 | 394 | 395 | -- Register Outputs 396 | process (pxl_clk) 397 | begin 398 | if (rising_edge(pxl_clk)) then 399 | 400 | v_sync_reg_dly <= v_sync_reg; 401 | h_sync_reg_dly <= h_sync_reg; 402 | vga_red_reg <= vga_red_cmb; 403 | vga_green_reg <= vga_green_cmb; 404 | vga_blue_reg <= vga_blue_cmb; 405 | end if; 406 | end process; 407 | 408 | -- Assign outputs 409 | VGA_HS_O <= h_sync_reg_dly; 410 | VGA_VS_O <= v_sync_reg_dly; 411 | VGA_RED_O <= vga_red_reg; 412 | VGA_GREEN_O <= vga_green_reg; 413 | VGA_BLUE_O <= vga_blue_reg; 414 | 415 | end Behavioral; 416 | -------------------------------------------------------------------------------- /Projects/Keyboard/proj/_READ_ME_.txt: -------------------------------------------------------------------------------- 1 | In order to run the create_project script successfully, the folder must be in its initial state 2 | containing only the cleanup, create_project scripts, and this document. 3 | 4 | To restore the folder to its initial state, double-click the cleanup Windows Command Script. 5 | 6 | !!!!CAUTION!!!! 7 | 8 | Moving or copying the cleanup Windows Command Script can result in unintentional loss of data on your 9 | system. The script contains a short list of specific files to ignore once it is run, all other files 10 | and folders within its directory location will be ERASED. Use this only within the project folder as 11 | instructed. 12 | 13 | See material on the usage of demo projects at reference.digilentinc.com -------------------------------------------------------------------------------- /Projects/Keyboard/proj/cleanup.cmd: -------------------------------------------------------------------------------- 1 | @echo off 2 | rem delete all files from subfolders 3 | for /d /r %%i in (*) do del /f /q %%i\* 4 | rem delete all subfolders 5 | for /d %%i in (*) do rd /S /Q %%i 6 | 7 | rem unmark read only from all files 8 | attrib -R .\* /S 9 | 10 | rem mark read only those we wish to keep 11 | attrib +R .\create_project.tcl 12 | attrib +R .\cleanup.sh 13 | attrib +R .\cleanup.cmd 14 | attrib +R .\.gitignore 15 | attrib +R .\_READ_ME_.txt 16 | 17 | rem delete all non read-only 18 | del /Q /A:-R .\* 19 | 20 | rem unmark read-only 21 | attrib -R .\* 22 | -------------------------------------------------------------------------------- /Projects/Keyboard/proj/cleanup.sh: -------------------------------------------------------------------------------- 1 | # This script is useful for cleaning up the 'project' 2 | # directory of a Digilent Vivado-project git repository 3 | ### 4 | # Run the following command to change permissions of 5 | # this 'cleanup' file if needed: 6 | # chmod u+x cleanup.sh 7 | ### 8 | # Remove directories/subdirectories 9 | find . -mindepth 1 -type d -exec rm -rf {} + 10 | # Remove any other files than: 11 | find . -type f ! -name 'cleanup.sh' \ 12 | ! -name 'cleanup.cmd' \ 13 | ! -name 'create_project.tcl' \ 14 | ! -name '.gitignore' \ 15 | -exec rm -rf {} + 16 | -------------------------------------------------------------------------------- /Projects/Keyboard/proj/create_project.tcl: -------------------------------------------------------------------------------- 1 | # Run this script to create the Vivado project files in the WORKING DIRECTORY 2 | # If ::create_path global variable is set, the project is created under that path instead of the working dir 3 | 4 | if {[info exists ::create_path]} { 5 | set dest_dir $::create_path 6 | } else { 7 | set dest_dir [pwd] 8 | } 9 | puts "INFO: Creating new project in $dest_dir" 10 | 11 | # Set the reference directory for source file relative paths (by default the value is script directory path) 12 | set proj_name "Keyboard" 13 | 14 | # Set the reference directory for source file relative paths (by default the value is script directory path) 15 | set origin_dir ".." 16 | 17 | # Set the directory path for the original project from where this script was exported 18 | set orig_proj_dir "[file normalize "$origin_dir/proj"]" 19 | 20 | set src_dir $origin_dir/src 21 | set repo_dir $origin_dir/repo 22 | 23 | # Set the board part number 24 | set part_num "xc7a35tcpg236-1" 25 | 26 | # Create project 27 | create_project $proj_name $dest_dir 28 | 29 | # Set the directory path for the new project 30 | set proj_dir [get_property directory [current_project]] 31 | 32 | # Set project properties 33 | set obj [get_projects $proj_name] 34 | set_property "default_lib" "xil_defaultlib" $obj 35 | set_property "part" "$part_num" $obj 36 | set_property "simulator_language" "Mixed" $obj 37 | set_property "target_language" "VHDL" $obj 38 | 39 | # Create 'sources_1' fileset (if not found) 40 | if {[string equal [get_filesets -quiet sources_1] ""]} { 41 | create_fileset -srcset sources_1 42 | } 43 | 44 | # Create 'constrs_1' fileset (if not found) 45 | if {[string equal [get_filesets -quiet constrs_1] ""]} { 46 | create_fileset -constrset constrs_1 47 | } 48 | 49 | # Set IP repository paths 50 | set obj [get_filesets sources_1] 51 | set_property "ip_repo_paths" "[file normalize $repo_dir]" $obj 52 | 53 | # Add conventional sources 54 | add_files -quiet $src_dir/hdl 55 | 56 | # Add IPs 57 | add_files -quiet [glob -nocomplain ../src/ip/*/*.xci] 58 | 59 | # Add constraints 60 | add_files -fileset constrs_1 -quiet $src_dir/constraints 61 | 62 | # Refresh IP Repositories 63 | update_ip_catalog 64 | 65 | # Create 'synth_1' run (if not found) 66 | if {[string equal [get_runs -quiet synth_1] ""]} { 67 | create_run -name synth_1 -part $part_num -flow {Vivado Synthesis 2014} -strategy "Flow_PerfOptimized_High" -constrset constrs_1 68 | } else { 69 | set_property strategy "Flow_PerfOptimized_High" [get_runs synth_1] 70 | set_property flow "Vivado Synthesis 2014" [get_runs synth_1] 71 | } 72 | set obj [get_runs synth_1] 73 | set_property "part" "$part_num" $obj 74 | set_property "steps.synth_design.args.fanout_limit" "400" $obj 75 | set_property "steps.synth_design.args.fsm_extraction" "one_hot" $obj 76 | set_property "steps.synth_design.args.keep_equivalent_registers" "1" $obj 77 | set_property "steps.synth_design.args.resource_sharing" "off" $obj 78 | set_property "steps.synth_design.args.no_lc" "1" $obj 79 | set_property "steps.synth_design.args.shreg_min_size" "5" $obj 80 | 81 | # set the current synth run 82 | current_run -synthesis [get_runs synth_1] 83 | 84 | # Create 'impl_1' run (if not found) 85 | if {[string equal [get_runs -quiet impl_1] ""]} { 86 | create_run -name impl_1 -part $part_num -flow {Vivado Implementation 2014} -strategy "Vivado Implementation Defaults" -constrset constrs_1 -parent_run synth_1 87 | } else { 88 | set_property strategy "Vivado Implementation Defaults" [get_runs impl_1] 89 | set_property flow "Vivado Implementation 2014" [get_runs impl_1] 90 | } 91 | set obj [get_runs impl_1] 92 | set_property "part" "$part_num" $obj 93 | set_property "steps.write_bitstream.args.bin_file" "1" $obj 94 | 95 | # set the current impl run 96 | current_run -implementation [get_runs impl_1] 97 | 98 | puts "INFO: Project created:$proj_name" 99 | 100 | # Comment the following section, if there is no block design 101 | # Create block design 102 | #source $origin_dir/src/bd/bt_gpio.tcl 103 | 104 | # Generate the wrapper 105 | #set design_name [get_bd_designs] 106 | #make_wrapper -files [get_files $design_name.bd] -top -import 107 | 108 | #set obj [get_filesets sources_1] 109 | #set_property "top" "bt_gpio_top" $obj 110 | 111 | #puts "INFO: Block design created: $design_name.bd" 112 | -------------------------------------------------------------------------------- /Projects/Keyboard/src/constraints/Basys3_Master.xdc: -------------------------------------------------------------------------------- 1 | ## This file is a general .xdc for the Basys3 rev B board 2 | ## To use it in a project: 3 | ## - uncomment the lines corresponding to used pins 4 | ## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project 5 | 6 | # Clock signal 7 | set_property PACKAGE_PIN W5 [get_ports clk] 8 | set_property IOSTANDARD LVCMOS33 [get_ports clk] 9 | create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports clk] 10 | 11 | ## Switches 12 | #set_property PACKAGE_PIN V17 [get_ports {sw[0]}] 13 | # set_property IOSTANDARD LVCMOS33 [get_ports {sw[0]}] 14 | #set_property PACKAGE_PIN V16 [get_ports {sw[1]}] 15 | # set_property IOSTANDARD LVCMOS33 [get_ports {sw[1]}] 16 | #set_property PACKAGE_PIN W16 [get_ports {sw[2]}] 17 | # set_property IOSTANDARD LVCMOS33 [get_ports {sw[2]}] 18 | #set_property PACKAGE_PIN W17 [get_ports {sw[3]}] 19 | # set_property IOSTANDARD LVCMOS33 [get_ports {sw[3]}] 20 | #set_property PACKAGE_PIN W15 [get_ports {sw[4]}] 21 | # set_property IOSTANDARD LVCMOS33 [get_ports {sw[4]}] 22 | #set_property PACKAGE_PIN V15 [get_ports {sw[5]}] 23 | # set_property IOSTANDARD LVCMOS33 [get_ports {sw[5]}] 24 | #set_property PACKAGE_PIN W14 [get_ports {sw[6]}] 25 | # set_property IOSTANDARD LVCMOS33 [get_ports {sw[6]}] 26 | #set_property PACKAGE_PIN W13 [get_ports {sw[7]}] 27 | # set_property IOSTANDARD LVCMOS33 [get_ports {sw[7]}] 28 | #set_property PACKAGE_PIN V2 [get_ports {sw[8]}] 29 | # set_property IOSTANDARD LVCMOS33 [get_ports {sw[8]}] 30 | #set_property PACKAGE_PIN T3 [get_ports {sw[9]}] 31 | # set_property IOSTANDARD LVCMOS33 [get_ports {sw[9]}] 32 | #set_property PACKAGE_PIN T2 [get_ports {sw[10]}] 33 | # set_property IOSTANDARD LVCMOS33 [get_ports {sw[10]}] 34 | #set_property PACKAGE_PIN R3 [get_ports {sw[11]}] 35 | # set_property IOSTANDARD LVCMOS33 [get_ports {sw[11]}] 36 | #set_property PACKAGE_PIN W2 [get_ports {sw[12]}] 37 | # set_property IOSTANDARD LVCMOS33 [get_ports {sw[12]}] 38 | #set_property PACKAGE_PIN U1 [get_ports {sw[13]}] 39 | # set_property IOSTANDARD LVCMOS33 [get_ports {sw[13]}] 40 | #set_property PACKAGE_PIN T1 [get_ports {sw[14]}] 41 | # set_property IOSTANDARD LVCMOS33 [get_ports {sw[14]}] 42 | #set_property PACKAGE_PIN R2 [get_ports {sw[15]}] 43 | # set_property IOSTANDARD LVCMOS33 [get_ports {sw[15]}] 44 | 45 | 46 | ## LEDs 47 | #set_property PACKAGE_PIN U16 [get_ports {led[0]}] 48 | # set_property IOSTANDARD LVCMOS33 [get_ports {led[0]}] 49 | #set_property PACKAGE_PIN E19 [get_ports {led[1]}] 50 | # set_property IOSTANDARD LVCMOS33 [get_ports {led[1]}] 51 | #set_property PACKAGE_PIN U19 [get_ports {led[2]}] 52 | # set_property IOSTANDARD LVCMOS33 [get_ports {led[2]}] 53 | #set_property PACKAGE_PIN V19 [get_ports {led[3]}] 54 | # set_property IOSTANDARD LVCMOS33 [get_ports {led[3]}] 55 | #set_property PACKAGE_PIN W18 [get_ports {led[4]}] 56 | # set_property IOSTANDARD LVCMOS33 [get_ports {led[4]}] 57 | #set_property PACKAGE_PIN U15 [get_ports {led[5]}] 58 | # set_property IOSTANDARD LVCMOS33 [get_ports {led[5]}] 59 | #set_property PACKAGE_PIN U14 [get_ports {led[6]}] 60 | # set_property IOSTANDARD LVCMOS33 [get_ports {led[6]}] 61 | #set_property PACKAGE_PIN V14 [get_ports {led[7]}] 62 | # set_property IOSTANDARD LVCMOS33 [get_ports {led[7]}] 63 | #set_property PACKAGE_PIN V13 [get_ports {led[8]}] 64 | # set_property IOSTANDARD LVCMOS33 [get_ports {led[8]}] 65 | #set_property PACKAGE_PIN V3 [get_ports {led[9]}] 66 | # set_property IOSTANDARD LVCMOS33 [get_ports {led[9]}] 67 | #set_property PACKAGE_PIN W3 [get_ports {led[10]}] 68 | # set_property IOSTANDARD LVCMOS33 [get_ports {led[10]}] 69 | #set_property PACKAGE_PIN U3 [get_ports {led[11]}] 70 | # set_property IOSTANDARD LVCMOS33 [get_ports {led[11]}] 71 | #set_property PACKAGE_PIN P3 [get_ports {led[12]}] 72 | # set_property IOSTANDARD LVCMOS33 [get_ports {led[12]}] 73 | #set_property PACKAGE_PIN N3 [get_ports {led[13]}] 74 | # set_property IOSTANDARD LVCMOS33 [get_ports {led[13]}] 75 | #set_property PACKAGE_PIN P1 [get_ports {led[14]}] 76 | # set_property IOSTANDARD LVCMOS33 [get_ports {led[14]}] 77 | #set_property PACKAGE_PIN L1 [get_ports {led[15]}] 78 | # set_property IOSTANDARD LVCMOS33 [get_ports {led[15]}] 79 | 80 | 81 | ##7 segment display 82 | #set_property PACKAGE_PIN W7 [get_ports {seg[0]}] 83 | #set_property IOSTANDARD LVCMOS33 [get_ports {seg[0]}] 84 | #set_property PACKAGE_PIN W6 [get_ports {seg[1]}] 85 | #set_property IOSTANDARD LVCMOS33 [get_ports {seg[1]}] 86 | #set_property PACKAGE_PIN U8 [get_ports {seg[2]}] 87 | #set_property IOSTANDARD LVCMOS33 [get_ports {seg[2]}] 88 | #set_property PACKAGE_PIN V8 [get_ports {seg[3]}] 89 | #set_property IOSTANDARD LVCMOS33 [get_ports {seg[3]}] 90 | #set_property PACKAGE_PIN U5 [get_ports {seg[4]}] 91 | #set_property IOSTANDARD LVCMOS33 [get_ports {seg[4]}] 92 | #set_property PACKAGE_PIN V5 [get_ports {seg[5]}] 93 | #set_property IOSTANDARD LVCMOS33 [get_ports {seg[5]}] 94 | #set_property PACKAGE_PIN U7 [get_ports {seg[6]}] 95 | #set_property IOSTANDARD LVCMOS33 [get_ports {seg[6]}] 96 | 97 | #set_property PACKAGE_PIN V7 [get_ports dp] 98 | #set_property IOSTANDARD LVCMOS33 [get_ports dp] 99 | 100 | #set_property PACKAGE_PIN U2 [get_ports {an[0]}] 101 | #set_property IOSTANDARD LVCMOS33 [get_ports {an[0]}] 102 | #set_property PACKAGE_PIN U4 [get_ports {an[1]}] 103 | #set_property IOSTANDARD LVCMOS33 [get_ports {an[1]}] 104 | #set_property PACKAGE_PIN V4 [get_ports {an[2]}] 105 | #set_property IOSTANDARD LVCMOS33 [get_ports {an[2]}] 106 | #set_property PACKAGE_PIN W4 [get_ports {an[3]}] 107 | #set_property IOSTANDARD LVCMOS33 [get_ports {an[3]}] 108 | 109 | 110 | ##Buttons 111 | #set_property PACKAGE_PIN U18 [get_ports btnC] 112 | # set_property IOSTANDARD LVCMOS33 [get_ports btnC] 113 | #set_property PACKAGE_PIN T18 [get_ports btnU] 114 | #set_property IOSTANDARD LVCMOS33 [get_ports btnU] 115 | #set_property PACKAGE_PIN W19 [get_ports btnL] 116 | #set_property IOSTANDARD LVCMOS33 [get_ports btnL] 117 | #set_property PACKAGE_PIN T17 [get_ports btnR] 118 | #set_property IOSTANDARD LVCMOS33 [get_ports btnR] 119 | #set_property PACKAGE_PIN U17 [get_ports btnD] 120 | #set_property IOSTANDARD LVCMOS33 [get_ports btnD] 121 | 122 | 123 | 124 | ##Pmod Header JA 125 | ##Sch name = JA1 126 | #set_property PACKAGE_PIN J1 [get_ports {JA[0]}] 127 | #set_property IOSTANDARD LVCMOS33 [get_ports {JA[0]}] 128 | ##Sch name = JA2 129 | #set_property PACKAGE_PIN L2 [get_ports {JA[1]}] 130 | #set_property IOSTANDARD LVCMOS33 [get_ports {JA[1]}] 131 | ##Sch name = JA3 132 | #set_property PACKAGE_PIN J2 [get_ports {JA[2]}] 133 | #set_property IOSTANDARD LVCMOS33 [get_ports {JA[2]}] 134 | ##Sch name = JA4 135 | #set_property PACKAGE_PIN G2 [get_ports {JA[3]}] 136 | #set_property IOSTANDARD LVCMOS33 [get_ports {JA[3]}] 137 | ##Sch name = JA7 138 | #set_property PACKAGE_PIN H1 [get_ports {JA[4]}] 139 | #set_property IOSTANDARD LVCMOS33 [get_ports {JA[4]}] 140 | ##Sch name = JA8 141 | #set_property PACKAGE_PIN K2 [get_ports {JA[5]}] 142 | #set_property IOSTANDARD LVCMOS33 [get_ports {JA[5]}] 143 | ##Sch name = JA9 144 | #set_property PACKAGE_PIN H2 [get_ports {JA[6]}] 145 | #set_property IOSTANDARD LVCMOS33 [get_ports {JA[6]}] 146 | ##Sch name = JA10 147 | #set_property PACKAGE_PIN G3 [get_ports {JA[7]}] 148 | #set_property IOSTANDARD LVCMOS33 [get_ports {JA[7]}] 149 | 150 | 151 | 152 | ##Pmod Header JB 153 | ##Sch name = JB1 154 | #set_property PACKAGE_PIN A14 [get_ports {JB[0]}] 155 | #set_property IOSTANDARD LVCMOS33 [get_ports {JB[0]}] 156 | ##Sch name = JB2 157 | #set_property PACKAGE_PIN A16 [get_ports {JB[1]}] 158 | #set_property IOSTANDARD LVCMOS33 [get_ports {JB[1]}] 159 | ##Sch name = JB3 160 | #set_property PACKAGE_PIN B15 [get_ports {JB[2]}] 161 | #set_property IOSTANDARD LVCMOS33 [get_ports {JB[2]}] 162 | ##Sch name = JB4 163 | #set_property PACKAGE_PIN B16 [get_ports {JB[3]}] 164 | #set_property IOSTANDARD LVCMOS33 [get_ports {JB[3]}] 165 | ##Sch name = JB7 166 | #set_property PACKAGE_PIN A15 [get_ports {JB[4]}] 167 | #set_property IOSTANDARD LVCMOS33 [get_ports {JB[4]}] 168 | ##Sch name = JB8 169 | #set_property PACKAGE_PIN A17 [get_ports {JB[5]}] 170 | #set_property IOSTANDARD LVCMOS33 [get_ports {JB[5]}] 171 | ##Sch name = JB9 172 | #set_property PACKAGE_PIN C15 [get_ports {JB[6]}] 173 | #set_property IOSTANDARD LVCMOS33 [get_ports {JB[6]}] 174 | ##Sch name = JB10 175 | #set_property PACKAGE_PIN C16 [get_ports {JB[7]}] 176 | #set_property IOSTANDARD LVCMOS33 [get_ports {JB[7]}] 177 | 178 | 179 | 180 | ##Pmod Header JC 181 | ##Sch name = JC1 182 | #set_property PACKAGE_PIN K17 [get_ports {JC[0]}] 183 | #set_property IOSTANDARD LVCMOS33 [get_ports {JC[0]}] 184 | ##Sch name = JC2 185 | #set_property PACKAGE_PIN M18 [get_ports {JC[1]}] 186 | #set_property IOSTANDARD LVCMOS33 [get_ports {JC[1]}] 187 | ##Sch name = JC3 188 | #set_property PACKAGE_PIN N17 [get_ports {JC[2]}] 189 | #set_property IOSTANDARD LVCMOS33 [get_ports {JC[2]}] 190 | ##Sch name = JC4 191 | #set_property PACKAGE_PIN P18 [get_ports {JC[3]}] 192 | #set_property IOSTANDARD LVCMOS33 [get_ports {JC[3]}] 193 | ##Sch name = JC7 194 | #set_property PACKAGE_PIN L17 [get_ports {JC[4]}] 195 | #set_property IOSTANDARD LVCMOS33 [get_ports {JC[4]}] 196 | ##Sch name = JC8 197 | #set_property PACKAGE_PIN M19 [get_ports {JC[5]}] 198 | #set_property IOSTANDARD LVCMOS33 [get_ports {JC[5]}] 199 | ##Sch name = JC9 200 | #set_property PACKAGE_PIN P17 [get_ports {JC[6]}] 201 | #set_property IOSTANDARD LVCMOS33 [get_ports {JC[6]}] 202 | ##Sch name = JC10 203 | #set_property PACKAGE_PIN R18 [get_ports {JC[7]}] 204 | #set_property IOSTANDARD LVCMOS33 [get_ports {JC[7]}] 205 | 206 | 207 | ##Pmod Header JXADC 208 | ##Sch name = XA1_P 209 | #set_property PACKAGE_PIN J3 [get_ports {JXADC[0]}] 210 | #set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[0]}] 211 | ##Sch name = XA2_P 212 | #set_property PACKAGE_PIN L3 [get_ports {JXADC[1]}] 213 | #set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[1]}] 214 | ##Sch name = XA3_P 215 | #set_property PACKAGE_PIN M2 [get_ports {JXADC[2]}] 216 | #set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[2]}] 217 | ##Sch name = XA4_P 218 | #set_property PACKAGE_PIN N2 [get_ports {JXADC[3]}] 219 | #set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[3]}] 220 | ##Sch name = XA1_N 221 | #set_property PACKAGE_PIN K3 [get_ports {JXADC[4]}] 222 | #set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[4]}] 223 | ##Sch name = XA2_N 224 | #set_property PACKAGE_PIN M3 [get_ports {JXADC[5]}] 225 | #set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[5]}] 226 | ##Sch name = XA3_N 227 | #set_property PACKAGE_PIN M1 [get_ports {JXADC[6]}] 228 | #set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[6]}] 229 | ##Sch name = XA4_N 230 | #set_property PACKAGE_PIN N1 [get_ports {JXADC[7]}] 231 | #set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[7]}] 232 | 233 | 234 | 235 | ##VGA Connector 236 | #set_property PACKAGE_PIN G19 [get_ports {vgaRed[0]}] 237 | #set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[0]}] 238 | #set_property PACKAGE_PIN H19 [get_ports {vgaRed[1]}] 239 | #set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[1]}] 240 | #set_property PACKAGE_PIN J19 [get_ports {vgaRed[2]}] 241 | #set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[2]}] 242 | #set_property PACKAGE_PIN N19 [get_ports {vgaRed[3]}] 243 | #set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[3]}] 244 | #set_property PACKAGE_PIN N18 [get_ports {vgaBlue[0]}] 245 | #set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[0]}] 246 | #set_property PACKAGE_PIN L18 [get_ports {vgaBlue[1]}] 247 | #set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[1]}] 248 | #set_property PACKAGE_PIN K18 [get_ports {vgaBlue[2]}] 249 | #set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[2]}] 250 | #set_property PACKAGE_PIN J18 [get_ports {vgaBlue[3]}] 251 | #set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[3]}] 252 | #set_property PACKAGE_PIN J17 [get_ports {vgaGreen[0]}] 253 | #set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[0]}] 254 | #set_property PACKAGE_PIN H17 [get_ports {vgaGreen[1]}] 255 | #set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[1]}] 256 | #set_property PACKAGE_PIN G17 [get_ports {vgaGreen[2]}] 257 | #set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[2]}] 258 | #set_property PACKAGE_PIN D17 [get_ports {vgaGreen[3]}] 259 | #set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[3]}] 260 | #set_property PACKAGE_PIN P19 [get_ports Hsync] 261 | #set_property IOSTANDARD LVCMOS33 [get_ports Hsync] 262 | #set_property PACKAGE_PIN R19 [get_ports Vsync] 263 | #set_property IOSTANDARD LVCMOS33 [get_ports Vsync] 264 | 265 | 266 | ##USB-RS232 Interface 267 | #set_property PACKAGE_PIN B18 [get_ports RsRx] 268 | #set_property IOSTANDARD LVCMOS33 [get_ports RsRx] 269 | set_property PACKAGE_PIN A18 [get_ports tx] 270 | set_property IOSTANDARD LVCMOS33 [get_ports tx] 271 | 272 | 273 | #USB HID (PS/2) 274 | set_property PACKAGE_PIN C17 [get_ports PS2Clk] 275 | set_property IOSTANDARD LVCMOS33 [get_ports PS2Clk] 276 | set_property PULLUP true [get_ports PS2Clk] 277 | set_property PACKAGE_PIN B17 [get_ports PS2Data] 278 | set_property IOSTANDARD LVCMOS33 [get_ports PS2Data] 279 | set_property PULLUP true [get_ports PS2Data] 280 | 281 | 282 | ##Quad SPI Flash 283 | ##Note that CCLK_0 cannot be placed in 7 series devices. You can access it using the 284 | ##STARTUPE2 primitive. 285 | #set_property PACKAGE_PIN D18 [get_ports {QspiDB[0]}] 286 | #set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[0]}] 287 | #set_property PACKAGE_PIN D19 [get_ports {QspiDB[1]}] 288 | #set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[1]}] 289 | #set_property PACKAGE_PIN G18 [get_ports {QspiDB[2]}] 290 | #set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[2]}] 291 | #set_property PACKAGE_PIN F18 [get_ports {QspiDB[3]}] 292 | #set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[3]}] 293 | #set_property PACKAGE_PIN K19 [get_ports QspiCSn] 294 | #set_property IOSTANDARD LVCMOS33 [get_ports QspiCSn] -------------------------------------------------------------------------------- /Projects/Keyboard/src/hdl/PS2Receiver.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: Digilent Inc. 4 | // Engineer: Thomas Kappenman 5 | // 6 | // Create Date: 03/03/2015 09:33:36 PM 7 | // Design Name: 8 | // Module Name: PS2Receiver 9 | // Project Name: Nexys4DDR Keyboard Demo 10 | // Target Devices: Nexys4DDR 11 | // Tool Versions: 12 | // Description: PS2 Receiver module used to shift in keycodes from a keyboard plugged into the PS2 port 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | 23 | module PS2Receiver( 24 | input clk, 25 | input kclk, 26 | input kdata, 27 | output reg [15:0] keycode=0, 28 | output reg oflag 29 | ); 30 | 31 | wire kclkf, kdataf; 32 | reg [7:0]datacur=0; 33 | reg [7:0]dataprev=0; 34 | reg [3:0]cnt=0; 35 | reg flag=0; 36 | 37 | debouncer #( 38 | .COUNT_MAX(19), 39 | .COUNT_WIDTH(5) 40 | ) db_clk( 41 | .clk(clk), 42 | .I(kclk), 43 | .O(kclkf) 44 | ); 45 | debouncer #( 46 | .COUNT_MAX(19), 47 | .COUNT_WIDTH(5) 48 | ) db_data( 49 | .clk(clk), 50 | .I(kdata), 51 | .O(kdataf) 52 | ); 53 | 54 | always@(negedge(kclkf))begin 55 | case(cnt) 56 | 0:;//Start bit 57 | 1:datacur[0]<=kdataf; 58 | 2:datacur[1]<=kdataf; 59 | 3:datacur[2]<=kdataf; 60 | 4:datacur[3]<=kdataf; 61 | 5:datacur[4]<=kdataf; 62 | 6:datacur[5]<=kdataf; 63 | 7:datacur[6]<=kdataf; 64 | 8:datacur[7]<=kdataf; 65 | 9:flag<=1'b1; 66 | 10:flag<=1'b0; 67 | 68 | endcase 69 | if(cnt<=9) cnt<=cnt+1; 70 | else if(cnt==10) cnt<=0; 71 | end 72 | 73 | reg pflag; 74 | always@(posedge clk) begin 75 | if (flag == 1'b1 && pflag == 1'b0) begin 76 | keycode <= {dataprev, datacur}; 77 | oflag <= 1'b1; 78 | dataprev <= datacur; 79 | end else 80 | oflag <= 'b0; 81 | pflag <= flag; 82 | end 83 | 84 | endmodule 85 | -------------------------------------------------------------------------------- /Projects/Keyboard/src/hdl/bin2ascii.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 07/27/2016 04:39:01 PM 7 | // Design Name: 8 | // Module Name: bin2ascii 9 | // Project Name: 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | 23 | module bin2ascii( 24 | input [NBYTES*8-1:0] I, 25 | output reg [NBYTES*16-1:0] O=0 26 | ); 27 | parameter NBYTES=2; 28 | genvar i; 29 | generate for (i=0; i= 4'h0 && I[4*i+3:4*i] <= 4'h9) 32 | O[8*i+7:8*i] = 8'd48 + I[4*i+3:4*i]; 33 | else 34 | O[8*i+7:8*i] = 8'd55 + I[4*i+3:4*i]; 35 | endgenerate 36 | endmodule 37 | -------------------------------------------------------------------------------- /Projects/Keyboard/src/hdl/debouncer.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 07/27/2016 02:04:22 PM 7 | // Design Name: 8 | // Module Name: debouncer 9 | // Project Name: 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | 23 | module debouncer( 24 | input clk, 25 | input I, 26 | output reg O 27 | ); 28 | parameter COUNT_MAX=255, COUNT_WIDTH=8; 29 | reg [COUNT_WIDTH-1:0] count; 30 | reg Iv=0; 31 | always@(posedge clk) 32 | if (I == Iv) begin 33 | if (count == COUNT_MAX) 34 | O <= I; 35 | else 36 | count <= count + 1'b1; 37 | end else begin 38 | count <= 'b0; 39 | Iv <= I; 40 | end 41 | 42 | endmodule 43 | -------------------------------------------------------------------------------- /Projects/Keyboard/src/hdl/top.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: Digilent Inc 4 | // Engineer: Arthur Brown 5 | // 6 | // Create Date: 07/27/2016 02:04:01 PM 7 | // Design Name: Basys3 Keyboard Demo 8 | // Module Name: top 9 | // Project Name: Keyboard 10 | // Target Devices: Basys3 11 | // Tool Versions: 2016.X 12 | // Description: 13 | // Receives input from USB-HID in the form of a PS/2, displays keyboard key presses and releases over USB-UART. 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // Known issue, when multiple buttons are pressed and one is released, the scan code of the one still held down is ometimes re-sent. 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | 23 | module top( 24 | input clk, 25 | input PS2Data, 26 | input PS2Clk, 27 | output tx 28 | ); 29 | wire tready; 30 | wire ready; 31 | wire tstart; 32 | reg start=0; 33 | reg CLK50MHZ=0; 34 | wire [31:0] tbuf; 35 | reg [15:0] keycodev=0; 36 | wire [15:0] keycode; 37 | wire [ 7:0] tbus; 38 | reg [ 2:0] bcount=0; 39 | wire flag; 40 | reg cn=0; 41 | 42 | always @(posedge(clk))begin 43 | CLK50MHZ<=~CLK50MHZ; 44 | end 45 | 46 | PS2Receiver uut ( 47 | .clk(CLK50MHZ), 48 | .kclk(PS2Clk), 49 | .kdata(PS2Data), 50 | .keycode(keycode), 51 | .oflag(flag) 52 | ); 53 | 54 | 55 | always@(keycode) 56 | if (keycode[7:0] == 8'hf0) begin 57 | cn <= 1'b0; 58 | bcount <= 3'd0; 59 | end else if (keycode[15:8] == 8'hf0) begin 60 | cn <= keycode != keycodev; 61 | bcount <= 3'd5; 62 | end else begin 63 | cn <= keycode[7:0] != keycodev[7:0] || keycodev[15:8] == 8'hf0; 64 | bcount <= 3'd2; 65 | end 66 | 67 | always@(posedge clk) 68 | if (flag == 1'b1 && cn == 1'b1) begin 69 | start <= 1'b1; 70 | keycodev <= keycode; 71 | end else 72 | start <= 1'b0; 73 | 74 | bin2ascii #( 75 | .NBYTES(2) 76 | ) conv ( 77 | .I(keycodev), 78 | .O(tbuf) 79 | ); 80 | 81 | uart_buf_con tx_con ( 82 | .clk (clk ), 83 | .bcount (bcount), 84 | .tbuf (tbuf ), 85 | .start (start ), 86 | .ready (ready ), 87 | .tstart (tstart), 88 | .tready (tready), 89 | .tbus (tbus ) 90 | ); 91 | 92 | uart_tx get_tx ( 93 | .clk (clk), 94 | .start (tstart), 95 | .tbus (tbus), 96 | .tx (tx), 97 | .ready (tready) 98 | ); 99 | 100 | endmodule 101 | -------------------------------------------------------------------------------- /Projects/Keyboard/src/hdl/uart_buf_con.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: Digilent Inc 4 | // Engineer: Arthur Brown 5 | // 6 | // Create Date: 07/27/2016 03:53:30 PM 7 | // Design Name: 8 | // Module Name: uart_buf_con 9 | // Project Name: 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | 23 | module uart_buf_con( 24 | input clk, 25 | input [ 2:0] bcount, 26 | input [31:0] tbuf, 27 | input start, 28 | output ready, 29 | output reg tstart=0, 30 | input tready, 31 | output reg [ 7:0] tbus=0 32 | ); 33 | reg [2:0] sel=0; 34 | reg [31:0] pbuf=0; 35 | reg running=0; 36 | initial tstart <= 'b0; 37 | initial tbus <= 'b0; 38 | always@(posedge clk) 39 | if (tready == 1'b1) begin 40 | if (running == 1'b1) begin 41 | if (sel == 4'd1) begin 42 | running <= 1'b0; 43 | sel <= bcount + 2'd2; 44 | end else begin 45 | sel <= sel - 1'b1; 46 | tstart <= 1'b1; 47 | running <= 1'b1; 48 | end 49 | end else begin 50 | if (bcount != 2'b0) begin 51 | pbuf <= tbuf; 52 | tstart <= start; 53 | running <= start; 54 | sel <= bcount + 2'd2; 55 | end 56 | end 57 | end else 58 | tstart <= 1'b0; 59 | assign ready = ~running; 60 | always@(sel, pbuf) 61 | case (sel) 62 | 1: tbus <= 8'd13; 63 | 2: tbus <= 8'd10; 64 | 3: tbus <= pbuf[7:0]; 65 | 4: tbus <= pbuf[15:8]; 66 | 5: tbus <= 8'd32; 67 | 6: tbus <= pbuf[23:16]; 68 | 7: tbus <= pbuf[31:24]; 69 | default: tbus <= 8'd0; 70 | endcase 71 | endmodule 72 | -------------------------------------------------------------------------------- /Projects/Keyboard/src/hdl/uart_tx.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 07/27/2016 02:04:01 PM 7 | // Design Name: 8 | // Module Name: uart_tx 9 | // Project Name: 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | 23 | module uart_tx( 24 | input clk , 25 | input [7:0] tbus , 26 | input start, 27 | output tx , 28 | output ready 29 | ); 30 | parameter CD_MAX=10416, CD_WIDTH=16; 31 | reg [CD_WIDTH-1:0] cd_count=0; 32 | reg [3:0] count=0; 33 | reg running=0; 34 | reg [10:0] shift=11'h7ff; 35 | always@(posedge clk) begin 36 | if (running == 1'b0) begin 37 | shift <= {2'b11, tbus, 1'b0}; 38 | running <= start; 39 | cd_count <= 'b0; 40 | count <= 'b0; 41 | end else if (cd_count == CD_MAX) begin 42 | shift <= {1'b1, shift[10:1]}; 43 | cd_count <= 'b0; 44 | if (count == 4'd10) begin 45 | running <= 1'b0; 46 | count <= 'b0; 47 | end 48 | else 49 | count <= count + 1'b1; 50 | end else 51 | cd_count <= cd_count + 1'b1; 52 | end 53 | assign tx = (running == 1'b1) ? shift[0] : 1'b1; 54 | assign ready = ((running == 1'b0 && start == 1'b0) || (cd_count == CD_MAX && count == 4'd10)) ? 1'b1 : 1'b0; 55 | endmodule 56 | -------------------------------------------------------------------------------- /Projects/XADC_Demo/proj/_READ_ME_.txt: -------------------------------------------------------------------------------- 1 | In order to run the create_project script successfully, the folder must be in its initial state 2 | containing only the cleanup, create_project scripts, and this document. 3 | 4 | To restore the folder to its initial state, double-click the cleanup Windows Command Script. 5 | 6 | !!!!CAUTION!!!! 7 | 8 | Moving or copying the cleanup Windows Command Script can result in unintentional loss of data on your 9 | system. The script contains a short list of specific files to ignore once it is run, all other files 10 | and folders within its directory location will be ERASED. Use this only within the project folder as 11 | instructed. 12 | 13 | See material on the usage of demo projects at reference.digilentinc.com -------------------------------------------------------------------------------- /Projects/XADC_Demo/proj/cleanup.cmd: -------------------------------------------------------------------------------- 1 | @echo off 2 | rem delete all files from subfolders 3 | for /d /r %%i in (*) do del /f /q %%i\* 4 | rem delete all subfolders 5 | for /d %%i in (*) do rd /S /Q %%i 6 | 7 | rem unmark read only from all files 8 | attrib -R .\* /S 9 | 10 | rem mark read only those we wish to keep 11 | attrib +R .\create_project.tcl 12 | attrib +R .\cleanup.sh 13 | attrib +R .\cleanup.cmd 14 | attrib +R .\.gitignore 15 | attrib +R .\_READ_ME_.txt 16 | 17 | rem delete all non read-only 18 | del /Q /A:-R .\* 19 | 20 | rem unmark read-only 21 | attrib -R .\* 22 | -------------------------------------------------------------------------------- /Projects/XADC_Demo/proj/cleanup.sh: -------------------------------------------------------------------------------- 1 | # This script is useful for cleaning up the 'project' 2 | # directory of a Digilent Vivado-project git repository 3 | ### 4 | # Run the following command to change permissions of 5 | # this 'cleanup' file if needed: 6 | # chmod u+x cleanup.sh 7 | ### 8 | # Remove directories/subdirectories 9 | find . -mindepth 1 -type d -exec rm -rf {} + 10 | # Remove any other files than: 11 | find . -type f ! -name 'cleanup.sh' \ 12 | ! -name 'cleanup.cmd' \ 13 | ! -name 'create_project.tcl' \ 14 | ! -name '.gitignore' \ 15 | -exec rm -rf {} + 16 | -------------------------------------------------------------------------------- /Projects/XADC_Demo/proj/create_project.tcl: -------------------------------------------------------------------------------- 1 | # Run this script to create the Vivado project files in the WORKING DIRECTORY 2 | # If ::create_path global variable is set, the project is created under that path instead of the working dir 3 | 4 | if {[info exists ::create_path]} { 5 | set dest_dir $::create_path 6 | } else { 7 | set dest_dir [pwd] 8 | } 9 | puts "INFO: Creating new project in $dest_dir" 10 | 11 | # Set the reference directory for source file relative paths (by default the value is script directory path) 12 | set proj_name "XADC_Demo" 13 | 14 | # Set the reference directory for source file relative paths (by default the value is script directory path) 15 | set origin_dir ".." 16 | 17 | # Set the directory path for the original project from where this script was exported 18 | set orig_proj_dir "[file normalize "$origin_dir/proj"]" 19 | 20 | set src_dir $origin_dir/src 21 | set repo_dir $origin_dir/repo 22 | 23 | # Set the board part number 24 | set part_num "xc7a35tcpg236-1" 25 | 26 | # Create project 27 | create_project $proj_name $dest_dir 28 | 29 | # Set the directory path for the new project 30 | set proj_dir [get_property directory [current_project]] 31 | 32 | # Set project properties 33 | set obj [get_projects $proj_name] 34 | set_property "default_lib" "xil_defaultlib" $obj 35 | set_property "part" "$part_num" $obj 36 | set_property "simulator_language" "Mixed" $obj 37 | set_property "target_language" "VHDL" $obj 38 | 39 | # Create 'sources_1' fileset (if not found) 40 | if {[string equal [get_filesets -quiet sources_1] ""]} { 41 | create_fileset -srcset sources_1 42 | } 43 | 44 | # Create 'constrs_1' fileset (if not found) 45 | if {[string equal [get_filesets -quiet constrs_1] ""]} { 46 | create_fileset -constrset constrs_1 47 | } 48 | 49 | # Set IP repository paths 50 | set obj [get_filesets sources_1] 51 | set_property "ip_repo_paths" "[file normalize $repo_dir]" $obj 52 | 53 | # Add conventional sources 54 | add_files -quiet $src_dir/hdl 55 | 56 | # Add IPs 57 | add_files -quiet [glob -nocomplain ../src/ip/*/*.xci] 58 | 59 | # Add constraints 60 | add_files -fileset constrs_1 -quiet $src_dir/constraints 61 | 62 | # Refresh IP Repositories 63 | #update_ip_catalog 64 | 65 | # Create 'synth_1' run (if not found) 66 | if {[string equal [get_runs -quiet synth_1] ""]} { 67 | create_run -name synth_1 -part $part_num -flow {Vivado Synthesis 2014} -strategy "Flow_PerfOptimized_High" -constrset constrs_1 68 | } else { 69 | set_property strategy "Flow_PerfOptimized_High" [get_runs synth_1] 70 | set_property flow "Vivado Synthesis 2014" [get_runs synth_1] 71 | } 72 | set obj [get_runs synth_1] 73 | set_property "part" "$part_num" $obj 74 | set_property "steps.synth_design.args.fanout_limit" "400" $obj 75 | set_property "steps.synth_design.args.fsm_extraction" "one_hot" $obj 76 | set_property "steps.synth_design.args.keep_equivalent_registers" "1" $obj 77 | set_property "steps.synth_design.args.resource_sharing" "off" $obj 78 | set_property "steps.synth_design.args.no_lc" "1" $obj 79 | set_property "steps.synth_design.args.shreg_min_size" "5" $obj 80 | 81 | # set the current synth run 82 | current_run -synthesis [get_runs synth_1] 83 | 84 | # Create 'impl_1' run (if not found) 85 | if {[string equal [get_runs -quiet impl_1] ""]} { 86 | create_run -name impl_1 -part $part_num -flow {Vivado Implementation 2014} -strategy "Vivado Implementation Defaults" -constrset constrs_1 -parent_run synth_1 87 | } else { 88 | set_property strategy "Vivado Implementation Defaults" [get_runs impl_1] 89 | set_property flow "Vivado Implementation 2014" [get_runs impl_1] 90 | } 91 | set obj [get_runs impl_1] 92 | set_property "part" "$part_num" $obj 93 | set_property "steps.write_bitstream.args.bin_file" "1" $obj 94 | 95 | # set the current impl run 96 | current_run -implementation [get_runs impl_1] 97 | 98 | #puts "INFO: Project created:$proj_name" 99 | 100 | # Comment the following section, if there is no block design 101 | # Create block design 102 | #source $origin_dir/src/bd/bt_gpio.tcl 103 | 104 | # Generate the wrapper 105 | #set design_name [get_bd_designs] 106 | #make_wrapper -files [get_files $design_name.bd] -top -import 107 | 108 | #set obj [get_filesets sources_1] 109 | #set_property "top" "bt_gpio_top" $obj 110 | 111 | #puts "INFO: Block design created: $design_name.bd" 112 | -------------------------------------------------------------------------------- /Projects/XADC_Demo/src/constraints/Basys3_Master.xdc: -------------------------------------------------------------------------------- 1 | ## This file is a general .xdc for the Basys3 rev B board 2 | ## To use it in a project: 3 | ## - uncomment the lines corresponding to used pins 4 | ## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project 5 | 6 | # Clock signal 7 | set_property PACKAGE_PIN W5 [get_ports CLK100MHZ] 8 | set_property IOSTANDARD LVCMOS33 [get_ports CLK100MHZ] 9 | create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports CLK100MHZ] 10 | 11 | # Switches 12 | set_property PACKAGE_PIN V17 [get_ports {sw[0]}] 13 | set_property IOSTANDARD LVCMOS33 [get_ports {sw[0]}] 14 | set_property PACKAGE_PIN V16 [get_ports {sw[1]}] 15 | set_property IOSTANDARD LVCMOS33 [get_ports {sw[1]}] 16 | #set_property PACKAGE_PIN W16 [get_ports {sw[2]}] 17 | #set_property IOSTANDARD LVCMOS33 [get_ports {sw[2]}] 18 | #set_property PACKAGE_PIN W17 [get_ports {sw[3]}] 19 | #set_property IOSTANDARD LVCMOS33 [get_ports {sw[3]}] 20 | #set_property PACKAGE_PIN W15 [get_ports {sw[4]}] 21 | #set_property IOSTANDARD LVCMOS33 [get_ports {sw[4]}] 22 | #set_property PACKAGE_PIN V15 [get_ports {sw[5]}] 23 | #set_property IOSTANDARD LVCMOS33 [get_ports {sw[5]}] 24 | #set_property PACKAGE_PIN W14 [get_ports {sw[6]}] 25 | #set_property IOSTANDARD LVCMOS33 [get_ports {sw[6]}] 26 | #set_property PACKAGE_PIN W13 [get_ports {sw[7]}] 27 | #set_property IOSTANDARD LVCMOS33 [get_ports {sw[7]}] 28 | #set_property PACKAGE_PIN V2 [get_ports {sw[8]}] 29 | #set_property IOSTANDARD LVCMOS33 [get_ports {sw[8]}] 30 | #set_property PACKAGE_PIN T3 [get_ports {sw[9]}] 31 | #set_property IOSTANDARD LVCMOS33 [get_ports {sw[9]}] 32 | #set_property PACKAGE_PIN T2 [get_ports {sw[10]}] 33 | #set_property IOSTANDARD LVCMOS33 [get_ports {sw[10]}] 34 | #set_property PACKAGE_PIN R3 [get_ports {sw[11]}] 35 | #set_property IOSTANDARD LVCMOS33 [get_ports {sw[11]}] 36 | #set_property PACKAGE_PIN W2 [get_ports {sw[12]}] 37 | #set_property IOSTANDARD LVCMOS33 [get_ports {sw[12]}] 38 | #set_property PACKAGE_PIN U1 [get_ports {sw[13]}] 39 | #set_property IOSTANDARD LVCMOS33 [get_ports {sw[13]}] 40 | #set_property PACKAGE_PIN T1 [get_ports {sw[14]}] 41 | #set_property IOSTANDARD LVCMOS33 [get_ports {sw[14]}] 42 | #set_property PACKAGE_PIN R2 [get_ports {sw[15]}] 43 | #set_property IOSTANDARD LVCMOS33 [get_ports {sw[15]}] 44 | 45 | 46 | # LEDs 47 | set_property PACKAGE_PIN U16 [get_ports {LED[0]}] 48 | set_property IOSTANDARD LVCMOS33 [get_ports {LED[0]}] 49 | set_property PACKAGE_PIN E19 [get_ports {LED[1]}] 50 | set_property IOSTANDARD LVCMOS33 [get_ports {LED[1]}] 51 | set_property PACKAGE_PIN U19 [get_ports {LED[2]}] 52 | set_property IOSTANDARD LVCMOS33 [get_ports {LED[2]}] 53 | set_property PACKAGE_PIN V19 [get_ports {LED[3]}] 54 | set_property IOSTANDARD LVCMOS33 [get_ports {LED[3]}] 55 | set_property PACKAGE_PIN W18 [get_ports {LED[4]}] 56 | set_property IOSTANDARD LVCMOS33 [get_ports {LED[4]}] 57 | set_property PACKAGE_PIN U15 [get_ports {LED[5]}] 58 | set_property IOSTANDARD LVCMOS33 [get_ports {LED[5]}] 59 | set_property PACKAGE_PIN U14 [get_ports {LED[6]}] 60 | set_property IOSTANDARD LVCMOS33 [get_ports {LED[6]}] 61 | set_property PACKAGE_PIN V14 [get_ports {LED[7]}] 62 | set_property IOSTANDARD LVCMOS33 [get_ports {LED[7]}] 63 | set_property PACKAGE_PIN V13 [get_ports {LED[8]}] 64 | set_property IOSTANDARD LVCMOS33 [get_ports {LED[8]}] 65 | set_property PACKAGE_PIN V3 [get_ports {LED[9]}] 66 | set_property IOSTANDARD LVCMOS33 [get_ports {LED[9]}] 67 | set_property PACKAGE_PIN W3 [get_ports {LED[10]}] 68 | set_property IOSTANDARD LVCMOS33 [get_ports {LED[10]}] 69 | set_property PACKAGE_PIN U3 [get_ports {LED[11]}] 70 | set_property IOSTANDARD LVCMOS33 [get_ports {LED[11]}] 71 | set_property PACKAGE_PIN P3 [get_ports {LED[12]}] 72 | set_property IOSTANDARD LVCMOS33 [get_ports {LED[12]}] 73 | set_property PACKAGE_PIN N3 [get_ports {LED[13]}] 74 | set_property IOSTANDARD LVCMOS33 [get_ports {LED[13]}] 75 | set_property PACKAGE_PIN P1 [get_ports {LED[14]}] 76 | set_property IOSTANDARD LVCMOS33 [get_ports {LED[14]}] 77 | set_property PACKAGE_PIN L1 [get_ports {LED[15]}] 78 | set_property IOSTANDARD LVCMOS33 [get_ports {LED[15]}] 79 | 80 | 81 | #7 segment display 82 | set_property PACKAGE_PIN W7 [get_ports {seg[0]}] 83 | set_property IOSTANDARD LVCMOS33 [get_ports {seg[0]}] 84 | set_property PACKAGE_PIN W6 [get_ports {seg[1]}] 85 | set_property IOSTANDARD LVCMOS33 [get_ports {seg[1]}] 86 | set_property PACKAGE_PIN U8 [get_ports {seg[2]}] 87 | set_property IOSTANDARD LVCMOS33 [get_ports {seg[2]}] 88 | set_property PACKAGE_PIN V8 [get_ports {seg[3]}] 89 | set_property IOSTANDARD LVCMOS33 [get_ports {seg[3]}] 90 | set_property PACKAGE_PIN U5 [get_ports {seg[4]}] 91 | set_property IOSTANDARD LVCMOS33 [get_ports {seg[4]}] 92 | set_property PACKAGE_PIN V5 [get_ports {seg[5]}] 93 | set_property IOSTANDARD LVCMOS33 [get_ports {seg[5]}] 94 | set_property PACKAGE_PIN U7 [get_ports {seg[6]}] 95 | set_property IOSTANDARD LVCMOS33 [get_ports {seg[6]}] 96 | 97 | set_property PACKAGE_PIN V7 [get_ports dp] 98 | set_property IOSTANDARD LVCMOS33 [get_ports dp] 99 | 100 | set_property PACKAGE_PIN U2 [get_ports {an[0]}] 101 | set_property IOSTANDARD LVCMOS33 [get_ports {an[0]}] 102 | set_property PACKAGE_PIN U4 [get_ports {an[1]}] 103 | set_property IOSTANDARD LVCMOS33 [get_ports {an[1]}] 104 | set_property PACKAGE_PIN V4 [get_ports {an[2]}] 105 | set_property IOSTANDARD LVCMOS33 [get_ports {an[2]}] 106 | set_property PACKAGE_PIN W4 [get_ports {an[3]}] 107 | set_property IOSTANDARD LVCMOS33 [get_ports {an[3]}] 108 | 109 | 110 | ##Buttons 111 | #set_property PACKAGE_PIN U18 [get_ports btnC] 112 | #set_property IOSTANDARD LVCMOS33 [get_ports btnC] 113 | #set_property PACKAGE_PIN T18 [get_ports btnU] 114 | #set_property IOSTANDARD LVCMOS33 [get_ports btnU] 115 | #set_property PACKAGE_PIN W19 [get_ports btnL] 116 | #set_property IOSTANDARD LVCMOS33 [get_ports btnL] 117 | #set_property PACKAGE_PIN T17 [get_ports btnR] 118 | #set_property IOSTANDARD LVCMOS33 [get_ports btnR] 119 | #set_property PACKAGE_PIN U17 [get_ports btnD] 120 | #set_property IOSTANDARD LVCMOS33 [get_ports btnD] 121 | 122 | 123 | 124 | ##Pmod Header JA 125 | ##Sch name = JA1 126 | #set_property PACKAGE_PIN J1 [get_ports {JA[0]}] 127 | #set_property IOSTANDARD LVCMOS33 [get_ports {JA[0]}] 128 | ##Sch name = JA2 129 | #set_property PACKAGE_PIN L2 [get_ports {JA[1]}] 130 | #set_property IOSTANDARD LVCMOS33 [get_ports {JA[1]}] 131 | ##Sch name = JA3 132 | #set_property PACKAGE_PIN J2 [get_ports {JA[2]}] 133 | #set_property IOSTANDARD LVCMOS33 [get_ports {JA[2]}] 134 | ##Sch name = JA4 135 | #set_property PACKAGE_PIN G2 [get_ports {JA[3]}] 136 | #set_property IOSTANDARD LVCMOS33 [get_ports {JA[3]}] 137 | ##Sch name = JA7 138 | #set_property PACKAGE_PIN H1 [get_ports {JA[4]}] 139 | #set_property IOSTANDARD LVCMOS33 [get_ports {JA[4]}] 140 | ##Sch name = JA8 141 | #set_property PACKAGE_PIN K2 [get_ports {JA[5]}] 142 | #set_property IOSTANDARD LVCMOS33 [get_ports {JA[5]}] 143 | ##Sch name = JA9 144 | #set_property PACKAGE_PIN H2 [get_ports {JA[6]}] 145 | #set_property IOSTANDARD LVCMOS33 [get_ports {JA[6]}] 146 | ##Sch name = JA10 147 | #set_property PACKAGE_PIN G3 [get_ports {JA[7]}] 148 | #set_property IOSTANDARD LVCMOS33 [get_ports {JA[7]}] 149 | 150 | 151 | 152 | ##Pmod Header JB 153 | ##Sch name = JB1 154 | #set_property PACKAGE_PIN A14 [get_ports {JB[0]}] 155 | #set_property IOSTANDARD LVCMOS33 [get_ports {JB[0]}] 156 | ##Sch name = JB2 157 | #set_property PACKAGE_PIN A16 [get_ports {JB[1]}] 158 | #set_property IOSTANDARD LVCMOS33 [get_ports {JB[1]}] 159 | ##Sch name = JB3 160 | #set_property PACKAGE_PIN B15 [get_ports {JB[2]}] 161 | #set_property IOSTANDARD LVCMOS33 [get_ports {JB[2]}] 162 | ##Sch name = JB4 163 | #set_property PACKAGE_PIN B16 [get_ports {JB[3]}] 164 | #set_property IOSTANDARD LVCMOS33 [get_ports {JB[3]}] 165 | ##Sch name = JB7 166 | #set_property PACKAGE_PIN A15 [get_ports {JB[4]}] 167 | #set_property IOSTANDARD LVCMOS33 [get_ports {JB[4]}] 168 | ##Sch name = JB8 169 | #set_property PACKAGE_PIN A17 [get_ports {JB[5]}] 170 | #set_property IOSTANDARD LVCMOS33 [get_ports {JB[5]}] 171 | ##Sch name = JB9 172 | #set_property PACKAGE_PIN C15 [get_ports {JB[6]}] 173 | #set_property IOSTANDARD LVCMOS33 [get_ports {JB[6]}] 174 | ##Sch name = JB10 175 | #set_property PACKAGE_PIN C16 [get_ports {JB[7]}] 176 | #set_property IOSTANDARD LVCMOS33 [get_ports {JB[7]}] 177 | 178 | 179 | 180 | ##Pmod Header JC 181 | ##Sch name = JC1 182 | #set_property PACKAGE_PIN K17 [get_ports {JC[0]}] 183 | #set_property IOSTANDARD LVCMOS33 [get_ports {JC[0]}] 184 | ##Sch name = JC2 185 | #set_property PACKAGE_PIN M18 [get_ports {JC[1]}] 186 | #set_property IOSTANDARD LVCMOS33 [get_ports {JC[1]}] 187 | ##Sch name = JC3 188 | #set_property PACKAGE_PIN N17 [get_ports {JC[2]}] 189 | #set_property IOSTANDARD LVCMOS33 [get_ports {JC[2]}] 190 | ##Sch name = JC4 191 | #set_property PACKAGE_PIN P18 [get_ports {JC[3]}] 192 | #set_property IOSTANDARD LVCMOS33 [get_ports {JC[3]}] 193 | ##Sch name = JC7 194 | #set_property PACKAGE_PIN L17 [get_ports {JC[4]}] 195 | #set_property IOSTANDARD LVCMOS33 [get_ports {JC[4]}] 196 | ##Sch name = JC8 197 | #set_property PACKAGE_PIN M19 [get_ports {JC[5]}] 198 | #set_property IOSTANDARD LVCMOS33 [get_ports {JC[5]}] 199 | ##Sch name = JC9 200 | #set_property PACKAGE_PIN P17 [get_ports {JC[6]}] 201 | #set_property IOSTANDARD LVCMOS33 [get_ports {JC[6]}] 202 | ##Sch name = JC10 203 | #set_property PACKAGE_PIN R18 [get_ports {JC[7]}] 204 | #set_property IOSTANDARD LVCMOS33 [get_ports {JC[7]}] 205 | 206 | 207 | #Pmod Header JXADC 208 | #Sch name = XA1_P 209 | set_property PACKAGE_PIN J3 [get_ports {vauxp6}] 210 | set_property IOSTANDARD LVCMOS33 [get_ports {vauxp6}] 211 | #Sch name = XA2_P 212 | set_property PACKAGE_PIN L3 [get_ports {vauxp14}] 213 | set_property IOSTANDARD LVCMOS33 [get_ports {vauxp14}] 214 | #Sch name = XA3_P 215 | set_property PACKAGE_PIN M2 [get_ports {vauxp7}] 216 | set_property IOSTANDARD LVCMOS33 [get_ports {vauxp7}] 217 | #Sch name = XA4_P 218 | set_property PACKAGE_PIN N2 [get_ports {vauxp15}] 219 | set_property IOSTANDARD LVCMOS33 [get_ports {vauxp15}] 220 | #Sch name = XA1_N 221 | set_property PACKAGE_PIN K3 [get_ports {vauxn6}] 222 | set_property IOSTANDARD LVCMOS33 [get_ports {vauxn6}] 223 | #Sch name = XA2_N 224 | set_property PACKAGE_PIN M3 [get_ports {vauxn14}] 225 | set_property IOSTANDARD LVCMOS33 [get_ports {vauxn14}] 226 | #Sch name = XA3_N 227 | set_property PACKAGE_PIN M1 [get_ports {vauxn7}] 228 | set_property IOSTANDARD LVCMOS33 [get_ports {vauxn7}] 229 | #Sch name = XA4_N 230 | set_property PACKAGE_PIN N1 [get_ports {vauxn15}] 231 | set_property IOSTANDARD LVCMOS33 [get_ports {vauxn15}] 232 | 233 | 234 | 235 | ##VGA Connector 236 | #set_property PACKAGE_PIN G19 [get_ports {vgaRed[0]}] 237 | #set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[0]}] 238 | #set_property PACKAGE_PIN H19 [get_ports {vgaRed[1]}] 239 | #set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[1]}] 240 | #set_property PACKAGE_PIN J19 [get_ports {vgaRed[2]}] 241 | #set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[2]}] 242 | #set_property PACKAGE_PIN N19 [get_ports {vgaRed[3]}] 243 | #set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[3]}] 244 | #set_property PACKAGE_PIN N18 [get_ports {vgaBlue[0]}] 245 | #set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[0]}] 246 | #set_property PACKAGE_PIN L18 [get_ports {vgaBlue[1]}] 247 | #set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[1]}] 248 | #set_property PACKAGE_PIN K18 [get_ports {vgaBlue[2]}] 249 | #set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[2]}] 250 | #set_property PACKAGE_PIN J18 [get_ports {vgaBlue[3]}] 251 | #set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[3]}] 252 | #set_property PACKAGE_PIN J17 [get_ports {vgaGreen[0]}] 253 | #set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[0]}] 254 | #set_property PACKAGE_PIN H17 [get_ports {vgaGreen[1]}] 255 | #set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[1]}] 256 | #set_property PACKAGE_PIN G17 [get_ports {vgaGreen[2]}] 257 | #set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[2]}] 258 | #set_property PACKAGE_PIN D17 [get_ports {vgaGreen[3]}] 259 | #set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[3]}] 260 | #set_property PACKAGE_PIN P19 [get_ports Hsync] 261 | #set_property IOSTANDARD LVCMOS33 [get_ports Hsync] 262 | #set_property PACKAGE_PIN R19 [get_ports Vsync] 263 | #set_property IOSTANDARD LVCMOS33 [get_ports Vsync] 264 | 265 | 266 | ##USB-RS232 Interface 267 | #set_property PACKAGE_PIN B18 [get_ports RsRx] 268 | #set_property IOSTANDARD LVCMOS33 [get_ports RsRx] 269 | #set_property PACKAGE_PIN A18 [get_ports RsTx] 270 | #set_property IOSTANDARD LVCMOS33 [get_ports RsTx] 271 | 272 | 273 | ##USB HID (PS/2) 274 | #set_property PACKAGE_PIN C17 [get_ports PS2Clk] 275 | #set_property IOSTANDARD LVCMOS33 [get_ports PS2Clk] 276 | #set_property PULLUP true [get_ports PS2Clk] 277 | #set_property PACKAGE_PIN B17 [get_ports PS2Data] 278 | #set_property IOSTANDARD LVCMOS33 [get_ports PS2Data] 279 | #set_property PULLUP true [get_ports PS2Data] 280 | 281 | 282 | ##Quad SPI Flash 283 | ##Note that CCLK_0 cannot be placed in 7 series devices. You can access it using the 284 | ##STARTUPE2 primitive. 285 | #set_property PACKAGE_PIN D18 [get_ports {QspiDB[0]}] 286 | #set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[0]}] 287 | #set_property PACKAGE_PIN D19 [get_ports {QspiDB[1]}] 288 | #set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[1]}] 289 | #set_property PACKAGE_PIN G18 [get_ports {QspiDB[2]}] 290 | #set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[2]}] 291 | #set_property PACKAGE_PIN F18 [get_ports {QspiDB[3]}] 292 | #set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[3]}] 293 | #set_property PACKAGE_PIN K19 [get_ports QspiCSn] 294 | #set_property IOSTANDARD LVCMOS33 [get_ports QspiCSn] 295 | 296 | -------------------------------------------------------------------------------- /Projects/XADC_Demo/src/hdl/DigitToSeg.v: -------------------------------------------------------------------------------- 1 | //////////////////////////////////////////////////////////////////////////////// 2 | // Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. 3 | //////////////////////////////////////////////////////////////////////////////// 4 | // ____ ____ 5 | // / /\/ / 6 | // /___/ \ / Vendor: Xilinx 7 | // \ \ \/ Version : 14.7 8 | // \ \ Application : sch2hdl 9 | // / / Filename : Top.vf 10 | // /___/ /\ Timestamp : 12/01/2014 17:59:05 11 | // \ \ / \ 12 | // \___\/\___\ 13 | // 14 | //Command: sch2hdl -intstyle ise -family spartan3e -verilog C:/Users/samue_000/Documents/FPGA/Projects/Stopwatch/sevensegdecoder/Top.vf -w C:/Users/samue_000/Documents/FPGA/Projects/Stopwatch/sevensegdecoder/Top.sch 15 | //Design Name: Top 16 | //Device: spartan3e 17 | //Purpose: 18 | // This verilog netlist is translated from an ECS schematic.It can be 19 | // synthesized and simulated, but it should not be modified. 20 | // 21 | `timescale 1ns / 1ps 22 | 23 | module DigitToSeg(in1, 24 | in2, 25 | in3, 26 | in4, 27 | in5, 28 | in6, 29 | in7, 30 | in8, 31 | mclk, 32 | an, 33 | dp, 34 | seg); 35 | 36 | input [3:0] in1; 37 | input [3:0] in2; 38 | input [3:0] in3; 39 | input [3:0] in4; 40 | input [3:0] in5; 41 | input [3:0] in6; 42 | input [3:0] in7; 43 | input [3:0] in8; 44 | input mclk; 45 | output [3:0] an; 46 | output [6:0] seg; 47 | output dp; 48 | 49 | //wire swt7; 50 | wire XLXN_94; 51 | wire [3:0] XLXN_102; 52 | wire [2:0] XLXN_109; 53 | 54 | sevensegdecoder XLXI_6 (.nIn(XLXN_102[3:0]), 55 | .ssOut(seg[6:0])); 56 | mux4_4bus XLXI_45 (.I0(in1[3:0]), 57 | .I1(in2[3:0]), 58 | .I2(in3[3:0]), 59 | .I3(in4[3:0]), 60 | .I4(in5[3:0]), 61 | .I5(in6[3:0]), 62 | .I6(in7[3:0]), 63 | .I7(in8[3:0]), 64 | .Sel(XLXN_109[2:0]), 65 | .Y(XLXN_102[3:0])); 66 | 67 | segClkDevider XLXI_47 (.clk(mclk), 68 | .rst(), 69 | .clk_div(XLXN_94)); 70 | 71 | //GND XLXI_48 (.G(swt7)); 72 | counter3bit XLXI_49 (.clk(XLXN_94), 73 | .rst(), 74 | .Q(XLXN_109[2:0])); 75 | decoder_3_8 XLXI_50 (.I(XLXN_109[2:0]), 76 | .dp(dp), 77 | .an(an[3:0])); 78 | 79 | 80 | endmodule 81 | -------------------------------------------------------------------------------- /Projects/XADC_Demo/src/hdl/UART_TX_CTRL.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------------------- 2 | -- UART_TX_CTRL.vhd -- UART Data Transfer Component 3 | ---------------------------------------------------------------------------- 4 | -- Author: Sam Bobrowicz 5 | -- Copyright 2011 Digilent, Inc. 6 | ---------------------------------------------------------------------------- 7 | -- 8 | ---------------------------------------------------------------------------- 9 | -- This component may be used to transfer data over a UART device. It will 10 | -- serialize a byte of data and transmit it over a TXD line. The serialized 11 | -- data has the following characteristics: 12 | -- *9600 Baud Rate 13 | -- *8 data bits, LSB first 14 | -- *1 stop bit 15 | -- *no parity 16 | -- 17 | -- Port Descriptions: 18 | -- 19 | -- SEND - Used to trigger a send operation. The upper layer logic should 20 | -- set this signal high for a single clock cycle to trigger a 21 | -- send. When this signal is set high DATA must be valid . Should 22 | -- not be asserted unless READY is high. 23 | -- DATA - The parallel data to be sent. Must be valid the clock cycle 24 | -- that SEND has gone high. 25 | -- CLK - A 100 MHz clock is expected 26 | -- READY - This signal goes low once a send operation has begun and 27 | -- remains low until it has completed and the module is ready to 28 | -- send another byte. 29 | -- UART_TX - This signal should be routed to the appropriate TX pin of the 30 | -- external UART device. 31 | -- 32 | ---------------------------------------------------------------------------- 33 | -- 34 | ---------------------------------------------------------------------------- 35 | -- Revision History: 36 | -- 08/08/2011(SamB): Created using Xilinx Tools 13.2 37 | ---------------------------------------------------------------------------- 38 | library IEEE; 39 | use IEEE.STD_LOGIC_1164.ALL; 40 | use IEEE.std_logic_unsigned.all; 41 | 42 | entity UART_TX_CTRL is 43 | Port ( SEND : in STD_LOGIC; 44 | DATA : in STD_LOGIC_VECTOR (7 downto 0); 45 | CLK : in STD_LOGIC; 46 | READY : out STD_LOGIC; 47 | UART_TX : out STD_LOGIC); 48 | end UART_TX_CTRL; 49 | 50 | architecture Behavioral of UART_TX_CTRL is 51 | 52 | type TX_STATE_TYPE is (RDY, LOAD_BIT, SEND_BIT); 53 | 54 | constant BIT_TMR_MAX : std_logic_vector(13 downto 0) := "10100010110000"; --10416 = (round(100MHz / 9600)) - 1 55 | constant BIT_INDEX_MAX : natural := 10; 56 | 57 | --Counter that keeps track of the number of clock cycles the current bit has been held stable over the 58 | --UART TX line. It is used to signal when the ne 59 | signal bitTmr : std_logic_vector(13 downto 0) := (others => '0'); 60 | 61 | --combinatorial logic that goes high when bitTmr has counted to the proper value to ensure 62 | --a 9600 baud rate 63 | signal bitDone : std_logic; 64 | 65 | --Contains the index of the next bit in txData that needs to be transferred 66 | signal bitIndex : natural; 67 | 68 | --a register that holds the current data being sent over the UART TX line 69 | signal txBit : std_logic := '1'; 70 | 71 | --A register that contains the whole data packet to be sent, including start and stop bits. 72 | signal txData : std_logic_vector(9 downto 0); 73 | 74 | signal txState : TX_STATE_TYPE := RDY; 75 | 76 | begin 77 | 78 | --Next state logic 79 | next_txState_process : process (CLK) 80 | begin 81 | if (rising_edge(CLK)) then 82 | case txState is 83 | when RDY => 84 | if (SEND = '1') then 85 | txState <= LOAD_BIT; 86 | end if; 87 | when LOAD_BIT => 88 | txState <= SEND_BIT; 89 | when SEND_BIT => 90 | if (bitDone = '1') then 91 | if (bitIndex = BIT_INDEX_MAX) then 92 | txState <= RDY; 93 | else 94 | txState <= LOAD_BIT; 95 | end if; 96 | end if; 97 | when others=> --should never be reached 98 | txState <= RDY; 99 | end case; 100 | end if; 101 | end process; 102 | 103 | bit_timing_process : process (CLK) 104 | begin 105 | if (rising_edge(CLK)) then 106 | if (txState = RDY) then 107 | bitTmr <= (others => '0'); 108 | else 109 | if (bitDone = '1') then 110 | bitTmr <= (others => '0'); 111 | else 112 | bitTmr <= bitTmr + 1; 113 | end if; 114 | end if; 115 | end if; 116 | end process; 117 | 118 | bitDone <= '1' when (bitTmr = BIT_TMR_MAX) else 119 | '0'; 120 | 121 | bit_counting_process : process (CLK) 122 | begin 123 | if (rising_edge(CLK)) then 124 | if (txState = RDY) then 125 | bitIndex <= 0; 126 | elsif (txState = LOAD_BIT) then 127 | bitIndex <= bitIndex + 1; 128 | end if; 129 | end if; 130 | end process; 131 | 132 | tx_data_latch_process : process (CLK) 133 | begin 134 | if (rising_edge(CLK)) then 135 | if (SEND = '1') then 136 | txData <= '1' & DATA & '0'; 137 | end if; 138 | end if; 139 | end process; 140 | 141 | tx_bit_process : process (CLK) 142 | begin 143 | if (rising_edge(CLK)) then 144 | if (txState = RDY) then 145 | txBit <= '1'; 146 | elsif (txState = LOAD_BIT) then 147 | txBit <= txData(bitIndex); 148 | end if; 149 | end if; 150 | end process; 151 | 152 | UART_TX <= txBit; 153 | READY <= '1' when (txState = RDY) else 154 | '0'; 155 | 156 | end Behavioral; 157 | 158 | -------------------------------------------------------------------------------- /Projects/XADC_Demo/src/hdl/XADCdemo.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 02/12/2015 03:26:51 PM 7 | // Design Name: 8 | // Module Name: // Project Name: 9 | // Target Devices: 10 | // Tool Versions: 11 | // Description: 12 | // 13 | // Dependencies: 14 | // 15 | // Revision: 16 | // Revision 0.01 - File Created 17 | // Additional Comments: 18 | // 19 | ////////////////////////////////////////////////////////////////////////////////// 20 | 21 | 22 | module XADCdemo( 23 | input CLK100MHZ, 24 | input vauxp6, 25 | input vauxn6, 26 | input vauxp7, 27 | input vauxn7, 28 | input vauxp15, 29 | input vauxn15, 30 | input vauxp14, 31 | input vauxn14, 32 | input [1:0] sw, 33 | output reg [15:0] LED, 34 | output [3:0] an, 35 | output dp, 36 | output [6:0] seg 37 | ); 38 | 39 | wire enable; 40 | wire ready; 41 | wire [15:0] data; 42 | reg [6:0] Address_in; 43 | reg [32:0] decimal; 44 | reg [3:0] dig0; 45 | reg [3:0] dig1; 46 | reg [3:0] dig2; 47 | reg [3:0] dig3; 48 | reg [3:0] dig4; 49 | reg [3:0] dig5; 50 | reg [3:0] dig6; 51 | 52 | 53 | 54 | 55 | //xadc instantiation connect the eoc_out .den_in to get continuous conversion 56 | xadc_wiz_0 XLXI_7 (.daddr_in(Address_in), //addresses can be found in the artix 7 XADC user guide DRP register space 57 | .dclk_in(CLK100MHZ), 58 | .den_in(enable), 59 | .di_in(), 60 | .dwe_in(), 61 | .busy_out(), 62 | .vauxp6(vauxp6), 63 | .vauxn6(vauxn6), 64 | .vauxp7(vauxp7), 65 | .vauxn7(vauxn7), 66 | .vauxp14(vauxp14), 67 | .vauxn14(vauxn14), 68 | .vauxp15(vauxp15), 69 | .vauxn15(vauxn15), 70 | .vn_in(), 71 | .vp_in(), 72 | .alarm_out(), 73 | .do_out(data), 74 | //.reset_in(), 75 | .eoc_out(enable), 76 | .channel_out(), 77 | .drdy_out(ready)); 78 | 79 | 80 | 81 | //led visual dmm 82 | always @( posedge(CLK100MHZ)) 83 | begin 84 | if(ready == 1'b1) 85 | begin 86 | case (data[15:12]) 87 | 1: LED <= 16'b11; 88 | 2: LED <= 16'b111; 89 | 3: LED <= 16'b1111; 90 | 4: LED <= 16'b11111; 91 | 5: LED <= 16'b111111; 92 | 6: LED <= 16'b1111111; 93 | 7: LED <= 16'b11111111; 94 | 8: LED <= 16'b111111111; 95 | 9: LED <= 16'b1111111111; 96 | 10: LED <= 16'b11111111111; 97 | 11: LED <= 16'b111111111111; 98 | 12: LED <= 16'b1111111111111; 99 | 13: LED <= 16'b11111111111111; 100 | 14: LED <= 16'b111111111111111; 101 | 15: LED <= 16'b1111111111111111; 102 | default: LED <= 16'b1; 103 | endcase 104 | end 105 | 106 | 107 | end 108 | 109 | reg [32:0] count; 110 | //binary to decimal conversion 111 | always @ (posedge(CLK100MHZ)) 112 | begin 113 | 114 | if(count == 10000000)begin 115 | 116 | decimal = data >> 4; 117 | //looks nicer if our max value is 1V instead of .999755 118 | if(decimal >= 4093) 119 | begin 120 | dig0 = 0; 121 | dig1 = 0; 122 | dig2 = 0; 123 | dig3 = 0; 124 | dig4 = 0; 125 | dig5 = 0; 126 | dig6 = 1; 127 | count = 0; 128 | end 129 | else 130 | begin 131 | decimal = decimal * 250000; 132 | decimal = decimal >> 10; 133 | 134 | 135 | dig0 = decimal % 10; 136 | decimal = decimal / 10; 137 | 138 | dig1 = decimal % 10; 139 | decimal = decimal / 10; 140 | 141 | dig2 = decimal % 10; 142 | decimal = decimal / 10; 143 | 144 | dig3 = decimal % 10; 145 | decimal = decimal / 10; 146 | 147 | dig4 = decimal % 10; 148 | decimal = decimal / 10; 149 | 150 | dig5 = decimal % 10; 151 | decimal = decimal / 10; 152 | 153 | dig6 = decimal % 10; 154 | decimal = decimal / 10; 155 | 156 | count = 0; 157 | end 158 | end 159 | 160 | count = count + 1; 161 | 162 | end 163 | 164 | always @(posedge(CLK100MHZ)) 165 | begin 166 | case(sw) 167 | 0: Address_in <= 8'h16; 168 | 1: Address_in <= 8'h17; 169 | 2: Address_in <= 8'h1e; 170 | 3: Address_in <= 8'h1f; 171 | endcase 172 | 173 | 174 | end 175 | 176 | DigitToSeg segment1(.in1(dig3), 177 | .in2(dig4), 178 | .in3(dig5), 179 | .in4(dig6), 180 | .in5(), 181 | .in6(), 182 | .in7(), 183 | .in8(), 184 | .mclk(CLK100MHZ), 185 | .an(an), 186 | .dp(dp), 187 | .seg(seg)); 188 | endmodule 189 | -------------------------------------------------------------------------------- /Projects/XADC_Demo/src/hdl/counter3bit.v: -------------------------------------------------------------------------------- 1 | module counter3bit ( 2 | input clk, 3 | input rst, 4 | output reg [2:0] Q 5 | ); 6 | 7 | always @ (posedge(clk)) // When will Always Block Be Triggered 8 | begin 9 | if (rst == 3'b111) 10 | // How Output reacts when Reset Is Asserted 11 | Q <= 3'b0; 12 | else 13 | // How Output reacts when Rising Edge of Clock Arrives? 14 | Q <= Q + 1'b1; 15 | end 16 | 17 | endmodule 18 | -------------------------------------------------------------------------------- /Projects/XADC_Demo/src/hdl/decoder3_8.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 00:48:27 09/09/2014 7 | // Design Name: 8 | // Module Name: decoder3_8 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module decoder_3_8 ( 22 | input [2:0] I, 23 | output [3:0] an, 24 | output dp 25 | ); 26 | 27 | assign an[0] = ~(~I[2] & ~I[1] & ~I[0]); 28 | assign an[1] = ~(~I[2] & ~I[1] & I[0]); 29 | 30 | assign an[2] = ~(~I[2] & I[1] & ~I[0]); 31 | assign an[3] = ~(~I[2] & I[1] & I[0]); 32 | 33 | //assign an[4] = ~(I[2] & ~I[1] & ~I[0]); 34 | //assign an[5] = ~(I[2] & ~I[1] & I[0]); 35 | //assign an[6] = ~(I[2] & I[1] & ~I[0]); 36 | //assign an[7] = ~(I[2] & I[1] & I[0]); 37 | 38 | //decimal place 39 | assign dp = ~(~I[2] & I[1] & I[0]); 40 | 41 | endmodule 42 | -------------------------------------------------------------------------------- /Projects/XADC_Demo/src/hdl/mux4_4bus.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 02:26:40 09/09/2014 7 | // Design Name: 8 | // Module Name: mux2_1bus 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module mux4_4bus( 22 | input [3:0] I0, 23 | input [3:0] I1, 24 | input [3:0] I2, 25 | input [3:0] I3, 26 | 27 | input [3:0] I4, 28 | input [3:0] I5, 29 | input [3:0] I6, 30 | input [3:0] I7, 31 | 32 | input [2:0] Sel, 33 | output [3:0] Y 34 | ); 35 | 36 | 37 | assign Y = ( Sel == 0 )? I0 : ( Sel == 1 )? I1 : ( Sel == 2 )? I2 : ( Sel == 3 )? I3 : ( Sel == 4 )? I4 :( Sel == 5 )? I5 :( Sel == 6 )? I6 : I7; 38 | 39 | endmodule 40 | -------------------------------------------------------------------------------- /Projects/XADC_Demo/src/hdl/segClkDevider.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 02:03:00 09/16/2014 7 | // Design Name: 8 | // Module Name: segClkDevider 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module segClkDevider( 22 | input clk, 23 | input rst, 24 | output reg clk_div 25 | ); 26 | 27 | localparam constantNumber = 10000; 28 | reg [31:0] count; 29 | 30 | always @ (posedge(clk), posedge(rst)) 31 | begin 32 | if (rst == 1'b1) 33 | count <= 32'b0; 34 | else if (count == constantNumber - 1) 35 | count <= 32'b0; 36 | else 37 | count <= count + 1; 38 | end 39 | 40 | always @ (posedge(clk), posedge(rst)) 41 | begin 42 | if (rst == 1'b1) 43 | clk_div <= 1'b0; 44 | else if (count == constantNumber - 1) 45 | clk_div <= ~clk_div; 46 | else 47 | clk_div <= clk_div; 48 | end 49 | endmodule -------------------------------------------------------------------------------- /Projects/XADC_Demo/src/hdl/sevensegdecoder.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 01:55:33 09/09/2014 7 | // Design Name: 8 | // Module Name: sevensegdecoder 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module sevensegdecoder( 22 | 23 | input [3:0] nIn, 24 | output reg [6:0] ssOut 25 | ); 26 | 27 | always @(nIn) 28 | case (nIn) 29 | 4'h0: ssOut = 7'b1000000; 30 | 4'h1: ssOut = 7'b1111001; 31 | 4'h2: ssOut = 7'b0100100; 32 | 4'h3: ssOut = 7'b0110000; 33 | 4'h4: ssOut = 7'b0011001; 34 | 4'h5: ssOut = 7'b0010010; 35 | 4'h6: ssOut = 7'b0000010; 36 | 4'h7: ssOut = 7'b1111000; 37 | 4'h8: ssOut = 7'b0000000; 38 | 4'h9: ssOut = 7'b0011000; 39 | 4'hA: ssOut = 7'b0001000; 40 | 4'hB: ssOut = 7'b0000011; 41 | 4'hC: ssOut = 7'b1000110; 42 | 4'hD: ssOut = 7'b0100001; 43 | 4'hE: ssOut = 7'b0000110; 44 | 4'hF: ssOut = 7'b0001110; 45 | default: ssOut = 7'b1001001; 46 | endcase 47 | 48 | endmodule 49 | -------------------------------------------------------------------------------- /Projects/XADC_Demo/src/ip/xadc_wiz_0_1/xadc_wiz_0.dcp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Digilent/Basys3/97c14a4f2f6d22047432c8752325a9aff83fa210/Projects/XADC_Demo/src/ip/xadc_wiz_0_1/xadc_wiz_0.dcp -------------------------------------------------------------------------------- /Projects/XADC_Demo/src/ip/xadc_wiz_0_1/xadc_wiz_0.upgrade_log: -------------------------------------------------------------------------------- 1 | Copyright 1986-2015 Xilinx, Inc. All Rights Reserved. 2 | ------------------------------------------------------------------------------------ 3 | | Tool Version : Vivado v.2015.1 (win64) Build 1215546 Mon Apr 27 19:22:08 MDT 2015 4 | | Date : Tue Jun 30 08:16:44 2015 5 | | Host : Sparky running 64-bit Service Pack 1 (build 7601) 6 | | Command : upgrade_ip 7 | | Device : xc7a35tcpg236-1 8 | ------------------------------------------------------------------------------------ 9 | 10 | Upgrade Log for IP 'xadc_wiz_0' 11 | 12 | 1. Summary 13 | ---------- 14 | 15 | SUCCESS in the upgrade of xadc_wiz_0 (xilinx.com:ip:xadc_wiz:3.0) from (Rev. 6) to (Rev. 7) 16 | 17 | -------------------------------------------------------------------------------- /Projects/XADC_Demo/src/ip/xadc_wiz_0_1/xadc_wiz_0.vhd: -------------------------------------------------------------------------------- 1 | -- file: xadc_wiz_0.vhd 2 | -- (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved. 3 | -- 4 | -- This file contains confidential and proprietary information 5 | -- of Xilinx, Inc. and is protected under U.S. and 6 | -- international copyright and other intellectual property 7 | -- laws. 8 | -- 9 | -- DISCLAIMER 10 | -- This disclaimer is not a license and does not grant any 11 | -- rights to the materials distributed herewith. Except as 12 | -- otherwise provided in a valid license issued to you by 13 | -- Xilinx, and to the maximum extent permitted by applicable 14 | -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 15 | -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 16 | -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 17 | -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 18 | -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 19 | -- (2) Xilinx shall not be liable (whether in contract or tort, 20 | -- including negligence, or under any other theory of 21 | -- liability) for any loss or damage of any kind or nature 22 | -- related to, arising under or in connection with these 23 | -- materials, including for any direct, or any indirect, 24 | -- special, incidental, or consequential loss or damage 25 | -- (including loss of data, profits, goodwill, or any type of 26 | -- loss or damage suffered as a result of any action brought 27 | -- by a third party) even if such damage or loss was 28 | -- reasonably foreseeable or Xilinx had been advised of the 29 | -- possibility of the same. 30 | -- 31 | -- CRITICAL APPLICATIONS 32 | -- Xilinx products are not designed or intended to be fail- 33 | -- safe, or for use in any application requiring fail-safe 34 | -- performance, such as life-support or safety devices or 35 | -- systems, Class III medical devices, nuclear facilities, 36 | -- applications related to the deployment of airbags, or any 37 | -- other applications that could lead to death, personal 38 | -- injury, or severe property or environmental damage 39 | -- (individually and collectively, "Critical 40 | -- Applications"). Customer assumes the sole risk and 41 | -- liability of any use of Xilinx products in Critical 42 | -- Applications, subject only to applicable laws and 43 | -- regulations governing limitations on product liability. 44 | -- 45 | -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 46 | -- PART OF THIS FILE AT ALL TIMES. 47 | 48 | library ieee; 49 | use ieee.std_logic_1164.all; 50 | use ieee.numeric_std.all; 51 | Library UNISIM; 52 | use UNISIM.VCOMPONENTS.ALL; 53 | 54 | entity xadc_wiz_0 is 55 | port 56 | ( 57 | daddr_in : in STD_LOGIC_VECTOR (6 downto 0); -- Address bus for the dynamic reconfiguration port 58 | den_in : in STD_LOGIC; -- Enable Signal for the dynamic reconfiguration port 59 | di_in : in STD_LOGIC_VECTOR (15 downto 0); -- Input data bus for the dynamic reconfiguration port 60 | dwe_in : in STD_LOGIC; -- Write Enable for the dynamic reconfiguration port 61 | do_out : out STD_LOGIC_VECTOR (15 downto 0); -- Output data bus for dynamic reconfiguration port 62 | drdy_out : out STD_LOGIC; -- Data ready signal for the dynamic reconfiguration port 63 | dclk_in : in STD_LOGIC; -- Clock input for the dynamic reconfiguration port 64 | vauxp6 : in STD_LOGIC; -- Auxiliary Channel 6 65 | vauxn6 : in STD_LOGIC; 66 | vauxp7 : in STD_LOGIC; -- Auxiliary Channel 7 67 | vauxn7 : in STD_LOGIC; 68 | vauxp14 : in STD_LOGIC; -- Auxiliary Channel 14 69 | vauxn14 : in STD_LOGIC; 70 | vauxp15 : in STD_LOGIC; -- Auxiliary Channel 15 71 | vauxn15 : in STD_LOGIC; 72 | busy_out : out STD_LOGIC; -- ADC Busy signal 73 | channel_out : out STD_LOGIC_VECTOR (4 downto 0); -- Channel Selection Outputs 74 | eoc_out : out STD_LOGIC; -- End of Conversion Signal 75 | eos_out : out STD_LOGIC; -- End of Sequence Signal 76 | alarm_out : out STD_LOGIC; -- OR'ed output of all the Alarms 77 | vp_in : in STD_LOGIC; -- Dedicated Analog Input Pair 78 | vn_in : in STD_LOGIC 79 | ); 80 | end xadc_wiz_0; 81 | 82 | architecture xilinx of xadc_wiz_0 is 83 | 84 | attribute CORE_GENERATION_INFO : string; 85 | attribute CORE_GENERATION_INFO of xilinx : architecture is "xadc_wiz_0,xadc_wiz_v3_0,{component_name=xadc_wiz_0,enable_axi=false,enable_axi4stream=false,dclk_frequency=100,enable_busy=true,enable_convst=false,enable_convstclk=false,enable_dclk=true,enable_drp=true,enable_eoc=true,enable_eos=true,enable_vbram_alaram=false,enable_vccddro_alaram=false,enable_Vccint_Alaram=false,enable_Vccaux_alaram=falseenable_vccpaux_alaram=false,enable_vccpint_alaram=false,ot_alaram=false,user_temp_alaram=false,timing_mode=continuous,channel_averaging=None,sequencer_mode=on,startup_channel_selection=contineous_sequence}"; 86 | 87 | 88 | signal FLOAT_VCCAUX_ALARM : std_logic; 89 | signal FLOAT_VCCINT_ALARM : std_logic; 90 | signal FLOAT_USER_TEMP_ALARM : std_logic; 91 | signal FLOAT_VBRAM_ALARM : std_logic; 92 | signal FLOAT_MUXADDR : std_logic_vector (4 downto 0); 93 | signal aux_channel_p : std_logic_vector (15 downto 0); 94 | signal aux_channel_n : std_logic_vector (15 downto 0); 95 | signal alm_int : std_logic_vector (7 downto 0); 96 | 97 | begin 98 | 99 | alarm_out <= alm_int(7); 100 | 101 | aux_channel_p(0) <= '0'; 102 | aux_channel_n(0) <= '0'; 103 | 104 | aux_channel_p(1) <= '0'; 105 | aux_channel_n(1) <= '0'; 106 | 107 | aux_channel_p(2) <= '0'; 108 | aux_channel_n(2) <= '0'; 109 | 110 | aux_channel_p(3) <= '0'; 111 | aux_channel_n(3) <= '0'; 112 | 113 | aux_channel_p(4) <= '0'; 114 | aux_channel_n(4) <= '0'; 115 | 116 | aux_channel_p(5) <= '0'; 117 | aux_channel_n(5) <= '0'; 118 | 119 | aux_channel_p(6) <= vauxp6; 120 | aux_channel_n(6) <= vauxn6; 121 | 122 | aux_channel_p(7) <= vauxp7; 123 | aux_channel_n(7) <= vauxn7; 124 | 125 | aux_channel_p(8) <= '0'; 126 | aux_channel_n(8) <= '0'; 127 | 128 | aux_channel_p(9) <= '0'; 129 | aux_channel_n(9) <= '0'; 130 | 131 | aux_channel_p(10) <= '0'; 132 | aux_channel_n(10) <= '0'; 133 | 134 | aux_channel_p(11) <= '0'; 135 | aux_channel_n(11) <= '0'; 136 | 137 | aux_channel_p(12) <= '0'; 138 | aux_channel_n(12) <= '0'; 139 | 140 | aux_channel_p(13) <= '0'; 141 | aux_channel_n(13) <= '0'; 142 | 143 | aux_channel_p(14) <= vauxp14; 144 | aux_channel_n(14) <= vauxn14; 145 | 146 | aux_channel_p(15) <= vauxp15; 147 | aux_channel_n(15) <= vauxn15; 148 | 149 | U0 : XADC 150 | generic map( 151 | INIT_40 => X"0000", -- config reg 0 152 | INIT_41 => X"210F", -- config reg 1 153 | INIT_42 => X"0400", -- config reg 2 154 | INIT_48 => X"0000", -- Sequencer channel selection 155 | INIT_49 => X"C0C0", -- Sequencer channel selection 156 | INIT_4A => X"0000", -- Sequencer Average selection 157 | INIT_4B => X"0000", -- Sequencer Average selection 158 | INIT_4C => X"0000", -- Sequencer Bipolar selection 159 | INIT_4D => X"0000", -- Sequencer Bipolar selection 160 | INIT_4E => X"0000", -- Sequencer Acq time selection 161 | INIT_4F => X"0000", -- Sequencer Acq time selection 162 | INIT_50 => X"B5ED", -- Temp alarm trigger 163 | INIT_51 => X"57E4", -- Vccint upper alarm limit 164 | INIT_52 => X"A147", -- Vccaux upper alarm limit 165 | INIT_53 => X"CA33", -- Temp alarm OT upper 166 | INIT_54 => X"A93A", -- Temp alarm reset 167 | INIT_55 => X"52C6", -- Vccint lower alarm limit 168 | INIT_56 => X"9555", -- Vccaux lower alarm limit 169 | INIT_57 => X"AE4E", -- Temp alarm OT reset 170 | INIT_58 => X"5999", -- Vccbram upper alarm limit 171 | INIT_5C => X"5111", -- Vccbram lower alarm limit 172 | SIM_DEVICE => "7SERIES", 173 | SIM_MONITOR_FILE => "c:/Users/Nate/Desktop/work/GitProject/Demos/DemoTest/Basys3/Projects/Basys3_XADC_Demo/src/ip/xadc_wiz_0_1/xadc_wiz_0/simulation/functional/design.txt" 174 | ) 175 | 176 | port map ( 177 | CONVST => '0', 178 | CONVSTCLK => '0', 179 | DADDR(6 downto 0) => daddr_in(6 downto 0), 180 | DCLK => dclk_in, 181 | DEN => den_in, 182 | DI(15 downto 0) => di_in(15 downto 0), 183 | DWE => dwe_in, 184 | RESET => '0', 185 | VAUXN(15 downto 0) => aux_channel_n(15 downto 0), 186 | VAUXP(15 downto 0) => aux_channel_p(15 downto 0), 187 | ALM => alm_int, 188 | BUSY => busy_out, 189 | CHANNEL(4 downto 0) => channel_out(4 downto 0), 190 | DO(15 downto 0) => do_out(15 downto 0), 191 | DRDY => drdy_out, 192 | EOC => eoc_out, 193 | EOS => eos_out, 194 | JTAGBUSY => open, 195 | JTAGLOCKED => open, 196 | JTAGMODIFIED => open, 197 | OT => open, 198 | 199 | MUXADDR => FLOAT_MUXADDR, 200 | VN => vn_in, 201 | VP => vp_in 202 | ); 203 | end xilinx; 204 | 205 | -------------------------------------------------------------------------------- /Projects/XADC_Demo/src/ip/xadc_wiz_0_1/xadc_wiz_0.xdc: -------------------------------------------------------------------------------- 1 | # file: xadc_wiz_0.xdc 2 | # (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved. 3 | # 4 | # This file contains confidential and proprietary information 5 | # of Xilinx, Inc. and is protected under U.S. and 6 | # international copyright and other intellectual property 7 | # laws. 8 | # 9 | # DISCLAIMER 10 | # This disclaimer is not a license and does not grant any 11 | # rights to the materials distributed herewith. Except as 12 | # otherwise provided in a valid license issued to you by 13 | # Xilinx, and to the maximum extent permitted by applicable 14 | # law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 15 | # WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 16 | # AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 17 | # BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 18 | # INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 19 | # (2) Xilinx shall not be liable (whether in contract or tort, 20 | # including negligence, or under any other theory of 21 | # liability) for any loss or damage of any kind or nature 22 | # related to, arising under or in connection with these 23 | # materials, including for any direct, or any indirect, 24 | # special, incidental, or consequential loss or damage 25 | # (including loss of data, profits, goodwill, or any type of 26 | # loss or damage suffered as a result of any action brought 27 | # by a third party) even if such damage or loss was 28 | # reasonably foreseeable or Xilinx had been advised of the 29 | # possibility of the same. 30 | # 31 | # CRITICAL APPLICATIONS 32 | # Xilinx products are not designed or intended to be fail- 33 | # safe, or for use in any application requiring fail-safe 34 | # performance, such as life-support or safety devices or 35 | # systems, Class III medical devices, nuclear facilities, 36 | # applications related to the deployment of airbags, or any 37 | # other applications that could lead to death, personal 38 | # injury, or severe property or environmental damage 39 | # (individually and collectively, "Critical 40 | # Applications"). Customer assumes the sole risk and 41 | # liability of any use of Xilinx products in Critical 42 | # Applications, subject only to applicable laws and 43 | # regulations governing limitations on product liability. 44 | # 45 | # THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 46 | # PART OF THIS FILE AT ALL TIMES. 47 | 48 | 49 | # Input clock periods. These duplicate the values entered for the 50 | # input clocks. You can use these to time your system 51 | #---------------------------------------------------------------- 52 | #create_clock -period 10 [get_ports dclk_in] 53 | -------------------------------------------------------------------------------- /Projects/XADC_Demo/src/ip/xadc_wiz_0_1/xadc_wiz_0_funcsim.v: -------------------------------------------------------------------------------- 1 | // Copyright 1986-2015 Xilinx, Inc. All Rights Reserved. 2 | // -------------------------------------------------------------------------------- 3 | // Tool Version: Vivado v.2015.1 (win64) Build 1215546 Mon Apr 27 19:22:08 MDT 2015 4 | // Date : Sun Oct 18 12:34:43 2015 5 | // Host : Sparky running 64-bit Service Pack 1 (build 7601) 6 | // Command : write_verilog -force -mode funcsim 7 | // C:/Users/Nate/Desktop/work/GitProject/Demos/DemoTest/Basys3/Projects/Basys3_XADC_Demo/src/ip/xadc_wiz_0_1/xadc_wiz_0_funcsim.v 8 | // Design : xadc_wiz_0 9 | // Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified 10 | // or synthesized. This netlist cannot be used for SDF annotated simulation. 11 | // Device : xc7a35tcpg236-1 12 | // -------------------------------------------------------------------------------- 13 | `timescale 1 ps / 1 ps 14 | 15 | (* core_generation_info = "xadc_wiz_0,xadc_wiz_v3_0,{component_name=xadc_wiz_0,enable_axi=false,enable_axi4stream=false,dclk_frequency=100,enable_busy=true,enable_convst=false,enable_convstclk=false,enable_dclk=true,enable_drp=true,enable_eoc=true,enable_eos=true,enable_vbram_alaram=false,enable_vccddro_alaram=false,enable_Vccint_Alaram=false,enable_Vccaux_alaram=falseenable_vccpaux_alaram=false,enable_vccpint_alaram=false,ot_alaram=false,user_temp_alaram=false,timing_mode=continuous,channel_averaging=None,sequencer_mode=on,startup_channel_selection=contineous_sequence}" *) 16 | (* NotValidForBitStream *) 17 | module xadc_wiz_0 18 | (daddr_in, 19 | den_in, 20 | di_in, 21 | dwe_in, 22 | do_out, 23 | drdy_out, 24 | dclk_in, 25 | vauxp6, 26 | vauxn6, 27 | vauxp7, 28 | vauxn7, 29 | vauxp14, 30 | vauxn14, 31 | vauxp15, 32 | vauxn15, 33 | busy_out, 34 | channel_out, 35 | eoc_out, 36 | eos_out, 37 | alarm_out, 38 | vp_in, 39 | vn_in); 40 | input [6:0]daddr_in; 41 | input den_in; 42 | input [15:0]di_in; 43 | input dwe_in; 44 | output [15:0]do_out; 45 | output drdy_out; 46 | input dclk_in; 47 | input vauxp6; 48 | input vauxn6; 49 | input vauxp7; 50 | input vauxn7; 51 | input vauxp14; 52 | input vauxn14; 53 | input vauxp15; 54 | input vauxn15; 55 | output busy_out; 56 | output [4:0]channel_out; 57 | output eoc_out; 58 | output eos_out; 59 | output alarm_out; 60 | input vp_in; 61 | input vn_in; 62 | 63 | wire alarm_out; 64 | wire busy_out; 65 | wire [4:0]channel_out; 66 | wire [6:0]daddr_in; 67 | wire dclk_in; 68 | wire den_in; 69 | wire [15:0]di_in; 70 | wire [15:0]do_out; 71 | wire drdy_out; 72 | wire dwe_in; 73 | wire eoc_out; 74 | wire eos_out; 75 | wire vauxn14; 76 | wire vauxn15; 77 | wire vauxn6; 78 | wire vauxn7; 79 | wire vauxp14; 80 | wire vauxp15; 81 | wire vauxp6; 82 | wire vauxp7; 83 | wire vn_in; 84 | wire vp_in; 85 | wire NLW_U0_JTAGBUSY_UNCONNECTED; 86 | wire NLW_U0_JTAGLOCKED_UNCONNECTED; 87 | wire NLW_U0_JTAGMODIFIED_UNCONNECTED; 88 | wire NLW_U0_OT_UNCONNECTED; 89 | wire [6:0]NLW_U0_ALM_UNCONNECTED; 90 | wire [4:0]NLW_U0_MUXADDR_UNCONNECTED; 91 | 92 | (* box_type = "PRIMITIVE" *) 93 | XADC #( 94 | .INIT_40(16'h0000), 95 | .INIT_41(16'h210F), 96 | .INIT_42(16'h0400), 97 | .INIT_43(16'h0000), 98 | .INIT_44(16'h0000), 99 | .INIT_45(16'h0000), 100 | .INIT_46(16'h0000), 101 | .INIT_47(16'h0000), 102 | .INIT_48(16'h0000), 103 | .INIT_49(16'hC0C0), 104 | .INIT_4A(16'h0000), 105 | .INIT_4B(16'h0000), 106 | .INIT_4C(16'h0000), 107 | .INIT_4D(16'h0000), 108 | .INIT_4E(16'h0000), 109 | .INIT_4F(16'h0000), 110 | .INIT_50(16'hB5ED), 111 | .INIT_51(16'h57E4), 112 | .INIT_52(16'hA147), 113 | .INIT_53(16'hCA33), 114 | .INIT_54(16'hA93A), 115 | .INIT_55(16'h52C6), 116 | .INIT_56(16'h9555), 117 | .INIT_57(16'hAE4E), 118 | .INIT_58(16'h5999), 119 | .INIT_59(16'h0000), 120 | .INIT_5A(16'h0000), 121 | .INIT_5B(16'h0000), 122 | .INIT_5C(16'h5111), 123 | .INIT_5D(16'h0000), 124 | .INIT_5E(16'h0000), 125 | .INIT_5F(16'h0000), 126 | .IS_CONVSTCLK_INVERTED(1'b0), 127 | .IS_DCLK_INVERTED(1'b0), 128 | .SIM_DEVICE("7SERIES"), 129 | .SIM_MONITOR_FILE("c:/Users/Nate/Desktop/work/GitProject/Demos/DemoTest/Basys3/Projects/Basys3_XADC_Demo/src/ip/xadc_wiz_0_1/xadc_wiz_0/simulation/functional/design.txt")) 130 | U0 131 | (.ALM({alarm_out,NLW_U0_ALM_UNCONNECTED[6:0]}), 132 | .BUSY(busy_out), 133 | .CHANNEL(channel_out), 134 | .CONVST(1'b0), 135 | .CONVSTCLK(1'b0), 136 | .DADDR(daddr_in), 137 | .DCLK(dclk_in), 138 | .DEN(den_in), 139 | .DI(di_in), 140 | .DO(do_out), 141 | .DRDY(drdy_out), 142 | .DWE(dwe_in), 143 | .EOC(eoc_out), 144 | .EOS(eos_out), 145 | .JTAGBUSY(NLW_U0_JTAGBUSY_UNCONNECTED), 146 | .JTAGLOCKED(NLW_U0_JTAGLOCKED_UNCONNECTED), 147 | .JTAGMODIFIED(NLW_U0_JTAGMODIFIED_UNCONNECTED), 148 | .MUXADDR(NLW_U0_MUXADDR_UNCONNECTED[4:0]), 149 | .OT(NLW_U0_OT_UNCONNECTED), 150 | .RESET(1'b0), 151 | .VAUXN({vauxn15,vauxn14,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,vauxn7,vauxn6,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), 152 | .VAUXP({vauxp15,vauxp14,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,vauxp7,vauxp6,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), 153 | .VN(vn_in), 154 | .VP(vp_in)); 155 | endmodule 156 | `ifndef GLBL 157 | `define GLBL 158 | `timescale 1 ps / 1 ps 159 | 160 | module glbl (); 161 | 162 | parameter ROC_WIDTH = 100000; 163 | parameter TOC_WIDTH = 0; 164 | 165 | //-------- STARTUP Globals -------------- 166 | wire GSR; 167 | wire GTS; 168 | wire GWE; 169 | wire PRLD; 170 | tri1 p_up_tmp; 171 | tri (weak1, strong0) PLL_LOCKG = p_up_tmp; 172 | 173 | wire PROGB_GLBL; 174 | wire CCLKO_GLBL; 175 | wire FCSBO_GLBL; 176 | wire [3:0] DO_GLBL; 177 | wire [3:0] DI_GLBL; 178 | 179 | reg GSR_int; 180 | reg GTS_int; 181 | reg PRLD_int; 182 | 183 | //-------- JTAG Globals -------------- 184 | wire JTAG_TDO_GLBL; 185 | wire JTAG_TCK_GLBL; 186 | wire JTAG_TDI_GLBL; 187 | wire JTAG_TMS_GLBL; 188 | wire JTAG_TRST_GLBL; 189 | 190 | reg JTAG_CAPTURE_GLBL; 191 | reg JTAG_RESET_GLBL; 192 | reg JTAG_SHIFT_GLBL; 193 | reg JTAG_UPDATE_GLBL; 194 | reg JTAG_RUNTEST_GLBL; 195 | 196 | reg JTAG_SEL1_GLBL = 0; 197 | reg JTAG_SEL2_GLBL = 0 ; 198 | reg JTAG_SEL3_GLBL = 0; 199 | reg JTAG_SEL4_GLBL = 0; 200 | 201 | reg JTAG_USER_TDO1_GLBL = 1'bz; 202 | reg JTAG_USER_TDO2_GLBL = 1'bz; 203 | reg JTAG_USER_TDO3_GLBL = 1'bz; 204 | reg JTAG_USER_TDO4_GLBL = 1'bz; 205 | 206 | assign (weak1, weak0) GSR = GSR_int; 207 | assign (weak1, weak0) GTS = GTS_int; 208 | assign (weak1, weak0) PRLD = PRLD_int; 209 | 210 | initial begin 211 | GSR_int = 1'b1; 212 | PRLD_int = 1'b1; 213 | #(ROC_WIDTH) 214 | GSR_int = 1'b0; 215 | PRLD_int = 1'b0; 216 | end 217 | 218 | initial begin 219 | GTS_int = 1'b1; 220 | #(TOC_WIDTH) 221 | GTS_int = 1'b0; 222 | end 223 | 224 | endmodule 225 | `endif 226 | -------------------------------------------------------------------------------- /Projects/XADC_Demo/src/ip/xadc_wiz_0_1/xadc_wiz_0_funcsim.vhdl: -------------------------------------------------------------------------------- 1 | -- Copyright 1986-2015 Xilinx, Inc. All Rights Reserved. 2 | -- -------------------------------------------------------------------------------- 3 | -- Tool Version: Vivado v.2015.1 (win64) Build 1215546 Mon Apr 27 19:22:08 MDT 2015 4 | -- Date : Sun Oct 18 12:34:43 2015 5 | -- Host : Sparky running 64-bit Service Pack 1 (build 7601) 6 | -- Command : write_vhdl -force -mode funcsim 7 | -- C:/Users/Nate/Desktop/work/GitProject/Demos/DemoTest/Basys3/Projects/Basys3_XADC_Demo/src/ip/xadc_wiz_0_1/xadc_wiz_0_funcsim.vhdl 8 | -- Design : xadc_wiz_0 9 | -- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or 10 | -- synthesized. This netlist cannot be used for SDF annotated simulation. 11 | -- Device : xc7a35tcpg236-1 12 | -- -------------------------------------------------------------------------------- 13 | library IEEE; 14 | use IEEE.STD_LOGIC_1164.ALL; 15 | library UNISIM; 16 | use UNISIM.VCOMPONENTS.ALL; 17 | entity xadc_wiz_0 is 18 | port ( 19 | daddr_in : in STD_LOGIC_VECTOR ( 6 downto 0 ); 20 | den_in : in STD_LOGIC; 21 | di_in : in STD_LOGIC_VECTOR ( 15 downto 0 ); 22 | dwe_in : in STD_LOGIC; 23 | do_out : out STD_LOGIC_VECTOR ( 15 downto 0 ); 24 | drdy_out : out STD_LOGIC; 25 | dclk_in : in STD_LOGIC; 26 | vauxp6 : in STD_LOGIC; 27 | vauxn6 : in STD_LOGIC; 28 | vauxp7 : in STD_LOGIC; 29 | vauxn7 : in STD_LOGIC; 30 | vauxp14 : in STD_LOGIC; 31 | vauxn14 : in STD_LOGIC; 32 | vauxp15 : in STD_LOGIC; 33 | vauxn15 : in STD_LOGIC; 34 | busy_out : out STD_LOGIC; 35 | channel_out : out STD_LOGIC_VECTOR ( 4 downto 0 ); 36 | eoc_out : out STD_LOGIC; 37 | eos_out : out STD_LOGIC; 38 | alarm_out : out STD_LOGIC; 39 | vp_in : in STD_LOGIC; 40 | vn_in : in STD_LOGIC 41 | ); 42 | attribute NotValidForBitStream : boolean; 43 | attribute NotValidForBitStream of xadc_wiz_0 : entity is true; 44 | attribute core_generation_info : string; 45 | attribute core_generation_info of xadc_wiz_0 : entity is "xadc_wiz_0,xadc_wiz_v3_0,{component_name=xadc_wiz_0,enable_axi=false,enable_axi4stream=false,dclk_frequency=100,enable_busy=true,enable_convst=false,enable_convstclk=false,enable_dclk=true,enable_drp=true,enable_eoc=true,enable_eos=true,enable_vbram_alaram=false,enable_vccddro_alaram=false,enable_Vccint_Alaram=false,enable_Vccaux_alaram=falseenable_vccpaux_alaram=false,enable_vccpint_alaram=false,ot_alaram=false,user_temp_alaram=false,timing_mode=continuous,channel_averaging=None,sequencer_mode=on,startup_channel_selection=contineous_sequence}"; 46 | end xadc_wiz_0; 47 | 48 | architecture STRUCTURE of xadc_wiz_0 is 49 | signal NLW_U0_JTAGBUSY_UNCONNECTED : STD_LOGIC; 50 | signal NLW_U0_JTAGLOCKED_UNCONNECTED : STD_LOGIC; 51 | signal NLW_U0_JTAGMODIFIED_UNCONNECTED : STD_LOGIC; 52 | signal NLW_U0_OT_UNCONNECTED : STD_LOGIC; 53 | signal NLW_U0_ALM_UNCONNECTED : STD_LOGIC_VECTOR ( 6 downto 0 ); 54 | signal NLW_U0_MUXADDR_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 ); 55 | attribute box_type : string; 56 | attribute box_type of U0 : label is "PRIMITIVE"; 57 | begin 58 | U0: unisim.vcomponents.XADC 59 | generic map( 60 | INIT_40 => X"0000", 61 | INIT_41 => X"210F", 62 | INIT_42 => X"0400", 63 | INIT_43 => X"0000", 64 | INIT_44 => X"0000", 65 | INIT_45 => X"0000", 66 | INIT_46 => X"0000", 67 | INIT_47 => X"0000", 68 | INIT_48 => X"0000", 69 | INIT_49 => X"C0C0", 70 | INIT_4A => X"0000", 71 | INIT_4B => X"0000", 72 | INIT_4C => X"0000", 73 | INIT_4D => X"0000", 74 | INIT_4E => X"0000", 75 | INIT_4F => X"0000", 76 | INIT_50 => X"B5ED", 77 | INIT_51 => X"57E4", 78 | INIT_52 => X"A147", 79 | INIT_53 => X"CA33", 80 | INIT_54 => X"A93A", 81 | INIT_55 => X"52C6", 82 | INIT_56 => X"9555", 83 | INIT_57 => X"AE4E", 84 | INIT_58 => X"5999", 85 | INIT_59 => X"0000", 86 | INIT_5A => X"0000", 87 | INIT_5B => X"0000", 88 | INIT_5C => X"5111", 89 | INIT_5D => X"0000", 90 | INIT_5E => X"0000", 91 | INIT_5F => X"0000", 92 | IS_CONVSTCLK_INVERTED => '0', 93 | IS_DCLK_INVERTED => '0', 94 | SIM_DEVICE => "7SERIES", 95 | SIM_MONITOR_FILE => "c:/Users/Nate/Desktop/work/GitProject/Demos/DemoTest/Basys3/Projects/Basys3_XADC_Demo/src/ip/xadc_wiz_0_1/xadc_wiz_0/simulation/functional/design.txt" 96 | ) 97 | port map ( 98 | ALM(7) => alarm_out, 99 | ALM(6 downto 0) => NLW_U0_ALM_UNCONNECTED(6 downto 0), 100 | BUSY => busy_out, 101 | CHANNEL(4 downto 0) => channel_out(4 downto 0), 102 | CONVST => '0', 103 | CONVSTCLK => '0', 104 | DADDR(6 downto 0) => daddr_in(6 downto 0), 105 | DCLK => dclk_in, 106 | DEN => den_in, 107 | DI(15 downto 0) => di_in(15 downto 0), 108 | DO(15 downto 0) => do_out(15 downto 0), 109 | DRDY => drdy_out, 110 | DWE => dwe_in, 111 | EOC => eoc_out, 112 | EOS => eos_out, 113 | JTAGBUSY => NLW_U0_JTAGBUSY_UNCONNECTED, 114 | JTAGLOCKED => NLW_U0_JTAGLOCKED_UNCONNECTED, 115 | JTAGMODIFIED => NLW_U0_JTAGMODIFIED_UNCONNECTED, 116 | MUXADDR(4 downto 0) => NLW_U0_MUXADDR_UNCONNECTED(4 downto 0), 117 | OT => NLW_U0_OT_UNCONNECTED, 118 | RESET => '0', 119 | VAUXN(15) => vauxn15, 120 | VAUXN(14) => vauxn14, 121 | VAUXN(13) => '0', 122 | VAUXN(12) => '0', 123 | VAUXN(11) => '0', 124 | VAUXN(10) => '0', 125 | VAUXN(9) => '0', 126 | VAUXN(8) => '0', 127 | VAUXN(7) => vauxn7, 128 | VAUXN(6) => vauxn6, 129 | VAUXN(5) => '0', 130 | VAUXN(4) => '0', 131 | VAUXN(3) => '0', 132 | VAUXN(2) => '0', 133 | VAUXN(1) => '0', 134 | VAUXN(0) => '0', 135 | VAUXP(15) => vauxp15, 136 | VAUXP(14) => vauxp14, 137 | VAUXP(13) => '0', 138 | VAUXP(12) => '0', 139 | VAUXP(11) => '0', 140 | VAUXP(10) => '0', 141 | VAUXP(9) => '0', 142 | VAUXP(8) => '0', 143 | VAUXP(7) => vauxp7, 144 | VAUXP(6) => vauxp6, 145 | VAUXP(5) => '0', 146 | VAUXP(4) => '0', 147 | VAUXP(3) => '0', 148 | VAUXP(2) => '0', 149 | VAUXP(1) => '0', 150 | VAUXP(0) => '0', 151 | VN => vn_in, 152 | VP => vp_in 153 | ); 154 | end STRUCTURE; 155 | -------------------------------------------------------------------------------- /Projects/XADC_Demo/src/ip/xadc_wiz_0_1/xadc_wiz_0_ooc.xdc: -------------------------------------------------------------------------------- 1 | # file: xadc_wiz_0_ooc.xdc 2 | # (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved. 3 | # 4 | # This file contains confidential and proprietary information 5 | # of Xilinx, Inc. and is protected under U.S. and 6 | # international copyright and other intellectual property 7 | # laws. 8 | # 9 | # DISCLAIMER 10 | # This disclaimer is not a license and does not grant any 11 | # rights to the materials distributed herewith. Except as 12 | # otherwise provided in a valid license issued to you by 13 | # Xilinx, and to the maximum extent permitted by applicable 14 | # law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 15 | # WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 16 | # AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 17 | # BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 18 | # INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 19 | # (2) Xilinx shall not be liable (whether in contract or tort, 20 | # including negligence, or under any other theory of 21 | # liability) for any loss or damage of any kind or nature 22 | # related to, arising under or in connection with these 23 | # materials, including for any direct, or any indirect, 24 | # special, incidental, or consequential loss or damage 25 | # (including loss of data, profits, goodwill, or any type of 26 | # loss or damage suffered as a result of any action brought 27 | # by a third party) even if such damage or loss was 28 | # reasonably foreseeable or Xilinx had been advised of the 29 | # possibility of the same. 30 | # 31 | # CRITICAL APPLICATIONS 32 | # Xilinx products are not designed or intended to be fail- 33 | # safe, or for use in any application requiring fail-safe 34 | # performance, such as life-support or safety devices or 35 | # systems, Class III medical devices, nuclear facilities, 36 | # applications related to the deployment of airbags, or any 37 | # other applications that could lead to death, personal 38 | # injury, or severe property or environmental damage 39 | # (individually and collectively, "Critical 40 | # Applications"). Customer assumes the sole risk and 41 | # liability of any use of Xilinx products in Critical 42 | # Applications, subject only to applicable laws and 43 | # regulations governing limitations on product liability. 44 | # 45 | # THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 46 | # PART OF THIS FILE AT ALL TIMES. 47 | 48 | ################# 49 | #DEFAULT CLOCK CONSTRAINTS 50 | 51 | ############################################################ 52 | # Clock Period Constraints # 53 | ############################################################ 54 | #create_clock -period 10 [get_ports dclk_in] 55 | 56 | -------------------------------------------------------------------------------- /Projects/XADC_Demo/src/ip/xadc_wiz_0_1/xadc_wiz_0_stub.v: -------------------------------------------------------------------------------- 1 | // Copyright 1986-2015 Xilinx, Inc. All Rights Reserved. 2 | // -------------------------------------------------------------------------------- 3 | // Tool Version: Vivado v.2015.1 (win64) Build 1215546 Mon Apr 27 19:22:08 MDT 2015 4 | // Date : Sun Oct 18 12:34:43 2015 5 | // Host : Sparky running 64-bit Service Pack 1 (build 7601) 6 | // Command : write_verilog -force -mode synth_stub 7 | // C:/Users/Nate/Desktop/work/GitProject/Demos/DemoTest/Basys3/Projects/Basys3_XADC_Demo/src/ip/xadc_wiz_0_1/xadc_wiz_0_stub.v 8 | // Design : xadc_wiz_0 9 | // Purpose : Stub declaration of top-level module interface 10 | // Device : xc7a35tcpg236-1 11 | // -------------------------------------------------------------------------------- 12 | 13 | // This empty module with port declaration file causes synthesis tools to infer a black box for IP. 14 | // The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. 15 | // Please paste the declaration into a Verilog source file or add the file as an additional source. 16 | module xadc_wiz_0(daddr_in, den_in, di_in, dwe_in, do_out, drdy_out, dclk_in, vauxp6, vauxn6, vauxp7, vauxn7, vauxp14, vauxn14, vauxp15, vauxn15, busy_out, channel_out, eoc_out, eos_out, alarm_out, vp_in, vn_in) 17 | /* synthesis syn_black_box black_box_pad_pin="daddr_in[6:0],den_in,di_in[15:0],dwe_in,do_out[15:0],drdy_out,dclk_in,vauxp6,vauxn6,vauxp7,vauxn7,vauxp14,vauxn14,vauxp15,vauxn15,busy_out,channel_out[4:0],eoc_out,eos_out,alarm_out,vp_in,vn_in" */; 18 | input [6:0]daddr_in; 19 | input den_in; 20 | input [15:0]di_in; 21 | input dwe_in; 22 | output [15:0]do_out; 23 | output drdy_out; 24 | input dclk_in; 25 | input vauxp6; 26 | input vauxn6; 27 | input vauxp7; 28 | input vauxn7; 29 | input vauxp14; 30 | input vauxn14; 31 | input vauxp15; 32 | input vauxn15; 33 | output busy_out; 34 | output [4:0]channel_out; 35 | output eoc_out; 36 | output eos_out; 37 | output alarm_out; 38 | input vp_in; 39 | input vn_in; 40 | endmodule 41 | -------------------------------------------------------------------------------- /Projects/XADC_Demo/src/ip/xadc_wiz_0_1/xadc_wiz_0_stub.vhdl: -------------------------------------------------------------------------------- 1 | -- Copyright 1986-2015 Xilinx, Inc. All Rights Reserved. 2 | -- -------------------------------------------------------------------------------- 3 | -- Tool Version: Vivado v.2015.1 (win64) Build 1215546 Mon Apr 27 19:22:08 MDT 2015 4 | -- Date : Sun Oct 18 12:34:43 2015 5 | -- Host : Sparky running 64-bit Service Pack 1 (build 7601) 6 | -- Command : write_vhdl -force -mode synth_stub 7 | -- C:/Users/Nate/Desktop/work/GitProject/Demos/DemoTest/Basys3/Projects/Basys3_XADC_Demo/src/ip/xadc_wiz_0_1/xadc_wiz_0_stub.vhdl 8 | -- Design : xadc_wiz_0 9 | -- Purpose : Stub declaration of top-level module interface 10 | -- Device : xc7a35tcpg236-1 11 | -- -------------------------------------------------------------------------------- 12 | library IEEE; 13 | use IEEE.STD_LOGIC_1164.ALL; 14 | 15 | entity xadc_wiz_0 is 16 | Port ( 17 | daddr_in : in STD_LOGIC_VECTOR ( 6 downto 0 ); 18 | den_in : in STD_LOGIC; 19 | di_in : in STD_LOGIC_VECTOR ( 15 downto 0 ); 20 | dwe_in : in STD_LOGIC; 21 | do_out : out STD_LOGIC_VECTOR ( 15 downto 0 ); 22 | drdy_out : out STD_LOGIC; 23 | dclk_in : in STD_LOGIC; 24 | vauxp6 : in STD_LOGIC; 25 | vauxn6 : in STD_LOGIC; 26 | vauxp7 : in STD_LOGIC; 27 | vauxn7 : in STD_LOGIC; 28 | vauxp14 : in STD_LOGIC; 29 | vauxn14 : in STD_LOGIC; 30 | vauxp15 : in STD_LOGIC; 31 | vauxn15 : in STD_LOGIC; 32 | busy_out : out STD_LOGIC; 33 | channel_out : out STD_LOGIC_VECTOR ( 4 downto 0 ); 34 | eoc_out : out STD_LOGIC; 35 | eos_out : out STD_LOGIC; 36 | alarm_out : out STD_LOGIC; 37 | vp_in : in STD_LOGIC; 38 | vn_in : in STD_LOGIC 39 | ); 40 | 41 | end xadc_wiz_0; 42 | 43 | architecture stub of xadc_wiz_0 is 44 | attribute syn_black_box : boolean; 45 | attribute black_box_pad_pin : string; 46 | attribute syn_black_box of stub : architecture is true; 47 | attribute black_box_pad_pin of stub : architecture is "daddr_in[6:0],den_in,di_in[15:0],dwe_in,do_out[15:0],drdy_out,dclk_in,vauxp6,vauxn6,vauxp7,vauxn7,vauxp14,vauxn14,vauxp15,vauxn15,busy_out,channel_out[4:0],eoc_out,eos_out,alarm_out,vp_in,vn_in"; 48 | begin 49 | end; 50 | -------------------------------------------------------------------------------- /Resources/XDC/Basys3_Master.xdc: -------------------------------------------------------------------------------- 1 | ## This file is a general .xdc for the Basys3 rev B board 2 | ## To use it in a project: 3 | ## - uncomment the lines corresponding to used pins 4 | ## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project 5 | 6 | ## Clock signal 7 | #set_property PACKAGE_PIN W5 [get_ports clk] 8 | #set_property IOSTANDARD LVCMOS33 [get_ports clk] 9 | #create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports clk] 10 | 11 | ## Switches 12 | #set_property PACKAGE_PIN V17 [get_ports {sw[0]}] 13 | #set_property IOSTANDARD LVCMOS33 [get_ports {sw[0]}] 14 | #set_property PACKAGE_PIN V16 [get_ports {sw[1]}] 15 | #set_property IOSTANDARD LVCMOS33 [get_ports {sw[1]}] 16 | #set_property PACKAGE_PIN W16 [get_ports {sw[2]}] 17 | #set_property IOSTANDARD LVCMOS33 [get_ports {sw[2]}] 18 | #set_property PACKAGE_PIN W17 [get_ports {sw[3]}] 19 | #set_property IOSTANDARD LVCMOS33 [get_ports {sw[3]}] 20 | #set_property PACKAGE_PIN W15 [get_ports {sw[4]}] 21 | #set_property IOSTANDARD LVCMOS33 [get_ports {sw[4]}] 22 | #set_property PACKAGE_PIN V15 [get_ports {sw[5]}] 23 | #set_property IOSTANDARD LVCMOS33 [get_ports {sw[5]}] 24 | #set_property PACKAGE_PIN W14 [get_ports {sw[6]}] 25 | #set_property IOSTANDARD LVCMOS33 [get_ports {sw[6]}] 26 | #set_property PACKAGE_PIN W13 [get_ports {sw[7]}] 27 | #set_property IOSTANDARD LVCMOS33 [get_ports {sw[7]}] 28 | #set_property PACKAGE_PIN V2 [get_ports {sw[8]}] 29 | #set_property IOSTANDARD LVCMOS33 [get_ports {sw[8]}] 30 | #set_property PACKAGE_PIN T3 [get_ports {sw[9]}] 31 | #set_property IOSTANDARD LVCMOS33 [get_ports {sw[9]}] 32 | #set_property PACKAGE_PIN T2 [get_ports {sw[10]}] 33 | #set_property IOSTANDARD LVCMOS33 [get_ports {sw[10]}] 34 | #set_property PACKAGE_PIN R3 [get_ports {sw[11]}] 35 | #set_property IOSTANDARD LVCMOS33 [get_ports {sw[11]}] 36 | #set_property PACKAGE_PIN W2 [get_ports {sw[12]}] 37 | #set_property IOSTANDARD LVCMOS33 [get_ports {sw[12]}] 38 | #set_property PACKAGE_PIN U1 [get_ports {sw[13]}] 39 | #set_property IOSTANDARD LVCMOS33 [get_ports {sw[13]}] 40 | #set_property PACKAGE_PIN T1 [get_ports {sw[14]}] 41 | #set_property IOSTANDARD LVCMOS33 [get_ports {sw[14]}] 42 | #set_property PACKAGE_PIN R2 [get_ports {sw[15]}] 43 | #set_property IOSTANDARD LVCMOS33 [get_ports {sw[15]}] 44 | 45 | 46 | ## LEDs 47 | #set_property PACKAGE_PIN U16 [get_ports {led[0]}] 48 | #set_property IOSTANDARD LVCMOS33 [get_ports {led[0]}] 49 | #set_property PACKAGE_PIN E19 [get_ports {led[1]}] 50 | #set_property IOSTANDARD LVCMOS33 [get_ports {led[1]}] 51 | #set_property PACKAGE_PIN U19 [get_ports {led[2]}] 52 | #set_property IOSTANDARD LVCMOS33 [get_ports {led[2]}] 53 | #set_property PACKAGE_PIN V19 [get_ports {led[3]}] 54 | #set_property IOSTANDARD LVCMOS33 [get_ports {led[3]}] 55 | #set_property PACKAGE_PIN W18 [get_ports {led[4]}] 56 | #set_property IOSTANDARD LVCMOS33 [get_ports {led[4]}] 57 | #set_property PACKAGE_PIN U15 [get_ports {led[5]}] 58 | #set_property IOSTANDARD LVCMOS33 [get_ports {led[5]}] 59 | #set_property PACKAGE_PIN U14 [get_ports {led[6]}] 60 | #set_property IOSTANDARD LVCMOS33 [get_ports {led[6]}] 61 | #set_property PACKAGE_PIN V14 [get_ports {led[7]}] 62 | #set_property IOSTANDARD LVCMOS33 [get_ports {led[7]}] 63 | #set_property PACKAGE_PIN V13 [get_ports {led[8]}] 64 | #set_property IOSTANDARD LVCMOS33 [get_ports {led[8]}] 65 | #set_property PACKAGE_PIN V3 [get_ports {led[9]}] 66 | #set_property IOSTANDARD LVCMOS33 [get_ports {led[9]}] 67 | #set_property PACKAGE_PIN W3 [get_ports {led[10]}] 68 | #set_property IOSTANDARD LVCMOS33 [get_ports {led[10]}] 69 | #set_property PACKAGE_PIN U3 [get_ports {led[11]}] 70 | #set_property IOSTANDARD LVCMOS33 [get_ports {led[11]}] 71 | #set_property PACKAGE_PIN P3 [get_ports {led[12]}] 72 | #set_property IOSTANDARD LVCMOS33 [get_ports {led[12]}] 73 | #set_property PACKAGE_PIN N3 [get_ports {led[13]}] 74 | #set_property IOSTANDARD LVCMOS33 [get_ports {led[13]}] 75 | #set_property PACKAGE_PIN P1 [get_ports {led[14]}] 76 | #set_property IOSTANDARD LVCMOS33 [get_ports {led[14]}] 77 | #set_property PACKAGE_PIN L1 [get_ports {led[15]}] 78 | #set_property IOSTANDARD LVCMOS33 [get_ports {led[15]}] 79 | 80 | 81 | ##7 segment display 82 | #set_property PACKAGE_PIN W7 [get_ports {seg[0]}] 83 | #set_property IOSTANDARD LVCMOS33 [get_ports {seg[0]}] 84 | #set_property PACKAGE_PIN W6 [get_ports {seg[1]}] 85 | #set_property IOSTANDARD LVCMOS33 [get_ports {seg[1]}] 86 | #set_property PACKAGE_PIN U8 [get_ports {seg[2]}] 87 | #set_property IOSTANDARD LVCMOS33 [get_ports {seg[2]}] 88 | #set_property PACKAGE_PIN V8 [get_ports {seg[3]}] 89 | #set_property IOSTANDARD LVCMOS33 [get_ports {seg[3]}] 90 | #set_property PACKAGE_PIN U5 [get_ports {seg[4]}] 91 | #set_property IOSTANDARD LVCMOS33 [get_ports {seg[4]}] 92 | #set_property PACKAGE_PIN V5 [get_ports {seg[5]}] 93 | #set_property IOSTANDARD LVCMOS33 [get_ports {seg[5]}] 94 | #set_property PACKAGE_PIN U7 [get_ports {seg[6]}] 95 | #set_property IOSTANDARD LVCMOS33 [get_ports {seg[6]}] 96 | 97 | #set_property PACKAGE_PIN V7 [get_ports dp] 98 | #set_property IOSTANDARD LVCMOS33 [get_ports dp] 99 | 100 | #set_property PACKAGE_PIN U2 [get_ports {an[0]}] 101 | #set_property IOSTANDARD LVCMOS33 [get_ports {an[0]}] 102 | #set_property PACKAGE_PIN U4 [get_ports {an[1]}] 103 | #set_property IOSTANDARD LVCMOS33 [get_ports {an[1]}] 104 | #set_property PACKAGE_PIN V4 [get_ports {an[2]}] 105 | #set_property IOSTANDARD LVCMOS33 [get_ports {an[2]}] 106 | #set_property PACKAGE_PIN W4 [get_ports {an[3]}] 107 | #set_property IOSTANDARD LVCMOS33 [get_ports {an[3]}] 108 | 109 | 110 | ##Buttons 111 | #set_property PACKAGE_PIN U18 [get_ports btnC] 112 | #set_property IOSTANDARD LVCMOS33 [get_ports btnC] 113 | #set_property PACKAGE_PIN T18 [get_ports btnU] 114 | #set_property IOSTANDARD LVCMOS33 [get_ports btnU] 115 | #set_property PACKAGE_PIN W19 [get_ports btnL] 116 | #set_property IOSTANDARD LVCMOS33 [get_ports btnL] 117 | #set_property PACKAGE_PIN T17 [get_ports btnR] 118 | #set_property IOSTANDARD LVCMOS33 [get_ports btnR] 119 | #set_property PACKAGE_PIN U17 [get_ports btnD] 120 | #set_property IOSTANDARD LVCMOS33 [get_ports btnD] 121 | 122 | 123 | 124 | ##Pmod Header JA 125 | ##Sch name = JA1 126 | #set_property PACKAGE_PIN J1 [get_ports {JA[0]}] 127 | #set_property IOSTANDARD LVCMOS33 [get_ports {JA[0]}] 128 | ##Sch name = JA2 129 | #set_property PACKAGE_PIN L2 [get_ports {JA[1]}] 130 | #set_property IOSTANDARD LVCMOS33 [get_ports {JA[1]}] 131 | ##Sch name = JA3 132 | #set_property PACKAGE_PIN J2 [get_ports {JA[2]}] 133 | #set_property IOSTANDARD LVCMOS33 [get_ports {JA[2]}] 134 | ##Sch name = JA4 135 | #set_property PACKAGE_PIN G2 [get_ports {JA[3]}] 136 | #set_property IOSTANDARD LVCMOS33 [get_ports {JA[3]}] 137 | ##Sch name = JA7 138 | #set_property PACKAGE_PIN H1 [get_ports {JA[4]}] 139 | #set_property IOSTANDARD LVCMOS33 [get_ports {JA[4]}] 140 | ##Sch name = JA8 141 | #set_property PACKAGE_PIN K2 [get_ports {JA[5]}] 142 | #set_property IOSTANDARD LVCMOS33 [get_ports {JA[5]}] 143 | ##Sch name = JA9 144 | #set_property PACKAGE_PIN H2 [get_ports {JA[6]}] 145 | #set_property IOSTANDARD LVCMOS33 [get_ports {JA[6]}] 146 | ##Sch name = JA10 147 | #set_property PACKAGE_PIN G3 [get_ports {JA[7]}] 148 | #set_property IOSTANDARD LVCMOS33 [get_ports {JA[7]}] 149 | 150 | 151 | 152 | ##Pmod Header JB 153 | ##Sch name = JB1 154 | #set_property PACKAGE_PIN A14 [get_ports {JB[0]}] 155 | #set_property IOSTANDARD LVCMOS33 [get_ports {JB[0]}] 156 | ##Sch name = JB2 157 | #set_property PACKAGE_PIN A16 [get_ports {JB[1]}] 158 | #set_property IOSTANDARD LVCMOS33 [get_ports {JB[1]}] 159 | ##Sch name = JB3 160 | #set_property PACKAGE_PIN B15 [get_ports {JB[2]}] 161 | #set_property IOSTANDARD LVCMOS33 [get_ports {JB[2]}] 162 | ##Sch name = JB4 163 | #set_property PACKAGE_PIN B16 [get_ports {JB[3]}] 164 | #set_property IOSTANDARD LVCMOS33 [get_ports {JB[3]}] 165 | ##Sch name = JB7 166 | #set_property PACKAGE_PIN A15 [get_ports {JB[4]}] 167 | #set_property IOSTANDARD LVCMOS33 [get_ports {JB[4]}] 168 | ##Sch name = JB8 169 | #set_property PACKAGE_PIN A17 [get_ports {JB[5]}] 170 | #set_property IOSTANDARD LVCMOS33 [get_ports {JB[5]}] 171 | ##Sch name = JB9 172 | #set_property PACKAGE_PIN C15 [get_ports {JB[6]}] 173 | #set_property IOSTANDARD LVCMOS33 [get_ports {JB[6]}] 174 | ##Sch name = JB10 175 | #set_property PACKAGE_PIN C16 [get_ports {JB[7]}] 176 | #set_property IOSTANDARD LVCMOS33 [get_ports {JB[7]}] 177 | 178 | 179 | 180 | ##Pmod Header JC 181 | ##Sch name = JC1 182 | #set_property PACKAGE_PIN K17 [get_ports {JC[0]}] 183 | #set_property IOSTANDARD LVCMOS33 [get_ports {JC[0]}] 184 | ##Sch name = JC2 185 | #set_property PACKAGE_PIN M18 [get_ports {JC[1]}] 186 | #set_property IOSTANDARD LVCMOS33 [get_ports {JC[1]}] 187 | ##Sch name = JC3 188 | #set_property PACKAGE_PIN N17 [get_ports {JC[2]}] 189 | #set_property IOSTANDARD LVCMOS33 [get_ports {JC[2]}] 190 | ##Sch name = JC4 191 | #set_property PACKAGE_PIN P18 [get_ports {JC[3]}] 192 | #set_property IOSTANDARD LVCMOS33 [get_ports {JC[3]}] 193 | ##Sch name = JC7 194 | #set_property PACKAGE_PIN L17 [get_ports {JC[4]}] 195 | #set_property IOSTANDARD LVCMOS33 [get_ports {JC[4]}] 196 | ##Sch name = JC8 197 | #set_property PACKAGE_PIN M19 [get_ports {JC[5]}] 198 | #set_property IOSTANDARD LVCMOS33 [get_ports {JC[5]}] 199 | ##Sch name = JC9 200 | #set_property PACKAGE_PIN P17 [get_ports {JC[6]}] 201 | #set_property IOSTANDARD LVCMOS33 [get_ports {JC[6]}] 202 | ##Sch name = JC10 203 | #set_property PACKAGE_PIN R18 [get_ports {JC[7]}] 204 | #set_property IOSTANDARD LVCMOS33 [get_ports {JC[7]}] 205 | 206 | 207 | ##Pmod Header JXADC 208 | ##Sch name = XA1_P 209 | #set_property PACKAGE_PIN J3 [get_ports {JXADC[0]}] 210 | #set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[0]}] 211 | ##Sch name = XA2_P 212 | #set_property PACKAGE_PIN L3 [get_ports {JXADC[1]}] 213 | #set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[1]}] 214 | ##Sch name = XA3_P 215 | #set_property PACKAGE_PIN M2 [get_ports {JXADC[2]}] 216 | #set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[2]}] 217 | ##Sch name = XA4_P 218 | #set_property PACKAGE_PIN N2 [get_ports {JXADC[3]}] 219 | #set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[3]}] 220 | ##Sch name = XA1_N 221 | #set_property PACKAGE_PIN K3 [get_ports {JXADC[4]}] 222 | #set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[4]}] 223 | ##Sch name = XA2_N 224 | #set_property PACKAGE_PIN M3 [get_ports {JXADC[5]}] 225 | #set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[5]}] 226 | ##Sch name = XA3_N 227 | #set_property PACKAGE_PIN M1 [get_ports {JXADC[6]}] 228 | #set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[6]}] 229 | ##Sch name = XA4_N 230 | #set_property PACKAGE_PIN N1 [get_ports {JXADC[7]}] 231 | #set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[7]}] 232 | 233 | 234 | 235 | ##VGA Connector 236 | #set_property PACKAGE_PIN G19 [get_ports {vgaRed[0]}] 237 | #set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[0]}] 238 | #set_property PACKAGE_PIN H19 [get_ports {vgaRed[1]}] 239 | #set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[1]}] 240 | #set_property PACKAGE_PIN J19 [get_ports {vgaRed[2]}] 241 | #set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[2]}] 242 | #set_property PACKAGE_PIN N19 [get_ports {vgaRed[3]}] 243 | #set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[3]}] 244 | #set_property PACKAGE_PIN N18 [get_ports {vgaBlue[0]}] 245 | #set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[0]}] 246 | #set_property PACKAGE_PIN L18 [get_ports {vgaBlue[1]}] 247 | #set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[1]}] 248 | #set_property PACKAGE_PIN K18 [get_ports {vgaBlue[2]}] 249 | #set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[2]}] 250 | #set_property PACKAGE_PIN J18 [get_ports {vgaBlue[3]}] 251 | #set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[3]}] 252 | #set_property PACKAGE_PIN J17 [get_ports {vgaGreen[0]}] 253 | #set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[0]}] 254 | #set_property PACKAGE_PIN H17 [get_ports {vgaGreen[1]}] 255 | #set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[1]}] 256 | #set_property PACKAGE_PIN G17 [get_ports {vgaGreen[2]}] 257 | #set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[2]}] 258 | #set_property PACKAGE_PIN D17 [get_ports {vgaGreen[3]}] 259 | #set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[3]}] 260 | #set_property PACKAGE_PIN P19 [get_ports Hsync] 261 | #set_property IOSTANDARD LVCMOS33 [get_ports Hsync] 262 | #set_property PACKAGE_PIN R19 [get_ports Vsync] 263 | #set_property IOSTANDARD LVCMOS33 [get_ports Vsync] 264 | 265 | 266 | ##USB-RS232 Interface 267 | #set_property PACKAGE_PIN B18 [get_ports RsRx] 268 | #set_property IOSTANDARD LVCMOS33 [get_ports RsRx] 269 | #set_property PACKAGE_PIN A18 [get_ports RsTx] 270 | #set_property IOSTANDARD LVCMOS33 [get_ports RsTx] 271 | 272 | 273 | ##USB HID (PS/2) 274 | #set_property PACKAGE_PIN C17 [get_ports PS2Clk] 275 | #set_property IOSTANDARD LVCMOS33 [get_ports PS2Clk] 276 | #set_property PULLUP true [get_ports PS2Clk] 277 | #set_property PACKAGE_PIN B17 [get_ports PS2Data] 278 | #set_property IOSTANDARD LVCMOS33 [get_ports PS2Data] 279 | #set_property PULLUP true [get_ports PS2Data] 280 | 281 | 282 | ##Quad SPI Flash 283 | ##Note that CCLK_0 cannot be placed in 7 series devices. You can access it using the 284 | ##STARTUPE2 primitive. 285 | #set_property PACKAGE_PIN D18 [get_ports {QspiDB[0]}] 286 | #set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[0]}] 287 | #set_property PACKAGE_PIN D19 [get_ports {QspiDB[1]}] 288 | #set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[1]}] 289 | #set_property PACKAGE_PIN G18 [get_ports {QspiDB[2]}] 290 | #set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[2]}] 291 | #set_property PACKAGE_PIN F18 [get_ports {QspiDB[3]}] 292 | #set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[3]}] 293 | #set_property PACKAGE_PIN K19 [get_ports QspiCSn] 294 | #set_property IOSTANDARD LVCMOS33 [get_ports QspiCSn] 295 | 296 | --------------------------------------------------------------------------------