├── .gitattributes ├── .gitignore ├── Projects ├── GPIO │ ├── proj │ │ ├── _READ_ME_.txt │ │ ├── cleanup.cmd │ │ ├── cleanup.sh │ │ └── create_project.tcl │ └── src │ │ ├── constraints │ │ └── Nexys4DDR_Master.xdc │ │ └── hdl │ │ ├── GPIO_Demo.vhd │ │ ├── RGB_controller.vhd │ │ ├── UART_TX_CTRL.vhd │ │ └── debouncer.vhd ├── Keyboard │ ├── proj │ │ ├── _READ_ME_.txt │ │ ├── cleanup.cmd │ │ ├── cleanup.sh │ │ └── create_project.tcl │ └── src │ │ ├── constraints │ │ └── Nexys4DDR_Master.xdc │ │ └── hdl │ │ ├── PS2Receiver.v │ │ ├── Seg_7_Display.v │ │ ├── debouncer.v │ │ └── top.v ├── Music_Looper_Demo │ ├── proj │ │ ├── _READ_ME_.txt │ │ ├── cleanup.cmd │ │ ├── cleanup.sh │ │ └── create_project.tcl │ └── src │ │ ├── constraints │ │ └── Nexys4DDR_Master.xdc │ │ ├── hdl │ │ ├── AnalogXADC.v │ │ ├── Binary_to_BCD_B_bcdout.v │ │ ├── DigitToSeg.v │ │ ├── Ram2Ddr.vhd │ │ ├── counter3bit.v │ │ ├── debounce.v │ │ ├── decoder3_8.v │ │ ├── loop_ctrl.v │ │ ├── looper1_1.v │ │ ├── mem_ctrl.v │ │ ├── mux4_4bus.v │ │ ├── pwm_module.v │ │ ├── segClkDevider.v │ │ └── sevensegdecoder.v │ │ └── ip │ │ ├── clk_wiz_0 │ │ ├── clk_wiz_0.upgrade_log │ │ ├── clk_wiz_0.xci │ │ └── clk_wiz_0.xml │ │ ├── mig_7series_0 │ │ ├── mig_7series_0.vho │ │ ├── mig_7series_0.xci │ │ ├── mig_7series_0.xml │ │ ├── mig_7series_0 │ │ │ ├── datasheet.txt │ │ │ ├── docs │ │ │ │ └── phy_only_support_readme.txt │ │ │ ├── example_design │ │ │ │ ├── log.txt │ │ │ │ ├── par │ │ │ │ │ ├── example_top.xdc │ │ │ │ │ └── readme.txt │ │ │ │ ├── rtl │ │ │ │ │ ├── example_top.vhd │ │ │ │ │ └── traffic_gen │ │ │ │ │ │ ├── mig_7series_v2_3_afifo.v │ │ │ │ │ │ ├── mig_7series_v2_3_cmd_gen.v │ │ │ │ │ │ ├── mig_7series_v2_3_cmd_prbs_gen.v │ │ │ │ │ │ ├── mig_7series_v2_3_data_prbs_gen.v │ │ │ │ │ │ ├── mig_7series_v2_3_init_mem_pattern_ctr.v │ │ │ │ │ │ ├── mig_7series_v2_3_memc_flow_vcontrol.v │ │ │ │ │ │ ├── mig_7series_v2_3_memc_traffic_gen.v │ │ │ │ │ │ ├── mig_7series_v2_3_rd_data_gen.v │ │ │ │ │ │ ├── mig_7series_v2_3_read_data_path.v │ │ │ │ │ │ ├── mig_7series_v2_3_read_posted_fifo.v │ │ │ │ │ │ ├── mig_7series_v2_3_s7ven_data_gen.v │ │ │ │ │ │ ├── mig_7series_v2_3_tg_prbs_gen.v │ │ │ │ │ │ ├── mig_7series_v2_3_tg_status.v │ │ │ │ │ │ ├── mig_7series_v2_3_traffic_gen_top.v │ │ │ │ │ │ ├── mig_7series_v2_3_vio_init_pattern_bram.v │ │ │ │ │ │ ├── mig_7series_v2_3_wr_data_gen.v │ │ │ │ │ │ └── mig_7series_v2_3_write_data_path.v │ │ │ │ └── sim │ │ │ │ │ ├── ddr2_model.v │ │ │ │ │ ├── ddr2_model_parameters.vh │ │ │ │ │ ├── ies_run.sh │ │ │ │ │ ├── readme.txt │ │ │ │ │ ├── sim.do │ │ │ │ │ ├── sim_tb_top.v │ │ │ │ │ ├── vcs_run.sh │ │ │ │ │ ├── wiredly.v │ │ │ │ │ ├── xsim_files.prj │ │ │ │ │ ├── xsim_options.tcl │ │ │ │ │ └── xsim_run.bat │ │ │ ├── mig.prj │ │ │ └── user_design │ │ │ │ ├── log.txt │ │ │ │ └── rtl │ │ │ │ └── mig_7series_0_mig_sim.vhd │ │ ├── mig_7series_0_xmdf.tcl │ │ ├── mig_a.prj │ │ ├── mig_b.prj │ │ ├── tcl.log │ │ ├── xil_txt.in │ │ └── xil_txt.out │ │ └── xadc_wiz_0 │ │ ├── xadc_wiz_0.xci │ │ └── xadc_wiz_0.xml ├── User_Demo │ ├── proj │ │ ├── _READ_ME_.txt │ │ ├── cleanup.cmd │ │ ├── cleanup.sh │ │ └── create_project.tcl │ └── src │ │ ├── constraints │ │ └── Nexys4DDR_C.xdc │ │ ├── hdl │ │ ├── ADXL362Ctrl.vhd │ │ ├── AccelArithmetics.vhd │ │ ├── AccelDisplay.vhd │ │ ├── AccelerometerCtl.vhd │ │ ├── AudioDemo.vhd │ │ ├── Dbncr.vhd │ │ ├── FPGAMonitor.vhd │ │ ├── LedBar.vhd │ │ ├── LocalRst.vhd │ │ ├── LogoDisplay.vhd │ │ ├── MicDisplay.vhd │ │ ├── MouseCtl.vhd │ │ ├── MouseDisplay.vhd │ │ ├── Nexys4DdrUserDemo.vhd │ │ ├── OverlayCtl.vhd │ │ ├── PdmDes.vhd │ │ ├── PdmSer.vhd │ │ ├── Ps2Interface.vhd │ │ ├── Pwm.vhd │ │ ├── Ram2Ddr.vhd │ │ ├── RamCntrl.vhd │ │ ├── RgbLed.vhd │ │ ├── RgbLedDisplay.vhd │ │ ├── SPI_If.vhd │ │ ├── TWICtl.vhd │ │ ├── TempDisplay.vhd │ │ ├── TempSensorCtl.vhd │ │ ├── Vga.vhd │ │ ├── sSegDemo.vhd │ │ └── sSegDisplay.vhd │ │ ├── ip │ │ ├── BRAM_1 │ │ │ ├── BRAM_1.upgrade_log │ │ │ ├── BRAM_1.xci │ │ │ └── BRAM_1.xml │ │ ├── ClkGen │ │ │ ├── ClkGen.upgrade_log │ │ │ ├── ClkGen.xci │ │ │ └── ClkGen.xml │ │ ├── PxlClkGen │ │ │ ├── PxlClkGen.upgrade_log │ │ │ ├── PxlClkGen.xci │ │ │ └── PxlClkGen.xml │ │ ├── Square_Root │ │ │ ├── Square_Root.upgrade_log │ │ │ ├── Square_Root.xci │ │ │ └── Square_Root.xml │ │ └── ddr │ │ │ ├── ddr.upgrade_log │ │ │ ├── ddr.vho │ │ │ ├── ddr.xci │ │ │ ├── ddr.xml │ │ │ ├── ddr │ │ │ ├── datasheet.txt │ │ │ ├── docs │ │ │ │ └── phy_only_support_readme.txt │ │ │ ├── example_design │ │ │ │ ├── log.txt │ │ │ │ ├── par │ │ │ │ │ ├── example_top.xdc │ │ │ │ │ └── readme.txt │ │ │ │ ├── rtl │ │ │ │ │ ├── example_top.vhd │ │ │ │ │ └── traffic_gen │ │ │ │ │ │ ├── mig_7series_v2_3_afifo.v │ │ │ │ │ │ ├── mig_7series_v2_3_cmd_gen.v │ │ │ │ │ │ ├── mig_7series_v2_3_cmd_prbs_gen.v │ │ │ │ │ │ ├── mig_7series_v2_3_data_prbs_gen.v │ │ │ │ │ │ ├── mig_7series_v2_3_init_mem_pattern_ctr.v │ │ │ │ │ │ ├── mig_7series_v2_3_memc_flow_vcontrol.v │ │ │ │ │ │ ├── mig_7series_v2_3_memc_traffic_gen.v │ │ │ │ │ │ ├── mig_7series_v2_3_rd_data_gen.v │ │ │ │ │ │ ├── mig_7series_v2_3_read_data_path.v │ │ │ │ │ │ ├── mig_7series_v2_3_read_posted_fifo.v │ │ │ │ │ │ ├── mig_7series_v2_3_s7ven_data_gen.v │ │ │ │ │ │ ├── mig_7series_v2_3_tg_prbs_gen.v │ │ │ │ │ │ ├── mig_7series_v2_3_tg_status.v │ │ │ │ │ │ ├── mig_7series_v2_3_traffic_gen_top.v │ │ │ │ │ │ ├── mig_7series_v2_3_vio_init_pattern_bram.v │ │ │ │ │ │ ├── mig_7series_v2_3_wr_data_gen.v │ │ │ │ │ │ └── mig_7series_v2_3_write_data_path.v │ │ │ │ └── sim │ │ │ │ │ ├── ddr2_model.v │ │ │ │ │ ├── ddr2_model_parameters.vh │ │ │ │ │ ├── ies_run.sh │ │ │ │ │ ├── readme.txt │ │ │ │ │ ├── sim.do │ │ │ │ │ ├── sim_tb_top.v │ │ │ │ │ ├── vcs_run.sh │ │ │ │ │ ├── wiredly.v │ │ │ │ │ ├── xsim_files.prj │ │ │ │ │ ├── xsim_options.tcl │ │ │ │ │ └── xsim_run.bat │ │ │ ├── mig.prj │ │ │ └── user_design │ │ │ │ ├── log.txt │ │ │ │ └── rtl │ │ │ │ └── ddr_mig_sim.vhd │ │ │ ├── ddr_xmdf.tcl │ │ │ ├── tcl.log │ │ │ ├── xil_txt.in │ │ │ └── xil_txt.out │ │ └── others │ │ ├── Nexys4_Overlay.bmp │ │ ├── Nexys4_Overlay.coe │ │ ├── Nexys4_all.bmp │ │ └── Nexys4_all.coe └── XADC_Demo │ ├── proj │ ├── _READ_ME_.txt │ ├── cleanup.cmd │ ├── cleanup.sh │ └── create_project.tcl │ └── src │ ├── constraints │ └── Nexys4DDR_Master.xdc │ ├── hdl │ ├── DigitToSeg.v │ ├── UART_TX_CTRL.vhd │ ├── XADCdemo.v │ ├── counter3bit.v │ ├── decoder3_8.v │ ├── mux4_4bus.v │ ├── segClkDevider.v │ └── sevensegdecoder.v │ └── ip │ └── xadc_wiz_0 │ ├── xadc_wiz_0.upgrade_log │ ├── xadc_wiz_0.xci │ └── xadc_wiz_0.xml └── Resources └── XDC └── Nexys4DDR_Master.xdc /.gitattributes: -------------------------------------------------------------------------------- 1 | # Auto detect text files and perform LF normalization 2 | * text=auto 3 | 4 | # Custom for Visual Studio 5 | *.cs diff=csharp 6 | 7 | # Standard to msysgit 8 | *.doc diff=astextplain 9 | *.DOC diff=astextplain 10 | *.docx diff=astextplain 11 | *.DOCX diff=astextplain 12 | *.dot diff=astextplain 13 | *.DOT diff=astextplain 14 | *.pdf diff=astextplain 15 | *.PDF diff=astextplain 16 | *.rtf diff=astextplain 17 | *.RTF diff=astextplain 18 | -------------------------------------------------------------------------------- /.gitignore: -------------------------------------------------------------------------------- 1 | # Windows image file caches 2 | Thumbs.db 3 | ehthumbs.db 4 | 5 | # Folder config file 6 | Desktop.ini 7 | 8 | # Recycle Bin used on file shares 9 | $RECYCLE.BIN/ 10 | 11 | # Windows Installer files 12 | *.cab 13 | *.msi 14 | *.msm 15 | *.msp 16 | 17 | # Windows shortcuts 18 | *.lnk 19 | 20 | # ========================= 21 | # Operating System Files 22 | # ========================= 23 | 24 | # OSX 25 | # ========================= 26 | 27 | .DS_Store 28 | .AppleDouble 29 | .LSOverride 30 | 31 | # Thumbnails 32 | ._* 33 | 34 | # Files that might appear on external disk 35 | .Spotlight-V100 36 | .Trashes 37 | 38 | # Directories potentially created on remote AFP share 39 | .AppleDB 40 | .AppleDesktop 41 | Network Trash Folder 42 | Temporary Items 43 | .apdisk 44 | 45 | *.jou 46 | *.log 47 | *.str 48 | *.xpr 49 | *.Xil 50 | *.cache 51 | *.data 52 | *.runs 53 | *.hw 54 | *.zip 55 | *.html 56 | *.bit 57 | *.elf 58 | *.bin 59 | *config_settings 60 | *example_designs 61 | *.debug 62 | *~ 63 | 64 | #Digilent Added ignore rules for Vivado projects 65 | 66 | # sdk exclusions 67 | Projects/*/sdk*/.metadata 68 | Projects/*/sdk*/**/*RemoteSystemsTempFiles 69 | Projects/*/sdk*/**/*Debug 70 | Projects/*/sdk*/**/*Release 71 | Projects/*/sdk*/**/*webtalk 72 | 73 | # ignore everything in the hw_platform 74 | Projects/*/sdk*/*hw_platform*/* 75 | # except 76 | !Projects/*/sdk*/*hw_platform*/*.hdf 77 | !Projects/*/sdk*/*hw_platform*/.*project 78 | 79 | # ignore everything in the BSP 80 | Projects/*/sdk*/*_bsp*/* 81 | # except 82 | !Projects/*/sdk*/*_bsp*/system.mss 83 | !Projects/*/sdk*/*_bsp*/Makefile 84 | !Projects/*/sdk*/*_bsp*/.*project 85 | 86 | # Make sure we keep only xci files in repo ip src subfolder 87 | Projects/*/repo/*/ip/*/src/*/* 88 | # Ignore 'generated_ip' directory inside repo/ip 89 | Projects/*/repo/*/ip/*/generated_ip 90 | !Projects/*/repo/*/ip/*/src/*/ 91 | !Projects/*/repo/*/ip/*/src/*/*.xci 92 | !Projects/*/repo/*/ip/*/src/*/*.patch 93 | !Projects/*/repo/*/ip/*/src/*/*.tcl 94 | 95 | # Make sure we keep only xci files in ip src subfolder 96 | Projects/*/src/ip/* 97 | !Projects/*/src/ip/*/ 98 | !Projects/*/src/ip/*/*.xci 99 | !Projects/*/src/ip/*/*.prj 100 | 101 | # Do not ignore anything in src/others 102 | !Projects/*/src/others/* 103 | 104 | # ignore everything in project folder 105 | Projects/*/proj/* 106 | # except this file and project generators 107 | !Projects/*/proj/create_project*.tcl 108 | !Projects/*/proj/cleanup.cmd 109 | !Projects/*/proj/cleanup.sh 110 | 111 | -------------------------------------------------------------------------------- /Projects/GPIO/proj/_READ_ME_.txt: -------------------------------------------------------------------------------- 1 | In order to run the create_project script successfully, the folder must be in its initial state 2 | containing only the cleanup, create_project scripts, and this document. 3 | 4 | To restore the folder to its initial state, double-click the cleanup Windows Command Script. 5 | 6 | !!!!CAUTION!!!! 7 | 8 | Moving or copying the cleanup Windows Command Script can result in unintentional loss of data on your 9 | system. The script contains a short list of specific files to ignore once it is run, all other files 10 | and folders within its directory location will be ERASED. Use this only within the project folder as 11 | instructed. 12 | 13 | See material on the usage of demo projects at reference.digilentinc.com -------------------------------------------------------------------------------- /Projects/GPIO/proj/cleanup.cmd: -------------------------------------------------------------------------------- 1 | @echo off 2 | rem delete all files from subfolders 3 | for /d /r %%i in (*) do del /f /q %%i\* 4 | rem delete all subfolders 5 | for /d %%i in (*) do rd /S /Q %%i 6 | 7 | rem unmark read only from all files 8 | attrib -R .\* /S 9 | 10 | rem mark read only those we wish to keep 11 | attrib +R .\create_project.tcl 12 | attrib +R .\cleanup.sh 13 | attrib +R .\cleanup.cmd 14 | attrib +R .\.gitignore 15 | attrib +R .\_READ_ME_.txt 16 | 17 | rem delete all non read-only 18 | del /Q /A:-R .\* 19 | 20 | rem unmark read-only 21 | attrib -R .\* 22 | -------------------------------------------------------------------------------- /Projects/GPIO/proj/cleanup.sh: -------------------------------------------------------------------------------- 1 | # This script is useful for cleaning up the 'project' 2 | # directory of a Digilent Vivado-project git repository 3 | ### 4 | # Run the following command to change permissions of 5 | # this 'cleanup' file if needed: 6 | # chmod u+x cleanup.sh 7 | ### 8 | # Remove directories/subdirectories 9 | find . -mindepth 1 -type d -exec rm -rf {} + 10 | # Remove any other files than: 11 | find . -type f ! -name 'cleanup.sh' \ 12 | ! -name 'cleanup.cmd' \ 13 | ! -name 'create_project.tcl' \ 14 | ! -name '.gitignore' \ 15 | -exec rm -rf {} + 16 | -------------------------------------------------------------------------------- /Projects/GPIO/proj/create_project.tcl: -------------------------------------------------------------------------------- 1 | # Run this script to create the Vivado project files in the WORKING DIRECTORY 2 | # If ::create_path global variable is set, the project is created under that path instead of the working dir 3 | 4 | if {[info exists ::create_path]} { 5 | set dest_dir $::create_path 6 | } else { 7 | set dest_dir [pwd] 8 | } 9 | puts "INFO: Creating new project in $dest_dir" 10 | 11 | # Set the reference directory for source file relative paths (by default the value is script directory path) 12 | set proj_name "GPIO" 13 | 14 | # Set the reference directory for source file relative paths (by default the value is script directory path) 15 | set origin_dir ".." 16 | 17 | # Set the directory path for the original project from where this script was exported 18 | set orig_proj_dir "[file normalize "$origin_dir/proj"]" 19 | 20 | set src_dir $origin_dir/src 21 | set repo_dir $origin_dir/repo 22 | 23 | # Set the board part number 24 | set part_num "xc7a100tcsg324-3" 25 | 26 | # Create project 27 | create_project $proj_name $dest_dir 28 | 29 | # Set the directory path for the new project 30 | set proj_dir [get_property directory [current_project]] 31 | 32 | # Set project properties 33 | set obj [get_projects $proj_name] 34 | set_property "default_lib" "xil_defaultlib" $obj 35 | set_property "part" "$part_num" $obj 36 | set_property "simulator_language" "Mixed" $obj 37 | set_property "target_language" "VHDL" $obj 38 | 39 | # Create 'sources_1' fileset (if not found) 40 | if {[string equal [get_filesets -quiet sources_1] ""]} { 41 | create_fileset -srcset sources_1 42 | } 43 | 44 | # Create 'constrs_1' fileset (if not found) 45 | if {[string equal [get_filesets -quiet constrs_1] ""]} { 46 | create_fileset -constrset constrs_1 47 | } 48 | 49 | # Set IP repository paths 50 | set obj [get_filesets sources_1] 51 | set_property "ip_repo_paths" "[file normalize $repo_dir]" $obj 52 | 53 | # Add conventional sources 54 | add_files -quiet $src_dir/hdl 55 | 56 | # Add IPs 57 | add_files -quiet [glob -nocomplain ../src/ip/*/*.xci] 58 | 59 | # Add constraints 60 | add_files -fileset constrs_1 -quiet $src_dir/constraints 61 | 62 | # Refresh IP Repositories 63 | update_ip_catalog 64 | 65 | # Create 'synth_1' run (if not found) 66 | if {[string equal [get_runs -quiet synth_1] ""]} { 67 | create_run -name synth_1 -part $part_num -flow {Vivado Synthesis 2014} -strategy "Flow_PerfOptimized_High" -constrset constrs_1 68 | } else { 69 | set_property strategy "Flow_PerfOptimized_High" [get_runs synth_1] 70 | set_property flow "Vivado Synthesis 2014" [get_runs synth_1] 71 | } 72 | set obj [get_runs synth_1] 73 | set_property "part" "$part_num" $obj 74 | set_property "steps.synth_design.args.fanout_limit" "400" $obj 75 | set_property "steps.synth_design.args.fsm_extraction" "one_hot" $obj 76 | set_property "steps.synth_design.args.keep_equivalent_registers" "1" $obj 77 | set_property "steps.synth_design.args.resource_sharing" "off" $obj 78 | set_property "steps.synth_design.args.no_lc" "1" $obj 79 | set_property "steps.synth_design.args.shreg_min_size" "5" $obj 80 | 81 | # set the current synth run 82 | current_run -synthesis [get_runs synth_1] 83 | 84 | # Create 'impl_1' run (if not found) 85 | if {[string equal [get_runs -quiet impl_1] ""]} { 86 | create_run -name impl_1 -part $part_num -flow {Vivado Implementation 2014} -strategy "Vivado Implementation Defaults" -constrset constrs_1 -parent_run synth_1 87 | } else { 88 | set_property strategy "Vivado Implementation Defaults" [get_runs impl_1] 89 | set_property flow "Vivado Implementation 2014" [get_runs impl_1] 90 | } 91 | set obj [get_runs impl_1] 92 | set_property "part" "$part_num" $obj 93 | set_property "steps.write_bitstream.args.bin_file" "1" $obj 94 | 95 | # set the current impl run 96 | current_run -implementation [get_runs impl_1] 97 | 98 | puts "INFO: Project created:$proj_name" 99 | 100 | # Comment the following section, if there is no block design 101 | # Create block design 102 | source $origin_dir/src/bd/bt_gpio.tcl 103 | 104 | # Generate the wrapper 105 | set design_name [get_bd_designs] 106 | make_wrapper -files [get_files $design_name.bd] -top -import 107 | 108 | set obj [get_filesets sources_1] 109 | set_property "top" "bt_gpio_top" $obj 110 | 111 | puts "INFO: Block design created: $design_name.bd" 112 | -------------------------------------------------------------------------------- /Projects/GPIO/src/hdl/RGB_controller.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------------------- 2 | -- RGB_controller.vhd -- Nexys4 RGB LED controller 3 | ---------------------------------------------------------------------------- 4 | -- Author: Marshall Wingerson 5 | -- Copyright 2013 Digilent, Inc. 6 | ---------------------------------------------------------------------------- 7 | -- 8 | ---------------------------------------------------------------------------- 9 | -- Revision History: 10 | -- 08/08/2013(MarshallW): Created 11 | -- 08/30/2013(SamB): Modified RGB pattern 12 | -- Added comments 13 | ---------------------------------------------------------------------------- 14 | 15 | LIBRARY IEEE; 16 | USE IEEE.STD_LOGIC_1164.ALL; 17 | USE IEEE.STD_LOGIC_UNSIGNED.ALL; 18 | USE IEEE.NUMERIC_STD.ALL; 19 | 20 | entity RGB_controller is 21 | port( 22 | GCLK : in std_logic; 23 | RGB_LED_1_O : out std_logic_vector(2 downto 0); 24 | RGB_LED_2_O : out std_logic_vector(2 downto 0) 25 | ); 26 | end RGB_controller; 27 | 28 | architecture Behavioral of RGB_controller is 29 | --counter signals 30 | constant window: std_logic_vector(7 downto 0) := "11111111"; 31 | signal windowcount: std_logic_vector(7 downto 0) := (others => '0'); 32 | 33 | constant deltacountMax: std_logic_vector(19 downto 0) := std_logic_vector(to_unsigned(1000000, 20)); 34 | signal deltacount: std_logic_vector(19 downto 0) := (others => '0'); 35 | 36 | constant valcountMax: std_logic_vector(8 downto 0) := "101111111"; 37 | signal valcount: std_logic_vector(8 downto 0) := (others => '0'); 38 | 39 | --color intensity signals 40 | signal incVal: std_logic_vector(7 downto 0); 41 | signal decVal: std_logic_vector(7 downto 0); 42 | 43 | signal redVal: std_logic_vector(7 downto 0); 44 | signal greenVal: std_logic_vector(7 downto 0); 45 | signal blueVal: std_logic_vector(7 downto 0); 46 | 47 | signal redVal2: std_logic_vector(7 downto 0); 48 | signal greenVal2: std_logic_vector(7 downto 0); 49 | signal blueVal2: std_logic_vector(7 downto 0); 50 | 51 | --PWM registers 52 | signal rgbLedReg1: std_logic_vector(2 downto 0); 53 | signal rgbLedReg2: std_logic_vector(2 downto 0); 54 | 55 | begin 56 | 57 | window_counter:process(GCLK) 58 | begin 59 | if(rising_edge(GCLK)) then 60 | if windowcount < (window) then 61 | windowcount <= windowcount + 1; 62 | else 63 | windowcount <= (others => '0'); 64 | end if; 65 | end if; 66 | end process; 67 | 68 | color_change_counter:process(GCLK) 69 | begin 70 | if(rising_edge(GCLK)) then 71 | if(deltacount < deltacountMax) then 72 | deltacount <= deltacount + 1; 73 | else 74 | deltacount <= (others => '0'); 75 | end if; 76 | end if; 77 | end process; 78 | 79 | color_intensity_counter:process(GCLK) 80 | begin 81 | if(rising_edge(GCLK)) then 82 | if(deltacount = 0) then 83 | if(valcount < valcountMax) then 84 | valcount <= valcount + 1; 85 | else 86 | valcount <= (others => '0'); 87 | end if; 88 | end if; 89 | end if; 90 | end process; 91 | 92 | incVal <= "0" & valcount(6 downto 0); 93 | 94 | --The folowing code sets decVal to (128 - incVal) 95 | decVal(7) <= '0'; 96 | decVal(6) <= not(valcount(6)); 97 | decVal(5) <= not(valcount(5)); 98 | decVal(4) <= not(valcount(4)); 99 | decVal(3) <= not(valcount(3)); 100 | decVal(2) <= not(valcount(2)); 101 | decVal(1) <= not(valcount(1)); 102 | decVal(0) <= not(valcount(0)); 103 | 104 | redVal <= incVal when (valcount(8 downto 7) = "00") else 105 | decVal when (valcount(8 downto 7) = "01") else 106 | (others => '0'); 107 | greenVal <= decVal when (valcount(8 downto 7) = "00") else 108 | (others => '0') when (valcount(8 downto 7) = "01") else 109 | incVal; 110 | blueVal <= (others => '0') when (valcount(8 downto 7) = "00") else 111 | incVal when (valcount(8 downto 7) = "01") else 112 | decVal; 113 | 114 | redVal2 <= incVal when (valcount(8 downto 7) = "00") else 115 | decVal when (valcount(8 downto 7) = "01") else 116 | (others => '0'); 117 | greenVal2 <= decVal when (valcount(8 downto 7) = "00") else 118 | (others => '0') when (valcount(8 downto 7) = "01") else 119 | incVal; 120 | blueVal2 <= (others => '0') when (valcount(8 downto 7) = "00") else 121 | incVal when (valcount(8 downto 7) = "01") else 122 | decVal; 123 | 124 | 125 | --red processes 126 | red_comp:process(GCLK) 127 | begin 128 | if(rising_edge(GCLK)) then 129 | if((redVal) > windowcount) then 130 | rgbLedReg1(2) <= '1'; 131 | else 132 | rgbLedReg1(2) <= '0'; 133 | end if; 134 | end if; 135 | end process; 136 | 137 | 138 | --green processes 139 | green_comp:process(GCLK) 140 | begin 141 | if(rising_edge(GCLK)) then 142 | if((greenVal) > windowcount) then 143 | rgbLedReg1(1) <= '1'; 144 | else 145 | rgbLedReg1(1) <= '0'; 146 | end if; 147 | end if; 148 | end process; 149 | 150 | 151 | --blue processes 152 | blue_comp:process(GCLK) 153 | begin 154 | if(rising_edge(GCLK)) then 155 | if((blueVal) > windowcount) then 156 | rgbLedReg1(0) <= '1'; 157 | else 158 | rgbLedReg1(0) <= '0'; 159 | end if; 160 | end if; 161 | end process; 162 | 163 | --RGB2 processes--- 164 | --red2 processes 165 | red2_comp:process(GCLK) 166 | begin 167 | if(rising_edge(GCLK)) then 168 | if((redVal2) > windowcount) then 169 | rgbLedReg2(2) <= '1'; 170 | else 171 | rgbLedReg2(2) <= '0'; 172 | end if; 173 | end if; 174 | end process; 175 | 176 | 177 | --green2 processes 178 | green2_comp:process(GCLK) 179 | begin 180 | if(rising_edge(GCLK)) then 181 | if((greenVal2) > windowcount) then 182 | rgbLedReg2(1) <= '1'; 183 | else 184 | rgbLedReg2(1) <= '0'; 185 | end if; 186 | end if; 187 | end process; 188 | 189 | 190 | --blue2 processes 191 | blue2_comp:process(GCLK) 192 | begin 193 | if(rising_edge(GCLK)) then 194 | if((blueVal2) > windowcount) then 195 | rgbLedReg2(0) <= '1'; 196 | else 197 | rgbLedReg2(0) <= '0'; 198 | end if; 199 | end if; 200 | end process; 201 | 202 | RGB_LED_1_O <= rgbLedReg1; 203 | RGB_LED_2_O <= rgbLedReg2; 204 | 205 | end Behavioral; 206 | 207 | -------------------------------------------------------------------------------- /Projects/GPIO/src/hdl/UART_TX_CTRL.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------------------- 2 | -- UART_TX_CTRL.vhd -- UART Data Transfer Component 3 | ---------------------------------------------------------------------------- 4 | -- Author: Sam Bobrowicz 5 | -- Copyright 2011 Digilent, Inc. 6 | ---------------------------------------------------------------------------- 7 | -- 8 | ---------------------------------------------------------------------------- 9 | -- This component may be used to transfer data over a UART device. It will 10 | -- serialize a byte of data and transmit it over a TXD line. The serialized 11 | -- data has the following characteristics: 12 | -- *9600 Baud Rate 13 | -- *8 data bits, LSB first 14 | -- *1 stop bit 15 | -- *no parity 16 | -- 17 | -- Port Descriptions: 18 | -- 19 | -- SEND - Used to trigger a send operation. The upper layer logic should 20 | -- set this signal high for a single clock cycle to trigger a 21 | -- send. When this signal is set high DATA must be valid . Should 22 | -- not be asserted unless READY is high. 23 | -- DATA - The parallel data to be sent. Must be valid the clock cycle 24 | -- that SEND has gone high. 25 | -- CLK - A 100 MHz clock is expected 26 | -- READY - This signal goes low once a send operation has begun and 27 | -- remains low until it has completed and the module is ready to 28 | -- send another byte. 29 | -- UART_TX - This signal should be routed to the appropriate TX pin of the 30 | -- external UART device. 31 | -- 32 | ---------------------------------------------------------------------------- 33 | -- 34 | ---------------------------------------------------------------------------- 35 | -- Revision History: 36 | -- 08/08/2011(SamB): Created using Xilinx Tools 13.2 37 | ---------------------------------------------------------------------------- 38 | library IEEE; 39 | use IEEE.STD_LOGIC_1164.ALL; 40 | use IEEE.std_logic_unsigned.all; 41 | 42 | entity UART_TX_CTRL is 43 | Port ( SEND : in STD_LOGIC; 44 | DATA : in STD_LOGIC_VECTOR (7 downto 0); 45 | CLK : in STD_LOGIC; 46 | READY : out STD_LOGIC; 47 | UART_TX : out STD_LOGIC); 48 | end UART_TX_CTRL; 49 | 50 | architecture Behavioral of UART_TX_CTRL is 51 | 52 | type TX_STATE_TYPE is (RDY, LOAD_BIT, SEND_BIT); 53 | 54 | constant BIT_TMR_MAX : std_logic_vector(13 downto 0) := "10100010110000"; --10416 = (round(100MHz / 9600)) - 1 55 | constant BIT_INDEX_MAX : natural := 10; 56 | 57 | --Counter that keeps track of the number of clock cycles the current bit has been held stable over the 58 | --UART TX line. It is used to signal when the ne 59 | signal bitTmr : std_logic_vector(13 downto 0) := (others => '0'); 60 | 61 | --combinatorial logic that goes high when bitTmr has counted to the proper value to ensure 62 | --a 9600 baud rate 63 | signal bitDone : std_logic; 64 | 65 | --Contains the index of the next bit in txData that needs to be transferred 66 | signal bitIndex : natural; 67 | 68 | --a register that holds the current data being sent over the UART TX line 69 | signal txBit : std_logic := '1'; 70 | 71 | --A register that contains the whole data packet to be sent, including start and stop bits. 72 | signal txData : std_logic_vector(9 downto 0); 73 | 74 | signal txState : TX_STATE_TYPE := RDY; 75 | 76 | begin 77 | 78 | --Next state logic 79 | next_txState_process : process (CLK) 80 | begin 81 | if (rising_edge(CLK)) then 82 | case txState is 83 | when RDY => 84 | if (SEND = '1') then 85 | txState <= LOAD_BIT; 86 | end if; 87 | when LOAD_BIT => 88 | txState <= SEND_BIT; 89 | when SEND_BIT => 90 | if (bitDone = '1') then 91 | if (bitIndex = BIT_INDEX_MAX) then 92 | txState <= RDY; 93 | else 94 | txState <= LOAD_BIT; 95 | end if; 96 | end if; 97 | when others=> --should never be reached 98 | txState <= RDY; 99 | end case; 100 | end if; 101 | end process; 102 | 103 | bit_timing_process : process (CLK) 104 | begin 105 | if (rising_edge(CLK)) then 106 | if (txState = RDY) then 107 | bitTmr <= (others => '0'); 108 | else 109 | if (bitDone = '1') then 110 | bitTmr <= (others => '0'); 111 | else 112 | bitTmr <= bitTmr + 1; 113 | end if; 114 | end if; 115 | end if; 116 | end process; 117 | 118 | bitDone <= '1' when (bitTmr = BIT_TMR_MAX) else 119 | '0'; 120 | 121 | bit_counting_process : process (CLK) 122 | begin 123 | if (rising_edge(CLK)) then 124 | if (txState = RDY) then 125 | bitIndex <= 0; 126 | elsif (txState = LOAD_BIT) then 127 | bitIndex <= bitIndex + 1; 128 | end if; 129 | end if; 130 | end process; 131 | 132 | tx_data_latch_process : process (CLK) 133 | begin 134 | if (rising_edge(CLK)) then 135 | if (SEND = '1') then 136 | txData <= '1' & DATA & '0'; 137 | end if; 138 | end if; 139 | end process; 140 | 141 | tx_bit_process : process (CLK) 142 | begin 143 | if (rising_edge(CLK)) then 144 | if (txState = RDY) then 145 | txBit <= '1'; 146 | elsif (txState = LOAD_BIT) then 147 | txBit <= txData(bitIndex); 148 | end if; 149 | end if; 150 | end process; 151 | 152 | UART_TX <= txBit; 153 | READY <= '1' when (txState = RDY) else 154 | '0'; 155 | 156 | end Behavioral; 157 | 158 | -------------------------------------------------------------------------------- /Projects/GPIO/src/hdl/debouncer.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------------------- 2 | -- debouncer.vhd -- Signal Debouncer 3 | ---------------------------------------------------------------------------- 4 | -- Author: Sam Bobrowicz 5 | -- Copyright 2011 Digilent, Inc. 6 | ---------------------------------------------------------------------------- 7 | -- 8 | ---------------------------------------------------------------------------- 9 | -- This component is used to debounce signals. It is designed to 10 | -- independently debounce a variable number of signals, the number of which 11 | -- are set using the PORT_WIDTH generic. Debouncing is done by only 12 | -- registering a change in a button state if it remains constant for 13 | -- the number of clocks determined by the DEBNC_CLOCKS generic. 14 | -- 15 | -- Generic Descriptions: 16 | -- 17 | -- PORT_WIDTH - The number of signals to debounce. determines the width 18 | -- of the SIGNAL_I and SIGNAL_O std_logic_vectors 19 | -- DEBNC_CLOCKS - The number of clocks (CLK_I) to wait before registering 20 | -- a change. 21 | -- 22 | -- Port Descriptions: 23 | -- 24 | -- SIGNAL_I - The input signals. A vector of width equal to PORT_WIDTH 25 | -- CLK_I - Input clock 26 | -- SIGNAL_O - The debounced signals. A vector of width equal to PORT_WIDTH 27 | -- 28 | ---------------------------------------------------------------------------- 29 | -- 30 | ---------------------------------------------------------------------------- 31 | -- Revision History: 32 | -- 08/08/2011(SamB): Created using Xilinx Tools 13.2 33 | -- 08/29/2013(SamB): Improved reuseability by using generics 34 | ---------------------------------------------------------------------------- 35 | 36 | library IEEE; 37 | use IEEE.STD_LOGIC_1164.ALL; 38 | use IEEE.std_logic_unsigned.all; 39 | USE IEEE.NUMERIC_STD.ALL; 40 | use IEEE.math_real.all; 41 | 42 | entity debouncer is 43 | Generic ( DEBNC_CLOCKS : INTEGER range 2 to (INTEGER'high) := 2**16; 44 | PORT_WIDTH : INTEGER range 1 to (INTEGER'high) := 5); 45 | Port ( SIGNAL_I : in STD_LOGIC_VECTOR ((PORT_WIDTH - 1) downto 0); 46 | CLK_I : in STD_LOGIC; 47 | SIGNAL_O : out STD_LOGIC_VECTOR ((PORT_WIDTH - 1) downto 0)); 48 | end debouncer; 49 | 50 | architecture Behavioral of debouncer is 51 | 52 | constant CNTR_WIDTH : integer := natural(ceil(LOG2(real(DEBNC_CLOCKS)))); 53 | constant CNTR_MAX : std_logic_vector((CNTR_WIDTH - 1) downto 0) := std_logic_vector(to_unsigned((DEBNC_CLOCKS - 1), CNTR_WIDTH)); 54 | type VECTOR_ARRAY_TYPE is array (integer range <>) of std_logic_vector((CNTR_WIDTH - 1) downto 0); 55 | 56 | signal sig_cntrs_ary : VECTOR_ARRAY_TYPE (0 to (PORT_WIDTH - 1)) := (others=>(others=>'0')); 57 | 58 | signal sig_out_reg : std_logic_vector((PORT_WIDTH - 1) downto 0) := (others => '0'); 59 | 60 | begin 61 | 62 | debounce_process : process (CLK_I) 63 | begin 64 | if (rising_edge(CLK_I)) then 65 | for index in 0 to (PORT_WIDTH - 1) loop 66 | if (sig_cntrs_ary(index) = CNTR_MAX) then 67 | sig_out_reg(index) <= not(sig_out_reg(index)); 68 | end if; 69 | end loop; 70 | end if; 71 | end process; 72 | 73 | counter_process : process (CLK_I) 74 | begin 75 | if (rising_edge(CLK_I)) then 76 | for index in 0 to (PORT_WIDTH - 1) loop 77 | 78 | if ((sig_out_reg(index) = '1') xor (SIGNAL_I(index) = '1')) then 79 | if (sig_cntrs_ary(index) = CNTR_MAX) then 80 | sig_cntrs_ary(index) <= (others => '0'); 81 | else 82 | sig_cntrs_ary(index) <= sig_cntrs_ary(index) + 1; 83 | end if; 84 | else 85 | sig_cntrs_ary(index) <= (others => '0'); 86 | end if; 87 | 88 | end loop; 89 | end if; 90 | end process; 91 | 92 | SIGNAL_O <= sig_out_reg; 93 | 94 | end Behavioral; 95 | 96 | -------------------------------------------------------------------------------- /Projects/Keyboard/proj/_READ_ME_.txt: -------------------------------------------------------------------------------- 1 | In order to run the create_project script successfully, the folder must be in its initial state 2 | containing only the cleanup, create_project scripts, and this document. 3 | 4 | To restore the folder to its initial state, double-click the cleanup Windows Command Script. 5 | 6 | !!!!CAUTION!!!! 7 | 8 | Moving or copying the cleanup Windows Command Script can result in unintentional loss of data on your 9 | system. The script contains a short list of specific files to ignore once it is run, all other files 10 | and folders within its directory location will be ERASED. Use this only within the project folder as 11 | instructed. 12 | 13 | See material on the usage of demo projects at reference.digilentinc.com -------------------------------------------------------------------------------- /Projects/Keyboard/proj/cleanup.cmd: -------------------------------------------------------------------------------- 1 | @echo off 2 | rem delete all files from subfolders 3 | for /d /r %%i in (*) do del /f /q %%i\* 4 | rem delete all subfolders 5 | for /d %%i in (*) do rd /S /Q %%i 6 | 7 | rem unmark read only from all files 8 | attrib -R .\* /S 9 | 10 | rem mark read only those we wish to keep 11 | attrib +R .\create_project.tcl 12 | attrib +R .\cleanup.sh 13 | attrib +R .\cleanup.cmd 14 | attrib +R .\.gitignore 15 | attrib +R .\_READ_ME_.txt 16 | 17 | rem delete all non read-only 18 | del /Q /A:-R .\* 19 | 20 | rem unmark read-only 21 | attrib -R .\* 22 | -------------------------------------------------------------------------------- /Projects/Keyboard/proj/cleanup.sh: -------------------------------------------------------------------------------- 1 | # This script is useful for cleaning up the 'project' 2 | # directory of a Digilent Vivado-project git repository 3 | ### 4 | # Run the following command to change permissions of 5 | # this 'cleanup' file if needed: 6 | # chmod u+x cleanup.sh 7 | ### 8 | # Remove directories/subdirectories 9 | find . -mindepth 1 -type d -exec rm -rf {} + 10 | # Remove any other files than: 11 | find . -type f ! -name 'cleanup.sh' \ 12 | ! -name 'cleanup.cmd' \ 13 | ! -name 'create_project.tcl' \ 14 | ! -name '.gitignore' \ 15 | -exec rm -rf {} + 16 | -------------------------------------------------------------------------------- /Projects/Keyboard/proj/create_project.tcl: -------------------------------------------------------------------------------- 1 | # Run this script to create the Vivado project files in the WORKING DIRECTORY 2 | # If ::create_path global variable is set, the project is created under that path instead of the working dir 3 | 4 | if {[info exists ::create_path]} { 5 | set dest_dir $::create_path 6 | } else { 7 | set dest_dir [pwd] 8 | } 9 | puts "INFO: Creating new project in $dest_dir" 10 | 11 | # Set the reference directory for source file relative paths (by default the value is script directory path) 12 | set proj_name "Keyboard" 13 | 14 | # Set the reference directory for source file relative paths (by default the value is script directory path) 15 | set origin_dir ".." 16 | 17 | # Set the directory path for the original project from where this script was exported 18 | set orig_proj_dir "[file normalize "$origin_dir/proj"]" 19 | 20 | set src_dir $origin_dir/src 21 | set repo_dir $origin_dir/repo 22 | 23 | # Set the board part number 24 | set part_num "xc7a100tcsg324-3" 25 | 26 | # Create project 27 | create_project $proj_name $dest_dir 28 | 29 | # Set the directory path for the new project 30 | set proj_dir [get_property directory [current_project]] 31 | 32 | # Set project properties 33 | set obj [get_projects $proj_name] 34 | set_property "default_lib" "xil_defaultlib" $obj 35 | set_property "part" "$part_num" $obj 36 | set_property "simulator_language" "Mixed" $obj 37 | set_property "target_language" "VHDL" $obj 38 | 39 | # Create 'sources_1' fileset (if not found) 40 | if {[string equal [get_filesets -quiet sources_1] ""]} { 41 | create_fileset -srcset sources_1 42 | } 43 | 44 | # Create 'constrs_1' fileset (if not found) 45 | if {[string equal [get_filesets -quiet constrs_1] ""]} { 46 | create_fileset -constrset constrs_1 47 | } 48 | 49 | # Set IP repository paths 50 | set obj [get_filesets sources_1] 51 | set_property "ip_repo_paths" "[file normalize $repo_dir]" $obj 52 | 53 | # Add conventional sources 54 | add_files -quiet $src_dir/hdl 55 | 56 | # Add IPs 57 | add_files -quiet [glob -nocomplain ../src/ip/*/*.xci] 58 | 59 | # Add constraints 60 | add_files -fileset constrs_1 -quiet $src_dir/constraints 61 | 62 | # Refresh IP Repositories 63 | update_ip_catalog 64 | 65 | # Create 'synth_1' run (if not found) 66 | if {[string equal [get_runs -quiet synth_1] ""]} { 67 | create_run -name synth_1 -part $part_num -flow {Vivado Synthesis 2014} -strategy "Flow_PerfOptimized_High" -constrset constrs_1 68 | } else { 69 | set_property strategy "Flow_PerfOptimized_High" [get_runs synth_1] 70 | set_property flow "Vivado Synthesis 2014" [get_runs synth_1] 71 | } 72 | set obj [get_runs synth_1] 73 | set_property "part" "$part_num" $obj 74 | set_property "steps.synth_design.args.fanout_limit" "400" $obj 75 | set_property "steps.synth_design.args.fsm_extraction" "one_hot" $obj 76 | set_property "steps.synth_design.args.keep_equivalent_registers" "1" $obj 77 | set_property "steps.synth_design.args.resource_sharing" "off" $obj 78 | set_property "steps.synth_design.args.no_lc" "1" $obj 79 | set_property "steps.synth_design.args.shreg_min_size" "5" $obj 80 | 81 | # set the current synth run 82 | current_run -synthesis [get_runs synth_1] 83 | 84 | # Create 'impl_1' run (if not found) 85 | if {[string equal [get_runs -quiet impl_1] ""]} { 86 | create_run -name impl_1 -part $part_num -flow {Vivado Implementation 2014} -strategy "Vivado Implementation Defaults" -constrset constrs_1 -parent_run synth_1 87 | } else { 88 | set_property strategy "Vivado Implementation Defaults" [get_runs impl_1] 89 | set_property flow "Vivado Implementation 2014" [get_runs impl_1] 90 | } 91 | set obj [get_runs impl_1] 92 | set_property "part" "$part_num" $obj 93 | set_property "steps.write_bitstream.args.bin_file" "1" $obj 94 | 95 | # set the current impl run 96 | current_run -implementation [get_runs impl_1] 97 | 98 | puts "INFO: Project created:$proj_name" 99 | 100 | # Comment the following section, if there is no block design 101 | # Create block design 102 | source $origin_dir/src/bd/bt_gpio.tcl 103 | 104 | # Generate the wrapper 105 | set design_name [get_bd_designs] 106 | make_wrapper -files [get_files $design_name.bd] -top -import 107 | 108 | set obj [get_filesets sources_1] 109 | set_property "top" "bt_gpio_top" $obj 110 | 111 | puts "INFO: Block design created: $design_name.bd" 112 | -------------------------------------------------------------------------------- /Projects/Keyboard/src/hdl/PS2Receiver.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: Digilent Inc. 4 | // Engineer: Thomas Kappenman 5 | // 6 | // Create Date: 03/03/2015 09:33:36 PM 7 | // Design Name: 8 | // Module Name: PS2Receiver 9 | // Project Name: Nexys4DDR Keyboard Demo 10 | // Target Devices: Nexys4DDR 11 | // Tool Versions: 12 | // Description: PS2 Receiver module used to shift in keycodes from a keyboard plugged into the PS2 port 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | 23 | module PS2Receiver( 24 | input clk, 25 | input kclk, 26 | input kdata, 27 | output [31:0] keycodeout 28 | ); 29 | 30 | 31 | wire kclkf, kdataf; 32 | reg [7:0]datacur; 33 | reg [7:0]dataprev; 34 | reg [3:0]cnt; 35 | reg [31:0]keycode; 36 | reg flag; 37 | 38 | initial begin 39 | keycode[31:0]<=0'h00000000; 40 | cnt<=4'b0000; 41 | flag<=1'b0; 42 | end 43 | 44 | debouncer debounce( 45 | .clk(clk), 46 | .I0(kclk), 47 | .I1(kdata), 48 | .O0(kclkf), 49 | .O1(kdataf) 50 | ); 51 | 52 | always@(negedge(kclkf))begin 53 | case(cnt) 54 | 0:;//Start bit 55 | 1:datacur[0]<=kdataf; 56 | 2:datacur[1]<=kdataf; 57 | 3:datacur[2]<=kdataf; 58 | 4:datacur[3]<=kdataf; 59 | 5:datacur[4]<=kdataf; 60 | 6:datacur[5]<=kdataf; 61 | 7:datacur[6]<=kdataf; 62 | 8:datacur[7]<=kdataf; 63 | 9:flag<=1'b1; 64 | 10:flag<=1'b0; 65 | 66 | endcase 67 | if(cnt<=9) cnt<=cnt+1; 68 | else if(cnt==10) cnt<=0; 69 | 70 | end 71 | 72 | always @(posedge flag)begin 73 | if (dataprev!=datacur)begin 74 | keycode[31:24]<=keycode[23:16]; 75 | keycode[23:16]<=keycode[15:8]; 76 | keycode[15:8]<=dataprev; 77 | keycode[7:0]<=datacur; 78 | dataprev<=datacur; 79 | end 80 | end 81 | 82 | assign keycodeout=keycode; 83 | 84 | endmodule 85 | -------------------------------------------------------------------------------- /Projects/Keyboard/src/hdl/Seg_7_Display.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: Digilent Inc. 4 | // Engineer: Thomas Kappenman 5 | // 6 | // Create Date: 03/03/2015 09:08:33 PM 7 | // Design Name: 8 | // Module Name: seg7decimal 9 | // Project Name: Nexys4DDR Keyboard Demo 10 | // Target Devices: Nexys4DDR 11 | // Tool Versions: 12 | // Description: 7 segment display driver 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module seg7decimal( 22 | 23 | input [31:0] x, 24 | input clk, 25 | output reg [6:0] seg, 26 | output reg [7:0] an, 27 | output wire dp 28 | ); 29 | 30 | 31 | wire [2:0] s; 32 | reg [3:0] digit; 33 | wire [7:0] aen; 34 | reg [19:0] clkdiv; 35 | 36 | assign dp = 1; 37 | assign s = clkdiv[19:17]; 38 | assign aen = 8'b11111111; // all turned off initially 39 | 40 | // quad 4to1 MUX. 41 | 42 | 43 | always @(posedge clk)// or posedge clr) 44 | 45 | case(s) 46 | 0:digit = x[3:0]; // s is 00 -->0 ; digit gets assigned 4 bit value assigned to x[3:0] 47 | 1:digit = x[7:4]; // s is 01 -->1 ; digit gets assigned 4 bit value assigned to x[7:4] 48 | 2:digit = x[11:8]; // s is 10 -->2 ; digit gets assigned 4 bit value assigned to x[11:8 49 | 3:digit = x[15:12]; // s is 11 -->3 ; digit gets assigned 4 bit value assigned to x[15:12] 50 | 4:digit = x[19:16]; // s is 00 -->0 ; digit gets assigned 4 bit value assigned to x[3:0] 51 | 5:digit = x[23:20]; // s is 01 -->1 ; digit gets assigned 4 bit value assigned to x[7:4] 52 | 6:digit = x[27:24]; // s is 10 -->2 ; digit gets assigned 4 bit value assigned to x[11:8 53 | 7:digit = x[31:28]; // s is 11 -->3 ; digit gets assigned 4 bit value assigned to x[15:12] 54 | 55 | default:digit = x[3:0]; 56 | 57 | endcase 58 | 59 | //decoder or truth-table for 7seg display values 60 | always @(*) 61 | 62 | case(digit) 63 | 64 | 65 | //////////<---MSB-LSB<--- 66 | //////////////gfedcba//////////////////////////////////////////// a 67 | 0:seg = 7'b1000000;////0000 __ 68 | 1:seg = 7'b1111001;////0001 f/ /b 69 | 2:seg = 7'b0100100;////0010 g 70 | // __ 71 | 3:seg = 7'b0110000;////0011 e / /c 72 | 4:seg = 7'b0011001;////0100 __ 73 | 5:seg = 7'b0010010;////0101 d 74 | 6:seg = 7'b0000010;////0110 75 | 7:seg = 7'b1111000;////0111 76 | 8:seg = 7'b0000000;////1000 77 | 9:seg = 7'b0010000;////1001 78 | 'hA:seg = 7'b0001000; 79 | 'hB:seg = 7'b0000011; 80 | 'hC:seg = 7'b1000110; 81 | 'hD:seg = 7'b0100001; 82 | 'hE:seg = 7'b0000110; 83 | 'hF:seg = 7'b0001110; 84 | 85 | default: seg = 7'b0000000; // U 86 | 87 | endcase 88 | 89 | 90 | always @(*)begin 91 | an=8'b11111111; 92 | if(aen[s] == 1) 93 | an[s] = 0; 94 | end 95 | 96 | 97 | //clkdiv 98 | 99 | always @(posedge clk) begin 100 | clkdiv <= clkdiv+1; 101 | end 102 | 103 | 104 | endmodule 105 | -------------------------------------------------------------------------------- /Projects/Keyboard/src/hdl/debouncer.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 03/03/2015 09:08:56 PM 7 | // Design Name: 8 | // Module Name: debouncer 9 | // Project Name: 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | 23 | module debouncer( 24 | input clk, 25 | input I0, 26 | input I1, 27 | output reg O0, 28 | output reg O1 29 | ); 30 | 31 | reg [4:0]cnt0, cnt1; 32 | reg Iv0=0,Iv1=0; 33 | reg out0, out1; 34 | 35 | always@(posedge(clk))begin 36 | if (I0==Iv0)begin 37 | if (cnt0==19)O0<=I0; 38 | else cnt0<=cnt0+1; 39 | end 40 | else begin 41 | cnt0<="00000"; 42 | Iv0<=I0; 43 | end 44 | if (I1==Iv1)begin 45 | if (cnt1==19)O1<=I1; 46 | else cnt1<=cnt1+1; 47 | end 48 | else begin 49 | cnt1<="00000"; 50 | Iv1<=I1; 51 | end 52 | end 53 | 54 | endmodule 55 | -------------------------------------------------------------------------------- /Projects/Keyboard/src/hdl/top.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: Digilent Inc. 4 | // Engineer: Thomas Kappenman 5 | // 6 | // Create Date: 03/03/2015 09:06:31 PM 7 | // Design Name: 8 | // Module Name: top 9 | // Project Name: Nexys4DDR Keyboard Demo 10 | // Target Devices: Nexys4DDR 11 | // Tool Versions: 12 | // Description: This project takes keyboard input from the PS2 port, 13 | // and outputs the keyboard scan code to the 7 segment display on the board. 14 | // The scan code is shifted left 2 characters each time a new code is 15 | // read. 16 | // 17 | // Dependencies: 18 | // 19 | // Revision: 20 | // Revision 0.01 - File Created 21 | // Additional Comments: 22 | // 23 | ////////////////////////////////////////////////////////////////////////////////// 24 | 25 | 26 | module top( 27 | input CLK100MHZ, 28 | input PS2_CLK, 29 | input PS2_DATA, 30 | output [6:0]SEG, 31 | output [7:0]AN, 32 | output DP, 33 | output UART_TXD 34 | ); 35 | 36 | reg CLK50MHZ=0; 37 | wire [31:0]keycode; 38 | 39 | always @(posedge(CLK100MHZ))begin 40 | CLK50MHZ<=~CLK50MHZ; 41 | end 42 | 43 | PS2Receiver keyboard ( 44 | .clk(CLK50MHZ), 45 | .kclk(PS2_CLK), 46 | .kdata(PS2_DATA), 47 | .keycodeout(keycode[31:0]) 48 | ); 49 | 50 | seg7decimal sevenSeg ( 51 | .x(keycode[31:0]), 52 | .clk(CLK100MHZ), 53 | .seg(SEG[6:0]), 54 | .an(AN[7:0]), 55 | .dp(DP) 56 | ); 57 | 58 | endmodule 59 | -------------------------------------------------------------------------------- /Projects/Music_Looper_Demo/proj/_READ_ME_.txt: -------------------------------------------------------------------------------- 1 | In order to run the create_project script successfully, the folder must be in its initial state 2 | containing only the cleanup, create_project scripts, and this document. 3 | 4 | To restore the folder to its initial state, double-click the cleanup Windows Command Script. 5 | 6 | !!!!CAUTION!!!! 7 | 8 | Moving or copying the cleanup Windows Command Script can result in unintentional loss of data on your 9 | system. The script contains a short list of specific files to ignore once it is run, all other files 10 | and folders within its directory location will be ERASED. Use this only within the project folder as 11 | instructed. 12 | 13 | See material on the usage of demo projects at reference.digilentinc.com -------------------------------------------------------------------------------- /Projects/Music_Looper_Demo/proj/cleanup.cmd: -------------------------------------------------------------------------------- 1 | @echo off 2 | rem delete all files from subfolders 3 | for /d /r %%i in (*) do del /f /q %%i\* 4 | rem delete all subfolders 5 | for /d %%i in (*) do rd /S /Q %%i 6 | 7 | rem unmark read only from all files 8 | attrib -R .\* /S 9 | 10 | rem mark read only those we wish to keep 11 | attrib +R .\create_project.tcl 12 | attrib +R .\cleanup.sh 13 | attrib +R .\cleanup.cmd 14 | attrib +R .\.gitignore 15 | attrib +R .\_READ_ME_.txt 16 | 17 | rem delete all non read-only 18 | del /Q /A:-R .\* 19 | 20 | rem unmark read-only 21 | attrib -R .\* 22 | -------------------------------------------------------------------------------- /Projects/Music_Looper_Demo/proj/cleanup.sh: -------------------------------------------------------------------------------- 1 | # This script is useful for cleaning up the 'project' 2 | # directory of a Digilent Vivado-project git repository 3 | ### 4 | # Run the following command to change permissions of 5 | # this 'cleanup' file if needed: 6 | # chmod u+x cleanup.sh 7 | ### 8 | # Remove directories/subdirectories 9 | find . -mindepth 1 -type d -exec rm -rf {} + 10 | # Remove any other files than: 11 | find . -type f ! -name 'cleanup.sh' \ 12 | ! -name 'cleanup.cmd' \ 13 | ! -name 'create_project.tcl' \ 14 | ! -name '.gitignore' \ 15 | -exec rm -rf {} + 16 | -------------------------------------------------------------------------------- /Projects/Music_Looper_Demo/proj/create_project.tcl: -------------------------------------------------------------------------------- 1 | # Run this script to create the Vivado project files in the WORKING DIRECTORY 2 | # If ::create_path global variable is set, the project is created under that path instead of the working dir 3 | 4 | if {[info exists ::create_path]} { 5 | set dest_dir $::create_path 6 | } else { 7 | set dest_dir [pwd] 8 | } 9 | puts "INFO: Creating new project in $dest_dir" 10 | 11 | # Set the reference directory for source file relative paths (by default the value is script directory path) 12 | set proj_name "Music_Looper_Demo" 13 | 14 | # Set the reference directory for source file relative paths (by default the value is script directory path) 15 | set origin_dir ".." 16 | 17 | # Set the directory path for the original project from where this script was exported 18 | set orig_proj_dir "[file normalize "$origin_dir/proj"]" 19 | 20 | set src_dir $origin_dir/src 21 | set repo_dir $origin_dir/repo 22 | 23 | # Set the board part number 24 | set part_num "xc7a100tcsg324-1" 25 | 26 | # Create project 27 | create_project $proj_name $dest_dir 28 | 29 | # Set the directory path for the new project 30 | set proj_dir [get_property directory [current_project]] 31 | 32 | # Set project properties 33 | set obj [get_projects $proj_name] 34 | set_property "default_lib" "xil_defaultlib" $obj 35 | set_property "part" "$part_num" $obj 36 | set_property "simulator_language" "Mixed" $obj 37 | set_property "target_language" "VHDL" $obj 38 | 39 | # Create 'sources_1' fileset (if not found) 40 | if {[string equal [get_filesets -quiet sources_1] ""]} { 41 | create_fileset -srcset sources_1 42 | } 43 | 44 | # Create 'constrs_1' fileset (if not found) 45 | if {[string equal [get_filesets -quiet constrs_1] ""]} { 46 | create_fileset -constrset constrs_1 47 | } 48 | 49 | # Set IP repository paths 50 | set obj [get_filesets sources_1] 51 | set_property "ip_repo_paths" "[file normalize $repo_dir]" $obj 52 | 53 | # Add conventional sources 54 | add_files -quiet $src_dir/hdl 55 | 56 | # Add IPs 57 | add_files -quiet [glob -nocomplain ../src/ip/*/*.xci] 58 | add_files -quiet [glob -nocomplain ../src/ip/*/*.xco] 59 | 60 | # Add constraints 61 | add_files -fileset constrs_1 -quiet $src_dir/constraints 62 | 63 | # Refresh IP Repositories 64 | #update_ip_catalog 65 | 66 | # Create 'synth_1' run (if not found) 67 | if {[string equal [get_runs -quiet synth_1] ""]} { 68 | create_run -name synth_1 -part $part_num -flow {Vivado Synthesis 2014} -strategy "Flow_PerfOptimized_High" -constrset constrs_1 69 | } else { 70 | set_property strategy "Flow_PerfOptimized_High" [get_runs synth_1] 71 | set_property flow "Vivado Synthesis 2014" [get_runs synth_1] 72 | } 73 | set obj [get_runs synth_1] 74 | set_property "part" "$part_num" $obj 75 | set_property "steps.synth_design.args.fanout_limit" "400" $obj 76 | set_property "steps.synth_design.args.fsm_extraction" "one_hot" $obj 77 | set_property "steps.synth_design.args.keep_equivalent_registers" "1" $obj 78 | set_property "steps.synth_design.args.resource_sharing" "off" $obj 79 | set_property "steps.synth_design.args.no_lc" "1" $obj 80 | set_property "steps.synth_design.args.shreg_min_size" "5" $obj 81 | 82 | # set the current synth run 83 | current_run -synthesis [get_runs synth_1] 84 | 85 | # Create 'impl_1' run (if not found) 86 | if {[string equal [get_runs -quiet impl_1] ""]} { 87 | create_run -name impl_1 -part $part_num -flow {Vivado Implementation 2014} -strategy "Vivado Implementation Defaults" -constrset constrs_1 -parent_run synth_1 88 | } else { 89 | set_property strategy "Vivado Implementation Defaults" [get_runs impl_1] 90 | set_property flow "Vivado Implementation 2014" [get_runs impl_1] 91 | } 92 | set obj [get_runs impl_1] 93 | set_property "part" "$part_num" $obj 94 | set_property "steps.write_bitstream.args.bin_file" "1" $obj 95 | 96 | # set the current impl run 97 | current_run -implementation [get_runs impl_1] 98 | 99 | puts "INFO: Project created:$proj_name" 100 | 101 | # Comment the following section, if there is no block design 102 | # Create block design 103 | #source $origin_dir/src/bd/bt_gpio.tcl 104 | 105 | # Generate the wrapper 106 | #set design_name [get_bd_designs] 107 | #make_wrapper -files [get_files $design_name.bd] -top -import 108 | 109 | #set obj [get_filesets sources_1] 110 | #set_property "top" "bt_gpio_top" $obj 111 | 112 | #puts "INFO: Block design created: $design_name.bd" 113 | -------------------------------------------------------------------------------- /Projects/Music_Looper_Demo/src/hdl/AnalogXADC.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 04/07/2015 01:43:34 PM 7 | // Design Name: 8 | // Module Name: AnalogXADC 9 | // Project Name: 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | 23 | module AnalogXADC( 24 | output reg [15:0] aux_data, 25 | output reg [15:0] temp_data, 26 | input vauxp3, 27 | input vauxn3, 28 | input CLK100MHZ 29 | ); 30 | 31 | 32 | 33 | 34 | 35 | wire enable; 36 | wire ready; 37 | wire [15:0] data_o; 38 | reg [6:0] Address_in; 39 | 40 | initial Address_in = 7'h13; 41 | 42 | xadc_wiz_0 XLXI_7 (.daddr_in(Address_in), //addresses can be found in the artix 7 XADC user guide DRP register space 43 | .dclk_in(CLK100MHZ), 44 | .den_in(enable), 45 | .di_in(0), 46 | .dwe_in(0), 47 | .busy_out(), 48 | 49 | .vauxp3(vauxp3), 50 | .vauxn3(vauxn3), 51 | 52 | .vn_in(0), 53 | .vp_in(0), 54 | .alarm_out(), 55 | .do_out(data_o), 56 | .eoc_out(enable), 57 | .eos_out(), 58 | .channel_out(), 59 | .drdy_out(ready)); 60 | 61 | 62 | 63 | ////assigning different values out from xadc 64 | always @(posedge(CLK100MHZ)) 65 | begin 66 | if(ready == 1'b1) 67 | begin 68 | if(Address_in == 7'h13) //audio in 69 | begin 70 | aux_data <= {data_o[15:4],4'b0000}; 71 | Address_in <= 7'h00; //change to temp read 72 | end 73 | else //temperature in 74 | begin 75 | temp_data <= data_o; 76 | Address_in <= 7'h13; 77 | end 78 | end 79 | end 80 | 81 | 82 | 83 | endmodule 84 | -------------------------------------------------------------------------------- /Projects/Music_Looper_Demo/src/hdl/Binary_to_BCD_B_bcdout.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 18:33:23 06/15/2014 7 | // Design Name: 8 | // Module Name: bin_to_decimal 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module bin_to_decimal( 22 | 23 | input [11:0] B, 24 | output reg [15:0] decimals 25 | ); 26 | 27 | integer i; 28 | 29 | always @(B) 30 | begin 31 | decimals = 0; 32 | for(i = 11; i >= 0; i = i-1) 33 | begin 34 | if (decimals[15:12]>4)decimals[15:12]=decimals[15:12]+3; 35 | if (decimals[11:8]>4)decimals[11:8]=decimals[11:8]+3; 36 | if (decimals[7:4]>4)decimals[7:4]=decimals[7:4]+3; 37 | if (decimals[3:0]>4)decimals[3:0]=decimals[3:0]+3; 38 | 39 | decimals = {decimals[14:0], B[i]}; 40 | end 41 | end 42 | endmodule 43 | -------------------------------------------------------------------------------- /Projects/Music_Looper_Demo/src/hdl/DigitToSeg.v: -------------------------------------------------------------------------------- 1 | //////////////////////////////////////////////////////////////////////////////// 2 | // Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. 3 | //////////////////////////////////////////////////////////////////////////////// 4 | // ____ ____ 5 | // / /\/ / 6 | // /___/ \ / Vendor: Xilinx 7 | // \ \ \/ Version : 14.7 8 | // \ \ Application : sch2hdl 9 | // / / Filename : Top.vf 10 | // /___/ /\ Timestamp : 12/01/2014 17:59:05 11 | // \ \ / \ 12 | // \___\/\___\ 13 | // 14 | //Command: sch2hdl -intstyle ise -family spartan3e -verilog C:/Users/samue_000/Documents/FPGA/Projects/Stopwatch/sevensegdecoder/Top.vf -w C:/Users/samue_000/Documents/FPGA/Projects/Stopwatch/sevensegdecoder/Top.sch 15 | //Design Name: Top 16 | //Device: spartan3e 17 | //Purpose: 18 | // This verilog netlist is translated from an ECS schematic.It can be 19 | // synthesized and simulated, but it should not be modified. 20 | // 21 | `timescale 1ns / 1ps 22 | 23 | module DigitToSeg( 24 | input [11:0] timer, 25 | input [7:0] r, 26 | input [7:0] p, 27 | input [7:0] active, 28 | input [2:0] bank, 29 | input mclk, 30 | input rst, 31 | output [7:0] an, 32 | output dp, 33 | output [6:0]seg 34 | ); 35 | 36 | wire [15:0] BCD; 37 | wire [4:0] dig4; 38 | wire [4:0] dig5; 39 | wire [4:0] dig6; 40 | wire [4:0] dig7; 41 | // assign dig4 = (r[3]==1)? 5'h10 : (p[3]==1)? 5'h11: (active[3]==1) ? 5'h5: 5'h12; 42 | // assign dig5 = (r[2]==1)? 5'h10 : (p[2]==1)? 5'h11: (active[2]==1) ? 5'h5: 5'h12; 43 | // assign dig6 = (r[1]==1)? 5'h10 : (p[1]==1)? 5'h11: (active[1]==1) ? 5'h5: 5'h12; 44 | // assign dig7 = (r[0]==1)? 5'h10 : (p[0]==1)? 5'h11: (active[0]==1) ? 5'h5: 5'h12; 45 | 46 | 47 | assign dig4 = (r[bank]==1)? 5'h10 : (p[bank]==1)? 5'h11: (active[bank]==1) ? 5'h5: 5'h12; 48 | assign dig5 = 5'h13; 49 | assign dig6 = {2'b00, bank}; 50 | assign dig7 = 5'hB; 51 | 52 | wire segClk; 53 | wire [4:0] number; 54 | wire [2:0] select; 55 | 56 | bin_to_decimal bintodecimal ( 57 | .B(timer), 58 | .decimals(BCD) 59 | ); 60 | 61 | sevensegdecoder charSelect (.nIn(number[4:0]), 62 | .ssOut(seg[6:0])); 63 | mux4_4bus sevensegmux (.I0({1'b0,BCD[3:0]}), 64 | .I1({1'b0,BCD[7:4]}), 65 | .I2({1'b0,BCD[11:8]}), 66 | .I3({1'b0,BCD[15:12]}), 67 | .I4(dig4[4:0]), 68 | .I5(dig5[4:0]), 69 | .I6(dig6[4:0]), 70 | .I7(dig7[4:0]), 71 | .Sel(select[2:0]), 72 | .Y(number[4:0])); 73 | 74 | segClkDevider seg_clk_div (.clk(mclk), 75 | .rst(rst), 76 | .clk_div(segClk)); 77 | 78 | counter3bit counter (.clk(segClk), 79 | .rst(rst), 80 | .Q(select[2:0])); 81 | decoder_3_8 segdecoder (.I(select[2:0]), 82 | .dp(dp), 83 | .an(an[7:0])); 84 | 85 | 86 | endmodule 87 | -------------------------------------------------------------------------------- /Projects/Music_Looper_Demo/src/hdl/counter3bit.v: -------------------------------------------------------------------------------- 1 | module counter3bit ( 2 | input clk, 3 | input rst, 4 | output reg [2:0] Q 5 | ); 6 | 7 | always @ (posedge(clk)) // When will Always Block Be Triggered 8 | begin 9 | if (rst == 3'b111) 10 | // How Output reacts when Reset Is Asserted 11 | Q <= 3'b0; 12 | else 13 | // How Output reacts when Rising Edge of Clock Arrives? 14 | Q <= Q + 1'b1; 15 | end 16 | 17 | endmodule 18 | -------------------------------------------------------------------------------- /Projects/Music_Looper_Demo/src/hdl/debounce.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 05/13/2015 09:14:14 PM 7 | // Design Name: 8 | // Module Name: debounce 9 | // Project Name: 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | 23 | module debounce( 24 | input clock,//100MHz clock 25 | input reset, 26 | input [3:0] button,//Buttons to debounce 27 | output reg [3:0]out 28 | ); 29 | 30 | reg [12:0] cnt0=0, cnt1=0, cnt2=0, cnt3=0; 31 | reg [3:0] IV = 0; 32 | 33 | //parameter dbTime = 19; 34 | parameter dbTime = 4000; 35 | 36 | always @ (posedge(clock))begin 37 | if(reset==1)begin 38 | cnt0<=0; 39 | cnt1<=0; 40 | cnt2<=0; 41 | cnt3<=0; 42 | out<=0; 43 | end 44 | else begin 45 | if(button[0]==IV[0]) begin 46 | if (cnt0==dbTime) begin 47 | out[0]<=IV[0]; 48 | end 49 | else begin 50 | cnt0<=cnt0+1; 51 | end 52 | end 53 | else begin 54 | cnt0<=0; 55 | IV[0]<=button[0]; 56 | end 57 | if(button[1]==IV[1]) begin 58 | if (cnt1==dbTime) begin 59 | out[1]<=IV[1]; 60 | end 61 | else begin 62 | cnt1<=cnt1+1; 63 | end 64 | end 65 | else begin 66 | cnt1<=0; 67 | IV[1]<=button[1]; 68 | end 69 | if(button[2]==IV[2]) begin 70 | if (cnt2==dbTime) begin 71 | out[2]<=IV[2]; 72 | end 73 | else begin 74 | cnt2<=cnt2+1; 75 | end 76 | end 77 | else begin 78 | cnt2<=0; 79 | IV[2]<=button[2]; 80 | end 81 | if(button[3]==IV[3]) begin 82 | if (cnt3==dbTime) begin 83 | out[3]<=IV[3]; 84 | end 85 | else begin 86 | cnt3<=cnt3+1; 87 | end 88 | end 89 | else begin 90 | cnt3<=0; 91 | IV[3]<=button[3]; 92 | end 93 | end 94 | end 95 | endmodule -------------------------------------------------------------------------------- /Projects/Music_Looper_Demo/src/hdl/decoder3_8.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 00:48:27 09/09/2014 7 | // Design Name: 8 | // Module Name: decoder3_8 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module decoder_3_8 ( 22 | input [2:0] I, 23 | output [7:0] an, 24 | output dp 25 | ); 26 | 27 | assign an[0] = ~(~I[2] & ~I[1] & ~I[0]); 28 | assign an[1] = ~(~I[2] & ~I[1] & I[0]); 29 | 30 | assign an[2] = ~(~I[2] & I[1] & ~I[0]); 31 | assign an[3] = ~(~I[2] & I[1] & I[0]); 32 | 33 | assign an[4] = ~(I[2] & ~I[1] & ~I[0]); 34 | assign an[5] = ~(I[2] & ~I[1] & I[0]); 35 | assign an[6] = ~(I[2] & I[1] & ~I[0]); 36 | assign an[7] = ~(I[2] & I[1] & I[0]); 37 | 38 | //decimal place 39 | assign dp = ~(I[2] & I[1] & ~I[0]); 40 | 41 | endmodule 42 | -------------------------------------------------------------------------------- /Projects/Music_Looper_Demo/src/hdl/mux4_4bus.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 02:26:40 09/09/2014 7 | // Design Name: 8 | // Module Name: mux2_1bus 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module mux4_4bus( 22 | input [4:0] I0, 23 | input [4:0] I1, 24 | input [4:0] I2, 25 | input [4:0] I3, 26 | 27 | input [4:0] I4, 28 | input [4:0] I5, 29 | input [4:0] I6, 30 | input [4:0] I7, 31 | 32 | input [2:0] Sel, 33 | output [4:0] Y 34 | ); 35 | 36 | 37 | assign Y = ( Sel == 0 )? I0 : ( Sel == 1 )? I1 : ( Sel == 2 )? I2 : ( Sel == 3 )? I3 : ( Sel == 4 )? I4 :( Sel == 5 )? I5 :( Sel == 6 )? I6 : I7; 38 | 39 | endmodule 40 | -------------------------------------------------------------------------------- /Projects/Music_Looper_Demo/src/hdl/pwm_module.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 07:54:30 10/28/2014 7 | // Design Name: 8 | // Module Name: pwm_module 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module pwm_module( 22 | input clk, 23 | input [10:0] PWM_in, 24 | output reg PWM_out 25 | ); 26 | 27 | reg [10:0]new_pwm=0; 28 | reg [10:0] PWM_ramp=0; 29 | always @(posedge clk) 30 | begin 31 | if (PWM_ramp==0)new_pwm<=PWM_in; 32 | PWM_ramp <= PWM_ramp + 1'b1; 33 | PWM_out<=(new_pwm>PWM_ramp); 34 | end 35 | 36 | endmodule 37 | 38 | 39 | -------------------------------------------------------------------------------- /Projects/Music_Looper_Demo/src/hdl/segClkDevider.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 02:03:00 09/16/2014 7 | // Design Name: 8 | // Module Name: segClkDevider 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module segClkDevider( 22 | input clk, 23 | input rst, 24 | output reg clk_div 25 | ); 26 | 27 | localparam constantNumber = 10000; 28 | reg [31:0] count; 29 | 30 | always @ (posedge(clk), posedge(rst)) 31 | begin 32 | if (rst == 1'b1) 33 | count <= 32'b0; 34 | else if (count == constantNumber - 1) 35 | count <= 32'b0; 36 | else 37 | count <= count + 1; 38 | end 39 | 40 | always @ (posedge(clk), posedge(rst)) 41 | begin 42 | if (rst == 1'b1) 43 | clk_div <= 1'b0; 44 | else if (count == constantNumber - 1) 45 | clk_div <= ~clk_div; 46 | else 47 | clk_div <= clk_div; 48 | end 49 | endmodule -------------------------------------------------------------------------------- /Projects/Music_Looper_Demo/src/hdl/sevensegdecoder.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 01:55:33 09/09/2014 7 | // Design Name: 8 | // Module Name: sevensegdecoder 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module sevensegdecoder( 22 | 23 | input [4:0] nIn, 24 | output reg [6:0] ssOut 25 | ); 26 | 27 | always @(nIn) 28 | case (nIn) 29 | 5'h0: ssOut = 7'b1000000; 30 | 5'h1: ssOut = 7'b1111001; 31 | 5'h2: ssOut = 7'b0100100; 32 | 5'h3: ssOut = 7'b0110000; 33 | 5'h4: ssOut = 7'b0011001; 34 | 5'h5: ssOut = 7'b0010010; 35 | 5'h6: ssOut = 7'b0000010; 36 | 5'h7: ssOut = 7'b1111000; 37 | 5'h8: ssOut = 7'b0000000; 38 | 5'h9: ssOut = 7'b0011000; 39 | 5'hA: ssOut = 7'b0001000; 40 | 5'hB: ssOut = 7'b0000011; 41 | 5'hC: ssOut = 7'b1000110; 42 | 5'hD: ssOut = 7'b0100001; 43 | 5'hE: ssOut = 7'b0000110; 44 | 5'hF: ssOut = 7'b0001110; 45 | 5'h10: ssOut = 7'b0101111; 46 | 5'h11: ssOut = 7'b0001100; 47 | 5'h12: ssOut = 7'b0000110; 48 | 5'h13: ssOut = 7'b1111111; 49 | default: ssOut = 7'b1001001; 50 | endcase 51 | 52 | endmodule 53 | -------------------------------------------------------------------------------- /Projects/Music_Looper_Demo/src/ip/mig_7series_0/mig_7series_0/datasheet.txt: -------------------------------------------------------------------------------- 1 | 2 | 3 | Vivado Project Options: 4 | Target Device : xc7a100t-csg324 5 | Speed Grade : -1 6 | HDL : vhdl 7 | Synthesis Tool : VIVADO 8 | 9 | MIG Output Options: 10 | Module Name : mig_7series_0 11 | No of Controllers : 1 12 | Selected Compatible Device(s) : -- 13 | 14 | FPGA Options: 15 | System Clock Type : No Buffer 16 | Reference Clock Type : Use System Clock 17 | Debug Port : OFF 18 | Internal Vref : enabled 19 | IO Power Reduction : ON 20 | XADC instantiation in MIG : Disabled 21 | 22 | Extended FPGA Options: 23 | DCI for DQ,DQS/DQS#,DM : enabled 24 | Internal Termination (HR Banks) : 50 Ohms 25 | 26 | /*******************************************************/ 27 | /* Controller 0 */ 28 | /*******************************************************/ 29 | Controller Options : 30 | Memory : DDR2_SDRAM 31 | Interface : NATIVE 32 | Design Clock Frequency : 3333 ps ( 0.00 MHz) 33 | Phy to Controller Clock Ratio : 4:1 34 | Input Clock Period : 4999 ps 35 | CLKFBOUT_MULT (PLL) : 6 36 | DIVCLK_DIVIDE (PLL) : 1 37 | VCC_AUX IO : 1.8V 38 | Memory Type : Components 39 | Memory Part : MT47H64M16HR-25E 40 | Equivalent Part(s) : -- 41 | Data Width : 16 42 | ECC : Disabled 43 | Data Mask : enabled 44 | ORDERING : Strict 45 | 46 | AXI Parameters : 47 | Data Width : 128 48 | Arbitration Scheme : RD_PRI_REG 49 | Narrow Burst Support : 0 50 | ID Width : 4 51 | 52 | Memory Options: 53 | Burst Length (MR0[1:0]) : 8 54 | CAS Latency (MR0[6:4]) : 5 55 | Output Drive Strength (MR1[5,1]) : Fullstrength 56 | Controller CS option : Enable 57 | Rtt_NOM - ODT (MR1[9,6,2]) : 50ohms 58 | Memory Address Mapping : BANK_ROW_COLUMN 59 | 60 | 61 | Bank Selections: 62 | 63 | System_Control: 64 | SignalName: sys_rst 65 | PadLocation: No connect Bank: Select Bank 66 | SignalName: init_calib_complete 67 | PadLocation: No connect Bank: Select Bank 68 | SignalName: tg_compare_error 69 | PadLocation: No connect Bank: Select Bank 70 | 71 | 72 | 73 | 74 | -------------------------------------------------------------------------------- /Projects/Music_Looper_Demo/src/ip/mig_7series_0/mig_7series_0/docs/phy_only_support_readme.txt: -------------------------------------------------------------------------------- 1 | This file includes the information about the PHY layer support: 2 | 3 | - Folder "/user_design/rtl/phy" includes the PHY layer 4 | RTL modules. 5 | - The top-level PHY module to be instantiated is ddr_phy_top (ddr_phy_top.v) 6 | - PHY modules can be used in any environment by taking the RTL modules 7 | listed in "phy" folder and PHY layer needs to be connected to 8 | the memory controller. 9 | - Refer to User Guide (UG586) section "Physical Layer Interface (Non-Memory 10 | Controller Design)" for more details on PHY interface signaling, 11 | parameter(s) and timing information. 12 | -------------------------------------------------------------------------------- /Projects/Music_Looper_Demo/src/ip/mig_7series_0/mig_7series_0/example_design/log.txt: -------------------------------------------------------------------------------- 1 | Log file 2 | 3 | Generated by MIG MIG Version 2.3 4 | Coregen 14.7 - Build Number P_INT.20150421 on Sat Oct 17 13:33:25 2015 5 | 6 | 7 | Creating the directory 8 | c:/Users/Nate/Desktop/work/GitProject/Demos/DemoTest/Nexys4DDR/Projects/Music_Looper/src/ip/mig_7series_0/_tmp/mig_7series_0/example_design 9 | Created the SDC file - c:/Users/Nate/Desktop/work/GitProject/Demos/DemoTest/Nexys4DDR/Projects/Music_Looper/src/ip/mig_7series_0/_tmp/mig_7series_0/example_design/par/example_top.xdc Successfully 10 | Copied the Traffic Gen Files Successfully 11 | Created the file - c:/Users/Nate/Desktop/work/GitProject/Demos/DemoTest/Nexys4DDR/Projects/Music_Looper/src/ip/mig_7series_0/_tmp/mig_7series_0/example_design/../docs/phy_only_support_readme.txt Successfully 12 | ..Successful 13 | Created the file - c:/Users/Nate/Desktop/work/GitProject/Demos/DemoTest/Nexys4DDR/Projects/Music_Looper/src/ip/mig_7series_0/_tmp/mig_7series_0/example_design/par/readme.txt Successfully 14 | ..Successful 15 | Created the file - c:/Users/Nate/Desktop/work/GitProject/Demos/DemoTest/Nexys4DDR/Projects/Music_Looper/src/ip/mig_7series_0/_tmp/mig_7series_0/example_design/sim/ddr2_model.v Successfully 16 | ..Successful 17 | Created the file - c:/Users/Nate/Desktop/work/GitProject/Demos/DemoTest/Nexys4DDR/Projects/Music_Looper/src/ip/mig_7series_0/_tmp/mig_7series_0/example_design/sim/ddr2_model_parameters.vh Successfully 18 | ..Successful 19 | Created the file - c:/Users/Nate/Desktop/work/GitProject/Demos/DemoTest/Nexys4DDR/Projects/Music_Looper/src/ip/mig_7series_0/_tmp/mig_7series_0/example_design/sim/xsim_files.prj Successfully 20 | ..Successful 21 | Created the file - c:/Users/Nate/Desktop/work/GitProject/Demos/DemoTest/Nexys4DDR/Projects/Music_Looper/src/ip/mig_7series_0/_tmp/mig_7series_0/example_design/sim/xsim_options.tcl Successfully 22 | ..Successful 23 | Created the file - c:/Users/Nate/Desktop/work/GitProject/Demos/DemoTest/Nexys4DDR/Projects/Music_Looper/src/ip/mig_7series_0/_tmp/mig_7series_0/example_design/sim/xsim_run.bat Successfully 24 | ..Successful 25 | Created the file - c:/Users/Nate/Desktop/work/GitProject/Demos/DemoTest/Nexys4DDR/Projects/Music_Looper/src/ip/mig_7series_0/_tmp/mig_7series_0/example_design/sim/readme.txt Successfully 26 | ..Successful 27 | Created the file - c:/Users/Nate/Desktop/work/GitProject/Demos/DemoTest/Nexys4DDR/Projects/Music_Looper/src/ip/mig_7series_0/_tmp/mig_7series_0/example_design/sim/sim.do Successfully 28 | ..Successful 29 | Created the file - c:/Users/Nate/Desktop/work/GitProject/Demos/DemoTest/Nexys4DDR/Projects/Music_Looper/src/ip/mig_7series_0/_tmp/mig_7series_0/example_design/sim/sim_tb_top.v Successfully 30 | ..Successful 31 | Created the file - c:/Users/Nate/Desktop/work/GitProject/Demos/DemoTest/Nexys4DDR/Projects/Music_Looper/src/ip/mig_7series_0/_tmp/mig_7series_0/example_design/sim/ies_run.sh Successfully 32 | ..Successful 33 | Created the file - c:/Users/Nate/Desktop/work/GitProject/Demos/DemoTest/Nexys4DDR/Projects/Music_Looper/src/ip/mig_7series_0/_tmp/mig_7series_0/example_design/sim/vcs_run.sh Successfully 34 | ..Successful 35 | Created the file - c:/Users/Nate/Desktop/work/GitProject/Demos/DemoTest/Nexys4DDR/Projects/Music_Looper/src/ip/mig_7series_0/_tmp/mig_7series_0/example_design/sim/wiredly.v Successfully 36 | ..Successful 37 | Created the Top Level File - c:/Users/Nate/Desktop/work/GitProject/Demos/DemoTest/Nexys4DDR/Projects/Music_Looper/src/ip/mig_7series_0/_tmp/mig_7series_0/example_design/rtl/example_top_temp.vhd 38 | Created the Top Level File - c:/Users/Nate/Desktop/work/GitProject/Demos/DemoTest/Nexys4DDR/Projects/Music_Looper/src/ip/mig_7series_0/_tmp/mig_7series_0/example_design/sim/sim_tb_top.v 39 | The design output files are located in c:/Users/Nate/Desktop/work/GitProject/Demos/DemoTest/Nexys4DDR/Projects/Music_Looper/src/ip/mig_7series_0/_tmp/mig_7series_0/example_design/rtl and ..example_design/par for rtl & ucf files respectively. 40 | -------------------------------------------------------------------------------- /Projects/Music_Looper_Demo/src/ip/mig_7series_0/mig_7series_0/example_design/par/example_top.xdc: -------------------------------------------------------------------------------- 1 | ################################################################################################## 2 | ## 3 | ## Xilinx, Inc. 2010 www.xilinx.com 4 | ## Sat Oct 17 13:33:25 2015 5 | ## Generated by MIG Version 2.3 6 | ## 7 | ################################################################################################## 8 | ## File name : example_top.xdc 9 | ## Details : Constraints file 10 | ## FPGA Family: ARTIX7 11 | ## FPGA Part: XC7A100T-CSG324 12 | ## Speedgrade: -1 13 | ## Design Entry: VHDL 14 | ## Frequency: 0 MHz 15 | ## Time Period: 3333 ps 16 | ################################################################################################## 17 | 18 | ################################################################################################## 19 | ## Controller 0 20 | ## Memory Device: DDR2_SDRAM->Components->MT47H64M16HR-25E 21 | ## Data Width: 16 22 | ## Time Period: 3333 23 | ## Data Mask: 1 24 | ################################################################################################## 25 | ############## NET - IOSTANDARD ################## 26 | 27 | 28 | 29 | set_property INTERNAL_VREF 0.900 [get_iobanks 34] -------------------------------------------------------------------------------- /Projects/Music_Looper_Demo/src/ip/mig_7series_0/mig_7series_0/example_design/par/readme.txt: -------------------------------------------------------------------------------- 1 | Files in PAR folder : 2 | 3 | * "example_top.xdc" file is the constraint file for the design. This is used 4 | by Vivado. It has clock constraints, location constraints, IO standards 5 | and false path/SLICE constraints if any. 6 | 7 | * LTX/probe file is required when programming BIT file to FPGA as it contains 8 | the information of debug signals like signal name and position with respect 9 | to ILA/VIO core. The probe file (debug_nets.ltx) is auto generated by 10 | vivado tool and is found in .runs/impl_1/debug_nets.ltx 11 | 12 | 13 | compatible_ucf folder: 14 | 15 | * MIG outputs this folder only when Pin Compatible FPGAs are checked in GUI 16 | (Pin Compatible FPGAs page in GUI). It generates the XDC files for all 17 | the Compatible FPGAs selected in GUI. If you want to switch to any of the 18 | Compatible FPGAs follow the steps mentioned below. 19 | -------------------------------------------------------------------------------- /Projects/Music_Looper_Demo/src/ip/mig_7series_0/mig_7series_0/example_design/rtl/traffic_gen/mig_7series_v2_3_afifo.v: -------------------------------------------------------------------------------- 1 | //***************************************************************************** 2 | // (c) Copyright 2008-2010 Xilinx, Inc. All rights reserved. 3 | // 4 | // This file contains confidential and proprietary information 5 | // of Xilinx, Inc. and is protected under U.S. and 6 | // international copyright and other intellectual property 7 | // laws. 8 | // 9 | // DISCLAIMER 10 | // This disclaimer is not a license and does not grant any 11 | // rights to the materials distributed herewith. Except as 12 | // otherwise provided in a valid license issued to you by 13 | // Xilinx, and to the maximum extent permitted by applicable 14 | // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 15 | // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 16 | // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 17 | // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 18 | // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 19 | // (2) Xilinx shall not be liable (whether in contract or tort, 20 | // including negligence, or under any other theory of 21 | // liability) for any loss or damage of any kind or nature 22 | // related to, arising under or in connection with these 23 | // materials, including for any direct, or any indirect, 24 | // special, incidental, or consequential loss or damage 25 | // (including loss of data, profits, goodwill, or any type of 26 | // loss or damage suffered as a result of any action brought 27 | // by a third party) even if such damage or loss was 28 | // reasonably foreseeable or Xilinx had been advised of the 29 | // possibility of the same. 30 | // 31 | // CRITICAL APPLICATIONS 32 | // Xilinx products are not designed or intended to be fail- 33 | // safe, or for use in any application requiring fail-safe 34 | // performance, such as life-support or safety devices or 35 | // systems, Class III medical devices, nuclear facilities, 36 | // applications related to the deployment of airbags, or any 37 | // other applications that could lead to death, personal 38 | // injury, or severe property or environmental damage 39 | // (individually and collectively, "Critical 40 | // Applications"). Customer assumes the sole risk and 41 | // liability of any use of Xilinx products in Critical 42 | // Applications, subject only to applicable laws and 43 | // regulations governing limitations on product liability. 44 | // 45 | // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 46 | // PART OF THIS FILE AT ALL TIMES. 47 | // 48 | //***************************************************************************** 49 | // ____ ____ 50 | // / /\/ / 51 | // /___/ \ / Vendor: Xilinx 52 | // \ \ \/ Version: %version 53 | // \ \ Application: MIG 54 | // / / Filename: afifo.v 55 | // /___/ /\ Date Last Modified: $Date: 2011/06/02 08:37:18 $ 56 | // \ \ / \ Date Created: Oct 21 2008 57 | // \___\/\___\ 58 | // 59 | //Device: Spartan6 60 | //Design Name: DDR/DDR2/DDR3/LPDDR 61 | //Purpose: A generic synchronous fifo. 62 | //Reference: 63 | //Revision History: 1.2 11/8/2010 Removed unused signals. 64 | 65 | //***************************************************************************** 66 | 67 | `timescale 1ps/1ps 68 | 69 | module mig_7series_v2_3_afifo # 70 | ( 71 | parameter TCQ = 100, 72 | parameter DSIZE = 32, 73 | parameter FIFO_DEPTH = 16, 74 | parameter ASIZE = 4, 75 | parameter SYNC = 1 // only has always '1' logic. 76 | ) 77 | ( 78 | input wr_clk, 79 | input rst, 80 | input wr_en, 81 | input [DSIZE-1:0] wr_data, 82 | input rd_en, 83 | input rd_clk, 84 | output [DSIZE-1:0] rd_data, 85 | output reg full, 86 | output reg empty, 87 | output reg almost_full 88 | ); 89 | 90 | // memory array 91 | reg [DSIZE-1:0] mem [0:FIFO_DEPTH-1]; 92 | 93 | //Read Capture Logic 94 | // if Sync = 1, then no need to remove metastability logic because wrclk = rdclk 95 | reg [ASIZE:0] rd_capture_ptr; 96 | reg [ASIZE:0] pre_rd_capture_gray_ptr; 97 | reg [ASIZE:0] rd_capture_gray_ptr; 98 | 99 | reg [ASIZE:0] wr_capture_ptr; 100 | reg [ASIZE:0] pre_wr_capture_gray_ptr; 101 | reg [ASIZE:0] wr_capture_gray_ptr; 102 | wire [ASIZE:0] buf_avail; 103 | wire [ASIZE:0] buf_filled; 104 | wire [ASIZE-1:0] wr_addr, rd_addr; 105 | wire COutb,COutd; 106 | reg COuta,COutc; 107 | reg [ASIZE:0] wr_ptr, rd_ptr,rd_ptr_cp; 108 | integer i,j,k; 109 | 110 | 111 | always @ (rd_ptr) 112 | rd_capture_ptr = rd_ptr; 113 | 114 | 115 | 116 | //capture the wr_gray_pointers to rd_clk domains and convert the gray pointers to binary pointers 117 | // before do comparison. 118 | 119 | 120 | 121 | always @ (wr_ptr) 122 | wr_capture_ptr = wr_ptr; 123 | 124 | // dualport ram 125 | // Memory (RAM) that holds the contents of the FIFO 126 | 127 | 128 | assign wr_addr = wr_ptr[ASIZE-1:0]; 129 | assign rd_data = mem[rd_addr]; 130 | always @(posedge wr_clk) 131 | begin 132 | if (wr_en && !full) 133 | mem[wr_addr] <= #TCQ wr_data; 134 | 135 | end 136 | 137 | 138 | // Read Side Logic 139 | 140 | 141 | assign rd_addr = rd_ptr_cp[ASIZE-1:0]; 142 | assign rd_strobe = rd_en && !empty; 143 | 144 | integer n; 145 | // change the binary pointer to gray pointer 146 | 147 | 148 | always @(posedge rd_clk) 149 | begin 150 | if (rst) 151 | begin 152 | rd_ptr <= #TCQ 'b0; 153 | rd_ptr_cp <= #TCQ 'b0; 154 | 155 | end 156 | else begin 157 | if (rd_strobe) begin 158 | {COuta,rd_ptr} <= #TCQ rd_ptr + 1'b1; 159 | rd_ptr_cp <= #TCQ rd_ptr_cp + 1'b1; 160 | 161 | end 162 | 163 | // change the binary pointer to gray pointer 164 | end 165 | 166 | end 167 | 168 | //generate empty signal 169 | assign {COutb,buf_filled} = wr_capture_ptr - rd_ptr; 170 | 171 | always @ (posedge rd_clk ) 172 | begin 173 | if (rst) 174 | empty <= #TCQ 1'b1; 175 | else if ((buf_filled == 0) || (buf_filled == 1 && rd_strobe)) 176 | empty <= #TCQ 1'b1; 177 | else 178 | empty <= #TCQ 1'b0; 179 | end 180 | 181 | 182 | // write side logic; 183 | 184 | reg [ASIZE:0] wbin; 185 | wire [ASIZE:0] wgraynext, wbinnext; 186 | 187 | 188 | 189 | always @(posedge rd_clk) 190 | begin 191 | if (rst) 192 | begin 193 | wr_ptr <= #TCQ 'b0; 194 | end 195 | else begin 196 | if (wr_en) 197 | {COutc, wr_ptr} <= #TCQ wr_ptr + 1'b1; 198 | 199 | // change the binary pointer to gray pointer 200 | end 201 | 202 | end 203 | 204 | 205 | // calculate how many buf still available 206 | //assign {COutd,buf_avail }= (rd_capture_ptr + 5'd16) - wr_ptr; 207 | assign {COutd,buf_avail }= rd_capture_ptr - wr_ptr + + 5'd16; 208 | 209 | 210 | always @ (posedge wr_clk ) 211 | begin 212 | if (rst) 213 | full <= #TCQ 1'b0; 214 | else if ((buf_avail == 0) || (buf_avail == 1 && wr_en)) 215 | full <= #TCQ 1'b1; 216 | else 217 | full <= #TCQ 1'b0; 218 | end 219 | 220 | 221 | always @ (posedge wr_clk ) 222 | begin 223 | if (rst) 224 | almost_full <= #TCQ 1'b0; 225 | else if ((buf_avail == FIFO_DEPTH - 2 ) || ((buf_avail == FIFO_DEPTH -3) && wr_en)) 226 | almost_full <= #TCQ 1'b1; 227 | else 228 | almost_full <= #TCQ 1'b0; 229 | end 230 | 231 | endmodule 232 | -------------------------------------------------------------------------------- /Projects/Music_Looper_Demo/src/ip/mig_7series_0/mig_7series_0/example_design/rtl/traffic_gen/mig_7series_v2_3_data_prbs_gen.v: -------------------------------------------------------------------------------- 1 | //***************************************************************************** 2 | // (c) Copyright 2008-2010 Xilinx, Inc. All rights reserved. 3 | // 4 | // This file contains confidential and proprietary information 5 | // of Xilinx, Inc. and is protected under U.S. and 6 | // international copyright and other intellectual property 7 | // laws. 8 | // 9 | // DISCLAIMER 10 | // This disclaimer is not a license and does not grant any 11 | // rights to the materials distributed herewith. Except as 12 | // otherwise provided in a valid license issued to you by 13 | // Xilinx, and to the maximum extent permitted by applicable 14 | // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 15 | // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 16 | // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 17 | // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 18 | // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 19 | // (2) Xilinx shall not be liable (whether in contract or tort, 20 | // including negligence, or under any other theory of 21 | // liability) for any loss or damage of any kind or nature 22 | // related to, arising under or in connection with these 23 | // materials, including for any direct, or any indirect, 24 | // special, incidental, or consequential loss or damage 25 | // (including loss of data, profits, goodwill, or any type of 26 | // loss or damage suffered as a result of any action brought 27 | // by a third party) even if such damage or loss was 28 | // reasonably foreseeable or Xilinx had been advised of the 29 | // possibility of the same. 30 | // 31 | // CRITICAL APPLICATIONS 32 | // Xilinx products are not designed or intended to be fail- 33 | // safe, or for use in any application requiring fail-safe 34 | // performance, such as life-support or safety devices or 35 | // systems, Class III medical devices, nuclear facilities, 36 | // applications related to the deployment of airbags, or any 37 | // other applications that could lead to death, personal 38 | // injury, or severe property or environmental damage 39 | // (individually and collectively, "Critical 40 | // Applications"). Customer assumes the sole risk and 41 | // liability of any use of Xilinx products in Critical 42 | // Applications, subject only to applicable laws and 43 | // regulations governing limitations on product liability. 44 | // 45 | // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 46 | // PART OF THIS FILE AT ALL TIMES. 47 | // 48 | //***************************************************************************** 49 | // ____ ____ 50 | // / /\/ / 51 | // /___/ \ / Vendor: Xilinx 52 | // \ \ \/ Version: %version 53 | // \ \ Application: MIG 54 | // / / Filename: data_prbs_gen.v 55 | // /___/ /\ Date Last Modified: $Date: 2011/06/02 08:37:19 $ 56 | // \ \ / \ Date Created: Fri Sep 01 2006 57 | // \___\/\___\ 58 | // 59 | //Device: Spartan6 60 | //Design Name: DDR/DDR2/DDR3/LPDDR 61 | //Purpose: This module is used LFSR to generate random data for memory 62 | // data write or memory data read comparison.The first data is 63 | // seeded by the input prbs_seed_i which is connected to memory address. 64 | //Reference: 65 | //Revision History: 66 | //***************************************************************************** 67 | 68 | `timescale 1ps/1ps 69 | 70 | module mig_7series_v2_3_data_prbs_gen # 71 | ( 72 | parameter TCQ = 100, 73 | 74 | parameter EYE_TEST = "FALSE", 75 | parameter PRBS_WIDTH = 32, // "SEQUENTIAL_BUrst_i" 76 | parameter SEED_WIDTH = 32 77 | ) 78 | ( 79 | input clk_i, 80 | input clk_en, 81 | input rst_i, 82 | input prbs_seed_init, // when high the prbs_x_seed will be loaded 83 | input [PRBS_WIDTH - 1:0] prbs_seed_i, 84 | 85 | output [PRBS_WIDTH - 1:0] prbs_o // generated address 86 | ); 87 | 88 | reg [PRBS_WIDTH - 1 :0] prbs; 89 | reg [PRBS_WIDTH :1] lfsr_q; 90 | integer i; 91 | 92 | 93 | 94 | always @ (posedge clk_i) 95 | begin 96 | if (prbs_seed_init && EYE_TEST == "FALSE" || rst_i ) //reset it to a known good state to prevent it locks up 97 | // if (rst_i ) //reset it to a known good state to prevent it locks up 98 | 99 | begin 100 | lfsr_q[4:1] <= #TCQ prbs_seed_i[3:0] | 4'h5; 101 | // lfsr_q[PRBS_WIDTH-1:4] <= #TCQ prbs_seed_i[PRBS_WIDTH-1:4] ; 102 | 103 | lfsr_q[PRBS_WIDTH:5] <= #TCQ prbs_seed_i[PRBS_WIDTH-1:4] ; 104 | end 105 | else if (clk_en) begin 106 | 107 | lfsr_q[32:9] <= #TCQ lfsr_q[31:8]; 108 | lfsr_q[8] <= #TCQ lfsr_q[32] ^ lfsr_q[7]; 109 | lfsr_q[7] <= #TCQ lfsr_q[32] ^ lfsr_q[6]; 110 | lfsr_q[6:4] <= #TCQ lfsr_q[5:3]; 111 | 112 | lfsr_q[3] <= #TCQ lfsr_q[32] ^ lfsr_q[2]; 113 | lfsr_q[2] <= #TCQ lfsr_q[1] ; 114 | lfsr_q[1] <= #TCQ lfsr_q[32]; 115 | 116 | 117 | end 118 | end 119 | 120 | always @ (lfsr_q[PRBS_WIDTH:1]) begin 121 | prbs = lfsr_q[PRBS_WIDTH:1]; 122 | end 123 | 124 | assign prbs_o = prbs; 125 | 126 | endmodule 127 | 128 | 129 | -------------------------------------------------------------------------------- /Projects/Music_Looper_Demo/src/ip/mig_7series_0/mig_7series_0/example_design/rtl/traffic_gen/mig_7series_v2_3_tg_status.v: -------------------------------------------------------------------------------- 1 | //***************************************************************************** 2 | // (c) Copyright 2008-2010 Xilinx, Inc. All rights reserved. 3 | // 4 | // This file contains confidential and proprietary information 5 | // of Xilinx, Inc. and is protected under U.S. and 6 | // international copyright and other intellectual property 7 | // laws. 8 | // 9 | // DISCLAIMER 10 | // This disclaimer is not a license and does not grant any 11 | // rights to the materials distributed herewith. Except as 12 | // otherwise provided in a valid license issued to you by 13 | // Xilinx, and to the maximum extent permitted by applicable 14 | // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 15 | // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 16 | // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 17 | // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 18 | // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 19 | // (2) Xilinx shall not be liable (whether in contract or tort, 20 | // including negligence, or under any other theory of 21 | // liability) for any loss or damage of any kind or nature 22 | // related to, arising under or in connection with these 23 | // materials, including for any direct, or any indirect, 24 | // special, incidental, or consequential loss or damage 25 | // (including loss of data, profits, goodwill, or any type of 26 | // loss or damage suffered as a result of any action brought 27 | // by a third party) even if such damage or loss was 28 | // reasonably foreseeable or Xilinx had been advised of the 29 | // possibility of the same. 30 | // 31 | // CRITICAL APPLICATIONS 32 | // Xilinx products are not designed or intended to be fail- 33 | // safe, or for use in any application requiring fail-safe 34 | // performance, such as life-support or safety devices or 35 | // systems, Class III medical devices, nuclear facilities, 36 | // applications related to the deployment of airbags, or any 37 | // other applications that could lead to death, personal 38 | // injury, or severe property or environmental damage 39 | // (individually and collectively, "Critical 40 | // Applications"). Customer assumes the sole risk and 41 | // liability of any use of Xilinx products in Critical 42 | // Applications, subject only to applicable laws and 43 | // regulations governing limitations on product liability. 44 | // 45 | // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 46 | // PART OF THIS FILE AT ALL TIMES. 47 | // 48 | //***************************************************************************** 49 | // ____ ____ 50 | // / /\/ / 51 | // /___/ \ / Vendor: Xilinx 52 | // \ \ \/ Version: %version 53 | // \ \ Application: MIG 54 | // / / Filename: tg_status.v 55 | // /___/ /\ Date Last Modified: 56 | // \ \ / \ Date Created: 57 | // \___\/\___\ 58 | // 59 | //Device: Spartan6 60 | //Design Name: DDR/DDR2/DDR3/LPDDR 61 | //Purpose: This module compare the memory read data agaisnt compare data that generated from data_gen module. 62 | // Error signal will be asserted if the comparsion is not equal. 63 | //Reference: 64 | //Revision History: 65 | //***************************************************************************** 66 | 67 | `timescale 1ps/1ps 68 | 69 | 70 | module mig_7series_v2_3_tg_status #( 71 | parameter TCQ = 100, 72 | 73 | parameter DWIDTH = 32 74 | ) 75 | ( 76 | 77 | 78 | input clk_i , 79 | input rst_i , 80 | input manual_clear_error, 81 | input data_error_i , 82 | input [DWIDTH-1:0] cmp_data_i, 83 | input [DWIDTH-1:0] rd_data_i , 84 | input [31:0] cmp_addr_i , 85 | input [5:0] cmp_bl_i , 86 | input mcb_cmd_full_i , 87 | input mcb_wr_full_i, 88 | input mcb_rd_empty_i, 89 | output reg [64 + (2*DWIDTH - 1):0] error_status, 90 | output error 91 | ); 92 | 93 | reg data_error_r; 94 | reg error_set; 95 | assign error = error_set; 96 | 97 | always @ (posedge clk_i) 98 | data_error_r <= #TCQ data_error_i; 99 | 100 | always @ (posedge clk_i) 101 | begin 102 | 103 | if (rst_i || manual_clear_error) begin 104 | error_status <= #TCQ 'b0; 105 | error_set <= #TCQ 1'b0; 106 | end 107 | else begin 108 | // latch the first error only 109 | if (data_error_i && ~data_error_r && ~error_set ) begin 110 | error_status[31:0] <= #TCQ cmp_addr_i; 111 | error_status[37:32] <= #TCQ cmp_bl_i; 112 | error_status[40] <= #TCQ mcb_cmd_full_i; 113 | error_status[41] <= #TCQ mcb_wr_full_i; 114 | error_status[42] <= #TCQ mcb_rd_empty_i; 115 | error_set <= #TCQ 1'b1; 116 | error_status[64 + (DWIDTH - 1) :64] <= #TCQ cmp_data_i; 117 | error_status[64 + (2*DWIDTH - 1):64 + DWIDTH] <= #TCQ rd_data_i; 118 | 119 | end 120 | 121 | error_status[39:38] <= #TCQ 'b0; // reserved 122 | error_status[63:43] <= #TCQ 'b0; // reserved 123 | 124 | 125 | end end 126 | 127 | endmodule 128 | -------------------------------------------------------------------------------- /Projects/Music_Looper_Demo/src/ip/mig_7series_0/mig_7series_0/example_design/sim/ies_run.sh: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Digilent/Nexys4DDR/bb66971474b74a0c55381625db3cfdceb3f21d78/Projects/Music_Looper_Demo/src/ip/mig_7series_0/mig_7series_0/example_design/sim/ies_run.sh -------------------------------------------------------------------------------- /Projects/Music_Looper_Demo/src/ip/mig_7series_0/mig_7series_0/example_design/sim/sim.do: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Digilent/Nexys4DDR/bb66971474b74a0c55381625db3cfdceb3f21d78/Projects/Music_Looper_Demo/src/ip/mig_7series_0/mig_7series_0/example_design/sim/sim.do -------------------------------------------------------------------------------- /Projects/Music_Looper_Demo/src/ip/mig_7series_0/mig_7series_0/example_design/sim/vcs_run.sh: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Digilent/Nexys4DDR/bb66971474b74a0c55381625db3cfdceb3f21d78/Projects/Music_Looper_Demo/src/ip/mig_7series_0/mig_7series_0/example_design/sim/vcs_run.sh -------------------------------------------------------------------------------- /Projects/Music_Looper_Demo/src/ip/mig_7series_0/mig_7series_0/example_design/sim/wiredly.v: -------------------------------------------------------------------------------- 1 | //***************************************************************************** 2 | // (c) Copyright 2009 - 2011 Xilinx, Inc. All rights reserved. 3 | // 4 | // This file contains confidential and proprietary information 5 | // of Xilinx, Inc. and is protected under U.S. and 6 | // international copyright and other intellectual property 7 | // laws. 8 | // 9 | // DISCLAIMER 10 | // This disclaimer is not a license and does not grant any 11 | // rights to the materials distributed herewith. Except as 12 | // otherwise provided in a valid license issued to you by 13 | // Xilinx, and to the maximum extent permitted by applicable 14 | // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 15 | // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 16 | // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 17 | // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 18 | // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 19 | // (2) Xilinx shall not be liable (whether in contract or tort, 20 | // including negligence, or under any other theory of 21 | // liability) for any loss or damage of any kind or nature 22 | // related to, arising under or in connection with these 23 | // materials, including for any direct, or any indirect, 24 | // special, incidental, or consequential loss or damage 25 | // (including loss of data, profits, goodwill, or any type of 26 | // loss or damage suffered as a result of any action brought 27 | // by a third party) even if such damage or loss was 28 | // reasonably foreseeable or Xilinx had been advised of the 29 | // possibility of the same. 30 | // 31 | // CRITICAL APPLICATIONS 32 | // Xilinx products are not designed or intended to be fail- 33 | // safe, or for use in any application requiring fail-safe 34 | // performance, such as life-support or safety devices or 35 | // systems, Class III medical devices, nuclear facilities, 36 | // applications related to the deployment of airbags, or any 37 | // other applications that could lead to death, personal 38 | // injury, or severe property or environmental damage 39 | // (individually and collectively, "Critical 40 | // Applications"). Customer assumes the sole risk and 41 | // liability of any use of Xilinx products in Critical 42 | // Applications, subject only to applicable laws and 43 | // regulations governing limitations on product liability. 44 | // 45 | // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 46 | // PART OF THIS FILE AT ALL TIMES. 47 | // 48 | //***************************************************************************** 49 | // ____ ____ 50 | // / /\/ / 51 | // /___/ \ / Vendor : Xilinx 52 | // \ \ \/ Version : 2.3 53 | // \ \ Application : MIG 54 | // / / Filename : wiredly.v 55 | // /___/ /\ Date Last Modified : $Date: 2011/06/23 08:25:20 $ 56 | // \ \ / \ Date Created : Fri Oct 14 2011 57 | // \___\/\___\ 58 | // 59 | // Device : 7Series 60 | // Design Name : DDR2 SDRAM 61 | // Purpose : 62 | // This module provide the definition of a zero ohm component (A, B). 63 | // 64 | // The applications of this component include: 65 | // . Normal operation of a jumper wire (data flowing in both directions) 66 | // This can corrupt data from DRAM to FPGA useful for verifying ECC function. 67 | // 68 | // The component consists of 2 ports: 69 | // . Port A: One side of the pass-through switch 70 | // . Port B: The other side of the pass-through switch 71 | 72 | // The model is sensitive to transactions on all ports. Once a transaction 73 | // is detected, all other transactions are ignored for that simulation time 74 | // (i.e. further transactions in that delta time are ignored). 75 | 76 | // Model Limitations and Restrictions: 77 | // Signals asserted on the ports of the error injector should not have 78 | // transactions occuring in multiple delta times because the model 79 | // is sensitive to transactions on port A, B ONLY ONCE during 80 | // a simulation time. Thus, once fired, a process will 81 | // not refire if there are multiple transactions occuring in delta times. 82 | // This condition may occur in gate level simulations with 83 | // ZERO delays because transactions may occur in multiple delta times. 84 | // 85 | // Reference : 86 | // Revision History : 87 | //***************************************************************************** 88 | 89 | `timescale 1ns / 1ps 90 | 91 | module WireDelay # ( 92 | parameter Delay_g = 0, 93 | parameter Delay_rd = 0, 94 | parameter ERR_INSERT = "OFF" 95 | ) 96 | ( 97 | inout A, 98 | inout B, 99 | input reset, 100 | input phy_init_done 101 | ); 102 | 103 | reg A_r; 104 | reg B_r; 105 | reg B_inv ; 106 | reg line_en; 107 | 108 | reg B_nonX; 109 | 110 | assign A = A_r; 111 | assign B = B_r; 112 | 113 | always @ (*) 114 | begin 115 | if (B === 1'bx) 116 | B_nonX <= $random; 117 | else 118 | B_nonX <= B; 119 | end 120 | 121 | always@(*) 122 | begin 123 | if((B_nonX == 'b1) || (B_nonX == 'b0)) 124 | B_inv <= #0 ~B_nonX ; 125 | else 126 | B_inv <= #0 'bz ; 127 | end 128 | 129 | always @(*) begin 130 | if (!reset) begin 131 | A_r <= 1'bz; 132 | B_r <= 1'bz; 133 | line_en <= 1'b0; 134 | end else begin 135 | if (line_en) begin 136 | B_r <= 1'bz; 137 | if ((ERR_INSERT == "ON") & (phy_init_done)) 138 | A_r <= #Delay_rd B_inv; 139 | else 140 | A_r <= #Delay_rd B_nonX; 141 | end else begin 142 | B_r <= #Delay_g A; 143 | A_r <= 1'bz; 144 | end 145 | end 146 | end 147 | 148 | always @(A or B) begin 149 | if (!reset) begin 150 | line_en <= 1'b0; 151 | end else if (A !== A_r) begin 152 | line_en <= 1'b0; 153 | end else if (B_r !== B) begin 154 | line_en <= 1'b1; 155 | end else begin 156 | line_en <= line_en; 157 | end 158 | end 159 | endmodule 160 | -------------------------------------------------------------------------------- /Projects/Music_Looper_Demo/src/ip/mig_7series_0/mig_7series_0/example_design/sim/xsim_options.tcl: -------------------------------------------------------------------------------- 1 | ############################################################################### 2 | ## (c) Copyright 2012 Xilinx, Inc. All rights reserved. 3 | ## 4 | ## This file contains confidential and proprietary information 5 | ## of Xilinx, Inc. and is protected under U.S. and 6 | ## international copyright and other intellectual property 7 | ## laws. 8 | ## 9 | ## DISCLAIMER 10 | ## This disclaimer is not a license and does not grant any 11 | ## rights to the materials distributed herewith. Except as 12 | ## otherwise provided in a valid license issued to you by 13 | ## Xilinx, and to the maximum extent permitted by applicable 14 | ## law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 15 | ## WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 16 | ## AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 17 | ## BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 18 | ## INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 19 | ## (2) Xilinx shall not be liable (whether in contract or tort, 20 | ## including negligence, or under any other theory of 21 | ## liability) for any loss or damage of any kind or nature 22 | ## related to, arising under or in connection with these 23 | ## materials, including for any direct, or any indirect, 24 | ## special, incidental, or consequential loss or damage 25 | ## (including loss of data, profits, goodwill, or any type of 26 | ## loss or damage suffered as a result of any action brought 27 | ## by a third party) even if such damage or loss was 28 | ## reasonably foreseeable or Xilinx had been advised of the 29 | ## possibility of the same. 30 | ## 31 | ## CRITICAL APPLICATIONS 32 | ## Xilinx products are not designed or intended to be fail- 33 | ## safe, or for use in any application requiring fail-safe 34 | ## performance, such as life-support or safety devices or 35 | ## systems, Class III medical devices, nuclear facilities, 36 | ## applications related to the deployment of airbags, or any 37 | ## other applications that could lead to death, personal 38 | ## injury, or severe property or environmental damage 39 | ## (individually and collectively, "Critical 40 | ## Applications"). Customer assumes the sole risk and 41 | ## liability of any use of Xilinx products in Critical 42 | ## Applications, subject only to applicable laws and 43 | ## regulations governing limitations on product liability. 44 | ## 45 | ## THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 46 | ## PART OF THIS FILE AT ALL TIMES. 47 | ## 48 | ############################################################################### 49 | ## ____ ____ 50 | ## / /\/ / 51 | ## /___/ \ / Vendor : Xilinx 52 | ## \ \ \/ Version : 2.3 53 | ## \ \ Application : MIG 54 | ## / / Filename : xsim_options.tcl 55 | ## /___/ /\ Date Last Modified : $Date: 2011/06/02 08:31:16 $ 56 | ## \ \ / \ Date Created : Tue Jun 05 2012 57 | ## \___\/\___\ 58 | ## 59 | ## Device : 7 Series 60 | ## Design Name : DDR2 SDRAM 61 | ## Purpose : To give commands to XSIM Simulator through batch mode 62 | ## Assumptions: 63 | ## - Simulation takes place in \sim folder of MIG output directory 64 | ## Reference : 65 | ## Revision History: 66 | ############################################################################### 67 | 68 | 69 | add_wave -radix hex /sim_tb_top 70 | run 1000 us 71 | -------------------------------------------------------------------------------- /Projects/Music_Looper_Demo/src/ip/mig_7series_0/mig_7series_0/example_design/sim/xsim_run.bat: -------------------------------------------------------------------------------- 1 | ::!/bin/csh -f 2 | ::***************************************************************************** 3 | :: (c) Copyright 2012 Xilinx, Inc. All rights reserved. 4 | :: 5 | :: This file contains confidential and proprietary information 6 | :: of Xilinx, Inc. and is protected under U.S. and 7 | :: international copyright and other intellectual property 8 | :: laws. 9 | :: 10 | :: DISCLAIMER 11 | :: This disclaimer is not a license and does not grant any 12 | :: rights to the materials distributed herewith. Except as 13 | :: otherwise provided in a valid license issued to you by 14 | :: Xilinx, and to the maximum extent permitted by applicable 15 | :: law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 16 | :: WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 17 | :: AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 18 | :: BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 19 | :: INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 20 | :: (2) Xilinx shall not be liable (whether in contract or tort, 21 | :: including negligence, or under any other theory of 22 | :: liability) for any loss or damage of any kind or nature 23 | :: related to, arising under or in connection with these 24 | :: materials, including for any direct, or any indirect, 25 | :: special, incidental, or consequential loss or damage 26 | :: (including loss of data, profits, goodwill, or any type of 27 | :: loss or damage suffered as a result of any action brought 28 | :: by a third party) even if such damage or loss was 29 | :: reasonably foreseeable or Xilinx had been advised of the 30 | :: possibility of the same. 31 | :: 32 | :: CRITICAL APPLICATIONS 33 | :: Xilinx products are not designed or intended to be fail- 34 | :: safe, or for use in any application requiring fail-safe 35 | :: performance, such as life-support or safety devices or 36 | :: systems, Class III medical devices, nuclear facilities, 37 | :: applications related to the deployment of airbags, or any 38 | :: other applications that could lead to death, personal 39 | :: injury, or severe property or environmental damage 40 | :: (individually and collectively, "Critical 41 | :: Applications"). Customer assumes the sole risk and 42 | :: liability of any use of Xilinx products in Critical 43 | :: Applications, subject only to applicable laws and 44 | :: regulations governing limitations on product liability. 45 | :: 46 | :: THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 47 | :: PART OF THIS FILE AT ALL TIMES. 48 | :: 49 | :: **************************************************************************** 50 | :: ____ ____ 51 | :: / /\/ / 52 | :: /___/ \ / Vendor : Xilinx 53 | :: \ \ \/ Version : 2.3 54 | :: \ \ Application : MIG 55 | :: / / Filename : xsim_run.bat 56 | :: /___/ /\ Date Last Modified : $Date: 2011/06/02 08:31:16 $ 57 | :: \ \ / \ Date Created : Tue Jun 05 2012 58 | :: \___\/\___\ 59 | :: 60 | :: Device : 7 Series 61 | :: Design Name : DDR2 SDRAM 62 | :: Purpose : Batch file to run Simulation through Vivado Simulator 63 | :: Reference : 64 | :: Revision History : 65 | :: **************************************************************************** 66 | 67 | 68 | echo Simulation Tool: Viavdo Simulator 69 | call xelab work.sim_tb_top work.glbl -prj xsim_files.prj -L unisims_ver -L secureip -s xsim_test -debug typical 70 | xsim -g -t xsim_options.tcl -wdb xsim_database.wdb xsim_test 71 | echo done 72 | -------------------------------------------------------------------------------- /Projects/Music_Looper_Demo/src/ip/mig_7series_0/xil_txt.in: -------------------------------------------------------------------------------- 1 | SET_FLAG MODE BATCH 2 | SET_FLAG STANDALONE_MODE TRUE 3 | SET_PREFERENCE ipi_mode no 4 | SET_PREFERENCE is_ip_locked false 5 | SET_PREFERENCE devicefamily artix7 6 | SET_PREFERENCE device xc7a100t 7 | SET_PREFERENCE speedgrade -1 8 | SET_PREFERENCE package csg324 9 | SET_PREFERENCE verilogsim false 10 | SET_PREFERENCE vhdlsim true 11 | SET_PREFERENCE designentry VHDL 12 | SET_PREFERENCE outputdirectory c:/Users/Nate/Desktop/work/GitProject/Demos/DemoTest/Nexys4DDR/Projects/Music_Looper/src/ip/mig_7series_0/_tmp/ 13 | SET_PREFERENCE subworkingdirectory c:/Users/Nate/Desktop/work/GitProject/Demos/DemoTest/Nexys4DDR/Projects/Music_Looper/src/ip/mig_7series_0/_tmp/ 14 | SET_PREFERENCE flowvendor Other 15 | SET_PREFERENCE tool vivado 16 | SET_PREFERENCE compnamestatus 0 17 | SET_PARAMETER component_name mig_7series_0 18 | SET_PARAMETER xml_input_file C:/Users/Nate/Desktop/work/GitProject/Demos/DemoTest/Nexys4DDR/Projects/Music_Looper/src/ip/mig_7series_0/mig_b.prj 19 | SET_PARAMETER data_dir_path c:/Xilinx/Vivado/2015.1/data/ip/xilinx/mig_7series_v2_3 20 | SET_CORE_NAME Memory Interface Generator (MIG 7 Series) 21 | SET_CORE_VERSION 2.3 22 | SET_CORE_VLNV xilinx.com:ip:mig_7series:2.3 23 | SET_CORE_PATH c:/Xilinx/Vivado/2015.1/data/ip/xilinx/mig_7series_v2_3 24 | SET_CORE_DATASHEET c:/Xilinx/Vivado/2015.1/data/ip/xilinx/mig_7series_v2_3/data/docs/ds176_7series_MIS.pdf 25 | -------------------------------------------------------------------------------- /Projects/Music_Looper_Demo/src/ip/mig_7series_0/xil_txt.out: -------------------------------------------------------------------------------- 1 | SET_ERROR_CODE 0 2 | SET_XMDF_PATH ./mig_7series_0_xmdf.tcl 3 | SET_PARAMETER component_name mig_7series_0 4 | SET_PARAMETER xml_input_file ./mig_7series_0/mig.prj 5 | -------------------------------------------------------------------------------- /Projects/User_Demo/proj/_READ_ME_.txt: -------------------------------------------------------------------------------- 1 | In order to run the create_project script successfully, the folder must be in its initial state 2 | containing only the cleanup, create_project scripts, and this document. 3 | 4 | To restore the folder to its initial state, double-click the cleanup Windows Command Script. 5 | 6 | !!!!CAUTION!!!! 7 | 8 | Moving or copying the cleanup Windows Command Script can result in unintentional loss of data on your 9 | system. The script contains a short list of specific files to ignore once it is run, all other files 10 | and folders within its directory location will be ERASED. Use this only within the project folder as 11 | instructed. 12 | 13 | See material on the usage of demo projects at reference.digilentinc.com -------------------------------------------------------------------------------- /Projects/User_Demo/proj/cleanup.cmd: -------------------------------------------------------------------------------- 1 | @echo off 2 | rem delete all files from subfolders 3 | for /d /r %%i in (*) do del /f /q %%i\* 4 | rem delete all subfolders 5 | for /d %%i in (*) do rd /S /Q %%i 6 | 7 | rem unmark read only from all files 8 | attrib -R .\* /S 9 | 10 | rem mark read only those we wish to keep 11 | attrib +R .\create_project.tcl 12 | attrib +R .\cleanup.sh 13 | attrib +R .\cleanup.cmd 14 | attrib +R .\.gitignore 15 | attrib +R .\_READ_ME_.txt 16 | 17 | rem delete all non read-only 18 | del /Q /A:-R .\* 19 | 20 | rem unmark read-only 21 | attrib -R .\* 22 | -------------------------------------------------------------------------------- /Projects/User_Demo/proj/cleanup.sh: -------------------------------------------------------------------------------- 1 | # This script is useful for cleaning up the 'project' 2 | # directory of a Digilent Vivado-project git repository 3 | ### 4 | # Run the following command to change permissions of 5 | # this 'cleanup' file if needed: 6 | # chmod u+x cleanup.sh 7 | ### 8 | # Remove directories/subdirectories 9 | find . -mindepth 1 -type d -exec rm -rf {} + 10 | # Remove any other files than: 11 | find . -type f ! -name 'cleanup.sh' \ 12 | ! -name 'cleanup.cmd' \ 13 | ! -name 'create_project.tcl' \ 14 | ! -name '.gitignore' \ 15 | -exec rm -rf {} + 16 | -------------------------------------------------------------------------------- /Projects/User_Demo/proj/create_project.tcl: -------------------------------------------------------------------------------- 1 | # Run this script to create the Vivado project files NEXT TO THIS script 2 | # If ::create_path global variable is set, the project is created under that path instead of the working dir 3 | 4 | if {[info exists ::create_path]} { 5 | set dest_dir $::create_path 6 | } else { 7 | set dest_dir [file normalize [file dirname [info script]]] 8 | } 9 | puts "INFO: Creating new project in $dest_dir" 10 | cd $dest_dir 11 | 12 | # Set the reference directory for source file relative paths (by default the value is script directory path) 13 | set proj_name "User_Demo" 14 | 15 | # Set the reference directory for source file relative paths (by default the value is script directory path) 16 | set origin_dir ".." 17 | 18 | # Set the directory path for the original project from where this script was exported 19 | set orig_proj_dir "[file normalize "$origin_dir/proj"]" 20 | 21 | set src_dir $origin_dir/src 22 | set repo_dir $origin_dir/repo 23 | 24 | # Set the board part number 25 | set part_num "xc7a100tcsg324-1" 26 | 27 | # Create project 28 | create_project $proj_name $dest_dir 29 | 30 | # Set the directory path for the new project 31 | set proj_dir [get_property directory [current_project]] 32 | 33 | # Set project properties 34 | set obj [get_projects $proj_name] 35 | set_property "default_lib" "xil_defaultlib" $obj 36 | set_property "part" "$part_num" $obj 37 | set_property "simulator_language" "Mixed" $obj 38 | set_property "target_language" "VHDL" $obj 39 | 40 | # Create 'sources_1' fileset (if not found) 41 | if {[string equal [get_filesets -quiet sources_1] ""]} { 42 | create_fileset -srcset sources_1 43 | } 44 | 45 | # Create 'constrs_1' fileset (if not found) 46 | if {[string equal [get_filesets -quiet constrs_1] ""]} { 47 | create_fileset -constrset constrs_1 48 | } 49 | 50 | # Set IP repository paths 51 | set obj [get_filesets sources_1] 52 | set_property "ip_repo_paths" "[file normalize $repo_dir]" $obj 53 | 54 | # Add conventional sources 55 | add_files -quiet $src_dir/hdl 56 | 57 | # Add IPs 58 | add_files -quiet [glob -nocomplain ../src/ip/*/*.xci] 59 | 60 | # Add constraints 61 | add_files -fileset constrs_1 -quiet $src_dir/constraints 62 | 63 | # Refresh IP Repositories 64 | #update_ip_catalog 65 | 66 | # Create 'synth_1' run (if not found) 67 | if {[string equal [get_runs -quiet synth_1] ""]} { 68 | create_run -name synth_1 -part $part_num -flow {Vivado Synthesis 2014} -strategy "Flow_PerfOptimized_High" -constrset constrs_1 69 | } else { 70 | set_property strategy "Flow_PerfOptimized_High" [get_runs synth_1] 71 | set_property flow "Vivado Synthesis 2014" [get_runs synth_1] 72 | } 73 | set obj [get_runs synth_1] 74 | set_property "part" "$part_num" $obj 75 | set_property "steps.synth_design.args.fanout_limit" "400" $obj 76 | set_property "steps.synth_design.args.fsm_extraction" "one_hot" $obj 77 | set_property "steps.synth_design.args.keep_equivalent_registers" "1" $obj 78 | set_property "steps.synth_design.args.resource_sharing" "off" $obj 79 | set_property "steps.synth_design.args.no_lc" "1" $obj 80 | set_property "steps.synth_design.args.shreg_min_size" "5" $obj 81 | 82 | # set the current synth run 83 | current_run -synthesis [get_runs synth_1] 84 | 85 | # Create 'impl_1' run (if not found) 86 | if {[string equal [get_runs -quiet impl_1] ""]} { 87 | create_run -name impl_1 -part $part_num -flow {Vivado Implementation 2014} -strategy "Vivado Implementation Defaults" -constrset constrs_1 -parent_run synth_1 88 | } else { 89 | set_property strategy "Vivado Implementation Defaults" [get_runs impl_1] 90 | set_property flow "Vivado Implementation 2014" [get_runs impl_1] 91 | } 92 | set obj [get_runs impl_1] 93 | set_property "part" "$part_num" $obj 94 | set_property "steps.write_bitstream.args.bin_file" "1" $obj 95 | 96 | # set the current impl run 97 | current_run -implementation [get_runs impl_1] 98 | 99 | #puts "INFO: Project created:$proj_name" 100 | 101 | # Comment the following section, if there is no block design 102 | # Create block design 103 | #source $origin_dir/src/bd/bt_gpio.tcl 104 | 105 | # Generate the wrapper 106 | #set design_name [get_bd_designs] 107 | #make_wrapper -files [get_files $design_name.bd] -top -import 108 | 109 | #set obj [get_filesets sources_1] 110 | #set_property "top" "bt_gpio_top" $obj 111 | 112 | #puts "INFO: Block design created: $design_name.bd" 113 | -------------------------------------------------------------------------------- /Projects/User_Demo/src/hdl/Dbncr.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------------------------- 2 | ---------------------------------------------------------------------------- 3 | -- Author: Mihaita Nagy 4 | -- Copyright 2014 Digilent, Inc. 5 | ---------------------------------------------------------------------------- 6 | -- 7 | -- Create Date: 17:11:29 03/06/2013 8 | -- Design Name: 9 | -- Module Name: dbncr - Behavioral 10 | -- Project Name: 11 | -- Target Devices: 12 | -- Tool versions: 13 | -- Description: 14 | -- This module represents a debouncer and is used to synchronize with the system clock 15 | -- and remove glitches from the incoming button signals 16 | -- 17 | -- 18 | -- Revision: 19 | -- Revision 0.01 - File Created 20 | -- Additional Comments: 21 | -- 22 | ---------------------------------------------------------------------------------- 23 | library IEEE; 24 | use IEEE.STD_LOGIC_1164.ALL; 25 | 26 | -- Uncomment the following library declaration if using 27 | -- arithmetic functions with Signed or Unsigned values 28 | --use IEEE.NUMERIC_STD.ALL; 29 | 30 | -- Uncomment the following library declaration if instantiating 31 | -- any Xilinx primitives in this code. 32 | --library UNISIM; 33 | --use UNISIM.VComponents.all; 34 | 35 | entity Dbncr is 36 | generic( 37 | NR_OF_CLKS : integer := 4095 -- Number of System Clock periods while the incoming signal 38 | ); -- has to be stable until a one-shot output signal is generated 39 | port( 40 | clk_i : in std_logic; 41 | sig_i : in std_logic; 42 | pls_o : out std_logic 43 | ); 44 | end Dbncr; 45 | 46 | architecture Behavioral of Dbncr is 47 | 48 | signal cnt : integer range 0 to NR_OF_CLKS-1; 49 | signal sigTmp : std_logic; 50 | signal stble, stbleTmp : std_logic; 51 | 52 | begin 53 | 54 | DEB: process(clk_i) 55 | begin 56 | if rising_edge(clk_i) then 57 | if sig_i = sigTmp then -- Count the number of clock periods if the signal is stable 58 | if cnt = NR_OF_CLKS-1 then 59 | stble <= sig_i; 60 | else 61 | cnt <= cnt + 1; 62 | end if; 63 | else -- Reset counter and sample the new signal value 64 | cnt <= 0; 65 | sigTmp <= sig_i; 66 | end if; 67 | end if; 68 | end process DEB; 69 | 70 | PLS: process(clk_i) 71 | begin 72 | if rising_edge(clk_i) then 73 | stbleTmp <= stble; 74 | end if; 75 | end process PLS; 76 | 77 | -- generate the one-shot output signal 78 | pls_o <= '1' when stbleTmp = '0' and stble = '1' else '0'; 79 | 80 | end Behavioral; 81 | 82 | -------------------------------------------------------------------------------- /Projects/User_Demo/src/hdl/LedBar.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------------------------- 2 | ---------------------------------------------------------------------------- 3 | -- Author: Mihaita Nagy 4 | -- Copyright 2014 Digilent, Inc. 5 | ---------------------------------------------------------------------------- 6 | -- 7 | -- Create Date: 14:23:44 04/02/2013 8 | -- Design Name: 9 | -- Module Name: LedBar - Behavioral 10 | -- Project Name: 11 | -- Target Devices: 12 | -- Tool versions: 13 | -- Description: 14 | -- This module generates a progressbar on the Nexys4 onboard LEDs. The progressbar moves to left 15 | -- when recording is in progress and moves to right when playback is in progress 16 | -- 17 | -- 18 | -- Revision: 19 | -- Revision 0.01 - File Created 20 | -- Additional Comments: 21 | -- 22 | ---------------------------------------------------------------------------------- 23 | library IEEE; 24 | use IEEE.STD_LOGIC_1164.ALL; 25 | use ieee.std_logic_arith.all; 26 | use ieee.std_logic_unsigned.all; 27 | 28 | -- Uncomment the following library declaration if using 29 | -- arithmetic functions with Signed or Unsigned values 30 | --use IEEE.NUMERIC_STD.ALL; 31 | 32 | -- Uncomment the following library declaration if instantiating 33 | -- any Xilinx primitives in this code. 34 | --library UNISIM; 35 | --use UNISIM.VComponents.all; 36 | 37 | entity LedBar is 38 | generic( 39 | C_SYS_CLK_FREQ_MHZ : integer := 100; -- system clock frequency in MHz 40 | C_SECONDS_TO_RECORD : integer := 3 -- number of seconds to record 41 | ); 42 | port( 43 | clk_i : in std_logic; -- system clock 44 | en_i : in std_logic; -- active-high enable 45 | rnl_i : in std_logic; -- Right/Left shift select 46 | leds_o : out std_logic_vector(15 downto 0) -- output LED bus 47 | ); 48 | end LedBar; 49 | 50 | architecture Behavioral of LedBar is 51 | 52 | ------------------------------------------------------------------------ 53 | -- Constant Declarations 54 | ------------------------------------------------------------------------ 55 | constant CLK_DIV_RATIO : integer := (((C_SECONDS_TO_RECORD * C_SYS_CLK_FREQ_MHZ * 1000000)/16) - 1); 56 | 57 | ------------------------------------------------------------------------ 58 | -- Signal Declarations 59 | ------------------------------------------------------------------------ 60 | -- Clock divider counter 61 | signal cnt_clk : integer := 0; 62 | signal clk_div : std_logic; 63 | --Shift register to hold the Led data 64 | signal tmp_sig : std_logic_vector(15 downto 0) := (others => '0'); 65 | 66 | ------------------------------------------------------------------------ 67 | -- Module Implementation 68 | ------------------------------------------------------------------------ 69 | begin 70 | 71 | -- shift register 72 | SHFT: process(clk_i) 73 | begin 74 | if rising_edge(clk_i) then 75 | if en_i = '1' then 76 | if clk_div = '1' then 77 | -- shift left 78 | if rnl_i = '0' then 79 | tmp_sig <= tmp_sig(14 downto 0) & '1'; 80 | -- shift right 81 | else 82 | tmp_sig <= '1' & tmp_sig(15 downto 1); 83 | end if; 84 | end if; 85 | else 86 | tmp_sig <= (others => '0'); 87 | end if; 88 | end if; 89 | end process SHFT; 90 | 91 | leds_o <= tmp_sig; 92 | 93 | -- Generate shift clock 94 | CLK_CNT: process(clk_i) 95 | begin 96 | if rising_edge(clk_i) then 97 | if en_i = '0' or cnt_clk = CLK_DIV_RATIO then 98 | cnt_clk <= 0; 99 | clk_div <= '1'; 100 | else 101 | cnt_clk <= cnt_clk + 1; 102 | clk_div <= '0'; 103 | end if; 104 | end if; 105 | end process CLK_CNT; 106 | 107 | end Behavioral; 108 | 109 | -------------------------------------------------------------------------------- /Projects/User_Demo/src/hdl/LocalRst.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------------------------- 2 | ---------------------------------------------------------------------------- 3 | -- Author: Elod Gyorgy 4 | -- Copyright 2014 Digilent, Inc. 5 | ---------------------------------------------------------------------------- 6 | -- 7 | -- Create Date: 13:59:06 04/04/2011 8 | -- Design Name: 9 | -- Module Name: LocalRst - Behavioral 10 | -- Project Name: 11 | -- Target Devices: 12 | -- Tool versions: 13 | -- Description: 14 | -- This module generates a synchronous reset signal with a length specified 15 | -- by the RESET_PERIOD parameter 16 | -- 17 | -- Revision: 18 | -- Revision 0.01 - File Created 19 | -- Additional Comments: 20 | -- 21 | ---------------------------------------------------------------------------------- 22 | library IEEE; 23 | use IEEE.STD_LOGIC_1164.ALL; 24 | 25 | -- Uncomment the following library declaration if using 26 | -- arithmetic functions with Signed or Unsigned values 27 | --use IEEE.NUMERIC_STD.ALL; 28 | 29 | -- Uncomment the following library declaration if instantiating 30 | -- any Xilinx primitives in this code. 31 | --library UNISIM; 32 | --use UNISIM.VComponents.all; 33 | 34 | entity LocalRst is 35 | Generic ( RESET_PERIOD : natural := 4); 36 | Port ( RST_I : in STD_LOGIC; 37 | CLK_I : in STD_LOGIC; 38 | SRST_O : out STD_LOGIC); 39 | end LocalRst; 40 | 41 | architecture Behavioral of LocalRst is 42 | signal RstQ : std_logic_vector(RESET_PERIOD downto 0) := (others => '1'); 43 | begin 44 | 45 | RstQ(0) <= '0'; 46 | 47 | RESET_LINE: for i in 1 to RESET_PERIOD generate 48 | process(CLK_I, RST_I) 49 | begin 50 | if (RST_I = '1') then 51 | RstQ(i) <= '1'; 52 | elsif Rising_Edge(CLK_I) then 53 | RstQ(i) <= RstQ(i-1); 54 | end if; 55 | end process; 56 | end generate; 57 | 58 | SRST_O <= RstQ(RESET_PERIOD); 59 | 60 | end Behavioral; 61 | 62 | -------------------------------------------------------------------------------- /Projects/User_Demo/src/hdl/LogoDisplay.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------------------------- 2 | ---------------------------------------------------------------------------- 3 | -- Author: Sam Bobrowicz 4 | -- Copyright 2014 Digilent, Inc. 5 | ---------------------------------------------------------------------------- 6 | -- 7 | -- Create Date: 15:40:47 03/15/2013 8 | -- Design Name: 9 | -- Module Name: logo_display - Behavioral 10 | -- Project Name: 11 | -- Target Devices: 12 | -- Tool versions: 13 | -- Description: 14 | -- 15 | -- 16 | -- Revision: 17 | -- Revision 0.01 - File Created 18 | -- Additional Comments: 19 | -- 20 | ---------------------------------------------------------------------------------- 21 | library IEEE; 22 | use IEEE.STD_LOGIC_1164.ALL; 23 | use IEEE.STD_LOGIC_ARITH.ALL; 24 | use IEEE.STD_LOGIC_UNSIGNED.ALL; 25 | 26 | -- Uncomment the following library declaration if using 27 | -- arithmetic functions with Signed or Unsigned values 28 | --use IEEE.NUMERIC_STD.ALL; 29 | 30 | -- Uncomment the following library declaration if instantiating 31 | -- any Xilinx primitives in this code. 32 | --library UNISIM; 33 | --use UNISIM.VComponents.all; 34 | 35 | entity LogoDisplay is 36 | Generic ( 37 | X_START : integer range 2 to (Integer'high) := 40; 38 | Y_START : integer := 512 39 | ); 40 | Port ( CLK_I : in STD_LOGIC; 41 | H_COUNT_I : in STD_LOGIC_VECTOR(11 downto 0); 42 | V_COUNT_I : in STD_LOGIC_VECTOR(11 downto 0); 43 | RED_O : out STD_LOGIC_VECTOR(3 downto 0); 44 | BLUE_O : out STD_LOGIC_VECTOR(3 downto 0); 45 | GREEN_O : out STD_LOGIC_VECTOR(3 downto 0)); 46 | end LogoDisplay; 47 | 48 | architecture Behavioral of LogoDisplay is 49 | 50 | constant SZ_LOGO_WIDTH : natural := 335; -- Width of the logo frame 51 | constant SZ_LOGO_HEIGHT : natural := 280; -- Height of the logo frame 52 | 53 | COMPONENT BRAM_1 54 | PORT ( 55 | clka : IN STD_LOGIC; 56 | addra : IN STD_LOGIC_VECTOR(16 DOWNTO 0); 57 | douta : OUT STD_LOGIC_VECTOR(11 DOWNTO 0) 58 | ); 59 | END COMPONENT; 60 | 61 | signal addr_reg : std_logic_vector(16 downto 0) := (others => '0'); 62 | signal douta : std_logic_vector(11 downto 0); 63 | signal rst : std_logic; 64 | signal en : std_logic; 65 | 66 | begin 67 | 68 | -- BRAM containing the logo data, 69 | -- content in the BRAM_1.ngc file 70 | Inst_BRAM_1 : BRAM_1 71 | PORT MAP ( 72 | clka => CLK_I, 73 | addra => addr_reg, 74 | douta => douta 75 | ); 76 | 77 | -- Restart Address Counter when Vcount arrives to the beginning of the Logo frame 78 | rst <= '1' when (H_COUNT_I = 0 and V_COUNT_I = Y_START-1) else '0'; 79 | 80 | -- Increment Address counter only inside the frame 81 | en <= '1' when (H_COUNT_I > X_START-2 and H_COUNT_I < X_START + SZ_LOGO_WIDTH - 1 82 | and V_COUNT_I > Y_START and V_COUNT_I < Y_START + SZ_LOGO_HEIGHT -1 ) 83 | else '0'; 84 | 85 | -- Address counter 86 | process (CLK_I, rst, en) 87 | begin 88 | if(rising_edge(CLK_I))then 89 | if(rst = '1') then 90 | addr_reg <= (others => '0'); 91 | elsif(en = '1') then 92 | addr_reg <= addr_reg + 1; 93 | end if; 94 | end if; 95 | 96 | end process; 97 | 98 | -- Assign Outputs 99 | RED_O <= douta(11 downto 8); 100 | BLUE_O <= douta(3 downto 0); 101 | GREEN_O <= douta(7 downto 4); 102 | 103 | 104 | end Behavioral; 105 | 106 | -------------------------------------------------------------------------------- /Projects/User_Demo/src/hdl/MouseCtl.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Digilent/Nexys4DDR/bb66971474b74a0c55381625db3cfdceb3f21d78/Projects/User_Demo/src/hdl/MouseCtl.vhd -------------------------------------------------------------------------------- /Projects/User_Demo/src/hdl/MouseDisplay.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Digilent/Nexys4DDR/bb66971474b74a0c55381625db3cfdceb3f21d78/Projects/User_Demo/src/hdl/MouseDisplay.vhd -------------------------------------------------------------------------------- /Projects/User_Demo/src/hdl/PdmDes.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------------------------- 2 | ---------------------------------------------------------------------------- 3 | -- Author: Mihaita Nagy 4 | -- Copyright 2014 Digilent, Inc. 5 | ---------------------------------------------------------------------------- 6 | -- 7 | -- Create Date: 14:24:36 04/02/2013 8 | -- Design Name: 9 | -- Module Name: PdmDes - Behavioral 10 | -- Project Name: 11 | -- Target Devices: 12 | -- Tool versions: 13 | -- Description: 14 | -- This module represents the deserializer of the microphone data. The module generates 15 | -- the pdm_m_clk_o signal to the ADMP421 Microphone (M_CLK) and data is read on the positive 16 | -- edge of this signal. 17 | -- 18 | -- Then the module deserializes the signal on 16 bits when en_i = '1' (it means that recoding 19 | -- is going on) 20 | -- 21 | -- The module also generates the pdm_clk_rising_o signal, that is active when the positive edge of the 22 | -- pdm_m_clk_o signal occures. This signal is used in the VGA controller, the MicDisplay component to 23 | -- display audio data on the screen. The signal is two system clock period length, in order to make it 24 | -- easier the synchronizing with the VGA clock domain (108MHz) 25 | -- 26 | -- Revision: 27 | -- Revision 0.01 - File Created 28 | -- Additional Comments: 29 | -- 30 | ---------------------------------------------------------------------------------- 31 | library IEEE; 32 | use IEEE.STD_LOGIC_1164.ALL; 33 | use ieee.std_logic_arith.all; 34 | use ieee.std_logic_unsigned.all; 35 | 36 | ------------------------------------------------------------------------ 37 | -- Module Declaration 38 | ------------------------------------------------------------------------ 39 | entity PdmDes is 40 | generic( 41 | C_NR_OF_BITS : integer := 16; 42 | C_SYS_CLK_FREQ_MHZ : integer := 100; 43 | C_PDM_FREQ_HZ : integer := 2000000 44 | ); 45 | port( 46 | clk_i : in std_logic; 47 | en_i : in std_logic; -- Enable deserializing (during record) 48 | 49 | done_o : out std_logic; -- Signaling that 16 bits are deserialized 50 | data_o : out std_logic_vector(C_NR_OF_BITS - 1 downto 0); -- output deserialized data 51 | 52 | -- PDM 53 | pdm_m_clk_o : out std_logic; -- Output M_CLK signal to the microphone 54 | pdm_m_data_i : in std_logic; -- Input PDM data from the microphone 55 | pdm_lrsel_o : out std_logic; -- Set to '0', therefore data is read on the positive edge 56 | pdm_clk_rising_o : out std_logic -- Signaling the rising edge of M_CLK, used by the MicDisplay 57 | -- component in the VGA controller 58 | ); 59 | end PdmDes; 60 | 61 | architecture Behavioral of PdmDes is 62 | 63 | ------------------------------------------------------------------------ 64 | -- Signal Declarations 65 | ------------------------------------------------------------------------ 66 | -- Divider to create pdm_m_clk_0 67 | signal cnt_clk : integer range 0 to 127 := 0; 68 | -- Internal pdm_m_clk_o signal 69 | signal clk_int : std_logic := '0'; 70 | 71 | -- Piped clk_int signal to create pdm_clk_rising 72 | signal pdm_clk_rising : std_logic; 73 | 74 | -- Shift register to deserialize incoming microphone data 75 | signal pdm_tmp : std_logic_vector((C_NR_OF_BITS - 1) downto 0); 76 | -- Count the number of bits 77 | signal cnt_bits : integer range 0 to 31 := 0; 78 | 79 | -- To create a pdm_clk_rising impulse of two clock period length 80 | -- This signal will be registered in the MicDisplay module on the 108MHz pxlclk 81 | signal pdm_clk_rising_reg : std_logic_vector (2 downto 0); 82 | 83 | signal en_int : std_logic; 84 | signal done_int : std_logic; 85 | 86 | ------------------------------------------------------------------------ 87 | -- Module Implementation 88 | ------------------------------------------------------------------------ 89 | begin 90 | 91 | -- with L/R Sel tied to GND => output = DATA1 (rising edge) 92 | pdm_lrsel_o <= '0'; 93 | 94 | -- Synchronize the enable input 95 | SYNC: process(clk_i) 96 | begin 97 | if rising_edge(clk_i) then 98 | en_int <= en_i; 99 | end if; 100 | end process SYNC; 101 | 102 | ------------------------------------------------------------------------ 103 | -- Deserializer 104 | ------------------------------------------------------------------------ 105 | -- Sample input serial data process 106 | SHFT_IN: process(clk_i) 107 | begin 108 | if rising_edge(clk_i) then 109 | if pdm_clk_rising = '1' then 110 | pdm_tmp <= pdm_tmp(C_NR_OF_BITS-2 downto 0) & pdm_m_data_i; 111 | end if; 112 | end if; 113 | end process SHFT_IN; 114 | 115 | 116 | -- Count the number of sampled bits 117 | CNT: process(clk_i) begin 118 | if rising_edge(clk_i) then 119 | if en_int = '0' then 120 | cnt_bits <= 0; 121 | else 122 | if pdm_clk_rising = '1' then 123 | if cnt_bits = (C_NR_OF_BITS-1) then 124 | cnt_bits <= 0; 125 | else 126 | cnt_bits <= cnt_bits + 1; 127 | end if; 128 | end if; 129 | end if; 130 | end if; 131 | end process CNT; 132 | 133 | -- Generate the done signal 134 | process(clk_i) 135 | begin 136 | if rising_edge(clk_i) then 137 | if pdm_clk_rising = '1' then 138 | if cnt_bits = 0 then 139 | if en_int = '1' then 140 | done_int <= '1'; 141 | data_o <= pdm_tmp; 142 | end if; 143 | end if; 144 | else 145 | done_int <= '0'; 146 | end if; 147 | end if; 148 | end process; 149 | 150 | done_o <= done_int; 151 | 152 | -- Generate PDM Clock, that runs independent from the enable signal, therefore 153 | -- the onboard microphone will always send data, that is displayed on the VGA screen 154 | -- using the MicDisplay component 155 | CLK_CNT: process(clk_i) 156 | begin 157 | if rising_edge(clk_i) then 158 | if cnt_clk = (((C_SYS_CLK_FREQ_MHZ*1000000)/(C_PDM_FREQ_HZ*2))-1) then 159 | cnt_clk <= 0; 160 | clk_int <= not clk_int; 161 | if clk_int = '0' then 162 | pdm_clk_rising <= '1'; 163 | end if; 164 | else 165 | cnt_clk <= cnt_clk + 1; 166 | pdm_clk_rising <= '0'; 167 | end if; 168 | end if; 169 | end process CLK_CNT; 170 | 171 | pdm_m_clk_o <= clk_int; 172 | 173 | -- Register pdm_clk_rising 174 | -- to create a two clock period length impulse 175 | RISING_IMP: process(clk_i) 176 | begin 177 | if rising_edge(clk_i) then 178 | pdm_clk_rising_reg <= pdm_clk_rising_reg (1 downto 0) & pdm_clk_rising; 179 | end if; 180 | end process RISING_IMP; 181 | 182 | -- Assign the output pdm_clk_rising impulse 183 | ASSIGN_PDM_CLK_RISING_IMP: process(clk_i) 184 | begin 185 | if rising_edge(clk_i) then 186 | pdm_clk_rising_o <= (pdm_clk_rising_reg(0) or pdm_clk_rising_reg(1)) and (not pdm_clk_rising_reg(2)); 187 | end if; 188 | end process ASSIGN_PDM_CLK_RISING_IMP; 189 | 190 | end Behavioral; 191 | -------------------------------------------------------------------------------- /Projects/User_Demo/src/hdl/PdmSer.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------------------------- 2 | ---------------------------------------------------------------------------- 3 | -- Author: Mihaita Nagy 4 | -- Copyright 2014 Digilent, Inc. 5 | ---------------------------------------------------------------------------- 6 | -- 7 | -- Create Date: 14:25:21 04/02/2013 8 | -- Design Name: 9 | -- Module Name: PdmSer - Behavioral 10 | -- Project Name: 11 | -- Target Devices: 12 | -- Tool versions: 13 | -- Description: 14 | -- This module represents the serializer for the audio output data. The module generates 15 | -- an internal clk_int signal, having the same frequency as the M_CLK signal sent to the 16 | -- ADMP421 Microphone (see description of the PdmDes component). Data is sent to the audio line 17 | -- at the positive edge of this internal clk signal. 18 | -- The audio data is filtered on the board by the Sallen-Key Butterworth Low Pass 4th Order Filter 19 | -- and sent to the audio output. 20 | -- 21 | -- 22 | -- Revision: 23 | -- Revision 0.01 - File Created 24 | -- Additional Comments: 25 | -- 26 | ---------------------------------------------------------------------------------- 27 | library IEEE; 28 | use IEEE.STD_LOGIC_1164.ALL; 29 | use ieee.std_logic_arith.all; 30 | use ieee.std_logic_unsigned.all; 31 | 32 | -- Uncomment the following library declaration if using 33 | -- arithmetic functions with Signed or Unsigned values 34 | --use IEEE.NUMERIC_STD.ALL; 35 | 36 | -- Uncomment the following library declaration if instantiating 37 | -- any Xilinx primitives in this code. 38 | --library UNISIM; 39 | --use UNISIM.VComponents.all; 40 | 41 | entity PdmSer is 42 | generic( 43 | C_NR_OF_BITS : integer := 16; 44 | C_SYS_CLK_FREQ_MHZ : integer := 100; 45 | C_PDM_FREQ_HZ : integer := 2000000 46 | ); 47 | port( 48 | clk_i : in std_logic; 49 | en_i : in std_logic; -- Enable serializing (during playback) 50 | 51 | done_o : out std_logic; -- Signaling that data_i is sent 52 | data_i : in std_logic_vector(C_NR_OF_BITS - 1 downto 0); -- input data 53 | 54 | -- PWM 55 | pwm_audio_o : inout std_logic -- Output audio data 56 | ); 57 | end PdmSer; 58 | 59 | architecture Behavioral of PdmSer is 60 | 61 | ------------------------------------------------------------------------ 62 | -- Signal Declarations 63 | ------------------------------------------------------------------------ 64 | -- divider to create clk_int 65 | signal cnt_clk : integer range 0 to 255 := 0; 66 | -- internal pdm_clk signal 67 | signal clk_int : std_logic := '0'; 68 | 69 | -- Piped clk_int signal to create pdm_clk_rising 70 | signal pdm_clk_rising : std_logic; 71 | 72 | -- Shift register used to temporary store then serialize data 73 | signal pdm_s_tmp : std_logic_vector((C_NR_OF_BITS-1) downto 0); 74 | -- Count the number of bits 75 | signal cnt_bits : integer range 0 to 31 := 0; 76 | 77 | signal en_int, done_int : std_logic; 78 | 79 | ------------------------------------------------------------------------ 80 | -- Module Implementation 81 | ------------------------------------------------------------------------ 82 | begin 83 | 84 | -- Register en_i 85 | SYNC: process(clk_i) 86 | begin 87 | if rising_edge(clk_i) then 88 | en_int <= en_i; 89 | end if; 90 | end process SYNC; 91 | 92 | -- Count the number of sampled bits 93 | CNT: process(clk_i) begin 94 | if rising_edge(clk_i) then 95 | if en_int = '0' then 96 | cnt_bits <= 0; 97 | else 98 | if pdm_clk_rising = '1' then 99 | if cnt_bits = (C_NR_OF_BITS-1) then 100 | cnt_bits <= 0; 101 | else 102 | cnt_bits <= cnt_bits + 1; 103 | end if; 104 | end if; 105 | end if; 106 | end if; 107 | end process CNT; 108 | 109 | -- Generate done_o when the number of bits are serialized 110 | process(clk_i) 111 | begin 112 | if rising_edge(clk_i) then 113 | if pdm_clk_rising = '1' then 114 | if cnt_bits = (C_NR_OF_BITS-1) then 115 | done_int <= '1'; 116 | end if; 117 | else 118 | done_int <= '0'; 119 | end if; 120 | end if; 121 | end process; 122 | 123 | done_o <= done_int; 124 | 125 | ------------------------------------------------------------------------ 126 | -- Serializer 127 | ------------------------------------------------------------------------ 128 | SHFT_OUT: process(clk_i) 129 | begin 130 | if rising_edge(clk_i) then 131 | if pdm_clk_rising = '1' then 132 | if cnt_bits = 0 then 133 | pdm_s_tmp <= data_i; 134 | else 135 | pdm_s_tmp <= pdm_s_tmp(C_NR_OF_BITS-2 downto 0) & '0'; 136 | end if; 137 | end if; 138 | end if; 139 | end process SHFT_OUT; 140 | 141 | -- output the serial pdm data 142 | pwm_audio_o <= '0' when pdm_s_tmp(C_NR_OF_BITS-1) = '0' else 'Z'; 143 | 144 | -- Generate the internal PDM Clock 145 | CLK_CNT: process(clk_i) 146 | begin 147 | if rising_edge(clk_i) then 148 | if en_int = '0' then 149 | cnt_clk <= 0; 150 | pdm_clk_rising <= '0'; 151 | else 152 | if cnt_clk = (((C_SYS_CLK_FREQ_MHZ*1000000)/C_PDM_FREQ_HZ)-1) then 153 | cnt_clk <= 0; 154 | pdm_clk_rising <= '1'; 155 | else 156 | cnt_clk <= cnt_clk + 1; 157 | pdm_clk_rising <= '0'; 158 | end if; 159 | end if; 160 | end if; 161 | end process CLK_CNT; 162 | 163 | 164 | end Behavioral; 165 | 166 | -------------------------------------------------------------------------------- /Projects/User_Demo/src/hdl/Ps2Interface.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Digilent/Nexys4DDR/bb66971474b74a0c55381625db3cfdceb3f21d78/Projects/User_Demo/src/hdl/Ps2Interface.vhd -------------------------------------------------------------------------------- /Projects/User_Demo/src/hdl/Pwm.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------------------------- 2 | ---------------------------------------------------------------------------- 3 | -- Author: Mihaita Nagy 4 | -- Copyright 2014 Digilent, Inc. 5 | ---------------------------------------------------------------------------- 6 | -- 7 | -- Create Date: 18:46:55 03/05/2013 8 | -- Design Name: 9 | -- Module Name: pwm - Behavioral 10 | -- Project Name: 11 | -- Target Devices: 12 | -- Tool versions: 13 | -- Description: 14 | -- This module represents the 8-bit PWM component, used by the RgbLed module 15 | -- to generate the sweeping colors 16 | -- 17 | -- 18 | -- Revision: 19 | -- Revision 0.01 - File Created 20 | -- Additional Comments: 21 | -- 22 | ---------------------------------------------------------------------------------- 23 | library ieee; 24 | use ieee.std_logic_1164.all; 25 | use ieee.std_logic_arith.all; 26 | use ieee.std_logic_signed.all; 27 | 28 | entity Pwm is 29 | port( 30 | clk_i : in std_logic; -- system clock = 100MHz 31 | data_i : in std_logic_vector(7 downto 0); -- the number to be modulated 32 | pwm_o : out std_logic 33 | ); 34 | end Pwm; 35 | 36 | architecture Behavioral of Pwm is 37 | 38 | signal cnt : std_logic_vector(7 downto 0); 39 | 40 | begin 41 | 42 | COUNT: process(clk_i) 43 | begin 44 | if rising_edge(clk_i) then 45 | cnt <= cnt + '1'; 46 | end if; 47 | end process COUNT; 48 | 49 | COMPARE: process(data_i, cnt) 50 | begin 51 | if unsigned(cnt) < unsigned(data_i) then 52 | pwm_o <= '1'; 53 | else 54 | pwm_o <= '0'; 55 | end if; 56 | end process COMPARE; 57 | 58 | end Behavioral; 59 | 60 | -------------------------------------------------------------------------------- /Projects/User_Demo/src/hdl/sSegDisplay.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------------------------- 2 | ---------------------------------------------------------------------------- 3 | -- Author: Mircea Dabacan 4 | -- Copyright 2014 Digilent, Inc. 5 | ---------------------------------------------------------------------------- 6 | -- 7 | -- Create Date: 13:13:49 12/16/2010 8 | -- Design Name: 9 | -- Module Name: sSegDisplay - Behavioral 10 | -- Description: 11 | -- This module represents the seven-segment display multiplexer 12 | -- Because the pattern to be displayed does not contain numerical or 13 | -- alphabetical characters representable on a seven-segment display, 14 | -- the incoming data is NOT encoded to seven-segment code, 15 | -- instead the incoming data is sent directly to the cathodes, 16 | -- according to the diagram shown below 17 | -- Segment encoding 18 | -- 0 19 | -- --- 20 | -- 5 | | 1 21 | -- --- <- 6 22 | -- 4 | | 2 23 | -- --- 24 | -- 3 25 | -- Decimal Point = 7 26 | -- 27 | -- 28 | -- Revision: 29 | -- Revision 0.01 - File Created 30 | -- Additional Comments: 31 | -- 32 | ---------------------------------------------------------------------------------- 33 | library ieee; 34 | use ieee.std_logic_1164.all; 35 | use ieee.numeric_std.all; 36 | use IEEE.std_logic_unsigned.all; -- add to do arithmetic operations 37 | use IEEE.std_logic_arith.all; -- add to do arithmetic operations 38 | 39 | entity sSegDisplay is 40 | Port(ck : in std_logic; -- 100MHz system clock 41 | number : in std_logic_vector (63 downto 0); -- eight digit number to be displayed 42 | seg : out std_logic_vector (7 downto 0); -- display cathodes 43 | an : out std_logic_vector (7 downto 0)); -- display anodes (active-low, due to transistor complementing) 44 | end sSegDisplay; 45 | 46 | architecture Behavioral of sSegDisplay is 47 | 48 | signal cnt: std_logic_vector(19 downto 0); -- divider counter for ~95.3Hz refresh rate (with 100MHz main clock) 49 | signal hex: std_logic_vector(7 downto 0); -- hexadecimal digit 50 | signal intAn: std_logic_vector(7 downto 0); -- internal signal representing anode data 51 | 52 | begin 53 | 54 | -- Assign outputs 55 | an <= intAn; 56 | seg <= hex; 57 | 58 | clockDivider: process(ck) 59 | begin 60 | if ck'event and ck = '1' then 61 | cnt <= cnt + '1'; 62 | end if; 63 | end process clockDivider; 64 | 65 | -- Anode Select 66 | with cnt(19 downto 17) select -- 100MHz/2^20 = 95.3Hz 67 | intAn <= 68 | "11111110" when "000", 69 | "11111101" when "001", 70 | "11111011" when "010", 71 | "11110111" when "011", 72 | "11101111" when "100", 73 | "11011111" when "101", 74 | "10111111" when "110", 75 | "01111111" when others; 76 | 77 | -- Digit Select 78 | with cnt(19 downto 17) select -- 100MHz/2^20 = 95.3Hz 79 | hex <= 80 | number(7 downto 0) when "000", 81 | number(15 downto 8) when "001", 82 | number(23 downto 16) when "010", 83 | number(31 downto 24) when "011", 84 | number(39 downto 32) when "100", 85 | number(47 downto 40) when "101", 86 | number(55 downto 48) when "110", 87 | number(63 downto 56) when others; 88 | 89 | end Behavioral; -------------------------------------------------------------------------------- /Projects/User_Demo/src/ip/BRAM_1/BRAM_1.upgrade_log: -------------------------------------------------------------------------------- 1 | Copyright 1986-2015 Xilinx, Inc. All Rights Reserved. 2 | ------------------------------------------------------------------------------------ 3 | | Tool Version : Vivado v.2015.1 (win64) Build 1215546 Mon Apr 27 19:22:08 MDT 2015 4 | | Date : Mon Jun 29 12:51:35 2015 5 | | Host : Sparky running 64-bit Service Pack 1 (build 7601) 6 | | Command : upgrade_ip 7 | | Device : xc7a100tcsg324-1 8 | ------------------------------------------------------------------------------------ 9 | 10 | Upgrade Log for IP 'BRAM_1' 11 | 12 | 1. Summary 13 | ---------- 14 | 15 | CAUTION (success, with warnings) in the upgrade of BRAM_1 (xilinx.com:ip:blk_mem_gen:8.2) from (Rev. 1) to (Rev. 5) 16 | 17 | After upgrade, an IP may have parameter differences compared to the original customization. Please review the parameters within the IP customization GUI to ensure proper functionality. 18 | 19 | 2. Customization warnings 20 | ------------------------- 21 | 22 | WARNING: The normal upgrade process failed due to validation failures in the given configuration . Attempting partial upgrade. 23 | This process will attempt to set as many user parameters as possible.Please check the parameters whose values were not applied 24 | 25 | WARNING: Unable to set the value 'true' on parameter 'Load Init File' due to the following failure - 26 | Validation failed for parameter 'Coe File(Coe_File)' with value 'no_coe_file_loaded' for IP 'BRAM_1'. No COE file loaded 27 | .Restoring to an old valid value of 'false' 28 | 29 | WARNING: An attempt to modify the value of disabled parameter 'Coe_File' from 'no_coe_file_loaded' to '../../../../../Nexys4DDRUserDemoPort/Nexys4_all.coe' has been ignored for IP 'BRAM_1' 30 | 31 | 32 | 3. Debug Commands 33 | ----------------- 34 | 35 | The following debug information can be passed to Vivado as Tcl commands, 36 | in order to validate or debug the output of the upgrade flow. 37 | Please consult the warnings from the previous sections, and alter or remove 38 | the configuration parameter(s) which caused the warning; then execute the Tcl 39 | commands, and use the IP Customization GUI to verify the IP configuration. 40 | 41 | create_ip -vlnv xilinx.com:ip:blk_mem_gen:8.2 -user_name BRAM_1 42 | set_property -dict "\ 43 | CONFIG.Remaining_Memory_Locations 0 \ 44 | CONFIG.Reset_Memory_Latch_A false \ 45 | CONFIG.Reset_Memory_Latch_B false \ 46 | CONFIG.Enable_32bit_Address false \ 47 | CONFIG.softecc false \ 48 | CONFIG.Register_PortA_Output_of_Memory_Primitives false \ 49 | CONFIG.Operating_Mode_A WRITE_FIRST \ 50 | CONFIG.AXI_Slave_Type Memory_Slave \ 51 | CONFIG.Operating_Mode_B WRITE_FIRST \ 52 | CONFIG.Port_A_Clock 100 \ 53 | CONFIG.Reset_Type SYNC \ 54 | CONFIG.Reset_Priority_A CE \ 55 | CONFIG.Reset_Priority_B CE \ 56 | CONFIG.Use_RSTB_Pin false \ 57 | CONFIG.register_portb_output_of_softecc false \ 58 | CONFIG.ecctype No_ECC \ 59 | CONFIG.MEM_FILE no_mem_loaded \ 60 | CONFIG.Port_A_Enable_Rate 100 \ 61 | CONFIG.use_bram_block Stand_Alone \ 62 | CONFIG.Use_Byte_Write_Enable false \ 63 | CONFIG.Use_AXI_ID false \ 64 | CONFIG.AXI_Type AXI4_Full \ 65 | CONFIG.AXI_ID_Width 4 \ 66 | CONFIG.Coe_File ../../../../../Nexys4DDRUserDemoPort/Nexys4_all.coe \ 67 | CONFIG.Additional_Inputs_for_Power_Estimation false \ 68 | CONFIG.Use_REGCEA_Pin false \ 69 | CONFIG.Port_A_Write_Rate 0 \ 70 | CONFIG.Write_Width_A 12 \ 71 | CONFIG.Memory_Type Single_Port_ROM \ 72 | CONFIG.register_porta_input_of_softecc false \ 73 | CONFIG.Write_Width_B 12 \ 74 | CONFIG.Pipeline_Stages 0 \ 75 | CONFIG.Error_Injection_Type Single_Bit_Error_Injection \ 76 | CONFIG.Write_Depth_A 131072 \ 77 | CONFIG.Algorithm Minimum_Area \ 78 | CONFIG.Assume_Synchronous_Clk false \ 79 | CONFIG.Use_Error_Injection_Pins false \ 80 | CONFIG.Register_PortB_Output_of_Memory_Primitives false \ 81 | CONFIG.EN_ECC_PIPE false \ 82 | CONFIG.Disable_Out_of_Range_Warnings false \ 83 | CONFIG.Register_PortB_Output_of_Memory_Core false \ 84 | CONFIG.CTRL_ECC_ALGO NONE \ 85 | CONFIG.EN_SLEEP_PIN false \ 86 | CONFIG.Interface_Type Native \ 87 | CONFIG.Component_Name BRAM_1 \ 88 | CONFIG.Use_RSTA_Pin false \ 89 | CONFIG.Byte_Size 9 \ 90 | CONFIG.Port_B_Enable_Rate 0 \ 91 | CONFIG.Enable_A Always_Enabled \ 92 | CONFIG.Enable_B Always_Enabled \ 93 | CONFIG.Load_Init_File true \ 94 | CONFIG.Port_B_Write_Rate 0 \ 95 | CONFIG.Fill_Remaining_Memory_Locations false \ 96 | CONFIG.Collision_Warnings ALL \ 97 | CONFIG.Register_PortA_Output_of_Memory_Core false \ 98 | CONFIG.Disable_Collision_Warnings false \ 99 | CONFIG.Output_Reset_Value_A 0 \ 100 | CONFIG.Output_Reset_Value_B 0 \ 101 | CONFIG.Port_B_Clock 0 \ 102 | CONFIG.Primitive 8kx2 \ 103 | CONFIG.Use_REGCEB_Pin false \ 104 | CONFIG.Read_Width_A 12 \ 105 | CONFIG.ECC false \ 106 | CONFIG.Read_Width_B 12 " [get_ips BRAM_1] 107 | 108 | 109 | -------------------------------------------------------------------------------- /Projects/User_Demo/src/ip/Square_Root/Square_Root.upgrade_log: -------------------------------------------------------------------------------- 1 | Copyright 1986-2015 Xilinx, Inc. All Rights Reserved. 2 | ------------------------------------------------------------------------------------ 3 | | Tool Version : Vivado v.2015.1 (win64) Build 1215546 Mon Apr 27 19:22:08 MDT 2015 4 | | Date : Mon Jun 29 12:51:40 2015 5 | | Host : Sparky running 64-bit Service Pack 1 (build 7601) 6 | | Command : upgrade_ip 7 | | Device : xc7a100tcsg324-1 8 | ------------------------------------------------------------------------------------ 9 | 10 | Upgrade Log for IP 'Square_Root' 11 | 12 | 1. Summary 13 | ---------- 14 | 15 | SUCCESS in the upgrade of Square_Root (xilinx.com:ip:cordic:6.0) from (Rev. 4) to (Rev. 7) 16 | 17 | 18 | 19 | 20 | 21 | 22 | Copyright 1986-2014 Xilinx, Inc. All Rights Reserved. 23 | ----------------------------------------------------------------------------------- 24 | | Tool Version : Vivado v.2014.2 (win64) Build 932637 Wed Jun 11 13:33:10 MDT 2014 25 | | Date : Tue Dec 09 14:56:46 2014 26 | | Host : WK86 running 64-bit Service Pack 1 (build 7601) 27 | | Command : upgrade_ip 28 | | Device : xc7a100tcsg324-1 29 | ----------------------------------------------------------------------------------- 30 | 31 | Upgrade Log for IP 'Square_Root' 32 | 33 | 1. Summary 34 | ---------- 35 | 36 | CAUTION (success, with warnings) in the upgrade of Square_Root from xilinx.com:ip:cordic:4.0 to xilinx.com:ip:cordic:6.0 (Rev. 4) 37 | 38 | After upgrade, an IP may have parameter differences compared to the original customization. Please review the parameters within the IP customization GUI to ensure proper functionality. 39 | 40 | 2. Warnings 41 | ----------- 42 | 43 | WARNING: Migration from v4.0 also requires pin name changes. See the core documentation for full instructions on migration. 44 | 45 | 3. Upgrade messages 46 | ------------------- 47 | 48 | Removed parameter ND 49 | Removed parameter RDY 50 | Removed parameter X_OUT 51 | Removed parameter Y_OUT 52 | Removed parameter Phase_Output 53 | Removed parameter Register_Inputs 54 | Removed parameter Register_Outputs 55 | Renamed parameter CE to ACLKEN 56 | Renamed parameter SCLR to ARESETN 57 | Added parameter cartesian_has_tuser with value false 58 | Added parameter cartesian_tuser_width with value 1 59 | Added parameter cartesian_has_tlast with value false 60 | Added parameter phase_has_tuser with value false 61 | Added parameter phase_tuser_width with value 1 62 | Added parameter phase_has_tlast with value false 63 | Added parameter flow_control with value NonBlocking 64 | Added parameter optimize_goal with value Resources 65 | Added parameter out_tready with value false 66 | Added parameter out_tlast_behv with value Null 67 | 68 | 4. Customization warnings 69 | ------------------------- 70 | 71 | WARNING: Attempt to set value 'Resources' on disabled parameter 'optimize_goal' is ignored for 'Square_Root' 72 | 73 | 74 | 5. Debug Commands 75 | ----------------- 76 | 77 | The following debug information can be passed to Vivado as Tcl commands, 78 | in order to validate or debug the output of the upgrade flow. 79 | Please consult the warnings from the previous sections, and alter or remove 80 | the configuration parameter(s) which caused the warning; then execute the Tcl 81 | commands, and use the IP Customization GUI to verify the IP configuration. 82 | 83 | create_ip -vlnv xilinx.com:ip:cordic:6.0 -user_name Square_Root 84 | set_property -dict "\ 85 | CONFIG.ACLKEN false \ 86 | CONFIG.Input_Width 26 \ 87 | CONFIG.Architectural_Configuration Parallel \ 88 | CONFIG.phase_has_tuser false \ 89 | CONFIG.Iterations 0 \ 90 | CONFIG.Compensation_Scaling No_Scale_Compensation \ 91 | CONFIG.Pipelining_Mode Maximum \ 92 | CONFIG.cartesian_has_tlast false \ 93 | CONFIG.out_tready false \ 94 | CONFIG.Phase_Format Radians \ 95 | CONFIG.out_tlast_behv Null \ 96 | CONFIG.flow_control NonBlocking \ 97 | CONFIG.Functional_Selection Square_Root \ 98 | CONFIG.Component_Name Square_Root \ 99 | CONFIG.Round_Mode Truncate \ 100 | CONFIG.Precision 0 \ 101 | CONFIG.Coarse_Rotation false \ 102 | CONFIG.cartesian_has_tuser false \ 103 | CONFIG.Output_Width 14 \ 104 | CONFIG.ARESETN false \ 105 | CONFIG.Data_Format UnsignedInteger \ 106 | CONFIG.optimize_goal Resources \ 107 | CONFIG.phase_has_tlast false \ 108 | CONFIG.cartesian_tuser_width 1 \ 109 | CONFIG.phase_tuser_width 1 " [get_ips Square_Root] 110 | 111 | 112 | -------------------------------------------------------------------------------- /Projects/User_Demo/src/ip/ddr/ddr.upgrade_log: -------------------------------------------------------------------------------- 1 | Copyright 1986-2015 Xilinx, Inc. All Rights Reserved. 2 | ------------------------------------------------------------------------------------ 3 | | Tool Version : Vivado v.2015.1 (win64) Build 1215546 Mon Apr 27 19:22:08 MDT 2015 4 | | Date : Mon Jun 29 12:51:52 2015 5 | | Host : Sparky running 64-bit Service Pack 1 (build 7601) 6 | | Command : upgrade_ip 7 | | Device : xc7a100tcsg324-1 8 | ------------------------------------------------------------------------------------ 9 | 10 | Upgrade Log for IP 'ddr' 11 | 12 | 1. Summary 13 | ---------- 14 | 15 | SUCCESS in the upgrade of ddr from xilinx.com:ip:mig_7series:1.9 to xilinx.com:ip:mig_7series:2.3 (Rev. 1) 16 | 17 | -------------------------------------------------------------------------------- /Projects/User_Demo/src/ip/ddr/ddr/datasheet.txt: -------------------------------------------------------------------------------- 1 | 2 | 3 | Vivado Project Options: 4 | Target Device : xc7a100t-csg324 5 | Speed Grade : -1 6 | HDL : vhdl 7 | Synthesis Tool : VIVADO 8 | 9 | MIG Output Options: 10 | Module Name : ddr 11 | No of Controllers : 1 12 | Selected Compatible Device(s) : -- 13 | 14 | FPGA Options: 15 | System Clock Type : No Buffer 16 | Reference Clock Type : Use System Clock 17 | Debug Port : OFF 18 | Internal Vref : enabled 19 | IO Power Reduction : ON 20 | XADC instantiation in MIG : Disabled 21 | 22 | Extended FPGA Options: 23 | DCI for DQ,DQS/DQS#,DM : enabled 24 | Internal Termination (HR Banks) : 50 Ohms 25 | 26 | /*******************************************************/ 27 | /* Controller 0 */ 28 | /*******************************************************/ 29 | Controller Options : 30 | Memory : DDR2_SDRAM 31 | Interface : NATIVE 32 | Design Clock Frequency : 3333 ps ( 0.00 MHz) 33 | Phy to Controller Clock Ratio : 4:1 34 | Input Clock Period : 4999 ps 35 | CLKFBOUT_MULT (PLL) : 6 36 | DIVCLK_DIVIDE (PLL) : 1 37 | VCC_AUX IO : 1.8V 38 | Memory Type : Components 39 | Memory Part : MT47H64M16HR-25E 40 | Equivalent Part(s) : -- 41 | Data Width : 16 42 | ECC : Disabled 43 | Data Mask : enabled 44 | ORDERING : Strict 45 | 46 | AXI Parameters : 47 | Data Width : 128 48 | Arbitration Scheme : RD_PRI_REG 49 | Narrow Burst Support : 0 50 | ID Width : 4 51 | 52 | Memory Options: 53 | Burst Length (MR0[1:0]) : 8 54 | CAS Latency (MR0[6:4]) : 5 55 | Output Drive Strength (MR1[5,1]) : Fullstrength 56 | Controller CS option : Enable 57 | Rtt_NOM - ODT (MR1[9,6,2]) : 50ohms 58 | Memory Address Mapping : BANK_ROW_COLUMN 59 | 60 | 61 | Bank Selections: 62 | 63 | System_Control: 64 | SignalName: sys_rst 65 | PadLocation: No connect Bank: Select Bank 66 | SignalName: init_calib_complete 67 | PadLocation: No connect Bank: Select Bank 68 | SignalName: tg_compare_error 69 | PadLocation: No connect Bank: Select Bank 70 | 71 | 72 | 73 | 74 | -------------------------------------------------------------------------------- /Projects/User_Demo/src/ip/ddr/ddr/docs/phy_only_support_readme.txt: -------------------------------------------------------------------------------- 1 | This file includes the information about the PHY layer support: 2 | 3 | - Folder "/user_design/rtl/phy" includes the PHY layer 4 | RTL modules. 5 | - The top-level PHY module to be instantiated is ddr_phy_top (ddr_phy_top.v) 6 | - PHY modules can be used in any environment by taking the RTL modules 7 | listed in "phy" folder and PHY layer needs to be connected to 8 | the memory controller. 9 | - Refer to User Guide (UG586) section "Physical Layer Interface (Non-Memory 10 | Controller Design)" for more details on PHY interface signaling, 11 | parameter(s) and timing information. 12 | -------------------------------------------------------------------------------- /Projects/User_Demo/src/ip/ddr/ddr/example_design/log.txt: -------------------------------------------------------------------------------- 1 | Log file 2 | 3 | Generated by MIG MIG Version 2.3 4 | Coregen 14.7 - Build Number P_INT.20150421 on Mon Jul 6 16:41:13 2015 5 | 6 | 7 | Creating the directory 8 | c:/Users/Nate/Desktop/Nexys4DDR/Projects/Nexys4DDR_User_Demo/src/ip/ddr/_tmp/ddr/example_design 9 | Created the SDC file - c:/Users/Nate/Desktop/Nexys4DDR/Projects/Nexys4DDR_User_Demo/src/ip/ddr/_tmp/ddr/example_design/par/example_top.xdc Successfully 10 | Copied the Traffic Gen Files Successfully 11 | Created the file - c:/Users/Nate/Desktop/Nexys4DDR/Projects/Nexys4DDR_User_Demo/src/ip/ddr/_tmp/ddr/example_design/../docs/phy_only_support_readme.txt Successfully 12 | ..Successful 13 | Created the file - c:/Users/Nate/Desktop/Nexys4DDR/Projects/Nexys4DDR_User_Demo/src/ip/ddr/_tmp/ddr/example_design/par/readme.txt Successfully 14 | ..Successful 15 | Created the file - c:/Users/Nate/Desktop/Nexys4DDR/Projects/Nexys4DDR_User_Demo/src/ip/ddr/_tmp/ddr/example_design/sim/ddr2_model.v Successfully 16 | ..Successful 17 | Created the file - c:/Users/Nate/Desktop/Nexys4DDR/Projects/Nexys4DDR_User_Demo/src/ip/ddr/_tmp/ddr/example_design/sim/ddr2_model_parameters.vh Successfully 18 | ..Successful 19 | Created the file - c:/Users/Nate/Desktop/Nexys4DDR/Projects/Nexys4DDR_User_Demo/src/ip/ddr/_tmp/ddr/example_design/sim/xsim_files.prj Successfully 20 | ..Successful 21 | Created the file - c:/Users/Nate/Desktop/Nexys4DDR/Projects/Nexys4DDR_User_Demo/src/ip/ddr/_tmp/ddr/example_design/sim/xsim_options.tcl Successfully 22 | ..Successful 23 | Created the file - c:/Users/Nate/Desktop/Nexys4DDR/Projects/Nexys4DDR_User_Demo/src/ip/ddr/_tmp/ddr/example_design/sim/xsim_run.bat Successfully 24 | ..Successful 25 | Created the file - c:/Users/Nate/Desktop/Nexys4DDR/Projects/Nexys4DDR_User_Demo/src/ip/ddr/_tmp/ddr/example_design/sim/readme.txt Successfully 26 | ..Successful 27 | Created the file - c:/Users/Nate/Desktop/Nexys4DDR/Projects/Nexys4DDR_User_Demo/src/ip/ddr/_tmp/ddr/example_design/sim/sim.do Successfully 28 | ..Successful 29 | Created the file - c:/Users/Nate/Desktop/Nexys4DDR/Projects/Nexys4DDR_User_Demo/src/ip/ddr/_tmp/ddr/example_design/sim/sim_tb_top.v Successfully 30 | ..Successful 31 | Created the file - c:/Users/Nate/Desktop/Nexys4DDR/Projects/Nexys4DDR_User_Demo/src/ip/ddr/_tmp/ddr/example_design/sim/ies_run.sh Successfully 32 | ..Successful 33 | Created the file - c:/Users/Nate/Desktop/Nexys4DDR/Projects/Nexys4DDR_User_Demo/src/ip/ddr/_tmp/ddr/example_design/sim/vcs_run.sh Successfully 34 | ..Successful 35 | Created the file - c:/Users/Nate/Desktop/Nexys4DDR/Projects/Nexys4DDR_User_Demo/src/ip/ddr/_tmp/ddr/example_design/sim/wiredly.v Successfully 36 | ..Successful 37 | Created the Top Level File - c:/Users/Nate/Desktop/Nexys4DDR/Projects/Nexys4DDR_User_Demo/src/ip/ddr/_tmp/ddr/example_design/rtl/example_top_temp.vhd 38 | Created the Top Level File - c:/Users/Nate/Desktop/Nexys4DDR/Projects/Nexys4DDR_User_Demo/src/ip/ddr/_tmp/ddr/example_design/sim/sim_tb_top.v 39 | The design output files are located in c:/Users/Nate/Desktop/Nexys4DDR/Projects/Nexys4DDR_User_Demo/src/ip/ddr/_tmp/ddr/example_design/rtl and ..example_design/par for rtl & ucf files respectively. 40 | -------------------------------------------------------------------------------- /Projects/User_Demo/src/ip/ddr/ddr/example_design/par/example_top.xdc: -------------------------------------------------------------------------------- 1 | ################################################################################################## 2 | ## 3 | ## Xilinx, Inc. 2010 www.xilinx.com 4 | ## Mon Jul 6 16:41:12 2015 5 | ## Generated by MIG Version 2.3 6 | ## 7 | ################################################################################################## 8 | ## File name : example_top.xdc 9 | ## Details : Constraints file 10 | ## FPGA Family: ARTIX7 11 | ## FPGA Part: XC7A100T-CSG324 12 | ## Speedgrade: -1 13 | ## Design Entry: VHDL 14 | ## Frequency: 0 MHz 15 | ## Time Period: 3333 ps 16 | ################################################################################################## 17 | 18 | ################################################################################################## 19 | ## Controller 0 20 | ## Memory Device: DDR2_SDRAM->Components->MT47H64M16HR-25E 21 | ## Data Width: 16 22 | ## Time Period: 3333 23 | ## Data Mask: 1 24 | ################################################################################################## 25 | ############## NET - IOSTANDARD ################## 26 | 27 | 28 | 29 | set_property INTERNAL_VREF 0.900 [get_iobanks 34] -------------------------------------------------------------------------------- /Projects/User_Demo/src/ip/ddr/ddr/example_design/par/readme.txt: -------------------------------------------------------------------------------- 1 | Files in PAR folder : 2 | 3 | * "example_top.xdc" file is the constraint file for the design. This is used 4 | by Vivado. It has clock constraints, location constraints, IO standards 5 | and false path/SLICE constraints if any. 6 | 7 | * LTX/probe file is required when programming BIT file to FPGA as it contains 8 | the information of debug signals like signal name and position with respect 9 | to ILA/VIO core. The probe file (debug_nets.ltx) is auto generated by 10 | vivado tool and is found in .runs/impl_1/debug_nets.ltx 11 | 12 | 13 | compatible_ucf folder: 14 | 15 | * MIG outputs this folder only when Pin Compatible FPGAs are checked in GUI 16 | (Pin Compatible FPGAs page in GUI). It generates the XDC files for all 17 | the Compatible FPGAs selected in GUI. If you want to switch to any of the 18 | Compatible FPGAs follow the steps mentioned below. 19 | -------------------------------------------------------------------------------- /Projects/User_Demo/src/ip/ddr/ddr/example_design/rtl/traffic_gen/mig_7series_v2_3_afifo.v: -------------------------------------------------------------------------------- 1 | //***************************************************************************** 2 | // (c) Copyright 2008-2010 Xilinx, Inc. All rights reserved. 3 | // 4 | // This file contains confidential and proprietary information 5 | // of Xilinx, Inc. and is protected under U.S. and 6 | // international copyright and other intellectual property 7 | // laws. 8 | // 9 | // DISCLAIMER 10 | // This disclaimer is not a license and does not grant any 11 | // rights to the materials distributed herewith. Except as 12 | // otherwise provided in a valid license issued to you by 13 | // Xilinx, and to the maximum extent permitted by applicable 14 | // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 15 | // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 16 | // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 17 | // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 18 | // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 19 | // (2) Xilinx shall not be liable (whether in contract or tort, 20 | // including negligence, or under any other theory of 21 | // liability) for any loss or damage of any kind or nature 22 | // related to, arising under or in connection with these 23 | // materials, including for any direct, or any indirect, 24 | // special, incidental, or consequential loss or damage 25 | // (including loss of data, profits, goodwill, or any type of 26 | // loss or damage suffered as a result of any action brought 27 | // by a third party) even if such damage or loss was 28 | // reasonably foreseeable or Xilinx had been advised of the 29 | // possibility of the same. 30 | // 31 | // CRITICAL APPLICATIONS 32 | // Xilinx products are not designed or intended to be fail- 33 | // safe, or for use in any application requiring fail-safe 34 | // performance, such as life-support or safety devices or 35 | // systems, Class III medical devices, nuclear facilities, 36 | // applications related to the deployment of airbags, or any 37 | // other applications that could lead to death, personal 38 | // injury, or severe property or environmental damage 39 | // (individually and collectively, "Critical 40 | // Applications"). Customer assumes the sole risk and 41 | // liability of any use of Xilinx products in Critical 42 | // Applications, subject only to applicable laws and 43 | // regulations governing limitations on product liability. 44 | // 45 | // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 46 | // PART OF THIS FILE AT ALL TIMES. 47 | // 48 | //***************************************************************************** 49 | // ____ ____ 50 | // / /\/ / 51 | // /___/ \ / Vendor: Xilinx 52 | // \ \ \/ Version: %version 53 | // \ \ Application: MIG 54 | // / / Filename: afifo.v 55 | // /___/ /\ Date Last Modified: $Date: 2011/06/02 08:37:18 $ 56 | // \ \ / \ Date Created: Oct 21 2008 57 | // \___\/\___\ 58 | // 59 | //Device: Spartan6 60 | //Design Name: DDR/DDR2/DDR3/LPDDR 61 | //Purpose: A generic synchronous fifo. 62 | //Reference: 63 | //Revision History: 1.2 11/8/2010 Removed unused signals. 64 | 65 | //***************************************************************************** 66 | 67 | `timescale 1ps/1ps 68 | 69 | module mig_7series_v2_3_afifo # 70 | ( 71 | parameter TCQ = 100, 72 | parameter DSIZE = 32, 73 | parameter FIFO_DEPTH = 16, 74 | parameter ASIZE = 4, 75 | parameter SYNC = 1 // only has always '1' logic. 76 | ) 77 | ( 78 | input wr_clk, 79 | input rst, 80 | input wr_en, 81 | input [DSIZE-1:0] wr_data, 82 | input rd_en, 83 | input rd_clk, 84 | output [DSIZE-1:0] rd_data, 85 | output reg full, 86 | output reg empty, 87 | output reg almost_full 88 | ); 89 | 90 | // memory array 91 | reg [DSIZE-1:0] mem [0:FIFO_DEPTH-1]; 92 | 93 | //Read Capture Logic 94 | // if Sync = 1, then no need to remove metastability logic because wrclk = rdclk 95 | reg [ASIZE:0] rd_capture_ptr; 96 | reg [ASIZE:0] pre_rd_capture_gray_ptr; 97 | reg [ASIZE:0] rd_capture_gray_ptr; 98 | 99 | reg [ASIZE:0] wr_capture_ptr; 100 | reg [ASIZE:0] pre_wr_capture_gray_ptr; 101 | reg [ASIZE:0] wr_capture_gray_ptr; 102 | wire [ASIZE:0] buf_avail; 103 | wire [ASIZE:0] buf_filled; 104 | wire [ASIZE-1:0] wr_addr, rd_addr; 105 | wire COutb,COutd; 106 | reg COuta,COutc; 107 | reg [ASIZE:0] wr_ptr, rd_ptr,rd_ptr_cp; 108 | integer i,j,k; 109 | 110 | 111 | always @ (rd_ptr) 112 | rd_capture_ptr = rd_ptr; 113 | 114 | 115 | 116 | //capture the wr_gray_pointers to rd_clk domains and convert the gray pointers to binary pointers 117 | // before do comparison. 118 | 119 | 120 | 121 | always @ (wr_ptr) 122 | wr_capture_ptr = wr_ptr; 123 | 124 | // dualport ram 125 | // Memory (RAM) that holds the contents of the FIFO 126 | 127 | 128 | assign wr_addr = wr_ptr[ASIZE-1:0]; 129 | assign rd_data = mem[rd_addr]; 130 | always @(posedge wr_clk) 131 | begin 132 | if (wr_en && !full) 133 | mem[wr_addr] <= #TCQ wr_data; 134 | 135 | end 136 | 137 | 138 | // Read Side Logic 139 | 140 | 141 | assign rd_addr = rd_ptr_cp[ASIZE-1:0]; 142 | assign rd_strobe = rd_en && !empty; 143 | 144 | integer n; 145 | // change the binary pointer to gray pointer 146 | 147 | 148 | always @(posedge rd_clk) 149 | begin 150 | if (rst) 151 | begin 152 | rd_ptr <= #TCQ 'b0; 153 | rd_ptr_cp <= #TCQ 'b0; 154 | 155 | end 156 | else begin 157 | if (rd_strobe) begin 158 | {COuta,rd_ptr} <= #TCQ rd_ptr + 1'b1; 159 | rd_ptr_cp <= #TCQ rd_ptr_cp + 1'b1; 160 | 161 | end 162 | 163 | // change the binary pointer to gray pointer 164 | end 165 | 166 | end 167 | 168 | //generate empty signal 169 | assign {COutb,buf_filled} = wr_capture_ptr - rd_ptr; 170 | 171 | always @ (posedge rd_clk ) 172 | begin 173 | if (rst) 174 | empty <= #TCQ 1'b1; 175 | else if ((buf_filled == 0) || (buf_filled == 1 && rd_strobe)) 176 | empty <= #TCQ 1'b1; 177 | else 178 | empty <= #TCQ 1'b0; 179 | end 180 | 181 | 182 | // write side logic; 183 | 184 | reg [ASIZE:0] wbin; 185 | wire [ASIZE:0] wgraynext, wbinnext; 186 | 187 | 188 | 189 | always @(posedge rd_clk) 190 | begin 191 | if (rst) 192 | begin 193 | wr_ptr <= #TCQ 'b0; 194 | end 195 | else begin 196 | if (wr_en) 197 | {COutc, wr_ptr} <= #TCQ wr_ptr + 1'b1; 198 | 199 | // change the binary pointer to gray pointer 200 | end 201 | 202 | end 203 | 204 | 205 | // calculate how many buf still available 206 | //assign {COutd,buf_avail }= (rd_capture_ptr + 5'd16) - wr_ptr; 207 | assign {COutd,buf_avail }= rd_capture_ptr - wr_ptr + + 5'd16; 208 | 209 | 210 | always @ (posedge wr_clk ) 211 | begin 212 | if (rst) 213 | full <= #TCQ 1'b0; 214 | else if ((buf_avail == 0) || (buf_avail == 1 && wr_en)) 215 | full <= #TCQ 1'b1; 216 | else 217 | full <= #TCQ 1'b0; 218 | end 219 | 220 | 221 | always @ (posedge wr_clk ) 222 | begin 223 | if (rst) 224 | almost_full <= #TCQ 1'b0; 225 | else if ((buf_avail == FIFO_DEPTH - 2 ) || ((buf_avail == FIFO_DEPTH -3) && wr_en)) 226 | almost_full <= #TCQ 1'b1; 227 | else 228 | almost_full <= #TCQ 1'b0; 229 | end 230 | 231 | endmodule 232 | -------------------------------------------------------------------------------- /Projects/User_Demo/src/ip/ddr/ddr/example_design/rtl/traffic_gen/mig_7series_v2_3_data_prbs_gen.v: -------------------------------------------------------------------------------- 1 | //***************************************************************************** 2 | // (c) Copyright 2008-2010 Xilinx, Inc. All rights reserved. 3 | // 4 | // This file contains confidential and proprietary information 5 | // of Xilinx, Inc. and is protected under U.S. and 6 | // international copyright and other intellectual property 7 | // laws. 8 | // 9 | // DISCLAIMER 10 | // This disclaimer is not a license and does not grant any 11 | // rights to the materials distributed herewith. Except as 12 | // otherwise provided in a valid license issued to you by 13 | // Xilinx, and to the maximum extent permitted by applicable 14 | // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 15 | // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 16 | // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 17 | // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 18 | // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 19 | // (2) Xilinx shall not be liable (whether in contract or tort, 20 | // including negligence, or under any other theory of 21 | // liability) for any loss or damage of any kind or nature 22 | // related to, arising under or in connection with these 23 | // materials, including for any direct, or any indirect, 24 | // special, incidental, or consequential loss or damage 25 | // (including loss of data, profits, goodwill, or any type of 26 | // loss or damage suffered as a result of any action brought 27 | // by a third party) even if such damage or loss was 28 | // reasonably foreseeable or Xilinx had been advised of the 29 | // possibility of the same. 30 | // 31 | // CRITICAL APPLICATIONS 32 | // Xilinx products are not designed or intended to be fail- 33 | // safe, or for use in any application requiring fail-safe 34 | // performance, such as life-support or safety devices or 35 | // systems, Class III medical devices, nuclear facilities, 36 | // applications related to the deployment of airbags, or any 37 | // other applications that could lead to death, personal 38 | // injury, or severe property or environmental damage 39 | // (individually and collectively, "Critical 40 | // Applications"). Customer assumes the sole risk and 41 | // liability of any use of Xilinx products in Critical 42 | // Applications, subject only to applicable laws and 43 | // regulations governing limitations on product liability. 44 | // 45 | // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 46 | // PART OF THIS FILE AT ALL TIMES. 47 | // 48 | //***************************************************************************** 49 | // ____ ____ 50 | // / /\/ / 51 | // /___/ \ / Vendor: Xilinx 52 | // \ \ \/ Version: %version 53 | // \ \ Application: MIG 54 | // / / Filename: data_prbs_gen.v 55 | // /___/ /\ Date Last Modified: $Date: 2011/06/02 08:37:19 $ 56 | // \ \ / \ Date Created: Fri Sep 01 2006 57 | // \___\/\___\ 58 | // 59 | //Device: Spartan6 60 | //Design Name: DDR/DDR2/DDR3/LPDDR 61 | //Purpose: This module is used LFSR to generate random data for memory 62 | // data write or memory data read comparison.The first data is 63 | // seeded by the input prbs_seed_i which is connected to memory address. 64 | //Reference: 65 | //Revision History: 66 | //***************************************************************************** 67 | 68 | `timescale 1ps/1ps 69 | 70 | module mig_7series_v2_3_data_prbs_gen # 71 | ( 72 | parameter TCQ = 100, 73 | 74 | parameter EYE_TEST = "FALSE", 75 | parameter PRBS_WIDTH = 32, // "SEQUENTIAL_BUrst_i" 76 | parameter SEED_WIDTH = 32 77 | ) 78 | ( 79 | input clk_i, 80 | input clk_en, 81 | input rst_i, 82 | input prbs_seed_init, // when high the prbs_x_seed will be loaded 83 | input [PRBS_WIDTH - 1:0] prbs_seed_i, 84 | 85 | output [PRBS_WIDTH - 1:0] prbs_o // generated address 86 | ); 87 | 88 | reg [PRBS_WIDTH - 1 :0] prbs; 89 | reg [PRBS_WIDTH :1] lfsr_q; 90 | integer i; 91 | 92 | 93 | 94 | always @ (posedge clk_i) 95 | begin 96 | if (prbs_seed_init && EYE_TEST == "FALSE" || rst_i ) //reset it to a known good state to prevent it locks up 97 | // if (rst_i ) //reset it to a known good state to prevent it locks up 98 | 99 | begin 100 | lfsr_q[4:1] <= #TCQ prbs_seed_i[3:0] | 4'h5; 101 | // lfsr_q[PRBS_WIDTH-1:4] <= #TCQ prbs_seed_i[PRBS_WIDTH-1:4] ; 102 | 103 | lfsr_q[PRBS_WIDTH:5] <= #TCQ prbs_seed_i[PRBS_WIDTH-1:4] ; 104 | end 105 | else if (clk_en) begin 106 | 107 | lfsr_q[32:9] <= #TCQ lfsr_q[31:8]; 108 | lfsr_q[8] <= #TCQ lfsr_q[32] ^ lfsr_q[7]; 109 | lfsr_q[7] <= #TCQ lfsr_q[32] ^ lfsr_q[6]; 110 | lfsr_q[6:4] <= #TCQ lfsr_q[5:3]; 111 | 112 | lfsr_q[3] <= #TCQ lfsr_q[32] ^ lfsr_q[2]; 113 | lfsr_q[2] <= #TCQ lfsr_q[1] ; 114 | lfsr_q[1] <= #TCQ lfsr_q[32]; 115 | 116 | 117 | end 118 | end 119 | 120 | always @ (lfsr_q[PRBS_WIDTH:1]) begin 121 | prbs = lfsr_q[PRBS_WIDTH:1]; 122 | end 123 | 124 | assign prbs_o = prbs; 125 | 126 | endmodule 127 | 128 | 129 | -------------------------------------------------------------------------------- /Projects/User_Demo/src/ip/ddr/ddr/example_design/rtl/traffic_gen/mig_7series_v2_3_tg_status.v: -------------------------------------------------------------------------------- 1 | //***************************************************************************** 2 | // (c) Copyright 2008-2010 Xilinx, Inc. All rights reserved. 3 | // 4 | // This file contains confidential and proprietary information 5 | // of Xilinx, Inc. and is protected under U.S. and 6 | // international copyright and other intellectual property 7 | // laws. 8 | // 9 | // DISCLAIMER 10 | // This disclaimer is not a license and does not grant any 11 | // rights to the materials distributed herewith. Except as 12 | // otherwise provided in a valid license issued to you by 13 | // Xilinx, and to the maximum extent permitted by applicable 14 | // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 15 | // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 16 | // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 17 | // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 18 | // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 19 | // (2) Xilinx shall not be liable (whether in contract or tort, 20 | // including negligence, or under any other theory of 21 | // liability) for any loss or damage of any kind or nature 22 | // related to, arising under or in connection with these 23 | // materials, including for any direct, or any indirect, 24 | // special, incidental, or consequential loss or damage 25 | // (including loss of data, profits, goodwill, or any type of 26 | // loss or damage suffered as a result of any action brought 27 | // by a third party) even if such damage or loss was 28 | // reasonably foreseeable or Xilinx had been advised of the 29 | // possibility of the same. 30 | // 31 | // CRITICAL APPLICATIONS 32 | // Xilinx products are not designed or intended to be fail- 33 | // safe, or for use in any application requiring fail-safe 34 | // performance, such as life-support or safety devices or 35 | // systems, Class III medical devices, nuclear facilities, 36 | // applications related to the deployment of airbags, or any 37 | // other applications that could lead to death, personal 38 | // injury, or severe property or environmental damage 39 | // (individually and collectively, "Critical 40 | // Applications"). Customer assumes the sole risk and 41 | // liability of any use of Xilinx products in Critical 42 | // Applications, subject only to applicable laws and 43 | // regulations governing limitations on product liability. 44 | // 45 | // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 46 | // PART OF THIS FILE AT ALL TIMES. 47 | // 48 | //***************************************************************************** 49 | // ____ ____ 50 | // / /\/ / 51 | // /___/ \ / Vendor: Xilinx 52 | // \ \ \/ Version: %version 53 | // \ \ Application: MIG 54 | // / / Filename: tg_status.v 55 | // /___/ /\ Date Last Modified: 56 | // \ \ / \ Date Created: 57 | // \___\/\___\ 58 | // 59 | //Device: Spartan6 60 | //Design Name: DDR/DDR2/DDR3/LPDDR 61 | //Purpose: This module compare the memory read data agaisnt compare data that generated from data_gen module. 62 | // Error signal will be asserted if the comparsion is not equal. 63 | //Reference: 64 | //Revision History: 65 | //***************************************************************************** 66 | 67 | `timescale 1ps/1ps 68 | 69 | 70 | module mig_7series_v2_3_tg_status #( 71 | parameter TCQ = 100, 72 | 73 | parameter DWIDTH = 32 74 | ) 75 | ( 76 | 77 | 78 | input clk_i , 79 | input rst_i , 80 | input manual_clear_error, 81 | input data_error_i , 82 | input [DWIDTH-1:0] cmp_data_i, 83 | input [DWIDTH-1:0] rd_data_i , 84 | input [31:0] cmp_addr_i , 85 | input [5:0] cmp_bl_i , 86 | input mcb_cmd_full_i , 87 | input mcb_wr_full_i, 88 | input mcb_rd_empty_i, 89 | output reg [64 + (2*DWIDTH - 1):0] error_status, 90 | output error 91 | ); 92 | 93 | reg data_error_r; 94 | reg error_set; 95 | assign error = error_set; 96 | 97 | always @ (posedge clk_i) 98 | data_error_r <= #TCQ data_error_i; 99 | 100 | always @ (posedge clk_i) 101 | begin 102 | 103 | if (rst_i || manual_clear_error) begin 104 | error_status <= #TCQ 'b0; 105 | error_set <= #TCQ 1'b0; 106 | end 107 | else begin 108 | // latch the first error only 109 | if (data_error_i && ~data_error_r && ~error_set ) begin 110 | error_status[31:0] <= #TCQ cmp_addr_i; 111 | error_status[37:32] <= #TCQ cmp_bl_i; 112 | error_status[40] <= #TCQ mcb_cmd_full_i; 113 | error_status[41] <= #TCQ mcb_wr_full_i; 114 | error_status[42] <= #TCQ mcb_rd_empty_i; 115 | error_set <= #TCQ 1'b1; 116 | error_status[64 + (DWIDTH - 1) :64] <= #TCQ cmp_data_i; 117 | error_status[64 + (2*DWIDTH - 1):64 + DWIDTH] <= #TCQ rd_data_i; 118 | 119 | end 120 | 121 | error_status[39:38] <= #TCQ 'b0; // reserved 122 | error_status[63:43] <= #TCQ 'b0; // reserved 123 | 124 | 125 | end end 126 | 127 | endmodule 128 | -------------------------------------------------------------------------------- /Projects/User_Demo/src/ip/ddr/ddr/example_design/sim/ies_run.sh: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Digilent/Nexys4DDR/bb66971474b74a0c55381625db3cfdceb3f21d78/Projects/User_Demo/src/ip/ddr/ddr/example_design/sim/ies_run.sh -------------------------------------------------------------------------------- /Projects/User_Demo/src/ip/ddr/ddr/example_design/sim/sim.do: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Digilent/Nexys4DDR/bb66971474b74a0c55381625db3cfdceb3f21d78/Projects/User_Demo/src/ip/ddr/ddr/example_design/sim/sim.do -------------------------------------------------------------------------------- /Projects/User_Demo/src/ip/ddr/ddr/example_design/sim/vcs_run.sh: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Digilent/Nexys4DDR/bb66971474b74a0c55381625db3cfdceb3f21d78/Projects/User_Demo/src/ip/ddr/ddr/example_design/sim/vcs_run.sh -------------------------------------------------------------------------------- /Projects/User_Demo/src/ip/ddr/ddr/example_design/sim/wiredly.v: -------------------------------------------------------------------------------- 1 | //***************************************************************************** 2 | // (c) Copyright 2009 - 2011 Xilinx, Inc. All rights reserved. 3 | // 4 | // This file contains confidential and proprietary information 5 | // of Xilinx, Inc. and is protected under U.S. and 6 | // international copyright and other intellectual property 7 | // laws. 8 | // 9 | // DISCLAIMER 10 | // This disclaimer is not a license and does not grant any 11 | // rights to the materials distributed herewith. Except as 12 | // otherwise provided in a valid license issued to you by 13 | // Xilinx, and to the maximum extent permitted by applicable 14 | // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 15 | // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 16 | // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 17 | // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 18 | // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 19 | // (2) Xilinx shall not be liable (whether in contract or tort, 20 | // including negligence, or under any other theory of 21 | // liability) for any loss or damage of any kind or nature 22 | // related to, arising under or in connection with these 23 | // materials, including for any direct, or any indirect, 24 | // special, incidental, or consequential loss or damage 25 | // (including loss of data, profits, goodwill, or any type of 26 | // loss or damage suffered as a result of any action brought 27 | // by a third party) even if such damage or loss was 28 | // reasonably foreseeable or Xilinx had been advised of the 29 | // possibility of the same. 30 | // 31 | // CRITICAL APPLICATIONS 32 | // Xilinx products are not designed or intended to be fail- 33 | // safe, or for use in any application requiring fail-safe 34 | // performance, such as life-support or safety devices or 35 | // systems, Class III medical devices, nuclear facilities, 36 | // applications related to the deployment of airbags, or any 37 | // other applications that could lead to death, personal 38 | // injury, or severe property or environmental damage 39 | // (individually and collectively, "Critical 40 | // Applications"). Customer assumes the sole risk and 41 | // liability of any use of Xilinx products in Critical 42 | // Applications, subject only to applicable laws and 43 | // regulations governing limitations on product liability. 44 | // 45 | // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 46 | // PART OF THIS FILE AT ALL TIMES. 47 | // 48 | //***************************************************************************** 49 | // ____ ____ 50 | // / /\/ / 51 | // /___/ \ / Vendor : Xilinx 52 | // \ \ \/ Version : 2.3 53 | // \ \ Application : MIG 54 | // / / Filename : wiredly.v 55 | // /___/ /\ Date Last Modified : $Date: 2011/06/23 08:25:20 $ 56 | // \ \ / \ Date Created : Fri Oct 14 2011 57 | // \___\/\___\ 58 | // 59 | // Device : 7Series 60 | // Design Name : DDR2 SDRAM 61 | // Purpose : 62 | // This module provide the definition of a zero ohm component (A, B). 63 | // 64 | // The applications of this component include: 65 | // . Normal operation of a jumper wire (data flowing in both directions) 66 | // This can corrupt data from DRAM to FPGA useful for verifying ECC function. 67 | // 68 | // The component consists of 2 ports: 69 | // . Port A: One side of the pass-through switch 70 | // . Port B: The other side of the pass-through switch 71 | 72 | // The model is sensitive to transactions on all ports. Once a transaction 73 | // is detected, all other transactions are ignored for that simulation time 74 | // (i.e. further transactions in that delta time are ignored). 75 | 76 | // Model Limitations and Restrictions: 77 | // Signals asserted on the ports of the error injector should not have 78 | // transactions occuring in multiple delta times because the model 79 | // is sensitive to transactions on port A, B ONLY ONCE during 80 | // a simulation time. Thus, once fired, a process will 81 | // not refire if there are multiple transactions occuring in delta times. 82 | // This condition may occur in gate level simulations with 83 | // ZERO delays because transactions may occur in multiple delta times. 84 | // 85 | // Reference : 86 | // Revision History : 87 | //***************************************************************************** 88 | 89 | `timescale 1ns / 1ps 90 | 91 | module WireDelay # ( 92 | parameter Delay_g = 0, 93 | parameter Delay_rd = 0, 94 | parameter ERR_INSERT = "OFF" 95 | ) 96 | ( 97 | inout A, 98 | inout B, 99 | input reset, 100 | input phy_init_done 101 | ); 102 | 103 | reg A_r; 104 | reg B_r; 105 | reg B_inv ; 106 | reg line_en; 107 | 108 | reg B_nonX; 109 | 110 | assign A = A_r; 111 | assign B = B_r; 112 | 113 | always @ (*) 114 | begin 115 | if (B === 1'bx) 116 | B_nonX <= $random; 117 | else 118 | B_nonX <= B; 119 | end 120 | 121 | always@(*) 122 | begin 123 | if((B_nonX == 'b1) || (B_nonX == 'b0)) 124 | B_inv <= #0 ~B_nonX ; 125 | else 126 | B_inv <= #0 'bz ; 127 | end 128 | 129 | always @(*) begin 130 | if (!reset) begin 131 | A_r <= 1'bz; 132 | B_r <= 1'bz; 133 | line_en <= 1'b0; 134 | end else begin 135 | if (line_en) begin 136 | B_r <= 1'bz; 137 | if ((ERR_INSERT == "ON") & (phy_init_done)) 138 | A_r <= #Delay_rd B_inv; 139 | else 140 | A_r <= #Delay_rd B_nonX; 141 | end else begin 142 | B_r <= #Delay_g A; 143 | A_r <= 1'bz; 144 | end 145 | end 146 | end 147 | 148 | always @(A or B) begin 149 | if (!reset) begin 150 | line_en <= 1'b0; 151 | end else if (A !== A_r) begin 152 | line_en <= 1'b0; 153 | end else if (B_r !== B) begin 154 | line_en <= 1'b1; 155 | end else begin 156 | line_en <= line_en; 157 | end 158 | end 159 | endmodule 160 | -------------------------------------------------------------------------------- /Projects/User_Demo/src/ip/ddr/ddr/example_design/sim/xsim_options.tcl: -------------------------------------------------------------------------------- 1 | ############################################################################### 2 | ## (c) Copyright 2012 Xilinx, Inc. All rights reserved. 3 | ## 4 | ## This file contains confidential and proprietary information 5 | ## of Xilinx, Inc. and is protected under U.S. and 6 | ## international copyright and other intellectual property 7 | ## laws. 8 | ## 9 | ## DISCLAIMER 10 | ## This disclaimer is not a license and does not grant any 11 | ## rights to the materials distributed herewith. Except as 12 | ## otherwise provided in a valid license issued to you by 13 | ## Xilinx, and to the maximum extent permitted by applicable 14 | ## law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 15 | ## WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 16 | ## AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 17 | ## BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 18 | ## INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 19 | ## (2) Xilinx shall not be liable (whether in contract or tort, 20 | ## including negligence, or under any other theory of 21 | ## liability) for any loss or damage of any kind or nature 22 | ## related to, arising under or in connection with these 23 | ## materials, including for any direct, or any indirect, 24 | ## special, incidental, or consequential loss or damage 25 | ## (including loss of data, profits, goodwill, or any type of 26 | ## loss or damage suffered as a result of any action brought 27 | ## by a third party) even if such damage or loss was 28 | ## reasonably foreseeable or Xilinx had been advised of the 29 | ## possibility of the same. 30 | ## 31 | ## CRITICAL APPLICATIONS 32 | ## Xilinx products are not designed or intended to be fail- 33 | ## safe, or for use in any application requiring fail-safe 34 | ## performance, such as life-support or safety devices or 35 | ## systems, Class III medical devices, nuclear facilities, 36 | ## applications related to the deployment of airbags, or any 37 | ## other applications that could lead to death, personal 38 | ## injury, or severe property or environmental damage 39 | ## (individually and collectively, "Critical 40 | ## Applications"). Customer assumes the sole risk and 41 | ## liability of any use of Xilinx products in Critical 42 | ## Applications, subject only to applicable laws and 43 | ## regulations governing limitations on product liability. 44 | ## 45 | ## THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 46 | ## PART OF THIS FILE AT ALL TIMES. 47 | ## 48 | ############################################################################### 49 | ## ____ ____ 50 | ## / /\/ / 51 | ## /___/ \ / Vendor : Xilinx 52 | ## \ \ \/ Version : 2.3 53 | ## \ \ Application : MIG 54 | ## / / Filename : xsim_options.tcl 55 | ## /___/ /\ Date Last Modified : $Date: 2011/06/02 08:31:16 $ 56 | ## \ \ / \ Date Created : Tue Jun 05 2012 57 | ## \___\/\___\ 58 | ## 59 | ## Device : 7 Series 60 | ## Design Name : DDR2 SDRAM 61 | ## Purpose : To give commands to XSIM Simulator through batch mode 62 | ## Assumptions: 63 | ## - Simulation takes place in \sim folder of MIG output directory 64 | ## Reference : 65 | ## Revision History: 66 | ############################################################################### 67 | 68 | 69 | add_wave -radix hex /sim_tb_top 70 | run 1000 us 71 | -------------------------------------------------------------------------------- /Projects/User_Demo/src/ip/ddr/ddr/example_design/sim/xsim_run.bat: -------------------------------------------------------------------------------- 1 | ::!/bin/csh -f 2 | ::***************************************************************************** 3 | :: (c) Copyright 2012 Xilinx, Inc. All rights reserved. 4 | :: 5 | :: This file contains confidential and proprietary information 6 | :: of Xilinx, Inc. and is protected under U.S. and 7 | :: international copyright and other intellectual property 8 | :: laws. 9 | :: 10 | :: DISCLAIMER 11 | :: This disclaimer is not a license and does not grant any 12 | :: rights to the materials distributed herewith. Except as 13 | :: otherwise provided in a valid license issued to you by 14 | :: Xilinx, and to the maximum extent permitted by applicable 15 | :: law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 16 | :: WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 17 | :: AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 18 | :: BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 19 | :: INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 20 | :: (2) Xilinx shall not be liable (whether in contract or tort, 21 | :: including negligence, or under any other theory of 22 | :: liability) for any loss or damage of any kind or nature 23 | :: related to, arising under or in connection with these 24 | :: materials, including for any direct, or any indirect, 25 | :: special, incidental, or consequential loss or damage 26 | :: (including loss of data, profits, goodwill, or any type of 27 | :: loss or damage suffered as a result of any action brought 28 | :: by a third party) even if such damage or loss was 29 | :: reasonably foreseeable or Xilinx had been advised of the 30 | :: possibility of the same. 31 | :: 32 | :: CRITICAL APPLICATIONS 33 | :: Xilinx products are not designed or intended to be fail- 34 | :: safe, or for use in any application requiring fail-safe 35 | :: performance, such as life-support or safety devices or 36 | :: systems, Class III medical devices, nuclear facilities, 37 | :: applications related to the deployment of airbags, or any 38 | :: other applications that could lead to death, personal 39 | :: injury, or severe property or environmental damage 40 | :: (individually and collectively, "Critical 41 | :: Applications"). Customer assumes the sole risk and 42 | :: liability of any use of Xilinx products in Critical 43 | :: Applications, subject only to applicable laws and 44 | :: regulations governing limitations on product liability. 45 | :: 46 | :: THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 47 | :: PART OF THIS FILE AT ALL TIMES. 48 | :: 49 | :: **************************************************************************** 50 | :: ____ ____ 51 | :: / /\/ / 52 | :: /___/ \ / Vendor : Xilinx 53 | :: \ \ \/ Version : 2.3 54 | :: \ \ Application : MIG 55 | :: / / Filename : xsim_run.bat 56 | :: /___/ /\ Date Last Modified : $Date: 2011/06/02 08:31:16 $ 57 | :: \ \ / \ Date Created : Tue Jun 05 2012 58 | :: \___\/\___\ 59 | :: 60 | :: Device : 7 Series 61 | :: Design Name : DDR2 SDRAM 62 | :: Purpose : Batch file to run Simulation through Vivado Simulator 63 | :: Reference : 64 | :: Revision History : 65 | :: **************************************************************************** 66 | 67 | 68 | echo Simulation Tool: Viavdo Simulator 69 | call xelab work.sim_tb_top work.glbl -prj xsim_files.prj -L unisims_ver -L secureip -s xsim_test -debug typical 70 | xsim -g -t xsim_options.tcl -wdb xsim_database.wdb xsim_test 71 | echo done 72 | -------------------------------------------------------------------------------- /Projects/User_Demo/src/ip/ddr/tcl.log: -------------------------------------------------------------------------------- 1 | MIG: 16:07:18 : Running synthesis.xit 2 | MIG: 16:09:29 : Running synthesis.xit 3 | MIG: 16:09:30 : IGN: ddr <==> ddr 4 | MIG: 16:09:30 : IGN: 200.02 <==> 200.02 5 | MIG: 16:09:30 : Running vhdl_synth_rpr.xit 6 | MIG: 16:09:30 : IGN: ddr <==> ddr 7 | MIG: 16:09:30 : IGN: 200.02 <==> 200.02 8 | MIG: 16:41:04 : Running synthesis.xit 9 | MIG: 16:41:04 : ################# RUNNING MIG BATCH ################### 10 | MIG: 16:41:04 : Writing IN file for 'ddr'...compDirPath: c:/Xilinx/Vivado/2015.1/data/ip/xilinx/mig_7series_v2_3... instDirPath: c:/Users/Nate/Desktop/Nexys4DDR/Projects/Nexys4DDR_User_Demo/src/ip/ddr 11 | MIG: 16:41:04 : synp_flow: -- synthesis_mode: Other 12 | MIG: 16:41:04 : outputDirectory: c:/Users/Nate/Desktop/Nexys4DDR/Projects/Nexys4DDR_User_Demo/src/ip/ddr/_tmp/ 13 | MIG: 16:41:04 : vivado_mode: xpg_pa 14 | MIG: 16:41:04 : locked false 15 | MIG: 16:41:04 : HDL Language: VHDL 16 | MIG: 16:41:04 : compInfo: false 17 | MIG: 16:41:04 : Vivado Options xc7a100t csg324 -1 18 | MIG: 16:41:04 : 1: xc7a100t 2: csg324 3: -1 19 | MIG: 16:41:04 : relative mig path: coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe 20 | MIG: 16:41:04 : xilinx_path: C:/Xilinx/Vivado/2015.1/ids_lite/ISE 21 | MIG: 16:41:04 : I am in catch area 22 | MIG: 16:41:04 : Running C:/Xilinx/Vivado/2015.1/ids_lite/ISE/coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe -cg_exc_inp c:/Users/Nate/Desktop/Nexys4DDR/Projects/Nexys4DDR_User_Demo/src/ip/ddr/xil_txt.in -cg_exc_out c:/Users/Nate/Desktop/Nexys4DDR/Projects/Nexys4DDR_User_Demo/src/ip/ddr/xil_txt.out ... 23 | MIG: 16:41:13 : XML_INPUT_FILE: c:/Users/Nate/Desktop/Nexys4DDR/Projects/Nexys4DDR_User_Demo/src/ip/ddr/ddr/mig.prj 24 | MIG: 16:41:13 : Component_Name: ddr 25 | MIG: 16:41:13 : Moving ddr ... 26 | MIG: 16:41:13 : Moving ddr.vho ... 27 | MIG: 16:41:13 : Moving ddr_xmdf.tcl ... 28 | MIG: 16:41:14 : Running vhdl_synth_rpr.xit 29 | MIG: 16:41:14 : IGN: ddr <==> ddr 30 | MIG: 16:41:14 : IGN: 200.02 <==> 200.02 31 | MIG: 16:41:14 : Running implementation.xit 32 | MIG: 16:41:14 : IGN: ddr <==> ddr 33 | MIG: 16:41:14 : IGN: 200.02 <==> 200.02 34 | -------------------------------------------------------------------------------- /Projects/User_Demo/src/ip/ddr/xil_txt.in: -------------------------------------------------------------------------------- 1 | SET_FLAG MODE BATCH 2 | SET_FLAG STANDALONE_MODE TRUE 3 | SET_PREFERENCE ipi_mode no 4 | SET_PREFERENCE is_ip_locked false 5 | SET_PREFERENCE devicefamily artix7 6 | SET_PREFERENCE device xc7a100t 7 | SET_PREFERENCE speedgrade -1 8 | SET_PREFERENCE package csg324 9 | SET_PREFERENCE verilogsim false 10 | SET_PREFERENCE vhdlsim true 11 | SET_PREFERENCE designentry VHDL 12 | SET_PREFERENCE outputdirectory c:/Users/Nate/Desktop/Nexys4DDR/Projects/Nexys4DDR_User_Demo/src/ip/ddr/_tmp/ 13 | SET_PREFERENCE subworkingdirectory c:/Users/Nate/Desktop/Nexys4DDR/Projects/Nexys4DDR_User_Demo/src/ip/ddr/_tmp/ 14 | SET_PREFERENCE flowvendor Other 15 | SET_PREFERENCE tool vivado 16 | SET_PREFERENCE compnamestatus 0 17 | SET_PARAMETER component_name ddr 18 | SET_PARAMETER xml_input_file C:/Users/Nate/Desktop/Nexys4DDR/Projects/Nexys4DDR_User_Demo/src/ip/ddr/ddr/mig.prj 19 | SET_PARAMETER data_dir_path c:/Xilinx/Vivado/2015.1/data/ip/xilinx/mig_7series_v2_3 20 | SET_CORE_NAME Memory Interface Generator (MIG 7 Series) 21 | SET_CORE_VERSION 2.3 22 | SET_CORE_VLNV xilinx.com:ip:mig_7series:2.3 23 | SET_CORE_PATH c:/Xilinx/Vivado/2015.1/data/ip/xilinx/mig_7series_v2_3 24 | SET_CORE_DATASHEET c:/Xilinx/Vivado/2015.1/data/ip/xilinx/mig_7series_v2_3/data/docs/ds176_7series_MIS.pdf 25 | -------------------------------------------------------------------------------- /Projects/User_Demo/src/ip/ddr/xil_txt.out: -------------------------------------------------------------------------------- 1 | SET_ERROR_CODE 0 2 | SET_XMDF_PATH ./ddr_xmdf.tcl 3 | SET_PARAMETER component_name ddr 4 | SET_PARAMETER xml_input_file ./ddr/mig.prj 5 | -------------------------------------------------------------------------------- /Projects/User_Demo/src/others/Nexys4_Overlay.bmp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Digilent/Nexys4DDR/bb66971474b74a0c55381625db3cfdceb3f21d78/Projects/User_Demo/src/others/Nexys4_Overlay.bmp -------------------------------------------------------------------------------- /Projects/User_Demo/src/others/Nexys4_all.bmp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Digilent/Nexys4DDR/bb66971474b74a0c55381625db3cfdceb3f21d78/Projects/User_Demo/src/others/Nexys4_all.bmp -------------------------------------------------------------------------------- /Projects/XADC_Demo/proj/_READ_ME_.txt: -------------------------------------------------------------------------------- 1 | In order to run the create_project script successfully, the folder must be in its initial state 2 | containing only the cleanup, create_project scripts, and this document. 3 | 4 | To restore the folder to its initial state, double-click the cleanup Windows Command Script. 5 | 6 | !!!!CAUTION!!!! 7 | 8 | Moving or copying the cleanup Windows Command Script can result in unintentional loss of data on your 9 | system. The script contains a short list of specific files to ignore once it is run, all other files 10 | and folders within its directory location will be ERASED. Use this only within the project folder as 11 | instructed. 12 | 13 | See material on the usage of demo projects at reference.digilentinc.com -------------------------------------------------------------------------------- /Projects/XADC_Demo/proj/cleanup.cmd: -------------------------------------------------------------------------------- 1 | @echo off 2 | rem delete all files from subfolders 3 | for /d /r %%i in (*) do del /f /q %%i\* 4 | rem delete all subfolders 5 | for /d %%i in (*) do rd /S /Q %%i 6 | 7 | rem unmark read only from all files 8 | attrib -R .\* /S 9 | 10 | rem mark read only those we wish to keep 11 | attrib +R .\create_project.tcl 12 | attrib +R .\cleanup.sh 13 | attrib +R .\cleanup.cmd 14 | attrib +R .\.gitignore 15 | attrib +R .\_READ_ME_.txt 16 | 17 | rem delete all non read-only 18 | del /Q /A:-R .\* 19 | 20 | rem unmark read-only 21 | attrib -R .\* 22 | -------------------------------------------------------------------------------- /Projects/XADC_Demo/proj/cleanup.sh: -------------------------------------------------------------------------------- 1 | # This script is useful for cleaning up the 'project' 2 | # directory of a Digilent Vivado-project git repository 3 | ### 4 | # Run the following command to change permissions of 5 | # this 'cleanup' file if needed: 6 | # chmod u+x cleanup.sh 7 | ### 8 | # Remove directories/subdirectories 9 | find . -mindepth 1 -type d -exec rm -rf {} + 10 | # Remove any other files than: 11 | find . -type f ! -name 'cleanup.sh' \ 12 | ! -name 'cleanup.cmd' \ 13 | ! -name 'create_project.tcl' \ 14 | ! -name '.gitignore' \ 15 | -exec rm -rf {} + 16 | -------------------------------------------------------------------------------- /Projects/XADC_Demo/proj/create_project.tcl: -------------------------------------------------------------------------------- 1 | # Run this script to create the Vivado project files in the WORKING DIRECTORY 2 | # If ::create_path global variable is set, the project is created under that path instead of the working dir 3 | 4 | if {[info exists ::create_path]} { 5 | set dest_dir $::create_path 6 | } else { 7 | set dest_dir [pwd] 8 | } 9 | puts "INFO: Creating new project in $dest_dir" 10 | 11 | # Set the reference directory for source file relative paths (by default the value is script directory path) 12 | set proj_name "XADC_Demo" 13 | 14 | # Set the reference directory for source file relative paths (by default the value is script directory path) 15 | set origin_dir ".." 16 | 17 | # Set the directory path for the original project from where this script was exported 18 | set orig_proj_dir "[file normalize "$origin_dir/proj"]" 19 | 20 | set src_dir $origin_dir/src 21 | set repo_dir $origin_dir/repo 22 | 23 | # Set the board part number 24 | set part_num "xc7a100tcsg324-1" 25 | 26 | # Create project 27 | create_project $proj_name $dest_dir 28 | 29 | # Set the directory path for the new project 30 | set proj_dir [get_property directory [current_project]] 31 | 32 | # Set project properties 33 | set obj [get_projects $proj_name] 34 | set_property "default_lib" "xil_defaultlib" $obj 35 | set_property "part" "$part_num" $obj 36 | set_property "simulator_language" "Mixed" $obj 37 | set_property "target_language" "VHDL" $obj 38 | 39 | # Create 'sources_1' fileset (if not found) 40 | if {[string equal [get_filesets -quiet sources_1] ""]} { 41 | create_fileset -srcset sources_1 42 | } 43 | 44 | # Create 'constrs_1' fileset (if not found) 45 | if {[string equal [get_filesets -quiet constrs_1] ""]} { 46 | create_fileset -constrset constrs_1 47 | } 48 | 49 | # Set IP repository paths 50 | set obj [get_filesets sources_1] 51 | set_property "ip_repo_paths" "[file normalize $repo_dir]" $obj 52 | 53 | # Add conventional sources 54 | add_files -quiet $src_dir/hdl 55 | 56 | # Add IPs 57 | add_files -quiet [glob -nocomplain ../src/ip/*/*.xci] 58 | 59 | # Add constraints 60 | add_files -fileset constrs_1 -quiet $src_dir/constraints 61 | 62 | # Refresh IP Repositories 63 | #update_ip_catalog 64 | 65 | # Create 'synth_1' run (if not found) 66 | if {[string equal [get_runs -quiet synth_1] ""]} { 67 | create_run -name synth_1 -part $part_num -flow {Vivado Synthesis 2014} -strategy "Flow_PerfOptimized_High" -constrset constrs_1 68 | } else { 69 | set_property strategy "Flow_PerfOptimized_High" [get_runs synth_1] 70 | set_property flow "Vivado Synthesis 2014" [get_runs synth_1] 71 | } 72 | set obj [get_runs synth_1] 73 | set_property "part" "$part_num" $obj 74 | set_property "steps.synth_design.args.fanout_limit" "400" $obj 75 | set_property "steps.synth_design.args.fsm_extraction" "one_hot" $obj 76 | set_property "steps.synth_design.args.keep_equivalent_registers" "1" $obj 77 | set_property "steps.synth_design.args.resource_sharing" "off" $obj 78 | set_property "steps.synth_design.args.no_lc" "1" $obj 79 | set_property "steps.synth_design.args.shreg_min_size" "5" $obj 80 | 81 | # set the current synth run 82 | current_run -synthesis [get_runs synth_1] 83 | 84 | # Create 'impl_1' run (if not found) 85 | if {[string equal [get_runs -quiet impl_1] ""]} { 86 | create_run -name impl_1 -part $part_num -flow {Vivado Implementation 2014} -strategy "Vivado Implementation Defaults" -constrset constrs_1 -parent_run synth_1 87 | } else { 88 | set_property strategy "Vivado Implementation Defaults" [get_runs impl_1] 89 | set_property flow "Vivado Implementation 2014" [get_runs impl_1] 90 | } 91 | set obj [get_runs impl_1] 92 | set_property "part" "$part_num" $obj 93 | set_property "steps.write_bitstream.args.bin_file" "1" $obj 94 | 95 | # set the current impl run 96 | current_run -implementation [get_runs impl_1] 97 | 98 | #puts "INFO: Project created:$proj_name" 99 | 100 | # Comment the following section, if there is no block design 101 | # Create block design 102 | #source $origin_dir/src/bd/bt_gpio.tcl 103 | 104 | # Generate the wrapper 105 | #set design_name [get_bd_designs] 106 | #make_wrapper -files [get_files $design_name.bd] -top -import 107 | 108 | #set obj [get_filesets sources_1] 109 | #set_property "top" "bt_gpio_top" $obj 110 | 111 | #puts "INFO: Block design created: $design_name.bd" 112 | -------------------------------------------------------------------------------- /Projects/XADC_Demo/src/hdl/DigitToSeg.v: -------------------------------------------------------------------------------- 1 | //////////////////////////////////////////////////////////////////////////////// 2 | // Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. 3 | //////////////////////////////////////////////////////////////////////////////// 4 | // ____ ____ 5 | // / /\/ / 6 | // /___/ \ / Vendor: Xilinx 7 | // \ \ \/ Version : 14.7 8 | // \ \ Application : sch2hdl 9 | // / / Filename : Top.vf 10 | // /___/ /\ Timestamp : 12/01/2014 17:59:05 11 | // \ \ / \ 12 | // \___\/\___\ 13 | // 14 | //Command: sch2hdl -intstyle ise -family spartan3e -verilog C:/Users/samue_000/Documents/FPGA/Projects/Stopwatch/sevensegdecoder/Top.vf -w C:/Users/samue_000/Documents/FPGA/Projects/Stopwatch/sevensegdecoder/Top.sch 15 | //Design Name: Top 16 | //Device: spartan3e 17 | //Purpose: 18 | // This verilog netlist is translated from an ECS schematic.It can be 19 | // synthesized and simulated, but it should not be modified. 20 | // 21 | `timescale 1ns / 1ps 22 | 23 | module DigitToSeg(in1, 24 | in2, 25 | in3, 26 | in4, 27 | in5, 28 | in6, 29 | in7, 30 | in8, 31 | mclk, 32 | an, 33 | dp, 34 | seg); 35 | 36 | input [3:0] in1; 37 | input [3:0] in2; 38 | input [3:0] in3; 39 | input [3:0] in4; 40 | input [3:0] in5; 41 | input [3:0] in6; 42 | input [3:0] in7; 43 | input [3:0] in8; 44 | input mclk; 45 | output [7:0] an; 46 | output [6:0] seg; 47 | output dp; 48 | 49 | //wire swt7; 50 | wire XLXN_94; 51 | wire [3:0] XLXN_102; 52 | wire [2:0] XLXN_109; 53 | 54 | sevensegdecoder XLXI_6 (.nIn(XLXN_102[3:0]), 55 | .ssOut(seg[6:0])); 56 | mux4_4bus XLXI_45 (.I0(in1[3:0]), 57 | .I1(in2[3:0]), 58 | .I2(in3[3:0]), 59 | .I3(in4[3:0]), 60 | .I4(in5[3:0]), 61 | .I5(in6[3:0]), 62 | .I6(in7[3:0]), 63 | .I7(in8[3:0]), 64 | .Sel(XLXN_109[2:0]), 65 | .Y(XLXN_102[3:0])); 66 | 67 | segClkDevider XLXI_47 (.clk(mclk), 68 | .rst(), 69 | .clk_div(XLXN_94)); 70 | 71 | //GND XLXI_48 (.G(swt7)); 72 | counter3bit XLXI_49 (.clk(XLXN_94), 73 | .rst(), 74 | .Q(XLXN_109[2:0])); 75 | decoder_3_8 XLXI_50 (.I(XLXN_109[2:0]), 76 | .dp(dp), 77 | .an(an[7:0])); 78 | 79 | 80 | endmodule 81 | -------------------------------------------------------------------------------- /Projects/XADC_Demo/src/hdl/UART_TX_CTRL.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------------------- 2 | -- UART_TX_CTRL.vhd -- UART Data Transfer Component 3 | ---------------------------------------------------------------------------- 4 | -- Author: Sam Bobrowicz 5 | -- Copyright 2011 Digilent, Inc. 6 | ---------------------------------------------------------------------------- 7 | -- 8 | ---------------------------------------------------------------------------- 9 | -- This component may be used to transfer data over a UART device. It will 10 | -- serialize a byte of data and transmit it over a TXD line. The serialized 11 | -- data has the following characteristics: 12 | -- *9600 Baud Rate 13 | -- *8 data bits, LSB first 14 | -- *1 stop bit 15 | -- *no parity 16 | -- 17 | -- Port Descriptions: 18 | -- 19 | -- SEND - Used to trigger a send operation. The upper layer logic should 20 | -- set this signal high for a single clock cycle to trigger a 21 | -- send. When this signal is set high DATA must be valid . Should 22 | -- not be asserted unless READY is high. 23 | -- DATA - The parallel data to be sent. Must be valid the clock cycle 24 | -- that SEND has gone high. 25 | -- CLK - A 100 MHz clock is expected 26 | -- READY - This signal goes low once a send operation has begun and 27 | -- remains low until it has completed and the module is ready to 28 | -- send another byte. 29 | -- UART_TX - This signal should be routed to the appropriate TX pin of the 30 | -- external UART device. 31 | -- 32 | ---------------------------------------------------------------------------- 33 | -- 34 | ---------------------------------------------------------------------------- 35 | -- Revision History: 36 | -- 08/08/2011(SamB): Created using Xilinx Tools 13.2 37 | ---------------------------------------------------------------------------- 38 | library IEEE; 39 | use IEEE.STD_LOGIC_1164.ALL; 40 | use IEEE.std_logic_unsigned.all; 41 | 42 | entity UART_TX_CTRL is 43 | Port ( SEND : in STD_LOGIC; 44 | DATA : in STD_LOGIC_VECTOR (7 downto 0); 45 | CLK : in STD_LOGIC; 46 | READY : out STD_LOGIC; 47 | UART_TX : out STD_LOGIC); 48 | end UART_TX_CTRL; 49 | 50 | architecture Behavioral of UART_TX_CTRL is 51 | 52 | type TX_STATE_TYPE is (RDY, LOAD_BIT, SEND_BIT); 53 | 54 | constant BIT_TMR_MAX : std_logic_vector(13 downto 0) := "10100010110000"; --10416 = (round(100MHz / 9600)) - 1 55 | constant BIT_INDEX_MAX : natural := 10; 56 | 57 | --Counter that keeps track of the number of clock cycles the current bit has been held stable over the 58 | --UART TX line. It is used to signal when the ne 59 | signal bitTmr : std_logic_vector(13 downto 0) := (others => '0'); 60 | 61 | --combinatorial logic that goes high when bitTmr has counted to the proper value to ensure 62 | --a 9600 baud rate 63 | signal bitDone : std_logic; 64 | 65 | --Contains the index of the next bit in txData that needs to be transferred 66 | signal bitIndex : natural; 67 | 68 | --a register that holds the current data being sent over the UART TX line 69 | signal txBit : std_logic := '1'; 70 | 71 | --A register that contains the whole data packet to be sent, including start and stop bits. 72 | signal txData : std_logic_vector(9 downto 0); 73 | 74 | signal txState : TX_STATE_TYPE := RDY; 75 | 76 | begin 77 | 78 | --Next state logic 79 | next_txState_process : process (CLK) 80 | begin 81 | if (rising_edge(CLK)) then 82 | case txState is 83 | when RDY => 84 | if (SEND = '1') then 85 | txState <= LOAD_BIT; 86 | end if; 87 | when LOAD_BIT => 88 | txState <= SEND_BIT; 89 | when SEND_BIT => 90 | if (bitDone = '1') then 91 | if (bitIndex = BIT_INDEX_MAX) then 92 | txState <= RDY; 93 | else 94 | txState <= LOAD_BIT; 95 | end if; 96 | end if; 97 | when others=> --should never be reached 98 | txState <= RDY; 99 | end case; 100 | end if; 101 | end process; 102 | 103 | bit_timing_process : process (CLK) 104 | begin 105 | if (rising_edge(CLK)) then 106 | if (txState = RDY) then 107 | bitTmr <= (others => '0'); 108 | else 109 | if (bitDone = '1') then 110 | bitTmr <= (others => '0'); 111 | else 112 | bitTmr <= bitTmr + 1; 113 | end if; 114 | end if; 115 | end if; 116 | end process; 117 | 118 | bitDone <= '1' when (bitTmr = BIT_TMR_MAX) else 119 | '0'; 120 | 121 | bit_counting_process : process (CLK) 122 | begin 123 | if (rising_edge(CLK)) then 124 | if (txState = RDY) then 125 | bitIndex <= 0; 126 | elsif (txState = LOAD_BIT) then 127 | bitIndex <= bitIndex + 1; 128 | end if; 129 | end if; 130 | end process; 131 | 132 | tx_data_latch_process : process (CLK) 133 | begin 134 | if (rising_edge(CLK)) then 135 | if (SEND = '1') then 136 | txData <= '1' & DATA & '0'; 137 | end if; 138 | end if; 139 | end process; 140 | 141 | tx_bit_process : process (CLK) 142 | begin 143 | if (rising_edge(CLK)) then 144 | if (txState = RDY) then 145 | txBit <= '1'; 146 | elsif (txState = LOAD_BIT) then 147 | txBit <= txData(bitIndex); 148 | end if; 149 | end if; 150 | end process; 151 | 152 | UART_TX <= txBit; 153 | READY <= '1' when (txState = RDY) else 154 | '0'; 155 | 156 | end Behavioral; 157 | 158 | -------------------------------------------------------------------------------- /Projects/XADC_Demo/src/hdl/XADCdemo.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 02/12/2015 03:26:51 PM 7 | // Design Name: 8 | // Module Name: // Project Name: 9 | // Target Devices: 10 | // Tool Versions: 11 | // Description: 12 | // 13 | // Dependencies: 14 | // 15 | // Revision: 16 | // Revision 0.01 - File Created 17 | // Additional Comments: 18 | // 19 | ////////////////////////////////////////////////////////////////////////////////// 20 | 21 | 22 | module XADCdemo( 23 | input CLK100MHZ, 24 | input vauxp2, 25 | input vauxn2, 26 | input vauxp3, 27 | input vauxn3, 28 | input vauxp10, 29 | input vauxn10, 30 | input vauxp11, 31 | input vauxn11, 32 | input [1:0] sw, 33 | output reg [15:0] LED, 34 | output [7:0] an, 35 | output dp, 36 | output [6:0] seg 37 | ); 38 | 39 | wire enable; 40 | wire ready; 41 | wire [15:0] data; 42 | reg [6:0] Address_in; 43 | reg [32:0] decimal; 44 | reg [3:0] dig0; 45 | reg [3:0] dig1; 46 | reg [3:0] dig2; 47 | reg [3:0] dig3; 48 | reg [3:0] dig4; 49 | reg [3:0] dig5; 50 | reg [3:0] dig6; 51 | 52 | 53 | 54 | 55 | //xadc instantiation connect the eoc_out .den_in to get continuous conversion 56 | xadc_wiz_0 XLXI_7 (.daddr_in(Address_in), //addresses can be found in the artix 7 XADC user guide DRP register space 57 | .dclk_in(CLK100MHZ), 58 | .den_in(enable), 59 | .di_in(), 60 | .dwe_in(), 61 | .busy_out(), 62 | .vauxp2(vauxp2), 63 | .vauxn2(vauxn2), 64 | .vauxp3(vauxp3), 65 | .vauxn3(vauxn3), 66 | .vauxp10(vauxp10), 67 | .vauxn10(vauxn10), 68 | .vauxp11(vauxp11), 69 | .vauxn11(vauxn11), 70 | .vn_in(), 71 | .vp_in(), 72 | .alarm_out(), 73 | .do_out(data), 74 | .reset_in(), 75 | .eoc_out(enable), 76 | .channel_out(), 77 | .drdy_out(ready)); 78 | 79 | 80 | 81 | //led visual dmm 82 | always @( posedge(CLK100MHZ)) 83 | begin 84 | if(ready == 1'b1) 85 | begin 86 | case (data[15:12]) 87 | 1: LED <= 16'b11; 88 | 2: LED <= 16'b111; 89 | 3: LED <= 16'b1111; 90 | 4: LED <= 16'b11111; 91 | 5: LED <= 16'b111111; 92 | 6: LED <= 16'b1111111; 93 | 7: LED <= 16'b11111111; 94 | 8: LED <= 16'b111111111; 95 | 9: LED <= 16'b1111111111; 96 | 10: LED <= 16'b11111111111; 97 | 11: LED <= 16'b111111111111; 98 | 12: LED <= 16'b1111111111111; 99 | 13: LED <= 16'b11111111111111; 100 | 14: LED <= 16'b111111111111111; 101 | 15: LED <= 16'b1111111111111111; 102 | default: LED <= 16'b1; 103 | endcase 104 | end 105 | 106 | 107 | end 108 | 109 | reg [32:0] count; 110 | //binary to decimal conversion 111 | always @ (posedge(CLK100MHZ)) 112 | begin 113 | 114 | if(count == 10000000)begin 115 | 116 | decimal = data >> 4; 117 | //looks nicer if our max value is 1V instead of .999755 118 | if(decimal >= 4093) 119 | begin 120 | dig0 = 0; 121 | dig1 = 0; 122 | dig2 = 0; 123 | dig3 = 0; 124 | dig4 = 0; 125 | dig5 = 0; 126 | dig6 = 1; 127 | count = 0; 128 | end 129 | else 130 | begin 131 | decimal = decimal * 250000; 132 | decimal = decimal >> 10; 133 | 134 | 135 | dig0 = decimal % 10; 136 | decimal = decimal / 10; 137 | 138 | dig1 = decimal % 10; 139 | decimal = decimal / 10; 140 | 141 | dig2 = decimal % 10; 142 | decimal = decimal / 10; 143 | 144 | dig3 = decimal % 10; 145 | decimal = decimal / 10; 146 | 147 | dig4 = decimal % 10; 148 | decimal = decimal / 10; 149 | 150 | dig5 = decimal % 10; 151 | decimal = decimal / 10; 152 | 153 | dig6 = decimal % 10; 154 | decimal = decimal / 10; 155 | 156 | count = 0; 157 | end 158 | end 159 | 160 | count = count + 1; 161 | 162 | end 163 | 164 | always @(posedge(CLK100MHZ)) 165 | begin 166 | case(sw) 167 | 0: Address_in <= 8'h12; 168 | 1: Address_in <= 8'h13; 169 | 2: Address_in <= 8'h1a; 170 | 3: Address_in <= 8'h1b; 171 | endcase 172 | 173 | 174 | end 175 | 176 | DigitToSeg segment1(.in1(dig0), 177 | .in2(dig1), 178 | .in3(dig2), 179 | .in4(dig3), 180 | .in5(dig4), 181 | .in6(dig5), 182 | .in7(dig6), 183 | .in8(), 184 | .mclk(CLK100MHZ), 185 | .an(an), 186 | .dp(dp), 187 | .seg(seg)); 188 | endmodule 189 | -------------------------------------------------------------------------------- /Projects/XADC_Demo/src/hdl/counter3bit.v: -------------------------------------------------------------------------------- 1 | module counter3bit ( 2 | input clk, 3 | input rst, 4 | output reg [2:0] Q 5 | ); 6 | 7 | always @ (posedge(clk)) // When will Always Block Be Triggered 8 | begin 9 | if (rst == 3'b111) 10 | // How Output reacts when Reset Is Asserted 11 | Q <= 3'b0; 12 | else 13 | // How Output reacts when Rising Edge of Clock Arrives? 14 | Q <= Q + 1'b1; 15 | end 16 | 17 | endmodule 18 | -------------------------------------------------------------------------------- /Projects/XADC_Demo/src/hdl/decoder3_8.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 00:48:27 09/09/2014 7 | // Design Name: 8 | // Module Name: decoder3_8 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module decoder_3_8 ( 22 | input [2:0] I, 23 | output [7:0] an, 24 | output dp 25 | ); 26 | 27 | assign an[0] = ~(~I[2] & ~I[1] & ~I[0]); 28 | assign an[1] = ~(~I[2] & ~I[1] & I[0]); 29 | 30 | assign an[2] = ~(~I[2] & I[1] & ~I[0]); 31 | assign an[3] = ~(~I[2] & I[1] & I[0]); 32 | 33 | assign an[4] = ~(I[2] & ~I[1] & ~I[0]); 34 | assign an[5] = ~(I[2] & ~I[1] & I[0]); 35 | assign an[6] = ~(I[2] & I[1] & ~I[0]); 36 | assign an[7] = ~(I[2] & I[1] & I[0]); 37 | 38 | //decimal place 39 | assign dp = ~(I[2] & I[1] & ~I[0]); 40 | 41 | endmodule 42 | -------------------------------------------------------------------------------- /Projects/XADC_Demo/src/hdl/mux4_4bus.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 02:26:40 09/09/2014 7 | // Design Name: 8 | // Module Name: mux2_1bus 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module mux4_4bus( 22 | input [3:0] I0, 23 | input [3:0] I1, 24 | input [3:0] I2, 25 | input [3:0] I3, 26 | 27 | input [3:0] I4, 28 | input [3:0] I5, 29 | input [3:0] I6, 30 | input [3:0] I7, 31 | 32 | input [2:0] Sel, 33 | output [3:0] Y 34 | ); 35 | 36 | 37 | assign Y = ( Sel == 0 )? I0 : ( Sel == 1 )? I1 : ( Sel == 2 )? I2 : ( Sel == 3 )? I3 : ( Sel == 4 )? I4 :( Sel == 5 )? I5 :( Sel == 6 )? I6 : I7; 38 | 39 | endmodule 40 | -------------------------------------------------------------------------------- /Projects/XADC_Demo/src/hdl/segClkDevider.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 02:03:00 09/16/2014 7 | // Design Name: 8 | // Module Name: segClkDevider 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module segClkDevider( 22 | input clk, 23 | input rst, 24 | output reg clk_div 25 | ); 26 | 27 | localparam constantNumber = 10000; 28 | reg [31:0] count; 29 | 30 | always @ (posedge(clk), posedge(rst)) 31 | begin 32 | if (rst == 1'b1) 33 | count <= 32'b0; 34 | else if (count == constantNumber - 1) 35 | count <= 32'b0; 36 | else 37 | count <= count + 1; 38 | end 39 | 40 | always @ (posedge(clk), posedge(rst)) 41 | begin 42 | if (rst == 1'b1) 43 | clk_div <= 1'b0; 44 | else if (count == constantNumber - 1) 45 | clk_div <= ~clk_div; 46 | else 47 | clk_div <= clk_div; 48 | end 49 | endmodule -------------------------------------------------------------------------------- /Projects/XADC_Demo/src/hdl/sevensegdecoder.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 01:55:33 09/09/2014 7 | // Design Name: 8 | // Module Name: sevensegdecoder 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module sevensegdecoder( 22 | 23 | input [3:0] nIn, 24 | output reg [6:0] ssOut 25 | ); 26 | 27 | always @(nIn) 28 | case (nIn) 29 | 4'h0: ssOut = 7'b1000000; 30 | 4'h1: ssOut = 7'b1111001; 31 | 4'h2: ssOut = 7'b0100100; 32 | 4'h3: ssOut = 7'b0110000; 33 | 4'h4: ssOut = 7'b0011001; 34 | 4'h5: ssOut = 7'b0010010; 35 | 4'h6: ssOut = 7'b0000010; 36 | 4'h7: ssOut = 7'b1111000; 37 | 4'h8: ssOut = 7'b0000000; 38 | 4'h9: ssOut = 7'b0011000; 39 | 4'hA: ssOut = 7'b0001000; 40 | 4'hB: ssOut = 7'b0000011; 41 | 4'hC: ssOut = 7'b1000110; 42 | 4'hD: ssOut = 7'b0100001; 43 | 4'hE: ssOut = 7'b0000110; 44 | 4'hF: ssOut = 7'b0001110; 45 | default: ssOut = 7'b1001001; 46 | endcase 47 | 48 | endmodule 49 | -------------------------------------------------------------------------------- /Projects/XADC_Demo/src/ip/xadc_wiz_0/xadc_wiz_0.upgrade_log: -------------------------------------------------------------------------------- 1 | Copyright 1986-2015 Xilinx, Inc. All Rights Reserved. 2 | ------------------------------------------------------------------------------------ 3 | | Tool Version : Vivado v.2015.1 (win64) Build 1215546 Mon Apr 27 19:22:08 MDT 2015 4 | | Date : Tue Jun 30 08:29:39 2015 5 | | Host : Sparky running 64-bit Service Pack 1 (build 7601) 6 | | Command : upgrade_ip 7 | | Device : xc7a100tcsg324-1 8 | ------------------------------------------------------------------------------------ 9 | 10 | Upgrade Log for IP 'xadc_wiz_0' 11 | 12 | 1. Summary 13 | ---------- 14 | 15 | SUCCESS in the upgrade of xadc_wiz_0 (xilinx.com:ip:xadc_wiz:3.0) from (Rev. 6) to (Rev. 7) 16 | 17 | --------------------------------------------------------------------------------