└── Projects ├── dma ├── sdk │ ├── dma │ │ ├── src │ │ │ ├── Xilinx.spec │ │ │ ├── platform_config.h │ │ │ ├── dma │ │ │ │ └── dma.h │ │ │ └── platform.h │ │ └── .project │ ├── design_1_wrapper_hw_platform_0 │ │ ├── system.hdf │ │ └── .project │ └── dma_bsp │ │ ├── .sdkproject │ │ ├── .cproject │ │ └── Makefile ├── repo │ └── local │ │ └── ip │ │ └── d_axi_i2s_audio_v2_0 │ │ └── src │ │ ├── d_axi_i2s_audio.xdc │ │ ├── Div_by_4.vhd │ │ ├── rst_sync.vhd │ │ └── Sync_ff.vhd └── proj │ ├── cleanup.cmd │ └── cleanup.sh ├── hdmi_in ├── sdk │ ├── HDMI_IN │ │ ├── src │ │ │ ├── README.txt │ │ │ └── timer_ps │ │ │ │ └── timer_ps.h │ │ └── .project │ ├── HDMI_IN_bsp │ │ ├── .sdkproject │ │ ├── .cproject │ │ └── Makefile │ └── hdmi_in_wrapper_hw_platform_0 │ │ ├── system.hdf │ │ └── .project ├── repo │ └── digilent │ │ ├── ip │ │ ├── dvi2rgb_v1_6 │ │ │ ├── src │ │ │ │ ├── dvi2rgb_ooc.xdc │ │ │ │ ├── dvi2rgb.xdc │ │ │ │ ├── 1024_edid.txt │ │ │ │ ├── 1080_edid.txt │ │ │ │ ├── 720p_edid.txt │ │ │ │ └── 900p_edid.txt │ │ │ ├── docs │ │ │ │ ├── dvi2rgb.pdf │ │ │ │ ├── dvi2rgb_v1_6.docx │ │ │ │ ├── 1024_edid.dat │ │ │ │ ├── 1080_edid.dat │ │ │ │ ├── 720p_edid.dat │ │ │ │ ├── 900p_edid.dat │ │ │ │ └── dat2txt.cpp │ │ │ └── gui │ │ │ │ └── dvi2rgb_v1_0.gtcl │ │ ├── Sync_v1_0 │ │ │ ├── docs │ │ │ │ └── Sync_v1_0.pdf │ │ │ └── src │ │ │ │ └── Sync.xdc │ │ ├── rgb2vga_v1_0 │ │ │ └── docs │ │ │ │ └── rgb2vga_v1_0.pdf │ │ ├── clock_forwarder_1.0 │ │ │ ├── xgui │ │ │ │ └── clock_forwarder_v1_0.tcl │ │ │ └── hdl │ │ │ │ └── clock_forwarder_v1_0.vhd │ │ └── axi_dynclk_v1_0 │ │ │ └── xgui │ │ │ └── axi_dynclk_v1_0.tcl │ │ └── if │ │ └── tmds_v1_0 │ │ └── tmds.xml └── proj │ ├── cleanup.cmd │ └── cleanup.sh ├── hdmi_out ├── hw_handoff │ └── hdmi_out_wrapper.hdf ├── sdk │ ├── fsbl_bsp │ │ ├── .sdkproject │ │ ├── .cproject │ │ └── Makefile │ ├── displaydemo_bsp │ │ ├── .sdkproject │ │ ├── .cproject │ │ └── Makefile │ ├── hdmi_out_wrapper_hw_platform_0 │ │ ├── system.hdf │ │ └── .project │ ├── displaydemo │ │ ├── .project │ │ └── src │ │ │ ├── timer_ps │ │ │ └── timer_ps.h │ │ │ └── display_demo.h │ └── fsbl │ │ └── .project ├── repo │ ├── digilent │ │ ├── ip │ │ │ ├── rgb2dvi_v1_2 │ │ │ │ ├── docs │ │ │ │ │ └── rgb2dvi_v1_2.pdf │ │ │ │ └── src │ │ │ │ │ ├── rgb2dvi_clocks.xdc │ │ │ │ │ ├── rgb2dvi_ooc.xdc │ │ │ │ │ └── rgb2dvi.xdc │ │ │ └── axi_dynclk_v1_0 │ │ │ │ └── xgui │ │ │ │ └── axi_dynclk_v1_0.tcl │ │ └── if │ │ │ └── tmds_v1_0 │ │ │ └── tmds.xml │ └── board_files │ │ └── zybo │ │ └── B.3 │ │ └── part0_pins.xml └── proj │ ├── cleanup.cmd │ └── cleanup.sh ├── linux_bd ├── hw_handoff │ └── linux_bd_wrapper.hdf ├── repo │ ├── vivado-library │ │ ├── ip │ │ │ ├── dvi2rgb_v1_6 │ │ │ │ ├── src │ │ │ │ │ ├── dvi2rgb_ooc.xdc │ │ │ │ │ ├── dvi2rgb.xdc │ │ │ │ │ ├── 1024_edid.txt │ │ │ │ │ ├── 1080_edid.txt │ │ │ │ │ ├── 720p_edid.txt │ │ │ │ │ └── 900p_edid.txt │ │ │ │ ├── docs │ │ │ │ │ ├── dvi2rgb.pdf │ │ │ │ │ ├── dvi2rgb_v1_6.docx │ │ │ │ │ ├── 1024_edid.dat │ │ │ │ │ ├── 1080_edid.dat │ │ │ │ │ ├── 720p_edid.dat │ │ │ │ │ ├── 900p_edid.dat │ │ │ │ │ └── dat2txt.cpp │ │ │ │ └── gui │ │ │ │ │ └── dvi2rgb_v1_0.gtcl │ │ │ ├── rgb2dvi │ │ │ │ ├── docs │ │ │ │ │ ├── rgb2dvi.docx │ │ │ │ │ └── rgb2dvi.pdf │ │ │ │ └── src │ │ │ │ │ ├── rgb2dvi_clocks.xdc │ │ │ │ │ ├── rgb2dvi_ooc.xdc │ │ │ │ │ └── rgb2dvi.xdc │ │ │ ├── Sync_v1_0 │ │ │ │ ├── docs │ │ │ │ │ └── Sync_v1_0.pdf │ │ │ │ └── src │ │ │ │ │ └── Sync.xdc │ │ │ ├── Pmods │ │ │ │ ├── PmodACL_v1_0 │ │ │ │ │ ├── src │ │ │ │ │ │ ├── PmodACL.hwdef │ │ │ │ │ │ ├── PmodACL_ooc.xdc │ │ │ │ │ │ └── PmodACL_pmod_bridge_0_0 │ │ │ │ │ │ │ └── PmodACL_pmod_bridge_0_0.upgrade_log │ │ │ │ │ ├── drivers │ │ │ │ │ │ └── PmodACL_v1_0 │ │ │ │ │ │ │ ├── src │ │ │ │ │ │ │ ├── PmodACL.c │ │ │ │ │ │ │ └── Makefile │ │ │ │ │ │ │ ├── data │ │ │ │ │ │ │ ├── PmodACL.mdd │ │ │ │ │ │ │ └── PmodACL.tcl │ │ │ │ │ │ │ └── examples │ │ │ │ │ │ │ └── main.c │ │ │ │ │ └── utils │ │ │ │ │ │ └── board │ │ │ │ │ │ └── board.xit │ │ │ │ ├── PmodALS_v1_0 │ │ │ │ │ ├── src │ │ │ │ │ │ ├── PmodALS.hwdef │ │ │ │ │ │ ├── PmodALS_ooc.xdc │ │ │ │ │ │ └── PmodALS_pmod_bridge_0_0 │ │ │ │ │ │ │ └── PmodALS_pmod_bridge_0_0.upgrade_log │ │ │ │ │ ├── drivers │ │ │ │ │ │ └── PmodALS_v1_0 │ │ │ │ │ │ │ ├── data │ │ │ │ │ │ │ ├── PmodALS.tcl │ │ │ │ │ │ │ └── PmodALS.mdd │ │ │ │ │ │ │ ├── src │ │ │ │ │ │ │ ├── Makefile │ │ │ │ │ │ │ └── PmodALS.h │ │ │ │ │ │ │ └── examples │ │ │ │ │ │ │ └── main.c │ │ │ │ │ └── utils │ │ │ │ │ │ └── board │ │ │ │ │ │ └── board.xit │ │ │ │ ├── PmodBT2_v1_0 │ │ │ │ │ ├── src │ │ │ │ │ │ ├── PmodBT2.hwdef │ │ │ │ │ │ ├── PmodBT2_ooc.xdc │ │ │ │ │ │ └── PmodBT2_pmod_bridge_0_0 │ │ │ │ │ │ │ └── PmodBT2_pmod_bridge_0_0.upgrade_log │ │ │ │ │ ├── drivers │ │ │ │ │ │ └── PmodBT2_v1_0 │ │ │ │ │ │ │ ├── data │ │ │ │ │ │ │ ├── PmodBT2.mdd │ │ │ │ │ │ │ └── PmodBT2.tcl │ │ │ │ │ │ │ ├── src │ │ │ │ │ │ │ ├── Makefile │ │ │ │ │ │ │ └── PmodBT2.h │ │ │ │ │ │ │ └── examples │ │ │ │ │ │ │ └── main.c │ │ │ │ │ └── utils │ │ │ │ │ │ └── board │ │ │ │ │ │ └── board.xit │ │ │ │ ├── PmodGPS_v1_1 │ │ │ │ │ ├── src │ │ │ │ │ │ ├── PmodGPS.hwdef │ │ │ │ │ │ └── PmodGPS_ooc.xdc │ │ │ │ │ ├── drivers │ │ │ │ │ │ └── PmodGPS_v1_1 │ │ │ │ │ │ │ ├── src │ │ │ │ │ │ │ ├── PmodGPS.c │ │ │ │ │ │ │ ├── PmodGPS.h │ │ │ │ │ │ │ ├── Makefile │ │ │ │ │ │ │ └── PmodGPS_selftest.c │ │ │ │ │ │ │ ├── data │ │ │ │ │ │ │ ├── PmodGPS.mdd │ │ │ │ │ │ │ └── PmodGPS.tcl │ │ │ │ │ │ │ └── examples │ │ │ │ │ │ │ └── main.c │ │ │ │ │ └── utils │ │ │ │ │ │ └── board │ │ │ │ │ │ └── board.xit │ │ │ │ ├── PmodAMP2_v1_0 │ │ │ │ │ ├── src │ │ │ │ │ │ ├── PmodAMP2.hwdef │ │ │ │ │ │ ├── PmodAMP2_ooc.xdc │ │ │ │ │ │ ├── PmodAMP2_xlslice_0_0 │ │ │ │ │ │ │ └── PmodAMP2_xlslice_0_0.upgrade_log │ │ │ │ │ │ ├── PmodAMP2_xlslice_0_1 │ │ │ │ │ │ │ └── PmodAMP2_xlslice_0_1.upgrade_log │ │ │ │ │ │ ├── PmodAMP2_xlslice_0_2 │ │ │ │ │ │ │ └── PmodAMP2_xlslice_0_2.upgrade_log │ │ │ │ │ │ ├── PmodAMP2_axi_gpio_0_0 │ │ │ │ │ │ │ └── PmodAMP2_axi_gpio_0_0.upgrade_log │ │ │ │ │ │ └── PmodAMP2_pmod_bridge_0_0 │ │ │ │ │ │ │ └── PmodAMP2_pmod_bridge_0_0.upgrade_log │ │ │ │ │ ├── ipshared │ │ │ │ │ │ └── digilentinc.com │ │ │ │ │ │ │ └── pwm_v1_0 │ │ │ │ │ │ │ └── drivers │ │ │ │ │ │ │ └── PWM_v1_0 │ │ │ │ │ │ │ ├── data │ │ │ │ │ │ │ ├── PWM.tcl │ │ │ │ │ │ │ └── PWM.mdd │ │ │ │ │ │ │ └── src │ │ │ │ │ │ │ ├── PWM.c │ │ │ │ │ │ │ ├── Makefile │ │ │ │ │ │ │ └── PWM_selftest.c │ │ │ │ │ ├── drivers │ │ │ │ │ │ └── PmodAMP2_v1_0 │ │ │ │ │ │ │ ├── data │ │ │ │ │ │ │ ├── PmodAMP2.tcl │ │ │ │ │ │ │ └── PmodAMP2.mdd │ │ │ │ │ │ │ ├── src │ │ │ │ │ │ │ ├── Makefile │ │ │ │ │ │ │ └── PmodAMP2.h │ │ │ │ │ │ │ └── examples │ │ │ │ │ │ │ └── main.c │ │ │ │ │ └── utils │ │ │ │ │ │ └── board │ │ │ │ │ │ └── board.xit │ │ │ │ ├── Pmod_Bridge_v1_0 │ │ │ │ │ ├── src │ │ │ │ │ │ ├── pmod_concat.hwdef │ │ │ │ │ │ └── pmod_concat_ooc.xdc │ │ │ │ │ └── utils │ │ │ │ │ │ └── board │ │ │ │ │ │ └── board.xit │ │ │ │ └── pmodOLEDrgb_v1_0 │ │ │ │ │ ├── ip │ │ │ │ │ ├── PmodOLEDrgb_axi_gpio_0_1.xcix │ │ │ │ │ ├── PmodOLEDrgb_pmod_bridge_0_0.xcix │ │ │ │ │ └── PmodOLEDrgb_axi_quad_spi_0_0.xcix │ │ │ │ │ ├── drivers │ │ │ │ │ └── PmodOLEDrgb_v1_0 │ │ │ │ │ │ ├── src │ │ │ │ │ │ ├── PmodOLEDrgb.c │ │ │ │ │ │ ├── Makefile │ │ │ │ │ │ └── PmodOLEDrgb_selftest.c │ │ │ │ │ │ ├── data │ │ │ │ │ │ ├── PmodOLEDrgb.mdd │ │ │ │ │ │ └── PmodOLEDrgb.tcl │ │ │ │ │ │ └── examples │ │ │ │ │ │ └── main.c │ │ │ │ │ └── utils │ │ │ │ │ └── board │ │ │ │ │ └── board.xit │ │ │ ├── rgb2vga_v1_0 │ │ │ │ └── docs │ │ │ │ │ └── rgb2vga_v1_0.pdf │ │ │ ├── rgb2dpvid_v1_0 │ │ │ │ ├── docs │ │ │ │ │ └── rgb2dpvid_v1_0.pdf │ │ │ │ └── xgui │ │ │ │ │ └── rgb2dpvid_v1_0.tcl │ │ │ ├── PWM_1.0 │ │ │ │ └── drivers │ │ │ │ │ └── PWM_v1_0 │ │ │ │ │ ├── data │ │ │ │ │ ├── PWM.tcl │ │ │ │ │ └── PWM.mdd │ │ │ │ │ └── src │ │ │ │ │ ├── PWM.c │ │ │ │ │ ├── Makefile │ │ │ │ │ └── PWM_selftest.c │ │ │ ├── axi_i2s_adi_1.2 │ │ │ │ ├── drivers │ │ │ │ │ └── axi_i2s_adi_v1_0 │ │ │ │ │ │ ├── data │ │ │ │ │ │ ├── axi_i2s_adi.tcl │ │ │ │ │ │ └── axi_i2s_adi.mdd │ │ │ │ │ │ └── src │ │ │ │ │ │ ├── axi_i2s_adi.c │ │ │ │ │ │ ├── Makefile │ │ │ │ │ │ └── axi_i2s_adi_selftest.c │ │ │ │ └── hdl │ │ │ │ │ └── adi_common │ │ │ │ │ ├── axi_streaming_dma_tx_fifo.vhd │ │ │ │ │ ├── dma_fifo.vhd │ │ │ │ │ └── axi_streaming_dma_rx_fifo.vhd │ │ │ ├── clock_forwarder_1.0 │ │ │ │ ├── xgui │ │ │ │ │ └── clock_forwarder_v1_0.tcl │ │ │ │ └── hdl │ │ │ │ │ └── clock_forwarder_v1_0.vhd │ │ │ └── axi_dynclk_v1_0 │ │ │ │ └── xgui │ │ │ │ └── axi_dynclk_v1_0.tcl │ │ └── if │ │ │ ├── pmod_v1_0 │ │ │ └── pmod.xml │ │ │ └── tmds_v1_0 │ │ │ └── tmds.xml │ └── ADI │ │ └── ip │ │ └── axi_i2s_adi │ │ ├── axi_streaming_dma_tx_fifo.vhd │ │ ├── dma_fifo.vhd │ │ └── axi_streaming_dma_rx_fifo.vhd ├── sdk │ ├── fsbl_bsp │ │ ├── .sdkproject │ │ ├── .cproject │ │ └── Makefile │ ├── linux_bd_wrapper_hw_platform_0 │ │ ├── system.hdf │ │ └── .project │ └── fsbl │ │ └── .project └── proj │ ├── cleanup.cmd │ └── cleanup.sh ├── sdsoc ├── hw_handoff │ └── zybo_hdmi_in_wrapper.hdf ├── repo │ └── digilent │ │ ├── ip │ │ ├── dvi2rgb_v1_6 │ │ │ ├── src │ │ │ │ ├── dvi2rgb_ooc.xdc │ │ │ │ ├── dvi2rgb.xdc │ │ │ │ ├── 1024_edid.txt │ │ │ │ ├── 1080_edid.txt │ │ │ │ ├── 720p_edid.txt │ │ │ │ └── 900p_edid.txt │ │ │ ├── docs │ │ │ │ ├── dvi2rgb.pdf │ │ │ │ ├── dvi2rgb_v1_6.docx │ │ │ │ ├── 1024_edid.dat │ │ │ │ ├── 1080_edid.dat │ │ │ │ ├── 720p_edid.dat │ │ │ │ ├── 900p_edid.dat │ │ │ │ └── dat2txt.cpp │ │ │ └── gui │ │ │ │ └── dvi2rgb_v1_0.gtcl │ │ ├── Sync_v1_0 │ │ │ ├── docs │ │ │ │ └── Sync_v1_0.pdf │ │ │ └── src │ │ │ │ └── Sync.xdc │ │ ├── rgb2vga_v1_0 │ │ │ └── docs │ │ │ │ └── rgb2vga_v1_0.pdf │ │ ├── clock_forwarder_1.0 │ │ │ ├── xgui │ │ │ │ └── clock_forwarder_v1_0.tcl │ │ │ └── hdl │ │ │ │ └── clock_forwarder_v1_0.vhd │ │ └── axi_dynclk_v1_0 │ │ │ └── xgui │ │ │ └── axi_dynclk_v1_0.tcl │ │ └── if │ │ └── tmds_v1_0 │ │ └── tmds.xml ├── sdk │ ├── fsbl_bsp │ │ ├── .sdkproject │ │ ├── .cproject │ │ └── Makefile │ ├── hello_bsp │ │ ├── .sdkproject │ │ ├── .cproject │ │ └── Makefile │ ├── zybo_hdmi_in_wrapper_hw_platform_0 │ │ ├── system.hdf │ │ └── .project │ ├── hello │ │ ├── src │ │ │ ├── platform_config.h │ │ │ └── platform.h │ │ └── .project │ └── fsbl │ │ └── .project ├── readme.txt ├── proj │ ├── cleanup.cmd │ └── cleanup.sh └── src │ └── others │ └── hw_pfm_gen.tcl └── XADC └── proj ├── cleanup.cmd └── cleanup.sh /Projects/dma/sdk/dma/src/Xilinx.spec: -------------------------------------------------------------------------------- 1 | *startfile: 2 | crti%O%s crtbegin%O%s 3 | -------------------------------------------------------------------------------- /Projects/hdmi_in/sdk/HDMI_IN/src/README.txt: -------------------------------------------------------------------------------- 1 | Empty application. Add your own sources. 2 | -------------------------------------------------------------------------------- /Projects/hdmi_out/hw_handoff/hdmi_out_wrapper.hdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Digilent/ZYBO/HEAD/Projects/hdmi_out/hw_handoff/hdmi_out_wrapper.hdf -------------------------------------------------------------------------------- /Projects/linux_bd/hw_handoff/linux_bd_wrapper.hdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Digilent/ZYBO/HEAD/Projects/linux_bd/hw_handoff/linux_bd_wrapper.hdf -------------------------------------------------------------------------------- /Projects/sdsoc/hw_handoff/zybo_hdmi_in_wrapper.hdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Digilent/ZYBO/HEAD/Projects/sdsoc/hw_handoff/zybo_hdmi_in_wrapper.hdf -------------------------------------------------------------------------------- /Projects/sdsoc/repo/digilent/ip/dvi2rgb_v1_6/src/dvi2rgb_ooc.xdc: -------------------------------------------------------------------------------- 1 | create_clock -period 6.060 [get_ports TMDS_Clk_p] 2 | create_clock -period 5.000 [get_ports RefClk] -------------------------------------------------------------------------------- /Projects/dma/sdk/design_1_wrapper_hw_platform_0/system.hdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Digilent/ZYBO/HEAD/Projects/dma/sdk/design_1_wrapper_hw_platform_0/system.hdf -------------------------------------------------------------------------------- /Projects/dma/sdk/dma_bsp/.sdkproject: -------------------------------------------------------------------------------- 1 | THIRPARTY=false 2 | HW_PROJECT_REFERENCE=design_1_wrapper_hw_platform_0 3 | PROCESSOR=ps7_cortexa9_0 4 | MSS_FILE=system.mss 5 | -------------------------------------------------------------------------------- /Projects/hdmi_in/repo/digilent/ip/dvi2rgb_v1_6/src/dvi2rgb_ooc.xdc: -------------------------------------------------------------------------------- 1 | create_clock -period 6.060 [get_ports TMDS_Clk_p] 2 | create_clock -period 5.000 [get_ports RefClk] -------------------------------------------------------------------------------- /Projects/hdmi_in/repo/digilent/ip/Sync_v1_0/docs/Sync_v1_0.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Digilent/ZYBO/HEAD/Projects/hdmi_in/repo/digilent/ip/Sync_v1_0/docs/Sync_v1_0.pdf -------------------------------------------------------------------------------- /Projects/hdmi_in/sdk/HDMI_IN_bsp/.sdkproject: -------------------------------------------------------------------------------- 1 | THIRPARTY=false 2 | HW_PROJECT_REFERENCE=hdmi_in_wrapper_hw_platform_0 3 | PROCESSOR=ps7_cortexa9_0 4 | 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create_clock -period 5.000 [get_ports RefClk] -------------------------------------------------------------------------------- /Projects/linux_bd/sdk/fsbl_bsp/.sdkproject: -------------------------------------------------------------------------------- 1 | THIRPARTY=false 2 | HW_PROJECT_REFERENCE=linux_bd_wrapper_hw_platform_0 3 | PROCESSOR=ps7_cortexa9_0 4 | MSS_FILE=system.mss 5 | -------------------------------------------------------------------------------- /Projects/sdsoc/repo/digilent/ip/Sync_v1_0/docs/Sync_v1_0.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Digilent/ZYBO/HEAD/Projects/sdsoc/repo/digilent/ip/Sync_v1_0/docs/Sync_v1_0.pdf -------------------------------------------------------------------------------- /Projects/sdsoc/repo/digilent/ip/dvi2rgb_v1_6/docs/dvi2rgb.pdf: -------------------------------------------------------------------------------- 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https://raw.githubusercontent.com/Digilent/ZYBO/HEAD/Projects/sdsoc/repo/digilent/ip/rgb2vga_v1_0/docs/rgb2vga_v1_0.pdf -------------------------------------------------------------------------------- /Projects/dma/sdk/dma/src/platform_config.h: -------------------------------------------------------------------------------- 1 | #ifndef __PLATFORM_CONFIG_H_ 2 | #define __PLATFORM_CONFIG_H_ 3 | 4 | #define STDOUT_IS_PS7_UART 5 | #define UART_DEVICE_ID 0 6 | #endif 7 | -------------------------------------------------------------------------------- /Projects/hdmi_in/repo/digilent/ip/dvi2rgb_v1_6/docs/dvi2rgb_v1_6.docx: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Digilent/ZYBO/HEAD/Projects/hdmi_in/repo/digilent/ip/dvi2rgb_v1_6/docs/dvi2rgb_v1_6.docx -------------------------------------------------------------------------------- /Projects/hdmi_in/repo/digilent/ip/rgb2vga_v1_0/docs/rgb2vga_v1_0.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Digilent/ZYBO/HEAD/Projects/hdmi_in/repo/digilent/ip/rgb2vga_v1_0/docs/rgb2vga_v1_0.pdf -------------------------------------------------------------------------------- /Projects/hdmi_out/repo/digilent/ip/rgb2dvi_v1_2/docs/rgb2dvi_v1_2.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Digilent/ZYBO/HEAD/Projects/hdmi_out/repo/digilent/ip/rgb2dvi_v1_2/docs/rgb2dvi_v1_2.pdf -------------------------------------------------------------------------------- /Projects/hdmi_out/repo/digilent/ip/rgb2dvi_v1_2/src/rgb2dvi_clocks.xdc: -------------------------------------------------------------------------------- 1 | ### Clock constraints ### 2 | create_generated_clock -source [get_ports PixelClk] -multiply_by 5 [get_ports SerialClk] -------------------------------------------------------------------------------- /Projects/linux_bd/repo/vivado-library/ip/Sync_v1_0/docs/Sync_v1_0.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Digilent/ZYBO/HEAD/Projects/linux_bd/repo/vivado-library/ip/Sync_v1_0/docs/Sync_v1_0.pdf -------------------------------------------------------------------------------- /Projects/sdsoc/sdk/hello/src/platform_config.h: -------------------------------------------------------------------------------- 1 | #ifndef __PLATFORM_CONFIG_H_ 2 | #define __PLATFORM_CONFIG_H_ 3 | 4 | #define STDOUT_IS_PS7_UART 5 | #define UART_DEVICE_ID 0 6 | #endif 7 | -------------------------------------------------------------------------------- /Projects/linux_bd/repo/vivado-library/ip/dvi2rgb_v1_6/docs/dvi2rgb.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Digilent/ZYBO/HEAD/Projects/linux_bd/repo/vivado-library/ip/dvi2rgb_v1_6/docs/dvi2rgb.pdf -------------------------------------------------------------------------------- /Projects/linux_bd/repo/vivado-library/ip/rgb2dvi/src/rgb2dvi_clocks.xdc: -------------------------------------------------------------------------------- 1 | ### Clock constraints ### 2 | create_generated_clock -source [get_ports PixelClk] -multiply_by 5 [get_ports SerialClk] -------------------------------------------------------------------------------- /Projects/linux_bd/repo/vivado-library/ip/Pmods/PmodACL_v1_0/src/PmodACL.hwdef: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Digilent/ZYBO/HEAD/Projects/linux_bd/repo/vivado-library/ip/Pmods/PmodACL_v1_0/src/PmodACL.hwdef -------------------------------------------------------------------------------- /Projects/linux_bd/repo/vivado-library/ip/Pmods/PmodALS_v1_0/src/PmodALS.hwdef: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Digilent/ZYBO/HEAD/Projects/linux_bd/repo/vivado-library/ip/Pmods/PmodALS_v1_0/src/PmodALS.hwdef -------------------------------------------------------------------------------- /Projects/linux_bd/repo/vivado-library/ip/Pmods/PmodBT2_v1_0/src/PmodBT2.hwdef: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Digilent/ZYBO/HEAD/Projects/linux_bd/repo/vivado-library/ip/Pmods/PmodBT2_v1_0/src/PmodBT2.hwdef -------------------------------------------------------------------------------- /Projects/linux_bd/repo/vivado-library/ip/Pmods/PmodGPS_v1_1/src/PmodGPS.hwdef: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Digilent/ZYBO/HEAD/Projects/linux_bd/repo/vivado-library/ip/Pmods/PmodGPS_v1_1/src/PmodGPS.hwdef -------------------------------------------------------------------------------- /Projects/linux_bd/repo/vivado-library/ip/dvi2rgb_v1_6/docs/dvi2rgb_v1_6.docx: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Digilent/ZYBO/HEAD/Projects/linux_bd/repo/vivado-library/ip/dvi2rgb_v1_6/docs/dvi2rgb_v1_6.docx -------------------------------------------------------------------------------- /Projects/linux_bd/repo/vivado-library/ip/rgb2vga_v1_0/docs/rgb2vga_v1_0.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Digilent/ZYBO/HEAD/Projects/linux_bd/repo/vivado-library/ip/rgb2vga_v1_0/docs/rgb2vga_v1_0.pdf -------------------------------------------------------------------------------- /Projects/hdmi_out/repo/digilent/ip/rgb2dvi_v1_2/src/rgb2dvi_ooc.xdc: -------------------------------------------------------------------------------- 1 | create_clock -period 6.060 [get_ports PixelClk] 2 | create_generated_clock -source [get_ports PixelClk] -multiply_by 5 [get_ports SerialClk] -------------------------------------------------------------------------------- /Projects/linux_bd/repo/vivado-library/ip/Pmods/PmodAMP2_v1_0/src/PmodAMP2.hwdef: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Digilent/ZYBO/HEAD/Projects/linux_bd/repo/vivado-library/ip/Pmods/PmodAMP2_v1_0/src/PmodAMP2.hwdef -------------------------------------------------------------------------------- /Projects/linux_bd/repo/vivado-library/ip/rgb2dpvid_v1_0/docs/rgb2dpvid_v1_0.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Digilent/ZYBO/HEAD/Projects/linux_bd/repo/vivado-library/ip/rgb2dpvid_v1_0/docs/rgb2dpvid_v1_0.pdf -------------------------------------------------------------------------------- /Projects/linux_bd/repo/vivado-library/ip/rgb2dvi/src/rgb2dvi_ooc.xdc: -------------------------------------------------------------------------------- 1 | create_clock -period 6.060 [get_ports PixelClk] 2 | create_generated_clock -source [get_ports PixelClk] -multiply_by 5 [get_ports SerialClk] -------------------------------------------------------------------------------- /Projects/linux_bd/repo/vivado-library/ip/Pmods/Pmod_Bridge_v1_0/src/pmod_concat.hwdef: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Digilent/ZYBO/HEAD/Projects/linux_bd/repo/vivado-library/ip/Pmods/Pmod_Bridge_v1_0/src/pmod_concat.hwdef -------------------------------------------------------------------------------- /Projects/linux_bd/repo/vivado-library/ip/Pmods/PmodACL_v1_0/drivers/PmodACL_v1_0/src/PmodACL.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Digilent/ZYBO/HEAD/Projects/linux_bd/repo/vivado-library/ip/Pmods/PmodACL_v1_0/drivers/PmodACL_v1_0/src/PmodACL.c -------------------------------------------------------------------------------- /Projects/linux_bd/repo/vivado-library/ip/Pmods/PmodGPS_v1_1/drivers/PmodGPS_v1_1/src/PmodGPS.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Digilent/ZYBO/HEAD/Projects/linux_bd/repo/vivado-library/ip/Pmods/PmodGPS_v1_1/drivers/PmodGPS_v1_1/src/PmodGPS.c -------------------------------------------------------------------------------- /Projects/linux_bd/repo/vivado-library/ip/Pmods/PmodGPS_v1_1/drivers/PmodGPS_v1_1/src/PmodGPS.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Digilent/ZYBO/HEAD/Projects/linux_bd/repo/vivado-library/ip/Pmods/PmodGPS_v1_1/drivers/PmodGPS_v1_1/src/PmodGPS.h -------------------------------------------------------------------------------- /Projects/linux_bd/repo/vivado-library/ip/Pmods/pmodOLEDrgb_v1_0/ip/PmodOLEDrgb_axi_gpio_0_1.xcix: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Digilent/ZYBO/HEAD/Projects/linux_bd/repo/vivado-library/ip/Pmods/pmodOLEDrgb_v1_0/ip/PmodOLEDrgb_axi_gpio_0_1.xcix -------------------------------------------------------------------------------- /Projects/linux_bd/repo/vivado-library/ip/Pmods/pmodOLEDrgb_v1_0/ip/PmodOLEDrgb_pmod_bridge_0_0.xcix: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Digilent/ZYBO/HEAD/Projects/linux_bd/repo/vivado-library/ip/Pmods/pmodOLEDrgb_v1_0/ip/PmodOLEDrgb_pmod_bridge_0_0.xcix -------------------------------------------------------------------------------- /Projects/linux_bd/repo/vivado-library/ip/Pmods/pmodOLEDrgb_v1_0/ip/PmodOLEDrgb_axi_quad_spi_0_0.xcix: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Digilent/ZYBO/HEAD/Projects/linux_bd/repo/vivado-library/ip/Pmods/pmodOLEDrgb_v1_0/ip/PmodOLEDrgb_axi_quad_spi_0_0.xcix -------------------------------------------------------------------------------- /Projects/linux_bd/repo/vivado-library/ip/PWM_1.0/drivers/PWM_v1_0/data/PWM.tcl: -------------------------------------------------------------------------------- 1 | 2 | 3 | proc generate {drv_handle} { 4 | xdefine_include_file $drv_handle "xparameters.h" "PWM" "NUM_INSTANCES" "DEVICE_ID" "C_PWM_AXI_BASEADDR" "C_PWM_AXI_HIGHADDR" 5 | } 6 | -------------------------------------------------------------------------------- /Projects/linux_bd/repo/vivado-library/ip/Pmods/pmodOLEDrgb_v1_0/drivers/PmodOLEDrgb_v1_0/src/PmodOLEDrgb.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Digilent/ZYBO/HEAD/Projects/linux_bd/repo/vivado-library/ip/Pmods/pmodOLEDrgb_v1_0/drivers/PmodOLEDrgb_v1_0/src/PmodOLEDrgb.c -------------------------------------------------------------------------------- /Projects/linux_bd/repo/vivado-library/ip/PWM_1.0/drivers/PWM_v1_0/src/PWM.c: -------------------------------------------------------------------------------- 1 | 2 | 3 | /***************************** Include Files *******************************/ 4 | #include "PWM.h" 5 | 6 | /************************** Function Definitions ***************************/ 7 | -------------------------------------------------------------------------------- /Projects/linux_bd/repo/vivado-library/ip/Pmods/PmodALS_v1_0/drivers/PmodALS_v1_0/data/PmodALS.tcl: -------------------------------------------------------------------------------- 1 | 2 | 3 | proc generate {drv_handle} { 4 | xdefine_include_file $drv_handle "xparameters.h" "PmodALS" "NUM_INSTANCES" "DEVICE_ID" "AXI_LITE_SPI_BASEADDR" "AXI_LITE_SPI_HIGHADDR" 5 | } 6 | -------------------------------------------------------------------------------- /Projects/linux_bd/repo/vivado-library/ip/PWM_1.0/drivers/PWM_v1_0/data/PWM.mdd: -------------------------------------------------------------------------------- 1 | 2 | 3 | OPTION psf_version = 2.1; 4 | 5 | BEGIN DRIVER PWM 6 | OPTION supported_peripherals = (PWM); 7 | OPTION copyfiles = all; 8 | OPTION VERSION = 1.0; 9 | OPTION NAME = PWM; 10 | END DRIVER 11 | -------------------------------------------------------------------------------- /Projects/linux_bd/repo/vivado-library/ip/axi_i2s_adi_1.2/drivers/axi_i2s_adi_v1_0/data/axi_i2s_adi.tcl: -------------------------------------------------------------------------------- 1 | 2 | 3 | proc generate {drv_handle} { 4 | xdefine_include_file $drv_handle "xparameters.h" "axi_i2s_adi" "NUM_INSTANCES" "DEVICE_ID" "C_S00_AXI_BASEADDR" "C_S00_AXI_HIGHADDR" 5 | } 6 | -------------------------------------------------------------------------------- /Projects/linux_bd/repo/vivado-library/ip/Pmods/PmodAMP2_v1_0/ipshared/digilentinc.com/pwm_v1_0/drivers/PWM_v1_0/data/PWM.tcl: -------------------------------------------------------------------------------- 1 | 2 | 3 | proc generate {drv_handle} { 4 | xdefine_include_file $drv_handle "xparameters.h" "PWM" "NUM_INSTANCES" "DEVICE_ID" "C_PWM_AXI_BASEADDR" "C_PWM_AXI_HIGHADDR" 5 | } 6 | -------------------------------------------------------------------------------- /Projects/linux_bd/repo/vivado-library/ip/axi_i2s_adi_1.2/drivers/axi_i2s_adi_v1_0/src/axi_i2s_adi.c: -------------------------------------------------------------------------------- 1 | 2 | 3 | /***************************** Include Files *******************************/ 4 | #include "axi_i2s_adi.h" 5 | 6 | /************************** Function Definitions ***************************/ 7 | -------------------------------------------------------------------------------- /Projects/linux_bd/repo/vivado-library/ip/Pmods/PmodAMP2_v1_0/drivers/PmodAMP2_v1_0/data/PmodAMP2.tcl: -------------------------------------------------------------------------------- 1 | 2 | 3 | proc generate {drv_handle} { 4 | xdefine_include_file $drv_handle "xparameters.h" "PmodAMP2" "NUM_INSTANCES" "DEVICE_ID" "PWM_AXI_BASEADDR" "PWM_AXI_HIGHADDR" "GPIO_AXI_BASEADDR" "GPIO_AXI_HIGHADDR" 5 | } 6 | -------------------------------------------------------------------------------- /Projects/linux_bd/repo/vivado-library/ip/Pmods/PmodAMP2_v1_0/ipshared/digilentinc.com/pwm_v1_0/drivers/PWM_v1_0/src/PWM.c: -------------------------------------------------------------------------------- 1 | 2 | 3 | /***************************** Include Files *******************************/ 4 | #include "PWM.h" 5 | 6 | /************************** Function Definitions ***************************/ 7 | -------------------------------------------------------------------------------- /Projects/hdmi_in/repo/digilent/ip/Sync_v1_0/src/Sync.xdc: -------------------------------------------------------------------------------- 1 | ### Asynchronous clock domain crossings ### 2 | set_false_path -through [get_pins -regexp SyncAsyncx/oSyncStages.*/(PRE|CLR)] 3 | set_false_path -through [get_pins SyncAsyncx/oSyncStages_reg[0]/D] 4 | set_false_path -through [get_pins -regexp ReRegister.iIn_q.*/(CLR|PRE)] -------------------------------------------------------------------------------- /Projects/linux_bd/repo/vivado-library/ip/Pmods/PmodACL_v1_0/drivers/PmodACL_v1_0/data/PmodACL.mdd: -------------------------------------------------------------------------------- 1 | 2 | 3 | OPTION psf_version = 2.1; 4 | 5 | BEGIN DRIVER PmodACL 6 | OPTION supported_peripherals = (PmodACL); 7 | OPTION copyfiles = all; 8 | OPTION VERSION = 1.0; 9 | OPTION NAME = PmodACL; 10 | END DRIVER 11 | -------------------------------------------------------------------------------- /Projects/linux_bd/repo/vivado-library/ip/Pmods/PmodALS_v1_0/drivers/PmodALS_v1_0/data/PmodALS.mdd: -------------------------------------------------------------------------------- 1 | 2 | 3 | OPTION psf_version = 2.1; 4 | 5 | BEGIN DRIVER PmodALS 6 | OPTION supported_peripherals = (PmodALS); 7 | OPTION copyfiles = all; 8 | OPTION VERSION = 1.0; 9 | OPTION NAME = PmodALS; 10 | END DRIVER 11 | -------------------------------------------------------------------------------- /Projects/linux_bd/repo/vivado-library/ip/Pmods/PmodBT2_v1_0/drivers/PmodBT2_v1_0/data/PmodBT2.mdd: -------------------------------------------------------------------------------- 1 | 2 | 3 | OPTION psf_version = 2.1; 4 | 5 | BEGIN DRIVER PmodBT2 6 | OPTION supported_peripherals = (PmodBT2); 7 | OPTION copyfiles = all; 8 | OPTION VERSION = 1.0; 9 | OPTION NAME = PmodBT2; 10 | END DRIVER 11 | -------------------------------------------------------------------------------- /Projects/linux_bd/repo/vivado-library/ip/Pmods/PmodGPS_v1_1/drivers/PmodGPS_v1_1/data/PmodGPS.mdd: -------------------------------------------------------------------------------- 1 | 2 | 3 | OPTION psf_version = 2.1; 4 | 5 | BEGIN DRIVER PmodGPS 6 | OPTION supported_peripherals = (PmodGPS); 7 | OPTION copyfiles = all; 8 | OPTION VERSION = 1.1; 9 | OPTION NAME = PmodGPS; 10 | END DRIVER 11 | -------------------------------------------------------------------------------- /Projects/sdsoc/repo/digilent/ip/Sync_v1_0/src/Sync.xdc: -------------------------------------------------------------------------------- 1 | ### Asynchronous clock domain crossings ### 2 | set_false_path -through [get_pins -regexp SyncAsyncx/oSyncStages.*/(PRE|CLR)] 3 | set_false_path -through [get_pins SyncAsyncx/oSyncStages_reg[0]/D] 4 | set_false_path -through [get_pins -regexp ReRegister.iIn_q.*/(CLR|PRE)] -------------------------------------------------------------------------------- /Projects/sdsoc/repo/digilent/ip/clock_forwarder_1.0/xgui/clock_forwarder_v1_0.tcl: -------------------------------------------------------------------------------- 1 | # Definitional proc to organize widgets for parameters. 2 | proc init_gui { IPINST } { 3 | ipgui::add_param $IPINST -name "Component_Name" 4 | #Adding Page 5 | ipgui::add_page $IPINST -name "Page 0" 6 | 7 | 8 | } 9 | 10 | 11 | -------------------------------------------------------------------------------- /Projects/hdmi_in/repo/digilent/ip/clock_forwarder_1.0/xgui/clock_forwarder_v1_0.tcl: -------------------------------------------------------------------------------- 1 | # Definitional proc to organize widgets for parameters. 2 | proc init_gui { IPINST } { 3 | ipgui::add_param $IPINST -name "Component_Name" 4 | #Adding Page 5 | ipgui::add_page $IPINST -name "Page 0" 6 | 7 | 8 | } 9 | 10 | 11 | -------------------------------------------------------------------------------- /Projects/linux_bd/repo/vivado-library/ip/Pmods/PmodAMP2_v1_0/drivers/PmodAMP2_v1_0/data/PmodAMP2.mdd: -------------------------------------------------------------------------------- 1 | 2 | 3 | OPTION psf_version = 2.1; 4 | 5 | BEGIN DRIVER PmodAMP2 6 | OPTION supported_peripherals = (PmodAMP2); 7 | OPTION copyfiles = all; 8 | OPTION VERSION = 1.0; 9 | OPTION NAME = PmodAMP2; 10 | END DRIVER 11 | -------------------------------------------------------------------------------- /Projects/linux_bd/repo/vivado-library/ip/Pmods/PmodACL_v1_0/drivers/PmodACL_v1_0/data/PmodACL.tcl: -------------------------------------------------------------------------------- 1 | 2 | 3 | proc generate {drv_handle} { 4 | xdefine_include_file $drv_handle "xparameters.h" "PmodACL" "NUM_INSTANCES" "DEVICE_ID" "AXI_LITE_SPI_BASEADDR" "AXI_LITE_SPI_HIGHADDR" "AXI_LITE_GPIO_BASEADDR" "AXI_LITE_GPIO_HIGHADDR" 5 | } 6 | -------------------------------------------------------------------------------- /Projects/linux_bd/repo/vivado-library/ip/Sync_v1_0/src/Sync.xdc: -------------------------------------------------------------------------------- 1 | ### Asynchronous clock domain crossings ### 2 | set_false_path -through [get_pins -regexp SyncAsyncx/oSyncStages.*/(PRE|CLR)] 3 | set_false_path -through [get_pins SyncAsyncx/oSyncStages_reg[0]/D] 4 | set_false_path -through [get_pins -regexp ReRegister.iIn_q.*/(CLR|PRE)] -------------------------------------------------------------------------------- /Projects/linux_bd/repo/vivado-library/ip/clock_forwarder_1.0/xgui/clock_forwarder_v1_0.tcl: -------------------------------------------------------------------------------- 1 | # Definitional proc to organize widgets for parameters. 2 | proc init_gui { IPINST } { 3 | ipgui::add_param $IPINST -name "Component_Name" 4 | #Adding Page 5 | ipgui::add_page $IPINST -name "Page 0" 6 | 7 | 8 | } 9 | 10 | 11 | -------------------------------------------------------------------------------- /Projects/linux_bd/repo/vivado-library/ip/Pmods/PmodAMP2_v1_0/ipshared/digilentinc.com/pwm_v1_0/drivers/PWM_v1_0/data/PWM.mdd: -------------------------------------------------------------------------------- 1 | 2 | 3 | OPTION psf_version = 2.1; 4 | 5 | BEGIN DRIVER PWM 6 | OPTION supported_peripherals = (PWM); 7 | OPTION copyfiles = all; 8 | OPTION VERSION = 1.0; 9 | OPTION NAME = PWM; 10 | END DRIVER 11 | -------------------------------------------------------------------------------- /Projects/linux_bd/repo/vivado-library/ip/Pmods/PmodGPS_v1_1/drivers/PmodGPS_v1_1/data/PmodGPS.tcl: -------------------------------------------------------------------------------- 1 | 2 | 3 | proc generate {drv_handle} { 4 | xdefine_include_file $drv_handle "xparameters.h" "PmodGPS" "NUM_INSTANCES" "DEVICE_ID" "AXI_LITE_UART_BASEADDR" "AXI_LITE_UART_HIGHADDR" "AXI_LITE_GPIO_BASEADDR" "AXI_LITE_GPIO_HIGHADDR" 5 | } 6 | -------------------------------------------------------------------------------- /Projects/linux_bd/repo/vivado-library/ip/axi_i2s_adi_1.2/drivers/axi_i2s_adi_v1_0/data/axi_i2s_adi.mdd: -------------------------------------------------------------------------------- 1 | 2 | 3 | OPTION psf_version = 2.1; 4 | 5 | BEGIN DRIVER axi_i2s_adi 6 | OPTION supported_peripherals = (axi_i2s_adi); 7 | OPTION copyfiles = all; 8 | OPTION VERSION = 1.0; 9 | OPTION NAME = axi_i2s_adi; 10 | END DRIVER 11 | -------------------------------------------------------------------------------- /Projects/linux_bd/repo/vivado-library/ip/Pmods/pmodOLEDrgb_v1_0/drivers/PmodOLEDrgb_v1_0/data/PmodOLEDrgb.mdd: -------------------------------------------------------------------------------- 1 | 2 | 3 | OPTION psf_version = 2.1; 4 | 5 | BEGIN DRIVER PmodOLEDrgb 6 | OPTION supported_peripherals = (PmodOLEDrgb); 7 | OPTION copyfiles = all; 8 | OPTION VERSION = 1.0; 9 | OPTION NAME = PmodOLEDrgb; 10 | END DRIVER 11 | -------------------------------------------------------------------------------- /Projects/linux_bd/repo/vivado-library/ip/Pmods/pmodOLEDrgb_v1_0/drivers/PmodOLEDrgb_v1_0/data/PmodOLEDrgb.tcl: -------------------------------------------------------------------------------- 1 | 2 | 3 | proc generate {drv_handle} { 4 | xdefine_include_file $drv_handle "xparameters.h" "PmodOLEDrgb" "NUM_INSTANCES" "DEVICE_ID" "C_AXI_LITE_GPIO_BASEADDR" "C_AXI_LITE_GPIO_HIGHADDR" "C_AXI_LITE_SPI_BASEADDR" "C_AXI_LITE_SPI_HIGHADDR" 5 | } 6 | -------------------------------------------------------------------------------- /Projects/hdmi_out/repo/digilent/ip/rgb2dvi_v1_2/src/rgb2dvi.xdc: -------------------------------------------------------------------------------- 1 | ### Clock constraints ### 2 | 3 | ### Asynchronous clock domain crossings ### 4 | set_false_path -through [get_pins -filter {NAME =~ */SyncAsync*/oSyncStages*/PRE || NAME =~ */SyncAsync*/oSyncStages*/CLR} -hier] 5 | set_false_path -through [get_pins -filter {NAME =~ *SyncAsync*/oSyncStages_reg[0]/D} -hier] -------------------------------------------------------------------------------- /Projects/linux_bd/repo/vivado-library/ip/rgb2dvi/src/rgb2dvi.xdc: -------------------------------------------------------------------------------- 1 | ### Clock constraints ### 2 | 3 | ### Asynchronous clock domain crossings ### 4 | set_false_path -through [get_pins -filter {NAME =~ */SyncAsync*/oSyncStages*/PRE || NAME =~ */SyncAsync*/oSyncStages*/CLR} -hier] 5 | set_false_path -through [get_pins -filter {NAME =~ *SyncAsync*/oSyncStages_reg[0]/D} -hier] -------------------------------------------------------------------------------- /Projects/linux_bd/repo/vivado-library/ip/Pmods/PmodBT2_v1_0/drivers/PmodBT2_v1_0/data/PmodBT2.tcl: -------------------------------------------------------------------------------- 1 | 2 | 3 | proc generate {drv_handle} { 4 | xdefine_include_file $drv_handle "xparameters.h" "PmodBT2" "NUM_INSTANCES" "DEVICE_ID" "AXI_LITE_SPI_BASEADDR" "AXI_LITE_SPI_HIGHADDR" "AXI_LITE_GPIO_BASEADDR" "AXI_LITE_GPIO_HIGHADDR" "AXI_LITE_UART_BASEADDR" "AXI_LITE_UART_HIGHADDR" 5 | } 6 | -------------------------------------------------------------------------------- /Projects/dma/repo/local/ip/d_axi_i2s_audio_v2_0/src/d_axi_i2s_audio.xdc: -------------------------------------------------------------------------------- 1 | set_false_path -through [get_pins -filter {NAME =~ */Inst_I2sCtl/Inst_SyncBit_*/sreg_reg[0]/D} -hier] 2 | set_false_path -through [get_pins -filter {NAME =~ */Inst_I2sCtl/Inst_Rst_Sync*/FDRE_inst_*/PRE} -hier] 3 | 4 | set_property ASYNC_REG true [get_cells -filter {NAME =~ */Inst_I2sCtl/Inst_Rst_Sync*} -hier] 5 | 6 | 7 | -------------------------------------------------------------------------------- /Projects/sdsoc/readme.txt: -------------------------------------------------------------------------------- 1 | 2 | This project is used by the zybo_hdmi_in SDSoC platform. It is version 3 | controlled here, but not meant to be used as a reference project, so 4 | no wiki documentation or tutorials will be created for it. If you would 5 | like to use the zybo_hdmi_in SDSoC platform, please goto the following 6 | site for instructions: 7 | 8 | https://reference.digilentinc.com/vivado:sdsoc 9 | 10 | 11 | 12 | -------------------------------------------------------------------------------- /Projects/hdmi_out/proj/cleanup.cmd: -------------------------------------------------------------------------------- 1 | @echo off 2 | rem delete all files from subfolders 3 | for /d /r %%i in (*) do del /f /q %%i\* 4 | rem delete all subfolders 5 | for /d %%i in (*) do rd /S /Q %%i 6 | 7 | rem unmark read only from all files 8 | attrib -R .\* /S 9 | 10 | rem mark read only those we wish to keep 11 | attrib +R .\create_project.tcl 12 | attrib +R .\cleanup.sh 13 | attrib +R .\cleanup.cmd 14 | attrib +R .\.gitignore 15 | 16 | rem delete all non read-only 17 | del /Q /A:-R .\* 18 | 19 | rem unmark read-only 20 | attrib -R .\* 21 | 22 | -------------------------------------------------------------------------------- /Projects/linux_bd/proj/cleanup.cmd: -------------------------------------------------------------------------------- 1 | @echo off 2 | rem delete all files from subfolders 3 | for /d /r %%i in (*) do del /f /q %%i\* 4 | rem delete all subfolders 5 | for /d %%i in (*) do rd /S /Q %%i 6 | 7 | rem unmark read only from all files 8 | attrib -R .\* /S 9 | 10 | rem mark read only those we wish to keep 11 | attrib +R .\create_project.tcl 12 | attrib +R .\cleanup.sh 13 | attrib +R .\cleanup.cmd 14 | attrib +R .\.gitignore 15 | 16 | rem delete all non read-only 17 | del /Q /A:-R .\* 18 | 19 | rem unmark read-only 20 | attrib -R .\* 21 | 22 | -------------------------------------------------------------------------------- /Projects/sdsoc/proj/cleanup.cmd: -------------------------------------------------------------------------------- 1 | @echo off 2 | rem delete all files from subfolders 3 | for /d /r %%i in (*) do del /f /q %%i\* 4 | rem delete all subfolders 5 | for /d %%i in (*) do rd /S /Q %%i 6 | 7 | rem unmark read only from all files 8 | attrib -R .\* /S 9 | 10 | rem mark read only those we wish to keep 11 | attrib +R .\create_project.tcl 12 | attrib +R .\cleanup.sh 13 | attrib +R .\cleanup.cmd 14 | attrib +R .\.gitignore 15 | 16 | rem delete all non read-only 17 | del /Q /A:-R .\* 18 | 19 | rem unmark read-only 20 | attrib -R .\* 21 | 22 | -------------------------------------------------------------------------------- /Projects/dma/proj/cleanup.cmd: -------------------------------------------------------------------------------- 1 | @echo off 2 | rem delete all files from subfolders 3 | for /d /r %%i in (*) do del /f /q %%i\* 4 | rem delete all subfolders 5 | for /d %%i in (*) do rd /S /Q %%i 6 | 7 | rem unmark read only from all files 8 | attrib -R .\* /S 9 | 10 | rem mark read only those we wish to keep 11 | attrib +R .\create_project.tcl 12 | attrib +R .\cleanup.sh 13 | attrib +R .\cleanup.cmd 14 | attrib +R .\.gitignore 15 | attrib +R .\_READ_ME_.txt 16 | 17 | rem delete all non read-only 18 | del /Q /A:-R .\* 19 | 20 | rem unmark read-only 21 | attrib -R .\* 22 | -------------------------------------------------------------------------------- /Projects/XADC/proj/cleanup.cmd: -------------------------------------------------------------------------------- 1 | @echo off 2 | rem delete all files from subfolders 3 | for /d /r %%i in (*) do del /f /q %%i\* 4 | rem delete all subfolders 5 | for /d %%i in (*) do rd /S /Q %%i 6 | 7 | rem unmark read only from all files 8 | attrib -R .\* /S 9 | 10 | rem mark read only those we wish to keep 11 | attrib +R .\create_project.tcl 12 | attrib +R .\cleanup.sh 13 | attrib +R .\cleanup.cmd 14 | attrib +R .\.gitignore 15 | attrib +R .\_READ_ME_.txt 16 | 17 | rem delete all non read-only 18 | del /Q /A:-R .\* 19 | 20 | rem unmark read-only 21 | attrib -R .\* 22 | -------------------------------------------------------------------------------- /Projects/hdmi_in/proj/cleanup.cmd: -------------------------------------------------------------------------------- 1 | @echo off 2 | rem delete all files from subfolders 3 | for /d /r %%i in (*) do del /f /q %%i\* 4 | rem delete all subfolders 5 | for /d %%i in (*) do rd /S /Q %%i 6 | 7 | rem unmark read only from all files 8 | attrib -R .\* /S 9 | 10 | rem mark read only those we wish to keep 11 | attrib +R .\create_project.tcl 12 | attrib +R .\cleanup.sh 13 | attrib +R .\cleanup.cmd 14 | attrib +R .\.gitignore 15 | attrib +R .\_READ_ME_.txt 16 | 17 | rem delete all non read-only 18 | del /Q /A:-R .\* 19 | 20 | rem unmark read-only 21 | attrib -R .\* 22 | -------------------------------------------------------------------------------- /Projects/XADC/proj/cleanup.sh: -------------------------------------------------------------------------------- 1 | # This script is useful for cleaning up the 'project' 2 | # directory of a Digilent Vivado-project git repository 3 | ### 4 | # Run the following command to change permissions of 5 | # this 'cleanup' file if needed: 6 | # chmod u+x cleanup.sh 7 | ### 8 | # Remove directories/subdirectories 9 | find . -mindepth 1 -type d -exec rm -rf {} + 10 | # Remove any other files than: 11 | find . -type f ! -name 'cleanup.sh' \ 12 | ! -name 'cleanup.cmd' \ 13 | ! -name 'create_project.tcl' \ 14 | ! -name '.gitignore' \ 15 | -exec rm -rf {} + 16 | -------------------------------------------------------------------------------- /Projects/dma/proj/cleanup.sh: -------------------------------------------------------------------------------- 1 | # This script is useful for cleaning up the 'project' 2 | # directory of a Digilent Vivado-project git repository 3 | ### 4 | # Run the following command to change permissions of 5 | # this 'cleanup' file if needed: 6 | # chmod u+x cleanup.sh 7 | ### 8 | # Remove directories/subdirectories 9 | find . -mindepth 1 -type d -exec rm -rf {} + 10 | # Remove any other files than: 11 | find . -type f ! -name 'cleanup.sh' \ 12 | ! -name 'cleanup.cmd' \ 13 | ! -name 'create_project.tcl' \ 14 | ! -name '.gitignore' \ 15 | -exec rm -rf {} + 16 | -------------------------------------------------------------------------------- /Projects/hdmi_in/proj/cleanup.sh: -------------------------------------------------------------------------------- 1 | # This script is useful for cleaning up the 'project' 2 | # directory of a Digilent Vivado-project git repository 3 | ### 4 | # Run the following command to change permissions of 5 | # this 'cleanup' file if needed: 6 | # chmod u+x cleanup.sh 7 | ### 8 | # Remove directories/subdirectories 9 | find . -mindepth 1 -type d -exec rm -rf {} + 10 | # Remove any other files than: 11 | find . -type f ! -name 'cleanup.sh' \ 12 | ! -name 'cleanup.cmd' \ 13 | ! -name 'create_project.tcl' \ 14 | ! -name '.gitignore' \ 15 | -exec rm -rf {} + 16 | -------------------------------------------------------------------------------- /Projects/hdmi_out/proj/cleanup.sh: -------------------------------------------------------------------------------- 1 | # This script is useful for cleaning up the 'project' 2 | # directory of a Digilent Vivado-project git repository 3 | ### 4 | # Run the following command to change permissions of 5 | # this 'cleanup' file if needed: 6 | # chmod u+x cleanup.sh 7 | ### 8 | # Remove directories/subdirectories 9 | find . -mindepth 1 -type d -exec rm -rf {} + 10 | # Remove any other files than: 11 | find . -type f ! -name 'cleanup.sh' \ 12 | ! -name 'cleanup.cmd' \ 13 | ! -name 'create_project.tcl' \ 14 | ! -name '.gitignore' \ 15 | -exec rm -rf {} + 16 | -------------------------------------------------------------------------------- /Projects/linux_bd/proj/cleanup.sh: -------------------------------------------------------------------------------- 1 | # This script is useful for cleaning up the 'project' 2 | # directory of a Digilent Vivado-project git repository 3 | ### 4 | # Run the following command to change permissions of 5 | # this 'cleanup' file if needed: 6 | # chmod u+x cleanup.sh 7 | ### 8 | # Remove directories/subdirectories 9 | find . -mindepth 1 -type d -exec rm -rf {} + 10 | # Remove any other files than: 11 | find . -type f ! -name 'cleanup.sh' \ 12 | ! -name 'cleanup.cmd' \ 13 | ! -name 'create_project.tcl' \ 14 | ! -name '.gitignore' \ 15 | -exec rm -rf {} + 16 | -------------------------------------------------------------------------------- /Projects/sdsoc/proj/cleanup.sh: -------------------------------------------------------------------------------- 1 | # This script is useful for cleaning up the 'project' 2 | # directory of a Digilent Vivado-project git repository 3 | ### 4 | # Run the following command to change permissions of 5 | # this 'cleanup' file if needed: 6 | # chmod u+x cleanup.sh 7 | ### 8 | # Remove directories/subdirectories 9 | find . -mindepth 1 -type d -exec rm -rf {} + 10 | # Remove any other files than: 11 | find . -type f ! -name 'cleanup.sh' \ 12 | ! -name 'cleanup.cmd' \ 13 | ! -name 'create_project.tcl' \ 14 | ! -name '.gitignore' \ 15 | -exec rm -rf {} + 16 | -------------------------------------------------------------------------------- /Projects/dma/sdk/dma/src/dma/dma.h: -------------------------------------------------------------------------------- 1 | /* 2 | * dma.h 3 | * 4 | * Created on: Jan 20, 2015 5 | * Author: ROHegbeC 6 | */ 7 | 8 | #ifndef DMA_H_ 9 | #define DMA_H_ 10 | 11 | #include "xparameters.h" 12 | #include "xil_printf.h" 13 | #include "xaxidma.h" 14 | 15 | /************************** Variable Definitions *****************************/ 16 | 17 | 18 | /************************** Function Definitions *****************************/ 19 | 20 | void fnS2MMInterruptHandler (void *Callback); 21 | void fnMM2SInterruptHandler (void *Callback); 22 | XStatus fnConfigDma(XAxiDma *AxiDma); 23 | 24 | #endif /* DMA_H_ */ 25 | -------------------------------------------------------------------------------- /Projects/linux_bd/repo/vivado-library/ip/PWM_1.0/drivers/PWM_v1_0/src/Makefile: -------------------------------------------------------------------------------- 1 | COMPILER= 2 | ARCHIVER= 3 | CP=cp 4 | COMPILER_FLAGS= 5 | EXTRA_COMPILER_FLAGS= 6 | LIB=libxil.a 7 | 8 | RELEASEDIR=../../../lib 9 | INCLUDEDIR=../../../include 10 | INCLUDES=-I./. -I${INCLUDEDIR} 11 | 12 | INCLUDEFILES=*.h 13 | LIBSOURCES=*.c 14 | OUTS = *.o 15 | 16 | libs: 17 | echo "Compiling PWM..." 18 | $(COMPILER) $(COMPILER_FLAGS) $(EXTRA_COMPILER_FLAGS) $(INCLUDES) $(LIBSOURCES) 19 | $(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OUTS} 20 | make clean 21 | 22 | include: 23 | ${CP} $(INCLUDEFILES) $(INCLUDEDIR) 24 | 25 | clean: 26 | rm -rf ${OUTS} 27 | -------------------------------------------------------------------------------- /Projects/hdmi_in/repo/digilent/ip/dvi2rgb_v1_6/docs/1024_edid.dat: -------------------------------------------------------------------------------- 1 | EDID BYTES: 2 | 0x 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 3 | ------------------------------------------------ 4 | 00 | 00 FF FF FF FF FF FF 00 10 EC 00 00 00 00 00 00 5 | 10 | 02 1A 01 03 A1 33 1D 78 0A EC 18 A3 54 46 98 25 6 | 20 | 0F 48 4C 21 08 00 B3 00 D1 C0 81 80 81 C0 A9 C0 7 | 30 | 01 01 01 01 01 01 30 2A 00 98 51 00 2A 40 30 70 8 | 40 | 13 00 00 00 54 00 00 1E 00 00 00 FC 20 44 69 67 9 | 50 | 69 6C 65 6E 74 44 56 49 2D 30 00 00 00 10 00 00 10 | 60 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 10 11 | 70 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 3A 12 | -------------------------------------------------------------------------------- /Projects/hdmi_in/repo/digilent/ip/dvi2rgb_v1_6/docs/1080_edid.dat: -------------------------------------------------------------------------------- 1 | EDID BYTES: 2 | 0x 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 3 | ------------------------------------------------ 4 | 00 | 00 FF FF FF FF FF FF 00 10 EC 03 00 00 00 00 00 5 | 10 | 02 1A 01 03 A1 33 1D 78 0A EC 18 A3 54 46 98 25 6 | 20 | 0F 48 4C 21 08 00 B3 00 D1 C0 81 80 81 C0 A9 C0 7 | 30 | 01 01 01 01 01 01 02 3A 80 18 71 38 2D 40 58 2C 8 | 40 | 45 00 80 38 74 00 00 1E 00 00 00 FC 20 44 69 67 9 | 50 | 69 6C 65 6E 74 44 56 49 2D 33 00 00 00 10 00 00 10 | 60 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 10 11 | 70 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 09 12 | -------------------------------------------------------------------------------- /Projects/hdmi_in/repo/digilent/ip/dvi2rgb_v1_6/docs/720p_edid.dat: -------------------------------------------------------------------------------- 1 | EDID BYTES: 2 | 0x 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 3 | ------------------------------------------------ 4 | 00 | 00 FF FF FF FF FF FF 00 10 EC 02 00 00 00 00 00 5 | 10 | 02 1A 01 03 A1 33 1D 78 0A EC 18 A3 54 46 98 25 6 | 20 | 0F 48 4C 21 08 00 B3 00 D1 C0 81 80 81 C0 A9 C0 7 | 30 | 01 01 01 01 01 01 01 1D 00 72 51 D0 1E 20 6E 28 8 | 40 | 55 00 00 D0 52 00 00 1E 00 00 00 FC 20 44 69 67 9 | 50 | 69 6C 65 6E 74 44 56 49 2D 32 00 00 00 10 00 00 10 | 60 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 10 11 | 70 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 EE 12 | -------------------------------------------------------------------------------- /Projects/hdmi_in/repo/digilent/ip/dvi2rgb_v1_6/docs/900p_edid.dat: -------------------------------------------------------------------------------- 1 | EDID BYTES: 2 | 0x 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 3 | ------------------------------------------------ 4 | 00 | 00 FF FF FF FF FF FF 00 10 EC 01 00 00 00 00 00 5 | 10 | 02 1A 01 03 A1 33 1D 78 0A EC 18 A3 54 46 98 25 6 | 20 | 0F 48 4C 21 08 00 B3 00 D1 C0 81 80 81 C0 A9 C0 7 | 30 | 01 01 01 01 01 01 2F 26 40 A0 60 84 1A 30 30 20 8 | 40 | 35 00 00 84 53 00 00 1A 00 00 00 FC 20 44 69 67 9 | 50 | 69 6C 65 6E 74 44 56 49 2D 31 00 00 00 10 00 00 10 | 60 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 10 11 | 70 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 31 12 | -------------------------------------------------------------------------------- /Projects/sdsoc/repo/digilent/ip/dvi2rgb_v1_6/docs/1024_edid.dat: -------------------------------------------------------------------------------- 1 | EDID BYTES: 2 | 0x 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 3 | ------------------------------------------------ 4 | 00 | 00 FF FF FF FF FF FF 00 10 EC 00 00 00 00 00 00 5 | 10 | 02 1A 01 03 A1 33 1D 78 0A EC 18 A3 54 46 98 25 6 | 20 | 0F 48 4C 21 08 00 B3 00 D1 C0 81 80 81 C0 A9 C0 7 | 30 | 01 01 01 01 01 01 30 2A 00 98 51 00 2A 40 30 70 8 | 40 | 13 00 00 00 54 00 00 1E 00 00 00 FC 20 44 69 67 9 | 50 | 69 6C 65 6E 74 44 56 49 2D 30 00 00 00 10 00 00 10 | 60 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 10 11 | 70 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 3A 12 | -------------------------------------------------------------------------------- /Projects/sdsoc/repo/digilent/ip/dvi2rgb_v1_6/docs/1080_edid.dat: -------------------------------------------------------------------------------- 1 | EDID BYTES: 2 | 0x 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 3 | ------------------------------------------------ 4 | 00 | 00 FF FF FF FF FF FF 00 10 EC 03 00 00 00 00 00 5 | 10 | 02 1A 01 03 A1 33 1D 78 0A EC 18 A3 54 46 98 25 6 | 20 | 0F 48 4C 21 08 00 B3 00 D1 C0 81 80 81 C0 A9 C0 7 | 30 | 01 01 01 01 01 01 02 3A 80 18 71 38 2D 40 58 2C 8 | 40 | 45 00 80 38 74 00 00 1E 00 00 00 FC 20 44 69 67 9 | 50 | 69 6C 65 6E 74 44 56 49 2D 33 00 00 00 10 00 00 10 | 60 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 10 11 | 70 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 09 12 | -------------------------------------------------------------------------------- /Projects/sdsoc/repo/digilent/ip/dvi2rgb_v1_6/docs/720p_edid.dat: -------------------------------------------------------------------------------- 1 | EDID BYTES: 2 | 0x 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 3 | ------------------------------------------------ 4 | 00 | 00 FF FF FF FF FF FF 00 10 EC 02 00 00 00 00 00 5 | 10 | 02 1A 01 03 A1 33 1D 78 0A EC 18 A3 54 46 98 25 6 | 20 | 0F 48 4C 21 08 00 B3 00 D1 C0 81 80 81 C0 A9 C0 7 | 30 | 01 01 01 01 01 01 01 1D 00 72 51 D0 1E 20 6E 28 8 | 40 | 55 00 00 D0 52 00 00 1E 00 00 00 FC 20 44 69 67 9 | 50 | 69 6C 65 6E 74 44 56 49 2D 32 00 00 00 10 00 00 10 | 60 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 10 11 | 70 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 EE 12 | -------------------------------------------------------------------------------- /Projects/sdsoc/repo/digilent/ip/dvi2rgb_v1_6/docs/900p_edid.dat: -------------------------------------------------------------------------------- 1 | EDID BYTES: 2 | 0x 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 3 | ------------------------------------------------ 4 | 00 | 00 FF FF FF FF FF FF 00 10 EC 01 00 00 00 00 00 5 | 10 | 02 1A 01 03 A1 33 1D 78 0A EC 18 A3 54 46 98 25 6 | 20 | 0F 48 4C 21 08 00 B3 00 D1 C0 81 80 81 C0 A9 C0 7 | 30 | 01 01 01 01 01 01 2F 26 40 A0 60 84 1A 30 30 20 8 | 40 | 35 00 00 84 53 00 00 1A 00 00 00 FC 20 44 69 67 9 | 50 | 69 6C 65 6E 74 44 56 49 2D 31 00 00 00 10 00 00 10 | 60 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 10 11 | 70 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 31 12 | -------------------------------------------------------------------------------- /Projects/linux_bd/repo/vivado-library/ip/dvi2rgb_v1_6/docs/1024_edid.dat: -------------------------------------------------------------------------------- 1 | EDID BYTES: 2 | 0x 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 3 | ------------------------------------------------ 4 | 00 | 00 FF FF FF FF FF FF 00 10 EC 00 00 00 00 00 00 5 | 10 | 02 1A 01 03 A1 33 1D 78 0A EC 18 A3 54 46 98 25 6 | 20 | 0F 48 4C 21 08 00 B3 00 D1 C0 81 80 81 C0 A9 C0 7 | 30 | 01 01 01 01 01 01 30 2A 00 98 51 00 2A 40 30 70 8 | 40 | 13 00 00 00 54 00 00 1E 00 00 00 FC 20 44 69 67 9 | 50 | 69 6C 65 6E 74 44 56 49 2D 30 00 00 00 10 00 00 10 | 60 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 10 11 | 70 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 3A 12 | -------------------------------------------------------------------------------- /Projects/linux_bd/repo/vivado-library/ip/dvi2rgb_v1_6/docs/1080_edid.dat: -------------------------------------------------------------------------------- 1 | EDID BYTES: 2 | 0x 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 3 | ------------------------------------------------ 4 | 00 | 00 FF FF FF FF FF FF 00 10 EC 03 00 00 00 00 00 5 | 10 | 02 1A 01 03 A1 33 1D 78 0A EC 18 A3 54 46 98 25 6 | 20 | 0F 48 4C 21 08 00 B3 00 D1 C0 81 80 81 C0 A9 C0 7 | 30 | 01 01 01 01 01 01 02 3A 80 18 71 38 2D 40 58 2C 8 | 40 | 45 00 80 38 74 00 00 1E 00 00 00 FC 20 44 69 67 9 | 50 | 69 6C 65 6E 74 44 56 49 2D 33 00 00 00 10 00 00 10 | 60 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 10 11 | 70 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 09 12 | -------------------------------------------------------------------------------- /Projects/linux_bd/repo/vivado-library/ip/dvi2rgb_v1_6/docs/720p_edid.dat: -------------------------------------------------------------------------------- 1 | EDID BYTES: 2 | 0x 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 3 | ------------------------------------------------ 4 | 00 | 00 FF FF FF FF FF FF 00 10 EC 02 00 00 00 00 00 5 | 10 | 02 1A 01 03 A1 33 1D 78 0A EC 18 A3 54 46 98 25 6 | 20 | 0F 48 4C 21 08 00 B3 00 D1 C0 81 80 81 C0 A9 C0 7 | 30 | 01 01 01 01 01 01 01 1D 00 72 51 D0 1E 20 6E 28 8 | 40 | 55 00 00 D0 52 00 00 1E 00 00 00 FC 20 44 69 67 9 | 50 | 69 6C 65 6E 74 44 56 49 2D 32 00 00 00 10 00 00 10 | 60 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 10 11 | 70 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 EE 12 | -------------------------------------------------------------------------------- /Projects/linux_bd/repo/vivado-library/ip/dvi2rgb_v1_6/docs/900p_edid.dat: -------------------------------------------------------------------------------- 1 | EDID BYTES: 2 | 0x 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 3 | ------------------------------------------------ 4 | 00 | 00 FF FF FF FF FF FF 00 10 EC 01 00 00 00 00 00 5 | 10 | 02 1A 01 03 A1 33 1D 78 0A EC 18 A3 54 46 98 25 6 | 20 | 0F 48 4C 21 08 00 B3 00 D1 C0 81 80 81 C0 A9 C0 7 | 30 | 01 01 01 01 01 01 2F 26 40 A0 60 84 1A 30 30 20 8 | 40 | 35 00 00 84 53 00 00 1A 00 00 00 FC 20 44 69 67 9 | 50 | 69 6C 65 6E 74 44 56 49 2D 31 00 00 00 10 00 00 10 | 60 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 10 11 | 70 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 31 12 | -------------------------------------------------------------------------------- /Projects/linux_bd/repo/vivado-library/ip/Pmods/PmodACL_v1_0/drivers/PmodACL_v1_0/src/Makefile: -------------------------------------------------------------------------------- 1 | COMPILER= 2 | ARCHIVER= 3 | CP=cp 4 | COMPILER_FLAGS= 5 | EXTRA_COMPILER_FLAGS= 6 | LIB=libxil.a 7 | 8 | RELEASEDIR=../../../lib 9 | INCLUDEDIR=../../../include 10 | INCLUDES=-I./. -I${INCLUDEDIR} 11 | 12 | INCLUDEFILES=*.h 13 | LIBSOURCES=*.c 14 | OUTS = *.o 15 | 16 | libs: 17 | echo "Compiling PmodGPS..." 18 | $(COMPILER) $(COMPILER_FLAGS) $(EXTRA_COMPILER_FLAGS) $(INCLUDES) $(LIBSOURCES) 19 | $(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OUTS} 20 | make clean 21 | 22 | include: 23 | ${CP} $(INCLUDEFILES) $(INCLUDEDIR) 24 | 25 | clean: 26 | rm -rf ${OUTS} 27 | -------------------------------------------------------------------------------- /Projects/linux_bd/repo/vivado-library/ip/Pmods/PmodALS_v1_0/drivers/PmodALS_v1_0/src/Makefile: -------------------------------------------------------------------------------- 1 | COMPILER= 2 | ARCHIVER= 3 | CP=cp 4 | COMPILER_FLAGS= 5 | EXTRA_COMPILER_FLAGS= 6 | LIB=libxil.a 7 | 8 | RELEASEDIR=../../../lib 9 | INCLUDEDIR=../../../include 10 | INCLUDES=-I./. -I${INCLUDEDIR} 11 | 12 | INCLUDEFILES=*.h 13 | LIBSOURCES=*.c 14 | OUTS = *.o 15 | 16 | libs: 17 | echo "Compiling PmodGPS..." 18 | $(COMPILER) $(COMPILER_FLAGS) $(EXTRA_COMPILER_FLAGS) $(INCLUDES) $(LIBSOURCES) 19 | $(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OUTS} 20 | make clean 21 | 22 | include: 23 | ${CP} $(INCLUDEFILES) $(INCLUDEDIR) 24 | 25 | clean: 26 | rm -rf ${OUTS} 27 | -------------------------------------------------------------------------------- /Projects/linux_bd/repo/vivado-library/ip/Pmods/PmodAMP2_v1_0/drivers/PmodAMP2_v1_0/src/Makefile: -------------------------------------------------------------------------------- 1 | COMPILER= 2 | ARCHIVER= 3 | CP=cp 4 | COMPILER_FLAGS= 5 | EXTRA_COMPILER_FLAGS= 6 | LIB=libxil.a 7 | 8 | RELEASEDIR=../../../lib 9 | INCLUDEDIR=../../../include 10 | INCLUDES=-I./. -I${INCLUDEDIR} 11 | 12 | INCLUDEFILES=*.h 13 | LIBSOURCES=*.c 14 | OUTS = *.o 15 | 16 | libs: 17 | echo "Compiling PmodGPS..." 18 | $(COMPILER) $(COMPILER_FLAGS) $(EXTRA_COMPILER_FLAGS) $(INCLUDES) $(LIBSOURCES) 19 | $(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OUTS} 20 | make clean 21 | 22 | include: 23 | ${CP} $(INCLUDEFILES) $(INCLUDEDIR) 24 | 25 | clean: 26 | rm -rf ${OUTS} 27 | -------------------------------------------------------------------------------- /Projects/linux_bd/repo/vivado-library/ip/Pmods/PmodBT2_v1_0/drivers/PmodBT2_v1_0/src/Makefile: -------------------------------------------------------------------------------- 1 | COMPILER= 2 | ARCHIVER= 3 | CP=cp 4 | COMPILER_FLAGS= 5 | EXTRA_COMPILER_FLAGS= 6 | LIB=libxil.a 7 | 8 | RELEASEDIR=../../../lib 9 | INCLUDEDIR=../../../include 10 | INCLUDES=-I./. -I${INCLUDEDIR} 11 | 12 | INCLUDEFILES=*.h 13 | LIBSOURCES=*.c 14 | OUTS = *.o 15 | 16 | libs: 17 | echo "Compiling PmodGPS..." 18 | $(COMPILER) $(COMPILER_FLAGS) $(EXTRA_COMPILER_FLAGS) $(INCLUDES) $(LIBSOURCES) 19 | $(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OUTS} 20 | make clean 21 | 22 | include: 23 | ${CP} $(INCLUDEFILES) $(INCLUDEDIR) 24 | 25 | clean: 26 | rm -rf ${OUTS} 27 | -------------------------------------------------------------------------------- /Projects/linux_bd/repo/vivado-library/ip/Pmods/PmodGPS_v1_1/drivers/PmodGPS_v1_1/src/Makefile: -------------------------------------------------------------------------------- 1 | COMPILER= 2 | ARCHIVER= 3 | CP=cp 4 | COMPILER_FLAGS= 5 | EXTRA_COMPILER_FLAGS= 6 | LIB=libxil.a 7 | 8 | RELEASEDIR=../../../lib 9 | INCLUDEDIR=../../../include 10 | INCLUDES=-I./. -I${INCLUDEDIR} 11 | 12 | INCLUDEFILES=*.h 13 | LIBSOURCES=*.c 14 | OUTS = *.o 15 | 16 | libs: 17 | echo "Compiling PmodGPS..." 18 | $(COMPILER) $(COMPILER_FLAGS) $(EXTRA_COMPILER_FLAGS) $(INCLUDES) $(LIBSOURCES) 19 | $(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OUTS} 20 | make clean 21 | 22 | include: 23 | ${CP} $(INCLUDEFILES) $(INCLUDEDIR) 24 | 25 | clean: 26 | rm -rf ${OUTS} 27 | -------------------------------------------------------------------------------- /Projects/linux_bd/repo/vivado-library/ip/Pmods/Pmod_Bridge_v1_0/src/pmod_concat_ooc.xdc: -------------------------------------------------------------------------------- 1 | ################################################################################ 2 | 3 | # This XDC is used only for OOC mode of synthesis, implementation 4 | # This constraints file contains default clock frequencies to be used during 5 | # out-of-context flows such as OOC Synthesis and Hierarchical Designs. 6 | # This constraints file is not used in normal top-down synthesis (default flow 7 | # of Vivado) 8 | ################################################################################ 9 | 10 | ################################################################################ -------------------------------------------------------------------------------- /Projects/linux_bd/repo/vivado-library/ip/axi_i2s_adi_1.2/drivers/axi_i2s_adi_v1_0/src/Makefile: -------------------------------------------------------------------------------- 1 | COMPILER= 2 | ARCHIVER= 3 | CP=cp 4 | COMPILER_FLAGS= 5 | EXTRA_COMPILER_FLAGS= 6 | LIB=libxil.a 7 | 8 | RELEASEDIR=../../../lib 9 | INCLUDEDIR=../../../include 10 | INCLUDES=-I./. -I${INCLUDEDIR} 11 | 12 | INCLUDEFILES=*.h 13 | LIBSOURCES=*.c 14 | OUTS = *.o 15 | 16 | libs: 17 | echo "Compiling axi_i2s_adi..." 18 | $(COMPILER) $(COMPILER_FLAGS) $(EXTRA_COMPILER_FLAGS) $(INCLUDES) $(LIBSOURCES) 19 | $(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OUTS} 20 | make clean 21 | 22 | include: 23 | ${CP} $(INCLUDEFILES) $(INCLUDEDIR) 24 | 25 | clean: 26 | rm -rf ${OUTS} 27 | -------------------------------------------------------------------------------- /Projects/linux_bd/repo/vivado-library/ip/Pmods/pmodOLEDrgb_v1_0/drivers/PmodOLEDrgb_v1_0/src/Makefile: -------------------------------------------------------------------------------- 1 | COMPILER= 2 | ARCHIVER= 3 | CP=cp 4 | COMPILER_FLAGS= 5 | EXTRA_COMPILER_FLAGS= 6 | LIB=libxil.a 7 | 8 | RELEASEDIR=../../../lib 9 | INCLUDEDIR=../../../include 10 | INCLUDES=-I./. -I${INCLUDEDIR} 11 | 12 | INCLUDEFILES=*.h 13 | LIBSOURCES=*.c 14 | OUTS = *.o 15 | 16 | libs: 17 | echo "Compiling PmodOLEDrgb..." 18 | $(COMPILER) $(COMPILER_FLAGS) $(EXTRA_COMPILER_FLAGS) $(INCLUDES) $(LIBSOURCES) 19 | $(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OUTS} 20 | make clean 21 | 22 | include: 23 | ${CP} $(INCLUDEFILES) $(INCLUDEDIR) 24 | 25 | clean: 26 | rm -rf ${OUTS} 27 | -------------------------------------------------------------------------------- /Projects/linux_bd/repo/vivado-library/ip/Pmods/PmodAMP2_v1_0/ipshared/digilentinc.com/pwm_v1_0/drivers/PWM_v1_0/src/Makefile: -------------------------------------------------------------------------------- 1 | COMPILER= 2 | ARCHIVER= 3 | CP=cp 4 | COMPILER_FLAGS= 5 | EXTRA_COMPILER_FLAGS= 6 | LIB=libxil.a 7 | 8 | RELEASEDIR=../../../lib 9 | INCLUDEDIR=../../../include 10 | INCLUDES=-I./. -I${INCLUDEDIR} 11 | 12 | INCLUDEFILES=*.h 13 | LIBSOURCES=*.c 14 | OUTS = *.o 15 | 16 | libs: 17 | echo "Compiling PWM..." 18 | $(COMPILER) $(COMPILER_FLAGS) $(EXTRA_COMPILER_FLAGS) $(INCLUDES) $(LIBSOURCES) 19 | $(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OUTS} 20 | make clean 21 | 22 | include: 23 | ${CP} $(INCLUDEFILES) $(INCLUDEDIR) 24 | 25 | clean: 26 | rm -rf ${OUTS} 27 | -------------------------------------------------------------------------------- /Projects/linux_bd/repo/vivado-library/ip/Pmods/PmodAMP2_v1_0/src/PmodAMP2_ooc.xdc: -------------------------------------------------------------------------------- 1 | ################################################################################ 2 | 3 | # This XDC is used only for OOC mode of synthesis, implementation 4 | # This constraints file contains default clock frequencies to be used during 5 | # out-of-context flows such as OOC Synthesis and Hierarchical Designs. 6 | # This constraints file is not used in normal top-down synthesis (default flow 7 | # of Vivado) 8 | ################################################################################ 9 | create_clock -name s_axi_aclk -period 10 [get_ports s_axi_aclk] 10 | 11 | ################################################################################ -------------------------------------------------------------------------------- /Projects/linux_bd/repo/vivado-library/ip/Pmods/PmodGPS_v1_1/src/PmodGPS_ooc.xdc: -------------------------------------------------------------------------------- 1 | ################################################################################ 2 | 3 | # This XDC is used only for OOC mode of synthesis, implementation 4 | # This constraints file contains default clock frequencies to be used during 5 | # out-of-context flows such as OOC Synthesis and Hierarchical Designs. 6 | # This constraints file is not used in normal top-down synthesis (default flow 7 | # of Vivado) 8 | ################################################################################ 9 | create_clock -name s_axi_aclk -period 10 [get_ports s_axi_aclk] 10 | 11 | ################################################################################ -------------------------------------------------------------------------------- /Projects/linux_bd/repo/vivado-library/ip/Pmods/PmodALS_v1_0/drivers/PmodALS_v1_0/examples/main.c: -------------------------------------------------------------------------------- 1 | #include "xparameters.h" 2 | #include "xil_types.h" 3 | #include "xil_io.h" 4 | #include "PmodALS.h" 5 | #include 6 | #include 7 | #include "xil_cache.h" 8 | 9 | void DemoInitialize(); 10 | void DemoRun(); 11 | 12 | PmodALS ALS; 13 | 14 | int main(void) 15 | { 16 | Xil_ICacheEnable(); 17 | 18 | DemoInitialize(); 19 | DemoRun(); 20 | return 0; 21 | } 22 | 23 | void DemoInitialize() 24 | { 25 | ALS_begin(&ALS, XPAR_PMODALS_0_AXI_LITE_SPI_BASEADDR); 26 | } 27 | 28 | 29 | void DemoRun() 30 | { 31 | int light=0; 32 | while (1){ 33 | light = ALS_read(&ALS); 34 | xil_printf("Light = %d\n\r", light); 35 | } 36 | } 37 | -------------------------------------------------------------------------------- /Projects/linux_bd/repo/vivado-library/ip/Pmods/PmodACL_v1_0/src/PmodACL_ooc.xdc: -------------------------------------------------------------------------------- 1 | ################################################################################ 2 | 3 | # This XDC is used only for OOC mode of synthesis, implementation 4 | # This constraints file contains default clock frequencies to be used during 5 | # out-of-context flows such as OOC Synthesis and Hierarchical Designs. 6 | # This constraints file is not used in normal top-down synthesis (default flow 7 | # of Vivado) 8 | ################################################################################ 9 | create_clock -name ext_spi_clk -period 10 [get_ports ext_spi_clk] 10 | create_clock -name s_axi_aclk -period 10 [get_ports s_axi_aclk] 11 | 12 | ################################################################################ -------------------------------------------------------------------------------- /Projects/linux_bd/repo/vivado-library/ip/Pmods/PmodALS_v1_0/src/PmodALS_ooc.xdc: -------------------------------------------------------------------------------- 1 | ################################################################################ 2 | 3 | # This XDC is used only for OOC mode of synthesis, implementation 4 | # This constraints file contains default clock frequencies to be used during 5 | # out-of-context flows such as OOC Synthesis and Hierarchical Designs. 6 | # This constraints file is not used in normal top-down synthesis (default flow 7 | # of Vivado) 8 | ################################################################################ 9 | create_clock -name ext_spi_clk -period 10 [get_ports ext_spi_clk] 10 | create_clock -name s_axi_aclk -period 10 [get_ports s_axi_aclk] 11 | 12 | ################################################################################ -------------------------------------------------------------------------------- /Projects/linux_bd/repo/vivado-library/ip/Pmods/PmodBT2_v1_0/src/PmodBT2_ooc.xdc: -------------------------------------------------------------------------------- 1 | ################################################################################ 2 | 3 | # This XDC is used only for OOC mode of synthesis, implementation 4 | # This constraints file contains default clock frequencies to be used during 5 | # out-of-context flows such as OOC Synthesis and Hierarchical Designs. 6 | # This constraints file is not used in normal top-down synthesis (default flow 7 | # of Vivado) 8 | ################################################################################ 9 | create_clock -name s_axi_aclk -period 10 [get_ports s_axi_aclk] 10 | create_clock -name ext_spi_clk -period 10 [get_ports ext_spi_clk] 11 | 12 | ################################################################################ -------------------------------------------------------------------------------- /Projects/dma/sdk/dma_bsp/.cproject: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | -------------------------------------------------------------------------------- /Projects/hdmi_out/sdk/fsbl_bsp/.cproject: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | -------------------------------------------------------------------------------- /Projects/linux_bd/sdk/fsbl_bsp/.cproject: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | -------------------------------------------------------------------------------- /Projects/sdsoc/sdk/fsbl_bsp/.cproject: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | -------------------------------------------------------------------------------- /Projects/sdsoc/sdk/hello_bsp/.cproject: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | -------------------------------------------------------------------------------- /Projects/hdmi_in/sdk/HDMI_IN_bsp/.cproject: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | -------------------------------------------------------------------------------- /Projects/linux_bd/repo/vivado-library/ip/Pmods/PmodAMP2_v1_0/src/PmodAMP2_xlslice_0_0/PmodAMP2_xlslice_0_0.upgrade_log: -------------------------------------------------------------------------------- 1 | Copyright 1986-2015 Xilinx, Inc. All Rights Reserved. 2 | ------------------------------------------------------------------------------------ 3 | | Tool Version : Vivado v.2015.4 (win64) Build 1412921 Wed Nov 18 09:43:45 MST 2015 4 | | Date : Mon Apr 11 11:18:16 2016 5 | | Host : WK116 running 64-bit major release (build 9200) 6 | | Command : upgrade_ip 7 | | Device : xc7a100tcsg324-1 8 | ------------------------------------------------------------------------------------ 9 | 10 | Upgrade Log for IP 'PmodAMP2_xlslice_0_0' 11 | 12 | 1. Summary 13 | ---------- 14 | 15 | SUCCESS in the update of PmodAMP2_xlslice_0_0 (xilinx.com:ip:xlslice:1.0) to current project options. 16 | 17 | -------------------------------------------------------------------------------- /Projects/linux_bd/repo/vivado-library/ip/Pmods/PmodAMP2_v1_0/src/PmodAMP2_xlslice_0_1/PmodAMP2_xlslice_0_1.upgrade_log: -------------------------------------------------------------------------------- 1 | Copyright 1986-2015 Xilinx, Inc. All Rights Reserved. 2 | ------------------------------------------------------------------------------------ 3 | | Tool Version : Vivado v.2015.4 (win64) Build 1412921 Wed Nov 18 09:43:45 MST 2015 4 | | Date : Mon Apr 11 11:18:16 2016 5 | | Host : WK116 running 64-bit major release (build 9200) 6 | | Command : upgrade_ip 7 | | Device : xc7a100tcsg324-1 8 | ------------------------------------------------------------------------------------ 9 | 10 | Upgrade Log for IP 'PmodAMP2_xlslice_0_1' 11 | 12 | 1. Summary 13 | ---------- 14 | 15 | SUCCESS in the update of PmodAMP2_xlslice_0_1 (xilinx.com:ip:xlslice:1.0) to current project options. 16 | 17 | -------------------------------------------------------------------------------- /Projects/linux_bd/repo/vivado-library/ip/Pmods/PmodAMP2_v1_0/src/PmodAMP2_xlslice_0_2/PmodAMP2_xlslice_0_2.upgrade_log: -------------------------------------------------------------------------------- 1 | Copyright 1986-2015 Xilinx, Inc. All Rights Reserved. 2 | ------------------------------------------------------------------------------------ 3 | | Tool Version : Vivado v.2015.4 (win64) Build 1412921 Wed Nov 18 09:43:45 MST 2015 4 | | Date : Mon Apr 11 11:18:16 2016 5 | | Host : WK116 running 64-bit major release (build 9200) 6 | | Command : upgrade_ip 7 | | Device : xc7a100tcsg324-1 8 | ------------------------------------------------------------------------------------ 9 | 10 | Upgrade Log for IP 'PmodAMP2_xlslice_0_2' 11 | 12 | 1. Summary 13 | ---------- 14 | 15 | SUCCESS in the update of PmodAMP2_xlslice_0_2 (xilinx.com:ip:xlslice:1.0) to current project options. 16 | 17 | -------------------------------------------------------------------------------- /Projects/hdmi_out/sdk/displaydemo_bsp/.cproject: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | -------------------------------------------------------------------------------- /Projects/linux_bd/repo/vivado-library/ip/Pmods/PmodAMP2_v1_0/src/PmodAMP2_axi_gpio_0_0/PmodAMP2_axi_gpio_0_0.upgrade_log: -------------------------------------------------------------------------------- 1 | Copyright 1986-2015 Xilinx, Inc. All Rights Reserved. 2 | ------------------------------------------------------------------------------------ 3 | | Tool Version : Vivado v.2015.4 (win64) Build 1412921 Wed Nov 18 09:43:45 MST 2015 4 | | Date : Mon Apr 11 11:18:15 2016 5 | | Host : WK116 running 64-bit major release (build 9200) 6 | | Command : upgrade_ip 7 | | Device : xc7a100tcsg324-1 8 | ------------------------------------------------------------------------------------ 9 | 10 | Upgrade Log for IP 'PmodAMP2_axi_gpio_0_0' 11 | 12 | 1. Summary 13 | ---------- 14 | 15 | SUCCESS in the update of PmodAMP2_axi_gpio_0_0 (xilinx.com:ip:axi_gpio:2.0 (Rev. 9)) to current project options. 16 | 17 | -------------------------------------------------------------------------------- /Projects/linux_bd/repo/vivado-library/ip/Pmods/PmodACL_v1_0/src/PmodACL_pmod_bridge_0_0/PmodACL_pmod_bridge_0_0.upgrade_log: -------------------------------------------------------------------------------- 1 | Copyright 1986-2015 Xilinx, Inc. All Rights Reserved. 2 | ------------------------------------------------------------------------------------ 3 | | Tool Version : Vivado v.2015.4 (win64) Build 1412921 Wed Nov 18 09:43:45 MST 2015 4 | | Date : Mon Mar 28 12:59:14 2016 5 | | Host : WK116 running 64-bit major release (build 9200) 6 | | Command : upgrade_ip 7 | | Device : xc7z010clg400-1 8 | ------------------------------------------------------------------------------------ 9 | 10 | Upgrade Log for IP 'PmodACL_pmod_bridge_0_0' 11 | 12 | 1. Summary 13 | ---------- 14 | 15 | SUCCESS in the upgrade of PmodACL_pmod_bridge_0_0 (digilentinc.com:ip:pmod_bridge:1.0) from (Rev. 2) to (Rev. 6) 16 | 17 | -------------------------------------------------------------------------------- /Projects/linux_bd/repo/vivado-library/ip/Pmods/PmodALS_v1_0/src/PmodALS_pmod_bridge_0_0/PmodALS_pmod_bridge_0_0.upgrade_log: -------------------------------------------------------------------------------- 1 | Copyright 1986-2015 Xilinx, Inc. All Rights Reserved. 2 | ------------------------------------------------------------------------------------ 3 | | Tool Version : Vivado v.2015.4 (win64) Build 1412921 Wed Nov 18 09:43:45 MST 2015 4 | | Date : Mon Mar 28 13:00:04 2016 5 | | Host : WK116 running 64-bit major release (build 9200) 6 | | Command : upgrade_ip 7 | | Device : xc7z010clg400-1 8 | ------------------------------------------------------------------------------------ 9 | 10 | Upgrade Log for IP 'PmodALS_pmod_bridge_0_0' 11 | 12 | 1. Summary 13 | ---------- 14 | 15 | SUCCESS in the upgrade of PmodALS_pmod_bridge_0_0 (digilentinc.com:ip:pmod_bridge:1.0) from (Rev. 2) to (Rev. 6) 16 | 17 | -------------------------------------------------------------------------------- /Projects/linux_bd/repo/vivado-library/ip/Pmods/PmodBT2_v1_0/src/PmodBT2_pmod_bridge_0_0/PmodBT2_pmod_bridge_0_0.upgrade_log: -------------------------------------------------------------------------------- 1 | Copyright 1986-2015 Xilinx, Inc. All Rights Reserved. 2 | ------------------------------------------------------------------------------------ 3 | | Tool Version : Vivado v.2015.4 (win64) Build 1412921 Wed Nov 18 09:43:45 MST 2015 4 | | Date : Mon Mar 28 13:00:56 2016 5 | | Host : WK116 running 64-bit major release (build 9200) 6 | | Command : upgrade_ip 7 | | Device : xc7z010clg400-1 8 | ------------------------------------------------------------------------------------ 9 | 10 | Upgrade Log for IP 'PmodBT2_pmod_bridge_0_0' 11 | 12 | 1. Summary 13 | ---------- 14 | 15 | SUCCESS in the upgrade of PmodBT2_pmod_bridge_0_0 (digilentinc.com:ip:pmod_bridge:1.0) from (Rev. 2) to (Rev. 6) 16 | 17 | -------------------------------------------------------------------------------- /Projects/linux_bd/repo/vivado-library/ip/Pmods/PmodAMP2_v1_0/src/PmodAMP2_pmod_bridge_0_0/PmodAMP2_pmod_bridge_0_0.upgrade_log: -------------------------------------------------------------------------------- 1 | Copyright 1986-2015 Xilinx, Inc. All Rights Reserved. 2 | ------------------------------------------------------------------------------------ 3 | | Tool Version : Vivado v.2015.4 (win64) Build 1412921 Wed Nov 18 09:43:45 MST 2015 4 | | Date : Mon Apr 11 11:18:16 2016 5 | | Host : WK116 running 64-bit major release (build 9200) 6 | | Command : upgrade_ip 7 | | Device : xc7a100tcsg324-1 8 | ------------------------------------------------------------------------------------ 9 | 10 | Upgrade Log for IP 'PmodAMP2_pmod_bridge_0_0' 11 | 12 | 1. Summary 13 | ---------- 14 | 15 | SUCCESS in the update of PmodAMP2_pmod_bridge_0_0 (digilentinc.com:ip:pmod_bridge:1.0 (Rev. 6)) to current project options. 16 | 17 | -------------------------------------------------------------------------------- /Projects/sdsoc/repo/digilent/ip/dvi2rgb_v1_6/src/dvi2rgb.xdc: -------------------------------------------------------------------------------- 1 | ### Clock constraints ### 2 | # Constrain TMDS clock to the 165 MHz maximum from DVI 1.0 specs 3 | create_clock -period 6.060 [get_ports TMDS_Clk_p] 4 | 5 | ### I/O constraints ### 6 | # group data channel IODELAYE2 cells with the IDELAYCTRL 7 | set_property IODELAY_GROUP dvi2rgb_iodelay_grp [get_cells DataDecoders[*].DecoderX/InputSERDES_X/InputDelay] 8 | set_property IODELAY_GROUP dvi2rgb_iodelay_grp [get_cells TMDS_ClockingX/IDelayCtrlX] 9 | 10 | ### Asynchronous clock domain crossings ### 11 | set_false_path -through [get_pins -filter {NAME =~ */SyncAsync*/oSyncStages*/PRE || NAME =~ */SyncAsync*/oSyncStages*/CLR} -hier] 12 | set_false_path -through [get_pins -filter {NAME =~ */SyncAsync*/oSyncStages_reg[0]/D} -hier] 13 | set_false_path -through [get_pins -filter {NAME =~ */SyncBase*/iIn_q*/PRE || NAME =~ */SyncBase*/iIn_q*/CLR} -hier] 14 | -------------------------------------------------------------------------------- /Projects/hdmi_in/repo/digilent/ip/dvi2rgb_v1_6/src/dvi2rgb.xdc: -------------------------------------------------------------------------------- 1 | ### Clock constraints ### 2 | # Constrain TMDS clock to the 165 MHz maximum from DVI 1.0 specs 3 | create_clock -period 6.060 [get_ports TMDS_Clk_p] 4 | 5 | ### I/O constraints ### 6 | # group data channel IODELAYE2 cells with the IDELAYCTRL 7 | set_property IODELAY_GROUP dvi2rgb_iodelay_grp [get_cells DataDecoders[*].DecoderX/InputSERDES_X/InputDelay] 8 | set_property IODELAY_GROUP dvi2rgb_iodelay_grp [get_cells TMDS_ClockingX/IDelayCtrlX] 9 | 10 | ### Asynchronous clock domain crossings ### 11 | set_false_path -through [get_pins -filter {NAME =~ */SyncAsync*/oSyncStages*/PRE || NAME =~ */SyncAsync*/oSyncStages*/CLR} -hier] 12 | set_false_path -through [get_pins -filter {NAME =~ */SyncAsync*/oSyncStages_reg[0]/D} -hier] 13 | set_false_path -through [get_pins -filter {NAME =~ */SyncBase*/iIn_q*/PRE || NAME =~ */SyncBase*/iIn_q*/CLR} -hier] 14 | -------------------------------------------------------------------------------- /Projects/dma/sdk/dma/.project: -------------------------------------------------------------------------------- 1 | 2 | 3 | dma 4 | Created by SDK v2016.2. dma_bsp - ps7_cortexa9_0 5 | 6 | dma_bsp 7 | 8 | 9 | 10 | org.eclipse.cdt.managedbuilder.core.genmakebuilder 11 | 12 | 13 | 14 | 15 | org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder 16 | full,incremental, 17 | 18 | 19 | 20 | 21 | 22 | org.eclipse.cdt.core.cnature 23 | org.eclipse.cdt.managedbuilder.core.managedBuildNature 24 | org.eclipse.cdt.managedbuilder.core.ScannerConfigNature 25 | 26 | 27 | -------------------------------------------------------------------------------- /Projects/sdsoc/sdk/hello/.project: -------------------------------------------------------------------------------- 1 | 2 | 3 | hello 4 | Created by SDK v2015.4. hello_bsp - ps7_cortexa9_0 5 | 6 | hello_bsp 7 | 8 | 9 | 10 | org.eclipse.cdt.managedbuilder.core.genmakebuilder 11 | 12 | 13 | 14 | 15 | org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder 16 | full,incremental, 17 | 18 | 19 | 20 | 21 | 22 | org.eclipse.cdt.core.cnature 23 | org.eclipse.cdt.managedbuilder.core.managedBuildNature 24 | org.eclipse.cdt.managedbuilder.core.ScannerConfigNature 25 | 26 | 27 | -------------------------------------------------------------------------------- /Projects/hdmi_in/sdk/HDMI_IN/.project: -------------------------------------------------------------------------------- 1 | 2 | 3 | HDMI_IN 4 | Created by SDK v2015.4. HDMI_IN_bsp - ps7_cortexa9_0 5 | 6 | HDMI_IN_bsp 7 | 8 | 9 | 10 | org.eclipse.cdt.managedbuilder.core.genmakebuilder 11 | 12 | 13 | 14 | 15 | org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder 16 | full,incremental, 17 | 18 | 19 | 20 | 21 | 22 | org.eclipse.cdt.core.cnature 23 | org.eclipse.cdt.managedbuilder.core.managedBuildNature 24 | org.eclipse.cdt.managedbuilder.core.ScannerConfigNature 25 | 26 | 27 | -------------------------------------------------------------------------------- /Projects/hdmi_out/sdk/displaydemo/.project: -------------------------------------------------------------------------------- 1 | 2 | 3 | displaydemo 4 | Created by SDK v2015.4. displaydemo_bsp - ps7_cortexa9_0 5 | 6 | displaydemo_bsp 7 | 8 | 9 | 10 | org.eclipse.cdt.managedbuilder.core.genmakebuilder 11 | 12 | 13 | 14 | 15 | org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder 16 | full,incremental, 17 | 18 | 19 | 20 | 21 | 22 | org.eclipse.cdt.core.cnature 23 | org.eclipse.cdt.managedbuilder.core.managedBuildNature 24 | org.eclipse.cdt.managedbuilder.core.ScannerConfigNature 25 | 26 | 27 | -------------------------------------------------------------------------------- /Projects/hdmi_in/repo/digilent/ip/dvi2rgb_v1_6/gui/dvi2rgb_v1_0.gtcl: -------------------------------------------------------------------------------- 1 | # This file is automatically written. Do not modify. 2 | proc gen_HDLPARAMETER_RST_POLARITY_VALUE {RST_POLARITY } {expr { ( $RST_POLARITY eq "ACTIVE_HIGH" ) ? 1 : 0}} 3 | proc gen_HDLPARAMETER_RESET_POLARITY_VALUE {RESET_POLARITY } {expr { ( $RESET_POLARITY eq "ACTIVE_HIGH" ) ? 1 : 0}} 4 | proc gen_HDLPARAMETER_TOTAL_PERIOD_VALUE {PULSE_PERIOD RST_PERIOD } {expr { ( $PULSE_PERIOD > 0 ) ? [expr $PULSE_PERIOD - $RST_PERIOD] : 0 }} 5 | proc gen_USERPARAMETER_kEDIDFile_ENABLEMENT {kEmulateDDC } {expr $kEmulateDDC} 6 | proc gen_USERPARAMETER_RESET_POLARITY_ENABLEMENT {CLOCK_TYPE } {expr { $CLOCK_TYPE eq "Single_Ended"} } 7 | proc gen_HDLPARAMETER_CLOCK_PERIOD_VALUE {FREQ_HZ } {expr { 1000000000.0 / $FREQ_HZ }} 8 | proc gen_USERPARAMETER_INITIAL_RESET_CLOCK_CYCLES_ENABLEMENT {CLOCK_TYPE } {expr { $CLOCK_TYPE eq "Single_Ended"} } 9 | proc gen_USERPARAMETER_kEdidFileName_ENABLEMENT {kEmulateDDC } {expr $kEmulateDDC} 10 | -------------------------------------------------------------------------------- /Projects/sdsoc/repo/digilent/ip/dvi2rgb_v1_6/gui/dvi2rgb_v1_0.gtcl: -------------------------------------------------------------------------------- 1 | # This file is automatically written. Do not modify. 2 | proc gen_HDLPARAMETER_RST_POLARITY_VALUE {RST_POLARITY } {expr { ( $RST_POLARITY eq "ACTIVE_HIGH" ) ? 1 : 0}} 3 | proc gen_HDLPARAMETER_RESET_POLARITY_VALUE {RESET_POLARITY } {expr { ( $RESET_POLARITY eq "ACTIVE_HIGH" ) ? 1 : 0}} 4 | proc gen_HDLPARAMETER_TOTAL_PERIOD_VALUE {PULSE_PERIOD RST_PERIOD } {expr { ( $PULSE_PERIOD > 0 ) ? [expr $PULSE_PERIOD - $RST_PERIOD] : 0 }} 5 | proc gen_USERPARAMETER_kEDIDFile_ENABLEMENT {kEmulateDDC } {expr $kEmulateDDC} 6 | proc gen_USERPARAMETER_RESET_POLARITY_ENABLEMENT {CLOCK_TYPE } {expr { $CLOCK_TYPE eq "Single_Ended"} } 7 | proc gen_HDLPARAMETER_CLOCK_PERIOD_VALUE {FREQ_HZ } {expr { 1000000000.0 / $FREQ_HZ }} 8 | proc gen_USERPARAMETER_INITIAL_RESET_CLOCK_CYCLES_ENABLEMENT {CLOCK_TYPE } {expr { $CLOCK_TYPE eq "Single_Ended"} } 9 | proc gen_USERPARAMETER_kEdidFileName_ENABLEMENT {kEmulateDDC } {expr $kEmulateDDC} 10 | -------------------------------------------------------------------------------- /Projects/linux_bd/repo/vivado-library/ip/dvi2rgb_v1_6/gui/dvi2rgb_v1_0.gtcl: -------------------------------------------------------------------------------- 1 | # This file is automatically written. Do not modify. 2 | proc gen_HDLPARAMETER_RST_POLARITY_VALUE {RST_POLARITY } {expr { ( $RST_POLARITY eq "ACTIVE_HIGH" ) ? 1 : 0}} 3 | proc gen_HDLPARAMETER_RESET_POLARITY_VALUE {RESET_POLARITY } {expr { ( $RESET_POLARITY eq "ACTIVE_HIGH" ) ? 1 : 0}} 4 | proc gen_HDLPARAMETER_TOTAL_PERIOD_VALUE {PULSE_PERIOD RST_PERIOD } {expr { ( $PULSE_PERIOD > 0 ) ? [expr $PULSE_PERIOD - $RST_PERIOD] : 0 }} 5 | proc gen_USERPARAMETER_kEDIDFile_ENABLEMENT {kEmulateDDC } {expr $kEmulateDDC} 6 | proc gen_USERPARAMETER_RESET_POLARITY_ENABLEMENT {CLOCK_TYPE } {expr { $CLOCK_TYPE eq "Single_Ended"} } 7 | proc gen_HDLPARAMETER_CLOCK_PERIOD_VALUE {FREQ_HZ } {expr { 1000000000.0 / $FREQ_HZ }} 8 | proc gen_USERPARAMETER_INITIAL_RESET_CLOCK_CYCLES_ENABLEMENT {CLOCK_TYPE } {expr { $CLOCK_TYPE eq "Single_Ended"} } 9 | proc gen_USERPARAMETER_kEdidFileName_ENABLEMENT {kEmulateDDC } {expr $kEmulateDDC} 10 | -------------------------------------------------------------------------------- /Projects/linux_bd/repo/vivado-library/if/pmod_v1_0/pmod.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | digilentinc.com 4 | interface 5 | pmod 6 | 1.0 7 | true 8 | false 9 | 1 10 | 1 11 | Pmod Interface for Digilent FPGAs 12 | 13 | 14 | Pmod Interface 15 | 16 | 17 | 18 | -------------------------------------------------------------------------------- /Projects/hdmi_in/repo/digilent/if/tmds_v1_0/tmds.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | digilentinc.com 4 | interface 5 | tmds 6 | 1.0 7 | false 8 | false 9 | 1 10 | 1 11 | Raw TMDS electrical interface as defined in DVI 1.0 12 | 13 | 14 | TMDS Interface for DVI and HDMI 15 | 16 | 17 | 18 | -------------------------------------------------------------------------------- /Projects/hdmi_out/repo/digilent/if/tmds_v1_0/tmds.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | digilentinc.com 4 | interface 5 | tmds 6 | 1.0 7 | false 8 | false 9 | 1 10 | 1 11 | Raw TMDS electrical interface as defined in DVI 1.0 12 | 13 | 14 | TMDS Interface for DVI and HDMI 15 | 16 | 17 | 18 | -------------------------------------------------------------------------------- /Projects/sdsoc/repo/digilent/if/tmds_v1_0/tmds.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | digilentinc.com 4 | interface 5 | tmds 6 | 1.0 7 | false 8 | false 9 | 1 10 | 1 11 | Raw TMDS electrical interface as defined in DVI 1.0 12 | 13 | 14 | TMDS Interface for DVI and HDMI 15 | 16 | 17 | 18 | -------------------------------------------------------------------------------- /Projects/linux_bd/repo/vivado-library/if/tmds_v1_0/tmds.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | digilentinc.com 4 | interface 5 | tmds 6 | 1.0 7 | false 8 | false 9 | 1 10 | 1 11 | Raw TMDS electrical interface as defined in DVI 1.0 12 | 13 | 14 | TMDS Interface for DVI and HDMI 15 | 16 | 17 | 18 | -------------------------------------------------------------------------------- /Projects/linux_bd/repo/vivado-library/ip/Pmods/PmodACL_v1_0/drivers/PmodACL_v1_0/examples/main.c: -------------------------------------------------------------------------------- 1 | #include "xparameters.h" 2 | #include "xil_types.h" 3 | #include "xil_io.h" 4 | #include "PmodACL.h" 5 | #include 6 | #include 7 | #include "xil_cache.h" 8 | 9 | void DemoInitialize(); 10 | void DemoRun(); 11 | 12 | PmodACL ACL; 13 | 14 | int main(void) 15 | { 16 | Xil_ICacheEnable(); 17 | 18 | DemoInitialize(); 19 | DemoRun(); 20 | return 0; 21 | } 22 | 23 | void DemoInitialize() 24 | { 25 | ACL_begin(&ACL, XPAR_PMODACL_0_AXI_LITE_GPIO_BASEADDR,XPAR_PMODACL_0_AXI_LITE_SPI_BASEADDR); 26 | SetMeasure(&ACL, FALSE); 27 | SetGRange(&ACL, PAR_GRANGE_PM4G); 28 | SetMeasure(&ACL, TRUE); 29 | CalibrateOneAxisGravitational(&ACL, PAR_AXIS_ZP); 30 | } 31 | 32 | 33 | void DemoRun() 34 | { 35 | float x; 36 | float y; 37 | float z; 38 | char strMes[150]; 39 | while (1){ 40 | ReadAccelG(&ACL, &x, &y, &z); 41 | sprintf(strMes ,"X=%f\tY=%f\tZ=%f\n\r", x, y, z); 42 | xil_printf(strMes); 43 | usleep(100000); 44 | } 45 | } 46 | -------------------------------------------------------------------------------- /Projects/linux_bd/repo/vivado-library/ip/dvi2rgb_v1_6/src/dvi2rgb.xdc: -------------------------------------------------------------------------------- 1 | ### Clock constraints ### 2 | # Constrain TMDS clock in the top-level project. Constraining it here, even if overridden in the top-level project 3 | # results in [DRC 23-20] Rule violation (PDRC-34) for the maximum MMCM VCO frequency. 4 | # create_clock -period 6.060 [get_ports TMDS_Clk_p] 5 | 6 | ### I/O constraints ### 7 | # group data channel IODELAYE2 cells with the IDELAYCTRL 8 | set_property IODELAY_GROUP dvi2rgb_iodelay_grp [get_cells DataDecoders[*].DecoderX/InputSERDES_X/InputDelay] 9 | set_property IODELAY_GROUP dvi2rgb_iodelay_grp [get_cells TMDS_ClockingX/IDelayCtrlX] 10 | 11 | ### Asynchronous clock domain crossings ### 12 | set_false_path -through [get_pins -filter {NAME =~ */SyncAsync*/oSyncStages*/PRE || NAME =~ */SyncAsync*/oSyncStages*/CLR} -hier] 13 | set_false_path -through [get_pins -filter {NAME =~ */SyncAsync*/oSyncStages_reg[0]/D} -hier] 14 | set_false_path -through [get_pins -filter {NAME =~ */SyncBase*/iIn_q*/PRE || NAME =~ */SyncBase*/iIn_q*/CLR} -hier] 15 | -------------------------------------------------------------------------------- /Projects/sdsoc/src/others/hw_pfm_gen.tcl: -------------------------------------------------------------------------------- 1 | #First run source -notrace C:/Xilinx/SDSoC/2015.4/scripts/vivado/sdsoc_pfm.tcl 2 | 3 | set pfm [sdsoc::create_pfm zybo_hdmi_in_hw.pfm] 4 | sdsoc::pfm_name $pfm "digilentinc.com" "xd" "zybo_hdmi_in" "1.0" 5 | sdsoc::pfm_description $pfm "ZYBO Development Platform with HDMI-in/VGA-out" 6 | sdsoc::pfm_clock $pfm FCLK_CLK0 processing_system7_0 0 true proc_sys_reset_0 7 | sdsoc::pfm_clock $pfm FCLK_CLK1 processing_system7_0 1 false proc_sys_reset_1 8 | sdsoc::pfm_clock $pfm FCLK_CLK3 processing_system7_0 3 false proc_sys_reset_3 9 | sdsoc::pfm_axi_port $pfm M_AXI_GP1 processing_system7_0 M_AXI_GP 10 | sdsoc::pfm_axi_port $pfm S_AXI_ACP processing_system7_0 S_AXI_ACP 11 | sdsoc::pfm_axi_port $pfm S_AXI_HP2 processing_system7_0 S_AXI_HP 12 | sdsoc::pfm_axi_port $pfm S_AXI_HP3 processing_system7_0 S_AXI_HP 13 | for {set i 5} {$i < 16} {incr i} { 14 | sdsoc::pfm_irq $pfm In$i xlconcat_0 15 | } 16 | sdsoc::pfm_iodev $pfm S_AXI axi_gpio_sw uio 17 | sdsoc::pfm_iodev $pfm S_AXI axi_gpio_led uio 18 | sdsoc::generate_hw_pfm $pfm 19 | -------------------------------------------------------------------------------- /Projects/sdsoc/repo/digilent/ip/clock_forwarder_1.0/hdl/clock_forwarder_v1_0.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | use ieee.numeric_std.all; 4 | 5 | Library UNISIM; 6 | use UNISIM.vcomponents.all; 7 | 8 | entity clock_forwarder_v1_0 is 9 | port ( 10 | aRst : in std_logic; 11 | InClk : in std_logic; 12 | iCE : in std_logic; 13 | OutClk : out std_logic 14 | ); 15 | end clock_forwarder_v1_0; 16 | 17 | architecture arch_imp of clock_forwarder_v1_0 is 18 | begin 19 | 20 | ODDR_inst : ODDR 21 | generic map( 22 | DDR_CLK_EDGE => "OPPOSITE_EDGE", -- "OPPOSITE_EDGE" or "SAME_EDGE" 23 | INIT => '0', -- Initial value for Q port ('1' or '0') 24 | SRTYPE => "ASYNC") -- Reset Type ("ASYNC" or "SYNC") 25 | port map ( 26 | Q => OutClk, -- 1-bit DDR output 27 | C => InClk, -- 1-bit clock input 28 | CE => iCE, -- 1-bit clock enable input 29 | D1 => '1', -- 1-bit data input (positive edge) 30 | D2 => '0', -- 1-bit data input (negative edge) 31 | R => aRst, -- 1-bit reset input 32 | S => '0' -- 1-bit set input 33 | ); 34 | end arch_imp; 35 | -------------------------------------------------------------------------------- /Projects/hdmi_in/repo/digilent/ip/clock_forwarder_1.0/hdl/clock_forwarder_v1_0.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | use ieee.numeric_std.all; 4 | 5 | Library UNISIM; 6 | use UNISIM.vcomponents.all; 7 | 8 | entity clock_forwarder_v1_0 is 9 | port ( 10 | aRst : in std_logic; 11 | InClk : in std_logic; 12 | iCE : in std_logic; 13 | OutClk : out std_logic 14 | ); 15 | end clock_forwarder_v1_0; 16 | 17 | architecture arch_imp of clock_forwarder_v1_0 is 18 | begin 19 | 20 | ODDR_inst : ODDR 21 | generic map( 22 | DDR_CLK_EDGE => "OPPOSITE_EDGE", -- "OPPOSITE_EDGE" or "SAME_EDGE" 23 | INIT => '0', -- Initial value for Q port ('1' or '0') 24 | SRTYPE => "ASYNC") -- Reset Type ("ASYNC" or "SYNC") 25 | port map ( 26 | Q => OutClk, -- 1-bit DDR output 27 | C => InClk, -- 1-bit clock input 28 | CE => iCE, -- 1-bit clock enable input 29 | D1 => '1', -- 1-bit data input (positive edge) 30 | D2 => '0', -- 1-bit data input (negative edge) 31 | R => aRst, -- 1-bit reset input 32 | S => '0' -- 1-bit set input 33 | ); 34 | end arch_imp; 35 | -------------------------------------------------------------------------------- /Projects/linux_bd/repo/vivado-library/ip/clock_forwarder_1.0/hdl/clock_forwarder_v1_0.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | use ieee.numeric_std.all; 4 | 5 | Library UNISIM; 6 | use UNISIM.vcomponents.all; 7 | 8 | entity clock_forwarder_v1_0 is 9 | port ( 10 | aRst : in std_logic; 11 | InClk : in std_logic; 12 | iCE : in std_logic; 13 | OutClk : out std_logic 14 | ); 15 | end clock_forwarder_v1_0; 16 | 17 | architecture arch_imp of clock_forwarder_v1_0 is 18 | begin 19 | 20 | ODDR_inst : ODDR 21 | generic map( 22 | DDR_CLK_EDGE => "OPPOSITE_EDGE", -- "OPPOSITE_EDGE" or "SAME_EDGE" 23 | INIT => '0', -- Initial value for Q port ('1' or '0') 24 | SRTYPE => "ASYNC") -- Reset Type ("ASYNC" or "SYNC") 25 | port map ( 26 | Q => OutClk, -- 1-bit DDR output 27 | C => InClk, -- 1-bit clock input 28 | CE => iCE, -- 1-bit clock enable input 29 | D1 => '1', -- 1-bit data input (positive edge) 30 | D2 => '0', -- 1-bit data input (negative edge) 31 | R => aRst, -- 1-bit reset input 32 | S => '0' -- 1-bit set input 33 | ); 34 | end arch_imp; 35 | -------------------------------------------------------------------------------- /Projects/hdmi_out/sdk/fsbl/.project: -------------------------------------------------------------------------------- 1 | 2 | 3 | fsbl 4 | Created by SDK v2015.4. fsbl_bsp - ps7_cortexa9_0 5 | 6 | fsbl_bsp 7 | 8 | 9 | 10 | org.eclipse.cdt.managedbuilder.core.genmakebuilder 11 | 12 | 13 | 14 | 15 | org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder 16 | full,incremental, 17 | 18 | 19 | 20 | 21 | 22 | org.eclipse.cdt.core.cnature 23 | org.eclipse.cdt.managedbuilder.core.managedBuildNature 24 | org.eclipse.cdt.managedbuilder.core.ScannerConfigNature 25 | 26 | 27 | 28 | src/ps7_init.c 29 | 1 30 | WORKSPACE_LOC/hdmi_out_wrapper_hw_platform_0/ps7_init.c 31 | 32 | 33 | 34 | -------------------------------------------------------------------------------- /Projects/linux_bd/sdk/fsbl/.project: -------------------------------------------------------------------------------- 1 | 2 | 3 | fsbl 4 | Created by SDK v2015.4. fsbl_bsp - ps7_cortexa9_0 5 | 6 | fsbl_bsp 7 | 8 | 9 | 10 | org.eclipse.cdt.managedbuilder.core.genmakebuilder 11 | 12 | 13 | 14 | 15 | org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder 16 | full,incremental, 17 | 18 | 19 | 20 | 21 | 22 | org.eclipse.cdt.core.cnature 23 | org.eclipse.cdt.managedbuilder.core.managedBuildNature 24 | org.eclipse.cdt.managedbuilder.core.ScannerConfigNature 25 | 26 | 27 | 28 | src/ps7_init.c 29 | 1 30 | WORKSPACE_LOC/linux_bd_wrapper_hw_platform_0/ps7_init.c 31 | 32 | 33 | 34 | -------------------------------------------------------------------------------- /Projects/sdsoc/sdk/fsbl/.project: -------------------------------------------------------------------------------- 1 | 2 | 3 | fsbl 4 | Created by SDK v2015.4. fsbl_bsp - ps7_cortexa9_0 5 | 6 | fsbl_bsp 7 | 8 | 9 | 10 | org.eclipse.cdt.managedbuilder.core.genmakebuilder 11 | 12 | 13 | 14 | 15 | org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder 16 | full,incremental, 17 | 18 | 19 | 20 | 21 | 22 | org.eclipse.cdt.core.cnature 23 | org.eclipse.cdt.managedbuilder.core.managedBuildNature 24 | org.eclipse.cdt.managedbuilder.core.ScannerConfigNature 25 | 26 | 27 | 28 | src/ps7_init.c 29 | 1 30 | WORKSPACE_LOC/zybo_hdmi_in_wrapper_hw_platform_0/ps7_init.c 31 | 32 | 33 | 34 | -------------------------------------------------------------------------------- /Projects/dma/sdk/design_1_wrapper_hw_platform_0/.project: -------------------------------------------------------------------------------- 1 | 2 | 3 | design_1_wrapper_hw_platform_0 4 | Created by SDK v2016.2 5 | 6 | 7 | 8 | 9 | 10 | com.xilinx.sdk.hw.HwProject 11 | 12 | 13 | 14 | 1472082612947 15 | 16 | 6 17 | 18 | org.eclipse.ui.ide.multiFilter 19 | 1.0-name-matches-false-false-*.xml 20 | 21 | 22 | 23 | 1472082612949 24 | 25 | 6 26 | 27 | org.eclipse.ui.ide.multiFilter 28 | 1.0-name-matches-false-false-*.svd 29 | 30 | 31 | 32 | 1472082612950 33 | 34 | 6 35 | 36 | org.eclipse.ui.ide.multiFilter 37 | 1.0-name-matches-false-false-*.hwh 38 | 39 | 40 | 41 | 42 | -------------------------------------------------------------------------------- /Projects/hdmi_in/sdk/hdmi_in_wrapper_hw_platform_0/.project: -------------------------------------------------------------------------------- 1 | 2 | 3 | hdmi_in_wrapper_hw_platform_0 4 | Created by SDK v2015.4 5 | 6 | 7 | 8 | 9 | 10 | com.xilinx.sdk.hw.HwProject 11 | 12 | 13 | 14 | 1475868578967 15 | 16 | 6 17 | 18 | org.eclipse.ui.ide.multiFilter 19 | 1.0-name-matches-false-false-*.xml 20 | 21 | 22 | 23 | 1475868578978 24 | 25 | 6 26 | 27 | org.eclipse.ui.ide.multiFilter 28 | 1.0-name-matches-false-false-*.svd 29 | 30 | 31 | 32 | 1475868579008 33 | 34 | 6 35 | 36 | org.eclipse.ui.ide.multiFilter 37 | 1.0-name-matches-false-false-*.hwh 38 | 39 | 40 | 41 | 42 | -------------------------------------------------------------------------------- /Projects/hdmi_out/sdk/hdmi_out_wrapper_hw_platform_0/.project: -------------------------------------------------------------------------------- 1 | 2 | 3 | hdmi_out_wrapper_hw_platform_0 4 | Created by SDK v2015.4 5 | 6 | 7 | 8 | 9 | 10 | com.xilinx.sdk.hw.HwProject 11 | 12 | 13 | 14 | 1454734519996 15 | 16 | 6 17 | 18 | org.eclipse.ui.ide.multiFilter 19 | 1.0-name-matches-false-false-*.xml 20 | 21 | 22 | 23 | 1454734520005 24 | 25 | 6 26 | 27 | org.eclipse.ui.ide.multiFilter 28 | 1.0-name-matches-false-false-*.svd 29 | 30 | 31 | 32 | 1454734520015 33 | 34 | 6 35 | 36 | org.eclipse.ui.ide.multiFilter 37 | 1.0-name-matches-false-false-*.hwh 38 | 39 | 40 | 41 | 42 | -------------------------------------------------------------------------------- /Projects/sdsoc/sdk/zybo_hdmi_in_wrapper_hw_platform_0/.project: -------------------------------------------------------------------------------- 1 | 2 | 3 | zybo_hdmi_in_wrapper_hw_platform_0 4 | Created by SDK v2015.4 5 | 6 | 7 | 8 | 9 | 10 | com.xilinx.sdk.hw.HwProject 11 | 12 | 13 | 14 | 1458177185154 15 | 16 | 6 17 | 18 | org.eclipse.ui.ide.multiFilter 19 | 1.0-name-matches-false-false-*.xml 20 | 21 | 22 | 23 | 1458177185162 24 | 25 | 6 26 | 27 | org.eclipse.ui.ide.multiFilter 28 | 1.0-name-matches-false-false-*.svd 29 | 30 | 31 | 32 | 1458177185171 33 | 34 | 6 35 | 36 | org.eclipse.ui.ide.multiFilter 37 | 1.0-name-matches-false-false-*.hwh 38 | 39 | 40 | 41 | 42 | -------------------------------------------------------------------------------- /Projects/hdmi_out/repo/board_files/zybo/B.3/part0_pins.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | -------------------------------------------------------------------------------- /Projects/sdsoc/sdk/fsbl_bsp/Makefile: -------------------------------------------------------------------------------- 1 | # Makefile generated by Xilinx. 2 | 3 | PROCESSOR = ps7_cortexa9_0 4 | LIBRARIES = ${PROCESSOR}/lib/libxil.a 5 | BSP_MAKEFILES := $(wildcard $(PROCESSOR)/libsrc/*/src/Makefile) 6 | SUBDIRS := $(patsubst %/Makefile, %, $(BSP_MAKEFILES)) 7 | 8 | ifneq (,$(findstring win,$(RDI_PLATFORM))) 9 | SHELL = CMD 10 | endif 11 | 12 | all: libs 13 | @echo 'Finished building libraries' 14 | 15 | include: $(addsuffix /make.include,$(SUBDIRS)) 16 | 17 | libs: $(addsuffix /make.libs,$(SUBDIRS)) 18 | 19 | $(PROCESSOR)/lib/libxil.a: $(PROCESSOR)/lib/libxil_init.a 20 | cp -f $< $@ 21 | 22 | %/make.include: $(if $(wildcard $(PROCESSOR)/lib/libxil_init.a),$(PROCESSOR)/lib/libxil.a,) 23 | @echo "Running Make include in $(subst /make.include,,$@)" 24 | $(MAKE) -C $(subst /make.include,,$@) -s include "SHELL=$(SHELL)" "COMPILER=arm-xilinx-eabi-gcc" "ARCHIVER=arm-xilinx-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-g" 25 | 26 | %/make.libs: include 27 | @echo "Running Make libs in $(subst /make.libs,,$@)" 28 | $(MAKE) -C $(subst /make.libs,,$@) -s libs "SHELL=$(SHELL)" "COMPILER=arm-xilinx-eabi-gcc" "ARCHIVER=arm-xilinx-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-g" 29 | 30 | clean: 31 | rm -f ${PROCESSOR}/lib/libxil.a 32 | -------------------------------------------------------------------------------- /Projects/hdmi_in/sdk/HDMI_IN_bsp/Makefile: -------------------------------------------------------------------------------- 1 | # Makefile generated by Xilinx. 2 | 3 | PROCESSOR = ps7_cortexa9_0 4 | LIBRARIES = ${PROCESSOR}/lib/libxil.a 5 | BSP_MAKEFILES := $(wildcard $(PROCESSOR)/libsrc/*/src/Makefile) 6 | SUBDIRS := $(patsubst %/Makefile, %, $(BSP_MAKEFILES)) 7 | 8 | ifneq (,$(findstring win,$(RDI_PLATFORM))) 9 | SHELL = CMD 10 | endif 11 | 12 | all: libs 13 | @echo 'Finished building libraries' 14 | 15 | include: $(addsuffix /make.include,$(SUBDIRS)) 16 | 17 | libs: $(addsuffix /make.libs,$(SUBDIRS)) 18 | 19 | $(PROCESSOR)/lib/libxil.a: $(PROCESSOR)/lib/libxil_init.a 20 | cp -f $< $@ 21 | 22 | %/make.include: $(if $(wildcard $(PROCESSOR)/lib/libxil_init.a),$(PROCESSOR)/lib/libxil.a,) 23 | @echo "Running Make include in $(subst /make.include,,$@)" 24 | $(MAKE) -C $(subst /make.include,,$@) -s include "SHELL=$(SHELL)" "COMPILER=arm-xilinx-eabi-gcc" "ARCHIVER=arm-xilinx-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-g" 25 | 26 | %/make.libs: include 27 | @echo "Running Make libs in $(subst /make.libs,,$@)" 28 | $(MAKE) -C $(subst /make.libs,,$@) -s libs "SHELL=$(SHELL)" "COMPILER=arm-xilinx-eabi-gcc" "ARCHIVER=arm-xilinx-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-g" 29 | 30 | clean: 31 | rm -f ${PROCESSOR}/lib/libxil.a 32 | -------------------------------------------------------------------------------- /Projects/hdmi_out/sdk/fsbl_bsp/Makefile: -------------------------------------------------------------------------------- 1 | # Makefile generated by Xilinx. 2 | 3 | PROCESSOR = ps7_cortexa9_0 4 | LIBRARIES = ${PROCESSOR}/lib/libxil.a 5 | BSP_MAKEFILES := $(wildcard $(PROCESSOR)/libsrc/*/src/Makefile) 6 | SUBDIRS := $(patsubst %/Makefile, %, $(BSP_MAKEFILES)) 7 | 8 | ifneq (,$(findstring win,$(RDI_PLATFORM))) 9 | SHELL = CMD 10 | endif 11 | 12 | all: libs 13 | @echo 'Finished building libraries' 14 | 15 | include: $(addsuffix /make.include,$(SUBDIRS)) 16 | 17 | libs: $(addsuffix /make.libs,$(SUBDIRS)) 18 | 19 | $(PROCESSOR)/lib/libxil.a: $(PROCESSOR)/lib/libxil_init.a 20 | cp -f $< $@ 21 | 22 | %/make.include: $(if $(wildcard $(PROCESSOR)/lib/libxil_init.a),$(PROCESSOR)/lib/libxil.a,) 23 | @echo "Running Make include in $(subst /make.include,,$@)" 24 | $(MAKE) -C $(subst /make.include,,$@) -s include "SHELL=$(SHELL)" "COMPILER=arm-xilinx-eabi-gcc" "ARCHIVER=arm-xilinx-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-g" 25 | 26 | %/make.libs: include 27 | @echo "Running Make libs in $(subst /make.libs,,$@)" 28 | $(MAKE) -C $(subst /make.libs,,$@) -s libs "SHELL=$(SHELL)" "COMPILER=arm-xilinx-eabi-gcc" "ARCHIVER=arm-xilinx-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-g" 29 | 30 | clean: 31 | rm -f ${PROCESSOR}/lib/libxil.a 32 | -------------------------------------------------------------------------------- /Projects/linux_bd/sdk/fsbl_bsp/Makefile: -------------------------------------------------------------------------------- 1 | # Makefile generated by Xilinx. 2 | 3 | PROCESSOR = ps7_cortexa9_0 4 | LIBRARIES = ${PROCESSOR}/lib/libxil.a 5 | BSP_MAKEFILES := $(wildcard $(PROCESSOR)/libsrc/*/src/Makefile) 6 | SUBDIRS := $(patsubst %/Makefile, %, $(BSP_MAKEFILES)) 7 | 8 | ifneq (,$(findstring win,$(RDI_PLATFORM))) 9 | SHELL = CMD 10 | endif 11 | 12 | all: libs 13 | @echo 'Finished building libraries' 14 | 15 | include: $(addsuffix /make.include,$(SUBDIRS)) 16 | 17 | libs: $(addsuffix /make.libs,$(SUBDIRS)) 18 | 19 | $(PROCESSOR)/lib/libxil.a: $(PROCESSOR)/lib/libxil_init.a 20 | cp -f $< $@ 21 | 22 | %/make.include: $(if $(wildcard $(PROCESSOR)/lib/libxil_init.a),$(PROCESSOR)/lib/libxil.a,) 23 | @echo "Running Make include in $(subst /make.include,,$@)" 24 | $(MAKE) -C $(subst /make.include,,$@) -s include "SHELL=$(SHELL)" "COMPILER=arm-xilinx-eabi-gcc" "ARCHIVER=arm-xilinx-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-g" 25 | 26 | %/make.libs: include 27 | @echo "Running Make libs in $(subst /make.libs,,$@)" 28 | $(MAKE) -C $(subst /make.libs,,$@) -s libs "SHELL=$(SHELL)" "COMPILER=arm-xilinx-eabi-gcc" "ARCHIVER=arm-xilinx-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-g" 29 | 30 | clean: 31 | rm -f ${PROCESSOR}/lib/libxil.a 32 | -------------------------------------------------------------------------------- /Projects/sdsoc/sdk/hello_bsp/Makefile: -------------------------------------------------------------------------------- 1 | # Makefile generated by Xilinx. 2 | 3 | PROCESSOR = ps7_cortexa9_0 4 | LIBRARIES = ${PROCESSOR}/lib/libxil.a 5 | BSP_MAKEFILES := $(wildcard $(PROCESSOR)/libsrc/*/src/Makefile) 6 | SUBDIRS := $(patsubst %/Makefile, %, $(BSP_MAKEFILES)) 7 | 8 | ifneq (,$(findstring win,$(RDI_PLATFORM))) 9 | SHELL = CMD 10 | endif 11 | 12 | all: libs 13 | @echo 'Finished building libraries' 14 | 15 | include: $(addsuffix /make.include,$(SUBDIRS)) 16 | 17 | libs: $(addsuffix /make.libs,$(SUBDIRS)) 18 | 19 | $(PROCESSOR)/lib/libxil.a: $(PROCESSOR)/lib/libxil_init.a 20 | cp -f $< $@ 21 | 22 | %/make.include: $(if $(wildcard $(PROCESSOR)/lib/libxil_init.a),$(PROCESSOR)/lib/libxil.a,) 23 | @echo "Running Make include in $(subst /make.include,,$@)" 24 | $(MAKE) -C $(subst /make.include,,$@) -s include "SHELL=$(SHELL)" "COMPILER=arm-xilinx-eabi-gcc" "ARCHIVER=arm-xilinx-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-g" 25 | 26 | %/make.libs: include 27 | @echo "Running Make libs in $(subst /make.libs,,$@)" 28 | $(MAKE) -C $(subst /make.libs,,$@) -s libs "SHELL=$(SHELL)" "COMPILER=arm-xilinx-eabi-gcc" "ARCHIVER=arm-xilinx-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-g" 29 | 30 | clean: 31 | rm -f ${PROCESSOR}/lib/libxil.a 32 | -------------------------------------------------------------------------------- /Projects/hdmi_out/sdk/displaydemo_bsp/Makefile: -------------------------------------------------------------------------------- 1 | # Makefile generated by Xilinx. 2 | 3 | PROCESSOR = ps7_cortexa9_0 4 | LIBRARIES = ${PROCESSOR}/lib/libxil.a 5 | BSP_MAKEFILES := $(wildcard $(PROCESSOR)/libsrc/*/src/Makefile) 6 | SUBDIRS := $(patsubst %/Makefile, %, $(BSP_MAKEFILES)) 7 | 8 | ifneq (,$(findstring win,$(RDI_PLATFORM))) 9 | SHELL = CMD 10 | endif 11 | 12 | all: libs 13 | @echo 'Finished building libraries' 14 | 15 | include: $(addsuffix /make.include,$(SUBDIRS)) 16 | 17 | libs: $(addsuffix /make.libs,$(SUBDIRS)) 18 | 19 | $(PROCESSOR)/lib/libxil.a: $(PROCESSOR)/lib/libxil_init.a 20 | cp -f $< $@ 21 | 22 | %/make.include: $(if $(wildcard $(PROCESSOR)/lib/libxil_init.a),$(PROCESSOR)/lib/libxil.a,) 23 | @echo "Running Make include in $(subst /make.include,,$@)" 24 | $(MAKE) -C $(subst /make.include,,$@) -s include "SHELL=$(SHELL)" "COMPILER=arm-xilinx-eabi-gcc" "ARCHIVER=arm-xilinx-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-g" 25 | 26 | %/make.libs: include 27 | @echo "Running Make libs in $(subst /make.libs,,$@)" 28 | $(MAKE) -C $(subst /make.libs,,$@) -s libs "SHELL=$(SHELL)" "COMPILER=arm-xilinx-eabi-gcc" "ARCHIVER=arm-xilinx-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-g" 29 | 30 | clean: 31 | rm -f ${PROCESSOR}/lib/libxil.a 32 | -------------------------------------------------------------------------------- /Projects/linux_bd/repo/vivado-library/ip/rgb2dpvid_v1_0/xgui/rgb2dpvid_v1_0.tcl: -------------------------------------------------------------------------------- 1 | # Definitional proc to organize widgets for parameters. 2 | proc init_gui { IPINST } { 3 | set Component_Name [ ipgui::add_param $IPINST -name "Component_Name" -display_name {Component Name}] 4 | set_property tooltip {Component Name} ${Component_Name} 5 | #Adding Page 6 | set Page_0 [ ipgui::add_page $IPINST -name "Page 0" -display_name {Page 0}] 7 | set_property tooltip {Page 0} ${Page_0} 8 | set kDataWidth [ ipgui::add_param $IPINST -name "kDataWidth" -parent ${Page_0} -display_name {Input Data Width}] 9 | set_property tooltip {Input Data Width} ${kDataWidth} 10 | 11 | 12 | } 13 | 14 | proc update_PARAM_VALUE.kDataWidth { PARAM_VALUE.kDataWidth } { 15 | # Procedure called to update kDataWidth when any of the dependent parameters in the arguments change 16 | } 17 | 18 | proc validate_PARAM_VALUE.kDataWidth { PARAM_VALUE.kDataWidth } { 19 | # Procedure called to validate kDataWidth 20 | return true 21 | } 22 | 23 | 24 | proc update_MODELPARAM_VALUE.kDataWidth { MODELPARAM_VALUE.kDataWidth PARAM_VALUE.kDataWidth } { 25 | # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value 26 | set_property value [get_property value ${PARAM_VALUE.kDataWidth}] ${MODELPARAM_VALUE.kDataWidth} 27 | } 28 | 29 | -------------------------------------------------------------------------------- /Projects/linux_bd/repo/vivado-library/ip/Pmods/PmodBT2_v1_0/drivers/PmodBT2_v1_0/examples/main.c: -------------------------------------------------------------------------------- 1 | #include "xparameters.h" 2 | //#include "xil_types.h" 3 | //#include "xil_io.h" 4 | 5 | #include "xil_cache.h" 6 | #include "PmodBT2.h" 7 | 8 | #define BUFFERSIZE 8 9 | 10 | void DemoInitialize(); 11 | void DemoRun(); 12 | 13 | void recv(PmodBT2* InstancePtr); 14 | void send(PmodBT2* InstancePtr); 15 | 16 | PmodBT2 BT2; 17 | 18 | 19 | int main(void) 20 | { 21 | Xil_ICacheEnable(); 22 | Xil_DCacheEnable(); 23 | 24 | DemoInitialize(); 25 | DemoRun(); 26 | return 0; 27 | } 28 | 29 | void DemoInitialize() 30 | { 31 | BT2_begin(&BT2, XPAR_PMODBT2_0_AXI_LITE_GPIO_BASEADDR, XPAR_PMODBT2_0_AXI_LITE_UART_BASEADDR); 32 | #ifndef NO_IRPT 33 | BT2_SetupInterruptSystem(&BT2, XPAR_INTC_0_PMODBT2_0_VEC_ID, recv, send); 34 | #endif 35 | } 36 | 37 | 38 | void DemoRun() 39 | { 40 | int len; 41 | 42 | BT2_getData(&BT2, BUFFERSIZE);//Start scanning for input 43 | while(1){ 44 | //Polled mode, if no interrupts 45 | /*if((len=BT2_getData(&BT2, BUFFERSIZE))){ 46 | BT2_sendData(&BT2, BT2.recv, len); 47 | }*/ 48 | } 49 | } 50 | 51 | void recv(PmodBT2* InstancePtr){ 52 | BT2_sendData(InstancePtr, BT2.recv, BUFFERSIZE);//Echo back through BT 53 | BT2_getData(&BT2, BUFFERSIZE);//Start scanning for next input 54 | } 55 | void send(PmodBT2* InstancePtr){ 56 | 57 | } 58 | -------------------------------------------------------------------------------- /Projects/dma/sdk/dma_bsp/Makefile: -------------------------------------------------------------------------------- 1 | # Makefile generated by Xilinx. 2 | 3 | PROCESSOR = ps7_cortexa9_0 4 | LIBRARIES = ${PROCESSOR}/lib/libxil.a 5 | BSP_MAKEFILES := $(wildcard $(PROCESSOR)/libsrc/*/src/Makefile) 6 | SUBDIRS := $(patsubst %/Makefile, %, $(BSP_MAKEFILES)) 7 | 8 | ifneq (,$(findstring win,$(RDI_PLATFORM))) 9 | SHELL = CMD 10 | endif 11 | 12 | all: libs 13 | @echo 'Finished building libraries' 14 | 15 | include: $(addsuffix /make.include,$(SUBDIRS)) 16 | 17 | libs: $(addsuffix /make.libs,$(SUBDIRS)) 18 | 19 | $(PROCESSOR)/lib/libxil.a: $(PROCESSOR)/lib/libxil_init.a 20 | cp -f $< $@ 21 | 22 | %/make.include: $(if $(wildcard $(PROCESSOR)/lib/libxil_init.a),$(PROCESSOR)/lib/libxil.a,) 23 | @echo "Running Make include in $(subst /make.include,,$@)" 24 | $(MAKE) -C $(subst /make.include,,$@) -s include "SHELL=$(SHELL)" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles" 25 | 26 | %/make.libs: include 27 | @echo "Running Make libs in $(subst /make.libs,,$@)" 28 | $(MAKE) -C $(subst /make.libs,,$@) -s libs "SHELL=$(SHELL)" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles" 29 | 30 | clean: 31 | rm -f ${PROCESSOR}/lib/libxil.a 32 | -------------------------------------------------------------------------------- /Projects/linux_bd/repo/vivado-library/ip/Pmods/PmodAMP2_v1_0/drivers/PmodAMP2_v1_0/examples/main.c: -------------------------------------------------------------------------------- 1 | #include "xil_cache.h" 2 | #include "xparameters.h" 3 | #include "PmodAMP2.h" 4 | 5 | void DemoInitialize(); 6 | void DemoRun(); 7 | void AMP2_interruptHandler(PmodAMP2* InstancePtr); 8 | PmodAMP2 AMP2; 9 | bool rise; 10 | 11 | int main(void) 12 | { 13 | Xil_ICacheEnable(); 14 | Xil_DCacheEnable(); 15 | 16 | DemoInitialize(); 17 | DemoRun(); 18 | return 0; 19 | } 20 | 21 | void DemoInitialize() 22 | { 23 | AMP2_begin(&2, XPAR_PMODAMP2_0_GPIO_AXI_BASEADDR, XPAR_PMODAMP2_0_PWM_AXI_BASEADDR); 24 | AMP2_setupInterrupt(&2, XPAR_AXI_INTC_0_DEVICE_ID, AMP2_interruptHandler); 25 | } 26 | 27 | 28 | void DemoRun() 29 | { 30 | //int i=0; 31 | while(1){ 32 | /*for (i=0; i<4096; i++) 33 | { 34 | AMP2_setPWM(&2, i); 35 | } 36 | for (i=4096; i>=0;i--) 37 | { 38 | AMP2_setPWM(&2, i); 39 | }*/ 40 | 41 | } 42 | 43 | } 44 | 45 | //Triggers after every PWM window 46 | //Basic function that creates a triangle wave 47 | void AMP2_interruptHandler(PmodAMP2* InstancePtr){ 48 | int duty=Xil_In32(InstancePtr->PWM_addr); 49 | if (duty >= Xil_In32(InstancePtr->PWM_addr+4)){ 50 | rise=0; 51 | } 52 | else if (duty==0){ 53 | rise=1; 54 | } 55 | if (rise)Xil_Out32(InstancePtr->PWM_addr, duty+175); 56 | else Xil_Out32(InstancePtr->PWM_addr, duty-175); 57 | } 58 | -------------------------------------------------------------------------------- /Projects/linux_bd/repo/vivado-library/ip/Pmods/PmodAMP2_v1_0/drivers/PmodAMP2_v1_0/src/PmodAMP2.h: -------------------------------------------------------------------------------- 1 | 2 | #ifndef PMODAMP2_H 3 | #define PMODAMP2_H 4 | 5 | 6 | /****************** Include Files ********************/ 7 | #include "xil_types.h" 8 | #include "xstatus.h" 9 | #include "xparameters.h" 10 | 11 | #ifdef XPAR_XINTC_NUM_INSTANCES 12 | #include "xintc.h" 13 | #define INTC XIntc 14 | #define INTC_HANDLER XIntc_InterruptHandler 15 | #else 16 | #ifdef XPAR_SCUGIC_0_DEVICE_ID 17 | #include "xscugic.h" 18 | #define INTC XScuGic 19 | #define INTC_HANDLER XScuGic_InterruptHandler 20 | #else 21 | #define NO_IRPT 1 22 | #endif 23 | #endif 24 | /* ------------------------------------------------------------ */ 25 | /* Definitions */ 26 | /* ------------------------------------------------------------ */ 27 | #define bool u8 28 | #define true 1 29 | #define false 0 30 | 31 | 32 | 33 | 34 | /* ------------------------------------------------------------ */ 35 | /* Procedure Declarations */ 36 | /* ------------------------------------------------------------ */ 37 | 38 | typedef struct PmodAMP2{ 39 | u32 GPIO_addr; 40 | u32 PWM_addr; 41 | #ifndef NO_IRPT 42 | INTC intc; 43 | #endif 44 | }PmodAMP2; 45 | 46 | int AMP2_setupInterrupt(PmodAMP2* InstancePtr, u32 interruptID, void* handlerFunction); 47 | void AMP2_begin(PmodAMP2* InstancePtr, u32 GPIO_Address, u32 PWM_Address); 48 | void AMP2_setPWM(PmodAMP2* InstancePtr,int duty); 49 | 50 | 51 | 52 | 53 | 54 | #endif // PMODAMP2_H 55 | -------------------------------------------------------------------------------- /Projects/linux_bd/repo/vivado-library/ip/Pmods/PmodALS_v1_0/drivers/PmodALS_v1_0/src/PmodALS.h: -------------------------------------------------------------------------------- 1 | 2 | #ifndef PMODALS_H 3 | #define PMODALS_H 4 | 5 | 6 | /****************** Include Files ********************/ 7 | #include "xil_types.h" 8 | #include "xstatus.h" 9 | #include "xspi_l.h" 10 | #include "xspi.h" 11 | 12 | /* ------------------------------------------------------------ */ 13 | /* Definitions */ 14 | /* ------------------------------------------------------------ */ 15 | #define bool u8 16 | #define true 1 17 | #define false 0 18 | 19 | 20 | /* ------------------------------------------------------------ */ 21 | /* Register addresses Definitions */ 22 | /* ------------------------------------------------------------ */ 23 | 24 | /* ------------------------------------------------------------ */ 25 | /* Bit masks Definitions */ 26 | /* ------------------------------------------------------------ */ 27 | 28 | 29 | /* ------------------------------------------------------------ */ 30 | /* Parameters Definitions */ 31 | /* ------------------------------------------------------------ */ 32 | 33 | 34 | 35 | /* ------------------------------------------------------------ */ 36 | /* Procedure Declarations */ 37 | /* ------------------------------------------------------------ */ 38 | 39 | typedef struct PmodALS{ 40 | XSpi ALSSpi; 41 | }PmodALS; 42 | 43 | void ALS_begin(PmodALS* InstancePtr, u32 SPI_Address); 44 | int ALS_SPIInit(XSpi *SpiInstancePtr); 45 | u8 ALS_read(PmodALS* InstancePtr); 46 | 47 | 48 | 49 | 50 | 51 | #endif // PMODALS_H 52 | -------------------------------------------------------------------------------- /Projects/linux_bd/repo/vivado-library/ip/Pmods/Pmod_Bridge_v1_0/utils/board/board.xit: -------------------------------------------------------------------------------- 1 | package require xilinx::board 1.0 2 | namespace import ::xilinx::board::* 3 | 4 | set instname [current_inst] 5 | set f_xdc [add_ipfile -usedIn [list synthesis implementation board ] -force ${instname}_board.xdc] 6 | puts_ipfile $f_xdc "#--------------------Physical Constraints-----------------\n" 7 | if { [get_project_property BOARD] == "" } { 8 | close_ipfile $f_xdc 9 | return 10 | } 11 | 12 | set board_if [get_property PARAM_VALUE.PMOD] 13 | if { $board_if ne "Custom"} { 14 | board_add_tri_state_port_constraints $f_xdc $board_if \ 15 | PIN1_O out0_O\ 16 | PIN1_I out0_I\ 17 | PIN1_T out0_T 18 | board_add_tri_state_port_constraints $f_xdc $board_if \ 19 | PIN2_O out1_O\ 20 | PIN2_I out1_I\ 21 | PIN2_T out1_T 22 | board_add_tri_state_port_constraints $f_xdc $board_if \ 23 | PIN3_O out2_O\ 24 | PIN3_I out2_I\ 25 | PIN3_T out2_T 26 | board_add_tri_state_port_constraints $f_xdc $board_if \ 27 | PIN4_O out3_O\ 28 | PIN4_I out3_I\ 29 | PIN4_T out3_T 30 | board_add_tri_state_port_constraints $f_xdc $board_if \ 31 | PIN7_O out4_O\ 32 | PIN7_I out4_I\ 33 | PIN7_T out4_T 34 | board_add_tri_state_port_constraints $f_xdc $board_if \ 35 | PIN8_O out5_O\ 36 | PIN8_I out5_I\ 37 | PIN8_T out5_T 38 | board_add_tri_state_port_constraints $f_xdc $board_if \ 39 | PIN9_O out6_O\ 40 | PIN9_I out6_I\ 41 | PIN9_T out6_T 42 | board_add_tri_state_port_constraints $f_xdc $board_if \ 43 | PIN10_O out7_O\ 44 | PIN10_I out7_I\ 45 | PIN10_T out7_T 46 | } 47 | close_ipfile $f_xdc 48 | -------------------------------------------------------------------------------- /Projects/linux_bd/repo/vivado-library/ip/Pmods/PmodGPS_v1_1/drivers/PmodGPS_v1_1/examples/main.c: -------------------------------------------------------------------------------- 1 | #include "xparameters.h" 2 | #include "xil_cache.h" 3 | #include "PmodGPS.h" 4 | 5 | void DemoInitialize(); 6 | void DemoRun(); 7 | 8 | PmodGPS GPS; 9 | 10 | int main(void) 11 | { 12 | Xil_ICacheEnable(); 13 | Xil_DCacheEnable(); 14 | 15 | DemoInitialize(); 16 | DemoRun(); 17 | return 0; 18 | } 19 | 20 | void DemoInitialize() 21 | { 22 | GPS_begin(&GPS, XPAR_PMODGPS_0_AXI_LITE_GPIO_BASEADDR, XPAR_PMODGPS_0_AXI_LITE_UART_BASEADDR); 23 | #ifndef NO_IRPT //If there are interrupts 24 | //GPS_SetupInterruptSystem(&GPS,XPAR_INTC_0_DEVICE_ID, XPAR_INTC_0_PMODGPS_0_VEC_ID);//Set up interrupts, Microblaze System 25 | GPS_SetupInterruptSystem(&GPS, XPAR_PS7_SCUGIC_0_DEVICE_ID, XPAR_FABRIC_PMODGPS_0_GPS_UART_INTERRUPT_INTR);//Setup interrupts, Zynq 26 | #endif 27 | 28 | GPS_setUpdateRate(&GPS, 1000); 29 | } 30 | 31 | 32 | void DemoRun() 33 | { 34 | while(1){ 35 | 36 | #ifdef NO_IRPT //If no interrupts 37 | GPS_getData(&GPS);//Receive data from GPS in Polled Mode 38 | #endif 39 | if (GPS.ping==true){ 40 | GPS_formatSentence(&GPS); 41 | if (GPS_isFixed(&GPS)){ 42 | xil_printf("Latitude: %s\n\r",GPS_getLatitude(&GPS)); 43 | xil_printf("Longitude: %s\n\r",GPS_getLongitude(&GPS)); 44 | xil_printf("Altitude: %s\n\r",GPS_getAltitudeString(&GPS)); 45 | xil_printf("Number of Satellites: %d\n\n\r",GPS_getNumSats(&GPS)); 46 | } 47 | else{ 48 | xil_printf("Number of Satellites: %d\n\r", GPS_getNumSats(&GPS)); 49 | } 50 | GPS.ping=false; 51 | } 52 | } 53 | } 54 | 55 | 56 | -------------------------------------------------------------------------------- /Projects/hdmi_in/repo/digilent/ip/dvi2rgb_v1_6/docs/dat2txt.cpp: -------------------------------------------------------------------------------- 1 | /* 2 | Simple program to convert a dat file created with phoenix edid designer to 3 | a .txt file that can be used to define the contents of an EEPROM implemented in HDL 4 | */ 5 | 6 | #include 7 | #include 8 | #include 9 | #include 10 | #include 11 | using namespace std; 12 | 13 | #define INPUT_DAT_LOC "C:\\Change_me.dat" 14 | #define OUTPUT_TXT_LOC "C:\\Change_me.txt" 15 | 16 | #define MAX_LINE_CNT 256 17 | 18 | int main( int argc, char* argv[] ) 19 | { 20 | char lineBuf[MAX_LINE_CNT]; 21 | char *token; 22 | long int value; 23 | ifstream input_dat; 24 | ofstream output_txt; 25 | output_txt.open (OUTPUT_TXT_LOC); 26 | input_dat.open (INPUT_DAT_LOC); 27 | 28 | if (output_txt.fail()) 29 | { 30 | printf("\nfail\n"); 31 | return 1; 32 | } 33 | if (input_dat.fail()) 34 | { 35 | printf("\nfail\n"); 36 | return 1; 37 | } 38 | 39 | //Skip header 40 | input_dat.getline(lineBuf, MAX_LINE_CNT); 41 | input_dat.getline(lineBuf, MAX_LINE_CNT); 42 | input_dat.getline(lineBuf, MAX_LINE_CNT); 43 | 44 | for( int j=0 ; j < 8 ; j++) 45 | { 46 | 47 | input_dat.getline(lineBuf, MAX_LINE_CNT); 48 | 49 | //Discard address and "|" 50 | token = strtok(lineBuf, " \n\r"); 51 | token = strtok(NULL, " \n\r"); 52 | for (int i=0 ; i < 16 ; i++) 53 | { 54 | token = strtok(NULL, " \n\r"); 55 | if (token == NULL) 56 | { 57 | printf("error\n"); 58 | return 1; 59 | } 60 | value = strtol(token, NULL, 16); 61 | output_txt << std::bitset<8>(value) << '\n'; 62 | } 63 | } 64 | 65 | output_txt.close(); 66 | input_dat.close(); 67 | 68 | return 0; 69 | } 70 | -------------------------------------------------------------------------------- /Projects/sdsoc/repo/digilent/ip/dvi2rgb_v1_6/docs/dat2txt.cpp: -------------------------------------------------------------------------------- 1 | /* 2 | Simple program to convert a dat file created with phoenix edid designer to 3 | a .txt file that can be used to define the contents of an EEPROM implemented in HDL 4 | */ 5 | 6 | #include 7 | #include 8 | #include 9 | #include 10 | #include 11 | using namespace std; 12 | 13 | #define INPUT_DAT_LOC "C:\\Change_me.dat" 14 | #define OUTPUT_TXT_LOC "C:\\Change_me.txt" 15 | 16 | #define MAX_LINE_CNT 256 17 | 18 | int main( int argc, char* argv[] ) 19 | { 20 | char lineBuf[MAX_LINE_CNT]; 21 | char *token; 22 | long int value; 23 | ifstream input_dat; 24 | ofstream output_txt; 25 | output_txt.open (OUTPUT_TXT_LOC); 26 | input_dat.open (INPUT_DAT_LOC); 27 | 28 | if (output_txt.fail()) 29 | { 30 | printf("\nfail\n"); 31 | return 1; 32 | } 33 | if (input_dat.fail()) 34 | { 35 | printf("\nfail\n"); 36 | return 1; 37 | } 38 | 39 | //Skip header 40 | input_dat.getline(lineBuf, MAX_LINE_CNT); 41 | input_dat.getline(lineBuf, MAX_LINE_CNT); 42 | input_dat.getline(lineBuf, MAX_LINE_CNT); 43 | 44 | for( int j=0 ; j < 8 ; j++) 45 | { 46 | 47 | input_dat.getline(lineBuf, MAX_LINE_CNT); 48 | 49 | //Discard address and "|" 50 | token = strtok(lineBuf, " \n\r"); 51 | token = strtok(NULL, " \n\r"); 52 | for (int i=0 ; i < 16 ; i++) 53 | { 54 | token = strtok(NULL, " \n\r"); 55 | if (token == NULL) 56 | { 57 | printf("error\n"); 58 | return 1; 59 | } 60 | value = strtol(token, NULL, 16); 61 | output_txt << std::bitset<8>(value) << '\n'; 62 | } 63 | } 64 | 65 | output_txt.close(); 66 | input_dat.close(); 67 | 68 | return 0; 69 | } 70 | -------------------------------------------------------------------------------- /Projects/dma/repo/local/ip/d_axi_i2s_audio_v2_0/src/Div_by_4.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------------------------- 2 | -- Company: 3 | -- Engineer: 4 | -- 5 | -- Create Date: 15:49:17 04/02/2014 6 | -- Design Name: 7 | -- Module Name: Div_by_4 - Behavioral 8 | -- Project Name: 9 | -- Target Devices: 10 | -- Tool versions: 11 | -- Description: 12 | -- 13 | -- Dependencies: 14 | -- 15 | -- Revision: 16 | -- Revision 0.01 - File Created 17 | -- Additional Comments: 18 | -- 19 | ---------------------------------------------------------------------------------- 20 | library IEEE; 21 | use IEEE.STD_LOGIC_1164.ALL; 22 | 23 | -- Uncomment the following library declaration if using 24 | -- arithmetic functions with Signed or Unsigned values 25 | --use IEEE.NUMERIC_STD.ALL; 26 | 27 | -- Uncomment the following library declaration if instantiating 28 | -- any Xilinx primitives in this code. 29 | --library UNISIM; 30 | --use UNISIM.VComponents.all; 31 | 32 | entity Div_by_4 is 33 | Port 34 | ( 35 | CE_I : in STD_LOGIC; 36 | CLK_I : in STD_LOGIC; 37 | DIV_O : out STD_LOGIC 38 | ); 39 | end Div_by_4; 40 | 41 | architecture Behavioral of Div_by_4 is 42 | 43 | signal cnt : integer range 0 to 2 :=0; 44 | signal clk_div : STD_LOGIC := '0'; 45 | 46 | begin 47 | 48 | process (CLK_I) 49 | begin 50 | if (CLK_I'event and CLK_I = '1') then 51 | if (CE_I = '1') then 52 | cnt <= cnt + 1; 53 | if cnt = 2 then 54 | cnt <= 0; 55 | clk_div <= not clk_div; 56 | end if; 57 | else 58 | cnt <= 0; 59 | end if; 60 | end if; 61 | end process; 62 | 63 | DIV_O <= clk_div; 64 | 65 | end Behavioral; 66 | 67 | -------------------------------------------------------------------------------- /Projects/linux_bd/repo/vivado-library/ip/dvi2rgb_v1_6/docs/dat2txt.cpp: -------------------------------------------------------------------------------- 1 | /* 2 | Simple program to convert a dat file created with phoenix edid designer to 3 | a .txt file that can be used to define the contents of an EEPROM implemented in HDL 4 | */ 5 | 6 | #include 7 | #include 8 | #include 9 | #include 10 | #include 11 | using namespace std; 12 | 13 | #define INPUT_DAT_LOC "C:\\Change_me.dat" 14 | #define OUTPUT_TXT_LOC "C:\\Change_me.txt" 15 | 16 | #define MAX_LINE_CNT 256 17 | 18 | int main( int argc, char* argv[] ) 19 | { 20 | char lineBuf[MAX_LINE_CNT]; 21 | char *token; 22 | long int value; 23 | ifstream input_dat; 24 | ofstream output_txt; 25 | output_txt.open (OUTPUT_TXT_LOC); 26 | input_dat.open (INPUT_DAT_LOC); 27 | 28 | if (output_txt.fail()) 29 | { 30 | printf("\nfail\n"); 31 | return 1; 32 | } 33 | if (input_dat.fail()) 34 | { 35 | printf("\nfail\n"); 36 | return 1; 37 | } 38 | 39 | //Skip header 40 | input_dat.getline(lineBuf, MAX_LINE_CNT); 41 | input_dat.getline(lineBuf, MAX_LINE_CNT); 42 | input_dat.getline(lineBuf, MAX_LINE_CNT); 43 | 44 | for( int j=0 ; j < 8 ; j++) 45 | { 46 | 47 | input_dat.getline(lineBuf, MAX_LINE_CNT); 48 | 49 | //Discard address and "|" 50 | token = strtok(lineBuf, " \n\r"); 51 | token = strtok(NULL, " \n\r"); 52 | for (int i=0 ; i < 16 ; i++) 53 | { 54 | token = strtok(NULL, " \n\r"); 55 | if (token == NULL) 56 | { 57 | printf("error\n"); 58 | return 1; 59 | } 60 | value = strtol(token, NULL, 16); 61 | output_txt << std::bitset<8>(value) << '\n'; 62 | } 63 | } 64 | 65 | output_txt.close(); 66 | input_dat.close(); 67 | 68 | return 0; 69 | } 70 | -------------------------------------------------------------------------------- /Projects/linux_bd/repo/vivado-library/ip/Pmods/PmodBT2_v1_0/drivers/PmodBT2_v1_0/src/PmodBT2.h: -------------------------------------------------------------------------------- 1 | 2 | #ifndef PMODBT2_H 3 | #define PMODBT2_H 4 | 5 | 6 | /****************** Include Files ********************/ 7 | #include "xil_types.h" 8 | #include "xstatus.h" 9 | #include "xuartlite_l.h" 10 | #include "xuartlite.h" 11 | #include "xparameters.h" 12 | 13 | #ifdef XPAR_XINTC_NUM_INSTANCES 14 | #include "xintc.h" 15 | #define INTC XIntc 16 | #define INTC_HANDLER XIntc_InterruptHandler 17 | #else 18 | #ifdef XPAR_SCUGIC_0_DEVICE_ID 19 | #include "xscugic.h" 20 | #define INTC XScuGic 21 | #define INTC_HANDLER XScuGic_InterruptHandler 22 | #else 23 | #define NO_IRPT 1 24 | #endif 25 | #endif 26 | 27 | /* ------------------------------------------------------------ */ 28 | /* Definitions */ 29 | /* ------------------------------------------------------------ */ 30 | #define bool u8 31 | #define true 1 32 | #define false 0 33 | 34 | 35 | /* ------------------------------------------------------------ */ 36 | /* Procedure Declarations */ 37 | /* ------------------------------------------------------------ */ 38 | 39 | typedef struct PmodBT2{ 40 | u32 GPIO_addr; 41 | #ifndef NO_IRPT 42 | INTC intc; 43 | #endif 44 | XUartLite BT2Uart; 45 | char recv[8]; 46 | 47 | }PmodBT2; 48 | 49 | void BT2_begin(PmodBT2* InstancePtr, u32 GPIO_Address, u32 UART_Address); 50 | int BT2_UARTInit(XUartLite *UartInstancePtr); 51 | int BT2_getData(PmodBT2* InstancePtr, int buffersize); 52 | int BT2_sendData(PmodBT2* InstancePtr, char* sendData, int size); 53 | int BT2_SetupInterruptSystem(PmodBT2* InstancePtr, u32 interruptID, void* receiveHandlerFunction, void* sendHandlerFunction); 54 | 55 | 56 | #endif // PMODBT2_H 57 | -------------------------------------------------------------------------------- /Projects/linux_bd/repo/vivado-library/ip/Pmods/PmodACL_v1_0/utils/board/board.xit: -------------------------------------------------------------------------------- 1 | package require xilinx::board 1.0 2 | namespace import ::xilinx::board::* 3 | 4 | set instname [current_inst] 5 | set f_xdc [add_ipfile -usedIn [list synthesis implementation board ] -force ${instname}_board.xdc] 6 | puts_ipfile $f_xdc "#--------------------Physical Constraints-----------------\n" 7 | if { [get_project_property BOARD] == "" } { 8 | close_ipfile $f_xdc 9 | return 10 | } 11 | 12 | set board_if [get_property PARAM_VALUE.PMOD] 13 | if { $board_if ne "Custom"} { 14 | board_add_tri_state_port_constraints $f_xdc $board_if \ 15 | PIN1_O Pmod_out_pin1_o\ 16 | PIN1_I Pmod_out_pin1_i\ 17 | PIN1_T Pmod_out_pin1_t 18 | board_add_tri_state_port_constraints $f_xdc $board_if \ 19 | PIN2_O Pmod_out_pin2_o\ 20 | PIN2_I Pmod_out_pin2_i\ 21 | PIN2_T Pmod_out_pin2_t 22 | board_add_tri_state_port_constraints $f_xdc $board_if \ 23 | PIN3_O Pmod_out_pin3_o\ 24 | PIN3_I Pmod_out_pin3_i\ 25 | PIN3_T Pmod_out_pin3_t 26 | board_add_tri_state_port_constraints $f_xdc $board_if \ 27 | PIN4_O Pmod_out_pin4_o\ 28 | PIN4_I Pmod_out_pin4_i\ 29 | PIN4_T Pmod_out_pin4_t 30 | board_add_tri_state_port_constraints $f_xdc $board_if \ 31 | PIN7_O Pmod_out_pin7_o\ 32 | PIN7_I Pmod_out_pin7_i\ 33 | PIN7_T Pmod_out_pin7_t 34 | board_add_tri_state_port_constraints $f_xdc $board_if \ 35 | PIN8_O Pmod_out_pin8_o\ 36 | PIN8_I Pmod_out_pin8_i\ 37 | PIN8_T Pmod_out_pin8_t 38 | board_add_tri_state_port_constraints $f_xdc $board_if \ 39 | PIN9_O Pmod_out_pin9_o\ 40 | PIN9_I Pmod_out_pin9_i\ 41 | PIN9_T Pmod_out_pin9_t 42 | board_add_tri_state_port_constraints $f_xdc $board_if \ 43 | PIN10_O Pmod_out_pin10_o\ 44 | PIN10_I Pmod_out_pin10_i\ 45 | PIN10_T Pmod_out_pin10_t 46 | } 47 | close_ipfile $f_xdc 48 | -------------------------------------------------------------------------------- /Projects/linux_bd/repo/vivado-library/ip/Pmods/PmodALS_v1_0/utils/board/board.xit: -------------------------------------------------------------------------------- 1 | package require xilinx::board 1.0 2 | namespace import ::xilinx::board::* 3 | 4 | set instname [current_inst] 5 | set f_xdc [add_ipfile -usedIn [list synthesis implementation board ] -force ${instname}_board.xdc] 6 | puts_ipfile $f_xdc "#--------------------Physical Constraints-----------------\n" 7 | if { [get_project_property BOARD] == "" } { 8 | close_ipfile $f_xdc 9 | return 10 | } 11 | 12 | set board_if [get_property PARAM_VALUE.PMOD] 13 | if { $board_if ne "Custom"} { 14 | board_add_tri_state_port_constraints $f_xdc $board_if \ 15 | PIN1_O Pmod_out_pin1_o\ 16 | PIN1_I Pmod_out_pin1_i\ 17 | PIN1_T Pmod_out_pin1_t 18 | board_add_tri_state_port_constraints $f_xdc $board_if \ 19 | PIN2_O Pmod_out_pin2_o\ 20 | PIN2_I Pmod_out_pin2_i\ 21 | PIN2_T Pmod_out_pin2_t 22 | board_add_tri_state_port_constraints $f_xdc $board_if \ 23 | PIN3_O Pmod_out_pin3_o\ 24 | PIN3_I Pmod_out_pin3_i\ 25 | PIN3_T Pmod_out_pin3_t 26 | board_add_tri_state_port_constraints $f_xdc $board_if \ 27 | PIN4_O Pmod_out_pin4_o\ 28 | PIN4_I Pmod_out_pin4_i\ 29 | PIN4_T Pmod_out_pin4_t 30 | board_add_tri_state_port_constraints $f_xdc $board_if \ 31 | PIN7_O Pmod_out_pin7_o\ 32 | PIN7_I Pmod_out_pin7_i\ 33 | PIN7_T Pmod_out_pin7_t 34 | board_add_tri_state_port_constraints $f_xdc $board_if \ 35 | PIN8_O Pmod_out_pin8_o\ 36 | PIN8_I Pmod_out_pin8_i\ 37 | PIN8_T Pmod_out_pin8_t 38 | board_add_tri_state_port_constraints $f_xdc $board_if \ 39 | PIN9_O Pmod_out_pin9_o\ 40 | PIN9_I Pmod_out_pin9_i\ 41 | PIN9_T Pmod_out_pin9_t 42 | board_add_tri_state_port_constraints $f_xdc $board_if \ 43 | PIN10_O Pmod_out_pin10_o\ 44 | PIN10_I Pmod_out_pin10_i\ 45 | PIN10_T Pmod_out_pin10_t 46 | } 47 | close_ipfile $f_xdc 48 | -------------------------------------------------------------------------------- /Projects/linux_bd/repo/vivado-library/ip/Pmods/PmodAMP2_v1_0/utils/board/board.xit: -------------------------------------------------------------------------------- 1 | package require xilinx::board 1.0 2 | namespace import ::xilinx::board::* 3 | 4 | set instname [current_inst] 5 | set f_xdc [add_ipfile -usedIn [list synthesis implementation board ] -force ${instname}_board.xdc] 6 | puts_ipfile $f_xdc "#--------------------Physical Constraints-----------------\n" 7 | if { [get_project_property BOARD] == "" } { 8 | close_ipfile $f_xdc 9 | return 10 | } 11 | 12 | set board_if [get_property PARAM_VALUE.PMOD] 13 | if { $board_if ne "Custom"} { 14 | board_add_tri_state_port_constraints $f_xdc $board_if \ 15 | PIN1_O Pmod_out_pin1_o\ 16 | PIN1_I Pmod_out_pin1_i\ 17 | PIN1_T Pmod_out_pin1_t 18 | board_add_tri_state_port_constraints $f_xdc $board_if \ 19 | PIN2_O Pmod_out_pin2_o\ 20 | PIN2_I Pmod_out_pin2_i\ 21 | PIN2_T Pmod_out_pin2_t 22 | board_add_tri_state_port_constraints $f_xdc $board_if \ 23 | PIN3_O Pmod_out_pin3_o\ 24 | PIN3_I Pmod_out_pin3_i\ 25 | PIN3_T Pmod_out_pin3_t 26 | board_add_tri_state_port_constraints $f_xdc $board_if \ 27 | PIN4_O Pmod_out_pin4_o\ 28 | PIN4_I Pmod_out_pin4_i\ 29 | PIN4_T Pmod_out_pin4_t 30 | board_add_tri_state_port_constraints $f_xdc $board_if \ 31 | PIN7_O Pmod_out_pin7_o\ 32 | PIN7_I Pmod_out_pin7_i\ 33 | PIN7_T Pmod_out_pin7_t 34 | board_add_tri_state_port_constraints $f_xdc $board_if \ 35 | PIN8_O Pmod_out_pin8_o\ 36 | PIN8_I Pmod_out_pin8_i\ 37 | PIN8_T Pmod_out_pin8_t 38 | board_add_tri_state_port_constraints $f_xdc $board_if \ 39 | PIN9_O Pmod_out_pin9_o\ 40 | PIN9_I Pmod_out_pin9_i\ 41 | PIN9_T Pmod_out_pin9_t 42 | board_add_tri_state_port_constraints $f_xdc $board_if \ 43 | PIN10_O Pmod_out_pin10_o\ 44 | PIN10_I Pmod_out_pin10_i\ 45 | PIN10_T Pmod_out_pin10_t 46 | } 47 | close_ipfile $f_xdc 48 | -------------------------------------------------------------------------------- /Projects/linux_bd/repo/vivado-library/ip/Pmods/PmodBT2_v1_0/utils/board/board.xit: -------------------------------------------------------------------------------- 1 | package require xilinx::board 1.0 2 | namespace import ::xilinx::board::* 3 | 4 | set instname [current_inst] 5 | set f_xdc [add_ipfile -usedIn [list synthesis implementation board ] -force ${instname}_board.xdc] 6 | puts_ipfile $f_xdc "#--------------------Physical Constraints-----------------\n" 7 | if { [get_project_property BOARD] == "" } { 8 | close_ipfile $f_xdc 9 | return 10 | } 11 | 12 | set board_if [get_property PARAM_VALUE.PMOD] 13 | if { $board_if ne "Custom"} { 14 | board_add_tri_state_port_constraints $f_xdc $board_if \ 15 | PIN1_O Pmod_out_pin1_o\ 16 | PIN1_I Pmod_out_pin1_i\ 17 | PIN1_T Pmod_out_pin1_t 18 | board_add_tri_state_port_constraints $f_xdc $board_if \ 19 | PIN2_O Pmod_out_pin2_o\ 20 | PIN2_I Pmod_out_pin2_i\ 21 | PIN2_T Pmod_out_pin2_t 22 | board_add_tri_state_port_constraints $f_xdc $board_if \ 23 | PIN3_O Pmod_out_pin3_o\ 24 | PIN3_I Pmod_out_pin3_i\ 25 | PIN3_T Pmod_out_pin3_t 26 | board_add_tri_state_port_constraints $f_xdc $board_if \ 27 | PIN4_O Pmod_out_pin4_o\ 28 | PIN4_I Pmod_out_pin4_i\ 29 | PIN4_T Pmod_out_pin4_t 30 | board_add_tri_state_port_constraints $f_xdc $board_if \ 31 | PIN7_O Pmod_out_pin7_o\ 32 | PIN7_I Pmod_out_pin7_i\ 33 | PIN7_T Pmod_out_pin7_t 34 | board_add_tri_state_port_constraints $f_xdc $board_if \ 35 | PIN8_O Pmod_out_pin8_o\ 36 | PIN8_I Pmod_out_pin8_i\ 37 | PIN8_T Pmod_out_pin8_t 38 | board_add_tri_state_port_constraints $f_xdc $board_if \ 39 | PIN9_O Pmod_out_pin9_o\ 40 | PIN9_I Pmod_out_pin9_i\ 41 | PIN9_T Pmod_out_pin9_t 42 | board_add_tri_state_port_constraints $f_xdc $board_if \ 43 | PIN10_O Pmod_out_pin10_o\ 44 | PIN10_I Pmod_out_pin10_i\ 45 | PIN10_T Pmod_out_pin10_t 46 | } 47 | close_ipfile $f_xdc 48 | -------------------------------------------------------------------------------- /Projects/linux_bd/repo/vivado-library/ip/Pmods/PmodGPS_v1_1/utils/board/board.xit: -------------------------------------------------------------------------------- 1 | package require xilinx::board 1.0 2 | namespace import ::xilinx::board::* 3 | 4 | set instname [current_inst] 5 | set f_xdc [add_ipfile -usedIn [list synthesis implementation board ] -force ${instname}_board.xdc] 6 | puts_ipfile $f_xdc "#--------------------Physical Constraints-----------------\n" 7 | if { [get_project_property BOARD] == "" } { 8 | close_ipfile $f_xdc 9 | return 10 | } 11 | 12 | set board_if [get_property PARAM_VALUE.PMOD] 13 | if { $board_if ne "Custom"} { 14 | board_add_tri_state_port_constraints $f_xdc $board_if \ 15 | PIN1_O Pmod_out_pin1_o\ 16 | PIN1_I Pmod_out_pin1_i\ 17 | PIN1_T Pmod_out_pin1_t 18 | board_add_tri_state_port_constraints $f_xdc $board_if \ 19 | PIN2_O Pmod_out_pin2_o\ 20 | PIN2_I Pmod_out_pin2_i\ 21 | PIN2_T Pmod_out_pin2_t 22 | board_add_tri_state_port_constraints $f_xdc $board_if \ 23 | PIN3_O Pmod_out_pin3_o\ 24 | PIN3_I Pmod_out_pin3_i\ 25 | PIN3_T Pmod_out_pin3_t 26 | board_add_tri_state_port_constraints $f_xdc $board_if \ 27 | PIN4_O Pmod_out_pin4_o\ 28 | PIN4_I Pmod_out_pin4_i\ 29 | PIN4_T Pmod_out_pin4_t 30 | board_add_tri_state_port_constraints $f_xdc $board_if \ 31 | PIN7_O Pmod_out_pin7_o\ 32 | PIN7_I Pmod_out_pin7_i\ 33 | PIN7_T Pmod_out_pin7_t 34 | board_add_tri_state_port_constraints $f_xdc $board_if \ 35 | PIN8_O Pmod_out_pin8_o\ 36 | PIN8_I Pmod_out_pin8_i\ 37 | PIN8_T Pmod_out_pin8_t 38 | board_add_tri_state_port_constraints $f_xdc $board_if \ 39 | PIN9_O Pmod_out_pin9_o\ 40 | PIN9_I Pmod_out_pin9_i\ 41 | PIN9_T Pmod_out_pin9_t 42 | board_add_tri_state_port_constraints $f_xdc $board_if \ 43 | PIN10_O Pmod_out_pin10_o\ 44 | PIN10_I Pmod_out_pin10_i\ 45 | PIN10_T Pmod_out_pin10_t 46 | } 47 | close_ipfile $f_xdc 48 | -------------------------------------------------------------------------------- /Projects/linux_bd/repo/vivado-library/ip/Pmods/pmodOLEDrgb_v1_0/utils/board/board.xit: -------------------------------------------------------------------------------- 1 | package require xilinx::board 1.0 2 | namespace import ::xilinx::board::* 3 | 4 | set instname [current_inst] 5 | set f_xdc [add_ipfile -usedIn [list synthesis implementation board ] -force ${instname}_board.xdc] 6 | puts_ipfile $f_xdc "#--------------------Physical Constraints-----------------\n" 7 | if { [get_project_property BOARD] == "" } { 8 | close_ipfile $f_xdc 9 | return 10 | } 11 | 12 | set board_if [get_property PARAM_VALUE.PMOD] 13 | if { $board_if ne "Custom"} { 14 | board_add_tri_state_port_constraints $f_xdc $board_if \ 15 | PIN1_O pmod_out_pin1_o\ 16 | PIN1_I pmod_out_pin1_i\ 17 | PIN1_T pmod_out_pin1_t 18 | board_add_tri_state_port_constraints $f_xdc $board_if \ 19 | PIN2_O pmod_out_pin2_o\ 20 | PIN2_I pmod_out_pin2_i\ 21 | PIN2_T pmod_out_pin2_t 22 | board_add_tri_state_port_constraints $f_xdc $board_if \ 23 | PIN3_O pmod_out_pin3_o\ 24 | PIN3_I pmod_out_pin3_i\ 25 | PIN3_T pmod_out_pin3_t 26 | board_add_tri_state_port_constraints $f_xdc $board_if \ 27 | PIN4_O pmod_out_pin4_o\ 28 | PIN4_I pmod_out_pin4_i\ 29 | PIN4_T pmod_out_pin4_t 30 | board_add_tri_state_port_constraints $f_xdc $board_if \ 31 | PIN7_O pmod_out_pin7_o\ 32 | PIN7_I pmod_out_pin7_i\ 33 | PIN7_T pmod_out_pin7_t 34 | board_add_tri_state_port_constraints $f_xdc $board_if \ 35 | PIN8_O pmod_out_pin8_o\ 36 | PIN8_I pmod_out_pin8_i\ 37 | PIN8_T pmod_out_pin8_t 38 | board_add_tri_state_port_constraints $f_xdc $board_if \ 39 | PIN9_O pmod_out_pin9_o\ 40 | PIN9_I pmod_out_pin9_i\ 41 | PIN9_T pmod_out_pin9_t 42 | board_add_tri_state_port_constraints $f_xdc $board_if \ 43 | PIN10_O pmod_out_pin10_o\ 44 | PIN10_I pmod_out_pin10_i\ 45 | PIN10_T pmod_out_pin10_t 46 | } 47 | close_ipfile $f_xdc 48 | -------------------------------------------------------------------------------- /Projects/hdmi_in/repo/digilent/ip/dvi2rgb_v1_6/src/1024_edid.txt: -------------------------------------------------------------------------------- 1 | 00000000 2 | 11111111 3 | 11111111 4 | 11111111 5 | 11111111 6 | 11111111 7 | 11111111 8 | 00000000 9 | 00010000 10 | 11101100 11 | 00000000 12 | 00000000 13 | 00000000 14 | 00000000 15 | 00000000 16 | 00000000 17 | 00000010 18 | 00011010 19 | 00000001 20 | 00000011 21 | 10100001 22 | 00110011 23 | 00011101 24 | 01111000 25 | 00001010 26 | 11101100 27 | 00011000 28 | 10100011 29 | 01010100 30 | 01000110 31 | 10011000 32 | 00100101 33 | 00001111 34 | 01001000 35 | 01001100 36 | 00100001 37 | 00001000 38 | 00000000 39 | 10110011 40 | 00000000 41 | 11010001 42 | 11000000 43 | 10000001 44 | 10000000 45 | 10000001 46 | 11000000 47 | 10101001 48 | 11000000 49 | 00000001 50 | 00000001 51 | 00000001 52 | 00000001 53 | 00000001 54 | 00000001 55 | 00110000 56 | 00101010 57 | 00000000 58 | 10011000 59 | 01010001 60 | 00000000 61 | 00101010 62 | 01000000 63 | 00110000 64 | 01110000 65 | 00010011 66 | 00000000 67 | 00000000 68 | 00000000 69 | 01010100 70 | 00000000 71 | 00000000 72 | 00011110 73 | 00000000 74 | 00000000 75 | 00000000 76 | 11111100 77 | 00100000 78 | 01000100 79 | 01101001 80 | 01100111 81 | 01101001 82 | 01101100 83 | 01100101 84 | 01101110 85 | 01110100 86 | 01000100 87 | 01010110 88 | 01001001 89 | 00101101 90 | 00110000 91 | 00000000 92 | 00000000 93 | 00000000 94 | 00010000 95 | 00000000 96 | 00000000 97 | 00000000 98 | 00000000 99 | 00000000 100 | 00000000 101 | 00000000 102 | 00000000 103 | 00000000 104 | 00000000 105 | 00000000 106 | 00000000 107 | 00000000 108 | 00000000 109 | 00000000 110 | 00000000 111 | 00000000 112 | 00010000 113 | 00000000 114 | 00000000 115 | 00000000 116 | 00000000 117 | 00000000 118 | 00000000 119 | 00000000 120 | 00000000 121 | 00000000 122 | 00000000 123 | 00000000 124 | 00000000 125 | 00000000 126 | 00000000 127 | 00000000 128 | 00111010 129 | -------------------------------------------------------------------------------- /Projects/hdmi_in/repo/digilent/ip/dvi2rgb_v1_6/src/1080_edid.txt: -------------------------------------------------------------------------------- 1 | 00000000 2 | 11111111 3 | 11111111 4 | 11111111 5 | 11111111 6 | 11111111 7 | 11111111 8 | 00000000 9 | 00010000 10 | 11101100 11 | 00000011 12 | 00000000 13 | 00000000 14 | 00000000 15 | 00000000 16 | 00000000 17 | 00000010 18 | 00011010 19 | 00000001 20 | 00000011 21 | 10100001 22 | 00110011 23 | 00011101 24 | 01111000 25 | 00001010 26 | 11101100 27 | 00011000 28 | 10100011 29 | 01010100 30 | 01000110 31 | 10011000 32 | 00100101 33 | 00001111 34 | 01001000 35 | 01001100 36 | 00100001 37 | 00001000 38 | 00000000 39 | 10110011 40 | 00000000 41 | 11010001 42 | 11000000 43 | 10000001 44 | 10000000 45 | 10000001 46 | 11000000 47 | 10101001 48 | 11000000 49 | 00000001 50 | 00000001 51 | 00000001 52 | 00000001 53 | 00000001 54 | 00000001 55 | 00000010 56 | 00111010 57 | 10000000 58 | 00011000 59 | 01110001 60 | 00111000 61 | 00101101 62 | 01000000 63 | 01011000 64 | 00101100 65 | 01000101 66 | 00000000 67 | 10000000 68 | 00111000 69 | 01110100 70 | 00000000 71 | 00000000 72 | 00011110 73 | 00000000 74 | 00000000 75 | 00000000 76 | 11111100 77 | 00100000 78 | 01000100 79 | 01101001 80 | 01100111 81 | 01101001 82 | 01101100 83 | 01100101 84 | 01101110 85 | 01110100 86 | 01000100 87 | 01010110 88 | 01001001 89 | 00101101 90 | 00110011 91 | 00000000 92 | 00000000 93 | 00000000 94 | 00010000 95 | 00000000 96 | 00000000 97 | 00000000 98 | 00000000 99 | 00000000 100 | 00000000 101 | 00000000 102 | 00000000 103 | 00000000 104 | 00000000 105 | 00000000 106 | 00000000 107 | 00000000 108 | 00000000 109 | 00000000 110 | 00000000 111 | 00000000 112 | 00010000 113 | 00000000 114 | 00000000 115 | 00000000 116 | 00000000 117 | 00000000 118 | 00000000 119 | 00000000 120 | 00000000 121 | 00000000 122 | 00000000 123 | 00000000 124 | 00000000 125 | 00000000 126 | 00000000 127 | 00000000 128 | 00001001 129 | -------------------------------------------------------------------------------- /Projects/hdmi_in/repo/digilent/ip/dvi2rgb_v1_6/src/720p_edid.txt: -------------------------------------------------------------------------------- 1 | 00000000 2 | 11111111 3 | 11111111 4 | 11111111 5 | 11111111 6 | 11111111 7 | 11111111 8 | 00000000 9 | 00010000 10 | 11101100 11 | 00000010 12 | 00000000 13 | 00000000 14 | 00000000 15 | 00000000 16 | 00000000 17 | 00000010 18 | 00011010 19 | 00000001 20 | 00000011 21 | 10100001 22 | 00110011 23 | 00011101 24 | 01111000 25 | 00001010 26 | 11101100 27 | 00011000 28 | 10100011 29 | 01010100 30 | 01000110 31 | 10011000 32 | 00100101 33 | 00001111 34 | 01001000 35 | 01001100 36 | 00100001 37 | 00001000 38 | 00000000 39 | 10110011 40 | 00000000 41 | 11010001 42 | 11000000 43 | 10000001 44 | 10000000 45 | 10000001 46 | 11000000 47 | 10101001 48 | 11000000 49 | 00000001 50 | 00000001 51 | 00000001 52 | 00000001 53 | 00000001 54 | 00000001 55 | 00000001 56 | 00011101 57 | 00000000 58 | 01110010 59 | 01010001 60 | 11010000 61 | 00011110 62 | 00100000 63 | 01101110 64 | 00101000 65 | 01010101 66 | 00000000 67 | 00000000 68 | 11010000 69 | 01010010 70 | 00000000 71 | 00000000 72 | 00011110 73 | 00000000 74 | 00000000 75 | 00000000 76 | 11111100 77 | 00100000 78 | 01000100 79 | 01101001 80 | 01100111 81 | 01101001 82 | 01101100 83 | 01100101 84 | 01101110 85 | 01110100 86 | 01000100 87 | 01010110 88 | 01001001 89 | 00101101 90 | 00110010 91 | 00000000 92 | 00000000 93 | 00000000 94 | 00010000 95 | 00000000 96 | 00000000 97 | 00000000 98 | 00000000 99 | 00000000 100 | 00000000 101 | 00000000 102 | 00000000 103 | 00000000 104 | 00000000 105 | 00000000 106 | 00000000 107 | 00000000 108 | 00000000 109 | 00000000 110 | 00000000 111 | 00000000 112 | 00010000 113 | 00000000 114 | 00000000 115 | 00000000 116 | 00000000 117 | 00000000 118 | 00000000 119 | 00000000 120 | 00000000 121 | 00000000 122 | 00000000 123 | 00000000 124 | 00000000 125 | 00000000 126 | 00000000 127 | 00000000 128 | 11101110 129 | -------------------------------------------------------------------------------- /Projects/hdmi_in/repo/digilent/ip/dvi2rgb_v1_6/src/900p_edid.txt: -------------------------------------------------------------------------------- 1 | 00000000 2 | 11111111 3 | 11111111 4 | 11111111 5 | 11111111 6 | 11111111 7 | 11111111 8 | 00000000 9 | 00010000 10 | 11101100 11 | 00000001 12 | 00000000 13 | 00000000 14 | 00000000 15 | 00000000 16 | 00000000 17 | 00000010 18 | 00011010 19 | 00000001 20 | 00000011 21 | 10100001 22 | 00110011 23 | 00011101 24 | 01111000 25 | 00001010 26 | 11101100 27 | 00011000 28 | 10100011 29 | 01010100 30 | 01000110 31 | 10011000 32 | 00100101 33 | 00001111 34 | 01001000 35 | 01001100 36 | 00100001 37 | 00001000 38 | 00000000 39 | 10110011 40 | 00000000 41 | 11010001 42 | 11000000 43 | 10000001 44 | 10000000 45 | 10000001 46 | 11000000 47 | 10101001 48 | 11000000 49 | 00000001 50 | 00000001 51 | 00000001 52 | 00000001 53 | 00000001 54 | 00000001 55 | 00101111 56 | 00100110 57 | 01000000 58 | 10100000 59 | 01100000 60 | 10000100 61 | 00011010 62 | 00110000 63 | 00110000 64 | 00100000 65 | 00110101 66 | 00000000 67 | 00000000 68 | 10000100 69 | 01010011 70 | 00000000 71 | 00000000 72 | 00011010 73 | 00000000 74 | 00000000 75 | 00000000 76 | 11111100 77 | 00100000 78 | 01000100 79 | 01101001 80 | 01100111 81 | 01101001 82 | 01101100 83 | 01100101 84 | 01101110 85 | 01110100 86 | 01000100 87 | 01010110 88 | 01001001 89 | 00101101 90 | 00110001 91 | 00000000 92 | 00000000 93 | 00000000 94 | 00010000 95 | 00000000 96 | 00000000 97 | 00000000 98 | 00000000 99 | 00000000 100 | 00000000 101 | 00000000 102 | 00000000 103 | 00000000 104 | 00000000 105 | 00000000 106 | 00000000 107 | 00000000 108 | 00000000 109 | 00000000 110 | 00000000 111 | 00000000 112 | 00010000 113 | 00000000 114 | 00000000 115 | 00000000 116 | 00000000 117 | 00000000 118 | 00000000 119 | 00000000 120 | 00000000 121 | 00000000 122 | 00000000 123 | 00000000 124 | 00000000 125 | 00000000 126 | 00000000 127 | 00000000 128 | 00110001 129 | -------------------------------------------------------------------------------- /Projects/sdsoc/repo/digilent/ip/dvi2rgb_v1_6/src/1024_edid.txt: -------------------------------------------------------------------------------- 1 | 00000000 2 | 11111111 3 | 11111111 4 | 11111111 5 | 11111111 6 | 11111111 7 | 11111111 8 | 00000000 9 | 00010000 10 | 11101100 11 | 00000000 12 | 00000000 13 | 00000000 14 | 00000000 15 | 00000000 16 | 00000000 17 | 00000010 18 | 00011010 19 | 00000001 20 | 00000011 21 | 10100001 22 | 00110011 23 | 00011101 24 | 01111000 25 | 00001010 26 | 11101100 27 | 00011000 28 | 10100011 29 | 01010100 30 | 01000110 31 | 10011000 32 | 00100101 33 | 00001111 34 | 01001000 35 | 01001100 36 | 00100001 37 | 00001000 38 | 00000000 39 | 10110011 40 | 00000000 41 | 11010001 42 | 11000000 43 | 10000001 44 | 10000000 45 | 10000001 46 | 11000000 47 | 10101001 48 | 11000000 49 | 00000001 50 | 00000001 51 | 00000001 52 | 00000001 53 | 00000001 54 | 00000001 55 | 00110000 56 | 00101010 57 | 00000000 58 | 10011000 59 | 01010001 60 | 00000000 61 | 00101010 62 | 01000000 63 | 00110000 64 | 01110000 65 | 00010011 66 | 00000000 67 | 00000000 68 | 00000000 69 | 01010100 70 | 00000000 71 | 00000000 72 | 00011110 73 | 00000000 74 | 00000000 75 | 00000000 76 | 11111100 77 | 00100000 78 | 01000100 79 | 01101001 80 | 01100111 81 | 01101001 82 | 01101100 83 | 01100101 84 | 01101110 85 | 01110100 86 | 01000100 87 | 01010110 88 | 01001001 89 | 00101101 90 | 00110000 91 | 00000000 92 | 00000000 93 | 00000000 94 | 00010000 95 | 00000000 96 | 00000000 97 | 00000000 98 | 00000000 99 | 00000000 100 | 00000000 101 | 00000000 102 | 00000000 103 | 00000000 104 | 00000000 105 | 00000000 106 | 00000000 107 | 00000000 108 | 00000000 109 | 00000000 110 | 00000000 111 | 00000000 112 | 00010000 113 | 00000000 114 | 00000000 115 | 00000000 116 | 00000000 117 | 00000000 118 | 00000000 119 | 00000000 120 | 00000000 121 | 00000000 122 | 00000000 123 | 00000000 124 | 00000000 125 | 00000000 126 | 00000000 127 | 00000000 128 | 00111010 129 | -------------------------------------------------------------------------------- /Projects/sdsoc/repo/digilent/ip/dvi2rgb_v1_6/src/1080_edid.txt: -------------------------------------------------------------------------------- 1 | 00000000 2 | 11111111 3 | 11111111 4 | 11111111 5 | 11111111 6 | 11111111 7 | 11111111 8 | 00000000 9 | 00010000 10 | 11101100 11 | 00000011 12 | 00000000 13 | 00000000 14 | 00000000 15 | 00000000 16 | 00000000 17 | 00000010 18 | 00011010 19 | 00000001 20 | 00000011 21 | 10100001 22 | 00110011 23 | 00011101 24 | 01111000 25 | 00001010 26 | 11101100 27 | 00011000 28 | 10100011 29 | 01010100 30 | 01000110 31 | 10011000 32 | 00100101 33 | 00001111 34 | 01001000 35 | 01001100 36 | 00100001 37 | 00001000 38 | 00000000 39 | 10110011 40 | 00000000 41 | 11010001 42 | 11000000 43 | 10000001 44 | 10000000 45 | 10000001 46 | 11000000 47 | 10101001 48 | 11000000 49 | 00000001 50 | 00000001 51 | 00000001 52 | 00000001 53 | 00000001 54 | 00000001 55 | 00000010 56 | 00111010 57 | 10000000 58 | 00011000 59 | 01110001 60 | 00111000 61 | 00101101 62 | 01000000 63 | 01011000 64 | 00101100 65 | 01000101 66 | 00000000 67 | 10000000 68 | 00111000 69 | 01110100 70 | 00000000 71 | 00000000 72 | 00011110 73 | 00000000 74 | 00000000 75 | 00000000 76 | 11111100 77 | 00100000 78 | 01000100 79 | 01101001 80 | 01100111 81 | 01101001 82 | 01101100 83 | 01100101 84 | 01101110 85 | 01110100 86 | 01000100 87 | 01010110 88 | 01001001 89 | 00101101 90 | 00110011 91 | 00000000 92 | 00000000 93 | 00000000 94 | 00010000 95 | 00000000 96 | 00000000 97 | 00000000 98 | 00000000 99 | 00000000 100 | 00000000 101 | 00000000 102 | 00000000 103 | 00000000 104 | 00000000 105 | 00000000 106 | 00000000 107 | 00000000 108 | 00000000 109 | 00000000 110 | 00000000 111 | 00000000 112 | 00010000 113 | 00000000 114 | 00000000 115 | 00000000 116 | 00000000 117 | 00000000 118 | 00000000 119 | 00000000 120 | 00000000 121 | 00000000 122 | 00000000 123 | 00000000 124 | 00000000 125 | 00000000 126 | 00000000 127 | 00000000 128 | 00001001 129 | -------------------------------------------------------------------------------- /Projects/sdsoc/repo/digilent/ip/dvi2rgb_v1_6/src/720p_edid.txt: -------------------------------------------------------------------------------- 1 | 00000000 2 | 11111111 3 | 11111111 4 | 11111111 5 | 11111111 6 | 11111111 7 | 11111111 8 | 00000000 9 | 00010000 10 | 11101100 11 | 00000010 12 | 00000000 13 | 00000000 14 | 00000000 15 | 00000000 16 | 00000000 17 | 00000010 18 | 00011010 19 | 00000001 20 | 00000011 21 | 10100001 22 | 00110011 23 | 00011101 24 | 01111000 25 | 00001010 26 | 11101100 27 | 00011000 28 | 10100011 29 | 01010100 30 | 01000110 31 | 10011000 32 | 00100101 33 | 00001111 34 | 01001000 35 | 01001100 36 | 00100001 37 | 00001000 38 | 00000000 39 | 10110011 40 | 00000000 41 | 11010001 42 | 11000000 43 | 10000001 44 | 10000000 45 | 10000001 46 | 11000000 47 | 10101001 48 | 11000000 49 | 00000001 50 | 00000001 51 | 00000001 52 | 00000001 53 | 00000001 54 | 00000001 55 | 00000001 56 | 00011101 57 | 00000000 58 | 01110010 59 | 01010001 60 | 11010000 61 | 00011110 62 | 00100000 63 | 01101110 64 | 00101000 65 | 01010101 66 | 00000000 67 | 00000000 68 | 11010000 69 | 01010010 70 | 00000000 71 | 00000000 72 | 00011110 73 | 00000000 74 | 00000000 75 | 00000000 76 | 11111100 77 | 00100000 78 | 01000100 79 | 01101001 80 | 01100111 81 | 01101001 82 | 01101100 83 | 01100101 84 | 01101110 85 | 01110100 86 | 01000100 87 | 01010110 88 | 01001001 89 | 00101101 90 | 00110010 91 | 00000000 92 | 00000000 93 | 00000000 94 | 00010000 95 | 00000000 96 | 00000000 97 | 00000000 98 | 00000000 99 | 00000000 100 | 00000000 101 | 00000000 102 | 00000000 103 | 00000000 104 | 00000000 105 | 00000000 106 | 00000000 107 | 00000000 108 | 00000000 109 | 00000000 110 | 00000000 111 | 00000000 112 | 00010000 113 | 00000000 114 | 00000000 115 | 00000000 116 | 00000000 117 | 00000000 118 | 00000000 119 | 00000000 120 | 00000000 121 | 00000000 122 | 00000000 123 | 00000000 124 | 00000000 125 | 00000000 126 | 00000000 127 | 00000000 128 | 11101110 129 | -------------------------------------------------------------------------------- /Projects/sdsoc/repo/digilent/ip/dvi2rgb_v1_6/src/900p_edid.txt: -------------------------------------------------------------------------------- 1 | 00000000 2 | 11111111 3 | 11111111 4 | 11111111 5 | 11111111 6 | 11111111 7 | 11111111 8 | 00000000 9 | 00010000 10 | 11101100 11 | 00000001 12 | 00000000 13 | 00000000 14 | 00000000 15 | 00000000 16 | 00000000 17 | 00000010 18 | 00011010 19 | 00000001 20 | 00000011 21 | 10100001 22 | 00110011 23 | 00011101 24 | 01111000 25 | 00001010 26 | 11101100 27 | 00011000 28 | 10100011 29 | 01010100 30 | 01000110 31 | 10011000 32 | 00100101 33 | 00001111 34 | 01001000 35 | 01001100 36 | 00100001 37 | 00001000 38 | 00000000 39 | 10110011 40 | 00000000 41 | 11010001 42 | 11000000 43 | 10000001 44 | 10000000 45 | 10000001 46 | 11000000 47 | 10101001 48 | 11000000 49 | 00000001 50 | 00000001 51 | 00000001 52 | 00000001 53 | 00000001 54 | 00000001 55 | 00101111 56 | 00100110 57 | 01000000 58 | 10100000 59 | 01100000 60 | 10000100 61 | 00011010 62 | 00110000 63 | 00110000 64 | 00100000 65 | 00110101 66 | 00000000 67 | 00000000 68 | 10000100 69 | 01010011 70 | 00000000 71 | 00000000 72 | 00011010 73 | 00000000 74 | 00000000 75 | 00000000 76 | 11111100 77 | 00100000 78 | 01000100 79 | 01101001 80 | 01100111 81 | 01101001 82 | 01101100 83 | 01100101 84 | 01101110 85 | 01110100 86 | 01000100 87 | 01010110 88 | 01001001 89 | 00101101 90 | 00110001 91 | 00000000 92 | 00000000 93 | 00000000 94 | 00010000 95 | 00000000 96 | 00000000 97 | 00000000 98 | 00000000 99 | 00000000 100 | 00000000 101 | 00000000 102 | 00000000 103 | 00000000 104 | 00000000 105 | 00000000 106 | 00000000 107 | 00000000 108 | 00000000 109 | 00000000 110 | 00000000 111 | 00000000 112 | 00010000 113 | 00000000 114 | 00000000 115 | 00000000 116 | 00000000 117 | 00000000 118 | 00000000 119 | 00000000 120 | 00000000 121 | 00000000 122 | 00000000 123 | 00000000 124 | 00000000 125 | 00000000 126 | 00000000 127 | 00000000 128 | 00110001 129 | -------------------------------------------------------------------------------- /Projects/linux_bd/repo/vivado-library/ip/dvi2rgb_v1_6/src/1024_edid.txt: -------------------------------------------------------------------------------- 1 | 00000000 2 | 11111111 3 | 11111111 4 | 11111111 5 | 11111111 6 | 11111111 7 | 11111111 8 | 00000000 9 | 00010000 10 | 11101100 11 | 00000000 12 | 00000000 13 | 00000000 14 | 00000000 15 | 00000000 16 | 00000000 17 | 00000010 18 | 00011010 19 | 00000001 20 | 00000011 21 | 10100001 22 | 00110011 23 | 00011101 24 | 01111000 25 | 00001010 26 | 11101100 27 | 00011000 28 | 10100011 29 | 01010100 30 | 01000110 31 | 10011000 32 | 00100101 33 | 00001111 34 | 01001000 35 | 01001100 36 | 00100001 37 | 00001000 38 | 00000000 39 | 10110011 40 | 00000000 41 | 11010001 42 | 11000000 43 | 10000001 44 | 10000000 45 | 10000001 46 | 11000000 47 | 10101001 48 | 11000000 49 | 00000001 50 | 00000001 51 | 00000001 52 | 00000001 53 | 00000001 54 | 00000001 55 | 00110000 56 | 00101010 57 | 00000000 58 | 10011000 59 | 01010001 60 | 00000000 61 | 00101010 62 | 01000000 63 | 00110000 64 | 01110000 65 | 00010011 66 | 00000000 67 | 00000000 68 | 00000000 69 | 01010100 70 | 00000000 71 | 00000000 72 | 00011110 73 | 00000000 74 | 00000000 75 | 00000000 76 | 11111100 77 | 00100000 78 | 01000100 79 | 01101001 80 | 01100111 81 | 01101001 82 | 01101100 83 | 01100101 84 | 01101110 85 | 01110100 86 | 01000100 87 | 01010110 88 | 01001001 89 | 00101101 90 | 00110000 91 | 00000000 92 | 00000000 93 | 00000000 94 | 00010000 95 | 00000000 96 | 00000000 97 | 00000000 98 | 00000000 99 | 00000000 100 | 00000000 101 | 00000000 102 | 00000000 103 | 00000000 104 | 00000000 105 | 00000000 106 | 00000000 107 | 00000000 108 | 00000000 109 | 00000000 110 | 00000000 111 | 00000000 112 | 00010000 113 | 00000000 114 | 00000000 115 | 00000000 116 | 00000000 117 | 00000000 118 | 00000000 119 | 00000000 120 | 00000000 121 | 00000000 122 | 00000000 123 | 00000000 124 | 00000000 125 | 00000000 126 | 00000000 127 | 00000000 128 | 00111010 129 | -------------------------------------------------------------------------------- /Projects/linux_bd/repo/vivado-library/ip/dvi2rgb_v1_6/src/1080_edid.txt: -------------------------------------------------------------------------------- 1 | 00000000 2 | 11111111 3 | 11111111 4 | 11111111 5 | 11111111 6 | 11111111 7 | 11111111 8 | 00000000 9 | 00010000 10 | 11101100 11 | 00000011 12 | 00000000 13 | 00000000 14 | 00000000 15 | 00000000 16 | 00000000 17 | 00000010 18 | 00011010 19 | 00000001 20 | 00000011 21 | 10100001 22 | 00110011 23 | 00011101 24 | 01111000 25 | 00001010 26 | 11101100 27 | 00011000 28 | 10100011 29 | 01010100 30 | 01000110 31 | 10011000 32 | 00100101 33 | 00001111 34 | 01001000 35 | 01001100 36 | 00100001 37 | 00001000 38 | 00000000 39 | 10110011 40 | 00000000 41 | 11010001 42 | 11000000 43 | 10000001 44 | 10000000 45 | 10000001 46 | 11000000 47 | 10101001 48 | 11000000 49 | 00000001 50 | 00000001 51 | 00000001 52 | 00000001 53 | 00000001 54 | 00000001 55 | 00000010 56 | 00111010 57 | 10000000 58 | 00011000 59 | 01110001 60 | 00111000 61 | 00101101 62 | 01000000 63 | 01011000 64 | 00101100 65 | 01000101 66 | 00000000 67 | 10000000 68 | 00111000 69 | 01110100 70 | 00000000 71 | 00000000 72 | 00011110 73 | 00000000 74 | 00000000 75 | 00000000 76 | 11111100 77 | 00100000 78 | 01000100 79 | 01101001 80 | 01100111 81 | 01101001 82 | 01101100 83 | 01100101 84 | 01101110 85 | 01110100 86 | 01000100 87 | 01010110 88 | 01001001 89 | 00101101 90 | 00110011 91 | 00000000 92 | 00000000 93 | 00000000 94 | 00010000 95 | 00000000 96 | 00000000 97 | 00000000 98 | 00000000 99 | 00000000 100 | 00000000 101 | 00000000 102 | 00000000 103 | 00000000 104 | 00000000 105 | 00000000 106 | 00000000 107 | 00000000 108 | 00000000 109 | 00000000 110 | 00000000 111 | 00000000 112 | 00010000 113 | 00000000 114 | 00000000 115 | 00000000 116 | 00000000 117 | 00000000 118 | 00000000 119 | 00000000 120 | 00000000 121 | 00000000 122 | 00000000 123 | 00000000 124 | 00000000 125 | 00000000 126 | 00000000 127 | 00000000 128 | 00001001 129 | -------------------------------------------------------------------------------- /Projects/linux_bd/repo/vivado-library/ip/dvi2rgb_v1_6/src/720p_edid.txt: -------------------------------------------------------------------------------- 1 | 00000000 2 | 11111111 3 | 11111111 4 | 11111111 5 | 11111111 6 | 11111111 7 | 11111111 8 | 00000000 9 | 00010000 10 | 11101100 11 | 00000010 12 | 00000000 13 | 00000000 14 | 00000000 15 | 00000000 16 | 00000000 17 | 00000010 18 | 00011010 19 | 00000001 20 | 00000011 21 | 10100001 22 | 00110011 23 | 00011101 24 | 01111000 25 | 00001010 26 | 11101100 27 | 00011000 28 | 10100011 29 | 01010100 30 | 01000110 31 | 10011000 32 | 00100101 33 | 00001111 34 | 01001000 35 | 01001100 36 | 00100001 37 | 00001000 38 | 00000000 39 | 10110011 40 | 00000000 41 | 11010001 42 | 11000000 43 | 10000001 44 | 10000000 45 | 10000001 46 | 11000000 47 | 10101001 48 | 11000000 49 | 00000001 50 | 00000001 51 | 00000001 52 | 00000001 53 | 00000001 54 | 00000001 55 | 00000001 56 | 00011101 57 | 00000000 58 | 01110010 59 | 01010001 60 | 11010000 61 | 00011110 62 | 00100000 63 | 01101110 64 | 00101000 65 | 01010101 66 | 00000000 67 | 00000000 68 | 11010000 69 | 01010010 70 | 00000000 71 | 00000000 72 | 00011110 73 | 00000000 74 | 00000000 75 | 00000000 76 | 11111100 77 | 00100000 78 | 01000100 79 | 01101001 80 | 01100111 81 | 01101001 82 | 01101100 83 | 01100101 84 | 01101110 85 | 01110100 86 | 01000100 87 | 01010110 88 | 01001001 89 | 00101101 90 | 00110010 91 | 00000000 92 | 00000000 93 | 00000000 94 | 00010000 95 | 00000000 96 | 00000000 97 | 00000000 98 | 00000000 99 | 00000000 100 | 00000000 101 | 00000000 102 | 00000000 103 | 00000000 104 | 00000000 105 | 00000000 106 | 00000000 107 | 00000000 108 | 00000000 109 | 00000000 110 | 00000000 111 | 00000000 112 | 00010000 113 | 00000000 114 | 00000000 115 | 00000000 116 | 00000000 117 | 00000000 118 | 00000000 119 | 00000000 120 | 00000000 121 | 00000000 122 | 00000000 123 | 00000000 124 | 00000000 125 | 00000000 126 | 00000000 127 | 00000000 128 | 11101110 129 | -------------------------------------------------------------------------------- /Projects/linux_bd/repo/vivado-library/ip/dvi2rgb_v1_6/src/900p_edid.txt: -------------------------------------------------------------------------------- 1 | 00000000 2 | 11111111 3 | 11111111 4 | 11111111 5 | 11111111 6 | 11111111 7 | 11111111 8 | 00000000 9 | 00010000 10 | 11101100 11 | 00000001 12 | 00000000 13 | 00000000 14 | 00000000 15 | 00000000 16 | 00000000 17 | 00000010 18 | 00011010 19 | 00000001 20 | 00000011 21 | 10100001 22 | 00110011 23 | 00011101 24 | 01111000 25 | 00001010 26 | 11101100 27 | 00011000 28 | 10100011 29 | 01010100 30 | 01000110 31 | 10011000 32 | 00100101 33 | 00001111 34 | 01001000 35 | 01001100 36 | 00100001 37 | 00001000 38 | 00000000 39 | 10110011 40 | 00000000 41 | 11010001 42 | 11000000 43 | 10000001 44 | 10000000 45 | 10000001 46 | 11000000 47 | 10101001 48 | 11000000 49 | 00000001 50 | 00000001 51 | 00000001 52 | 00000001 53 | 00000001 54 | 00000001 55 | 00101111 56 | 00100110 57 | 01000000 58 | 10100000 59 | 01100000 60 | 10000100 61 | 00011010 62 | 00110000 63 | 00110000 64 | 00100000 65 | 00110101 66 | 00000000 67 | 00000000 68 | 10000100 69 | 01010011 70 | 00000000 71 | 00000000 72 | 00011010 73 | 00000000 74 | 00000000 75 | 00000000 76 | 11111100 77 | 00100000 78 | 01000100 79 | 01101001 80 | 01100111 81 | 01101001 82 | 01101100 83 | 01100101 84 | 01101110 85 | 01110100 86 | 01000100 87 | 01010110 88 | 01001001 89 | 00101101 90 | 00110001 91 | 00000000 92 | 00000000 93 | 00000000 94 | 00010000 95 | 00000000 96 | 00000000 97 | 00000000 98 | 00000000 99 | 00000000 100 | 00000000 101 | 00000000 102 | 00000000 103 | 00000000 104 | 00000000 105 | 00000000 106 | 00000000 107 | 00000000 108 | 00000000 109 | 00000000 110 | 00000000 111 | 00000000 112 | 00010000 113 | 00000000 114 | 00000000 115 | 00000000 116 | 00000000 117 | 00000000 118 | 00000000 119 | 00000000 120 | 00000000 121 | 00000000 122 | 00000000 123 | 00000000 124 | 00000000 125 | 00000000 126 | 00000000 127 | 00000000 128 | 00110001 129 | -------------------------------------------------------------------------------- /Projects/linux_bd/repo/ADI/ip/axi_i2s_adi/axi_streaming_dma_tx_fifo.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | 4 | library work; 5 | use work.dma_fifo; 6 | 7 | entity axi_streaming_dma_tx_fifo is 8 | generic ( 9 | RAM_ADDR_WIDTH : integer := 3; 10 | FIFO_DWIDTH : integer := 32 11 | ); 12 | port ( 13 | clk : in std_logic; 14 | resetn : in std_logic; 15 | fifo_reset : in std_logic; 16 | 17 | -- Enable DMA interface 18 | enable : in Boolean; 19 | 20 | -- Write port 21 | S_AXIS_ACLK : in std_logic; 22 | S_AXIS_TREADY : out std_logic; 23 | S_AXIS_TDATA : in std_logic_vector(FIFO_DWIDTH-1 downto 0); 24 | S_AXIS_TLAST : in std_logic; 25 | S_AXIS_TVALID : in std_logic; 26 | 27 | -- Read port 28 | out_stb : out std_logic; 29 | out_ack : in std_logic; 30 | out_data : out std_logic_vector(FIFO_DWIDTH-1 downto 0) 31 | ); 32 | end; 33 | 34 | architecture imp of axi_streaming_dma_tx_fifo is 35 | signal in_ack : std_logic; 36 | signal drain_dma : Boolean; 37 | begin 38 | 39 | fifo: entity dma_fifo 40 | generic map ( 41 | RAM_ADDR_WIDTH => RAM_ADDR_WIDTH, 42 | FIFO_DWIDTH => FIFO_DWIDTH 43 | ) 44 | port map ( 45 | clk => clk, 46 | resetn => resetn, 47 | fifo_reset => fifo_reset, 48 | in_stb => S_AXIS_TVALID, 49 | in_ack => in_ack, 50 | in_data => S_AXIS_TDATA, 51 | out_stb => out_stb, 52 | out_ack => out_ack, 53 | out_data => out_data 54 | ); 55 | 56 | drain_process: process (S_AXIS_ACLK) is 57 | variable enable_d1 : Boolean; 58 | begin 59 | if rising_edge(S_AXIS_ACLK) then 60 | if resetn = '0' then 61 | drain_dma <= False; 62 | else 63 | if S_AXIS_TLAST = '1' then 64 | drain_dma <= False; 65 | elsif enable_d1 and enable then 66 | drain_dma <= True; 67 | end if; 68 | enable_d1 := enable; 69 | end if; 70 | end if; 71 | end process; 72 | 73 | S_AXIS_TREADY <= '1' when in_ack = '1' or drain_dma else '0'; 74 | end; 75 | -------------------------------------------------------------------------------- /Projects/dma/sdk/dma/src/platform.h: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * 3 | * Copyright (C) 2008 - 2014 Xilinx, Inc. All rights reserved. 4 | * 5 | * Permission is hereby granted, free of charge, to any person obtaining a copy 6 | * of this software and associated documentation files (the "Software"), to deal 7 | * in the Software without restriction, including without limitation the rights 8 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | * copies of the Software, and to permit persons to whom the Software is 10 | * furnished to do so, subject to the following conditions: 11 | * 12 | * The above copyright notice and this permission notice shall be included in 13 | * all copies or substantial portions of the Software. 14 | * 15 | * Use of the Software is limited solely to applications: 16 | * (a) running on a Xilinx device, or 17 | * (b) that interact with a Xilinx device through a bus or interconnect. 18 | * 19 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 20 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 21 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 22 | * XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 23 | * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF 24 | * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 25 | * SOFTWARE. 26 | * 27 | * Except as contained in this notice, the name of the Xilinx shall not be used 28 | * in advertising or otherwise to promote the sale, use or other dealings in 29 | * this Software without prior written authorization from Xilinx. 30 | * 31 | ******************************************************************************/ 32 | 33 | #ifndef __PLATFORM_H_ 34 | #define __PLATFORM_H_ 35 | 36 | #include "platform_config.h" 37 | 38 | void init_platform(); 39 | void cleanup_platform(); 40 | 41 | #endif 42 | -------------------------------------------------------------------------------- /Projects/sdsoc/sdk/hello/src/platform.h: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * 3 | * Copyright (C) 2008 - 2014 Xilinx, Inc. All rights reserved. 4 | * 5 | * Permission is hereby granted, free of charge, to any person obtaining a copy 6 | * of this software and associated documentation files (the "Software"), to deal 7 | * in the Software without restriction, including without limitation the rights 8 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | * copies of the Software, and to permit persons to whom the Software is 10 | * furnished to do so, subject to the following conditions: 11 | * 12 | * The above copyright notice and this permission notice shall be included in 13 | * all copies or substantial portions of the Software. 14 | * 15 | * Use of the Software is limited solely to applications: 16 | * (a) running on a Xilinx device, or 17 | * (b) that interact with a Xilinx device through a bus or interconnect. 18 | * 19 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 20 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 21 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 22 | * XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 23 | * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF 24 | * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 25 | * SOFTWARE. 26 | * 27 | * Except as contained in this notice, the name of the Xilinx shall not be used 28 | * in advertising or otherwise to promote the sale, use or other dealings in 29 | * this Software without prior written authorization from Xilinx. 30 | * 31 | ******************************************************************************/ 32 | 33 | #ifndef __PLATFORM_H_ 34 | #define __PLATFORM_H_ 35 | 36 | #include "platform_config.h" 37 | 38 | void init_platform(); 39 | void cleanup_platform(); 40 | 41 | #endif 42 | -------------------------------------------------------------------------------- /Projects/linux_bd/sdk/linux_bd_wrapper_hw_platform_0/.project: -------------------------------------------------------------------------------- 1 | 2 | 3 | linux_bd_wrapper_hw_platform_0 4 | Created by SDK v2015.4 5 | 6 | 7 | 8 | 9 | 10 | com.xilinx.sdk.hw.HwProject 11 | 12 | 13 | 14 | 1456806732418 15 | 16 | 6 17 | 18 | org.eclipse.ui.ide.multiFilter 19 | 1.0-name-matches-false-false-*.xml 20 | 21 | 22 | 23 | 1456806732428 24 | 25 | 6 26 | 27 | org.eclipse.ui.ide.multiFilter 28 | 1.0-name-matches-false-false-*.svd 29 | 30 | 31 | 32 | 1456806732438 33 | 34 | 6 35 | 36 | org.eclipse.ui.ide.multiFilter 37 | 1.0-name-matches-false-false-*.hwh 38 | 39 | 40 | 41 | 1465032502621 42 | 43 | 6 44 | 45 | org.eclipse.ui.ide.multiFilter 46 | 1.0-name-matches-false-false-*.xml 47 | 48 | 49 | 50 | 1465032502631 51 | 52 | 6 53 | 54 | org.eclipse.ui.ide.multiFilter 55 | 1.0-name-matches-false-false-*.svd 56 | 57 | 58 | 59 | 1465032502642 60 | 61 | 6 62 | 63 | org.eclipse.ui.ide.multiFilter 64 | 1.0-name-matches-false-false-*.hwh 65 | 66 | 67 | 68 | 69 | -------------------------------------------------------------------------------- /Projects/linux_bd/repo/ADI/ip/axi_i2s_adi/dma_fifo.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | use ieee.numeric_std.all; 4 | 5 | entity dma_fifo is 6 | generic ( 7 | RAM_ADDR_WIDTH : integer := 3; 8 | FIFO_DWIDTH : integer := 32 9 | ); 10 | port ( 11 | clk : in std_logic; 12 | resetn : in std_logic; 13 | fifo_reset : in std_logic; 14 | 15 | -- Write port 16 | in_stb : in std_logic; 17 | in_ack : out std_logic; 18 | in_data : in std_logic_vector(FIFO_DWIDTH-1 downto 0); 19 | 20 | -- Read port 21 | out_stb : out std_logic; 22 | out_ack : in std_logic; 23 | out_data : out std_logic_vector(FIFO_DWIDTH-1 downto 0) 24 | ); 25 | end; 26 | 27 | architecture imp of dma_fifo is 28 | 29 | constant FIFO_MAX : natural := 2**RAM_ADDR_WIDTH -1; 30 | type MEM is array (0 to FIFO_MAX) of std_logic_vector(FIFO_DWIDTH - 1 downto 0); 31 | signal data_fifo : MEM; 32 | signal wr_addr : natural range 0 to FIFO_MAX; 33 | signal rd_addr : natural range 0 to FIFO_MAX; 34 | signal full, empty : Boolean; 35 | 36 | begin 37 | in_ack <= '0' when full else '1'; 38 | 39 | out_stb <= '0' when empty else '1'; 40 | out_data <= data_fifo(rd_addr); 41 | 42 | fifo: process (clk) is 43 | variable free_cnt : integer range 0 to FIFO_MAX + 1; 44 | begin 45 | if rising_edge(clk) then 46 | if (resetn = '0') or (fifo_reset = '1') then 47 | wr_addr <= 0; 48 | rd_addr <= 0; 49 | free_cnt := FIFO_MAX + 1; 50 | empty <= True; 51 | full <= False; 52 | else 53 | if in_stb = '1' and not full then 54 | data_fifo(wr_addr) <= in_data; 55 | wr_addr <= (wr_addr + 1) mod (FIFO_MAX + 1); 56 | free_cnt := free_cnt - 1; 57 | end if; 58 | 59 | if out_ack = '1' and not empty then 60 | rd_addr <= (rd_addr + 1) mod (FIFO_MAX + 1); 61 | free_cnt := free_cnt + 1; 62 | end if; 63 | 64 | full <= free_cnt = 0; 65 | empty <= free_cnt = FIFO_MAX + 1; 66 | end if; 67 | end if; 68 | end process; 69 | end; 70 | -------------------------------------------------------------------------------- /Projects/linux_bd/repo/vivado-library/ip/axi_i2s_adi_1.2/hdl/adi_common/axi_streaming_dma_tx_fifo.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | 4 | library adi_common_v1_00_a; 5 | use adi_common_v1_00_a.dma_fifo; 6 | 7 | entity axi_streaming_dma_tx_fifo is 8 | generic ( 9 | RAM_ADDR_WIDTH : integer := 3; 10 | FIFO_DWIDTH : integer := 32 11 | ); 12 | port ( 13 | clk : in std_logic; 14 | resetn : in std_logic; 15 | fifo_reset : in std_logic; 16 | 17 | -- Enable DMA interface 18 | enable : in Boolean; 19 | 20 | -- Write port 21 | S_AXIS_ACLK : in std_logic; 22 | S_AXIS_TREADY : out std_logic; 23 | S_AXIS_TDATA : in std_logic_vector(FIFO_DWIDTH-1 downto 0); 24 | S_AXIS_TLAST : in std_logic; 25 | S_AXIS_TVALID : in std_logic; 26 | 27 | -- Read port 28 | out_stb : out std_logic; 29 | out_ack : in std_logic; 30 | out_data : out std_logic_vector(FIFO_DWIDTH-1 downto 0) 31 | ); 32 | end; 33 | 34 | architecture imp of axi_streaming_dma_tx_fifo is 35 | signal in_ack : std_logic; 36 | signal drain_dma : Boolean; 37 | begin 38 | 39 | fifo: entity dma_fifo 40 | generic map ( 41 | RAM_ADDR_WIDTH => RAM_ADDR_WIDTH, 42 | FIFO_DWIDTH => FIFO_DWIDTH 43 | ) 44 | port map ( 45 | clk => clk, 46 | resetn => resetn, 47 | fifo_reset => fifo_reset, 48 | in_stb => S_AXIS_TVALID, 49 | in_ack => in_ack, 50 | in_data => S_AXIS_TDATA, 51 | out_stb => out_stb, 52 | out_ack => out_ack, 53 | out_data => out_data 54 | ); 55 | 56 | drain_process: process (S_AXIS_ACLK) is 57 | variable enable_d1 : Boolean; 58 | begin 59 | if rising_edge(S_AXIS_ACLK) then 60 | if resetn = '0' then 61 | drain_dma <= False; 62 | else 63 | if S_AXIS_TLAST = '1' then 64 | drain_dma <= False; 65 | elsif enable_d1 and enable then 66 | drain_dma <= True; 67 | end if; 68 | enable_d1 := enable; 69 | end if; 70 | end if; 71 | end process; 72 | 73 | S_AXIS_TREADY <= '1' when in_ack = '1' or drain_dma else '0'; 74 | end; 75 | -------------------------------------------------------------------------------- /Projects/linux_bd/repo/vivado-library/ip/axi_i2s_adi_1.2/hdl/adi_common/dma_fifo.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | use ieee.numeric_std.all; 4 | 5 | entity dma_fifo is 6 | generic ( 7 | RAM_ADDR_WIDTH : integer := 3; 8 | FIFO_DWIDTH : integer := 32 9 | ); 10 | port ( 11 | clk : in std_logic; 12 | resetn : in std_logic; 13 | fifo_reset : in std_logic; 14 | 15 | -- Write port 16 | in_stb : in std_logic; 17 | in_ack : out std_logic; 18 | in_data : in std_logic_vector(FIFO_DWIDTH-1 downto 0); 19 | 20 | -- Read port 21 | out_stb : out std_logic; 22 | out_ack : in std_logic; 23 | out_data : out std_logic_vector(FIFO_DWIDTH-1 downto 0) 24 | ); 25 | end; 26 | 27 | architecture imp of dma_fifo is 28 | 29 | constant FIFO_MAX : natural := 2**RAM_ADDR_WIDTH -1; 30 | type MEM is array (0 to FIFO_MAX) of std_logic_vector(FIFO_DWIDTH - 1 downto 0); 31 | signal data_fifo : MEM; 32 | signal wr_addr : natural range 0 to FIFO_MAX; 33 | signal rd_addr : natural range 0 to FIFO_MAX; 34 | signal full, empty : Boolean; 35 | 36 | begin 37 | in_ack <= '0' when full else '1'; 38 | 39 | out_stb <= '0' when empty else '1'; 40 | out_data <= data_fifo(rd_addr); 41 | 42 | fifo: process (clk) is 43 | variable free_cnt : integer range 0 to FIFO_MAX + 1; 44 | begin 45 | if rising_edge(clk) then 46 | if (resetn = '0') or (fifo_reset = '1') then 47 | wr_addr <= 0; 48 | rd_addr <= 0; 49 | free_cnt := FIFO_MAX + 1; 50 | empty <= True; 51 | full <= False; 52 | else 53 | if in_stb = '1' and not full then 54 | data_fifo(wr_addr) <= in_data; 55 | wr_addr <= (wr_addr + 1) mod (FIFO_MAX + 1); 56 | free_cnt := free_cnt - 1; 57 | end if; 58 | 59 | if out_ack = '1' and not empty then 60 | rd_addr <= (rd_addr + 1) mod (FIFO_MAX + 1); 61 | free_cnt := free_cnt + 1; 62 | end if; 63 | 64 | full <= free_cnt = 0; 65 | empty <= free_cnt = FIFO_MAX + 1; 66 | end if; 67 | end if; 68 | end process; 69 | end; 70 | -------------------------------------------------------------------------------- /Projects/hdmi_in/sdk/HDMI_IN/src/timer_ps/timer_ps.h: -------------------------------------------------------------------------------- 1 | /************************************************************************/ 2 | /* */ 3 | /* timer_ps.h -- Timer Delay for Zynq systems */ 4 | /* */ 5 | /************************************************************************/ 6 | /* Author: Sam Bobrowicz */ 7 | /* Copyright 2014, Digilent Inc. */ 8 | /************************************************************************/ 9 | /* Module Description: */ 10 | /* */ 11 | /* Implements an accurate delay function using the scu timer. */ 12 | /* Code from this module will cause conflicts with other code that */ 13 | /* requires the Zynq's scu timer. */ 14 | /* */ 15 | /* This module contains code from the Xilinx Demo titled */ 16 | /* "xscutimer_polled_example.c" */ 17 | /* */ 18 | /************************************************************************/ 19 | /* Revision History: */ 20 | /* */ 21 | /* 2/14/2014(SamB): Created */ 22 | /* */ 23 | /************************************************************************/ 24 | #ifndef TIMER_PS_H_ 25 | #define TIMER_PS_H_ 26 | 27 | #include "xil_types.h" 28 | #include "xparameters.h" 29 | 30 | /* ------------------------------------------------------------ */ 31 | /* Miscellaneous Declarations */ 32 | /* ------------------------------------------------------------ */ 33 | 34 | #define TIMER_FREQ_HZ (XPAR_CPU_CORTEXA9_0_CPU_CLK_FREQ_HZ / 2) 35 | 36 | /* ------------------------------------------------------------ */ 37 | /* Procedure Declarations */ 38 | /* ------------------------------------------------------------ */ 39 | 40 | int TimerInitialize(u16 TimerDeviceId); 41 | void TimerDelay(u32 uSDelay); 42 | 43 | /* ------------------------------------------------------------ */ 44 | 45 | /************************************************************************/ 46 | 47 | 48 | #endif /* TIMER_H_ */ 49 | -------------------------------------------------------------------------------- /Projects/hdmi_out/sdk/displaydemo/src/timer_ps/timer_ps.h: -------------------------------------------------------------------------------- 1 | /************************************************************************/ 2 | /* */ 3 | /* timer_ps.h -- Timer Delay for Zynq systems */ 4 | /* */ 5 | /************************************************************************/ 6 | /* Author: Sam Bobrowicz */ 7 | /* Copyright 2014, Digilent Inc. */ 8 | /************************************************************************/ 9 | /* Module Description: */ 10 | /* */ 11 | /* Implements an accurate delay function using the scu timer. */ 12 | /* Code from this module will cause conflicts with other code that */ 13 | /* requires the Zynq's scu timer. */ 14 | /* */ 15 | /* This module contains code from the Xilinx Demo titled */ 16 | /* "xscutimer_polled_example.c" */ 17 | /* */ 18 | /************************************************************************/ 19 | /* Revision History: */ 20 | /* */ 21 | /* 2/14/2014(SamB): Created */ 22 | /* */ 23 | /************************************************************************/ 24 | #ifndef TIMER_PS_H_ 25 | #define TIMER_PS_H_ 26 | 27 | #include "xil_types.h" 28 | #include "xparameters.h" 29 | 30 | /* ------------------------------------------------------------ */ 31 | /* Miscellaneous Declarations */ 32 | /* ------------------------------------------------------------ */ 33 | 34 | #define TIMER_FREQ_HZ (XPAR_CPU_CORTEXA9_0_CPU_CLK_FREQ_HZ / 2) 35 | 36 | /* ------------------------------------------------------------ */ 37 | /* Procedure Declarations */ 38 | /* ------------------------------------------------------------ */ 39 | 40 | int TimerInitialize(u16 TimerDeviceId); 41 | void TimerDelay(u32 uSDelay); 42 | 43 | /* ------------------------------------------------------------ */ 44 | 45 | /************************************************************************/ 46 | 47 | 48 | #endif /* TIMER_H_ */ 49 | -------------------------------------------------------------------------------- /Projects/hdmi_in/repo/digilent/ip/axi_dynclk_v1_0/xgui/axi_dynclk_v1_0.tcl: -------------------------------------------------------------------------------- 1 | # Definitional proc to organize widgets for parameters. 2 | proc init_gui { IPINST } { 3 | ipgui::add_param $IPINST -name "Component_Name" 4 | #Adding Page 5 | set Page_0 [ipgui::add_page $IPINST -name "Page 0"] 6 | set ADD_BUFMR [ipgui::add_param $IPINST -name "ADD_BUFMR" -parent ${Page_0}] 7 | set_property tooltip {Add a BUFMR between the MMCM output and BUFIO/BUFR inputs to allow the MMCM to be placed in a different bank than the high-speed data bus. Useful if two high-speed data buses that require MMCMs are on the same bank.} ${ADD_BUFMR} 8 | 9 | 10 | } 11 | 12 | proc update_PARAM_VALUE.ADD_BUFMR { PARAM_VALUE.ADD_BUFMR } { 13 | # Procedure called to update ADD_BUFMR when any of the dependent parameters in the arguments change 14 | } 15 | 16 | proc validate_PARAM_VALUE.ADD_BUFMR { PARAM_VALUE.ADD_BUFMR } { 17 | # Procedure called to validate ADD_BUFMR 18 | return true 19 | } 20 | 21 | 22 | proc update_MODELPARAM_VALUE.C_S00_AXI_DATA_WIDTH { MODELPARAM_VALUE.C_S00_AXI_DATA_WIDTH } { 23 | # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value 24 | # WARNING: There is no corresponding user parameter named "C_S00_AXI_DATA_WIDTH". Setting updated value from the model parameter. 25 | set_property value 32 ${MODELPARAM_VALUE.C_S00_AXI_DATA_WIDTH} 26 | } 27 | 28 | proc update_MODELPARAM_VALUE.C_S00_AXI_ADDR_WIDTH { MODELPARAM_VALUE.C_S00_AXI_ADDR_WIDTH } { 29 | # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value 30 | # WARNING: There is no corresponding user parameter named "C_S00_AXI_ADDR_WIDTH". Setting updated value from the model parameter. 31 | set_property value 5 ${MODELPARAM_VALUE.C_S00_AXI_ADDR_WIDTH} 32 | } 33 | 34 | proc update_MODELPARAM_VALUE.ADD_BUFMR { MODELPARAM_VALUE.ADD_BUFMR PARAM_VALUE.ADD_BUFMR } { 35 | # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value 36 | set_property value [get_property value ${PARAM_VALUE.ADD_BUFMR}] ${MODELPARAM_VALUE.ADD_BUFMR} 37 | } 38 | 39 | -------------------------------------------------------------------------------- /Projects/hdmi_out/repo/digilent/ip/axi_dynclk_v1_0/xgui/axi_dynclk_v1_0.tcl: -------------------------------------------------------------------------------- 1 | # Definitional proc to organize widgets for parameters. 2 | proc init_gui { IPINST } { 3 | ipgui::add_param $IPINST -name "Component_Name" 4 | #Adding Page 5 | set Page_0 [ipgui::add_page $IPINST -name "Page 0"] 6 | set ADD_BUFMR [ipgui::add_param $IPINST -name "ADD_BUFMR" -parent ${Page_0}] 7 | set_property tooltip {Add a BUFMR between the MMCM output and BUFIO/BUFR inputs to allow the MMCM to be placed in a different bank than the high-speed data bus. Useful if two high-speed data buses that require MMCMs are on the same bank.} ${ADD_BUFMR} 8 | 9 | 10 | } 11 | 12 | proc update_PARAM_VALUE.ADD_BUFMR { PARAM_VALUE.ADD_BUFMR } { 13 | # Procedure called to update ADD_BUFMR when any of the dependent parameters in the arguments change 14 | } 15 | 16 | proc validate_PARAM_VALUE.ADD_BUFMR { PARAM_VALUE.ADD_BUFMR } { 17 | # Procedure called to validate ADD_BUFMR 18 | return true 19 | } 20 | 21 | 22 | proc update_MODELPARAM_VALUE.C_S00_AXI_DATA_WIDTH { MODELPARAM_VALUE.C_S00_AXI_DATA_WIDTH } { 23 | # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value 24 | # WARNING: There is no corresponding user parameter named "C_S00_AXI_DATA_WIDTH". Setting updated value from the model parameter. 25 | set_property value 32 ${MODELPARAM_VALUE.C_S00_AXI_DATA_WIDTH} 26 | } 27 | 28 | proc update_MODELPARAM_VALUE.C_S00_AXI_ADDR_WIDTH { MODELPARAM_VALUE.C_S00_AXI_ADDR_WIDTH } { 29 | # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value 30 | # WARNING: There is no corresponding user parameter named "C_S00_AXI_ADDR_WIDTH". Setting updated value from the model parameter. 31 | set_property value 5 ${MODELPARAM_VALUE.C_S00_AXI_ADDR_WIDTH} 32 | } 33 | 34 | proc update_MODELPARAM_VALUE.ADD_BUFMR { MODELPARAM_VALUE.ADD_BUFMR PARAM_VALUE.ADD_BUFMR } { 35 | # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value 36 | set_property value [get_property value ${PARAM_VALUE.ADD_BUFMR}] ${MODELPARAM_VALUE.ADD_BUFMR} 37 | } 38 | 39 | -------------------------------------------------------------------------------- /Projects/sdsoc/repo/digilent/ip/axi_dynclk_v1_0/xgui/axi_dynclk_v1_0.tcl: -------------------------------------------------------------------------------- 1 | # Definitional proc to organize widgets for parameters. 2 | proc init_gui { IPINST } { 3 | ipgui::add_param $IPINST -name "Component_Name" 4 | #Adding Page 5 | set Page_0 [ipgui::add_page $IPINST -name "Page 0"] 6 | set ADD_BUFMR [ipgui::add_param $IPINST -name "ADD_BUFMR" -parent ${Page_0}] 7 | set_property tooltip {Add a BUFMR between the MMCM output and BUFIO/BUFR inputs to allow the MMCM to be placed in a different bank than the high-speed data bus. Useful if two high-speed data buses that require MMCMs are on the same bank.} ${ADD_BUFMR} 8 | 9 | 10 | } 11 | 12 | proc update_PARAM_VALUE.ADD_BUFMR { PARAM_VALUE.ADD_BUFMR } { 13 | # Procedure called to update ADD_BUFMR when any of the dependent parameters in the arguments change 14 | } 15 | 16 | proc validate_PARAM_VALUE.ADD_BUFMR { PARAM_VALUE.ADD_BUFMR } { 17 | # Procedure called to validate ADD_BUFMR 18 | return true 19 | } 20 | 21 | 22 | proc update_MODELPARAM_VALUE.C_S00_AXI_DATA_WIDTH { MODELPARAM_VALUE.C_S00_AXI_DATA_WIDTH } { 23 | # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value 24 | # WARNING: There is no corresponding user parameter named "C_S00_AXI_DATA_WIDTH". Setting updated value from the model parameter. 25 | set_property value 32 ${MODELPARAM_VALUE.C_S00_AXI_DATA_WIDTH} 26 | } 27 | 28 | proc update_MODELPARAM_VALUE.C_S00_AXI_ADDR_WIDTH { MODELPARAM_VALUE.C_S00_AXI_ADDR_WIDTH } { 29 | # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value 30 | # WARNING: There is no corresponding user parameter named "C_S00_AXI_ADDR_WIDTH". Setting updated value from the model parameter. 31 | set_property value 5 ${MODELPARAM_VALUE.C_S00_AXI_ADDR_WIDTH} 32 | } 33 | 34 | proc update_MODELPARAM_VALUE.ADD_BUFMR { MODELPARAM_VALUE.ADD_BUFMR PARAM_VALUE.ADD_BUFMR } { 35 | # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value 36 | set_property value [get_property value ${PARAM_VALUE.ADD_BUFMR}] ${MODELPARAM_VALUE.ADD_BUFMR} 37 | } 38 | 39 | -------------------------------------------------------------------------------- /Projects/linux_bd/repo/vivado-library/ip/axi_dynclk_v1_0/xgui/axi_dynclk_v1_0.tcl: -------------------------------------------------------------------------------- 1 | # Definitional proc to organize widgets for parameters. 2 | proc init_gui { IPINST } { 3 | ipgui::add_param $IPINST -name "Component_Name" 4 | #Adding Page 5 | set Page_0 [ipgui::add_page $IPINST -name "Page 0"] 6 | set ADD_BUFMR [ipgui::add_param $IPINST -name "ADD_BUFMR" -parent ${Page_0}] 7 | set_property tooltip {Add a BUFMR between the MMCM output and BUFIO/BUFR inputs to allow the MMCM to be placed in a different bank than the high-speed data bus. Useful if two high-speed data buses that require MMCMs are on the same bank.} ${ADD_BUFMR} 8 | 9 | 10 | } 11 | 12 | proc update_PARAM_VALUE.ADD_BUFMR { PARAM_VALUE.ADD_BUFMR } { 13 | # Procedure called to update ADD_BUFMR when any of the dependent parameters in the arguments change 14 | } 15 | 16 | proc validate_PARAM_VALUE.ADD_BUFMR { PARAM_VALUE.ADD_BUFMR } { 17 | # Procedure called to validate ADD_BUFMR 18 | return true 19 | } 20 | 21 | 22 | proc update_MODELPARAM_VALUE.C_S00_AXI_DATA_WIDTH { MODELPARAM_VALUE.C_S00_AXI_DATA_WIDTH } { 23 | # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value 24 | # WARNING: There is no corresponding user parameter named "C_S00_AXI_DATA_WIDTH". Setting updated value from the model parameter. 25 | set_property value 32 ${MODELPARAM_VALUE.C_S00_AXI_DATA_WIDTH} 26 | } 27 | 28 | proc update_MODELPARAM_VALUE.C_S00_AXI_ADDR_WIDTH { MODELPARAM_VALUE.C_S00_AXI_ADDR_WIDTH } { 29 | # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value 30 | # WARNING: There is no corresponding user parameter named "C_S00_AXI_ADDR_WIDTH". Setting updated value from the model parameter. 31 | set_property value 5 ${MODELPARAM_VALUE.C_S00_AXI_ADDR_WIDTH} 32 | } 33 | 34 | proc update_MODELPARAM_VALUE.ADD_BUFMR { MODELPARAM_VALUE.ADD_BUFMR PARAM_VALUE.ADD_BUFMR } { 35 | # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value 36 | set_property value [get_property value ${PARAM_VALUE.ADD_BUFMR}] ${MODELPARAM_VALUE.ADD_BUFMR} 37 | } 38 | 39 | -------------------------------------------------------------------------------- /Projects/linux_bd/repo/ADI/ip/axi_i2s_adi/axi_streaming_dma_rx_fifo.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | 4 | library work; 5 | use work.dma_fifo; 6 | 7 | entity axi_streaming_dma_rx_fifo is 8 | generic ( 9 | RAM_ADDR_WIDTH : integer := 3; 10 | FIFO_DWIDTH : integer := 32 11 | ); 12 | port ( 13 | clk : in std_logic; 14 | resetn : in std_logic; 15 | fifo_reset : in std_logic; 16 | 17 | -- Enable DMA interface 18 | enable : in Boolean; 19 | 20 | period_len : in integer range 0 to 65535; 21 | 22 | -- Read port 23 | M_AXIS_ACLK : in std_logic; 24 | M_AXIS_TREADY : in std_logic; 25 | M_AXIS_TDATA : out std_logic_vector(FIFO_DWIDTH-1 downto 0); 26 | M_AXIS_TLAST : out std_logic; 27 | M_AXIS_TVALID : out std_logic; 28 | M_AXIS_TKEEP : out std_logic_vector(3 downto 0); 29 | 30 | -- Write port 31 | in_stb : in std_logic; 32 | in_ack : out std_logic; 33 | in_data : in std_logic_vector(FIFO_DWIDTH-1 downto 0) 34 | ); 35 | end; 36 | 37 | architecture imp of axi_streaming_dma_rx_fifo is 38 | signal out_stb : std_logic; 39 | 40 | signal period_count : integer range 0 to 65535; 41 | signal last : std_logic; 42 | begin 43 | 44 | M_AXIS_TVALID <= out_stb; 45 | 46 | fifo: entity dma_fifo 47 | generic map ( 48 | RAM_ADDR_WIDTH => RAM_ADDR_WIDTH, 49 | FIFO_DWIDTH => FIFO_DWIDTH 50 | ) 51 | port map ( 52 | clk => clk, 53 | resetn => resetn, 54 | fifo_reset => fifo_reset, 55 | in_stb => in_stb, 56 | in_ack => in_ack, 57 | in_data => in_data, 58 | out_stb => out_stb, 59 | out_ack => M_AXIS_TREADY, 60 | out_data => M_AXIS_TDATA 61 | ); 62 | 63 | M_AXIS_TKEEP <= "1111"; 64 | M_AXIS_TLAST <= '1' when period_count = 0 else '0'; 65 | 66 | period_counter: process(M_AXIS_ACLK) is 67 | begin 68 | if resetn = '0' then 69 | period_count <= period_len; 70 | else 71 | if out_stb = '1' and M_AXIS_TREADY = '1' then 72 | if period_count = 0 then 73 | period_count <= period_len; 74 | else 75 | period_count <= period_count - 1; 76 | end if; 77 | end if; 78 | end if; 79 | end process; 80 | end; 81 | -------------------------------------------------------------------------------- /Projects/dma/repo/local/ip/d_axi_i2s_audio_v2_0/src/rst_sync.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------------------------- 2 | -- Company: 3 | -- Engineer: 4 | -- 5 | -- Create Date: 10/29/2014 12:36:46 PM 6 | -- Design Name: 7 | -- Module Name: rst_sync - Behavioral 8 | -- Project Name: 9 | -- Target Devices: 10 | -- Tool Versions: 11 | -- Description: 12 | -- 13 | -- Dependencies: 14 | -- 15 | -- Revision: 16 | -- Revision 0.01 - File Created 17 | -- Additional Comments: 18 | -- 19 | ---------------------------------------------------------------------------------- 20 | 21 | 22 | library IEEE; 23 | use IEEE.STD_LOGIC_1164.ALL; 24 | 25 | Library UNISIM; 26 | use UNISIM.vcomponents.all; 27 | 28 | -- Uncomment the following library declaration if using 29 | -- arithmetic functions with Signed or Unsigned values 30 | --use IEEE.NUMERIC_STD.ALL; 31 | 32 | -- Uncomment the following library declaration if instantiating 33 | -- any Xilinx leaf cells in this code. 34 | --library UNISIM; 35 | --use UNISIM.VComponents.all; 36 | 37 | entity rst_sync is 38 | Port ( RST_I : in STD_LOGIC; 39 | CLK : in STD_LOGIC; 40 | Q_O : out STD_LOGIC); 41 | end rst_sync; 42 | 43 | architecture Behavioral of rst_sync is 44 | 45 | signal d_int: std_logic; 46 | signal q_int: std_logic; 47 | 48 | begin 49 | 50 | FDRE_inst_1 : FDPE 51 | generic map ( 52 | INIT => '0') -- Initial value of register ('0' or '1') 53 | port map ( 54 | Q => d_int, -- Data output 55 | C => CLK, -- Clock input 56 | CE => '1', -- Clock enable input 57 | PRE => RST_I, -- Synchronous reset input 58 | D => '0' -- Data input 59 | ); 60 | 61 | FDRE_inst_2 : FDPE 62 | generic map ( 63 | INIT => '0') -- Initial value of register ('0' or '1') 64 | port map ( 65 | Q => q_int, -- Data output 66 | C => CLK, -- Clock input 67 | CE => '1', -- Clock enable input 68 | PRE => RST_I, -- Synchronous reset input 69 | D => d_int -- Data input 70 | ); 71 | 72 | Q_O <= q_int; 73 | end Behavioral; 74 | -------------------------------------------------------------------------------- /Projects/linux_bd/repo/vivado-library/ip/Pmods/pmodOLEDrgb_v1_0/drivers/PmodOLEDrgb_v1_0/examples/main.c: -------------------------------------------------------------------------------- 1 | /* 2 | * main.cpp 3 | * 4 | * Created on: Feb 8, 2016 5 | * Author: tkappenm 6 | */ 7 | #include "xil_types.h" 8 | #include "xil_cache.h" 9 | #include "bitmap.h" 10 | 11 | #include "xparameters.h" 12 | #include "PmodOLEDrgb.h" 13 | void DemoInitialize(); 14 | void DemoRun(); 15 | 16 | PmodOLEDrgb oledrgb; 17 | 18 | uint8_t rgbUserFont[] = { 19 | 0x00, 0x04, 0x02, 0x1F, 0x02, 0x04, 0x00, 0x00, // 0x00 20 | 0x0E, 0x1F, 0x15, 0x1F, 0x17, 0x10, 0x1F, 0x0E, // 0x01 21 | 0x00, 0x1F, 0x11, 0x00, 0x00, 0x11, 0x1F, 0x00, // 0x02 22 | 0x00, 0x0A, 0x15, 0x11, 0x0A, 0x04, 0x00, 0x00, // 0x03 23 | 0x07, 0x0C, 0xFA, 0x2F, 0x2F, 0xFA, 0x0C, 0x07 // 0x04 24 | }; // this table defines 5 user characters, although only one is used 25 | 26 | 27 | 28 | int main(void) 29 | { 30 | Xil_ICacheEnable(); 31 | Xil_DCacheEnable(); 32 | DemoInitialize(); 33 | DemoRun(); 34 | return 0; 35 | } 36 | 37 | void DemoInitialize() 38 | { 39 | OLEDrgb_begin(&oledrgb, XPAR_PMODOLEDRGB_0_AXI_LITE_GPIO_BASEADDR, XPAR_PMODOLEDRGB_0_AXI_LITE_SPI_BASEADDR); 40 | } 41 | 42 | 43 | void DemoRun() 44 | { 45 | char ch; 46 | 47 | /* Define the user definable characters . 48 | */ 49 | for (ch = 0; ch < 5; ch++) { 50 | OLEDrgb_DefUserChar(&oledrgb,ch, &rgbUserFont[ch*8]); 51 | } 52 | 53 | OLEDrgb_SetCursor(&oledrgb, 2, 1); 54 | OLEDrgb_PutString(&oledrgb,"Digilent"); // default color (green) 55 | OLEDrgb_SetCursor(&oledrgb, 4, 4); 56 | OLEDrgb_SetFontColor(&oledrgb ,OLEDrgb_BuildRGB( 0, 0, 255)); // blue font 57 | OLEDrgb_PutString(&oledrgb,"OledRGB"); 58 | 59 | OLEDrgb_SetFontColor(&oledrgb,OLEDrgb_BuildRGB( 200, 200, 44)); 60 | OLEDrgb_SetCursor(&oledrgb,1, 6); 61 | OLEDrgb_PutChar(&oledrgb, 4); 62 | 63 | OLEDrgb_SetFontColor(&oledrgb,OLEDrgb_BuildRGB(200, 12,44)); 64 | OLEDrgb_SetCursor(&oledrgb,5, 6); 65 | OLEDrgb_PutString(&oledrgb,"Demo"); 66 | OLEDrgb_PutChar(&oledrgb, 0); 67 | 68 | usleep(5000);//Wait 5 seconds 69 | 70 | OLEDrgb_DrawBitmap(&oledrgb,0,0,95,63, (u8*)tommy); 71 | } 72 | -------------------------------------------------------------------------------- /Projects/linux_bd/repo/vivado-library/ip/axi_i2s_adi_1.2/hdl/adi_common/axi_streaming_dma_rx_fifo.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | 4 | library adi_common_v1_00_a; 5 | use adi_common_v1_00_a.dma_fifo; 6 | 7 | entity axi_streaming_dma_rx_fifo is 8 | generic ( 9 | RAM_ADDR_WIDTH : integer := 3; 10 | FIFO_DWIDTH : integer := 32 11 | ); 12 | port ( 13 | clk : in std_logic; 14 | resetn : in std_logic; 15 | fifo_reset : in std_logic; 16 | 17 | -- Enable DMA interface 18 | enable : in Boolean; 19 | 20 | period_len : in integer range 0 to 65535; 21 | 22 | -- Read port 23 | M_AXIS_ACLK : in std_logic; 24 | M_AXIS_TREADY : in std_logic; 25 | M_AXIS_TDATA : out std_logic_vector(FIFO_DWIDTH-1 downto 0); 26 | M_AXIS_TLAST : out std_logic; 27 | M_AXIS_TVALID : out std_logic; 28 | M_AXIS_TKEEP : out std_logic_vector(3 downto 0); 29 | 30 | -- Write port 31 | in_stb : in std_logic; 32 | in_ack : out std_logic; 33 | in_data : in std_logic_vector(FIFO_DWIDTH-1 downto 0) 34 | ); 35 | end; 36 | 37 | architecture imp of axi_streaming_dma_rx_fifo is 38 | signal out_stb : std_logic; 39 | 40 | signal period_count : integer range 0 to 65535; 41 | signal last : std_logic; 42 | begin 43 | 44 | M_AXIS_TVALID <= out_stb; 45 | 46 | fifo: entity dma_fifo 47 | generic map ( 48 | RAM_ADDR_WIDTH => RAM_ADDR_WIDTH, 49 | FIFO_DWIDTH => FIFO_DWIDTH 50 | ) 51 | port map ( 52 | clk => clk, 53 | resetn => resetn, 54 | fifo_reset => fifo_reset, 55 | in_stb => in_stb, 56 | in_ack => in_ack, 57 | in_data => in_data, 58 | out_stb => out_stb, 59 | out_ack => M_AXIS_TREADY, 60 | out_data => M_AXIS_TDATA 61 | ); 62 | 63 | M_AXIS_TKEEP <= "1111"; 64 | M_AXIS_TLAST <= '1' when period_count = 0 else '0'; 65 | 66 | period_counter: process(M_AXIS_ACLK) is 67 | begin 68 | if resetn = '0' then 69 | period_count <= period_len; 70 | else 71 | if out_stb = '1' and M_AXIS_TREADY = '1' then 72 | if period_count = 0 then 73 | period_count <= period_len; 74 | else 75 | period_count <= period_count - 1; 76 | end if; 77 | end if; 78 | end if; 79 | end process; 80 | end; -------------------------------------------------------------------------------- /Projects/linux_bd/repo/vivado-library/ip/PWM_1.0/drivers/PWM_v1_0/src/PWM_selftest.c: -------------------------------------------------------------------------------- 1 | 2 | /***************************** Include Files *******************************/ 3 | #include "PWM.h" 4 | #include "xparameters.h" 5 | #include "stdio.h" 6 | #include "xil_io.h" 7 | 8 | /************************** Constant Definitions ***************************/ 9 | #define READ_WRITE_MUL_FACTOR 0x10 10 | 11 | /************************** Function Definitions ***************************/ 12 | /** 13 | * 14 | * Run a self-test on the driver/device. Note this may be a destructive test if 15 | * resets of the device are performed. 16 | * 17 | * If the hardware system is not built correctly, this function may never 18 | * return to the caller. 19 | * 20 | * @param baseaddr_p is the base address of the PWMinstance to be worked on. 21 | * 22 | * @return 23 | * 24 | * - XST_SUCCESS if all self-test code passed 25 | * - XST_FAILURE if any self-test code failed 26 | * 27 | * @note Caching must be turned off for this function to work. 28 | * @note Self test may fail if data memory and device are not on the same bus. 29 | * 30 | */ 31 | XStatus PWM_Reg_SelfTest(void * baseaddr_p) 32 | { 33 | u32 baseaddr; 34 | int write_loop_index; 35 | int read_loop_index; 36 | int Index; 37 | 38 | baseaddr = (u32) baseaddr_p; 39 | 40 | xil_printf("******************************\n\r"); 41 | xil_printf("* User Peripheral Self Test\n\r"); 42 | xil_printf("******************************\n\n\r"); 43 | 44 | /* 45 | * Write to user logic slave module register(s) and read back 46 | */ 47 | xil_printf("User logic slave module test...\n\r"); 48 | 49 | for (write_loop_index = 0 ; write_loop_index < 4; write_loop_index++) 50 | PWM_mWriteReg (baseaddr, write_loop_index*4, (write_loop_index+1)*READ_WRITE_MUL_FACTOR); 51 | for (read_loop_index = 0 ; read_loop_index < 4; read_loop_index++) 52 | if ( PWM_mReadReg (baseaddr, read_loop_index*4) != (read_loop_index+1)*READ_WRITE_MUL_FACTOR){ 53 | xil_printf ("Error reading register value at address %x\n", (int)baseaddr + read_loop_index*4); 54 | return XST_FAILURE; 55 | } 56 | 57 | xil_printf(" - slave register write/read passed\n\n\r"); 58 | 59 | return XST_SUCCESS; 60 | } 61 | -------------------------------------------------------------------------------- /Projects/linux_bd/repo/vivado-library/ip/Pmods/PmodGPS_v1_1/drivers/PmodGPS_v1_1/src/PmodGPS_selftest.c: -------------------------------------------------------------------------------- 1 | 2 | /***************************** Include Files *******************************/ 3 | #include "PmodGPS.h" 4 | #include "xparameters.h" 5 | #include "stdio.h" 6 | #include "xil_io.h" 7 | 8 | /************************** Constant Definitions ***************************/ 9 | #define READ_WRITE_MUL_FACTOR 0x10 10 | 11 | /************************** Function Definitions ***************************/ 12 | /** 13 | * 14 | * Run a self-test on the driver/device. Note this may be a destructive test if 15 | * resets of the device are performed. 16 | * 17 | * If the hardware system is not built correctly, this function may never 18 | * return to the caller. 19 | * 20 | * @param baseaddr_p is the base address of the PMODOLEDRGBinstance to be worked on. 21 | * 22 | * @return 23 | * 24 | * - XST_SUCCESS if all self-test code passed 25 | * - XST_FAILURE if any self-test code failed 26 | * 27 | * @note Caching must be turned off for this function to work. 28 | * @note Self test may fail if data memory and device are not on the same bus. 29 | * 30 | */ 31 | XStatus PMODGPS_Reg_SelfTest(void * baseaddr_p) 32 | { 33 | u32 baseaddr; 34 | int write_loop_index; 35 | int read_loop_index; 36 | int Index; 37 | 38 | baseaddr = (u32) baseaddr_p; 39 | 40 | xil_printf("******************************\n\r"); 41 | xil_printf("* User Peripheral Self Test\n\r"); 42 | xil_printf("******************************\n\n\r"); 43 | 44 | /* 45 | * Write to user logic slave module register(s) and read back 46 | */ 47 | xil_printf("User logic slave module test...\n\r"); 48 | 49 | for (write_loop_index = 0 ; write_loop_index < 4; write_loop_index++) 50 | PMODGPS_mWriteReg (baseaddr, write_loop_index*4, (write_loop_index+1)*READ_WRITE_MUL_FACTOR); 51 | for (read_loop_index = 0 ; read_loop_index < 4; read_loop_index++) 52 | if ( PMODGPS_mReadReg (baseaddr, read_loop_index*4) != (read_loop_index+1)*READ_WRITE_MUL_FACTOR){ 53 | xil_printf ("Error reading register value at address %x\n", (int)baseaddr + read_loop_index*4); 54 | return XST_FAILURE; 55 | } 56 | 57 | xil_printf(" - slave register write/read passed\n\n\r"); 58 | 59 | return XST_SUCCESS; 60 | } 61 | -------------------------------------------------------------------------------- /Projects/linux_bd/repo/vivado-library/ip/Pmods/PmodAMP2_v1_0/ipshared/digilentinc.com/pwm_v1_0/drivers/PWM_v1_0/src/PWM_selftest.c: -------------------------------------------------------------------------------- 1 | 2 | /***************************** Include Files *******************************/ 3 | #include "PWM.h" 4 | #include "xparameters.h" 5 | #include "stdio.h" 6 | #include "xil_io.h" 7 | 8 | /************************** Constant Definitions ***************************/ 9 | #define READ_WRITE_MUL_FACTOR 0x10 10 | 11 | /************************** Function Definitions ***************************/ 12 | /** 13 | * 14 | * Run a self-test on the driver/device. Note this may be a destructive test if 15 | * resets of the device are performed. 16 | * 17 | * If the hardware system is not built correctly, this function may never 18 | * return to the caller. 19 | * 20 | * @param baseaddr_p is the base address of the PWMinstance to be worked on. 21 | * 22 | * @return 23 | * 24 | * - XST_SUCCESS if all self-test code passed 25 | * - XST_FAILURE if any self-test code failed 26 | * 27 | * @note Caching must be turned off for this function to work. 28 | * @note Self test may fail if data memory and device are not on the same bus. 29 | * 30 | */ 31 | XStatus PWM_Reg_SelfTest(void * baseaddr_p) 32 | { 33 | u32 baseaddr; 34 | int write_loop_index; 35 | int read_loop_index; 36 | int Index; 37 | 38 | baseaddr = (u32) baseaddr_p; 39 | 40 | xil_printf("******************************\n\r"); 41 | xil_printf("* User Peripheral Self Test\n\r"); 42 | xil_printf("******************************\n\n\r"); 43 | 44 | /* 45 | * Write to user logic slave module register(s) and read back 46 | */ 47 | xil_printf("User logic slave module test...\n\r"); 48 | 49 | for (write_loop_index = 0 ; write_loop_index < 4; write_loop_index++) 50 | PWM_mWriteReg (baseaddr, write_loop_index*4, (write_loop_index+1)*READ_WRITE_MUL_FACTOR); 51 | for (read_loop_index = 0 ; read_loop_index < 4; read_loop_index++) 52 | if ( PWM_mReadReg (baseaddr, read_loop_index*4) != (read_loop_index+1)*READ_WRITE_MUL_FACTOR){ 53 | xil_printf ("Error reading register value at address %x\n", (int)baseaddr + read_loop_index*4); 54 | return XST_FAILURE; 55 | } 56 | 57 | xil_printf(" - slave register write/read passed\n\n\r"); 58 | 59 | return XST_SUCCESS; 60 | } 61 | -------------------------------------------------------------------------------- /Projects/linux_bd/repo/vivado-library/ip/axi_i2s_adi_1.2/drivers/axi_i2s_adi_v1_0/src/axi_i2s_adi_selftest.c: -------------------------------------------------------------------------------- 1 | 2 | /***************************** Include Files *******************************/ 3 | #include "axi_i2s_adi.h" 4 | #include "xparameters.h" 5 | #include "stdio.h" 6 | #include "xil_io.h" 7 | 8 | /************************** Constant Definitions ***************************/ 9 | #define READ_WRITE_MUL_FACTOR 0x10 10 | 11 | /************************** Function Definitions ***************************/ 12 | /** 13 | * 14 | * Run a self-test on the driver/device. Note this may be a destructive test if 15 | * resets of the device are performed. 16 | * 17 | * If the hardware system is not built correctly, this function may never 18 | * return to the caller. 19 | * 20 | * @param baseaddr_p is the base address of the AXI_I2S_ADIinstance to be worked on. 21 | * 22 | * @return 23 | * 24 | * - XST_SUCCESS if all self-test code passed 25 | * - XST_FAILURE if any self-test code failed 26 | * 27 | * @note Caching must be turned off for this function to work. 28 | * @note Self test may fail if data memory and device are not on the same bus. 29 | * 30 | */ 31 | XStatus AXI_I2S_ADI_Reg_SelfTest(void * baseaddr_p) 32 | { 33 | u32 baseaddr; 34 | int write_loop_index; 35 | int read_loop_index; 36 | int Index; 37 | 38 | baseaddr = (u32) baseaddr_p; 39 | 40 | xil_printf("******************************\n\r"); 41 | xil_printf("* User Peripheral Self Test\n\r"); 42 | xil_printf("******************************\n\n\r"); 43 | 44 | /* 45 | * Write to user logic slave module register(s) and read back 46 | */ 47 | xil_printf("User logic slave module test...\n\r"); 48 | 49 | for (write_loop_index = 0 ; write_loop_index < 4; write_loop_index++) 50 | AXI_I2S_ADI_mWriteReg (baseaddr, write_loop_index*4, (write_loop_index+1)*READ_WRITE_MUL_FACTOR); 51 | for (read_loop_index = 0 ; read_loop_index < 4; read_loop_index++) 52 | if ( AXI_I2S_ADI_mReadReg (baseaddr, read_loop_index*4) != (read_loop_index+1)*READ_WRITE_MUL_FACTOR){ 53 | xil_printf ("Error reading register value at address %x\n", (int)baseaddr + read_loop_index*4); 54 | return XST_FAILURE; 55 | } 56 | 57 | xil_printf(" - slave register write/read passed\n\n\r"); 58 | 59 | return XST_SUCCESS; 60 | } 61 | -------------------------------------------------------------------------------- /Projects/linux_bd/repo/vivado-library/ip/Pmods/pmodOLEDrgb_v1_0/drivers/PmodOLEDrgb_v1_0/src/PmodOLEDrgb_selftest.c: -------------------------------------------------------------------------------- 1 | 2 | /***************************** Include Files *******************************/ 3 | #include "PmodOLEDrgb.h" 4 | #include "xparameters.h" 5 | #include "stdio.h" 6 | #include "xil_io.h" 7 | 8 | /************************** Constant Definitions ***************************/ 9 | #define READ_WRITE_MUL_FACTOR 0x10 10 | 11 | /************************** Function Definitions ***************************/ 12 | /** 13 | * 14 | * Run a self-test on the driver/device. Note this may be a destructive test if 15 | * resets of the device are performed. 16 | * 17 | * If the hardware system is not built correctly, this function may never 18 | * return to the caller. 19 | * 20 | * @param baseaddr_p is the base address of the PMODOLEDRGBinstance to be worked on. 21 | * 22 | * @return 23 | * 24 | * - XST_SUCCESS if all self-test code passed 25 | * - XST_FAILURE if any self-test code failed 26 | * 27 | * @note Caching must be turned off for this function to work. 28 | * @note Self test may fail if data memory and device are not on the same bus. 29 | * 30 | */ 31 | XStatus PMODOLEDRGB_Reg_SelfTest(void * baseaddr_p) 32 | { 33 | u32 baseaddr; 34 | int write_loop_index; 35 | int read_loop_index; 36 | int Index; 37 | 38 | baseaddr = (u32) baseaddr_p; 39 | 40 | xil_printf("******************************\n\r"); 41 | xil_printf("* User Peripheral Self Test\n\r"); 42 | xil_printf("******************************\n\n\r"); 43 | 44 | /* 45 | * Write to user logic slave module register(s) and read back 46 | */ 47 | xil_printf("User logic slave module test...\n\r"); 48 | 49 | for (write_loop_index = 0 ; write_loop_index < 4; write_loop_index++) 50 | PMODOLEDRGB_mWriteReg (baseaddr, write_loop_index*4, (write_loop_index+1)*READ_WRITE_MUL_FACTOR); 51 | for (read_loop_index = 0 ; read_loop_index < 4; read_loop_index++) 52 | if ( PMODOLEDRGB_mReadReg (baseaddr, read_loop_index*4) != (read_loop_index+1)*READ_WRITE_MUL_FACTOR){ 53 | xil_printf ("Error reading register value at address %x\n", (int)baseaddr + read_loop_index*4); 54 | return XST_FAILURE; 55 | } 56 | 57 | xil_printf(" - slave register write/read passed\n\n\r"); 58 | 59 | return XST_SUCCESS; 60 | } 61 | -------------------------------------------------------------------------------- /Projects/dma/repo/local/ip/d_axi_i2s_audio_v2_0/src/Sync_ff.vhd: -------------------------------------------------------------------------------- 1 | ------------------------------------------------------------------------------- 2 | -- 3 | -- COPYRIGHT (C) 2012, Digilent RO. All rights reserved 4 | -- 5 | ------------------------------------------------------------------------------- 6 | -- FILE NAME : Sync_ff.vhd 7 | -- MODULE NAME : Synchornisation Flip-Flops 8 | -- AUTHOR : Hegbeli Ciprian 9 | -- AUTHOR'S EMAIL : ciprian.hegbeli@digilent.ro 10 | ------------------------------------------------------------------------------- 11 | -- REVISION HISTORY 12 | -- VERSION DATE AUTHOR DESCRIPTION 13 | -- 1.0 2014-04-02 CiprianH Created 14 | ------------------------------------------------------------------------------- 15 | -- KEYWORDS : Sync 16 | ------------------------------------------------------------------------------- 17 | library IEEE; 18 | use IEEE.STD_LOGIC_1164.ALL; 19 | 20 | ------------------------------------------------------------------------ 21 | -- Module Declaration 22 | ------------------------------------------------------------------------ 23 | entity Sync_ff is 24 | Port ( 25 | -- Input Clock 26 | CLK : in STD_LOGIC; 27 | -- Asynchorn signal 28 | D_I : in STD_LOGIC; 29 | -- Sync signal 30 | Q_O : out STD_LOGIC 31 | ); 32 | end Sync_ff; 33 | 34 | architecture Behavioral of Sync_ff is 35 | 36 | ------------------------------------------------------------------------ 37 | -- Signal Declarations 38 | ------------------------------------------------------------------------ 39 | signal sreg : std_logic_vector(1 downto 0); 40 | 41 | attribute ASYNC_REG : string; 42 | attribute ASYNC_REG of sreg : signal is "TRUE"; 43 | 44 | attribute TIG : string; 45 | attribute TIG of D_I: signal is "TRUE"; 46 | 47 | begin 48 | 49 | ------------------------------------------------------------------------ 50 | -- Output synchro with second CLK 51 | ------------------------------------------------------------------------ 52 | sync_b_proc_2: process(CLK) 53 | begin 54 | if rising_edge(CLK) then 55 | Q_O <= sreg(1); 56 | sreg <= sreg(0) & D_I; 57 | end if; 58 | end process; 59 | 60 | end Behavioral; 61 | 62 | -------------------------------------------------------------------------------- /Projects/hdmi_out/sdk/displaydemo/src/display_demo.h: -------------------------------------------------------------------------------- 1 | /************************************************************************/ 2 | /* */ 3 | /* display_demo.h -- ZYBO display demonstration */ 4 | /* */ 5 | /************************************************************************/ 6 | /* Author: Sam Bobrowicz */ 7 | /* Copyright 2016, Digilent Inc. */ 8 | /************************************************************************/ 9 | /* Module Description: */ 10 | /* */ 11 | /* This file contains code for running a demonstration of the */ 12 | /* HDMI output capabilities on the ZYBO. It is a good */ 13 | /* example of how to properly use the display_ctrl drivers. */ 14 | /* */ 15 | /************************************************************************/ 16 | /* Revision History: */ 17 | /* */ 18 | /* 2/5/2016(SamB): Created */ 19 | /* */ 20 | /************************************************************************/ 21 | 22 | #ifndef DISPLAY_DEMO_H_ 23 | #define DISPLAY_DEMO_H_ 24 | 25 | /* ------------------------------------------------------------ */ 26 | /* Include File Definitions */ 27 | /* ------------------------------------------------------------ */ 28 | 29 | #include "xil_types.h" 30 | 31 | /* ------------------------------------------------------------ */ 32 | /* Miscellaneous Declarations */ 33 | /* ------------------------------------------------------------ */ 34 | 35 | #define DEMO_PATTERN_0 0 36 | #define DEMO_PATTERN_1 1 37 | 38 | #define DEMO_MAX_FRAME (1920*1080*4) 39 | #define DEMO_STRIDE (1920 * 4) 40 | 41 | /* ------------------------------------------------------------ */ 42 | /* Procedure Declarations */ 43 | /* ------------------------------------------------------------ */ 44 | 45 | void DemoInitialize(); 46 | void DemoRun(); 47 | void DemoPrintMenu(); 48 | void DemoChangeRes(); 49 | void DemoCRMenu(); 50 | void DemoInvertFrame(u8 *srcFrame, u8 *destFrame, u32 width, u32 height, u32 stride); 51 | void DemoPrintTest(u8 *frame, u32 width, u32 height, u32 stride, int pattern); 52 | 53 | /* ------------------------------------------------------------ */ 54 | 55 | /************************************************************************/ 56 | 57 | #endif /* DISPLAY_DEMO_H_ */ 58 | --------------------------------------------------------------------------------