├── .gitignore ├── .gitmodules ├── README.md ├── hw_handoff ├── .keep ├── hdmi_in._wrapper.hdf └── hdmi_in_wrapper.hdf ├── proj ├── cleanup.cmd ├── cleanup.sh ├── create_project.tcl └── release.py ├── repo ├── cache │ └── .keep └── local │ └── .keep ├── sdk ├── .keep ├── HDMI_IN │ ├── .cproject │ ├── .project │ ├── Debug │ │ ├── HDMI_IN.elf │ │ └── HDMI_IN.elf.size │ └── src │ │ ├── README.txt │ │ ├── display_ctrl │ │ ├── display_ctrl.c │ │ ├── display_ctrl.h │ │ └── vga_modes.h │ │ ├── dynclk │ │ ├── dynclk.c │ │ └── dynclk.h │ │ ├── intc │ │ ├── intc.c │ │ └── intc.h │ │ ├── lscript.ld │ │ ├── timer_ps │ │ ├── timer_ps.c │ │ └── timer_ps.h │ │ ├── video_capture │ │ ├── video_capture.c │ │ └── video_capture.h │ │ ├── video_demo.c │ │ └── video_demo.h ├── HDMI_IN_bsp │ ├── .cproject │ ├── .project │ ├── .sdkproject │ ├── Makefile │ └── system.mss └── hdmi_in_wrapper_hw_platform_0 │ ├── .project │ └── system.hdf └── src ├── bd ├── .keep └── hdmi_in │ ├── hdl │ ├── hdmi_in.hwdef │ ├── hdmi_in.vhd │ └── hdmi_in_wrapper.vhd │ ├── hdmi_in.bd │ ├── hdmi_in.bxml │ ├── hdmi_in_ooc.xdc │ ├── hw_handoff │ ├── hdmi_in.hwh │ └── hdmi_in_bd.tcl │ ├── ip │ ├── hdmi_in_auto_pc_0 │ │ ├── hdmi_in_auto_pc_0.xci │ │ ├── hdmi_in_auto_pc_0.xml │ │ ├── hdmi_in_auto_pc_0_ooc.xdc │ │ ├── sim │ │ │ └── hdmi_in_auto_pc_0.v │ │ └── synth │ │ │ └── hdmi_in_auto_pc_0.v │ ├── hdmi_in_auto_pc_1 │ │ ├── hdmi_in_auto_pc_1.xci │ │ ├── hdmi_in_auto_pc_1.xml │ │ ├── hdmi_in_auto_pc_1_ooc.xdc │ │ ├── sim │ │ │ └── hdmi_in_auto_pc_1.v │ │ └── synth │ │ │ └── hdmi_in_auto_pc_1.v │ ├── hdmi_in_auto_us_df_0 │ │ ├── hdmi_in_auto_us_df_0.xci │ │ ├── hdmi_in_auto_us_df_0.xml │ │ ├── hdmi_in_auto_us_df_0_clocks.xdc │ │ ├── hdmi_in_auto_us_df_0_ooc.xdc │ │ ├── sim │ │ │ └── hdmi_in_auto_us_df_0.v │ │ └── synth │ │ │ └── hdmi_in_auto_us_df_0.v │ ├── hdmi_in_auto_us_df_1 │ │ ├── hdmi_in_auto_us_df_1.xci │ │ ├── hdmi_in_auto_us_df_1.xml │ │ ├── hdmi_in_auto_us_df_1_clocks.xdc │ │ ├── hdmi_in_auto_us_df_1_ooc.xdc │ │ ├── sim │ │ │ └── hdmi_in_auto_us_df_1.v │ │ └── synth │ │ │ └── hdmi_in_auto_us_df_1.v │ ├── hdmi_in_axi_dynclk_0_0 │ │ ├── hdmi_in_axi_dynclk_0_0.xci │ │ ├── hdmi_in_axi_dynclk_0_0.xml │ │ ├── sim │ │ │ └── hdmi_in_axi_dynclk_0_0.vhd │ │ └── synth │ │ │ └── hdmi_in_axi_dynclk_0_0.vhd │ ├── hdmi_in_axi_gpio_btn_0 │ │ ├── hdmi_in_axi_gpio_btn_0.xci │ │ ├── hdmi_in_axi_gpio_btn_0.xdc │ │ ├── hdmi_in_axi_gpio_btn_0.xml │ │ ├── hdmi_in_axi_gpio_btn_0_board.xdc │ │ ├── hdmi_in_axi_gpio_btn_0_ooc.xdc │ │ ├── sim │ │ │ └── hdmi_in_axi_gpio_btn_0.vhd │ │ └── synth │ │ │ └── hdmi_in_axi_gpio_btn_0.vhd │ ├── hdmi_in_axi_gpio_led_0 │ │ ├── hdmi_in_axi_gpio_led_0.xci │ │ ├── hdmi_in_axi_gpio_led_0.xdc │ │ ├── hdmi_in_axi_gpio_led_0.xml │ │ ├── hdmi_in_axi_gpio_led_0_board.xdc │ │ ├── hdmi_in_axi_gpio_led_0_ooc.xdc │ │ ├── sim │ │ │ └── hdmi_in_axi_gpio_led_0.vhd │ │ └── synth │ │ │ └── hdmi_in_axi_gpio_led_0.vhd │ ├── hdmi_in_axi_gpio_sw_0 │ │ ├── hdmi_in_axi_gpio_sw_0.xci │ │ ├── hdmi_in_axi_gpio_sw_0.xdc │ │ ├── hdmi_in_axi_gpio_sw_0.xml │ │ ├── hdmi_in_axi_gpio_sw_0_board.xdc │ │ ├── hdmi_in_axi_gpio_sw_0_ooc.xdc │ │ ├── sim │ │ │ └── hdmi_in_axi_gpio_sw_0.vhd │ │ └── synth │ │ │ └── hdmi_in_axi_gpio_sw_0.vhd │ ├── hdmi_in_axi_gpio_video_0 │ │ ├── hdmi_in_axi_gpio_video_0.xci │ │ ├── hdmi_in_axi_gpio_video_0.xdc │ │ ├── hdmi_in_axi_gpio_video_0.xml │ │ ├── hdmi_in_axi_gpio_video_0_board.xdc │ │ ├── hdmi_in_axi_gpio_video_0_ooc.xdc │ │ ├── sim │ │ │ └── hdmi_in_axi_gpio_video_0.vhd │ │ └── synth │ │ │ └── hdmi_in_axi_gpio_video_0.vhd │ ├── hdmi_in_axi_mem_intercon_0 │ │ ├── hdmi_in_axi_mem_intercon_0.xci │ │ └── hdmi_in_axi_mem_intercon_0.xml │ ├── hdmi_in_axi_vdma_0_0 │ │ ├── hdmi_in_axi_vdma_0_0.xci │ │ ├── hdmi_in_axi_vdma_0_0.xdc │ │ ├── hdmi_in_axi_vdma_0_0.xml │ │ ├── hdmi_in_axi_vdma_0_0_clocks.xdc │ │ ├── hdmi_in_axi_vdma_0_0_ooc.xdc │ │ ├── sim │ │ │ └── hdmi_in_axi_vdma_0_0.vhd │ │ └── synth │ │ │ └── hdmi_in_axi_vdma_0_0.vhd │ ├── hdmi_in_dvi2rgb_0_0 │ │ ├── hdmi_in_dvi2rgb_0_0.xci │ │ ├── hdmi_in_dvi2rgb_0_0.xml │ │ ├── sim │ │ │ └── hdmi_in_dvi2rgb_0_0.vhd │ │ ├── src │ │ │ ├── 1024_edid.data │ │ │ ├── 1080_edid.data │ │ │ ├── 720p_edid.data │ │ │ ├── 900p_edid.data │ │ │ ├── dvi2rgb.xdc │ │ │ └── dvi2rgb_ooc.xdc │ │ └── synth │ │ │ └── hdmi_in_dvi2rgb_0_0.vhd │ ├── hdmi_in_m00_data_fifo_0 │ │ ├── hdmi_in_m00_data_fifo_0.xci │ │ ├── hdmi_in_m00_data_fifo_0.xml │ │ ├── hdmi_in_m00_data_fifo_0_ooc.xdc │ │ ├── sim │ │ │ └── hdmi_in_m00_data_fifo_0.v │ │ └── synth │ │ │ └── hdmi_in_m00_data_fifo_0.v │ ├── hdmi_in_m00_regslice_0 │ │ ├── hdmi_in_m00_regslice_0.xci │ │ ├── hdmi_in_m00_regslice_0.xml │ │ ├── hdmi_in_m00_regslice_0_ooc.xdc │ │ ├── sim │ │ │ └── hdmi_in_m00_regslice_0.v │ │ └── synth │ │ │ └── hdmi_in_m00_regslice_0.v │ ├── hdmi_in_proc_sys_reset_0_0 │ │ ├── hdmi_in_proc_sys_reset_0_0.xci │ │ ├── hdmi_in_proc_sys_reset_0_0.xdc │ │ ├── hdmi_in_proc_sys_reset_0_0.xml │ │ ├── hdmi_in_proc_sys_reset_0_0_board.xdc │ │ ├── hdmi_in_proc_sys_reset_0_0_ooc.xdc │ │ ├── sim │ │ │ └── hdmi_in_proc_sys_reset_0_0.vhd │ │ └── synth │ │ │ └── hdmi_in_proc_sys_reset_0_0.vhd │ ├── hdmi_in_processing_system7_0_0 │ │ ├── hdl │ │ │ └── verilog │ │ │ │ ├── hdmi_in_processing_system7_0_0.hwdef │ │ │ │ └── processing_system7_v5_5_processing_system7.v │ │ ├── hdmi_in_processing_system7_0_0.xci │ │ ├── hdmi_in_processing_system7_0_0.xdc │ │ ├── hdmi_in_processing_system7_0_0.xml │ │ ├── ps7_init.c │ │ ├── ps7_init.h │ │ ├── ps7_init.html │ │ ├── ps7_init.tcl │ │ ├── ps7_init_gpl.c │ │ ├── ps7_init_gpl.h │ │ ├── ps7_parameters.xml │ │ ├── sim │ │ │ ├── hdmi_in_processing_system7_0_0.v │ │ │ ├── libps7.so │ │ │ └── libremoteport.so │ │ └── synth │ │ │ └── hdmi_in_processing_system7_0_0.v │ ├── hdmi_in_processing_system7_0_axi_periph_0 │ │ ├── hdmi_in_processing_system7_0_axi_periph_0.xci │ │ └── hdmi_in_processing_system7_0_axi_periph_0.xml │ ├── hdmi_in_rgb2vga_0_0 │ │ ├── hdmi_in_rgb2vga_0_0.xci │ │ ├── hdmi_in_rgb2vga_0_0.xml │ │ ├── sim │ │ │ └── hdmi_in_rgb2vga_0_0.vhd │ │ └── synth │ │ │ └── hdmi_in_rgb2vga_0_0.vhd │ ├── hdmi_in_rst_processing_system7_0_100M_0 │ │ ├── hdmi_in_rst_processing_system7_0_100M_0.xci │ │ ├── hdmi_in_rst_processing_system7_0_100M_0.xdc │ │ ├── hdmi_in_rst_processing_system7_0_100M_0.xml │ │ ├── hdmi_in_rst_processing_system7_0_100M_0_board.xdc │ │ ├── hdmi_in_rst_processing_system7_0_100M_0_ooc.xdc │ │ ├── sim │ │ │ └── hdmi_in_rst_processing_system7_0_100M_0.vhd │ │ └── synth │ │ │ └── hdmi_in_rst_processing_system7_0_100M_0.vhd │ ├── hdmi_in_rst_processing_system7_0_150M_0 │ │ ├── hdmi_in_rst_processing_system7_0_150M_0.xci │ │ ├── hdmi_in_rst_processing_system7_0_150M_0.xdc │ │ ├── hdmi_in_rst_processing_system7_0_150M_0.xml │ │ ├── hdmi_in_rst_processing_system7_0_150M_0_board.xdc │ │ ├── hdmi_in_rst_processing_system7_0_150M_0_ooc.xdc │ │ ├── sim │ │ │ └── hdmi_in_rst_processing_system7_0_150M_0.vhd │ │ └── synth │ │ │ └── hdmi_in_rst_processing_system7_0_150M_0.vhd │ ├── hdmi_in_s00_regslice_0 │ │ ├── hdmi_in_s00_regslice_0.xci │ │ ├── hdmi_in_s00_regslice_0.xml │ │ ├── hdmi_in_s00_regslice_0_ooc.xdc │ │ ├── sim │ │ │ └── hdmi_in_s00_regslice_0.v │ │ └── synth │ │ │ └── hdmi_in_s00_regslice_0.v │ ├── hdmi_in_s01_regslice_0 │ │ ├── hdmi_in_s01_regslice_0.xci │ │ ├── hdmi_in_s01_regslice_0.xml │ │ ├── hdmi_in_s01_regslice_0_ooc.xdc │ │ ├── sim │ │ │ └── hdmi_in_s01_regslice_0.v │ │ └── synth │ │ │ └── hdmi_in_s01_regslice_0.v │ ├── hdmi_in_v_axi4s_vid_out_0_0 │ │ ├── hdmi_in_v_axi4s_vid_out_0_0.xci │ │ ├── hdmi_in_v_axi4s_vid_out_0_0.xml │ │ ├── hdmi_in_v_axi4s_vid_out_0_0_clocks.xdc │ │ ├── hdmi_in_v_axi4s_vid_out_0_0_ooc.xdc │ │ ├── sim │ │ │ └── hdmi_in_v_axi4s_vid_out_0_0.v │ │ └── synth │ │ │ └── hdmi_in_v_axi4s_vid_out_0_0.v │ ├── hdmi_in_v_tc_0_0 │ │ ├── hdmi_in_v_tc_0_0.xci │ │ ├── hdmi_in_v_tc_0_0.xml │ │ ├── hdmi_in_v_tc_0_0_clocks.xdc │ │ ├── hdmi_in_v_tc_0_0_ooc.xdc │ │ ├── sim │ │ │ └── hdmi_in_v_tc_0_0.vhd │ │ └── synth │ │ │ └── hdmi_in_v_tc_0_0.vhd │ ├── hdmi_in_v_tc_1_0 │ │ ├── hdmi_in_v_tc_1_0.xci │ │ ├── hdmi_in_v_tc_1_0.xml │ │ ├── hdmi_in_v_tc_1_0_clocks.xdc │ │ ├── hdmi_in_v_tc_1_0_ooc.xdc │ │ ├── sim │ │ │ └── hdmi_in_v_tc_1_0.vhd │ │ └── synth │ │ │ └── hdmi_in_v_tc_1_0.vhd │ ├── hdmi_in_v_vid_in_axi4s_0_0 │ │ ├── hdmi_in_v_vid_in_axi4s_0_0.xci │ │ ├── hdmi_in_v_vid_in_axi4s_0_0.xml │ │ ├── hdmi_in_v_vid_in_axi4s_0_0_clocks.xdc │ │ ├── hdmi_in_v_vid_in_axi4s_0_0_ooc.xdc │ │ ├── sim │ │ │ └── hdmi_in_v_vid_in_axi4s_0_0.v │ │ └── synth │ │ │ └── hdmi_in_v_vid_in_axi4s_0_0.v │ ├── hdmi_in_xbar_0 │ │ ├── hdmi_in_xbar_0.xci │ │ ├── hdmi_in_xbar_0.xml │ │ ├── hdmi_in_xbar_0_ooc.xdc │ │ ├── sim │ │ │ └── hdmi_in_xbar_0.v │ │ └── synth │ │ │ └── hdmi_in_xbar_0.v │ ├── hdmi_in_xbar_1 │ │ ├── hdmi_in_xbar_1.xci │ │ ├── hdmi_in_xbar_1.xml │ │ ├── hdmi_in_xbar_1_ooc.xdc │ │ ├── sim │ │ │ └── hdmi_in_xbar_1.v │ │ └── synth │ │ │ └── hdmi_in_xbar_1.v │ ├── hdmi_in_xlconcat_0_0 │ │ ├── hdmi_in_xlconcat_0_0.xci │ │ ├── hdmi_in_xlconcat_0_0.xml │ │ ├── sim │ │ │ └── hdmi_in_xlconcat_0_0.vhd │ │ └── synth │ │ │ └── hdmi_in_xlconcat_0_0.vhd │ └── hdmi_in_xlconstant_0_0 │ │ ├── hdmi_in_xlconstant_0_0.xci │ │ ├── hdmi_in_xlconstant_0_0.xml │ │ └── sim │ │ └── hdmi_in_xlconstant_0_0.vhd │ ├── ipshared │ ├── 1923 │ │ └── hdl │ │ │ └── v_axi4s_vid_out_v4_0_vl_rfs.v │ ├── 6039 │ │ └── hdl │ │ │ └── lib_srl_fifo_v1_0_rfs.vhd │ ├── 6273 │ │ ├── hdl │ │ │ └── blk_mem_gen_v8_3_vhsyn_rfs.vhd │ │ └── simulation │ │ │ └── blk_mem_gen_v8_3.v │ ├── 8479 │ │ └── hdl │ │ │ └── axi_clock_converter_v2_1_vl_rfs.v │ ├── 9097 │ │ └── src │ │ │ ├── axi_dynclk.vhd │ │ │ ├── axi_dynclk_S00_AXI.vhd │ │ │ └── mmcme2_drp.v │ ├── 04b4 │ │ └── hdl │ │ │ └── proc_sys_reset_v5_0_vh_rfs.vhd │ ├── 0b6b │ │ └── hdl │ │ │ └── axi_register_slice_v2_1_vl_rfs.v │ ├── 0ba0 │ │ └── hdl │ │ │ └── axi_lite_ipif_v3_0_vh_rfs.vhd │ ├── 2e37 │ │ └── xlconcat.vhd │ ├── 38e8 │ │ └── hdl │ │ │ └── lib_bmg_v1_0_rfs.vhd │ ├── 39ba │ │ └── hdl │ │ │ └── axi_data_fifo_v2_1_vl_rfs.v │ ├── 3c71 │ │ └── hdl │ │ │ └── v_vid_in_axi4s_v4_0_vl_rfs.v │ ├── 4f16 │ │ └── hdl │ │ │ └── axi_gpio_v2_0_vh_rfs.vhd │ ├── 52cb │ │ └── hdl │ │ │ └── lib_cdc_v1_0_rfs.vhd │ ├── 564d │ │ ├── hdl │ │ │ ├── fifo_generator_v13_1_rfs.v │ │ │ ├── fifo_generator_v13_1_rfs.vhd │ │ │ └── fifo_generator_v13_1_vhsyn_rfs.vhd │ │ └── simulation │ │ │ └── fifo_generator_vlog_beh.v │ ├── 5ab6 │ │ └── hdl │ │ │ └── lib_fifo_v1_0_rfs.vhd │ ├── 69dc │ │ └── src │ │ │ └── rgb2vga.vhd │ ├── 7dd0 │ │ └── hdl │ │ │ ├── processing_system7_bfm_v2_0_5_apis.v │ │ │ ├── processing_system7_bfm_v2_0_5_axi_acp.v │ │ │ ├── processing_system7_bfm_v2_0_5_axi_gp.v │ │ │ ├── processing_system7_bfm_v2_0_5_axi_hp.v │ │ │ ├── processing_system7_bfm_v2_0_5_local_params.v │ │ │ ├── processing_system7_bfm_v2_0_5_reg_init.v │ │ │ ├── processing_system7_bfm_v2_0_5_reg_params.v │ │ │ ├── processing_system7_bfm_v2_0_5_unused_ports.v │ │ │ └── processing_system7_bfm_v2_0_vl_rfs.v │ ├── 7e3a │ │ └── hdl │ │ │ ├── axi_infrastructure_v1_1_0.vh │ │ │ └── axi_infrastructure_v1_1_vl_rfs.v │ ├── 7ee0 │ │ └── hdl │ │ │ └── generic_baseblocks_v2_1_vl_rfs.v │ ├── 832a │ │ └── hdl │ │ │ └── lib_pkg_v1_0_rfs.vhd │ ├── 896d │ │ └── hdl │ │ │ └── axi_crossbar_v2_1_vl_rfs.v │ ├── 8c13 │ │ └── hdl │ │ │ └── verilog │ │ │ ├── processing_system7_v5_5_atc.v │ │ │ ├── processing_system7_v5_5_aw_atc.v │ │ │ ├── processing_system7_v5_5_b_atc.v │ │ │ ├── processing_system7_v5_5_trace_buffer.v │ │ │ └── processing_system7_v5_5_w_atc.v │ ├── a4c8 │ │ └── hdl │ │ │ ├── axi_dwidth_converter_v2_1_vl_rfs.v │ │ │ └── axi_dwidth_converter_v2_1_vlsyn_rfs.v │ ├── bf41 │ │ └── hdl │ │ │ └── axi_datamover_v5_1_vh_rfs.vhd │ ├── d2d3 │ │ └── src │ │ │ ├── ChannelBond.vhd │ │ │ ├── DVI_Constants.vhd │ │ │ ├── EEPROM_8b.vhd │ │ │ ├── GlitchFilter.vhd │ │ │ ├── InputSERDES.vhd │ │ │ ├── PhaseAlign.vhd │ │ │ ├── ResyncToBUFG.vhd │ │ │ ├── SyncAsync.vhd │ │ │ ├── SyncAsyncReset.vhd │ │ │ ├── SyncBase.vhd │ │ │ ├── TMDS_Clocking.vhd │ │ │ ├── TMDS_Decoder.vhd │ │ │ ├── TWI_SlaveCtl.vhd │ │ │ └── dvi2rgb.vhd │ ├── d9f8 │ │ └── hdl │ │ │ └── v_tc_v6_1_vh_rfs.vhd │ ├── df1b │ │ └── hdl │ │ │ └── axi_protocol_converter_v2_1_vl_rfs.v │ ├── e147 │ │ └── xlconstant.vhd │ ├── e956 │ │ └── hdl │ │ │ └── interrupt_control_v3_1_vh_rfs.vhd │ └── ed72 │ │ └── hdl │ │ ├── axi_vdma_v6_2_10.vh │ │ ├── axi_vdma_v6_2_rfs.v │ │ └── axi_vdma_v6_2_rfs.vhd │ └── ui │ └── bd_3e36a3ac.ui ├── constraints ├── .keep └── ZYBO_Master.xdc ├── hdl └── .keep ├── ip └── .keep └── others └── .keep /.gitignore: -------------------------------------------------------------------------------- 1 | # Blacklist everything 2 | /* 3 | 4 | # whitelist the necessary files and folders, this gets everything from inside them too 5 | !.gitignore 6 | !.gitmodules 7 | !README.md 8 | !hw_handoff/ 9 | !proj/ 10 | !repo/ 11 | !sdk/ 12 | !src/ 13 | 14 | #Digilent Added ignore rules for Vivado projects 15 | 16 | # sdk exclusions 17 | sdk/.metadata 18 | sdk/**/*RemoteSystemsTempFiles 19 | sdk/**/*Debug/* 20 | sdk/**/*Release 21 | sdk/**/*webtalk 22 | sdk/.sdk 23 | sdk/*.log 24 | # ignore everything in the hw_platform 25 | sdk/*hw_platform*/* 26 | # except 27 | !sdk/*hw_platform*/*.hdf 28 | !sdk/*hw_platform*/.*project 29 | # ignore everything in the BSP 30 | sdk/*_bsp*/* 31 | # except 32 | !sdk/*_bsp*/system.mss 33 | !sdk/*_bsp*/Makefile 34 | !sdk/*_bsp*/.*project 35 | # include the relevant elf files 36 | !sdk/**/*Debug/*.elf 37 | !sdk/**/*Debug/*.elf.size 38 | 39 | repo/** 40 | # whitelist vivado-library if it exists 41 | !repo/vivado-library 42 | #do not white-list submodule contents 43 | !repo/local 44 | !repo/local/** 45 | !repo/cache 46 | repo/cache/** 47 | 48 | # Make sure we keep only xci files in ip src subfolder 49 | src/ip/*/** 50 | !src/ip/*/*.xci 51 | !src/ip/*/*.prj 52 | # Do not ignore anything in src/others 53 | !src/others/* 54 | # Do not ignore block diagram files 55 | !src/bd/** 56 | 57 | 58 | # ignore everything in project folder 59 | proj/* 60 | # except this file and project generators 61 | !proj/create_project.tcl 62 | !proj/cleanup.cmd 63 | !proj/cleanup.sh 64 | !proj/release.py 65 | 66 | # keep the empty folders 67 | !**/.keep -------------------------------------------------------------------------------- /.gitmodules: -------------------------------------------------------------------------------- 1 | [submodule "repo/vivado-library"] 2 | path = repo/vivado-library 3 | url = http://github.com/digilent/vivado-library.git 4 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # Zybo hdmi-in 2 | Created for Vivado 2016.4 3 | 4 | [Link to the project wiki](https://reference.digilentinc.com/learn/programmable-logic/tutorials/zybo-hdmi-demo/start) 5 | 6 | -------------------------------------------------------------------------------- /hw_handoff/.keep: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Digilent/Zybo-hdmi-in/5f423ed8732a72c07d0ae40418ac6f44f4256f02/hw_handoff/.keep -------------------------------------------------------------------------------- /hw_handoff/hdmi_in_wrapper.hdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Digilent/Zybo-hdmi-in/5f423ed8732a72c07d0ae40418ac6f44f4256f02/hw_handoff/hdmi_in_wrapper.hdf -------------------------------------------------------------------------------- /proj/cleanup.cmd: -------------------------------------------------------------------------------- 1 | @echo off 2 | rem delete all files from subfolders 3 | for /d /r %%i in (*) do del /f /q %%i\* 4 | rem delete all subfolders 5 | for /d %%i in (*) do rd /S /Q %%i 6 | 7 | rem unmark read only from all files 8 | attrib -R .\* /S 9 | 10 | rem mark read only those we wish to keep 11 | attrib +R .\create_project.tcl 12 | attrib +R .\cleanup.sh 13 | attrib +R .\cleanup.cmd 14 | attrib +R .\release.py 15 | attrib +R .\.gitignore 16 | attrib +R .\_READ_ME_.txt 17 | 18 | rem delete all non read-only 19 | del /Q /A:-R .\* 20 | 21 | rem unmark read-only 22 | attrib -R .\* 23 | -------------------------------------------------------------------------------- /proj/cleanup.sh: -------------------------------------------------------------------------------- 1 | # This script is useful for cleaning up the 'project' 2 | # directory of a Digilent Vivado-project git repository 3 | ### 4 | # Run the following command to change permissions of 5 | # this 'cleanup' file if needed: 6 | # chmod u+x cleanup.sh 7 | ### 8 | # Remove directories/subdirectories 9 | find . -mindepth 1 -type d -exec rm -rf {} + 10 | # Remove any other files than: 11 | find . -type f ! -name 'cleanup.sh' \ 12 | ! -name 'cleanup.cmd' \ 13 | ! -name 'create_project.tcl' \ 14 | ! -name 'release.py' \ 15 | ! -name '.gitignore' \ 16 | -exec rm -rf {} + 17 | -------------------------------------------------------------------------------- /proj/release.py: -------------------------------------------------------------------------------- 1 | """ 2 | This script builds a release zip of the project it is run in. The release 3 | script mimics what a Github release zip would like. While not explicitly 4 | referencing the .gitignore, how this script builds this release is based 5 | of the Vivado projects .gitignore, which is universal across all Vivado 6 | projects. 7 | 8 | Author: Andrew Holzer 9 | Date: 02/09/2017 10 | 11 | Updated: 12 | 03/10/2017: added Debug file to zipped folders/files 13 | 05/12/2017(ArtVVB): added full /local inclusion in /repo 14 | """ 15 | 16 | import fnmatch 17 | import glob 18 | import os 19 | import zipfile 20 | from sys import argv 21 | 22 | 23 | def zip(filename, dirname, projname, abs_src, zf): 24 | absname = os.path.abspath(os.path.join(dirname, filename)) 25 | arcname = absname[len(abs_src) + 1:] 26 | zf.write(absname, os.path.join(projname, arcname)) 27 | 28 | def main(dest): 29 | zf = zipfile.ZipFile("%s-20xx.x-y.zip" % (dest), "w", zipfile.ZIP_DEFLATED) 30 | abs_src = os.getcwd() # absolute path for the source directory 31 | projname = dest 32 | 33 | if os.path.isdir("hw_handoff"): # zip everything here 34 | for dirname, subdirs, files in os.walk(os.path.join(abs_src, "hw_handoff")): 35 | for filename in files: 36 | zip(filename, dirname, projname, abs_src, zf) 37 | 38 | if os.path.isdir("proj"): # Only zip the create_project and cleanup scripts 39 | files = ["create_project.tcl", "cleanup.sh", "cleanup.cmd"] 40 | for filename in files: 41 | if os.path.isfile(os.path.join("proj", filename)): 42 | zip(filename, "proj", projname, abs_src, zf) 43 | 44 | if os.path.isdir("repo"): # cache should be empty (only the .keep), but zip any .xci, .patch and .tcl file 45 | for dirname, subdirs, files in os.walk(os.path.join(abs_src, "repo")): 46 | curdir = os.path.basename(dirname) 47 | if (curdir == "cache"): 48 | zip(".keep", dirname, projname, abs_src, zf) 49 | subdirs[:] = [] # just skip everything else in cache 50 | else: 51 | for filename in files: 52 | zip(filename, dirname, projname, abs_src, zf) # keep contents of all other subdirectories (local, vivado-library usually) 53 | 54 | if os.path.isdir("sdk"): # system.mss, Makefile, .*project and .hdf files are to be zipped, and specific folders ignored 55 | for dirname, subdirs, files in os.walk(os.path.join(abs_src, "sdk")): 56 | curdir = os.path.basename(dirname) 57 | if (fnmatch.fnmatch(dirname, "*hw_platform*") or fnmatch.fnmatch(dirname, "*_bsp*")): 58 | for filename in files: 59 | if (fnmatch.fnmatch(filename, "*.hdf") or fnmatch.fnmatch(filename, ".*project") \ 60 | or fnmatch.fnmatch(filename, "system.mss") or fnmatch.fnmatch(filename, "Makefile")): 61 | zip(filename, dirname, projname, abs_src, zf) 62 | elif (fnmatch.fnmatch(curdir, ".metadata") or fnmatch.fnmatch(curdir, "*RemoteSystemsTempFiles")\ 63 | or fnmatch.fnmatch(curdir, "*Release") or fnmatch.fnmatch(curdir, "*webtalk")\ 64 | or fnmatch.fnmatch(curdir, ".sdk")): # if within one of these directories we should just skip out 65 | subdirs[:] = [] 66 | files[:] = [] 67 | else: 68 | if fnmatch.fnmatch(curdir, "*Debug"): 69 | for filename in files: 70 | if fnmatch.fnmatch(filename, "*.elf*"): 71 | zip(filename, dirname, projname, abs_src, zf) 72 | else: 73 | for filename in files: 74 | if filename != "SDK.log": 75 | zip(filename, dirname, projname, abs_src, zf) 76 | 77 | if os.path.isdir("src"): # anything in others and bd, .xci and .prj files are top be zipped 78 | for dirname, subdirs, files in os.walk(os.path.join(abs_src, "src")): 79 | curdir = os.path.basename(dirname) 80 | if (curdir == "bd"): 81 | for bddir, bdsubdir, bdfiles in os.walk(dirname): 82 | for filename in bdfiles: 83 | zip(filename, bddir, projname, abs_src, zf) 84 | subdirs[:] = [] 85 | files[:] = [] 86 | if (curdir == "ip"): # this cannot be the ip dir underneath bd 87 | for ipdir, ipsubdir, ipfiles in os.walk(dirname): 88 | if not ipdir == "generated_ip": 89 | for filename in ipfiles: 90 | if (fnmatch.fnmatch(filename, "*.xci") or fnmatch.fnmatch(filename, "*.prj") or fnmatch.fnmatch(filename, ".keep")): 91 | zip(filename, ipdir, projname, abs_src, zf) 92 | subdirs[:] = [] 93 | files[:] = [] 94 | for filename in files: 95 | zip(filename, dirname, projname, abs_src, zf) 96 | 97 | if os.path.isfile(".gitignore"): 98 | zip(".gitignore", "", projname, abs_src, zf) 99 | 100 | if os.path.isfile(".gitmodules"): 101 | zip(".gitmodules", "", projname, abs_src, zf) 102 | 103 | if os.path.isfile("README.md"): 104 | zip("README.md", "", projname, abs_src, zf) 105 | 106 | zf.close() 107 | 108 | 109 | os.chdir('..') 110 | 111 | if len(argv) == 2: 112 | zipname = argv[1] 113 | else: 114 | zipname = os.path.basename(os.getcwd()) 115 | 116 | main(zipname) 117 | -------------------------------------------------------------------------------- /repo/cache/.keep: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Digilent/Zybo-hdmi-in/5f423ed8732a72c07d0ae40418ac6f44f4256f02/repo/cache/.keep -------------------------------------------------------------------------------- /repo/local/.keep: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Digilent/Zybo-hdmi-in/5f423ed8732a72c07d0ae40418ac6f44f4256f02/repo/local/.keep -------------------------------------------------------------------------------- /sdk/.keep: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Digilent/Zybo-hdmi-in/5f423ed8732a72c07d0ae40418ac6f44f4256f02/sdk/.keep -------------------------------------------------------------------------------- /sdk/HDMI_IN/.project: -------------------------------------------------------------------------------- 1 | 2 | 3 | HDMI_IN 4 | Created by SDK v2015.4. HDMI_IN_bsp - ps7_cortexa9_0 5 | 6 | HDMI_IN_bsp 7 | 8 | 9 | 10 | org.eclipse.cdt.managedbuilder.core.genmakebuilder 11 | 12 | 13 | 14 | 15 | org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder 16 | full,incremental, 17 | 18 | 19 | 20 | 21 | 22 | org.eclipse.cdt.core.cnature 23 | org.eclipse.cdt.managedbuilder.core.managedBuildNature 24 | org.eclipse.cdt.managedbuilder.core.ScannerConfigNature 25 | 26 | 27 | -------------------------------------------------------------------------------- /sdk/HDMI_IN/Debug/HDMI_IN.elf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Digilent/Zybo-hdmi-in/5f423ed8732a72c07d0ae40418ac6f44f4256f02/sdk/HDMI_IN/Debug/HDMI_IN.elf -------------------------------------------------------------------------------- /sdk/HDMI_IN/Debug/HDMI_IN.elf.size: -------------------------------------------------------------------------------- 1 | text data bss dec hex filename 2 | 105496 3304 18688240 18797040 11ed1f0 HDMI_IN.elf 3 | -------------------------------------------------------------------------------- /sdk/HDMI_IN/src/README.txt: -------------------------------------------------------------------------------- 1 | Empty application. Add your own sources. 2 | -------------------------------------------------------------------------------- /sdk/HDMI_IN/src/display_ctrl/display_ctrl.h: -------------------------------------------------------------------------------- 1 | /************************************************************************/ 2 | /* */ 3 | /* display_ctrl.h -- Digilent Display Controller Driver */ 4 | /* */ 5 | /************************************************************************/ 6 | /* Author: Sam Bobrowicz */ 7 | /* Copyright 2014, Digilent Inc. */ 8 | /************************************************************************/ 9 | /* Module Description: */ 10 | /* */ 11 | /* This module provides an easy to use API for controlling a */ 12 | /* Display attached to a Digilent system board via VGA or HDMI. */ 13 | /* run-time resolution setting and seamless framebuffer-swapping */ 14 | /* for tear-free animation. */ 15 | /* */ 16 | /* To use this driver, you must have a Xilinx Video Timing */ 17 | /* Controller core (vtc), Xilinx axi_vdma core, a Digilent */ 18 | /* axi_dynclk core, a Xilinx AXI Stream to Video core, and either */ 19 | /* a Digilent RGB2VGA or RGB2DVI core all present in your design. */ 20 | /* See the Video in or Display out reference projects for your */ 21 | /* system board to see how they need to be connected. Digilent */ 22 | /* reference projects and IP cores can be found at */ 23 | /* www.github.com/Digilent. */ 24 | /* */ 25 | /* The following steps should be followed to use this driver: */ 26 | /* 1) Create a DisplayCtrl object and pass a pointer to it to */ 27 | /* DisplayInitialize. */ 28 | /* 2) Call DisplaySetMode to set the desired mode */ 29 | /* 3) Call DisplayStart to begin outputting data to the display */ 30 | /* 4) To create a seamless animation, draw the next image to a */ 31 | /* framebuffer currently not being displayed. Then call */ 32 | /* DisplayChangeFrame to begin displaying that frame. */ 33 | /* Repeat as needed, only ever modifying inactive frames. */ 34 | /* 5) To change the resolution, call DisplaySetMode, followed by */ 35 | /* DisplayStart again. */ 36 | /* */ 37 | /* */ 38 | /************************************************************************/ 39 | /* Revision History: */ 40 | /* */ 41 | /* 2/20/2014(SamB): Created */ 42 | /* 11/25/2015(SamB): Changed from axi_dispctrl to Xilinx cores */ 43 | /* Separated Clock functions into dynclk library */ 44 | /* */ 45 | /************************************************************************/ 46 | 47 | #ifndef DISPLAY_CTRL_H_ 48 | #define DISPLAY_CTRL_H_ 49 | 50 | /* ------------------------------------------------------------ */ 51 | /* Include File Definitions */ 52 | /* ------------------------------------------------------------ */ 53 | 54 | #include "xil_types.h" 55 | #include "vga_modes.h" 56 | #include "xaxivdma.h" 57 | #include "xvtc.h" 58 | #include "../dynclk/dynclk.h" 59 | 60 | /* ------------------------------------------------------------ */ 61 | /* Miscellaneous Declarations */ 62 | /* ------------------------------------------------------------ */ 63 | 64 | #define BIT_DISPLAY_RED 16 65 | #define BIT_DISPLAY_BLUE 8 66 | #define BIT_DISPLAY_GREEN 0 67 | 68 | /* 69 | * This driver currently supports 3 frames. 70 | */ 71 | #define DISPLAY_NUM_FRAMES 3 72 | 73 | /* ------------------------------------------------------------ */ 74 | /* General Type Declarations */ 75 | /* ------------------------------------------------------------ */ 76 | 77 | typedef enum { 78 | DISPLAY_STOPPED = 0, 79 | DISPLAY_RUNNING = 1 80 | } DisplayState; 81 | 82 | typedef struct { 83 | u32 dynClkAddr; /*Physical Base address of the dynclk core*/ 84 | XAxiVdma *vdma; /*VDMA driver struct*/ 85 | XAxiVdma_DmaSetup vdmaConfig; /*VDMA channel configuration*/ 86 | XVtc vtc; /*VTC driver struct*/ 87 | VideoMode vMode; /*Current Video mode*/ 88 | u8 *framePtr[DISPLAY_NUM_FRAMES]; /* Array of pointers to the framebuffers */ 89 | u32 stride; /* The line stride of the framebuffers, in bytes */ 90 | double pxlFreq; /* Frequency of clock currently being generated */ 91 | u32 curFrame; /* Current frame being displayed */ 92 | DisplayState state; /* Indicates if the Display is currently running */ 93 | } DisplayCtrl; 94 | 95 | /* ------------------------------------------------------------ */ 96 | /* Procedure Declarations */ 97 | /* ------------------------------------------------------------ */ 98 | 99 | int DisplayStop(DisplayCtrl *dispPtr); 100 | int DisplayStart(DisplayCtrl *dispPtr); 101 | int DisplayInitialize(DisplayCtrl *dispPtr, XAxiVdma *vdma, u16 vtcId, u32 dynClkAddr, u8 *framePtr[DISPLAY_NUM_FRAMES], u32 stride); 102 | int DisplaySetMode(DisplayCtrl *dispPtr, const VideoMode *newMode); 103 | int DisplayChangeFrame(DisplayCtrl *dispPtr, u32 frameIndex); 104 | 105 | /* ------------------------------------------------------------ */ 106 | 107 | /************************************************************************/ 108 | 109 | #endif /* DISPLAY_CTRL_H_ */ 110 | 111 | -------------------------------------------------------------------------------- /sdk/HDMI_IN/src/display_ctrl/vga_modes.h: -------------------------------------------------------------------------------- 1 | /************************************************************************/ 2 | /* */ 3 | /* vga_modes.h -- VideoMode definitions */ 4 | /* */ 5 | /************************************************************************/ 6 | /* Author: Sam Bobrowicz */ 7 | /* Copyright 2014, Digilent Inc. */ 8 | /************************************************************************/ 9 | /* Module Description: */ 10 | /* */ 11 | /* This file contains the definition of the VideoMode type, and */ 12 | /* also defines several common video modes */ 13 | /* */ 14 | /************************************************************************/ 15 | /* Revision History: */ 16 | /* */ 17 | /* 2/17/2014(SamB): Created */ 18 | /* */ 19 | /************************************************************************/ 20 | 21 | #ifndef VGA_MODES_H_ 22 | #define VGA_MODES_H_ 23 | 24 | typedef struct { 25 | char label[64]; /* Label describing the resolution */ 26 | u32 width; /*Width of the active video frame*/ 27 | u32 height; /*Height of the active video frame*/ 28 | u32 hps; /*Start time of Horizontal sync pulse, in pixel clocks (active width + H. front porch)*/ 29 | u32 hpe; /*End time of Horizontal sync pulse, in pixel clocks (active width + H. front porch + H. sync width)*/ 30 | u32 hmax; /*Total number of pixel clocks per line (active width + H. front porch + H. sync width + H. back porch) */ 31 | u32 hpol; /*hsync pulse polarity*/ 32 | u32 vps; /*Start time of Vertical sync pulse, in lines (active height + V. front porch)*/ 33 | u32 vpe; /*End time of Vertical sync pulse, in lines (active height + V. front porch + V. sync width)*/ 34 | u32 vmax; /*Total number of lines per frame (active height + V. front porch + V. sync width + V. back porch) */ 35 | u32 vpol; /*vsync pulse polarity*/ 36 | double freq; /*Pixel Clock frequency*/ 37 | } VideoMode; 38 | 39 | static const VideoMode VMODE_640x480 = { 40 | .label = "640x480@60Hz", 41 | .width = 640, 42 | .height = 480, 43 | .hps = 656, 44 | .hpe = 752, 45 | .hmax = 799, 46 | .hpol = 0, 47 | .vps = 490, 48 | .vpe = 492, 49 | .vmax = 524, 50 | .vpol = 0, 51 | .freq = 25.0 52 | }; 53 | 54 | 55 | static const VideoMode VMODE_800x600 = { 56 | .label = "800x600@60Hz", 57 | .width = 800, 58 | .height = 600, 59 | .hps = 840, 60 | .hpe = 968, 61 | .hmax = 1055, 62 | .hpol = 1, 63 | .vps = 601, 64 | .vpe = 605, 65 | .vmax = 627, 66 | .vpol = 1, 67 | .freq = 40.0 68 | }; 69 | 70 | static const VideoMode VMODE_1280x1024 = { 71 | .label = "1280x1024@60Hz", 72 | .width = 1280, 73 | .height = 1024, 74 | .hps = 1328, 75 | .hpe = 1440, 76 | .hmax = 1687, 77 | .hpol = 1, 78 | .vps = 1025, 79 | .vpe = 1028, 80 | .vmax = 1065, 81 | .vpol = 1, 82 | .freq = 108.0 83 | }; 84 | 85 | static const VideoMode VMODE_1280x720 = { 86 | .label = "1280x720@60Hz", 87 | .width = 1280, 88 | .height = 720, 89 | .hps = 1390, 90 | .hpe = 1430, 91 | .hmax = 1649, 92 | .hpol = 1, 93 | .vps = 725, 94 | .vpe = 730, 95 | .vmax = 749, 96 | .vpol = 1, 97 | .freq = 74.25, //74.2424 is close enough 98 | }; 99 | 100 | static const VideoMode VMODE_1920x1080 = { 101 | .label = "1920x1080@60Hz", 102 | .width = 1920, 103 | .height = 1080, 104 | .hps = 2008, 105 | .hpe = 2052, 106 | .hmax = 2199, 107 | .hpol = 1, 108 | .vps = 1084, 109 | .vpe = 1089, 110 | .vmax = 1124, 111 | .vpol = 1, 112 | .freq = 148.5 //148.57 is close enough 113 | }; 114 | 115 | 116 | #endif /* VGA_MODES_H_ */ 117 | -------------------------------------------------------------------------------- /sdk/HDMI_IN/src/intc/intc.c: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * @file intc.c 3 | * Interrupt system initialization. 4 | * 5 | * @author Elod Gyorgy 6 | * 7 | * @date 2015-Jan-3 8 | * 9 | * @copyright 10 | * (c) 2015 Copyright Digilent Incorporated 11 | * All Rights Reserved 12 | * 13 | * This program is free software; distributed under the terms of BSD 3-clause 14 | * license ("Revised BSD License", "New BSD License", or "Modified BSD License") 15 | * 16 | * Redistribution and use in source and binary forms, with or without modification, 17 | * are permitted provided that the following conditions are met: 18 | * 19 | * 1. Redistributions of source code must retain the above copyright notice, this 20 | * list of conditions and the following disclaimer. 21 | * 2. Redistributions in binary form must reproduce the above copyright notice, 22 | * this list of conditions and the following disclaimer in the documentation 23 | * and/or other materials provided with the distribution. 24 | * 3. Neither the name(s) of the above-listed copyright holder(s) nor the names 25 | * of its contributors may be used to endorse or promote products derived 26 | * from this software without specific prior written permission. 27 | * 28 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 29 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 30 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 31 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE 32 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 33 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 34 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 35 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 36 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 37 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 38 | 39 | * @desciption 40 | * Contains interrupt controller initialization function. 41 | * 42 | * 
 43 |  * MODIFICATION HISTORY:
 44 |  *
 45 |  * Ver   Who          Date     Changes
 46 |  * ----- ------------ ----------- -----------------------------------------------
 47 |  * 1.00  Elod Gyorgy   2015-Jan-3  First release
 48 |  * 1.01  Sam Bobrowicz 2015-Nov-20 Added Zynq Support
 49 |  *
 50 |  *
51 | * 52 | *****************************************************************************/ 53 | 54 | #include "intc.h" 55 | #include "xparameters.h" 56 | 57 | XStatus fnInitInterruptController(INTC *psIntc) 58 | { 59 | #ifdef XPAR_INTC_0_DEVICE_ID 60 | 61 | // Init driver instance 62 | RETURN_ON_FAILURE(XIntc_Initialize(psIntc, INTC_DEVICE_ID)); 63 | 64 | // Start interrupt controller 65 | RETURN_ON_FAILURE(XIntc_Start(psIntc, XIN_REAL_MODE)); 66 | 67 | #else 68 | XScuGic_Config *IntcConfig; 69 | 70 | /* 71 | * Initialize the interrupt controller driver so that it is ready to 72 | * use. 73 | */ 74 | IntcConfig = XScuGic_LookupConfig(INTC_DEVICE_ID); 75 | if (NULL == IntcConfig) { 76 | return XST_FAILURE; 77 | } 78 | 79 | RETURN_ON_FAILURE(XScuGic_CfgInitialize(psIntc, IntcConfig, 80 | IntcConfig->CpuBaseAddress)); 81 | #endif 82 | 83 | return XST_SUCCESS; 84 | } 85 | 86 | /* 87 | * This function enables interrupts and connects interrupt service routines declared in 88 | * an interrupt vector table 89 | */ 90 | void fnEnableInterrupts(INTC *psIntc, const ivt_t *prgsIvt, unsigned int csIVectors) 91 | { 92 | unsigned int isIVector; 93 | 94 | Xil_AssertVoid(psIntc != NULL); 95 | Xil_AssertVoid(psIntc->IsReady == XIL_COMPONENT_IS_READY); 96 | 97 | /* Hook up interrupt service routines from IVT */ 98 | for (isIVector = 0; isIVector < csIVectors; isIVector++) 99 | { 100 | #ifdef XPAR_INTC_0_DEVICE_ID 101 | XIntc_Connect(psIntc, prgsIvt[isIVector].id, prgsIvt[isIVector].handler, prgsIvt[isIVector].pvCallbackRef); 102 | 103 | /* Enable the interrupt vector at the interrupt controller */ 104 | XIntc_Enable(psIntc, prgsIvt[isIVector].id); 105 | #else 106 | XScuGic_SetPriorityTriggerType(psIntc, prgsIvt[isIVector].id, 107 | prgsIvt[isIVector].priority, prgsIvt[isIVector].trigType); 108 | 109 | XScuGic_Connect(psIntc, prgsIvt[isIVector].id, 110 | (Xil_ExceptionHandler)prgsIvt[isIVector].handler, prgsIvt[isIVector].pvCallbackRef); 111 | 112 | XScuGic_Enable(psIntc, prgsIvt[isIVector].id); 113 | #endif 114 | } 115 | 116 | Xil_ExceptionInit(); 117 | // Register the interrupt controller handler with the exception table. 118 | // This is in fact the ISR dispatch routine, which calls our ISRs 119 | Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT, 120 | (Xil_ExceptionHandler)INTC_HANDLER, 121 | psIntc); 122 | Xil_ExceptionEnable(); 123 | 124 | } 125 | 126 | -------------------------------------------------------------------------------- /sdk/HDMI_IN/src/intc/intc.h: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * @file intc.h 3 | * Interrupt system initialization. 4 | * 5 | * @author Elod Gyorgy 6 | * 7 | * @date 2015-Jan-3 8 | * 9 | * @copyright 10 | * (c) 2015 Copyright Digilent Incorporated 11 | * All Rights Reserved 12 | * 13 | * This program is free software; distributed under the terms of BSD 3-clause 14 | * license ("Revised BSD License", "New BSD License", or "Modified BSD License") 15 | * 16 | * Redistribution and use in source and binary forms, with or without modification, 17 | * are permitted provided that the following conditions are met: 18 | * 19 | * 1. Redistributions of source code must retain the above copyright notice, this 20 | * list of conditions and the following disclaimer. 21 | * 2. Redistributions in binary form must reproduce the above copyright notice, 22 | * this list of conditions and the following disclaimer in the documentation 23 | * and/or other materials provided with the distribution. 24 | * 3. Neither the name(s) of the above-listed copyright holder(s) nor the names 25 | * of its contributors may be used to endorse or promote products derived 26 | * from this software without specific prior written permission. 27 | * 28 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 29 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 30 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 31 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE 32 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 33 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 34 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 35 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 36 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 37 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 38 | 39 | * @desciption 40 | * Contains interrupt controller initialization function. 41 | * 42 | * 
43 |  * MODIFICATION HISTORY:
44 |  *
45 |  * Ver   Who           Date        Changes
46 |  * ----- ------------  ----------- -----------------------------------------------
47 |  * 1.00  Elod Gyorgy   2015-Jan-3  First release
48 |  * 1.01  Sam Bobrowicz 2015-Nov-20 Added Zynq Support
49 |  *
50 |  *
51 | * 52 | *****************************************************************************/ 53 | 54 | #ifndef INTC_H_ 55 | #define INTC_H_ 56 | 57 | #include "xstatus.h" 58 | 59 | /* 60 | * TODO: check if there is a better preprocessor check to determine 61 | * if this is a microblaze or zynq system. 62 | */ 63 | #ifdef XPAR_INTC_0_DEVICE_ID 64 | #include "xintc.h" 65 | #else 66 | #include "xscugic.h" 67 | #endif 68 | 69 | #ifdef XPAR_INTC_0_DEVICE_ID 70 | #define INTC_DEVICE_ID XPAR_INTC_0_DEVICE_ID 71 | #define INTC XIntc 72 | #define INTC_HANDLER XIntc_InterruptHandler 73 | #else 74 | #define INTC_DEVICE_ID XPAR_SCUGIC_SINGLE_DEVICE_ID 75 | #define INTC XScuGic 76 | #define INTC_HANDLER XScuGic_InterruptHandler 77 | #endif 78 | 79 | #define RETURN_ON_FAILURE(x) if ((x) != XST_SUCCESS) return XST_FAILURE; 80 | 81 | /* 82 | * Structure for interrupt id, handler and callback reference 83 | */ 84 | typedef struct { 85 | u8 id; 86 | XInterruptHandler handler; 87 | void *pvCallbackRef; 88 | u8 priority; //not used for microblaze, set to 0 89 | u8 trigType; //not used for microblaze, set to 0 90 | } ivt_t; 91 | 92 | XStatus fnInitInterruptController(INTC *psIntc); 93 | void fnEnableInterrupts(INTC *psIntc, const ivt_t *prgsIvt, unsigned int csIVectors); 94 | 95 | #endif /* INTC_H_ */ 96 | -------------------------------------------------------------------------------- /sdk/HDMI_IN/src/timer_ps/timer_ps.c: -------------------------------------------------------------------------------- 1 | /************************************************************************/ 2 | /* */ 3 | /* timer_ps.c -- Timer Delay for Zynq systems */ 4 | /* */ 5 | /************************************************************************/ 6 | /* Author: Sam Bobrowicz */ 7 | /* Copyright 2014, Digilent Inc. */ 8 | /************************************************************************/ 9 | /* Module Description: */ 10 | /* */ 11 | /* Implements an accurate delay function using the scu timer. */ 12 | /* Code from this module will cause conflicts with other code that */ 13 | /* requires the Zynq's scu timer. */ 14 | /* */ 15 | /* This module contains code from the Xilinx Demo titled */ 16 | /* "xscutimer_polled_example.c" */ 17 | /* */ 18 | /************************************************************************/ 19 | /* Revision History: */ 20 | /* */ 21 | /* 2/14/2014(SamB): Created */ 22 | /* */ 23 | /************************************************************************/ 24 | 25 | 26 | /* ------------------------------------------------------------ */ 27 | /* Include File Definitions */ 28 | /* ------------------------------------------------------------ */ 29 | #include "timer_ps.h" 30 | #include "xscutimer.h" 31 | #include "xil_types.h" 32 | 33 | /* ------------------------------------------------------------ */ 34 | /* Global Variables */ 35 | /* ------------------------------------------------------------ */ 36 | 37 | XScuTimer TimerInstance; /* Cortex A9 Scu Private Timer Instance */ 38 | 39 | /* ------------------------------------------------------------ */ 40 | /* Procedure Definitions */ 41 | /* ------------------------------------------------------------ */ 42 | 43 | /*** TimerInitialize(u16 TimerDeviceId) 44 | ** 45 | ** Parameters: 46 | ** TimerDeviceId - The DEVICE ID of the Zynq SCU TIMER 47 | ** 48 | ** Return Value: int 49 | ** XST_SUCCESS if successful 50 | ** 51 | ** Errors: 52 | ** 53 | ** Description: Configures the global timer struct to access the 54 | ** the SCU timer. Can be called multiple times without 55 | ** error. 56 | ** 57 | */ 58 | int TimerInitialize(u16 TimerDeviceId) 59 | { 60 | int Status; 61 | XScuTimer *TimerInstancePtr = &TimerInstance; 62 | XScuTimer_Config *ConfigTmrPtr; 63 | 64 | /* 65 | * Initialize the Scu Private Timer driver. 66 | */ 67 | ConfigTmrPtr = XScuTimer_LookupConfig(TimerDeviceId); 68 | 69 | /* 70 | * This is where the virtual address would be used, this example 71 | * uses physical address. Note that it is not considered an error 72 | * if the timer has already been initialized. 73 | */ 74 | Status = XScuTimer_CfgInitialize(TimerInstancePtr, ConfigTmrPtr, 75 | ConfigTmrPtr->BaseAddr); 76 | if (Status != XST_SUCCESS || Status != XST_DEVICE_IS_STARTED) { 77 | return XST_FAILURE; 78 | } 79 | 80 | /* 81 | * Set prescaler to 1 82 | */ 83 | XScuTimer_SetPrescaler(TimerInstancePtr, 0); 84 | 85 | return Status; 86 | } 87 | /* ------------------------------------------------------------ */ 88 | 89 | /*** TimerDelay(u32 uSDelay) 90 | ** 91 | ** Parameters: 92 | ** uSDelay - Desired delay in micro seconds 93 | ** 94 | ** Return Value: 95 | ** 96 | ** Errors: 97 | ** 98 | ** Description: Blocks execution for the desired amount of time. 99 | ** TimerInitialize must have been called at least once 100 | ** before calling this function. 101 | */ 102 | /* ------------------------------------------------------------ */ 103 | void TimerDelay(u32 uSDelay) 104 | { 105 | u32 timerCnt; 106 | 107 | timerCnt = (TIMER_FREQ_HZ / 1000000) * uSDelay; 108 | 109 | XScuTimer_Stop(&TimerInstance); 110 | XScuTimer_DisableAutoReload(&TimerInstance); 111 | XScuTimer_LoadTimer(&TimerInstance, timerCnt); 112 | XScuTimer_Start(&TimerInstance); 113 | while (XScuTimer_GetCounterValue(&TimerInstance)) 114 | {} 115 | 116 | return; 117 | } 118 | 119 | /************************************************************************/ 120 | -------------------------------------------------------------------------------- /sdk/HDMI_IN/src/timer_ps/timer_ps.h: -------------------------------------------------------------------------------- 1 | /************************************************************************/ 2 | /* */ 3 | /* timer_ps.h -- Timer Delay for Zynq systems */ 4 | /* */ 5 | /************************************************************************/ 6 | /* Author: Sam Bobrowicz */ 7 | /* Copyright 2014, Digilent Inc. */ 8 | /************************************************************************/ 9 | /* Module Description: */ 10 | /* */ 11 | /* Implements an accurate delay function using the scu timer. */ 12 | /* Code from this module will cause conflicts with other code that */ 13 | /* requires the Zynq's scu timer. */ 14 | /* */ 15 | /* This module contains code from the Xilinx Demo titled */ 16 | /* "xscutimer_polled_example.c" */ 17 | /* */ 18 | /************************************************************************/ 19 | /* Revision History: */ 20 | /* */ 21 | /* 2/14/2014(SamB): Created */ 22 | /* */ 23 | /************************************************************************/ 24 | #ifndef TIMER_PS_H_ 25 | #define TIMER_PS_H_ 26 | 27 | #include "xil_types.h" 28 | #include "xparameters.h" 29 | 30 | /* ------------------------------------------------------------ */ 31 | /* Miscellaneous Declarations */ 32 | /* ------------------------------------------------------------ */ 33 | 34 | #define TIMER_FREQ_HZ (XPAR_CPU_CORTEXA9_0_CPU_CLK_FREQ_HZ / 2) 35 | 36 | /* ------------------------------------------------------------ */ 37 | /* Procedure Declarations */ 38 | /* ------------------------------------------------------------ */ 39 | 40 | int TimerInitialize(u16 TimerDeviceId); 41 | void TimerDelay(u32 uSDelay); 42 | 43 | /* ------------------------------------------------------------ */ 44 | 45 | /************************************************************************/ 46 | 47 | 48 | #endif /* TIMER_H_ */ 49 | -------------------------------------------------------------------------------- /sdk/HDMI_IN/src/video_demo.h: -------------------------------------------------------------------------------- 1 | /************************************************************************/ 2 | /* */ 3 | /* video_demo.h -- ZYBO Video demonstration */ 4 | /* */ 5 | /************************************************************************/ 6 | /* Author: Sam Bobrowicz */ 7 | /* Copyright 2015, Digilent Inc. */ 8 | /************************************************************************/ 9 | /* Module Description: */ 10 | /* */ 11 | /* This file contains code for running a demonstration of the */ 12 | /* Video input and output capabilities on the ZYBO. It is a good */ 13 | /* example of how to properly use the display_ctrl and */ 14 | /* video_capture drivers. */ 15 | /* */ 16 | /* */ 17 | /************************************************************************/ 18 | /* Revision History: */ 19 | /* */ 20 | /* 11/25/2015(SamB): Created */ 21 | /* */ 22 | /************************************************************************/ 23 | 24 | #ifndef VIDEO_DEMO_H_ 25 | #define VIDEO_DEMO_H_ 26 | 27 | /* ------------------------------------------------------------ */ 28 | /* Include File Definitions */ 29 | /* ------------------------------------------------------------ */ 30 | 31 | #include "xil_types.h" 32 | 33 | /* ------------------------------------------------------------ */ 34 | /* Miscellaneous Declarations */ 35 | /* ------------------------------------------------------------ */ 36 | 37 | #define DEMO_PATTERN_0 0 38 | #define DEMO_PATTERN_1 1 39 | 40 | #define DEMO_MAX_FRAME (1920*1080*3) 41 | #define DEMO_STRIDE (1920 * 3) 42 | 43 | /* 44 | * Configure the Video capture driver to start streaming on signal 45 | * detection 46 | */ 47 | #define DEMO_START_ON_DET 1 48 | 49 | /* ------------------------------------------------------------ */ 50 | /* Procedure Declarations */ 51 | /* ------------------------------------------------------------ */ 52 | 53 | void DemoInitialize(); 54 | void DemoRun(); 55 | void DemoPrintMenu(); 56 | void DemoChangeRes(); 57 | void DemoCRMenu(); 58 | void DemoInvertFrame(u8 *srcFrame, u8 *destFrame, u32 width, u32 height, u32 stride); 59 | void DemoPrintTest(u8 *frame, u32 width, u32 height, u32 stride, int pattern); 60 | void DemoScaleFrame(u8 *srcFrame, u8 *destFrame, u32 srcWidth, u32 srcHeight, u32 destWidth, u32 destHeight, u32 stride); 61 | void DemoISR(void *callBackRef, void *pVideo); 62 | 63 | /* ------------------------------------------------------------ */ 64 | 65 | /************************************************************************/ 66 | 67 | #endif /* VIDEO_DEMO_H_ */ 68 | -------------------------------------------------------------------------------- /sdk/HDMI_IN_bsp/.cproject: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | -------------------------------------------------------------------------------- /sdk/HDMI_IN_bsp/.project: -------------------------------------------------------------------------------- 1 | 2 | 3 | HDMI_IN_bsp 4 | Created by SDK v2015.4 5 | 6 | 7 | 8 | 9 | org.eclipse.cdt.make.core.makeBuilder 10 | 11 | 12 | org.eclipse.cdt.core.errorOutputParser 13 | org.eclipse.cdt.core.GASErrorParser;org.eclipse.cdt.core.GLDErrorParser;org.eclipse.cdt.core.GCCErrorParser;org.eclipse.cdt.core.GmakeErrorParser;org.eclipse.cdt.core.VCErrorParser;org.eclipse.cdt.core.CWDLocator;org.eclipse.cdt.core.MakeErrorParser; 14 | 15 | 16 | org.eclipse.cdt.make.core.append_environment 17 | true 18 | 19 | 20 | org.eclipse.cdt.make.core.build.arguments 21 | 22 | 23 | 24 | org.eclipse.cdt.make.core.build.command 25 | make 26 | 27 | 28 | org.eclipse.cdt.make.core.build.target.auto 29 | all 30 | 31 | 32 | org.eclipse.cdt.make.core.build.target.clean 33 | clean 34 | 35 | 36 | org.eclipse.cdt.make.core.build.target.inc 37 | all 38 | 39 | 40 | org.eclipse.cdt.make.core.enableAutoBuild 41 | true 42 | 43 | 44 | org.eclipse.cdt.make.core.enableCleanBuild 45 | true 46 | 47 | 48 | org.eclipse.cdt.make.core.enableFullBuild 49 | true 50 | 51 | 52 | org.eclipse.cdt.make.core.enabledIncrementalBuild 53 | true 54 | 55 | 56 | org.eclipse.cdt.make.core.environment 57 | 58 | 59 | 60 | org.eclipse.cdt.make.core.stopOnError 61 | false 62 | 63 | 64 | org.eclipse.cdt.make.core.useDefaultBuildCmd 65 | true 66 | 67 | 68 | 69 | 70 | 71 | com.xilinx.sdk.sw.SwProjectNature 72 | org.eclipse.cdt.core.cnature 73 | org.eclipse.cdt.make.core.makeNature 74 | 75 | 76 | -------------------------------------------------------------------------------- /sdk/HDMI_IN_bsp/.sdkproject: -------------------------------------------------------------------------------- 1 | THIRPARTY=false 2 | HW_PROJECT_REFERENCE=hdmi_in_wrapper_hw_platform_0 3 | PROCESSOR=ps7_cortexa9_0 4 | MSS_FILE=system.mss 5 | -------------------------------------------------------------------------------- /sdk/HDMI_IN_bsp/Makefile: -------------------------------------------------------------------------------- 1 | # Makefile generated by Xilinx. 2 | 3 | PROCESSOR = ps7_cortexa9_0 4 | LIBRARIES = ${PROCESSOR}/lib/libxil.a 5 | BSP_MAKEFILES := $(wildcard $(PROCESSOR)/libsrc/*/src/Makefile) 6 | SUBDIRS := $(patsubst %/Makefile, %, $(BSP_MAKEFILES)) 7 | 8 | ifneq (,$(findstring win,$(RDI_PLATFORM))) 9 | SHELL = CMD 10 | endif 11 | 12 | all: libs 13 | @echo 'Finished building libraries' 14 | 15 | include: $(addsuffix /make.include,$(SUBDIRS)) 16 | 17 | libs: $(addsuffix /make.libs,$(SUBDIRS)) 18 | 19 | $(PROCESSOR)/lib/libxil.a: $(PROCESSOR)/lib/libxil_init.a 20 | cp -f $< $@ 21 | 22 | %/make.include: $(if $(wildcard $(PROCESSOR)/lib/libxil_init.a),$(PROCESSOR)/lib/libxil.a,) 23 | @echo "Running Make include in $(subst /make.include,,$@)" 24 | $(MAKE) -C $(subst /make.include,,$@) -s include "SHELL=$(SHELL)" "COMPILER=arm-xilinx-eabi-gcc" "ARCHIVER=arm-xilinx-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-g" 25 | 26 | %/make.libs: include 27 | @echo "Running Make libs in $(subst /make.libs,,$@)" 28 | $(MAKE) -C $(subst /make.libs,,$@) -s libs "SHELL=$(SHELL)" "COMPILER=arm-xilinx-eabi-gcc" "ARCHIVER=arm-xilinx-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-g" 29 | 30 | clean: 31 | rm -f ${PROCESSOR}/lib/libxil.a 32 | -------------------------------------------------------------------------------- /sdk/hdmi_in_wrapper_hw_platform_0/.project: -------------------------------------------------------------------------------- 1 | 2 | 3 | hdmi_in_wrapper_hw_platform_0 4 | Created by SDK v2016.4 5 | 6 | 7 | 8 | 9 | 10 | com.xilinx.sdk.hw.HwProject 11 | 12 | 13 | 14 | 1488225148553 15 | 16 | 6 17 | 18 | org.eclipse.ui.ide.multiFilter 19 | 1.0-name-matches-false-false-*.xml 20 | 21 | 22 | 23 | 1488225148562 24 | 25 | 6 26 | 27 | org.eclipse.ui.ide.multiFilter 28 | 1.0-name-matches-false-false-*.svd 29 | 30 | 31 | 32 | 1488225148571 33 | 34 | 6 35 | 36 | org.eclipse.ui.ide.multiFilter 37 | 1.0-name-matches-false-false-*.hwh 38 | 39 | 40 | 41 | 42 | -------------------------------------------------------------------------------- /sdk/hdmi_in_wrapper_hw_platform_0/system.hdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Digilent/Zybo-hdmi-in/5f423ed8732a72c07d0ae40418ac6f44f4256f02/sdk/hdmi_in_wrapper_hw_platform_0/system.hdf -------------------------------------------------------------------------------- /src/bd/.keep: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Digilent/Zybo-hdmi-in/5f423ed8732a72c07d0ae40418ac6f44f4256f02/src/bd/.keep -------------------------------------------------------------------------------- /src/bd/hdmi_in/hdl/hdmi_in.hwdef: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Digilent/Zybo-hdmi-in/5f423ed8732a72c07d0ae40418ac6f44f4256f02/src/bd/hdmi_in/hdl/hdmi_in.hwdef -------------------------------------------------------------------------------- /src/bd/hdmi_in/hdmi_in_ooc.xdc: -------------------------------------------------------------------------------- 1 | ################################################################################ 2 | 3 | # This XDC is used only for OOC mode of synthesis, implementation 4 | # This constraints file contains default clock frequencies to be used during 5 | # out-of-context flows such as OOC Synthesis and Hierarchical Designs. 6 | # This constraints file is not used in normal top-down synthesis (default flow 7 | # of Vivado) 8 | ################################################################################ 9 | create_clock -name TMDS_clk_p -period 10 [get_ports TMDS_clk_p] 10 | create_clock -name TMDS_clk_n -period 10 [get_ports TMDS_clk_n] 11 | create_clock -name processing_system7_0_FCLK_CLK0 -period 10 [get_pins processing_system7_0/FCLK_CLK0] 12 | create_clock -name processing_system7_0_FCLK_CLK1 -period 7 [get_pins processing_system7_0/FCLK_CLK1] 13 | create_clock -name processing_system7_0_FCLK_CLK2 -period 5 [get_pins processing_system7_0/FCLK_CLK2] 14 | 15 | ################################################################################ -------------------------------------------------------------------------------- /src/bd/hdmi_in/ip/hdmi_in_auto_pc_0/hdmi_in_auto_pc_0_ooc.xdc: -------------------------------------------------------------------------------- 1 | # (c) Copyright 2012-2017 Xilinx, Inc. All rights reserved. 2 | # 3 | # This file contains confidential and proprietary information 4 | # of Xilinx, Inc. and is protected under U.S. and 5 | # international copyright and other intellectual property 6 | # laws. 7 | # 8 | # DISCLAIMER 9 | # This disclaimer is not a license and does not grant any 10 | # rights to the materials distributed herewith. Except as 11 | # otherwise provided in a valid license issued to you by 12 | # Xilinx, and to the maximum extent permitted by applicable 13 | # law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 14 | # WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 15 | # AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 16 | # BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 17 | # INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 18 | # (2) Xilinx shall not be liable (whether in contract or tort, 19 | # including negligence, or under any other theory of 20 | # liability) for any loss or damage of any kind or nature 21 | # related to, arising under or in connection with these 22 | # materials, including for any direct, or any indirect, 23 | # special, incidental, or consequential loss or damage 24 | # (including loss of data, profits, goodwill, or any type of 25 | # loss or damage suffered as a result of any action brought 26 | # by a third party) even if such damage or loss was 27 | # reasonably foreseeable or Xilinx had been advised of the 28 | # possibility of the same. 29 | # 30 | # CRITICAL APPLICATIONS 31 | # Xilinx products are not designed or intended to be fail- 32 | # safe, or for use in any application requiring fail-safe 33 | # performance, such as life-support or safety devices or 34 | # systems, Class III medical devices, nuclear facilities, 35 | # applications related to the deployment of airbags, or any 36 | # other applications that could lead to death, personal 37 | # injury, or severe property or environmental damage 38 | # (individually and collectively, "Critical 39 | # Applications"). Customer assumes the sole risk and 40 | # liability of any use of Xilinx products in Critical 41 | # Applications, subject only to applicable laws and 42 | # regulations governing limitations on product liability. 43 | # 44 | # THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 45 | # PART OF THIS FILE AT ALL TIMES. 46 | # 47 | # DO NOT MODIFY THIS FILE. 48 | # ######################################################### 49 | # 50 | # This XDC is used only in OOC mode for synthesis, implementation 51 | # 52 | # ######################################################### 53 | 54 | 55 | create_clock -period 7 -name aclk [get_ports aclk] 56 | 57 | 58 | -------------------------------------------------------------------------------- /src/bd/hdmi_in/ip/hdmi_in_auto_pc_1/hdmi_in_auto_pc_1_ooc.xdc: -------------------------------------------------------------------------------- 1 | # (c) Copyright 2012-2017 Xilinx, Inc. All rights reserved. 2 | # 3 | # This file contains confidential and proprietary information 4 | # of Xilinx, Inc. and is protected under U.S. and 5 | # international copyright and other intellectual property 6 | # laws. 7 | # 8 | # DISCLAIMER 9 | # This disclaimer is not a license and does not grant any 10 | # rights to the materials distributed herewith. Except as 11 | # otherwise provided in a valid license issued to you by 12 | # Xilinx, and to the maximum extent permitted by applicable 13 | # law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 14 | # WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 15 | # AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 16 | # BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 17 | # INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 18 | # (2) Xilinx shall not be liable (whether in contract or tort, 19 | # including negligence, or under any other theory of 20 | # liability) for any loss or damage of any kind or nature 21 | # related to, arising under or in connection with these 22 | # materials, including for any direct, or any indirect, 23 | # special, incidental, or consequential loss or damage 24 | # (including loss of data, profits, goodwill, or any type of 25 | # loss or damage suffered as a result of any action brought 26 | # by a third party) even if such damage or loss was 27 | # reasonably foreseeable or Xilinx had been advised of the 28 | # possibility of the same. 29 | # 30 | # CRITICAL APPLICATIONS 31 | # Xilinx products are not designed or intended to be fail- 32 | # safe, or for use in any application requiring fail-safe 33 | # performance, such as life-support or safety devices or 34 | # systems, Class III medical devices, nuclear facilities, 35 | # applications related to the deployment of airbags, or any 36 | # other applications that could lead to death, personal 37 | # injury, or severe property or environmental damage 38 | # (individually and collectively, "Critical 39 | # Applications"). Customer assumes the sole risk and 40 | # liability of any use of Xilinx products in Critical 41 | # Applications, subject only to applicable laws and 42 | # regulations governing limitations on product liability. 43 | # 44 | # THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 45 | # PART OF THIS FILE AT ALL TIMES. 46 | # 47 | # DO NOT MODIFY THIS FILE. 48 | # ######################################################### 49 | # 50 | # This XDC is used only in OOC mode for synthesis, implementation 51 | # 52 | # ######################################################### 53 | 54 | 55 | create_clock -period 10 -name aclk [get_ports aclk] 56 | 57 | 58 | -------------------------------------------------------------------------------- /src/bd/hdmi_in/ip/hdmi_in_auto_us_df_0/hdmi_in_auto_us_df_0_clocks.xdc: -------------------------------------------------------------------------------- 1 | ############################################################################################################### 2 | # Core-Level Timing Constraints for axi_dwidth_converter Component "hdmi_in_auto_us_df_0" 3 | ############################################################################################################### 4 | # 5 | # This component is not configured to perform asynchronous clock-domain-crossing. 6 | # No timing core-level constraints are needed. 7 | # (Synchronous clock-domain-crossings, if any, remain covered by your system-level PERIOD constraints.) 8 | -------------------------------------------------------------------------------- /src/bd/hdmi_in/ip/hdmi_in_auto_us_df_0/hdmi_in_auto_us_df_0_ooc.xdc: -------------------------------------------------------------------------------- 1 | # (c) Copyright 2012-2017 Xilinx, Inc. All rights reserved. 2 | # 3 | # This file contains confidential and proprietary information 4 | # of Xilinx, Inc. and is protected under U.S. and 5 | # international copyright and other intellectual property 6 | # laws. 7 | # 8 | # DISCLAIMER 9 | # This disclaimer is not a license and does not grant any 10 | # rights to the materials distributed herewith. Except as 11 | # otherwise provided in a valid license issued to you by 12 | # Xilinx, and to the maximum extent permitted by applicable 13 | # law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 14 | # WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 15 | # AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 16 | # BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 17 | # INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 18 | # (2) Xilinx shall not be liable (whether in contract or tort, 19 | # including negligence, or under any other theory of 20 | # liability) for any loss or damage of any kind or nature 21 | # related to, arising under or in connection with these 22 | # materials, including for any direct, or any indirect, 23 | # special, incidental, or consequential loss or damage 24 | # (including loss of data, profits, goodwill, or any type of 25 | # loss or damage suffered as a result of any action brought 26 | # by a third party) even if such damage or loss was 27 | # reasonably foreseeable or Xilinx had been advised of the 28 | # possibility of the same. 29 | # 30 | # CRITICAL APPLICATIONS 31 | # Xilinx products are not designed or intended to be fail- 32 | # safe, or for use in any application requiring fail-safe 33 | # performance, such as life-support or safety devices or 34 | # systems, Class III medical devices, nuclear facilities, 35 | # applications related to the deployment of airbags, or any 36 | # other applications that could lead to death, personal 37 | # injury, or severe property or environmental damage 38 | # (individually and collectively, "Critical 39 | # Applications"). Customer assumes the sole risk and 40 | # liability of any use of Xilinx products in Critical 41 | # Applications, subject only to applicable laws and 42 | # regulations governing limitations on product liability. 43 | # 44 | # THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 45 | # PART OF THIS FILE AT ALL TIMES. 46 | # 47 | # DO NOT MODIFY THIS FILE. 48 | # ######################################################### 49 | # 50 | # This XDC is used only in OOC mode for synthesis, implementation 51 | # 52 | # ######################################################### 53 | 54 | 55 | create_clock -period 7 -name s_axi_aclk [get_ports s_axi_aclk] 56 | 57 | 58 | -------------------------------------------------------------------------------- /src/bd/hdmi_in/ip/hdmi_in_auto_us_df_1/hdmi_in_auto_us_df_1_clocks.xdc: -------------------------------------------------------------------------------- 1 | ############################################################################################################### 2 | # Core-Level Timing Constraints for axi_dwidth_converter Component "hdmi_in_auto_us_df_1" 3 | ############################################################################################################### 4 | # 5 | # This component is not configured to perform asynchronous clock-domain-crossing. 6 | # No timing core-level constraints are needed. 7 | # (Synchronous clock-domain-crossings, if any, remain covered by your system-level PERIOD constraints.) 8 | -------------------------------------------------------------------------------- /src/bd/hdmi_in/ip/hdmi_in_auto_us_df_1/hdmi_in_auto_us_df_1_ooc.xdc: -------------------------------------------------------------------------------- 1 | # (c) Copyright 2012-2017 Xilinx, Inc. All rights reserved. 2 | # 3 | # This file contains confidential and proprietary information 4 | # of Xilinx, Inc. and is protected under U.S. and 5 | # international copyright and other intellectual property 6 | # laws. 7 | # 8 | # DISCLAIMER 9 | # This disclaimer is not a license and does not grant any 10 | # rights to the materials distributed herewith. Except as 11 | # otherwise provided in a valid license issued to you by 12 | # Xilinx, and to the maximum extent permitted by applicable 13 | # law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 14 | # WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 15 | # AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 16 | # BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 17 | # INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 18 | # (2) Xilinx shall not be liable (whether in contract or tort, 19 | # including negligence, or under any other theory of 20 | # liability) for any loss or damage of any kind or nature 21 | # related to, arising under or in connection with these 22 | # materials, including for any direct, or any indirect, 23 | # special, incidental, or consequential loss or damage 24 | # (including loss of data, profits, goodwill, or any type of 25 | # loss or damage suffered as a result of any action brought 26 | # by a third party) even if such damage or loss was 27 | # reasonably foreseeable or Xilinx had been advised of the 28 | # possibility of the same. 29 | # 30 | # CRITICAL APPLICATIONS 31 | # Xilinx products are not designed or intended to be fail- 32 | # safe, or for use in any application requiring fail-safe 33 | # performance, such as life-support or safety devices or 34 | # systems, Class III medical devices, nuclear facilities, 35 | # applications related to the deployment of airbags, or any 36 | # other applications that could lead to death, personal 37 | # injury, or severe property or environmental damage 38 | # (individually and collectively, "Critical 39 | # Applications"). Customer assumes the sole risk and 40 | # liability of any use of Xilinx products in Critical 41 | # Applications, subject only to applicable laws and 42 | # regulations governing limitations on product liability. 43 | # 44 | # THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 45 | # PART OF THIS FILE AT ALL TIMES. 46 | # 47 | # DO NOT MODIFY THIS FILE. 48 | # ######################################################### 49 | # 50 | # This XDC is used only in OOC mode for synthesis, implementation 51 | # 52 | # ######################################################### 53 | 54 | 55 | create_clock -period 7 -name s_axi_aclk [get_ports s_axi_aclk] 56 | 57 | 58 | -------------------------------------------------------------------------------- /src/bd/hdmi_in/ip/hdmi_in_axi_gpio_btn_0/hdmi_in_axi_gpio_btn_0.xdc: -------------------------------------------------------------------------------- 1 | 2 | # (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved. 3 | # 4 | # This file contains confidential and proprietary information 5 | # of Xilinx, Inc. and is protected under U.S. and 6 | # international copyright and other intellectual property 7 | # laws. 8 | # 9 | # DISCLAIMER 10 | # This disclaimer is not a license and does not grant any 11 | # rights to the materials distributed herewith. Except as 12 | # otherwise provided in a valid license issued to you by 13 | # Xilinx, and to the maximum extent permitted by applicable 14 | # law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 15 | # WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 16 | # AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 17 | # BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 18 | # INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 19 | # (2) Xilinx shall not be liable (whether in contract or tort, 20 | # including negligence, or under any other theory of 21 | # liability) for any loss or damage of any kind or nature 22 | # related to, arising under or in connection with these 23 | # materials, including for any direct, or any indirect, 24 | # special, incidental, or consequential loss or damage 25 | # (including loss of data, profits, goodwill, or any type of 26 | # loss or damage suffered as a result of any action brought 27 | # by a third party) even if such damage or loss was 28 | # reasonably foreseeable or Xilinx had been advised of the 29 | # possibility of the same. 30 | # 31 | # CRITICAL APPLICATIONS 32 | # Xilinx products are not designed or intended to be fail- 33 | # safe, or for use in any application requiring fail-safe 34 | # performance, such as life-support or safety devices or 35 | # systems, Class III medical devices, nuclear facilities, 36 | # applications related to the deployment of airbags, or any 37 | # other applications that could lead to death, personal 38 | # injury, or severe property or environmental damage 39 | # (individually and collectively, "Critical 40 | # Applications"). Customer assumes the sole risk and 41 | # liability of any use of Xilinx products in Critical 42 | # Applications, subject only to applicable laws and 43 | # regulations governing limitations on product liability. 44 | # 45 | # THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 46 | # PART OF THIS FILE AT ALL TIMES. 47 | 48 | 49 | set_false_path -to [get_pins -hier *cdc_to*/D] 50 | 51 | -------------------------------------------------------------------------------- /src/bd/hdmi_in/ip/hdmi_in_axi_gpio_btn_0/hdmi_in_axi_gpio_btn_0_board.xdc: -------------------------------------------------------------------------------- 1 | #--------------------Physical Constraints----------------- 2 | 3 | set_property BOARD_PIN {btns_4bits_tri_i_0} [get_ports gpio_io_i[0]] 4 | 5 | set_property BOARD_PIN {btns_4bits_tri_i_1} [get_ports gpio_io_i[1]] 6 | 7 | set_property BOARD_PIN {btns_4bits_tri_i_2} [get_ports gpio_io_i[2]] 8 | 9 | set_property BOARD_PIN {btns_4bits_tri_i_3} [get_ports gpio_io_i[3]] 10 | 11 | -------------------------------------------------------------------------------- /src/bd/hdmi_in/ip/hdmi_in_axi_gpio_btn_0/hdmi_in_axi_gpio_btn_0_ooc.xdc: -------------------------------------------------------------------------------- 1 | 2 | ################################################################################ 3 | # (c) Copyright 2012 - 2013 Xilinx, Inc. All rights reserved. 4 | # 5 | # This file contains confidential and proprietary information 6 | # of Xilinx, Inc. and is protected under U.S. and 7 | # international copyright and other intellectual property 8 | # laws. 9 | # 10 | # DISCLAIMER 11 | # This disclaimer is not a license and does not grant any 12 | # rights to the materials distributed herewith. Except as 13 | # otherwise provided in a valid license issued to you by 14 | # Xilinx, and to the maximum extent permitted by applicable 15 | # law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 16 | # WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 17 | # AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 18 | # BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 19 | # INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 20 | # (2) Xilinx shall not be liable (whether in contract or tort, 21 | # including negligence, or under any other theory of 22 | # liability) for any loss or damage of any kind or nature 23 | # related to, arising under or in connection with these 24 | # materials, including for any direct, or any indirect, 25 | # special, incidental, or consequential loss or damage 26 | # (including loss of data, profits, goodwill, or any type of 27 | # loss or damage suffered as a result of any action brought 28 | # by a third party) even if such damage or loss was 29 | # reasonably foreseeable or Xilinx had been advised of the 30 | # possibility of the same. 31 | # 32 | # CRITICAL APPLICATIONS 33 | # Xilinx products are not designed or intended to be fail- 34 | # safe, or for use in any application requiring fail-safe 35 | # performance, such as life-support or safety devices or 36 | # systems, Class III medical devices, nuclear facilities, 37 | # applications related to the deployment of airbags, or any 38 | # other applications that could lead to death, personal 39 | # injury, or severe property or environmental damage 40 | # (individually and collectively, "Critical 41 | # Applications"). Customer assumes the sole risk and 42 | # liability of any use of Xilinx products in Critical 43 | # Applications, subject only to applicable laws and 44 | # regulations governing limitations on product liability. 45 | # 46 | # THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 47 | # PART OF THIS FILE AT ALL TIMES. 48 | 49 | ################################################################################ 50 | 51 | # This XDC is used only for OOC mode of synthesis, implementation 52 | # User should update the correct clock period before proceeding further 53 | # This constraints file contains default clock frequencies to be used during 54 | # out-of-context flows such as OOC Synthesis and Hierarchical Designs. 55 | # For best results the frequencies should be modified# to match the target 56 | # frequencies. 57 | 58 | 59 | create_clock -name s_axi_clk -period 10 [get_ports s_axi_aclk] 60 | ## set_property HD.CLK_SRC BUFGCTRL_X0Y0 [get_ports s_axi_aclk] 61 | 62 | ################################################################################ 63 | -------------------------------------------------------------------------------- /src/bd/hdmi_in/ip/hdmi_in_axi_gpio_led_0/hdmi_in_axi_gpio_led_0.xdc: -------------------------------------------------------------------------------- 1 | 2 | # (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved. 3 | # 4 | # This file contains confidential and proprietary information 5 | # of Xilinx, Inc. and is protected under U.S. and 6 | # international copyright and other intellectual property 7 | # laws. 8 | # 9 | # DISCLAIMER 10 | # This disclaimer is not a license and does not grant any 11 | # rights to the materials distributed herewith. Except as 12 | # otherwise provided in a valid license issued to you by 13 | # Xilinx, and to the maximum extent permitted by applicable 14 | # law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 15 | # WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 16 | # AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 17 | # BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 18 | # INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 19 | # (2) Xilinx shall not be liable (whether in contract or tort, 20 | # including negligence, or under any other theory of 21 | # liability) for any loss or damage of any kind or nature 22 | # related to, arising under or in connection with these 23 | # materials, including for any direct, or any indirect, 24 | # special, incidental, or consequential loss or damage 25 | # (including loss of data, profits, goodwill, or any type of 26 | # loss or damage suffered as a result of any action brought 27 | # by a third party) even if such damage or loss was 28 | # reasonably foreseeable or Xilinx had been advised of the 29 | # possibility of the same. 30 | # 31 | # CRITICAL APPLICATIONS 32 | # Xilinx products are not designed or intended to be fail- 33 | # safe, or for use in any application requiring fail-safe 34 | # performance, such as life-support or safety devices or 35 | # systems, Class III medical devices, nuclear facilities, 36 | # applications related to the deployment of airbags, or any 37 | # other applications that could lead to death, personal 38 | # injury, or severe property or environmental damage 39 | # (individually and collectively, "Critical 40 | # Applications"). Customer assumes the sole risk and 41 | # liability of any use of Xilinx products in Critical 42 | # Applications, subject only to applicable laws and 43 | # regulations governing limitations on product liability. 44 | # 45 | # THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 46 | # PART OF THIS FILE AT ALL TIMES. 47 | 48 | 49 | set_false_path -to [get_pins -hier *cdc_to*/D] 50 | 51 | -------------------------------------------------------------------------------- /src/bd/hdmi_in/ip/hdmi_in_axi_gpio_led_0/hdmi_in_axi_gpio_led_0_board.xdc: -------------------------------------------------------------------------------- 1 | #--------------------Physical Constraints----------------- 2 | 3 | set_property BOARD_PIN {leds_4bits_tri_o_0} [get_ports gpio_io_t[0]] 4 | 5 | set_property BOARD_PIN {leds_4bits_tri_o_1} [get_ports gpio_io_t[1]] 6 | 7 | set_property BOARD_PIN {leds_4bits_tri_o_2} [get_ports gpio_io_t[2]] 8 | 9 | set_property BOARD_PIN {leds_4bits_tri_o_3} [get_ports gpio_io_t[3]] 10 | 11 | -------------------------------------------------------------------------------- /src/bd/hdmi_in/ip/hdmi_in_axi_gpio_led_0/hdmi_in_axi_gpio_led_0_ooc.xdc: -------------------------------------------------------------------------------- 1 | 2 | ################################################################################ 3 | # (c) Copyright 2012 - 2013 Xilinx, Inc. All rights reserved. 4 | # 5 | # This file contains confidential and proprietary information 6 | # of Xilinx, Inc. and is protected under U.S. and 7 | # international copyright and other intellectual property 8 | # laws. 9 | # 10 | # DISCLAIMER 11 | # This disclaimer is not a license and does not grant any 12 | # rights to the materials distributed herewith. Except as 13 | # otherwise provided in a valid license issued to you by 14 | # Xilinx, and to the maximum extent permitted by applicable 15 | # law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 16 | # WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 17 | # AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 18 | # BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 19 | # INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 20 | # (2) Xilinx shall not be liable (whether in contract or tort, 21 | # including negligence, or under any other theory of 22 | # liability) for any loss or damage of any kind or nature 23 | # related to, arising under or in connection with these 24 | # materials, including for any direct, or any indirect, 25 | # special, incidental, or consequential loss or damage 26 | # (including loss of data, profits, goodwill, or any type of 27 | # loss or damage suffered as a result of any action brought 28 | # by a third party) even if such damage or loss was 29 | # reasonably foreseeable or Xilinx had been advised of the 30 | # possibility of the same. 31 | # 32 | # CRITICAL APPLICATIONS 33 | # Xilinx products are not designed or intended to be fail- 34 | # safe, or for use in any application requiring fail-safe 35 | # performance, such as life-support or safety devices or 36 | # systems, Class III medical devices, nuclear facilities, 37 | # applications related to the deployment of airbags, or any 38 | # other applications that could lead to death, personal 39 | # injury, or severe property or environmental damage 40 | # (individually and collectively, "Critical 41 | # Applications"). Customer assumes the sole risk and 42 | # liability of any use of Xilinx products in Critical 43 | # Applications, subject only to applicable laws and 44 | # regulations governing limitations on product liability. 45 | # 46 | # THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 47 | # PART OF THIS FILE AT ALL TIMES. 48 | 49 | ################################################################################ 50 | 51 | # This XDC is used only for OOC mode of synthesis, implementation 52 | # User should update the correct clock period before proceeding further 53 | # This constraints file contains default clock frequencies to be used during 54 | # out-of-context flows such as OOC Synthesis and Hierarchical Designs. 55 | # For best results the frequencies should be modified# to match the target 56 | # frequencies. 57 | 58 | 59 | create_clock -name s_axi_clk -period 10 [get_ports s_axi_aclk] 60 | ## set_property HD.CLK_SRC BUFGCTRL_X0Y0 [get_ports s_axi_aclk] 61 | 62 | ################################################################################ 63 | -------------------------------------------------------------------------------- /src/bd/hdmi_in/ip/hdmi_in_axi_gpio_sw_0/hdmi_in_axi_gpio_sw_0.xdc: -------------------------------------------------------------------------------- 1 | 2 | # (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved. 3 | # 4 | # This file contains confidential and proprietary information 5 | # of Xilinx, Inc. and is protected under U.S. and 6 | # international copyright and other intellectual property 7 | # laws. 8 | # 9 | # DISCLAIMER 10 | # This disclaimer is not a license and does not grant any 11 | # rights to the materials distributed herewith. Except as 12 | # otherwise provided in a valid license issued to you by 13 | # Xilinx, and to the maximum extent permitted by applicable 14 | # law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 15 | # WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 16 | # AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 17 | # BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 18 | # INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 19 | # (2) Xilinx shall not be liable (whether in contract or tort, 20 | # including negligence, or under any other theory of 21 | # liability) for any loss or damage of any kind or nature 22 | # related to, arising under or in connection with these 23 | # materials, including for any direct, or any indirect, 24 | # special, incidental, or consequential loss or damage 25 | # (including loss of data, profits, goodwill, or any type of 26 | # loss or damage suffered as a result of any action brought 27 | # by a third party) even if such damage or loss was 28 | # reasonably foreseeable or Xilinx had been advised of the 29 | # possibility of the same. 30 | # 31 | # CRITICAL APPLICATIONS 32 | # Xilinx products are not designed or intended to be fail- 33 | # safe, or for use in any application requiring fail-safe 34 | # performance, such as life-support or safety devices or 35 | # systems, Class III medical devices, nuclear facilities, 36 | # applications related to the deployment of airbags, or any 37 | # other applications that could lead to death, personal 38 | # injury, or severe property or environmental damage 39 | # (individually and collectively, "Critical 40 | # Applications"). Customer assumes the sole risk and 41 | # liability of any use of Xilinx products in Critical 42 | # Applications, subject only to applicable laws and 43 | # regulations governing limitations on product liability. 44 | # 45 | # THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 46 | # PART OF THIS FILE AT ALL TIMES. 47 | 48 | 49 | set_false_path -to [get_pins -hier *cdc_to*/D] 50 | 51 | -------------------------------------------------------------------------------- /src/bd/hdmi_in/ip/hdmi_in_axi_gpio_sw_0/hdmi_in_axi_gpio_sw_0_board.xdc: -------------------------------------------------------------------------------- 1 | #--------------------Physical Constraints----------------- 2 | 3 | set_property BOARD_PIN {sws_4bits_tri_i_0} [get_ports gpio_io_i[0]] 4 | 5 | set_property BOARD_PIN {sws_4bits_tri_i_1} [get_ports gpio_io_i[1]] 6 | 7 | set_property BOARD_PIN {sws_4bits_tri_i_2} [get_ports gpio_io_i[2]] 8 | 9 | set_property BOARD_PIN {sws_4bits_tri_i_3} [get_ports gpio_io_i[3]] 10 | 11 | -------------------------------------------------------------------------------- /src/bd/hdmi_in/ip/hdmi_in_axi_gpio_sw_0/hdmi_in_axi_gpio_sw_0_ooc.xdc: -------------------------------------------------------------------------------- 1 | 2 | ################################################################################ 3 | # (c) Copyright 2012 - 2013 Xilinx, Inc. All rights reserved. 4 | # 5 | # This file contains confidential and proprietary information 6 | # of Xilinx, Inc. and is protected under U.S. and 7 | # international copyright and other intellectual property 8 | # laws. 9 | # 10 | # DISCLAIMER 11 | # This disclaimer is not a license and does not grant any 12 | # rights to the materials distributed herewith. Except as 13 | # otherwise provided in a valid license issued to you by 14 | # Xilinx, and to the maximum extent permitted by applicable 15 | # law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 16 | # WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 17 | # AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 18 | # BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 19 | # INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 20 | # (2) Xilinx shall not be liable (whether in contract or tort, 21 | # including negligence, or under any other theory of 22 | # liability) for any loss or damage of any kind or nature 23 | # related to, arising under or in connection with these 24 | # materials, including for any direct, or any indirect, 25 | # special, incidental, or consequential loss or damage 26 | # (including loss of data, profits, goodwill, or any type of 27 | # loss or damage suffered as a result of any action brought 28 | # by a third party) even if such damage or loss was 29 | # reasonably foreseeable or Xilinx had been advised of the 30 | # possibility of the same. 31 | # 32 | # CRITICAL APPLICATIONS 33 | # Xilinx products are not designed or intended to be fail- 34 | # safe, or for use in any application requiring fail-safe 35 | # performance, such as life-support or safety devices or 36 | # systems, Class III medical devices, nuclear facilities, 37 | # applications related to the deployment of airbags, or any 38 | # other applications that could lead to death, personal 39 | # injury, or severe property or environmental damage 40 | # (individually and collectively, "Critical 41 | # Applications"). Customer assumes the sole risk and 42 | # liability of any use of Xilinx products in Critical 43 | # Applications, subject only to applicable laws and 44 | # regulations governing limitations on product liability. 45 | # 46 | # THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 47 | # PART OF THIS FILE AT ALL TIMES. 48 | 49 | ################################################################################ 50 | 51 | # This XDC is used only for OOC mode of synthesis, implementation 52 | # User should update the correct clock period before proceeding further 53 | # This constraints file contains default clock frequencies to be used during 54 | # out-of-context flows such as OOC Synthesis and Hierarchical Designs. 55 | # For best results the frequencies should be modified# to match the target 56 | # frequencies. 57 | 58 | 59 | create_clock -name s_axi_clk -period 10 [get_ports s_axi_aclk] 60 | ## set_property HD.CLK_SRC BUFGCTRL_X0Y0 [get_ports s_axi_aclk] 61 | 62 | ################################################################################ 63 | -------------------------------------------------------------------------------- /src/bd/hdmi_in/ip/hdmi_in_axi_gpio_video_0/hdmi_in_axi_gpio_video_0.xdc: -------------------------------------------------------------------------------- 1 | 2 | # (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved. 3 | # 4 | # This file contains confidential and proprietary information 5 | # of Xilinx, Inc. and is protected under U.S. and 6 | # international copyright and other intellectual property 7 | # laws. 8 | # 9 | # DISCLAIMER 10 | # This disclaimer is not a license and does not grant any 11 | # rights to the materials distributed herewith. Except as 12 | # otherwise provided in a valid license issued to you by 13 | # Xilinx, and to the maximum extent permitted by applicable 14 | # law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 15 | # WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 16 | # AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 17 | # BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 18 | # INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 19 | # (2) Xilinx shall not be liable (whether in contract or tort, 20 | # including negligence, or under any other theory of 21 | # liability) for any loss or damage of any kind or nature 22 | # related to, arising under or in connection with these 23 | # materials, including for any direct, or any indirect, 24 | # special, incidental, or consequential loss or damage 25 | # (including loss of data, profits, goodwill, or any type of 26 | # loss or damage suffered as a result of any action brought 27 | # by a third party) even if such damage or loss was 28 | # reasonably foreseeable or Xilinx had been advised of the 29 | # possibility of the same. 30 | # 31 | # CRITICAL APPLICATIONS 32 | # Xilinx products are not designed or intended to be fail- 33 | # safe, or for use in any application requiring fail-safe 34 | # performance, such as life-support or safety devices or 35 | # systems, Class III medical devices, nuclear facilities, 36 | # applications related to the deployment of airbags, or any 37 | # other applications that could lead to death, personal 38 | # injury, or severe property or environmental damage 39 | # (individually and collectively, "Critical 40 | # Applications"). Customer assumes the sole risk and 41 | # liability of any use of Xilinx products in Critical 42 | # Applications, subject only to applicable laws and 43 | # regulations governing limitations on product liability. 44 | # 45 | # THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 46 | # PART OF THIS FILE AT ALL TIMES. 47 | 48 | 49 | set_false_path -to [get_pins -hier *cdc_to*/D] 50 | 51 | -------------------------------------------------------------------------------- /src/bd/hdmi_in/ip/hdmi_in_axi_gpio_video_0/hdmi_in_axi_gpio_video_0_board.xdc: -------------------------------------------------------------------------------- 1 | #--------------------Physical Constraints----------------- 2 | 3 | -------------------------------------------------------------------------------- /src/bd/hdmi_in/ip/hdmi_in_axi_gpio_video_0/hdmi_in_axi_gpio_video_0_ooc.xdc: -------------------------------------------------------------------------------- 1 | 2 | ################################################################################ 3 | # (c) Copyright 2012 - 2013 Xilinx, Inc. All rights reserved. 4 | # 5 | # This file contains confidential and proprietary information 6 | # of Xilinx, Inc. and is protected under U.S. and 7 | # international copyright and other intellectual property 8 | # laws. 9 | # 10 | # DISCLAIMER 11 | # This disclaimer is not a license and does not grant any 12 | # rights to the materials distributed herewith. Except as 13 | # otherwise provided in a valid license issued to you by 14 | # Xilinx, and to the maximum extent permitted by applicable 15 | # law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 16 | # WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 17 | # AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 18 | # BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 19 | # INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 20 | # (2) Xilinx shall not be liable (whether in contract or tort, 21 | # including negligence, or under any other theory of 22 | # liability) for any loss or damage of any kind or nature 23 | # related to, arising under or in connection with these 24 | # materials, including for any direct, or any indirect, 25 | # special, incidental, or consequential loss or damage 26 | # (including loss of data, profits, goodwill, or any type of 27 | # loss or damage suffered as a result of any action brought 28 | # by a third party) even if such damage or loss was 29 | # reasonably foreseeable or Xilinx had been advised of the 30 | # possibility of the same. 31 | # 32 | # CRITICAL APPLICATIONS 33 | # Xilinx products are not designed or intended to be fail- 34 | # safe, or for use in any application requiring fail-safe 35 | # performance, such as life-support or safety devices or 36 | # systems, Class III medical devices, nuclear facilities, 37 | # applications related to the deployment of airbags, or any 38 | # other applications that could lead to death, personal 39 | # injury, or severe property or environmental damage 40 | # (individually and collectively, "Critical 41 | # Applications"). Customer assumes the sole risk and 42 | # liability of any use of Xilinx products in Critical 43 | # Applications, subject only to applicable laws and 44 | # regulations governing limitations on product liability. 45 | # 46 | # THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 47 | # PART OF THIS FILE AT ALL TIMES. 48 | 49 | ################################################################################ 50 | 51 | # This XDC is used only for OOC mode of synthesis, implementation 52 | # User should update the correct clock period before proceeding further 53 | # This constraints file contains default clock frequencies to be used during 54 | # out-of-context flows such as OOC Synthesis and Hierarchical Designs. 55 | # For best results the frequencies should be modified# to match the target 56 | # frequencies. 57 | 58 | 59 | create_clock -name s_axi_clk -period 10 [get_ports s_axi_aclk] 60 | ## set_property HD.CLK_SRC BUFGCTRL_X0Y0 [get_ports s_axi_aclk] 61 | 62 | ################################################################################ 63 | -------------------------------------------------------------------------------- /src/bd/hdmi_in/ip/hdmi_in_axi_vdma_0_0/hdmi_in_axi_vdma_0_0.xdc: -------------------------------------------------------------------------------- 1 | # (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved. 2 | # 3 | # This file contains confidential and proprietary information 4 | # of Xilinx, Inc. and is protected under U.S. and 5 | # international copyright and other intellectual property 6 | # laws. 7 | # 8 | # DISCLAIMER 9 | # This disclaimer is not a license and does not grant any 10 | # rights to the materials distributed herewith. Except as 11 | # otherwise provided in a valid license issued to you by 12 | # Xilinx, and to the maximum extent permitted by applicable 13 | # law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 14 | # WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 15 | # AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 16 | # BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 17 | # INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 18 | # (2) Xilinx shall not be liable (whether in contract or tort, 19 | # including negligence, or under any other theory of 20 | # liability) for any loss or damage of any kind or nature 21 | # related to, arising under or in connection with these 22 | # materials, including for any direct, or any indirect, 23 | # special, incidental, or consequential loss or damage 24 | # (including loss of data, profits, goodwill, or any type of 25 | # loss or damage suffered as a result of any action brought 26 | # by a third party) even if such damage or loss was 27 | # reasonably foreseeable or Xilinx had been advised of the 28 | # possibility of the same. 29 | # 30 | # CRITICAL APPLICATIONS 31 | # Xilinx products are not designed or intended to be fail- 32 | # safe, or for use in any application requiring fail-safe 33 | # performance, such as life-support or safety devices or 34 | # systems, Class III medical devices, nuclear facilities, 35 | # applications related to the deployment of airbags, or any 36 | # other applications that could lead to death, personal 37 | # injury, or severe property or environmental damage 38 | # (individually and collectively, "Critical 39 | # Applications"). Customer assumes the sole risk and 40 | # liability of any use of Xilinx products in Critical 41 | # Applications, subject only to applicable laws and 42 | # regulations governing limitations on product liability. 43 | # 44 | # THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 45 | # PART OF THIS FILE AT ALL TIMES. 46 | ################################################################################################################################## 47 | ################################################################################################################################## 48 | 49 | ## INFO: AXI-Lite to&fro MMAP clock domain Register & Misc crossings in axi_vdma 50 | set_false_path -to [get_pins -leaf -of_objects [get_cells -hier *cdc_tig* -filter {is_sequential}] -filter {NAME=~*/D}] 51 | 52 | ## INFO: CDC Crossing in axi_vdma 53 | set_false_path -from [get_cells -hier *cdc_from* -filter {is_sequential}] -to [get_cells -hier *cdc_to* -filter {is_sequential}] 54 | 55 | ## Following constraints are needed for ASYNC FIFOs in axi_vdma 56 | 57 | 58 | set_false_path -from [get_cells -hierarchical -filter {NAME =~*MM2S*LB_BUILT_IN*/*rstbt*/*rst_reg[*]}] 59 | set_false_path -from [get_cells -hierarchical -filter {NAME =~*MM2S*LB_BUILT_IN*/*rstbt*/*rst_reg_reg}] 60 | set_false_path -to [get_pins -hierarchical -filter {NAME =~*MM2S*LB_BUILT_IN*/*rstbt*/*PRE}] 61 | 62 | 63 | 64 | set_false_path -to [get_pins -hierarchical -filter {NAME =~*S2MM*LB_BUILT_IN*/*rstbt*/*PRE}] 65 | set_false_path -from [get_cells -hierarchical -filter {NAME =~*S2MM*LB_BUILT_IN*/*rstbt*/*rst_reg_reg && IS_SEQUENTIAL}] 66 | set_false_path -from [get_cells -hierarchical -filter {NAME =~*S2MM*LB_BUILT_IN*/*rstbt*/*rst_reg[*]}] 67 | 68 | -------------------------------------------------------------------------------- /src/bd/hdmi_in/ip/hdmi_in_axi_vdma_0_0/hdmi_in_axi_vdma_0_0_clocks.xdc: -------------------------------------------------------------------------------- 1 | # (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved. 2 | # 3 | # This file contains confidential and proprietary information 4 | # of Xilinx, Inc. and is protected under U.S. and 5 | # international copyright and other intellectual property 6 | # laws. 7 | # 8 | # DISCLAIMER 9 | # This disclaimer is not a license and does not grant any 10 | # rights to the materials distributed herewith. Except as 11 | # otherwise provided in a valid license issued to you by 12 | # Xilinx, and to the maximum extent permitted by applicable 13 | # law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 14 | # WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 15 | # AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 16 | # BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 17 | # INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 18 | # (2) Xilinx shall not be liable (whether in contract or tort, 19 | # including negligence, or under any other theory of 20 | # liability) for any loss or damage of any kind or nature 21 | # related to, arising under or in connection with these 22 | # materials, including for any direct, or any indirect, 23 | # special, incidental, or consequential loss or damage 24 | # (including loss of data, profits, goodwill, or any type of 25 | # loss or damage suffered as a result of any action brought 26 | # by a third party) even if such damage or loss was 27 | # reasonably foreseeable or Xilinx had been advised of the 28 | # possibility of the same. 29 | # 30 | # CRITICAL APPLICATIONS 31 | # Xilinx products are not designed or intended to be fail- 32 | # safe, or for use in any application requiring fail-safe 33 | # performance, such as life-support or safety devices or 34 | # systems, Class III medical devices, nuclear facilities, 35 | # applications related to the deployment of airbags, or any 36 | # other applications that could lead to death, personal 37 | # injury, or severe property or environmental damage 38 | # (individually and collectively, "Critical 39 | # Applications"). Customer assumes the sole risk and 40 | # liability of any use of Xilinx products in Critical 41 | # Applications, subject only to applicable laws and 42 | # regulations governing limitations on product liability. 43 | # 44 | # THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 45 | # PART OF THIS FILE AT ALL TIMES. 46 | ################################################################################################################################## 47 | ################################################################################################################################## 48 | 49 | ## Following constraints are needed for ASYNC FIFOs in axi_vdma 50 | 51 | 52 | 53 | 54 | 55 | 56 | -------------------------------------------------------------------------------- /src/bd/hdmi_in/ip/hdmi_in_axi_vdma_0_0/hdmi_in_axi_vdma_0_0_ooc.xdc: -------------------------------------------------------------------------------- 1 | # (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved. 2 | # 3 | # This file contains confidential and proprietary information 4 | # of Xilinx, Inc. and is protected under U.S. and 5 | # international copyright and other intellectual property 6 | # laws. 7 | # 8 | # DISCLAIMER 9 | # This disclaimer is not a license and does not grant any 10 | # rights to the materials distributed herewith. Except as 11 | # otherwise provided in a valid license issued to you by 12 | # Xilinx, and to the maximum extent permitted by applicable 13 | # law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 14 | # WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 15 | # AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 16 | # BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 17 | # INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 18 | # (2) Xilinx shall not be liable (whether in contract or tort, 19 | # including negligence, or under any other theory of 20 | # liability) for any loss or damage of any kind or nature 21 | # related to, arising under or in connection with these 22 | # materials, including for any direct, or any indirect, 23 | # special, incidental, or consequential loss or damage 24 | # (including loss of data, profits, goodwill, or any type of 25 | # loss or damage suffered as a result of any action brought 26 | # by a third party) even if such damage or loss was 27 | # reasonably foreseeable or Xilinx had been advised of the 28 | # possibility of the same. 29 | # 30 | # CRITICAL APPLICATIONS 31 | # Xilinx products are not designed or intended to be fail- 32 | # safe, or for use in any application requiring fail-safe 33 | # performance, such as life-support or safety devices or 34 | # systems, Class III medical devices, nuclear facilities, 35 | # applications related to the deployment of airbags, or any 36 | # other applications that could lead to death, personal 37 | # injury, or severe property or environmental damage 38 | # (individually and collectively, "Critical 39 | # Applications"). Customer assumes the sole risk and 40 | # liability of any use of Xilinx products in Critical 41 | # Applications, subject only to applicable laws and 42 | # regulations governing limitations on product liability. 43 | # 44 | # THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 45 | # PART OF THIS FILE AT ALL TIMES. 46 | 47 | 48 | # This XDC is used only for OOC mode of synthesis, implementation 49 | # User should update the correct clock period before proceeding further 50 | 51 | 52 | create_clock -name s_axi_lite_aclk -period 50 [get_ports s_axi_lite_aclk] 53 | ## set_property HD.CLK_SRC BUFGCTRL_X0Y0 [get_ports s_axi_lite_aclk] 54 | create_clock -name m_axi_mm2s_aclk -period 10 [get_ports m_axi_mm2s_aclk] 55 | ## set_property HD.CLK_SRC BUFGCTRL_X0Y1 [get_ports m_axi_mm2s_aclk] 56 | create_clock -name m_axis_mm2s_aclk -period 20 [get_ports m_axis_mm2s_aclk] 57 | ## set_property HD.CLK_SRC BUFGCTRL_X0Y4 [get_ports m_axis_mm2s_aclk] 58 | create_clock -name m_axi_s2mm_aclk -period 10 [get_ports m_axi_s2mm_aclk] 59 | ## set_property HD.CLK_SRC BUFGCTRL_X0Y2 [get_ports m_axi_s2mm_aclk] 60 | create_clock -name s_axis_s2mm_aclk -period 20 [get_ports s_axis_s2mm_aclk] 61 | ## set_property HD.CLK_SRC BUFGCTRL_X0Y5 [get_ports s_axis_s2mm_aclk] 62 | -------------------------------------------------------------------------------- /src/bd/hdmi_in/ip/hdmi_in_dvi2rgb_0_0/src/1024_edid.data: -------------------------------------------------------------------------------- 1 | 00000000 2 | 11111111 3 | 11111111 4 | 11111111 5 | 11111111 6 | 11111111 7 | 11111111 8 | 00000000 9 | 00010000 10 | 11101100 11 | 00000000 12 | 00000000 13 | 00000000 14 | 00000000 15 | 00000000 16 | 00000000 17 | 00000010 18 | 00011010 19 | 00000001 20 | 00000011 21 | 10100001 22 | 00110011 23 | 00011101 24 | 01111000 25 | 00001010 26 | 11101100 27 | 00011000 28 | 10100011 29 | 01010100 30 | 01000110 31 | 10011000 32 | 00100101 33 | 00001111 34 | 01001000 35 | 01001100 36 | 00100001 37 | 00001000 38 | 00000000 39 | 10110011 40 | 00000000 41 | 11010001 42 | 11000000 43 | 10000001 44 | 10000000 45 | 10000001 46 | 11000000 47 | 10101001 48 | 11000000 49 | 00000001 50 | 00000001 51 | 00000001 52 | 00000001 53 | 00000001 54 | 00000001 55 | 00110000 56 | 00101010 57 | 00000000 58 | 10011000 59 | 01010001 60 | 00000000 61 | 00101010 62 | 01000000 63 | 00110000 64 | 01110000 65 | 00010011 66 | 00000000 67 | 00000000 68 | 00000000 69 | 01010100 70 | 00000000 71 | 00000000 72 | 00011110 73 | 00000000 74 | 00000000 75 | 00000000 76 | 11111100 77 | 00100000 78 | 01000100 79 | 01101001 80 | 01100111 81 | 01101001 82 | 01101100 83 | 01100101 84 | 01101110 85 | 01110100 86 | 01000100 87 | 01010110 88 | 01001001 89 | 00101101 90 | 00110000 91 | 00000000 92 | 00000000 93 | 00000000 94 | 00010000 95 | 00000000 96 | 00000000 97 | 00000000 98 | 00000000 99 | 00000000 100 | 00000000 101 | 00000000 102 | 00000000 103 | 00000000 104 | 00000000 105 | 00000000 106 | 00000000 107 | 00000000 108 | 00000000 109 | 00000000 110 | 00000000 111 | 00000000 112 | 00010000 113 | 00000000 114 | 00000000 115 | 00000000 116 | 00000000 117 | 00000000 118 | 00000000 119 | 00000000 120 | 00000000 121 | 00000000 122 | 00000000 123 | 00000000 124 | 00000000 125 | 00000000 126 | 00000000 127 | 00000000 128 | 00111010 129 | -------------------------------------------------------------------------------- /src/bd/hdmi_in/ip/hdmi_in_dvi2rgb_0_0/src/1080_edid.data: -------------------------------------------------------------------------------- 1 | 00000000 2 | 11111111 3 | 11111111 4 | 11111111 5 | 11111111 6 | 11111111 7 | 11111111 8 | 00000000 9 | 00010000 10 | 11101100 11 | 00000011 12 | 00000000 13 | 00000000 14 | 00000000 15 | 00000000 16 | 00000000 17 | 00000010 18 | 00011010 19 | 00000001 20 | 00000011 21 | 10100001 22 | 00110011 23 | 00011101 24 | 01111000 25 | 00001010 26 | 11101100 27 | 00011000 28 | 10100011 29 | 01010100 30 | 01000110 31 | 10011000 32 | 00100101 33 | 00001111 34 | 01001000 35 | 01001100 36 | 00100001 37 | 00001000 38 | 00000000 39 | 10110011 40 | 00000000 41 | 11010001 42 | 11000000 43 | 10000001 44 | 10000000 45 | 10000001 46 | 11000000 47 | 10101001 48 | 11000000 49 | 00000001 50 | 00000001 51 | 00000001 52 | 00000001 53 | 00000001 54 | 00000001 55 | 00000010 56 | 00111010 57 | 10000000 58 | 00011000 59 | 01110001 60 | 00111000 61 | 00101101 62 | 01000000 63 | 01011000 64 | 00101100 65 | 01000101 66 | 00000000 67 | 10000000 68 | 00111000 69 | 01110100 70 | 00000000 71 | 00000000 72 | 00011110 73 | 00000000 74 | 00000000 75 | 00000000 76 | 11111100 77 | 00100000 78 | 01000100 79 | 01101001 80 | 01100111 81 | 01101001 82 | 01101100 83 | 01100101 84 | 01101110 85 | 01110100 86 | 01000100 87 | 01010110 88 | 01001001 89 | 00101101 90 | 00110011 91 | 00000000 92 | 00000000 93 | 00000000 94 | 00010000 95 | 00000000 96 | 00000000 97 | 00000000 98 | 00000000 99 | 00000000 100 | 00000000 101 | 00000000 102 | 00000000 103 | 00000000 104 | 00000000 105 | 00000000 106 | 00000000 107 | 00000000 108 | 00000000 109 | 00000000 110 | 00000000 111 | 00000000 112 | 00010000 113 | 00000000 114 | 00000000 115 | 00000000 116 | 00000000 117 | 00000000 118 | 00000000 119 | 00000000 120 | 00000000 121 | 00000000 122 | 00000000 123 | 00000000 124 | 00000000 125 | 00000000 126 | 00000000 127 | 00000000 128 | 00001001 129 | -------------------------------------------------------------------------------- /src/bd/hdmi_in/ip/hdmi_in_dvi2rgb_0_0/src/720p_edid.data: -------------------------------------------------------------------------------- 1 | 00000000 2 | 11111111 3 | 11111111 4 | 11111111 5 | 11111111 6 | 11111111 7 | 11111111 8 | 00000000 9 | 00010000 10 | 11101100 11 | 00000010 12 | 00000000 13 | 00000000 14 | 00000000 15 | 00000000 16 | 00000000 17 | 00000010 18 | 00011010 19 | 00000001 20 | 00000011 21 | 10100001 22 | 00110011 23 | 00011101 24 | 01111000 25 | 00001010 26 | 11101100 27 | 00011000 28 | 10100011 29 | 01010100 30 | 01000110 31 | 10011000 32 | 00100101 33 | 00001111 34 | 01001000 35 | 01001100 36 | 00100001 37 | 00001000 38 | 00000000 39 | 10110011 40 | 00000000 41 | 11010001 42 | 11000000 43 | 10000001 44 | 10000000 45 | 10000001 46 | 11000000 47 | 10101001 48 | 11000000 49 | 00000001 50 | 00000001 51 | 00000001 52 | 00000001 53 | 00000001 54 | 00000001 55 | 00000001 56 | 00011101 57 | 00000000 58 | 01110010 59 | 01010001 60 | 11010000 61 | 00011110 62 | 00100000 63 | 01101110 64 | 00101000 65 | 01010101 66 | 00000000 67 | 00000000 68 | 11010000 69 | 01010010 70 | 00000000 71 | 00000000 72 | 00011110 73 | 00000000 74 | 00000000 75 | 00000000 76 | 11111100 77 | 00100000 78 | 01000100 79 | 01101001 80 | 01100111 81 | 01101001 82 | 01101100 83 | 01100101 84 | 01101110 85 | 01110100 86 | 01000100 87 | 01010110 88 | 01001001 89 | 00101101 90 | 00110010 91 | 00000000 92 | 00000000 93 | 00000000 94 | 00010000 95 | 00000000 96 | 00000000 97 | 00000000 98 | 00000000 99 | 00000000 100 | 00000000 101 | 00000000 102 | 00000000 103 | 00000000 104 | 00000000 105 | 00000000 106 | 00000000 107 | 00000000 108 | 00000000 109 | 00000000 110 | 00000000 111 | 00000000 112 | 00010000 113 | 00000000 114 | 00000000 115 | 00000000 116 | 00000000 117 | 00000000 118 | 00000000 119 | 00000000 120 | 00000000 121 | 00000000 122 | 00000000 123 | 00000000 124 | 00000000 125 | 00000000 126 | 00000000 127 | 00000000 128 | 11101110 129 | -------------------------------------------------------------------------------- /src/bd/hdmi_in/ip/hdmi_in_dvi2rgb_0_0/src/900p_edid.data: -------------------------------------------------------------------------------- 1 | 00000000 2 | 11111111 3 | 11111111 4 | 11111111 5 | 11111111 6 | 11111111 7 | 11111111 8 | 00000000 9 | 00010000 10 | 11101100 11 | 00000001 12 | 00000000 13 | 00000000 14 | 00000000 15 | 00000000 16 | 00000000 17 | 00000010 18 | 00011010 19 | 00000001 20 | 00000011 21 | 10100001 22 | 00110011 23 | 00011101 24 | 01111000 25 | 00001010 26 | 11101100 27 | 00011000 28 | 10100011 29 | 01010100 30 | 01000110 31 | 10011000 32 | 00100101 33 | 00001111 34 | 01001000 35 | 01001100 36 | 00100001 37 | 00001000 38 | 00000000 39 | 10110011 40 | 00000000 41 | 11010001 42 | 11000000 43 | 10000001 44 | 10000000 45 | 10000001 46 | 11000000 47 | 10101001 48 | 11000000 49 | 00000001 50 | 00000001 51 | 00000001 52 | 00000001 53 | 00000001 54 | 00000001 55 | 00101111 56 | 00100110 57 | 01000000 58 | 10100000 59 | 01100000 60 | 10000100 61 | 00011010 62 | 00110000 63 | 00110000 64 | 00100000 65 | 00110101 66 | 00000000 67 | 00000000 68 | 10000100 69 | 01010011 70 | 00000000 71 | 00000000 72 | 00011010 73 | 00000000 74 | 00000000 75 | 00000000 76 | 11111100 77 | 00100000 78 | 01000100 79 | 01101001 80 | 01100111 81 | 01101001 82 | 01101100 83 | 01100101 84 | 01101110 85 | 01110100 86 | 01000100 87 | 01010110 88 | 01001001 89 | 00101101 90 | 00110001 91 | 00000000 92 | 00000000 93 | 00000000 94 | 00010000 95 | 00000000 96 | 00000000 97 | 00000000 98 | 00000000 99 | 00000000 100 | 00000000 101 | 00000000 102 | 00000000 103 | 00000000 104 | 00000000 105 | 00000000 106 | 00000000 107 | 00000000 108 | 00000000 109 | 00000000 110 | 00000000 111 | 00000000 112 | 00010000 113 | 00000000 114 | 00000000 115 | 00000000 116 | 00000000 117 | 00000000 118 | 00000000 119 | 00000000 120 | 00000000 121 | 00000000 122 | 00000000 123 | 00000000 124 | 00000000 125 | 00000000 126 | 00000000 127 | 00000000 128 | 00110001 129 | -------------------------------------------------------------------------------- /src/bd/hdmi_in/ip/hdmi_in_dvi2rgb_0_0/src/dvi2rgb.xdc: -------------------------------------------------------------------------------- 1 | ### Clock constraints ### 2 | # Constrain TMDS clock in the top-level project. Constraining it here, even if overridden in the top-level project 3 | # results in [DRC 23-20] Rule violation (PDRC-34) for the maximum MMCM VCO frequency. 4 | # create_clock -period 6.060 [get_ports TMDS_Clk_p] 5 | 6 | ### I/O constraints ### 7 | # group data channel IODELAYE2 cells with the IDELAYCTRL 8 | set_property IODELAY_GROUP dvi2rgb_iodelay_grp [get_cells DataDecoders[*].DecoderX/InputSERDES_X/InputDelay] 9 | set_property IODELAY_GROUP dvi2rgb_iodelay_grp [get_cells TMDS_ClockingX/IDelayCtrlX] 10 | 11 | ### Asynchronous clock domain crossings ### 12 | set_false_path -through [get_pins -filter {NAME =~ */SyncAsync*/oSyncStages*/PRE || NAME =~ */SyncAsync*/oSyncStages*/CLR} -hier] 13 | set_false_path -through [get_pins -filter {NAME =~ */SyncAsync*/oSyncStages_reg[0]/D} -hier] 14 | set_false_path -through [get_pins -filter {NAME =~ */SyncBase*/iIn_q*/PRE || NAME =~ */SyncBase*/iIn_q*/CLR} -hier] 15 | -------------------------------------------------------------------------------- /src/bd/hdmi_in/ip/hdmi_in_dvi2rgb_0_0/src/dvi2rgb_ooc.xdc: -------------------------------------------------------------------------------- 1 | create_clock -period 6.060 [get_ports TMDS_Clk_p] 2 | create_clock -period 5.000 [get_ports RefClk] -------------------------------------------------------------------------------- /src/bd/hdmi_in/ip/hdmi_in_m00_data_fifo_0/hdmi_in_m00_data_fifo_0_ooc.xdc: -------------------------------------------------------------------------------- 1 | # (c) Copyright 2012-2017 Xilinx, Inc. All rights reserved. 2 | # 3 | # This file contains confidential and proprietary information 4 | # of Xilinx, Inc. and is protected under U.S. and 5 | # international copyright and other intellectual property 6 | # laws. 7 | # 8 | # DISCLAIMER 9 | # This disclaimer is not a license and does not grant any 10 | # rights to the materials distributed herewith. Except as 11 | # otherwise provided in a valid license issued to you by 12 | # Xilinx, and to the maximum extent permitted by applicable 13 | # law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 14 | # WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 15 | # AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 16 | # BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 17 | # INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 18 | # (2) Xilinx shall not be liable (whether in contract or tort, 19 | # including negligence, or under any other theory of 20 | # liability) for any loss or damage of any kind or nature 21 | # related to, arising under or in connection with these 22 | # materials, including for any direct, or any indirect, 23 | # special, incidental, or consequential loss or damage 24 | # (including loss of data, profits, goodwill, or any type of 25 | # loss or damage suffered as a result of any action brought 26 | # by a third party) even if such damage or loss was 27 | # reasonably foreseeable or Xilinx had been advised of the 28 | # possibility of the same. 29 | # 30 | # CRITICAL APPLICATIONS 31 | # Xilinx products are not designed or intended to be fail- 32 | # safe, or for use in any application requiring fail-safe 33 | # performance, such as life-support or safety devices or 34 | # systems, Class III medical devices, nuclear facilities, 35 | # applications related to the deployment of airbags, or any 36 | # other applications that could lead to death, personal 37 | # injury, or severe property or environmental damage 38 | # (individually and collectively, "Critical 39 | # Applications"). Customer assumes the sole risk and 40 | # liability of any use of Xilinx products in Critical 41 | # Applications, subject only to applicable laws and 42 | # regulations governing limitations on product liability. 43 | # 44 | # THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 45 | # PART OF THIS FILE AT ALL TIMES. 46 | # 47 | # DO NOT MODIFY THIS FILE. 48 | # ######################################################### 49 | # 50 | # This XDC is used only in OOC mode for synthesis, implementation 51 | # 52 | # ######################################################### 53 | 54 | 55 | create_clock -period 7 -name aclk [get_ports aclk] 56 | 57 | 58 | -------------------------------------------------------------------------------- /src/bd/hdmi_in/ip/hdmi_in_m00_regslice_0/hdmi_in_m00_regslice_0_ooc.xdc: -------------------------------------------------------------------------------- 1 | # (c) Copyright 2012-2017 Xilinx, Inc. All rights reserved. 2 | # 3 | # This file contains confidential and proprietary information 4 | # of Xilinx, Inc. and is protected under U.S. and 5 | # international copyright and other intellectual property 6 | # laws. 7 | # 8 | # DISCLAIMER 9 | # This disclaimer is not a license and does not grant any 10 | # rights to the materials distributed herewith. Except as 11 | # otherwise provided in a valid license issued to you by 12 | # Xilinx, and to the maximum extent permitted by applicable 13 | # law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 14 | # WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 15 | # AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 16 | # BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 17 | # INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 18 | # (2) Xilinx shall not be liable (whether in contract or tort, 19 | # including negligence, or under any other theory of 20 | # liability) for any loss or damage of any kind or nature 21 | # related to, arising under or in connection with these 22 | # materials, including for any direct, or any indirect, 23 | # special, incidental, or consequential loss or damage 24 | # (including loss of data, profits, goodwill, or any type of 25 | # loss or damage suffered as a result of any action brought 26 | # by a third party) even if such damage or loss was 27 | # reasonably foreseeable or Xilinx had been advised of the 28 | # possibility of the same. 29 | # 30 | # CRITICAL APPLICATIONS 31 | # Xilinx products are not designed or intended to be fail- 32 | # safe, or for use in any application requiring fail-safe 33 | # performance, such as life-support or safety devices or 34 | # systems, Class III medical devices, nuclear facilities, 35 | # applications related to the deployment of airbags, or any 36 | # other applications that could lead to death, personal 37 | # injury, or severe property or environmental damage 38 | # (individually and collectively, "Critical 39 | # Applications"). Customer assumes the sole risk and 40 | # liability of any use of Xilinx products in Critical 41 | # Applications, subject only to applicable laws and 42 | # regulations governing limitations on product liability. 43 | # 44 | # THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 45 | # PART OF THIS FILE AT ALL TIMES. 46 | # 47 | # DO NOT MODIFY THIS FILE. 48 | # ######################################################### 49 | # 50 | # This XDC is used only in OOC mode for synthesis, implementation 51 | # 52 | # ######################################################### 53 | 54 | 55 | create_clock -period 7 -name aclk [get_ports aclk] 56 | 57 | 58 | -------------------------------------------------------------------------------- /src/bd/hdmi_in/ip/hdmi_in_proc_sys_reset_0_0/hdmi_in_proc_sys_reset_0_0.xdc: -------------------------------------------------------------------------------- 1 | 2 | # file: hdmi_in_proc_sys_reset_0_0.xdc 3 | # (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved. 4 | # 5 | # This file contains confidential and proprietary information 6 | # of Xilinx, Inc. and is protected under U.S. and 7 | # international copyright and other intellectual property 8 | # laws. 9 | # 10 | # DISCLAIMER 11 | # This disclaimer is not a license and does not grant any 12 | # rights to the materials distributed herewith. Except as 13 | # otherwise provided in a valid license issued to you by 14 | # Xilinx, and to the maximum extent permitted by applicable 15 | # law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 16 | # WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 17 | # AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 18 | # BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 19 | # INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 20 | # (2) Xilinx shall not be liable (whether in contract or tort, 21 | # including negligence, or under any other theory of 22 | # liability) for any loss or damage of any kind or nature 23 | # related to, arising under or in connection with these 24 | # materials, including for any direct, or any indirect, 25 | # special, incidental, or consequential loss or damage 26 | # (including loss of data, profits, goodwill, or any type of 27 | # loss or damage suffered as a result of any action brought 28 | # by a third party) even if such damage or loss was 29 | # reasonably foreseeable or Xilinx had been advised of the 30 | # possibility of the same. 31 | # 32 | # CRITICAL APPLICATIONS 33 | # Xilinx products are not designed or intended to be fail- 34 | # safe, or for use in any application requiring fail-safe 35 | # performance, such as life-support or safety devices or 36 | # systems, Class III medical devices, nuclear facilities, 37 | # applications related to the deployment of airbags, or any 38 | # other applications that could lead to death, personal 39 | # injury, or severe property or environmental damage 40 | # (individually and collectively, "Critical 41 | # Applications"). Customer assumes the sole risk and 42 | # liability of any use of Xilinx products in Critical 43 | # Applications, subject only to applicable laws and 44 | # regulations governing limitations on product liability. 45 | # 46 | # THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 47 | # PART OF THIS FILE AT ALL TIMES. 48 | 49 | set_false_path -to [get_pins -hier *cdc_to*/D] 50 | -------------------------------------------------------------------------------- /src/bd/hdmi_in/ip/hdmi_in_proc_sys_reset_0_0/hdmi_in_proc_sys_reset_0_0_board.xdc: -------------------------------------------------------------------------------- 1 | #--------------------Physical Constraints----------------- 2 | 3 | -------------------------------------------------------------------------------- /src/bd/hdmi_in/ip/hdmi_in_proc_sys_reset_0_0/hdmi_in_proc_sys_reset_0_0_ooc.xdc: -------------------------------------------------------------------------------- 1 | # (c) Copyright 2012-2017 Xilinx, Inc. All rights reserved. 2 | # 3 | # This file contains confidential and proprietary information 4 | # of Xilinx, Inc. and is protected under U.S. and 5 | # international copyright and other intellectual property 6 | # laws. 7 | # 8 | # DISCLAIMER 9 | # This disclaimer is not a license and does not grant any 10 | # rights to the materials distributed herewith. Except as 11 | # otherwise provided in a valid license issued to you by 12 | # Xilinx, and to the maximum extent permitted by applicable 13 | # law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 14 | # WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 15 | # AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 16 | # BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 17 | # INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 18 | # (2) Xilinx shall not be liable (whether in contract or tort, 19 | # including negligence, or under any other theory of 20 | # liability) for any loss or damage of any kind or nature 21 | # related to, arising under or in connection with these 22 | # materials, including for any direct, or any indirect, 23 | # special, incidental, or consequential loss or damage 24 | # (including loss of data, profits, goodwill, or any type of 25 | # loss or damage suffered as a result of any action brought 26 | # by a third party) even if such damage or loss was 27 | # reasonably foreseeable or Xilinx had been advised of the 28 | # possibility of the same. 29 | # 30 | # CRITICAL APPLICATIONS 31 | # Xilinx products are not designed or intended to be fail- 32 | # safe, or for use in any application requiring fail-safe 33 | # performance, such as life-support or safety devices or 34 | # systems, Class III medical devices, nuclear facilities, 35 | # applications related to the deployment of airbags, or any 36 | # other applications that could lead to death, personal 37 | # injury, or severe property or environmental damage 38 | # (individually and collectively, "Critical 39 | # Applications"). Customer assumes the sole risk and 40 | # liability of any use of Xilinx products in Critical 41 | # Applications, subject only to applicable laws and 42 | # regulations governing limitations on product liability. 43 | # 44 | # THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 45 | # PART OF THIS FILE AT ALL TIMES. 46 | # 47 | # DO NOT MODIFY THIS FILE. 48 | # ######################################################### 49 | # 50 | # This XDC is used only in OOC mode for synthesis, implementation 51 | # 52 | # ######################################################### 53 | 54 | 55 | create_clock -period 10 -name slowest_sync_clk [get_ports slowest_sync_clk] 56 | 57 | 58 | -------------------------------------------------------------------------------- /src/bd/hdmi_in/ip/hdmi_in_processing_system7_0_0/hdl/verilog/hdmi_in_processing_system7_0_0.hwdef: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Digilent/Zybo-hdmi-in/5f423ed8732a72c07d0ae40418ac6f44f4256f02/src/bd/hdmi_in/ip/hdmi_in_processing_system7_0_0/hdl/verilog/hdmi_in_processing_system7_0_0.hwdef -------------------------------------------------------------------------------- /src/bd/hdmi_in/ip/hdmi_in_processing_system7_0_0/ps7_init.h: -------------------------------------------------------------------------------- 1 | 2 | /****************************************************************************** 3 | * 4 | * (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved. 5 | * 6 | * Permission is hereby granted, free of charge, to any person obtaining a copy of this 7 | * software and associated documentation files (the "Software"), to deal in the Software 8 | * without restriction, including without limitation the rights to use, copy, modify, merge, 9 | * publish, distribute, sublicense, and/or sell copies of the Software, and to permit 10 | * persons to whom the Software is furnished to do so, subject to the following conditions: 11 | * 12 | * The above copyright notice and this permission notice shall be included in all copies or 13 | * substantial portions of the Software. 14 | * 15 | * Use of the Software is limited solely to applications: (a) running on a Xilinx device, or 16 | * (b) that interact with a Xilinx device through a bus or interconnect. 17 | * 18 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING 19 | * BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 20 | * NONINFRINGEMENT. IN NO EVENT SHALL THE X CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 22 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 23 | * 24 | * Except as contained in this notice, the name of the Xilinx shall not be used in advertising or 25 | * otherwise to promote the sale, use or other dealings in this Software without prior written 26 | * authorization from Xilinx. 27 | * 28 | *******************************************************************************/ 29 | /****************************************************************************/ 30 | /** 31 | * 32 | * @file ps7_init.h 33 | * 34 | * This file can be included in FSBL code 35 | * to get prototype of ps7_init() function 36 | * and error codes 37 | * 38 | *****************************************************************************/ 39 | 40 | #ifdef __cplusplus 41 | extern "C" { 42 | #endif 43 | 44 | 45 | //typedef unsigned int u32; 46 | 47 | 48 | /** do we need to make this name more unique ? **/ 49 | //extern u32 ps7_init_data[]; 50 | extern unsigned long * ps7_ddr_init_data; 51 | extern unsigned long * ps7_mio_init_data; 52 | extern unsigned long * ps7_pll_init_data; 53 | extern unsigned long * ps7_clock_init_data; 54 | extern unsigned long * ps7_peripherals_init_data; 55 | 56 | 57 | 58 | #define OPCODE_EXIT 0U 59 | #define OPCODE_CLEAR 1U 60 | #define OPCODE_WRITE 2U 61 | #define OPCODE_MASKWRITE 3U 62 | #define OPCODE_MASKPOLL 4U 63 | #define OPCODE_MASKDELAY 5U 64 | #define NEW_PS7_ERR_CODE 1 65 | 66 | /* Encode number of arguments in last nibble */ 67 | #define EMIT_EXIT() ( (OPCODE_EXIT << 4 ) | 0 ) 68 | #define EMIT_CLEAR(addr) ( (OPCODE_CLEAR << 4 ) | 1 ) , addr 69 | #define EMIT_WRITE(addr,val) ( (OPCODE_WRITE << 4 ) | 2 ) , addr, val 70 | #define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val 71 | #define EMIT_MASKPOLL(addr,mask) ( (OPCODE_MASKPOLL << 4 ) | 2 ) , addr, mask 72 | #define EMIT_MASKDELAY(addr,mask) ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask 73 | 74 | /* Returns codes of PS7_Init */ 75 | #define PS7_INIT_SUCCESS (0) // 0 is success in good old C 76 | #define PS7_INIT_CORRUPT (1) // 1 the data is corrupted, and slcr reg are in corrupted state now 77 | #define PS7_INIT_TIMEOUT (2) // 2 when a poll operation timed out 78 | #define PS7_POLL_FAILED_DDR_INIT (3) // 3 when a poll operation timed out for ddr init 79 | #define PS7_POLL_FAILED_DMA (4) // 4 when a poll operation timed out for dma done bit 80 | #define PS7_POLL_FAILED_PLL (5) // 5 when a poll operation timed out for pll sequence init 81 | 82 | 83 | /* Silicon Versions */ 84 | #define PCW_SILICON_VERSION_1 0 85 | #define PCW_SILICON_VERSION_2 1 86 | #define PCW_SILICON_VERSION_3 2 87 | 88 | /* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */ 89 | #define PS7_POST_CONFIG 90 | 91 | /* Freq of all peripherals */ 92 | 93 | #define APU_FREQ 650000000 94 | #define DDR_FREQ 525000000 95 | #define DCI_FREQ 10096154 96 | #define QSPI_FREQ 200000000 97 | #define SMC_FREQ 10000000 98 | #define ENET0_FREQ 125000000 99 | #define ENET1_FREQ 10000000 100 | #define USB0_FREQ 60000000 101 | #define USB1_FREQ 60000000 102 | #define SDIO_FREQ 50000000 103 | #define UART_FREQ 100000000 104 | #define SPI_FREQ 10000000 105 | #define I2C_FREQ 108333336 106 | #define WDT_FREQ 108333336 107 | #define TTC_FREQ 50000000 108 | #define CAN_FREQ 10000000 109 | #define PCAP_FREQ 200000000 110 | #define TPIU_FREQ 200000000 111 | #define FPGA0_FREQ 100000000 112 | #define FPGA1_FREQ 142857132 113 | #define FPGA2_FREQ 200000000 114 | #define FPGA3_FREQ 10000000 115 | 116 | 117 | /* For delay calculation using global registers*/ 118 | #define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200 119 | #define SCU_GLOBAL_TIMER_COUNT_U32 0xF8F00204 120 | #define SCU_GLOBAL_TIMER_CONTROL 0xF8F00208 121 | #define SCU_GLOBAL_TIMER_AUTO_INC 0xF8F00218 122 | 123 | int ps7_config( unsigned long*); 124 | int ps7_init(); 125 | int ps7_post_config(); 126 | int ps7_debug(); 127 | char* getPS7MessageInfo(unsigned key); 128 | 129 | void perf_start_clock(void); 130 | void perf_disable_clock(void); 131 | void perf_reset_clock(void); 132 | void perf_reset_and_start_timer(); 133 | int get_number_of_cycles_for_delay(unsigned int delay); 134 | #ifdef __cplusplus 135 | } 136 | #endif 137 | 138 | -------------------------------------------------------------------------------- /src/bd/hdmi_in/ip/hdmi_in_processing_system7_0_0/ps7_init_gpl.h: -------------------------------------------------------------------------------- 1 | 2 | /****************************************************************************** 3 | * 4 | * (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved. 5 | * 6 | * Permission is hereby granted, free of charge, to any person obtaining a copy of this 7 | * software and associated documentation files (the "Software"), to deal in the Software 8 | * without restriction, including without limitation the rights to use, copy, modify, merge, 9 | * publish, distribute, sublicense, and/or sell copies of the Software, and to permit 10 | * persons to whom the Software is furnished to do so, subject to the following conditions: 11 | * 12 | * The above copyright notice and this permission notice shall be included in all copies or 13 | * substantial portions of the Software. 14 | * 15 | * Use of the Software is limited solely to applications: (a) running on a Xilinx device, or 16 | * (b) that interact with a Xilinx device through a bus or interconnect. 17 | * 18 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING 19 | * BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 20 | * NONINFRINGEMENT. IN NO EVENT SHALL THE X CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 22 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 23 | * 24 | * Except as contained in this notice, the name of the Xilinx shall not be used in advertising or 25 | * otherwise to promote the sale, use or other dealings in this Software without prior written 26 | * authorization from Xilinx. 27 | * 28 | *******************************************************************************/ 29 | /****************************************************************************/ 30 | /** 31 | * 32 | * @file ps7_init.h 33 | * 34 | * This file can be included in FSBL code 35 | * to get prototype of ps7_init() function 36 | * and error codes 37 | * 38 | *****************************************************************************/ 39 | 40 | #ifdef __cplusplus 41 | extern "C" { 42 | #endif 43 | 44 | 45 | //typedef unsigned int u32; 46 | 47 | 48 | /** do we need to make this name more unique ? **/ 49 | //extern u32 ps7_init_data[]; 50 | extern unsigned long * ps7_ddr_init_data; 51 | extern unsigned long * ps7_mio_init_data; 52 | extern unsigned long * ps7_pll_init_data; 53 | extern unsigned long * ps7_clock_init_data; 54 | extern unsigned long * ps7_peripherals_init_data; 55 | 56 | 57 | 58 | #define OPCODE_EXIT 0U 59 | #define OPCODE_CLEAR 1U 60 | #define OPCODE_WRITE 2U 61 | #define OPCODE_MASKWRITE 3U 62 | #define OPCODE_MASKPOLL 4U 63 | #define OPCODE_MASKDELAY 5U 64 | #define NEW_PS7_ERR_CODE 1 65 | 66 | /* Encode number of arguments in last nibble */ 67 | #define EMIT_EXIT() ( (OPCODE_EXIT << 4 ) | 0 ) 68 | #define EMIT_CLEAR(addr) ( (OPCODE_CLEAR << 4 ) | 1 ) , addr 69 | #define EMIT_WRITE(addr,val) ( (OPCODE_WRITE << 4 ) | 2 ) , addr, val 70 | #define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val 71 | #define EMIT_MASKPOLL(addr,mask) ( (OPCODE_MASKPOLL << 4 ) | 2 ) , addr, mask 72 | #define EMIT_MASKDELAY(addr,mask) ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask 73 | 74 | /* Returns codes of PS7_Init */ 75 | #define PS7_INIT_SUCCESS (0) // 0 is success in good old C 76 | #define PS7_INIT_CORRUPT (1) // 1 the data is corrupted, and slcr reg are in corrupted state now 77 | #define PS7_INIT_TIMEOUT (2) // 2 when a poll operation timed out 78 | #define PS7_POLL_FAILED_DDR_INIT (3) // 3 when a poll operation timed out for ddr init 79 | #define PS7_POLL_FAILED_DMA (4) // 4 when a poll operation timed out for dma done bit 80 | #define PS7_POLL_FAILED_PLL (5) // 5 when a poll operation timed out for pll sequence init 81 | 82 | 83 | /* Silicon Versions */ 84 | #define PCW_SILICON_VERSION_1 0 85 | #define PCW_SILICON_VERSION_2 1 86 | #define PCW_SILICON_VERSION_3 2 87 | 88 | /* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */ 89 | #define PS7_POST_CONFIG 90 | 91 | /* Freq of all peripherals */ 92 | 93 | #define APU_FREQ 650000000 94 | #define DDR_FREQ 525000000 95 | #define DCI_FREQ 10096154 96 | #define QSPI_FREQ 200000000 97 | #define SMC_FREQ 10000000 98 | #define ENET0_FREQ 125000000 99 | #define ENET1_FREQ 10000000 100 | #define USB0_FREQ 60000000 101 | #define USB1_FREQ 60000000 102 | #define SDIO_FREQ 50000000 103 | #define UART_FREQ 100000000 104 | #define SPI_FREQ 10000000 105 | #define I2C_FREQ 108333336 106 | #define WDT_FREQ 108333336 107 | #define TTC_FREQ 50000000 108 | #define CAN_FREQ 10000000 109 | #define PCAP_FREQ 200000000 110 | #define TPIU_FREQ 200000000 111 | #define FPGA0_FREQ 100000000 112 | #define FPGA1_FREQ 142857132 113 | #define FPGA2_FREQ 200000000 114 | #define FPGA3_FREQ 10000000 115 | 116 | 117 | /* For delay calculation using global registers*/ 118 | #define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200 119 | #define SCU_GLOBAL_TIMER_COUNT_U32 0xF8F00204 120 | #define SCU_GLOBAL_TIMER_CONTROL 0xF8F00208 121 | #define SCU_GLOBAL_TIMER_AUTO_INC 0xF8F00218 122 | 123 | int ps7_config( unsigned long*); 124 | int ps7_init(); 125 | int ps7_post_config(); 126 | int ps7_debug(); 127 | char* getPS7MessageInfo(unsigned key); 128 | 129 | void perf_start_clock(void); 130 | void perf_disable_clock(void); 131 | void perf_reset_clock(void); 132 | void perf_reset_and_start_timer(); 133 | int get_number_of_cycles_for_delay(unsigned int delay); 134 | #ifdef __cplusplus 135 | } 136 | #endif 137 | 138 | -------------------------------------------------------------------------------- /src/bd/hdmi_in/ip/hdmi_in_processing_system7_0_0/sim/libps7.so: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Digilent/Zybo-hdmi-in/5f423ed8732a72c07d0ae40418ac6f44f4256f02/src/bd/hdmi_in/ip/hdmi_in_processing_system7_0_0/sim/libps7.so -------------------------------------------------------------------------------- /src/bd/hdmi_in/ip/hdmi_in_processing_system7_0_0/sim/libremoteport.so: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Digilent/Zybo-hdmi-in/5f423ed8732a72c07d0ae40418ac6f44f4256f02/src/bd/hdmi_in/ip/hdmi_in_processing_system7_0_0/sim/libremoteport.so -------------------------------------------------------------------------------- /src/bd/hdmi_in/ip/hdmi_in_rgb2vga_0_0/hdmi_in_rgb2vga_0_0.xci: -------------------------------------------------------------------------------- 1 | 2 | 3 | xilinx.com 4 | xci 5 | unknown 6 | 1.0 7 | 8 | 9 | hdmi_in_rgb2vga_0_0 10 | 11 | 12 | 13 | hdmi_in_axi_dynclk_0_0_PXL_CLK_O 14 | 100000000 15 | 0.000 16 | 24 17 | 5 18 | 6 19 | 5 20 | hdmi_in_rgb2vga_0_0 21 | 24 22 | 5 23 | 6 24 | 5 25 | zynq 26 | digilentinc.com:zybo:part0:1.0 27 | xc7z010 28 | clg400 29 | VHDL 30 | 31 | MIXED 32 | -1 33 | 34 | TRUE 35 | TRUE 36 | IP_Integrator 37 | 3 38 | TRUE 39 | . 40 | 41 | ../../ipshared 42 | 2016.4 43 | OUT_OF_CONTEXT 44 | 45 | 46 | 47 | 48 | 49 | 50 | 51 | 52 | 53 | 54 | 55 | 56 | -------------------------------------------------------------------------------- /src/bd/hdmi_in/ip/hdmi_in_rgb2vga_0_0/sim/hdmi_in_rgb2vga_0_0.vhd: -------------------------------------------------------------------------------- 1 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved. 2 | -- 3 | -- This file contains confidential and proprietary information 4 | -- of Xilinx, Inc. and is protected under U.S. and 5 | -- international copyright and other intellectual property 6 | -- laws. 7 | -- 8 | -- DISCLAIMER 9 | -- This disclaimer is not a license and does not grant any 10 | -- rights to the materials distributed herewith. Except as 11 | -- otherwise provided in a valid license issued to you by 12 | -- Xilinx, and to the maximum extent permitted by applicable 13 | -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 14 | -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 15 | -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 16 | -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 17 | -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 18 | -- (2) Xilinx shall not be liable (whether in contract or tort, 19 | -- including negligence, or under any other theory of 20 | -- liability) for any loss or damage of any kind or nature 21 | -- related to, arising under or in connection with these 22 | -- materials, including for any direct, or any indirect, 23 | -- special, incidental, or consequential loss or damage 24 | -- (including loss of data, profits, goodwill, or any type of 25 | -- loss or damage suffered as a result of any action brought 26 | -- by a third party) even if such damage or loss was 27 | -- reasonably foreseeable or Xilinx had been advised of the 28 | -- possibility of the same. 29 | -- 30 | -- CRITICAL APPLICATIONS 31 | -- Xilinx products are not designed or intended to be fail- 32 | -- safe, or for use in any application requiring fail-safe 33 | -- performance, such as life-support or safety devices or 34 | -- systems, Class III medical devices, nuclear facilities, 35 | -- applications related to the deployment of airbags, or any 36 | -- other applications that could lead to death, personal 37 | -- injury, or severe property or environmental damage 38 | -- (individually and collectively, "Critical 39 | -- Applications"). Customer assumes the sole risk and 40 | -- liability of any use of Xilinx products in Critical 41 | -- Applications, subject only to applicable laws and 42 | -- regulations governing limitations on product liability. 43 | -- 44 | -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 45 | -- PART OF THIS FILE AT ALL TIMES. 46 | -- 47 | -- DO NOT MODIFY THIS FILE. 48 | 49 | -- IP VLNV: digilentinc.com:ip:rgb2vga:1.0 50 | -- IP Revision: 3 51 | 52 | LIBRARY ieee; 53 | USE ieee.std_logic_1164.ALL; 54 | USE ieee.numeric_std.ALL; 55 | 56 | ENTITY hdmi_in_rgb2vga_0_0 IS 57 | PORT ( 58 | rgb_pData : IN STD_LOGIC_VECTOR(23 DOWNTO 0); 59 | rgb_pVDE : IN STD_LOGIC; 60 | rgb_pHSync : IN STD_LOGIC; 61 | rgb_pVSync : IN STD_LOGIC; 62 | PixelClk : IN STD_LOGIC; 63 | vga_pRed : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); 64 | vga_pGreen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); 65 | vga_pBlue : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); 66 | vga_pHSync : OUT STD_LOGIC; 67 | vga_pVSync : OUT STD_LOGIC 68 | ); 69 | END hdmi_in_rgb2vga_0_0; 70 | 71 | ARCHITECTURE hdmi_in_rgb2vga_0_0_arch OF hdmi_in_rgb2vga_0_0 IS 72 | ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING; 73 | ATTRIBUTE DowngradeIPIdentifiedWarnings OF hdmi_in_rgb2vga_0_0_arch: ARCHITECTURE IS "yes"; 74 | COMPONENT rgb2vga IS 75 | GENERIC ( 76 | VID_IN_DATA_WIDTH : INTEGER; 77 | kRedDepth : INTEGER; 78 | kGreenDepth : INTEGER; 79 | kBlueDepth : INTEGER 80 | ); 81 | PORT ( 82 | rgb_pData : IN STD_LOGIC_VECTOR(23 DOWNTO 0); 83 | rgb_pVDE : IN STD_LOGIC; 84 | rgb_pHSync : IN STD_LOGIC; 85 | rgb_pVSync : IN STD_LOGIC; 86 | PixelClk : IN STD_LOGIC; 87 | vga_pRed : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); 88 | vga_pGreen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); 89 | vga_pBlue : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); 90 | vga_pHSync : OUT STD_LOGIC; 91 | vga_pVSync : OUT STD_LOGIC 92 | ); 93 | END COMPONENT rgb2vga; 94 | ATTRIBUTE X_INTERFACE_INFO : STRING; 95 | ATTRIBUTE X_INTERFACE_INFO OF rgb_pData: SIGNAL IS "xilinx.com:interface:vid_io:1.0 vid_in DATA"; 96 | ATTRIBUTE X_INTERFACE_INFO OF rgb_pVDE: SIGNAL IS "xilinx.com:interface:vid_io:1.0 vid_in ACTIVE_VIDEO"; 97 | ATTRIBUTE X_INTERFACE_INFO OF rgb_pHSync: SIGNAL IS "xilinx.com:interface:vid_io:1.0 vid_in HSYNC"; 98 | ATTRIBUTE X_INTERFACE_INFO OF rgb_pVSync: SIGNAL IS "xilinx.com:interface:vid_io:1.0 vid_in VSYNC"; 99 | ATTRIBUTE X_INTERFACE_INFO OF PixelClk: SIGNAL IS "xilinx.com:signal:clock:1.0 signal_clock CLK"; 100 | BEGIN 101 | U0 : rgb2vga 102 | GENERIC MAP ( 103 | VID_IN_DATA_WIDTH => 24, 104 | kRedDepth => 5, 105 | kGreenDepth => 6, 106 | kBlueDepth => 5 107 | ) 108 | PORT MAP ( 109 | rgb_pData => rgb_pData, 110 | rgb_pVDE => rgb_pVDE, 111 | rgb_pHSync => rgb_pHSync, 112 | rgb_pVSync => rgb_pVSync, 113 | PixelClk => PixelClk, 114 | vga_pRed => vga_pRed, 115 | vga_pGreen => vga_pGreen, 116 | vga_pBlue => vga_pBlue, 117 | vga_pHSync => vga_pHSync, 118 | vga_pVSync => vga_pVSync 119 | ); 120 | END hdmi_in_rgb2vga_0_0_arch; 121 | -------------------------------------------------------------------------------- /src/bd/hdmi_in/ip/hdmi_in_rgb2vga_0_0/synth/hdmi_in_rgb2vga_0_0.vhd: -------------------------------------------------------------------------------- 1 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved. 2 | -- 3 | -- This file contains confidential and proprietary information 4 | -- of Xilinx, Inc. and is protected under U.S. and 5 | -- international copyright and other intellectual property 6 | -- laws. 7 | -- 8 | -- DISCLAIMER 9 | -- This disclaimer is not a license and does not grant any 10 | -- rights to the materials distributed herewith. Except as 11 | -- otherwise provided in a valid license issued to you by 12 | -- Xilinx, and to the maximum extent permitted by applicable 13 | -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 14 | -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 15 | -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 16 | -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 17 | -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 18 | -- (2) Xilinx shall not be liable (whether in contract or tort, 19 | -- including negligence, or under any other theory of 20 | -- liability) for any loss or damage of any kind or nature 21 | -- related to, arising under or in connection with these 22 | -- materials, including for any direct, or any indirect, 23 | -- special, incidental, or consequential loss or damage 24 | -- (including loss of data, profits, goodwill, or any type of 25 | -- loss or damage suffered as a result of any action brought 26 | -- by a third party) even if such damage or loss was 27 | -- reasonably foreseeable or Xilinx had been advised of the 28 | -- possibility of the same. 29 | -- 30 | -- CRITICAL APPLICATIONS 31 | -- Xilinx products are not designed or intended to be fail- 32 | -- safe, or for use in any application requiring fail-safe 33 | -- performance, such as life-support or safety devices or 34 | -- systems, Class III medical devices, nuclear facilities, 35 | -- applications related to the deployment of airbags, or any 36 | -- other applications that could lead to death, personal 37 | -- injury, or severe property or environmental damage 38 | -- (individually and collectively, "Critical 39 | -- Applications"). Customer assumes the sole risk and 40 | -- liability of any use of Xilinx products in Critical 41 | -- Applications, subject only to applicable laws and 42 | -- regulations governing limitations on product liability. 43 | -- 44 | -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 45 | -- PART OF THIS FILE AT ALL TIMES. 46 | -- 47 | -- DO NOT MODIFY THIS FILE. 48 | 49 | -- IP VLNV: digilentinc.com:ip:rgb2vga:1.0 50 | -- IP Revision: 3 51 | 52 | LIBRARY ieee; 53 | USE ieee.std_logic_1164.ALL; 54 | USE ieee.numeric_std.ALL; 55 | 56 | ENTITY hdmi_in_rgb2vga_0_0 IS 57 | PORT ( 58 | rgb_pData : IN STD_LOGIC_VECTOR(23 DOWNTO 0); 59 | rgb_pVDE : IN STD_LOGIC; 60 | rgb_pHSync : IN STD_LOGIC; 61 | rgb_pVSync : IN STD_LOGIC; 62 | PixelClk : IN STD_LOGIC; 63 | vga_pRed : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); 64 | vga_pGreen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); 65 | vga_pBlue : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); 66 | vga_pHSync : OUT STD_LOGIC; 67 | vga_pVSync : OUT STD_LOGIC 68 | ); 69 | END hdmi_in_rgb2vga_0_0; 70 | 71 | ARCHITECTURE hdmi_in_rgb2vga_0_0_arch OF hdmi_in_rgb2vga_0_0 IS 72 | ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING; 73 | ATTRIBUTE DowngradeIPIdentifiedWarnings OF hdmi_in_rgb2vga_0_0_arch: ARCHITECTURE IS "yes"; 74 | COMPONENT rgb2vga IS 75 | GENERIC ( 76 | VID_IN_DATA_WIDTH : INTEGER; 77 | kRedDepth : INTEGER; 78 | kGreenDepth : INTEGER; 79 | kBlueDepth : INTEGER 80 | ); 81 | PORT ( 82 | rgb_pData : IN STD_LOGIC_VECTOR(23 DOWNTO 0); 83 | rgb_pVDE : IN STD_LOGIC; 84 | rgb_pHSync : IN STD_LOGIC; 85 | rgb_pVSync : IN STD_LOGIC; 86 | PixelClk : IN STD_LOGIC; 87 | vga_pRed : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); 88 | vga_pGreen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); 89 | vga_pBlue : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); 90 | vga_pHSync : OUT STD_LOGIC; 91 | vga_pVSync : OUT STD_LOGIC 92 | ); 93 | END COMPONENT rgb2vga; 94 | ATTRIBUTE X_CORE_INFO : STRING; 95 | ATTRIBUTE X_CORE_INFO OF hdmi_in_rgb2vga_0_0_arch: ARCHITECTURE IS "rgb2vga,Vivado 2016.4"; 96 | ATTRIBUTE CHECK_LICENSE_TYPE : STRING; 97 | ATTRIBUTE CHECK_LICENSE_TYPE OF hdmi_in_rgb2vga_0_0_arch : ARCHITECTURE IS "hdmi_in_rgb2vga_0_0,rgb2vga,{}"; 98 | ATTRIBUTE X_INTERFACE_INFO : STRING; 99 | ATTRIBUTE X_INTERFACE_INFO OF rgb_pData: SIGNAL IS "xilinx.com:interface:vid_io:1.0 vid_in DATA"; 100 | ATTRIBUTE X_INTERFACE_INFO OF rgb_pVDE: SIGNAL IS "xilinx.com:interface:vid_io:1.0 vid_in ACTIVE_VIDEO"; 101 | ATTRIBUTE X_INTERFACE_INFO OF rgb_pHSync: SIGNAL IS "xilinx.com:interface:vid_io:1.0 vid_in HSYNC"; 102 | ATTRIBUTE X_INTERFACE_INFO OF rgb_pVSync: SIGNAL IS "xilinx.com:interface:vid_io:1.0 vid_in VSYNC"; 103 | ATTRIBUTE X_INTERFACE_INFO OF PixelClk: SIGNAL IS "xilinx.com:signal:clock:1.0 signal_clock CLK"; 104 | BEGIN 105 | U0 : rgb2vga 106 | GENERIC MAP ( 107 | VID_IN_DATA_WIDTH => 24, 108 | kRedDepth => 5, 109 | kGreenDepth => 6, 110 | kBlueDepth => 5 111 | ) 112 | PORT MAP ( 113 | rgb_pData => rgb_pData, 114 | rgb_pVDE => rgb_pVDE, 115 | rgb_pHSync => rgb_pHSync, 116 | rgb_pVSync => rgb_pVSync, 117 | PixelClk => PixelClk, 118 | vga_pRed => vga_pRed, 119 | vga_pGreen => vga_pGreen, 120 | vga_pBlue => vga_pBlue, 121 | vga_pHSync => vga_pHSync, 122 | vga_pVSync => vga_pVSync 123 | ); 124 | END hdmi_in_rgb2vga_0_0_arch; 125 | -------------------------------------------------------------------------------- /src/bd/hdmi_in/ip/hdmi_in_rst_processing_system7_0_100M_0/hdmi_in_rst_processing_system7_0_100M_0.xdc: -------------------------------------------------------------------------------- 1 | 2 | # file: hdmi_in_rst_processing_system7_0_100M_0.xdc 3 | # (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved. 4 | # 5 | # This file contains confidential and proprietary information 6 | # of Xilinx, Inc. and is protected under U.S. and 7 | # international copyright and other intellectual property 8 | # laws. 9 | # 10 | # DISCLAIMER 11 | # This disclaimer is not a license and does not grant any 12 | # rights to the materials distributed herewith. Except as 13 | # otherwise provided in a valid license issued to you by 14 | # Xilinx, and to the maximum extent permitted by applicable 15 | # law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 16 | # WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 17 | # AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 18 | # BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 19 | # INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 20 | # (2) Xilinx shall not be liable (whether in contract or tort, 21 | # including negligence, or under any other theory of 22 | # liability) for any loss or damage of any kind or nature 23 | # related to, arising under or in connection with these 24 | # materials, including for any direct, or any indirect, 25 | # special, incidental, or consequential loss or damage 26 | # (including loss of data, profits, goodwill, or any type of 27 | # loss or damage suffered as a result of any action brought 28 | # by a third party) even if such damage or loss was 29 | # reasonably foreseeable or Xilinx had been advised of the 30 | # possibility of the same. 31 | # 32 | # CRITICAL APPLICATIONS 33 | # Xilinx products are not designed or intended to be fail- 34 | # safe, or for use in any application requiring fail-safe 35 | # performance, such as life-support or safety devices or 36 | # systems, Class III medical devices, nuclear facilities, 37 | # applications related to the deployment of airbags, or any 38 | # other applications that could lead to death, personal 39 | # injury, or severe property or environmental damage 40 | # (individually and collectively, "Critical 41 | # Applications"). Customer assumes the sole risk and 42 | # liability of any use of Xilinx products in Critical 43 | # Applications, subject only to applicable laws and 44 | # regulations governing limitations on product liability. 45 | # 46 | # THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 47 | # PART OF THIS FILE AT ALL TIMES. 48 | 49 | set_false_path -to [get_pins -hier *cdc_to*/D] 50 | -------------------------------------------------------------------------------- /src/bd/hdmi_in/ip/hdmi_in_rst_processing_system7_0_100M_0/hdmi_in_rst_processing_system7_0_100M_0_board.xdc: -------------------------------------------------------------------------------- 1 | #--------------------Physical Constraints----------------- 2 | 3 | -------------------------------------------------------------------------------- /src/bd/hdmi_in/ip/hdmi_in_rst_processing_system7_0_100M_0/hdmi_in_rst_processing_system7_0_100M_0_ooc.xdc: -------------------------------------------------------------------------------- 1 | # (c) Copyright 2012-2017 Xilinx, Inc. All rights reserved. 2 | # 3 | # This file contains confidential and proprietary information 4 | # of Xilinx, Inc. and is protected under U.S. and 5 | # international copyright and other intellectual property 6 | # laws. 7 | # 8 | # DISCLAIMER 9 | # This disclaimer is not a license and does not grant any 10 | # rights to the materials distributed herewith. Except as 11 | # otherwise provided in a valid license issued to you by 12 | # Xilinx, and to the maximum extent permitted by applicable 13 | # law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 14 | # WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 15 | # AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 16 | # BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 17 | # INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 18 | # (2) Xilinx shall not be liable (whether in contract or tort, 19 | # including negligence, or under any other theory of 20 | # liability) for any loss or damage of any kind or nature 21 | # related to, arising under or in connection with these 22 | # materials, including for any direct, or any indirect, 23 | # special, incidental, or consequential loss or damage 24 | # (including loss of data, profits, goodwill, or any type of 25 | # loss or damage suffered as a result of any action brought 26 | # by a third party) even if such damage or loss was 27 | # reasonably foreseeable or Xilinx had been advised of the 28 | # possibility of the same. 29 | # 30 | # CRITICAL APPLICATIONS 31 | # Xilinx products are not designed or intended to be fail- 32 | # safe, or for use in any application requiring fail-safe 33 | # performance, such as life-support or safety devices or 34 | # systems, Class III medical devices, nuclear facilities, 35 | # applications related to the deployment of airbags, or any 36 | # other applications that could lead to death, personal 37 | # injury, or severe property or environmental damage 38 | # (individually and collectively, "Critical 39 | # Applications"). Customer assumes the sole risk and 40 | # liability of any use of Xilinx products in Critical 41 | # Applications, subject only to applicable laws and 42 | # regulations governing limitations on product liability. 43 | # 44 | # THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 45 | # PART OF THIS FILE AT ALL TIMES. 46 | # 47 | # DO NOT MODIFY THIS FILE. 48 | # ######################################################### 49 | # 50 | # This XDC is used only in OOC mode for synthesis, implementation 51 | # 52 | # ######################################################### 53 | 54 | 55 | create_clock -period 10 -name slowest_sync_clk [get_ports slowest_sync_clk] 56 | 57 | 58 | -------------------------------------------------------------------------------- /src/bd/hdmi_in/ip/hdmi_in_rst_processing_system7_0_150M_0/hdmi_in_rst_processing_system7_0_150M_0.xdc: -------------------------------------------------------------------------------- 1 | 2 | # file: hdmi_in_rst_processing_system7_0_150M_0.xdc 3 | # (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved. 4 | # 5 | # This file contains confidential and proprietary information 6 | # of Xilinx, Inc. and is protected under U.S. and 7 | # international copyright and other intellectual property 8 | # laws. 9 | # 10 | # DISCLAIMER 11 | # This disclaimer is not a license and does not grant any 12 | # rights to the materials distributed herewith. Except as 13 | # otherwise provided in a valid license issued to you by 14 | # Xilinx, and to the maximum extent permitted by applicable 15 | # law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 16 | # WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 17 | # AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 18 | # BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 19 | # INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 20 | # (2) Xilinx shall not be liable (whether in contract or tort, 21 | # including negligence, or under any other theory of 22 | # liability) for any loss or damage of any kind or nature 23 | # related to, arising under or in connection with these 24 | # materials, including for any direct, or any indirect, 25 | # special, incidental, or consequential loss or damage 26 | # (including loss of data, profits, goodwill, or any type of 27 | # loss or damage suffered as a result of any action brought 28 | # by a third party) even if such damage or loss was 29 | # reasonably foreseeable or Xilinx had been advised of the 30 | # possibility of the same. 31 | # 32 | # CRITICAL APPLICATIONS 33 | # Xilinx products are not designed or intended to be fail- 34 | # safe, or for use in any application requiring fail-safe 35 | # performance, such as life-support or safety devices or 36 | # systems, Class III medical devices, nuclear facilities, 37 | # applications related to the deployment of airbags, or any 38 | # other applications that could lead to death, personal 39 | # injury, or severe property or environmental damage 40 | # (individually and collectively, "Critical 41 | # Applications"). Customer assumes the sole risk and 42 | # liability of any use of Xilinx products in Critical 43 | # Applications, subject only to applicable laws and 44 | # regulations governing limitations on product liability. 45 | # 46 | # THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 47 | # PART OF THIS FILE AT ALL TIMES. 48 | 49 | set_false_path -to [get_pins -hier *cdc_to*/D] 50 | -------------------------------------------------------------------------------- /src/bd/hdmi_in/ip/hdmi_in_rst_processing_system7_0_150M_0/hdmi_in_rst_processing_system7_0_150M_0_board.xdc: -------------------------------------------------------------------------------- 1 | #--------------------Physical Constraints----------------- 2 | 3 | -------------------------------------------------------------------------------- /src/bd/hdmi_in/ip/hdmi_in_rst_processing_system7_0_150M_0/hdmi_in_rst_processing_system7_0_150M_0_ooc.xdc: -------------------------------------------------------------------------------- 1 | # (c) Copyright 2012-2017 Xilinx, Inc. All rights reserved. 2 | # 3 | # This file contains confidential and proprietary information 4 | # of Xilinx, Inc. and is protected under U.S. and 5 | # international copyright and other intellectual property 6 | # laws. 7 | # 8 | # DISCLAIMER 9 | # This disclaimer is not a license and does not grant any 10 | # rights to the materials distributed herewith. Except as 11 | # otherwise provided in a valid license issued to you by 12 | # Xilinx, and to the maximum extent permitted by applicable 13 | # law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 14 | # WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 15 | # AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 16 | # BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 17 | # INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 18 | # (2) Xilinx shall not be liable (whether in contract or tort, 19 | # including negligence, or under any other theory of 20 | # liability) for any loss or damage of any kind or nature 21 | # related to, arising under or in connection with these 22 | # materials, including for any direct, or any indirect, 23 | # special, incidental, or consequential loss or damage 24 | # (including loss of data, profits, goodwill, or any type of 25 | # loss or damage suffered as a result of any action brought 26 | # by a third party) even if such damage or loss was 27 | # reasonably foreseeable or Xilinx had been advised of the 28 | # possibility of the same. 29 | # 30 | # CRITICAL APPLICATIONS 31 | # Xilinx products are not designed or intended to be fail- 32 | # safe, or for use in any application requiring fail-safe 33 | # performance, such as life-support or safety devices or 34 | # systems, Class III medical devices, nuclear facilities, 35 | # applications related to the deployment of airbags, or any 36 | # other applications that could lead to death, personal 37 | # injury, or severe property or environmental damage 38 | # (individually and collectively, "Critical 39 | # Applications"). Customer assumes the sole risk and 40 | # liability of any use of Xilinx products in Critical 41 | # Applications, subject only to applicable laws and 42 | # regulations governing limitations on product liability. 43 | # 44 | # THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 45 | # PART OF THIS FILE AT ALL TIMES. 46 | # 47 | # DO NOT MODIFY THIS FILE. 48 | # ######################################################### 49 | # 50 | # This XDC is used only in OOC mode for synthesis, implementation 51 | # 52 | # ######################################################### 53 | 54 | 55 | create_clock -period 7 -name slowest_sync_clk [get_ports slowest_sync_clk] 56 | 57 | 58 | -------------------------------------------------------------------------------- /src/bd/hdmi_in/ip/hdmi_in_s00_regslice_0/hdmi_in_s00_regslice_0_ooc.xdc: -------------------------------------------------------------------------------- 1 | # (c) Copyright 2012-2017 Xilinx, Inc. All rights reserved. 2 | # 3 | # This file contains confidential and proprietary information 4 | # of Xilinx, Inc. and is protected under U.S. and 5 | # international copyright and other intellectual property 6 | # laws. 7 | # 8 | # DISCLAIMER 9 | # This disclaimer is not a license and does not grant any 10 | # rights to the materials distributed herewith. Except as 11 | # otherwise provided in a valid license issued to you by 12 | # Xilinx, and to the maximum extent permitted by applicable 13 | # law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 14 | # WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 15 | # AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 16 | # BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 17 | # INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 18 | # (2) Xilinx shall not be liable (whether in contract or tort, 19 | # including negligence, or under any other theory of 20 | # liability) for any loss or damage of any kind or nature 21 | # related to, arising under or in connection with these 22 | # materials, including for any direct, or any indirect, 23 | # special, incidental, or consequential loss or damage 24 | # (including loss of data, profits, goodwill, or any type of 25 | # loss or damage suffered as a result of any action brought 26 | # by a third party) even if such damage or loss was 27 | # reasonably foreseeable or Xilinx had been advised of the 28 | # possibility of the same. 29 | # 30 | # CRITICAL APPLICATIONS 31 | # Xilinx products are not designed or intended to be fail- 32 | # safe, or for use in any application requiring fail-safe 33 | # performance, such as life-support or safety devices or 34 | # systems, Class III medical devices, nuclear facilities, 35 | # applications related to the deployment of airbags, or any 36 | # other applications that could lead to death, personal 37 | # injury, or severe property or environmental damage 38 | # (individually and collectively, "Critical 39 | # Applications"). Customer assumes the sole risk and 40 | # liability of any use of Xilinx products in Critical 41 | # Applications, subject only to applicable laws and 42 | # regulations governing limitations on product liability. 43 | # 44 | # THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 45 | # PART OF THIS FILE AT ALL TIMES. 46 | # 47 | # DO NOT MODIFY THIS FILE. 48 | # ######################################################### 49 | # 50 | # This XDC is used only in OOC mode for synthesis, implementation 51 | # 52 | # ######################################################### 53 | 54 | 55 | create_clock -period 7 -name aclk [get_ports aclk] 56 | 57 | 58 | -------------------------------------------------------------------------------- /src/bd/hdmi_in/ip/hdmi_in_s01_regslice_0/hdmi_in_s01_regslice_0_ooc.xdc: -------------------------------------------------------------------------------- 1 | # (c) Copyright 2012-2017 Xilinx, Inc. All rights reserved. 2 | # 3 | # This file contains confidential and proprietary information 4 | # of Xilinx, Inc. and is protected under U.S. and 5 | # international copyright and other intellectual property 6 | # laws. 7 | # 8 | # DISCLAIMER 9 | # This disclaimer is not a license and does not grant any 10 | # rights to the materials distributed herewith. Except as 11 | # otherwise provided in a valid license issued to you by 12 | # Xilinx, and to the maximum extent permitted by applicable 13 | # law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 14 | # WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 15 | # AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 16 | # BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 17 | # INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 18 | # (2) Xilinx shall not be liable (whether in contract or tort, 19 | # including negligence, or under any other theory of 20 | # liability) for any loss or damage of any kind or nature 21 | # related to, arising under or in connection with these 22 | # materials, including for any direct, or any indirect, 23 | # special, incidental, or consequential loss or damage 24 | # (including loss of data, profits, goodwill, or any type of 25 | # loss or damage suffered as a result of any action brought 26 | # by a third party) even if such damage or loss was 27 | # reasonably foreseeable or Xilinx had been advised of the 28 | # possibility of the same. 29 | # 30 | # CRITICAL APPLICATIONS 31 | # Xilinx products are not designed or intended to be fail- 32 | # safe, or for use in any application requiring fail-safe 33 | # performance, such as life-support or safety devices or 34 | # systems, Class III medical devices, nuclear facilities, 35 | # applications related to the deployment of airbags, or any 36 | # other applications that could lead to death, personal 37 | # injury, or severe property or environmental damage 38 | # (individually and collectively, "Critical 39 | # Applications"). Customer assumes the sole risk and 40 | # liability of any use of Xilinx products in Critical 41 | # Applications, subject only to applicable laws and 42 | # regulations governing limitations on product liability. 43 | # 44 | # THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 45 | # PART OF THIS FILE AT ALL TIMES. 46 | # 47 | # DO NOT MODIFY THIS FILE. 48 | # ######################################################### 49 | # 50 | # This XDC is used only in OOC mode for synthesis, implementation 51 | # 52 | # ######################################################### 53 | 54 | 55 | create_clock -period 7 -name aclk [get_ports aclk] 56 | 57 | 58 | -------------------------------------------------------------------------------- /src/bd/hdmi_in/ip/hdmi_in_v_axi4s_vid_out_0_0/hdmi_in_v_axi4s_vid_out_0_0_clocks.xdc: -------------------------------------------------------------------------------- 1 | 2 | -------------------------------------------------------------------------------- /src/bd/hdmi_in/ip/hdmi_in_v_axi4s_vid_out_0_0/hdmi_in_v_axi4s_vid_out_0_0_ooc.xdc: -------------------------------------------------------------------------------- 1 | # (c) Copyright 2012-2017 Xilinx, Inc. All rights reserved. 2 | # 3 | # This file contains confidential and proprietary information 4 | # of Xilinx, Inc. and is protected under U.S. and 5 | # international copyright and other intellectual property 6 | # laws. 7 | # 8 | # DISCLAIMER 9 | # This disclaimer is not a license and does not grant any 10 | # rights to the materials distributed herewith. Except as 11 | # otherwise provided in a valid license issued to you by 12 | # Xilinx, and to the maximum extent permitted by applicable 13 | # law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 14 | # WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 15 | # AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 16 | # BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 17 | # INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 18 | # (2) Xilinx shall not be liable (whether in contract or tort, 19 | # including negligence, or under any other theory of 20 | # liability) for any loss or damage of any kind or nature 21 | # related to, arising under or in connection with these 22 | # materials, including for any direct, or any indirect, 23 | # special, incidental, or consequential loss or damage 24 | # (including loss of data, profits, goodwill, or any type of 25 | # loss or damage suffered as a result of any action brought 26 | # by a third party) even if such damage or loss was 27 | # reasonably foreseeable or Xilinx had been advised of the 28 | # possibility of the same. 29 | # 30 | # CRITICAL APPLICATIONS 31 | # Xilinx products are not designed or intended to be fail- 32 | # safe, or for use in any application requiring fail-safe 33 | # performance, such as life-support or safety devices or 34 | # systems, Class III medical devices, nuclear facilities, 35 | # applications related to the deployment of airbags, or any 36 | # other applications that could lead to death, personal 37 | # injury, or severe property or environmental damage 38 | # (individually and collectively, "Critical 39 | # Applications"). Customer assumes the sole risk and 40 | # liability of any use of Xilinx products in Critical 41 | # Applications, subject only to applicable laws and 42 | # regulations governing limitations on product liability. 43 | # 44 | # THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 45 | # PART OF THIS FILE AT ALL TIMES. 46 | # 47 | # DO NOT MODIFY THIS FILE. 48 | # ######################################################### 49 | # 50 | # This XDC is used only in OOC mode for synthesis, implementation 51 | # 52 | # ######################################################### 53 | 54 | 55 | create_clock -period 10 -name aclk [get_ports aclk] 56 | 57 | 58 | -------------------------------------------------------------------------------- /src/bd/hdmi_in/ip/hdmi_in_v_tc_0_0/hdmi_in_v_tc_0_0_clocks.xdc: -------------------------------------------------------------------------------- 1 | 2 | set video_clk [get_clocks -of [get_ports clk]] 3 | set axilite_clk [get_clocks -of [get_ports s_axi_aclk]] 4 | 5 | set_max_delay -from $video_clk -to [all_registers -clock $axilite_clk] -datapath_only [get_property -min PERIOD $video_clk] 6 | set_max_delay -from $axilite_clk -to [all_registers -clock $video_clk] -datapath_only [get_property -min PERIOD $axilite_clk] 7 | 8 | -------------------------------------------------------------------------------- /src/bd/hdmi_in/ip/hdmi_in_v_tc_0_0/hdmi_in_v_tc_0_0_ooc.xdc: -------------------------------------------------------------------------------- 1 | # (c) Copyright 2012-2017 Xilinx, Inc. All rights reserved. 2 | # 3 | # This file contains confidential and proprietary information 4 | # of Xilinx, Inc. and is protected under U.S. and 5 | # international copyright and other intellectual property 6 | # laws. 7 | # 8 | # DISCLAIMER 9 | # This disclaimer is not a license and does not grant any 10 | # rights to the materials distributed herewith. Except as 11 | # otherwise provided in a valid license issued to you by 12 | # Xilinx, and to the maximum extent permitted by applicable 13 | # law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 14 | # WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 15 | # AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 16 | # BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 17 | # INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 18 | # (2) Xilinx shall not be liable (whether in contract or tort, 19 | # including negligence, or under any other theory of 20 | # liability) for any loss or damage of any kind or nature 21 | # related to, arising under or in connection with these 22 | # materials, including for any direct, or any indirect, 23 | # special, incidental, or consequential loss or damage 24 | # (including loss of data, profits, goodwill, or any type of 25 | # loss or damage suffered as a result of any action brought 26 | # by a third party) even if such damage or loss was 27 | # reasonably foreseeable or Xilinx had been advised of the 28 | # possibility of the same. 29 | # 30 | # CRITICAL APPLICATIONS 31 | # Xilinx products are not designed or intended to be fail- 32 | # safe, or for use in any application requiring fail-safe 33 | # performance, such as life-support or safety devices or 34 | # systems, Class III medical devices, nuclear facilities, 35 | # applications related to the deployment of airbags, or any 36 | # other applications that could lead to death, personal 37 | # injury, or severe property or environmental damage 38 | # (individually and collectively, "Critical 39 | # Applications"). Customer assumes the sole risk and 40 | # liability of any use of Xilinx products in Critical 41 | # Applications, subject only to applicable laws and 42 | # regulations governing limitations on product liability. 43 | # 44 | # THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 45 | # PART OF THIS FILE AT ALL TIMES. 46 | # 47 | # DO NOT MODIFY THIS FILE. 48 | # ######################################################### 49 | # 50 | # This XDC is used only in OOC mode for synthesis, implementation 51 | # 52 | # ######################################################### 53 | 54 | 55 | create_clock -period 10 -name clk [get_ports clk] 56 | 57 | create_clock -period 10 -name s_axi_aclk [get_ports s_axi_aclk] 58 | 59 | 60 | -------------------------------------------------------------------------------- /src/bd/hdmi_in/ip/hdmi_in_v_tc_1_0/hdmi_in_v_tc_1_0_clocks.xdc: -------------------------------------------------------------------------------- 1 | 2 | set video_clk [get_clocks -of [get_ports clk]] 3 | set axilite_clk [get_clocks -of [get_ports s_axi_aclk]] 4 | 5 | set_max_delay -from $video_clk -to [all_registers -clock $axilite_clk] -datapath_only [get_property -min PERIOD $video_clk] 6 | set_max_delay -from $axilite_clk -to [all_registers -clock $video_clk] -datapath_only [get_property -min PERIOD $axilite_clk] 7 | 8 | -------------------------------------------------------------------------------- /src/bd/hdmi_in/ip/hdmi_in_v_tc_1_0/hdmi_in_v_tc_1_0_ooc.xdc: -------------------------------------------------------------------------------- 1 | # (c) Copyright 2012-2017 Xilinx, Inc. All rights reserved. 2 | # 3 | # This file contains confidential and proprietary information 4 | # of Xilinx, Inc. and is protected under U.S. and 5 | # international copyright and other intellectual property 6 | # laws. 7 | # 8 | # DISCLAIMER 9 | # This disclaimer is not a license and does not grant any 10 | # rights to the materials distributed herewith. Except as 11 | # otherwise provided in a valid license issued to you by 12 | # Xilinx, and to the maximum extent permitted by applicable 13 | # law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 14 | # WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 15 | # AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 16 | # BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 17 | # INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 18 | # (2) Xilinx shall not be liable (whether in contract or tort, 19 | # including negligence, or under any other theory of 20 | # liability) for any loss or damage of any kind or nature 21 | # related to, arising under or in connection with these 22 | # materials, including for any direct, or any indirect, 23 | # special, incidental, or consequential loss or damage 24 | # (including loss of data, profits, goodwill, or any type of 25 | # loss or damage suffered as a result of any action brought 26 | # by a third party) even if such damage or loss was 27 | # reasonably foreseeable or Xilinx had been advised of the 28 | # possibility of the same. 29 | # 30 | # CRITICAL APPLICATIONS 31 | # Xilinx products are not designed or intended to be fail- 32 | # safe, or for use in any application requiring fail-safe 33 | # performance, such as life-support or safety devices or 34 | # systems, Class III medical devices, nuclear facilities, 35 | # applications related to the deployment of airbags, or any 36 | # other applications that could lead to death, personal 37 | # injury, or severe property or environmental damage 38 | # (individually and collectively, "Critical 39 | # Applications"). Customer assumes the sole risk and 40 | # liability of any use of Xilinx products in Critical 41 | # Applications, subject only to applicable laws and 42 | # regulations governing limitations on product liability. 43 | # 44 | # THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 45 | # PART OF THIS FILE AT ALL TIMES. 46 | # 47 | # DO NOT MODIFY THIS FILE. 48 | # ######################################################### 49 | # 50 | # This XDC is used only in OOC mode for synthesis, implementation 51 | # 52 | # ######################################################### 53 | 54 | 55 | create_clock -period 10 -name clk [get_ports clk] 56 | 57 | create_clock -period 10 -name s_axi_aclk [get_ports s_axi_aclk] 58 | 59 | 60 | -------------------------------------------------------------------------------- /src/bd/hdmi_in/ip/hdmi_in_v_vid_in_axi4s_0_0/hdmi_in_v_vid_in_axi4s_0_0_clocks.xdc: -------------------------------------------------------------------------------- 1 | 2 | #------------------------------------------------------------------------------# 3 | # Native FIFO Constraints # 4 | #------------------------------------------------------------------------------# 5 | set fg_root {COUPLER_INST/FIFO_INST} 6 | set wr_clock [get_clocks -of_objects [get_ports vid_io_in_clk]] 7 | set rd_clock [get_clocks -of_objects [get_ports aclk]] 8 | 9 | # Set max delay on cross clock domain path for Block RAM based FIFO 10 | set_max_delay -from [get_cells ${fg_root}/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/*rd_pntr_gc_reg[*]] -to [get_cells ${fg_root}/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/*gsync_stage[*].wr_stg_inst/Q_reg_reg[*]] -datapath_only [get_property -min PERIOD $rd_clock] 11 | set_max_delay -from [get_cells ${fg_root}/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/*wr_pntr_gc_reg[*]] -to [get_cells ${fg_root}/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/*gsync_stage[*].rd_stg_inst/Q_reg_reg[*]] -datapath_only [get_property -min PERIOD $wr_clock] 12 | 13 | # Set false path on the reset synchronizers 14 | set_false_path -through [get_ports aresetn] -to [get_pins -hierarchical -filter {NAME =~ */COUPLER_INST/FIFO_INST/inst_fifo_gen/gconvfifo.rf/grf.rf/*rstblk*/*PRE*}] 15 | set_false_path -through [get_ports vid_io_in_reset] -to [get_pins -hierarchical -filter {NAME =~ */COUPLER_INST/FIFO_INST/inst_fifo_gen/gconvfifo.rf/grf.rf/*rstblk*/*PRE*}] 16 | set_false_path -from [get_cells -hierarchical -filter {NAME =~ */COUPLER_INST/FIFO_INST/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/*rst_reg_reg[*]}] 17 | 18 | -------------------------------------------------------------------------------- /src/bd/hdmi_in/ip/hdmi_in_v_vid_in_axi4s_0_0/hdmi_in_v_vid_in_axi4s_0_0_ooc.xdc: -------------------------------------------------------------------------------- 1 | # (c) Copyright 2012-2017 Xilinx, Inc. All rights reserved. 2 | # 3 | # This file contains confidential and proprietary information 4 | # of Xilinx, Inc. and is protected under U.S. and 5 | # international copyright and other intellectual property 6 | # laws. 7 | # 8 | # DISCLAIMER 9 | # This disclaimer is not a license and does not grant any 10 | # rights to the materials distributed herewith. Except as 11 | # otherwise provided in a valid license issued to you by 12 | # Xilinx, and to the maximum extent permitted by applicable 13 | # law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 14 | # WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 15 | # AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 16 | # BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 17 | # INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 18 | # (2) Xilinx shall not be liable (whether in contract or tort, 19 | # including negligence, or under any other theory of 20 | # liability) for any loss or damage of any kind or nature 21 | # related to, arising under or in connection with these 22 | # materials, including for any direct, or any indirect, 23 | # special, incidental, or consequential loss or damage 24 | # (including loss of data, profits, goodwill, or any type of 25 | # loss or damage suffered as a result of any action brought 26 | # by a third party) even if such damage or loss was 27 | # reasonably foreseeable or Xilinx had been advised of the 28 | # possibility of the same. 29 | # 30 | # CRITICAL APPLICATIONS 31 | # Xilinx products are not designed or intended to be fail- 32 | # safe, or for use in any application requiring fail-safe 33 | # performance, such as life-support or safety devices or 34 | # systems, Class III medical devices, nuclear facilities, 35 | # applications related to the deployment of airbags, or any 36 | # other applications that could lead to death, personal 37 | # injury, or severe property or environmental damage 38 | # (individually and collectively, "Critical 39 | # Applications"). Customer assumes the sole risk and 40 | # liability of any use of Xilinx products in Critical 41 | # Applications, subject only to applicable laws and 42 | # regulations governing limitations on product liability. 43 | # 44 | # THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 45 | # PART OF THIS FILE AT ALL TIMES. 46 | # 47 | # DO NOT MODIFY THIS FILE. 48 | # ######################################################### 49 | # 50 | # This XDC is used only in OOC mode for synthesis, implementation 51 | # 52 | # ######################################################### 53 | 54 | 55 | create_clock -period 10 -name vid_io_in_clk [get_ports vid_io_in_clk] 56 | 57 | create_clock -period 7 -name aclk [get_ports aclk] 58 | 59 | 60 | -------------------------------------------------------------------------------- /src/bd/hdmi_in/ip/hdmi_in_xbar_0/hdmi_in_xbar_0_ooc.xdc: -------------------------------------------------------------------------------- 1 | # (c) Copyright 2012-2017 Xilinx, Inc. All rights reserved. 2 | # 3 | # This file contains confidential and proprietary information 4 | # of Xilinx, Inc. and is protected under U.S. and 5 | # international copyright and other intellectual property 6 | # laws. 7 | # 8 | # DISCLAIMER 9 | # This disclaimer is not a license and does not grant any 10 | # rights to the materials distributed herewith. Except as 11 | # otherwise provided in a valid license issued to you by 12 | # Xilinx, and to the maximum extent permitted by applicable 13 | # law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 14 | # WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 15 | # AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 16 | # BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 17 | # INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 18 | # (2) Xilinx shall not be liable (whether in contract or tort, 19 | # including negligence, or under any other theory of 20 | # liability) for any loss or damage of any kind or nature 21 | # related to, arising under or in connection with these 22 | # materials, including for any direct, or any indirect, 23 | # special, incidental, or consequential loss or damage 24 | # (including loss of data, profits, goodwill, or any type of 25 | # loss or damage suffered as a result of any action brought 26 | # by a third party) even if such damage or loss was 27 | # reasonably foreseeable or Xilinx had been advised of the 28 | # possibility of the same. 29 | # 30 | # CRITICAL APPLICATIONS 31 | # Xilinx products are not designed or intended to be fail- 32 | # safe, or for use in any application requiring fail-safe 33 | # performance, such as life-support or safety devices or 34 | # systems, Class III medical devices, nuclear facilities, 35 | # applications related to the deployment of airbags, or any 36 | # other applications that could lead to death, personal 37 | # injury, or severe property or environmental damage 38 | # (individually and collectively, "Critical 39 | # Applications"). Customer assumes the sole risk and 40 | # liability of any use of Xilinx products in Critical 41 | # Applications, subject only to applicable laws and 42 | # regulations governing limitations on product liability. 43 | # 44 | # THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 45 | # PART OF THIS FILE AT ALL TIMES. 46 | # 47 | # DO NOT MODIFY THIS FILE. 48 | # ######################################################### 49 | # 50 | # This XDC is used only in OOC mode for synthesis, implementation 51 | # 52 | # ######################################################### 53 | 54 | 55 | create_clock -period 7 -name aclk [get_ports aclk] 56 | 57 | 58 | -------------------------------------------------------------------------------- /src/bd/hdmi_in/ip/hdmi_in_xbar_1/hdmi_in_xbar_1_ooc.xdc: -------------------------------------------------------------------------------- 1 | # (c) Copyright 2012-2017 Xilinx, Inc. All rights reserved. 2 | # 3 | # This file contains confidential and proprietary information 4 | # of Xilinx, Inc. and is protected under U.S. and 5 | # international copyright and other intellectual property 6 | # laws. 7 | # 8 | # DISCLAIMER 9 | # This disclaimer is not a license and does not grant any 10 | # rights to the materials distributed herewith. Except as 11 | # otherwise provided in a valid license issued to you by 12 | # Xilinx, and to the maximum extent permitted by applicable 13 | # law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 14 | # WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 15 | # AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 16 | # BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 17 | # INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 18 | # (2) Xilinx shall not be liable (whether in contract or tort, 19 | # including negligence, or under any other theory of 20 | # liability) for any loss or damage of any kind or nature 21 | # related to, arising under or in connection with these 22 | # materials, including for any direct, or any indirect, 23 | # special, incidental, or consequential loss or damage 24 | # (including loss of data, profits, goodwill, or any type of 25 | # loss or damage suffered as a result of any action brought 26 | # by a third party) even if such damage or loss was 27 | # reasonably foreseeable or Xilinx had been advised of the 28 | # possibility of the same. 29 | # 30 | # CRITICAL APPLICATIONS 31 | # Xilinx products are not designed or intended to be fail- 32 | # safe, or for use in any application requiring fail-safe 33 | # performance, such as life-support or safety devices or 34 | # systems, Class III medical devices, nuclear facilities, 35 | # applications related to the deployment of airbags, or any 36 | # other applications that could lead to death, personal 37 | # injury, or severe property or environmental damage 38 | # (individually and collectively, "Critical 39 | # Applications"). Customer assumes the sole risk and 40 | # liability of any use of Xilinx products in Critical 41 | # Applications, subject only to applicable laws and 42 | # regulations governing limitations on product liability. 43 | # 44 | # THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 45 | # PART OF THIS FILE AT ALL TIMES. 46 | # 47 | # DO NOT MODIFY THIS FILE. 48 | # ######################################################### 49 | # 50 | # This XDC is used only in OOC mode for synthesis, implementation 51 | # 52 | # ######################################################### 53 | 54 | 55 | create_clock -period 10 -name aclk [get_ports aclk] 56 | 57 | 58 | -------------------------------------------------------------------------------- /src/bd/hdmi_in/ip/hdmi_in_xlconstant_0_0/hdmi_in_xlconstant_0_0.xci: -------------------------------------------------------------------------------- 1 | 2 | 3 | xilinx.com 4 | xci 5 | unknown 6 | 1.0 7 | 8 | 9 | hdmi_in_xlconstant_0_0 10 | 11 | 12 | 0 13 | 1 14 | 0 15 | 1 16 | hdmi_in_xlconstant_0_0 17 | zynq 18 | digilentinc.com:zybo:part0:1.0 19 | xc7z010 20 | clg400 21 | VHDL 22 | 23 | MIXED 24 | -1 25 | 26 | TRUE 27 | TRUE 28 | IP_Integrator 29 | 2 30 | TRUE 31 | . 32 | 33 | ../../ipshared 34 | 2016.4 35 | OUT_OF_CONTEXT 36 | 37 | 38 | 39 | 40 | 41 | 42 | 43 | 44 | 45 | 46 | 47 | -------------------------------------------------------------------------------- /src/bd/hdmi_in/ip/hdmi_in_xlconstant_0_0/sim/hdmi_in_xlconstant_0_0.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------------------------- 2 | -- Company: 3 | -- Engineer: 4 | -- 5 | -- Create Date: 08/14/2014 12:18:30 PM 6 | -- Design Name: 7 | -- Module Name: tb_vhdl - Behavioral 8 | -- Project Name: 9 | -- Target Devices: 10 | -- Tool Versions: 11 | -- Description: 12 | -- 13 | -- Dependencies: 14 | -- 15 | -- Revision: 16 | -- Revision 0.01 - File Created 17 | -- Additional Comments: 18 | -- 19 | ---------------------------------------------------------------------------------- 20 | 21 | 22 | LIBRARY ieee; 23 | USE ieee.std_logic_1164.ALL; 24 | USE ieee.numeric_std.ALL; 25 | 26 | LIBRARY work; 27 | USE work.xlconstant; 28 | 29 | ENTITY hdmi_in_xlconstant_0_0 IS 30 | PORT ( 31 | dout : OUT STD_LOGIC_VECTOR(1-1 DOWNTO 0) 32 | ); 33 | END hdmi_in_xlconstant_0_0; 34 | 35 | ARCHITECTURE hdmi_in_xlconstant_0_0_arch OF hdmi_in_xlconstant_0_0 IS 36 | ATTRIBUTE DowngradeIPIdentifiedWarnings : string; 37 | ATTRIBUTE DowngradeIPIdentifiedWarnings OF hdmi_in_xlconstant_0_0_arch: ARCHITECTURE IS "yes"; 38 | 39 | COMPONENT xlconstant IS 40 | GENERIC ( 41 | CONST_VAL : STD_LOGIC_VECTOR(1-1 DOWNTO 0); 42 | CONST_WIDTH : INTEGER 43 | ); 44 | PORT ( 45 | dout : OUT STD_LOGIC_VECTOR(1-1 DOWNTO 0) 46 | ); 47 | END COMPONENT xlconstant; 48 | BEGIN 49 | U0 : xlconstant 50 | GENERIC MAP ( 51 | CONST_VAL => "0", 52 | CONST_WIDTH => 1 53 | ) 54 | PORT MAP ( 55 | dout => dout 56 | ); 57 | END hdmi_in_xlconstant_0_0_arch; 58 | -------------------------------------------------------------------------------- /src/bd/hdmi_in/ipshared/0ba0/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Digilent/Zybo-hdmi-in/5f423ed8732a72c07d0ae40418ac6f44f4256f02/src/bd/hdmi_in/ipshared/0ba0/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd -------------------------------------------------------------------------------- /src/bd/hdmi_in/ipshared/5ab6/hdl/lib_fifo_v1_0_rfs.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Digilent/Zybo-hdmi-in/5f423ed8732a72c07d0ae40418ac6f44f4256f02/src/bd/hdmi_in/ipshared/5ab6/hdl/lib_fifo_v1_0_rfs.vhd -------------------------------------------------------------------------------- /src/bd/hdmi_in/ipshared/6039/hdl/lib_srl_fifo_v1_0_rfs.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Digilent/Zybo-hdmi-in/5f423ed8732a72c07d0ae40418ac6f44f4256f02/src/bd/hdmi_in/ipshared/6039/hdl/lib_srl_fifo_v1_0_rfs.vhd -------------------------------------------------------------------------------- /src/bd/hdmi_in/ipshared/69dc/src/rgb2vga.vhd: -------------------------------------------------------------------------------- 1 | ------------------------------------------------------------------------------- 2 | -- 3 | -- File: rgb2vga.vhd 4 | -- Author: Elod Gyorgy 5 | -- Original Project: Genesys 2 demo project 6 | -- Date: 20 March 2015 7 | -- 8 | ------------------------------------------------------------------------------- 9 | -- (c) 2015 Copyright Digilent Incorporated 10 | -- All Rights Reserved 11 | -- 12 | -- This program is free software; distributed under the terms of BSD 3-clause 13 | -- license ("Revised BSD License", "New BSD License", or "Modified BSD License") 14 | -- 15 | -- Redistribution and use in source and binary forms, with or without modification, 16 | -- are permitted provided that the following conditions are met: 17 | -- 18 | -- 1. Redistributions of source code must retain the above copyright notice, this 19 | -- list of conditions and the following disclaimer. 20 | -- 2. Redistributions in binary form must reproduce the above copyright notice, 21 | -- this list of conditions and the following disclaimer in the documentation 22 | -- and/or other materials provided with the distribution. 23 | -- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names 24 | -- of its contributors may be used to endorse or promote products derived 25 | -- from this software without specific prior written permission. 26 | -- 27 | -- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 28 | -- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 29 | -- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 30 | -- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE 31 | -- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 32 | -- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 33 | -- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 34 | -- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 35 | -- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 36 | -- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 37 | -- 38 | ------------------------------------------------------------------------------- 39 | -- 40 | -- Purpose: 41 | -- To provide a properly blanked vga signal from an rgb interface 42 | -- 43 | ------------------------------------------------------------------------------- 44 | 45 | 46 | library IEEE; 47 | use IEEE.STD_LOGIC_1164.ALL; 48 | 49 | -- Uncomment the following library declaration if using 50 | -- arithmetic functions with Signed or Unsigned values 51 | --use IEEE.NUMERIC_STD.ALL; 52 | 53 | -- Uncomment the following library declaration if instantiating 54 | -- any Xilinx leaf cells in this code. 55 | --library UNISIM; 56 | --use UNISIM.VComponents.all; 57 | 58 | entity rgb2vga is 59 | Generic ( 60 | VID_IN_DATA_WIDTH : natural := 24; 61 | kRedDepth : natural := 5; 62 | kGreenDepth : natural := 6; 63 | kBlueDepth : natural := 5 64 | ); 65 | Port ( 66 | rgb_pData : in std_logic_vector(VID_IN_DATA_WIDTH-1 downto 0); 67 | rgb_pVDE : in std_logic; 68 | rgb_pHSync : in std_logic; 69 | rgb_pVSync : in std_logic; 70 | 71 | PixelClk : in std_logic; --pixel clock 72 | 73 | vga_pRed : out std_logic_vector(kRedDepth-1 downto 0); 74 | vga_pGreen : out std_logic_vector(kGreenDepth-1 downto 0); 75 | vga_pBlue : out std_logic_vector(kBlueDepth-1 downto 0); 76 | vga_pHSync : out std_logic; 77 | vga_pVSync : out std_logic 78 | ); 79 | end rgb2vga; 80 | 81 | architecture Behavioral of rgb2vga is 82 | signal int_pData : std_logic_vector(VID_IN_DATA_WIDTH-1 downto 0); 83 | 84 | begin 85 | 86 | Blanking: process(PixelClk) 87 | begin 88 | if Rising_Edge(PixelClk) then 89 | if (rgb_pVDE = '1') then 90 | int_pData <= rgb_pData; 91 | else 92 | int_pData <= (others => '0'); 93 | end if; 94 | 95 | vga_pHSync <= rgb_pHSync; 96 | vga_pVSync <= rgb_pVSync; 97 | end if; 98 | end process Blanking; 99 | 100 | vga_pRed <= int_pData(VID_IN_DATA_WIDTH-1 downto VID_IN_DATA_WIDTH - kRedDepth); 101 | vga_pBlue <= int_pData(VID_IN_DATA_WIDTH/3*2-1 downto VID_IN_DATA_WIDTH/3*2 - kBlueDepth); 102 | vga_pGreen <= int_pData(VID_IN_DATA_WIDTH/3-1 downto VID_IN_DATA_WIDTH/3 - kGreenDepth); 103 | 104 | 105 | end Behavioral; 106 | -------------------------------------------------------------------------------- /src/bd/hdmi_in/ipshared/7dd0/hdl/processing_system7_bfm_v2_0_5_axi_acp.v: -------------------------------------------------------------------------------- 1 | /***************************************************************************** 2 | * File : processing_system7_bfm_v2_0_5_axi_acp.v 3 | * 4 | * Date : 2012-11 5 | * 6 | * Description : Connections for ACP port 7 | * 8 | *****************************************************************************/ 9 | 10 | /* AXI Slave ACP */ 11 | processing_system7_bfm_v2_0_5_axi_slave #( C_USE_S_AXI_ACP, // enable 12 | axi_acp_name, // name 13 | axi_acp_data_width, // data width 14 | addr_width, /// address width 15 | axi_acp_id_width, // ID width 16 | C_S_AXI_ACP_BASEADDR, // slave base address 17 | C_S_AXI_ACP_HIGHADDR,// slave size 18 | axi_acp_outstanding, // outstanding transactions // 7 Reads and 3 Writes 19 | axi_slv_excl_support, // Exclusive access support 20 | axi_acp_wr_outstanding, 21 | axi_acp_rd_outstanding) 22 | S_AXI_ACP(.S_RESETN (net_axi_acp_rstn), 23 | .S_ACLK (S_AXI_ACP_ACLK), 24 | // Write Address Channel 25 | .S_AWID (S_AXI_ACP_AWID), 26 | .S_AWADDR (S_AXI_ACP_AWADDR), 27 | .S_AWLEN (S_AXI_ACP_AWLEN), 28 | .S_AWSIZE (S_AXI_ACP_AWSIZE), 29 | .S_AWBURST (S_AXI_ACP_AWBURST), 30 | .S_AWLOCK (S_AXI_ACP_AWLOCK), 31 | .S_AWCACHE (S_AXI_ACP_AWCACHE), 32 | .S_AWPROT (S_AXI_ACP_AWPROT), 33 | .S_AWVALID (S_AXI_ACP_AWVALID), 34 | .S_AWREADY (S_AXI_ACP_AWREADY), 35 | // Write Data Channel Signals. 36 | .S_WID (S_AXI_ACP_WID), 37 | .S_WDATA (S_AXI_ACP_WDATA), 38 | .S_WSTRB (S_AXI_ACP_WSTRB), 39 | .S_WLAST (S_AXI_ACP_WLAST), 40 | .S_WVALID (S_AXI_ACP_WVALID), 41 | .S_WREADY (S_AXI_ACP_WREADY), 42 | // Write Response Channel Signals. 43 | .S_BID (S_AXI_ACP_BID), 44 | .S_BRESP (S_AXI_ACP_BRESP), 45 | .S_BVALID (S_AXI_ACP_BVALID), 46 | .S_BREADY (S_AXI_ACP_BREADY), 47 | // Read Address Channel Signals. 48 | .S_ARID (S_AXI_ACP_ARID), 49 | .S_ARADDR (S_AXI_ACP_ARADDR), 50 | .S_ARLEN (S_AXI_ACP_ARLEN), 51 | .S_ARSIZE (S_AXI_ACP_ARSIZE), 52 | .S_ARBURST (S_AXI_ACP_ARBURST), 53 | .S_ARLOCK (S_AXI_ACP_ARLOCK), 54 | .S_ARCACHE (S_AXI_ACP_ARCACHE), 55 | .S_ARPROT (S_AXI_ACP_ARPROT), 56 | .S_ARVALID (S_AXI_ACP_ARVALID), 57 | .S_ARREADY (S_AXI_ACP_ARREADY), 58 | // Read Data Channel Signals. 59 | .S_RID (S_AXI_ACP_RID), 60 | .S_RDATA (S_AXI_ACP_RDATA), 61 | .S_RRESP (S_AXI_ACP_RRESP), 62 | .S_RLAST (S_AXI_ACP_RLAST), 63 | .S_RVALID (S_AXI_ACP_RVALID), 64 | .S_RREADY (S_AXI_ACP_RREADY), 65 | // Side band signals 66 | .S_AWQOS (S_AXI_ACP_AWQOS), 67 | .S_ARQOS (S_AXI_ACP_ARQOS), // Side band signals 68 | 69 | .SW_CLK (net_sw_clk), 70 | /* This goes to port 0 of DDR and port 0 of OCM , port 0 of REG*/ 71 | .WR_DATA_ACK_DDR (ddr_wr_ack_port0), 72 | .WR_DATA_ACK_OCM (ocm_wr_ack_port0), 73 | .WR_DATA (net_wr_data_acp), 74 | .WR_ADDR (net_wr_addr_acp), 75 | .WR_BYTES (net_wr_bytes_acp), 76 | .WR_DATA_VALID_DDR (ddr_wr_dv_port0), 77 | .WR_DATA_VALID_OCM (ocm_wr_dv_port0), 78 | .WR_QOS (net_wr_qos_acp), 79 | 80 | .RD_REQ_DDR (ddr_rd_req_port0), 81 | .RD_REQ_OCM (ocm_rd_req_port0), 82 | .RD_REQ_REG (reg_rd_req_port0), 83 | .RD_ADDR (net_rd_addr_acp), 84 | .RD_DATA_DDR (ddr_rd_data_port0), 85 | .RD_DATA_OCM (ocm_rd_data_port0), 86 | .RD_DATA_REG (reg_rd_data_port0), 87 | .RD_BYTES (net_rd_bytes_acp), 88 | .RD_DATA_VALID_DDR (ddr_rd_dv_port0), 89 | .RD_DATA_VALID_OCM (ocm_rd_dv_port0), 90 | .RD_DATA_VALID_REG (reg_rd_dv_port0), 91 | .RD_QOS (net_rd_qos_acp) 92 | 93 | ); 94 | -------------------------------------------------------------------------------- /src/bd/hdmi_in/ipshared/832a/hdl/lib_pkg_v1_0_rfs.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Digilent/Zybo-hdmi-in/5f423ed8732a72c07d0ae40418ac6f44f4256f02/src/bd/hdmi_in/ipshared/832a/hdl/lib_pkg_v1_0_rfs.vhd -------------------------------------------------------------------------------- /src/bd/hdmi_in/ipshared/d2d3/src/DVI_Constants.vhd: -------------------------------------------------------------------------------- 1 | ------------------------------------------------------------------------------- 2 | -- 3 | -- File: DVI_Constants.vhd 4 | -- Author: Elod Gyorgy 5 | -- Original Project: HDMI input on 7-series Xilinx FPGA 6 | -- Date: 8 October 2014 7 | -- 8 | ------------------------------------------------------------------------------- 9 | -- (c) 2014 Copyright Digilent Incorporated 10 | -- All Rights Reserved 11 | -- 12 | -- This program is free software; distributed under the terms of BSD 3-clause 13 | -- license ("Revised BSD License", "New BSD License", or "Modified BSD License") 14 | -- 15 | -- Redistribution and use in source and binary forms, with or without modification, 16 | -- are permitted provided that the following conditions are met: 17 | -- 18 | -- 1. Redistributions of source code must retain the above copyright notice, this 19 | -- list of conditions and the following disclaimer. 20 | -- 2. Redistributions in binary form must reproduce the above copyright notice, 21 | -- this list of conditions and the following disclaimer in the documentation 22 | -- and/or other materials provided with the distribution. 23 | -- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names 24 | -- of its contributors may be used to endorse or promote products derived 25 | -- from this software without specific prior written permission. 26 | -- 27 | -- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 28 | -- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 29 | -- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 30 | -- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE 31 | -- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 32 | -- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 33 | -- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 34 | -- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 35 | -- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 36 | -- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 37 | -- 38 | ------------------------------------------------------------------------------- 39 | -- 40 | -- Purpose: 41 | -- This package defines constants/parameters taken from the DVI specs. 42 | -- 43 | ------------------------------------------------------------------------------- 44 | 45 | library IEEE; 46 | use IEEE.STD_LOGIC_1164.ALL; 47 | 48 | -- Uncomment the following library declaration if using 49 | -- arithmetic functions with Signed or Unsigned values 50 | --use IEEE.NUMERIC_STD.ALL; 51 | 52 | -- Uncomment the following library declaration if instantiating 53 | -- any Xilinx leaf cells in this code. 54 | --library UNISIM; 55 | --use UNISIM.VComponents.all; 56 | 57 | package DVI_Constants is 58 | -- DVI Control Tokens 59 | constant kCtlTkn0 : std_logic_vector(9 downto 0) := "1101010100"; 60 | constant kCtlTkn1 : std_logic_vector(9 downto 0) := "0010101011"; 61 | constant kCtlTkn2 : std_logic_vector(9 downto 0) := "0101010100"; 62 | constant kCtlTkn3 : std_logic_vector(9 downto 0) := "1010101011"; 63 | 64 | constant kMinTknCntForBlank : natural := 128; --tB 65 | constant kBlankTimeoutMs : natural := 50; 66 | end DVI_Constants; 67 | 68 | package body DVI_Constants is 69 | end DVI_Constants; 70 | -------------------------------------------------------------------------------- /src/bd/hdmi_in/ipshared/d2d3/src/GlitchFilter.vhd: -------------------------------------------------------------------------------- 1 | ------------------------------------------------------------------------------- 2 | -- 3 | -- File: GlitchFilter.vhd 4 | -- Author: Elod Gyorgy 5 | -- Original Project: HDMI input on 7-series Xilinx FPGA 6 | -- Date: 22 October 2014 7 | -- 8 | ------------------------------------------------------------------------------- 9 | -- (c) 2014 Copyright Digilent Incorporated 10 | -- All Rights Reserved 11 | -- 12 | -- This program is free software; distributed under the terms of BSD 3-clause 13 | -- license ("Revised BSD License", "New BSD License", or "Modified BSD License") 14 | -- 15 | -- Redistribution and use in source and binary forms, with or without modification, 16 | -- are permitted provided that the following conditions are met: 17 | -- 18 | -- 1. Redistributions of source code must retain the above copyright notice, this 19 | -- list of conditions and the following disclaimer. 20 | -- 2. Redistributions in binary form must reproduce the above copyright notice, 21 | -- this list of conditions and the following disclaimer in the documentation 22 | -- and/or other materials provided with the distribution. 23 | -- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names 24 | -- of its contributors may be used to endorse or promote products derived 25 | -- from this software without specific prior written permission. 26 | -- 27 | -- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 28 | -- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 29 | -- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 30 | -- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE 31 | -- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 32 | -- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 33 | -- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 34 | -- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 35 | -- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 36 | -- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 37 | -- 38 | ------------------------------------------------------------------------------- 39 | -- 40 | -- Purpose: 41 | -- This module filters any pulses on sIn lasting less than the number of 42 | -- periods specified in kNoOfPeriodsToFilter. The output sOut will be 43 | -- delayed by kNoOfPeriodsToFilter cycles, but glitch-free. 44 | -- 45 | ------------------------------------------------------------------------------- 46 | 47 | library IEEE; 48 | use IEEE.STD_LOGIC_1164.ALL; 49 | 50 | -- Uncomment the following library declaration if using 51 | -- arithmetic functions with Signed or Unsigned values 52 | --use IEEE.NUMERIC_STD.ALL; 53 | 54 | -- Uncomment the following library declaration if instantiating 55 | -- any Xilinx leaf cells in this code. 56 | --library UNISIM; 57 | --use UNISIM.VComponents.all; 58 | 59 | entity GlitchFilter is 60 | Generic ( 61 | kNoOfPeriodsToFilter : natural); 62 | Port ( 63 | SampleClk : in STD_LOGIC; 64 | sIn : in STD_LOGIC; 65 | sOut : out STD_LOGIC; 66 | sRst : in STD_LOGIC); 67 | end GlitchFilter; 68 | 69 | architecture Behavioral of GlitchFilter is 70 | signal cntPeriods : natural range 0 to kNoOfPeriodsToFilter - 1 := kNoOfPeriodsToFilter - 1; 71 | signal sIn_q : std_logic; 72 | begin 73 | 74 | Bypass: if kNoOfPeriodsToFilter = 0 generate 75 | sOut <= sIn; 76 | end generate Bypass; 77 | 78 | Filter: if kNoOfPeriodsToFilter > 0 generate 79 | process (SampleClk) 80 | begin 81 | if Rising_Edge(SampleClk) then 82 | sIn_q <= sIn; 83 | if (cntPeriods = 0) then 84 | sOut <= sIn_q; 85 | end if; 86 | end if; 87 | end process; 88 | 89 | PeriodCounter: process (SampleClk) 90 | begin 91 | if Rising_Edge(SampleClk) then 92 | if (sIn_q /= sIn or sRst = '1') then --edge detected 93 | cntPeriods <= kNoOfPeriodsToFilter - 1; --reset counter 94 | elsif (cntPeriods /= 0) then 95 | cntPeriods <= cntPeriods - 1; --count down 96 | end if; 97 | end if; 98 | end process PeriodCounter; 99 | end generate Filter; 100 | 101 | end Behavioral; 102 | -------------------------------------------------------------------------------- /src/bd/hdmi_in/ipshared/d2d3/src/ResyncToBUFG.vhd: -------------------------------------------------------------------------------- 1 | ------------------------------------------------------------------------------- 2 | -- 3 | -- File: ResyncToBUFG.vhd 4 | -- Author: Elod Gyorgy 5 | -- Original Project: HDMI input on 7-series Xilinx FPGA 6 | -- Date: 7 July 2015 7 | -- 8 | ------------------------------------------------------------------------------- 9 | -- (c) 2015 Copyright Digilent Incorporated 10 | -- All Rights Reserved 11 | -- 12 | -- This program is free software; distributed under the terms of BSD 3-clause 13 | -- license ("Revised BSD License", "New BSD License", or "Modified BSD License") 14 | -- 15 | -- Redistribution and use in source and binary forms, with or without modification, 16 | -- are permitted provided that the following conditions are met: 17 | -- 18 | -- 1. Redistributions of source code must retain the above copyright notice, this 19 | -- list of conditions and the following disclaimer. 20 | -- 2. Redistributions in binary form must reproduce the above copyright notice, 21 | -- this list of conditions and the following disclaimer in the documentation 22 | -- and/or other materials provided with the distribution. 23 | -- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names 24 | -- of its contributors may be used to endorse or promote products derived 25 | -- from this software without specific prior written permission. 26 | -- 27 | -- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 28 | -- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 29 | -- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 30 | -- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE 31 | -- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 32 | -- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 33 | -- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 34 | -- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 35 | -- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 36 | -- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 37 | -- 38 | ------------------------------------------------------------------------------- 39 | -- 40 | -- Purpose: 41 | -- This module inserts a BUFG on the PixelClk path so that the pixel bus can be 42 | -- routed globally on the device. It also synchronizes data to the new BUFG 43 | -- clock. 44 | -- 45 | ------------------------------------------------------------------------------- 46 | 47 | 48 | 49 | library IEEE; 50 | use IEEE.STD_LOGIC_1164.ALL; 51 | 52 | -- Uncomment the following library declaration if using 53 | -- arithmetic functions with Signed or Unsigned values 54 | --use IEEE.NUMERIC_STD.ALL; 55 | 56 | -- Uncomment the following library declaration if instantiating 57 | -- any Xilinx leaf cells in this code. 58 | library UNISIM; 59 | use UNISIM.VComponents.all; 60 | 61 | entity ResyncToBUFG is 62 | Port ( 63 | -- Video in 64 | piData : in std_logic_vector(23 downto 0); 65 | piVDE : in std_logic; 66 | piHSync : in std_logic; 67 | piVSync : in std_logic; 68 | PixelClkIn : in std_logic; 69 | -- Video out 70 | poData : out std_logic_vector(23 downto 0); 71 | poVDE : out std_logic; 72 | poHSync : out std_logic; 73 | poVSync : out std_logic; 74 | PixelClkOut : out std_logic 75 | ); 76 | end ResyncToBUFG; 77 | 78 | architecture Behavioral of ResyncToBUFG is 79 | 80 | signal PixelClkInt : std_logic; 81 | 82 | begin 83 | -- Insert BUFG on clock path 84 | InstBUFG: BUFG 85 | port map ( 86 | O => PixelClkInt, -- 1-bit output: Clock output 87 | I => PixelClkIn -- 1-bit input: Clock input 88 | ); 89 | PixelClkOut <= PixelClkInt; 90 | 91 | -- Try simple registering 92 | RegisterData: process(PixelClkInt) 93 | begin 94 | if Rising_Edge(PixelClkInt) then 95 | poData <= piData; 96 | poVDE <= piVDE; 97 | poHSync <= piHSync; 98 | poVSync <= piVSync; 99 | end if; 100 | end process RegisterData; 101 | 102 | end Behavioral; 103 | -------------------------------------------------------------------------------- /src/bd/hdmi_in/ipshared/d2d3/src/SyncAsync.vhd: -------------------------------------------------------------------------------- 1 | ------------------------------------------------------------------------------- 2 | -- 3 | -- File: SyncAsync.vhd 4 | -- Author: Elod Gyorgy 5 | -- Original Project: HDMI input on 7-series Xilinx FPGA 6 | -- Date: 20 October 2014 7 | -- 8 | ------------------------------------------------------------------------------- 9 | -- (c) 2014 Copyright Digilent Incorporated 10 | -- All Rights Reserved 11 | -- 12 | -- This program is free software; distributed under the terms of BSD 3-clause 13 | -- license ("Revised BSD License", "New BSD License", or "Modified BSD License") 14 | -- 15 | -- Redistribution and use in source and binary forms, with or without modification, 16 | -- are permitted provided that the following conditions are met: 17 | -- 18 | -- 1. Redistributions of source code must retain the above copyright notice, this 19 | -- list of conditions and the following disclaimer. 20 | -- 2. Redistributions in binary form must reproduce the above copyright notice, 21 | -- this list of conditions and the following disclaimer in the documentation 22 | -- and/or other materials provided with the distribution. 23 | -- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names 24 | -- of its contributors may be used to endorse or promote products derived 25 | -- from this software without specific prior written permission. 26 | -- 27 | -- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 28 | -- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 29 | -- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 30 | -- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE 31 | -- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 32 | -- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 33 | -- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 34 | -- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 35 | -- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 36 | -- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 37 | -- 38 | ------------------------------------------------------------------------------- 39 | -- 40 | -- Purpose: 41 | -- This module synchronizes the asynchronous signal (aIn) with the OutClk clock 42 | -- domain and provides it on oOut. The number of FFs in the synchronizer chain 43 | -- can be configured with kStages. The reset value for oOut can be configured 44 | -- with kResetTo. The asynchronous reset (aReset) is always active-high. 45 | -- 46 | ------------------------------------------------------------------------------- 47 | 48 | 49 | library IEEE; 50 | use IEEE.STD_LOGIC_1164.ALL; 51 | 52 | -- Uncomment the following library declaration if using 53 | -- arithmetic functions with Signed or Unsigned values 54 | --use IEEE.NUMERIC_STD.ALL; 55 | 56 | -- Uncomment the following library declaration if instantiating 57 | -- any Xilinx leaf cells in this code. 58 | --library UNISIM; 59 | --use UNISIM.VComponents.all; 60 | 61 | entity SyncAsync is 62 | Generic ( 63 | kResetTo : std_logic := '0'; --value when reset and upon init 64 | kStages : natural := 2); --double sync by default 65 | Port ( 66 | aReset : in STD_LOGIC; -- active-high asynchronous reset 67 | aIn : in STD_LOGIC; 68 | OutClk : in STD_LOGIC; 69 | oOut : out STD_LOGIC); 70 | end SyncAsync; 71 | 72 | architecture Behavioral of SyncAsync is 73 | signal oSyncStages : std_logic_vector(kStages-1 downto 0) := (others => kResetTo); 74 | attribute ASYNC_REG : string; 75 | attribute ASYNC_REG of oSyncStages: signal is "TRUE"; 76 | begin 77 | 78 | Sync: process (OutClk, aReset) 79 | begin 80 | if (aReset = '1') then 81 | oSyncStages <= (others => kResetTo); 82 | elsif Rising_Edge(OutClk) then 83 | oSyncStages <= oSyncStages(oSyncStages'high-1 downto 0) & aIn; 84 | end if; 85 | end process Sync; 86 | oOut <= oSyncStages(oSyncStages'high); 87 | 88 | end Behavioral; 89 | -------------------------------------------------------------------------------- /src/bd/hdmi_in/ipshared/d2d3/src/SyncAsyncReset.vhd: -------------------------------------------------------------------------------- 1 | ------------------------------------------------------------------------------- 2 | -- 3 | -- File: SyncAsyncReset.vhd 4 | -- Author: Elod Gyorgy 5 | -- Original Project: HDMI input on 7-series Xilinx FPGA 6 | -- Date: 20 October 2014 7 | -- 8 | ------------------------------------------------------------------------------- 9 | -- (c) 2014 Copyright Digilent Incorporated 10 | -- All Rights Reserved 11 | -- 12 | -- This program is free software; distributed under the terms of BSD 3-clause 13 | -- license ("Revised BSD License", "New BSD License", or "Modified BSD License") 14 | -- 15 | -- Redistribution and use in source and binary forms, with or without modification, 16 | -- are permitted provided that the following conditions are met: 17 | -- 18 | -- 1. Redistributions of source code must retain the above copyright notice, this 19 | -- list of conditions and the following disclaimer. 20 | -- 2. Redistributions in binary form must reproduce the above copyright notice, 21 | -- this list of conditions and the following disclaimer in the documentation 22 | -- and/or other materials provided with the distribution. 23 | -- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names 24 | -- of its contributors may be used to endorse or promote products derived 25 | -- from this software without specific prior written permission. 26 | -- 27 | -- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 28 | -- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 29 | -- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 30 | -- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE 31 | -- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 32 | -- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 33 | -- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 34 | -- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 35 | -- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 36 | -- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 37 | -- 38 | ------------------------------------------------------------------------------- 39 | -- 40 | -- Purpose: 41 | -- This module is a reset-bridge. It takes a reset signal asynchronous to the 42 | -- target clock domain (OutClk) and provides a safe asynchronous or synchronous 43 | -- reset for the OutClk domain (oRst). The signal oRst is asserted immediately 44 | -- as aRst arrives, but is de-asserted synchronously with the OutClk rising 45 | -- edge. This means it can be used to safely reset any FF in the OutClk domain, 46 | -- respecting recovery time specs for FFs. 47 | -- 48 | ------------------------------------------------------------------------------- 49 | 50 | 51 | library IEEE; 52 | use IEEE.STD_LOGIC_1164.ALL; 53 | 54 | -- Uncomment the following library declaration if using 55 | -- arithmetic functions with Signed or Unsigned values 56 | --use IEEE.NUMERIC_STD.ALL; 57 | 58 | -- Uncomment the following library declaration if instantiating 59 | -- any Xilinx leaf cells in this code. 60 | --library UNISIM; 61 | --use UNISIM.VComponents.all; 62 | 63 | entity ResetBridge is 64 | Generic ( 65 | kPolarity : std_logic := '1'); 66 | Port ( 67 | aRst : in STD_LOGIC; -- asynchronous reset; active-high, if kPolarity=1 68 | OutClk : in STD_LOGIC; 69 | oRst : out STD_LOGIC); 70 | end ResetBridge; 71 | 72 | architecture Behavioral of ResetBridge is 73 | signal aRst_int : std_logic; 74 | attribute KEEP : string; 75 | attribute KEEP of aRst_int: signal is "TRUE"; 76 | begin 77 | 78 | aRst_int <= kPolarity xnor aRst; --SyncAsync uses active-high reset 79 | 80 | SyncAsyncx: entity work.SyncAsync 81 | generic map ( 82 | kResetTo => kPolarity, 83 | kStages => 2) --use double FF synchronizer 84 | port map ( 85 | aReset => aRst_int, 86 | aIn => not kPolarity, 87 | OutClk => OutClk, 88 | oOut => oRst); 89 | 90 | end Behavioral; 91 | -------------------------------------------------------------------------------- /src/bd/hdmi_in/ipshared/d2d3/src/SyncBase.vhd: -------------------------------------------------------------------------------- 1 | ------------------------------------------------------------------------------- 2 | -- 3 | -- File: SyncBase.vhd 4 | -- Author: Elod Gyorgy 5 | -- Original Project: HDMI input on 7-series Xilinx FPGA 6 | -- Date: 20 October 2014 7 | -- 8 | ------------------------------------------------------------------------------- 9 | -- (c) 2014 Copyright Digilent Incorporated 10 | -- All Rights Reserved 11 | -- 12 | -- This program is free software; distributed under the terms of BSD 3-clause 13 | -- license ("Revised BSD License", "New BSD License", or "Modified BSD License") 14 | -- 15 | -- Redistribution and use in source and binary forms, with or without modification, 16 | -- are permitted provided that the following conditions are met: 17 | -- 18 | -- 1. Redistributions of source code must retain the above copyright notice, this 19 | -- list of conditions and the following disclaimer. 20 | -- 2. Redistributions in binary form must reproduce the above copyright notice, 21 | -- this list of conditions and the following disclaimer in the documentation 22 | -- and/or other materials provided with the distribution. 23 | -- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names 24 | -- of its contributors may be used to endorse or promote products derived 25 | -- from this software without specific prior written permission. 26 | -- 27 | -- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 28 | -- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 29 | -- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 30 | -- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE 31 | -- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 32 | -- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 33 | -- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 34 | -- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 35 | -- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 36 | -- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 37 | -- 38 | ------------------------------------------------------------------------------- 39 | -- 40 | -- Purpose: 41 | -- This module synchronizes a signal (iIn) in one clock domain (InClk) with 42 | -- another clock domain (OutClk) and provides it on oOut. 43 | -- The number of FFs in the synchronizer chain 44 | -- can be configured with kStages. The reset value for oOut can be configured 45 | -- with kResetTo. The asynchronous reset (aReset) is always active-high. 46 | -- 47 | ------------------------------------------------------------------------------- 48 | 49 | 50 | library IEEE; 51 | use IEEE.STD_LOGIC_1164.ALL; 52 | 53 | -- Uncomment the following library declaration if using 54 | -- arithmetic functions with Signed or Unsigned values 55 | --use IEEE.NUMERIC_STD.ALL; 56 | 57 | -- Uncomment the following library declaration if instantiating 58 | -- any Xilinx leaf cells in this code. 59 | --library UNISIM; 60 | --use UNISIM.VComponents.all; 61 | 62 | entity SyncBase is 63 | Generic ( 64 | kResetTo : std_logic := '0'; --value when reset and upon init 65 | kStages : natural := 2); --double sync by default 66 | Port ( 67 | aReset : in STD_LOGIC; -- active-high asynchronous reset 68 | InClk : in std_logic; 69 | iIn : in STD_LOGIC; 70 | OutClk : in STD_LOGIC; 71 | oOut : out STD_LOGIC); 72 | end SyncBase; 73 | 74 | architecture Behavioral of SyncBase is 75 | 76 | signal iIn_q : std_logic; 77 | begin 78 | 79 | --By re-registering iIn on its own domain, we make sure iIn_q is glitch-free 80 | SyncSource: process(aReset, InClk) 81 | begin 82 | if (aReset = '1') then 83 | iIn_q <= kResetTo; 84 | elsif Rising_Edge(InClk) then 85 | iIn_q <= iIn; 86 | end if; 87 | end process SyncSource; 88 | 89 | --Crossing clock boundary here 90 | SyncAsyncx: entity work.SyncAsync 91 | generic map ( 92 | kResetTo => kResetTo, 93 | kStages => kStages) 94 | port map ( 95 | aReset => aReset, 96 | aIn => iIn_q, 97 | OutClk => OutClk, 98 | oOut => oOut); 99 | 100 | end Behavioral; 101 | -------------------------------------------------------------------------------- /src/bd/hdmi_in/ipshared/df1b/hdl/axi_protocol_converter_v2_1_vl_rfs.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Digilent/Zybo-hdmi-in/5f423ed8732a72c07d0ae40418ac6f44f4256f02/src/bd/hdmi_in/ipshared/df1b/hdl/axi_protocol_converter_v2_1_vl_rfs.v -------------------------------------------------------------------------------- /src/bd/hdmi_in/ipshared/e147/xlconstant.vhd: -------------------------------------------------------------------------------- 1 | ------------------------------------------------------------------------ 2 | -- 3 | -- Filename : xlconstant.vhd 4 | -- 5 | -- Date : 06/05/12 6 | -- 7 | -- Description : VHDL description of a constant block. This 8 | -- block does not use a core. 9 | -- 10 | ------------------------------------------------------------------------ 11 | 12 | 13 | ------------------------------------------------------------------------ 14 | -- 15 | -- Entity : xlconstant 16 | -- 17 | -- Architecture : behavior 18 | -- 19 | -- Description : Top level VHDL description of constant block 20 | -- 21 | ------------------------------------------------------------------------ 22 | 23 | library IEEE; 24 | use IEEE.std_logic_1164.all; 25 | use IEEE.numeric_std.all; 26 | 27 | entity xlconstant is 28 | generic ( 29 | CONST_VAL : std_logic_vector := "1"; -- Din lsb position to constant to 30 | CONST_WIDTH : integer := 1); -- Width of output 31 | port ( 32 | dout : out std_logic_vector (CONST_WIDTH-1 downto 0) 33 | ); 34 | end xlconstant; 35 | 36 | architecture behavioral of xlconstant is 37 | begin 38 | 39 | dout <= CONST_VAL; 40 | 41 | end behavioral; 42 | -------------------------------------------------------------------------------- /src/bd/hdmi_in/ui/bd_3e36a3ac.ui: -------------------------------------------------------------------------------- 1 | { 2 | DisplayTieOff: "1", 3 | guistr: "# # String gsaved with Nlview 6.6.5b 2016-09-06 bk=1.3687 VDI=39 GEI=35 GUI=JA:1.6 4 | # -string -flagsOSRD 5 | preplace port btns_4bits -pg 1 -y 320 -defaultsOSRD 6 | preplace port DDR -pg 1 -y 580 -defaultsOSRD 7 | preplace port TMDS -pg 1 -y 1220 -defaultsOSRD 8 | preplace port hdmi_hpd -pg 1 -y 1290 -defaultsOSRD 9 | preplace port vga_hs -pg 1 -y 1100 -defaultsOSRD 10 | preplace port sws_4bits -pg 1 -y 80 -defaultsOSRD 11 | preplace port leds_4bits -pg 1 -y 200 -defaultsOSRD 12 | preplace port IIC_0 -pg 1 -y 660 -defaultsOSRD 13 | preplace port FIXED_IO -pg 1 -y 640 -defaultsOSRD 14 | preplace port vga_vs -pg 1 -y 1120 -defaultsOSRD 15 | preplace port DDC -pg 1 -y 1210 -defaultsOSRD 16 | preplace portBus vga_b -pg 1 -y 1080 -defaultsOSRD 17 | preplace portBus vga_r -pg 1 -y 1040 -defaultsOSRD 18 | preplace portBus vga_g -pg 1 -y 1060 -defaultsOSRD 19 | preplace portBus HDMI_OEN -pg 1 -y 1160 -defaultsOSRD 20 | preplace inst v_axi4s_vid_out_0 -pg 1 -lvl 6 -y 310 -defaultsOSRD 21 | preplace inst v_tc_0 -pg 1 -lvl 5 -y 330 -defaultsOSRD 22 | preplace inst axi_vdma_0 -pg 1 -lvl 5 -y 720 -defaultsOSRD 23 | preplace inst v_tc_1 -pg 1 -lvl 3 -y 1010 -defaultsOSRD 24 | preplace inst rst_processing_system7_0_100M -pg 1 -lvl 1 -y 140 -defaultsOSRD 25 | preplace inst xlconstant_0 -pg 1 -lvl 7 -y 1210 -defaultsOSRD 26 | preplace inst axi_gpio_sw -pg 1 -lvl 7 -y 80 -defaultsOSRD 27 | preplace inst axi_gpio_btn -pg 1 -lvl 7 -y 320 -defaultsOSRD 28 | preplace inst proc_sys_reset_0 -pg 1 -lvl 2 -y 1120 -defaultsOSRD 29 | preplace inst axi_gpio_led -pg 1 -lvl 7 -y 200 -defaultsOSRD 30 | preplace inst xlconcat_0 -pg 1 -lvl 6 -y 960 -defaultsOSRD 31 | preplace inst axi_gpio_video -pg 1 -lvl 7 -y 1350 -defaultsOSRD 32 | preplace inst axi_dynclk_0 -pg 1 -lvl 4 -y 360 -defaultsOSRD 33 | preplace inst v_vid_in_axi4s_0 -pg 1 -lvl 2 -y 860 -defaultsOSRD 34 | preplace inst dvi2rgb_0 -pg 1 -lvl 1 -y 1320 -defaultsOSRD 35 | preplace inst axi_mem_intercon -pg 1 -lvl 6 -y 670 -defaultsOSRD 36 | preplace inst rst_processing_system7_0_150M -pg 1 -lvl 5 -y 1010 -defaultsOSRD 37 | preplace inst processing_system7_0_axi_periph -pg 1 -lvl 2 -y 250 -defaultsOSRD 38 | preplace inst processing_system7_0 -pg 1 -lvl 7 -y 690 -defaultsOSRD 39 | preplace inst rgb2vga_0 -pg 1 -lvl 7 -y 1080 -defaultsOSRD 40 | preplace netloc processing_system7_0_DDR 1 7 1 3060 41 | preplace netloc rgb2vga_0_vga_pRed 1 7 1 N 42 | preplace netloc v_vid_in_axi4s_0_video_out 1 2 3 NJ 820 NJ 820 1620J 43 | preplace netloc axi_vdma_0_s2mm_introut 1 5 1 2010 44 | preplace netloc axi_gpio_video_ip2intc_irpt 1 5 3 2100 1050 2530J 990 3040 45 | preplace netloc axi_dynclk_0_PXL_CLK_O 1 4 3 1630 200 2060 200 2480 46 | preplace netloc processing_system7_0_axi_periph_M03_AXI 1 2 3 NJ 240 NJ 240 1650J 47 | preplace netloc processing_system7_0_axi_periph_M00_AXI 1 2 5 N 180 NJ 180 NJ 180 2000J 150 2530J 48 | preplace netloc rgb2vga_0_vga_pGreen 1 7 1 N 49 | preplace netloc TMDS_1 1 0 1 0 50 | preplace netloc v_axi4s_vid_out_0_vid_io_out 1 6 1 2470 51 | preplace netloc processing_system7_0_axi_periph_M07_AXI 1 2 5 1050 1330 NJ 1330 NJ 1330 NJ 1330 NJ 52 | preplace netloc processing_system7_0_M_AXI_GP0 1 1 7 710 510 NJ 510 NJ 510 NJ 510 NJ 510 NJ 510 3040 53 | preplace netloc axi_vdma_0_M_AXI_MM2S 1 5 1 2070 54 | preplace netloc rst_processing_system7_0_150M_peripheral_aresetn 1 5 1 2090 55 | preplace netloc processing_system7_0_axi_periph_M05_AXI 1 2 3 N 280 NJ 280 1600J 56 | preplace netloc axi_vdma_0_M_AXIS_MM2S 1 5 1 2040 57 | preplace netloc v_tc_0_irq 1 5 1 2030 58 | preplace netloc processing_system7_0_FCLK_RESET0_N 1 0 8 20J 740 670J 740 1060J 870 NJ 870 1600J 870 NJ 870 NJ 870 3030 59 | preplace netloc axi_gpio_led_GPIO 1 7 1 N 60 | preplace netloc processing_system7_0_IIC_0 1 7 1 3050 61 | preplace netloc axi_mem_intercon_M00_AXI 1 6 1 N 62 | preplace netloc processing_system7_0_axi_periph_M02_AXI 1 2 5 1040 60 NJ 60 NJ 60 NJ 60 NJ 63 | preplace netloc v_tc_1_irq 1 3 3 N 1020 1630J 920 2000J 64 | preplace netloc rst_processing_system7_0_150M_interconnect_aresetn 1 5 1 2080 65 | preplace netloc rst_processing_system7_0_100M_peripheral_aresetn 1 0 7 10 530 680 1370 1080 1370 1350 1370 1610J 1370 NJ 1370 2500 66 | preplace netloc axi_gpio_0_GPIO1 1 7 1 N 67 | preplace netloc dvi2rgb_0_DDC 1 1 7 670 1260 NJ 1260 NJ 1260 NJ 1260 NJ 1260 NJ 1260 3060J 68 | preplace netloc processing_system7_0_axi_periph_M06_AXI 1 2 1 1090 69 | preplace netloc xlconstant_0_dout 1 7 1 3050 70 | preplace netloc xlconcat_0_dout 1 6 1 2490 71 | preplace netloc dvi2rgb_0_aPixelClkLckd 1 1 7 700J 1350 N 1350 NJ 1350 NJ 1350 NJ 1350 2470J 1430 3030 72 | preplace netloc axi_gpio_0_GPIO2 1 7 1 3060 73 | preplace netloc processing_system7_0_FIXED_IO 1 7 1 3060 74 | preplace netloc rgb2vga_0_vga_pVSync 1 7 1 N 75 | preplace netloc rgb2vga_0_vga_pHSync 1 7 1 N 76 | preplace netloc axi_vdma_0_mm2s_introut 1 5 1 2020 77 | preplace netloc axi_gpio_0_GPIO 1 7 1 N 78 | preplace netloc proc_sys_reset_0_peripheral_reset 1 1 2 710 990 1030 79 | preplace netloc proc_sys_reset_0_peripheral_aresetn 1 2 1 1060 80 | preplace netloc rst_processing_system7_0_100M_interconnect_aresetn 1 1 1 660 81 | preplace netloc processing_system7_0_FCLK_CLK0 1 0 8 10 520 670 520 1070 520 1340 520 1640J 520 2020J 180 2510 880 3060 82 | preplace netloc v_vid_in_axi4s_0_vtiming_out 1 2 1 1040 83 | preplace netloc v_tc_0_vtiming_out 1 5 1 2030 84 | preplace netloc axi_vdma_0_M_AXI_S2MM 1 5 1 2050 85 | preplace netloc processing_system7_0_FCLK_CLK1 1 1 7 700 710 NJ 710 NJ 710 1650J 600 2060 520 2530 520 3030 86 | preplace netloc processing_system7_0_axi_periph_M04_AXI 1 2 2 NJ 260 1340 87 | preplace netloc processing_system7_0_axi_periph_M01_AXI 1 2 5 1090J 160 NJ 160 NJ 160 NJ 160 2520 88 | preplace netloc dvi2rgb_0_RGB 1 1 1 660 89 | preplace netloc rgb2vga_0_vga_pBlue 1 7 1 N 90 | preplace netloc processing_system7_0_FCLK_CLK2 1 0 8 30J 730 NJ 730 1080J 860 NJ 860 NJ 860 NJ 860 NJ 860 3040 91 | preplace netloc dvi2rgb_0_PixelClk 1 1 2 690 1330 1040 92 | levelinfo -pg 1 -20 500 870 1230 1480 1840 2340 2817 3080 -top 0 -bot 1440 93 | ", 94 | } 95 | 0 -------------------------------------------------------------------------------- /src/constraints/.keep: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Digilent/Zybo-hdmi-in/5f423ed8732a72c07d0ae40418ac6f44f4256f02/src/constraints/.keep -------------------------------------------------------------------------------- /src/hdl/.keep: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Digilent/Zybo-hdmi-in/5f423ed8732a72c07d0ae40418ac6f44f4256f02/src/hdl/.keep -------------------------------------------------------------------------------- /src/ip/.keep: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Digilent/Zybo-hdmi-in/5f423ed8732a72c07d0ae40418ac6f44f4256f02/src/ip/.keep -------------------------------------------------------------------------------- /src/others/.keep: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Digilent/Zybo-hdmi-in/5f423ed8732a72c07d0ae40418ac6f44f4256f02/src/others/.keep --------------------------------------------------------------------------------