├── README.md ├── VLSI MINI PROJECT.docx └── Verilog Code ├── clock_gen.v ├── coeff_rom.v ├── coefficient.v ├── counter.v ├── fa.v ├── ha.v ├── jk_ff.v ├── main.v ├── multiplier.v ├── mux16_1.v ├── mux2_1.v ├── mux4_1.v ├── output_fir.txt ├── outputdata_signed.txt ├── romtesy.v └── test.v /README.md: -------------------------------------------------------------------------------- 1 | 8-Bit FIR Filter in Verilog using Pipelining 2 | -------------------------------------------------------------------------------- /VLSI MINI PROJECT.docx: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Divyansh03/FIR-Filter-in-Verilog/HEAD/VLSI MINI PROJECT.docx -------------------------------------------------------------------------------- /Verilog Code/clock_gen.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Divyansh03/FIR-Filter-in-Verilog/HEAD/Verilog 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