├── Debug ├── Drivers │ └── STM32F1xx_HAL_Driver │ │ └── Src │ │ ├── stm32f1xx_hal_tim.su │ │ ├── stm32f1xx_hal_tim_ex.su │ │ ├── stm32f1xx_hal_gpio_ex.su │ │ ├── stm32f1xx_hal_rcc_ex.su │ │ ├── stm32f1xx_hal_pcd_ex.su │ │ ├── stm32f1xx_hal_gpio.su │ │ ├── stm32f1xx_hal_dma.su │ │ ├── stm32f1xx_hal_flash.su │ │ ├── stm32f1xx_hal_rcc.su │ │ ├── stm32f1xx_hal_flash_ex.su │ │ ├── stm32f1xx_hal_pwr.su │ │ ├── stm32f1xx_hal.su │ │ ├── stm32f1xx_hal_cortex.su │ │ ├── stm32f1xx_ll_usb.su │ │ ├── stm32f1xx_hal_pcd.su │ │ └── stm32f1xx_hal_uart.su └── Middlewares │ └── ST │ └── STM32_USB_Device_Library │ ├── Core │ └── Src │ │ ├── usbd_ioreq.su │ │ ├── usbd_ctlreq.su │ │ └── usbd_core.su │ └── Class │ └── HID │ └── Src │ └── usbd_hid.su ├── app.apk ├── hid.cpp ├── mfwrap.dll ├── TouchInput.dll ├── rtcompress.dll ├── swresample-4.dll ├── Mai2Touchscreen.exe ├── Mai2Touchscreen.obj ├── Mai2Touchscreen.pdb ├── CMSIS ├── Device │ └── ST │ │ └── STM32F1xx │ │ └── Include │ │ ├── stm32f1xx.h │ │ ├── stm32f103xb.h │ │ └── system_stm32f1xx.h └── Include │ ├── cmsis_version.h │ ├── tz_context.h │ ├── cmsis_compiler.h │ ├── mpu_armv8.h │ ├── mpu_armv7.h │ ├── cmsis_armcc.h │ ├── cmsis_iccarm.h │ ├── core_cm0.h │ └── core_cm1.h ├── README.md ├── LICENSE └── touch.c /Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.su: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.su: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /app.apk: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Doviet18/Mai2TouchscreenHID/HEAD/app.apk -------------------------------------------------------------------------------- /hid.cpp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Doviet18/Mai2TouchscreenHID/HEAD/hid.cpp -------------------------------------------------------------------------------- /mfwrap.dll: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Doviet18/Mai2TouchscreenHID/HEAD/mfwrap.dll -------------------------------------------------------------------------------- /TouchInput.dll: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Doviet18/Mai2TouchscreenHID/HEAD/TouchInput.dll -------------------------------------------------------------------------------- /rtcompress.dll: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Doviet18/Mai2TouchscreenHID/HEAD/rtcompress.dll -------------------------------------------------------------------------------- /swresample-4.dll: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Doviet18/Mai2TouchscreenHID/HEAD/swresample-4.dll -------------------------------------------------------------------------------- /Mai2Touchscreen.exe: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Doviet18/Mai2TouchscreenHID/HEAD/Mai2Touchscreen.exe -------------------------------------------------------------------------------- /Mai2Touchscreen.obj: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Doviet18/Mai2TouchscreenHID/HEAD/Mai2Touchscreen.obj -------------------------------------------------------------------------------- /Mai2Touchscreen.pdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Doviet18/Mai2TouchscreenHID/HEAD/Mai2Touchscreen.pdb -------------------------------------------------------------------------------- /CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Doviet18/Mai2TouchscreenHID/HEAD/CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.h -------------------------------------------------------------------------------- /CMSIS/Device/ST/STM32F1xx/Include/stm32f103xb.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Doviet18/Mai2TouchscreenHID/HEAD/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xb.h -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # Mai2TouchscreenHID 2 | 让你Android设备变成Maimai的屏幕，上位机往PC端注册一个HID TouchScreen设备，下位机APP用于向上位机发送触屏信息。 3 | 用网络来进行通讯，没写COM或USB通讯（嫌麻烦），最好是RNDIS（有线连接到电脑共享网络） 4 | 性能好到能打红12+。 5 | * 你需要让手机时间和电脑时间以及中间路由设备的时间都同步，不然会有一些奇怪的延迟BUG 6 | 7 | -------------------------------------------------------------------------------- /Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.su: -------------------------------------------------------------------------------- 1 | stm32f1xx_hal_gpio_ex.c:81:6:HAL_GPIOEx_ConfigEventout 16 static 2 | stm32f1xx_hal_gpio_ex.c:95:6:HAL_GPIOEx_EnableEventout 4 static 3 | stm32f1xx_hal_gpio_ex.c:104:6:HAL_GPIOEx_DisableEventout 4 static 4 | -------------------------------------------------------------------------------- /Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.su: -------------------------------------------------------------------------------- 1 | stm32f1xx_hal_rcc_ex.c:100:19:HAL_RCCEx_PeriphCLKConfig 32 static 2 | stm32f1xx_hal_rcc_ex.c:294:6:HAL_RCCEx_GetPeriphCLKConfig 24 static 3 | stm32f1xx_hal_rcc_ex.c:387:10:HAL_RCCEx_GetPeriphCLKFreq 64 static 4 | -------------------------------------------------------------------------------- /Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pcd_ex.su: -------------------------------------------------------------------------------- 1 | stm32f1xx_hal_pcd_ex.c:138:20:HAL_PCDEx_PMAConfig 32 static 2 | stm32f1xx_hal_pcd_ex.c:183:13:HAL_PCDEx_SetConnectionState 16 static 3 | stm32f1xx_hal_pcd_ex.c:200:13:HAL_PCDEx_LPM_Callback 16 static 4 | stm32f1xx_hal_pcd_ex.c:217:13:HAL_PCDEx_BCD_Callback 16 static 5 | -------------------------------------------------------------------------------- /Debug/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.su: -------------------------------------------------------------------------------- 1 | usbd_ioreq.c:87:20:USBD_CtlSendData 24 static 2 | usbd_ioreq.c:109:20:USBD_CtlContinueSendData 24 static 3 | usbd_ioreq.c:126:20:USBD_CtlPrepareRx 24 static 4 | usbd_ioreq.c:148:20:USBD_CtlContinueRx 24 static 5 | usbd_ioreq.c:162:20:USBD_CtlSendStatus 16 static 6 | usbd_ioreq.c:179:20:USBD_CtlReceiveStatus 16 static 7 | usbd_ioreq.c:197:10:USBD_GetRxCount 16 static 8 | -------------------------------------------------------------------------------- /Debug/Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.su: -------------------------------------------------------------------------------- 1 | usbd_hid.c:487:17:USBD_HID_Init 24 static 2 | usbd_hid.c:518:17:USBD_HID_DeInit 16 static 3 | usbd_hid.c:542:17:USBD_HID_Setup 32 static 4 | usbd_hid.c:656:9:USBD_HID_SendReport 32 static 5 | usbd_hid.c:682:10:USBD_HID_GetPollingInterval 24 static 6 | usbd_hid.c:711:18:USBD_HID_GetCfgDesc 16 static 7 | usbd_hid.c:725:17:USBD_HID_DataIn 16 static 8 | usbd_hid.c:742:18:USBD_HID_GetDeviceQualifierDesc 16 static 9 | -------------------------------------------------------------------------------- /Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.su: -------------------------------------------------------------------------------- 1 | stm32f1xx_hal_gpio.c:178:6:HAL_GPIO_Init 48 static 2 | stm32f1xx_hal_gpio.c:351:6:HAL_GPIO_DeInit 40 static 3 | stm32f1xx_hal_gpio.c:431:15:HAL_GPIO_ReadPin 24 static 4 | stm32f1xx_hal_gpio.c:465:6:HAL_GPIO_WritePin 16 static 5 | stm32f1xx_hal_gpio.c:487:6:HAL_GPIO_TogglePin 16 static 6 | stm32f1xx_hal_gpio.c:512:19:HAL_GPIO_LockPin 24 static 7 | stm32f1xx_hal_gpio.c:547:6:HAL_GPIO_EXTI_IRQHandler 16 static 8 | stm32f1xx_hal_gpio.c:562:13:HAL_GPIO_EXTI_Callback 16 static 9 | -------------------------------------------------------------------------------- /Debug/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.su: -------------------------------------------------------------------------------- 1 | usbd_ctlreq.c:114:21:USBD_StdDevReq 24 static 2 | usbd_ctlreq.c:178:21:USBD_StdItfReq 24 static 3 | usbd_ctlreq.c:230:21:USBD_StdEPReq 24 static 4 | usbd_ctlreq.c:405:13:USBD_GetDescriptor 24 static 5 | usbd_ctlreq.c:595:13:USBD_SetAddress 24 static 6 | usbd_ctlreq.c:637:13:USBD_SetConfig 16 static 7 | usbd_ctlreq.c:712:13:USBD_GetConfig 16 static 8 | usbd_ctlreq.c:746:13:USBD_GetStatus 16 static 9 | usbd_ctlreq.c:787:13:USBD_SetFeature 16 static 10 | usbd_ctlreq.c:805:13:USBD_ClrFeature 16 static 11 | usbd_ctlreq.c:834:6:USBD_ParseSetupRequest 16 static 12 | usbd_ctlreq.c:852:6:USBD_CtlError 16 static 13 | usbd_ctlreq.c:868:6:USBD_GetString 32 static 14 | usbd_ctlreq.c:892:16:USBD_GetLen 24 static 15 | -------------------------------------------------------------------------------- /Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.su: -------------------------------------------------------------------------------- 1 | stm32f1xx_hal_dma.c:143:19:HAL_DMA_Init 24 static 2 | stm32f1xx_hal_dma.c:220:19:HAL_DMA_DeInit 16 static 3 | stm32f1xx_hal_dma.c:319:19:HAL_DMA_Start 32 static 4 | stm32f1xx_hal_dma.c:362:19:HAL_DMA_Start_IT 32 static 5 | stm32f1xx_hal_dma.c:416:19:HAL_DMA_Abort 24 static 6 | stm32f1xx_hal_dma.c:457:19:HAL_DMA_Abort_IT 24 static 7 | stm32f1xx_hal_dma.c:502:19:HAL_DMA_PollForTransfer 32 static 8 | stm32f1xx_hal_dma.c:603:6:HAL_DMA_IRQHandler 24 static 9 | stm32f1xx_hal_dma.c:693:19:HAL_DMA_RegisterCallback 32 static 10 | stm32f1xx_hal_dma.c:744:19:HAL_DMA_UnRegisterCallback 24 static 11 | stm32f1xx_hal_dma.c:820:22:HAL_DMA_GetState 16 static 12 | stm32f1xx_hal_dma.c:832:10:HAL_DMA_GetError 16 static 13 | stm32f1xx_hal_dma.c:858:13:DMA_SetConfig 24 static 14 | -------------------------------------------------------------------------------- /Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.su: -------------------------------------------------------------------------------- 1 | stm32f1xx_hal_flash.c:168:19:HAL_FLASH_Program 48 static 2 | stm32f1xx_hal_flash.c:267:19:HAL_FLASH_Program_IT 40 static 3 | stm32f1xx_hal_flash.c:332:6:HAL_FLASH_IRQHandler 24 static 4 | stm32f1xx_hal_flash.c:606:13:HAL_FLASH_EndOfOperationCallback 16 static 5 | stm32f1xx_hal_flash.c:624:13:HAL_FLASH_OperationErrorCallback 16 static 6 | stm32f1xx_hal_flash.c:657:19:HAL_FLASH_Unlock 16 static 7 | stm32f1xx_hal_flash.c:695:19:HAL_FLASH_Lock 4 static 8 | stm32f1xx_hal_flash.c:712:19:HAL_FLASH_OB_Unlock 4 static 9 | stm32f1xx_hal_flash.c:732:19:HAL_FLASH_OB_Lock 4 static 10 | stm32f1xx_hal_flash.c:745:6:HAL_FLASH_OB_Launch 8 static 11 | stm32f1xx_hal_flash.c:774:10:HAL_FLASH_GetError 4 static 12 | stm32f1xx_hal_flash.c:797:13:FLASH_Program_HalfWord 16 static 13 | stm32f1xx_hal_flash.c:826:19:FLASH_WaitForLastOperation 24 static 14 | stm32f1xx_hal_flash.c:914:13:FLASH_SetErrorCode 16 static 15 | -------------------------------------------------------------------------------- /Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.su: -------------------------------------------------------------------------------- 1 | stm32f1xx_hal_rcc.c:202:19:HAL_RCC_DeInit 16 static 2 | stm32f1xx_hal_rcc.c:347:19:HAL_RCC_OscConfig 32 static 3 | stm32f1xx_hal_rcc.c:813:19:HAL_RCC_ClockConfig 24 static 4 | stm32f1xx_hal_rcc.c:1002:6:HAL_RCC_MCOConfig 48 static 5 | stm32f1xx_hal_rcc.c:1039:6:HAL_RCC_EnableCSS 4 static 6 | stm32f1xx_hal_rcc.c:1048:6:HAL_RCC_DisableCSS 4 static 7 | stm32f1xx_hal_rcc.c:1082:10:HAL_RCC_GetSysClockFreq 48 static 8 | stm32f1xx_hal_rcc.c:1176:10:HAL_RCC_GetHCLKFreq 4 static 9 | stm32f1xx_hal_rcc.c:1187:10:HAL_RCC_GetPCLK1Freq 8 static 10 | stm32f1xx_hal_rcc.c:1199:10:HAL_RCC_GetPCLK2Freq 8 static 11 | stm32f1xx_hal_rcc.c:1212:6:HAL_RCC_GetOscConfig 16 static 12 | stm32f1xx_hal_rcc.c:1312:6:HAL_RCC_GetClockConfig 16 static 13 | stm32f1xx_hal_rcc.c:1347:6:HAL_RCC_NMI_IRQHandler 8 static 14 | stm32f1xx_hal_rcc.c:1365:13:RCC_Delay 24 static,ignoring_inline_asm 15 | stm32f1xx_hal_rcc.c:1379:13:HAL_RCC_CSSCallback 4 static 16 | -------------------------------------------------------------------------------- /Debug/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.su: -------------------------------------------------------------------------------- 1 | usbd_core.c:89:20:USBD_Init 24 static 2 | usbd_core.c:128:20:USBD_DeInit 16 static 3 | usbd_core.c:152:21:USBD_RegisterClass 24 static 4 | usbd_core.c:178:21:USBD_Start 16 static 5 | usbd_core.c:192:21:USBD_Stop 16 static 6 | usbd_core.c:209:21:USBD_RunTestMode 16 static 7 | usbd_core.c:225:20:USBD_SetClassConfig 24 static 8 | usbd_core.c:248:20:USBD_ClrClassConfig 16 static 9 | usbd_core.c:263:20:USBD_LL_SetupStage 16 static 10 | usbd_core.c:300:20:USBD_LL_DataOutStage 32 static 11 | usbd_core.c:361:20:USBD_LL_DataInStage 32 static 12 | usbd_core.c:442:20:USBD_LL_Reset 16 static 13 | usbd_core.c:476:20:USBD_LL_SetSpeed 16 static 14 | usbd_core.c:491:20:USBD_LL_Suspend 16 static 15 | usbd_core.c:506:20:USBD_LL_Resume 16 static 16 | usbd_core.c:523:20:USBD_LL_SOF 16 static 17 | usbd_core.c:542:20:USBD_LL_IsoINIncomplete 16 static 18 | usbd_core.c:558:20:USBD_LL_IsoOUTIncomplete 16 static 19 | usbd_core.c:574:20:USBD_LL_DevConnected 16 static 20 | usbd_core.c:588:20:USBD_LL_DevDisconnected 16 static 21 | -------------------------------------------------------------------------------- /Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.su: -------------------------------------------------------------------------------- 1 | stm32f1xx_hal_flash_ex.c:159:19:HAL_FLASHEx_Erase 24 static 2 | stm32f1xx_hal_flash_ex.c:319:19:HAL_FLASHEx_Erase_IT 24 static 3 | stm32f1xx_hal_flash_ex.c:397:19:HAL_FLASHEx_OBErase 16 static 4 | stm32f1xx_hal_flash_ex.c:446:19:HAL_FLASHEx_OBProgram 24 static 5 | stm32f1xx_hal_flash_ex.c:527:6:HAL_FLASHEx_OBGetConfig 16 static 6 | stm32f1xx_hal_flash_ex.c:549:10:HAL_FLASHEx_OBGetUserData 24 static 7 | stm32f1xx_hal_flash_ex.c:595:13:FLASH_MassErase 16 static 8 | stm32f1xx_hal_flash_ex.c:644:26:FLASH_OB_EnableWRP 32 static 9 | stm32f1xx_hal_flash_ex.c:767:26:FLASH_OB_DisableWRP 32 static 10 | stm32f1xx_hal_flash_ex.c:886:26:FLASH_OB_RDP_LevelConfig 24 static 11 | stm32f1xx_hal_flash_ex.c:937:26:FLASH_OB_UserConfig 24 static 12 | stm32f1xx_hal_flash_ex.c:988:26:FLASH_OB_ProgramData 24 static 13 | stm32f1xx_hal_flash_ex.c:1021:17:FLASH_OB_GetWRP 4 static 14 | stm32f1xx_hal_flash_ex.c:1034:17:FLASH_OB_GetRDP 16 static 15 | stm32f1xx_hal_flash_ex.c:1060:16:FLASH_OB_GetUser 4 static 16 | stm32f1xx_hal_flash_ex.c:1089:6:FLASH_PageErase 16 static 17 | -------------------------------------------------------------------------------- /Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.su: -------------------------------------------------------------------------------- 1 | stm32f1xx_hal_pwr.c:117:13:PWR_OverloadWfe 4 static,ignoring_inline_asm 2 | stm32f1xx_hal_pwr.c:156:6:HAL_PWR_DeInit 4 static 3 | stm32f1xx_hal_pwr.c:169:6:HAL_PWR_EnableBkUpAccess 4 static 4 | stm32f1xx_hal_pwr.c:182:6:HAL_PWR_DisableBkUpAccess 4 static 5 | stm32f1xx_hal_pwr.c:316:6:HAL_PWR_ConfigPVD 16 static 6 | stm32f1xx_hal_pwr.c:359:6:HAL_PWR_EnablePVD 4 static 7 | stm32f1xx_hal_pwr.c:369:6:HAL_PWR_DisablePVD 4 static 8 | stm32f1xx_hal_pwr.c:382:6:HAL_PWR_EnableWakeUpPin 24 static,ignoring_inline_asm 9 | stm32f1xx_hal_pwr.c:397:6:HAL_PWR_DisableWakeUpPin 24 static,ignoring_inline_asm 10 | stm32f1xx_hal_pwr.c:417:6:HAL_PWR_EnterSLEEPMode 16 static,ignoring_inline_asm 11 | stm32f1xx_hal_pwr.c:463:6:HAL_PWR_EnterSTOPMode 16 static,ignoring_inline_asm 12 | stm32f1xx_hal_pwr.c:503:6:HAL_PWR_EnterSTANDBYMode 4 static,ignoring_inline_asm 13 | stm32f1xx_hal_pwr.c:528:6:HAL_PWR_EnableSleepOnExit 4 static 14 | stm32f1xx_hal_pwr.c:541:6:HAL_PWR_DisableSleepOnExit 4 static 15 | stm32f1xx_hal_pwr.c:554:6:HAL_PWR_EnableSEVOnPend 4 static 16 | stm32f1xx_hal_pwr.c:567:6:HAL_PWR_DisableSEVOnPend 4 static 17 | stm32f1xx_hal_pwr.c:580:6:HAL_PWR_PVD_IRQHandler 8 static 18 | stm32f1xx_hal_pwr.c:597:13:HAL_PWR_PVDCallback 4 static 19 | -------------------------------------------------------------------------------- /Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.su: -------------------------------------------------------------------------------- 1 | stm32f1xx_hal.c:142:19:HAL_Init 8 static 2 | stm32f1xx_hal.c:175:19:HAL_DeInit 8 static 3 | stm32f1xx_hal.c:200:13:HAL_MspInit 4 static 4 | stm32f1xx_hal.c:211:13:HAL_MspDeInit 4 static 5 | stm32f1xx_hal.c:234:26:HAL_InitTick 16 static 6 | stm32f1xx_hal.c:293:13:HAL_IncTick 4 static 7 | stm32f1xx_hal.c:304:17:HAL_GetTick 4 static 8 | stm32f1xx_hal.c:313:10:HAL_GetTickPrio 4 static 9 | stm32f1xx_hal.c:322:19:HAL_SetTickFreq 24 static 10 | stm32f1xx_hal.c:344:21:HAL_GetTickFreq 4 static 11 | stm32f1xx_hal.c:360:13:HAL_Delay 24 static 12 | stm32f1xx_hal.c:386:13:HAL_SuspendTick 4 static 13 | stm32f1xx_hal.c:402:13:HAL_ResumeTick 4 static 14 | stm32f1xx_hal.c:412:10:HAL_GetHalVersion 4 static 15 | stm32f1xx_hal.c:428:10:HAL_GetREVID 4 static 16 | stm32f1xx_hal.c:444:10:HAL_GetDEVID 4 static 17 | stm32f1xx_hal.c:453:10:HAL_GetUIDw0 4 static 18 | stm32f1xx_hal.c:462:10:HAL_GetUIDw1 4 static 19 | stm32f1xx_hal.c:471:10:HAL_GetUIDw2 4 static 20 | stm32f1xx_hal.c:480:6:HAL_DBGMCU_EnableDBGSleepMode 4 static 21 | stm32f1xx_hal.c:496:6:HAL_DBGMCU_DisableDBGSleepMode 4 static 22 | stm32f1xx_hal.c:526:6:HAL_DBGMCU_EnableDBGStopMode 4 static 23 | stm32f1xx_hal.c:542:6:HAL_DBGMCU_DisableDBGStopMode 4 static 24 | stm32f1xx_hal.c:558:6:HAL_DBGMCU_EnableDBGStandbyMode 4 static 25 | stm32f1xx_hal.c:574:6:HAL_DBGMCU_DisableDBGStandbyMode 4 static 26 | -------------------------------------------------------------------------------- /LICENSE: -------------------------------------------------------------------------------- 1 | BSD 3-Clause License 2 | 3 | Copyright (c) 2023, 托司机 4 | 5 | Redistribution and use in source and binary forms, with or without 6 | modification, are permitted provided that the following conditions are met: 7 | 8 | 1. Redistributions of source code must retain the above copyright notice, this 9 | list of conditions and the following disclaimer. 10 | 11 | 2. Redistributions in binary form must reproduce the above copyright notice, 12 | this list of conditions and the following disclaimer in the documentation 13 | and/or other materials provided with the distribution. 14 | 15 | 3. Neither the name of the copyright holder nor the names of its 16 | contributors may be used to endorse or promote products derived from 17 | this software without specific prior written permission. 18 | 19 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 20 | AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 | IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 22 | DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 23 | FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 | DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 25 | SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 26 | CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 27 | OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 28 | OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 29 | -------------------------------------------------------------------------------- /Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.su: -------------------------------------------------------------------------------- 1 | core_cm3.h:1480:22:__NVIC_SetPriorityGrouping 24 static 2 | core_cm3.h:1499:26:__NVIC_GetPriorityGrouping 4 static 3 | core_cm3.h:1511:22:__NVIC_EnableIRQ 16 static 4 | core_cm3.h:1547:22:__NVIC_DisableIRQ 16 static,ignoring_inline_asm 5 | core_cm3.h:1566:26:__NVIC_GetPendingIRQ 16 static 6 | core_cm3.h:1585:22:__NVIC_SetPendingIRQ 16 static 7 | core_cm3.h:1600:22:__NVIC_ClearPendingIRQ 16 static 8 | core_cm3.h:1617:26:__NVIC_GetActive 16 static 9 | core_cm3.h:1639:22:__NVIC_SetPriority 16 static 10 | core_cm3.h:1661:26:__NVIC_GetPriority 16 static 11 | core_cm3.h:1686:26:NVIC_EncodePriority 40 static 12 | core_cm3.h:1713:22:NVIC_DecodePriority 40 static 13 | core_cm3.h:1762:34:__NVIC_SystemReset 4 static,ignoring_inline_asm 14 | core_cm3.h:1834:26:SysTick_Config 16 static 15 | stm32f1xx_hal_cortex.c:143:6:HAL_NVIC_SetPriorityGrouping 16 static 16 | stm32f1xx_hal_cortex.c:165:6:HAL_NVIC_SetPriority 32 static 17 | stm32f1xx_hal_cortex.c:187:6:HAL_NVIC_EnableIRQ 16 static 18 | stm32f1xx_hal_cortex.c:203:6:HAL_NVIC_DisableIRQ 16 static 19 | stm32f1xx_hal_cortex.c:216:6:HAL_NVIC_SystemReset 8 static 20 | stm32f1xx_hal_cortex.c:229:10:HAL_SYSTICK_Config 16 static 21 | stm32f1xx_hal_cortex.c:344:10:HAL_NVIC_GetPriorityGrouping 8 static 22 | stm32f1xx_hal_cortex.c:371:6:HAL_NVIC_GetPriority 24 static 23 | stm32f1xx_hal_cortex.c:386:6:HAL_NVIC_SetPendingIRQ 16 static 24 | stm32f1xx_hal_cortex.c:404:10:HAL_NVIC_GetPendingIRQ 16 static 25 | stm32f1xx_hal_cortex.c:420:6:HAL_NVIC_ClearPendingIRQ 16 static 26 | stm32f1xx_hal_cortex.c:437:10:HAL_NVIC_GetActive 16 static 27 | stm32f1xx_hal_cortex.c:454:6:HAL_SYSTICK_CLKSourceConfig 16 static 28 | stm32f1xx_hal_cortex.c:472:6:HAL_SYSTICK_IRQHandler 8 static 29 | stm32f1xx_hal_cortex.c:481:13:HAL_SYSTICK_Callback 4 static 30 | -------------------------------------------------------------------------------- /Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_usb.su: -------------------------------------------------------------------------------- 1 | stm32f1xx_ll_usb.c:1769:19:USB_CoreInit 16 static 2 | stm32f1xx_ll_usb.c:1789:19:USB_EnableGlobalInt 24 static 3 | stm32f1xx_ll_usb.c:1811:19:USB_DisableGlobalInt 24 static 4 | stm32f1xx_ll_usb.c:1835:19:USB_SetCurrentMode 16 static 5 | stm32f1xx_ll_usb.c:1856:19:USB_DevInit 16 static 6 | stm32f1xx_ll_usb.c:1887:19:USB_SetDevSpeed 16 static 7 | stm32f1xx_ll_usb.c:1909:19:USB_FlushTxFifo 16 static 8 | stm32f1xx_ll_usb.c:1928:19:USB_FlushRxFifo 16 static 9 | stm32f1xx_ll_usb.c:1947:19:USB_ActivateEndpoint 24 static 10 | stm32f1xx_ll_usb.c:2063:19:USB_DeactivateEndpoint 16 static 11 | stm32f1xx_ll_usb.c:2116:19:USB_EPStartXfer 64 static 12 | stm32f1xx_ll_usb.c:2204:19:USB_WritePacket 24 static 13 | stm32f1xx_ll_usb.c:2226:7:USB_ReadPacket 24 static 14 | stm32f1xx_ll_usb.c:2245:19:USB_EPSetStall 16 static 15 | stm32f1xx_ll_usb.c:2265:19:USB_EPClearStall 16 static 16 | stm32f1xx_ll_usb.c:2296:19:USB_StopDevice 16 static 17 | stm32f1xx_ll_usb.c:2317:20:USB_SetDevAddress 16 static 18 | stm32f1xx_ll_usb.c:2333:20:USB_DevConnect 16 static 19 | stm32f1xx_ll_usb.c:2350:20:USB_DevDisconnect 16 static 20 | stm32f1xx_ll_usb.c:2367:11:USB_ReadInterrupts 24 static 21 | stm32f1xx_ll_usb.c:2380:10:USB_ReadDevAllOutEpInterrupt 16 static 22 | stm32f1xx_ll_usb.c:2396:10:USB_ReadDevAllInEpInterrupt 16 static 23 | stm32f1xx_ll_usb.c:2414:10:USB_ReadDevOutEPInterrupt 16 static 24 | stm32f1xx_ll_usb.c:2433:10:USB_ReadDevInEPInterrupt 16 static 25 | stm32f1xx_ll_usb.c:2451:7:USB_ClearInterrupts 16 static 26 | stm32f1xx_ll_usb.c:2468:19:USB_EP0_OutStart 16 static 27 | stm32f1xx_ll_usb.c:2485:19:USB_ActivateRemoteWakeup 16 static 28 | stm32f1xx_ll_usb.c:2497:19:USB_DeActivateRemoteWakeup 16 static 29 | stm32f1xx_ll_usb.c:2511:6:USB_WritePMA 56 static 30 | stm32f1xx_ll_usb.c:2545:6:USB_ReadPMA 48 static 31 | -------------------------------------------------------------------------------- /CMSIS/Include/cmsis_version.h: -------------------------------------------------------------------------------- 1 | /**************************************************************************//** 2 | * @file cmsis_version.h 3 | * @brief CMSIS Core(M) Version definitions 4 | * @version V5.0.2 5 | * @date 19. April 2017 6 | ******************************************************************************/ 7 | /* 8 | * Copyright (c) 2009-2017 ARM Limited. All rights reserved. 9 | * 10 | * SPDX-License-Identifier: Apache-2.0 11 | * 12 | * Licensed under the Apache License, Version 2.0 (the License); you may 13 | * not use this file except in compliance with the License. 14 | * You may obtain a copy of the License at 15 | * 16 | * www.apache.org/licenses/LICENSE-2.0 17 | * 18 | * Unless required by applicable law or agreed to in writing, software 19 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT 20 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21 | * See the License for the specific language governing permissions and 22 | * limitations under the License. 23 | */ 24 | 25 | #if defined ( __ICCARM__ ) 26 | #pragma system_include /* treat file as system include file for MISRA check */ 27 | #elif defined (__clang__) 28 | #pragma clang system_header /* treat file as system include file */ 29 | #endif 30 | 31 | #ifndef __CMSIS_VERSION_H 32 | #define __CMSIS_VERSION_H 33 | 34 | /* CMSIS Version definitions */ 35 | #define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */ 36 | #define __CM_CMSIS_VERSION_SUB ( 1U) /*!< [15:0] CMSIS Core(M) sub version */ 37 | #define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \ 38 | __CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */ 39 | #endif 40 | -------------------------------------------------------------------------------- /Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pcd.su: -------------------------------------------------------------------------------- 1 | stm32f1xx_hal_pcd.c:126:19:HAL_PCD_Init 64 static 2 | stm32f1xx_hal_pcd.c:244:19:HAL_PCD_DeInit 16 static 3 | stm32f1xx_hal_pcd.c:280:13:HAL_PCD_MspInit 16 static 4 | stm32f1xx_hal_pcd.c:295:13:HAL_PCD_MspDeInit 16 static 5 | stm32f1xx_hal_pcd.c:845:19:HAL_PCD_Start 16 static 6 | stm32f1xx_hal_pcd.c:862:19:HAL_PCD_Stop 16 static 7 | stm32f1xx_hal_pcd.c:1215:6:HAL_PCD_IRQHandler 16 static 8 | stm32f1xx_hal_pcd.c:1309:13:HAL_PCD_DataOutStageCallback 16 static 9 | stm32f1xx_hal_pcd.c:1326:13:HAL_PCD_DataInStageCallback 16 static 10 | stm32f1xx_hal_pcd.c:1341:13:HAL_PCD_SetupStageCallback 16 static 11 | stm32f1xx_hal_pcd.c:1356:13:HAL_PCD_SOFCallback 16 static 12 | stm32f1xx_hal_pcd.c:1371:13:HAL_PCD_ResetCallback 16 static 13 | stm32f1xx_hal_pcd.c:1386:13:HAL_PCD_SuspendCallback 16 static 14 | stm32f1xx_hal_pcd.c:1401:13:HAL_PCD_ResumeCallback 16 static 15 | stm32f1xx_hal_pcd.c:1417:13:HAL_PCD_ISOOUTIncompleteCallback 16 static 16 | stm32f1xx_hal_pcd.c:1434:13:HAL_PCD_ISOINIncompleteCallback 16 static 17 | stm32f1xx_hal_pcd.c:1450:13:HAL_PCD_ConnectCallback 16 static 18 | stm32f1xx_hal_pcd.c:1465:13:HAL_PCD_DisconnectCallback 16 static 19 | stm32f1xx_hal_pcd.c:1499:19:HAL_PCD_DevConnect 16 static 20 | stm32f1xx_hal_pcd.c:1515:19:HAL_PCD_DevDisconnect 16 static 21 | stm32f1xx_hal_pcd.c:1532:19:HAL_PCD_SetAddress 16 static 22 | stm32f1xx_hal_pcd.c:1548:19:HAL_PCD_EP_Open 24 static 23 | stm32f1xx_hal_pcd.c:1592:19:HAL_PCD_EP_Close 24 static 24 | stm32f1xx_hal_pcd.c:1623:19:HAL_PCD_EP_Receive 32 static 25 | stm32f1xx_hal_pcd.c:1654:10:HAL_PCD_EP_GetRxCount 16 static 26 | stm32f1xx_hal_pcd.c:1666:19:HAL_PCD_EP_Transmit 32 static 27 | stm32f1xx_hal_pcd.c:1697:19:HAL_PCD_EP_SetStall 24 static 28 | stm32f1xx_hal_pcd.c:1738:19:HAL_PCD_EP_ClrStall 24 static 29 | stm32f1xx_hal_pcd.c:1774:19:HAL_PCD_EP_Flush 16 static 30 | stm32f1xx_hal_pcd.c:1797:19:HAL_PCD_ActivateRemoteWakeup 16 static 31 | stm32f1xx_hal_pcd.c:1807:19:HAL_PCD_DeActivateRemoteWakeup 16 static 32 | stm32f1xx_hal_pcd.c:1836:18:HAL_PCD_GetState 16 static 33 | stm32f1xx_hal_pcd.c:1997:26:PCD_EP_ISR_Handler 48 static 34 | -------------------------------------------------------------------------------- /CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file system_stm32f10x.h 4 | * @author MCD Application Team 5 | * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Header File. 6 | ****************************************************************************** 7 | * @attention 8 | * 9 | *

© Copyright (c) 2017 STMicroelectronics. 10 | * All rights reserved.

11 | * 12 | * This software component is licensed by ST under BSD 3-Clause license, 13 | * the "License"; You may not use this file except in compliance with the 14 | * License. You may obtain a copy of the License at: 15 | * opensource.org/licenses/BSD-3-Clause 16 | * 17 | ****************************************************************************** 18 | */ 19 | 20 | /** @addtogroup CMSIS 21 | * @{ 22 | */ 23 | 24 | /** @addtogroup stm32f10x_system 25 | * @{ 26 | */ 27 | 28 | /** 29 | * @brief Define to prevent recursive inclusion 30 | */ 31 | #ifndef __SYSTEM_STM32F10X_H 32 | #define __SYSTEM_STM32F10X_H 33 | 34 | #ifdef __cplusplus 35 | extern "C" { 36 | #endif 37 | 38 | /** @addtogroup STM32F10x_System_Includes 39 | * @{ 40 | */ 41 | 42 | /** 43 | * @} 44 | */ 45 | 46 | 47 | /** @addtogroup STM32F10x_System_Exported_types 48 | * @{ 49 | */ 50 | 51 | extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ 52 | extern const uint8_t AHBPrescTable[16U]; /*!< AHB prescalers table values */ 53 | extern const uint8_t APBPrescTable[8U]; /*!< APB prescalers table values */ 54 | 55 | /** 56 | * @} 57 | */ 58 | 59 | /** @addtogroup STM32F10x_System_Exported_Constants 60 | * @{ 61 | */ 62 | 63 | /** 64 | * @} 65 | */ 66 | 67 | /** @addtogroup STM32F10x_System_Exported_Macros 68 | * @{ 69 | */ 70 | 71 | /** 72 | * @} 73 | */ 74 | 75 | /** @addtogroup STM32F10x_System_Exported_Functions 76 | * @{ 77 | */ 78 | 79 | extern void SystemInit(void); 80 | extern void SystemCoreClockUpdate(void); 81 | /** 82 | * @} 83 | */ 84 | 85 | #ifdef __cplusplus 86 | } 87 | #endif 88 | 89 | #endif /*__SYSTEM_STM32F10X_H */ 90 | 91 | /** 92 | * @} 93 | */ 94 | 95 | /** 96 | * @} 97 | */ 98 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 99 | -------------------------------------------------------------------------------- /CMSIS/Include/tz_context.h: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * @file tz_context.h 3 | * @brief Context Management for Armv8-M TrustZone 4 | * @version V1.0.1 5 | * @date 10. January 2018 6 | ******************************************************************************/ 7 | /* 8 | * Copyright (c) 2017-2018 Arm Limited. All rights reserved. 9 | * 10 | * SPDX-License-Identifier: Apache-2.0 11 | * 12 | * Licensed under the Apache License, Version 2.0 (the License); you may 13 | * not use this file except in compliance with the License. 14 | * You may obtain a copy of the License at 15 | * 16 | * www.apache.org/licenses/LICENSE-2.0 17 | * 18 | * Unless required by applicable law or agreed to in writing, software 19 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT 20 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21 | * See the License for the specific language governing permissions and 22 | * limitations under the License. 23 | */ 24 | 25 | #if defined ( __ICCARM__ ) 26 | #pragma system_include /* treat file as system include file for MISRA check */ 27 | #elif defined (__clang__) 28 | #pragma clang system_header /* treat file as system include file */ 29 | #endif 30 | 31 | #ifndef TZ_CONTEXT_H 32 | #define TZ_CONTEXT_H 33 | 34 | #include 35 | 36 | #ifndef TZ_MODULEID_T 37 | #define TZ_MODULEID_T 38 | /// \details Data type that identifies secure software modules called by a process. 39 | typedef uint32_t TZ_ModuleId_t; 40 | #endif 41 | 42 | /// \details TZ Memory ID identifies an allocated memory slot. 43 | typedef uint32_t TZ_MemoryId_t; 44 | 45 | /// Initialize secure context memory system 46 | /// \return execution status (1: success, 0: error) 47 | uint32_t TZ_InitContextSystem_S (void); 48 | 49 | /// Allocate context memory for calling secure software modules in TrustZone 50 | /// \param[in] module identifies software modules called from non-secure mode 51 | /// \return value != 0 id TrustZone memory slot identifier 52 | /// \return value 0 no memory available or internal error 53 | TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module); 54 | 55 | /// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S 56 | /// \param[in] id TrustZone memory slot identifier 57 | /// \return execution status (1: success, 0: error) 58 | uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id); 59 | 60 | /// Load secure context (called on RTOS thread context switch) 61 | /// \param[in] id TrustZone memory slot identifier 62 | /// \return execution status (1: success, 0: error) 63 | uint32_t TZ_LoadContext_S (TZ_MemoryId_t id); 64 | 65 | /// Store secure context (called on RTOS thread context switch) 66 | /// \param[in] id TrustZone memory slot identifier 67 | /// \return execution status (1: success, 0: error) 68 | uint32_t TZ_StoreContext_S (TZ_MemoryId_t id); 69 | 70 | #endif // TZ_CONTEXT_H 71 | -------------------------------------------------------------------------------- /Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.su: -------------------------------------------------------------------------------- 1 | stm32f1xx_hal_uart.c:314:19:HAL_UART_Init 16 static 2 | stm32f1xx_hal_uart.c:391:19:HAL_HalfDuplex_Init 16 static 3 | stm32f1xx_hal_uart.c:466:19:HAL_LIN_Init 16 static 4 | stm32f1xx_hal_uart.c:549:19:HAL_MultiProcessor_Init 24 static 5 | stm32f1xx_hal_uart.c:628:19:HAL_UART_DeInit 16 static 6 | stm32f1xx_hal_uart.c:672:13:HAL_UART_MspInit 16 static 7 | stm32f1xx_hal_uart.c:687:13:HAL_UART_MspDeInit 16 static 8 | stm32f1xx_hal_uart.c:1027:19:HAL_UART_Transmit 40 static 9 | stm32f1xx_hal_uart.c:1112:19:HAL_UART_Receive 40 static 10 | stm32f1xx_hal_uart.c:1203:19:HAL_UART_Transmit_IT 24 static 11 | stm32f1xx_hal_uart.c:1248:19:HAL_UART_Receive_IT 24 static 12 | stm32f1xx_hal_uart.c:1299:19:HAL_UART_Transmit_DMA 32 static 13 | stm32f1xx_hal_uart.c:1367:19:HAL_UART_Receive_DMA 32 static 14 | stm32f1xx_hal_uart.c:1434:19:HAL_UART_DMAPause 24 static 15 | stm32f1xx_hal_uart.c:1471:19:HAL_UART_DMAResume 24 static 16 | stm32f1xx_hal_uart.c:1507:19:HAL_UART_DMAStop 24 static 17 | stm32f1xx_hal_uart.c:1559:19:HAL_UART_Abort 16 static 18 | stm32f1xx_hal_uart.c:1641:19:HAL_UART_AbortTransmit 16 static 19 | stm32f1xx_hal_uart.c:1692:19:HAL_UART_AbortReceive 16 static 20 | stm32f1xx_hal_uart.c:1746:19:HAL_UART_Abort_IT 24 static 21 | stm32f1xx_hal_uart.c:1874:19:HAL_UART_AbortTransmit_IT 16 static 22 | stm32f1xx_hal_uart.c:1951:19:HAL_UART_AbortReceive_IT 16 static 23 | stm32f1xx_hal_uart.c:2021:6:HAL_UART_IRQHandler 40 static 24 | stm32f1xx_hal_uart.c:2167:13:HAL_UART_TxCpltCallback 16 static 25 | stm32f1xx_hal_uart.c:2182:13:HAL_UART_TxHalfCpltCallback 16 static 26 | stm32f1xx_hal_uart.c:2197:13:HAL_UART_RxCpltCallback 16 static 27 | stm32f1xx_hal_uart.c:2212:13:HAL_UART_RxHalfCpltCallback 16 static 28 | stm32f1xx_hal_uart.c:2227:13:HAL_UART_ErrorCallback 16 static 29 | stm32f1xx_hal_uart.c:2241:13:HAL_UART_AbortCpltCallback 16 static 30 | stm32f1xx_hal_uart.c:2256:13:HAL_UART_AbortTransmitCpltCallback 16 static 31 | stm32f1xx_hal_uart.c:2271:13:HAL_UART_AbortReceiveCpltCallback 16 static 32 | stm32f1xx_hal_uart.c:2310:19:HAL_LIN_SendBreak 16 static 33 | stm32f1xx_hal_uart.c:2337:19:HAL_MultiProcessor_EnterMuteMode 16 static 34 | stm32f1xx_hal_uart.c:2364:19:HAL_MultiProcessor_ExitMuteMode 16 static 35 | stm32f1xx_hal_uart.c:2391:19:HAL_HalfDuplex_EnableTransmitter 24 static 36 | stm32f1xx_hal_uart.c:2426:19:HAL_HalfDuplex_EnableReceiver 24 static 37 | stm32f1xx_hal_uart.c:2483:23:HAL_UART_GetState 24 static 38 | stm32f1xx_hal_uart.c:2498:10:HAL_UART_GetError 16 static 39 | stm32f1xx_hal_uart.c:2542:13:UART_DMATransmitCplt 24 static 40 | stm32f1xx_hal_uart.c:2577:13:UART_DMATxHalfCplt 24 static 41 | stm32f1xx_hal_uart.c:2596:13:UART_DMAReceiveCplt 24 static 42 | stm32f1xx_hal_uart.c:2630:13:UART_DMARxHalfCplt 24 static 43 | stm32f1xx_hal_uart.c:2649:13:UART_DMAError 24 static 44 | stm32f1xx_hal_uart.c:2690:26:UART_WaitOnFlagUntilTimeout 24 static 45 | stm32f1xx_hal_uart.c:2722:13:UART_EndTxTransfer 16 static 46 | stm32f1xx_hal_uart.c:2736:13:UART_EndRxTransfer 16 static 47 | stm32f1xx_hal_uart.c:2753:13:UART_DMAAbortOnError 24 static 48 | stm32f1xx_hal_uart.c:2777:13:UART_DMATxAbortCallback 24 static 49 | stm32f1xx_hal_uart.c:2822:13:UART_DMARxAbortCallback 24 static 50 | stm32f1xx_hal_uart.c:2867:13:UART_DMATxOnlyAbortCallback 24 static 51 | stm32f1xx_hal_uart.c:2895:13:UART_DMARxOnlyAbortCallback 24 static 52 | stm32f1xx_hal_uart.c:2920:26:UART_Transmit_IT 24 static 53 | stm32f1xx_hal_uart.c:2967:26:UART_EndTransmit_IT 16 static 54 | stm32f1xx_hal_uart.c:2992:26:UART_Receive_IT 24 static 55 | stm32f1xx_hal_uart.c:3063:13:UART_SetConfig 24 static 56 | -------------------------------------------------------------------------------- /touch.c: -------------------------------------------------------------------------------- 1 | /* 2 | * touch.c 3 | * 4 | * Created on: 2018. 12. 7. 5 | * Author: chand 6 | */ 7 | #include "stm32f1xx_hal.h" 8 | #include "touch.h" 9 | #include "i2c.h" 10 | #include "usb_device.h" 11 | 12 | #define max_point_num 5 13 | 14 | #define FT5316_I2C_ID 0x70 15 | 16 | #define TOUCH_I2C_ID FT5316_I2C_ID 17 | 18 | extern USBD_HandleTypeDef hUsbDeviceFS; 19 | extern uint8_t USBD_HID_SendReport (USBD_HandleTypeDef *pdev, uint8_t *report, uint16_t len); 20 | 21 | static uint8_t touchIrq = 0; 22 | //static uint16_t oldX[max_point_num]={0,}; 23 | //static uint16_t oldY[max_point_num]={0,}; 24 | static uint16_t oldid[max_point_num]; 25 | //static uint8_t p_point_num = 0; 26 | 27 | 28 | //https://docs.microsoft.com/en-us/windows-hardware/design/component-guidelines/touch-and-pen-support 29 | const uint8_t touchQualityKey[] = { 30 | 0x05, //reportid 31 | 0xfc, 0x28, 0xfe, 0x84, 0x40, 0xcb, 0x9a, 0x87, 0x0d, 0xbe, 0x57, 0x3c, 0xb6, 0x70, 0x09, 0x88, 32 | 0x07, 0x97, 0x2d, 0x2b, 0xe3, 0x38, 0x34, 0xb6, 0x6c, 0xed, 0xb0, 0xf7, 0xe5, 0x9c, 0xf6, 0xc2, 33 | 0x2e, 0x84, 0x1b, 0xe8, 0xb4, 0x51, 0x78, 0x43, 0x1f, 0x28, 0x4b, 0x7c, 0x2d, 0x53, 0xaf, 0xfc, 34 | 0x47, 0x70, 0x1b, 0x59, 0x6f, 0x74, 0x43, 0xc4, 0xf3, 0x47, 0x18, 0x53, 0x1a, 0xa2, 0xa1, 0x71, 35 | 0xc7, 0x95, 0x0e, 0x31, 0x55, 0x21, 0xd3, 0xb5, 0x1e, 0xe9, 0x0c, 0xba, 0xec, 0xb8, 0x89, 0x19, 36 | 0x3e, 0xb3, 0xaf, 0x75, 0x81, 0x9d, 0x53, 0xb9, 0x41, 0x57, 0xf4, 0x6d, 0x39, 0x25, 0x29, 0x7c, 37 | 0x87, 0xd9, 0xb4, 0x98, 0x45, 0x7d, 0xa7, 0x26, 0x9c, 0x65, 0x3b, 0x85, 0x68, 0x89, 0xd7, 0x3b, 38 | 0xbd, 0xff, 0x14, 0x67, 0xf2, 0x2b, 0xf0, 0x2a, 0x41, 0x54, 0xf0, 0xfd, 0x2c, 0x66, 0x7c, 0xf8, 39 | 0xc0, 0x8f, 0x33, 0x13, 0x03, 0xf1, 0xd3, 0xc1, 0x0b, 0x89, 0xd9, 0x1b, 0x62, 0xcd, 0x51, 0xb7, 40 | 0x80, 0xb8, 0xaf, 0x3a, 0x10, 0xc1, 0x8a, 0x5b, 0xe8, 0x8a, 0x56, 0xf0, 0x8c, 0xaa, 0xfa, 0x35, 41 | 0xe9, 0x42, 0xc4, 0xd8, 0x55, 0xc3, 0x38, 0xcc, 0x2b, 0x53, 0x5c, 0x69, 0x52, 0xd5, 0xc8, 0x73, 42 | 0x02, 0x38, 0x7c, 0x73, 0xb6, 0x41, 0xe7, 0xff, 0x05, 0xd8, 0x2b, 0x79, 0x9a, 0xe2, 0x34, 0x60, 43 | 0x8f, 0xa3, 0x32, 0x1f, 0x09, 0x78, 0x62, 0xbc, 0x80, 0xe3, 0x0f, 0xbd, 0x65, 0x20, 0x08, 0x13, 44 | 0xc1, 0xe2, 0xee, 0x53, 0x2d, 0x86, 0x7e, 0xa7, 0x5a, 0xc5, 0xd3, 0x7d, 0x98, 0xbe, 0x31, 0x48, 45 | 0x1f, 0xfb, 0xda, 0xaf, 0xa2, 0xa8, 0x6a, 0x89, 0xd6, 0xbf, 0xf2, 0xd3, 0x32, 0x2a, 0x9a, 0xe4, 46 | 0xcf, 0x17, 0xb7, 0xb8, 0xf4, 0xe1, 0x33, 0x08, 0x24, 0x8b, 0xc4, 0x43, 0xa5, 0xe5, 0x24, 0xc2 47 | }; 48 | 49 | 50 | struct __packed touchHid_t { 51 | uint8_t tip; 52 | uint8_t num; 53 | uint16_t x; 54 | uint16_t y; 55 | uint8_t width; 56 | uint8_t height; 57 | 58 | }; 59 | struct __packed multiTouchHid_t { 60 | uint8_t report; 61 | struct touchHid_t touch[max_point_num]; 62 | uint16_t count; 63 | uint8_t id; 64 | }; 65 | struct multiTouchHid_t multiTouch; 66 | 67 | void tpd_down(uint16_t x, uint16_t y, uint16_t p) 68 | { 69 | multiTouch.touch[multiTouch.id].tip = 0x01; 70 | multiTouch.touch[multiTouch.id].num = p; //contact id 71 | multiTouch.touch[multiTouch.id].x = x; 72 | multiTouch.touch[multiTouch.id].y = y; 73 | multiTouch.touch[multiTouch.id].width = 0x30; //width of contact 74 | multiTouch.touch[multiTouch.id].height = 0x30; 75 | multiTouch.id++; 76 | 77 | } 78 | void tpd_up(uint16_t x, uint16_t y, uint16_t p) 79 | { 80 | multiTouch.touch[multiTouch.id].tip = 0x00; 81 | //multiTouch.touch[multiTouch.id].num = multiTouch.id; 82 | multiTouch.touch[multiTouch.id].num = p; 83 | //multiTouch.touch[multiTouch.id].x = x; 84 | //multiTouch.touch[multiTouch.id].y = y; 85 | multiTouch.touch[multiTouch.id].width = 0; 86 | multiTouch.touch[multiTouch.id].height = 0; 87 | multiTouch.id++; 88 | 89 | } 90 | 91 | void input_sync() 92 | { 93 | multiTouch.report = 0x01; 94 | multiTouch.count++; 95 | /* 96 | for(int i=0;i max_point_num) 180 | point_num = max_point_num; 181 | 182 | for(i = 0; i < point_num; i++) 183 | { 184 | //03H [7:6] Event Flag - not used 185 | // 0 : down 186 | // 1 : up 187 | // 2 : contact 188 | // 3 : reserved 189 | //05H [7:4] Touch ID 190 | // [3:0] Touch ID of Touch Point 191 | 192 | //03H [3:0] MSB of Touch X Position in pixels [11:8] 193 | //04H [7:0] LSB of Touch X Position in pixels [7:0] 194 | //05H [3:0] MSB of Touch Y Position in pixels [11:8] 195 | //06H [7:0] LSB of Touch Y Position in pixels [7:0] 196 | 197 | x[i] = (((uint16_t)dat[3+6*i]&0x0F)<<8)|dat[3+6*i+1]; 198 | y[i] = (((uint16_t)dat[3+6*i+2]&0x0F)<<8)|dat[3+6*i+3]; 199 | 200 | id[i] = dat[5+6*i]>>4; 201 | 202 | if(x[i] > 1024) 203 | x[i] = 1024; 204 | if(y[i] > 600) 205 | y[i] = 600; 206 | x[i] = (x[i]*2048)/1024;// touch range ( 0 ~ 1024 ) to USB HID range (0 ~ 2048) 207 | y[i] = (y[i]*2048)/600; // touch range ( 0 ~ 1024 ) to USB HID range (0 ~ 2048) 208 | 209 | tpd_down(x[i], y[i], id[i]); 210 | 211 | 212 | for(uint8_t c = 0; c < point_num; c++) 213 | { 214 | if(id[i] == oldid[c]) 215 | { 216 | oldid[c]=255; 217 | } 218 | 219 | } 220 | 221 | } 222 | //input_sync(); 223 | 224 | 225 | for(i=0; i < point_num; i++) 226 | { 227 | if(oldid[i]!=255) 228 | { 229 | tpd_up(x[i], y[i], oldid[i]); 230 | 231 | } 232 | oldid[i] = id[i]; 233 | } 234 | input_sync(); 235 | 236 | /* 237 | input_sync(); 238 | for(i = 0; i < point_num; i++) 239 | { 240 | if(id[i]!=oldid[i]) 241 | { 242 | tpd_up(x[i], y[i], oldid[i]); 243 | //input_sync(); 244 | } 245 | oldid[i] = id[i]; 246 | } 247 | input_sync(); 248 | */ 249 | 250 | 251 | /* 252 | if(point_num > 0) 253 | { 254 | // pressed 255 | for(i=0;i point_num) 263 | { 264 | for(i=0;i0) 274 | { 275 | //release 276 | for(i=0;i 29 | 30 | /* 31 | * Arm Compiler 4/5 32 | */ 33 | #if defined ( __CC_ARM ) 34 | #include "cmsis_armcc.h" 35 | 36 | 37 | /* 38 | * Arm Compiler 6 (armclang) 39 | */ 40 | #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) 41 | #include "cmsis_armclang.h" 42 | 43 | 44 | /* 45 | * GNU Compiler 46 | */ 47 | #elif defined ( __GNUC__ ) 48 | #include "cmsis_gcc.h" 49 | 50 | 51 | /* 52 | * IAR Compiler 53 | */ 54 | #elif defined ( __ICCARM__ ) 55 | #include 56 | 57 | 58 | /* 59 | * TI Arm Compiler 60 | */ 61 | #elif defined ( __TI_ARM__ ) 62 | #include 63 | 64 | #ifndef __ASM 65 | #define __ASM __asm 66 | #endif 67 | #ifndef __INLINE 68 | #define __INLINE inline 69 | #endif 70 | #ifndef __STATIC_INLINE 71 | #define __STATIC_INLINE static inline 72 | #endif 73 | #ifndef __STATIC_FORCEINLINE 74 | #define __STATIC_FORCEINLINE __STATIC_INLINE 75 | #endif 76 | #ifndef __NO_RETURN 77 | #define __NO_RETURN __attribute__((noreturn)) 78 | #endif 79 | #ifndef __USED 80 | #define __USED __attribute__((used)) 81 | #endif 82 | #ifndef __WEAK 83 | #define __WEAK __attribute__((weak)) 84 | #endif 85 | #ifndef __PACKED 86 | #define __PACKED __attribute__((packed)) 87 | #endif 88 | #ifndef __PACKED_STRUCT 89 | #define __PACKED_STRUCT struct __attribute__((packed)) 90 | #endif 91 | #ifndef __PACKED_UNION 92 | #define __PACKED_UNION union __attribute__((packed)) 93 | #endif 94 | #ifndef __UNALIGNED_UINT32 /* deprecated */ 95 | struct __attribute__((packed)) T_UINT32 { uint32_t v; }; 96 | #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) 97 | #endif 98 | #ifndef __UNALIGNED_UINT16_WRITE 99 | __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; 100 | #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val)) 101 | #endif 102 | #ifndef __UNALIGNED_UINT16_READ 103 | __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; 104 | #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) 105 | #endif 106 | #ifndef __UNALIGNED_UINT32_WRITE 107 | __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; 108 | #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) 109 | #endif 110 | #ifndef __UNALIGNED_UINT32_READ 111 | __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; 112 | #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) 113 | #endif 114 | #ifndef __ALIGNED 115 | #define __ALIGNED(x) __attribute__((aligned(x))) 116 | #endif 117 | #ifndef __RESTRICT 118 | #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. 119 | #define __RESTRICT 120 | #endif 121 | 122 | 123 | /* 124 | * TASKING Compiler 125 | */ 126 | #elif defined ( __TASKING__ ) 127 | /* 128 | * The CMSIS functions have been implemented as intrinsics in the compiler. 129 | * Please use "carm -?i" to get an up to date list of all intrinsics, 130 | * Including the CMSIS ones. 131 | */ 132 | 133 | #ifndef __ASM 134 | #define __ASM __asm 135 | #endif 136 | #ifndef __INLINE 137 | #define __INLINE inline 138 | #endif 139 | #ifndef __STATIC_INLINE 140 | #define __STATIC_INLINE static inline 141 | #endif 142 | #ifndef __STATIC_FORCEINLINE 143 | #define __STATIC_FORCEINLINE __STATIC_INLINE 144 | #endif 145 | #ifndef __NO_RETURN 146 | #define __NO_RETURN __attribute__((noreturn)) 147 | #endif 148 | #ifndef __USED 149 | #define __USED __attribute__((used)) 150 | #endif 151 | #ifndef __WEAK 152 | #define __WEAK __attribute__((weak)) 153 | #endif 154 | #ifndef __PACKED 155 | #define __PACKED __packed__ 156 | #endif 157 | #ifndef __PACKED_STRUCT 158 | #define __PACKED_STRUCT struct __packed__ 159 | #endif 160 | #ifndef __PACKED_UNION 161 | #define __PACKED_UNION union __packed__ 162 | #endif 163 | #ifndef __UNALIGNED_UINT32 /* deprecated */ 164 | struct __packed__ T_UINT32 { uint32_t v; }; 165 | #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) 166 | #endif 167 | #ifndef __UNALIGNED_UINT16_WRITE 168 | __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; 169 | #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) 170 | #endif 171 | #ifndef __UNALIGNED_UINT16_READ 172 | __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; 173 | #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) 174 | #endif 175 | #ifndef __UNALIGNED_UINT32_WRITE 176 | __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; 177 | #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) 178 | #endif 179 | #ifndef __UNALIGNED_UINT32_READ 180 | __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; 181 | #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) 182 | #endif 183 | #ifndef __ALIGNED 184 | #define __ALIGNED(x) __align(x) 185 | #endif 186 | #ifndef __RESTRICT 187 | #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. 188 | #define __RESTRICT 189 | #endif 190 | 191 | 192 | /* 193 | * COSMIC Compiler 194 | */ 195 | #elif defined ( __CSMC__ ) 196 | #include 197 | 198 | #ifndef __ASM 199 | #define __ASM _asm 200 | #endif 201 | #ifndef __INLINE 202 | #define __INLINE inline 203 | #endif 204 | #ifndef __STATIC_INLINE 205 | #define __STATIC_INLINE static inline 206 | #endif 207 | #ifndef __STATIC_FORCEINLINE 208 | #define __STATIC_FORCEINLINE __STATIC_INLINE 209 | #endif 210 | #ifndef __NO_RETURN 211 | // NO RETURN is automatically detected hence no warning here 212 | #define __NO_RETURN 213 | #endif 214 | #ifndef __USED 215 | #warning No compiler specific solution for __USED. __USED is ignored. 216 | #define __USED 217 | #endif 218 | #ifndef __WEAK 219 | #define __WEAK __weak 220 | #endif 221 | #ifndef __PACKED 222 | #define __PACKED @packed 223 | #endif 224 | #ifndef __PACKED_STRUCT 225 | #define __PACKED_STRUCT @packed struct 226 | #endif 227 | #ifndef __PACKED_UNION 228 | #define __PACKED_UNION @packed union 229 | #endif 230 | #ifndef __UNALIGNED_UINT32 /* deprecated */ 231 | @packed struct T_UINT32 { uint32_t v; }; 232 | #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) 233 | #endif 234 | #ifndef __UNALIGNED_UINT16_WRITE 235 | __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; 236 | #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) 237 | #endif 238 | #ifndef __UNALIGNED_UINT16_READ 239 | __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; 240 | #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) 241 | #endif 242 | #ifndef __UNALIGNED_UINT32_WRITE 243 | __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; 244 | #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) 245 | #endif 246 | #ifndef __UNALIGNED_UINT32_READ 247 | __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; 248 | #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) 249 | #endif 250 | #ifndef __ALIGNED 251 | #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored. 252 | #define __ALIGNED(x) 253 | #endif 254 | #ifndef __RESTRICT 255 | #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. 256 | #define __RESTRICT 257 | #endif 258 | 259 | 260 | #else 261 | #error Unknown compiler. 262 | #endif 263 | 264 | 265 | #endif /* __CMSIS_COMPILER_H */ 266 | 267 | -------------------------------------------------------------------------------- /CMSIS/Include/mpu_armv8.h: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * @file mpu_armv8.h 3 | * @brief CMSIS MPU API for Armv8-M MPU 4 | * @version V5.0.4 5 | * @date 10. January 2018 6 | ******************************************************************************/ 7 | /* 8 | * Copyright (c) 2017-2018 Arm Limited. All rights reserved. 9 | * 10 | * SPDX-License-Identifier: Apache-2.0 11 | * 12 | * Licensed under the Apache License, Version 2.0 (the License); you may 13 | * not use this file except in compliance with the License. 14 | * You may obtain a copy of the License at 15 | * 16 | * www.apache.org/licenses/LICENSE-2.0 17 | * 18 | * Unless required by applicable law or agreed to in writing, software 19 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT 20 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21 | * See the License for the specific language governing permissions and 22 | * limitations under the License. 23 | */ 24 | 25 | #if defined ( __ICCARM__ ) 26 | #pragma system_include /* treat file as system include file for MISRA check */ 27 | #elif defined (__clang__) 28 | #pragma clang system_header /* treat file as system include file */ 29 | #endif 30 | 31 | #ifndef ARM_MPU_ARMV8_H 32 | #define ARM_MPU_ARMV8_H 33 | 34 | /** \brief Attribute for device memory (outer only) */ 35 | #define ARM_MPU_ATTR_DEVICE ( 0U ) 36 | 37 | /** \brief Attribute for non-cacheable, normal memory */ 38 | #define ARM_MPU_ATTR_NON_CACHEABLE ( 4U ) 39 | 40 | /** \brief Attribute for normal memory (outer and inner) 41 | * \param NT Non-Transient: Set to 1 for non-transient data. 42 | * \param WB Write-Back: Set to 1 to use write-back update policy. 43 | * \param RA Read Allocation: Set to 1 to use cache allocation on read miss. 44 | * \param WA Write Allocation: Set to 1 to use cache allocation on write miss. 45 | */ 46 | #define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \ 47 | (((NT & 1U) << 3U) | ((WB & 1U) << 2U) | ((RA & 1U) << 1U) | (WA & 1U)) 48 | 49 | /** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */ 50 | #define ARM_MPU_ATTR_DEVICE_nGnRnE (0U) 51 | 52 | /** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */ 53 | #define ARM_MPU_ATTR_DEVICE_nGnRE (1U) 54 | 55 | /** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */ 56 | #define ARM_MPU_ATTR_DEVICE_nGRE (2U) 57 | 58 | /** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */ 59 | #define ARM_MPU_ATTR_DEVICE_GRE (3U) 60 | 61 | /** \brief Memory Attribute 62 | * \param O Outer memory attributes 63 | * \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes 64 | */ 65 | #define ARM_MPU_ATTR(O, I) (((O & 0xFU) << 4U) | (((O & 0xFU) != 0U) ? (I & 0xFU) : ((I & 0x3U) << 2U))) 66 | 67 | /** \brief Normal memory non-shareable */ 68 | #define ARM_MPU_SH_NON (0U) 69 | 70 | /** \brief Normal memory outer shareable */ 71 | #define ARM_MPU_SH_OUTER (2U) 72 | 73 | /** \brief Normal memory inner shareable */ 74 | #define ARM_MPU_SH_INNER (3U) 75 | 76 | /** \brief Memory access permissions 77 | * \param RO Read-Only: Set to 1 for read-only memory. 78 | * \param NP Non-Privileged: Set to 1 for non-privileged memory. 79 | */ 80 | #define ARM_MPU_AP_(RO, NP) (((RO & 1U) << 1U) | (NP & 1U)) 81 | 82 | /** \brief Region Base Address Register value 83 | * \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned. 84 | * \param SH Defines the Shareability domain for this memory region. 85 | * \param RO Read-Only: Set to 1 for a read-only memory region. 86 | * \param NP Non-Privileged: Set to 1 for a non-privileged memory region. 87 | * \oaram XN eXecute Never: Set to 1 for a non-executable memory region. 88 | */ 89 | #define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \ 90 | ((BASE & MPU_RBAR_BASE_Msk) | \ 91 | ((SH << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \ 92 | ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \ 93 | ((XN << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk)) 94 | 95 | /** \brief Region Limit Address Register value 96 | * \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. 97 | * \param IDX The attribute index to be associated with this memory region. 98 | */ 99 | #define ARM_MPU_RLAR(LIMIT, IDX) \ 100 | ((LIMIT & MPU_RLAR_LIMIT_Msk) | \ 101 | ((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ 102 | (MPU_RLAR_EN_Msk)) 103 | 104 | /** 105 | * Struct for a single MPU Region 106 | */ 107 | typedef struct { 108 | uint32_t RBAR; /*!< Region Base Address Register value */ 109 | uint32_t RLAR; /*!< Region Limit Address Register value */ 110 | } ARM_MPU_Region_t; 111 | 112 | /** Enable the MPU. 113 | * \param MPU_Control Default access permissions for unconfigured regions. 114 | */ 115 | __STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) 116 | { 117 | __DSB(); 118 | __ISB(); 119 | MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; 120 | #ifdef SCB_SHCSR_MEMFAULTENA_Msk 121 | SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; 122 | #endif 123 | } 124 | 125 | /** Disable the MPU. 126 | */ 127 | __STATIC_INLINE void ARM_MPU_Disable(void) 128 | { 129 | __DSB(); 130 | __ISB(); 131 | #ifdef SCB_SHCSR_MEMFAULTENA_Msk 132 | SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; 133 | #endif 134 | MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; 135 | } 136 | 137 | #ifdef MPU_NS 138 | /** Enable the Non-secure MPU. 139 | * \param MPU_Control Default access permissions for unconfigured regions. 140 | */ 141 | __STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control) 142 | { 143 | __DSB(); 144 | __ISB(); 145 | MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; 146 | #ifdef SCB_SHCSR_MEMFAULTENA_Msk 147 | SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; 148 | #endif 149 | } 150 | 151 | /** Disable the Non-secure MPU. 152 | */ 153 | __STATIC_INLINE void ARM_MPU_Disable_NS(void) 154 | { 155 | __DSB(); 156 | __ISB(); 157 | #ifdef SCB_SHCSR_MEMFAULTENA_Msk 158 | SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; 159 | #endif 160 | MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk; 161 | } 162 | #endif 163 | 164 | /** Set the memory attribute encoding to the given MPU. 165 | * \param mpu Pointer to the MPU to be configured. 166 | * \param idx The attribute index to be set [0-7] 167 | * \param attr The attribute value to be set. 168 | */ 169 | __STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr) 170 | { 171 | const uint8_t reg = idx / 4U; 172 | const uint32_t pos = ((idx % 4U) * 8U); 173 | const uint32_t mask = 0xFFU << pos; 174 | 175 | if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) { 176 | return; // invalid index 177 | } 178 | 179 | mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask)); 180 | } 181 | 182 | /** Set the memory attribute encoding. 183 | * \param idx The attribute index to be set [0-7] 184 | * \param attr The attribute value to be set. 185 | */ 186 | __STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr) 187 | { 188 | ARM_MPU_SetMemAttrEx(MPU, idx, attr); 189 | } 190 | 191 | #ifdef MPU_NS 192 | /** Set the memory attribute encoding to the Non-secure MPU. 193 | * \param idx The attribute index to be set [0-7] 194 | * \param attr The attribute value to be set. 195 | */ 196 | __STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr) 197 | { 198 | ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr); 199 | } 200 | #endif 201 | 202 | /** Clear and disable the given MPU region of the given MPU. 203 | * \param mpu Pointer to MPU to be used. 204 | * \param rnr Region number to be cleared. 205 | */ 206 | __STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr) 207 | { 208 | mpu->RNR = rnr; 209 | mpu->RLAR = 0U; 210 | } 211 | 212 | /** Clear and disable the given MPU region. 213 | * \param rnr Region number to be cleared. 214 | */ 215 | __STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) 216 | { 217 | ARM_MPU_ClrRegionEx(MPU, rnr); 218 | } 219 | 220 | #ifdef MPU_NS 221 | /** Clear and disable the given Non-secure MPU region. 222 | * \param rnr Region number to be cleared. 223 | */ 224 | __STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr) 225 | { 226 | ARM_MPU_ClrRegionEx(MPU_NS, rnr); 227 | } 228 | #endif 229 | 230 | /** Configure the given MPU region of the given MPU. 231 | * \param mpu Pointer to MPU to be used. 232 | * \param rnr Region number to be configured. 233 | * \param rbar Value for RBAR register. 234 | * \param rlar Value for RLAR register. 235 | */ 236 | __STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar) 237 | { 238 | mpu->RNR = rnr; 239 | mpu->RBAR = rbar; 240 | mpu->RLAR = rlar; 241 | } 242 | 243 | /** Configure the given MPU region. 244 | * \param rnr Region number to be configured. 245 | * \param rbar Value for RBAR register. 246 | * \param rlar Value for RLAR register. 247 | */ 248 | __STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar) 249 | { 250 | ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar); 251 | } 252 | 253 | #ifdef MPU_NS 254 | /** Configure the given Non-secure MPU region. 255 | * \param rnr Region number to be configured. 256 | * \param rbar Value for RBAR register. 257 | * \param rlar Value for RLAR register. 258 | */ 259 | __STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar) 260 | { 261 | ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar); 262 | } 263 | #endif 264 | 265 | /** Memcopy with strictly ordered memory access, e.g. for register targets. 266 | * \param dst Destination data is copied to. 267 | * \param src Source data is copied from. 268 | * \param len Amount of data words to be copied. 269 | */ 270 | __STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) 271 | { 272 | uint32_t i; 273 | for (i = 0U; i < len; ++i) 274 | { 275 | dst[i] = src[i]; 276 | } 277 | } 278 | 279 | /** Load the given number of MPU regions from a table to the given MPU. 280 | * \param mpu Pointer to the MPU registers to be used. 281 | * \param rnr First region number to be configured. 282 | * \param table Pointer to the MPU configuration table. 283 | * \param cnt Amount of regions to be configured. 284 | */ 285 | __STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) 286 | { 287 | const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; 288 | if (cnt == 1U) { 289 | mpu->RNR = rnr; 290 | orderedCpy(&(mpu->RBAR), &(table->RBAR), rowWordSize); 291 | } else { 292 | uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U); 293 | uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES; 294 | 295 | mpu->RNR = rnrBase; 296 | while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) { 297 | uint32_t c = MPU_TYPE_RALIASES - rnrOffset; 298 | orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize); 299 | table += c; 300 | cnt -= c; 301 | rnrOffset = 0U; 302 | rnrBase += MPU_TYPE_RALIASES; 303 | mpu->RNR = rnrBase; 304 | } 305 | 306 | orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize); 307 | } 308 | } 309 | 310 | /** Load the given number of MPU regions from a table. 311 | * \param rnr First region number to be configured. 312 | * \param table Pointer to the MPU configuration table. 313 | * \param cnt Amount of regions to be configured. 314 | */ 315 | __STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) 316 | { 317 | ARM_MPU_LoadEx(MPU, rnr, table, cnt); 318 | } 319 | 320 | #ifdef MPU_NS 321 | /** Load the given number of MPU regions from a table to the Non-secure MPU. 322 | * \param rnr First region number to be configured. 323 | * \param table Pointer to the MPU configuration table. 324 | * \param cnt Amount of regions to be configured. 325 | */ 326 | __STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) 327 | { 328 | ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt); 329 | } 330 | #endif 331 | 332 | #endif 333 | 334 | -------------------------------------------------------------------------------- /CMSIS/Include/mpu_armv7.h: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * @file mpu_armv7.h 3 | * @brief CMSIS MPU API for Armv7-M MPU 4 | * @version V5.0.4 5 | * @date 10. January 2018 6 | ******************************************************************************/ 7 | /* 8 | * Copyright (c) 2017-2018 Arm Limited. All rights reserved. 9 | * 10 | * SPDX-License-Identifier: Apache-2.0 11 | * 12 | * Licensed under the Apache License, Version 2.0 (the License); you may 13 | * not use this file except in compliance with the License. 14 | * You may obtain a copy of the License at 15 | * 16 | * www.apache.org/licenses/LICENSE-2.0 17 | * 18 | * Unless required by applicable law or agreed to in writing, software 19 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT 20 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21 | * See the License for the specific language governing permissions and 22 | * limitations under the License. 23 | */ 24 | 25 | #if defined ( __ICCARM__ ) 26 | #pragma system_include /* treat file as system include file for MISRA check */ 27 | #elif defined (__clang__) 28 | #pragma clang system_header /* treat file as system include file */ 29 | #endif 30 | 31 | #ifndef ARM_MPU_ARMV7_H 32 | #define ARM_MPU_ARMV7_H 33 | 34 | #define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes 35 | #define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes 36 | #define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes 37 | #define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes 38 | #define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes 39 | #define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte 40 | #define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes 41 | #define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes 42 | #define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes 43 | #define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes 44 | #define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes 45 | #define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes 46 | #define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes 47 | #define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes 48 | #define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes 49 | #define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte 50 | #define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes 51 | #define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes 52 | #define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes 53 | #define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes 54 | #define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes 55 | #define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes 56 | #define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes 57 | #define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes 58 | #define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes 59 | #define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte 60 | #define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes 61 | #define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes 62 | 63 | #define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access 64 | #define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only 65 | #define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only 66 | #define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access 67 | #define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only 68 | #define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access 69 | 70 | /** MPU Region Base Address Register Value 71 | * 72 | * \param Region The region to be configured, number 0 to 15. 73 | * \param BaseAddress The base address for the region. 74 | */ 75 | #define ARM_MPU_RBAR(Region, BaseAddress) \ 76 | (((BaseAddress) & MPU_RBAR_ADDR_Msk) | \ 77 | ((Region) & MPU_RBAR_REGION_Msk) | \ 78 | (MPU_RBAR_VALID_Msk)) 79 | 80 | /** 81 | * MPU Memory Access Attributes 82 | * 83 | * \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. 84 | * \param IsShareable Region is shareable between multiple bus masters. 85 | * \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. 86 | * \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. 87 | */ 88 | #define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \ 89 | ((((TypeExtField ) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \ 90 | (((IsShareable ) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \ 91 | (((IsCacheable ) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \ 92 | (((IsBufferable ) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk)) 93 | 94 | /** 95 | * MPU Region Attribute and Size Register Value 96 | * 97 | * \param DisableExec Instruction access disable bit, 1= disable instruction fetches. 98 | * \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. 99 | * \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_. 100 | * \param SubRegionDisable Sub-region disable field. 101 | * \param Size Region size of the region to be configured, for example 4K, 8K. 102 | */ 103 | #define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \ 104 | ((((DisableExec ) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \ 105 | (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \ 106 | (((AccessAttributes) ) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) 107 | 108 | /** 109 | * MPU Region Attribute and Size Register Value 110 | * 111 | * \param DisableExec Instruction access disable bit, 1= disable instruction fetches. 112 | * \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. 113 | * \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. 114 | * \param IsShareable Region is shareable between multiple bus masters. 115 | * \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. 116 | * \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. 117 | * \param SubRegionDisable Sub-region disable field. 118 | * \param Size Region size of the region to be configured, for example 4K, 8K. 119 | */ 120 | #define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \ 121 | ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size) 122 | 123 | /** 124 | * MPU Memory Access Attribute for strongly ordered memory. 125 | * - TEX: 000b 126 | * - Shareable 127 | * - Non-cacheable 128 | * - Non-bufferable 129 | */ 130 | #define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U) 131 | 132 | /** 133 | * MPU Memory Access Attribute for device memory. 134 | * - TEX: 000b (if non-shareable) or 010b (if shareable) 135 | * - Shareable or non-shareable 136 | * - Non-cacheable 137 | * - Bufferable (if shareable) or non-bufferable (if non-shareable) 138 | * 139 | * \param IsShareable Configures the device memory as shareable or non-shareable. 140 | */ 141 | #define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U)) 142 | 143 | /** 144 | * MPU Memory Access Attribute for normal memory. 145 | * - TEX: 1BBb (reflecting outer cacheability rules) 146 | * - Shareable or non-shareable 147 | * - Cacheable or non-cacheable (reflecting inner cacheability rules) 148 | * - Bufferable or non-bufferable (reflecting inner cacheability rules) 149 | * 150 | * \param OuterCp Configures the outer cache policy. 151 | * \param InnerCp Configures the inner cache policy. 152 | * \param IsShareable Configures the memory as shareable or non-shareable. 153 | */ 154 | #define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) & 2U), ((InnerCp) & 1U)) 155 | 156 | /** 157 | * MPU Memory Access Attribute non-cacheable policy. 158 | */ 159 | #define ARM_MPU_CACHEP_NOCACHE 0U 160 | 161 | /** 162 | * MPU Memory Access Attribute write-back, write and read allocate policy. 163 | */ 164 | #define ARM_MPU_CACHEP_WB_WRA 1U 165 | 166 | /** 167 | * MPU Memory Access Attribute write-through, no write allocate policy. 168 | */ 169 | #define ARM_MPU_CACHEP_WT_NWA 2U 170 | 171 | /** 172 | * MPU Memory Access Attribute write-back, no write allocate policy. 173 | */ 174 | #define ARM_MPU_CACHEP_WB_NWA 3U 175 | 176 | 177 | /** 178 | * Struct for a single MPU Region 179 | */ 180 | typedef struct { 181 | uint32_t RBAR; //!< The region base address register value (RBAR) 182 | uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR 183 | } ARM_MPU_Region_t; 184 | 185 | /** Enable the MPU. 186 | * \param MPU_Control Default access permissions for unconfigured regions. 187 | */ 188 | __STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) 189 | { 190 | __DSB(); 191 | __ISB(); 192 | MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; 193 | #ifdef SCB_SHCSR_MEMFAULTENA_Msk 194 | SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; 195 | #endif 196 | } 197 | 198 | /** Disable the MPU. 199 | */ 200 | __STATIC_INLINE void ARM_MPU_Disable(void) 201 | { 202 | __DSB(); 203 | __ISB(); 204 | #ifdef SCB_SHCSR_MEMFAULTENA_Msk 205 | SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; 206 | #endif 207 | MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; 208 | } 209 | 210 | /** Clear and disable the given MPU region. 211 | * \param rnr Region number to be cleared. 212 | */ 213 | __STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) 214 | { 215 | MPU->RNR = rnr; 216 | MPU->RASR = 0U; 217 | } 218 | 219 | /** Configure an MPU region. 220 | * \param rbar Value for RBAR register. 221 | * \param rsar Value for RSAR register. 222 | */ 223 | __STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr) 224 | { 225 | MPU->RBAR = rbar; 226 | MPU->RASR = rasr; 227 | } 228 | 229 | /** Configure the given MPU region. 230 | * \param rnr Region number to be configured. 231 | * \param rbar Value for RBAR register. 232 | * \param rsar Value for RSAR register. 233 | */ 234 | __STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr) 235 | { 236 | MPU->RNR = rnr; 237 | MPU->RBAR = rbar; 238 | MPU->RASR = rasr; 239 | } 240 | 241 | /** Memcopy with strictly ordered memory access, e.g. for register targets. 242 | * \param dst Destination data is copied to. 243 | * \param src Source data is copied from. 244 | * \param len Amount of data words to be copied. 245 | */ 246 | __STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) 247 | { 248 | uint32_t i; 249 | for (i = 0U; i < len; ++i) 250 | { 251 | dst[i] = src[i]; 252 | } 253 | } 254 | 255 | /** Load the given number of MPU regions from a table. 256 | * \param table Pointer to the MPU configuration table. 257 | * \param cnt Amount of regions to be configured. 258 | */ 259 | __STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt) 260 | { 261 | const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; 262 | while (cnt > MPU_TYPE_RALIASES) { 263 | orderedCpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize); 264 | table += MPU_TYPE_RALIASES; 265 | cnt -= MPU_TYPE_RALIASES; 266 | } 267 | orderedCpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize); 268 | } 269 | 270 | #endif 271 | -------------------------------------------------------------------------------- /CMSIS/Include/cmsis_armcc.h: -------------------------------------------------------------------------------- 1 | /**************************************************************************//** 2 | * @file cmsis_armcc.h 3 | * @brief CMSIS compiler ARMCC (Arm Compiler 5) header file 4 | * @version V5.0.4 5 | * @date 10. January 2018 6 | ******************************************************************************/ 7 | /* 8 | * Copyright (c) 2009-2018 Arm Limited. All rights reserved. 9 | * 10 | * SPDX-License-Identifier: Apache-2.0 11 | * 12 | * Licensed under the Apache License, Version 2.0 (the License); you may 13 | * not use this file except in compliance with the License. 14 | * You may obtain a copy of the License at 15 | * 16 | * www.apache.org/licenses/LICENSE-2.0 17 | * 18 | * Unless required by applicable law or agreed to in writing, software 19 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT 20 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21 | * See the License for the specific language governing permissions and 22 | * limitations under the License. 23 | */ 24 | 25 | #ifndef __CMSIS_ARMCC_H 26 | #define __CMSIS_ARMCC_H 27 | 28 | 29 | #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677) 30 | #error "Please use Arm Compiler Toolchain V4.0.677 or later!" 31 | #endif 32 | 33 | /* CMSIS compiler control architecture macros */ 34 | #if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \ 35 | (defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) ) 36 | #define __ARM_ARCH_6M__ 1 37 | #endif 38 | 39 | #if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1)) 40 | #define __ARM_ARCH_7M__ 1 41 | #endif 42 | 43 | #if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1)) 44 | #define __ARM_ARCH_7EM__ 1 45 | #endif 46 | 47 | /* __ARM_ARCH_8M_BASE__ not applicable */ 48 | /* __ARM_ARCH_8M_MAIN__ not applicable */ 49 | 50 | 51 | /* CMSIS compiler specific defines */ 52 | #ifndef __ASM 53 | #define __ASM __asm 54 | #endif 55 | #ifndef __INLINE 56 | #define __INLINE __inline 57 | #endif 58 | #ifndef __STATIC_INLINE 59 | #define __STATIC_INLINE static __inline 60 | #endif 61 | #ifndef __STATIC_FORCEINLINE 62 | #define __STATIC_FORCEINLINE static __forceinline 63 | #endif 64 | #ifndef __NO_RETURN 65 | #define __NO_RETURN __declspec(noreturn) 66 | #endif 67 | #ifndef __USED 68 | #define __USED __attribute__((used)) 69 | #endif 70 | #ifndef __WEAK 71 | #define __WEAK __attribute__((weak)) 72 | #endif 73 | #ifndef __PACKED 74 | #define __PACKED __attribute__((packed)) 75 | #endif 76 | #ifndef __PACKED_STRUCT 77 | #define __PACKED_STRUCT __packed struct 78 | #endif 79 | #ifndef __PACKED_UNION 80 | #define __PACKED_UNION __packed union 81 | #endif 82 | #ifndef __UNALIGNED_UINT32 /* deprecated */ 83 | #define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x))) 84 | #endif 85 | #ifndef __UNALIGNED_UINT16_WRITE 86 | #define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val)) 87 | #endif 88 | #ifndef __UNALIGNED_UINT16_READ 89 | #define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr))) 90 | #endif 91 | #ifndef __UNALIGNED_UINT32_WRITE 92 | #define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val)) 93 | #endif 94 | #ifndef __UNALIGNED_UINT32_READ 95 | #define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr))) 96 | #endif 97 | #ifndef __ALIGNED 98 | #define __ALIGNED(x) __attribute__((aligned(x))) 99 | #endif 100 | #ifndef __RESTRICT 101 | #define __RESTRICT __restrict 102 | #endif 103 | 104 | /* ########################### Core Function Access ########################### */ 105 | /** \ingroup CMSIS_Core_FunctionInterface 106 | \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions 107 | @{ 108 | */ 109 | 110 | /** 111 | \brief Enable IRQ Interrupts 112 | \details Enables IRQ interrupts by clearing the I-bit in the CPSR. 113 | Can only be executed in Privileged modes. 114 | */ 115 | /* intrinsic void __enable_irq(); */ 116 | 117 | 118 | /** 119 | \brief Disable IRQ Interrupts 120 | \details Disables IRQ interrupts by setting the I-bit in the CPSR. 121 | Can only be executed in Privileged modes. 122 | */ 123 | /* intrinsic void __disable_irq(); */ 124 | 125 | /** 126 | \brief Get Control Register 127 | \details Returns the content of the Control Register. 128 | \return Control Register value 129 | */ 130 | __STATIC_INLINE uint32_t __get_CONTROL(void) 131 | { 132 | register uint32_t __regControl __ASM("control"); 133 | return(__regControl); 134 | } 135 | 136 | 137 | /** 138 | \brief Set Control Register 139 | \details Writes the given value to the Control Register. 140 | \param [in] control Control Register value to set 141 | */ 142 | __STATIC_INLINE void __set_CONTROL(uint32_t control) 143 | { 144 | register uint32_t __regControl __ASM("control"); 145 | __regControl = control; 146 | } 147 | 148 | 149 | /** 150 | \brief Get IPSR Register 151 | \details Returns the content of the IPSR Register. 152 | \return IPSR Register value 153 | */ 154 | __STATIC_INLINE uint32_t __get_IPSR(void) 155 | { 156 | register uint32_t __regIPSR __ASM("ipsr"); 157 | return(__regIPSR); 158 | } 159 | 160 | 161 | /** 162 | \brief Get APSR Register 163 | \details Returns the content of the APSR Register. 164 | \return APSR Register value 165 | */ 166 | __STATIC_INLINE uint32_t __get_APSR(void) 167 | { 168 | register uint32_t __regAPSR __ASM("apsr"); 169 | return(__regAPSR); 170 | } 171 | 172 | 173 | /** 174 | \brief Get xPSR Register 175 | \details Returns the content of the xPSR Register. 176 | \return xPSR Register value 177 | */ 178 | __STATIC_INLINE uint32_t __get_xPSR(void) 179 | { 180 | register uint32_t __regXPSR __ASM("xpsr"); 181 | return(__regXPSR); 182 | } 183 | 184 | 185 | /** 186 | \brief Get Process Stack Pointer 187 | \details Returns the current value of the Process Stack Pointer (PSP). 188 | \return PSP Register value 189 | */ 190 | __STATIC_INLINE uint32_t __get_PSP(void) 191 | { 192 | register uint32_t __regProcessStackPointer __ASM("psp"); 193 | return(__regProcessStackPointer); 194 | } 195 | 196 | 197 | /** 198 | \brief Set Process Stack Pointer 199 | \details Assigns the given value to the Process Stack Pointer (PSP). 200 | \param [in] topOfProcStack Process Stack Pointer value to set 201 | */ 202 | __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) 203 | { 204 | register uint32_t __regProcessStackPointer __ASM("psp"); 205 | __regProcessStackPointer = topOfProcStack; 206 | } 207 | 208 | 209 | /** 210 | \brief Get Main Stack Pointer 211 | \details Returns the current value of the Main Stack Pointer (MSP). 212 | \return MSP Register value 213 | */ 214 | __STATIC_INLINE uint32_t __get_MSP(void) 215 | { 216 | register uint32_t __regMainStackPointer __ASM("msp"); 217 | return(__regMainStackPointer); 218 | } 219 | 220 | 221 | /** 222 | \brief Set Main Stack Pointer 223 | \details Assigns the given value to the Main Stack Pointer (MSP). 224 | \param [in] topOfMainStack Main Stack Pointer value to set 225 | */ 226 | __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) 227 | { 228 | register uint32_t __regMainStackPointer __ASM("msp"); 229 | __regMainStackPointer = topOfMainStack; 230 | } 231 | 232 | 233 | /** 234 | \brief Get Priority Mask 235 | \details Returns the current state of the priority mask bit from the Priority Mask Register. 236 | \return Priority Mask value 237 | */ 238 | __STATIC_INLINE uint32_t __get_PRIMASK(void) 239 | { 240 | register uint32_t __regPriMask __ASM("primask"); 241 | return(__regPriMask); 242 | } 243 | 244 | 245 | /** 246 | \brief Set Priority Mask 247 | \details Assigns the given value to the Priority Mask Register. 248 | \param [in] priMask Priority Mask 249 | */ 250 | __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) 251 | { 252 | register uint32_t __regPriMask __ASM("primask"); 253 | __regPriMask = (priMask); 254 | } 255 | 256 | 257 | #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ 258 | (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) 259 | 260 | /** 261 | \brief Enable FIQ 262 | \details Enables FIQ interrupts by clearing the F-bit in the CPSR. 263 | Can only be executed in Privileged modes. 264 | */ 265 | #define __enable_fault_irq __enable_fiq 266 | 267 | 268 | /** 269 | \brief Disable FIQ 270 | \details Disables FIQ interrupts by setting the F-bit in the CPSR. 271 | Can only be executed in Privileged modes. 272 | */ 273 | #define __disable_fault_irq __disable_fiq 274 | 275 | 276 | /** 277 | \brief Get Base Priority 278 | \details Returns the current value of the Base Priority register. 279 | \return Base Priority register value 280 | */ 281 | __STATIC_INLINE uint32_t __get_BASEPRI(void) 282 | { 283 | register uint32_t __regBasePri __ASM("basepri"); 284 | return(__regBasePri); 285 | } 286 | 287 | 288 | /** 289 | \brief Set Base Priority 290 | \details Assigns the given value to the Base Priority register. 291 | \param [in] basePri Base Priority value to set 292 | */ 293 | __STATIC_INLINE void __set_BASEPRI(uint32_t basePri) 294 | { 295 | register uint32_t __regBasePri __ASM("basepri"); 296 | __regBasePri = (basePri & 0xFFU); 297 | } 298 | 299 | 300 | /** 301 | \brief Set Base Priority with condition 302 | \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, 303 | or the new value increases the BASEPRI priority level. 304 | \param [in] basePri Base Priority value to set 305 | */ 306 | __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) 307 | { 308 | register uint32_t __regBasePriMax __ASM("basepri_max"); 309 | __regBasePriMax = (basePri & 0xFFU); 310 | } 311 | 312 | 313 | /** 314 | \brief Get Fault Mask 315 | \details Returns the current value of the Fault Mask register. 316 | \return Fault Mask register value 317 | */ 318 | __STATIC_INLINE uint32_t __get_FAULTMASK(void) 319 | { 320 | register uint32_t __regFaultMask __ASM("faultmask"); 321 | return(__regFaultMask); 322 | } 323 | 324 | 325 | /** 326 | \brief Set Fault Mask 327 | \details Assigns the given value to the Fault Mask register. 328 | \param [in] faultMask Fault Mask value to set 329 | */ 330 | __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) 331 | { 332 | register uint32_t __regFaultMask __ASM("faultmask"); 333 | __regFaultMask = (faultMask & (uint32_t)1U); 334 | } 335 | 336 | #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ 337 | (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ 338 | 339 | 340 | /** 341 | \brief Get FPSCR 342 | \details Returns the current value of the Floating Point Status/Control register. 343 | \return Floating Point Status/Control register value 344 | */ 345 | __STATIC_INLINE uint32_t __get_FPSCR(void) 346 | { 347 | #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ 348 | (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) 349 | register uint32_t __regfpscr __ASM("fpscr"); 350 | return(__regfpscr); 351 | #else 352 | return(0U); 353 | #endif 354 | } 355 | 356 | 357 | /** 358 | \brief Set FPSCR 359 | \details Assigns the given value to the Floating Point Status/Control register. 360 | \param [in] fpscr Floating Point Status/Control value to set 361 | */ 362 | __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) 363 | { 364 | #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ 365 | (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) 366 | register uint32_t __regfpscr __ASM("fpscr"); 367 | __regfpscr = (fpscr); 368 | #else 369 | (void)fpscr; 370 | #endif 371 | } 372 | 373 | 374 | /*@} end of CMSIS_Core_RegAccFunctions */ 375 | 376 | 377 | /* ########################## Core Instruction Access ######################### */ 378 | /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface 379 | Access to dedicated instructions 380 | @{ 381 | */ 382 | 383 | /** 384 | \brief No Operation 385 | \details No Operation does nothing. This instruction can be used for code alignment purposes. 386 | */ 387 | #define __NOP __nop 388 | 389 | 390 | /** 391 | \brief Wait For Interrupt 392 | \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. 393 | */ 394 | #define __WFI __wfi 395 | 396 | 397 | /** 398 | \brief Wait For Event 399 | \details Wait For Event is a hint instruction that permits the processor to enter 400 | a low-power state until one of a number of events occurs. 401 | */ 402 | #define __WFE __wfe 403 | 404 | 405 | /** 406 | \brief Send Event 407 | \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. 408 | */ 409 | #define __SEV __sev 410 | 411 | 412 | /** 413 | \brief Instruction Synchronization Barrier 414 | \details Instruction Synchronization Barrier flushes the pipeline in the processor, 415 | so that all instructions following the ISB are fetched from cache or memory, 416 | after the instruction has been completed. 417 | */ 418 | #define __ISB() do {\ 419 | __schedule_barrier();\ 420 | __isb(0xF);\ 421 | __schedule_barrier();\ 422 | } while (0U) 423 | 424 | /** 425 | \brief Data Synchronization Barrier 426 | \details Acts as a special kind of Data Memory Barrier. 427 | It completes when all explicit memory accesses before this instruction complete. 428 | */ 429 | #define __DSB() do {\ 430 | __schedule_barrier();\ 431 | __dsb(0xF);\ 432 | __schedule_barrier();\ 433 | } while (0U) 434 | 435 | /** 436 | \brief Data Memory Barrier 437 | \details Ensures the apparent order of the explicit memory operations before 438 | and after the instruction, without ensuring their completion. 439 | */ 440 | #define __DMB() do {\ 441 | __schedule_barrier();\ 442 | __dmb(0xF);\ 443 | __schedule_barrier();\ 444 | } while (0U) 445 | 446 | 447 | /** 448 | \brief Reverse byte order (32 bit) 449 | \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. 450 | \param [in] value Value to reverse 451 | \return Reversed value 452 | */ 453 | #define __REV __rev 454 | 455 | 456 | /** 457 | \brief Reverse byte order (16 bit) 458 | \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. 459 | \param [in] value Value to reverse 460 | \return Reversed value 461 | */ 462 | #ifndef __NO_EMBEDDED_ASM 463 | __attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) 464 | { 465 | rev16 r0, r0 466 | bx lr 467 | } 468 | #endif 469 | 470 | 471 | /** 472 | \brief Reverse byte order (16 bit) 473 | \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. 474 | \param [in] value Value to reverse 475 | \return Reversed value 476 | */ 477 | #ifndef __NO_EMBEDDED_ASM 478 | __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value) 479 | { 480 | revsh r0, r0 481 | bx lr 482 | } 483 | #endif 484 | 485 | 486 | /** 487 | \brief Rotate Right in unsigned value (32 bit) 488 | \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. 489 | \param [in] op1 Value to rotate 490 | \param [in] op2 Number of Bits to rotate 491 | \return Rotated value 492 | */ 493 | #define __ROR __ror 494 | 495 | 496 | /** 497 | \brief Breakpoint 498 | \details Causes the processor to enter Debug state. 499 | Debug tools can use this to investigate system state when the instruction at a particular address is reached. 500 | \param [in] value is ignored by the processor. 501 | If required, a debugger can use it to store additional information about the breakpoint. 502 | */ 503 | #define __BKPT(value) __breakpoint(value) 504 | 505 | 506 | /** 507 | \brief Reverse bit order of value 508 | \details Reverses the bit order of the given value. 509 | \param [in] value Value to reverse 510 | \return Reversed value 511 | */ 512 | #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ 513 | (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) 514 | #define __RBIT __rbit 515 | #else 516 | __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) 517 | { 518 | uint32_t result; 519 | uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ 520 | 521 | result = value; /* r will be reversed bits of v; first get LSB of v */ 522 | for (value >>= 1U; value != 0U; value >>= 1U) 523 | { 524 | result <<= 1U; 525 | result |= value & 1U; 526 | s--; 527 | } 528 | result <<= s; /* shift when v's highest bits are zero */ 529 | return result; 530 | } 531 | #endif 532 | 533 | 534 | /** 535 | \brief Count leading zeros 536 | \details Counts the number of leading zeros of a data value. 537 | \param [in] value Value to count the leading zeros 538 | \return number of leading zeros in value 539 | */ 540 | #define __CLZ __clz 541 | 542 | 543 | #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ 544 | (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) 545 | 546 | /** 547 | \brief LDR Exclusive (8 bit) 548 | \details Executes a exclusive LDR instruction for 8 bit value. 549 | \param [in] ptr Pointer to data 550 | \return value of type uint8_t at (*ptr) 551 | */ 552 | #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) 553 | #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) 554 | #else 555 | #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop") 556 | #endif 557 | 558 | 559 | /** 560 | \brief LDR Exclusive (16 bit) 561 | \details Executes a exclusive LDR instruction for 16 bit values. 562 | \param [in] ptr Pointer to data 563 | \return value of type uint16_t at (*ptr) 564 | */ 565 | #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) 566 | #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) 567 | #else 568 | #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop") 569 | #endif 570 | 571 | 572 | /** 573 | \brief LDR Exclusive (32 bit) 574 | \details Executes a exclusive LDR instruction for 32 bit values. 575 | \param [in] ptr Pointer to data 576 | \return value of type uint32_t at (*ptr) 577 | */ 578 | #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) 579 | #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) 580 | #else 581 | #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop") 582 | #endif 583 | 584 | 585 | /** 586 | \brief STR Exclusive (8 bit) 587 | \details Executes a exclusive STR instruction for 8 bit values. 588 | \param [in] value Value to store 589 | \param [in] ptr Pointer to location 590 | \return 0 Function succeeded 591 | \return 1 Function failed 592 | */ 593 | #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) 594 | #define __STREXB(value, ptr) __strex(value, ptr) 595 | #else 596 | #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") 597 | #endif 598 | 599 | 600 | /** 601 | \brief STR Exclusive (16 bit) 602 | \details Executes a exclusive STR instruction for 16 bit values. 603 | \param [in] value Value to store 604 | \param [in] ptr Pointer to location 605 | \return 0 Function succeeded 606 | \return 1 Function failed 607 | */ 608 | #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) 609 | #define __STREXH(value, ptr) __strex(value, ptr) 610 | #else 611 | #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") 612 | #endif 613 | 614 | 615 | /** 616 | \brief STR Exclusive (32 bit) 617 | \details Executes a exclusive STR instruction for 32 bit values. 618 | \param [in] value Value to store 619 | \param [in] ptr Pointer to location 620 | \return 0 Function succeeded 621 | \return 1 Function failed 622 | */ 623 | #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) 624 | #define __STREXW(value, ptr) __strex(value, ptr) 625 | #else 626 | #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") 627 | #endif 628 | 629 | 630 | /** 631 | \brief Remove the exclusive lock 632 | \details Removes the exclusive lock which is created by LDREX. 633 | */ 634 | #define __CLREX __clrex 635 | 636 | 637 | /** 638 | \brief Signed Saturate 639 | \details Saturates a signed value. 640 | \param [in] value Value to be saturated 641 | \param [in] sat Bit position to saturate to (1..32) 642 | \return Saturated value 643 | */ 644 | #define __SSAT __ssat 645 | 646 | 647 | /** 648 | \brief Unsigned Saturate 649 | \details Saturates an unsigned value. 650 | \param [in] value Value to be saturated 651 | \param [in] sat Bit position to saturate to (0..31) 652 | \return Saturated value 653 | */ 654 | #define __USAT __usat 655 | 656 | 657 | /** 658 | \brief Rotate Right with Extend (32 bit) 659 | \details Moves each bit of a bitstring right by one bit. 660 | The carry input is shifted in at the left end of the bitstring. 661 | \param [in] value Value to rotate 662 | \return Rotated value 663 | */ 664 | #ifndef __NO_EMBEDDED_ASM 665 | __attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) 666 | { 667 | rrx r0, r0 668 | bx lr 669 | } 670 | #endif 671 | 672 | 673 | /** 674 | \brief LDRT Unprivileged (8 bit) 675 | \details Executes a Unprivileged LDRT instruction for 8 bit value. 676 | \param [in] ptr Pointer to data 677 | \return value of type uint8_t at (*ptr) 678 | */ 679 | #define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr)) 680 | 681 | 682 | /** 683 | \brief LDRT Unprivileged (16 bit) 684 | \details Executes a Unprivileged LDRT instruction for 16 bit values. 685 | \param [in] ptr Pointer to data 686 | \return value of type uint16_t at (*ptr) 687 | */ 688 | #define __LDRHT(ptr) ((uint16_t) __ldrt(ptr)) 689 | 690 | 691 | /** 692 | \brief LDRT Unprivileged (32 bit) 693 | \details Executes a Unprivileged LDRT instruction for 32 bit values. 694 | \param [in] ptr Pointer to data 695 | \return value of type uint32_t at (*ptr) 696 | */ 697 | #define __LDRT(ptr) ((uint32_t ) __ldrt(ptr)) 698 | 699 | 700 | /** 701 | \brief STRT Unprivileged (8 bit) 702 | \details Executes a Unprivileged STRT instruction for 8 bit values. 703 | \param [in] value Value to store 704 | \param [in] ptr Pointer to location 705 | */ 706 | #define __STRBT(value, ptr) __strt(value, ptr) 707 | 708 | 709 | /** 710 | \brief STRT Unprivileged (16 bit) 711 | \details Executes a Unprivileged STRT instruction for 16 bit values. 712 | \param [in] value Value to store 713 | \param [in] ptr Pointer to location 714 | */ 715 | #define __STRHT(value, ptr) __strt(value, ptr) 716 | 717 | 718 | /** 719 | \brief STRT Unprivileged (32 bit) 720 | \details Executes a Unprivileged STRT instruction for 32 bit values. 721 | \param [in] value Value to store 722 | \param [in] ptr Pointer to location 723 | */ 724 | #define __STRT(value, ptr) __strt(value, ptr) 725 | 726 | #else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ 727 | (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ 728 | 729 | /** 730 | \brief Signed Saturate 731 | \details Saturates a signed value. 732 | \param [in] value Value to be saturated 733 | \param [in] sat Bit position to saturate to (1..32) 734 | \return Saturated value 735 | */ 736 | __attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) 737 | { 738 | if ((sat >= 1U) && (sat <= 32U)) 739 | { 740 | const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); 741 | const int32_t min = -1 - max ; 742 | if (val > max) 743 | { 744 | return max; 745 | } 746 | else if (val < min) 747 | { 748 | return min; 749 | } 750 | } 751 | return val; 752 | } 753 | 754 | /** 755 | \brief Unsigned Saturate 756 | \details Saturates an unsigned value. 757 | \param [in] value Value to be saturated 758 | \param [in] sat Bit position to saturate to (0..31) 759 | \return Saturated value 760 | */ 761 | __attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) 762 | { 763 | if (sat <= 31U) 764 | { 765 | const uint32_t max = ((1U << sat) - 1U); 766 | if (val > (int32_t)max) 767 | { 768 | return max; 769 | } 770 | else if (val < 0) 771 | { 772 | return 0U; 773 | } 774 | } 775 | return (uint32_t)val; 776 | } 777 | 778 | #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ 779 | (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ 780 | 781 | /*@}*/ /* end of group CMSIS_Core_InstructionInterface */ 782 | 783 | 784 | /* ################### Compiler specific Intrinsics ########################### */ 785 | /** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics 786 | Access to dedicated SIMD instructions 787 | @{ 788 | */ 789 | 790 | #if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) 791 | 792 | #define __SADD8 __sadd8 793 | #define __QADD8 __qadd8 794 | #define __SHADD8 __shadd8 795 | #define __UADD8 __uadd8 796 | #define __UQADD8 __uqadd8 797 | #define __UHADD8 __uhadd8 798 | #define __SSUB8 __ssub8 799 | #define __QSUB8 __qsub8 800 | #define __SHSUB8 __shsub8 801 | #define __USUB8 __usub8 802 | #define __UQSUB8 __uqsub8 803 | #define __UHSUB8 __uhsub8 804 | #define __SADD16 __sadd16 805 | #define __QADD16 __qadd16 806 | #define __SHADD16 __shadd16 807 | #define __UADD16 __uadd16 808 | #define __UQADD16 __uqadd16 809 | #define __UHADD16 __uhadd16 810 | #define __SSUB16 __ssub16 811 | #define __QSUB16 __qsub16 812 | #define __SHSUB16 __shsub16 813 | #define __USUB16 __usub16 814 | #define __UQSUB16 __uqsub16 815 | #define __UHSUB16 __uhsub16 816 | #define __SASX __sasx 817 | #define __QASX __qasx 818 | #define __SHASX __shasx 819 | #define __UASX __uasx 820 | #define __UQASX __uqasx 821 | #define __UHASX __uhasx 822 | #define __SSAX __ssax 823 | #define __QSAX __qsax 824 | #define __SHSAX __shsax 825 | #define __USAX __usax 826 | #define __UQSAX __uqsax 827 | #define __UHSAX __uhsax 828 | #define __USAD8 __usad8 829 | #define __USADA8 __usada8 830 | #define __SSAT16 __ssat16 831 | #define __USAT16 __usat16 832 | #define __UXTB16 __uxtb16 833 | #define __UXTAB16 __uxtab16 834 | #define __SXTB16 __sxtb16 835 | #define __SXTAB16 __sxtab16 836 | #define __SMUAD __smuad 837 | #define __SMUADX __smuadx 838 | #define __SMLAD __smlad 839 | #define __SMLADX __smladx 840 | #define __SMLALD __smlald 841 | #define __SMLALDX __smlaldx 842 | #define __SMUSD __smusd 843 | #define __SMUSDX __smusdx 844 | #define __SMLSD __smlsd 845 | #define __SMLSDX __smlsdx 846 | #define __SMLSLD __smlsld 847 | #define __SMLSLDX __smlsldx 848 | #define __SEL __sel 849 | #define __QADD __qadd 850 | #define __QSUB __qsub 851 | 852 | #define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ 853 | ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) 854 | 855 | #define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ 856 | ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) 857 | 858 | #define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ 859 | ((int64_t)(ARG3) << 32U) ) >> 32U)) 860 | 861 | #endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ 862 | /*@} end of group CMSIS_SIMD_intrinsics */ 863 | 864 | 865 | #endif /* __CMSIS_ARMCC_H */ 866 | -------------------------------------------------------------------------------- /CMSIS/Include/cmsis_iccarm.h: -------------------------------------------------------------------------------- 1 | /**************************************************************************//** 2 | * @file cmsis_iccarm.h 3 | * @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file 4 | * @version V5.0.7 5 | * @date 19. June 2018 6 | ******************************************************************************/ 7 | 8 | //------------------------------------------------------------------------------ 9 | // 10 | // Copyright (c) 2017-2018 IAR Systems 11 | // 12 | // Licensed under the Apache License, Version 2.0 (the "License") 13 | // you may not use this file except in compliance with the License. 14 | // You may obtain a copy of the License at 15 | // http://www.apache.org/licenses/LICENSE-2.0 16 | // 17 | // Unless required by applicable law or agreed to in writing, software 18 | // distributed under the License is distributed on an "AS IS" BASIS, 19 | // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 20 | // See the License for the specific language governing permissions and 21 | // limitations under the License. 22 | // 23 | //------------------------------------------------------------------------------ 24 | 25 | 26 | #ifndef __CMSIS_ICCARM_H__ 27 | #define __CMSIS_ICCARM_H__ 28 | 29 | #ifndef __ICCARM__ 30 | #error This file should only be compiled by ICCARM 31 | #endif 32 | 33 | #pragma system_include 34 | 35 | #define __IAR_FT _Pragma("inline=forced") __intrinsic 36 | 37 | #if (__VER__ >= 8000000) 38 | #define __ICCARM_V8 1 39 | #else 40 | #define __ICCARM_V8 0 41 | #endif 42 | 43 | #ifndef __ALIGNED 44 | #if __ICCARM_V8 45 | #define __ALIGNED(x) __attribute__((aligned(x))) 46 | #elif (__VER__ >= 7080000) 47 | /* Needs IAR language extensions */ 48 | #define __ALIGNED(x) __attribute__((aligned(x))) 49 | #else 50 | #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored. 51 | #define __ALIGNED(x) 52 | #endif 53 | #endif 54 | 55 | 56 | /* Define compiler macros for CPU architecture, used in CMSIS 5. 57 | */ 58 | #if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__ 59 | /* Macros already defined */ 60 | #else 61 | #if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__) 62 | #define __ARM_ARCH_8M_MAIN__ 1 63 | #elif defined(__ARM8M_BASELINE__) 64 | #define __ARM_ARCH_8M_BASE__ 1 65 | #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M' 66 | #if __ARM_ARCH == 6 67 | #define __ARM_ARCH_6M__ 1 68 | #elif __ARM_ARCH == 7 69 | #if __ARM_FEATURE_DSP 70 | #define __ARM_ARCH_7EM__ 1 71 | #else 72 | #define __ARM_ARCH_7M__ 1 73 | #endif 74 | #endif /* __ARM_ARCH */ 75 | #endif /* __ARM_ARCH_PROFILE == 'M' */ 76 | #endif 77 | 78 | /* Alternativ core deduction for older ICCARM's */ 79 | #if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \ 80 | !defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__) 81 | #if defined(__ARM6M__) && (__CORE__ == __ARM6M__) 82 | #define __ARM_ARCH_6M__ 1 83 | #elif defined(__ARM7M__) && (__CORE__ == __ARM7M__) 84 | #define __ARM_ARCH_7M__ 1 85 | #elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__) 86 | #define __ARM_ARCH_7EM__ 1 87 | #elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__) 88 | #define __ARM_ARCH_8M_BASE__ 1 89 | #elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__) 90 | #define __ARM_ARCH_8M_MAIN__ 1 91 | #elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__) 92 | #define __ARM_ARCH_8M_MAIN__ 1 93 | #else 94 | #error "Unknown target." 95 | #endif 96 | #endif 97 | 98 | 99 | 100 | #if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1 101 | #define __IAR_M0_FAMILY 1 102 | #elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1 103 | #define __IAR_M0_FAMILY 1 104 | #else 105 | #define __IAR_M0_FAMILY 0 106 | #endif 107 | 108 | 109 | #ifndef __ASM 110 | #define __ASM __asm 111 | #endif 112 | 113 | #ifndef __INLINE 114 | #define __INLINE inline 115 | #endif 116 | 117 | #ifndef __NO_RETURN 118 | #if __ICCARM_V8 119 | #define __NO_RETURN __attribute__((__noreturn__)) 120 | #else 121 | #define __NO_RETURN _Pragma("object_attribute=__noreturn") 122 | #endif 123 | #endif 124 | 125 | #ifndef __PACKED 126 | #if __ICCARM_V8 127 | #define __PACKED __attribute__((packed, aligned(1))) 128 | #else 129 | /* Needs IAR language extensions */ 130 | #define __PACKED __packed 131 | #endif 132 | #endif 133 | 134 | #ifndef __PACKED_STRUCT 135 | #if __ICCARM_V8 136 | #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) 137 | #else 138 | /* Needs IAR language extensions */ 139 | #define __PACKED_STRUCT __packed struct 140 | #endif 141 | #endif 142 | 143 | #ifndef __PACKED_UNION 144 | #if __ICCARM_V8 145 | #define __PACKED_UNION union __attribute__((packed, aligned(1))) 146 | #else 147 | /* Needs IAR language extensions */ 148 | #define __PACKED_UNION __packed union 149 | #endif 150 | #endif 151 | 152 | #ifndef __RESTRICT 153 | #define __RESTRICT __restrict 154 | #endif 155 | 156 | #ifndef __STATIC_INLINE 157 | #define __STATIC_INLINE static inline 158 | #endif 159 | 160 | #ifndef __FORCEINLINE 161 | #define __FORCEINLINE _Pragma("inline=forced") 162 | #endif 163 | 164 | #ifndef __STATIC_FORCEINLINE 165 | #define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE 166 | #endif 167 | 168 | #ifndef __UNALIGNED_UINT16_READ 169 | #pragma language=save 170 | #pragma language=extended 171 | __IAR_FT uint16_t __iar_uint16_read(void const *ptr) 172 | { 173 | return *(__packed uint16_t*)(ptr); 174 | } 175 | #pragma language=restore 176 | #define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR) 177 | #endif 178 | 179 | 180 | #ifndef __UNALIGNED_UINT16_WRITE 181 | #pragma language=save 182 | #pragma language=extended 183 | __IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val) 184 | { 185 | *(__packed uint16_t*)(ptr) = val;; 186 | } 187 | #pragma language=restore 188 | #define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL) 189 | #endif 190 | 191 | #ifndef __UNALIGNED_UINT32_READ 192 | #pragma language=save 193 | #pragma language=extended 194 | __IAR_FT uint32_t __iar_uint32_read(void const *ptr) 195 | { 196 | return *(__packed uint32_t*)(ptr); 197 | } 198 | #pragma language=restore 199 | #define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR) 200 | #endif 201 | 202 | #ifndef __UNALIGNED_UINT32_WRITE 203 | #pragma language=save 204 | #pragma language=extended 205 | __IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val) 206 | { 207 | *(__packed uint32_t*)(ptr) = val;; 208 | } 209 | #pragma language=restore 210 | #define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL) 211 | #endif 212 | 213 | #ifndef __UNALIGNED_UINT32 /* deprecated */ 214 | #pragma language=save 215 | #pragma language=extended 216 | __packed struct __iar_u32 { uint32_t v; }; 217 | #pragma language=restore 218 | #define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v) 219 | #endif 220 | 221 | #ifndef __USED 222 | #if __ICCARM_V8 223 | #define __USED __attribute__((used)) 224 | #else 225 | #define __USED _Pragma("__root") 226 | #endif 227 | #endif 228 | 229 | #ifndef __WEAK 230 | #if __ICCARM_V8 231 | #define __WEAK __attribute__((weak)) 232 | #else 233 | #define __WEAK _Pragma("__weak") 234 | #endif 235 | #endif 236 | 237 | 238 | #ifndef __ICCARM_INTRINSICS_VERSION__ 239 | #define __ICCARM_INTRINSICS_VERSION__ 0 240 | #endif 241 | 242 | #if __ICCARM_INTRINSICS_VERSION__ == 2 243 | 244 | #if defined(__CLZ) 245 | #undef __CLZ 246 | #endif 247 | #if defined(__REVSH) 248 | #undef __REVSH 249 | #endif 250 | #if defined(__RBIT) 251 | #undef __RBIT 252 | #endif 253 | #if defined(__SSAT) 254 | #undef __SSAT 255 | #endif 256 | #if defined(__USAT) 257 | #undef __USAT 258 | #endif 259 | 260 | #include "iccarm_builtin.h" 261 | 262 | #define __disable_fault_irq __iar_builtin_disable_fiq 263 | #define __disable_irq __iar_builtin_disable_interrupt 264 | #define __enable_fault_irq __iar_builtin_enable_fiq 265 | #define __enable_irq __iar_builtin_enable_interrupt 266 | #define __arm_rsr __iar_builtin_rsr 267 | #define __arm_wsr __iar_builtin_wsr 268 | 269 | 270 | #define __get_APSR() (__arm_rsr("APSR")) 271 | #define __get_BASEPRI() (__arm_rsr("BASEPRI")) 272 | #define __get_CONTROL() (__arm_rsr("CONTROL")) 273 | #define __get_FAULTMASK() (__arm_rsr("FAULTMASK")) 274 | 275 | #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ 276 | (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) 277 | #define __get_FPSCR() (__arm_rsr("FPSCR")) 278 | #define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE))) 279 | #else 280 | #define __get_FPSCR() ( 0 ) 281 | #define __set_FPSCR(VALUE) ((void)VALUE) 282 | #endif 283 | 284 | #define __get_IPSR() (__arm_rsr("IPSR")) 285 | #define __get_MSP() (__arm_rsr("MSP")) 286 | #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ 287 | (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) 288 | // without main extensions, the non-secure MSPLIM is RAZ/WI 289 | #define __get_MSPLIM() (0U) 290 | #else 291 | #define __get_MSPLIM() (__arm_rsr("MSPLIM")) 292 | #endif 293 | #define __get_PRIMASK() (__arm_rsr("PRIMASK")) 294 | #define __get_PSP() (__arm_rsr("PSP")) 295 | 296 | #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ 297 | (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) 298 | // without main extensions, the non-secure PSPLIM is RAZ/WI 299 | #define __get_PSPLIM() (0U) 300 | #else 301 | #define __get_PSPLIM() (__arm_rsr("PSPLIM")) 302 | #endif 303 | 304 | #define __get_xPSR() (__arm_rsr("xPSR")) 305 | 306 | #define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE))) 307 | #define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE))) 308 | #define __set_CONTROL(VALUE) (__arm_wsr("CONTROL", (VALUE))) 309 | #define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE))) 310 | #define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE))) 311 | 312 | #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ 313 | (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) 314 | // without main extensions, the non-secure MSPLIM is RAZ/WI 315 | #define __set_MSPLIM(VALUE) ((void)(VALUE)) 316 | #else 317 | #define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE))) 318 | #endif 319 | #define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE))) 320 | #define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE))) 321 | #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ 322 | (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) 323 | // without main extensions, the non-secure PSPLIM is RAZ/WI 324 | #define __set_PSPLIM(VALUE) ((void)(VALUE)) 325 | #else 326 | #define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE))) 327 | #endif 328 | 329 | #define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS")) 330 | #define __TZ_set_CONTROL_NS(VALUE) (__arm_wsr("CONTROL_NS", (VALUE))) 331 | #define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS")) 332 | #define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE))) 333 | #define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS")) 334 | #define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE))) 335 | #define __TZ_get_SP_NS() (__arm_rsr("SP_NS")) 336 | #define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE))) 337 | #define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS")) 338 | #define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE))) 339 | #define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS")) 340 | #define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE))) 341 | #define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS")) 342 | #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE))) 343 | 344 | #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ 345 | (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) 346 | // without main extensions, the non-secure PSPLIM is RAZ/WI 347 | #define __TZ_get_PSPLIM_NS() (0U) 348 | #define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE)) 349 | #else 350 | #define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS")) 351 | #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE))) 352 | #endif 353 | 354 | #define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS")) 355 | #define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE))) 356 | 357 | #define __NOP __iar_builtin_no_operation 358 | 359 | #define __CLZ __iar_builtin_CLZ 360 | #define __CLREX __iar_builtin_CLREX 361 | 362 | #define __DMB __iar_builtin_DMB 363 | #define __DSB __iar_builtin_DSB 364 | #define __ISB __iar_builtin_ISB 365 | 366 | #define __LDREXB __iar_builtin_LDREXB 367 | #define __LDREXH __iar_builtin_LDREXH 368 | #define __LDREXW __iar_builtin_LDREX 369 | 370 | #define __RBIT __iar_builtin_RBIT 371 | #define __REV __iar_builtin_REV 372 | #define __REV16 __iar_builtin_REV16 373 | 374 | __IAR_FT int16_t __REVSH(int16_t val) 375 | { 376 | return (int16_t) __iar_builtin_REVSH(val); 377 | } 378 | 379 | #define __ROR __iar_builtin_ROR 380 | #define __RRX __iar_builtin_RRX 381 | 382 | #define __SEV __iar_builtin_SEV 383 | 384 | #if !__IAR_M0_FAMILY 385 | #define __SSAT __iar_builtin_SSAT 386 | #endif 387 | 388 | #define __STREXB __iar_builtin_STREXB 389 | #define __STREXH __iar_builtin_STREXH 390 | #define __STREXW __iar_builtin_STREX 391 | 392 | #if !__IAR_M0_FAMILY 393 | #define __USAT __iar_builtin_USAT 394 | #endif 395 | 396 | #define __WFE __iar_builtin_WFE 397 | #define __WFI __iar_builtin_WFI 398 | 399 | #if __ARM_MEDIA__ 400 | #define __SADD8 __iar_builtin_SADD8 401 | #define __QADD8 __iar_builtin_QADD8 402 | #define __SHADD8 __iar_builtin_SHADD8 403 | #define __UADD8 __iar_builtin_UADD8 404 | #define __UQADD8 __iar_builtin_UQADD8 405 | #define __UHADD8 __iar_builtin_UHADD8 406 | #define __SSUB8 __iar_builtin_SSUB8 407 | #define __QSUB8 __iar_builtin_QSUB8 408 | #define __SHSUB8 __iar_builtin_SHSUB8 409 | #define __USUB8 __iar_builtin_USUB8 410 | #define __UQSUB8 __iar_builtin_UQSUB8 411 | #define __UHSUB8 __iar_builtin_UHSUB8 412 | #define __SADD16 __iar_builtin_SADD16 413 | #define __QADD16 __iar_builtin_QADD16 414 | #define __SHADD16 __iar_builtin_SHADD16 415 | #define __UADD16 __iar_builtin_UADD16 416 | #define __UQADD16 __iar_builtin_UQADD16 417 | #define __UHADD16 __iar_builtin_UHADD16 418 | #define __SSUB16 __iar_builtin_SSUB16 419 | #define __QSUB16 __iar_builtin_QSUB16 420 | #define __SHSUB16 __iar_builtin_SHSUB16 421 | #define __USUB16 __iar_builtin_USUB16 422 | #define __UQSUB16 __iar_builtin_UQSUB16 423 | #define __UHSUB16 __iar_builtin_UHSUB16 424 | #define __SASX __iar_builtin_SASX 425 | #define __QASX __iar_builtin_QASX 426 | #define __SHASX __iar_builtin_SHASX 427 | #define __UASX __iar_builtin_UASX 428 | #define __UQASX __iar_builtin_UQASX 429 | #define __UHASX __iar_builtin_UHASX 430 | #define __SSAX __iar_builtin_SSAX 431 | #define __QSAX __iar_builtin_QSAX 432 | #define __SHSAX __iar_builtin_SHSAX 433 | #define __USAX __iar_builtin_USAX 434 | #define __UQSAX __iar_builtin_UQSAX 435 | #define __UHSAX __iar_builtin_UHSAX 436 | #define __USAD8 __iar_builtin_USAD8 437 | #define __USADA8 __iar_builtin_USADA8 438 | #define __SSAT16 __iar_builtin_SSAT16 439 | #define __USAT16 __iar_builtin_USAT16 440 | #define __UXTB16 __iar_builtin_UXTB16 441 | #define __UXTAB16 __iar_builtin_UXTAB16 442 | #define __SXTB16 __iar_builtin_SXTB16 443 | #define __SXTAB16 __iar_builtin_SXTAB16 444 | #define __SMUAD __iar_builtin_SMUAD 445 | #define __SMUADX __iar_builtin_SMUADX 446 | #define __SMMLA __iar_builtin_SMMLA 447 | #define __SMLAD __iar_builtin_SMLAD 448 | #define __SMLADX __iar_builtin_SMLADX 449 | #define __SMLALD __iar_builtin_SMLALD 450 | #define __SMLALDX __iar_builtin_SMLALDX 451 | #define __SMUSD __iar_builtin_SMUSD 452 | #define __SMUSDX __iar_builtin_SMUSDX 453 | #define __SMLSD __iar_builtin_SMLSD 454 | #define __SMLSDX __iar_builtin_SMLSDX 455 | #define __SMLSLD __iar_builtin_SMLSLD 456 | #define __SMLSLDX __iar_builtin_SMLSLDX 457 | #define __SEL __iar_builtin_SEL 458 | #define __QADD __iar_builtin_QADD 459 | #define __QSUB __iar_builtin_QSUB 460 | #define __PKHBT __iar_builtin_PKHBT 461 | #define __PKHTB __iar_builtin_PKHTB 462 | #endif 463 | 464 | #else /* __ICCARM_INTRINSICS_VERSION__ == 2 */ 465 | 466 | #if __IAR_M0_FAMILY 467 | /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ 468 | #define __CLZ __cmsis_iar_clz_not_active 469 | #define __SSAT __cmsis_iar_ssat_not_active 470 | #define __USAT __cmsis_iar_usat_not_active 471 | #define __RBIT __cmsis_iar_rbit_not_active 472 | #define __get_APSR __cmsis_iar_get_APSR_not_active 473 | #endif 474 | 475 | 476 | #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ 477 | (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) 478 | #define __get_FPSCR __cmsis_iar_get_FPSR_not_active 479 | #define __set_FPSCR __cmsis_iar_set_FPSR_not_active 480 | #endif 481 | 482 | #ifdef __INTRINSICS_INCLUDED 483 | #error intrinsics.h is already included previously! 484 | #endif 485 | 486 | #include 487 | 488 | #if __IAR_M0_FAMILY 489 | /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ 490 | #undef __CLZ 491 | #undef __SSAT 492 | #undef __USAT 493 | #undef __RBIT 494 | #undef __get_APSR 495 | 496 | __STATIC_INLINE uint8_t __CLZ(uint32_t data) 497 | { 498 | if (data == 0U) { return 32U; } 499 | 500 | uint32_t count = 0U; 501 | uint32_t mask = 0x80000000U; 502 | 503 | while ((data & mask) == 0U) 504 | { 505 | count += 1U; 506 | mask = mask >> 1U; 507 | } 508 | return count; 509 | } 510 | 511 | __STATIC_INLINE uint32_t __RBIT(uint32_t v) 512 | { 513 | uint8_t sc = 31U; 514 | uint32_t r = v; 515 | for (v >>= 1U; v; v >>= 1U) 516 | { 517 | r <<= 1U; 518 | r |= v & 1U; 519 | sc--; 520 | } 521 | return (r << sc); 522 | } 523 | 524 | __STATIC_INLINE uint32_t __get_APSR(void) 525 | { 526 | uint32_t res; 527 | __asm("MRS %0,APSR" : "=r" (res)); 528 | return res; 529 | } 530 | 531 | #endif 532 | 533 | #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ 534 | (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) 535 | #undef __get_FPSCR 536 | #undef __set_FPSCR 537 | #define __get_FPSCR() (0) 538 | #define __set_FPSCR(VALUE) ((void)VALUE) 539 | #endif 540 | 541 | #pragma diag_suppress=Pe940 542 | #pragma diag_suppress=Pe177 543 | 544 | #define __enable_irq __enable_interrupt 545 | #define __disable_irq __disable_interrupt 546 | #define __NOP __no_operation 547 | 548 | #define __get_xPSR __get_PSR 549 | 550 | #if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0) 551 | 552 | __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr) 553 | { 554 | return __LDREX((unsigned long *)ptr); 555 | } 556 | 557 | __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr) 558 | { 559 | return __STREX(value, (unsigned long *)ptr); 560 | } 561 | #endif 562 | 563 | 564 | /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ 565 | #if (__CORTEX_M >= 0x03) 566 | 567 | __IAR_FT uint32_t __RRX(uint32_t value) 568 | { 569 | uint32_t result; 570 | __ASM("RRX %0, %1" : "=r"(result) : "r" (value) : "cc"); 571 | return(result); 572 | } 573 | 574 | __IAR_FT void __set_BASEPRI_MAX(uint32_t value) 575 | { 576 | __asm volatile("MSR BASEPRI_MAX,%0"::"r" (value)); 577 | } 578 | 579 | 580 | #define __enable_fault_irq __enable_fiq 581 | #define __disable_fault_irq __disable_fiq 582 | 583 | 584 | #endif /* (__CORTEX_M >= 0x03) */ 585 | 586 | __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2) 587 | { 588 | return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2)); 589 | } 590 | 591 | #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ 592 | (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) 593 | 594 | __IAR_FT uint32_t __get_MSPLIM(void) 595 | { 596 | uint32_t res; 597 | #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ 598 | (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) 599 | // without main extensions, the non-secure MSPLIM is RAZ/WI 600 | res = 0U; 601 | #else 602 | __asm volatile("MRS %0,MSPLIM" : "=r" (res)); 603 | #endif 604 | return res; 605 | } 606 | 607 | __IAR_FT void __set_MSPLIM(uint32_t value) 608 | { 609 | #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ 610 | (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) 611 | // without main extensions, the non-secure MSPLIM is RAZ/WI 612 | (void)value; 613 | #else 614 | __asm volatile("MSR MSPLIM,%0" :: "r" (value)); 615 | #endif 616 | } 617 | 618 | __IAR_FT uint32_t __get_PSPLIM(void) 619 | { 620 | uint32_t res; 621 | #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ 622 | (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) 623 | // without main extensions, the non-secure PSPLIM is RAZ/WI 624 | res = 0U; 625 | #else 626 | __asm volatile("MRS %0,PSPLIM" : "=r" (res)); 627 | #endif 628 | return res; 629 | } 630 | 631 | __IAR_FT void __set_PSPLIM(uint32_t value) 632 | { 633 | #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ 634 | (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) 635 | // without main extensions, the non-secure PSPLIM is RAZ/WI 636 | (void)value; 637 | #else 638 | __asm volatile("MSR PSPLIM,%0" :: "r" (value)); 639 | #endif 640 | } 641 | 642 | __IAR_FT uint32_t __TZ_get_CONTROL_NS(void) 643 | { 644 | uint32_t res; 645 | __asm volatile("MRS %0,CONTROL_NS" : "=r" (res)); 646 | return res; 647 | } 648 | 649 | __IAR_FT void __TZ_set_CONTROL_NS(uint32_t value) 650 | { 651 | __asm volatile("MSR CONTROL_NS,%0" :: "r" (value)); 652 | } 653 | 654 | __IAR_FT uint32_t __TZ_get_PSP_NS(void) 655 | { 656 | uint32_t res; 657 | __asm volatile("MRS %0,PSP_NS" : "=r" (res)); 658 | return res; 659 | } 660 | 661 | __IAR_FT void __TZ_set_PSP_NS(uint32_t value) 662 | { 663 | __asm volatile("MSR PSP_NS,%0" :: "r" (value)); 664 | } 665 | 666 | __IAR_FT uint32_t __TZ_get_MSP_NS(void) 667 | { 668 | uint32_t res; 669 | __asm volatile("MRS %0,MSP_NS" : "=r" (res)); 670 | return res; 671 | } 672 | 673 | __IAR_FT void __TZ_set_MSP_NS(uint32_t value) 674 | { 675 | __asm volatile("MSR MSP_NS,%0" :: "r" (value)); 676 | } 677 | 678 | __IAR_FT uint32_t __TZ_get_SP_NS(void) 679 | { 680 | uint32_t res; 681 | __asm volatile("MRS %0,SP_NS" : "=r" (res)); 682 | return res; 683 | } 684 | __IAR_FT void __TZ_set_SP_NS(uint32_t value) 685 | { 686 | __asm volatile("MSR SP_NS,%0" :: "r" (value)); 687 | } 688 | 689 | __IAR_FT uint32_t __TZ_get_PRIMASK_NS(void) 690 | { 691 | uint32_t res; 692 | __asm volatile("MRS %0,PRIMASK_NS" : "=r" (res)); 693 | return res; 694 | } 695 | 696 | __IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value) 697 | { 698 | __asm volatile("MSR PRIMASK_NS,%0" :: "r" (value)); 699 | } 700 | 701 | __IAR_FT uint32_t __TZ_get_BASEPRI_NS(void) 702 | { 703 | uint32_t res; 704 | __asm volatile("MRS %0,BASEPRI_NS" : "=r" (res)); 705 | return res; 706 | } 707 | 708 | __IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value) 709 | { 710 | __asm volatile("MSR BASEPRI_NS,%0" :: "r" (value)); 711 | } 712 | 713 | __IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void) 714 | { 715 | uint32_t res; 716 | __asm volatile("MRS %0,FAULTMASK_NS" : "=r" (res)); 717 | return res; 718 | } 719 | 720 | __IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value) 721 | { 722 | __asm volatile("MSR FAULTMASK_NS,%0" :: "r" (value)); 723 | } 724 | 725 | __IAR_FT uint32_t __TZ_get_PSPLIM_NS(void) 726 | { 727 | uint32_t res; 728 | #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ 729 | (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) 730 | // without main extensions, the non-secure PSPLIM is RAZ/WI 731 | res = 0U; 732 | #else 733 | __asm volatile("MRS %0,PSPLIM_NS" : "=r" (res)); 734 | #endif 735 | return res; 736 | } 737 | 738 | __IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value) 739 | { 740 | #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ 741 | (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) 742 | // without main extensions, the non-secure PSPLIM is RAZ/WI 743 | (void)value; 744 | #else 745 | __asm volatile("MSR PSPLIM_NS,%0" :: "r" (value)); 746 | #endif 747 | } 748 | 749 | __IAR_FT uint32_t __TZ_get_MSPLIM_NS(void) 750 | { 751 | uint32_t res; 752 | __asm volatile("MRS %0,MSPLIM_NS" : "=r" (res)); 753 | return res; 754 | } 755 | 756 | __IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value) 757 | { 758 | __asm volatile("MSR MSPLIM_NS,%0" :: "r" (value)); 759 | } 760 | 761 | #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ 762 | 763 | #endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */ 764 | 765 | #define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value)) 766 | 767 | #if __IAR_M0_FAMILY 768 | __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) 769 | { 770 | if ((sat >= 1U) && (sat <= 32U)) 771 | { 772 | const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); 773 | const int32_t min = -1 - max ; 774 | if (val > max) 775 | { 776 | return max; 777 | } 778 | else if (val < min) 779 | { 780 | return min; 781 | } 782 | } 783 | return val; 784 | } 785 | 786 | __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) 787 | { 788 | if (sat <= 31U) 789 | { 790 | const uint32_t max = ((1U << sat) - 1U); 791 | if (val > (int32_t)max) 792 | { 793 | return max; 794 | } 795 | else if (val < 0) 796 | { 797 | return 0U; 798 | } 799 | } 800 | return (uint32_t)val; 801 | } 802 | #endif 803 | 804 | #if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ 805 | 806 | __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr) 807 | { 808 | uint32_t res; 809 | __ASM("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); 810 | return ((uint8_t)res); 811 | } 812 | 813 | __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr) 814 | { 815 | uint32_t res; 816 | __ASM("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); 817 | return ((uint16_t)res); 818 | } 819 | 820 | __IAR_FT uint32_t __LDRT(volatile uint32_t *addr) 821 | { 822 | uint32_t res; 823 | __ASM("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); 824 | return res; 825 | } 826 | 827 | __IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr) 828 | { 829 | __ASM("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); 830 | } 831 | 832 | __IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr) 833 | { 834 | __ASM("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); 835 | } 836 | 837 | __IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr) 838 | { 839 | __ASM("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory"); 840 | } 841 | 842 | #endif /* (__CORTEX_M >= 0x03) */ 843 | 844 | #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ 845 | (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) 846 | 847 | 848 | __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr) 849 | { 850 | uint32_t res; 851 | __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); 852 | return ((uint8_t)res); 853 | } 854 | 855 | __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr) 856 | { 857 | uint32_t res; 858 | __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); 859 | return ((uint16_t)res); 860 | } 861 | 862 | __IAR_FT uint32_t __LDA(volatile uint32_t *ptr) 863 | { 864 | uint32_t res; 865 | __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); 866 | return res; 867 | } 868 | 869 | __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr) 870 | { 871 | __ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); 872 | } 873 | 874 | __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr) 875 | { 876 | __ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); 877 | } 878 | 879 | __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr) 880 | { 881 | __ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); 882 | } 883 | 884 | __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr) 885 | { 886 | uint32_t res; 887 | __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); 888 | return ((uint8_t)res); 889 | } 890 | 891 | __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr) 892 | { 893 | uint32_t res; 894 | __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); 895 | return ((uint16_t)res); 896 | } 897 | 898 | __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr) 899 | { 900 | uint32_t res; 901 | __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); 902 | return res; 903 | } 904 | 905 | __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) 906 | { 907 | uint32_t res; 908 | __ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); 909 | return res; 910 | } 911 | 912 | __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) 913 | { 914 | uint32_t res; 915 | __ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); 916 | return res; 917 | } 918 | 919 | __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) 920 | { 921 | uint32_t res; 922 | __ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); 923 | return res; 924 | } 925 | 926 | #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ 927 | 928 | #undef __IAR_FT 929 | #undef __IAR_M0_FAMILY 930 | #undef __ICCARM_V8 931 | 932 | #pragma diag_default=Pe940 933 | #pragma diag_default=Pe177 934 | 935 | #endif /* __CMSIS_ICCARM_H__ */ 936 | -------------------------------------------------------------------------------- /CMSIS/Include/core_cm0.h: -------------------------------------------------------------------------------- 1 | /**************************************************************************//** 2 | * @file core_cm0.h 3 | * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File 4 | * @version V5.0.5 5 | * @date 28. May 2018 6 | ******************************************************************************/ 7 | /* 8 | * Copyright (c) 2009-2018 Arm Limited. All rights reserved. 9 | * 10 | * SPDX-License-Identifier: Apache-2.0 11 | * 12 | * Licensed under the Apache License, Version 2.0 (the License); you may 13 | * not use this file except in compliance with the License. 14 | * You may obtain a copy of the License at 15 | * 16 | * www.apache.org/licenses/LICENSE-2.0 17 | * 18 | * Unless required by applicable law or agreed to in writing, software 19 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT 20 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21 | * See the License for the specific language governing permissions and 22 | * limitations under the License. 23 | */ 24 | 25 | #if defined ( __ICCARM__ ) 26 | #pragma system_include /* treat file as system include file for MISRA check */ 27 | #elif defined (__clang__) 28 | #pragma clang system_header /* treat file as system include file */ 29 | #endif 30 | 31 | #ifndef __CORE_CM0_H_GENERIC 32 | #define __CORE_CM0_H_GENERIC 33 | 34 | #include 35 | 36 | #ifdef __cplusplus 37 | extern "C" { 38 | #endif 39 | 40 | /** 41 | \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions 42 | CMSIS violates the following MISRA-C:2004 rules: 43 | 44 | \li Required Rule 8.5, object/function definition in header file.
45 | Function definitions in header files are used to allow 'inlining'. 46 | 47 | \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
48 | Unions are used for effective representation of core registers. 49 | 50 | \li Advisory Rule 19.7, Function-like macro defined.
51 | Function-like macros are used to allow more efficient code. 52 | */ 53 | 54 | 55 | /******************************************************************************* 56 | * CMSIS definitions 57 | ******************************************************************************/ 58 | /** 59 | \ingroup Cortex_M0 60 | @{ 61 | */ 62 | 63 | #include "cmsis_version.h" 64 | 65 | /* CMSIS CM0 definitions */ 66 | #define __CM0_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ 67 | #define __CM0_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ 68 | #define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \ 69 | __CM0_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ 70 | 71 | #define __CORTEX_M (0U) /*!< Cortex-M Core */ 72 | 73 | /** __FPU_USED indicates whether an FPU is used or not. 74 | This core does not support an FPU at all 75 | */ 76 | #define __FPU_USED 0U 77 | 78 | #if defined ( __CC_ARM ) 79 | #if defined __TARGET_FPU_VFP 80 | #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 81 | #endif 82 | 83 | #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) 84 | #if defined __ARM_PCS_VFP 85 | #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 86 | #endif 87 | 88 | #elif defined ( __GNUC__ ) 89 | #if defined (__VFP_FP__) && !defined(__SOFTFP__) 90 | #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 91 | #endif 92 | 93 | #elif defined ( __ICCARM__ ) 94 | #if defined __ARMVFP__ 95 | #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 96 | #endif 97 | 98 | #elif defined ( __TI_ARM__ ) 99 | #if defined __TI_VFP_SUPPORT__ 100 | #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 101 | #endif 102 | 103 | #elif defined ( __TASKING__ ) 104 | #if defined __FPU_VFP__ 105 | #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 106 | #endif 107 | 108 | #elif defined ( __CSMC__ ) 109 | #if ( __CSMC__ & 0x400U) 110 | #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 111 | #endif 112 | 113 | #endif 114 | 115 | #include "cmsis_compiler.h" /* CMSIS compiler specific defines */ 116 | 117 | 118 | #ifdef __cplusplus 119 | } 120 | #endif 121 | 122 | #endif /* __CORE_CM0_H_GENERIC */ 123 | 124 | #ifndef __CMSIS_GENERIC 125 | 126 | #ifndef __CORE_CM0_H_DEPENDANT 127 | #define __CORE_CM0_H_DEPENDANT 128 | 129 | #ifdef __cplusplus 130 | extern "C" { 131 | #endif 132 | 133 | /* check device defines and use defaults */ 134 | #if defined __CHECK_DEVICE_DEFINES 135 | #ifndef __CM0_REV 136 | #define __CM0_REV 0x0000U 137 | #warning "__CM0_REV not defined in device header file; using default!" 138 | #endif 139 | 140 | #ifndef __NVIC_PRIO_BITS 141 | #define __NVIC_PRIO_BITS 2U 142 | #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" 143 | #endif 144 | 145 | #ifndef __Vendor_SysTickConfig 146 | #define __Vendor_SysTickConfig 0U 147 | #warning "__Vendor_SysTickConfig not defined in device header file; using default!" 148 | #endif 149 | #endif 150 | 151 | /* IO definitions (access restrictions to peripheral registers) */ 152 | /** 153 | \defgroup CMSIS_glob_defs CMSIS Global Defines 154 | 155 | IO Type Qualifiers are used 156 | \li to specify the access to peripheral variables. 157 | \li for automatic generation of peripheral register debug information. 158 | */ 159 | #ifdef __cplusplus 160 | #define __I volatile /*!< Defines 'read only' permissions */ 161 | #else 162 | #define __I volatile const /*!< Defines 'read only' permissions */ 163 | #endif 164 | #define __O volatile /*!< Defines 'write only' permissions */ 165 | #define __IO volatile /*!< Defines 'read / write' permissions */ 166 | 167 | /* following defines should be used for structure members */ 168 | #define __IM volatile const /*! Defines 'read only' structure member permissions */ 169 | #define __OM volatile /*! Defines 'write only' structure member permissions */ 170 | #define __IOM volatile /*! Defines 'read / write' structure member permissions */ 171 | 172 | /*@} end of group Cortex_M0 */ 173 | 174 | 175 | 176 | /******************************************************************************* 177 | * Register Abstraction 178 | Core Register contain: 179 | - Core Register 180 | - Core NVIC Register 181 | - Core SCB Register 182 | - Core SysTick Register 183 | ******************************************************************************/ 184 | /** 185 | \defgroup CMSIS_core_register Defines and Type Definitions 186 | \brief Type definitions and defines for Cortex-M processor based devices. 187 | */ 188 | 189 | /** 190 | \ingroup CMSIS_core_register 191 | \defgroup CMSIS_CORE Status and Control Registers 192 | \brief Core Register type definitions. 193 | @{ 194 | */ 195 | 196 | /** 197 | \brief Union type to access the Application Program Status Register (APSR). 198 | */ 199 | typedef union 200 | { 201 | struct 202 | { 203 | uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ 204 | uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ 205 | uint32_t C:1; /*!< bit: 29 Carry condition code flag */ 206 | uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ 207 | uint32_t N:1; /*!< bit: 31 Negative condition code flag */ 208 | } b; /*!< Structure used for bit access */ 209 | uint32_t w; /*!< Type used for word access */ 210 | } APSR_Type; 211 | 212 | /* APSR Register Definitions */ 213 | #define APSR_N_Pos 31U /*!< APSR: N Position */ 214 | #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ 215 | 216 | #define APSR_Z_Pos 30U /*!< APSR: Z Position */ 217 | #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ 218 | 219 | #define APSR_C_Pos 29U /*!< APSR: C Position */ 220 | #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ 221 | 222 | #define APSR_V_Pos 28U /*!< APSR: V Position */ 223 | #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ 224 | 225 | 226 | /** 227 | \brief Union type to access the Interrupt Program Status Register (IPSR). 228 | */ 229 | typedef union 230 | { 231 | struct 232 | { 233 | uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ 234 | uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ 235 | } b; /*!< Structure used for bit access */ 236 | uint32_t w; /*!< Type used for word access */ 237 | } IPSR_Type; 238 | 239 | /* IPSR Register Definitions */ 240 | #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ 241 | #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ 242 | 243 | 244 | /** 245 | \brief Union type to access the Special-Purpose Program Status Registers (xPSR). 246 | */ 247 | typedef union 248 | { 249 | struct 250 | { 251 | uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ 252 | uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ 253 | uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ 254 | uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ 255 | uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ 256 | uint32_t C:1; /*!< bit: 29 Carry condition code flag */ 257 | uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ 258 | uint32_t N:1; /*!< bit: 31 Negative condition code flag */ 259 | } b; /*!< Structure used for bit access */ 260 | uint32_t w; /*!< Type used for word access */ 261 | } xPSR_Type; 262 | 263 | /* xPSR Register Definitions */ 264 | #define xPSR_N_Pos 31U /*!< xPSR: N Position */ 265 | #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ 266 | 267 | #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ 268 | #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ 269 | 270 | #define xPSR_C_Pos 29U /*!< xPSR: C Position */ 271 | #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ 272 | 273 | #define xPSR_V_Pos 28U /*!< xPSR: V Position */ 274 | #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ 275 | 276 | #define xPSR_T_Pos 24U /*!< xPSR: T Position */ 277 | #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ 278 | 279 | #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ 280 | #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ 281 | 282 | 283 | /** 284 | \brief Union type to access the Control Registers (CONTROL). 285 | */ 286 | typedef union 287 | { 288 | struct 289 | { 290 | uint32_t _reserved0:1; /*!< bit: 0 Reserved */ 291 | uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ 292 | uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ 293 | } b; /*!< Structure used for bit access */ 294 | uint32_t w; /*!< Type used for word access */ 295 | } CONTROL_Type; 296 | 297 | /* CONTROL Register Definitions */ 298 | #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ 299 | #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ 300 | 301 | /*@} end of group CMSIS_CORE */ 302 | 303 | 304 | /** 305 | \ingroup CMSIS_core_register 306 | \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) 307 | \brief Type definitions for the NVIC Registers 308 | @{ 309 | */ 310 | 311 | /** 312 | \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). 313 | */ 314 | typedef struct 315 | { 316 | __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ 317 | uint32_t RESERVED0[31U]; 318 | __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ 319 | uint32_t RSERVED1[31U]; 320 | __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ 321 | uint32_t RESERVED2[31U]; 322 | __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ 323 | uint32_t RESERVED3[31U]; 324 | uint32_t RESERVED4[64U]; 325 | __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ 326 | } NVIC_Type; 327 | 328 | /*@} end of group CMSIS_NVIC */ 329 | 330 | 331 | /** 332 | \ingroup CMSIS_core_register 333 | \defgroup CMSIS_SCB System Control Block (SCB) 334 | \brief Type definitions for the System Control Block Registers 335 | @{ 336 | */ 337 | 338 | /** 339 | \brief Structure type to access the System Control Block (SCB). 340 | */ 341 | typedef struct 342 | { 343 | __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ 344 | __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ 345 | uint32_t RESERVED0; 346 | __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ 347 | __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ 348 | __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ 349 | uint32_t RESERVED1; 350 | __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ 351 | __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ 352 | } SCB_Type; 353 | 354 | /* SCB CPUID Register Definitions */ 355 | #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ 356 | #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ 357 | 358 | #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ 359 | #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ 360 | 361 | #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ 362 | #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ 363 | 364 | #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ 365 | #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ 366 | 367 | #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ 368 | #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ 369 | 370 | /* SCB Interrupt Control State Register Definitions */ 371 | #define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ 372 | #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ 373 | 374 | #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ 375 | #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ 376 | 377 | #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ 378 | #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ 379 | 380 | #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ 381 | #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ 382 | 383 | #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ 384 | #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ 385 | 386 | #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ 387 | #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ 388 | 389 | #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ 390 | #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ 391 | 392 | #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ 393 | #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ 394 | 395 | #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ 396 | #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ 397 | 398 | /* SCB Application Interrupt and Reset Control Register Definitions */ 399 | #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ 400 | #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ 401 | 402 | #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ 403 | #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ 404 | 405 | #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ 406 | #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ 407 | 408 | #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ 409 | #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ 410 | 411 | #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ 412 | #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ 413 | 414 | /* SCB System Control Register Definitions */ 415 | #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ 416 | #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ 417 | 418 | #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ 419 | #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ 420 | 421 | #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ 422 | #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ 423 | 424 | /* SCB Configuration Control Register Definitions */ 425 | #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ 426 | #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ 427 | 428 | #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ 429 | #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ 430 | 431 | /* SCB System Handler Control and State Register Definitions */ 432 | #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ 433 | #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ 434 | 435 | /*@} end of group CMSIS_SCB */ 436 | 437 | 438 | /** 439 | \ingroup CMSIS_core_register 440 | \defgroup CMSIS_SysTick System Tick Timer (SysTick) 441 | \brief Type definitions for the System Timer Registers. 442 | @{ 443 | */ 444 | 445 | /** 446 | \brief Structure type to access the System Timer (SysTick). 447 | */ 448 | typedef struct 449 | { 450 | __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ 451 | __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ 452 | __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ 453 | __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ 454 | } SysTick_Type; 455 | 456 | /* SysTick Control / Status Register Definitions */ 457 | #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ 458 | #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ 459 | 460 | #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ 461 | #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ 462 | 463 | #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ 464 | #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ 465 | 466 | #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ 467 | #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ 468 | 469 | /* SysTick Reload Register Definitions */ 470 | #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ 471 | #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ 472 | 473 | /* SysTick Current Register Definitions */ 474 | #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ 475 | #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ 476 | 477 | /* SysTick Calibration Register Definitions */ 478 | #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ 479 | #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ 480 | 481 | #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ 482 | #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ 483 | 484 | #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ 485 | #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ 486 | 487 | /*@} end of group CMSIS_SysTick */ 488 | 489 | 490 | /** 491 | \ingroup CMSIS_core_register 492 | \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) 493 | \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. 494 | Therefore they are not covered by the Cortex-M0 header file. 495 | @{ 496 | */ 497 | /*@} end of group CMSIS_CoreDebug */ 498 | 499 | 500 | /** 501 | \ingroup CMSIS_core_register 502 | \defgroup CMSIS_core_bitfield Core register bit field macros 503 | \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). 504 | @{ 505 | */ 506 | 507 | /** 508 | \brief Mask and shift a bit field value for use in a register bit range. 509 | \param[in] field Name of the register bit field. 510 | \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. 511 | \return Masked and shifted value. 512 | */ 513 | #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) 514 | 515 | /** 516 | \brief Mask and shift a register value to extract a bit filed value. 517 | \param[in] field Name of the register bit field. 518 | \param[in] value Value of register. This parameter is interpreted as an uint32_t type. 519 | \return Masked and shifted bit field value. 520 | */ 521 | #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) 522 | 523 | /*@} end of group CMSIS_core_bitfield */ 524 | 525 | 526 | /** 527 | \ingroup CMSIS_core_register 528 | \defgroup CMSIS_core_base Core Definitions 529 | \brief Definitions for base addresses, unions, and structures. 530 | @{ 531 | */ 532 | 533 | /* Memory mapping of Core Hardware */ 534 | #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ 535 | #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ 536 | #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ 537 | #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ 538 | 539 | #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ 540 | #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ 541 | #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ 542 | 543 | 544 | /*@} */ 545 | 546 | 547 | 548 | /******************************************************************************* 549 | * Hardware Abstraction Layer 550 | Core Function Interface contains: 551 | - Core NVIC Functions 552 | - Core SysTick Functions 553 | - Core Register Access Functions 554 | ******************************************************************************/ 555 | /** 556 | \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference 557 | */ 558 | 559 | 560 | 561 | /* ########################## NVIC functions #################################### */ 562 | /** 563 | \ingroup CMSIS_Core_FunctionInterface 564 | \defgroup CMSIS_Core_NVICFunctions NVIC Functions 565 | \brief Functions that manage interrupts and exceptions via the NVIC. 566 | @{ 567 | */ 568 | 569 | #ifdef CMSIS_NVIC_VIRTUAL 570 | #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE 571 | #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" 572 | #endif 573 | #include CMSIS_NVIC_VIRTUAL_HEADER_FILE 574 | #else 575 | #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping 576 | #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping 577 | #define NVIC_EnableIRQ __NVIC_EnableIRQ 578 | #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ 579 | #define NVIC_DisableIRQ __NVIC_DisableIRQ 580 | #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ 581 | #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ 582 | #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ 583 | /*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0 */ 584 | #define NVIC_SetPriority __NVIC_SetPriority 585 | #define NVIC_GetPriority __NVIC_GetPriority 586 | #define NVIC_SystemReset __NVIC_SystemReset 587 | #endif /* CMSIS_NVIC_VIRTUAL */ 588 | 589 | #ifdef CMSIS_VECTAB_VIRTUAL 590 | #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE 591 | #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" 592 | #endif 593 | #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE 594 | #else 595 | #define NVIC_SetVector __NVIC_SetVector 596 | #define NVIC_GetVector __NVIC_GetVector 597 | #endif /* (CMSIS_VECTAB_VIRTUAL) */ 598 | 599 | #define NVIC_USER_IRQ_OFFSET 16 600 | 601 | 602 | /* The following EXC_RETURN values are saved the LR on exception entry */ 603 | #define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ 604 | #define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ 605 | #define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ 606 | 607 | 608 | /* Interrupt Priorities are WORD accessible only under Armv6-M */ 609 | /* The following MACROS handle generation of the register offset and byte masks */ 610 | #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) 611 | #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) 612 | #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) 613 | 614 | #define __NVIC_SetPriorityGrouping(X) (void)(X) 615 | #define __NVIC_GetPriorityGrouping() (0U) 616 | 617 | /** 618 | \brief Enable Interrupt 619 | \details Enables a device specific interrupt in the NVIC interrupt controller. 620 | \param [in] IRQn Device specific interrupt number. 621 | \note IRQn must not be negative. 622 | */ 623 | __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) 624 | { 625 | if ((int32_t)(IRQn) >= 0) 626 | { 627 | NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 628 | } 629 | } 630 | 631 | 632 | /** 633 | \brief Get Interrupt Enable status 634 | \details Returns a device specific interrupt enable status from the NVIC interrupt controller. 635 | \param [in] IRQn Device specific interrupt number. 636 | \return 0 Interrupt is not enabled. 637 | \return 1 Interrupt is enabled. 638 | \note IRQn must not be negative. 639 | */ 640 | __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) 641 | { 642 | if ((int32_t)(IRQn) >= 0) 643 | { 644 | return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); 645 | } 646 | else 647 | { 648 | return(0U); 649 | } 650 | } 651 | 652 | 653 | /** 654 | \brief Disable Interrupt 655 | \details Disables a device specific interrupt in the NVIC interrupt controller. 656 | \param [in] IRQn Device specific interrupt number. 657 | \note IRQn must not be negative. 658 | */ 659 | __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) 660 | { 661 | if ((int32_t)(IRQn) >= 0) 662 | { 663 | NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 664 | __DSB(); 665 | __ISB(); 666 | } 667 | } 668 | 669 | 670 | /** 671 | \brief Get Pending Interrupt 672 | \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. 673 | \param [in] IRQn Device specific interrupt number. 674 | \return 0 Interrupt status is not pending. 675 | \return 1 Interrupt status is pending. 676 | \note IRQn must not be negative. 677 | */ 678 | __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) 679 | { 680 | if ((int32_t)(IRQn) >= 0) 681 | { 682 | return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); 683 | } 684 | else 685 | { 686 | return(0U); 687 | } 688 | } 689 | 690 | 691 | /** 692 | \brief Set Pending Interrupt 693 | \details Sets the pending bit of a device specific interrupt in the NVIC pending register. 694 | \param [in] IRQn Device specific interrupt number. 695 | \note IRQn must not be negative. 696 | */ 697 | __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) 698 | { 699 | if ((int32_t)(IRQn) >= 0) 700 | { 701 | NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 702 | } 703 | } 704 | 705 | 706 | /** 707 | \brief Clear Pending Interrupt 708 | \details Clears the pending bit of a device specific interrupt in the NVIC pending register. 709 | \param [in] IRQn Device specific interrupt number. 710 | \note IRQn must not be negative. 711 | */ 712 | __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) 713 | { 714 | if ((int32_t)(IRQn) >= 0) 715 | { 716 | NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 717 | } 718 | } 719 | 720 | 721 | /** 722 | \brief Set Interrupt Priority 723 | \details Sets the priority of a device specific interrupt or a processor exception. 724 | The interrupt number can be positive to specify a device specific interrupt, 725 | or negative to specify a processor exception. 726 | \param [in] IRQn Interrupt number. 727 | \param [in] priority Priority to set. 728 | \note The priority cannot be set for every processor exception. 729 | */ 730 | __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) 731 | { 732 | if ((int32_t)(IRQn) >= 0) 733 | { 734 | NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | 735 | (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); 736 | } 737 | else 738 | { 739 | SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | 740 | (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); 741 | } 742 | } 743 | 744 | 745 | /** 746 | \brief Get Interrupt Priority 747 | \details Reads the priority of a device specific interrupt or a processor exception. 748 | The interrupt number can be positive to specify a device specific interrupt, 749 | or negative to specify a processor exception. 750 | \param [in] IRQn Interrupt number. 751 | \return Interrupt Priority. 752 | Value is aligned automatically to the implemented priority bits of the microcontroller. 753 | */ 754 | __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) 755 | { 756 | 757 | if ((int32_t)(IRQn) >= 0) 758 | { 759 | return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); 760 | } 761 | else 762 | { 763 | return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); 764 | } 765 | } 766 | 767 | 768 | /** 769 | \brief Encode Priority 770 | \details Encodes the priority for an interrupt with the given priority group, 771 | preemptive priority value, and subpriority value. 772 | In case of a conflict between priority grouping and available 773 | priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. 774 | \param [in] PriorityGroup Used priority group. 775 | \param [in] PreemptPriority Preemptive priority value (starting from 0). 776 | \param [in] SubPriority Subpriority value (starting from 0). 777 | \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). 778 | */ 779 | __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) 780 | { 781 | uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 782 | uint32_t PreemptPriorityBits; 783 | uint32_t SubPriorityBits; 784 | 785 | PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); 786 | SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); 787 | 788 | return ( 789 | ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 790 | ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) 791 | ); 792 | } 793 | 794 | 795 | /** 796 | \brief Decode Priority 797 | \details Decodes an interrupt priority value with a given priority group to 798 | preemptive priority value and subpriority value. 799 | In case of a conflict between priority grouping and available 800 | priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. 801 | \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). 802 | \param [in] PriorityGroup Used priority group. 803 | \param [out] pPreemptPriority Preemptive priority value (starting from 0). 804 | \param [out] pSubPriority Subpriority value (starting from 0). 805 | */ 806 | __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) 807 | { 808 | uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 809 | uint32_t PreemptPriorityBits; 810 | uint32_t SubPriorityBits; 811 | 812 | PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); 813 | SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); 814 | 815 | *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); 816 | *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); 817 | } 818 | 819 | 820 | 821 | /** 822 | \brief Set Interrupt Vector 823 | \details Sets an interrupt vector in SRAM based interrupt vector table. 824 | The interrupt number can be positive to specify a device specific interrupt, 825 | or negative to specify a processor exception. 826 | Address 0 must be mapped to SRAM. 827 | \param [in] IRQn Interrupt number 828 | \param [in] vector Address of interrupt handler function 829 | */ 830 | __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) 831 | { 832 | uint32_t *vectors = (uint32_t *)0x0U; 833 | vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; 834 | } 835 | 836 | 837 | /** 838 | \brief Get Interrupt Vector 839 | \details Reads an interrupt vector from interrupt vector table. 840 | The interrupt number can be positive to specify a device specific interrupt, 841 | or negative to specify a processor exception. 842 | \param [in] IRQn Interrupt number. 843 | \return Address of interrupt handler function 844 | */ 845 | __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) 846 | { 847 | uint32_t *vectors = (uint32_t *)0x0U; 848 | return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; 849 | } 850 | 851 | 852 | /** 853 | \brief System Reset 854 | \details Initiates a system reset request to reset the MCU. 855 | */ 856 | __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) 857 | { 858 | __DSB(); /* Ensure all outstanding memory accesses included 859 | buffered write are completed before reset */ 860 | SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 861 | SCB_AIRCR_SYSRESETREQ_Msk); 862 | __DSB(); /* Ensure completion of memory access */ 863 | 864 | for(;;) /* wait until reset */ 865 | { 866 | __NOP(); 867 | } 868 | } 869 | 870 | /*@} end of CMSIS_Core_NVICFunctions */ 871 | 872 | 873 | /* ########################## FPU functions #################################### */ 874 | /** 875 | \ingroup CMSIS_Core_FunctionInterface 876 | \defgroup CMSIS_Core_FpuFunctions FPU Functions 877 | \brief Function that provides FPU type. 878 | @{ 879 | */ 880 | 881 | /** 882 | \brief get FPU type 883 | \details returns the FPU type 884 | \returns 885 | - \b 0: No FPU 886 | - \b 1: Single precision FPU 887 | - \b 2: Double + Single precision FPU 888 | */ 889 | __STATIC_INLINE uint32_t SCB_GetFPUType(void) 890 | { 891 | return 0U; /* No FPU */ 892 | } 893 | 894 | 895 | /*@} end of CMSIS_Core_FpuFunctions */ 896 | 897 | 898 | 899 | /* ################################## SysTick function ############################################ */ 900 | /** 901 | \ingroup CMSIS_Core_FunctionInterface 902 | \defgroup CMSIS_Core_SysTickFunctions SysTick Functions 903 | \brief Functions that configure the System. 904 | @{ 905 | */ 906 | 907 | #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) 908 | 909 | /** 910 | \brief System Tick Configuration 911 | \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. 912 | Counter is in free running mode to generate periodic interrupts. 913 | \param [in] ticks Number of ticks between two interrupts. 914 | \return 0 Function succeeded. 915 | \return 1 Function failed. 916 | \note When the variable __Vendor_SysTickConfig is set to 1, then the 917 | function SysTick_Config is not included. In this case, the file device.h 918 | must contain a vendor-specific implementation of this function. 919 | */ 920 | __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) 921 | { 922 | if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) 923 | { 924 | return (1UL); /* Reload value impossible */ 925 | } 926 | 927 | SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ 928 | NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ 929 | SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ 930 | SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | 931 | SysTick_CTRL_TICKINT_Msk | 932 | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ 933 | return (0UL); /* Function successful */ 934 | } 935 | 936 | #endif 937 | 938 | /*@} end of CMSIS_Core_SysTickFunctions */ 939 | 940 | 941 | 942 | 943 | #ifdef __cplusplus 944 | } 945 | #endif 946 | 947 | #endif /* __CORE_CM0_H_DEPENDANT */ 948 | 949 | #endif /* __CMSIS_GENERIC */ 950 | -------------------------------------------------------------------------------- /CMSIS/Include/core_cm1.h: -------------------------------------------------------------------------------- 1 | /**************************************************************************//** 2 | * @file core_cm1.h 3 | * @brief CMSIS Cortex-M1 Core Peripheral Access Layer Header File 4 | * @version V1.0.0 5 | * @date 23. July 2018 6 | ******************************************************************************/ 7 | /* 8 | * Copyright (c) 2009-2018 Arm Limited. All rights reserved. 9 | * 10 | * SPDX-License-Identifier: Apache-2.0 11 | * 12 | * Licensed under the Apache License, Version 2.0 (the License); you may 13 | * not use this file except in compliance with the License. 14 | * You may obtain a copy of the License at 15 | * 16 | * www.apache.org/licenses/LICENSE-2.0 17 | * 18 | * Unless required by applicable law or agreed to in writing, software 19 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT 20 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21 | * See the License for the specific language governing permissions and 22 | * limitations under the License. 23 | */ 24 | 25 | #if defined ( __ICCARM__ ) 26 | #pragma system_include /* treat file as system include file for MISRA check */ 27 | #elif defined (__clang__) 28 | #pragma clang system_header /* treat file as system include file */ 29 | #endif 30 | 31 | #ifndef __CORE_CM1_H_GENERIC 32 | #define __CORE_CM1_H_GENERIC 33 | 34 | #include 35 | 36 | #ifdef __cplusplus 37 | extern "C" { 38 | #endif 39 | 40 | /** 41 | \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions 42 | CMSIS violates the following MISRA-C:2004 rules: 43 | 44 | \li Required Rule 8.5, object/function definition in header file.
45 | Function definitions in header files are used to allow 'inlining'. 46 | 47 | \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
48 | Unions are used for effective representation of core registers. 49 | 50 | \li Advisory Rule 19.7, Function-like macro defined.
51 | Function-like macros are used to allow more efficient code. 52 | */ 53 | 54 | 55 | /******************************************************************************* 56 | * CMSIS definitions 57 | ******************************************************************************/ 58 | /** 59 | \ingroup Cortex_M1 60 | @{ 61 | */ 62 | 63 | #include "cmsis_version.h" 64 | 65 | /* CMSIS CM1 definitions */ 66 | #define __CM1_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ 67 | #define __CM1_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ 68 | #define __CM1_CMSIS_VERSION ((__CM1_CMSIS_VERSION_MAIN << 16U) | \ 69 | __CM1_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ 70 | 71 | #define __CORTEX_M (1U) /*!< Cortex-M Core */ 72 | 73 | /** __FPU_USED indicates whether an FPU is used or not. 74 | This core does not support an FPU at all 75 | */ 76 | #define __FPU_USED 0U 77 | 78 | #if defined ( __CC_ARM ) 79 | #if defined __TARGET_FPU_VFP 80 | #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 81 | #endif 82 | 83 | #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) 84 | #if defined __ARM_PCS_VFP 85 | #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 86 | #endif 87 | 88 | #elif defined ( __GNUC__ ) 89 | #if defined (__VFP_FP__) && !defined(__SOFTFP__) 90 | #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 91 | #endif 92 | 93 | #elif defined ( __ICCARM__ ) 94 | #if defined __ARMVFP__ 95 | #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 96 | #endif 97 | 98 | #elif defined ( __TI_ARM__ ) 99 | #if defined __TI_VFP_SUPPORT__ 100 | #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 101 | #endif 102 | 103 | #elif defined ( __TASKING__ ) 104 | #if defined __FPU_VFP__ 105 | #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 106 | #endif 107 | 108 | #elif defined ( __CSMC__ ) 109 | #if ( __CSMC__ & 0x400U) 110 | #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 111 | #endif 112 | 113 | #endif 114 | 115 | #include "cmsis_compiler.h" /* CMSIS compiler specific defines */ 116 | 117 | 118 | #ifdef __cplusplus 119 | } 120 | #endif 121 | 122 | #endif /* __CORE_CM1_H_GENERIC */ 123 | 124 | #ifndef __CMSIS_GENERIC 125 | 126 | #ifndef __CORE_CM1_H_DEPENDANT 127 | #define __CORE_CM1_H_DEPENDANT 128 | 129 | #ifdef __cplusplus 130 | extern "C" { 131 | #endif 132 | 133 | /* check device defines and use defaults */ 134 | #if defined __CHECK_DEVICE_DEFINES 135 | #ifndef __CM1_REV 136 | #define __CM1_REV 0x0100U 137 | #warning "__CM1_REV not defined in device header file; using default!" 138 | #endif 139 | 140 | #ifndef __NVIC_PRIO_BITS 141 | #define __NVIC_PRIO_BITS 2U 142 | #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" 143 | #endif 144 | 145 | #ifndef __Vendor_SysTickConfig 146 | #define __Vendor_SysTickConfig 0U 147 | #warning "__Vendor_SysTickConfig not defined in device header file; using default!" 148 | #endif 149 | #endif 150 | 151 | /* IO definitions (access restrictions to peripheral registers) */ 152 | /** 153 | \defgroup CMSIS_glob_defs CMSIS Global Defines 154 | 155 | IO Type Qualifiers are used 156 | \li to specify the access to peripheral variables. 157 | \li for automatic generation of peripheral register debug information. 158 | */ 159 | #ifdef __cplusplus 160 | #define __I volatile /*!< Defines 'read only' permissions */ 161 | #else 162 | #define __I volatile const /*!< Defines 'read only' permissions */ 163 | #endif 164 | #define __O volatile /*!< Defines 'write only' permissions */ 165 | #define __IO volatile /*!< Defines 'read / write' permissions */ 166 | 167 | /* following defines should be used for structure members */ 168 | #define __IM volatile const /*! Defines 'read only' structure member permissions */ 169 | #define __OM volatile /*! Defines 'write only' structure member permissions */ 170 | #define __IOM volatile /*! Defines 'read / write' structure member permissions */ 171 | 172 | /*@} end of group Cortex_M1 */ 173 | 174 | 175 | 176 | /******************************************************************************* 177 | * Register Abstraction 178 | Core Register contain: 179 | - Core Register 180 | - Core NVIC Register 181 | - Core SCB Register 182 | - Core SysTick Register 183 | ******************************************************************************/ 184 | /** 185 | \defgroup CMSIS_core_register Defines and Type Definitions 186 | \brief Type definitions and defines for Cortex-M processor based devices. 187 | */ 188 | 189 | /** 190 | \ingroup CMSIS_core_register 191 | \defgroup CMSIS_CORE Status and Control Registers 192 | \brief Core Register type definitions. 193 | @{ 194 | */ 195 | 196 | /** 197 | \brief Union type to access the Application Program Status Register (APSR). 198 | */ 199 | typedef union 200 | { 201 | struct 202 | { 203 | uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ 204 | uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ 205 | uint32_t C:1; /*!< bit: 29 Carry condition code flag */ 206 | uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ 207 | uint32_t N:1; /*!< bit: 31 Negative condition code flag */ 208 | } b; /*!< Structure used for bit access */ 209 | uint32_t w; /*!< Type used for word access */ 210 | } APSR_Type; 211 | 212 | /* APSR Register Definitions */ 213 | #define APSR_N_Pos 31U /*!< APSR: N Position */ 214 | #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ 215 | 216 | #define APSR_Z_Pos 30U /*!< APSR: Z Position */ 217 | #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ 218 | 219 | #define APSR_C_Pos 29U /*!< APSR: C Position */ 220 | #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ 221 | 222 | #define APSR_V_Pos 28U /*!< APSR: V Position */ 223 | #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ 224 | 225 | 226 | /** 227 | \brief Union type to access the Interrupt Program Status Register (IPSR). 228 | */ 229 | typedef union 230 | { 231 | struct 232 | { 233 | uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ 234 | uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ 235 | } b; /*!< Structure used for bit access */ 236 | uint32_t w; /*!< Type used for word access */ 237 | } IPSR_Type; 238 | 239 | /* IPSR Register Definitions */ 240 | #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ 241 | #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ 242 | 243 | 244 | /** 245 | \brief Union type to access the Special-Purpose Program Status Registers (xPSR). 246 | */ 247 | typedef union 248 | { 249 | struct 250 | { 251 | uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ 252 | uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ 253 | uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ 254 | uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ 255 | uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ 256 | uint32_t C:1; /*!< bit: 29 Carry condition code flag */ 257 | uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ 258 | uint32_t N:1; /*!< bit: 31 Negative condition code flag */ 259 | } b; /*!< Structure used for bit access */ 260 | uint32_t w; /*!< Type used for word access */ 261 | } xPSR_Type; 262 | 263 | /* xPSR Register Definitions */ 264 | #define xPSR_N_Pos 31U /*!< xPSR: N Position */ 265 | #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ 266 | 267 | #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ 268 | #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ 269 | 270 | #define xPSR_C_Pos 29U /*!< xPSR: C Position */ 271 | #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ 272 | 273 | #define xPSR_V_Pos 28U /*!< xPSR: V Position */ 274 | #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ 275 | 276 | #define xPSR_T_Pos 24U /*!< xPSR: T Position */ 277 | #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ 278 | 279 | #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ 280 | #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ 281 | 282 | 283 | /** 284 | \brief Union type to access the Control Registers (CONTROL). 285 | */ 286 | typedef union 287 | { 288 | struct 289 | { 290 | uint32_t _reserved0:1; /*!< bit: 0 Reserved */ 291 | uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ 292 | uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ 293 | } b; /*!< Structure used for bit access */ 294 | uint32_t w; /*!< Type used for word access */ 295 | } CONTROL_Type; 296 | 297 | /* CONTROL Register Definitions */ 298 | #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ 299 | #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ 300 | 301 | /*@} end of group CMSIS_CORE */ 302 | 303 | 304 | /** 305 | \ingroup CMSIS_core_register 306 | \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) 307 | \brief Type definitions for the NVIC Registers 308 | @{ 309 | */ 310 | 311 | /** 312 | \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). 313 | */ 314 | typedef struct 315 | { 316 | __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ 317 | uint32_t RESERVED0[31U]; 318 | __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ 319 | uint32_t RSERVED1[31U]; 320 | __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ 321 | uint32_t RESERVED2[31U]; 322 | __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ 323 | uint32_t RESERVED3[31U]; 324 | uint32_t RESERVED4[64U]; 325 | __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ 326 | } NVIC_Type; 327 | 328 | /*@} end of group CMSIS_NVIC */ 329 | 330 | 331 | /** 332 | \ingroup CMSIS_core_register 333 | \defgroup CMSIS_SCB System Control Block (SCB) 334 | \brief Type definitions for the System Control Block Registers 335 | @{ 336 | */ 337 | 338 | /** 339 | \brief Structure type to access the System Control Block (SCB). 340 | */ 341 | typedef struct 342 | { 343 | __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ 344 | __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ 345 | uint32_t RESERVED0; 346 | __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ 347 | __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ 348 | __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ 349 | uint32_t RESERVED1; 350 | __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ 351 | __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ 352 | } SCB_Type; 353 | 354 | /* SCB CPUID Register Definitions */ 355 | #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ 356 | #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ 357 | 358 | #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ 359 | #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ 360 | 361 | #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ 362 | #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ 363 | 364 | #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ 365 | #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ 366 | 367 | #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ 368 | #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ 369 | 370 | /* SCB Interrupt Control State Register Definitions */ 371 | #define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ 372 | #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ 373 | 374 | #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ 375 | #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ 376 | 377 | #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ 378 | #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ 379 | 380 | #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ 381 | #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ 382 | 383 | #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ 384 | #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ 385 | 386 | #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ 387 | #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ 388 | 389 | #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ 390 | #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ 391 | 392 | #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ 393 | #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ 394 | 395 | #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ 396 | #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ 397 | 398 | /* SCB Application Interrupt and Reset Control Register Definitions */ 399 | #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ 400 | #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ 401 | 402 | #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ 403 | #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ 404 | 405 | #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ 406 | #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ 407 | 408 | #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ 409 | #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ 410 | 411 | #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ 412 | #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ 413 | 414 | /* SCB System Control Register Definitions */ 415 | #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ 416 | #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ 417 | 418 | #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ 419 | #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ 420 | 421 | #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ 422 | #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ 423 | 424 | /* SCB Configuration Control Register Definitions */ 425 | #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ 426 | #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ 427 | 428 | #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ 429 | #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ 430 | 431 | /* SCB System Handler Control and State Register Definitions */ 432 | #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ 433 | #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ 434 | 435 | /*@} end of group CMSIS_SCB */ 436 | 437 | 438 | /** 439 | \ingroup CMSIS_core_register 440 | \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) 441 | \brief Type definitions for the System Control and ID Register not in the SCB 442 | @{ 443 | */ 444 | 445 | /** 446 | \brief Structure type to access the System Control and ID Register not in the SCB. 447 | */ 448 | typedef struct 449 | { 450 | uint32_t RESERVED0[2U]; 451 | __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ 452 | } SCnSCB_Type; 453 | 454 | /* Auxiliary Control Register Definitions */ 455 | #define SCnSCB_ACTLR_ITCMUAEN_Pos 4U /*!< ACTLR: Instruction TCM Upper Alias Enable Position */ 456 | #define SCnSCB_ACTLR_ITCMUAEN_Msk (1UL << SCnSCB_ACTLR_ITCMUAEN_Pos) /*!< ACTLR: Instruction TCM Upper Alias Enable Mask */ 457 | 458 | #define SCnSCB_ACTLR_ITCMLAEN_Pos 3U /*!< ACTLR: Instruction TCM Lower Alias Enable Position */ 459 | #define SCnSCB_ACTLR_ITCMLAEN_Msk (1UL << SCnSCB_ACTLR_ITCMLAEN_Pos) /*!< ACTLR: Instruction TCM Lower Alias Enable Mask */ 460 | 461 | /*@} end of group CMSIS_SCnotSCB */ 462 | 463 | 464 | /** 465 | \ingroup CMSIS_core_register 466 | \defgroup CMSIS_SysTick System Tick Timer (SysTick) 467 | \brief Type definitions for the System Timer Registers. 468 | @{ 469 | */ 470 | 471 | /** 472 | \brief Structure type to access the System Timer (SysTick). 473 | */ 474 | typedef struct 475 | { 476 | __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ 477 | __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ 478 | __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ 479 | __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ 480 | } SysTick_Type; 481 | 482 | /* SysTick Control / Status Register Definitions */ 483 | #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ 484 | #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ 485 | 486 | #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ 487 | #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ 488 | 489 | #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ 490 | #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ 491 | 492 | #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ 493 | #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ 494 | 495 | /* SysTick Reload Register Definitions */ 496 | #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ 497 | #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ 498 | 499 | /* SysTick Current Register Definitions */ 500 | #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ 501 | #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ 502 | 503 | /* SysTick Calibration Register Definitions */ 504 | #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ 505 | #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ 506 | 507 | #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ 508 | #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ 509 | 510 | #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ 511 | #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ 512 | 513 | /*@} end of group CMSIS_SysTick */ 514 | 515 | 516 | /** 517 | \ingroup CMSIS_core_register 518 | \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) 519 | \brief Cortex-M1 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. 520 | Therefore they are not covered by the Cortex-M1 header file. 521 | @{ 522 | */ 523 | /*@} end of group CMSIS_CoreDebug */ 524 | 525 | 526 | /** 527 | \ingroup CMSIS_core_register 528 | \defgroup CMSIS_core_bitfield Core register bit field macros 529 | \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). 530 | @{ 531 | */ 532 | 533 | /** 534 | \brief Mask and shift a bit field value for use in a register bit range. 535 | \param[in] field Name of the register bit field. 536 | \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. 537 | \return Masked and shifted value. 538 | */ 539 | #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) 540 | 541 | /** 542 | \brief Mask and shift a register value to extract a bit filed value. 543 | \param[in] field Name of the register bit field. 544 | \param[in] value Value of register. This parameter is interpreted as an uint32_t type. 545 | \return Masked and shifted bit field value. 546 | */ 547 | #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) 548 | 549 | /*@} end of group CMSIS_core_bitfield */ 550 | 551 | 552 | /** 553 | \ingroup CMSIS_core_register 554 | \defgroup CMSIS_core_base Core Definitions 555 | \brief Definitions for base addresses, unions, and structures. 556 | @{ 557 | */ 558 | 559 | /* Memory mapping of Core Hardware */ 560 | #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ 561 | #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ 562 | #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ 563 | #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ 564 | 565 | #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ 566 | #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ 567 | #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ 568 | #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ 569 | 570 | 571 | /*@} */ 572 | 573 | 574 | 575 | /******************************************************************************* 576 | * Hardware Abstraction Layer 577 | Core Function Interface contains: 578 | - Core NVIC Functions 579 | - Core SysTick Functions 580 | - Core Register Access Functions 581 | ******************************************************************************/ 582 | /** 583 | \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference 584 | */ 585 | 586 | 587 | 588 | /* ########################## NVIC functions #################################### */ 589 | /** 590 | \ingroup CMSIS_Core_FunctionInterface 591 | \defgroup CMSIS_Core_NVICFunctions NVIC Functions 592 | \brief Functions that manage interrupts and exceptions via the NVIC. 593 | @{ 594 | */ 595 | 596 | #ifdef CMSIS_NVIC_VIRTUAL 597 | #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE 598 | #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" 599 | #endif 600 | #include CMSIS_NVIC_VIRTUAL_HEADER_FILE 601 | #else 602 | #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping 603 | #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping 604 | #define NVIC_EnableIRQ __NVIC_EnableIRQ 605 | #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ 606 | #define NVIC_DisableIRQ __NVIC_DisableIRQ 607 | #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ 608 | #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ 609 | #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ 610 | /*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M1 */ 611 | #define NVIC_SetPriority __NVIC_SetPriority 612 | #define NVIC_GetPriority __NVIC_GetPriority 613 | #define NVIC_SystemReset __NVIC_SystemReset 614 | #endif /* CMSIS_NVIC_VIRTUAL */ 615 | 616 | #ifdef CMSIS_VECTAB_VIRTUAL 617 | #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE 618 | #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" 619 | #endif 620 | #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE 621 | #else 622 | #define NVIC_SetVector __NVIC_SetVector 623 | #define NVIC_GetVector __NVIC_GetVector 624 | #endif /* (CMSIS_VECTAB_VIRTUAL) */ 625 | 626 | #define NVIC_USER_IRQ_OFFSET 16 627 | 628 | 629 | /* The following EXC_RETURN values are saved the LR on exception entry */ 630 | #define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ 631 | #define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ 632 | #define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ 633 | 634 | 635 | /* Interrupt Priorities are WORD accessible only under Armv6-M */ 636 | /* The following MACROS handle generation of the register offset and byte masks */ 637 | #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) 638 | #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) 639 | #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) 640 | 641 | #define __NVIC_SetPriorityGrouping(X) (void)(X) 642 | #define __NVIC_GetPriorityGrouping() (0U) 643 | 644 | /** 645 | \brief Enable Interrupt 646 | \details Enables a device specific interrupt in the NVIC interrupt controller. 647 | \param [in] IRQn Device specific interrupt number. 648 | \note IRQn must not be negative. 649 | */ 650 | __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) 651 | { 652 | if ((int32_t)(IRQn) >= 0) 653 | { 654 | NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 655 | } 656 | } 657 | 658 | 659 | /** 660 | \brief Get Interrupt Enable status 661 | \details Returns a device specific interrupt enable status from the NVIC interrupt controller. 662 | \param [in] IRQn Device specific interrupt number. 663 | \return 0 Interrupt is not enabled. 664 | \return 1 Interrupt is enabled. 665 | \note IRQn must not be negative. 666 | */ 667 | __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) 668 | { 669 | if ((int32_t)(IRQn) >= 0) 670 | { 671 | return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); 672 | } 673 | else 674 | { 675 | return(0U); 676 | } 677 | } 678 | 679 | 680 | /** 681 | \brief Disable Interrupt 682 | \details Disables a device specific interrupt in the NVIC interrupt controller. 683 | \param [in] IRQn Device specific interrupt number. 684 | \note IRQn must not be negative. 685 | */ 686 | __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) 687 | { 688 | if ((int32_t)(IRQn) >= 0) 689 | { 690 | NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 691 | __DSB(); 692 | __ISB(); 693 | } 694 | } 695 | 696 | 697 | /** 698 | \brief Get Pending Interrupt 699 | \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. 700 | \param [in] IRQn Device specific interrupt number. 701 | \return 0 Interrupt status is not pending. 702 | \return 1 Interrupt status is pending. 703 | \note IRQn must not be negative. 704 | */ 705 | __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) 706 | { 707 | if ((int32_t)(IRQn) >= 0) 708 | { 709 | return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); 710 | } 711 | else 712 | { 713 | return(0U); 714 | } 715 | } 716 | 717 | 718 | /** 719 | \brief Set Pending Interrupt 720 | \details Sets the pending bit of a device specific interrupt in the NVIC pending register. 721 | \param [in] IRQn Device specific interrupt number. 722 | \note IRQn must not be negative. 723 | */ 724 | __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) 725 | { 726 | if ((int32_t)(IRQn) >= 0) 727 | { 728 | NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 729 | } 730 | } 731 | 732 | 733 | /** 734 | \brief Clear Pending Interrupt 735 | \details Clears the pending bit of a device specific interrupt in the NVIC pending register. 736 | \param [in] IRQn Device specific interrupt number. 737 | \note IRQn must not be negative. 738 | */ 739 | __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) 740 | { 741 | if ((int32_t)(IRQn) >= 0) 742 | { 743 | NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 744 | } 745 | } 746 | 747 | 748 | /** 749 | \brief Set Interrupt Priority 750 | \details Sets the priority of a device specific interrupt or a processor exception. 751 | The interrupt number can be positive to specify a device specific interrupt, 752 | or negative to specify a processor exception. 753 | \param [in] IRQn Interrupt number. 754 | \param [in] priority Priority to set. 755 | \note The priority cannot be set for every processor exception. 756 | */ 757 | __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) 758 | { 759 | if ((int32_t)(IRQn) >= 0) 760 | { 761 | NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | 762 | (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); 763 | } 764 | else 765 | { 766 | SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | 767 | (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); 768 | } 769 | } 770 | 771 | 772 | /** 773 | \brief Get Interrupt Priority 774 | \details Reads the priority of a device specific interrupt or a processor exception. 775 | The interrupt number can be positive to specify a device specific interrupt, 776 | or negative to specify a processor exception. 777 | \param [in] IRQn Interrupt number. 778 | \return Interrupt Priority. 779 | Value is aligned automatically to the implemented priority bits of the microcontroller. 780 | */ 781 | __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) 782 | { 783 | 784 | if ((int32_t)(IRQn) >= 0) 785 | { 786 | return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); 787 | } 788 | else 789 | { 790 | return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); 791 | } 792 | } 793 | 794 | 795 | /** 796 | \brief Encode Priority 797 | \details Encodes the priority for an interrupt with the given priority group, 798 | preemptive priority value, and subpriority value. 799 | In case of a conflict between priority grouping and available 800 | priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. 801 | \param [in] PriorityGroup Used priority group. 802 | \param [in] PreemptPriority Preemptive priority value (starting from 0). 803 | \param [in] SubPriority Subpriority value (starting from 0). 804 | \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). 805 | */ 806 | __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) 807 | { 808 | uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 809 | uint32_t PreemptPriorityBits; 810 | uint32_t SubPriorityBits; 811 | 812 | PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); 813 | SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); 814 | 815 | return ( 816 | ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 817 | ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) 818 | ); 819 | } 820 | 821 | 822 | /** 823 | \brief Decode Priority 824 | \details Decodes an interrupt priority value with a given priority group to 825 | preemptive priority value and subpriority value. 826 | In case of a conflict between priority grouping and available 827 | priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. 828 | \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). 829 | \param [in] PriorityGroup Used priority group. 830 | \param [out] pPreemptPriority Preemptive priority value (starting from 0). 831 | \param [out] pSubPriority Subpriority value (starting from 0). 832 | */ 833 | __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) 834 | { 835 | uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 836 | uint32_t PreemptPriorityBits; 837 | uint32_t SubPriorityBits; 838 | 839 | PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); 840 | SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); 841 | 842 | *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); 843 | *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); 844 | } 845 | 846 | 847 | 848 | /** 849 | \brief Set Interrupt Vector 850 | \details Sets an interrupt vector in SRAM based interrupt vector table. 851 | The interrupt number can be positive to specify a device specific interrupt, 852 | or negative to specify a processor exception. 853 | Address 0 must be mapped to SRAM. 854 | \param [in] IRQn Interrupt number 855 | \param [in] vector Address of interrupt handler function 856 | */ 857 | __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) 858 | { 859 | uint32_t *vectors = (uint32_t *)0x0U; 860 | vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; 861 | } 862 | 863 | 864 | /** 865 | \brief Get Interrupt Vector 866 | \details Reads an interrupt vector from interrupt vector table. 867 | The interrupt number can be positive to specify a device specific interrupt, 868 | or negative to specify a processor exception. 869 | \param [in] IRQn Interrupt number. 870 | \return Address of interrupt handler function 871 | */ 872 | __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) 873 | { 874 | uint32_t *vectors = (uint32_t *)0x0U; 875 | return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; 876 | } 877 | 878 | 879 | /** 880 | \brief System Reset 881 | \details Initiates a system reset request to reset the MCU. 882 | */ 883 | __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) 884 | { 885 | __DSB(); /* Ensure all outstanding memory accesses included 886 | buffered write are completed before reset */ 887 | SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 888 | SCB_AIRCR_SYSRESETREQ_Msk); 889 | __DSB(); /* Ensure completion of memory access */ 890 | 891 | for(;;) /* wait until reset */ 892 | { 893 | __NOP(); 894 | } 895 | } 896 | 897 | /*@} end of CMSIS_Core_NVICFunctions */ 898 | 899 | 900 | /* ########################## FPU functions #################################### */ 901 | /** 902 | \ingroup CMSIS_Core_FunctionInterface 903 | \defgroup CMSIS_Core_FpuFunctions FPU Functions 904 | \brief Function that provides FPU type. 905 | @{ 906 | */ 907 | 908 | /** 909 | \brief get FPU type 910 | \details returns the FPU type 911 | \returns 912 | - \b 0: No FPU 913 | - \b 1: Single precision FPU 914 | - \b 2: Double + Single precision FPU 915 | */ 916 | __STATIC_INLINE uint32_t SCB_GetFPUType(void) 917 | { 918 | return 0U; /* No FPU */ 919 | } 920 | 921 | 922 | /*@} end of CMSIS_Core_FpuFunctions */ 923 | 924 | 925 | 926 | /* ################################## SysTick function ############################################ */ 927 | /** 928 | \ingroup CMSIS_Core_FunctionInterface 929 | \defgroup CMSIS_Core_SysTickFunctions SysTick Functions 930 | \brief Functions that configure the System. 931 | @{ 932 | */ 933 | 934 | #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) 935 | 936 | /** 937 | \brief System Tick Configuration 938 | \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. 939 | Counter is in free running mode to generate periodic interrupts. 940 | \param [in] ticks Number of ticks between two interrupts. 941 | \return 0 Function succeeded. 942 | \return 1 Function failed. 943 | \note When the variable __Vendor_SysTickConfig is set to 1, then the 944 | function SysTick_Config is not included. In this case, the file device.h 945 | must contain a vendor-specific implementation of this function. 946 | */ 947 | __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) 948 | { 949 | if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) 950 | { 951 | return (1UL); /* Reload value impossible */ 952 | } 953 | 954 | SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ 955 | NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ 956 | SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ 957 | SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | 958 | SysTick_CTRL_TICKINT_Msk | 959 | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ 960 | return (0UL); /* Function successful */ 961 | } 962 | 963 | #endif 964 | 965 | /*@} end of CMSIS_Core_SysTickFunctions */ 966 | 967 | 968 | 969 | 970 | #ifdef __cplusplus 971 | } 972 | #endif 973 | 974 | #endif /* __CORE_CM1_H_DEPENDANT */ 975 | 976 | #endif /* __CMSIS_GENERIC */ 977 | --------------------------------------------------------------------------------