├── .ciignore ├── .ctags ├── .ctagsignore ├── .githooks └── ignore-certain-dirs-commit-msg ├── .github ├── CI_README.md ├── ISSUE_TEMPLATE │ ├── bug-report.yml │ ├── config.yml │ └── feature-request.yml ├── PULL_REQUEST_TEMPLATE.md ├── actions │ ├── job-end │ │ └── action.yml │ ├── job-start │ │ └── action.yml │ ├── prepare-rtl │ │ └── action.yml │ ├── run-tests │ │ └── action.yml │ └── toolchain-build │ │ └── action.yml ├── scripts │ ├── build-extra-tests.sh │ ├── build-toolchains.sh │ ├── check-commit.sh │ ├── clean-old-files.sh │ ├── create-hash.sh │ ├── defaults.sh │ ├── remote-do-rtl-build.sh │ ├── remote-install-verilator.sh │ ├── remote-run-firesim-scala-tests.sh │ └── run-tests.sh └── workflows │ └── chipyard-run-tests.yml ├── .gitignore ├── .gitmodules ├── .java_tmp └── .gitignore ├── .readthedocs.yml ├── CHANGELOG.md ├── CONTRIBUTING.md ├── LICENSE ├── LICENSE.SiFive ├── README.md ├── build.sbt ├── common.mk ├── dockerfiles ├── Dockerfile └── README.md ├── docs ├── .gitignore ├── Advanced-Concepts │ ├── CDEs.rst │ ├── Chip-Communication.rst │ ├── Debugging-BOOM.rst │ ├── Debugging-RTL.rst │ ├── Harness-Clocks.rst │ ├── Managing-Published-Scala-Dependencies.rst │ ├── Resources.rst │ ├── Top-Testharness.rst │ └── index.rst ├── Chipyard-Basics │ ├── Chipyard-Components.rst │ ├── Configs-Parameters-Mixins.rst │ ├── Development-Ecosystem.rst │ ├── Initial-Repo-Setup.rst │ └── index.rst ├── Customization │ ├── Boot-Process.rst │ ├── Custom-Chisel.rst │ ├── Custom-Core.rst │ ├── DMA-Devices.rst │ ├── Dsptools-Blocks.rst │ ├── Firrtl-Transforms.rst │ ├── Heterogeneous-SoCs.rst │ ├── IOBinders.rst │ ├── Incorporating-Verilog-Blocks.rst │ ├── Keys-Traits-Configs.rst │ ├── MMIO-Peripherals.rst │ ├── Memory-Hierarchy.rst │ ├── RoCC-Accelerators.rst │ ├── RoCC-or-MMIO.rst │ └── index.rst ├── Generators │ ├── BOOM.rst │ ├── CVA6.rst │ ├── Gemmini.rst │ ├── Hwacha.rst │ ├── Ibex.rst │ ├── IceNet.rst │ ├── NVDLA.rst │ ├── Rocket-Chip.rst │ ├── Rocket.rst │ ├── SHA3.rst │ ├── SiFive-Generators.rst │ ├── Sodor.rst │ ├── TestChipIP.rst │ ├── fft.rst │ └── index.rst ├── Makefile ├── Prototyping │ ├── Arty.rst │ ├── General.rst │ ├── VCU118.rst │ └── index.rst ├── Simulation │ ├── FPGA-Accelerated-Simulation.rst │ ├── Software-RTL-Simulation.rst │ └── index.rst ├── Software │ ├── Baremetal.rst │ ├── FireMarshal.rst │ ├── Spike.rst │ └── index.rst ├── TileLink-Diplomacy-Reference │ ├── Diplomacy-Connectors.rst │ ├── EdgeFunctions.rst │ ├── NodeTypes.rst │ ├── Register-Router.rst │ ├── Widgets.rst │ └── index.rst ├── Tools │ ├── Barstools.rst │ ├── Chisel-Testers.rst │ ├── Chisel.rst │ ├── Dromajo.rst │ ├── Dsptools.rst │ ├── FIRRTL.rst │ ├── Treadle.rst │ └── index.rst ├── VLSI │ ├── ASAP7-Tutorial.rst │ ├── Advanced-Usage.rst │ ├── Basic-Flow.rst │ ├── Building-A-Chip.rst │ ├── Hammer.rst │ ├── Sky130-Tutorial.rst │ └── index.rst ├── _static │ ├── css │ │ └── custom.css │ └── images │ │ ├── boom-pipeline-detailed.png │ │ ├── bringup-chipyard-config-communication.png │ │ ├── chip-bringup-simulation.png │ │ ├── chip-bringup.png │ │ ├── chip-communication.png │ │ ├── chipyard-logo-full.png │ │ ├── chipyard-logo.png │ │ ├── chipyard-logo.svg │ │ ├── default-chipyard-config-communication.png │ │ ├── fir-block-diagram.svg │ │ ├── gemmini-system.png │ │ ├── nic-design.png │ │ ├── rocketchip-diagram.png │ │ └── sha3.png ├── conf.py ├── index.rst └── requirements.txt ├── fpga ├── .gitignore ├── Makefile ├── scripts │ └── run_impl_bitstream.tcl └── src │ └── main │ ├── resources │ └── vcu118 │ │ └── sdboot │ │ ├── .gitignore │ │ ├── Makefile │ │ ├── common.h │ │ ├── head.S │ │ ├── include │ │ ├── bits.h │ │ ├── const.h │ │ ├── devices │ │ │ ├── clint.h │ │ │ ├── gpio.h │ │ │ ├── plic.h │ │ │ ├── spi.h │ │ │ └── uart.h │ │ ├── platform.h │ │ ├── sections.h │ │ └── smp.h │ │ ├── kprintf.c │ │ ├── kprintf.h │ │ ├── linker │ │ ├── memory.lds │ │ └── sdboot.elf.lds │ │ └── sd.c │ └── scala │ ├── arty │ ├── Configs.scala │ ├── HarnessBinders.scala │ ├── IOBinders.scala │ └── TestHarness.scala │ └── vcu118 │ ├── Configs.scala │ ├── CustomOverlays.scala │ ├── FMCUtil.scala │ ├── HarnessBinders.scala │ ├── IOBinders.scala │ ├── TestHarness.scala │ └── bringup │ ├── BringupGPIOs.scala │ ├── Configs.scala │ ├── CustomOverlays.scala │ ├── DigitalTop.scala │ ├── HarnessBinders.scala │ ├── IOBinders.scala │ └── TestHarness.scala ├── generators ├── chipyard │ └── src │ │ ├── main │ │ ├── resources │ │ │ ├── csrc │ │ │ │ └── emulator.cc │ │ │ └── vsrc │ │ │ │ ├── ClockDividerN.sv │ │ │ │ └── GCDMMIOBlackBox.v │ │ └── scala │ │ │ ├── ChipTop.scala │ │ │ ├── CustomBusTopologies.scala │ │ │ ├── DigitalTop.scala │ │ │ ├── Generator.scala │ │ │ ├── HarnessBinders.scala │ │ │ ├── IOBinders.scala │ │ │ ├── Subsystem.scala │ │ │ ├── System.scala │ │ │ ├── TestHarness.scala │ │ │ ├── TestSuites.scala │ │ │ ├── clocking │ │ │ ├── ClockDividerN.scala │ │ │ ├── ClockGroupCombiner.scala │ │ │ ├── ClockGroupNamePrefixer.scala │ │ │ ├── DividerOnlyClockGenerator.scala │ │ │ ├── HasChipyardPRCI.scala │ │ │ ├── TileClockGater.scala │ │ │ └── TileResetSetter.scala │ │ │ ├── config │ │ │ ├── AbstractConfig.scala │ │ │ ├── BoomConfigs.scala │ │ │ ├── CVA6Configs.scala │ │ │ ├── HeteroConfigs.scala │ │ │ ├── IbexConfigs.scala │ │ │ ├── RocketConfigs.scala │ │ │ ├── SodorConfigs.scala │ │ │ ├── TracegenConfigs.scala │ │ │ ├── TutorialConfigs.scala │ │ │ └── fragments │ │ │ │ ├── ClockingFragments.scala │ │ │ │ ├── PeripheralFragments.scala │ │ │ │ ├── RoCCFragments.scala │ │ │ │ ├── SubsystemFragments.scala │ │ │ │ ├── TileFragments.scala │ │ │ │ └── TracegenFragments.scala │ │ │ ├── example │ │ │ ├── GCD.scala │ │ │ ├── InitZero.scala │ │ │ ├── NodeTypes.scala │ │ │ ├── RegisterNodeExample.scala │ │ │ ├── TutorialTile.scala │ │ │ └── dsptools │ │ │ │ ├── DspBlocks.scala │ │ │ │ ├── GenericFIR.scala │ │ │ │ └── StreamingPassthrough.scala │ │ │ ├── stage │ │ │ ├── ChipyardAnnotations.scala │ │ │ ├── ChipyardCli.scala │ │ │ ├── ChipyardStage.scala │ │ │ └── phases │ │ │ │ ├── AddDefaultTests.scala │ │ │ │ └── GenerateTestSuiteMakefrags.scala │ │ │ └── unittest │ │ │ ├── TestHarness.scala │ │ │ └── UnitTestSuite.scala │ │ └── test │ │ └── scala │ │ └── clocking │ │ └── SimplePllConfigurationSpec.scala ├── firechip │ └── src │ │ ├── main │ │ └── scala │ │ │ ├── BridgeBinders.scala │ │ │ ├── FireSim.scala │ │ │ ├── TargetConfigs.scala │ │ │ └── TargetLandTestSuites.scala │ │ └── test │ │ └── scala │ │ └── ScalaTestSuite.scala └── tracegen │ ├── src │ └── main │ │ └── scala │ │ ├── Configs.scala │ │ ├── System.scala │ │ └── Tile.scala │ └── tracegen.mk ├── project ├── build.properties └── plugins.sbt ├── scripts ├── add-githooks.sh ├── build-openocd.sh ├── build-toolchains.sh ├── build-util.sh ├── centos-req.sh ├── check-tracegen.sh ├── entrypoint.sh ├── firesim-setup.sh ├── gen-tags.sh ├── init-fpga.sh ├── init-software.sh ├── init-submodules-no-riscv-tools-nolog.sh ├── init-submodules-no-riscv-tools.sh ├── init-vlsi.sh ├── insert-includes.py ├── numa_prefix ├── smartelf2hex.sh ├── tutorial-patches │ ├── RocketConfigs.scala.patch │ └── build.sbt.patch ├── tutorial-setup.sh └── ubuntu-req.sh ├── sims ├── common-sim-flags.mk ├── vcs │ ├── .gitignore │ └── Makefile └── verilator │ ├── .gitignore │ └── Makefile ├── tests ├── .gitignore ├── Makefile ├── accum.c ├── big-blkdev.c ├── blkdev.c ├── blkdev.h ├── charcount.c ├── fft.c ├── gcd.c ├── htif.ld ├── libgloss.mk ├── mmio.h ├── nic-loopback.c ├── nic.h ├── nvdla.c ├── nvdla.h ├── pingd.c ├── pwm.c ├── rocc.h ├── spiflash.h ├── spiflash.py ├── spiflashread.c ├── spiflashwrite.c ├── streaming-fir.c └── streaming-passthrough.c ├── tools ├── dromajo │ └── dromajo.mk └── torture.mk ├── variables.mk ├── vcs.mk └── vlsi ├── .gitignore ├── Makefile ├── env.yml ├── example-asap7.yml ├── example-design.yml ├── example-nangate45.yml ├── example-sky130.yml ├── example-tech.yml ├── example-tools.yml ├── example-vlsi ├── example-vlsi-sky130 ├── power.mk ├── sim.mk └── view_gds.py /.ciignore: -------------------------------------------------------------------------------- 1 | docs/* 2 | -------------------------------------------------------------------------------- /.ctags: -------------------------------------------------------------------------------- 1 | --langdef=scala 2 | --langmap=scala:.scala 3 | 4 | --regex-scala=/^[ \t]*((abstract|final|sealed|implicit|lazy)[ \t]*)*(private[^ ]*|protected)?[ \t]*class[ \t]+([a-zA-Z0-9_]+)/\4/c,classes/ 5 | --regex-scala=/^[ \t]*((abstract|final|sealed|implicit|lazy)[ \t]*)*(private[^ ]*|protected)?[ \t]*object[ \t]+([a-zA-Z0-9_]+)/\4/o,objects/ 6 | --regex-scala=/^[ \t]*((abstract|final|sealed|implicit|lazy)[ \t]*)*(private[^ ]*|protected)?[ \t]*((abstract|final|sealed|implicit|lazy)[ \t ]*)*case class[ \t ]+([a-zA-Z0-9_]+)/\6/C,case classes/ 7 | --regex-scala=/^[ \t]*((abstract|final|sealed|implicit|lazy)[ \t]*)*(private[^ ]*|protected)?[ \t]*case object[ \t]+([a-zA-Z0-9_]+)/\4/O,case objects/ 8 | --regex-scala=/^[ \t]*((abstract|final|sealed|implicit|lazy)[ \t]*)*(private[^ ]*|protected)?[ \t]*trait[ \t]+([a-zA-Z0-9_]+)/\4/t,traits/ 9 | --regex-scala=/^[ \t]*type[ \t]+([a-zA-Z0-9_]+)/\1/T,types/ 10 | --regex-scala=/^[ \t]*((abstract|final|sealed|implicit|lazy|override|private[^ ]*(\[[a-z]*\])*|protected)[ \t]*)*def[ \t]+([a-zA-Z0-9_]+)/\4/m,methods/ 11 | --regex-scala=/^[ \t]*((abstract|final|sealed|implicit|lazy|override|private[^ ]*|protected)[ \t]*)*val[ \t]+([a-zA-Z0-9_]+)/\3/V,values/ 12 | --regex-scala=/^[ \t]*((abstract|final|sealed|implicit|lazy|override|private[^ ]*|protected)[ \t]*)*var[ \t]+([a-zA-Z0-9_]+)/\3/v,variables/ 13 | --regex-scala=/^[ \t]*package[ \t]+([a-zA-Z0-9_.]+)/\1/p,packages/ 14 | -------------------------------------------------------------------------------- /.ctagsignore: -------------------------------------------------------------------------------- 1 | */target 2 | sims 3 | toolchains 4 | -------------------------------------------------------------------------------- /.githooks/ignore-certain-dirs-commit-msg: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env bash 2 | 3 | if [[ ! -a .ciignore ]]; then 4 | exit # If .ciignore doesn't exists, just quit this Git hook 5 | fi 6 | 7 | # Load in every file that will be changed via this commit into an array 8 | changes=( `git diff --name-only --cached` ) 9 | 10 | # Load the patterns we want to skip into an array 11 | mapfile -t blocklist < .ciignore 12 | 13 | for i in "${blocklist[@]}" 14 | do 15 | # Remove the current pattern from the list of changes 16 | changes=( ${changes[@]/$i/} ) 17 | 18 | if [[ ${#changes[@]} -eq 0 ]]; then 19 | # If we've exhausted the list of changes before we've finished going 20 | # through patterns, that's okay, just quit the loop 21 | break 22 | fi 23 | done 24 | 25 | if [[ ${#changes[@]} -gt 0 ]]; then 26 | # If there's still changes left, then we have stuff to build, leave the commit alone. 27 | exit 28 | fi 29 | 30 | # Prefix the commit message with "[skip ci]" 31 | sed -i '1s/^/[skip ci] /' "$1" 32 | -------------------------------------------------------------------------------- /.github/ISSUE_TEMPLATE/bug-report.yml: -------------------------------------------------------------------------------- 1 | name: Bug Report 2 | description: File a bug report 3 | labels: ["bug"] 4 | body: 5 | - type: checkboxes 6 | attributes: 7 | label: Background Work 8 | description: Yes, I searched the following areas for a prior solution. 9 | options: 10 | - label: Yes, I searched the [mailing list](https://groups.google.com/forum/#!forum/chipyard) 11 | required: true 12 | - label: Yes, I searched [prior issues](https://github.com/ucb-bar/chipyard/issues) 13 | required: true 14 | - label: Yes, I searched the [documentation](https://chipyard.readthedocs.io/) 15 | required: true 16 | 17 | - type: textarea 18 | attributes: 19 | label: Chipyard Version and Hash 20 | description: Repository version for reproducibility 21 | placeholder: Version + Hash 22 | value: | 23 | Release: 1.5.0 24 | Hash: a6a6a6 25 | validations: 26 | required: true 27 | 28 | - type: textarea 29 | attributes: 30 | label: OS Setup 31 | description: OS setup for reproducibility 32 | placeholder: OS information 33 | value: | 34 | Ex: Output of `uname -a` and `lsb_release -a` 35 | validations: 36 | required: true 37 | 38 | - type: textarea 39 | attributes: 40 | label: Other Setup 41 | description: Any other setup relevant 42 | placeholder: Other setup 43 | value: | 44 | Ex: Prior steps taken / Documentation Followed / etc... 45 | validations: 46 | required: false 47 | 48 | - type: textarea 49 | attributes: 50 | label: Current Behavior 51 | description: A concise description of what you're experiencing. 52 | validations: 53 | required: true 54 | 55 | - type: textarea 56 | attributes: 57 | label: Expected Behavior 58 | description: A concise description of what you expected to happen. 59 | validations: 60 | required: true 61 | 62 | - type: textarea 63 | attributes: 64 | label: Other Information 65 | description: Other information needed to reproduce the issue. 66 | placeholder: | 67 | Detailed explanations 68 | Stack traces 69 | Log files. Tip - You can add images / log files by clicking this area to highlight it and then dragging files in 70 | Related issues 71 | Suggestions on fixes 72 | Other links 73 | validations: 74 | required: false 75 | -------------------------------------------------------------------------------- /.github/ISSUE_TEMPLATE/config.yml: -------------------------------------------------------------------------------- 1 | blank_issues_enabled: false 2 | contact_links: 3 | - name: Chipyard Mailing List 4 | url: https://groups.google.com/forum/#!forum/chipyard 5 | about: Please ask and answer questions here. 6 | - name: Rocket Chip Support 7 | url: https://github.com/chipsalliance/rocket-chip/issues 8 | about: Please ask and answer questions here. 9 | - name: Chisel Support 10 | url: https://www.chisel-lang.org/community.html 11 | about: Please ask and answer questions here. 12 | -------------------------------------------------------------------------------- /.github/ISSUE_TEMPLATE/feature-request.yml: -------------------------------------------------------------------------------- 1 | name: Feature Request 2 | description: File a feature request 3 | labels: ["enhancement"] 4 | body: 5 | - type: checkboxes 6 | attributes: 7 | label: Background Work 8 | description: Yes, I searched the following areas for a prior feature/solution to this problem. 9 | options: 10 | - label: Yes, I searched the [mailing list](https://groups.google.com/forum/#!forum/chipyard) 11 | required: true 12 | - label: Yes, I searched the [documentation](https://chipyard.readthedocs.io/) 13 | required: true 14 | 15 | - type: textarea 16 | attributes: 17 | label: Feature Description 18 | description: Description of feature wanted 19 | validations: 20 | required: true 21 | 22 | - type: textarea 23 | attributes: 24 | label: Motivating Example 25 | description: A concise example demonstrating the feature. 26 | validations: 27 | required: true 28 | -------------------------------------------------------------------------------- /.github/PULL_REQUEST_TEMPLATE.md: -------------------------------------------------------------------------------- 1 | **Related PRs / Issues **: 2 | 3 | 4 | 5 | **Type of change**: 6 | - [ ] Bug fix 7 | - [ ] New feature 8 | - [ ] Other enhancement 9 | 10 | 11 | **Impact**: 12 | - [ ] RTL change 13 | - [ ] Software change (RISC-V software) 14 | - [ ] Build system change 15 | - [ ] Other 16 | 17 | 18 | **Contributor Checklist**: 19 | - [ ] Did you set `main` as the base branch? 20 | - [ ] Did you delete any extraneous prints/debugging code? 21 | - [ ] (If applicable) Did you add documentation for the feature? 22 | - [ ] (If applicable) Did you add a test demonstrating the PR? 23 | 24 | - [ ] (If applicable) Did you mark the PR as "Please Backport"? 25 | 26 | **Release Notes** 27 | 28 | -------------------------------------------------------------------------------- /.github/actions/job-end/action.yml: -------------------------------------------------------------------------------- 1 | name: job-end 2 | description: "Save a job status" 3 | 4 | runs: 5 | using: "composite" 6 | steps: 7 | - run: echo "success" > run_result 8 | shell: bash 9 | -------------------------------------------------------------------------------- /.github/actions/job-start/action.yml: -------------------------------------------------------------------------------- 1 | name: job-start 2 | description: "Setup a job status" 3 | outputs: 4 | run_result: 5 | value: ${{ steps.run_result.outputs.run_result }} 6 | 7 | runs: 8 | using: "composite" 9 | steps: 10 | - name: Restore the previous run result 11 | uses: actions/cache@v2 12 | with: 13 | path: run_result 14 | key: ${{ github.run_id }}-${{ github.job }} 15 | restore-keys: ${{ github.run_id }}-${{ github.job }} 16 | - name: Set run_result to default or use cached value 17 | id: run_result 18 | run: echo "::set-output name=run_result::$(cat run_result 2>/dev/null || echo 'default')" 19 | shell: bash 20 | -------------------------------------------------------------------------------- /.github/actions/prepare-rtl/action.yml: -------------------------------------------------------------------------------- 1 | name: prepare-rtl 2 | description: 'Builds RTL based on parameters, caches the entire chipyard root dir when done' 3 | 4 | inputs: 5 | group-key: 6 | description: group key 7 | required: true 8 | build-script: 9 | description: rtl build script to use 10 | required: false 11 | default: "remote-do-rtl-build.sh" 12 | build-type: 13 | description: type of build 14 | required: false 15 | default: "sim" 16 | 17 | runs: 18 | using: "composite" 19 | steps: 20 | - name: Build RISC-V toolchains 21 | uses: ./.github/actions/toolchain-build 22 | 23 | - uses: actions/cache@v2 24 | id: rtl-build-id 25 | with: 26 | path: | 27 | sims/verilator 28 | sims/firesim/sim 29 | generators/gemmini/software/gemmini-rocc-tests 30 | key: ${{ inputs.group-key }}-${{ github.ref }}-${{ github.sha }} 31 | 32 | - name: Run RTL build if not cached 33 | run: | 34 | if [[ "${{ steps.rtl-build-id.outputs.cache-hit }}" != 'true' ]]; then 35 | echo "Cache miss on ${{ inputs.group-key }}-${{ github.ref }}-${{ github.sha }}" 36 | ./.github/scripts/${{ inputs.build-script }} ${{ inputs.group-key }} ${{ inputs.build-type }} 37 | else 38 | echo "Cache hit do not rebuild RTL for ${{ inputs.group-key }}" 39 | fi 40 | shell: bash 41 | -------------------------------------------------------------------------------- /.github/actions/run-tests/action.yml: -------------------------------------------------------------------------------- 1 | name: run-tests 2 | description: 'Runs tests according to input parameters' 3 | 4 | inputs: 5 | group-key: 6 | description: group key 7 | required: true 8 | project-key: 9 | description: project key 10 | required: true 11 | run-script: 12 | description: rtl build script to use 13 | required: false 14 | default: "run-tests.sh" 15 | 16 | runs: 17 | using: "composite" 18 | steps: 19 | - name: Init submodules (since only the RTL is cached) 20 | run: ./scripts/init-submodules-no-riscv-tools.sh --skip-validate 21 | shell: bash 22 | 23 | # Note: You shouldn't need the other inputs since it shouldn't build RTL from scratch 24 | - name: Build RTL 25 | uses: ./.github/actions/prepare-rtl 26 | with: 27 | group-key: ${{ inputs.group-key }} 28 | 29 | - name: Run RTL tests 30 | run: ./.github/scripts/${{ inputs.run-script }} ${{ inputs.project-key }} 31 | shell: bash 32 | -------------------------------------------------------------------------------- /.github/actions/toolchain-build/action.yml: -------------------------------------------------------------------------------- 1 | name: toolchain-build 2 | description: 'Build/cache both toolchains' 3 | 4 | runs: 5 | using: "composite" 6 | steps: 7 | - name: Generate hashes 8 | run: .github/scripts/create-hash.sh 9 | shell: bash 10 | 11 | # since "hashFiles" function differs on self-hosted vs GH-A machines 12 | # make sure to cache the GH-A hashFiles result so that self-hosted can use it 13 | - run: | 14 | echo "${{ hashFiles('**/riscv-tools.hash') }}" > riscv-tools.hashFilesOutput 15 | echo "${{ hashFiles('**/esp-tools.hash') }}" > esp-tools.hashFilesOutput 16 | shell: bash 17 | 18 | - name: Cache hashFiles outputs 19 | uses: actions/cache@v2 20 | with: 21 | path: | 22 | riscv-tools.hashFilesOutput 23 | esp-tools.hashFilesOutput 24 | key: hashFiles-${{ github.sha }} 25 | 26 | - name: Generate cache keys based off hashFiles output 27 | id: genkey 28 | run: | 29 | echo "::set-output name=riscv-tools-cache-key::$(cat riscv-tools.hashFilesOutput)" 30 | echo "::set-output name=esp-tools-cache-key::$(cat esp-tools.hashFilesOutput)" 31 | shell: bash 32 | 33 | - name: Cache riscv-tools 34 | uses: actions/cache@v2 35 | with: 36 | path: riscv-tools-install 37 | key: riscv-tools-installed-${{ env.tools-cache-version }}-${{ steps.genkey.outputs.riscv-tools-cache-key }} 38 | 39 | - name: Cache esp-tools 40 | uses: actions/cache@v2 41 | with: 42 | path: esp-tools-install 43 | key: esp-tools-installed-${{ env.tools-cache-version }}-${{ steps.genkey.outputs.esp-tools-cache-key }} 44 | 45 | - name: Build RISC-V toolchain if not cached 46 | run: ./.github/scripts/build-toolchains.sh riscv-tools 47 | shell: bash 48 | 49 | - name: Build ESP RISC-V toolchain if not cached 50 | run: ./.github/scripts/build-toolchains.sh esp-tools 51 | shell: bash 52 | -------------------------------------------------------------------------------- /.github/scripts/build-extra-tests.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | # turn echo on and error on earliest command 4 | set -ex 5 | 6 | # get shared variables 7 | SCRIPT_DIR="$( cd "$( dirname "$0" )" && pwd )" 8 | source $SCRIPT_DIR/defaults.sh 9 | 10 | export RISCV="$GITHUB_WORKSPACE/riscv-tools-install" 11 | export LD_LIBRARY_PATH="$RISCV/lib" 12 | export PATH="$RISCV/bin:$PATH" 13 | 14 | make -C $LOCAL_CHIPYARD_DIR/tests clean 15 | make -C $LOCAL_CHIPYARD_DIR/tests 16 | -------------------------------------------------------------------------------- /.github/scripts/build-toolchains.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | # create the riscv tools/esp tools binaries 4 | # passed in as 5 | 6 | # turn echo on and error on earliest command 7 | set -ex 8 | 9 | # get shared variables 10 | SCRIPT_DIR="$( cd "$( dirname "$0" )" && pwd )" 11 | source $SCRIPT_DIR/defaults.sh 12 | 13 | if [ ! -d "$HOME/$1-install" ]; then 14 | cd $HOME 15 | 16 | # init all submodules including the tools 17 | CHIPYARD_DIR="$LOCAL_CHIPYARD_DIR" NPROC=$CI_MAKE_NPROC $LOCAL_CHIPYARD_DIR/scripts/build-toolchains.sh $1 18 | 19 | # de-init the toolchain area to save on space (forced to ignore local changes) 20 | git submodule deinit --force $LOCAL_CHIPYARD_DIR/toolchains/$1 21 | fi 22 | -------------------------------------------------------------------------------- /.github/scripts/clean-old-files.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | # clean directories that are older than 14 days 4 | # argument is used as the directory to look in 5 | 6 | age () { 7 | local AGE_SEC 8 | local CUR_SEC 9 | local DIFF_SEC 10 | local SEC_PER_DAY 11 | 12 | SEC_PER_DAY=86400 13 | 14 | CUR_SEC=$(date +%s) 15 | AGE_SEC=$(stat -c %Y -- "$1") 16 | DIFF_SEC=$(expr $CUR_SEC - $AGE_SEC) 17 | 18 | echo $(expr $DIFF_SEC / $SEC_PER_DAY) 19 | } 20 | 21 | for d in $1/*/ ; do 22 | DIR_AGE="$(age $d)" 23 | if [ $DIR_AGE -ge 14 ]; then 24 | echo "Deleting $d since is it $DIR_AGE old" 25 | rm -rf $d 26 | else 27 | echo "Keep $d since it is $DIR_AGE old" 28 | fi 29 | done 30 | -------------------------------------------------------------------------------- /.github/scripts/create-hash.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | # get the hash of riscv-tools 4 | 5 | # turn echo on and error on earliest command 6 | set -ex 7 | set -o pipefail 8 | 9 | # get shared variables 10 | SCRIPT_DIR="$( cd "$( dirname "$0" )" && pwd )" 11 | source $SCRIPT_DIR/defaults.sh 12 | 13 | # Use normalized output of git-submodule status as hashfile 14 | for tools in 'riscv-tools' 'esp-tools' ; do 15 | git submodule status "toolchains/${tools}" 'toolchains/libgloss' 'toolchains/qemu' | 16 | while read -r line ; do 17 | echo "${line#[!0-9a-f]}" 18 | done > "${tools}.hash" 19 | done 20 | echo "Hashfile for riscv-tools and esp-tools created in $PWD" 21 | -------------------------------------------------------------------------------- /.github/scripts/remote-do-rtl-build.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | # create the different verilator builds 4 | # usage: 5 | # do-rtl-build.sh sim 6 | # run rtl build for simulations and copy back results 7 | # do-rtl-build.sh fpga 8 | # run rtl build for fpga and don't copy back results 9 | 10 | # turn echo on and error on earliest command 11 | set -ex 12 | 13 | # get shared variables 14 | SCRIPT_DIR="$( cd "$( dirname "$0" )" && pwd )" 15 | source $SCRIPT_DIR/defaults.sh 16 | 17 | cd $REMOTE_CHIPYARD_DIR 18 | ./scripts/init-submodules-no-riscv-tools.sh --skip-validate 19 | ./scripts/init-fpga.sh 20 | 21 | TOOLS_DIR=$REMOTE_RISCV_DIR 22 | LD_LIB_DIR=$REMOTE_RISCV_DIR/lib 23 | 24 | if [ $1 = "group-accels" ]; then 25 | export RISCV=$REMOTE_ESP_DIR 26 | export LD_LIBRARY_PATH=$REMOTE_ESP_DIR/lib 27 | export PATH=$RISCV/bin:$PATH 28 | pushd $REMOTE_CHIPYARD_DIR/generators/gemmini/software 29 | git submodule update --init --recursive gemmini-rocc-tests 30 | pushd gemmini-rocc-tests 31 | ./build.sh 32 | popd 33 | popd 34 | fi 35 | 36 | # choose what make dir to use 37 | case $2 in 38 | "sim") 39 | REMOTE_MAKE_DIR=$REMOTE_SIM_DIR 40 | ;; 41 | "fpga") 42 | REMOTE_MAKE_DIR=$REMOTE_FPGA_DIR 43 | ;; 44 | esac 45 | 46 | # enter the verilator directory and build the specific config on remote server 47 | export RISCV=$TOOLS_DIR 48 | make -C $REMOTE_MAKE_DIR clean 49 | 50 | read -a keys <<< ${grouping[$1]} 51 | 52 | # need to set the PATH to use the new verilator (with the new verilator root) 53 | for key in "${keys[@]}" 54 | do 55 | export RISCV=$TOOLS_DIR 56 | export LD_LIBRARY_PATH=$LD_LIB_DIR 57 | export PATH=$REMOTE_VERILATOR_DIR/bin:$PATH 58 | export VERILATOR_ROOT=$REMOTE_VERILATOR_DIR 59 | export COURSIER_CACHE=$REMOTE_WORK_DIR/.coursier-cache 60 | make -j$REMOTE_MAKE_NPROC -C $REMOTE_MAKE_DIR FIRRTL_LOGLEVEL=info JAVA_OPTS="$REMOTE_JAVA_OPTS" SBT_OPTS="$REMOTE_SBT_OPTS" ${mapping[$key]} 61 | done 62 | -------------------------------------------------------------------------------- /.github/scripts/remote-install-verilator.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | # install verilator 4 | 5 | # turn echo on and error on earliest command 6 | set -ex 7 | 8 | # get shared variables 9 | SCRIPT_DIR="$( cd "$( dirname "$0" )" && pwd )" 10 | source $SCRIPT_DIR/defaults.sh 11 | 12 | # clean older directories (delete prior directories related to this branch also) 13 | $SCRIPT_DIR/clean-old-files.sh $CI_DIR 14 | rm -rf $REMOTE_PREFIX* 15 | 16 | git clone http://git.veripool.org/git/verilator $REMOTE_VERILATOR_DIR 17 | cd $REMOTE_VERILATOR_DIR 18 | git checkout $VERILATOR_VERSION 19 | autoconf 20 | export VERILATOR_ROOT=$REMOTE_VERILATOR_DIR 21 | ./configure 22 | make -j$REMOTE_MAKE_NPROC 23 | -------------------------------------------------------------------------------- /.github/scripts/remote-run-firesim-scala-tests.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | # create the different verilator builds 4 | # argument is the make command string 5 | 6 | # turn echo on and error on earliest command 7 | set -ex 8 | 9 | # get shared variables 10 | SCRIPT_DIR="$( cd "$( dirname "$0" )" && pwd )" 11 | source $SCRIPT_DIR/defaults.sh 12 | 13 | export RISCV="$REMOTE_RISCV_DIR" 14 | export LD_LIBRARY_PATH="$RISCV/lib" 15 | export PATH="$RISCV/bin:$PATH" 16 | 17 | # Directory locations for handling firesim-local installations of libelf/libdwarf 18 | # This would generally be handled by build-setup.sh/firesim-setup.sh 19 | REMOTE_FIRESIM_SYSROOT=$REMOTE_FIRESIM_DIR/lib-install 20 | 21 | ./scripts/init-submodules-no-riscv-tools.sh --skip-validate 22 | cd $REMOTE_CHIPYARD_DIR/sims/firesim/sim/firesim-lib/src/main/cc/lib 23 | git submodule update --init elfutils libdwarf 24 | cd $REMOTE_CHIPYARD_DIR/sims/firesim 25 | mkdir -p $REMOTE_FIRESIM_SYSROOT 26 | ./scripts/build-libelf.sh $REMOTE_FIRESIM_SYSROOT 27 | ./scripts/build-libdwarf.sh $REMOTE_FIRESIM_SYSROOT 28 | cd $REMOTE_CHIPYARD_DIR 29 | 30 | make -C $REMOTE_CHIPYARD_DIR/tools/dromajo/dromajo-src/src 31 | 32 | TOOLS_DIR=$REMOTE_RISCV_DIR 33 | 34 | LD_LIB_DIR=$REMOTE_FIRESIM_SYSROOT/lib:$REMOTE_RISCV_DIR/lib 35 | 36 | # Run Firesim Scala Tests 37 | export RISCV=$TOOLS_DIR 38 | export LD_LIBRARY_PATH=$LD_LIB_DIR 39 | export FIRESIM_ENV_SOURCED=1; 40 | export PATH=$REMOTE_VERILATOR_DIR/bin:$PATH 41 | export VERILATOR_ROOT=$REMOTE_VERILATOR_DIR 42 | export COURSIER_CACHE=$REMOTE_WORK_DIR/.coursier-cache 43 | make -C $REMOTE_FIRESIM_DIR JAVA_OPTS="$REMOTE_JAVA_OPTS" SBT_OPTS="$REMOTE_SBT_OPTS" testOnly ${mapping[$1]} 44 | -------------------------------------------------------------------------------- /.gitignore: -------------------------------------------------------------------------------- 1 | bootrom/* 2 | docs/warnings.txt 3 | /Makefrag.pkgs 4 | target 5 | *.jar 6 | *.stamp 7 | *.vcd 8 | *.swp 9 | *.swo 10 | *.log 11 | *# 12 | *~ 13 | .idea 14 | .DS_Store 15 | env.sh 16 | riscv-tools-install 17 | esp-tools-install 18 | tags 19 | *~ 20 | env-riscv-tools.sh 21 | env-esp-tools.sh 22 | .bsp/ 23 | -------------------------------------------------------------------------------- /.java_tmp/.gitignore: -------------------------------------------------------------------------------- 1 | # Ignore everything in this directory 2 | * 3 | # Except this file 4 | !.gitignore 5 | -------------------------------------------------------------------------------- /.readthedocs.yml: -------------------------------------------------------------------------------- 1 | version: 2 2 | 3 | build: 4 | os: ubuntu-20.04 5 | tools: 6 | python: "3.6" 7 | 8 | formats: all 9 | 10 | sphinx: 11 | configuration: docs/conf.py 12 | fail_on_warning: true 13 | 14 | python: 15 | install: 16 | - requirements: docs/requirements.txt 17 | -------------------------------------------------------------------------------- /CONTRIBUTING.md: -------------------------------------------------------------------------------- 1 | Contributing to Chipyard 2 | ============================= 3 | 4 | ### Branch management: 5 | 6 | 1) github:com/ucb-bar/chipyard: main = pre-release non-stable branch with latest features. All merges to main must go through PR. 7 | 2) github:com/ucb-bar/chipyard: specific tag = official chipyard release. 8 | 3) Other dependencies pointed at by Chipyard (e.g. firesim, boom): master/main should be the version submoduled in ucb-bar/chipyard main. 9 | -------------------------------------------------------------------------------- /LICENSE: -------------------------------------------------------------------------------- 1 | BSD 3-Clause License 2 | 3 | Copyright (c) 2017-2020, The Regents of the University of California (Regents) 4 | All Rights Reserved. 5 | 6 | Redistribution and use in source and binary forms, with or without 7 | modification, are permitted provided that the following conditions are met: 8 | 9 | 1. Redistributions of source code must retain the above copyright notice, this 10 | list of conditions and the following disclaimer. 11 | 12 | 2. Redistributions in binary form must reproduce the above copyright notice, 13 | this list of conditions and the following disclaimer in the documentation 14 | and/or other materials provided with the distribution. 15 | 16 | 3. Neither the name of the copyright holder nor the names of its 17 | contributors may be used to endorse or promote products derived from 18 | this software without specific prior written permission. 19 | 20 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 | AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 | IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 23 | DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 24 | FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 25 | DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 26 | SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 27 | CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 28 | OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 29 | OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 | 31 | -------------------------------------------------------------------------------- /dockerfiles/Dockerfile: -------------------------------------------------------------------------------- 1 | ### This is a full chipyard setup 2 | 3 | # BUILD BASE FOR CI 4 | 5 | FROM ubuntu:18.04 as base 6 | ARG CHIPYARD_HASH 7 | 8 | MAINTAINER https://groups.google.com/forum/#!forum/chipyard 9 | 10 | SHELL ["/bin/bash", "-c"] 11 | 12 | # Install dependencies for ubuntu-req.sh 13 | RUN apt-get update && \ 14 | DEBIAN_FRONTEND=noninteractive apt-get install -y --no-install-recommends \ 15 | curl \ 16 | git \ 17 | sudo \ 18 | ca-certificates \ 19 | keyboard-configuration \ 20 | console-setup \ 21 | bc \ 22 | unzip 23 | 24 | WORKDIR /root 25 | 26 | # Install Chipyard and run ubuntu-req.sh to install necessary dependencies 27 | RUN git clone https://github.com/ucb-bar/chipyard.git && \ 28 | cd chipyard && \ 29 | git checkout $CHIPYARD_HASH && \ 30 | ./scripts/ubuntu-req.sh 1>/dev/null && \ 31 | sudo rm -rf /var/lib/apt/lists/* 32 | 33 | # Update PATH for RISCV toolchain (note: hardcoded for CircleCI) 34 | ENV RISCV="/root/riscv-tools-install" 35 | ENV LD_LIBRARY_PATH="$RISCV/lib" 36 | ENV PATH="$RISCV/bin:$PATH" 37 | 38 | # BUILD IMAGE WITH TOOLCHAINS 39 | 40 | # Use above build as base 41 | FROM base as base-with-tools 42 | 43 | # Init submodules 44 | RUN cd chipyard && \ 45 | export MAKEFLAGS=-"j $(nproc)" && \ 46 | ./scripts/init-submodules-no-riscv-tools.sh 1>/dev/null 47 | 48 | # Install riscv-tools 49 | RUN cd chipyard && \ 50 | export MAKEFLAGS=-"j $(nproc)" && \ 51 | ./scripts/build-toolchains.sh riscv-tools 1>/dev/null 52 | 53 | # Install esp-tools 54 | RUN cd chipyard && \ 55 | export MAKEFLAGS=-"j $(nproc)" && \ 56 | ./scripts/build-toolchains.sh esp-tools 1>/dev/null 57 | 58 | 59 | # Set up FireMarshal. Building and cleaning br-base.json builds the underlying 60 | # buildroot image (which takes a long time) but doesn't keep all the br-base 61 | # stuff around (since that's faster to rebuild). 62 | RUN cd chipyard && \ 63 | source env.sh && \ 64 | cd software/firemarshal && \ 65 | ./init-submodules.sh && \ 66 | pip3 install -r python-requirements.txt && \ 67 | marshal build br-base.json && \ 68 | marshal clean br-base.json 69 | 70 | 71 | # Run script to set environment variables on entry 72 | ENTRYPOINT ["chipyard/scripts/entrypoint.sh"] 73 | 74 | # END IMAGE CUSTOMIZATIONS 75 | 76 | CMD ["/bin/sh"] 77 | -------------------------------------------------------------------------------- /dockerfiles/README.md: -------------------------------------------------------------------------------- 1 | General 2 | ------- 3 | This DockerFile contains the necessary steps to build a Docker container that can run 4 | projects with riscv-tools, chisel3, firrtl, and verilator. When run up to the base stage, it installs the necessary 5 | apt-get packages and sets the environment variables needed for CircleCI. When run up to the base-with-tools stage, it initializes and installs the necessary toolchains for running simulations and testing projects. 6 | 7 | Build and Deploy the Container 8 | ------------------------------ 9 | 10 | sudo docker build --target base . # to build the image for the CI 11 | sudo docker build --target base --build-arg CHIPYARD_HASH= . # to build the image for the CI from a specific chipyard commit 12 | sudo docker build --target base-with-tools . # to build the full image 13 | sudo docker tag :tag . # to tag the image after the build (ex. 0.0.3) 14 | sudo docker login # login into the account to push to 15 | sudo docker push :tag # to push to repo with tag 16 | sudo docker run -it --privileged bash # to run an interactive version of the container 17 | 18 | 19 | Path Names 20 | ---------- 21 | Older docker images (when this Dockerfile was in `riscv-boom/riscv-boom`) can be found in the `riscvboom/riscvboom-images`. 22 | Current up-to-date images are located in `ucbbar/chipyard-image`. NOTE: Less recent images in this path may not have toolchains initialized 23 | Current up-to-date CI images are located in `ucbbar/chipyard-ci-image`. 24 | -------------------------------------------------------------------------------- /docs/.gitignore: -------------------------------------------------------------------------------- 1 | _build 2 | -------------------------------------------------------------------------------- /docs/Advanced-Concepts/Debugging-BOOM.rst: -------------------------------------------------------------------------------- 1 | Debugging BOOM 2 | ====================== 3 | 4 | In addition to the default debugging techniques specified in :ref:`Advanced-Concepts/Debugging-RTL:Debugging RTL`, 5 | single-core BOOM designs can utilize the Dromajo co-simulator (see :ref:`Tools/Dromajo:Dromajo`) 6 | to verify functionality. 7 | 8 | .. warning:: Dromajo currently only works in single-core BOOM systems without accelerators. 9 | 10 | .. warning:: Dromajo currently only works in VCS simulation and FireSim. 11 | 12 | Setting up Dromajo Co-simulation 13 | -------------------------------------- 14 | 15 | Dromajo co-simulation is setup to work when three config fragments are added to a BOOM config. 16 | 17 | * A ``chipyard.config.WithTraceIO`` config fragment must be added so that BOOM's traceport is enabled. 18 | * A ``chipyard.iobinders.WithTraceIOPunchthrough`` config fragment must be added to add the ``TraceIO`` to the ``ChipTop`` 19 | * A ``chipyard.harness.WithSimDromajoBridge`` config fragment must be added to instantiate a Dromajo cosimulator in the ``TestHarness`` and connect it to the ``ChipTop``'s ``TraceIO`` 20 | 21 | 22 | Once all config fragments are added Dromajo should be enabled. 23 | 24 | To build/run Dromajo with a BOOM design, run your configuration the following make commands: 25 | 26 | .. code-block:: shell 27 | 28 | # build the default Dromajo BOOM config without waveform dumps 29 | # replace "DromajoBoomConfig" with your particular config 30 | make CONFIG=DromajoBoomConfig ENABLE_DROMAJO=1 31 | 32 | # run a simulation with Dromajo 33 | make CONFIG=DromajoBoomConfig ENABLE_DROMAJO=1 BINARY= run-binary 34 | -------------------------------------------------------------------------------- /docs/Advanced-Concepts/Harness-Clocks.rst: -------------------------------------------------------------------------------- 1 | .. _harness-clocks: 2 | 3 | Creating Clocks in the Test Harness 4 | =================================== 5 | 6 | Chipyard currently allows the SoC design (everything under ``ChipTop``) to 7 | have independent clock domains through diplomacy. 8 | This implies that some reference clock enters the ``ChipTop`` and then is divided down into 9 | separate clock domains. 10 | From the perspective of the ``TestHarness`` module, the ``ChipTop`` clock and reset is 11 | provided from a clock and reset called ``buildtopClock`` and ``buildtopReset``. 12 | In the default case, this ``buildtopClock`` and ``buildtopReset`` is directly wired to the 13 | clock and reset IO's of the ``TestHarness`` module. 14 | However, the ``TestHarness`` has the ability to generate a standalone clock and reset signal 15 | that is separate from the reference clock/reset of ``ChipTop``. 16 | This allows harness components (including harness binders) the ability to "request" a clock 17 | for a new clock domain. 18 | This is useful for simulating systems in which modules in the harness have independent clock domains 19 | from the DUT. 20 | 21 | Requests for a harness clock is done by the ``HarnessClockInstantiator`` class in ``generators/chipyard/src/main/scala/TestHarness.scala``. 22 | This class is accessed in harness components by referencing the Rocket Chip parameters key ``p(HarnessClockInstantiatorKey)``. 23 | Then you can request a clock and syncronized reset at a particular frequency by invoking the ``requestClockBundle`` function. 24 | Take the following example: 25 | 26 | .. literalinclude:: ../../generators/chipyard/src/main/scala/HarnessBinders.scala 27 | :language: scala 28 | :start-after: DOC include start: HarnessClockInstantiatorEx 29 | :end-before: DOC include end: HarnessClockInstantiatorEx 30 | 31 | Here you can see the ``p(HarnessClockInstantiatorKey)`` is used to request a clock and reset at ``memFreq`` frequency. 32 | 33 | .. note:: 34 | In the case that the reference clock entering ``ChipTop`` is not the overall reference clock of the simulation 35 | (i.e. the clock/reset coming into the ``TestHarness`` module), the ``buildtopClock`` and ``buildtopReset`` can 36 | differ from the implicit ``TestHarness`` clock and reset. For example, if the ``ChipTop`` reference is 500MHz but an 37 | extra harness clock is requested at 1GHz, the ``TestHarness`` implicit clock/reset will be at 1GHz while the ``buildtopClock`` 38 | and ``buildtopReset`` will be at 500MHz. 39 | -------------------------------------------------------------------------------- /docs/Advanced-Concepts/Resources.rst: -------------------------------------------------------------------------------- 1 | Accessing Scala Resources 2 | =============================== 3 | 4 | A simple way to copy over a source file to the build directory to be used for a simulation compile or VLSI flow is to use the ``addResource`` function given by FIRRTL. 5 | An example of its use can be seen in `generators/testchipip/src/main/scala/SerialAdapter.scala `_. 6 | Here is the example inlined: 7 | 8 | .. code-block:: scala 9 | 10 | class SimSerial(w: Int) extends BlackBox with HasBlackBoxResource { 11 | val io = IO(new Bundle { 12 | val clock = Input(Clock()) 13 | val reset = Input(Bool()) 14 | val serial = Flipped(new SerialIO(w)) 15 | val exit = Output(Bool()) 16 | }) 17 | 18 | addResource("/testchipip/vsrc/SimSerial.v") 19 | addResource("/testchipip/csrc/SimSerial.cc") 20 | } 21 | 22 | In this example, the ``SimSerial`` files will be copied from a specific folder (in this case the ``path/to/testchipip/src/main/resources/testchipip/...``) to the build folder. 23 | The ``addResource`` path retrieves resources from the ``src/main/resources`` directory. 24 | So to get an item at ``src/main/resources/fileA.v`` you can use ``addResource("/fileA.v")``. 25 | However, one caveat of this approach is that to retrieve the file during the FIRRTL compile, you must have that project in the FIRRTL compiler's classpath. 26 | Thus, you need to add the SBT project as a dependency to the FIRRTL compiler in the Chipyard ``build.sbt``, which in Chipyards case is the ``tapeout`` project. 27 | For example, you added a new project called ``myAwesomeAccel`` in the Chipyard ``build.sbt``. 28 | Then you can add it as a ``dependsOn`` dependency to the ``tapeout`` project. 29 | For example: 30 | 31 | .. code-block:: scala 32 | 33 | lazy val myAwesomeAccel = (project in file("generators/myAwesomeAccelFolder")) 34 | .dependsOn(rocketchip) 35 | .settings(commonSettings) 36 | 37 | lazy val tapeout = conditionalDependsOn(project in file("./tools/barstools/tapeout/")) 38 | .dependsOn(myAwesomeAccel) 39 | .settings(commonSettings) 40 | -------------------------------------------------------------------------------- /docs/Advanced-Concepts/index.rst: -------------------------------------------------------------------------------- 1 | Advanced Concepts 2 | ================================ 3 | 4 | The following sections are advanced topics about how to Chipyard works, how to use Chipyard, and special features of the framework. 5 | They expect you to know about Chisel, Parameters, configs, etc. 6 | 7 | .. toctree:: 8 | :maxdepth: 2 9 | :caption: Advanced Concepts: 10 | 11 | Top-Testharness 12 | Chip-Communication 13 | Debugging-RTL 14 | Debugging-BOOM 15 | Resources 16 | CDEs 17 | Harness-Clocks 18 | Managing-Published-Scala-Dependencies 19 | 20 | -------------------------------------------------------------------------------- /docs/Chipyard-Basics/Development-Ecosystem.rst: -------------------------------------------------------------------------------- 1 | Development Ecosystem 2 | =============================== 3 | 4 | Chipyard Approach 5 | ------------------------------------------- 6 | 7 | The trend towards agile hardware design and evaluation provides an ecosystem of debugging and implementation tools, that make it easier for computer architecture researchers to develop novel concepts. 8 | Chipyard hopes to build on this prior work in order to create a singular location to which multiple projects within the `Berkeley Architecture Research `__ can coexist and be used together. 9 | Chipyard aims to be the "one-stop shop" for creating and testing your own unique System on a Chip (SoC). 10 | 11 | Chisel/FIRRTL 12 | ------------------------------------------- 13 | 14 | One of the tools to help create new RTL designs quickly is the `Chisel Hardware Construction Language `__ and the `FIRRTL Compiler `__. 15 | Chisel is an embedded language within Scala that provides a set of libraries to help hardware designers create highly parameterizable RTL. 16 | FIRRTL on the other hand is a compiler for hardware which allows the user to run FIRRTL passes that can do dead code elimination, circuit analysis, connectivity checks, and much more! 17 | These two tools in combination allow quick design space exploration and development of new RTL. 18 | 19 | RTL Generators 20 | ------------------------------------------- 21 | 22 | Within this repository, all of the Chisel RTL is written as generators. 23 | Generators are parametrized programs designed to generate RTL code based on configuration specifications. 24 | Generators can be used to generate Systems-on-Chip (SoCs) using a collection of system components organized in unique generator projects. 25 | Generators allow you to create a family of SoC designs instead of a single instance of a design! 26 | -------------------------------------------------------------------------------- /docs/Chipyard-Basics/index.rst: -------------------------------------------------------------------------------- 1 | Chipyard Basics 2 | ================================ 3 | 4 | These sections will walk you through the basics of the Chipyard framework: 5 | 6 | - First, we will go over the components of the framework. 7 | 8 | - Next, we will go over how to understand how Chipyard configures its designs. 9 | 10 | - Then, we will go over initial framework setup. 11 | 12 | Hit next to get started! 13 | 14 | .. toctree:: 15 | :maxdepth: 2 16 | :caption: Chipyard Basics: 17 | 18 | Chipyard-Components 19 | Development-Ecosystem 20 | Configs-Parameters-Mixins 21 | Initial-Repo-Setup 22 | 23 | 24 | -------------------------------------------------------------------------------- /docs/Customization/Custom-Chisel.rst: -------------------------------------------------------------------------------- 1 | .. _custom_chisel: 2 | 3 | Integrating Custom Chisel Projects into the Generator Build System 4 | ================================================================== 5 | 6 | .. warning:: 7 | This section assumes integration of custom Chisel through git submodules. 8 | While it is possible to directly commit custom Chisel into the Chipyard framework, 9 | we heavily recommend managing custom code through git submodules. Using submodules decouples 10 | development of custom features from development on the Chipyard framework. 11 | 12 | 13 | While developing, you want to include Chisel code in a submodule so that it can be shared by different projects. 14 | To add a submodule to the Chipyard framework, make sure that your project is organized as follows. 15 | 16 | .. code-block:: none 17 | 18 | yourproject/ 19 | build.sbt 20 | src/main/scala/ 21 | YourFile.scala 22 | 23 | Put this in a git repository and make it accessible. 24 | Then add it as a submodule to under the following directory hierarchy: ``generators/yourproject``. 25 | 26 | The ``build.sbt`` is a minimal file which describes metadata for a Chisel project. 27 | For a simple project, the ``build.sbt`` can even be empty, but below we provide an example 28 | build.sbt. 29 | 30 | .. code-block:: scala 31 | 32 | organization := "edu.berkeley.cs" 33 | 34 | version := "1.0" 35 | 36 | name := "yourproject" 37 | 38 | scalaVersion := "2.12.4" 39 | 40 | 41 | 42 | .. code-block:: shell 43 | 44 | cd generators/ 45 | git submodule add https://git-repository.com/yourproject.git 46 | 47 | Then add ``yourproject`` to the Chipyard top-level build.sbt file. 48 | 49 | .. code-block:: scala 50 | 51 | lazy val yourproject = (project in file("generators/yourproject")).settings(commonSettings).dependsOn(rocketchip) 52 | 53 | You can then import the classes defined in the submodule in a new project if 54 | you add it as a dependency. For instance, if you want to use this code in 55 | the ``chipyard`` project, change the final line in build.sbt to the following. 56 | 57 | .. code-block:: scala 58 | 59 | lazy val chipyard = (project in file(".")).settings(commonSettings).dependsOn(testchipip, yourproject) 60 | -------------------------------------------------------------------------------- /docs/Customization/DMA-Devices.rst: -------------------------------------------------------------------------------- 1 | .. _dma-devices: 2 | 3 | Adding a DMA Device 4 | =================== 5 | 6 | DMA devices are Tilelink widgets which act as masters. In other words, 7 | DMA devices can send their own read and write requests to the chip's memory 8 | system. 9 | 10 | For IO devices or accelerators (like a disk or network driver), instead of 11 | having the CPU poll data from the device, we may want to have the device write 12 | directly to the coherent memory system instead. For example, here is a device 13 | that writes zeros to the memory at a configured address. 14 | 15 | .. literalinclude:: ../../generators/chipyard/src/main/scala/example/InitZero.scala 16 | :language: scala 17 | 18 | .. literalinclude:: ../../generators/chipyard/src/main/scala/DigitalTop.scala 19 | :language: scala 20 | :start-after: DOC include start: DigitalTop 21 | :end-before: DOC include end: DigitalTop 22 | 23 | We use ``TLHelper.makeClientNode`` to create a TileLink client node for us. 24 | We then connect the client node to the memory system through the front bus (fbus). 25 | For more info on creating TileLink client nodes, take a look at :ref:`TileLink-Diplomacy-Reference/NodeTypes:Client Node`. 26 | 27 | Once we've created our top-level module including the DMA widget, we can create a configuration for it as we did before. 28 | 29 | .. literalinclude:: ../../generators/chipyard/src/main/scala/example/InitZero.scala 30 | :language: scala 31 | :start-after: DOC include start: WithInitZero 32 | :end-before: DOC include end: WithInitZero 33 | 34 | .. literalinclude:: ../../generators/chipyard/src/main/scala/config/RocketConfigs.scala 35 | :language: scala 36 | :start-after: DOC include start: InitZeroRocketConfig 37 | :end-before: DOC include end: InitZeroRocketConfig 38 | 39 | 40 | -------------------------------------------------------------------------------- /docs/Customization/RoCC-or-MMIO.rst: -------------------------------------------------------------------------------- 1 | .. _rocc-vs-mmio: 2 | 3 | RoCC vs MMIO 4 | ------------ 5 | 6 | Accelerators or custom IO devices can be added to your SoC in several ways: 7 | 8 | * MMIO Peripheral (a.k.a TileLink-Attached Accelerator) 9 | * Tightly-Coupled RoCC Accelerator 10 | 11 | These approaches differ in the method of the communication between the processor and the custom block. 12 | 13 | With the TileLink-Attached approach, the processor communicates with MMIO peripherals through memory-mapped registers. 14 | 15 | In contrast, the processor communicates with a RoCC accelerators through a custom protocol and custom non-standard ISA instructions reserved in the RISC-V ISA encoding space. 16 | Each core can have up to four accelerators that are controlled by custom instructions and share resources with the CPU. 17 | RoCC coprocessor instructions have the following form. 18 | 19 | .. code-block:: none 20 | 21 | customX rd, rs1, rs2, funct 22 | 23 | The X will be a number 0-3, and determines the opcode of the instruction, which controls which accelerator an instruction will be routed to. 24 | The ``rd``, ``rs1``, and ``rs2`` fields are the register numbers of the destination register and two source registers. 25 | The ``funct`` field is a 7-bit integer that the accelerator can use to distinguish different instructions from each other. 26 | 27 | Note that communication through a RoCC interface requires a custom software toolchain, whereas MMIO peripherals can use that standard toolchain with appropriate driver support. 28 | -------------------------------------------------------------------------------- /docs/Customization/index.rst: -------------------------------------------------------------------------------- 1 | Customization 2 | ================================ 3 | 4 | These guides will walk you through customization of your system-on-chip: 5 | 6 | - Contructing heterogenous systems-on-chip using the existing Chipyard generators and configuration system. 7 | 8 | - How to include your custom Chisel sources in the Chipyard build system 9 | 10 | - Adding custom core 11 | 12 | - Adding custom RoCC accelerators to an existing Chipyard core (BOOM or Rocket) 13 | 14 | - Adding custom MMIO widgets to the Chipyard memory system by Tilelink or AXI4, with custom Top-level IOs 15 | 16 | - Adding custom Dsptools based blocks as MMIO widgets. 17 | 18 | - Standard practices for using Keys, Traits, and Configs to parameterize your design 19 | 20 | - Customizing the memory hierarchy 21 | 22 | - Connect widgets which act as TileLink masters 23 | 24 | - Adding custom blackboxed Verilog to a Chipyard design 25 | 26 | We also provide information on: 27 | 28 | - The boot process for Chipyard SoCs 29 | 30 | - Examples of FIRRTL transforms used in Chipyard, and where they are specified 31 | 32 | We recommend reading all these pages in order. Hit next to get started! 33 | 34 | .. toctree:: 35 | :maxdepth: 2 36 | :caption: Customization: 37 | 38 | Heterogeneous-SoCs 39 | Custom-Chisel 40 | Custom-Core 41 | RoCC-or-MMIO 42 | RoCC-Accelerators 43 | MMIO-Peripherals 44 | Dsptools-Blocks 45 | Keys-Traits-Configs 46 | DMA-Devices 47 | Incorporating-Verilog-Blocks 48 | Memory-Hierarchy 49 | Boot-Process 50 | Firrtl-Transforms 51 | IOBinders 52 | -------------------------------------------------------------------------------- /docs/Generators/BOOM.rst: -------------------------------------------------------------------------------- 1 | Berkeley Out-of-Order Machine (BOOM) 2 | ============================================== 3 | 4 | .. image:: ../_static/images/boom-pipeline-detailed.png 5 | 6 | The `Berkeley Out-of-Order Machine (BOOM) `__ is a synthesizable and parameterizable open source RV64GC RISC-V core written in the Chisel hardware construction language. 7 | It serves as a drop-in replacement to the Rocket core given by Rocket Chip (replaces the RocketTile with a BoomTile). 8 | BOOM is heavily inspired by the MIPS R10k and the Alpha 21264 out-of-order processors. 9 | Like the R10k and the 21264, BOOM is a unified physical register file design (also known as “explicit register renaming”). 10 | Conceptually, BOOM is broken up into 10 stages: Fetch, Decode, Register Rename, Dispatch, Issue, Register Read, Execute, Memory, Writeback and Commit. 11 | However, many of those stages are combined in the current implementation, yielding seven stages: Fetch, Decode/Rename, Rename/Dispatch, Issue/RegisterRead, Execute, Memory and Writeback (Commit occurs asynchronously, so it is not counted as part of the “pipeline”). 12 | 13 | Additional information about the BOOM micro-architecture can be found in the `BOOM documentation pages `__. 14 | -------------------------------------------------------------------------------- /docs/Generators/CVA6.rst: -------------------------------------------------------------------------------- 1 | CVA6 Core 2 | ==================================== 3 | 4 | `CVA6 `__ (previously called Ariane) is a 6-stage in-order scalar processor core, originally developed at ETH-Zurich by F. Zaruba and L. Benini. 5 | The `CVA6 core` is wrapped in an `CVA6 tile` so it can be used as a component within the `Rocket Chip SoC generator`. 6 | The core by itself exposes an AXI interface, interrupt ports, and other misc. ports that are connected from within the tile to TileLink buses and other parameterization signals. 7 | 8 | .. Warning:: Since the core uses an AXI interface to connect to memory, it is highly recommended to use the core in a single-core setup (since AXI is a non-coherent memory interface). 9 | 10 | While the core itself is not a generator, we expose the same parameterization that the CVA6 core provides (i.e. change branch prediction parameters). 11 | 12 | .. Warning:: This target does not support Verilator simulation at this time. Please use VCS. 13 | 14 | For more information, please refer to the `GitHub repository `__. 15 | -------------------------------------------------------------------------------- /docs/Generators/Gemmini.rst: -------------------------------------------------------------------------------- 1 | Gemmini 2 | ==================================== 3 | 4 | The Gemmini project is developing a full-system, full-stack DNN hardware exploration and evaluation platform. 5 | Gemmini enables architects to make useful insights into how different components of the system and software stack (outside of just the accelerator itself) interact to affect overall DNN performance. 6 | 7 | Check out `Gemmini's documentation `__ to learn how to generate, simulate, and profile DNN accelerators with Gemmini and Chipyard. 8 | 9 | .. image:: ../_static/images/gemmini-system.png 10 | 11 | -------------------------------------------------------------------------------- /docs/Generators/Hwacha.rst: -------------------------------------------------------------------------------- 1 | Hwacha 2 | ==================================== 3 | 4 | The Hwacha project is developing a new vector architecture for future computer systems that are constrained in their power and energy consumption. 5 | The Hwacha project is inspired by traditional vector machines from the 70s and 80s, and lessons learned from our previous vector-thread architectures such as Scale and Maven 6 | The Hwacha project includes the Hwacha microarchitecture generator, as well as the ``XHwacha`` non-standard RISC-V extension. Hwacha does not implement the RISC-V standard vector extension proposal. 7 | 8 | For more information on the Hwacha project, please visit the `Hwacha website `__. 9 | 10 | To add the Hwacha vector unit to an SoC, you should add the ``hwacha.DefaultHwachaConfig`` config fragment to the SoC configurations. The Hwacha vector unit uses the RoCC port of a Rocket or BOOM `tile`, and by default connects to the memory system through the `System Bus` (i.e., directly to the L2 cache). 11 | 12 | To change the configuration of the Hwacha vector unit, you can write a custom configuration to replace the ``DefaultHwachaConfig``. You can view the ``DefaultHwachaConfig`` under `generators/hwacha/src/main/scala/configs.scala `__ to see the possible configuration parameters. 13 | 14 | Since Hwacha implements a non-standard RISC-V extension, it requires a unique software toolchain to be able to compile and assemble its vector instructions. 15 | To install the Hwacha toolchain, run the ``./scripts/build-toolchains.sh esp-tools`` command within the root Chipyard directory. This may take a while, and it will install the ``esp-tools-install`` directory within your Chipyard root directory. ``esp-tools`` is a fork of ``riscv-tools`` (formerly a collection of relevant software RISC-V tools) that was enhanced with additional non-standard vector instructions. However, due to the upstreaming of the equivalent RISC-V toolchains, ``esp-tools`` may not be up-to-date with the latest mainline version of the tools included in it. 16 | -------------------------------------------------------------------------------- /docs/Generators/Ibex.rst: -------------------------------------------------------------------------------- 1 | Ibex Core 2 | ==================================== 3 | 4 | `Ibex `__ is a parameterizable RV32IMC embedded core written in SystemVerilog, currently maintained by `lowRISC `__. 5 | The `Ibex core` is wrapped in an `Ibex tile` so it can be used with the `Rocket Chip SoC generator`. 6 | The core exposes a custom memory interface, interrupt ports, and other misc. ports that are connected from within the tile to TileLink buses and other parameterization signals. 7 | 8 | .. Warning:: The Ibex mtvec register is 256 byte aligned. When writing/running tests, ensure that the trap vector is also 256 byte aligned. 9 | 10 | .. Warning:: The Ibex reset vector is located at BOOT_ADDR + 0x80. 11 | 12 | While the core itself is not a generator, we expose the same parameterization that the Ibex core provides so that all supported Ibex configurations are available. 13 | 14 | For more information, see the `GitHub repository for Ibex `__. -------------------------------------------------------------------------------- /docs/Generators/NVDLA.rst: -------------------------------------------------------------------------------- 1 | NVDLA 2 | ==================================== 3 | 4 | `NVDLA `_ is an open-source deep learning accelerator developed by NVIDIA. 5 | The `NVDLA` is attached as a TileLink peripheral so it can be used as a component within the `Rocket Chip SoC generator`. 6 | The accelerator by itself exposes an AXI memory interface (or two if you use the "Large" configuration), a control interface, and an interrupt line. 7 | The main way to use the accelerator in Chipyard is to use the `NVDLA SW repository `_ that was ported to work on FireSim Linux. 8 | However, you can also use the accelerator in baremetal simulations (refer to ``tests/nvdla.c``). 9 | 10 | For more information on both the HW architecture and the SW, please visit their `website `_. 11 | 12 | NVDLA Software with FireMarshal 13 | ------------------------------- 14 | 15 | Located at ``software/nvdla-workload`` is a FireMarshal-based workload to boot Linux with the proper NVDLA drivers. 16 | Refer to that ``README.md`` for more information on how to run a simulation. 17 | -------------------------------------------------------------------------------- /docs/Generators/Rocket.rst: -------------------------------------------------------------------------------- 1 | Rocket Core 2 | ==================================== 3 | 4 | `Rocket `__ is a 5-stage in-order scalar processor core generator, originally developed at UC Berkeley and currently supported by `SiFive `__. The `Rocket core` is used as a component within the `Rocket Chip SoC generator`. A Rocket core combined with L1 caches (data and instruction caches) form a `Rocket tile`. The `Rocket tile` is the replicable component of the `Rocket Chip SoC generator`. 5 | 6 | The Rocket core supports the open-source RV64GC RISC-V instruction set and is written in the Chisel hardware construction language. 7 | It has an MMU that supports page-based virtual memory, a non-blocking data cache, and a front-end with branch prediction. 8 | Branch prediction is configurable and provided by a branch target buffer (BTB), branch history table (BHT), and a return address stack (RAS). 9 | For floating-point, Rocket makes use of Berkeley’s Chisel implementations of floating-point units. 10 | Rocket also supports the RISC-V machine, supervisor, and user privilege levels. 11 | A number of parameters are exposed, including the optional support of some ISA extensions (M, A, F, D), the number of floating-point pipeline stages, and the cache and TLB sizes. 12 | 13 | For more information, please refer to the `GitHub repository `__, `technical report `__ or to `this Chisel Community Conference video `__. 14 | -------------------------------------------------------------------------------- /docs/Generators/SiFive-Generators.rst: -------------------------------------------------------------------------------- 1 | SiFive Generators 2 | ================== 3 | 4 | Chipyard includes several open-source generators developed and maintained by `SiFive `__. 5 | These are currently organized within two submodules named ``sifive-blocks`` and ``sifive-cache``. 6 | 7 | Last-Level Cache Generator 8 | ----------------------------- 9 | 10 | ``sifive-cache`` includes last-level cache geneator. The Chipyard framework uses this last-level cache as an L2 cache. To use this L2 cache, you should add the ``freechips.rocketchip.subsystem.WithInclusiveCache`` config fragment to your SoC configuration. 11 | To learn more about configuring this L2 cache, please refer to the :ref:`memory-hierarchy` section. 12 | 13 | 14 | Peripheral Devices 15 | ------------------- 16 | ``sifive-blocks`` includes multiple peripheral device generators, such as UART, SPI, PWM, JTAG, GPIO and more. 17 | 18 | These peripheral devices usually affect the memory map of the SoC, and its top-level IO as well. 19 | To integrate one of these devices in your SoC, you will need to define a custom config fragment with the approriate address for the device using the Rocket Chip parameter system. As an example, for a GPIO device you could add the following config fragment to set the GPIO address to ``0x10012000``. This address is the start address for the GPIO configuration registers. 20 | 21 | .. literalinclude:: ../../generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala 22 | :language: scala 23 | :start-after: DOC include start: gpio config fragment 24 | :end-before: DOC include end: gpio config fragment 25 | 26 | Additionally, if the device requires top-level IOs, you will need to define a config fragment to change the top-level configuration of your SoC. 27 | When adding a top-level IO, you should also be aware of whether it interacts with the test-harness. 28 | 29 | This example instantiates a top-level module with include GPIO ports, and then ties-off the GPIO port inputs to 0 (``false.B``). 30 | 31 | 32 | Finally, you add the relevant config fragment to the SoC config. For example: 33 | 34 | .. literalinclude:: ../../generators/chipyard/src/main/scala/config/RocketConfigs.scala 35 | :language: scala 36 | :start-after: DOC include start: GPIORocketConfig 37 | :end-before: DOC include end: GPIORocketConfig 38 | 39 | Some of the devices in ``sifive-blocks`` (such as GPIO) may already have pre-defined config fragments within the Chipyard example project. You may be able to use these config fragments directly, but you should be aware of their addresses within the SoC address map. 40 | -------------------------------------------------------------------------------- /docs/Generators/Sodor.rst: -------------------------------------------------------------------------------- 1 | Sodor Core 2 | ==================================== 3 | 4 | `Sodor `__ is a collection of 5 simple RV32MI cores designed for educational purpose. 5 | The `Sodor core` is wrapped in an tile during generation so it can be used as a component within the `Rocket Chip SoC generator`. 6 | The cores contain a small scratchpad memory to which the program are loaded through a TileLink slave port, and the cores **DO NOT** 7 | support external memory. 8 | 9 | The five available cores and their corresponding generator configuration are: 10 | 11 | * 1-stage (essentially an ISA simulator) - ``Sodor1StageConfig`` 12 | * 2-stage (demonstrates pipelining in Chisel) - ``Sodor2StageConfig`` 13 | * 3-stage (uses sequential memory; supports both Harvard (``Sodor3StageConfig``) and Princeton (``Sodor3StageSinglePortConfig``) versions) 14 | * 5-stage (can toggle between fully bypassed or fully interlocked) - ``Sodor5StageConfig`` 15 | * "bus"-based micro-coded implementation - ``SodorUCodeConfig`` 16 | 17 | For more information, please refer to the `GitHub repository `__. 18 | -------------------------------------------------------------------------------- /docs/Generators/index.rst: -------------------------------------------------------------------------------- 1 | .. _generator-index: 2 | 3 | Included RTL Generators 4 | ============================ 5 | 6 | A Generator can be thought of as a generalized RTL design, written using a mix of meta-programming and standard RTL. 7 | This type of meta-programming is enabled by the Chisel hardware description language (see :ref:`Tools/Chisel:Chisel`). 8 | A standard RTL design is essentially just a single instance of a design coming from a generator. 9 | However, by using meta-programming and parameter systems, generators can allow for integration of complex hardware designs in automated ways. 10 | The following pages introduce the generators integrated with the Chipyard framework. 11 | 12 | Chipyard bundles the source code for the generators, under the ``generators/`` directory. 13 | It builds them from source each time (although the build system will cache results if they have not changed), 14 | so changes to the generators themselves will automatically be used when building with Chipyard and propagate to software simulation, FPGA-accelerated simulation, and VLSI flows. 15 | 16 | 17 | .. toctree:: 18 | :maxdepth: 2 19 | :caption: Generators: 20 | 21 | Rocket-Chip 22 | Rocket 23 | BOOM 24 | Hwacha 25 | Gemmini 26 | IceNet 27 | TestChipIP 28 | SiFive-Generators 29 | SHA3 30 | CVA6 31 | Ibex 32 | fft 33 | NVDLA 34 | Sodor 35 | 36 | -------------------------------------------------------------------------------- /docs/Makefile: -------------------------------------------------------------------------------- 1 | # Minimal makefile for Sphinx documentation 2 | # 3 | 4 | # You can set these variables from the command line. 5 | SPHINXOPTS = -w warnings.txt -n -W 6 | SPHINXBUILD = python3 -msphinx 7 | SPHINXPROJ = Chipyard 8 | SOURCEDIR = . 9 | BUILDDIR = _build 10 | 11 | # Put it first so that "make" without argument is like "make help". 12 | help: 13 | @$(SPHINXBUILD) -M help "$(SOURCEDIR)" "$(BUILDDIR)" $(SPHINXOPTS) $(O) 14 | 15 | .PHONY: help Makefile 16 | 17 | # Catch-all target: route all unknown targets to Sphinx using the new 18 | # "make mode" option. $(O) is meant as a shortcut for $(SPHINXOPTS). 19 | %: Makefile 20 | @$(SPHINXBUILD) -M $@ "$(SOURCEDIR)" "$(BUILDDIR)" $(SPHINXOPTS) $(O) 21 | -------------------------------------------------------------------------------- /docs/Prototyping/index.rst: -------------------------------------------------------------------------------- 1 | Prototyping Flow 2 | ================ 3 | 4 | Chipyard supports FPGA prototyping for local FPGAs supported by `fpga-shells `__. 5 | This includes popular FPGAs such as the Xilinx VCU118 and the Xilinx Arty 35T board. 6 | 7 | .. Note:: While ``fpga-shells`` provides harnesses for other FPGA development boards such as the Xilinx VC707 and some MicroSemi PolarFire, only harnesses for the Xilinx VCU118 and Xilinx Arty 35T boards are currently supported in Chipyard. 8 | However, the VCU118 and Arty 35T examples demonstrate how a user may implement support for other harnesses provided by fpga-shells. 9 | 10 | .. toctree:: 11 | :maxdepth: 2 12 | :caption: Prototyping Flow: 13 | 14 | General 15 | VCU118 16 | Arty 17 | -------------------------------------------------------------------------------- /docs/Simulation/index.rst: -------------------------------------------------------------------------------- 1 | Simulation 2 | ======================= 3 | 4 | Chipyard supports two classes of simulation: 5 | 6 | #. Software RTL simulation using commercial or open-source (Verilator) RTL simulators 7 | #. FPGA-accelerated full-system simulation using FireSim 8 | 9 | Software RTL simulators of Chipyard designs run at O(1 KHz), but compile 10 | quickly and provide full waveforms. Conversely, FPGA-accelerated simulators run 11 | at O(100 MHz), making them appropriate for booting an operating system and 12 | running a complete workload, but have multi-hour compile times and poorer debug 13 | visibility. 14 | 15 | Click next to see how to run a simulation. 16 | 17 | .. toctree:: 18 | :maxdepth: 2 19 | :caption: Simulation: 20 | 21 | Software-RTL-Simulation 22 | FPGA-Accelerated-Simulation 23 | -------------------------------------------------------------------------------- /docs/Software/Baremetal.rst: -------------------------------------------------------------------------------- 1 | .. _baremetal-programs: 2 | 3 | Baremetal RISC-V Programs 4 | ========================== 5 | 6 | To build baremetal RISC-V programs to run in simulation, we use the riscv64-unknown-elf cross-compiler and a fork of the libgloss board support package. To build such a program yourself, simply invoke the cross-compiler with the flags "-fno-common -fno-builtin-printf -specs=htif_nano.specs" and the link with the arguments "-static -specs=htif_nano.specs". For instance, if we want to run a "Hello, World" program in baremetal, we could do the following. 7 | 8 | .. code:: c 9 | 10 | #include 11 | 12 | int main(void) 13 | { 14 | printf("Hello, World!\n"); 15 | return 0; 16 | } 17 | 18 | .. code:: bash 19 | 20 | $ riscv64-unknown-elf-gcc -fno-common -fno-builtin-printf -specs=htif_nano.specs -c hello.c 21 | $ riscv64-unknown-elf-gcc -static -specs=htif_nano.specs hello.o -o hello.riscv 22 | $ spike hello.riscv 23 | Hello, World! 24 | 25 | For more examples, look at the `tests/ directory `_ in the chipyard repository. 26 | 27 | For more information about the libgloss port, take a look at `its README `_. 28 | -------------------------------------------------------------------------------- /docs/Software/FireMarshal.rst: -------------------------------------------------------------------------------- 1 | .. _fire-marshal: 2 | 3 | FireMarshal 4 | ================= 5 | 6 | FireMarshal is a workload generation tool for RISC-V based systems. It 7 | currently only supports the FireSim FPGA-accelerated simulation platform. 8 | 9 | **Workloads** in FireMarshal consist of a series of **Jobs** that are assigned 10 | to logical nodes in the target system. If no jobs are specified, then the 11 | workload is considered ``uniform`` and only a single image will be produced for 12 | all nodes in the system. Workloads are described by a ``json`` file and a 13 | corresponding workload directory and can inherit their definitions from 14 | existing workloads. Typically, workload configurations are kept in 15 | ``workloads/`` although you can use any directory you like. We provide a few 16 | basic workloads to start with including buildroot or Fedora-based linux 17 | distributions and bare-metal. 18 | 19 | Once you define a workload, the ``marshal`` command will produce a 20 | corresponding boot-binary and rootfs for each job in the workload. This binary 21 | and rootfs can then be launched on qemu or spike (for functional simulation), or 22 | installed to a platform for running on real RTL (currently only FireSim is 23 | automated). 24 | 25 | To get started, checkout the full `FireMarshal documentation `_. 26 | -------------------------------------------------------------------------------- /docs/Software/Spike.rst: -------------------------------------------------------------------------------- 1 | The RISC-V ISA Simulator (Spike) 2 | ================================= 3 | 4 | Spike is the golden reference functional RISC-V ISA C++ sofware simulator. 5 | It provides full system emulation or proxied emulation with `HTIF/FESVR `__. 6 | It serves as a starting point for running software on a RISC-V target. 7 | Here is a highlight of some of Spikes main features: 8 | 9 | * Multiple ISAs: RV32IMAFDQCV extensions 10 | * Multiple memory models: Weak Memory Ordering (WMO) and Total Store Ordering (TSO) 11 | * Privileged Spec: Machine, Supervisor, User modes (v1.11) 12 | * Debug Spec 13 | * Single-step debugging with support for viewing memory/register contents 14 | * Multiple CPU support 15 | * JTAG support 16 | * Highly extensible (add and test new instructions) 17 | 18 | In most cases, software development for a Chipyard target will begin with functional simulation using Spike 19 | (usually with the addition of custom Spike models for custom accelerator functions), and only later move on to 20 | full cycle-accurate simulation using software RTL simulators or FireSim. 21 | 22 | Spike comes pre-packaged in the RISC-V toolchain and is available on the path as ``spike``. 23 | More information can be found in the `Spike repository `__. 24 | -------------------------------------------------------------------------------- /docs/Software/index.rst: -------------------------------------------------------------------------------- 1 | Target Software 2 | ================================== 3 | 4 | Chipyard includes tools for developing target software workloads. The primary 5 | tool is FireMarshal, which manages workload descriptions and generates binaries 6 | and disk images to run on your target designs. Workloads can be bare-metal, or 7 | be based on standard Linux distributions. Users can customize every part of the 8 | build process, including providing custom kernels (if needed by the hardware). 9 | 10 | FireMarshal can also run your workloads on high-performance functional 11 | simulators like Spike and Qemu. Spike is easily customized and serves as the 12 | official RISC-V ISA reference implementation. Qemu is a high-performance 13 | functional simulator that can run nearly as fast as native code, but can be 14 | challenging to modify. 15 | 16 | To initialize additional software repositories, such as wrappers for Coremark, 17 | SPEC2017, and workloads for the NVDLA, run the following script. The 18 | submodules are located in the ``software`` directory. 19 | 20 | .. code-block:: shell 21 | 22 | ./scripts/init-software.sh 23 | 24 | 25 | .. toctree:: 26 | :maxdepth: 2 27 | :caption: Contents: 28 | 29 | FireMarshal 30 | Spike 31 | Baremetal 32 | -------------------------------------------------------------------------------- /docs/TileLink-Diplomacy-Reference/Diplomacy-Connectors.rst: -------------------------------------------------------------------------------- 1 | Diplomacy Connectors 2 | ==================== 3 | 4 | Nodes in a Diplomacy graph are connected to each other with edges. The Diplomacy 5 | library provides four operators that can be used to form edges between nodes. 6 | 7 | := 8 | -- 9 | 10 | This is the basic connection operator. It is the same syntax as the Chisel 11 | uni-directional connector, but it is not equivalent. This operator connects 12 | Diplomacy nodes, not Chisel bundles. 13 | 14 | The basic connection operator always creates a single edge between the two 15 | nodes. 16 | 17 | :=\* 18 | ---- 19 | 20 | This is a "query" type connection operator. It can create multiple edges 21 | between nodes, with the number of edges determined by the client node 22 | (the node on the right side of the operator). This can be useful if you 23 | are connecting a multi-edge client to a nexus node or adapter node. 24 | 25 | :\*= 26 | ---- 27 | 28 | This is a "star" type connection operator. It also creates multiple edges, 29 | but the number of edges is determined by the manager (left side of operator), 30 | rather than the client. It's useful for connecting nexus nodes to multi-edge 31 | manager nodes. 32 | 33 | :\*=\* 34 | ------ 35 | 36 | This is a "flex" connection operator. It creates multiple edges based on 37 | whichever side of the operator has a known number of edges. This can be used 38 | in generators where the type of node on either side isn't known until runtime. 39 | -------------------------------------------------------------------------------- /docs/TileLink-Diplomacy-Reference/index.rst: -------------------------------------------------------------------------------- 1 | .. _tilelink_and_diplomacy: 2 | 3 | TileLink and Diplomacy Reference 4 | ================================ 5 | 6 | TileLink is the cache coherence and memory protocol used by RocketChip and 7 | other Chipyard generators. It is how different modules like caches, memories, 8 | peripherals, and DMA devices communicate with each other. 9 | 10 | RocketChip's TileLink implementation is built on top of Diplomacy, a framework 11 | for exchanging configuration information among Chisel generators in a two-phase 12 | elaboration scheme. For a detailed explanation of Diplomacy, see `the paper 13 | by Cook, Terpstra, and Lee `_. 14 | 15 | A brief overview of how to connect simple TileLink widgets can be found 16 | in the :ref:`mmio-accelerators` section. This section will provide a 17 | detailed reference for the TileLink and Diplomacy functionality provided by 18 | RocketChip. 19 | 20 | A detailed specification of the TileLink 1.7 protocol can be found on the 21 | `SiFive website `_. 22 | 23 | 24 | .. toctree:: 25 | :maxdepth: 2 26 | :caption: Reference 27 | 28 | NodeTypes 29 | Diplomacy-Connectors 30 | EdgeFunctions 31 | Register-Router 32 | Widgets 33 | -------------------------------------------------------------------------------- /docs/Tools/Chisel-Testers.rst: -------------------------------------------------------------------------------- 1 | Chisel Testers 2 | ============================== 3 | 4 | `Chisel Testers `__ is a library for writing tests for Chisel designs. 5 | It provides a Scala API for interacting with a DUT. 6 | It can use multiple backends, including things such as Treadle and Verilator. 7 | See :ref:`Tools/Treadle:Treadle and FIRRTL Interpreter` and :ref:`sw-rtl-sim-intro` for more information on these simulation methods. 8 | -------------------------------------------------------------------------------- /docs/Tools/Chisel.rst: -------------------------------------------------------------------------------- 1 | Chisel 2 | =========================== 3 | 4 | `Chisel `__ is an open-source hardware description language embedded in Scala. 5 | It supports advanced hardware design using highly parameterized generators and supports things such as Rocket Chip and BOOM. 6 | 7 | After writing Chisel, there are multiple steps before the Chisel source code "turns into" Verilog. 8 | First is the compilation step. 9 | If Chisel is thought as a library within Scala, then these classes being built are just Scala classes which call Chisel functions. 10 | Thus, any errors that you get in compiling the Scala/Chisel files are errors that you have violated the typing system, messed up syntax, or more. 11 | After the compilation is complete, elaboration begins. 12 | The Chisel generator starts elaboration using the module and configuration classes passed to it. 13 | This is where the Chisel "library functions" are called with the parameters given and Chisel tries to construct a circuit based on the Chisel code. 14 | If a runtime error happens here, Chisel is stating that it cannot "build" your circuit due to "violations" between your code and the Chisel "library". 15 | However, if that passes, the output of the generator gives you an FIRRTL file and other misc collateral! 16 | See :ref:`Tools/FIRRTL:FIRRTL` for more information on how to get a FIRRTL file to Verilog. 17 | 18 | For an interactive tutorial on how to use Chisel and get started please visit the `Chisel Bootcamp `__. 19 | Otherwise, for all things Chisel related including API documentation, news, etc, visit their `website `__. 20 | -------------------------------------------------------------------------------- /docs/Tools/Dromajo.rst: -------------------------------------------------------------------------------- 1 | Dromajo 2 | =============================== 3 | 4 | `Dromajo `__ is a RV64GC functional simulator designed for co-simulation. 5 | To use it as a co-simulator, it requires you to pass the committed trace of instructions coming from the core into the tool. 6 | Within Chipyard, this is done by connecting to the `TracePort`` signals that are piped to the top level of the DUT. 7 | While the Rocket core does have a `TracePort`, it does not provide the committed write data that Dromajo requires. 8 | Thus, Dromajo uses the `ExtendedTracePort` only probided by BOOM (BOOM is the only core that supports Dromajo co-simulation). 9 | An example of a divergence and Dromajo's printout is shown below. 10 | 11 | .. code-block:: shell 12 | 13 | [error] EMU PC ffffffe001055d84, DUT PC ffffffe001055d84 14 | [error] EMU INSN 14102973, DUT INSN 14102973 15 | [error] EMU WDATA 00000000000220d6, DUT WDATA 00000000000220d4 16 | [error] EMU MSTATUS a000000a0, DUT MSTATUS 00000000 17 | [error] DUT pending exception -1 pending interrupt -1 18 | 19 | Dromajo shows the divergence compared to simulation (PC, inst, inst-bits, write data, etc) and also provides the register state on failure. 20 | It is useful to catch bugs that affect architectural state before a simulation hangs or crashes. 21 | 22 | To use Dromajo with BOOM, refer to :ref:`Advanced-Concepts/Debugging-RTL:Debugging RTL` section on Dromajo. 23 | -------------------------------------------------------------------------------- /docs/Tools/Dsptools.rst: -------------------------------------------------------------------------------- 1 | Dsptools 2 | =============================== 3 | 4 | `Dsptools `__ is a Chisel library for writing custom signal processing hardware. 5 | Additionally, dsptools is useful for integrating custom signal processing hardware into an SoC (especially a Rocket-based SoC). 6 | 7 | Some features: 8 | 9 | * Complex type 10 | * Typeclasses for writing polymorphic hardware generators 11 | * For example, write one FIR filter generator that works for real or complex inputs 12 | * Extensions to Chisel testers for fixed point and floating point types 13 | * A diplomatic implementation of AXI4-Stream 14 | * Models for verifying APB, AXI-4, and TileLink interfaces with chisel-testers 15 | * DSP building blocks 16 | -------------------------------------------------------------------------------- /docs/Tools/FIRRTL.rst: -------------------------------------------------------------------------------- 1 | FIRRTL 2 | ================================ 3 | 4 | `FIRRTL `__ is an intermediate representation of your circuit. 5 | It is emitted by the Chisel compiler and is used to translate Chisel source files into another representation such as Verilog. 6 | Without going into too much detail, FIRRTL is consumed by a FIRRTL compiler (another Scala program) which passes the circuit through a series of circuit-level transformations. 7 | An example of a FIRRTL pass (transformation) is one that optimizes out unused signals. 8 | Once the transformations are done, a Verilog file is emitted and the build process is done. 9 | 10 | For more information on please visit their `website `__. 11 | -------------------------------------------------------------------------------- /docs/Tools/Treadle.rst: -------------------------------------------------------------------------------- 1 | Treadle and FIRRTL Interpreter 2 | ============================== 3 | 4 | `Treadle `__ and 5 | `FIRRTL Interpreter `__ 6 | are circuit simulators that directly execute FIRRTL (specifically low-firrtl IR). 7 | Treadle is the replacement for FIRRTL Interpreter but FIRRTL Interpreter is still used within some 8 | projects. Treadle is useful for simulating modules in a larger SoC design. Many projects 9 | use Treadle for interactive debugging and a low-overhead simulator. 10 | -------------------------------------------------------------------------------- /docs/Tools/index.rst: -------------------------------------------------------------------------------- 1 | Development Tools 2 | ============================== 3 | 4 | The Chipyard framework relays heavily on a set of Scala-based tools. 5 | The following pages will introduce them, and how we can use them in order to generate flexible designs. 6 | 7 | .. toctree:: 8 | :maxdepth: 2 9 | :caption: Tools: 10 | 11 | Chisel 12 | FIRRTL 13 | Treadle 14 | Chisel-Testers 15 | Dsptools 16 | Barstools 17 | Dromajo 18 | -------------------------------------------------------------------------------- /docs/VLSI/index.rst: -------------------------------------------------------------------------------- 1 | VLSI Flow 2 | ================================ 3 | 4 | The Chipyard framework aims to provide wrappers for a general VLSI flow. 5 | In particular, we aim to support the Hammer physical design generator flow. 6 | 7 | .. toctree:: 8 | :maxdepth: 2 9 | :caption: VLSI Flow: 10 | 11 | Building-A-Chip 12 | Hammer 13 | Basic-Flow 14 | ASAP7-Tutorial 15 | Sky130-Tutorial 16 | Advanced-Usage 17 | -------------------------------------------------------------------------------- /docs/_static/css/custom.css: -------------------------------------------------------------------------------- 1 | .important { 2 | font-size: 175%; 3 | } 4 | .important p{ 5 | font-size: 100%; 6 | } 7 | -------------------------------------------------------------------------------- /docs/_static/images/boom-pipeline-detailed.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/EECS-NTNU/chipyard/51fea1f8c610001558b4f8eda6fe199993b825ef/docs/_static/images/boom-pipeline-detailed.png -------------------------------------------------------------------------------- /docs/_static/images/bringup-chipyard-config-communication.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/EECS-NTNU/chipyard/51fea1f8c610001558b4f8eda6fe199993b825ef/docs/_static/images/bringup-chipyard-config-communication.png -------------------------------------------------------------------------------- /docs/_static/images/chip-bringup-simulation.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/EECS-NTNU/chipyard/51fea1f8c610001558b4f8eda6fe199993b825ef/docs/_static/images/chip-bringup-simulation.png -------------------------------------------------------------------------------- /docs/_static/images/chip-bringup.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/EECS-NTNU/chipyard/51fea1f8c610001558b4f8eda6fe199993b825ef/docs/_static/images/chip-bringup.png -------------------------------------------------------------------------------- /docs/_static/images/chip-communication.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/EECS-NTNU/chipyard/51fea1f8c610001558b4f8eda6fe199993b825ef/docs/_static/images/chip-communication.png -------------------------------------------------------------------------------- /docs/_static/images/chipyard-logo-full.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/EECS-NTNU/chipyard/51fea1f8c610001558b4f8eda6fe199993b825ef/docs/_static/images/chipyard-logo-full.png -------------------------------------------------------------------------------- /docs/_static/images/chipyard-logo.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/EECS-NTNU/chipyard/51fea1f8c610001558b4f8eda6fe199993b825ef/docs/_static/images/chipyard-logo.png -------------------------------------------------------------------------------- /docs/_static/images/default-chipyard-config-communication.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/EECS-NTNU/chipyard/51fea1f8c610001558b4f8eda6fe199993b825ef/docs/_static/images/default-chipyard-config-communication.png -------------------------------------------------------------------------------- /docs/_static/images/gemmini-system.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/EECS-NTNU/chipyard/51fea1f8c610001558b4f8eda6fe199993b825ef/docs/_static/images/gemmini-system.png -------------------------------------------------------------------------------- /docs/_static/images/nic-design.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/EECS-NTNU/chipyard/51fea1f8c610001558b4f8eda6fe199993b825ef/docs/_static/images/nic-design.png -------------------------------------------------------------------------------- /docs/_static/images/rocketchip-diagram.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/EECS-NTNU/chipyard/51fea1f8c610001558b4f8eda6fe199993b825ef/docs/_static/images/rocketchip-diagram.png -------------------------------------------------------------------------------- /docs/_static/images/sha3.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/EECS-NTNU/chipyard/51fea1f8c610001558b4f8eda6fe199993b825ef/docs/_static/images/sha3.png -------------------------------------------------------------------------------- /docs/index.rst: -------------------------------------------------------------------------------- 1 | Welcome to Chipyard's documentation (version "|version|")! 2 | ========================================================== 3 | 4 | .. image:: ./_static/images/chipyard-logo.svg 5 | 6 | Chipyard is a framework for designing and evaluating full-system hardware using agile teams. 7 | It is composed of a collection of tools and libraries designed to provide an integration between open-source and commercial tools for the development of systems-on-chip. 8 | This work is supported by the NSF CCRI ENS Chipyard Award #201662. 9 | 10 | .. IMPORTANT:: **New to Chipyard?** Jump to the :ref:`Chipyard-Basics/Initial-Repo-Setup:Initial Repository Setup` page for setup instructions. 11 | 12 | Getting Help 13 | ------------ 14 | 15 | If you have a question about Chipyard that isn't answered by the existing 16 | documentation, feel free to ask for help on the 17 | `Chipyard Google Group `_. 18 | 19 | Table of Contents 20 | ----------------- 21 | 22 | .. toctree:: 23 | :maxdepth: 3 24 | :numbered: 25 | 26 | Chipyard-Basics/index 27 | 28 | Simulation/index 29 | 30 | Generators/index 31 | 32 | Tools/index 33 | 34 | VLSI/index 35 | 36 | Customization/index 37 | 38 | Software/index 39 | 40 | Advanced-Concepts/index 41 | 42 | TileLink-Diplomacy-Reference/index 43 | 44 | Prototyping/index 45 | 46 | 47 | Indices and tables 48 | ================== 49 | 50 | * :ref:`genindex` 51 | * :ref:`modindex` 52 | * :ref:`search` 53 | -------------------------------------------------------------------------------- /docs/requirements.txt: -------------------------------------------------------------------------------- 1 | Sphinx==1.8.5 2 | Pygments==2.7.4 3 | sphinx-autobuild 4 | sphinx_rtd_theme==0.2.5b1 5 | docutils==0.16 6 | -------------------------------------------------------------------------------- /fpga/.gitignore: -------------------------------------------------------------------------------- 1 | generated-src 2 | -------------------------------------------------------------------------------- /fpga/scripts/run_impl_bitstream.tcl: -------------------------------------------------------------------------------- 1 | #### Command line arguments to this script 2 | # argv[0] = absolute path to post_synth checkpoint file 3 | # argv[1] = part 4 | # argv[2] = output directory 5 | # argv[3] = common fpga brand tcl 6 | 7 | set synth_checkpoint_file [lindex $argv 0] 8 | set board [lindex $argv 1] 9 | set wrkdir [lindex $argv 2] 10 | 11 | set scriptdir [lindex $argv 3] 12 | 13 | # Set the variable for all the common files 14 | set commondir [file dirname $scriptdir] 15 | 16 | # Set the variable that points to board specific files 17 | set boarddir [file join [file dirname $commondir] $board] 18 | source [file join $boarddir tcl board.tcl] 19 | 20 | # Set the project part to the part passed into this script 21 | set_part $part_fpga 22 | 23 | # Create output directories if they doesn't exist 24 | file mkdir $wrkdir 25 | set rptdir [file join $wrkdir report] 26 | file mkdir $rptdir 27 | 28 | # Load synthesis checkpoint 29 | open_checkpoint $synth_checkpoint_file 30 | 31 | # opt 32 | opt_design 33 | write_checkpoint -force [file join $wrkdir post_opt] 34 | 35 | # place 36 | place_design 37 | phys_opt_design 38 | write_checkpoint -force [file join $wrkdir post_place] 39 | 40 | report_timing_summary -file [file join $rptdir post_place_timing_summary.rpt] 41 | report_drc -file [file join $rptdir post_place_drc.rpt] 42 | 43 | # route 44 | route_design 45 | write_checkpoint -force [file join $wrkdir post_route] 46 | report_timing_summary -file [file join $rptdir post_route_timing_summary.rpt] 47 | report_timing -sort_by group -max_paths 100 -path_type summary -file [file join $rptdir post_route_timing.rpt] 48 | report_clock_utilization -file [file join $rptdir post_route_clock_utilization.rpt] 49 | report_utilization -file [file join $rptdir post_route_utilization.rpt] 50 | report_drc -file [file join $rptdir post_route_drc.rpt] 51 | report_cdc -details -file [file join $rptdir post_route_cdc.rpt] 52 | report_clock_interaction -file [file join $rptdir post_route_clock_interaction.rpt] 53 | report_bus_skew -file [file join $rptdir post_route_bus_skew.rpt] 54 | report_design_analysis -logic_level_distribution -of_timing_paths [get_timing_paths -max_paths 1000 -slack_lesser_than 0] -file [file join $rptdir post_route_timing_violations.rpt] 55 | 56 | # bitstream 57 | write_verilog -force [file join $wrkdir post_route.v] 58 | write_xdc -no_fixed_only -force [file join $wrkdir post_route.xdc] 59 | write_bitstream -force [file join $wrkdir top.bit] 60 | write_debug_probes -force [file join $wrkdir debug_nets.ltx] 61 | -------------------------------------------------------------------------------- /fpga/src/main/resources/vcu118/sdboot/.gitignore: -------------------------------------------------------------------------------- 1 | build 2 | -------------------------------------------------------------------------------- /fpga/src/main/resources/vcu118/sdboot/Makefile: -------------------------------------------------------------------------------- 1 | # RISCV environment variable must be set 2 | ROOT_DIR := $(dir $(abspath $(lastword $(MAKEFILE_LIST)))) 3 | BUILD_DIR := $(ROOT_DIR)/build 4 | 5 | CC=$(RISCV)/bin/riscv64-unknown-elf-gcc 6 | OBJCOPY=$(RISCV)/bin/riscv64-unknown-elf-objcopy 7 | OBJDUMP=$(RISCV)/bin/riscv64-unknown-elf-objdump 8 | CFLAGS=-march=rv64ima -mcmodel=medany -O2 -std=gnu11 -Wall -nostartfiles 9 | CFLAGS+= -fno-common -g -DENTROPY=0 -mabi=lp64 -DNONSMP_HART=0 10 | CFLAGS+= -I $(ROOT_DIR)/include -I. 11 | LFLAGS=-static -nostdlib -L $(ROOT_DIR)/linker -T sdboot.elf.lds 12 | 13 | PBUS_CLK ?= 1000000 # default to 1MHz but really should be overridden 14 | 15 | default: elf bin dump 16 | 17 | elf := $(BUILD_DIR)/sdboot.elf 18 | $(elf): head.S kprintf.c sd.c 19 | mkdir -p $(BUILD_DIR) 20 | $(CC) $(CFLAGS) -DTL_CLK="$(PBUS_CLK)UL" $(LFLAGS) -o $@ head.S sd.c kprintf.c 21 | 22 | .PHONY: elf 23 | elf: $(elf) 24 | 25 | bin := $(BUILD_DIR)/sdboot.bin 26 | $(bin): $(elf) 27 | mkdir -p $(BUILD_DIR) 28 | $(OBJCOPY) -O binary --change-addresses=-0x10000 $< $@ 29 | 30 | .PHONY: bin 31 | bin: $(bin) 32 | 33 | dump := $(BUILD_DIR)/sdboot.dump 34 | $(dump): $(elf) 35 | $(OBJDUMP) -D -S $< > $@ 36 | 37 | .PHONY: dump 38 | dump: $(dump) 39 | 40 | .PHONY: clean 41 | clean:: 42 | rm -rf $(BUILD_DIR) 43 | -------------------------------------------------------------------------------- /fpga/src/main/resources/vcu118/sdboot/common.h: -------------------------------------------------------------------------------- 1 | // See LICENSE.Sifive for license details. 2 | #ifndef _SDBOOT_COMMON_H 3 | #define _SDBOOT_COMMON_H 4 | 5 | #ifndef PAYLOAD_DEST 6 | #define PAYLOAD_DEST MEMORY_MEM_ADDR 7 | #endif 8 | 9 | 10 | #endif 11 | -------------------------------------------------------------------------------- /fpga/src/main/resources/vcu118/sdboot/head.S: -------------------------------------------------------------------------------- 1 | // See LICENSE.Sifive for license details. 2 | #include 3 | #include 4 | #include "common.h" 5 | 6 | .section .text.init 7 | .option norvc 8 | .globl _prog_start 9 | _prog_start: 10 | smp_pause(s1, s2) 11 | li sp, (PAYLOAD_DEST + 0xffff000) 12 | call main 13 | smp_resume(s1, s2) 14 | csrr a0, mhartid // hartid for next level bootloader 15 | la a1, dtb // dtb address for next level bootloader 16 | li s1, PAYLOAD_DEST 17 | jr s1 18 | 19 | .section .dtb 20 | .align 3 21 | dtb: 22 | -------------------------------------------------------------------------------- /fpga/src/main/resources/vcu118/sdboot/include/bits.h: -------------------------------------------------------------------------------- 1 | // See LICENSE.Sifive for license details. 2 | #ifndef _RISCV_BITS_H 3 | #define _RISCV_BITS_H 4 | 5 | #define likely(x) __builtin_expect((x), 1) 6 | #define unlikely(x) __builtin_expect((x), 0) 7 | 8 | #define ROUNDUP(a, b) ((((a)-1)/(b)+1)*(b)) 9 | #define ROUNDDOWN(a, b) ((a)/(b)*(b)) 10 | 11 | #define MAX(a, b) ((a) > (b) ? (a) : (b)) 12 | #define MIN(a, b) ((a) < (b) ? (a) : (b)) 13 | #define CLAMP(a, lo, hi) MIN(MAX(a, lo), hi) 14 | 15 | #define EXTRACT_FIELD(val, which) (((val) & (which)) / ((which) & ~((which)-1))) 16 | #define INSERT_FIELD(val, which, fieldval) (((val) & ~(which)) | ((fieldval) * ((which) & ~((which)-1)))) 17 | 18 | #define STR(x) XSTR(x) 19 | #define XSTR(x) #x 20 | 21 | #if __riscv_xlen == 64 22 | # define SLL32 sllw 23 | # define STORE sd 24 | # define LOAD ld 25 | # define LWU lwu 26 | # define LOG_REGBYTES 3 27 | #else 28 | # define SLL32 sll 29 | # define STORE sw 30 | # define LOAD lw 31 | # define LWU lw 32 | # define LOG_REGBYTES 2 33 | #endif 34 | #define REGBYTES (1 << LOG_REGBYTES) 35 | 36 | #endif 37 | -------------------------------------------------------------------------------- /fpga/src/main/resources/vcu118/sdboot/include/const.h: -------------------------------------------------------------------------------- 1 | // See LICENSE.Sifive for license details. 2 | /* Derived from */ 3 | 4 | #ifndef _SIFIVE_CONST_H 5 | #define _SIFIVE_CONST_H 6 | 7 | #ifdef __ASSEMBLER__ 8 | #define _AC(X,Y) X 9 | #define _AT(T,X) X 10 | #else 11 | #define _AC(X,Y) (X##Y) 12 | #define _AT(T,X) ((T)(X)) 13 | #endif /* !__ASSEMBLER__*/ 14 | 15 | #define _BITUL(x) (_AC(1,UL) << (x)) 16 | #define _BITULL(x) (_AC(1,ULL) << (x)) 17 | 18 | #endif /* _SIFIVE_CONST_H */ 19 | -------------------------------------------------------------------------------- /fpga/src/main/resources/vcu118/sdboot/include/devices/clint.h: -------------------------------------------------------------------------------- 1 | // See LICENSE.Sifive for license details. 2 | 3 | #ifndef _SIFIVE_CLINT_H 4 | #define _SIFIVE_CLINT_H 5 | 6 | 7 | #define CLINT_MSIP 0x0000 8 | #define CLINT_MSIP_size 0x4 9 | #define CLINT_MTIMECMP 0x4000 10 | #define CLINT_MTIMECMP_size 0x8 11 | #define CLINT_MTIME 0xBFF8 12 | #define CLINT_MTIME_size 0x8 13 | 14 | #endif /* _SIFIVE_CLINT_H */ 15 | -------------------------------------------------------------------------------- /fpga/src/main/resources/vcu118/sdboot/include/devices/gpio.h: -------------------------------------------------------------------------------- 1 | // See LICENSE.Sifive for license details. 2 | 3 | #ifndef _SIFIVE_GPIO_H 4 | #define _SIFIVE_GPIO_H 5 | 6 | #define GPIO_INPUT_VAL (0x00) 7 | #define GPIO_INPUT_EN (0x04) 8 | #define GPIO_OUTPUT_EN (0x08) 9 | #define GPIO_OUTPUT_VAL (0x0C) 10 | #define GPIO_PULLUP_EN (0x10) 11 | #define GPIO_DRIVE (0x14) 12 | #define GPIO_RISE_IE (0x18) 13 | #define GPIO_RISE_IP (0x1C) 14 | #define GPIO_FALL_IE (0x20) 15 | #define GPIO_FALL_IP (0x24) 16 | #define GPIO_HIGH_IE (0x28) 17 | #define GPIO_HIGH_IP (0x2C) 18 | #define GPIO_LOW_IE (0x30) 19 | #define GPIO_LOW_IP (0x34) 20 | #define GPIO_IOF_EN (0x38) 21 | #define GPIO_IOF_SEL (0x3C) 22 | #define GPIO_OUTPUT_XOR (0x40) 23 | 24 | #endif /* _SIFIVE_GPIO_H */ 25 | -------------------------------------------------------------------------------- /fpga/src/main/resources/vcu118/sdboot/include/devices/plic.h: -------------------------------------------------------------------------------- 1 | // See LICENSE.Sifive for license details. 2 | 3 | #ifndef PLIC_H 4 | #define PLIC_H 5 | 6 | #include 7 | 8 | // 32 bits per source 9 | #define PLIC_PRIORITY_OFFSET _AC(0x0000,UL) 10 | #define PLIC_PRIORITY_SHIFT_PER_SOURCE 2 11 | // 1 bit per source (1 address) 12 | #define PLIC_PENDING_OFFSET _AC(0x1000,UL) 13 | #define PLIC_PENDING_SHIFT_PER_SOURCE 0 14 | 15 | //0x80 per target 16 | #define PLIC_ENABLE_OFFSET _AC(0x2000,UL) 17 | #define PLIC_ENABLE_SHIFT_PER_TARGET 7 18 | 19 | 20 | #define PLIC_THRESHOLD_OFFSET _AC(0x200000,UL) 21 | #define PLIC_CLAIM_OFFSET _AC(0x200004,UL) 22 | #define PLIC_THRESHOLD_SHIFT_PER_TARGET 12 23 | #define PLIC_CLAIM_SHIFT_PER_TARGET 12 24 | 25 | #define PLIC_MAX_SOURCE 1023 26 | #define PLIC_SOURCE_MASK 0x3FF 27 | 28 | #define PLIC_MAX_TARGET 15871 29 | #define PLIC_TARGET_MASK 0x3FFF 30 | 31 | #endif /* PLIC_H */ 32 | -------------------------------------------------------------------------------- /fpga/src/main/resources/vcu118/sdboot/include/devices/spi.h: -------------------------------------------------------------------------------- 1 | // See LICENSE.Sifive for license details. 2 | 3 | #ifndef _SIFIVE_SPI_H 4 | #define _SIFIVE_SPI_H 5 | 6 | /* Register offsets */ 7 | 8 | #define SPI_REG_SCKDIV 0x00 9 | #define SPI_REG_SCKMODE 0x04 10 | #define SPI_REG_CSID 0x10 11 | #define SPI_REG_CSDEF 0x14 12 | #define SPI_REG_CSMODE 0x18 13 | 14 | #define SPI_REG_DCSSCK 0x28 15 | #define SPI_REG_DSCKCS 0x2a 16 | #define SPI_REG_DINTERCS 0x2c 17 | #define SPI_REG_DINTERXFR 0x2e 18 | 19 | #define SPI_REG_FMT 0x40 20 | #define SPI_REG_TXFIFO 0x48 21 | #define SPI_REG_RXFIFO 0x4c 22 | #define SPI_REG_TXCTRL 0x50 23 | #define SPI_REG_RXCTRL 0x54 24 | 25 | #define SPI_REG_FCTRL 0x60 26 | #define SPI_REG_FFMT 0x64 27 | 28 | #define SPI_REG_IE 0x70 29 | #define SPI_REG_IP 0x74 30 | 31 | /* Fields */ 32 | 33 | #define SPI_SCK_POL 0x1 34 | #define SPI_SCK_PHA 0x2 35 | 36 | #define SPI_FMT_PROTO(x) ((x) & 0x3) 37 | #define SPI_FMT_ENDIAN(x) (((x) & 0x1) << 2) 38 | #define SPI_FMT_DIR(x) (((x) & 0x1) << 3) 39 | #define SPI_FMT_LEN(x) (((x) & 0xf) << 16) 40 | 41 | /* TXCTRL register */ 42 | #define SPI_TXWM(x) ((x) & 0xffff) 43 | /* RXCTRL register */ 44 | #define SPI_RXWM(x) ((x) & 0xffff) 45 | 46 | #define SPI_IP_TXWM 0x1 47 | #define SPI_IP_RXWM 0x2 48 | 49 | #define SPI_FCTRL_EN 0x1 50 | 51 | #define SPI_INSN_CMD_EN 0x1 52 | #define SPI_INSN_ADDR_LEN(x) (((x) & 0x7) << 1) 53 | #define SPI_INSN_PAD_CNT(x) (((x) & 0xf) << 4) 54 | #define SPI_INSN_CMD_PROTO(x) (((x) & 0x3) << 8) 55 | #define SPI_INSN_ADDR_PROTO(x) (((x) & 0x3) << 10) 56 | #define SPI_INSN_DATA_PROTO(x) (((x) & 0x3) << 12) 57 | #define SPI_INSN_CMD_CODE(x) (((x) & 0xff) << 16) 58 | #define SPI_INSN_PAD_CODE(x) (((x) & 0xff) << 24) 59 | 60 | #define SPI_TXFIFO_FULL (1 << 31) 61 | #define SPI_RXFIFO_EMPTY (1 << 31) 62 | 63 | /* Values */ 64 | 65 | #define SPI_CSMODE_AUTO 0 66 | #define SPI_CSMODE_HOLD 2 67 | #define SPI_CSMODE_OFF 3 68 | 69 | #define SPI_DIR_RX 0 70 | #define SPI_DIR_TX 1 71 | 72 | #define SPI_PROTO_S 0 73 | #define SPI_PROTO_D 1 74 | #define SPI_PROTO_Q 2 75 | 76 | #define SPI_ENDIAN_MSB 0 77 | #define SPI_ENDIAN_LSB 1 78 | 79 | #endif /* _SIFIVE_SPI_H */ 80 | -------------------------------------------------------------------------------- /fpga/src/main/resources/vcu118/sdboot/include/devices/uart.h: -------------------------------------------------------------------------------- 1 | // See LICENSE.Sifive for license details. 2 | 3 | #ifndef _SIFIVE_UART_H 4 | #define _SIFIVE_UART_H 5 | 6 | /* Register offsets */ 7 | #define UART_REG_TXFIFO 0x00 8 | #define UART_REG_RXFIFO 0x04 9 | #define UART_REG_TXCTRL 0x08 10 | #define UART_REG_RXCTRL 0x0c 11 | #define UART_REG_IE 0x10 12 | #define UART_REG_IP 0x14 13 | #define UART_REG_DIV 0x18 14 | 15 | /* TXCTRL register */ 16 | #define UART_TXEN 0x1 17 | #define UART_TXNSTOP 0x2 18 | #define UART_TXWM(x) (((x) & 0xffff) << 16) 19 | 20 | /* RXCTRL register */ 21 | #define UART_RXEN 0x1 22 | #define UART_RXWM(x) (((x) & 0xffff) << 16) 23 | 24 | /* IP register */ 25 | #define UART_IP_TXWM 0x1 26 | #define UART_IP_RXWM 0x2 27 | 28 | #endif /* _SIFIVE_UART_H */ 29 | -------------------------------------------------------------------------------- /fpga/src/main/resources/vcu118/sdboot/include/sections.h: -------------------------------------------------------------------------------- 1 | // See LICENSE.Sifive for license details. 2 | #ifndef _SECTIONS_H 3 | #define _SECTIONS_H 4 | 5 | extern unsigned char _rom[]; 6 | extern unsigned char _rom_end[]; 7 | 8 | extern unsigned char _ram[]; 9 | extern unsigned char _ram_end[]; 10 | 11 | extern unsigned char _ftext[]; 12 | extern unsigned char _etext[]; 13 | extern unsigned char _fbss[]; 14 | extern unsigned char _ebss[]; 15 | extern unsigned char _end[]; 16 | 17 | #endif /* _SECTIONS_H */ 18 | -------------------------------------------------------------------------------- /fpga/src/main/resources/vcu118/sdboot/kprintf.c: -------------------------------------------------------------------------------- 1 | // See LICENSE.Sifive for license details. 2 | #include 3 | #include 4 | #include 5 | 6 | #include "kprintf.h" 7 | 8 | static inline void _kputs(const char *s) 9 | { 10 | char c; 11 | for (; (c = *s) != '\0'; s++) 12 | kputc(c); 13 | } 14 | 15 | void kputs(const char *s) 16 | { 17 | _kputs(s); 18 | kputc('\r'); 19 | kputc('\n'); 20 | } 21 | 22 | void kprintf(const char *fmt, ...) 23 | { 24 | va_list vl; 25 | bool is_format, is_long, is_char; 26 | char c; 27 | 28 | va_start(vl, fmt); 29 | is_format = false; 30 | is_long = false; 31 | is_char = false; 32 | while ((c = *fmt++) != '\0') { 33 | if (is_format) { 34 | switch (c) { 35 | case 'l': 36 | is_long = true; 37 | continue; 38 | case 'h': 39 | is_char = true; 40 | continue; 41 | case 'x': { 42 | unsigned long n; 43 | long i; 44 | if (is_long) { 45 | n = va_arg(vl, unsigned long); 46 | i = (sizeof(unsigned long) << 3) - 4; 47 | } else { 48 | n = va_arg(vl, unsigned int); 49 | i = is_char ? 4 : (sizeof(unsigned int) << 3) - 4; 50 | } 51 | for (; i >= 0; i -= 4) { 52 | long d; 53 | d = (n >> i) & 0xF; 54 | kputc(d < 10 ? '0' + d : 'a' + d - 10); 55 | } 56 | break; 57 | } 58 | case 's': 59 | _kputs(va_arg(vl, const char *)); 60 | break; 61 | case 'c': 62 | kputc(va_arg(vl, int)); 63 | break; 64 | } 65 | is_format = false; 66 | is_long = false; 67 | is_char = false; 68 | } else if (c == '%') { 69 | is_format = true; 70 | } else { 71 | kputc(c); 72 | } 73 | } 74 | va_end(vl); 75 | } 76 | -------------------------------------------------------------------------------- /fpga/src/main/resources/vcu118/sdboot/kprintf.h: -------------------------------------------------------------------------------- 1 | // See LICENSE.Sifive for license details. 2 | #ifndef _SDBOOT_KPRINTF_H 3 | #define _SDBOOT_KPRINTF_H 4 | 5 | #include 6 | #include 7 | 8 | #define REG32(p, i) ((p)[(i) >> 2]) 9 | 10 | #ifndef UART_CTRL_ADDR 11 | #ifndef UART_NUM 12 | #define UART_NUM 0 13 | #endif 14 | 15 | #define _CONCAT3(A, B, C) A ## B ## C 16 | #define _UART_CTRL_ADDR(UART_NUM) _CONCAT3(UART, UART_NUM, _CTRL_ADDR) 17 | #define UART_CTRL_ADDR _UART_CTRL_ADDR(UART_NUM) 18 | #endif 19 | static volatile uint32_t * const uart = (void *)(UART_CTRL_ADDR); 20 | 21 | static inline void kputc(char c) 22 | { 23 | volatile uint32_t *tx = ®32(uart, UART_REG_TXFIFO); 24 | #ifdef __riscv_atomic 25 | int32_t r; 26 | do { 27 | __asm__ __volatile__ ( 28 | "amoor.w %0, %2, %1\n" 29 | : "=r" (r), "+A" (*tx) 30 | : "r" (c)); 31 | } while (r < 0); 32 | #else 33 | while ((int32_t)(*tx) < 0); 34 | *tx = c; 35 | #endif 36 | } 37 | 38 | extern void kputs(const char *); 39 | extern void kprintf(const char *, ...); 40 | 41 | #ifdef DEBUG 42 | #define dprintf(s, ...) kprintf((s), ##__VA_ARGS__) 43 | #define dputs(s) kputs((s)) 44 | #else 45 | #define dprintf(s, ...) do { } while (0) 46 | #define dputs(s) do { } while (0) 47 | #endif 48 | 49 | #endif /* _SDBOOT_KPRINTF_H */ 50 | -------------------------------------------------------------------------------- /fpga/src/main/resources/vcu118/sdboot/linker/memory.lds: -------------------------------------------------------------------------------- 1 | MEMORY 2 | { 3 | bootrom_mem (rx) : ORIGIN = 0x10000, LENGTH = 0x2000 4 | memory_mem (rwx) : ORIGIN = 0x80000000, LENGTH = 0x40000000 5 | } 6 | -------------------------------------------------------------------------------- /fpga/src/main/scala/arty/Configs.scala: -------------------------------------------------------------------------------- 1 | // See LICENSE for license details. 2 | package chipyard.fpga.arty 3 | 4 | import freechips.rocketchip.config._ 5 | import freechips.rocketchip.subsystem._ 6 | import freechips.rocketchip.devices.debug._ 7 | import freechips.rocketchip.devices.tilelink._ 8 | import freechips.rocketchip.diplomacy.{DTSModel, DTSTimebase} 9 | import freechips.rocketchip.system._ 10 | import freechips.rocketchip.tile._ 11 | 12 | import sifive.blocks.devices.uart._ 13 | 14 | import testchipip.{SerialTLKey} 15 | 16 | import chipyard.{BuildSystem} 17 | 18 | class WithDefaultPeripherals extends Config((site, here, up) => { 19 | case PeripheryUARTKey => List( 20 | UARTParams(address = 0x10013000)) 21 | case DTSTimebase => BigInt(32768) 22 | case JtagDTMKey => new JtagDTMConfig ( 23 | idcodeVersion = 2, 24 | idcodePartNum = 0x000, 25 | idcodeManufId = 0x489, 26 | debugIdleCycles = 5) 27 | case SerialTLKey => None // remove serialized tl port 28 | }) 29 | // DOC include start: AbstractArty and Rocket 30 | class WithArtyTweaks extends Config( 31 | new WithArtyJTAGHarnessBinder ++ 32 | new WithArtyUARTHarnessBinder ++ 33 | new WithArtyResetHarnessBinder ++ 34 | new WithDebugResetPassthrough ++ 35 | new WithDefaultPeripherals ++ 36 | new freechips.rocketchip.subsystem.WithNBreakpoints(2)) 37 | 38 | class TinyRocketArtyConfig extends Config( 39 | new WithArtyTweaks ++ 40 | new chipyard.TinyRocketConfig) 41 | // DOC include end: AbstractArty and Rocket 42 | -------------------------------------------------------------------------------- /fpga/src/main/scala/arty/HarnessBinders.scala: -------------------------------------------------------------------------------- 1 | package chipyard.fpga.arty 2 | 3 | import chisel3._ 4 | 5 | import freechips.rocketchip.devices.debug._ 6 | import freechips.rocketchip.jtag.{JTAGIO} 7 | import freechips.rocketchip.subsystem._ 8 | 9 | import sifive.blocks.devices.uart._ 10 | import sifive.blocks.devices.jtag._ 11 | import sifive.blocks.devices.pinctrl._ 12 | 13 | import sifive.fpgashells.ip.xilinx.{IBUFG, IOBUF, PULLUP, PowerOnResetFPGAOnly} 14 | 15 | import chipyard.harness.{ComposeHarnessBinder, OverrideHarnessBinder} 16 | import chipyard.iobinders.JTAGChipIO 17 | 18 | class WithArtyResetHarnessBinder extends ComposeHarnessBinder({ 19 | (system: HasPeripheryDebugModuleImp, th: ArtyFPGATestHarness, ports: Seq[Bool]) => { 20 | require(ports.size == 2) 21 | 22 | withClockAndReset(th.clock_32MHz, th.ck_rst) { 23 | // Debug module reset 24 | th.dut_ndreset := ports(0) 25 | 26 | // JTAG reset 27 | ports(1) := PowerOnResetFPGAOnly(th.clock_32MHz) 28 | } 29 | } 30 | }) 31 | 32 | class WithArtyJTAGHarnessBinder extends OverrideHarnessBinder({ 33 | (system: HasPeripheryDebug, th: ArtyFPGATestHarness, ports: Seq[Data]) => { 34 | ports.map { 35 | case j: JTAGChipIO => 36 | withClockAndReset(th.buildtopClock, th.hReset) { 37 | val jtag_wire = Wire(new JTAGIO) 38 | jtag_wire.TDO.data := j.TDO 39 | jtag_wire.TDO.driven := true.B 40 | j.TCK := jtag_wire.TCK 41 | j.TMS := jtag_wire.TMS 42 | j.TDI := jtag_wire.TDI 43 | 44 | val io_jtag = Wire(new JTAGPins(() => new BasePin(), false)).suggestName("jtag") 45 | 46 | JTAGPinsFromPort(io_jtag, jtag_wire) 47 | 48 | io_jtag.TCK.i.ival := IBUFG(IOBUF(th.jd_2).asClock).asBool 49 | 50 | IOBUF(th.jd_5, io_jtag.TMS) 51 | PULLUP(th.jd_5) 52 | 53 | IOBUF(th.jd_4, io_jtag.TDI) 54 | PULLUP(th.jd_4) 55 | 56 | IOBUF(th.jd_0, io_jtag.TDO) 57 | 58 | // mimic putting a pullup on this line (part of reset vote) 59 | th.SRST_n := IOBUF(th.jd_6) 60 | PULLUP(th.jd_6) 61 | 62 | // ignore the po input 63 | io_jtag.TCK.i.po.map(_ := DontCare) 64 | io_jtag.TDI.i.po.map(_ := DontCare) 65 | io_jtag.TMS.i.po.map(_ := DontCare) 66 | io_jtag.TDO.i.po.map(_ := DontCare) 67 | } 68 | } 69 | } 70 | }) 71 | 72 | class WithArtyUARTHarnessBinder extends OverrideHarnessBinder({ 73 | (system: HasPeripheryUARTModuleImp, th: ArtyFPGATestHarness, ports: Seq[UARTPortIO]) => { 74 | withClockAndReset(th.clock_32MHz, th.ck_rst) { 75 | IOBUF(th.uart_rxd_out, ports.head.txd) 76 | ports.head.rxd := IOBUF(th.uart_txd_in) 77 | } 78 | } 79 | }) 80 | -------------------------------------------------------------------------------- /fpga/src/main/scala/arty/IOBinders.scala: -------------------------------------------------------------------------------- 1 | package chipyard.fpga.arty 2 | 3 | import chisel3._ 4 | import chisel3.experimental.{IO} 5 | 6 | import freechips.rocketchip.util._ 7 | import freechips.rocketchip.devices.debug._ 8 | 9 | import chipyard.iobinders.{ComposeIOBinder} 10 | 11 | class WithDebugResetPassthrough extends ComposeIOBinder({ 12 | (system: HasPeripheryDebugModuleImp) => { 13 | // Debug module reset 14 | val io_ndreset: Bool = IO(Output(Bool())).suggestName("ndreset") 15 | io_ndreset := system.debug.get.ndreset 16 | 17 | // JTAG reset 18 | val sjtag = system.debug.get.systemjtag.get 19 | val io_sjtag_reset: Bool = IO(Input(Bool())).suggestName("sjtag_reset") 20 | sjtag.reset := io_sjtag_reset 21 | 22 | (Seq(io_ndreset, io_sjtag_reset), Nil) 23 | } 24 | }) 25 | -------------------------------------------------------------------------------- /fpga/src/main/scala/arty/TestHarness.scala: -------------------------------------------------------------------------------- 1 | package chipyard.fpga.arty 2 | 3 | import chisel3._ 4 | 5 | import freechips.rocketchip.diplomacy.{LazyModule} 6 | import freechips.rocketchip.config.{Parameters} 7 | 8 | import sifive.fpgashells.shell.xilinx.artyshell.{ArtyShell} 9 | 10 | import chipyard.{BuildTop, HasHarnessSignalReferences} 11 | import chipyard.harness.{ApplyHarnessBinders} 12 | import chipyard.iobinders.{HasIOBinders} 13 | 14 | class ArtyFPGATestHarness(override implicit val p: Parameters) extends ArtyShell with HasHarnessSignalReferences { 15 | 16 | val lazyDut = LazyModule(p(BuildTop)(p)).suggestName("chiptop") 17 | 18 | // Convert harness resets from Bool to Reset type. 19 | val hReset = Wire(Reset()) 20 | hReset := ck_rst 21 | 22 | val dReset = Wire(AsyncReset()) 23 | dReset := reset_core.asAsyncReset 24 | 25 | // default to 32MHz clock 26 | withClockAndReset(clock_32MHz, hReset) { 27 | val dut = Module(lazyDut.module) 28 | } 29 | 30 | val buildtopClock = clock_32MHz 31 | val buildtopReset = hReset 32 | val success = false.B 33 | 34 | val dutReset = dReset 35 | 36 | // must be after HasHarnessSignalReferences assignments 37 | lazyDut match { case d: HasIOBinders => 38 | ApplyHarnessBinders(this, d.lazySystem, d.portMap) 39 | } 40 | } 41 | 42 | -------------------------------------------------------------------------------- /fpga/src/main/scala/vcu118/HarnessBinders.scala: -------------------------------------------------------------------------------- 1 | package chipyard.fpga.vcu118 2 | 3 | import chisel3._ 4 | import chisel3.experimental.{BaseModule} 5 | 6 | import freechips.rocketchip.util.{HeterogeneousBag} 7 | import freechips.rocketchip.tilelink.{TLBundle} 8 | 9 | import sifive.blocks.devices.uart.{HasPeripheryUARTModuleImp, UARTPortIO} 10 | import sifive.blocks.devices.spi.{HasPeripherySPI, SPIPortIO} 11 | 12 | import chipyard.{HasHarnessSignalReferences, CanHaveMasterTLMemPort} 13 | import chipyard.harness.{OverrideHarnessBinder} 14 | 15 | /*** UART ***/ 16 | class WithUART extends OverrideHarnessBinder({ 17 | (system: HasPeripheryUARTModuleImp, th: BaseModule with HasHarnessSignalReferences, ports: Seq[UARTPortIO]) => { 18 | th match { case vcu118th: VCU118FPGATestHarnessImp => { 19 | vcu118th.vcu118Outer.io_uart_bb.bundle <> ports.head 20 | } } 21 | } 22 | }) 23 | 24 | /*** SPI ***/ 25 | class WithSPISDCard extends OverrideHarnessBinder({ 26 | (system: HasPeripherySPI, th: BaseModule with HasHarnessSignalReferences, ports: Seq[SPIPortIO]) => { 27 | th match { case vcu118th: VCU118FPGATestHarnessImp => { 28 | vcu118th.vcu118Outer.io_spi_bb.bundle <> ports.head 29 | } } 30 | } 31 | }) 32 | 33 | /*** Experimental DDR ***/ 34 | class WithDDRMem extends OverrideHarnessBinder({ 35 | (system: CanHaveMasterTLMemPort, th: BaseModule with HasHarnessSignalReferences, ports: Seq[HeterogeneousBag[TLBundle]]) => { 36 | th match { case vcu118th: VCU118FPGATestHarnessImp => { 37 | require(ports.size == 1) 38 | 39 | val bundles = vcu118th.vcu118Outer.ddrClient.out.map(_._1) 40 | val ddrClientBundle = Wire(new HeterogeneousBag(bundles.map(_.cloneType))) 41 | bundles.zip(ddrClientBundle).foreach { case (bundle, io) => bundle <> io } 42 | ddrClientBundle <> ports.head 43 | } } 44 | } 45 | }) 46 | -------------------------------------------------------------------------------- /fpga/src/main/scala/vcu118/IOBinders.scala: -------------------------------------------------------------------------------- 1 | package chipyard.fpga.vcu118 2 | 3 | import chisel3._ 4 | import chisel3.experimental.{IO, DataMirror} 5 | 6 | import freechips.rocketchip.diplomacy.{ResourceBinding, Resource, ResourceAddress, InModuleBody} 7 | import freechips.rocketchip.subsystem.{BaseSubsystem} 8 | import freechips.rocketchip.util.{HeterogeneousBag} 9 | import freechips.rocketchip.tilelink.{TLBundle} 10 | 11 | import sifive.blocks.devices.uart.{HasPeripheryUARTModuleImp} 12 | import sifive.blocks.devices.spi.{HasPeripherySPI, HasPeripherySPIModuleImp, MMCDevice} 13 | 14 | import chipyard.{CanHaveMasterTLMemPort} 15 | import chipyard.iobinders.{OverrideIOBinder, OverrideLazyIOBinder} 16 | 17 | class WithUARTIOPassthrough extends OverrideIOBinder({ 18 | (system: HasPeripheryUARTModuleImp) => { 19 | val io_uart_pins_temp = system.uart.zipWithIndex.map { case (dio, i) => IO(dio.cloneType).suggestName(s"uart_$i") } 20 | (io_uart_pins_temp zip system.uart).map { case (io, sysio) => 21 | io <> sysio 22 | } 23 | (io_uart_pins_temp, Nil) 24 | } 25 | }) 26 | 27 | class WithSPIIOPassthrough extends OverrideLazyIOBinder({ 28 | (system: HasPeripherySPI) => { 29 | // attach resource to 1st SPI 30 | ResourceBinding { 31 | Resource(new MMCDevice(system.tlSpiNodes.head.device, 1), "reg").bind(ResourceAddress(0)) 32 | } 33 | 34 | InModuleBody { 35 | system.asInstanceOf[BaseSubsystem].module match { case system: HasPeripherySPIModuleImp => { 36 | val io_spi_pins_temp = system.spi.zipWithIndex.map { case (dio, i) => IO(dio.cloneType).suggestName(s"spi_$i") } 37 | (io_spi_pins_temp zip system.spi).map { case (io, sysio) => 38 | io <> sysio 39 | } 40 | (io_spi_pins_temp, Nil) 41 | } } 42 | } 43 | } 44 | }) 45 | 46 | class WithTLIOPassthrough extends OverrideIOBinder({ 47 | (system: CanHaveMasterTLMemPort) => { 48 | val io_tl_mem_pins_temp = IO(DataMirror.internal.chiselTypeClone[HeterogeneousBag[TLBundle]](system.mem_tl)).suggestName("tl_slave") 49 | io_tl_mem_pins_temp <> system.mem_tl 50 | (Seq(io_tl_mem_pins_temp), Nil) 51 | } 52 | }) 53 | -------------------------------------------------------------------------------- /fpga/src/main/scala/vcu118/bringup/BringupGPIOs.scala: -------------------------------------------------------------------------------- 1 | package chipyard.fpga.vcu118.bringup 2 | 3 | import scala.collection.mutable.{LinkedHashMap} 4 | 5 | object BringupGPIOs { 6 | // map of the pin name (akin to die pin name) to (fpga package pin, IOSTANDARD, add pullup resistor?) 7 | val pinMapping = LinkedHashMap( 8 | // these connect to LEDs and switches on the VCU118 (and use 1.2V) 9 | "led0" -> ("AT32", "LVCMOS12", false), // 0 10 | "led1" -> ("AV34", "LVCMOS12", false), // 1 11 | "led2" -> ("AY30", "LVCMOS12", false), // 2 12 | "led3" -> ("BB32", "LVCMOS12", false), // 3 13 | "led4" -> ("BF32", "LVCMOS12", false), // 4 14 | "led5" -> ("AU37", "LVCMOS12", false), // 5 15 | "led6" -> ("AV36", "LVCMOS12", false), // 6 16 | "led7" -> ("BA37", "LVCMOS12", false), // 7 17 | "sw0" -> ("B17", "LVCMOS12", false), // 8 18 | "sw1" -> ("G16", "LVCMOS12", false), // 9 19 | "sw2" -> ("J16", "LVCMOS12", false), // 10 20 | "sw3" -> ("D21", "LVCMOS12", false) // 11 21 | ) 22 | 23 | // return list of names (ordered) 24 | def names: Seq[String] = pinMapping.keys.toSeq 25 | 26 | // return number of GPIOs 27 | def width: Int = pinMapping.size 28 | } 29 | -------------------------------------------------------------------------------- /fpga/src/main/scala/vcu118/bringup/DigitalTop.scala: -------------------------------------------------------------------------------- 1 | package chipyard.fpga.vcu118.bringup 2 | 3 | import chisel3._ 4 | 5 | import freechips.rocketchip.subsystem._ 6 | import freechips.rocketchip.system._ 7 | import freechips.rocketchip.config.Parameters 8 | import freechips.rocketchip.devices.tilelink._ 9 | import freechips.rocketchip.diplomacy._ 10 | import freechips.rocketchip.tilelink._ 11 | 12 | import chipyard.{DigitalTop, DigitalTopModule} 13 | 14 | // ------------------------------------ 15 | // Bringup VCU118 DigitalTop 16 | // ------------------------------------ 17 | 18 | class BringupVCU118DigitalTop(implicit p: Parameters) extends DigitalTop 19 | with sifive.blocks.devices.i2c.HasPeripheryI2C 20 | with testchipip.HasPeripheryTSIHostWidget 21 | { 22 | override lazy val module = new BringupVCU118DigitalTopModule(this) 23 | } 24 | 25 | class BringupVCU118DigitalTopModule[+L <: BringupVCU118DigitalTop](l: L) extends DigitalTopModule(l) 26 | with sifive.blocks.devices.i2c.HasPeripheryI2CModuleImp 27 | -------------------------------------------------------------------------------- /fpga/src/main/scala/vcu118/bringup/HarnessBinders.scala: -------------------------------------------------------------------------------- 1 | package chipyard.fpga.vcu118.bringup 2 | 3 | import chisel3._ 4 | import chisel3.experimental.{Analog, IO, BaseModule} 5 | 6 | import freechips.rocketchip.util.{HeterogeneousBag} 7 | import freechips.rocketchip.tilelink.{TLBundle} 8 | 9 | import sifive.blocks.devices.uart.{HasPeripheryUARTModuleImp, UARTPortIO} 10 | import sifive.blocks.devices.spi.{HasPeripherySPI, SPIPortIO} 11 | import sifive.blocks.devices.i2c.{HasPeripheryI2CModuleImp, I2CPort} 12 | import sifive.blocks.devices.gpio.{HasPeripheryGPIOModuleImp, GPIOPortIO} 13 | 14 | import testchipip.{HasPeripheryTSIHostWidget, TSIHostWidgetIO} 15 | 16 | import chipyard.{HasHarnessSignalReferences} 17 | import chipyard.harness.{ComposeHarnessBinder, OverrideHarnessBinder} 18 | 19 | /*** UART ***/ 20 | class WithBringupUART extends ComposeHarnessBinder({ 21 | (system: HasPeripheryUARTModuleImp, th: BaseModule with HasHarnessSignalReferences, ports: Seq[UARTPortIO]) => { 22 | th match { case vcu118th: BringupVCU118FPGATestHarnessImp => { 23 | require(ports.size == 2) 24 | 25 | vcu118th.bringupOuter.io_fmc_uart_bb.bundle <> ports.last 26 | } } 27 | } 28 | }) 29 | 30 | /*** I2C ***/ 31 | class WithBringupI2C extends OverrideHarnessBinder({ 32 | (system: HasPeripheryI2CModuleImp, th: BaseModule with HasHarnessSignalReferences, ports: Seq[I2CPort]) => { 33 | th match { case vcu118th: BringupVCU118FPGATestHarnessImp => { 34 | require(ports.size == 1) 35 | 36 | vcu118th.bringupOuter.io_i2c_bb.bundle <> ports.head 37 | } } 38 | } 39 | }) 40 | 41 | /*** GPIO ***/ 42 | class WithBringupGPIO extends OverrideHarnessBinder({ 43 | (system: HasPeripheryGPIOModuleImp, th: BaseModule with HasHarnessSignalReferences, ports: Seq[GPIOPortIO]) => { 44 | th match { case vcu118th: BringupVCU118FPGATestHarnessImp => { 45 | (vcu118th.bringupOuter.io_gpio_bb zip ports).map { case (bb_io, dut_io) => 46 | bb_io.bundle <> dut_io 47 | } 48 | } } 49 | } 50 | }) 51 | 52 | /*** TSI Host Widget ***/ 53 | class WithBringupTSIHost extends OverrideHarnessBinder({ 54 | (system: HasPeripheryTSIHostWidget, th: BaseModule with HasHarnessSignalReferences, ports: Seq[Data]) => { 55 | th match { case vcu118th: BringupVCU118FPGATestHarnessImp => { 56 | require(ports.size == 2) // 1st goes to the TL mem, 2nd goes to the serial link 57 | 58 | ports.head match { case tlPort: HeterogeneousBag[TLBundle] => 59 | val tsiBundles = vcu118th.bringupOuter.tsiDdrClient.out.map(_._1) 60 | val tsiDdrClientBundle = Wire(new HeterogeneousBag(tsiBundles.map(_.cloneType))) 61 | tsiBundles.zip(tsiDdrClientBundle).foreach { case (bundle, io) => bundle <> io } 62 | tsiDdrClientBundle <> tlPort 63 | } 64 | 65 | ports.last match { case serialPort: TSIHostWidgetIO => 66 | vcu118th.bringupOuter.io_tsi_serial_bb.bundle <> serialPort 67 | } 68 | } } 69 | } 70 | }) 71 | -------------------------------------------------------------------------------- /fpga/src/main/scala/vcu118/bringup/IOBinders.scala: -------------------------------------------------------------------------------- 1 | package chipyard.fpga.vcu118.bringup 2 | 3 | import chisel3._ 4 | import chisel3.experimental.{IO, DataMirror} 5 | 6 | import freechips.rocketchip.util.{HeterogeneousBag} 7 | import freechips.rocketchip.tilelink.{TLBundle} 8 | 9 | import sifive.blocks.devices.gpio.{HasPeripheryGPIOModuleImp} 10 | import sifive.blocks.devices.i2c.{HasPeripheryI2CModuleImp} 11 | 12 | import testchipip.{HasPeripheryTSIHostWidget, TSIHostWidgetIO} 13 | 14 | import chipyard.iobinders.{OverrideIOBinder} 15 | 16 | class WithGPIOIOPassthrough extends OverrideIOBinder({ 17 | (system: HasPeripheryGPIOModuleImp) => { 18 | val io_gpio_pins_temp = system.gpio.zipWithIndex.map { case (dio, i) => IO(dio.cloneType).suggestName(s"gpio_$i") } 19 | (io_gpio_pins_temp zip system.gpio).map { case (io, sysio) => 20 | io <> sysio 21 | } 22 | (io_gpio_pins_temp, Nil) 23 | } 24 | }) 25 | 26 | class WithI2CIOPassthrough extends OverrideIOBinder({ 27 | (system: HasPeripheryI2CModuleImp) => { 28 | val io_i2c_pins_temp = system.i2c.zipWithIndex.map { case (dio, i) => IO(dio.cloneType).suggestName(s"i2c_$i") } 29 | (io_i2c_pins_temp zip system.i2c).map { case (io, sysio) => 30 | io <> sysio 31 | } 32 | (io_i2c_pins_temp, Nil) 33 | } 34 | }) 35 | 36 | class WithTSITLIOPassthrough extends OverrideIOBinder({ 37 | (system: HasPeripheryTSIHostWidget) => { 38 | require(system.tsiTLMem.size == 1) 39 | val io_tsi_tl_mem_pins_temp = IO(DataMirror.internal.chiselTypeClone[HeterogeneousBag[TLBundle]](system.tsiTLMem.head)).suggestName("tsi_tl_slave") 40 | io_tsi_tl_mem_pins_temp <> system.tsiTLMem.head 41 | 42 | require(system.tsiSerial.size == 1) 43 | val io_tsi_serial_pins_temp = IO(DataMirror.internal.chiselTypeClone[TSIHostWidgetIO](system.tsiSerial.head)).suggestName("tsi_serial") 44 | io_tsi_serial_pins_temp <> system.tsiSerial.head 45 | (Seq(io_tsi_tl_mem_pins_temp, io_tsi_serial_pins_temp), Nil) 46 | } 47 | }) 48 | -------------------------------------------------------------------------------- /generators/chipyard/src/main/resources/vsrc/ClockDividerN.sv: -------------------------------------------------------------------------------- 1 | // See LICENSE for license details. 2 | 3 | /** 4 | * An unsynthesizable divide-by-N clock divider. 5 | * Duty cycle is 100 * (ceil(DIV / 2)) / DIV. 6 | */ 7 | 8 | module ClockDividerN #(parameter DIV = 1)(output logic clk_out = 1'b0, input clk_in); 9 | 10 | localparam CWIDTH = $clog2(DIV); 11 | localparam LOW_CYCLES = DIV / 2; 12 | localparam HIGH_TRANSITION = LOW_CYCLES - 1; 13 | localparam LOW_TRANSITION = DIV - 1; 14 | 15 | generate 16 | if (DIV == 1) begin 17 | // This needs to be procedural because of the assignment on declaration 18 | always @(clk_in) begin 19 | clk_out = clk_in; 20 | end 21 | end else begin 22 | reg [CWIDTH - 1: 0] count = HIGH_TRANSITION[CWIDTH-1:0]; 23 | // The blocking assignment to clock out is used to conform what was done 24 | // in RC's clock dividers. 25 | // It should have the effect of preventing registers in the divided clock 26 | // domain latching register updates launched by the fast clock-domain edge 27 | // that occurs at the same simulated time (as the divided clock edge). 28 | always @(posedge clk_in) begin 29 | if (count == LOW_TRANSITION[CWIDTH-1:0]) begin 30 | clk_out = 1'b0; 31 | count <= '0; 32 | end 33 | else begin 34 | if (count == HIGH_TRANSITION[CWIDTH-1:0]) begin 35 | clk_out = 1'b1; 36 | end 37 | count <= count + 1'b1; 38 | end 39 | end 40 | end 41 | endgenerate 42 | endmodule // ClockDividerN 43 | -------------------------------------------------------------------------------- /generators/chipyard/src/main/resources/vsrc/GCDMMIOBlackBox.v: -------------------------------------------------------------------------------- 1 | // DOC include start: GCD portlist 2 | module GCDMMIOBlackBox 3 | #(parameter WIDTH) 4 | ( 5 | input clock, 6 | input reset, 7 | output input_ready, 8 | input input_valid, 9 | input [WIDTH-1:0] x, 10 | input [WIDTH-1:0] y, 11 | input output_ready, 12 | output output_valid, 13 | output reg [WIDTH-1:0] gcd, 14 | output busy 15 | ); 16 | // DOC include end: GCD portlist 17 | 18 | localparam S_IDLE = 2'b00, S_RUN = 2'b01, S_DONE = 2'b10; 19 | 20 | reg [1:0] state; 21 | reg [WIDTH-1:0] tmp; 22 | 23 | assign input_ready = state == S_IDLE; 24 | assign output_valid = state == S_DONE; 25 | assign busy = state != S_IDLE; 26 | 27 | always @(posedge clock) begin 28 | if (reset) 29 | state <= S_IDLE; 30 | else if (state == S_IDLE && input_valid) 31 | state <= S_RUN; 32 | else if (state == S_RUN && tmp == 0) 33 | state <= S_DONE; 34 | else if (state == S_DONE && output_ready) 35 | state <= S_IDLE; 36 | end 37 | 38 | always @(posedge clock) begin 39 | if (state == S_IDLE && input_valid) begin 40 | gcd <= x; 41 | tmp <= y; 42 | end else if (state == S_RUN) begin 43 | if (gcd > tmp) 44 | gcd <= gcd - tmp; 45 | else 46 | tmp <= tmp - gcd; 47 | end 48 | end 49 | 50 | endmodule // GCDMMIOBlackBox 51 | -------------------------------------------------------------------------------- /generators/chipyard/src/main/scala/ChipTop.scala: -------------------------------------------------------------------------------- 1 | package chipyard 2 | 3 | import chisel3._ 4 | 5 | import scala.collection.mutable.{ArrayBuffer} 6 | 7 | import freechips.rocketchip.prci.{ClockGroupIdentityNode, ClockSinkParameters, ClockSinkNode, ClockGroup} 8 | import freechips.rocketchip.subsystem.{BaseSubsystem, SubsystemDriveAsyncClockGroupsKey} 9 | import freechips.rocketchip.config.{Parameters, Field} 10 | import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp, LazyRawModuleImp, LazyModuleImpLike, BindingScope} 11 | import freechips.rocketchip.util.{ResetCatchAndSync} 12 | import chipyard.iobinders._ 13 | 14 | import barstools.iocell.chisel._ 15 | 16 | case object BuildSystem extends Field[Parameters => LazyModule]((p: Parameters) => new DigitalTop()(p)) 17 | 18 | /** 19 | * The base class used for building chips. This constructor instantiates a module specified by the BuildSystem parameter, 20 | * named "system", which is an instance of DigitalTop by default. The diplomatic clocks of System, as well as its implicit clock, 21 | * is aggregated into the clockGroupNode. The parameterized functions controlled by ClockingSchemeKey and GlobalResetSchemeKey 22 | * drive clock and reset generation 23 | */ 24 | 25 | class ChipTop(implicit p: Parameters) extends LazyModule with BindingScope 26 | with HasIOBinders { 27 | // The system module specified by BuildSystem 28 | lazy val lazySystem = LazyModule(p(BuildSystem)(p)).suggestName("system") 29 | 30 | // NOTE: Making this a LazyRawModule is moderately dangerous, as anonymous children 31 | // of ChipTop (ex: ClockGroup) do not receive clock or reset. 32 | // However. anonymous children of ChipTop should not need an implicit Clock or Reset 33 | // anyways, they probably need to be explicitly clocked. 34 | lazy val module: LazyModuleImpLike = new LazyRawModuleImp(this) { } 35 | } 36 | 37 | -------------------------------------------------------------------------------- /generators/chipyard/src/main/scala/Generator.scala: -------------------------------------------------------------------------------- 1 | package chipyard 2 | 3 | import firrtl.options.{StageMain} 4 | import chipyard.stage.ChipyardStage 5 | 6 | object Generator extends StageMain(new ChipyardStage) 7 | -------------------------------------------------------------------------------- /generators/chipyard/src/main/scala/clocking/ClockDividerN.scala: -------------------------------------------------------------------------------- 1 | // See LICENSE for license details. 2 | 3 | package chipyard.clocking 4 | 5 | import chisel3._ 6 | import chisel3.util._ 7 | 8 | class ClockDividerN(div: Int) extends BlackBox(Map("DIV" -> div)) with HasBlackBoxResource { 9 | require(div > 0); 10 | val io = IO(new Bundle { 11 | val clk_out = Output(Clock()) 12 | val clk_in = Input(Clock()) 13 | }) 14 | addResource("/vsrc/ClockDividerN.sv") 15 | } 16 | 17 | object ClockDivideByN { 18 | def apply(clockIn: Clock, div: Int): Clock = { 19 | val clockDivider = Module(new ClockDividerN(div)) 20 | clockDivider.io.clk_in := clockIn 21 | clockDivider.io.clk_out 22 | } 23 | } 24 | -------------------------------------------------------------------------------- /generators/chipyard/src/main/scala/clocking/TileClockGater.scala: -------------------------------------------------------------------------------- 1 | package chipyard.clocking 2 | 3 | import chisel3._ 4 | import chisel3.util._ 5 | import chisel3.experimental.{Analog, IO} 6 | 7 | import freechips.rocketchip.config._ 8 | import freechips.rocketchip.subsystem._ 9 | import freechips.rocketchip.diplomacy._ 10 | import freechips.rocketchip.prci._ 11 | import freechips.rocketchip.util._ 12 | import freechips.rocketchip.tilelink._ 13 | import freechips.rocketchip.devices.tilelink._ 14 | import freechips.rocketchip.regmapper._ 15 | import freechips.rocketchip.subsystem._ 16 | 17 | /** This node adds clock gating control registers. 18 | * If deploying on a platform which does not support clock gating, deasserting the enable 19 | * flag will generate the registers, preserving the same memory map and behavior, but will not 20 | * generate any gaters 21 | */ 22 | class TileClockGater(address: BigInt, beatBytes: Int, enable: Boolean)(implicit p: Parameters, valName: ValName) extends LazyModule 23 | { 24 | val device = new SimpleDevice(s"clock-gater", Nil) 25 | val clockNode = ClockGroupIdentityNode() 26 | val tlNode = TLRegisterNode(Seq(AddressSet(address, 4096-1)), device, "reg/control", beatBytes=beatBytes) 27 | lazy val module = new LazyModuleImp(this) { 28 | val sources = clockNode.in.head._1.member.data.toSeq 29 | val sinks = clockNode.out.head._1.member.elements.toSeq 30 | val nSinks = sinks.size 31 | val regs = (0 until nSinks).map({i => 32 | val sinkName = sinks(i)._1 33 | val reg = withReset(sources(i).reset) { Module(new AsyncResetRegVec(w=1, init=1)) } 34 | if (sinkName.contains("tile") && enable) { 35 | println(s"ClockGate for ${sinkName} regmapped at ${(address+i*4).toString(16)}") 36 | sinks(i)._2.clock := ClockGate(sources(i).clock, reg.io.q.asBool) 37 | sinks(i)._2.reset := sources(i).reset 38 | } else { 39 | sinks(i)._2 := sources(i) 40 | } 41 | reg 42 | }) 43 | tlNode.regmap((0 until nSinks).map({i => 44 | i*4 -> Seq(RegField.rwReg(1, regs(i).io)) 45 | }): _*) 46 | } 47 | } 48 | 49 | object TileClockGater { 50 | def apply(address: BigInt, tlbus: TLBusWrapper, enable: Boolean)(implicit p: Parameters, v: ValName) = { 51 | val gater = LazyModule(new TileClockGater(address, tlbus.beatBytes, enable)) 52 | tlbus.toVariableWidthSlave(Some("clock-gater")) { gater.tlNode := TLBuffer() } 53 | gater.clockNode 54 | } 55 | } 56 | -------------------------------------------------------------------------------- /generators/chipyard/src/main/scala/config/BoomConfigs.scala: -------------------------------------------------------------------------------- 1 | package chipyard 2 | 3 | import freechips.rocketchip.config.{Config} 4 | 5 | // --------------------- 6 | // BOOM Configs 7 | // --------------------- 8 | 9 | class SmallBoomConfig extends Config( 10 | new boom.common.WithNSmallBooms(1) ++ // small boom config 11 | new chipyard.config.AbstractConfig) 12 | 13 | class MediumBoomConfig extends Config( 14 | new boom.common.WithNMediumBooms(1) ++ // medium boom config 15 | new chipyard.config.AbstractConfig) 16 | 17 | class LargeBoomConfig extends Config( 18 | new boom.common.WithNLargeBooms(1) ++ // large boom config 19 | new chipyard.config.AbstractConfig) 20 | 21 | class MegaBoomConfig extends Config( 22 | new boom.common.WithNMegaBooms(1) ++ // mega boom config 23 | new chipyard.config.AbstractConfig) 24 | 25 | class DualSmallBoomConfig extends Config( 26 | new boom.common.WithNSmallBooms(2) ++ // 2 boom cores 27 | new chipyard.config.AbstractConfig) 28 | 29 | class HwachaLargeBoomConfig extends Config( 30 | new chipyard.config.WithHwachaTest ++ 31 | new hwacha.DefaultHwachaConfig ++ // use Hwacha vector accelerator 32 | new boom.common.WithNLargeBooms(1) ++ 33 | new chipyard.config.AbstractConfig) 34 | 35 | class LoopbackNICLargeBoomConfig extends Config( 36 | new chipyard.harness.WithLoopbackNIC ++ // drive NIC IOs with loopback 37 | new icenet.WithIceNIC ++ // build a NIC 38 | new boom.common.WithNLargeBooms(1) ++ 39 | new chipyard.config.AbstractConfig) 40 | 41 | class DromajoBoomConfig extends Config( 42 | new chipyard.harness.WithSimDromajoBridge ++ // attach Dromajo 43 | new chipyard.config.WithTraceIO ++ // enable the traceio 44 | new boom.common.WithNSmallBooms(1) ++ 45 | new chipyard.config.AbstractConfig) 46 | -------------------------------------------------------------------------------- /generators/chipyard/src/main/scala/config/CVA6Configs.scala: -------------------------------------------------------------------------------- 1 | package chipyard 2 | 3 | import chisel3._ 4 | 5 | import freechips.rocketchip.config.{Config} 6 | 7 | // --------------------- 8 | // CVA6 Configs 9 | // --------------------- 10 | 11 | class CVA6Config extends Config( 12 | new cva6.WithNCVA6Cores(1) ++ // single CVA6 core 13 | new chipyard.config.AbstractConfig) 14 | 15 | class dmiCVA6Config extends Config( 16 | new chipyard.harness.WithSerialAdapterTiedOff ++ // Tie off the serial port, override default instantiation of SimSerial 17 | new chipyard.config.WithDMIDTM ++ // have debug module expose a clocked DMI port 18 | new cva6.WithNCVA6Cores(1) ++ // single CVA6 core 19 | new chipyard.config.AbstractConfig) 20 | -------------------------------------------------------------------------------- /generators/chipyard/src/main/scala/config/IbexConfigs.scala: -------------------------------------------------------------------------------- 1 | package chipyard 2 | 3 | import chisel3._ 4 | 5 | import freechips.rocketchip.config.{Config} 6 | 7 | // --------------------- 8 | // Ibex Configs 9 | // --------------------- 10 | 11 | // Multi-core and 32b heterogeneous configs are supported 12 | 13 | class IbexConfig extends Config( 14 | new ibex.WithNIbexCores(1) ++ 15 | new chipyard.config.AbstractConfig) -------------------------------------------------------------------------------- /generators/chipyard/src/main/scala/config/TracegenConfigs.scala: -------------------------------------------------------------------------------- 1 | package chipyard 2 | 3 | import freechips.rocketchip.config.{Config} 4 | import freechips.rocketchip.rocket.{DCacheParams} 5 | 6 | class AbstractTraceGenConfig extends Config( 7 | new chipyard.harness.WithBlackBoxSimMem ++ 8 | new chipyard.harness.WithTraceGenSuccess ++ 9 | new chipyard.harness.WithClockAndResetFromHarness ++ 10 | new chipyard.iobinders.WithAXI4MemPunchthrough ++ 11 | new chipyard.iobinders.WithTraceGenSuccessPunchthrough ++ 12 | new chipyard.iobinders.WithDividerOnlyClockGenerator ++ 13 | new chipyard.config.WithTracegenSystem ++ 14 | new chipyard.config.WithNoSubsystemDrivenClocks ++ 15 | new chipyard.config.WithPeripheryBusFrequencyAsDefault ++ 16 | new chipyard.config.WithMemoryBusFrequency(100.0) ++ 17 | new chipyard.config.WithPeripheryBusFrequency(100.0) ++ 18 | new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ 19 | new freechips.rocketchip.groundtest.GroundTestBaseConfig) 20 | 21 | 22 | class TraceGenConfig extends Config( 23 | new tracegen.WithTraceGen()(List.fill(2) { DCacheParams(nMSHRs = 0, nSets = 16, nWays = 2) }) ++ 24 | new AbstractTraceGenConfig) 25 | 26 | class NonBlockingTraceGenConfig extends Config( 27 | new tracegen.WithTraceGen()(List.fill(2) { DCacheParams(nMSHRs = 2, nSets = 16, nWays = 2) }) ++ 28 | new AbstractTraceGenConfig) 29 | 30 | class BoomTraceGenConfig extends Config( 31 | new tracegen.WithBoomTraceGen()(List.fill(2) { DCacheParams(nMSHRs = 8, nSets = 16, nWays = 2) }) ++ 32 | new freechips.rocketchip.subsystem.WithInclusiveCache ++ 33 | new AbstractTraceGenConfig) 34 | 35 | class NonBlockingTraceGenL2Config extends Config( 36 | new tracegen.WithL2TraceGen()(List.fill(2)(DCacheParams(nMSHRs = 2, nSets = 16, nWays = 4))) ++ 37 | new freechips.rocketchip.subsystem.WithInclusiveCache ++ 38 | new AbstractTraceGenConfig) 39 | 40 | class NonBlockingTraceGenL2RingConfig extends Config( 41 | new tracegen.WithL2TraceGen()(List.fill(2)(DCacheParams(nMSHRs = 2, nSets = 16, nWays = 4))) ++ 42 | new testchipip.WithRingSystemBus ++ 43 | new freechips.rocketchip.subsystem.WithInclusiveCache ++ 44 | new AbstractTraceGenConfig) 45 | -------------------------------------------------------------------------------- /generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala: -------------------------------------------------------------------------------- 1 | package chipyard.config 2 | 3 | import scala.util.matching.Regex 4 | import chisel3._ 5 | import chisel3.util.{log2Up} 6 | 7 | import freechips.rocketchip.config.{Config} 8 | import freechips.rocketchip.devices.tilelink.{BootROMLocated} 9 | import freechips.rocketchip.devices.debug.{Debug, ExportDebug, DebugModuleKey, DMI} 10 | import freechips.rocketchip.stage.phases.TargetDirKey 11 | import freechips.rocketchip.subsystem._ 12 | import freechips.rocketchip.tile.{XLen} 13 | 14 | import sifive.blocks.devices.gpio._ 15 | import sifive.blocks.devices.uart._ 16 | import sifive.blocks.devices.spi._ 17 | 18 | import testchipip._ 19 | 20 | import chipyard.{ExtTLMem} 21 | 22 | // Set the bootrom to the Chipyard bootrom 23 | class WithBootROM extends Config((site, here, up) => { 24 | case BootROMLocated(x) => up(BootROMLocated(x), site) 25 | .map(_.copy(contentFileName = s"${site(TargetDirKey)}/bootrom.rv${site(XLen)}.img")) 26 | }) 27 | 28 | // DOC include start: gpio config fragment 29 | class WithGPIO extends Config((site, here, up) => { 30 | case PeripheryGPIOKey => Seq( 31 | GPIOParams(address = 0x10012000, width = 4, includeIOF = false)) 32 | }) 33 | // DOC include end: gpio config fragment 34 | 35 | class WithUART(baudrate: BigInt = 115200) extends Config((site, here, up) => { 36 | case PeripheryUARTKey => Seq( 37 | UARTParams(address = 0x54000000L, nTxEntries = 256, nRxEntries = 256, initBaudRate = baudrate)) 38 | }) 39 | 40 | class WithSPIFlash(size: BigInt = 0x10000000) extends Config((site, here, up) => { 41 | // Note: the default size matches freedom with the addresses below 42 | case PeripherySPIFlashKey => Seq( 43 | SPIFlashParams(rAddress = 0x10040000, fAddress = 0x20000000, fSize = size)) 44 | }) 45 | 46 | class WithDMIDTM extends Config((site, here, up) => { 47 | case ExportDebug => up(ExportDebug, site).copy(protocols = Set(DMI)) 48 | }) 49 | 50 | class WithNoDebug extends Config((site, here, up) => { 51 | case DebugModuleKey => None 52 | }) 53 | 54 | class WithTLSerialLocation(masterWhere: TLBusWrapperLocation, slaveWhere: TLBusWrapperLocation) extends Config((site, here, up) => { 55 | case SerialTLAttachKey => up(SerialTLAttachKey, site).copy(masterWhere = masterWhere, slaveWhere = slaveWhere) 56 | }) 57 | 58 | class WithTLBackingMemory extends Config((site, here, up) => { 59 | case ExtMem => None // disable AXI backing memory 60 | case ExtTLMem => up(ExtMem, site) // enable TL backing memory 61 | }) 62 | 63 | class WithSerialTLBackingMemory extends Config((site, here, up) => { 64 | case ExtMem => None 65 | case SerialTLKey => up(SerialTLKey, site).map { k => k.copy( 66 | memParams = { 67 | val memPortParams = up(ExtMem, site).get 68 | require(memPortParams.nMemoryChannels == 1) 69 | memPortParams.master 70 | }, 71 | isMemoryDevice = true 72 | )} 73 | }) 74 | 75 | -------------------------------------------------------------------------------- /generators/chipyard/src/main/scala/config/fragments/SubsystemFragments.scala: -------------------------------------------------------------------------------- 1 | package chipyard.config 2 | 3 | import freechips.rocketchip.config.{Config} 4 | import freechips.rocketchip.subsystem.{SystemBusKey, BankedL2Key, CoherenceManagerWrapper} 5 | 6 | // Replaces the L2 with a broadcast manager for maintaining coherence 7 | class WithBroadcastManager extends Config((site, here, up) => { 8 | case BankedL2Key => up(BankedL2Key, site).copy(coherenceManager = CoherenceManagerWrapper.broadcastManager) 9 | }) 10 | 11 | class WithSystemBusWidth(bitWidth: Int) extends Config((site, here, up) => { 12 | case SystemBusKey => up(SystemBusKey, site).copy(beatBytes=bitWidth/8) 13 | }) 14 | -------------------------------------------------------------------------------- /generators/chipyard/src/main/scala/config/fragments/TileFragments.scala: -------------------------------------------------------------------------------- 1 | package chipyard.config 2 | 3 | import chisel3._ 4 | 5 | import freechips.rocketchip.config.{Field, Parameters, Config} 6 | import freechips.rocketchip.tile._ 7 | import freechips.rocketchip.subsystem._ 8 | import freechips.rocketchip.rocket.{RocketCoreParams, MulDivParams, DCacheParams, ICacheParams} 9 | 10 | import boom.common.{BoomTileAttachParams} 11 | import cva6.{CVA6TileAttachParams} 12 | 13 | import testchipip._ 14 | 15 | class WithL2TLBs(entries: Int) extends Config((site, here, up) => { 16 | case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map { 17 | case tp: RocketTileAttachParams => tp.copy(tileParams = tp.tileParams.copy( 18 | core = tp.tileParams.core.copy(nL2TLBEntries = entries))) 19 | case tp: BoomTileAttachParams => tp.copy(tileParams = tp.tileParams.copy( 20 | core = tp.tileParams.core.copy(nL2TLBEntries = entries))) 21 | case other => other 22 | } 23 | }) 24 | 25 | class WithTraceIO extends Config((site, here, up) => { 26 | case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map { 27 | case tp: BoomTileAttachParams => tp.copy(tileParams = tp.tileParams.copy( 28 | trace = true)) 29 | case tp: CVA6TileAttachParams => tp.copy(tileParams = tp.tileParams.copy( 30 | trace = true)) 31 | case other => other 32 | } 33 | case TracePortKey => Some(TracePortParams()) 34 | }) 35 | 36 | class WithNPerfCounters(n: Int = 29) extends Config((site, here, up) => { 37 | case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map { 38 | case tp: RocketTileAttachParams => tp.copy(tileParams = tp.tileParams.copy( 39 | core = tp.tileParams.core.copy(nPerfCounters = n))) 40 | case tp: BoomTileAttachParams => tp.copy(tileParams = tp.tileParams.copy( 41 | core = tp.tileParams.core.copy(nPerfCounters = n))) 42 | case other => other 43 | } 44 | }) 45 | 46 | class WithNPMPs(n: Int = 8) extends Config((site, here, up) => { 47 | case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map { 48 | case tp: RocketTileAttachParams => tp.copy(tileParams = tp.tileParams.copy( 49 | core = tp.tileParams.core.copy(nPMPs = n))) 50 | case tp: BoomTileAttachParams => tp.copy(tileParams = tp.tileParams.copy( 51 | core = tp.tileParams.core.copy(nPMPs = n))) 52 | case other => other 53 | } 54 | }) 55 | 56 | class WithRocketICacheScratchpad extends Config((site, here, up) => { 57 | case RocketTilesKey => up(RocketTilesKey, site) map { r => 58 | r.copy(icache = r.icache.map(_.copy(itimAddr = Some(0x300000 + r.hartId * 0x10000)))) 59 | } 60 | }) 61 | 62 | class WithRocketDCacheScratchpad extends Config((site, here, up) => { 63 | case RocketTilesKey => up(RocketTilesKey, site) map { r => 64 | r.copy(dcache = r.dcache.map(_.copy(nSets = 32, nWays = 1, scratch = Some(0x200000 + r.hartId * 0x10000)))) 65 | } 66 | }) 67 | 68 | -------------------------------------------------------------------------------- /generators/chipyard/src/main/scala/config/fragments/TracegenFragments.scala: -------------------------------------------------------------------------------- 1 | package chipyard.config 2 | 3 | import freechips.rocketchip.config.{Config, Field, Parameters} 4 | import tracegen.{TraceGenSystem} 5 | import chipyard.{BuildSystem} 6 | import chipyard.clocking.{HasChipyardPRCI} 7 | 8 | class TraceGenTop(implicit p: Parameters) extends TraceGenSystem 9 | with HasChipyardPRCI 10 | 11 | class WithTracegenSystem extends Config((site, here, up) => { 12 | case BuildSystem => (p: Parameters) => new TraceGenTop()(p) 13 | }) 14 | 15 | -------------------------------------------------------------------------------- /generators/chipyard/src/main/scala/example/InitZero.scala: -------------------------------------------------------------------------------- 1 | package chipyard.example 2 | 3 | import chisel3._ 4 | import chisel3.util._ 5 | import freechips.rocketchip.subsystem.{BaseSubsystem, CacheBlockBytes} 6 | import freechips.rocketchip.config.{Parameters, Field, Config} 7 | import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp, IdRange} 8 | import testchipip.TLHelper 9 | 10 | case class InitZeroConfig(base: BigInt, size: BigInt) 11 | case object InitZeroKey extends Field[Option[InitZeroConfig]](None) 12 | 13 | class InitZero(implicit p: Parameters) extends LazyModule { 14 | val node = TLHelper.makeClientNode( 15 | name = "init-zero", sourceId = IdRange(0, 1)) 16 | 17 | lazy val module = new InitZeroModuleImp(this) 18 | } 19 | 20 | class InitZeroModuleImp(outer: InitZero) extends LazyModuleImp(outer) { 21 | val config = p(InitZeroKey).get 22 | 23 | val (mem, edge) = outer.node.out(0) 24 | val addrBits = edge.bundle.addressBits 25 | val blockBytes = p(CacheBlockBytes) 26 | 27 | require(config.size % blockBytes == 0) 28 | 29 | val s_init :: s_write :: s_resp :: s_done :: Nil = Enum(4) 30 | val state = RegInit(s_init) 31 | 32 | val addr = Reg(UInt(addrBits.W)) 33 | val bytesLeft = Reg(UInt(log2Ceil(config.size+1).W)) 34 | 35 | mem.a.valid := state === s_write 36 | mem.a.bits := edge.Put( 37 | fromSource = 0.U, 38 | toAddress = addr, 39 | lgSize = log2Ceil(blockBytes).U, 40 | data = 0.U)._2 41 | mem.d.ready := state === s_resp 42 | 43 | when (state === s_init) { 44 | addr := config.base.U 45 | bytesLeft := config.size.U 46 | state := s_write 47 | } 48 | 49 | when (edge.done(mem.a)) { 50 | addr := addr + blockBytes.U 51 | bytesLeft := bytesLeft - blockBytes.U 52 | state := s_resp 53 | } 54 | 55 | when (mem.d.fire) { 56 | state := Mux(bytesLeft === 0.U, s_done, s_write) 57 | } 58 | } 59 | 60 | trait CanHavePeripheryInitZero { this: BaseSubsystem => 61 | implicit val p: Parameters 62 | 63 | p(InitZeroKey) .map { k => 64 | val initZero = LazyModule(new InitZero()(p)) 65 | fbus.fromPort(Some("init-zero"))() := initZero.node 66 | } 67 | } 68 | 69 | 70 | // DOC include start: WithInitZero 71 | class WithInitZero(base: BigInt, size: BigInt) extends Config((site, here, up) => { 72 | case InitZeroKey => Some(InitZeroConfig(base, size)) 73 | }) 74 | // DOC include end: WithInitZero 75 | -------------------------------------------------------------------------------- /generators/chipyard/src/main/scala/stage/ChipyardAnnotations.scala: -------------------------------------------------------------------------------- 1 | // See LICENSE for license details. 2 | // Based on Rocket Chip's stage implementation 3 | 4 | package chipyard.stage 5 | 6 | import freechips.rocketchip.stage.ConfigsAnnotation 7 | import firrtl.options.{HasShellOptions, ShellOption} 8 | 9 | /** This hijacks the existing ConfigAnnotation to accept the legacy _-delimited format */ 10 | private[stage] object UnderscoreDelimitedConfigsAnnotation extends HasShellOptions { 11 | override val options = Seq( 12 | new ShellOption[String]( 13 | longOption = "legacy-configs", 14 | toAnnotationSeq = a => { 15 | val split = a.split(':') 16 | assert(split.length == 2) 17 | val packageName = split.head 18 | val configs = split.last.split("_") 19 | Seq(new ConfigsAnnotation(configs map { config => if (config contains ".") s"${config}" else s"${packageName}.${config}" } )) 20 | }, 21 | helpText = "A string of underscore-delimited configs (configs have decreasing precendence from left to right).", 22 | shortOption = Some("LC") 23 | ) 24 | ) 25 | } 26 | 27 | -------------------------------------------------------------------------------- /generators/chipyard/src/main/scala/stage/ChipyardCli.scala: -------------------------------------------------------------------------------- 1 | // See LICENSE for license details. 2 | // Based on Rocket Chip's stage implementation 3 | 4 | package chipyard.stage 5 | 6 | import firrtl.options.Shell 7 | 8 | trait ChipyardCli { this: Shell => 9 | 10 | parser.note("Chipyard Generator Options") 11 | Seq( 12 | UnderscoreDelimitedConfigsAnnotation 13 | ).foreach(_.addOptions(parser)) 14 | } 15 | -------------------------------------------------------------------------------- /generators/chipyard/src/main/scala/stage/ChipyardStage.scala: -------------------------------------------------------------------------------- 1 | // See LICENSE for license details. 2 | // Based on Rocket Chip's stage implementation 3 | 4 | package chipyard.stage 5 | 6 | import chisel3.stage.{ChiselCli, ChiselStage} 7 | import firrtl.options.PhaseManager.PhaseDependency 8 | import firrtl.options.{Phase, PreservesAll, Shell} 9 | import firrtl.stage.FirrtlCli 10 | import freechips.rocketchip.stage.RocketChipCli 11 | import freechips.rocketchip.system.RocketChipStage 12 | 13 | import firrtl.options.{Phase, PhaseManager, PreservesAll, Shell, Stage, StageError, StageMain, Dependency} 14 | import firrtl.options.phases.DeletedWrapper 15 | 16 | class ChipyardStage extends ChiselStage { 17 | override val shell = new Shell("chipyard") with ChipyardCli with RocketChipCli with ChiselCli with FirrtlCli 18 | override val targets: Seq[PhaseDependency] = Seq( 19 | Dependency[freechips.rocketchip.stage.phases.Checks], 20 | Dependency[freechips.rocketchip.stage.phases.TransformAnnotations], 21 | Dependency[freechips.rocketchip.stage.phases.PreElaboration], 22 | Dependency[chisel3.stage.phases.Checks], 23 | Dependency[chisel3.stage.phases.Elaborate], 24 | Dependency[freechips.rocketchip.stage.phases.GenerateROMs], 25 | Dependency[chisel3.stage.phases.AddImplicitOutputFile], 26 | Dependency[chisel3.stage.phases.AddImplicitOutputAnnotationFile], 27 | Dependency[chisel3.stage.phases.MaybeAspectPhase], 28 | Dependency[chisel3.stage.phases.Emitter], 29 | Dependency[chisel3.stage.phases.Convert], 30 | Dependency[freechips.rocketchip.stage.phases.GenerateFirrtlAnnos], 31 | Dependency[freechips.rocketchip.stage.phases.AddDefaultTests], 32 | Dependency[chipyard.stage.phases.AddDefaultTests], 33 | Dependency[chipyard.stage.phases.GenerateTestSuiteMakefrags], 34 | Dependency[freechips.rocketchip.stage.phases.GenerateArtefacts], 35 | ) 36 | override final def invalidates(a: Phase): Boolean = false 37 | } 38 | -------------------------------------------------------------------------------- /generators/chipyard/src/main/scala/stage/phases/AddDefaultTests.scala: -------------------------------------------------------------------------------- 1 | // See LICENSE for license details. 2 | // Based on Rocket Chip's stage implementation 3 | 4 | package chipyard.stage.phases 5 | 6 | import scala.util.Try 7 | import scala.collection.mutable 8 | 9 | import chipsalliance.rocketchip.config.Parameters 10 | import chisel3.stage.phases.Elaborate 11 | import firrtl.AnnotationSeq 12 | import firrtl.annotations.{Annotation, NoTargetAnnotation} 13 | import firrtl.options.{Phase, PreservesAll, Dependency} 14 | import firrtl.options.Viewer.view 15 | import freechips.rocketchip.stage.RocketChipOptions 16 | import freechips.rocketchip.stage.phases.{RocketTestSuiteAnnotation} 17 | import freechips.rocketchip.system.{RocketTestSuite, TestGeneration} 18 | import freechips.rocketchip.subsystem.{TilesLocated, InSubsystem} 19 | import freechips.rocketchip.util.HasRocketChipStageUtils 20 | import freechips.rocketchip.tile.XLen 21 | 22 | import chipyard.TestSuiteHelper 23 | import chipyard.TestSuitesKey 24 | 25 | class AddDefaultTests extends Phase with HasRocketChipStageUtils { 26 | // Make sure we run both after RocketChip's version of this phase, and Rocket Chip's annotation emission phase 27 | // because the RocketTestSuiteAnnotation is not serializable (but is not marked as such). 28 | override val prerequisites = Seq( 29 | Dependency[freechips.rocketchip.stage.phases.GenerateFirrtlAnnos], 30 | Dependency[freechips.rocketchip.stage.phases.AddDefaultTests]) 31 | override val dependents = Seq(Dependency[freechips.rocketchip.stage.phases.GenerateTestSuiteMakefrags]) 32 | 33 | private def addTestSuiteAnnotations(implicit p: Parameters): Seq[Annotation] = { 34 | val annotations = mutable.ArrayBuffer[Annotation]() 35 | val suiteHelper = new TestSuiteHelper 36 | // Use Xlen as a proxy for detecting if we are a processor-like target 37 | // The underlying test suites expect this field to be defined 38 | val tileParams = p(TilesLocated(InSubsystem)) map (tp => tp.tileParams) 39 | if (p.lift(XLen).nonEmpty) 40 | // If a custom test suite is set up, use the custom test suite 41 | annotations += CustomMakefragSnippet(p(TestSuitesKey).apply(tileParams, suiteHelper, p)) 42 | 43 | RocketTestSuiteAnnotation(suiteHelper.suites.values.toSeq) +: annotations 44 | } 45 | 46 | 47 | override def transform(annotations: AnnotationSeq): AnnotationSeq = { 48 | val (testSuiteAnnos, oAnnos) = annotations.partition { 49 | case RocketTestSuiteAnnotation(_) => true 50 | case o => false 51 | } 52 | implicit val p = getConfig(view[RocketChipOptions](annotations).configNames.get).toInstance 53 | addTestSuiteAnnotations ++ oAnnos 54 | } 55 | 56 | override final def invalidates(a: Phase): Boolean = false 57 | } 58 | -------------------------------------------------------------------------------- /generators/chipyard/src/main/scala/stage/phases/GenerateTestSuiteMakefrags.scala: -------------------------------------------------------------------------------- 1 | // See LICENSE for license details. 2 | // Based on Rocket Chip's stage implementation 3 | 4 | package chipyard.stage.phases 5 | 6 | import scala.collection.mutable 7 | 8 | import firrtl.AnnotationSeq 9 | import firrtl.annotations.{Annotation, NoTargetAnnotation} 10 | import firrtl.options.{Phase, PreservesAll, StageOptions, Unserializable, Dependency} 11 | import firrtl.options.Viewer.view 12 | import freechips.rocketchip.stage.RocketChipOptions 13 | import freechips.rocketchip.stage.phases.{RocketTestSuiteAnnotation} 14 | import freechips.rocketchip.system.TestGeneration 15 | import freechips.rocketchip.util.HasRocketChipStageUtils 16 | 17 | trait MakefragSnippet { self: Annotation => 18 | def toMakefrag: String 19 | } 20 | 21 | case class CustomMakefragSnippet(val toMakefrag: String) extends NoTargetAnnotation with MakefragSnippet with Unserializable 22 | 23 | /** Generates a make script to run tests in [[RocketTestSuiteAnnotation]]. */ 24 | class GenerateTestSuiteMakefrags extends Phase with HasRocketChipStageUtils { 25 | 26 | // Our annotations tend not to be serializable, but are not marked as such. 27 | override val prerequisites = Seq(Dependency[freechips.rocketchip.stage.phases.GenerateFirrtlAnnos], 28 | Dependency[chipyard.stage.phases.AddDefaultTests]) 29 | 30 | override def transform(annotations: AnnotationSeq): AnnotationSeq = { 31 | val targetDir = view[StageOptions](annotations).targetDir 32 | val fileName = s"${view[RocketChipOptions](annotations).longName.get}.d" 33 | 34 | val makefragBuilder = new mutable.StringBuilder() 35 | val outputAnnotations = annotations.flatMap { 36 | case RocketTestSuiteAnnotation(tests) => 37 | // Unfortunately the gen method of TestGeneration is rocketchip package 38 | // private, so we either have to copy code in or use the stateful form 39 | TestGeneration.addSuites(tests) 40 | None 41 | case a: MakefragSnippet => 42 | makefragBuilder :+ ("\n" + a.toMakefrag) 43 | None 44 | case a => Some(a) 45 | } 46 | writeOutputFile(targetDir, fileName, TestGeneration.generateMakeFrag ++ makefragBuilder.toString) 47 | outputAnnotations 48 | } 49 | 50 | override final def invalidates(a: Phase): Boolean = false 51 | } 52 | -------------------------------------------------------------------------------- /generators/chipyard/src/main/scala/unittest/TestHarness.scala: -------------------------------------------------------------------------------- 1 | package chipyard.unittest 2 | 3 | import chisel3._ 4 | import freechips.rocketchip.config.Parameters 5 | 6 | class TestHarness(implicit val p: Parameters) extends Module { 7 | val io = IO(new Bundle { val success = Output(Bool()) }) 8 | io.success := Module(new UnitTestSuite).io.finished 9 | } 10 | -------------------------------------------------------------------------------- /generators/chipyard/src/main/scala/unittest/UnitTestSuite.scala: -------------------------------------------------------------------------------- 1 | package chipyard.unittest 2 | 3 | import freechips.rocketchip.config.Parameters 4 | import freechips.rocketchip.util.{ElaborationArtefacts, PlusArgArtefacts} 5 | 6 | class UnitTestSuite(implicit p: Parameters) extends freechips.rocketchip.unittest.UnitTestSuite { 7 | ElaborationArtefacts.add("plusArgs", PlusArgArtefacts.serialize_cHeader) 8 | } 9 | -------------------------------------------------------------------------------- /generators/chipyard/src/test/scala/clocking/SimplePllConfigurationSpec.scala: -------------------------------------------------------------------------------- 1 | //See LICENSE for license details. 2 | package chipyard.clocking 3 | 4 | import freechips.rocketchip.prci._ 5 | 6 | class SimplePllConfigurationSpec extends org.scalatest.flatspec.AnyFlatSpec { 7 | 8 | def genConf(freqMHz: Iterable[Double]): SimplePllConfiguration = new SimplePllConfiguration( 9 | "testPLL", 10 | freqMHz.map({ f => ClockSinkParameters( 11 | name = Some(s"desiredFreq_$f"), 12 | take = Some(ClockParameters(f))) }).toSeq, 13 | maximumAllowableFreqMHz = 16000.0) 14 | 15 | def trySuccessfulConf(requestedFreqs: Seq[Double], expected: Double): Unit = { 16 | val freqStr = requestedFreqs.mkString(", ") 17 | it should s"select a reference of ${expected} MHz for ${freqStr} MHz" in { 18 | val conf = genConf(requestedFreqs) 19 | conf.emitSummaries 20 | assert(expected == conf.referenceFreqMHz) 21 | } 22 | } 23 | 24 | trySuccessfulConf(Seq(3200.0, 1600.0, 1000.0, 100.0), 16000.0) 25 | trySuccessfulConf(Seq(3200.0, 1600.0), 3200.0) 26 | trySuccessfulConf(Seq(3200.0, 1066.7), 3200.0) 27 | trySuccessfulConf(Seq(100, 50, 6.67), 100) 28 | trySuccessfulConf(Seq(1, 2, 3, 5, 7, 11, 13).map(_ * 10.0), 1560.0) 29 | } 30 | -------------------------------------------------------------------------------- /generators/firechip/src/main/scala/TargetLandTestSuites.scala: -------------------------------------------------------------------------------- 1 | //See LICENSE for license details. 2 | package firesim.firesim 3 | 4 | import scala.collection.mutable.LinkedHashSet 5 | 6 | import freechips.rocketchip.system.{TestGeneration, RocketTestSuite} 7 | 8 | /* This imports tests from FireChip to test devices that aren't natively 9 | * tested by the riscv assembly tests. 10 | * Firesim's target-specific makefrag gives the recipes for building the 11 | * binaries. 12 | */ 13 | 14 | class BlockdevTestSuite(prefix: String, val names: LinkedHashSet[String]) extends RocketTestSuite { 15 | val envName = "" 16 | // fc_test_dir is is defined in firesim's Makefrag 17 | val dir = "$(fc_test_dir)" 18 | val makeTargetName = prefix + "-blkdev-tests" 19 | def kind = "blockdev" 20 | // Blockdev tests need an image, which complicates this 21 | def additionalArgs = "+blkdev-in-mem0=128 +nic-loopback0" 22 | override def toString = s"$makeTargetName = \\\n" + 23 | // Make variable with the binaries of the suite 24 | names.map(n => s"\t$n.riscv").mkString(" \\\n") + "\n\n" + 25 | // Variables with binary specific arguments 26 | names.map(n => s"$n.riscv_ARGS=$additionalArgs").mkString(" \n") + 27 | postScript 28 | } 29 | 30 | object FastBlockdevTests extends BlockdevTestSuite("fast", LinkedHashSet("blkdev")) 31 | object SlowBlockdevTests extends BlockdevTestSuite("slow", LinkedHashSet("big-blkdev")) 32 | 33 | class NICTestSuite(prefix: String, val names: LinkedHashSet[String]) extends RocketTestSuite { 34 | val envName = "" 35 | val dir = "$(fc_test_dir)" 36 | val makeTargetName = prefix + "-nic-tests" 37 | def kind = "nic" 38 | def additionalArgs = "+netbw0=100 +linklatency0=6405 +netburst0=8 +slotid=0 +nic-loopback0" 39 | override def toString = s"$makeTargetName = \\\n" + 40 | names.map(n => s"\t$n.riscv").mkString(" \\\n") + "\n\n" + 41 | names.map(n => s"$n.riscv_ARGS=$additionalArgs").mkString(" \n") + 42 | postScript 43 | } 44 | 45 | object NICLoopbackTests extends NICTestSuite("loopback", LinkedHashSet("nic-loopback")) 46 | -------------------------------------------------------------------------------- /generators/tracegen/src/main/scala/System.scala: -------------------------------------------------------------------------------- 1 | package tracegen 2 | 3 | import chisel3._ 4 | import freechips.rocketchip.config.{Field, Parameters} 5 | import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp, BufferParams} 6 | import freechips.rocketchip.interrupts.{IntSinkNode, IntSinkPortSimple} 7 | import freechips.rocketchip.groundtest.{DebugCombiner, TraceGenParams, GroundTestTile} 8 | import freechips.rocketchip.subsystem._ 9 | 10 | class TraceGenSystem(implicit p: Parameters) extends BaseSubsystem 11 | with HasTiles 12 | with CanHaveMasterAXI4MemPort { 13 | 14 | def coreMonitorBundles = Nil 15 | val tileStatusNodes = tiles.collect { 16 | case t: GroundTestTile => t.statusNode.makeSink() 17 | case t: BoomTraceGenTile => t.statusNode.makeSink() 18 | } 19 | override lazy val module = new TraceGenSystemModuleImp(this) 20 | } 21 | 22 | class TraceGenSystemModuleImp(outer: TraceGenSystem) 23 | extends BaseSubsystemModuleImp(outer) 24 | { 25 | val success = IO(Output(Bool())) 26 | 27 | val status = dontTouch(DebugCombiner(outer.tileStatusNodes.map(_.bundle))) 28 | 29 | success := outer.tileCeaseSinkNode.in.head._1.asUInt.andR 30 | 31 | } 32 | -------------------------------------------------------------------------------- /generators/tracegen/tracegen.mk: -------------------------------------------------------------------------------- 1 | ############################################################## 2 | # extra variables/targets ingested by the chipyard make system 3 | ############################################################## 4 | 5 | AXE_DIR=$(base_dir)/tools/axe/src 6 | AXE=$(AXE_DIR)/axe 7 | 8 | $(AXE): $(wildcard $(AXE_DIR)/*.[ch]) $(AXE_DIR)/make.sh 9 | cd $(AXE_DIR) && ./make.sh 10 | 11 | $(output_dir)/tracegen.out: $(SIM_PREREQ) 12 | mkdir -p $(output_dir) && $(sim) $(PERMISSIVE_ON) $(SIM_FLAGS) $(EXTRA_SIM_FLAGS) $(SEED_FLAG) $(VERBOSE_FLAGS) $(PERMISSIVE_OFF) none $@ 13 | 14 | $(output_dir)/tracegen.result: $(output_dir)/tracegen.out $(AXE) 15 | $(base_dir)/scripts/check-tracegen.sh $< > $@ 16 | 17 | .PHONY: tracegen 18 | tracegen: $(output_dir)/tracegen.result 19 | -------------------------------------------------------------------------------- /project/build.properties: -------------------------------------------------------------------------------- 1 | sbt.version=1.5.5 2 | -------------------------------------------------------------------------------- /project/plugins.sbt: -------------------------------------------------------------------------------- 1 | addSbtPlugin("com.eed3si9n" % "sbt-assembly" % "0.15.0") 2 | addSbtPlugin("ch.epfl.scala" % "sbt-scalafix" % "0.9.21") 3 | -------------------------------------------------------------------------------- /scripts/add-githooks.sh: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env bash 2 | 3 | # adds githooks, expects to be run from base directory 4 | 5 | git config core.hooksPath .githooks 6 | -------------------------------------------------------------------------------- /scripts/build-openocd.sh: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env bash 2 | 3 | # exit script if any command fails 4 | set -e 5 | set -o pipefail 6 | 7 | RDIR=$(git rev-parse --show-toplevel) 8 | 9 | if [ -z "${RISCV}" ] ; then 10 | ! [ -r "${RDIR}/env.sh" ] || . "${RDIR}/env.sh" 11 | if [ -z "${RISCV}" ] ; then 12 | echo "${0}: set the RISCV environment variable to desired install path" 13 | exit 1 14 | fi 15 | fi 16 | 17 | SRCDIR="${RDIR}/toolchains/riscv-tools" 18 | . "${RDIR}/scripts/build-util.sh" 19 | 20 | git config --unset submodule.toolchains/riscv-tools/riscv-openocd.update || : 21 | module_prepare riscv-openocd 22 | module_run riscv-openocd ./bootstrap 23 | module_build riscv-openocd --prefix="${RISCV}" \ 24 | --enable-remote-bitbang --enable-jtag_vpi --disable-werror 25 | -------------------------------------------------------------------------------- /scripts/build-util.sh: -------------------------------------------------------------------------------- 1 | # Derived from 2 | # https://github.com/riscv/riscv-tools/blob/master/build.common 3 | 4 | [ -n "${SRCDIR}" ] || exit 1 5 | 6 | # Scale number of parallel make jobs by hardware thread count 7 | ncpu="${NPROC:-$(getconf _NPROCESSORS_ONLN || # GNU 8 | getconf NPROCESSORS_ONLN || # *BSD, Solaris 9 | nproc --all || # Linux 10 | sysctl -n hw.ncpu || # *BSD, OS X 11 | :)}" 2>/dev/null 12 | case ${ncpu} in 13 | ''|*[!0-9]*) ;; # Ignore non-integer values 14 | *) export MAKEFLAGS="-j ${ncpu} ${MAKEFLAGS}" ;; 15 | esac 16 | 17 | # Allow user to override MAKE 18 | [ -n "${MAKE:+x}" ] || MAKE=$(command -v gnumake || command -v gmake || command -v make) 19 | readonly MAKE 20 | 21 | 22 | module_prepare() ( # [ignored-submodule..] 23 | set -e 24 | name=$1 25 | shift 26 | 27 | dir="${SRCDIR}/${name}" 28 | echo "=> Starting ${name} build" 29 | echo "==> Initializing ${name} submodule" 30 | if [ $# -gt 0 ] ; then 31 | git submodule update --init "${dir}" 32 | while [ -n "$1" ] ; do 33 | git -C "${dir}" config submodule."${1}".update none 34 | shift 35 | done 36 | fi 37 | git submodule update --init --recursive "${dir}" 38 | ) 39 | 40 | module_run() ( # 41 | set -e 42 | cd "${SRCDIR}/${1}" 43 | shift 44 | "$@" 45 | ) 46 | 47 | module_make() ( # 48 | set -e -o pipefail 49 | cd "${SRCDIR}/${1}/build" 50 | shift 51 | "${MAKE}" "$@" | tee "build-${1:-make}.log" 52 | if [ -n "$CLEANAFTERINSTALL" ] ; then 53 | "${MAKE}" clean # get rid of intermediate files 54 | fi 55 | ) 56 | 57 | module_build() ( # [configure-arg..] 58 | set -e -o pipefail 59 | name=$1 60 | shift 61 | 62 | cd "${SRCDIR}/${name}" 63 | 64 | if [ -e build ] ; then 65 | echo "==> Removing existing ${name}/build directory" 66 | rm -rf build 67 | fi 68 | if ! [ -e configure ] ; then 69 | echo "==> Updating autoconf files for ${name}" 70 | find . -iname configure.ac -type f -print0 | 71 | while read -r -d '' file ; do 72 | mkdir -p -- "${file%/*}/m4" 73 | done 74 | autoreconf -i 75 | fi 76 | 77 | mkdir -p build 78 | cd build 79 | { 80 | export PATH="${RISCV:+${RISCV}/bin:}${PATH}" 81 | echo "==> Configuring ${name}" 82 | ../configure "$@" 83 | echo "==> Building ${name}" 84 | "${MAKE}" 85 | echo "==> Installing ${name}" 86 | "${MAKE}" install 87 | if [ -n "$CLEANAFTERINSTALL" ] ; then 88 | "${MAKE}" clean # get rid of intermediate files 89 | fi 90 | } 2>&1 | tee build.log 91 | ) 92 | 93 | module_all() { # [configure-arg..] 94 | module_prepare "$1" 95 | module_build "$@" 96 | } 97 | -------------------------------------------------------------------------------- /scripts/centos-req.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | set -ex 4 | 5 | sudo yum groupinstall -y "Development tools" 6 | sudo yum install -y gmp-devel mpfr-devel libmpc-devel zlib-devel vim git java java-devel 7 | 8 | # Install SBT https://www.scala-sbt.org/release/docs/Installing-sbt-on-Linux.html#Red+Hat+Enterprise+Linux+and+other+RPM-based+distributions 9 | # sudo rm -f /etc/yum.repos.d/bintray-rpm.repo 10 | # Use rm above if sbt installed from bintray before. 11 | curl -L https://www.scala-sbt.org/sbt-rpm.repo > sbt-rpm.repo 12 | sudo mv sbt-rpm.repo /etc/yum.repos.d/ 13 | 14 | sudo yum install -y sbt texinfo gengetopt 15 | sudo yum install -y expat-devel libusb1-devel ncurses-devel cmake "perl(ExtUtils::MakeMaker)" 16 | # deps for poky 17 | sudo yum install -y python38 patch diffstat texi2html texinfo subversion chrpath git wget 18 | # deps for qemu 19 | sudo yum install -y gtk3-devel 20 | # deps for firemarshal 21 | sudo yum install -y python38-pip python38-devel rsync libguestfs-tools makeinfo expat ctags 22 | # Install GNU make 4.x (needed to cross-compile glibc 2.28+) 23 | sudo yum install -y centos-release-scl 24 | sudo yum install -y devtoolset-8-make 25 | # install DTC 26 | sudo yum install -y dtc 27 | sudo yum install -y python 28 | 29 | # install verilator 30 | git clone http://git.veripool.org/git/verilator 31 | cd verilator 32 | git checkout v4.034 33 | autoconf && ./configure && make -j$(nproc) && sudo make install 34 | -------------------------------------------------------------------------------- /scripts/check-tracegen.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | set -e 4 | 5 | SCRIPT_DIR=$(dirname $0) 6 | AXE_DIR=$(realpath ${SCRIPT_DIR}/../tools/axe) 7 | ROCKET_DIR=$(realpath ${SCRIPT_DIR}/../generators/rocket-chip) 8 | 9 | TO_AXE=${ROCKET_DIR}/scripts/toaxe.py 10 | AXE=${AXE_DIR}/src/axe 11 | AXE_SHRINK=${AXE_DIR}/src/axe-shrink.py 12 | 13 | PATH=$PATH:${AXE_DIR}/src 14 | 15 | grep '.*:.*#.*@' $1 > /tmp/clean-trace.txt 16 | python2 "$TO_AXE" /tmp/clean-trace.txt > /tmp/trace.axe 17 | result=$("$AXE" check wmo /tmp/trace.axe) 18 | 19 | if [ "$result" != OK ]; then 20 | "$AXE_SHRINK" wmo /tmp/trace.axe 21 | else 22 | echo OK 23 | fi 24 | -------------------------------------------------------------------------------- /scripts/entrypoint.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | # used with the dockerfile to set up enviroment variables by running env.sh 4 | # adapted from https://stackoverflow.com/questions/55921914/how-to-source-a-script-with-environment-variables-in-a-docker-build-process 5 | 6 | . /root/chipyard/env.sh 7 | 8 | exec "$@" 9 | -------------------------------------------------------------------------------- /scripts/firesim-setup.sh: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env bash 2 | 3 | # Sets up FireSim for use as a library within Chipyard 4 | 5 | set -e 6 | set -o pipefail 7 | 8 | RDIR=$(pwd) 9 | scripts_dir="$( cd "$( dirname "${BASH_SOURCE[0]:-${(%):-%x}}" )" >/dev/null 2>&1 && pwd )" 10 | 11 | cd "${scripts_dir}/.." 12 | 13 | # Reenable the FireSim submodule 14 | git config --unset submodule.sims/firesim.update || true 15 | cd sims/firesim 16 | ./build-setup.sh "$@" --library --skip-validate 17 | cd "$RDIR" 18 | -------------------------------------------------------------------------------- /scripts/gen-tags.sh: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env bash 2 | 3 | # run this script in the main Chipyard directory to generate ctags for all relevant repos 4 | # note: this requires exuberant-ctags 5 | # tested with: Exuberant Ctags 5.8 6 | # instructions: 7 | # cd /path/to/chipyard/ 8 | # ./scripts/gen-tags.sh 9 | # 10 | # input: 11 | # * nothing 12 | # 13 | # output: 14 | # * tags file in the directory that this was called in 15 | 16 | # ctags wrapper 17 | ctags -R --exclude=@.ctagsignore --links=no --languages=scala,C,C++,python 18 | -------------------------------------------------------------------------------- /scripts/init-fpga.sh: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env bash 2 | # exit script if any command fails 3 | set -e 4 | set -o pipefail 5 | 6 | # Enable submodule update for FPGA tools. 7 | git config --unset submodule.fpga/fpga-shells.update || : 8 | # Initialize local FPGA tools. 9 | git submodule update --init --recursive fpga/fpga-shells 10 | # Disable submodule update for FPGA tools. 11 | git config submodule.fpga/fpga-shells.update none 12 | -------------------------------------------------------------------------------- /scripts/init-software.sh: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env bash 2 | # exit script if any command fails 3 | set -e 4 | set -o pipefail 5 | 6 | # Enable submodule update for software submodules 7 | git config --unset submodule.software/nvdla-workload.update || : 8 | git config --unset submodule.software/coremark.update || : 9 | git config --unset submodule.software/spec2017.update || : 10 | 11 | # Initialize local software submodules 12 | git submodule update --init --recursive software/nvdla-workload 13 | git submodule update --init --recursive software/coremark 14 | git submodule update --init --recursive software/spec2017 15 | -------------------------------------------------------------------------------- /scripts/init-submodules-no-riscv-tools.sh: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env bash 2 | 3 | # wrapper to log output from init-submodules script 4 | 5 | set -e 6 | set -o pipefail 7 | 8 | RDIR=$(git rev-parse --show-toplevel) 9 | cd "$RDIR" 10 | 11 | ./scripts/init-submodules-no-riscv-tools-nolog.sh "$@" 2>&1 | tee init-submodules-no-riscv-tools.log 12 | -------------------------------------------------------------------------------- /scripts/init-vlsi.sh: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env bash 2 | # exit script if any command fails 3 | set -e 4 | set -o pipefail 5 | 6 | # Initialize HAMMER and CAD-plugins 7 | git submodule update --init --recursive vlsi/hammer 8 | git submodule update --init --recursive vlsi/hammer-cadence-plugins 9 | git submodule update --init --recursive vlsi/hammer-synopsys-plugins 10 | git submodule update --init --recursive vlsi/hammer-mentor-plugins 11 | 12 | # Initialize HAMMER tech plugin 13 | if [[ $1 != *asap7* ]] && [[ $1 != *sky130* ]]; then 14 | git submodule update --init --recursive vlsi/hammer-$1-plugin 15 | fi 16 | -------------------------------------------------------------------------------- /scripts/insert-includes.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/python 2 | 3 | # replaces a `include with the full include file 4 | # 5 | # args 6 | # $1 - file to remove includes from 7 | # $2 - file to write output to 8 | # $3 - list of directories to search for includes in (note: NON-RECURSIVE must specify all dirs) 9 | # includes are found relative to this path 10 | # this is equivalent to something like +incdir+ 11 | 12 | import sys 13 | import re 14 | import os 15 | 16 | inVlog = sys.argv[1] 17 | outVlog = sys.argv[2] 18 | print("[INFO] Replaces includes from: " + str(inVlog)) 19 | 20 | if inVlog == outVlog: 21 | sys.exit("[ERROR] The input and output file cannot be the same.") 22 | 23 | # add directories to search list 24 | incDirs = sys.argv[3:] 25 | print("[INFO] Searching following dirs for includes: " + str(incDirs)) 26 | 27 | # open file 28 | with open(inVlog, 'r') as inFile: 29 | with open(outVlog, 'w') as outFile: 30 | # for each include found, search through all dirs and replace if found, error if not 31 | for num, line in enumerate(inFile, 1): 32 | match = re.match(r"^ *`include +\"(.*)\"", line) 33 | if match: 34 | # search for include and replace 35 | found = False 36 | for d in incDirs: 37 | potentialIncFileName = d + "/" + match.group(1) 38 | if os.path.exists(potentialIncFileName): 39 | found = True 40 | with open(potentialIncFileName, 'r') as incFile: 41 | for iline in incFile: 42 | outFile.write(iline) 43 | break 44 | 45 | # must find something to include with 46 | if not found: 47 | sys.exit("[ERROR] Couldn't replace include \"" + str(match.group(1)) + "\" found on line " + str(num)) 48 | else: 49 | outFile.write(line) 50 | 51 | print("[INFO] Success. Writing output to: " + str(outVlog)) 52 | -------------------------------------------------------------------------------- /scripts/smartelf2hex.sh: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env bash 2 | 3 | # This script find the appropriate arguments to pass to elf2hex by inspecting the given RISC-V elf binary 4 | # First and only argument is the binary to be converted. 5 | # The output of this script should be redirected to a file (as with normal elf2hex). 6 | 7 | binary=$1 8 | segments=`readelf --segments --wide $binary` 9 | entry_hex=`echo -e "$segments" | grep "Entry point" | cut -f3 -d' ' | sed 's/0x//' | tr [:lower:] [:upper:]` 10 | entry_dec=`bc <<< "ibase=16;$entry_hex"` 11 | length_hex=`echo "$segments" | grep "LOAD\|TLS" | tail -n 1 | tr -s [:space:] | cut -f4,7 -d' '` 12 | length_dec=`echo $length_hex | tr -d x | tr [:lower:] [:upper:] | tr ' ' + | sed 's/^/ibase=16;/' | sed "s/$/-$entry_hex/" | bc` 13 | power_2_length=`echo "x=l($length_dec)/l(2); scale=0; 2^((x+1)/1)" | bc -l` 14 | width=64 15 | depth=$((power_2_length / width)) 16 | elf2hex $width $depth $binary $entry_dec 17 | -------------------------------------------------------------------------------- /scripts/tutorial-patches/RocketConfigs.scala.patch: -------------------------------------------------------------------------------- 1 | diff --git a/generators/chipyard/src/main/scala/config/RocketConfigs.scala b/generators/chipyard/src/main/scala/config/RocketConfigs.scala 2 | index 8e6e486..fc3a811 100644 3 | --- a/generators/chipyard/src/main/scala/config/RocketConfigs.scala 4 | +++ b/generators/chipyard/src/main/scala/config/RocketConfigs.scala 5 | @@ -105,7 +105,7 @@ class GB1MemoryRocketConfig extends Config( 6 | 7 | // DOC include start: Sha3Rocket 8 | class Sha3RocketConfig extends Config( 9 | - new sha3.WithSha3Accel ++ // add SHA3 rocc accelerator 10 | +// new sha3.WithSha3Accel ++ // add SHA3 rocc accelerator 11 | new freechips.rocketchip.subsystem.WithNBigCores(1) ++ 12 | new chipyard.config.AbstractConfig) 13 | // DOC include end: Sha3Rocket 14 | -------------------------------------------------------------------------------- /scripts/tutorial-patches/build.sbt.patch: -------------------------------------------------------------------------------- 1 | diff --git a/build.sbt b/build.sbt 2 | index bbbb8251..b7adcb73 100644 3 | --- a/build.sbt 4 | +++ b/build.sbt 5 | @@ -143,7 +143,7 @@ lazy val testchipip = (project in file("generators/testchipip")) 6 | 7 | lazy val chipyard = (project in file("generators/chipyard")) 8 | .dependsOn(testchipip, rocketchip, boom, hwacha, sifive_blocks, sifive_cache, iocell, 9 | - sha3, // On separate line to allow for cleaner tutorial-setup patches 10 | +// sha3, // On separate line to allow for cleaner tutorial-setup patches 11 | dsptools, `rocket-dsp-utils`, 12 | gemmini, icenet, tracegen, cva6, nvdla, sodor, ibex, fft_generator) 13 | .settings(libraryDependencies ++= rocketLibDeps.value) 14 | @@ -189,11 +189,11 @@ lazy val sodor = (project in file("generators/riscv-sodor")) 15 | .settings(libraryDependencies ++= rocketLibDeps.value) 16 | .settings(commonSettings) 17 | 18 | -lazy val sha3 = (project in file("generators/sha3")) 19 | - .dependsOn(rocketchip, midasTargetUtils) 20 | - .settings(libraryDependencies ++= rocketLibDeps.value) 21 | - .settings(chiselTestSettings) 22 | - .settings(commonSettings) 23 | +//lazy val sha3 = (project in file("generators/sha3")) 24 | +// .dependsOn(rocketchip, midasTargetUtils) 25 | +// .settings(libraryDependencies ++= rocketLibDeps.value) 26 | +// .settings(chiselTestSettings) 27 | +// .settings(commonSettings) 28 | 29 | lazy val gemmini = (project in file("generators/gemmini")) 30 | .dependsOn(testchipip, rocketchip) 31 | -------------------------------------------------------------------------------- /scripts/tutorial-setup.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | set -e -x 4 | 5 | rm -rf generators/sha3 6 | 7 | for p in scripts/tutorial-patches/*.patch 8 | do 9 | echo "Applying tutorial patch $p" 10 | git apply $p 11 | done 12 | -------------------------------------------------------------------------------- /scripts/ubuntu-req.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | set -ex 4 | 5 | sudo apt-get install -y build-essential bison flex software-properties-common curl 6 | sudo apt-get install -y libgmp-dev libmpfr-dev libmpc-dev zlib1g-dev vim default-jdk default-jre 7 | # install sbt: https://www.scala-sbt.org/release/docs/Installing-sbt-on-Linux.html#Ubuntu+and+other+Debian-based+distributions 8 | echo "deb https://repo.scala-sbt.org/scalasbt/debian /" | sudo tee -a /etc/apt/sources.list.d/sbt.list 9 | curl -sL "https://keyserver.ubuntu.com/pks/lookup?op=get&search=0x2EE0EA64E40A89B84B2DF73499E82A75642AC823" | sudo apt-key add 10 | sudo apt-get update 11 | sudo apt-get install -y sbt 12 | sudo apt-get install -y texinfo gengetopt 13 | sudo apt-get install -y libexpat1-dev libusb-dev libncurses5-dev cmake 14 | # deps for poky 15 | sudo apt-get install -y python3.8 patch diffstat texi2html texinfo subversion chrpath wget 16 | # deps for qemu 17 | sudo apt-get install -y libgtk-3-dev gettext 18 | # deps for firemarshal 19 | sudo apt-get install -y python3-pip python3.8-dev rsync libguestfs-tools expat ctags 20 | # install DTC 21 | sudo apt-get install -y device-tree-compiler 22 | sudo apt-get install -y python 23 | # install git >= 2.17 24 | sudo add-apt-repository ppa:git-core/ppa -y 25 | sudo apt-get update 26 | sudo apt-get install git -y 27 | 28 | # install verilator 29 | sudo apt-get install -y autoconf 30 | git clone http://git.veripool.org/git/verilator 31 | cd verilator 32 | git checkout v4.034 33 | autoconf && ./configure && make -j$(nproc) && sudo make install 34 | -------------------------------------------------------------------------------- /sims/common-sim-flags.mk: -------------------------------------------------------------------------------- 1 | #---------------------------------------------------------------------------------------- 2 | # common gcc configuration/optimization 3 | #---------------------------------------------------------------------------------------- 4 | SIM_OPT_CXXFLAGS := -O3 5 | 6 | SIM_CXXFLAGS = \ 7 | $(CXXFLAGS) \ 8 | $(SIM_OPT_CXXFLAGS) \ 9 | -std=c++11 \ 10 | -I$(RISCV)/include \ 11 | -I$(dramsim_dir) \ 12 | -I$(build_dir) \ 13 | $(EXTRA_SIM_CXXFLAGS) 14 | 15 | SIM_LDFLAGS = \ 16 | $(LDFLAGS) \ 17 | -L$(RISCV)/lib \ 18 | -Wl,-rpath,$(RISCV)/lib \ 19 | -L$(sim_dir) \ 20 | -L$(dramsim_dir) \ 21 | -lfesvr \ 22 | -ldramsim \ 23 | $(EXTRA_SIM_LDFLAGS) 24 | 25 | SIM_FILE_REQS += \ 26 | $(ROCKETCHIP_RSRCS_DIR)/vsrc/EICG_wrapper.v 27 | -------------------------------------------------------------------------------- /sims/vcs/.gitignore: -------------------------------------------------------------------------------- 1 | * 2 | !.gitignore 3 | !Makefile 4 | !dramsim2_ini 5 | -------------------------------------------------------------------------------- /sims/verilator/.gitignore: -------------------------------------------------------------------------------- 1 | * 2 | !.gitignore 3 | !Makefile 4 | !verilator.mk 5 | !dramsim2_ini 6 | -------------------------------------------------------------------------------- /tests/.gitignore: -------------------------------------------------------------------------------- 1 | *.o 2 | *.riscv 3 | *.dump 4 | *.img 5 | libgloss/ 6 | -------------------------------------------------------------------------------- /tests/Makefile: -------------------------------------------------------------------------------- 1 | GCC=riscv64-unknown-elf-gcc 2 | OBJDUMP=riscv64-unknown-elf-objdump 3 | CFLAGS= -std=gnu99 -O2 -fno-common -fno-builtin-printf -Wall 4 | LDFLAGS= -static 5 | 6 | include libgloss.mk 7 | 8 | PROGRAMS = pwm blkdev accum charcount nic-loopback big-blkdev pingd \ 9 | streaming-passthrough streaming-fir nvdla spiflashread spiflashwrite fft 10 | 11 | spiflash.img: spiflash.py 12 | python3 $< 13 | 14 | .DEFAULT_GOAL := default 15 | 16 | .PHONY: default 17 | default: $(addsuffix .riscv,$(PROGRAMS)) spiflash.img 18 | 19 | .PHONY: dumps 20 | dumps: $(addsuffix .dump,$(PROGRAMS)) 21 | 22 | %.o: %.S 23 | $(GCC) $(CFLAGS) -D__ASSEMBLY__=1 -c $< -o $@ 24 | 25 | %.o: %.c mmio.h spiflash.h 26 | $(GCC) $(CFLAGS) -c $< -o $@ 27 | 28 | %.riscv: %.o $(libgloss) 29 | $(GCC) $(LDFLAGS) $< -o $@ 30 | 31 | %.dump: %.riscv 32 | $(OBJDUMP) -D $< > $@ 33 | 34 | 35 | .PHONY: clean 36 | clean: 37 | rm -f *.riscv *.o *.dump 38 | $(if $(libgloss),rm -rf $(libgloss_builddir)/) 39 | -------------------------------------------------------------------------------- /tests/accum.c: -------------------------------------------------------------------------------- 1 | #include "rocc.h" 2 | 3 | static inline void accum_write(int idx, unsigned long data) 4 | { 5 | ROCC_INSTRUCTION_SS(0, data, idx, 0); 6 | } 7 | 8 | static inline unsigned long accum_read(int idx) 9 | { 10 | unsigned long value; 11 | ROCC_INSTRUCTION_DSS(0, value, 0, idx, 1); 12 | return value; 13 | } 14 | 15 | static inline void accum_load(int idx, void *ptr) 16 | { 17 | asm volatile ("fence"); 18 | ROCC_INSTRUCTION_SS(0, (uintptr_t) ptr, idx, 2); 19 | } 20 | 21 | static inline void accum_add(int idx, unsigned long addend) 22 | { 23 | ROCC_INSTRUCTION_SS(0, addend, idx, 3); 24 | } 25 | 26 | unsigned long data = 0x3421L; 27 | 28 | int main(void) 29 | { 30 | unsigned long result; 31 | 32 | accum_load(0, &data); 33 | accum_add(0, 2); 34 | result = accum_read(0); 35 | 36 | if (result != data + 2) 37 | return 1; 38 | 39 | accum_write(0, 3); 40 | accum_add(0, 1); 41 | result = accum_read(0); 42 | 43 | if (result != 4) 44 | return 2; 45 | 46 | return 0; 47 | } 48 | -------------------------------------------------------------------------------- /tests/big-blkdev.c: -------------------------------------------------------------------------------- 1 | #include 2 | #include 3 | 4 | #include "mmio.h" 5 | #include "blkdev.h" 6 | 7 | #define SECTOR_WORDS (BLKDEV_SECTOR_SIZE / sizeof(uint64_t)) 8 | #define TEST_SECTORS 16 9 | 10 | unsigned long sector_buf[SECTOR_WORDS]; 11 | 12 | void write_sector(unsigned int secnum) 13 | { 14 | int req_tag, resp_tag; 15 | 16 | for (int i = 0; i < SECTOR_WORDS; i++) 17 | sector_buf[i] = (secnum << 6) | i; 18 | 19 | while (reg_read8(BLKDEV_NREQUEST) == 0); 20 | req_tag = blkdev_send_request((unsigned long) sector_buf, secnum, 1, 1); 21 | while (reg_read8(BLKDEV_NCOMPLETE) == 0); 22 | resp_tag = reg_read8(BLKDEV_COMPLETE); 23 | 24 | if (req_tag != resp_tag) { 25 | printf("Response tag %d does not match request tag %d\n", 26 | req_tag, resp_tag); 27 | exit(EXIT_FAILURE); 28 | } 29 | } 30 | 31 | void check_sector(unsigned int secnum) 32 | { 33 | int req_tag, resp_tag; 34 | 35 | while (reg_read8(BLKDEV_NREQUEST) == 0); 36 | req_tag = blkdev_send_request((unsigned long) sector_buf, secnum, 1, 0); 37 | while (reg_read8(BLKDEV_NCOMPLETE) == 0); 38 | resp_tag = reg_read8(BLKDEV_COMPLETE); 39 | 40 | if (req_tag != resp_tag) { 41 | printf("Response tag %d does not match request tag %d\n", 42 | req_tag, resp_tag); 43 | exit(EXIT_FAILURE); 44 | } 45 | 46 | for (int i = 0; i < SECTOR_WORDS; i++) { 47 | unsigned long expected = (secnum << 6) | i; 48 | unsigned long actual = sector_buf[i]; 49 | if (actual != expected) { 50 | printf("Word %d in sector %x does not match expected\n", 51 | i, secnum); 52 | printf("Expected %lx, got %lx\n", 53 | expected, actual); 54 | exit(EXIT_FAILURE); 55 | } 56 | } 57 | } 58 | 59 | int main(void) 60 | { 61 | unsigned int nsectors = blkdev_nsectors(); 62 | unsigned int stride = nsectors / TEST_SECTORS; 63 | 64 | printf("Writing %u of %u sectors\n", TEST_SECTORS, nsectors); 65 | 66 | for (int i = 0; i < TEST_SECTORS; i++) { 67 | int sector = i * stride; 68 | write_sector(sector); 69 | } 70 | 71 | printf("Checking sectors\n", nsectors); 72 | 73 | for (int i = 0; i < TEST_SECTORS; i++) { 74 | int sector = i * stride; 75 | check_sector(sector); 76 | } 77 | 78 | return 0; 79 | } 80 | -------------------------------------------------------------------------------- /tests/blkdev.h: -------------------------------------------------------------------------------- 1 | #define BLKDEV_BASE 0x10015000 2 | #define BLKDEV_ADDR BLKDEV_BASE 3 | #define BLKDEV_OFFSET (BLKDEV_BASE + 8) 4 | #define BLKDEV_LEN (BLKDEV_BASE + 12) 5 | #define BLKDEV_WRITE (BLKDEV_BASE + 16) 6 | #define BLKDEV_REQUEST (BLKDEV_BASE + 17) 7 | #define BLKDEV_NREQUEST (BLKDEV_BASE + 18) 8 | #define BLKDEV_COMPLETE (BLKDEV_BASE + 19) 9 | #define BLKDEV_NCOMPLETE (BLKDEV_BASE + 20) 10 | #define BLKDEV_NSECTORS (BLKDEV_BASE + 24) 11 | #define BLKDEV_MAX_REQUEST_LENGTH (BLKDEV_BASE + 28) 12 | #define BLKDEV_SECTOR_SIZE 512 13 | #define BLKDEV_SECTOR_SHIFT 9 14 | 15 | static inline size_t blkdev_nsectors(void) 16 | { 17 | return reg_read32(BLKDEV_NSECTORS); 18 | } 19 | 20 | static inline size_t blkdev_max_req_len(void) 21 | { 22 | return reg_read32(BLKDEV_MAX_REQUEST_LENGTH); 23 | } 24 | 25 | static inline unsigned int blkdev_send_request( 26 | unsigned long addr, 27 | unsigned int offset, 28 | unsigned int len, 29 | unsigned char write) 30 | { 31 | reg_write64(BLKDEV_ADDR, addr); 32 | reg_write32(BLKDEV_OFFSET, offset); 33 | reg_write32(BLKDEV_LEN, len); 34 | reg_write8(BLKDEV_WRITE, write); 35 | 36 | asm volatile ("fence"); 37 | return reg_read8(BLKDEV_REQUEST); 38 | } 39 | -------------------------------------------------------------------------------- /tests/charcount.c: -------------------------------------------------------------------------------- 1 | #include "rocc.h" 2 | 3 | char string[64] __attribute__ ((aligned (64))) = "The quick brown fox jumped over the lazy dog"; 4 | 5 | static inline unsigned long count_chars(char *start, char needle) 6 | { 7 | unsigned long count; 8 | asm volatile ("fence"); 9 | ROCC_INSTRUCTION_DSS(2, count, start, needle, 0); 10 | return count; 11 | } 12 | 13 | int main(void) 14 | { 15 | unsigned long count = count_chars(string + 14, 'o'); 16 | if (count != 3) 17 | return count + 1; 18 | return 0; 19 | } 20 | -------------------------------------------------------------------------------- /tests/fft.c: -------------------------------------------------------------------------------- 1 | /* This Test should be used with the fft generator config -- FFTRocketConfig. */ 2 | 3 | #include 4 | #include 5 | #include 6 | 7 | #define FFT_WRITE_LANE 0x2000 8 | #define FFT_RD_LANE_BASE 0x2008 9 | // addr of read lane i is FFT_RD_LANE_BASE + i * 8 10 | 11 | // from generators/fft-generator/test_pts.py (in the fft-generator repo) 12 | // point size (and therefore integer width/uint32_t) determined by IOWidth from Tail.scala 13 | // point size is 2 * IOWidth since both real and imaginary components get IOWidth bits 14 | const uint32_t points[8] = { 15 | 0b00000000101101011111111101001011, // 00B5FF4B 16 | 0b00000000000000001111111100000000, // 0000FF00 17 | 0b11111111010010111111111101001011, // FF4BFF4B 18 | 0b11111111000000000000000000000000, // FF000000 19 | 0b11111111010010110000000010110101, // FF4B00B5 20 | 0b00000000000000000000000100000000, // 00000100 21 | 0b00000000101101010000000010110101, // 00B500B5 22 | 0b00000001000000000000000000000000 // 01000000 23 | }; 24 | 25 | const uint32_t expected_outputs[8] = { 26 | 0x00000000, // read 0 27 | 0x00000000, // read 1 28 | 0x00000000, // read 2 29 | 0xffff0000, // read 3 -- real portion is 0xff (very small negative number) 30 | 0x00000000, // read 4 31 | 0x00000000, // read 5 32 | 0x00000000, // read 6 33 | 0x05a8fa57, // read 7 -- real: ~5.656 imaginary: ~-5.656 34 | }; 35 | 36 | int main(void) { 37 | int num_points = 8; 38 | 39 | // write points to fft 40 | for (int i = 0; i < num_points; i++) { 41 | uint32_t write_val = points[i]; 42 | volatile uint32_t* ptr = (volatile uint32_t*) FFT_WRITE_LANE; 43 | *ptr = write_val; 44 | } 45 | 46 | for (int i = 0; i < num_points; i++) { 47 | volatile uint32_t* ptr_0 = (volatile uint32_t*) (FFT_RD_LANE_BASE + (i * 8)); 48 | uint32_t read_val = *ptr_0; 49 | 50 | /* To convert binary to floating point 51 | * However, RISC-V compiler can't print floats. You can use this by copy-pasting it into an online 52 | * C compiler. The printf at the bottom of this for loop will print out the values of real_part_bin 53 | * and imag_part_bin 54 | * 55 | * Code is commented out because default risc-v compiler doesn't support pow 56 | */ 57 | // uint16_t real_part_bin = read_val >> 16; 58 | // uint16_t imag_part_bin = read_val & 0xFFFF; 59 | // int bp = 8; // from tail.scala 60 | // float real_comp = ((int16_t) real_part_bin) * pow(2, bp); 61 | // float imag_comp = ((int16_t) imag_part_bin) * pow(2, bp); 62 | 63 | if (read_val != expected_outputs[i]) { 64 | printf("FAIL: Expected and real differed: %x %x", read_val, expected_outputs[i]); 65 | return -1; 66 | } 67 | } 68 | 69 | printf("PASS: FFT Test Passed\n"); 70 | return 0; 71 | } -------------------------------------------------------------------------------- /tests/gcd.c: -------------------------------------------------------------------------------- 1 | #include "mmio.h" 2 | 3 | #define GCD_STATUS 0x2000 4 | #define GCD_X 0x2004 5 | #define GCD_Y 0x2008 6 | #define GCD_GCD 0x200C 7 | 8 | unsigned int gcd_ref(unsigned int x, unsigned int y) { 9 | while (y != 0) { 10 | if (x > y) 11 | x = x - y; 12 | else 13 | y = y - x; 14 | } 15 | return x; 16 | } 17 | 18 | // DOC include start: GCD test 19 | int main(void) 20 | { 21 | uint32_t result, ref, x = 20, y = 15; 22 | 23 | // wait for peripheral to be ready 24 | while ((reg_read8(GCD_STATUS) & 0x2) == 0) ; 25 | 26 | reg_write32(GCD_X, x); 27 | reg_write32(GCD_Y, y); 28 | 29 | 30 | // wait for peripheral to complete 31 | while ((reg_read8(GCD_STATUS) & 0x1) == 0) ; 32 | 33 | result = reg_read32(GCD_GCD); 34 | ref = gcd_ref(x, y); 35 | 36 | if (result != ref) { 37 | printf("Hardware result %d does not match reference value %d\n", result, ref); 38 | return 1; 39 | } 40 | return 0; 41 | } 42 | // DOC include end: GCD test 43 | -------------------------------------------------------------------------------- /tests/htif.ld: -------------------------------------------------------------------------------- 1 | ../toolchains/libgloss/util/htif.ld -------------------------------------------------------------------------------- /tests/libgloss.mk: -------------------------------------------------------------------------------- 1 | # Handle libgloss-htif dependency 2 | ifndef libgloss 3 | 4 | ifndef GCC 5 | $(error GCC is not defined) 6 | endif 7 | 8 | libgloss_specs := htif_nano.specs 9 | 10 | # Test whether libgloss-htif is globally installed and usable 11 | # Define BUILD_LIBGLOSS=1 to unconditionally force a local build 12 | BUILD_LIBGLOSS ?= $(shell { echo 'int main(void) { return 0; }' | \ 13 | $(GCC) -xc -specs=$(libgloss_specs) -o /dev/null - 2> /dev/null ; } || \ 14 | echo "$$?") 15 | 16 | ifneq ($(BUILD_LIBGLOSS),) 17 | $(info libgloss-htif: Using local build) 18 | 19 | libgloss_srcdir := ../toolchains/libgloss 20 | libgloss_builddir := libgloss 21 | libgloss_specs := $(libgloss_srcdir)/util/$(libgloss_specs) 22 | libgloss_lib := $(libgloss_builddir)/libgloss_htif.a 23 | libgloss := $(libgloss_lib) $(libgloss_specs) htif.ld 24 | 25 | LDFLAGS += -L libgloss 26 | 27 | $(libgloss_builddir)/Makefile: $(libgloss_srcdir)/configure 28 | mkdir -p $(dir $@) 29 | cd $(dir $@) && $(realpath $<) \ 30 | --prefix=$(shell $(GCC) -print-sysroot) \ 31 | --host=$(TARGET) \ 32 | --disable-multilib 33 | 34 | $(libgloss_lib): $(libgloss_builddir)/Makefile 35 | $(MAKE) -C $(dir $^) 36 | 37 | .PHONY: libgloss 38 | libgloss: $(libgloss) 39 | 40 | else 41 | 42 | $(info libgloss-htif: Using global install) 43 | libgloss := # No additional prerequisites 44 | 45 | endif 46 | 47 | CFLAGS += -specs=$(libgloss_specs) 48 | LDFLAGS += -specs=$(libgloss_specs) 49 | 50 | endif # libgloss 51 | -------------------------------------------------------------------------------- /tests/mmio.h: -------------------------------------------------------------------------------- 1 | #ifndef __MMIO_H__ 2 | #define __MMIO_H__ 3 | 4 | #include 5 | 6 | static inline void reg_write8(uintptr_t addr, uint8_t data) 7 | { 8 | volatile uint8_t *ptr = (volatile uint8_t *) addr; 9 | *ptr = data; 10 | } 11 | 12 | static inline uint8_t reg_read8(uintptr_t addr) 13 | { 14 | volatile uint8_t *ptr = (volatile uint8_t *) addr; 15 | return *ptr; 16 | } 17 | 18 | static inline void reg_write16(uintptr_t addr, uint16_t data) 19 | { 20 | volatile uint16_t *ptr = (volatile uint16_t *) addr; 21 | *ptr = data; 22 | } 23 | 24 | static inline uint16_t reg_read16(uintptr_t addr) 25 | { 26 | volatile uint16_t *ptr = (volatile uint16_t *) addr; 27 | return *ptr; 28 | } 29 | 30 | static inline void reg_write32(uintptr_t addr, uint32_t data) 31 | { 32 | volatile uint32_t *ptr = (volatile uint32_t *) addr; 33 | *ptr = data; 34 | } 35 | 36 | static inline uint32_t reg_read32(uintptr_t addr) 37 | { 38 | volatile uint32_t *ptr = (volatile uint32_t *) addr; 39 | return *ptr; 40 | } 41 | 42 | static inline void reg_write64(unsigned long addr, uint64_t data) 43 | { 44 | volatile uint64_t *ptr = (volatile uint64_t *) addr; 45 | *ptr = data; 46 | } 47 | 48 | static inline uint64_t reg_read64(unsigned long addr) 49 | { 50 | volatile uint64_t *ptr = (volatile uint64_t *) addr; 51 | return *ptr; 52 | } 53 | 54 | #endif 55 | -------------------------------------------------------------------------------- /tests/nic-loopback.c: -------------------------------------------------------------------------------- 1 | #include "mmio.h" 2 | #include 3 | #include 4 | #include 5 | 6 | #include 7 | #include "nic.h" 8 | 9 | #define NPACKETS 10 10 | #define TEST_OFFSET 3 11 | #define TEST_LEN 356 12 | #define ARRAY_LEN 360 13 | #define NTRIALS 3 14 | 15 | uint32_t src[NPACKETS][ARRAY_LEN]; 16 | uint32_t dst[NPACKETS][ARRAY_LEN]; 17 | uint64_t lengths[NPACKETS]; 18 | 19 | static inline void send_recv() 20 | { 21 | uint64_t send_packet, recv_addr; 22 | int ncomps, send_comps_left = NPACKETS, recv_comps_left = NPACKETS; 23 | int recv_idx = 0; 24 | 25 | for (int i = 0; i < NPACKETS; i++) { 26 | uint64_t pkt_size = TEST_LEN * sizeof(uint32_t); 27 | uint64_t src_addr = (uint64_t) &src[i][TEST_OFFSET]; 28 | send_packet = (pkt_size << 48) | src_addr; 29 | recv_addr = (uint64_t) dst[i]; 30 | reg_write64(SIMPLENIC_SEND_REQ, send_packet); 31 | reg_write64(SIMPLENIC_RECV_REQ, recv_addr); 32 | } 33 | 34 | while (send_comps_left > 0 || recv_comps_left > 0) { 35 | ncomps = nic_send_comp_avail(); 36 | asm volatile ("fence"); 37 | for (int i = 0; i < ncomps; i++) 38 | reg_read16(SIMPLENIC_SEND_COMP); 39 | send_comps_left -= ncomps; 40 | 41 | ncomps = nic_recv_comp_avail(); 42 | asm volatile ("fence"); 43 | for (int i = 0; i < ncomps; i++) { 44 | lengths[recv_idx] = reg_read16(SIMPLENIC_RECV_COMP); 45 | recv_idx++; 46 | } 47 | recv_comps_left -= ncomps; 48 | } 49 | } 50 | 51 | void run_test(void) 52 | { 53 | unsigned long start, end; 54 | int i, j; 55 | 56 | memset(dst, 0, sizeof(dst)); 57 | asm volatile ("fence"); 58 | 59 | start = rdcycle(); 60 | send_recv(); 61 | end = rdcycle(); 62 | 63 | printf("send/recv %lu cycles\n", end - start); 64 | 65 | for (i = 0; i < NPACKETS; i++) { 66 | if (lengths[i] != TEST_LEN * sizeof(uint32_t)) { 67 | printf("recv got wrong # bytes\n"); 68 | exit(EXIT_FAILURE); 69 | } 70 | 71 | for (j = 0; j < TEST_LEN; j++) { 72 | if (dst[i][j] != src[i][j + TEST_OFFSET]) { 73 | printf("Data mismatch @ %d, %d: %x != %x\n", 74 | i, j, dst[i][j], src[i][j + TEST_OFFSET]); 75 | exit(EXIT_FAILURE); 76 | } 77 | } 78 | } 79 | } 80 | 81 | int main(void) 82 | { 83 | int i, j; 84 | 85 | for (i = 0; i < NPACKETS; i++) { 86 | for (j = 0; j < ARRAY_LEN; j++) 87 | src[i][j] = i * ARRAY_LEN + j; 88 | } 89 | 90 | for (i = 0; i < NTRIALS; i++) { 91 | printf("Trial %d\n", i); 92 | run_test(); 93 | } 94 | 95 | printf("All correct\n"); 96 | 97 | return 0; 98 | } 99 | -------------------------------------------------------------------------------- /tests/nic.h: -------------------------------------------------------------------------------- 1 | #define SIMPLENIC_BASE 0x10016000L 2 | #define SIMPLENIC_SEND_REQ (SIMPLENIC_BASE + 0) 3 | #define SIMPLENIC_RECV_REQ (SIMPLENIC_BASE + 8) 4 | #define SIMPLENIC_SEND_COMP (SIMPLENIC_BASE + 16) 5 | #define SIMPLENIC_RECV_COMP (SIMPLENIC_BASE + 18) 6 | #define SIMPLENIC_COUNTS (SIMPLENIC_BASE + 20) 7 | #define SIMPLENIC_MACADDR (SIMPLENIC_BASE + 24) 8 | 9 | static inline int nic_send_req_avail(void) 10 | { 11 | return reg_read32(SIMPLENIC_COUNTS) & 0xff; 12 | } 13 | 14 | static inline int nic_recv_req_avail(void) 15 | { 16 | return (reg_read32(SIMPLENIC_COUNTS) >> 8) & 0xff; 17 | } 18 | 19 | static inline int nic_send_comp_avail(void) 20 | { 21 | return (reg_read32(SIMPLENIC_COUNTS) >> 16) & 0xff; 22 | } 23 | 24 | static inline int nic_recv_comp_avail(void) 25 | { 26 | return (reg_read32(SIMPLENIC_COUNTS) >> 24) & 0xff; 27 | } 28 | 29 | static void nic_send(void *data, unsigned long len) 30 | { 31 | uintptr_t addr = ((uintptr_t) data) & ((1L << 48) - 1); 32 | unsigned long packet = (len << 48) | addr; 33 | 34 | while (nic_send_req_avail() == 0); 35 | reg_write64(SIMPLENIC_SEND_REQ, packet); 36 | 37 | while (nic_send_comp_avail() == 0); 38 | reg_read16(SIMPLENIC_SEND_COMP); 39 | } 40 | 41 | static int nic_recv(void *dest) 42 | { 43 | uintptr_t addr = (uintptr_t) dest; 44 | int len; 45 | 46 | while (nic_recv_req_avail() == 0); 47 | reg_write64(SIMPLENIC_RECV_REQ, addr); 48 | 49 | // Poll for completion 50 | while (nic_recv_comp_avail() == 0); 51 | len = reg_read16(SIMPLENIC_RECV_COMP); 52 | asm volatile ("fence"); 53 | 54 | return len; 55 | } 56 | 57 | static inline uint64_t nic_macaddr(void) 58 | { 59 | return reg_read64(SIMPLENIC_MACADDR); 60 | } 61 | -------------------------------------------------------------------------------- /tests/pwm.c: -------------------------------------------------------------------------------- 1 | #define PWM_PERIOD 0x2000 2 | #define PWM_DUTY 0x2004 3 | #define PWM_ENABLE 0x2008 4 | 5 | #include "mmio.h" 6 | 7 | int main(void) 8 | { 9 | reg_write32(PWM_PERIOD, 20); 10 | reg_write32(PWM_DUTY, 5); 11 | reg_write32(PWM_ENABLE, 1); 12 | 13 | return 0; 14 | } 15 | -------------------------------------------------------------------------------- /tests/spiflash.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env python3 2 | 3 | # Generates a binary file that the SPI test uses 4 | 5 | outfile = "spiflash.img" 6 | 7 | with open(outfile, 'wb') as f: 8 | for i in range(0,0x100000,4): 9 | check = 0xdeadbeef - i 10 | f.write(check.to_bytes(4,'little')) 11 | 12 | -------------------------------------------------------------------------------- /tests/spiflashwrite.c: -------------------------------------------------------------------------------- 1 | #include 2 | #include 3 | 4 | #include "mmio.h" 5 | #include "spiflash.h" 6 | 7 | int main(void) 8 | { 9 | spiflash_ffmt ffmt; 10 | ffmt.fields.cmd_en = 1; 11 | ffmt.fields.addr_len = 4; // Valid options are 3 or 4 for our model 12 | ffmt.fields.pad_cnt = 0; // Our SPI flash model assumes 8 dummy cycles for fast reads, 0 for slow 13 | ffmt.fields.cmd_proto = SPIFLASH_PROTO_SINGLE; // Our SPI flash model only supports single-bit commands 14 | ffmt.fields.addr_proto = SPIFLASH_PROTO_SINGLE; // We support both single and quad 15 | ffmt.fields.data_proto = SPIFLASH_PROTO_SINGLE; // We support both single and quad 16 | ffmt.fields.cmd_code = 0x13; // Slow read 4 byte 17 | ffmt.fields.pad_code = 0x00; // Not used by our model 18 | 19 | // Test that we can read 20 | printf("Testing SPI flash command 0x13...\n"); 21 | configure_spiflash(ffmt); 22 | if (test_spiflash(0x0, 0x100, 0)) return 1; 23 | 24 | // 0x02: 3 byte addr, single/single 25 | printf("Testing SPI flash command 0x02...\n"); 26 | write_spiflash(test_data, test_len, 0x200, 0x02, 3, SPIFLASH_PROTO_SINGLE, SPIFLASH_PROTO_SINGLE); 27 | if (check_write(test_data, test_len, 0x200)) return 1; 28 | 29 | // 0x32: 3 byte addr, single/quad 30 | printf("Testing SPI flash command 0x32...\n"); 31 | write_spiflash(test_data, test_len, 0x300, 0x32, 3, SPIFLASH_PROTO_SINGLE, SPIFLASH_PROTO_QUAD); 32 | if (check_write(test_data, test_len, 0x300)) return 1; 33 | 34 | // 0x38: 3 byte addr, quad/quad 35 | printf("Testing SPI flash command 0x38...\n"); 36 | write_spiflash(test_data, test_len, 0x400, 0x38, 3, SPIFLASH_PROTO_QUAD, SPIFLASH_PROTO_QUAD); 37 | if (check_write(test_data, test_len, 0x400)) return 1; 38 | 39 | // 0x12: 4 byte addr, single/single 40 | printf("Testing SPI flash command 0x12...\n"); 41 | write_spiflash(test_data, test_len, 0x500, 0x12, 4, SPIFLASH_PROTO_SINGLE, SPIFLASH_PROTO_SINGLE); 42 | if (check_write(test_data, test_len, 0x500)) return 1; 43 | 44 | // 0x34: 4 byte addr, single/quad 45 | printf("Testing SPI flash command 0x34...\n"); 46 | write_spiflash(test_data, test_len, 0x600, 0x34, 4, SPIFLASH_PROTO_SINGLE, SPIFLASH_PROTO_QUAD); 47 | if (check_write(test_data, test_len, 0x600)) return 1; 48 | 49 | // 0x3E: 4 byte addr, quad/quad 50 | printf("Testing SPI flash command 0x3E...\n"); 51 | write_spiflash(test_data, test_len, 0x700, 0x3E, 4, SPIFLASH_PROTO_QUAD, SPIFLASH_PROTO_QUAD); 52 | if (check_write(test_data, test_len, 0x700)) return 1; 53 | 54 | return 0; 55 | } 56 | -------------------------------------------------------------------------------- /tests/streaming-fir.c: -------------------------------------------------------------------------------- 1 | #define PASSTHROUGH_WRITE 0x2000 2 | #define PASSTHROUGH_WRITE_COUNT 0x2008 3 | #define PASSTHROUGH_READ 0x2100 4 | #define PASSTHROUGH_READ_COUNT 0x2108 5 | 6 | #define BP 3 7 | #define BP_SCALE ((double)(1 << BP)) 8 | 9 | #include "mmio.h" 10 | 11 | #include 12 | #include 13 | #include 14 | #include 15 | 16 | uint64_t roundi(double x) 17 | { 18 | if (x < 0.0) { 19 | return (uint64_t)(x - 0.5); 20 | } else { 21 | return (uint64_t)(x + 0.5); 22 | } 23 | } 24 | 25 | int main(void) 26 | { 27 | double test_vector[15] = {1.0, 2.0, 3.0, 4.0, 5.0, 4.0, 3.0, 2.0, 1.0, 0.5, 0.25, 0.125, 0.125}; 28 | uint32_t num_tests = sizeof(test_vector) / sizeof(double); 29 | printf("Starting writing %d inputs\n", num_tests); 30 | 31 | for (int i = 0; i < num_tests; i++) { 32 | reg_write64(PASSTHROUGH_WRITE, roundi(test_vector[i] * BP_SCALE)); 33 | } 34 | 35 | printf("Done writing\n"); 36 | uint32_t rcnt = reg_read32(PASSTHROUGH_READ_COUNT); 37 | printf("Write count: %d\n", reg_read32(PASSTHROUGH_WRITE_COUNT)); 38 | printf("Read count: %d\n", rcnt); 39 | 40 | int failed = 0; 41 | if (rcnt != 0) { 42 | for (int i = 0; i < num_tests - 3; i++) { 43 | uint32_t res = reg_read32(PASSTHROUGH_READ); 44 | // double res = ((double)reg_read32(PASSTHROUGH_READ)) / BP_SCALE; 45 | double expected_double = 3*test_vector[i] + 2*test_vector[i+1] + test_vector[i+2]; 46 | uint32_t expected = ((uint32_t)(expected_double * BP_SCALE + 0.5)) & 0xFF; 47 | if (res == expected) { 48 | printf("\n\nPass: Got %u Expected %u\n\n", res, expected); 49 | } else { 50 | failed = 1; 51 | printf("\n\nFail: Got %u Expected %u\n\n", res, expected); 52 | } 53 | } 54 | } else { 55 | failed = 1; 56 | } 57 | 58 | if (failed) { 59 | printf("\n\nSome tests failed\n\n"); 60 | } else { 61 | printf("\n\nAll tests passed\n\n"); 62 | } 63 | 64 | return 0; 65 | } 66 | -------------------------------------------------------------------------------- /tests/streaming-passthrough.c: -------------------------------------------------------------------------------- 1 | #define PASSTHROUGH_WRITE 0x2000 2 | #define PASSTHROUGH_WRITE_COUNT 0x2008 3 | #define PASSTHROUGH_READ 0x2100 4 | #define PASSTHROUGH_READ_COUNT 0x2108 5 | 6 | #include "mmio.h" 7 | 8 | #include 9 | #include 10 | #include 11 | #include 12 | 13 | int main(void) 14 | { 15 | printf("Starting writing\n"); 16 | uint32_t test_vector[7] = {3, 2, 1, 0, -1, -2, -3} ; 17 | for (int i = 0; i < 7; i++) { 18 | reg_write64(PASSTHROUGH_WRITE, test_vector[i]); 19 | } 20 | 21 | printf("Done writing\n"); 22 | uint32_t rcnt = reg_read32(PASSTHROUGH_READ_COUNT); 23 | printf("Write count: %d\n", reg_read32(PASSTHROUGH_WRITE_COUNT)); 24 | printf("Read count: %d\n", rcnt); 25 | 26 | int failed = 0; 27 | if (rcnt != 0) { 28 | for (int i = 0; i < 7; i++) { 29 | uint32_t res = reg_read32(PASSTHROUGH_READ); 30 | uint32_t expected = test_vector[i]; 31 | if (res == expected) { 32 | printf("\n\nPass: Got %d Expected %d\n\n", res, test_vector[i]); 33 | } else { 34 | failed = 1; 35 | printf("\n\nFail: Got %d Expected %d\n\n", res, test_vector[i]); 36 | } 37 | } 38 | } else { 39 | failed = 1; 40 | } 41 | 42 | if (failed) { 43 | printf("\n\nSome tests failed\n\n"); 44 | } else { 45 | printf("\n\nAll tests passed\n\n"); 46 | } 47 | 48 | return 0; 49 | } 50 | -------------------------------------------------------------------------------- /tools/dromajo/dromajo.mk: -------------------------------------------------------------------------------- 1 | ############################################################## 2 | # extra variables/targets ingested by the chipyard make system 3 | ############################################################## 4 | 5 | DROMAJO_DIR = $(base_dir)/tools/dromajo/dromajo-src/src 6 | DROMAJO_LIB_NAME = dromajo_cosim 7 | DROMAJO_LIB = $(DROMAJO_DIR)/lib$(DROMAJO_LIB_NAME).a 8 | 9 | # Dromajo assumes using the default bootrom 10 | DROMAJO_ROM = $(base_dir)/bootrom/bootrom.rv64.img 11 | 12 | DTS_FILE = $(build_dir)/$(long_name).dts 13 | DROMAJO_DTB = $(build_dir)/$(long_name).dtb 14 | 15 | $(DTS_FILE): $(FIRRTL_FILE) 16 | 17 | $(DROMAJO_DTB): $(DTS_FILE) 18 | dtc -I dts -O dtb -o $(DROMAJO_DTB) $(DTS_FILE) 19 | 20 | DROMAJO_SRCS = $(call lookup_srcs,$(DROMAJO_DIR),cc) $(call lookup_srcs,$(DROMAJO_DIR),h) 21 | 22 | $(DROMAJO_LIB): $(DROMAJO_SRCS) 23 | $(MAKE) -C $(DROMAJO_DIR) 24 | 25 | # depending on where the simulation is done, use the auto-variable or the hardcoded defined one 26 | ifeq ($(BINARY),) 27 | DROMAJO_BIN = $(<) 28 | else 29 | DROMAJO_BIN = $(BINARY) 30 | endif 31 | 32 | DROMAJO_FLAGS = +drj_dtb=$(DROMAJO_DTB) +drj_rom=$(DROMAJO_ROM) +drj_bin=$(DROMAJO_BIN) 33 | 34 | DROMAJO_PARAMS_FILE = $(build_dir)/$(long_name).dromajo_params.h 35 | DROMAJO_PARAMS_SYMLINK = $(build_dir)/dromajo_params.h 36 | 37 | $(DROMAJO_PARAMS_FILE): $(FIRRTL_FILE) 38 | 39 | $(DROMAJO_PARAMS_SYMLINK): $(DROMAJO_PARAMS_FILE) 40 | rm -rf $(DROMAJO_PARAMS_SYMLINK) 41 | ln -s $(DROMAJO_PARAMS_FILE) $(DROMAJO_PARAMS_SYMLINK) 42 | 43 | ################################################################## 44 | # THE FOLLOWING MUST BE += operators 45 | ################################################################## 46 | 47 | # simargs needed (i.e. like +drj_test=hello) 48 | ifdef ENABLE_DROMAJO 49 | EXTRA_SIM_FLAGS += $(DROMAJO_FLAGS) 50 | 51 | # CC flags needed for all simulations 52 | EXTRA_SIM_CXXFLAGS += -I$(DROMAJO_DIR) 53 | 54 | # sourced needed for simulation 55 | EXTRA_SIM_SOURCES += $(DROMAJO_LIB) 56 | 57 | # requirements needed for simulation 58 | EXTRA_SIM_REQS += $(DROMAJO_PARAMS_SYMLINK) $(DROMAJO_LIB) $(DROMAJO_DTB) 59 | endif 60 | -------------------------------------------------------------------------------- /tools/torture.mk: -------------------------------------------------------------------------------- 1 | HELP_COMMANDS += \ 2 | " torture = run torture on the RTL testbench" \ 3 | " torture-overnight = run torture overnight tests (set TORTURE_ONIGHT_OPTIONS to pass test options)" 4 | 5 | ######################################################################################### 6 | # run torture rules 7 | ######################################################################################### 8 | .PHONY: torture torture-overnight 9 | 10 | torture: $(output_dir) $(sim) 11 | $(MAKE) -C $(base_dir)/tools/torture/output clean 12 | $(MAKE) -C $(base_dir)/tools/torture R_SIM=$(sim) gen rtest 13 | cp -r $(base_dir)/tools/torture/output $(output_dir)/torture 14 | rm $(output_dir)/torture/Makefile 15 | 16 | TORTURE_ONIGHT_OPTIONS := 17 | torture-overnight: $(output_dir) $(sim) 18 | $(MAKE) -C $(base_dir)/tools/torture R_SIM=$(sim) OPTIONS="$(TORTURE_ONIGHT_OPTIONS)" rnight 19 | -------------------------------------------------------------------------------- /vcs.mk: -------------------------------------------------------------------------------- 1 | HELP_COMPILATION_VARIABLES += \ 2 | " USE_FSDB = set to '1' to build VCS simulator to emit FSDB instead of VPD." 3 | 4 | HELP_SIMULATION_VARIABLES += \ 5 | " USE_FSDB = set to '1' to run VCS simulator emitting FSDB instead of VPD." 6 | 7 | ifdef USE_FSDB 8 | WAVEFORM_FLAG=+fsdbfile=$(sim_out_name).fsdb 9 | else 10 | WAVEFORM_FLAG=+vcdplusfile=$(sim_out_name).vpd 11 | endif 12 | 13 | # If ntb_random_seed unspecified, vcs uses 1 as constant seed. 14 | # Set ntb_random_seed_automatic to actually get a random seed 15 | ifdef RANDOM_SEED 16 | SEED_FLAG=+ntb_random_seed=$(RANDOM_SEED) 17 | else 18 | SEED_FLAG=+ntb_random_seed_automatic 19 | endif 20 | 21 | CLOCK_PERIOD ?= 1.0 22 | RESET_DELAY ?= 777.7 23 | 24 | #---------------------------------------------------------------------------------------- 25 | # gcc configuration/optimization 26 | #---------------------------------------------------------------------------------------- 27 | include $(base_dir)/sims/common-sim-flags.mk 28 | 29 | VCS_CXXFLAGS = $(SIM_CXXFLAGS) 30 | VCS_LDFLAGS = $(SIM_LDFLAGS) 31 | 32 | # vcs requires LDFLAGS to not include library names (i.e. -l needs to be separate) 33 | VCS_CC_OPTS = \ 34 | -CFLAGS "$(VCS_CXXFLAGS)" \ 35 | -LDFLAGS "$(filter-out -l%,$(VCS_LDFLAGS))" \ 36 | $(filter -l%,$(VCS_LDFLAGS)) 37 | 38 | VCS_NONCC_OPTS = \ 39 | -notice \ 40 | -line \ 41 | +lint=all,noVCDE,noONGS,noUI \ 42 | -error=PCWM-L \ 43 | -error=noZMMCM \ 44 | -timescale=1ns/10ps \ 45 | -quiet \ 46 | -q \ 47 | +rad \ 48 | +vcs+lic+wait \ 49 | +vc+list \ 50 | -f $(sim_common_files) \ 51 | -sverilog +systemverilogext+.sv+.svi+.svh+.svt -assert svaext +libext+.sv \ 52 | +v2k +verilog2001ext+.v95+.vt+.vp +libext+.v \ 53 | -debug_pp \ 54 | +incdir+$(build_dir) \ 55 | $(sim_vsrcs) 56 | 57 | PREPROC_DEFINES = \ 58 | +define+VCS \ 59 | +define+CLOCK_PERIOD=$(CLOCK_PERIOD) \ 60 | +define+RESET_DELAY=$(RESET_DELAY) \ 61 | +define+PRINTF_COND=$(TB).printf_cond \ 62 | +define+STOP_COND=!$(TB).reset \ 63 | +define+MODEL=$(MODEL) \ 64 | +define+RANDOMIZE_MEM_INIT \ 65 | +define+RANDOMIZE_REG_INIT \ 66 | +define+RANDOMIZE_GARBAGE_ASSIGN \ 67 | +define+RANDOMIZE_INVALID_ASSIGN 68 | 69 | ifdef USE_FSDB 70 | PREPROC_DEFINES += +define+FSDB 71 | endif 72 | -------------------------------------------------------------------------------- /vlsi/.gitignore: -------------------------------------------------------------------------------- 1 | inputs.yml 2 | __pycache__ 3 | hammer*.log 4 | build 5 | src/test/output-*.json 6 | generated-src 7 | output.json 8 | -------------------------------------------------------------------------------- /vlsi/env.yml: -------------------------------------------------------------------------------- 1 | # Base path to where Mentor tools are installed 2 | mentor.mentor_home: "" 3 | # Mentor license server/file 4 | mentor.MGLS_LICENSE_FILE: "" 5 | # Base path to where Cadence tools are installed 6 | cadence.cadence_home: "" 7 | # Cadence license server/file 8 | cadence.CDS_LIC_FILE: "" 9 | # Base path to where Synopsys tools are installed 10 | synopsys.synopsys_home: "" 11 | # Synopsys license server/files 12 | synopsys.SNPSLMD_LICENSE_FILE: "" 13 | synopsys.MGLS_LICENSE_FILE: "" 14 | -------------------------------------------------------------------------------- /vlsi/example-design.yml: -------------------------------------------------------------------------------- 1 | # General Hammer Inputs Related to the Design and Build System 2 | 3 | # Generate Make include to aid in flow 4 | vlsi.core.build_system: make 5 | vlsi.core.max_threads: 12 6 | 7 | # Hammer will auto-generate a CPF for simple power designs; see hammer/src/hammer-vlsi/defaults.yml for more info 8 | vlsi.inputs.power_spec_mode: "auto" 9 | vlsi.inputs.power_spec_type: "cpf" 10 | 11 | # Specify clock signals 12 | vlsi.inputs.clocks: [ 13 | {name: "clock_clock", period: "2ns", uncertainty: "0.1ns"} 14 | ] 15 | 16 | # Specify pin properties 17 | # Default pin placement can be set by the tool 18 | # Default pin layer assignments can be found in some tech plug-ins 19 | vlsi.inputs.pin_mode: generated 20 | vlsi.inputs.pin.generate_mode: semi_auto 21 | 22 | # Specify the floorplan 23 | # Default floor plan can be set by the tool 24 | # The path name should match the VLSI_TOP makefile parameter if it is set 25 | par.innovus.floorplan_mode: "auto" 26 | vlsi.inputs.placement_constraints: 27 | - path: "ChipTop" 28 | type: toplevel 29 | x: 0 30 | y: 0 31 | width: 300 32 | height: 300 33 | margins: 34 | left: 0 35 | right: 0 36 | top: 0 37 | bottom: 0 38 | -------------------------------------------------------------------------------- /vlsi/example-nangate45.yml: -------------------------------------------------------------------------------- 1 | #---------------------- 2 | # Technology Setup 3 | #---------------------- 4 | 5 | vlsi.core.technology: nangate45 6 | 7 | # the nangate45.tech.json can't reference the $OPENROAD environment variable, 8 | # so we need to set the install dir here. 9 | # TODO: figure out how to remove this, or override it within OpenROADTool 10 | technology.nangate45.install_dir: "/k/work/OpenROAD-flow/tools/OpenROAD" 11 | 12 | vlsi.core.max_threads: 12 13 | 14 | #---------------------- 15 | # General Hammer Inputs 16 | #---------------------- 17 | 18 | # Hammer will auto-generate a CPF for simple power designs; 19 | # see hammer/src/hammer-vlsi/defaults.yml for more info 20 | vlsi.inputs.power_spec_mode: "auto" 21 | vlsi.inputs.power_spec_type: "cpf" 22 | 23 | # Specify clock signals 24 | vlsi.inputs.clocks: [ 25 | {name: "clock_clock", period: "5ns", uncertainty: "0.5ns"} 26 | ] 27 | 28 | # Generate Make include to aid in flow 29 | vlsi.core.build_system: make 30 | 31 | #---------------------- 32 | # Placement Constraints 33 | #---------------------- 34 | 35 | # For nangate45, size should be multiple of (0.19,1.4) placement grid 36 | vlsi.inputs.placement_constraints: 37 | - path: "ChipTop" 38 | type: toplevel 39 | x: 0 40 | y: 0 41 | width: 3334.72 42 | height: 3798.2 43 | margins: 44 | left: 0 45 | right: 0 46 | top: 0 47 | bottom: 0 48 | 49 | # SRAM Compiler compiler options 50 | vlsi.core.sram_generator_tool: "sram_compiler" 51 | ## You should specify a location for the SRAM generator in the tech plugin 52 | vlsi.core.sram_generator_tool_path: [ 53 | "hammer/src/hammer-vlsi/technology/nangate45"] 54 | vlsi.core.sram_generator_tool_path_meta: "append" 55 | 56 | #---------------------- 57 | # Tool options. Replace with your tool plugin of choice. 58 | #---------------------- 59 | 60 | # OpenROAD-yosys options 61 | vlsi.core.synthesis_tool: "yosys" 62 | vlsi.core.synthesis_tool_path: ["hammer/src/hammer-vlsi/synthesis/yosys"] 63 | vlsi.core.synthesis_tool_path_meta: "append" 64 | 65 | # OpenROAD-par options 66 | vlsi.core.par_tool: "openroad" 67 | vlsi.core.par_tool_path: ["hammer/src/hammer-vlsi/par"] 68 | vlsi.core.par_tool_path_meta: "append" 69 | 70 | # OpenROAD-drc options (no lvs) 71 | vlsi.core.drc_tool: "openroad" 72 | vlsi.core.drc_tool_path: ["hammer/src/hammer-vlsi/drc"] 73 | vlsi.core.drc_tool_path_meta: "append" 74 | -------------------------------------------------------------------------------- /vlsi/example-tech.yml: -------------------------------------------------------------------------------- 1 | # Technology Setup 2 | vlsi.core.technology: 3 | vlsi.core.technology_path: ["hammer--plugin"] 4 | vlsi.core.technology_path_meta: append 5 | 6 | # technology files installation directory 7 | technology..install_dir: "" 8 | -------------------------------------------------------------------------------- /vlsi/example-tools.yml: -------------------------------------------------------------------------------- 1 | # SRAM Compiler compiler options 2 | vlsi.core.sram_generator_tool: "sram_compiler" 3 | # You should specify a location for the SRAM generator in the tech plugin 4 | vlsi.core.sram_generator_tool_path: [] 5 | vlsi.core.sram_generator_tool_path_meta: "append" 6 | 7 | # Tool options. Replace with your tool plugin of choice. 8 | # Genus options 9 | vlsi.core.synthesis_tool: "genus" 10 | vlsi.core.synthesis_tool_path: ["hammer-cadence-plugins/synthesis"] 11 | vlsi.core.synthesis_tool_path_meta: "append" 12 | synthesis.genus.version: "1813" 13 | # Innovus options 14 | vlsi.core.par_tool: "innovus" 15 | vlsi.core.par_tool_path: ["hammer-cadence-plugins/par"] 16 | vlsi.core.par_tool_path_meta: "append" 17 | par.innovus.version: "191_ISR3" 18 | par.innovus.design_flow_effort: "standard" 19 | par.inputs.gds_merge: true 20 | # Calibre options 21 | vlsi.core.drc_tool: "calibre" 22 | vlsi.core.drc_tool_path: ["hammer-mentor-plugins/drc"] 23 | drc.calibre.version: "2017.3_38.30" 24 | vlsi.core.lvs_tool: "calibre" 25 | vlsi.core.lvs_tool_path: ["hammer-mentor-plugins/lvs"] 26 | lvs.calibre.version: "2017.3_38.30" 27 | # VCS options 28 | vlsi.core.sim_tool: "vcs" 29 | vlsi.core.sim_tool_path: ["hammer-synopsys-plugins/sim"] 30 | sim.vcs.version: "P-2019.06-SP2-5" 31 | # Voltus options 32 | vlsi.core.power_tool: "voltus" 33 | vlsi.core.power_tool_path: ["hammer-cadence-plugins/power"] 34 | vlsi.core.power_tool_path_meta: "append" 35 | power.voltus.version: "191_ISR3" 36 | -------------------------------------------------------------------------------- /vlsi/example-vlsi: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env python3 2 | # 3 | # NOTE: this ExampleDriver works for asap7 and nangate45. the custom hooks are 4 | # only used for asap7 though. 5 | 6 | import os 7 | 8 | import hammer_vlsi 9 | from hammer_vlsi import CLIDriver, HammerToolHookAction 10 | 11 | from typing import Dict, Callable, Optional, List 12 | 13 | def example_place_tap_cells(x: hammer_vlsi.HammerTool) -> bool: 14 | if x.get_setting("vlsi.core.technology") == "asap7": 15 | x.append(''' 16 | # TODO 17 | # Place custom TCL here 18 | ''') 19 | return True 20 | 21 | def example_add_fillers(x: hammer_vlsi.HammerTool) -> bool: 22 | if x.get_setting("vlsi.core.technology") == "asap7": 23 | x.append(''' 24 | # TODO 25 | # Place custom TCL here 26 | ''') 27 | return True 28 | 29 | def example_tool_settings(x: hammer_vlsi.HammerTool) -> bool: 30 | if x.get_setting("vlsi.core.technology") == "asap7": 31 | x.append(''' 32 | # TODO 33 | # Place custom TCL here 34 | set_db route_design_bottom_routing_layer 2 35 | set_db route_design_top_routing_layer 7 36 | ''') 37 | return True 38 | 39 | class ExampleDriver(CLIDriver): 40 | def get_extra_par_hooks(self) -> List[HammerToolHookAction]: 41 | extra_hooks = [ 42 | # Default set of steps can be found in the CAD tool plugin's __init__.py 43 | 44 | # make_pre_insertion_hook will execute the custom hook before the specified step 45 | # SYNTAX: make_pre_insertion_hook("EXISTING_STEP", INSERTED_HOOK) 46 | # hammer_vlsi.HammerTool.make_pre_insertion_hook("route_design", example_add_fillers), 47 | 48 | # make_post_insertion_hook will execute the custom hook after the specified step 49 | # hammer_vlsi.HammerTool.make_post_insertion_hook("init_design", example_tool_settings), 50 | 51 | # make_replacement_hook will replace the specified step with a custom hook 52 | # hammer_vlsi.HammerTool.make_replacement_hook("place_tap_cells", example_place_tap_cells), 53 | 54 | # make_removal_hook will remove the specified step from the flow 55 | hammer_vlsi.HammerTool.make_removal_hook("place_bumps"), 56 | 57 | # The target step in any of the above calls may be a default step or another one of your custom hooks 58 | ] 59 | return extra_hooks 60 | 61 | if __name__ == '__main__': 62 | ExampleDriver().main() 63 | -------------------------------------------------------------------------------- /vlsi/example-vlsi-sky130: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env python3 2 | # 3 | # NOTE: the custom hooks are only used for sky130. 4 | 5 | import os 6 | 7 | import hammer_vlsi 8 | from hammer_vlsi import CLIDriver, HammerToolHookAction 9 | 10 | from typing import Dict, Callable, Optional, List 11 | 12 | from technology.sky130 import SKY130Tech 13 | 14 | def example_place_tap_cells(x: hammer_vlsi.HammerTool) -> bool: 15 | if x.get_setting("vlsi.core.technology") == "sky130": 16 | x.append(''' 17 | # TODO 18 | # Place custom TCL here 19 | ''') 20 | return True 21 | 22 | def example_add_fillers(x: hammer_vlsi.HammerTool) -> bool: 23 | if x.get_setting("vlsi.core.technology") == "sky130": 24 | x.append(''' 25 | # TODO 26 | # Place custom TCL here 27 | ''') 28 | return True 29 | 30 | def example_tool_settings(x: hammer_vlsi.HammerTool) -> bool: 31 | if x.get_setting("vlsi.core.technology") == "sky130": 32 | x.append(''' 33 | # TODO 34 | # Place custom TCL here 35 | # only route in met1 to met4 [metal layers: li1(1), met1(2), ..., met4(5), met5(6)] 36 | set_db route_design_bottom_routing_layer 2 37 | set_db route_design_top_routing_layer 5 38 | ''') 39 | return True 40 | 41 | class ExampleDriver(CLIDriver): 42 | def get_extra_par_hooks(self) -> List[HammerToolHookAction]: 43 | extra_hooks = [ 44 | # Default set of steps can be found in the CAD tool plugin's __init__.py 45 | 46 | # make_pre_insertion_hook will execute the custom hook before the specified step 47 | # SYNTAX: make_pre_insertion_hook("EXISTING_STEP", INSERTED_HOOK) 48 | # hammer_vlsi.HammerTool.make_pre_insertion_hook("route_design", example_add_fillers), 49 | 50 | # make_post_insertion_hook will execute the custom hook after the specified step 51 | hammer_vlsi.HammerTool.make_post_insertion_hook("init_design", example_tool_settings), 52 | 53 | # make_replacement_hook will replace the specified step with a custom hook 54 | # hammer_vlsi.HammerTool.make_replacement_hook("place_tap_cells", example_place_tap_cells), 55 | 56 | # make_removal_hook will remove the specified step from the flow 57 | hammer_vlsi.HammerTool.make_removal_hook("place_bumps"), 58 | 59 | # The target step in any of the above calls may be a default step or another one of your custom hooks 60 | ] 61 | return extra_hooks 62 | 63 | if __name__ == '__main__': 64 | ExampleDriver().main() 65 | -------------------------------------------------------------------------------- /vlsi/power.mk: -------------------------------------------------------------------------------- 1 | .PHONY: $(POWER_CONF) 2 | power-par: $(POWER_CONF) sim-par-debug 3 | power-par-$(VLSI_TOP): $(POWER_CONF) sim-par-debug-$(VLSI_TOP) 4 | power-par: override HAMMER_POWER_EXTRA_ARGS += -p $(POWER_CONF) 5 | power-par-$(VLSI_TOP): override HAMMER_POWER_EXTRA_ARGS += -p $(POWER_CONF) 6 | redo-power-par: $(POWER_CONF) 7 | redo-power-par-$(VLSI_TOP): $(POWER_CONF) 8 | redo-power-par: override HAMMER_EXTRA_ARGS += -p $(POWER_CONF) 9 | redo-power-par-$(VLSI_TOP): override HAMMER_EXTRA_ARGS += -p $(POWER_CONF) 10 | $(OBJ_DIR)/power-par-%/power-output-full.json: private override HAMMER_EXTRA_ARGS += $(HAMMER_POWER_EXTRA_ARGS) 11 | -------------------------------------------------------------------------------- /vlsi/view_gds.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/python3 2 | 3 | import sys, os, subprocess 4 | 5 | print('Loading GDS...') 6 | 7 | try: 8 | # gdstk created SVG 9 | import gdstk 10 | except ImportError: 11 | try: 12 | import gdspy 13 | import tkinter 14 | except ImportError: 15 | print('Bad gdspy (requires tkinter) installation!') 16 | sys.exit() 17 | 18 | if 'gdstk' in sys.modules: 19 | svg_file = os.path.splitext(str(sys.argv[1]))[0] + '.svg' 20 | print('Opening {} with xdg-open...'.format(os.path.basename(svg_file))) 21 | subprocess.call(['xdg-open', svg_file]) 22 | 23 | elif 'gdspy' in sys.modules: 24 | gds_lib = gdspy.GdsLibrary().read_gds(infile=str(sys.argv[1]), units='import') 25 | 26 | # Comment to show layer 27 | hidden=[ 28 | (1, 0), #well 29 | (1, 251), #well lbl 30 | (2, 0), #fin 31 | (3, 0), #psub 32 | (3, 251), #psub lbl 33 | (7, 0), #gate 34 | (8, 0), #dummy 35 | (10, 0), #gate cut 36 | (11, 0), #active 37 | (12, 0), #nselect 38 | (13, 0), #pselect 39 | (16, 0), #LIG 40 | (17, 0), #LISD 41 | (18, 0), #V0 42 | (19, 0), #M1 43 | (19, 251), #M1 lbl 44 | (21, 0), #V1 45 | #(20, 0), #M2 46 | (20, 251), #M2 lbl 47 | #(25, 0), #V2 48 | #(30, 0), #M3 49 | (30, 251), #M3 lbl 50 | #(35, 0), #V3 51 | #(40, 0), #M4 52 | (40, 251), #M4 lbl 53 | (45, 0), #V4 54 | (50, 0), #M5 55 | (50, 251), #M5 lbl 56 | (55, 0), #V5 57 | (60, 0), #M6 58 | (60, 251), #M6 lbl 59 | (65, 0), #V6 60 | (70, 0), #M7 61 | (70, 251), #M7 lbl 62 | (75, 0), #V7 63 | (80, 0), #M8 64 | (80, 251), #M8 lbl 65 | (85, 0), #V8 66 | (88, 0), #SDT 67 | (90, 0), #M9 68 | (90, 251), #M9 lbl 69 | (95, 0), #V9 70 | (96, 0), #Pad 71 | (97, 0), #SLVT 72 | (98, 0), #LVT 73 | (99, 0), #SRAMDRC 74 | (100, 0), #BOUNDARY 75 | (101, 0), #TEXT 76 | (110, 0), #SRAMVT 77 | (235, 5) #DIEAREA 78 | ] 79 | 80 | print('Opening layout in gdspy...') 81 | gdspy.LayoutViewer(gds_lib, hidden_types=hidden, depth=1) 82 | --------------------------------------------------------------------------------