├── Readme.md ├── arm_nnexamples_cifar10 ├── ARMCM7_debug │ ├── arm_convolve_1x1_hwc_q7_fast_nonsquare.crf │ ├── arm_convolve_hwc_q15_basic.crf │ ├── arm_convolve_hwc_q15_fast.crf │ ├── arm_convolve_hwc_q7_basic.crf │ ├── arm_convolve_hwc_q7_basic_nonsquare.crf │ ├── arm_convolve_hwc_q7_fast.crf │ ├── arm_convolve_hwc_q7_fast_nonsquare.crf │ ├── arm_convolve_hwc_q7_rgb.crf │ ├── arm_depthwise_conv_u8_basic_ver1.crf │ ├── arm_depthwise_separable_conv_hwc_q7.crf │ ├── arm_depthwise_separable_conv_hwc_q7_nonsquare.crf │ ├── arm_fully_connected_mat_q7_vec_q15.crf │ ├── arm_fully_connected_mat_q7_vec_q15_opt.crf │ ├── arm_fully_connected_q15.crf │ ├── arm_fully_connected_q15_opt.crf │ ├── arm_fully_connected_q7.crf │ ├── arm_fully_connected_q7_opt.crf │ ├── arm_nn_activations_q15.crf │ ├── arm_nn_activations_q7.crf │ ├── arm_nn_mat_mult_kernel_q7_q15.crf │ ├── arm_nn_mat_mult_kernel_q7_q15_reordered.crf │ ├── arm_nn_mult_q15.crf │ ├── arm_nn_mult_q7.crf │ ├── arm_nnexample_cifar10.build_log.htm │ ├── arm_nnexamples_cifar10.crf │ ├── arm_nntables.crf │ ├── arm_pool_q7_hwc.crf │ ├── arm_q7_to_q15_no_shift.crf │ ├── arm_q7_to_q15_reordered_no_shift.crf │ ├── arm_relu_q15.crf │ ├── arm_relu_q7.crf │ ├── arm_softmax_q15.crf │ ├── arm_softmax_q7.crf │ ├── retarget_io.crf │ └── system_armcm7.crf ├── EventRecorderStub.scvd ├── RTE │ ├── Compiler │ │ └── EventRecorderConf.h │ ├── Device │ │ ├── ARMCM0 │ │ │ ├── startup_ARMCM0.s │ │ │ └── system_ARMCM0.c │ │ ├── ARMCM3 │ │ │ ├── startup_ARMCM3.s │ │ │ └── system_ARMCM3.c │ │ ├── ARMCM4_FP │ │ │ ├── startup_ARMCM4.s │ │ │ └── system_ARMCM4.c │ │ └── ARMCM7_SP │ │ │ ├── gcc_arm.ld │ │ │ ├── startup_ARMCM7.c │ │ │ ├── startup_ARMCM7.s │ │ │ └── system_ARMCM7.c │ ├── _ARMCM0 │ │ └── RTE_Components.h │ ├── _ARMCM3 │ │ └── RTE_Components.h │ ├── _ARMCM4_FP │ │ └── RTE_Components.h │ └── _ARMCM7_SP │ │ └── RTE_Components.h ├── arm_nnexamples_cifar10.uvguix.Administrator ├── arm_nnexamples_cifar10.uvoptx ├── arm_nnexamples_cifar10.uvprojx ├── readme.md └── src │ ├── arm_nnexamples_cifar10.cpp │ ├── arm_nnexamples_cifar10_inputs.h │ ├── arm_nnexamples_cifar10_parameter.h │ └── arm_nnexamples_cifar10_weights.h ├── assets └── img │ ├── arm_nn_cifar_debug.png │ ├── array_to_image.png │ ├── image_convert_array.png │ ├── input_image.png │ ├── resize_and_convert_array.png │ ├── stm32_image_classifier.png │ └── stm32_image_classifier_output_result.png ├── script ├── Readme.md ├── array_convert_to_image.py ├── image_convert_to_array.py └── resize_image_and_to_array.py ├── test_images_from_cifar10 ├── Readme.md ├── airplane4.png ├── automobile5.png ├── cat9.png ├── deer2.png ├── horse5.png └── image_convert_to_array.py └── test_images_from_internet ├── Readme.md ├── cat00.png ├── cat01.jpg ├── dog00.jpg ├── horse00.jpg └── resize_image_and_to_array.py /Readme.md: -------------------------------------------------------------------------------- 1 | # STM32图像分类 2 | 3 | ![](https://github.com/edgeML/cifar10_image_classifier_on_stm32/blob/master/assets/img/stm32_image_classifier.png) 4 | 5 | 6 | ## 项目简介 7 | 8 | 本项目实现了在STM32上进行图像分类的任务。使用CIFAR-10数据集，通过Caffe机器学习框架搭建和训练神经网络模型，然后将所得模型进行转换，使其能够运行在STM32上。本项目运行在Keil的模拟器中，所以无需开发板也能体验机器学习在STM32上的应用效果。 9 | 10 | ## 目录说明 11 | 12 | |目录|描述| 13 | |----|----| 14 | |arm_nnexamples_cifar10|STM32图像分类MDK项目源码| 15 | |script|图片预处理脚本| 16 | |test_images_from_cifar10|来自CIFAR-10数据集的测试图片| 17 | |test_images_from_internet|来自互联网的测试图片| 18 | 19 | ## 项目的输入 20 | 21 | ![](https://github.com/edgeML/cifar10_image_classifier_on_stm32/blob/master/assets/img/input_image.png) 22 | 23 | 一幅宽32像素高32像素的彩色图像，为方便STM32实验操作， 24 | 事先将图像转换为像素值数组，存放在arm_nnexamples_cifar10_inputs.h中。 25 | 26 | ## 项目的输出 27 | 28 | 输出是测试图像所属的类别的概率，概率值最大的就是目标图像的所属类别，输出结果如下图所示： 29 | 30 | ![](https://github.com/edgeML/cifar10_image_classifier_on_stm32/blob/master/assets/img/stm32_image_classifier_output_result.png) 31 | 32 | 细心的同学可能要问了，为什么这里的输出是127，而不是一个0~1之间的数？ 33 | 34 | 这个跟我们使用的Softmax函数有关，一般Softmax函数的公式是这样的： 35 | ``` 36 | y_i = e^(x_i) / sum(e^x_j) 37 | ``` 38 | 而在STM32上我们采用的是以2为底Softmax函数，所以其输出会有所不同。 39 | ``` 40 | y_i = 2^(x_i) / sum(2^x_j) 41 | ``` 42 | 众所周知，微控制器的计算性能有限，这样做可以大大减小计算量，并且从数学上来讲梯度是一样的，我们依然能够很好地分辨出目标图像的所属类别。 43 | 44 | ## 使用说明： 45 | 46 | 编译 -> Debug调试运行 -> 打开Debug (printf) Viewer (View->Serial Windows->Debug (printf) Viewer) 47 | 48 | ![](https://github.com/edgeML/cifar10_image_classifier_on_stm32/blob/master/assets/img/arm_nn_cifar_debug.png) 49 | 50 | ## 相关链接 51 | 52 | * https://mp.weixin.qq.com/s/KUaZlZa6GuHJkKwhGmzczw 53 | * https://github.com/BVLC/caffe 54 | * https://github.com/ARM-software/ML-examples/tree/master/cmsisnn-cifar10 55 | * https://github.com/ARM-software/CMSIS_5/tree/develop/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10 56 | 57 | -------------------------------------------------------------------------------- /arm_nnexamples_cifar10/ARMCM7_debug/arm_convolve_1x1_hwc_q7_fast_nonsquare.crf: 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All rights reserved. 4 | *------------------------------------------------------------------------------ 5 | * Name: EventRecorderConf.h 6 | * Purpose: Event Recorder Configuration 7 | * Rev.: V1.0.0 8 | *----------------------------------------------------------------------------*/ 9 | 10 | //-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- 11 | 12 | // Event Recorder 13 | 14 | // Number of Records 15 | // <8=>8 <16=>16 <32=>32 <64=>64 <128=>128 <256=>256 <512=>512 <1024=>1024 16 | // <2048=>2048 <4096=>4096 <8192=>8192 <16384=>16384 <32768=>32768 17 | // <65536=>65536 <131072=>131072 <262144=>262144 <524288=>524288 18 | // <1048576=>1048576 19 | // Configure size of Event Record Buffer (each record is 16 bytes) 20 | // Must be 2^n (min=8, max=1048576) 21 | #define EVENT_RECORD_COUNT 64U 22 | 23 | // Time Stamp Source 24 | // <0=> DWT Cycle Counter <1=> SysTick 25 | // <3=> User Timer (Normal Reset) <4=> User Timer (Power-On Reset) 26 | // Selects source for 32-bit time stamp 27 | #define EVENT_TIMESTAMP_SOURCE 1 28 | 29 | // SysTick Configuration 30 | // Configure values when Time Stamp Source is set to SysTick 31 | 32 | // SysTick Input Clock Frequency [Hz] <1-1000000000> 33 | // Defines SysTick input clock (typical identical with processor clock) 34 | #define SYSTICK_CLOCK 100000000U 35 | 36 | // SysTick Interrupt Period [us] <1-1000000000> 37 | // Defines time period of the SysTick timer interrupt 38 | #define SYSTICK_PERIOD_US 1000U 39 | 40 | // 41 | 42 | // 43 | 44 | //------------- <<< end of configuration section >>> --------------------------- 45 | -------------------------------------------------------------------------------- /arm_nnexamples_cifar10/RTE/Device/ARMCM0/startup_ARMCM0.s: -------------------------------------------------------------------------------- 1 | ;/**************************************************************************//** 2 | ; * @file startup_ARMCM0.s 3 | ; * @brief CMSIS Core Device Startup File for 4 | ; * ARMCM0 Device Series 5 | ; * @version V5.00 6 | ; * @date 02. March 2016 7 | ; ******************************************************************************/ 8 | ;/* 9 | ; * Copyright (c) 2009-2016 ARM Limited. All rights reserved. 10 | ; * 11 | ; * SPDX-License-Identifier: Apache-2.0 12 | ; * 13 | ; * Licensed under the Apache License, Version 2.0 (the License); you may 14 | ; * not use this file except in compliance with the License. 15 | ; * You may obtain a copy of the License at 16 | ; * 17 | ; * www.apache.org/licenses/LICENSE-2.0 18 | ; * 19 | ; * Unless required by applicable law or agreed to in writing, software 20 | ; * distributed under the License is distributed on an AS IS BASIS, WITHOUT 21 | ; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 | ; * See the License for the specific language governing permissions and 23 | ; * limitations under the License. 24 | ; */ 25 | 26 | ;/* 27 | ;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ 28 | ;*/ 29 | 30 | 31 | ; Stack Configuration 32 | ; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> 33 | ; 34 | 35 | Stack_Size EQU 0x00000400 36 | 37 | AREA STACK, NOINIT, READWRITE, ALIGN=3 38 | Stack_Mem SPACE Stack_Size 39 | __initial_sp 40 | 41 | 42 | ; Heap Configuration 43 | ; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> 44 | ; 45 | 46 | Heap_Size EQU 0x00000C00 47 | 48 | AREA HEAP, NOINIT, READWRITE, ALIGN=3 49 | __heap_base 50 | Heap_Mem SPACE Heap_Size 51 | __heap_limit 52 | 53 | 54 | PRESERVE8 55 | THUMB 56 | 57 | 58 | ; Vector Table Mapped to Address 0 at Reset 59 | 60 | AREA RESET, DATA, READONLY 61 | EXPORT __Vectors 62 | EXPORT __Vectors_End 63 | EXPORT __Vectors_Size 64 | 65 | __Vectors DCD __initial_sp ; Top of Stack 66 | DCD Reset_Handler ; Reset Handler 67 | DCD NMI_Handler ; NMI Handler 68 | DCD HardFault_Handler ; Hard Fault Handler 69 | DCD 0 ; Reserved 70 | DCD 0 ; Reserved 71 | DCD 0 ; Reserved 72 | DCD 0 ; Reserved 73 | DCD 0 ; Reserved 74 | DCD 0 ; Reserved 75 | DCD 0 ; Reserved 76 | DCD SVC_Handler ; SVCall Handler 77 | DCD 0 ; Reserved 78 | DCD 0 ; Reserved 79 | DCD PendSV_Handler ; PendSV Handler 80 | DCD SysTick_Handler ; SysTick Handler 81 | 82 | ; External Interrupts 83 | DCD WDT_IRQHandler ; 0: Watchdog Timer 84 | DCD RTC_IRQHandler ; 1: Real Time Clock 85 | DCD TIM0_IRQHandler ; 2: Timer0 / Timer1 86 | DCD TIM2_IRQHandler ; 3: Timer2 / Timer3 87 | DCD MCIA_IRQHandler ; 4: MCIa 88 | DCD MCIB_IRQHandler ; 5: MCIb 89 | DCD UART0_IRQHandler ; 6: UART0 - DUT FPGA 90 | DCD UART1_IRQHandler ; 7: UART1 - DUT FPGA 91 | DCD UART2_IRQHandler ; 8: UART2 - DUT FPGA 92 | DCD UART4_IRQHandler ; 9: UART4 - not connected 93 | DCD AACI_IRQHandler ; 10: AACI / AC97 94 | DCD CLCD_IRQHandler ; 11: CLCD Combined Interrupt 95 | DCD ENET_IRQHandler ; 12: Ethernet 96 | DCD USBDC_IRQHandler ; 13: USB Device 97 | DCD USBHC_IRQHandler ; 14: USB Host Controller 98 | DCD CHLCD_IRQHandler ; 15: Character LCD 99 | DCD FLEXRAY_IRQHandler ; 16: Flexray 100 | DCD CAN_IRQHandler ; 17: CAN 101 | DCD LIN_IRQHandler ; 18: LIN 102 | DCD I2C_IRQHandler ; 19: I2C ADC/DAC 103 | DCD 0 ; 20: Reserved 104 | DCD 0 ; 21: Reserved 105 | DCD 0 ; 22: Reserved 106 | DCD 0 ; 23: Reserved 107 | DCD 0 ; 24: Reserved 108 | DCD 0 ; 25: Reserved 109 | DCD 0 ; 26: Reserved 110 | DCD 0 ; 27: Reserved 111 | DCD CPU_CLCD_IRQHandler ; 28: Reserved - CPU FPGA CLCD 112 | DCD 0 ; 29: Reserved - CPU FPGA 113 | DCD UART3_IRQHandler ; 30: UART3 - CPU FPGA 114 | DCD SPI_IRQHandler ; 31: SPI Touchscreen - CPU FPGA 115 | __Vectors_End 116 | 117 | __Vectors_Size EQU __Vectors_End - __Vectors 118 | 119 | AREA |.text|, CODE, READONLY 120 | 121 | 122 | ; Reset Handler 123 | 124 | Reset_Handler PROC 125 | EXPORT Reset_Handler [WEAK] 126 | IMPORT SystemInit 127 | IMPORT __main 128 | LDR R0, =SystemInit 129 | BLX R0 130 | LDR R0, =__main 131 | BX R0 132 | ENDP 133 | 134 | 135 | ; Dummy Exception Handlers (infinite loops which can be modified) 136 | 137 | NMI_Handler PROC 138 | EXPORT NMI_Handler [WEAK] 139 | B . 140 | ENDP 141 | HardFault_Handler\ 142 | PROC 143 | EXPORT HardFault_Handler [WEAK] 144 | B . 145 | ENDP 146 | SVC_Handler PROC 147 | EXPORT SVC_Handler [WEAK] 148 | B . 149 | ENDP 150 | PendSV_Handler PROC 151 | EXPORT PendSV_Handler [WEAK] 152 | B . 153 | ENDP 154 | SysTick_Handler PROC 155 | EXPORT SysTick_Handler [WEAK] 156 | B . 157 | ENDP 158 | 159 | Default_Handler PROC 160 | 161 | EXPORT WDT_IRQHandler [WEAK] 162 | EXPORT RTC_IRQHandler [WEAK] 163 | EXPORT TIM0_IRQHandler [WEAK] 164 | EXPORT TIM2_IRQHandler [WEAK] 165 | EXPORT MCIA_IRQHandler [WEAK] 166 | EXPORT MCIB_IRQHandler [WEAK] 167 | EXPORT UART0_IRQHandler [WEAK] 168 | EXPORT UART1_IRQHandler [WEAK] 169 | EXPORT UART2_IRQHandler [WEAK] 170 | EXPORT UART3_IRQHandler [WEAK] 171 | EXPORT UART4_IRQHandler [WEAK] 172 | EXPORT AACI_IRQHandler [WEAK] 173 | EXPORT CLCD_IRQHandler [WEAK] 174 | EXPORT ENET_IRQHandler [WEAK] 175 | EXPORT USBDC_IRQHandler [WEAK] 176 | EXPORT USBHC_IRQHandler [WEAK] 177 | EXPORT CHLCD_IRQHandler [WEAK] 178 | EXPORT FLEXRAY_IRQHandler [WEAK] 179 | EXPORT CAN_IRQHandler [WEAK] 180 | EXPORT LIN_IRQHandler [WEAK] 181 | EXPORT I2C_IRQHandler [WEAK] 182 | EXPORT CPU_CLCD_IRQHandler [WEAK] 183 | EXPORT SPI_IRQHandler [WEAK] 184 | 185 | WDT_IRQHandler 186 | RTC_IRQHandler 187 | TIM0_IRQHandler 188 | TIM2_IRQHandler 189 | MCIA_IRQHandler 190 | MCIB_IRQHandler 191 | UART0_IRQHandler 192 | UART1_IRQHandler 193 | UART2_IRQHandler 194 | UART3_IRQHandler 195 | UART4_IRQHandler 196 | AACI_IRQHandler 197 | CLCD_IRQHandler 198 | ENET_IRQHandler 199 | USBDC_IRQHandler 200 | USBHC_IRQHandler 201 | CHLCD_IRQHandler 202 | FLEXRAY_IRQHandler 203 | CAN_IRQHandler 204 | LIN_IRQHandler 205 | I2C_IRQHandler 206 | CPU_CLCD_IRQHandler 207 | SPI_IRQHandler 208 | B . 209 | 210 | ENDP 211 | 212 | 213 | ALIGN 214 | 215 | 216 | ; User Initial Stack & Heap 217 | 218 | IF :DEF:__MICROLIB 219 | 220 | EXPORT __initial_sp 221 | EXPORT __heap_base 222 | EXPORT __heap_limit 223 | 224 | ELSE 225 | 226 | IMPORT __use_two_region_memory 227 | EXPORT __user_initial_stackheap 228 | 229 | __user_initial_stackheap PROC 230 | LDR R0, = Heap_Mem 231 | LDR R1, =(Stack_Mem + Stack_Size) 232 | LDR R2, = (Heap_Mem + Heap_Size) 233 | LDR R3, = Stack_Mem 234 | BX LR 235 | ENDP 236 | 237 | ALIGN 238 | 239 | ENDIF 240 | 241 | 242 | END 243 | -------------------------------------------------------------------------------- /arm_nnexamples_cifar10/RTE/Device/ARMCM0/system_ARMCM0.c: -------------------------------------------------------------------------------- 1 | /**************************************************************************//** 2 | * @file system_ARMCM0.c 3 | * @brief CMSIS Device System Source File for 4 | * ARMCM0 Device Series 5 | * @version V5.00 6 | * @date 08. April 2016 7 | ******************************************************************************/ 8 | /* 9 | * Copyright (c) 2009-2016 ARM Limited. All rights reserved. 10 | * 11 | * SPDX-License-Identifier: Apache-2.0 12 | * 13 | * Licensed under the Apache License, Version 2.0 (the License); you may 14 | * not use this file except in compliance with the License. 15 | * You may obtain a copy of the License at 16 | * 17 | * www.apache.org/licenses/LICENSE-2.0 18 | * 19 | * Unless required by applicable law or agreed to in writing, software 20 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT 21 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 | * See the License for the specific language governing permissions and 23 | * limitations under the License. 24 | */ 25 | 26 | #include "ARMCM0.h" 27 | 28 | /*---------------------------------------------------------------------------- 29 | Define clocks 30 | *----------------------------------------------------------------------------*/ 31 | #define XTAL ( 5000000U) /* Oscillator frequency */ 32 | 33 | #define SYSTEM_CLOCK (5 * XTAL) 34 | 35 | 36 | /*---------------------------------------------------------------------------- 37 | System Core Clock Variable 38 | *----------------------------------------------------------------------------*/ 39 | uint32_t SystemCoreClock = SYSTEM_CLOCK; 40 | 41 | 42 | /*---------------------------------------------------------------------------- 43 | System Core Clock update function 44 | *----------------------------------------------------------------------------*/ 45 | void SystemCoreClockUpdate (void) 46 | { 47 | SystemCoreClock = SYSTEM_CLOCK; 48 | } 49 | 50 | /*---------------------------------------------------------------------------- 51 | System initialization function 52 | *----------------------------------------------------------------------------*/ 53 | void SystemInit (void) 54 | { 55 | SystemCoreClock = SYSTEM_CLOCK; 56 | } 57 | -------------------------------------------------------------------------------- /arm_nnexamples_cifar10/RTE/Device/ARMCM3/startup_ARMCM3.s: -------------------------------------------------------------------------------- 1 | ;/**************************************************************************//** 2 | ; * @file startup_ARMCM3.s 3 | ; * @brief CMSIS Core Device Startup File for 4 | ; * ARMCM3 Device Series 5 | ; * @version V5.00 6 | ; * @date 02. March 2016 7 | ; ******************************************************************************/ 8 | ;/* 9 | ; * Copyright (c) 2009-2016 ARM Limited. All rights reserved. 10 | ; * 11 | ; * SPDX-License-Identifier: Apache-2.0 12 | ; * 13 | ; * Licensed under the Apache License, Version 2.0 (the License); you may 14 | ; * not use this file except in compliance with the License. 15 | ; * You may obtain a copy of the License at 16 | ; * 17 | ; * www.apache.org/licenses/LICENSE-2.0 18 | ; * 19 | ; * Unless required by applicable law or agreed to in writing, software 20 | ; * distributed under the License is distributed on an AS IS BASIS, WITHOUT 21 | ; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 | ; * See the License for the specific language governing permissions and 23 | ; * limitations under the License. 24 | ; */ 25 | 26 | ;/* 27 | ;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ 28 | ;*/ 29 | 30 | 31 | ; Stack Configuration 32 | ; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> 33 | ; 34 | 35 | Stack_Size EQU 0x00000400 36 | 37 | AREA STACK, NOINIT, READWRITE, ALIGN=3 38 | Stack_Mem SPACE Stack_Size 39 | __initial_sp 40 | 41 | 42 | ; Heap Configuration 43 | ; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> 44 | ; 45 | 46 | Heap_Size EQU 0x00000C00 47 | 48 | AREA HEAP, NOINIT, READWRITE, ALIGN=3 49 | __heap_base 50 | Heap_Mem SPACE Heap_Size 51 | __heap_limit 52 | 53 | 54 | PRESERVE8 55 | THUMB 56 | 57 | 58 | ; Vector Table Mapped to Address 0 at Reset 59 | 60 | AREA RESET, DATA, READONLY 61 | EXPORT __Vectors 62 | EXPORT __Vectors_End 63 | EXPORT __Vectors_Size 64 | 65 | __Vectors DCD __initial_sp ; Top of Stack 66 | DCD Reset_Handler ; Reset Handler 67 | DCD NMI_Handler ; NMI Handler 68 | DCD HardFault_Handler ; Hard Fault Handler 69 | DCD MemManage_Handler ; MPU Fault Handler 70 | DCD BusFault_Handler ; Bus Fault Handler 71 | DCD UsageFault_Handler ; Usage Fault Handler 72 | DCD 0 ; Reserved 73 | DCD 0 ; Reserved 74 | DCD 0 ; Reserved 75 | DCD 0 ; Reserved 76 | DCD SVC_Handler ; SVCall Handler 77 | DCD DebugMon_Handler ; Debug Monitor Handler 78 | DCD 0 ; Reserved 79 | DCD PendSV_Handler ; PendSV Handler 80 | DCD SysTick_Handler ; SysTick Handler 81 | 82 | ; External Interrupts 83 | DCD WDT_IRQHandler ; 0: Watchdog Timer 84 | DCD RTC_IRQHandler ; 1: Real Time Clock 85 | DCD TIM0_IRQHandler ; 2: Timer0 / Timer1 86 | DCD TIM2_IRQHandler ; 3: Timer2 / Timer3 87 | DCD MCIA_IRQHandler ; 4: MCIa 88 | DCD MCIB_IRQHandler ; 5: MCIb 89 | DCD UART0_IRQHandler ; 6: UART0 - DUT FPGA 90 | DCD UART1_IRQHandler ; 7: UART1 - DUT FPGA 91 | DCD UART2_IRQHandler ; 8: UART2 - DUT FPGA 92 | DCD UART4_IRQHandler ; 9: UART4 - not connected 93 | DCD AACI_IRQHandler ; 10: AACI / AC97 94 | DCD CLCD_IRQHandler ; 11: CLCD Combined Interrupt 95 | DCD ENET_IRQHandler ; 12: Ethernet 96 | DCD USBDC_IRQHandler ; 13: USB Device 97 | DCD USBHC_IRQHandler ; 14: USB Host Controller 98 | DCD CHLCD_IRQHandler ; 15: Character LCD 99 | DCD FLEXRAY_IRQHandler ; 16: Flexray 100 | DCD CAN_IRQHandler ; 17: CAN 101 | DCD LIN_IRQHandler ; 18: LIN 102 | DCD I2C_IRQHandler ; 19: I2C ADC/DAC 103 | DCD 0 ; 20: Reserved 104 | DCD 0 ; 21: Reserved 105 | DCD 0 ; 22: Reserved 106 | DCD 0 ; 23: Reserved 107 | DCD 0 ; 24: Reserved 108 | DCD 0 ; 25: Reserved 109 | DCD 0 ; 26: Reserved 110 | DCD 0 ; 27: Reserved 111 | DCD CPU_CLCD_IRQHandler ; 28: Reserved - CPU FPGA CLCD 112 | DCD 0 ; 29: Reserved - CPU FPGA 113 | DCD UART3_IRQHandler ; 30: UART3 - CPU FPGA 114 | DCD SPI_IRQHandler ; 31: SPI Touchscreen - CPU FPGA 115 | __Vectors_End 116 | 117 | __Vectors_Size EQU __Vectors_End - __Vectors 118 | 119 | AREA |.text|, CODE, READONLY 120 | 121 | 122 | ; Reset Handler 123 | 124 | Reset_Handler PROC 125 | EXPORT Reset_Handler [WEAK] 126 | IMPORT SystemInit 127 | IMPORT __main 128 | LDR R0, =SystemInit 129 | BLX R0 130 | LDR R0, =__main 131 | BX R0 132 | ENDP 133 | 134 | 135 | ; Dummy Exception Handlers (infinite loops which can be modified) 136 | 137 | NMI_Handler PROC 138 | EXPORT NMI_Handler [WEAK] 139 | B . 140 | ENDP 141 | HardFault_Handler\ 142 | PROC 143 | EXPORT HardFault_Handler [WEAK] 144 | B . 145 | ENDP 146 | MemManage_Handler\ 147 | PROC 148 | EXPORT MemManage_Handler [WEAK] 149 | B . 150 | ENDP 151 | BusFault_Handler\ 152 | PROC 153 | EXPORT BusFault_Handler [WEAK] 154 | B . 155 | ENDP 156 | UsageFault_Handler\ 157 | PROC 158 | EXPORT UsageFault_Handler [WEAK] 159 | B . 160 | ENDP 161 | SVC_Handler PROC 162 | EXPORT SVC_Handler [WEAK] 163 | B . 164 | ENDP 165 | DebugMon_Handler\ 166 | PROC 167 | EXPORT DebugMon_Handler [WEAK] 168 | B . 169 | ENDP 170 | PendSV_Handler PROC 171 | EXPORT PendSV_Handler [WEAK] 172 | B . 173 | ENDP 174 | SysTick_Handler PROC 175 | EXPORT SysTick_Handler [WEAK] 176 | B . 177 | ENDP 178 | 179 | Default_Handler PROC 180 | 181 | EXPORT WDT_IRQHandler [WEAK] 182 | EXPORT RTC_IRQHandler [WEAK] 183 | EXPORT TIM0_IRQHandler [WEAK] 184 | EXPORT TIM2_IRQHandler [WEAK] 185 | EXPORT MCIA_IRQHandler [WEAK] 186 | EXPORT MCIB_IRQHandler [WEAK] 187 | EXPORT UART0_IRQHandler [WEAK] 188 | EXPORT UART1_IRQHandler [WEAK] 189 | EXPORT UART2_IRQHandler [WEAK] 190 | EXPORT UART3_IRQHandler [WEAK] 191 | EXPORT UART4_IRQHandler [WEAK] 192 | EXPORT AACI_IRQHandler [WEAK] 193 | EXPORT CLCD_IRQHandler [WEAK] 194 | EXPORT ENET_IRQHandler [WEAK] 195 | EXPORT USBDC_IRQHandler [WEAK] 196 | EXPORT USBHC_IRQHandler [WEAK] 197 | EXPORT CHLCD_IRQHandler [WEAK] 198 | EXPORT FLEXRAY_IRQHandler [WEAK] 199 | EXPORT CAN_IRQHandler [WEAK] 200 | EXPORT LIN_IRQHandler [WEAK] 201 | EXPORT I2C_IRQHandler [WEAK] 202 | EXPORT CPU_CLCD_IRQHandler [WEAK] 203 | EXPORT SPI_IRQHandler [WEAK] 204 | 205 | WDT_IRQHandler 206 | RTC_IRQHandler 207 | TIM0_IRQHandler 208 | TIM2_IRQHandler 209 | MCIA_IRQHandler 210 | MCIB_IRQHandler 211 | UART0_IRQHandler 212 | UART1_IRQHandler 213 | UART2_IRQHandler 214 | UART3_IRQHandler 215 | UART4_IRQHandler 216 | AACI_IRQHandler 217 | CLCD_IRQHandler 218 | ENET_IRQHandler 219 | USBDC_IRQHandler 220 | USBHC_IRQHandler 221 | CHLCD_IRQHandler 222 | FLEXRAY_IRQHandler 223 | CAN_IRQHandler 224 | LIN_IRQHandler 225 | I2C_IRQHandler 226 | CPU_CLCD_IRQHandler 227 | SPI_IRQHandler 228 | B . 229 | 230 | ENDP 231 | 232 | 233 | ALIGN 234 | 235 | 236 | ; User Initial Stack & Heap 237 | 238 | IF :DEF:__MICROLIB 239 | 240 | EXPORT __initial_sp 241 | EXPORT __heap_base 242 | EXPORT __heap_limit 243 | 244 | ELSE 245 | 246 | IMPORT __use_two_region_memory 247 | EXPORT __user_initial_stackheap 248 | 249 | __user_initial_stackheap PROC 250 | LDR R0, = Heap_Mem 251 | LDR R1, =(Stack_Mem + Stack_Size) 252 | LDR R2, = (Heap_Mem + Heap_Size) 253 | LDR R3, = Stack_Mem 254 | BX LR 255 | ENDP 256 | 257 | ALIGN 258 | 259 | ENDIF 260 | 261 | 262 | END 263 | -------------------------------------------------------------------------------- /arm_nnexamples_cifar10/RTE/Device/ARMCM3/system_ARMCM3.c: -------------------------------------------------------------------------------- 1 | /**************************************************************************//** 2 | * @file system_ARMCM3.c 3 | * @brief CMSIS Device System Source File for 4 | * ARMCM3 Device Series 5 | * @version V5.00 6 | * @date 08. April 2016 7 | ******************************************************************************/ 8 | /* 9 | * Copyright (c) 2009-2016 ARM Limited. All rights reserved. 10 | * 11 | * SPDX-License-Identifier: Apache-2.0 12 | * 13 | * Licensed under the Apache License, Version 2.0 (the License); you may 14 | * not use this file except in compliance with the License. 15 | * You may obtain a copy of the License at 16 | * 17 | * www.apache.org/licenses/LICENSE-2.0 18 | * 19 | * Unless required by applicable law or agreed to in writing, software 20 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT 21 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 | * See the License for the specific language governing permissions and 23 | * limitations under the License. 24 | */ 25 | 26 | #include "ARMCM3.h" 27 | 28 | /*---------------------------------------------------------------------------- 29 | Define clocks 30 | *----------------------------------------------------------------------------*/ 31 | #define XTAL ( 5000000U) /* Oscillator frequency */ 32 | 33 | #define SYSTEM_CLOCK (5 * XTAL) 34 | 35 | 36 | /*---------------------------------------------------------------------------- 37 | Externals 38 | *----------------------------------------------------------------------------*/ 39 | #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1) 40 | extern uint32_t __Vectors; 41 | #endif 42 | 43 | /*---------------------------------------------------------------------------- 44 | System Core Clock Variable 45 | *----------------------------------------------------------------------------*/ 46 | uint32_t SystemCoreClock = SYSTEM_CLOCK; 47 | 48 | 49 | /*---------------------------------------------------------------------------- 50 | System Core Clock update function 51 | *----------------------------------------------------------------------------*/ 52 | void SystemCoreClockUpdate (void) 53 | { 54 | SystemCoreClock = SYSTEM_CLOCK; 55 | } 56 | 57 | /*---------------------------------------------------------------------------- 58 | System initialization function 59 | *----------------------------------------------------------------------------*/ 60 | void SystemInit (void) 61 | { 62 | 63 | #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1) 64 | SCB->VTOR = (uint32_t) &__Vectors; 65 | #endif 66 | 67 | SystemCoreClock = SYSTEM_CLOCK; 68 | } 69 | -------------------------------------------------------------------------------- /arm_nnexamples_cifar10/RTE/Device/ARMCM4_FP/startup_ARMCM4.s: -------------------------------------------------------------------------------- 1 | ;/**************************************************************************//** 2 | ; * @file startup_ARMCM4.s 3 | ; * @brief CMSIS Core Device Startup File for 4 | ; * ARMCM4 Device Series 5 | ; * @version V5.00 6 | ; * @date 02. March 2016 7 | ; ******************************************************************************/ 8 | ;/* 9 | ; * Copyright (c) 2009-2016 ARM Limited. All rights reserved. 10 | ; * 11 | ; * SPDX-License-Identifier: Apache-2.0 12 | ; * 13 | ; * Licensed under the Apache License, Version 2.0 (the License); you may 14 | ; * not use this file except in compliance with the License. 15 | ; * You may obtain a copy of the License at 16 | ; * 17 | ; * www.apache.org/licenses/LICENSE-2.0 18 | ; * 19 | ; * Unless required by applicable law or agreed to in writing, software 20 | ; * distributed under the License is distributed on an AS IS BASIS, WITHOUT 21 | ; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 | ; * See the License for the specific language governing permissions and 23 | ; * limitations under the License. 24 | ; */ 25 | 26 | ;/* 27 | ;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ 28 | ;*/ 29 | 30 | 31 | ; Stack Configuration 32 | ; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> 33 | ; 34 | 35 | Stack_Size EQU 0x00000400 36 | 37 | AREA STACK, NOINIT, READWRITE, ALIGN=3 38 | Stack_Mem SPACE Stack_Size 39 | __initial_sp 40 | 41 | 42 | ; Heap Configuration 43 | ; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> 44 | ; 45 | 46 | Heap_Size EQU 0x00000C00 47 | 48 | AREA HEAP, NOINIT, READWRITE, ALIGN=3 49 | __heap_base 50 | Heap_Mem SPACE Heap_Size 51 | __heap_limit 52 | 53 | 54 | PRESERVE8 55 | THUMB 56 | 57 | 58 | ; Vector Table Mapped to Address 0 at Reset 59 | 60 | AREA RESET, DATA, READONLY 61 | EXPORT __Vectors 62 | EXPORT __Vectors_End 63 | EXPORT __Vectors_Size 64 | 65 | __Vectors DCD __initial_sp ; Top of Stack 66 | DCD Reset_Handler ; Reset Handler 67 | DCD NMI_Handler ; NMI Handler 68 | DCD HardFault_Handler ; Hard Fault Handler 69 | DCD MemManage_Handler ; MPU Fault Handler 70 | DCD BusFault_Handler ; Bus Fault Handler 71 | DCD UsageFault_Handler ; Usage Fault Handler 72 | DCD 0 ; Reserved 73 | DCD 0 ; Reserved 74 | DCD 0 ; Reserved 75 | DCD 0 ; Reserved 76 | DCD SVC_Handler ; SVCall Handler 77 | DCD DebugMon_Handler ; Debug Monitor Handler 78 | DCD 0 ; Reserved 79 | DCD PendSV_Handler ; PendSV Handler 80 | DCD SysTick_Handler ; SysTick Handler 81 | 82 | ; External Interrupts 83 | DCD WDT_IRQHandler ; 0: Watchdog Timer 84 | DCD RTC_IRQHandler ; 1: Real Time Clock 85 | DCD TIM0_IRQHandler ; 2: Timer0 / Timer1 86 | DCD TIM2_IRQHandler ; 3: Timer2 / Timer3 87 | DCD MCIA_IRQHandler ; 4: MCIa 88 | DCD MCIB_IRQHandler ; 5: MCIb 89 | DCD UART0_IRQHandler ; 6: UART0 - DUT FPGA 90 | DCD UART1_IRQHandler ; 7: UART1 - DUT FPGA 91 | DCD UART2_IRQHandler ; 8: UART2 - DUT FPGA 92 | DCD UART4_IRQHandler ; 9: UART4 - not connected 93 | DCD AACI_IRQHandler ; 10: AACI / AC97 94 | DCD CLCD_IRQHandler ; 11: CLCD Combined Interrupt 95 | DCD ENET_IRQHandler ; 12: Ethernet 96 | DCD USBDC_IRQHandler ; 13: USB Device 97 | DCD USBHC_IRQHandler ; 14: USB Host Controller 98 | DCD CHLCD_IRQHandler ; 15: Character LCD 99 | DCD FLEXRAY_IRQHandler ; 16: Flexray 100 | DCD CAN_IRQHandler ; 17: CAN 101 | DCD LIN_IRQHandler ; 18: LIN 102 | DCD I2C_IRQHandler ; 19: I2C ADC/DAC 103 | DCD 0 ; 20: Reserved 104 | DCD 0 ; 21: Reserved 105 | DCD 0 ; 22: Reserved 106 | DCD 0 ; 23: Reserved 107 | DCD 0 ; 24: Reserved 108 | DCD 0 ; 25: Reserved 109 | DCD 0 ; 26: Reserved 110 | DCD 0 ; 27: Reserved 111 | DCD CPU_CLCD_IRQHandler ; 28: Reserved - CPU FPGA CLCD 112 | DCD 0 ; 29: Reserved - CPU FPGA 113 | DCD UART3_IRQHandler ; 30: UART3 - CPU FPGA 114 | DCD SPI_IRQHandler ; 31: SPI Touchscreen - CPU FPGA 115 | __Vectors_End 116 | 117 | __Vectors_Size EQU __Vectors_End - __Vectors 118 | 119 | AREA |.text|, CODE, READONLY 120 | 121 | 122 | ; Reset Handler 123 | 124 | Reset_Handler PROC 125 | EXPORT Reset_Handler [WEAK] 126 | IMPORT SystemInit 127 | IMPORT __main 128 | LDR R0, =SystemInit 129 | BLX R0 130 | LDR R0, =__main 131 | BX R0 132 | ENDP 133 | 134 | 135 | ; Dummy Exception Handlers (infinite loops which can be modified) 136 | 137 | NMI_Handler PROC 138 | EXPORT NMI_Handler [WEAK] 139 | B . 140 | ENDP 141 | HardFault_Handler\ 142 | PROC 143 | EXPORT HardFault_Handler [WEAK] 144 | B . 145 | ENDP 146 | MemManage_Handler\ 147 | PROC 148 | EXPORT MemManage_Handler [WEAK] 149 | B . 150 | ENDP 151 | BusFault_Handler\ 152 | PROC 153 | EXPORT BusFault_Handler [WEAK] 154 | B . 155 | ENDP 156 | UsageFault_Handler\ 157 | PROC 158 | EXPORT UsageFault_Handler [WEAK] 159 | B . 160 | ENDP 161 | SVC_Handler PROC 162 | EXPORT SVC_Handler [WEAK] 163 | B . 164 | ENDP 165 | DebugMon_Handler\ 166 | PROC 167 | EXPORT DebugMon_Handler [WEAK] 168 | B . 169 | ENDP 170 | PendSV_Handler PROC 171 | EXPORT PendSV_Handler [WEAK] 172 | B . 173 | ENDP 174 | SysTick_Handler PROC 175 | EXPORT SysTick_Handler [WEAK] 176 | B . 177 | ENDP 178 | 179 | Default_Handler PROC 180 | 181 | EXPORT WDT_IRQHandler [WEAK] 182 | EXPORT RTC_IRQHandler [WEAK] 183 | EXPORT TIM0_IRQHandler [WEAK] 184 | EXPORT TIM2_IRQHandler [WEAK] 185 | EXPORT MCIA_IRQHandler [WEAK] 186 | EXPORT MCIB_IRQHandler [WEAK] 187 | EXPORT UART0_IRQHandler [WEAK] 188 | EXPORT UART1_IRQHandler [WEAK] 189 | EXPORT UART2_IRQHandler [WEAK] 190 | EXPORT UART3_IRQHandler [WEAK] 191 | EXPORT UART4_IRQHandler [WEAK] 192 | EXPORT AACI_IRQHandler [WEAK] 193 | EXPORT CLCD_IRQHandler [WEAK] 194 | EXPORT ENET_IRQHandler [WEAK] 195 | EXPORT USBDC_IRQHandler [WEAK] 196 | EXPORT USBHC_IRQHandler [WEAK] 197 | EXPORT CHLCD_IRQHandler [WEAK] 198 | EXPORT FLEXRAY_IRQHandler [WEAK] 199 | EXPORT CAN_IRQHandler [WEAK] 200 | EXPORT LIN_IRQHandler [WEAK] 201 | EXPORT I2C_IRQHandler [WEAK] 202 | EXPORT CPU_CLCD_IRQHandler [WEAK] 203 | EXPORT SPI_IRQHandler [WEAK] 204 | 205 | WDT_IRQHandler 206 | RTC_IRQHandler 207 | TIM0_IRQHandler 208 | TIM2_IRQHandler 209 | MCIA_IRQHandler 210 | MCIB_IRQHandler 211 | UART0_IRQHandler 212 | UART1_IRQHandler 213 | UART2_IRQHandler 214 | UART3_IRQHandler 215 | UART4_IRQHandler 216 | AACI_IRQHandler 217 | CLCD_IRQHandler 218 | ENET_IRQHandler 219 | USBDC_IRQHandler 220 | USBHC_IRQHandler 221 | CHLCD_IRQHandler 222 | FLEXRAY_IRQHandler 223 | CAN_IRQHandler 224 | LIN_IRQHandler 225 | I2C_IRQHandler 226 | CPU_CLCD_IRQHandler 227 | SPI_IRQHandler 228 | B . 229 | 230 | ENDP 231 | 232 | 233 | ALIGN 234 | 235 | 236 | ; User Initial Stack & Heap 237 | 238 | IF :DEF:__MICROLIB 239 | 240 | EXPORT __initial_sp 241 | EXPORT __heap_base 242 | EXPORT __heap_limit 243 | 244 | ELSE 245 | 246 | IMPORT __use_two_region_memory 247 | EXPORT __user_initial_stackheap 248 | 249 | __user_initial_stackheap PROC 250 | LDR R0, = Heap_Mem 251 | LDR R1, =(Stack_Mem + Stack_Size) 252 | LDR R2, = (Heap_Mem + Heap_Size) 253 | LDR R3, = Stack_Mem 254 | BX LR 255 | ENDP 256 | 257 | ALIGN 258 | 259 | ENDIF 260 | 261 | 262 | END 263 | -------------------------------------------------------------------------------- /arm_nnexamples_cifar10/RTE/Device/ARMCM4_FP/system_ARMCM4.c: -------------------------------------------------------------------------------- 1 | /**************************************************************************//** 2 | * @file system_ARMCM4.c 3 | * @brief CMSIS Device System Source File for 4 | * ARMCM4 Device Series 5 | * @version V5.00 6 | * @date 08. April 2016 7 | ******************************************************************************/ 8 | /* 9 | * Copyright (c) 2009-2016 ARM Limited. All rights reserved. 10 | * 11 | * SPDX-License-Identifier: Apache-2.0 12 | * 13 | * Licensed under the Apache License, Version 2.0 (the License); you may 14 | * not use this file except in compliance with the License. 15 | * You may obtain a copy of the License at 16 | * 17 | * www.apache.org/licenses/LICENSE-2.0 18 | * 19 | * Unless required by applicable law or agreed to in writing, software 20 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT 21 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 | * See the License for the specific language governing permissions and 23 | * limitations under the License. 24 | */ 25 | 26 | #if defined (ARMCM4) 27 | #include "ARMCM4.h" 28 | #elif defined (ARMCM4_FP) 29 | #include "ARMCM4_FP.h" 30 | #else 31 | #error device not specified! 32 | #endif 33 | 34 | /*---------------------------------------------------------------------------- 35 | Define clocks 36 | *----------------------------------------------------------------------------*/ 37 | #define XTAL ( 5000000U) /* Oscillator frequency */ 38 | 39 | #define SYSTEM_CLOCK (5 * XTAL) 40 | 41 | 42 | /*---------------------------------------------------------------------------- 43 | Externals 44 | *----------------------------------------------------------------------------*/ 45 | #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1) 46 | extern uint32_t __Vectors; 47 | #endif 48 | 49 | /*---------------------------------------------------------------------------- 50 | System Core Clock Variable 51 | *----------------------------------------------------------------------------*/ 52 | uint32_t SystemCoreClock = SYSTEM_CLOCK; 53 | 54 | 55 | /*---------------------------------------------------------------------------- 56 | System Core Clock update function 57 | *----------------------------------------------------------------------------*/ 58 | void SystemCoreClockUpdate (void) 59 | { 60 | SystemCoreClock = SYSTEM_CLOCK; 61 | } 62 | 63 | /*---------------------------------------------------------------------------- 64 | System initialization function 65 | *----------------------------------------------------------------------------*/ 66 | void SystemInit (void) 67 | { 68 | 69 | #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1) 70 | SCB->VTOR = (uint32_t) &__Vectors; 71 | #endif 72 | 73 | #if defined (__FPU_USED) && (__FPU_USED == 1) 74 | SCB->CPACR |= ((3U << 10*2) | /* set CP10 Full Access */ 75 | (3U << 11*2) ); /* set CP11 Full Access */ 76 | #endif 77 | 78 | #ifdef UNALIGNED_SUPPORT_DISABLE 79 | SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; 80 | #endif 81 | 82 | SystemCoreClock = SYSTEM_CLOCK; 83 | } 84 | -------------------------------------------------------------------------------- /arm_nnexamples_cifar10/RTE/Device/ARMCM7_SP/gcc_arm.ld: -------------------------------------------------------------------------------- 1 | /* Linker script to configure memory regions. */ 2 | MEMORY 3 | { 4 | FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 512K 5 | RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 256K 6 | } 7 | 8 | /* Library configurations */ 9 | GROUP(libgcc.a libc.a libm.a libnosys.a) 10 | 11 | /* Linker script to place sections and symbol values. Should be used together 12 | * with other linker script that defines memory regions FLASH and RAM. 13 | * It references following symbols, which must be defined in code: 14 | * Reset_Handler : Entry of reset handler 15 | * 16 | * It defines following symbols, which code can use without definition: 17 | * __exidx_start 18 | * __exidx_end 19 | * __copy_table_start__ 20 | * __copy_table_end__ 21 | * __zero_table_start__ 22 | * __zero_table_end__ 23 | * __etext 24 | * __data_start__ 25 | * __preinit_array_start 26 | * __preinit_array_end 27 | * __init_array_start 28 | * __init_array_end 29 | * __fini_array_start 30 | * __fini_array_end 31 | * __data_end__ 32 | * __bss_start__ 33 | * __bss_end__ 34 | * __end__ 35 | * end 36 | * __HeapBase 37 | * __HeapLimit 38 | * __StackLimit 39 | * __StackTop 40 | * __stack 41 | * __Vectors_End 42 | * __Vectors_Size 43 | */ 44 | ENTRY(Reset_Handler) 45 | 46 | SECTIONS 47 | { 48 | .text : 49 | { 50 | KEEP(*(.vectors)) 51 | __Vectors_End = .; 52 | __Vectors_Size = __Vectors_End - __Vectors; 53 | __end__ = .; 54 | 55 | *(.text*) 56 | 57 | KEEP(*(.init)) 58 | KEEP(*(.fini)) 59 | 60 | /* .ctors */ 61 | *crtbegin.o(.ctors) 62 | *crtbegin?.o(.ctors) 63 | *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) 64 | *(SORT(.ctors.*)) 65 | *(.ctors) 66 | 67 | /* .dtors */ 68 | *crtbegin.o(.dtors) 69 | *crtbegin?.o(.dtors) 70 | *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) 71 | *(SORT(.dtors.*)) 72 | *(.dtors) 73 | 74 | *(.rodata*) 75 | 76 | KEEP(*(.eh_frame*)) 77 | } > FLASH 78 | 79 | .ARM.extab : 80 | { 81 | *(.ARM.extab* .gnu.linkonce.armextab.*) 82 | } > FLASH 83 | 84 | __exidx_start = .; 85 | .ARM.exidx : 86 | { 87 | *(.ARM.exidx* .gnu.linkonce.armexidx.*) 88 | } > FLASH 89 | __exidx_end = .; 90 | 91 | /* To copy multiple ROM to RAM sections, 92 | * uncomment .copy.table section and, 93 | * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */ 94 | /* 95 | .copy.table : 96 | { 97 | . = ALIGN(4); 98 | __copy_table_start__ = .; 99 | LONG (__etext) 100 | LONG (__data_start__) 101 | LONG (__data_end__ - __data_start__) 102 | LONG (__etext2) 103 | LONG (__data2_start__) 104 | LONG (__data2_end__ - __data2_start__) 105 | __copy_table_end__ = .; 106 | } > FLASH 107 | */ 108 | 109 | /* To clear multiple BSS sections, 110 | * uncomment .zero.table section and, 111 | * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */ 112 | /* 113 | .zero.table : 114 | { 115 | . = ALIGN(4); 116 | __zero_table_start__ = .; 117 | LONG (__bss_start__) 118 | LONG (__bss_end__ - __bss_start__) 119 | LONG (__bss2_start__) 120 | LONG (__bss2_end__ - __bss2_start__) 121 | __zero_table_end__ = .; 122 | } > FLASH 123 | */ 124 | 125 | __etext = .; 126 | 127 | .data : AT (__etext) 128 | { 129 | __data_start__ = .; 130 | *(vtable) 131 | *(.data*) 132 | 133 | . = ALIGN(4); 134 | /* preinit data */ 135 | PROVIDE_HIDDEN (__preinit_array_start = .); 136 | KEEP(*(.preinit_array)) 137 | PROVIDE_HIDDEN (__preinit_array_end = .); 138 | 139 | . = ALIGN(4); 140 | /* init data */ 141 | PROVIDE_HIDDEN (__init_array_start = .); 142 | KEEP(*(SORT(.init_array.*))) 143 | KEEP(*(.init_array)) 144 | PROVIDE_HIDDEN (__init_array_end = .); 145 | 146 | 147 | . = ALIGN(4); 148 | /* finit data */ 149 | PROVIDE_HIDDEN (__fini_array_start = .); 150 | KEEP(*(SORT(.fini_array.*))) 151 | KEEP(*(.fini_array)) 152 | PROVIDE_HIDDEN (__fini_array_end = .); 153 | 154 | KEEP(*(.jcr*)) 155 | . = ALIGN(4); 156 | /* All data end */ 157 | __data_end__ = .; 158 | 159 | } > RAM 160 | 161 | .bss : 162 | { 163 | . = ALIGN(4); 164 | __bss_start__ = .; 165 | *(.bss*) 166 | *(COMMON) 167 | . = ALIGN(4); 168 | __bss_end__ = .; 169 | } > RAM 170 | 171 | .heap (COPY): 172 | { 173 | __HeapBase = .; 174 | __end__ = .; 175 | end = __end__; 176 | KEEP(*(.heap*)) 177 | __HeapLimit = .; 178 | } > RAM 179 | 180 | /* .stack_dummy section doesn't contains any symbols. It is only 181 | * used for linker to calculate size of stack sections, and assign 182 | * values to stack symbols later */ 183 | .stack_dummy (COPY): 184 | { 185 | KEEP(*(.stack*)) 186 | } > RAM 187 | 188 | /* Set stack top to end of RAM, and stack limit move down by 189 | * size of stack_dummy section */ 190 | __StackTop = ORIGIN(RAM) + LENGTH(RAM); 191 | __StackLimit = __StackTop - SIZEOF(.stack_dummy); 192 | PROVIDE(__stack = __StackTop); 193 | 194 | /* Check if data + heap + stack exceeds RAM limit */ 195 | ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") 196 | } 197 | -------------------------------------------------------------------------------- /arm_nnexamples_cifar10/RTE/Device/ARMCM7_SP/startup_ARMCM7.c: -------------------------------------------------------------------------------- 1 | /**************************************************************************//** 2 | * @file startup_ARMCM7.s 3 | * @brief CMSIS Core Device Startup File for 4 | * ARMCM7 Device Series 5 | * @version V5.00 6 | * @date 26. April 2016 7 | ******************************************************************************/ 8 | /* 9 | * Copyright (c) 2009-2016 ARM Limited. All rights reserved. 10 | * 11 | * SPDX-License-Identifier: Apache-2.0 12 | * 13 | * Licensed under the Apache License, Version 2.0 (the License); you may 14 | * not use this file except in compliance with the License. 15 | * You may obtain a copy of the License at 16 | * 17 | * www.apache.org/licenses/LICENSE-2.0 18 | * 19 | * Unless required by applicable law or agreed to in writing, software 20 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT 21 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 | * See the License for the specific language governing permissions and 23 | * limitations under the License. 24 | */ 25 | 26 | #include 27 | 28 | 29 | /*---------------------------------------------------------------------------- 30 | Linker generated Symbols 31 | *----------------------------------------------------------------------------*/ 32 | extern uint32_t __etext; 33 | extern uint32_t __data_start__; 34 | extern uint32_t __data_end__; 35 | extern uint32_t __copy_table_start__; 36 | extern uint32_t __copy_table_end__; 37 | extern uint32_t __zero_table_start__; 38 | extern uint32_t __zero_table_end__; 39 | extern uint32_t __bss_start__; 40 | extern uint32_t __bss_end__; 41 | extern uint32_t __StackTop; 42 | 43 | /*---------------------------------------------------------------------------- 44 | Exception / Interrupt Handler Function Prototype 45 | *----------------------------------------------------------------------------*/ 46 | typedef void( *pFunc )( void ); 47 | 48 | 49 | /*---------------------------------------------------------------------------- 50 | External References 51 | *----------------------------------------------------------------------------*/ 52 | #ifndef __START 53 | extern void _start(void) __attribute__((noreturn)); /* PreeMain (C library entry point) */ 54 | #else 55 | extern int __START(void) __attribute__((noreturn)); /* main entry point */ 56 | #endif 57 | 58 | #ifndef __NO_SYSTEM_INIT 59 | extern void SystemInit (void); /* CMSIS System Initialization */ 60 | #endif 61 | 62 | 63 | /*---------------------------------------------------------------------------- 64 | Internal References 65 | *----------------------------------------------------------------------------*/ 66 | void Default_Handler(void); /* Default empty handler */ 67 | void Reset_Handler(void); /* Reset Handler */ 68 | 69 | 70 | /*---------------------------------------------------------------------------- 71 | User Initial Stack & Heap 72 | *----------------------------------------------------------------------------*/ 73 | #ifndef __STACK_SIZE 74 | #define __STACK_SIZE 0x00000400 75 | #endif 76 | static uint8_t stack[__STACK_SIZE] __attribute__ ((aligned(8), used, section(".stack"))); 77 | 78 | #ifndef __HEAP_SIZE 79 | #define __HEAP_SIZE 0x00000C00 80 | #endif 81 | #if __HEAP_SIZE > 0 82 | static uint8_t heap[__HEAP_SIZE] __attribute__ ((aligned(8), used, section(".heap"))); 83 | #endif 84 | 85 | 86 | /*---------------------------------------------------------------------------- 87 | Exception / Interrupt Handler 88 | *----------------------------------------------------------------------------*/ 89 | /* Cortex-M7 Processor Exceptions */ 90 | void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); 91 | void HardFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); 92 | void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); 93 | void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); 94 | void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); 95 | void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); 96 | void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); 97 | void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); 98 | void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); 99 | 100 | /* ARMCM7 Specific Interrupts */ 101 | void WDT_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); 102 | void RTC_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); 103 | void TIM0_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); 104 | void TIM2_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); 105 | void MCIA_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); 106 | void MCIB_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); 107 | void UART0_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); 108 | void UART1_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); 109 | void UART2_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); 110 | void UART4_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); 111 | void AACI_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); 112 | void CLCD_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); 113 | void ENET_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); 114 | void USBDC_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); 115 | void USBHC_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); 116 | void CHLCD_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); 117 | void FLEXRAY_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); 118 | void CAN_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); 119 | void LIN_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); 120 | void I2C_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); 121 | void CPU_CLCD_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); 122 | void UART3_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); 123 | void SPI_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); 124 | 125 | 126 | /*---------------------------------------------------------------------------- 127 | Exception / Interrupt Vector table 128 | *----------------------------------------------------------------------------*/ 129 | const pFunc __Vectors[] __attribute__ ((section(".vectors"))) = { 130 | /* Cortex-M7 Exceptions Handler */ 131 | (pFunc)((uint32_t)&__StackTop), /* Initial Stack Pointer */ 132 | Reset_Handler, /* Reset Handler */ 133 | NMI_Handler, /* NMI Handler */ 134 | HardFault_Handler, /* Hard Fault Handler */ 135 | MemManage_Handler, /* MPU Fault Handler */ 136 | BusFault_Handler, /* Bus Fault Handler */ 137 | UsageFault_Handler, /* Usage Fault Handler */ 138 | 0, /* Reserved */ 139 | 0, /* Reserved */ 140 | 0, /* Reserved */ 141 | 0, /* Reserved */ 142 | SVC_Handler, /* SVCall Handler */ 143 | DebugMon_Handler, /* Debug Monitor Handler */ 144 | 0, /* Reserved */ 145 | PendSV_Handler, /* PendSV Handler */ 146 | SysTick_Handler, /* SysTick Handler */ 147 | 148 | /* External interrupts */ 149 | WDT_IRQHandler, /* 0: Watchdog Timer */ 150 | RTC_IRQHandler, /* 1: Real Time Clock */ 151 | TIM0_IRQHandler, /* 2: Timer0 / Timer1 */ 152 | TIM2_IRQHandler, /* 3: Timer2 / Timer3 */ 153 | MCIA_IRQHandler, /* 4: MCIa */ 154 | MCIB_IRQHandler, /* 5: MCIb */ 155 | UART0_IRQHandler, /* 6: UART0 - DUT FPGA */ 156 | UART1_IRQHandler, /* 7: UART1 - DUT FPGA */ 157 | UART2_IRQHandler, /* 8: UART2 - DUT FPGA */ 158 | UART4_IRQHandler, /* 9: UART4 - not connected */ 159 | AACI_IRQHandler, /* 10: AACI / AC97 */ 160 | CLCD_IRQHandler, /* 11: CLCD Combined Interrupt */ 161 | ENET_IRQHandler, /* 12: Ethernet */ 162 | USBDC_IRQHandler, /* 13: USB Device */ 163 | USBHC_IRQHandler, /* 14: USB Host Controller */ 164 | CHLCD_IRQHandler, /* 15: Character LCD */ 165 | FLEXRAY_IRQHandler, /* 16: Flexray */ 166 | CAN_IRQHandler, /* 17: CAN */ 167 | LIN_IRQHandler, /* 18: LIN */ 168 | I2C_IRQHandler, /* 19: I2C ADC/DAC */ 169 | 0, /* 20: Reserved */ 170 | 0, /* 21: Reserved */ 171 | 0, /* 22: Reserved */ 172 | 0, /* 23: Reserved */ 173 | 0, /* 24: Reserved */ 174 | 0, /* 25: Reserved */ 175 | 0, /* 26: Reserved */ 176 | 0, /* 27: Reserved */ 177 | CPU_CLCD_IRQHandler, /* 28: Reserved - CPU FPGA CLCD */ 178 | 0, /* 29: Reserved - CPU FPGA */ 179 | UART3_IRQHandler, /* 30: UART3 - CPU FPGA */ 180 | SPI_IRQHandler /* 31: SPI Touchscreen - CPU FPGA */ 181 | }; 182 | 183 | 184 | /*---------------------------------------------------------------------------- 185 | Reset Handler called on controller reset 186 | *----------------------------------------------------------------------------*/ 187 | void Reset_Handler(void) { 188 | uint32_t *pSrc, *pDest; 189 | uint32_t *pTable __attribute__((unused)); 190 | 191 | /* Firstly it copies data from read only memory to RAM. There are two schemes 192 | * to copy. One can copy more than one sections. Another can only copy 193 | * one section. The former scheme needs more instructions and read-only 194 | * data to implement than the latter. 195 | * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */ 196 | 197 | #ifdef __STARTUP_COPY_MULTIPLE 198 | /* Multiple sections scheme. 199 | * 200 | * Between symbol address __copy_table_start__ and __copy_table_end__, 201 | * there are array of triplets, each of which specify: 202 | * offset 0: LMA of start of a section to copy from 203 | * offset 4: VMA of start of a section to copy to 204 | * offset 8: size of the section to copy. Must be multiply of 4 205 | * 206 | * All addresses must be aligned to 4 bytes boundary. 207 | */ 208 | pTable = &__copy_table_start__; 209 | 210 | for (; pTable < &__copy_table_end__; pTable = pTable + 3) { 211 | pSrc = (uint32_t*)*(pTable + 0); 212 | pDest = (uint32_t*)*(pTable + 1); 213 | for (; pDest < (uint32_t*)(*(pTable + 1) + *(pTable + 2)) ; ) { 214 | *pDest++ = *pSrc++; 215 | } 216 | } 217 | #else 218 | /* Single section scheme. 219 | * 220 | * The ranges of copy from/to are specified by following symbols 221 | * __etext: LMA of start of the section to copy from. Usually end of text 222 | * __data_start__: VMA of start of the section to copy to 223 | * __data_end__: VMA of end of the section to copy to 224 | * 225 | * All addresses must be aligned to 4 bytes boundary. 226 | */ 227 | pSrc = &__etext; 228 | pDest = &__data_start__; 229 | 230 | for ( ; pDest < &__data_end__ ; ) { 231 | *pDest++ = *pSrc++; 232 | } 233 | #endif /*__STARTUP_COPY_MULTIPLE */ 234 | 235 | /* This part of work usually is done in C library startup code. Otherwise, 236 | * define this macro to enable it in this startup. 237 | * 238 | * There are two schemes too. One can clear multiple BSS sections. Another 239 | * can only clear one section. The former is more size expensive than the 240 | * latter. 241 | * 242 | * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former. 243 | * Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later. 244 | */ 245 | #ifdef __STARTUP_CLEAR_BSS_MULTIPLE 246 | /* Multiple sections scheme. 247 | * 248 | * Between symbol address __copy_table_start__ and __copy_table_end__, 249 | * there are array of tuples specifying: 250 | * offset 0: Start of a BSS section 251 | * offset 4: Size of this BSS section. Must be multiply of 4 252 | */ 253 | pTable = &__zero_table_start__; 254 | 255 | for (; pTable < &__zero_table_end__; pTable = pTable + 2) { 256 | pDest = (uint32_t*)*(pTable + 0); 257 | for (; pDest < (uint32_t*)(*(pTable + 0) + *(pTable + 1)) ; ) { 258 | *pDest++ = 0; 259 | } 260 | } 261 | #elif defined (__STARTUP_CLEAR_BSS) 262 | /* Single BSS section scheme. 263 | * 264 | * The BSS section is specified by following symbols 265 | * __bss_start__: start of the BSS section. 266 | * __bss_end__: end of the BSS section. 267 | * 268 | * Both addresses must be aligned to 4 bytes boundary. 269 | */ 270 | pDest = &__bss_start__; 271 | 272 | for ( ; pDest < &__bss_end__ ; ) { 273 | *pDest++ = 0UL; 274 | } 275 | #endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */ 276 | 277 | #ifndef __NO_SYSTEM_INIT 278 | SystemInit(); 279 | #endif 280 | 281 | #ifndef __START 282 | #define __START _start 283 | #endif 284 | __START(); 285 | 286 | } 287 | 288 | 289 | /*---------------------------------------------------------------------------- 290 | Default Handler for Exceptions / Interrupts 291 | *----------------------------------------------------------------------------*/ 292 | void Default_Handler(void) { 293 | 294 | while(1); 295 | } 296 | -------------------------------------------------------------------------------- /arm_nnexamples_cifar10/RTE/Device/ARMCM7_SP/startup_ARMCM7.s: -------------------------------------------------------------------------------- 1 | ;/**************************************************************************//** 2 | ; * @file startup_ARMCM7.s 3 | ; * @brief CMSIS Core Device Startup File for 4 | ; * ARMCM7 Device Series 5 | ; * @version V5.00 6 | ; * @date 02. March 2016 7 | ; ******************************************************************************/ 8 | ;/* 9 | ; * Copyright (c) 2009-2016 ARM Limited. All rights reserved. 10 | ; * 11 | ; * SPDX-License-Identifier: Apache-2.0 12 | ; * 13 | ; * Licensed under the Apache License, Version 2.0 (the License); you may 14 | ; * not use this file except in compliance with the License. 15 | ; * You may obtain a copy of the License at 16 | ; * 17 | ; * www.apache.org/licenses/LICENSE-2.0 18 | ; * 19 | ; * Unless required by applicable law or agreed to in writing, software 20 | ; * distributed under the License is distributed on an AS IS BASIS, WITHOUT 21 | ; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 | ; * See the License for the specific language governing permissions and 23 | ; * limitations under the License. 24 | ; */ 25 | 26 | ;/* 27 | ;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ 28 | ;*/ 29 | 30 | 31 | ; Stack Configuration 32 | ; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> 33 | ; 34 | 35 | Stack_Size EQU 0x00000400 36 | 37 | AREA STACK, NOINIT, READWRITE, ALIGN=3 38 | Stack_Mem SPACE Stack_Size 39 | __initial_sp 40 | 41 | 42 | ; Heap Configuration 43 | ; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> 44 | ; 45 | 46 | Heap_Size EQU 0x00000C00 47 | 48 | AREA HEAP, NOINIT, READWRITE, ALIGN=3 49 | __heap_base 50 | Heap_Mem SPACE Heap_Size 51 | __heap_limit 52 | 53 | 54 | PRESERVE8 55 | THUMB 56 | 57 | 58 | ; Vector Table Mapped to Address 0 at Reset 59 | 60 | AREA RESET, DATA, READONLY 61 | EXPORT __Vectors 62 | EXPORT __Vectors_End 63 | EXPORT __Vectors_Size 64 | 65 | __Vectors DCD __initial_sp ; Top of Stack 66 | DCD Reset_Handler ; Reset Handler 67 | DCD NMI_Handler ; NMI Handler 68 | DCD HardFault_Handler ; Hard Fault Handler 69 | DCD MemManage_Handler ; MPU Fault Handler 70 | DCD BusFault_Handler ; Bus Fault Handler 71 | DCD UsageFault_Handler ; Usage Fault Handler 72 | DCD 0 ; Reserved 73 | DCD 0 ; Reserved 74 | DCD 0 ; Reserved 75 | DCD 0 ; Reserved 76 | DCD SVC_Handler ; SVCall Handler 77 | DCD DebugMon_Handler ; Debug Monitor Handler 78 | DCD 0 ; Reserved 79 | DCD PendSV_Handler ; PendSV Handler 80 | DCD SysTick_Handler ; SysTick Handler 81 | 82 | ; External Interrupts 83 | DCD WDT_IRQHandler ; 0: Watchdog Timer 84 | DCD RTC_IRQHandler ; 1: Real Time Clock 85 | DCD TIM0_IRQHandler ; 2: Timer0 / Timer1 86 | DCD TIM2_IRQHandler ; 3: Timer2 / Timer3 87 | DCD MCIA_IRQHandler ; 4: MCIa 88 | DCD MCIB_IRQHandler ; 5: MCIb 89 | DCD UART0_IRQHandler ; 6: UART0 - DUT FPGA 90 | DCD UART1_IRQHandler ; 7: UART1 - DUT FPGA 91 | DCD UART2_IRQHandler ; 8: UART2 - DUT FPGA 92 | DCD UART4_IRQHandler ; 9: UART4 - not connected 93 | DCD AACI_IRQHandler ; 10: AACI / AC97 94 | DCD CLCD_IRQHandler ; 11: CLCD Combined Interrupt 95 | DCD ENET_IRQHandler ; 12: Ethernet 96 | DCD USBDC_IRQHandler ; 13: USB Device 97 | DCD USBHC_IRQHandler ; 14: USB Host Controller 98 | DCD CHLCD_IRQHandler ; 15: Character LCD 99 | DCD FLEXRAY_IRQHandler ; 16: Flexray 100 | DCD CAN_IRQHandler ; 17: CAN 101 | DCD LIN_IRQHandler ; 18: LIN 102 | DCD I2C_IRQHandler ; 19: I2C ADC/DAC 103 | DCD 0 ; 20: Reserved 104 | DCD 0 ; 21: Reserved 105 | DCD 0 ; 22: Reserved 106 | DCD 0 ; 23: Reserved 107 | DCD 0 ; 24: Reserved 108 | DCD 0 ; 25: Reserved 109 | DCD 0 ; 26: Reserved 110 | DCD 0 ; 27: Reserved 111 | DCD CPU_CLCD_IRQHandler ; 28: Reserved - CPU FPGA CLCD 112 | DCD 0 ; 29: Reserved - CPU FPGA 113 | DCD UART3_IRQHandler ; 30: UART3 - CPU FPGA 114 | DCD SPI_IRQHandler ; 31: SPI Touchscreen - CPU FPGA 115 | __Vectors_End 116 | 117 | __Vectors_Size EQU __Vectors_End - __Vectors 118 | 119 | AREA |.text|, CODE, READONLY 120 | 121 | 122 | ; Reset Handler 123 | 124 | Reset_Handler PROC 125 | EXPORT Reset_Handler [WEAK] 126 | IMPORT SystemInit 127 | IMPORT __main 128 | LDR R0, =SystemInit 129 | BLX R0 130 | LDR R0, =__main 131 | BX R0 132 | ENDP 133 | 134 | 135 | ; Dummy Exception Handlers (infinite loops which can be modified) 136 | 137 | NMI_Handler PROC 138 | EXPORT NMI_Handler [WEAK] 139 | B . 140 | ENDP 141 | HardFault_Handler\ 142 | PROC 143 | EXPORT HardFault_Handler [WEAK] 144 | B . 145 | ENDP 146 | MemManage_Handler\ 147 | PROC 148 | EXPORT MemManage_Handler [WEAK] 149 | B . 150 | ENDP 151 | BusFault_Handler\ 152 | PROC 153 | EXPORT BusFault_Handler [WEAK] 154 | B . 155 | ENDP 156 | UsageFault_Handler\ 157 | PROC 158 | EXPORT UsageFault_Handler [WEAK] 159 | B . 160 | ENDP 161 | SVC_Handler PROC 162 | EXPORT SVC_Handler [WEAK] 163 | B . 164 | ENDP 165 | DebugMon_Handler\ 166 | PROC 167 | EXPORT DebugMon_Handler [WEAK] 168 | B . 169 | ENDP 170 | PendSV_Handler PROC 171 | EXPORT PendSV_Handler [WEAK] 172 | B . 173 | ENDP 174 | SysTick_Handler PROC 175 | EXPORT SysTick_Handler [WEAK] 176 | B . 177 | ENDP 178 | 179 | Default_Handler PROC 180 | 181 | EXPORT WDT_IRQHandler [WEAK] 182 | EXPORT RTC_IRQHandler [WEAK] 183 | EXPORT TIM0_IRQHandler [WEAK] 184 | EXPORT TIM2_IRQHandler [WEAK] 185 | EXPORT MCIA_IRQHandler [WEAK] 186 | EXPORT MCIB_IRQHandler [WEAK] 187 | EXPORT UART0_IRQHandler [WEAK] 188 | EXPORT UART1_IRQHandler [WEAK] 189 | EXPORT UART2_IRQHandler [WEAK] 190 | EXPORT UART3_IRQHandler [WEAK] 191 | EXPORT UART4_IRQHandler [WEAK] 192 | EXPORT AACI_IRQHandler [WEAK] 193 | EXPORT CLCD_IRQHandler [WEAK] 194 | EXPORT ENET_IRQHandler [WEAK] 195 | EXPORT USBDC_IRQHandler [WEAK] 196 | EXPORT USBHC_IRQHandler [WEAK] 197 | EXPORT CHLCD_IRQHandler [WEAK] 198 | EXPORT FLEXRAY_IRQHandler [WEAK] 199 | EXPORT CAN_IRQHandler [WEAK] 200 | EXPORT LIN_IRQHandler [WEAK] 201 | EXPORT I2C_IRQHandler [WEAK] 202 | EXPORT CPU_CLCD_IRQHandler [WEAK] 203 | EXPORT SPI_IRQHandler [WEAK] 204 | 205 | WDT_IRQHandler 206 | RTC_IRQHandler 207 | TIM0_IRQHandler 208 | TIM2_IRQHandler 209 | MCIA_IRQHandler 210 | MCIB_IRQHandler 211 | UART0_IRQHandler 212 | UART1_IRQHandler 213 | UART2_IRQHandler 214 | UART3_IRQHandler 215 | UART4_IRQHandler 216 | AACI_IRQHandler 217 | CLCD_IRQHandler 218 | ENET_IRQHandler 219 | USBDC_IRQHandler 220 | USBHC_IRQHandler 221 | CHLCD_IRQHandler 222 | FLEXRAY_IRQHandler 223 | CAN_IRQHandler 224 | LIN_IRQHandler 225 | I2C_IRQHandler 226 | CPU_CLCD_IRQHandler 227 | SPI_IRQHandler 228 | B . 229 | 230 | ENDP 231 | 232 | 233 | ALIGN 234 | 235 | 236 | ; User Initial Stack & Heap 237 | 238 | IF :DEF:__MICROLIB 239 | 240 | EXPORT __initial_sp 241 | EXPORT __heap_base 242 | EXPORT __heap_limit 243 | 244 | ELSE 245 | 246 | IMPORT __use_two_region_memory 247 | EXPORT __user_initial_stackheap 248 | 249 | __user_initial_stackheap PROC 250 | LDR R0, = Heap_Mem 251 | LDR R1, =(Stack_Mem + Stack_Size) 252 | LDR R2, = (Heap_Mem + Heap_Size) 253 | LDR R3, = Stack_Mem 254 | BX LR 255 | ENDP 256 | 257 | ALIGN 258 | 259 | ENDIF 260 | 261 | 262 | END 263 | -------------------------------------------------------------------------------- /arm_nnexamples_cifar10/RTE/Device/ARMCM7_SP/system_ARMCM7.c: -------------------------------------------------------------------------------- 1 | /**************************************************************************//** 2 | * @file system_ARMCM7.c 3 | * @brief CMSIS Device System Source File for 4 | * ARMCM7 Device Series 5 | * @version V5.00 6 | * @date 08. April 2016 7 | ******************************************************************************/ 8 | /* 9 | * Copyright (c) 2009-2016 ARM Limited. All rights reserved. 10 | * 11 | * SPDX-License-Identifier: Apache-2.0 12 | * 13 | * Licensed under the Apache License, Version 2.0 (the License); you may 14 | * not use this file except in compliance with the License. 15 | * You may obtain a copy of the License at 16 | * 17 | * www.apache.org/licenses/LICENSE-2.0 18 | * 19 | * Unless required by applicable law or agreed to in writing, software 20 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT 21 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 | * See the License for the specific language governing permissions and 23 | * limitations under the License. 24 | */ 25 | 26 | #if defined (ARMCM7) 27 | #include "ARMCM7.h" 28 | #elif defined (ARMCM7_SP) 29 | #include "ARMCM7_SP.h" 30 | #elif defined (ARMCM7_DP) 31 | #include "ARMCM7_DP.h" 32 | #else 33 | #error device not specified! 34 | #endif 35 | 36 | /*---------------------------------------------------------------------------- 37 | Define clocks 38 | *----------------------------------------------------------------------------*/ 39 | #define XTAL ( 5000000U) /* Oscillator frequency */ 40 | 41 | #define SYSTEM_CLOCK (5 * XTAL) 42 | 43 | 44 | /*---------------------------------------------------------------------------- 45 | Externals 46 | *----------------------------------------------------------------------------*/ 47 | #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1) 48 | extern uint32_t __Vectors; 49 | #endif 50 | 51 | /*---------------------------------------------------------------------------- 52 | System Core Clock Variable 53 | *----------------------------------------------------------------------------*/ 54 | uint32_t SystemCoreClock = SYSTEM_CLOCK; 55 | 56 | 57 | /*---------------------------------------------------------------------------- 58 | System Core Clock update function 59 | *----------------------------------------------------------------------------*/ 60 | void SystemCoreClockUpdate (void) 61 | { 62 | SystemCoreClock = SYSTEM_CLOCK; 63 | } 64 | 65 | /*---------------------------------------------------------------------------- 66 | System initialization function 67 | *----------------------------------------------------------------------------*/ 68 | void SystemInit (void) 69 | { 70 | 71 | #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1) 72 | SCB->VTOR = (uint32_t) &__Vectors; 73 | #endif 74 | 75 | #if defined (__FPU_USED) && (__FPU_USED == 1) 76 | SCB->CPACR |= ((3U << 10*2) | /* set CP10 Full Access */ 77 | (3U << 11*2) ); /* set CP11 Full Access */ 78 | #endif 79 | 80 | #ifdef UNALIGNED_SUPPORT_DISABLE 81 | SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; 82 | #endif 83 | 84 | SystemCoreClock = SYSTEM_CLOCK; 85 | } 86 | -------------------------------------------------------------------------------- /arm_nnexamples_cifar10/RTE/_ARMCM0/RTE_Components.h: -------------------------------------------------------------------------------- 1 | 2 | /* 3 | * Auto generated Run-Time-Environment Component Configuration File 4 | * *** Do not modify ! *** 5 | * 6 | * Project: 'arm_nnexamples_cifar10' 7 | * Target: 'ARMCM0' 8 | */ 9 | 10 | #ifndef RTE_COMPONENTS_H 11 | #define RTE_COMPONENTS_H 12 | 13 | 14 | /* 15 | * Define the Device Header File: 16 | */ 17 | #define CMSIS_device_header "ARMCM0.h" 18 | 19 | #define RTE_Compiler_EventRecorder 20 | #define RTE_Compiler_EventRecorder_DAP 21 | #define RTE_Compiler_IO_STDOUT /* Compiler I/O: STDOUT */ 22 | #define RTE_Compiler_IO_STDOUT_EVR /* Compiler I/O: STDOUT EVR */ 23 | 24 | #endif /* RTE_COMPONENTS_H */ 25 | -------------------------------------------------------------------------------- /arm_nnexamples_cifar10/RTE/_ARMCM3/RTE_Components.h: -------------------------------------------------------------------------------- 1 | 2 | /* 3 | * Auto generated Run-Time-Environment Component Configuration File 4 | * *** Do not modify ! *** 5 | * 6 | * Project: 'arm_nnexamples_cifar10' 7 | * Target: 'ARMCM3' 8 | */ 9 | 10 | #ifndef RTE_COMPONENTS_H 11 | #define RTE_COMPONENTS_H 12 | 13 | 14 | /* 15 | * Define the Device Header File: 16 | */ 17 | #define CMSIS_device_header "ARMCM3.h" 18 | 19 | #define RTE_Compiler_IO_STDOUT /* Compiler I/O: STDOUT */ 20 | #define RTE_Compiler_IO_STDOUT_ITM /* Compiler I/O: STDOUT ITM */ 21 | 22 | #endif /* RTE_COMPONENTS_H */ 23 | -------------------------------------------------------------------------------- /arm_nnexamples_cifar10/RTE/_ARMCM4_FP/RTE_Components.h: -------------------------------------------------------------------------------- 1 | 2 | /* 3 | * Auto generated Run-Time-Environment Component Configuration File 4 | * *** Do not modify ! *** 5 | * 6 | * Project: 'arm_nnexamples_cifar10' 7 | * Target: 'ARMCM4_FP' 8 | */ 9 | 10 | #ifndef RTE_COMPONENTS_H 11 | #define RTE_COMPONENTS_H 12 | 13 | 14 | /* 15 | * Define the Device Header File: 16 | */ 17 | #define CMSIS_device_header "ARMCM4_FP.h" 18 | 19 | #define RTE_Compiler_IO_STDOUT /* Compiler I/O: STDOUT */ 20 | #define RTE_Compiler_IO_STDOUT_ITM /* Compiler I/O: STDOUT ITM */ 21 | 22 | #endif /* RTE_COMPONENTS_H */ 23 | -------------------------------------------------------------------------------- /arm_nnexamples_cifar10/RTE/_ARMCM7_SP/RTE_Components.h: -------------------------------------------------------------------------------- 1 | 2 | /* 3 | * Auto generated Run-Time-Environment Configuration File 4 | * *** Do not modify ! *** 5 | * 6 | * Project: 'arm_nnexamples_cifar10' 7 | * Target: 'ARMCM7_SP' 8 | */ 9 | 10 | #ifndef RTE_COMPONENTS_H 11 | #define RTE_COMPONENTS_H 12 | 13 | 14 | /* 15 | * Define the Device Header File: 16 | */ 17 | #define CMSIS_device_header "ARMCM7_SP.h" 18 | 19 | /* Keil.ARM Compiler::Compiler:I/O:STDOUT:ITM:1.2.0 */ 20 | #define RTE_Compiler_IO_STDOUT /* Compiler I/O: STDOUT */ 21 | #define RTE_Compiler_IO_STDOUT_ITM /* Compiler I/O: STDOUT ITM */ 22 | 23 | 24 | #endif /* RTE_COMPONENTS_H */ 25 | -------------------------------------------------------------------------------- /arm_nnexamples_cifar10/arm_nnexamples_cifar10.uvoptx: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 1.0 5 | 6 |
### uVision Project, (C) Keil Software
7 | 8 | 9 | *.c 10 | *.s*; *.src; *.a* 11 | *.obj; *.o 12 | *.lib 13 | *.txt; *.h; *.inc 14 | *.plm 15 | *.cpp 16 | 0 17 | 18 | 19 | 20 | 0 21 | 0 22 | 23 | 24 | 25 | ARMCM0 26 | 0x4 27 | ARM-ADS 28 | 29 | 10000000 30 | 31 | 1 32 | 1 33 | 0 34 | 1 35 | 0 36 | 37 | 38 | 1 39 | 65535 40 | 0 41 | 0 42 | 0 43 | 44 | 45 | 79 46 | 66 47 | 8 48 | .\ARMCM0_debug\ 49 | 50 | 51 | 1 52 | 1 53 | 1 54 | 0 55 | 1 56 | 1 57 | 0 58 | 1 59 | 0 60 | 0 61 | 0 62 | 0 63 | 64 | 65 | 1 66 | 1 67 | 1 68 | 1 69 | 1 70 | 1 71 | 1 72 | 0 73 | 0 74 | 75 | 76 | 1 77 | 0 78 | 0 79 | 80 | 7 81 | 82 | 1 83 | 0 84 | 1 85 | 1 86 | 1 87 | 1 88 | 1 89 | 1 90 | 1 91 | 1 92 | 1 93 | 1 94 | 1 95 | 1 96 | 0 97 | 1 98 | 0 99 | 1 100 | 1 101 | 0 102 | 0 103 | 1 104 | 0 105 | 0 106 | 0 107 | 108 | 109 | 110 | 111 | 112 | 113 | 114 | 115 | 116 | 117 | BIN\UL2CM3.DLL 118 | 119 | 120 | 121 | 0 122 | ARMRTXEVENTFLAGS 123 | -L70 -Z18 -C0 -M0 -T1 124 | 125 | 126 | 0 127 | UL2CM3 128 | UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0NEW_DEVICE -FS00 -FL040000 -FP0($$Device:ARMCM0$Device\ARM\Flash\NEW_DEVICE.FLM)) 129 | 130 | 131 | 0 132 | DLGDARM 133 | (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) 134 | 135 | 136 | 0 137 | ARMDBGFLAGS 138 | -T0 139 | 140 | 141 | 142 | 143 | C:\KEIL_V5\ARM\PACK\Keil\ARM_Compiler\1.3.3\EventRecorder.scvd 144 | Keil.ARM_Compiler.1.3.3 145 | 1 146 | 147 | 148 | 0 149 | 150 | 151 | 0 152 | 0 153 | 1 154 | 0 155 | 0 156 | 0 157 | 0 158 | 1 159 | 0 160 | 0 161 | 0 162 | 0 163 | 0 164 | 0 165 | 0 166 | 0 167 | 0 168 | 0 169 | 0 170 | 1 171 | 0 172 | 0 173 | 0 174 | 0 175 | 176 | 177 | 178 | 0 179 | 0 180 | 0 181 | 182 | 183 | 184 | 185 | 186 | 187 | 188 | 189 | 190 | 191 | 192 | 193 | ARMCM3 194 | 0x4 195 | ARM-ADS 196 | 197 | 10000000 198 | 199 | 1 200 | 1 201 | 0 202 | 1 203 | 0 204 | 205 | 206 | 1 207 | 65535 208 | 0 209 | 0 210 | 0 211 | 212 | 213 | 79 214 | 66 215 | 8 216 | .\ARMCM3_debug\ 217 | 218 | 219 | 1 220 | 1 221 | 1 222 | 0 223 | 1 224 | 1 225 | 0 226 | 1 227 | 0 228 | 0 229 | 0 230 | 0 231 | 232 | 233 | 1 234 | 1 235 | 1 236 | 1 237 | 1 238 | 1 239 | 1 240 | 0 241 | 0 242 | 243 | 244 | 1 245 | 0 246 | 0 247 | 248 | 7 249 | 250 | 1 251 | 0 252 | 1 253 | 1 254 | 1 255 | 1 256 | 1 257 | 1 258 | 1 259 | 1 260 | 1 261 | 1 262 | 1 263 | 1 264 | 0 265 | 1 266 | 0 267 | 1 268 | 1 269 | 0 270 | 0 271 | 1 272 | 0 273 | 0 274 | 0 275 | 276 | 277 | 278 | 279 | 280 | 281 | 282 | 283 | 284 | 285 | BIN\UL2CM3.DLL 286 | 287 | 288 | 289 | 0 290 | ARMRTXEVENTFLAGS 291 | -L70 -Z18 -C0 -M0 -T1 292 | 293 | 294 | 0 295 | UL2CM3 296 | UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0NEW_DEVICE -FS00 -FL040000 -FP0($$Device:ARMCM3$Device\ARM\Flash\NEW_DEVICE.FLM)) 297 | 298 | 299 | 0 300 | DLGDARM 301 | (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) 302 | 303 | 304 | 0 305 | ARMDBGFLAGS 306 | -T0 307 | 308 | 309 | 310 | 311 | 0 312 | 313 | 314 | 0 315 | 0 316 | 1 317 | 0 318 | 0 319 | 0 320 | 0 321 | 1 322 | 0 323 | 0 324 | 0 325 | 0 326 | 0 327 | 0 328 | 0 329 | 0 330 | 0 331 | 0 332 | 0 333 | 0 334 | 0 335 | 0 336 | 0 337 | 0 338 | 339 | 340 | 341 | 0 342 | 0 343 | 0 344 | 345 | 346 | 347 | 348 | 349 | 350 | 351 | 352 | 353 | 354 | 355 | 356 | ARMCM4_FP 357 | 0x4 358 | ARM-ADS 359 | 360 | 12000000 361 | 362 | 1 363 | 1 364 | 0 365 | 1 366 | 0 367 | 368 | 369 | 1 370 | 65535 371 | 0 372 | 0 373 | 0 374 | 375 | 376 | 79 377 | 66 378 | 8 379 | .\ARMCM4_debug\ 380 | 381 | 382 | 1 383 | 1 384 | 1 385 | 0 386 | 1 387 | 1 388 | 0 389 | 1 390 | 0 391 | 0 392 | 0 393 | 0 394 | 395 | 396 | 1 397 | 1 398 | 1 399 | 1 400 | 1 401 | 1 402 | 1 403 | 0 404 | 0 405 | 406 | 407 | 1 408 | 0 409 | 0 410 | 411 | 7 412 | 413 | 1 414 | 0 415 | 1 416 | 1 417 | 1 418 | 1 419 | 1 420 | 1 421 | 1 422 | 1 423 | 1 424 | 1 425 | 1 426 | 1 427 | 0 428 | 1 429 | 0 430 | 1 431 | 1 432 | 0 433 | 0 434 | 1 435 | 0 436 | 0 437 | 0 438 | 439 | 440 | 441 | 442 | 443 | 444 | 445 | 446 | 447 | 448 | BIN\UL2CM3.DLL 449 | 450 | 451 | 452 | 0 453 | ARMRTXEVENTFLAGS 454 | -L70 -Z18 -C0 -M0 -T1 455 | 456 | 457 | 0 458 | UL2CM3 459 | UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0NEW_DEVICE -FL080000 -FS00 -FP0($$Device:ARMCM4_FP$Device\ARM\Flash\NEW_DEVICE.FLM) 460 | 461 | 462 | 0 463 | DLGDARM 464 | (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(1012=-1,-1,-1,-1,0) 465 | 466 | 467 | 0 468 | ARMDBGFLAGS 469 | -T0 470 | 471 | 472 | 473 | 474 | 0 475 | 476 | 477 | 0 478 | 0 479 | 1 480 | 0 481 | 0 482 | 0 483 | 0 484 | 1 485 | 0 486 | 0 487 | 0 488 | 0 489 | 0 490 | 0 491 | 0 492 | 1 493 | 0 494 | 0 495 | 0 496 | 1 497 | 0 498 | 0 499 | 0 500 | 0 501 | 502 | 503 | 504 | 0 505 | 0 506 | 0 507 | 508 | 509 | 510 | 511 | 512 | 513 | 514 | 515 | 516 | 517 | 518 | 519 | ARMCM7_SP 520 | 0x4 521 | ARM-ADS 522 | 523 | 12000000 524 | 525 | 1 526 | 1 527 | 0 528 | 1 529 | 0 530 | 531 | 532 | 1 533 | 65535 534 | 0 535 | 0 536 | 0 537 | 538 | 539 | 79 540 | 66 541 | 8 542 | .\ARMCM7_debug\ 543 | 544 | 545 | 1 546 | 1 547 | 1 548 | 0 549 | 1 550 | 1 551 | 0 552 | 1 553 | 0 554 | 0 555 | 0 556 | 0 557 | 558 | 559 | 1 560 | 1 561 | 1 562 | 1 563 | 1 564 | 1 565 | 1 566 | 0 567 | 0 568 | 569 | 570 | 1 571 | 0 572 | 1 573 | 574 | 7 575 | 576 | 1 577 | 0 578 | 1 579 | 1 580 | 1 581 | 1 582 | 1 583 | 1 584 | 1 585 | 1 586 | 1 587 | 1 588 | 1 589 | 1 590 | 0 591 | 1 592 | 0 593 | 1 594 | 1 595 | 0 596 | 0 597 | 1 598 | 0 599 | 0 600 | 0 601 | 602 | 603 | 604 | 605 | 606 | 607 | 608 | 609 | 610 | 611 | BIN\UL2CM3.DLL 612 | 613 | 614 | 615 | 0 616 | ARMRTXEVENTFLAGS 617 | -L70 -Z18 -C0 -M0 -T1 618 | 619 | 620 | 0 621 | UL2CM3 622 | UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0NEW_DEVICE -FL080000 -FS00 -FP0($$Device:ARMCM7_SP$Device\ARM\Flash\NEW_DEVICE.FLM) 623 | 624 | 625 | 0 626 | DLGDARM 627 | (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(1012=-1,-1,-1,-1,0) 628 | 629 | 630 | 0 631 | ARMDBGFLAGS 632 | -T0 633 | 634 | 635 | 636 | 637 | 638 | 1 639 | 0 640 | img_buffer2 641 | 0 642 | 643 | 644 | 645 | 0 646 | 647 | 648 | 0 649 | 0 650 | 0 651 | 0 652 | 0 653 | 0 654 | 0 655 | 1 656 | 0 657 | 0 658 | 0 659 | 0 660 | 0 661 | 0 662 | 0 663 | 0 664 | 0 665 | 0 666 | 0 667 | 1 668 | 0 669 | 0 670 | 0 671 | 0 672 | 673 | 674 | 675 | 0 676 | 0 677 | 0 678 | 679 | 680 | 681 | 682 | 683 | 684 | 685 | 686 | 687 | 688 | 689 | 690 | Source Files 691 | 1 692 | 0 693 | 0 694 | 0 695 | 696 | 1 697 | 1 698 | 8 699 | 0 700 | 0 701 | 0 702 | .\src\arm_nnexamples_cifar10.cpp 703 | arm_nnexamples_cifar10.cpp 704 | 0 705 | 0 706 | 707 | 708 | 709 | 710 | Documentation 711 | 0 712 | 0 713 | 0 714 | 0 715 | 716 | 2 717 | 2 718 | 5 719 | 0 720 | 0 721 | 0 722 | .\readme.txt 723 | readme.txt 724 | 0 725 | 0 726 | 727 | 728 | 729 | 730 | ::CMSIS 731 | 0 732 | 0 733 | 0 734 | 1 735 | 736 | 737 | 738 | ::Compiler 739 | 0 740 | 0 741 | 0 742 | 1 743 | 744 | 745 | 746 | ::Device 747 | 1 748 | 0 749 | 0 750 | 1 751 | 752 | 753 | 754 | -------------------------------------------------------------------------------- /arm_nnexamples_cifar10/readme.md: -------------------------------------------------------------------------------- 1 | 2 | # 项目简介 3 | 本项目实现了在STM32上进行图像分类的任务。使用CIFAR-10数据集，通过Caffe机器学习框架搭建和训练 4 | 神经网络模型，然后将所得模型进行转换，使其能够运行在STM32上。本项目运行在Keil的模拟器中， 5 | 所以无需开发板即可体验机器学习在STM32上的应用效果。 6 | 7 | # 项目的输入 8 | 一幅宽32像素高32像素的彩色图像（来自于CIFAR-10数据集），为方便STM32实验操作， 9 | 事先将图像转换为像素值数组，存放在arm_nnexamples_cifar10_inputs.h中。 10 | 11 | # 项目的输出 12 | 测试图像所属的类别 13 | 14 | # 使用说明： 15 | 编译 -> Debug调试运行 -> 打开Debug (printf) Viewer (View->Serial Windows->Debug (printf) Viewer) 16 | 17 | # 参考 18 | * https://github.com/BVLC/caffe 19 | * https://github.com/ARM-software/ML-examples/tree/master/cmsisnn-cifar10 20 | * https://github.com/ARM-software/CMSIS_5/tree/develop/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10 21 | 22 | -------------------------------------------------------------------------------- /arm_nnexamples_cifar10/src/arm_nnexamples_cifar10.cpp: -------------------------------------------------------------------------------- 1 | /* ---------------------------------------------------------------------- 2 | * Copyright (C) 2010-2018 Arm Limited. All rights reserved. 3 | * 4 | * 5 | * Project: CMSIS NN Library 6 | * Title: arm_nnexamples_cifar10.cpp 7 | * 8 | * Description: Convolutional Neural Network Example 9 | * 10 | * Target Processor: Cortex-M4/Cortex-M7 11 | * 12 | * Redistribution and use in source and binary forms, with or without 13 | * modification, are permitted provided that the following conditions 14 | * are met: 15 | * - Redistributions of source code must retain the above copyright 16 | * notice, this list of conditions and the following disclaimer. 17 | * - Redistributions in binary form must reproduce the above copyright 18 | * notice, this list of conditions and the following disclaimer in 19 | * the documentation and/or other materials provided with the 20 | * distribution. 21 | * - Neither the name of Arm LIMITED nor the names of its contributors 22 | * may be used to endorse or promote products derived from this 23 | * software without specific prior written permission. 24 | * 25 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 26 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 27 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 28 | * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 29 | * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 30 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 31 | * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 32 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 33 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 34 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 35 | * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 | * POSSIBILITY OF SUCH DAMAGE. 37 | * -------------------------------------------------------------------- */ 38 | 39 | /** 40 | * @ingroup groupExamples 41 | */ 42 | 43 | /** 44 | * @defgroup CNNExample Convolutional Neural Network Example 45 | * 46 | * \par Description: 47 | * \par 48 | * Demonstrates a convolutional neural network (CNN) example with the use of convolution, 49 | * ReLU activation, pooling and fully-connected functions. 50 | * 51 | * \par Model definition: 52 | * \par 53 | * The CNN used in this example is based on CIFAR-10 example from Caffe [1]. 54 | * The neural network consists 55 | * of 3 convolution layers interspersed by ReLU activation and max pooling layers, followed by a 56 | * fully-connected layer at the end. The input to the network is a 32x32 pixel color image, which will 57 | * be classified into one of the 10 output classes. 58 | * This example model implementation needs 32.3 KB to store weights, 40 KB for activations and 59 | * 3.1 KB for storing the \c im2col data. 60 | * 61 | * \image html CIFAR10_CNN.gif "Neural Network model definition" 62 | * 63 | * \par Variables Description: 64 | * \par 65 | * \li \c conv1_wt, \c conv2_wt, \c conv3_wt are convolution layer weight matrices 66 | * \li \c conv1_bias, \c conv2_bias, \c conv3_bias are convolution layer bias arrays 67 | * \li \c ip1_wt, ip1_bias point to fully-connected layer weights and biases 68 | * \li \c input_data points to the input image data 69 | * \li \c output_data points to the classification output 70 | * \li \c col_buffer is a buffer to store the \c im2col output 71 | * \li \c scratch_buffer is used to store the activation data (intermediate layer outputs) 72 | * 73 | * \par CMSIS DSP Software Library Functions Used: 74 | * \par 75 | * - arm_convolve_HWC_q7_RGB() 76 | * - arm_convolve_HWC_q7_fast() 77 | * - arm_relu_q7() 78 | * - arm_maxpool_q7_HWC() 79 | * - arm_avepool_q7_HWC() 80 | * - arm_fully_connected_q7_opt() 81 | * - arm_fully_connected_q7() 82 | * 83 | * Refer 84 | * \link arm_nnexamples_cifar10.cpp \endlink 85 | * 86 | * \par [1] https://github.com/BVLC/caffe 87 | */ 88 | 89 | /* ------------------------------------------------------------------ 90 | * 边缘智能实验室(微信公众号) 91 | * 92 | * 项目简介： 93 | * 本项目实现了在STM32上进行图像分类的任务。使用CIFAR-10数据集，通过Caffe机器学习框架搭建和训练 94 | * 神经网络模型，然后将所得模型进行转换，使其能够运行在STM32上。本项目运行在Keil的模拟器中， 95 | * 所以无需开发板即可体验机器学习在STM32上的应用效果。 96 | * 97 | * 项目的输入： 98 | * 一幅宽32像素高32像素的彩色图像，为方便STM32实验操作， 99 | * 事先将图像转换为像素值数组，存放在arm_nnexamples_cifar10_inputs.h中 100 | * 101 | * 项目的输出： 102 | * 测试图像所属的类别 103 | * 104 | * 使用说明： 105 | * 编译 -> Debug调试运行 -> 打开Debug (printf) Viewer (View->Serial Windows->Debug (printf) Viewer) 106 | * 107 | * 参考: 108 | * https://github.com/BVLC/caffe 109 | * https://github.com/ARM-software/ML-examples/tree/master/cmsisnn-cifar10 110 | * https://github.com/ARM-software/CMSIS_5/tree/develop/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10 111 | * 112 | */ 113 | 114 | #include 115 | #include 116 | #include "arm_math.h" 117 | #include "arm_nnexamples_cifar10_parameter.h" 118 | #include "arm_nnexamples_cifar10_weights.h" 119 | 120 | #include "arm_nnfunctions.h" 121 | #include "arm_nnexamples_cifar10_inputs.h" 122 | 123 | #ifdef _RTE_ 124 | #include "RTE_Components.h" 125 | #ifdef RTE_Compiler_EventRecorder 126 | #include "EventRecorder.h" 127 | #endif 128 | #endif 129 | 130 | // include the input and weights 131 | 132 | static q7_t conv1_wt[CONV1_IM_CH * CONV1_KER_DIM * CONV1_KER_DIM * CONV1_OUT_CH] = CONV1_WT; 133 | static q7_t conv1_bias[CONV1_OUT_CH] = CONV1_BIAS; 134 | 135 | static q7_t conv2_wt[CONV2_IM_CH * CONV2_KER_DIM * CONV2_KER_DIM * CONV2_OUT_CH] = CONV2_WT; 136 | static q7_t conv2_bias[CONV2_OUT_CH] = CONV2_BIAS; 137 | 138 | static q7_t conv3_wt[CONV3_IM_CH * CONV3_KER_DIM * CONV3_KER_DIM * CONV3_OUT_CH] = CONV3_WT; 139 | static q7_t conv3_bias[CONV3_OUT_CH] = CONV3_BIAS; 140 | 141 | static q7_t ip1_wt[IP1_DIM * IP1_OUT] = IP1_WT; 142 | static q7_t ip1_bias[IP1_OUT] = IP1_BIAS; 143 | 144 | /* Here the image_data should be the raw uint8 type RGB image in [RGB, RGB, RGB ... RGB] format */ 145 | uint8_t image_data[CONV1_IM_CH * CONV1_IM_DIM * CONV1_IM_DIM] = IMG_DATA; 146 | q7_t output_data[IP1_OUT]; 147 | 148 | //vector buffer: max(im2col buffer,average pool buffer, fully connected buffer) 149 | q7_t col_buffer[2 * 5 * 5 * 32 * 2]; 150 | 151 | q7_t scratch_buffer[32 * 32 * 10 * 4]; 152 | 153 | // the label 154 | const char* cifar10_label[] = {"airplane", "automobile", "bird", "cat", "deer", 155 | "dog", "frog", "horse", "ship", "truck"}; 156 | 157 | // get the index of the max value 158 | uint8_t get_max_index(q7_t *array,uint8_t len) 159 | { 160 | int max = array[0]; 161 | int max_index; 162 | for (int i = 1; i < len; i++) 163 | { 164 | if(max> scale_data[0], 8); 191 | img_buffer2[i+1] = (q7_t)__SSAT( ((((int)image_data[i+1] - mean_data[1])<<7) + (0x1<<(scale_data[1]-1))) 192 | >> scale_data[1], 8); 193 | img_buffer2[i+2] = (q7_t)__SSAT( ((((int)image_data[i+2] - mean_data[2])<<7) + (0x1<<(scale_data[2]-1))) 194 | >> scale_data[2], 8); 195 | } 196 | 197 | // conv1 img_buffer2 -> img_buffer1 198 | arm_convolve_HWC_q7_RGB(img_buffer2, CONV1_IM_DIM, CONV1_IM_CH, conv1_wt, CONV1_OUT_CH, CONV1_KER_DIM, CONV1_PADDING, 199 | CONV1_STRIDE, conv1_bias, CONV1_BIAS_LSHIFT, CONV1_OUT_RSHIFT, img_buffer1, CONV1_OUT_DIM, 200 | (q15_t *) col_buffer, NULL); 201 | 202 | arm_relu_q7(img_buffer1, CONV1_OUT_DIM * CONV1_OUT_DIM * CONV1_OUT_CH); 203 | 204 | // pool1 img_buffer1 -> img_buffer2 205 | arm_maxpool_q7_HWC(img_buffer1, CONV1_OUT_DIM, CONV1_OUT_CH, POOL1_KER_DIM, 206 | POOL1_PADDING, POOL1_STRIDE, POOL1_OUT_DIM, NULL, img_buffer2); 207 | 208 | // conv2 img_buffer2 -> img_buffer1 209 | arm_convolve_HWC_q7_fast(img_buffer2, CONV2_IM_DIM, CONV2_IM_CH, conv2_wt, CONV2_OUT_CH, CONV2_KER_DIM, 210 | CONV2_PADDING, CONV2_STRIDE, conv2_bias, CONV2_BIAS_LSHIFT, CONV2_OUT_RSHIFT, img_buffer1, 211 | CONV2_OUT_DIM, (q15_t *) col_buffer, NULL); 212 | 213 | arm_relu_q7(img_buffer1, CONV2_OUT_DIM * CONV2_OUT_DIM * CONV2_OUT_CH); 214 | 215 | // pool2 img_buffer1 -> img_buffer2 216 | arm_maxpool_q7_HWC(img_buffer1, CONV2_OUT_DIM, CONV2_OUT_CH, POOL2_KER_DIM, 217 | POOL2_PADDING, POOL2_STRIDE, POOL2_OUT_DIM, col_buffer, img_buffer2); 218 | 219 | // conv3 img_buffer2 -> img_buffer1 220 | arm_convolve_HWC_q7_fast(img_buffer2, CONV3_IM_DIM, CONV3_IM_CH, conv3_wt, CONV3_OUT_CH, CONV3_KER_DIM, 221 | CONV3_PADDING, CONV3_STRIDE, conv3_bias, CONV3_BIAS_LSHIFT, CONV3_OUT_RSHIFT, img_buffer1, 222 | CONV3_OUT_DIM, (q15_t *) col_buffer, NULL); 223 | 224 | arm_relu_q7(img_buffer1, CONV3_OUT_DIM * CONV3_OUT_DIM * CONV3_OUT_CH); 225 | 226 | // pool3 img_buffer-> img_buffer2 227 | arm_maxpool_q7_HWC(img_buffer1, CONV3_OUT_DIM, CONV3_OUT_CH, POOL3_KER_DIM, 228 | POOL3_PADDING, POOL3_STRIDE, POOL3_OUT_DIM, col_buffer, img_buffer2); 229 | 230 | arm_fully_connected_q7_opt(img_buffer2, ip1_wt, IP1_DIM, IP1_OUT, IP1_BIAS_LSHIFT, IP1_OUT_RSHIFT, ip1_bias, 231 | output_data, (q15_t *) img_buffer1); 232 | 233 | arm_softmax_q7(output_data, 10, output_data); 234 | 235 | for (int i = 0; i < 10; i++) 236 | { 237 | printf("%d: %d\n", i, output_data[i]); 238 | } 239 | 240 | printf("It is %s.\n",cifar10_label[get_max_index(output_data,sizeof(output_data)/sizeof(output_data[0]))]); 241 | 242 | 243 | return 0; 244 | } 245 | -------------------------------------------------------------------------------- /arm_nnexamples_cifar10/src/arm_nnexamples_cifar10_inputs.h: -------------------------------------------------------------------------------- 1 | /* Here are some images */ 2 | 3 | // cat 4 | //#define IMG_DATA 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3,71,107,133,49,89,114,31,77,105,27,71,105,38,82,117,49,93,128,56,100,135,58,102,137,53,92,128,56,94,131,60,99,137,57,99,139,53,97,138,50,95,137,45,94,136,39,88,131,33,83,125,42,91,133,62,112,154,79,132,179,73,131,181,56,116,168,38,97,146,13,64,108,40,85,127,61,116,168,49,102,148,35,85,132,43,91,143,39,90,139,42,92,134,44,88,125,40,81,112,42,85,115,27,72,104,23,67,102,30,74,109,27,71,106,29,73,108,36,80,115,47,86,120,56,95,128,62,101,135,66,109,144,75,119,156,69,113,152,49,95,134,43,88,127,43,88,127,60,105,144,85,130,170,109,156,197,93,145,190,60,115,164,26,82,130,29,82,126,20,64,107,54,107,160,56,105,149,45,89,132,43,86,134,40,89,134,40,92,132,40,87,123,38,81,115,36,79,114,26,69,105,22,66,101,29,73,108,25,69,104,29,73,108,19,63,98,18,58,89,32,70,100,47,87,118,61,104,137,74,119,152,66,111,145,53,96,131,52,95,130,45,87,123,67,109,145,89,131,167,105,146,182,89,135,175,48,99,145,24,77,124,34,84,129,21,67,110} 5 | 6 | // horse 7 | //#define IMG_DATA {38,64,17,39,65,20,41,66,27,37,61,27,34,54,27,39,59,34,48,66,42,46,64,38,31,50,22,52,71,39,57,78,45,47,71,37,62,86,54,88,113,84,86,111,89,62,87,68,43,70,55,70,97,82,61,83,70,54,77,59,88,107,88,87,108,89,61,83,70,61,87,76,37,63,60,24,52,53,27,55,59,55,80,87,52,69,77,29,42,50,33,42,49,27,34,40,125,152,101,119,145,98,114,137,95,105,127,91,97,113,84,93,109,82,94,108,82,92,105,79,82,95,65,99,113,80,116,132,96,126,143,107,135,155,120,142,163,132,136,159,133,125,147,126,114,137,119,111,132,117,84,102,86,80,97,79,115,130,111,115,129,112,67,85,73,36,56,47,39,61,59,26,50,52,29,52,58,57,77,84,44,61,68,17,28,34,24,31,37,25,33,36,182,207,150,178,203,148,178,200,153,181,197,158,180,191,157,174,181,150,168,173,143,168,168,140,163,164,132,168,170,133,181,185,148,194,202,163,194,204,167,181,195,159,175,190,159,178,192,166,182,197,176,151,164,146,113,124,107,111,120,103,145,149,132,155,159,145,115,120,113,69,78,73,46,57,59,39,54,59,45,62,69,69,86,93,51,64,70,20,30,32,28,34,34,30,36,34,186,211,146,191,215,155,202,219,167,213,225,179,217,222,182,208,205,172,198,189,158,197,184,152,203,189,154,205,191,154,210,201,160,216,211,169,218,216,175,213,215,175,211,215,180,212,217,185,216,221,198,180,183,162,145,146,128,128,125,108,125,118,102,122,114,103,93,86,80,49,45,44,40,39,44,44,49,55,55,62,70,72,81,86,57,65,68,40,46,44,49,54,48,46,49,42,195,218,148,202,223,156,200,214,155,194,198,148,188,181,139,172,156,122,159,136,104,161,132,100,174,144,108,195,165,127,214,186,146,226,203,159,241,224,180,253,242,197,246,239,197,229,223,187,208,203,174,165,157,134,119,106,87,81,64,48,58,36,23,62,37,30,64,40,40,48,27,32,34,18,28,40,30,41,40,37,46,49,50,55,49,51,50,61,64,57,91,93,80,87,90,73,199,221,148,208,225,155,186,196,135,149,147,96,130,115,74,120,94,59,122,86,54,134,91,59,140,94,61,178,132,96,213,169,130,228,189,146,246,215,169,254,230,184,233,211,170,194,176,138,126,109,79,113,93,68,106,81,61,101,72,56,99,62,53,97,58,53,86,47,50,64,29,36,55,27,39,45,23,35,31,18,28,36,30,34,46,43,38,77,78,64,139,138,118,160,160,136,190,211,136,205,220,151,177,181,122,120,112,63,96,72,34,100,64,32,120,70,43,143,86,59,147,86,57,185,122,89,211,153,116,216,163,123,218,173,131,219,180,137,192,157,119,155,122,87,130,101,71,129,99,73,128,91,72,128,86,70,133,85,75,128,77,74,115,64,69,104,57,67,96,56,67,60,30,42,36,15,22,50,38,38,57,48,39,81,76,57,157,156,128,213,212,181,186,203,132,210,222,156,181,182,125,116,103,58,89,60,26,99,55,30,124,66,46,151,84,65,171,99,77,195,121,96,206,137,106,201,137,102,196,138,101,194,142,105,179,133,97,161,118,84,151,112,83,153,113,88,141,94,74,127,76,59,126,69,58,123,64,60,123,64,68,133,77,86,120,74,85,67,31,41,40,15,19,66,51,48,65,53,39,66,60,36,148,143,111,226,222,185,188,205,137,205,215,154,165,163,112,83,68,27,78,44,17,113,66,48,130,68,55,161,89,77,190,112,99,179,100,83,173,95,73,174,100,73,179,112,83,187,126,95,181,126,95,165,114,85,150,100,75,150,100,77,141,89,68,149,92,75,129,67,56,117,52,46,143,79,80,126,70,73,114,67,73,72,36,40,36,10,11,57,40,33,62,49,33,51,44,18,135,129,95,246,241,203,193,209,147,200,211,153,136,135,89,65,49,15,66,34,13,96,48,36,124,64,56,155,84,78,184,105,98,165,83,71,157,78,61,171,94,74,181,109,85,182,116,90,181,119,94,176,118,94,145,88,68,144,87,67,147,89,69,168,107,89,150,84,70,123,59,50,136,75,70,124,68,67,107,63,62,52,18,16,40,15,11,83,66,56,77,64,45,64,54,27,142,134,98,228,220,181,190,207,152,190,203,150,102,103,63,48,37,7,57,30,11,74,31,22,114,59,56,143,78,76,166,93,87,141,64,56,138,60,48,161,85,69,173,102,82,172,106,84,174,112,91,180,119,100,139,80,62,138,79,61,154,93,74,184,121,103,169,106,89,133,74,60,128,74,62,117,70,60,87,50,41,56,28,17,40,20,9,73,60,44,79,68,46,70,61,32,137,129,93,220,210,174,184,202,150,187,201,152,85,89,52,43,36,8,55,34,17,57,23,14,106,58,56,136,78,77,138,73,69,124,53,47,125,52,43,145,73,59,158,89,73,164,97,78,169,104,86,170,107,90,135,73,58,138,76,61,158,97,79,184,123,105,175,117,97,147,92,72,124,77,57,103,66,47,62,35,16,99,81,61,64,51,32,44,36,15,68,61,35,69,62,33,121,110,78,213,203,168,186,206,155,192,210,162,88,96,59,37,35,10,45,32,16,48,21,14,98,60,59,135,87,87,111,56,53,113,52,47,120,56,46,129,63,49,139,74,56,155,90,70,160,97,79,152,89,72,120,58,47,128,66,55,153,91,78,167,110,91,167,112,91,147,101,75,114,77,48,89,62,33,90,73,45,163,153,126,121,115,89,49,45,20,48,44,19,67,60,34,126,115,87,208,194,165,191,214,162,201,220,174,100,112,76,25,29,4,30,23,7,43,24,17,83,55,52,123,85,84,93,48,43,105,55,46,114,60,48,115,58,41,119,61,41,140,79,60,150,89,70,141,79,64,105,45,35,109,49,41,132,74,62,138,85,67,138,91,65,131,92,59,109,81,44,105,90,51,180,172,135,217,217,181,173,177,144,85,88,57,36,35,7,61,55,29,150,141,112,215,204,176,186,210,158,201,223,176,115,129,93,18,27,0,22,21,1,44,34,22,56,37,31,87,59,55,87,53,43,96,56,44,105,59,44,106,57,40,107,55,34,120,65,44,136,80,63,141,85,72,115,56,50,94,37,30,103,49,37,101,52,35,98,59,30,100,70,32,116,97,54,168,162,114,229,231,184,233,242,197,201,212,170,151,159,122,91,95,62,70,69,38,138,131,102,210,201,170,177,199,150,198,217,171,126,142,10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8 | 9 | // ship 10 | //#define IMG_DATA {235,235,235,231,231,231,232,232,232,232,232,232,232,232,232,232,232,232,232,232,232,232,232,232,232,232,232,232,232,232,233,233,233,233,233,233,233,233,233,233,233,233,233,233,233,233,232,233,233,231,233,232,231,233,231,233,233,230,233,232,232,232,234,232,231,234,232,232,232,233,233,230,232,233,231,233,233,233,232,232,232,232,232,232,232,232,232,233,233,233,233,233,233,232,232,232,238,238,238,235,235,235,235,235,235,235,235,235,235,235,235,235,235,235,235,235,235,235,235,235,235,235,235,235,235,235,236,236,236,236,236,236,236,236,236,236,236,236,236,236,236,236,236,236,237,234,233,236,234,233,236,236,234,234,236,234,234,235,237,234,234,238,235,236,237,236,236,235,236,236,234,236,236,236,235,235,235,235,235,235,235,235,235,236,236,236,236,236,236,235,235,235,237,237,237,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,235,235,235,235,234,234,236,233,231,236,234,231,235,235,234,234,235,236,227,230,233,231,235,238,231,233,235,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,235,235,235,235,235,235,234,234,234,238,238,238,235,235,235,235,235,235,235,235,235,235,235,235,235,235,235,235,235,235,235,235,235,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,235,235,235,235,235,234,233,233,230,232,232,231,228,230,232,223,226,231,186,192,197,209,216,219,207,210,213,228,228,230,236,235,235,234,234,234,234,234,234,234,234,234,234,234,234,235,235,235,235,235,235,235,235,235,237,237,237,234,234,234,235,235,235,235,235,235,235,235,235,235,235,235,235,235,235,235,235,235,234,234,234,234,234,234,235,235,235,235,235,235,234,234,234,234,234,234,235,235,235,235,235,235,236,238,236,233,237,237,219,225,230,203,210,219,163,172,179,195,205,208,214,218,221,230,229,232,237,235,237,235,235,235,235,235,235,235,235,235,235,236,236,236,236,236,236,236,236,236,236,236,239,239,238,236,235,235,236,235,235,236,235,235,236,235,235,236,235,235,235,236,235,235,235,235,234,234,234,235,235,235,237,236,236,237,236,236,234,235,236,232,233,234,235,237,237,229,231,232,208,216,218,194,205,210,185,198,207,174,188,200,165,179,189,184,196,202,207,215,220,226,228,232,236,235,237,236,236,235,236,236,235,236,236,235,236,236,236,237,237,237,237,237,237,237,237,237,228,229,229,228,227,228,232,230,231,231,228,230,234,232,233,237,236,236,237,237,235,236,237,235,237,235,236,237,235,236,239,236,237,239,237,238,225,229,230,224,228,229,233,237,238,221,226,228,183,197,204,161,180,190,159,180,191,154,176,190,144,163,177,143,159,171,156,169,177,198,206,211,233,238,239,236,237,234,235,236,233,235,235,235,235,236,236,236,238,237,237,237,237,239,237,238,212,220,222,224,230,233,230,234,238,227,232,234,229,234,234,234,237,236,237,238,235,238,237,236,239,237,238,239,237,238,239,236,237,240,238,239,201,204,203,219,222,221,233,236,235,214,218,218,193,204,210,185,201,210,184,201,211,173,191,203,165,182,196,159,174,187,162,176,185,186,199,204,229,239,240,234,239,238,233,238,237,233,238,238,234,239,238,236,239,238,237,239,238,238,238,238,216,234,241,221,236,243,225,238,246,225,239,243,227,240,240,231,238,237,236,237,235,238,236,235,238,236,237,238,236,237,237,237,237,239,239,239,197,198,196,220,221,218,233,234,231,230,231,229,209,213,217,209,216,222,219,228,235,208,218,227,209,221,234,210,224,235,217,233,240,218,235,241,225,240,243,228,238,240,228,239,240,230,240,240,230,240,239,235,240,239,237,240,239,238,238,238,118,140,149,119,138,148,124,142,153,136,155,161,172,188,191,225,234,233,235,236,233,237,234,232,236,233,234,235,235,235,235,237,236,233,237,235,214,216,214,226,228,226,232,234,232,236,237,236,228,230,232,227,230,235,231,236,241,225,232,239,225,237,247,217,233,243,201,219,226,185,204,211,172,189,195,167,179,186,167,180,185,186,199,201,223,235,235,235,241,239,236,240,239,238,240,239,109,130,141,103,121,133,108,125,137,111,127,137,146,159,165,222,229,231,227,228,225,229,226,224,236,232,233,234,234,234,231,236,234,230,237,235,229,234,235,231,235,236,232,237,238,230,235,236,231,236,238,231,237,240,229,237,241,223,232,238,191,206,213,164,184,191,146,165,172,137,156,163,134,149,159,128,140,153,121,133,143,149,162,166,216,228,229,234,241,239,235,240,238,237,240,239,195,212,224,188,202,215,199,211,224,200,211,223,209,217,227,223,227,231,213,213,211,211,209,206,216,213,214,220,222,222,219,226,225,210,221,219,209,219,223,211,221,225,216,225,230,220,229,233,225,234,237,226,236,239,225,237,241,218,231,237,183,204,208,175,198,203,181,200,207,178,194,202,186,197,211,170,178,196,142,151,164,185,195,202,219,230,233,231,240,238,234,241,239,236,240,239,193,207,222,191,202,217,202,211,224,214,217,234,223,225,241,214,219,227,203,208,208,171,174,174,177,180,183,207,213,214,174,184,188,98,112,121,93,114,126,101,121,132,111,129,139,122,138,147,137,152,161,153,167,174,202,216,220,223,236,237,218,232,235,220,233,238,223,234,240,217,226,233,221,228,237,212,219,229,196,203,212,222,230,237,219,227,234,221,230,233,232,239,242,235,241,242,113,130,1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115,122,126,115,121,127,118,132,139,131,147,157,150,165,179,174,176,191,187,186,201,199,92,102,93,54,60,50,6,7,3,3,2,1,2,2,0,1,3,1,1,3,3,1,2,2,1,1,1,1,0,0,1,0,0,1,1,1,0,3,2,15,1,0,102,19,28,157,31,47,117,17,23,74,13,12,56,27,22,74,58,55,99,90,81,115,115,99,122,126,111,124,124,112,123,123,113,125,130,119,128,135,126,136,145,137,148,159,151,162,176,171,177,192,188,188,202,201,87,99,89,43,51,37,19,23,11,11,12,4,8,10,2,5,11,4,2,10,4,2,7,2,3,4,1,3,4,1,3,4,1,2,3,2,0,6,6,4,5,2,42,13,13,71,21,24,53,27,25,57,50,41,80,77,62,113,98,82,132,113,101,134,126,113,123,126,112,116,125,111,120,128,115,131,138,126,139,148,137,143,154,145,156,168,161,169,184,179,182,197,193,188,202,201,82,96,82,46,57,36,36,44,22,31,35,17,27,30,15,22,28,15,17,26,13,16,23,12,18,21,12,19,21,13,20,22,14,19,23,15,19,27,20,23,31,21,37,40,27,64,55,45,87,70,67,104,88,81,116,102,85,128,112,88,139,121,105,131,122,110,117,122,107,115,127,112,123,133,119,131,139,127,139,149,138,148,160,151,159,172,164,174,189,183,185,200,196,187,202,200,85,101,83,62,75,48,58,67,38,55,61,37,51,56,35,47,53,33,46,53,34,48,55,38,49,55,40,51,56,41,53,58,44,55,62,46,59,67,45,68,71,48,81,84,59,104,96,74,116,103,83,127,109,92,133,116,97,127,121,97,127,127,107,118,124,106,114,125,108,122,131,117,129,136,123,136,145,133,141,152,141,149,162,153,158,171,163,168,183,178,180,195,191,186,200,199} 11 | 12 | // cat 13 | //#define IMG_DATA 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14 | 15 | // dog 16 | #define IMG_DATA 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17 | 18 | 19 | 20 | -------------------------------------------------------------------------------- /arm_nnexamples_cifar10/src/arm_nnexamples_cifar10_parameter.h: -------------------------------------------------------------------------------- 1 | #define CONV1_IM_DIM 32 2 | #define CONV1_IM_CH 3 3 | #define CONV1_KER_DIM 5 4 | #define CONV1_PADDING 2 5 | #define CONV1_STRIDE 1 6 | #define CONV1_OUT_CH 32 7 | #define CONV1_OUT_DIM 32 8 | 9 | #define POOL1_KER_DIM 3 10 | #define POOL1_STRIDE 2 11 | #define POOL1_PADDING 0 12 | #define POOL1_OUT_DIM 16 13 | 14 | #define CONV2_IM_DIM 16 15 | #define CONV2_IM_CH 32 16 | #define CONV2_KER_DIM 5 17 | #define CONV2_PADDING 2 18 | #define CONV2_STRIDE 1 19 | #define CONV2_OUT_CH 16 20 | #define CONV2_OUT_DIM 16 21 | 22 | #define POOL2_KER_DIM 3 23 | #define POOL2_STRIDE 2 24 | #define POOL2_PADDING 0 25 | #define POOL2_OUT_DIM 8 26 | 27 | #define CONV3_IM_DIM 8 28 | #define CONV3_IM_CH 16 29 | #define CONV3_KER_DIM 5 30 | #define CONV3_PADDING 2 31 | #define CONV3_STRIDE 1 32 | #define CONV3_OUT_CH 32 33 | #define CONV3_OUT_DIM 8 34 | 35 | #define POOL3_KER_DIM 3 36 | #define POOL3_STRIDE 2 37 | #define POOL3_PADDING 0 38 | #define POOL3_OUT_DIM 4 39 | 40 | #define IP1_DIM 4*4*32 41 | #define IP1_IM_DIM 4 42 | #define IP1_IM_CH 32 43 | #define IP1_OUT 10 44 | -------------------------------------------------------------------------------- /assets/img/arm_nn_cifar_debug.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/EdgeAI-Lab/cifar10_image_classifier_on_stm32/a3c5e911baf60c745fc9b286675cac057425061c/assets/img/arm_nn_cifar_debug.png -------------------------------------------------------------------------------- /assets/img/array_to_image.png: -------------------------------------------------------------------------------- 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-------------------------------------------------------------------------------- /script/Readme.md: -------------------------------------------------------------------------------- 1 | # Usage 2 | 3 | ## array_convert_to_image.py 4 | 5 | ![](https://github.com/edgeML/cifar10_image_classifier_on_stm32/blob/master/assets/img/array_to_image.png) 6 | 7 | 将一维数组转换为图片并显示 8 | 9 | ``` 10 | # 替换这个 11 | image = [38,64,17, ... ,124,128,173,118] 12 | ``` 13 | 14 | ## image_convert_to_array.py 15 | 16 | ![](https://github.com/edgeML/cifar10_image_classifier_on_stm32/blob/master/assets/img/image_convert_array.png) 17 | 18 | 注意：脚本image_convert_to_array.py仅支持32*32的彩色图像 19 | 20 | 去[CIFAR-10数据集官网下载图片](https://www.cs.toronto.edu/~kriz/cifar.html)然后使用脚本image_convert_to_array.py将图像转换为一维数组，将该一维数组复制到STM32项目中的arm_nnexamples_cifar10_inputs.h文件中。 21 | 22 | ``` 23 | python image_convert_to_array.py path_to_image 24 | ``` 25 | 26 | ## resize_image_and_to_array.py 27 | 28 | ![](https://github.com/edgeML/cifar10_image_classifier_on_stm32/blob/master/assets/img/resize_and_convert_array.png) 29 | 30 | 去互联网下载图片，然后使用脚本resize_image_and_to_array.py将图像转换为32*32大小的图像，并得到图像的一维数组，将该一维数组复制到STM32项目中的arm_nnexamples_cifar10_inputs.h文件中。 31 | 32 | ``` 33 | python resize_image_and_to_array.py path_to_image 34 | ``` -------------------------------------------------------------------------------- /script/array_convert_to_image.py: -------------------------------------------------------------------------------- 1 | import numpy as np 2 | from matplotlib import pyplot as plt 3 | 4 | image = [38,64,17,39,65,20,41,66,27,37,61,27,34,54,27,39,59,34,48,66,42,46,64,38,31,50,22,52,71,39,57,78,45,47,71,37,62,86,54,88,113,84,86,111,89,62,87,68,43,70,55,70,97,82,61,83,70,54,77,59,88,107,88,87,108,89,61,83,70,61,87,76,37,63,60,24,52,53,27,55,59,55,80,87,52,69,77,29,42,50,33,42,49,27,34,40,125,152,101,119,145,98,114,137,95,105,127,91,97,113,84,93,109,82,94,108,82,92,105,79,82,95,65,99,113,80,116,132,96,126,143,107,135,155,120,142,163,132,136,159,133,125,147,126,114,137,119,111,132,117,84,102,86,80,97,79,115,130,111,115,129,112,67,85,73,36,56,47,39,61,59,26,50,52,29,52,58,57,77,84,44,61,68,17,28,34,24,31,37,25,33,36,182,207,150,178,203,148,178,200,153,181,197,158,180,191,157,174,181,150,168,173,143,168,168,140,163,164,132,168,170,133,181,185,148,194,202,163,194,204,167,181,195,159,175,190,159,178,192,166,182,197,176,151,164,146,113,124,107,111,120,103,145,149,132,155,159,145,115,120,113,69,78,73,46,57,59,39,54,59,45,62,69,69,86,93,51,64,70,20,30,32,28,34,34,30,36,34,186,211,146,191,215,155,202,219,167,213,225,179,217,222,182,208,205,172,198,189,158,197,184,152,203,189,154,205,191,154,210,201,160,216,211,169,218,216,175,213,215,175,211,215,180,212,217,185,216,221,198,180,183,162,145,146,128,128,125,108,125,118,102,122,114,103,93,86,80,49,45,44,40,39,44,44,49,55,55,62,70,72,81,86,57,65,68,40,46,44,49,54,48,46,49,42,195,218,148,202,223,156,200,214,155,194,198,148,188,181,139,172,156,122,159,136,104,161,132,100,174,144,108,195,165,127,214,186,146,226,203,159,241,224,180,253,242,197,246,239,197,229,223,187,208,203,174,165,157,134,119,106,87,81,64,48,58,36,23,62,37,30,64,40,40,48,27,32,34,18,28,40,30,41,40,37,46,49,50,55,49,51,50,61,64,57,91,93,80,87,90,73,199,221,148,208,225,155,186,196,135,149,147,96,130,115,74,120,94,59,122,86,54,134,91,59,140,94,61,178,132,96,213,169,130,228,189,146,246,215,169,254,230,184,233,211,170,194,176,138,126,109,79,113,93,68,106,81,61,101,72,56,99,62,53,97,58,53,86,47,50,64,29,36,55,27,39,45,23,35,31,18,28,36,30,34,46,43,38,77,78,64,139,138,118,160,160,136,190,211,136,205,220,151,177,181,122,120,112,63,96,72,34,100,64,32,120,70,43,143,86,59,147,86,57,185,122,89,211,153,116,216,163,123,218,173,131,219,180,137,192,157,119,155,122,87,130,101,71,129,99,73,128,91,72,128,86,70,133,85,75,128,77,74,115,64,69,104,57,67,96,56,67,60,30,42,36,15,22,50,38,38,57,48,39,81,76,57,157,156,128,213,212,181,186,203,132,210,222,156,181,182,125,116,103,58,89,60,26,99,55,30,124,66,46,151,84,65,171,99,77,195,121,96,206,137,106,201,137,102,196,138,101,194,142,105,179,133,97,161,118,84,151,112,83,153,113,88,141,94,74,127,76,59,126,69,58,123,64,60,123,64,68,133,77,86,120,74,85,67,31,41,40,15,19,66,51,48,65,53,39,66,60,36,148,143,111,226,222,185,188,205,137,205,215,154,165,163,112,83,68,27,78,44,17,113,66,48,130,68,55,161,89,77,190,112,99,179,100,83,173,95,73,174,100,73,179,112,83,187,126,95,181,126,95,165,114,85,150,100,75,150,100,77,141,89,68,149,92,75,129,67,56,117,52,46,143,79,80,126,70,73,114,67,73,72,36,40,36,10,11,57,40,33,62,49,33,51,44,18,135,129,95,246,241,203,193,209,147,200,211,153,136,135,89,65,49,15,66,34,13,96,48,36,124,64,56,155,84,78,184,105,98,165,83,71,157,78,61,171,94,74,181,109,85,182,116,90,181,119,94,176,118,94,145,88,68,144,87,67,147,89,69,168,107,89,150,84,70,123,59,50,136,75,70,124,68,67,107,63,62,52,18,16,40,15,11,83,66,56,77,64,45,64,54,27,142,134,98,228,220,181,190,207,152,190,203,150,102,103,63,48,37,7,57,30,11,74,31,22,114,59,56,143,78,76,166,93,87,141,64,56,138,60,48,161,85,69,173,102,82,172,106,84,174,112,91,180,119,100,139,80,62,138,79,61,154,93,74,184,121,103,169,106,89,133,74,60,128,74,62,117,70,60,87,50,41,56,28,17,40,20,9,73,60,44,79,68,46,70,61,32,137,129,93,220,210,174,184,202,150,187,201,152,85,89,52,43,36,8,55,34,17,57,23,14,106,58,56,136,78,77,138,73,69,124,53,47,125,52,43,145,73,59,158,89,73,164,97,78,169,104,86,170,107,90,135,73,58,138,76,61,158,97,79,184,123,105,175,117,97,147,92,72,124,77,57,103,66,47,62,35,16,99,81,61,64,51,32,44,36,15,68,61,35,69,62,33,121,110,78,213,203,168,186,206,155,192,210,162,88,96,59,37,35,10,45,32,16,48,21,14,98,60,59,135,87,87,111,56,53,113,52,47,120,56,46,129,63,49,139,74,56,155,90,70,160,97,79,152,89,72,120,58,47,128,66,55,153,91,78,167,110,91,167,112,91,147,101,75,114,77,48,89,62,33,90,73,45,163,153,126,121,115,89,49,45,20,48,44,19,67,60,34,126,115,87,208,194,165,191,214,162,201,220,174,100,112,76,25,29,4,30,23,7,43,24,17,83,55,52,123,85,84,93,48,43,105,55,46,114,60,48,115,58,41,119,61,41,140,79,60,150,89,70,141,79,64,105,45,35,109,49,41,132,74,62,138,85,67,138,91,65,131,92,59,109,81,44,105,90,51,180,172,135,217,217,181,173,177,144,85,88,57,36,35,7,61,55,29,150,141,112,215,204,176,186,210,158,201,223,176,115,129,93,18,27,0,22,21,1,44,34,22,56,37,31,87,59,55,87,53,43,96,56,44,105,59,44,106,57,40,107,55,34,120,65,44,136,80,63,141,85,72,115,56,50,94,37,30,103,49,37,101,52,35,98,59,30,100,70,32,116,97,54,168,162,114,229,231,184,233,242,197,201,212,170,151,159,122,91,95,62,70,69,38,138,131,102,210,201,170,177,199,150,198,217,171,126,142,106,20,29,0,22,26,3,48,45,28,32,19,10,49,31,21,85,62,46,84,55,37,91,58,39,99,61,42,95,54,34,101,56,37,123,77,62,143,95,85,131,80,76,86,35,31,79,31,19,70,29,9,66,33,2,75,53,12,128,118,69,230,230,176,205,214,159,219,233,180,210,227,175,218,231,185,182,190,149,91,96,56,94,94,56,176,174,136,179,196,151,182,199,155,100,114,81,10,19,0,83,87,62,137,136,115,26,20,6,75,66,51,142,130,106,97,81,56,61,40,19,62,36,19,70,43,24,77,48,32,105,71,61,140,103,97,164,123,121,105,62,56,62,22,10,58,26,5,66,43,11,55,42,0,179,177,126,221,229,170,204,218,156,219,238,174,208,226,164,215,233,173,216,233,178,140,154,101,114,124,74,193,203,153,195,212,167,161,178,136,53,67,34,31,42,12,131,140,109,141,147,119,32,34,13,89,88,67,200,199,168,127,123,88,53,46,18,33,21,0,45,30,7,59,42,22,74,55,41,91,66,59,102,71,68,90,57,50,61,32,18,44,22,0,60,45,12,105,101,56,205,210,156,221,235,173,218,238,169,220,241,172,216,239,169,228,251,183,231,253,188,194,216,152,182,202,141,217,237,178,197,219,170,134,156,110,7,24,0,67,82,49,177,192,153,116,128,92,26,36,9,109,118,89,218,227,184,178,186,139,126,131,91,84,86,49,57,57,21,49,46,15,61,55,31,82,69,53,122,102,93,112,90,79,62,45,29,42,30,4,72,68,33,168,171,126,213,226,170,211,232,167,205,231,160,199,227,153,207,235,161,215,243,169,207,237,165,205,235,165,210,237,170,207,233,168,186,213,160,122,148,100,3,25,0,107,129,90,191,213,167,72,91,46,17,32,0,135,151,114,192,209,157,203,218,163,200,214,165,175,187,141,145,154,107,135,144,99,157,161,126,184,182,157,202,193,176,141,129,115,41,34,15,34,33,5,93,97,60,205,217,169,202,221,165,203,228,163,202,232,160,200,232,157,212,244,168,213,245,170,197,229,154,198,230,157,205,236,166,197,228,160,187,216,160,126,155,101,30,57,12,145,172,129,196,222,174,59,85,37,24,47,5,159,181,135,198,222,162,199,221,157,196,217,158,193,213,154,199,219,158,212,232,173,225,239,190,229,239,202,235,237,213,149,148,130,17,19,0,18,24,0,107,119,79,217,237,186,197,222,164,204,234,170,194,230,158,196,234,159,200,237,160,203,240,163,203,239,165,197,230,159,193,226,155,198,231,160,195,224,168,119,149,95,63,92,46,167,196,150,201,229,180,89,117,66,43,70,25,166,193,142,197,226,160,191,221,151,187,213,148,189,215,150,199,226,155,208,235,166,207,231,171,202,219,174,226,237,207,165,173,150,31,41,17,14,27,0,120,138,98,208,232,182,197,226,168,195,230,164,178,215,145,177,217,144,171,209,134,180,218,143,203,239,165,197,233,161,185,218,147,193,226,155,191,218,165,90,118,69,77,104,59,167,194,149,188,216,167,109,137,88,39,66,21,147,175,124,170,201,133,177,209,136,187,218,150,194,225,157,195,229,153,197,229,154,200,230,166,207,231,181,210,227,193,170,184,159,40,56,30,14,33,3,136,158,119,182,210,161,187,221,161,180,216,152,180,220,149,185,225,152,179,217,142,177,215,140,192,228,154,193,229,155,187,220,149,189,222,151,177,201,153,57,83,36,78,103,63,157,182,142,167,193,146,105,133,85,18,45,2,122,152,102,171,202,135,162,196,122,158,190,123,164,197,128,173,207,131,178,212,136,182,214,149,186,214,163,189,211,175,144,163,135,16,35,7,4,25,0,146,171,131,160,188,139,179,212,155,177,212,148,184,221,152,197,235,162,197,233,161,177,213,139,165,198,127,170,203,132,176,207,137,172,203,133,162,183,140,44,67,25,61,83,47,152,174,138,180,203,161,105,130,88,36,61,22,89,116,71,155,183,124,154,185,118,152,182,118,151,181,117,160,191,121,174,205,135,178,208,148,175,203,154,153,175,139,51,71,43,16,36,8,10,31,0,137,162,120,172,200,151,186,215,161,156,187,127,176,208,143,191,223,156,195,228,159,184,217,146,178,209,141,181,212,144,179,208,141,168,197,130,146,167,126,55,76,37,74,93,61,144,163,131,162,184,146,98,120,82,24,48,14,56,81,41,147,174,119,153,181,120,151,179,121,151,181,121,167,198,131,175,205,141,146,175,119,105,131,86,44,66,30,58,79,48,70,91,58,34,56,18,131,156,114,152,178,130,176,205,151,195,224,166,168,198,136,180,210,146,189,218,152,186,215,149,184,213,147,186,215,149,185,211,146,179,205,140,137,158,117,82,103,64,98,117,85,134,153,123,145,167,131,108,130,94,50,71,40,59,81,45,126,150,100,143,171,113,151,178,125,149,176,123,157,186,128,153,182,124,99,125,77,31,56,16,32,54,18,102,123,90,100,122,86,35,57,18,138,164,119,168,194,146,168,195,142,193,221,163,177,205,146,183,211,150,192,218,157,196,222,159,195,221,158,189,215,152,182,210,149,179,207,146,136,159,115,111,133,94,116,137,104,120,141,108,128,152,116,128,152,116,100,123,94,98,122,86,110,136,88,134,161,108,150,176,128,145,173,124,137,166,112,118,146,95,72,97,55,21,46,7,95,119,83,141,166,127,96,121,81,20,45,3,129,155,108,180,208,159,167,194,141,177,204,149,196,224,166,192,220,161,195,223,164,201,229,170,196,224,165,182,210,151,171,200,142,169,198,140,132,162,112,127,156,110,125,153,113,115,143,105,122,150,110,139,167,127,134,159,127,128,154,117,126,154,105,137,166,112,148,176,128,146,175,129,134,164,114,114,143,95,90,116,77,72,98,61,120,146,107,144,171,128,107,134,89,45,73,25,105,133,84,154,184,132,162,191,137,185,214,158,188,217,161,180,211,152,179,210,151,183,217,157,179,212,155,164,197,140,154,187,130,154,187,130,134,169,113,138,173,119,137,170,125,133,166,123,135, 5 | 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6 | 7 | a=np.array(image).reshape(32,32,3) 8 | 9 | plt.imshow(a) 10 | plt.show() -------------------------------------------------------------------------------- /script/image_convert_to_array.py: -------------------------------------------------------------------------------- 1 | import sys 2 | from PIL import Image 3 | import numpy as np 4 | 5 | def print_array_for_c(_array): 6 | print("{",end="") 7 | for pixel in _array: 8 | print(pixel,end=",") 9 | print("}") 10 | 11 | def main(): 12 | if len(sys.argv) == 2: 13 | print("convert image: "+sys.argv[1]) 14 | img=np.asarray(Image.open(sys.argv[1]).convert("RGB")).flatten() 15 | print(img.shape) 16 | print_array_for_c(img) 17 | else: 18 | print("Usage: python image_convert_to_array.py path_to_image") 19 | 20 | if __name__ == "__main__": 21 | main() 22 | 23 | -------------------------------------------------------------------------------- /script/resize_image_and_to_array.py: -------------------------------------------------------------------------------- 1 | import sys 2 | from PIL import Image, ImageOps 3 | import numpy as np 4 | 5 | np.set_printoptions(threshold=np.inf) 6 | 7 | def resize_image(image, _width=32, _height=32): 8 | new_image = Image.open(image) 9 | new_image = ImageOps.fit(new_image , (_width, _height), Image.ANTIALIAS) 10 | new_image_rgb = new_image.convert('RGB') 11 | return np.asarray(new_image_rgb).flatten() 12 | 13 | def print_array_for_c(_array): 14 | print("{",end="") 15 | for pixel in _array: 16 | print(pixel,end=",") 17 | print("}") 18 | 19 | def main(): 20 | if len(sys.argv) == 2: 21 | print("resize and convert image: "+sys.argv[1]) 22 | print_array_for_c(resize_image(sys.argv[1])) 23 | else: 24 | print("Usage: python resize_image_and_to_array.py path_to_image") 25 | 26 | if __name__ == "__main__": 27 | main() -------------------------------------------------------------------------------- /test_images_from_cifar10/Readme.md: -------------------------------------------------------------------------------- 1 | # Usage 2 | 3 | ![](https://github.com/edgeML/cifar10_image_classifier_on_stm32/blob/master/assets/img/image_convert_array.png) 4 | 5 | 注意：脚本image_convert_to_array.py仅支持32*32的彩色图像 6 | 7 | 去[CIFAR-10数据集官网下载图片](https://www.cs.toronto.edu/~kriz/cifar.html)然后使用脚本image_convert_to_array.py将图像转换为一维数组，将该一维数组复制到STM32项目中的arm_nnexamples_cifar10_inputs.h文件中。 8 | 9 | ``` 10 | python image_convert_to_array.py path_to_image 11 | ``` -------------------------------------------------------------------------------- /test_images_from_cifar10/airplane4.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/EdgeAI-Lab/cifar10_image_classifier_on_stm32/a3c5e911baf60c745fc9b286675cac057425061c/test_images_from_cifar10/airplane4.png -------------------------------------------------------------------------------- /test_images_from_cifar10/automobile5.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/EdgeAI-Lab/cifar10_image_classifier_on_stm32/a3c5e911baf60c745fc9b286675cac057425061c/test_images_from_cifar10/automobile5.png -------------------------------------------------------------------------------- /test_images_from_cifar10/cat9.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/EdgeAI-Lab/cifar10_image_classifier_on_stm32/a3c5e911baf60c745fc9b286675cac057425061c/test_images_from_cifar10/cat9.png -------------------------------------------------------------------------------- /test_images_from_cifar10/deer2.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/EdgeAI-Lab/cifar10_image_classifier_on_stm32/a3c5e911baf60c745fc9b286675cac057425061c/test_images_from_cifar10/deer2.png -------------------------------------------------------------------------------- /test_images_from_cifar10/horse5.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/EdgeAI-Lab/cifar10_image_classifier_on_stm32/a3c5e911baf60c745fc9b286675cac057425061c/test_images_from_cifar10/horse5.png -------------------------------------------------------------------------------- /test_images_from_cifar10/image_convert_to_array.py: -------------------------------------------------------------------------------- 1 | import sys 2 | from PIL import Image 3 | import numpy as np 4 | 5 | def print_array_for_c(_array): 6 | print("{",end="") 7 | for pixel in _array: 8 | print(pixel,end=",") 9 | print("}") 10 | 11 | def main(): 12 | if len(sys.argv) == 2: 13 | print("convert image: "+sys.argv[1]) 14 | img=np.asarray(Image.open(sys.argv[1]).convert("RGB")).flatten() 15 | print(img.shape) 16 | print_array_for_c(img) 17 | else: 18 | print("Usage: python image_convert_to_array.py path_to_image") 19 | 20 | if __name__ == "__main__": 21 | main() 22 | 23 | -------------------------------------------------------------------------------- /test_images_from_internet/Readme.md: -------------------------------------------------------------------------------- 1 | # Usage 2 | 3 | ![](https://github.com/edgeML/cifar10_image_classifier_on_stm32/blob/master/assets/img/resize_and_convert_array.png) 4 | 5 | 去互联网下载图片，然后使用脚本resize_image_and_to_array.py将图像转换为32*32大小的图像，并得到图像的一维数组，将该一维数组复制到STM32项目中的arm_nnexamples_cifar10_inputs.h文件中。 6 | 7 | ``` 8 | python resize_image_and_to_array.py path_to_image 9 | ``` -------------------------------------------------------------------------------- /test_images_from_internet/cat00.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/EdgeAI-Lab/cifar10_image_classifier_on_stm32/a3c5e911baf60c745fc9b286675cac057425061c/test_images_from_internet/cat00.png -------------------------------------------------------------------------------- /test_images_from_internet/cat01.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/EdgeAI-Lab/cifar10_image_classifier_on_stm32/a3c5e911baf60c745fc9b286675cac057425061c/test_images_from_internet/cat01.jpg -------------------------------------------------------------------------------- /test_images_from_internet/dog00.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/EdgeAI-Lab/cifar10_image_classifier_on_stm32/a3c5e911baf60c745fc9b286675cac057425061c/test_images_from_internet/dog00.jpg -------------------------------------------------------------------------------- /test_images_from_internet/horse00.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/EdgeAI-Lab/cifar10_image_classifier_on_stm32/a3c5e911baf60c745fc9b286675cac057425061c/test_images_from_internet/horse00.jpg -------------------------------------------------------------------------------- /test_images_from_internet/resize_image_and_to_array.py: -------------------------------------------------------------------------------- 1 | import sys 2 | from PIL import Image, ImageOps 3 | import numpy as np 4 | 5 | np.set_printoptions(threshold=np.inf) 6 | 7 | def resize_image(image, _width=32, _height=32): 8 | new_image = Image.open(image) 9 | new_image = ImageOps.fit(new_image , (_width, _height), Image.ANTIALIAS) 10 | new_image_rgb = new_image.convert('RGB') 11 | return np.asarray(new_image_rgb).flatten() 12 | 13 | def print_array_for_c(_array): 14 | print("{",end="") 15 | for pixel in _array: 16 | print(pixel,end=",") 17 | print("}") 18 | 19 | def main(): 20 | if len(sys.argv) == 2: 21 | print("resize and convert image: "+sys.argv[1]) 22 | print_array_for_c(resize_image(sys.argv[1])) 23 | else: 24 | print("Usage: python resize_image_and_to_array.py path_to_image") 25 | 26 | if __name__ == "__main__": 27 | main() --------------------------------------------------------------------------------