├── LICENSE ├── README.md └── RISC-V Main Modules Designs ├── ALU Control ├── Design.v ├── Elaborated Design.png ├── Implemented Design.png ├── Simulation Output.png └── Testbench.v ├── ALU Decoder ├── Design.v ├── Elaborated Design.png ├── Implemented Design.png ├── Simulation Output.png └── Testbench.v ├── Adder for PCPlus4 ├── Design.v ├── Elaborated Design.png ├── Implemented Design.png ├── Simulation Output.png └── Testbench.v ├── Adder for PCTarget ├── Design.v ├── Elaborated Design.png ├── Implemented Design.png ├── Simulation Output.png └── Testbench.v ├── Arithmetic Logic Unit ├── Design.v ├── Elaborated Design.png ├── Implemented Design.png ├── Simulation Output.png └── Testbench.v ├── Data Memory ├── Close up for Implemented Design.png ├── Design.v ├── Elaborated Design.png ├── Implemented Design.png ├── Simulation Output.png └── Testbench.v ├── Data Path ├── Close up of Implemented Design.png ├── Design.v ├── Elaborated Design.png ├── Implemented Design.png ├── Simulation Output.png └── Testbench.v ├── Extend ├── Design.v ├── Elaborated Design.png ├── Implemented Design.png ├── Simulation Output.png └── Testbench.v ├── Instruction Memory ├── Design.v ├── Elaborated Design.png ├── Implemented Design.png ├── Simulation Output.png └── Testbench.v ├── Main Decoder ├── Design.v ├── Elaborated Design.png ├── Implemented Design.png ├── Simulation Output.png └── Testbench.v ├── Multiplexer for ALUSrc ├── Design.v ├── Elaborated Design.png ├── Implemented Design.png ├── Simulation Output.png └── Testbench.v ├── Multiplexer for PCSrc ├── Design.v ├── Elaborated Design.png ├── Implemented Design.png ├── Simulation Output.png └── Testbench.v ├── Multiplexer for ResultSrc ├── Design.v ├── Elaborated Design.png ├── Implemented Design.png ├── Simulation Output.png └── Testbench.v ├── Program Counter ├── Close up of Implemented Design.png ├── Design.v ├── Elaborated Design.png ├── Implemented Design.png ├── Simulation Output.png └── Testbench.v └── Register File ├── Design.v ├── Elaborated Design.png ├── Implemented Design.png ├── Simulation Output.png └── Testbench.v /LICENSE: -------------------------------------------------------------------------------- 1 | MIT License 2 | 3 | Copyright (c) 2024 Ektha Reddy 4 | MIT License with No-Fork Clause 5 | 6 | Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, publish, merge, and distribute copies of the Software, subject to the following conditions: 7 | 8 | 1. The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. 9 | 2. The name of the original author must remain in all copies or substantial portions of the Software. 10 | 3. The Software may not be forked or modified to create derivative works based on the Software without explicit permission from the original author. 11 | 12 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 13 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # RISC-V Single Cycle Processor Design 2 | 3 | In this repository of RISC-V, you will get to know the main modules of the MIPS Architecture with their codes, testbench and the design using the Verilog Language only. The purpose of this repository is to make an understable and easy-to-go code for the complex project i.e., RISC-V, where anyone with the basic knowledge on the Verilog can create. 4 | 5 | ## Software used 6 | Xilinx Vivado version 2024.1 7 | 8 | This is an industry level tool, which will produce the gate level design, schematic design and it can also implement the code in an FPGA kit by using bitstream generation. 9 | 10 | ## What to expect 11 | The instruction I-type, B-type, S-type snd J-type have been proposed. 12 | This repository will picture out the main idea on various main block of RISC-V along with the excecution of each module in Vivado. 13 | 14 | 15 | ## Architecture Design 16 | 17 | ![image](https://github.com/EkthaReddy/RISC-V-Single-Cycle-Processor/assets/152515939/a96949c0-6e89-426c-97c5-8d158f3afae8) 18 | 19 | ## Instruction Set 20 | 21 | ![image](https://github.com/EkthaReddy/RISC-V-Single-Cycle-Processor/assets/152515939/e5042813-b772-4bf1-a8a8-44d33539c6b8) 22 | 23 | ## ALU Table 24 | 25 | ![image](https://github.com/EkthaReddy/RISC-V-Single-Cycle-Processor/assets/152515939/9b26d4e0-50c2-43be-aef5-47effa00f8ff) 26 | 27 | 28 | 29 | 30 | ## what are the main blocks in this Single cycle processor? 31 | The RISC-V contains the four essential blocks, 32 | #### ‣ [Program Counter](https://github.com/EkthaReddy/RISC-V-Single-Cycle-Processor/tree/main/RISC-V%20Main%20Modules%20Designs/Program%20Counter) 33 | #### ‣ [Instruction Memory](https://github.com/EkthaReddy/RISC-V-Single-Cycle-Processor/tree/main/RISC-V%20Main%20Modules%20Designs/Instruction%20Memory) 34 | #### ‣ [Register File](https://github.com/EkthaReddy/RISC-V-Single-Cycle-Processor/tree/main/RISC-V%20Main%20Modules%20Designs/Register%20File) 35 | #### ‣ [Data Memory](https://github.com/EkthaReddy/RISC-V-Single-Cycle-Processor/tree/main/RISC-V%20Main%20Modules%20Designs/Data%20Memory) 36 | This four blocks are the key componenets of the processor. But, to bluid the whole architecture it is not enough, you need the connecting components for the above which plays a greater role in selecting the data, to ensure data is being read or written to. We need, 37 | #### ‣ Multiplexers - 3 are required 38 | - [**Multiplexer for PCSrc**](https://github.com/EkthaReddy/RISC-V-Single-Cycle-Processor/tree/main/RISC-V%20Main%20Modules%20Designs/Multiplexer%20for%20PCSrc) 39 | - [**Multiplexer for ALUSrc**](https://github.com/EkthaReddy/RISC-V-Single-Cycle-Processor/tree/main/RISC-V%20Main%20Modules%20Designs/Multiplexer%20for%20ALUSrc) 40 | - [**Multiplexer for ResultSrc**](https://github.com/EkthaReddy/RISC-V-Single-Cycle-Processor/blob/main/RISC-V%20Main%20Modules%20Designs/Multiplexer%20for%20ResultSrc/Design.v) 41 | 42 | The count is 3, for selecting their desired selection line which are PCSrc, ALUSrc, ResultSrc. 43 | #### ‣ Adders - 2 are required 44 | - [**Adder for PCPlus4**](https://github.com/EkthaReddy/RISC-V-Single-Cycle-Processor/tree/main/RISC-V%20Main%20Modules%20Designs/Adder%20for%20PCPlus4) 45 | - [**Adder for PCTarget**](https://github.com/EkthaReddy/RISC-V-Single-Cycle-Processor/tree/main/RISC-V%20Main%20Modules%20Designs/Adder%20for%20PCTarget) 46 | 47 | The adder will increment the value. For PCPlus4 the previous input is added with four as an output to give the next input for program counter. And, for PCTarget the addition is between the ImmExt (output of Extend File) and PC input. 48 | #### ‣ [Arithmetic logic unit](https://github.com/EkthaReddy/RISC-V-Single-Cycle-Processor/tree/main/RISC-V%20Main%20Modules%20Designs/Arithmetic%20Logic%20Unit) 49 | #### ‣ [ALU Control unit](https://github.com/EkthaReddy/RISC-V-Single-Cycle-Processor/tree/main/RISC-V%20Main%20Modules%20Designs/ALU%20Control) 50 | ALU Control unit, comprises of the, 51 | 52 | - [**Main Decoder**](https://github.com/EkthaReddy/RISC-V-Single-Cycle-Processor/tree/main/RISC-V%20Main%20Modules%20Designs/Main%20Decoder) 53 | - [**ALU Decoder**](https://github.com/EkthaReddy/RISC-V-Single-Cycle-Processor/tree/main/RISC-V%20Main%20Modules%20Designs/ALU%20Decoder) 54 | 55 | #### ‣ [Extend File](https://github.com/EkthaReddy/RISC-V-Single-Cycle-Processor/tree/main/RISC-V%20Main%20Modules%20Designs/Extend) 56 | #### ‣ [Datapath](https://github.com/EkthaReddy/RISC-V-Single-Cycle-Processor/tree/main/RISC-V%20Main%20Modules%20Designs/Data%20Path) 57 | 58 | All this combined together with the appropriate logic flow will give the architecture of MIPS. 59 | 60 | 61 | **Here is the MIPS generated by using all the sub-modules mentioned above** 62 | 63 | ![Elaborated Design](https://github.com/user-attachments/assets/0292a6bb-dcc1-4124-8592-588b8f058b48) 64 | 65 | 66 | ## What datapath does the load word, store word, and Branch equal word follow 67 | 68 | ### Load Word 69 | Step 1: The type of instruction used will determine the path for data to flow. To explain in simpler ways, the data will follow a path from the program counter at an initial address let's take 1000. It will give the instruction in machine code language after being fed into the instruction Memory. 70 | 71 | 72 | Step 2: The opcode and instruction used will excute path in a certain direction. To know which path to choose, the multiplexer is been placed. 73 | 74 | 75 | Step 3:The sourse register from instruction set is fed into the register file at source operand A1(for single source register) which now gives us SrcA. For SrcB, add the extend file which will convert the small bits to 32 bit wide. 76 | 77 | Note: If two single source register are used then both A1 and A2 source operand are used. 78 | 79 | 80 | Step 4: The SrcA and SrcB will be computed in ALU Logice where it comprise of Main Decoder and ALU Decoder which are controlled by ALU Controller. 81 | 82 | 83 | Step 5: The ALUResult is fed into the Data memory and where the Result is added back to the Register File of WD3. RegWrite is added as a control signal to ALU Controller. 84 | Now, we need the next instruction to pass on, the adder is used which gives output as PCPlus4 which addes the previous input with four. 85 | 86 | 87 | ### Store word 88 | Step 1: The whole structure of store word is almost same like the load word. 89 | The changes to be made are 90 | - Two single source register is used. 91 | - ImmSrc from from extend file and MemWrite from the Data memory as a control signal is supplied to the ALU Controller. 92 | - Second Register is fed into the A2 source operand. 93 | 94 | ### Branch Equal 95 | 96 | Follow the same data path till store word. 97 | additionals are 98 | 99 | - Perform substraction operation on SrcA and SrcB, if the result gives us zero then add zero flag to show the results are obtained for beq instructions. 100 | - ResultSrc and RD is disabled. 101 | - Calcualte the Target Address 102 | PCTarget = PC input + ImmExt 103 | the PCTarget is fed into the Program Counter by using multipler. 104 | 105 | 106 | 107 | ## What does the repository contain? 108 | 109 | You can expect four things which will be given for every modules; 110 | ### Verilog Code 111 | Design of the main modules of risc-v will be build with the logic to implement it in a very simpler way. 112 | ### Testbench 113 | This will test the various case scenario of your main design of the particluar main module to ensure the correctness, range and fulfillment of every test cases given. 114 | ### Simulation output 115 | The simulation will generate the waveform based on the test cases provided in testbench and also make ensure it is instatiating the suitable main design module in the testbench. It will check for errors in the main design and testbench, whether it be syntax, junk error, bit length error or logic flow error. 116 | ### Elaborated Design 117 | After passing the simulation, if the code is meeting the expected ouput, it will show the elaborated design of the module created. 118 | ### Implemented Design 119 | When the synthesis and implementation is successful in vivado, it will produce an implemented design which can are implementable. 120 | -------------------------------------------------------------------------------- /RISC-V Main Modules Designs/ALU Control/Design.v: -------------------------------------------------------------------------------- 1 | 2 | module ALUControl( 3 | input [6:0] op, 4 | input [2:0] funct3, 5 | input funct7, 6 | input zero, 7 | output wire PCSrc, 8 | output wire jump, 9 | output wire ALUSrc, 10 | output wire RegWrite, 11 | output wire MemWrite, 12 | output wire branch, 13 | output wire [1:0] ImmSrc, 14 | output wire [2:0] ALUControl 15 | ); 16 | wire [1:0] ALUop; 17 | MainDecoder md(op, RegWrite, MemWrite, branch, ALUSrc, ALUop, ImmSrc); 18 | ALUDecoder ad(op, funct3, funct7, ALUop, ALUControl); 19 | 20 | assign PCSrc = branch & zero | jump; 21 | endmodule 22 | -------------------------------------------------------------------------------- /RISC-V Main Modules Designs/ALU Control/Elaborated Design.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/EkthaReddy/RISC-V-Single-Cycle-Processor/1ce946ef061feb79c6e2539f8247bd11a78d83ac/RISC-V Main Modules Designs/ALU Control/Elaborated Design.png -------------------------------------------------------------------------------- /RISC-V Main Modules Designs/ALU Control/Implemented Design.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/EkthaReddy/RISC-V-Single-Cycle-Processor/1ce946ef061feb79c6e2539f8247bd11a78d83ac/RISC-V Main Modules Designs/ALU Control/Implemented Design.png -------------------------------------------------------------------------------- /RISC-V Main Modules Designs/ALU Control/Simulation Output.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/EkthaReddy/RISC-V-Single-Cycle-Processor/1ce946ef061feb79c6e2539f8247bd11a78d83ac/RISC-V Main Modules Designs/ALU Control/Simulation Output.png -------------------------------------------------------------------------------- /RISC-V Main Modules Designs/ALU Control/Testbench.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns/1ps 2 | 3 | module ALUControl_tb; 4 | // Inputs 5 | reg [6:0] op; 6 | reg [2:0] funct3; 7 | reg funct7; 8 | reg zero; 9 | 10 | // Outputs 11 | wire PCSrc; 12 | wire jump; 13 | wire ALUSrc; 14 | wire RegWrite; 15 | wire MemWrite; 16 | wire branch; 17 | wire [1:0] ImmSrc; 18 | wire [2:0] ALUControl; 19 | 20 | // Instantiate the ALUControl module 21 | ALUControl uut ( 22 | .op(op), 23 | .funct3(funct3), 24 | .funct7(funct7), 25 | .zero(zero), 26 | .PCSrc(PCSrc), 27 | .jump(jump), 28 | .ALUSrc(ALUSrc), 29 | .RegWrite(RegWrite), 30 | .MemWrite(MemWrite), 31 | .branch(branch), 32 | .ImmSrc(ImmSrc), 33 | .ALUControl(ALUControl) 34 | ); 35 | 36 | // Initialize inputs and apply stimulus 37 | initial begin 38 | // Initialize signals 39 | op = 7'b0000000; 40 | funct3 = 3'b000; 41 | funct7 = 1'b0; 42 | zero = 1'b0; 43 | 44 | // Apply test cases 45 | // Test Case 1: Load Word Instruction 46 | op = 7'b0000011; 47 | #10; 48 | 49 | // Test Case 2: Store Word Instruction 50 | op = 7'b0100011; 51 | #10; 52 | 53 | // Test Case 3: Branch Instruction 54 | op = 7'b1100011; 55 | zero = 1'b1; 56 | #10; 57 | 58 | // Test Case 4: J-type Instruction (JAL) 59 | op = 7'b1101111; 60 | #10; 61 | 62 | // Test Case 5: I-type Load Instruction 63 | op = 7'b0000011; 64 | funct3 = 3'b010; 65 | #10; 66 | 67 | // End simulation 68 | $finish; 69 | end 70 | endmodule 71 | -------------------------------------------------------------------------------- /RISC-V Main Modules Designs/ALU Decoder/Design.v: -------------------------------------------------------------------------------- 1 | 2 | module ALUDecoder( 3 | input [6:0] op, 4 | input [2:0] funct3, 5 | input funct7, 6 | input [1:0] ALUop, 7 | output reg [2:0] ALUControl 8 | ); 9 | always @(*) begin 10 | if (ALUop == 2'b00) begin 11 | ALUControl <= 3'b000; // ADD 12 | end else if (ALUop == 2'b01) begin 13 | ALUControl <= 3'b001; // SUB 14 | end else if (ALUop == 2'b10) begin 15 | case({funct7, funct3, op}) 16 | 10'b0000000_000: ALUControl <= 3'b000; 17 | 10'b0100000_000: ALUControl <= 3'b001; 18 | 10'b0000000_111: ALUControl <= 3'b011; 19 | 10'b0000000_110: ALUControl <= 3'b010; 20 | default: ALUControl <= 3'bxxx; 21 | endcase 22 | end 23 | end 24 | endmodule 25 | -------------------------------------------------------------------------------- /RISC-V Main Modules Designs/ALU Decoder/Elaborated Design.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/EkthaReddy/RISC-V-Single-Cycle-Processor/1ce946ef061feb79c6e2539f8247bd11a78d83ac/RISC-V Main Modules Designs/ALU Decoder/Elaborated Design.png -------------------------------------------------------------------------------- /RISC-V Main Modules Designs/ALU Decoder/Implemented Design.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/EkthaReddy/RISC-V-Single-Cycle-Processor/1ce946ef061feb79c6e2539f8247bd11a78d83ac/RISC-V Main Modules Designs/ALU Decoder/Implemented Design.png -------------------------------------------------------------------------------- /RISC-V Main Modules Designs/ALU Decoder/Simulation Output.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/EkthaReddy/RISC-V-Single-Cycle-Processor/1ce946ef061feb79c6e2539f8247bd11a78d83ac/RISC-V Main Modules Designs/ALU Decoder/Simulation Output.png -------------------------------------------------------------------------------- /RISC-V Main Modules Designs/ALU Decoder/Testbench.v: -------------------------------------------------------------------------------- 1 | module ALUDecoder_tb; 2 | 3 | // Testbench signals 4 | reg [6:0] op; 5 | reg [2:0] funct3; 6 | reg funct7; 7 | reg [1:0] ALUop; 8 | wire [2:0] ALUControl; 9 | 10 | // Instantiate the ALUDecoder 11 | ALUDecoder uut ( 12 | .op(op), 13 | .funct3(funct3), 14 | .funct7(funct7), 15 | .ALUop(ALUop), 16 | .ALUControl(ALUControl) 17 | ); 18 | 19 | // Testbench logic 20 | initial begin 21 | $dumpfile("dump.file"); 22 | $dumpvars; 23 | // Initialize inputs 24 | op = 7'b0000000; 25 | funct3 = 3'b000; 26 | funct7 = 1'b0; 27 | ALUop = 2'b00; 28 | 29 | // Apply test vectors 30 | #10; 31 | ALUop = 2'b00; // Test ADD 32 | #10; 33 | ALUop = 2'b01; // Test SUB 34 | #10; 35 | ALUop = 2'b10; // Test R-type instructions 36 | 37 | // Test ADD 38 | op = 7'b0000000; 39 | funct3 = 3'b000; 40 | funct7 = 1'b0; 41 | #10; 42 | 43 | // Test SUB 44 | op = 7'b0100000; 45 | funct3 = 3'b000; 46 | funct7 = 1'b0; 47 | #10; 48 | 49 | // Test AND 50 | op = 7'b0000000; 51 | funct3 = 3'b111; 52 | funct7 = 1'b0; 53 | #10; 54 | 55 | // Test OR 56 | op = 7'b0000000; 57 | funct3 = 3'b110; 58 | funct7 = 1'b0; 59 | #10; 60 | 61 | // Default case (unexpected combination) 62 | op = 7'b1111111; 63 | funct3 = 3'b111; 64 | funct7 = 1'b1; 65 | #10; 66 | 67 | // End simulation 68 | $finish; 69 | end 70 | endmodule 71 | -------------------------------------------------------------------------------- /RISC-V Main Modules Designs/Adder for PCPlus4/Design.v: -------------------------------------------------------------------------------- 1 | // Adder for result PCPlus4 2 | 3 | module Adder_for_PCPlus4( 4 | input pc_out, 5 | output PCPlus4 6 | ); 7 | assign PCPlus4 = pc_out + 4; // Increment for next instruction in program counter by four 8 | endmodule 9 | -------------------------------------------------------------------------------- /RISC-V Main Modules Designs/Adder for PCPlus4/Elaborated Design.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/EkthaReddy/RISC-V-Single-Cycle-Processor/1ce946ef061feb79c6e2539f8247bd11a78d83ac/RISC-V Main Modules Designs/Adder for PCPlus4/Elaborated Design.png -------------------------------------------------------------------------------- /RISC-V Main Modules Designs/Adder for PCPlus4/Implemented Design.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/EkthaReddy/RISC-V-Single-Cycle-Processor/1ce946ef061feb79c6e2539f8247bd11a78d83ac/RISC-V Main Modules Designs/Adder for PCPlus4/Implemented Design.png -------------------------------------------------------------------------------- /RISC-V Main Modules Designs/Adder for PCPlus4/Simulation Output.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/EkthaReddy/RISC-V-Single-Cycle-Processor/1ce946ef061feb79c6e2539f8247bd11a78d83ac/RISC-V Main Modules Designs/Adder for PCPlus4/Simulation Output.png -------------------------------------------------------------------------------- /RISC-V Main Modules Designs/Adder for PCPlus4/Testbench.v: -------------------------------------------------------------------------------- 1 | // Testbench 2 | 3 | module Adder_for_PCPlus4_tb; 4 | reg pc_out; 5 | wire PCPlus4; 6 | 7 | Adder_for_PCPlus4 dut(pc_out, PCPlus4); 8 | 9 | initial begin 10 | $dumpfile("dump.file"); 11 | $dumpvars; 12 | 13 | pc_out<=1'b0; 14 | 15 | #10 $finish(); 16 | end 17 | 18 | always #2 pc_out<=~pc_out; 19 | 20 | endmodule 21 | 22 | 23 | -------------------------------------------------------------------------------- /RISC-V Main Modules Designs/Adder for PCTarget/Design.v: -------------------------------------------------------------------------------- 1 | // Design of Adder for result PC Target 2 | 3 | module Adder_for_PCTarget( 4 | input pc_out, ImmExt, 5 | output PCTarget 6 | ); 7 | 8 | assign PCTarget = pc_out + ImmExt; 9 | 10 | endmodule 11 | 12 | -------------------------------------------------------------------------------- /RISC-V Main Modules Designs/Adder for PCTarget/Elaborated Design.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/EkthaReddy/RISC-V-Single-Cycle-Processor/1ce946ef061feb79c6e2539f8247bd11a78d83ac/RISC-V Main Modules Designs/Adder for PCTarget/Elaborated Design.png -------------------------------------------------------------------------------- /RISC-V Main Modules Designs/Adder for PCTarget/Implemented Design.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/EkthaReddy/RISC-V-Single-Cycle-Processor/1ce946ef061feb79c6e2539f8247bd11a78d83ac/RISC-V Main Modules Designs/Adder for PCTarget/Implemented Design.png -------------------------------------------------------------------------------- /RISC-V Main Modules Designs/Adder for PCTarget/Simulation Output.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/EkthaReddy/RISC-V-Single-Cycle-Processor/1ce946ef061feb79c6e2539f8247bd11a78d83ac/RISC-V Main Modules Designs/Adder for PCTarget/Simulation Output.png -------------------------------------------------------------------------------- /RISC-V Main Modules Designs/Adder for PCTarget/Testbench.v: -------------------------------------------------------------------------------- 1 | // Testbench 2 | 3 | module Adder_for_PCTarget_tb; 4 | 5 | reg pc_out, ImmExt; 6 | wire PCTarget; 7 | 8 | Adder_for_PCTarget dut(pc_out, ImmExt, PCTarget); 9 | 10 | initial begin 11 | $dumpfile("dump.file"); 12 | $dumpvars; 13 | 14 | pc_out<=1'b0; 15 | ImmExt<=1'b0; 16 | 17 | #10 $finish(); 18 | end 19 | 20 | always #2 pc_out<=~pc_out; 21 | always #2 ImmExt<=~ImmExt; 22 | 23 | endmodule 24 | -------------------------------------------------------------------------------- /RISC-V Main Modules Designs/Arithmetic Logic Unit/Design.v: -------------------------------------------------------------------------------- 1 | module ALU( 2 | input [31:0] SrcA, SrcB, 3 | input [2:0] ALUControl, 4 | output reg zero, 5 | output reg [31:0] ALUResult 6 | ); 7 | always @(*) begin 8 | case(ALUControl) 9 | 3'b000: ALUResult <= SrcA + SrcB; // Addition 10 | 3'b001: ALUResult <= SrcA - SrcB; // Subtraction 11 | 3'b010: ALUResult <= SrcA & SrcB; // AND operation 12 | 3'b011: ALUResult <= SrcA | SrcB; // OR operation 13 | 3'b100: ALUResult <= (SrcA < SrcB) ? 1 : 0 ; // SLT (set less than) operation 14 | 3'b101: zero <= (SrcA == SrcB); // BEQ (Branch if equal) operation 15 | default: ALUResult <= 32'bx; // DONT CARE 16 | endcase 17 | end 18 | endmodule 19 | -------------------------------------------------------------------------------- /RISC-V Main Modules Designs/Arithmetic Logic Unit/Elaborated Design.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/EkthaReddy/RISC-V-Single-Cycle-Processor/1ce946ef061feb79c6e2539f8247bd11a78d83ac/RISC-V Main Modules Designs/Arithmetic Logic Unit/Elaborated Design.png -------------------------------------------------------------------------------- /RISC-V Main Modules Designs/Arithmetic Logic Unit/Implemented Design.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/EkthaReddy/RISC-V-Single-Cycle-Processor/1ce946ef061feb79c6e2539f8247bd11a78d83ac/RISC-V Main Modules Designs/Arithmetic Logic Unit/Implemented Design.png -------------------------------------------------------------------------------- /RISC-V Main Modules Designs/Arithmetic Logic Unit/Simulation Output.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/EkthaReddy/RISC-V-Single-Cycle-Processor/1ce946ef061feb79c6e2539f8247bd11a78d83ac/RISC-V Main Modules Designs/Arithmetic Logic Unit/Simulation Output.png -------------------------------------------------------------------------------- /RISC-V Main Modules Designs/Arithmetic Logic Unit/Testbench.v: -------------------------------------------------------------------------------- 1 | // Testbench 2 | 3 | module ALU_tb; 4 | 5 | reg [1:0] A, B; 6 | reg [2:0] ALUControl; 7 | wire zero; 8 | wire [2:0] ALUResult; 9 | 10 | // Instantiate the ALU module 11 | ALU uut (.A(A), .B(B), .ALUControl(ALUControl), .zero(zero), .ALUResult(ALUResult)); 12 | 13 | initial begin 14 | $dumpfile("dump.vcd"); 15 | $dumpvars(0); 16 | 17 | 18 | // Test Add operation (ALUControl = 3'b000) 19 | A = 2'b01; B = 2'b01; ALUControl = 3'b000; 20 | #10; 21 | 22 | // Test Subtract operation (ALUControl = 3'b001) 23 | A = 2'b10; B = 2'b01; ALUControl = 3'b001; 24 | #10; 25 | 26 | // Test AND operation (ALUControl = 3'b010) 27 | A = 2'b11; B = 2'b01; ALUControl = 3'b010; 28 | #10; 29 | 30 | // Test OR operation (ALUControl = 3'b011) 31 | A = 2'b10; B = 2'b01; ALUControl = 3'b011; 32 | #10; 33 | 34 | // Test SLT operation (ALUControl = 3'b100) 35 | A = 2'b01; B = 2'b10; ALUControl = 3'b100; 36 | #10; 37 | 38 | // Test BEQ operation (ALUControl = 3'b101) 39 | A = 2'b01; B = 2'b10; ALUControl = 3'b101; 40 | #10; 41 | 42 | // Test default case 43 | ALUControl = 3'b111; 44 | #10; 45 | 46 | // End the simulation 47 | $finish; 48 | end 49 | endmodule 50 | -------------------------------------------------------------------------------- /RISC-V Main Modules Designs/Data Memory/Close up for Implemented Design.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/EkthaReddy/RISC-V-Single-Cycle-Processor/1ce946ef061feb79c6e2539f8247bd11a78d83ac/RISC-V Main Modules Designs/Data Memory/Close up for Implemented Design.png -------------------------------------------------------------------------------- /RISC-V Main Modules Designs/Data Memory/Design.v: -------------------------------------------------------------------------------- 1 | // Design of Data Memory 2 | 3 | module Data_Memory( 4 | input clk, WE, 5 | input [31:0]A, // Address Input 6 | input [31:0] WD, // Write Data Input 7 | output [31:0]RD // Read Data Output 8 | ); 9 | reg [31:0] mem[63:0]; // Memory of 64 register each 32 bit wide 10 | 11 | assign RD = mem[A[31:2]]; 12 | 13 | always @(posedge clk) begin 14 | if (WE) 15 | mem[A[31:2]]<= WD; 16 | end 17 | 18 | 19 | endmodule 20 | -------------------------------------------------------------------------------- /RISC-V Main Modules Designs/Data Memory/Elaborated Design.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/EkthaReddy/RISC-V-Single-Cycle-Processor/1ce946ef061feb79c6e2539f8247bd11a78d83ac/RISC-V Main Modules Designs/Data Memory/Elaborated Design.png -------------------------------------------------------------------------------- /RISC-V Main Modules Designs/Data Memory/Implemented Design.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/EkthaReddy/RISC-V-Single-Cycle-Processor/1ce946ef061feb79c6e2539f8247bd11a78d83ac/RISC-V Main Modules Designs/Data Memory/Implemented Design.png -------------------------------------------------------------------------------- /RISC-V Main Modules Designs/Data Memory/Simulation Output.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/EkthaReddy/RISC-V-Single-Cycle-Processor/1ce946ef061feb79c6e2539f8247bd11a78d83ac/RISC-V Main Modules Designs/Data Memory/Simulation Output.png -------------------------------------------------------------------------------- /RISC-V Main Modules Designs/Data Memory/Testbench.v: -------------------------------------------------------------------------------- 1 | // Testbench for Data Memory 2 | 3 | `timescale 1ns / 1ps 4 | 5 | module Data_Memory_tb(); 6 | 7 | // Inputs 8 | reg clk; 9 | reg WE; 10 | reg [31:0] A; 11 | reg [31:0] WD; 12 | 13 | // Outputs 14 | wire [31:0] RD; 15 | 16 | // Instantiate the module under test 17 | Data_Memory dut ( 18 | .clk(clk), 19 | .WE(WE), 20 | .A(A), 21 | .WD(WD), 22 | .RD(RD) 23 | ); 24 | 25 | // Clock generation 26 | always begin 27 | clk = 0; 28 | #5; 29 | clk = 1; 30 | #5; 31 | end 32 | 33 | // Testbench stimulus 34 | initial begin 35 | // Initialize inputs 36 | WE = 1; 37 | A = 32'h00000004; // Example address (assuming little-endian) 38 | WD = 32'hABCDEFFF; // Example data to write 39 | 40 | // Wait a few clock cycles 41 | #20; 42 | 43 | // Change inputs for a read operation 44 | WE = 0; 45 | A = 32'h00000004; // Example address for read 46 | 47 | // Wait a few clock cycles 48 | #20; 49 | 50 | // Add more test cases as needed 51 | 52 | // End simulation 53 | $finish; 54 | end 55 | 56 | endmodule 57 | -------------------------------------------------------------------------------- /RISC-V Main Modules Designs/Data Path/Close up of Implemented Design.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/EkthaReddy/RISC-V-Single-Cycle-Processor/1ce946ef061feb79c6e2539f8247bd11a78d83ac/RISC-V Main Modules Designs/Data Path/Close up of Implemented Design.png -------------------------------------------------------------------------------- /RISC-V Main Modules Designs/Data Path/Design.v: -------------------------------------------------------------------------------- 1 | // Logic Blocks of RISC-v Processor 2 | 3 | ///////////////////Logic for MUX for PCSrc///////////////////////////////////////////////////////////////////////////////////////////////// 4 | 5 | module MUX_for_PCSrc( 6 | input PCPlus4, PCTarget, PCSrc, 7 | output PCNext 8 | ); 9 | 10 | assign PCNext = PCSrc?PCTarget:PCPlus4; 11 | endmodule 12 | 13 | /////////////////PC Logic////////////////////////////////////////////////////////////////////////////////////////////////////////////////// 14 | module program_counter( 15 | input clk, reset, 16 | input [31:0] pc_in, 17 | output reg [31:0] pc_out 18 | ); 19 | always@(posedge clk) 20 | if (reset) 21 | pc_out<=pc_in; 22 | else 23 | pc_out<=pc_in + 4; 24 | endmodule 25 | ///////////////Logic of Adder for PCPlus4//////////////////////////////////////////////////////////////////////////////////////////////////// 26 | 27 | module Adder_for_PCPlus4( 28 | input pc_out, 29 | output PCPlus4 30 | ); 31 | 32 | assign PCPlus4 = pc_out + 4; 33 | endmodule 34 | 35 | //////////////////Logic of Adder for PCTarget///////////////////////////////////////////////////////////////////////////////////////////// 36 | module Adder_for_PCTarget( 37 | input pc_out, ImmExt, 38 | output PCTarget 39 | ); 40 | 41 | assign PCTarget = pc_out + ImmExt; 42 | 43 | endmodule 44 | 45 | ///////////////////////Logic for Instruction Memory//////////////////////////////////////// 46 | module Instruction_Memory( 47 | input [31:0]A, // Address input 48 | output reg [31:0]RD // Instruction output 49 | ); 50 | // Instruction memory array (ROM) 51 | reg [31:0] mem[63:0]; 52 | 53 | // Initialize the ROM with the program instructions 54 | initial begin 55 | mem[0] = 32'h00500093; // li x1, 5 (addi x1, x0, 5) 56 | mem[1] = 32'h00A00113; // li x2, 10 (addi x2, x0, 10) 57 | mem[2] = 32'h002081B3; // add x3, x1, x2 58 | mem[3] = 32'h00300023; // sw x3, 0(x0) 59 | end 60 | 61 | // Read operation 62 | always @(*) begin 63 | RD = mem[A[31:2]]; // Address decoding (assuming word addressing) 64 | end 65 | endmodule 66 | 67 | ////////////////////////// Logic for Register File////////////////////////////////////////// 68 | 69 | module RegFile( 70 | input WE3, clk, 71 | input [4:0] A1, 72 | input [4:0] A2, 73 | input [4:0] A3, 74 | input [31:0] WD3, 75 | output reg [31:0] RD1, 76 | output reg [31:0] RD2 77 | ); 78 | 79 | reg [31:0] register_file[31:0]; 80 | 81 | always@(posedge clk) 82 | if (WE3) 83 | register_file[A3] <= WD3; 84 | 85 | always@(*) begin 86 | RD1 = (A1==1)? register_file[A1]:0; 87 | RD2 = (A2==1)? register_file[A2]:0; 88 | end 89 | 90 | endmodule 91 | 92 | /////////////////Logic of MUX for ALUSrc///////////////////////////////////////////////////// 93 | 94 | module MUX_for_ALUSrc( 95 | input RD2, ImmExt, ALUSrc, 96 | output SrcB 97 | ); 98 | assign SrcB=ALUSrc?ImmExt:RD2; 99 | endmodule 100 | 101 | //////////////////Logic of Extend/////////////////////////////////////////////////////////// 102 | 103 | module Extend( 104 | input [31:7]instruction, 105 | input [1:0]ImmSrc, 106 | output reg [31:0]ImmExt 107 | ); 108 | 109 | always@(*) begin 110 | case(ImmSrc) 111 | 2'b00: ImmExt = {{20{instruction[31]}}, instruction[31:20]};// I 112 | 2'b01: ImmExt = {{20{instruction[31]}}, instruction[31:25], instruction[11:7]};// S 113 | 2'b10: ImmExt = {{20{instruction[31]}}, instruction[7], instruction[30:25], instruction[11:8], 1'b0};// B 114 | 2'b11: ImmExt = {{12{instruction[31]}}, instruction[19:12], instruction[20], instruction[30:21], 1'b0};// J 115 | endcase 116 | end 117 | endmodule 118 | 119 | ////////////////////////// Logic For ALU///////////////////////////////////////////////////// 120 | module ALU( 121 | input [31:0] SrcA, SrcB, 122 | input [2:0] ALUControl, 123 | output reg zero, 124 | output reg [31:0] ALUResult 125 | ); 126 | always @(*) begin 127 | case(ALUControl) 128 | 3'b000: ALUResult <= SrcA + SrcB; // Addition 129 | 3'b001: ALUResult <= SrcA - SrcB; // Subtraction 130 | 3'b010: ALUResult <= SrcA & SrcB; // AND operation 131 | 3'b011: ALUResult <= SrcA | SrcB; // OR operation 132 | 3'b100: ALUResult <= (SrcA < SrcB) ? 1 : 0 ; // SLT (set less than) operation 133 | 3'b101: zero <= (SrcA == SrcB); // BEQ (Branch if equal) operation 134 | default: ALUResult <= 32'bx; // DONT CARE 135 | endcase 136 | end 137 | endmodule 138 | 139 | 140 | /////////////////////////Logic for ALU Decoder////////////////////////////////////////// 141 | 142 | module ALUDecoder( 143 | input [6:0] op, 144 | input [2:0] funct3, 145 | input funct7, 146 | input [1:0] ALUop, 147 | output reg [2:0] ALUControl 148 | ); 149 | always @(*) begin 150 | if (ALUop == 2'b00) begin 151 | ALUControl <= 3'b000; // ADD 152 | end else if (ALUop == 2'b01) begin 153 | ALUControl <= 3'b001; // SUB 154 | end else if (ALUop == 2'b10) begin 155 | case({funct7, funct3, op}) 156 | 10'b0000000_000: ALUControl <= 3'b000; 157 | 10'b0100000_000: ALUControl <= 3'b001; 158 | 10'b0000000_111: ALUControl <= 3'b011; 159 | 10'b0000000_110: ALUControl <= 3'b010; 160 | default: ALUControl <= 3'bxxx; 161 | endcase 162 | end 163 | end 164 | endmodule 165 | 166 | 167 | /////////////////////Logic for Main Decoder//////////////////////////////////////////////////// 168 | module MainDecoder( 169 | input [6:0] op, 170 | output reg RegWrite, 171 | output reg MemWrite, 172 | output reg Branch, 173 | output reg ALUSrc, 174 | output reg [1:0] ALUop, 175 | output reg [1:0] ImmSrc 176 | ); 177 | always @(*) begin 178 | case(op) 179 | 7'b0000011: begin // Load Word Instruction 180 | RegWrite <= 1; 181 | MemWrite <= 0; 182 | Branch <= 0; 183 | ALUSrc <= 1; 184 | ALUop <= 2'b00; 185 | ImmSrc <= 2'b00; 186 | end 187 | 7'b0100011: begin // Store Word Instruction 188 | RegWrite <= 0; 189 | MemWrite <= 1; 190 | Branch <= 0; 191 | ALUSrc <= 1; 192 | ALUop <= 2'b00; 193 | ImmSrc <= 2'b01; 194 | end 195 | 7'b1100011: begin // Branch Instruction 196 | RegWrite <= 0; 197 | MemWrite <= 0; 198 | Branch <= 1; 199 | ALUSrc <= 0; 200 | ALUop <= 2'b01; 201 | ImmSrc <= 2'b10; 202 | end 203 | 7'b0010011: begin // I-type Instruction 204 | RegWrite <= 1; 205 | MemWrite <= 0; 206 | Branch <= 0; 207 | ALUSrc <= 1; 208 | ALUop <= 2'b10; 209 | ImmSrc <= 2'b00; 210 | end 211 | default: begin 212 | RegWrite <= 0; 213 | MemWrite <= 0; 214 | Branch <= 0; 215 | ALUSrc <= 0; 216 | ALUop <= 2'b00; 217 | ImmSrc <= 2'b00; 218 | end 219 | endcase 220 | end 221 | endmodule 222 | 223 | //////////////////////////Logic for ALU Control/////////////////////////////////////////////////// 224 | 225 | module ALUControl( 226 | input [6:0] op, 227 | input [2:0] funct3, 228 | input funct7, 229 | input zero, 230 | output wire PCSrc, 231 | output wire jump, 232 | output wire ALUSrc, 233 | output wire RegWrite, 234 | output wire MemWrite, 235 | output wire branch, 236 | output wire [1:0] ImmSrc, 237 | output wire [2:0] ALUControl 238 | ); 239 | wire [1:0] ALUop; 240 | MainDecoder md(op, RegWrite, MemWrite, branch, ALUSrc, ALUop, ImmSrc); 241 | ALUDecoder ad(op, funct3, funct7, ALUop, ALUControl); 242 | 243 | assign PCSrc = branch & zero | jump; 244 | endmodule 245 | 246 | 247 | /////////////////////Logic for Data Memory////////////////////////////////////////////////////////// 248 | module Data_Memory( 249 | input clk, WE, 250 | input [31:0]A, 251 | input [31:0] WD, 252 | output [31:0]RD 253 | ); 254 | reg [31:0] mem[63:0]; 255 | 256 | assign RD = mem[A[31:2]]; 257 | 258 | always @(posedge clk) begin 259 | if (WE) 260 | mem[A[31:2]]<= WD; 261 | end 262 | 263 | endmodule 264 | 265 | 266 | //////////////////Logic for MUX for ResultSrc//////////////////////////////////////////////// 267 | 268 | module MUX_for_ResultSrc( 269 | input [31:0] ALUResult, 270 | input [31:0] RD, 271 | input [31:0] PCPlus4, 272 | input [1:0] ResultSrc, 273 | output reg [31:0] Result 274 | ); 275 | always @(*) begin 276 | case (ResultSrc) 277 | 2'b00: Result = ALUResult; // Select ALUResult 278 | 2'b01: Result = RD; // Select RD 279 | 2'b10: Result = PCPlus4; // Select PCPlus4 280 | default: Result = 32'b0; // Default case (can be defined as needed) 281 | endcase 282 | end 283 | endmodule 284 | 285 | /////////////////////////// Logic for Datapath////////////////////////////////////////////////////////// 286 | module Data_Path( 287 | input clk, reset, 288 | input PCSrc, jump, ALUSrc, RegWrite, 289 | input [1:0] MemWrite, ResultSrc, 290 | input [2:0] ALUControl, 291 | input [1:0] ImmSrc, 292 | input [31:0] instruction, 293 | output zero, 294 | output [31:0] PC, 295 | output [31:0] WriteData, 296 | output [31:0] ReadData, 297 | output [31:0] ALUResult 298 | ); 299 | wire [31:0] PCNext, PCPlus4, ImmExt, PCTarget, Result, SrcA, SrcB; 300 | wire [31:0] PC_out; 301 | 302 | // PC Logic flow 303 | program_counter pc(clk, reset, PCNext, PC_out); 304 | Adder_for_PCPlus4 a1(PC_out, PCPlus4); 305 | Adder_for_PCTarget a2(PC_out, ImmExt, PCTarget); 306 | MUX_for_PCSrc m1(PCPlus4, PCTarget, PCSrc, PCNext); 307 | 308 | // Register File Logic Flow 309 | RegFile rf(RegWrite, clk, instruction[19:15], instruction[24:20], instruction[11:7], Result, SrcA, WriteData); 310 | Extend e(instruction[31:7], ImmSrc, ImmExt); 311 | 312 | // ALU Logic 313 | MUX_for_ALUSrc m2(WriteData, ImmExt, ALUSrc, SrcB); 314 | ALU alu(SrcA, SrcB, ALUControl, zero, ALUResult); 315 | 316 | // Data Memory Logic 317 | Data_Memory dm(clk, MemWrite, ALUResult, WriteData, ReadData); 318 | 319 | // MUX for ResultSrc 320 | MUX_for_ResultSrc m3(ALUResult, ReadData, PCPlus4, ResultSrc, Result); 321 | 322 | // Output Assignments 323 | assign PC = PC_out; 324 | endmodule 325 | -------------------------------------------------------------------------------- /RISC-V Main Modules Designs/Data Path/Elaborated Design.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/EkthaReddy/RISC-V-Single-Cycle-Processor/1ce946ef061feb79c6e2539f8247bd11a78d83ac/RISC-V Main Modules Designs/Data Path/Elaborated Design.png -------------------------------------------------------------------------------- /RISC-V Main Modules Designs/Data Path/Implemented Design.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/EkthaReddy/RISC-V-Single-Cycle-Processor/1ce946ef061feb79c6e2539f8247bd11a78d83ac/RISC-V Main Modules Designs/Data Path/Implemented Design.png -------------------------------------------------------------------------------- /RISC-V Main Modules Designs/Data Path/Simulation Output.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/EkthaReddy/RISC-V-Single-Cycle-Processor/1ce946ef061feb79c6e2539f8247bd11a78d83ac/RISC-V Main Modules Designs/Data Path/Simulation Output.png -------------------------------------------------------------------------------- /RISC-V Main Modules Designs/Data Path/Testbench.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module RISC_V_Testbench; 4 | 5 | // Clock and Reset Signals 6 | reg clk; 7 | reg reset; 8 | 9 | // Outputs from the Data Path 10 | wire zero; 11 | wire [31:0] PC; 12 | wire [31:0] WriteData; 13 | wire [31:0] ReadData; 14 | wire [31:0] ALUResult; 15 | 16 | // Wires for the control signals 17 | wire PCSrc, jump, ALUSrc, RegWrite; 18 | wire [1:0] MemWrite, ResultSrc; 19 | wire [2:0] ALUControl; 20 | wire [1:0] ImmSrc; 21 | 22 | // Instruction memory output 23 | wire [31:0] instruction; 24 | 25 | 26 | // Instantiate the Data Path 27 | Data_Path datapath( 28 | .clk(clk), 29 | .reset(reset), 30 | .PCSrc(PCSrc), 31 | .jump(jump), 32 | .ALUSrc(ALUSrc), 33 | .RegWrite(RegWrite), 34 | .MemWrite(MemWrite), 35 | .ResultSrc(ResultSrc), 36 | .ALUControl(ALUControl), 37 | .ImmSrc(ImmSrc), 38 | .instruction(instruction), 39 | .zero(zero), 40 | .PC(PC), 41 | .WriteData(WriteData), 42 | .ReadData(ReadData), 43 | .ALUResult(ALUResult) 44 | ); 45 | 46 | 47 | initial begin 48 | $dumpfile("dump.vcd"); 49 | $dumpvars(0); 50 | 51 | clk <=1'b0; 52 | reset <=1'b0; 53 | 54 | 55 | 56 | #10 $finish(); 57 | end 58 | 59 | always #2 clk<=~clk; 60 | always #1.2 reset<=~reset; 61 | 62 | 63 | endmodule 64 | 65 | -------------------------------------------------------------------------------- /RISC-V Main Modules Designs/Extend/Design.v: -------------------------------------------------------------------------------- 1 | 2 | module Extend( 3 | input [31:7]instruction, 4 | input [1:0]ImmSrc, 5 | output reg [31:0]ImmExt 6 | ); 7 | 8 | always@(*) begin 9 | case(ImmSrc) 10 | 2'b00: ImmExt = {{20{instruction[31]}}, instruction[31:20]};// I 11 | 2'b01: ImmExt = {{20{instruction[31]}}, instruction[31:25], instruction[11:7]};// S 12 | 2'b10: ImmExt = {{20{instruction[31]}}, instruction[7], instruction[30:25], instruction[11:8], 1'b0};// B 13 | 2'b11: ImmExt = {{12{instruction[31]}}, instruction[19:12], instruction[20], instruction[30:21], 1'b0};// J 14 | endcase 15 | end 16 | endmodule 17 | -------------------------------------------------------------------------------- /RISC-V Main Modules Designs/Extend/Elaborated Design.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/EkthaReddy/RISC-V-Single-Cycle-Processor/1ce946ef061feb79c6e2539f8247bd11a78d83ac/RISC-V Main Modules Designs/Extend/Elaborated Design.png -------------------------------------------------------------------------------- /RISC-V Main Modules Designs/Extend/Implemented Design.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/EkthaReddy/RISC-V-Single-Cycle-Processor/1ce946ef061feb79c6e2539f8247bd11a78d83ac/RISC-V Main Modules Designs/Extend/Implemented Design.png -------------------------------------------------------------------------------- /RISC-V Main Modules Designs/Extend/Simulation Output.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/EkthaReddy/RISC-V-Single-Cycle-Processor/1ce946ef061feb79c6e2539f8247bd11a78d83ac/RISC-V Main Modules Designs/Extend/Simulation Output.png -------------------------------------------------------------------------------- /RISC-V Main Modules Designs/Extend/Testbench.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module Extend_tb; 4 | 5 | reg [31:7] instruction; 6 | reg [1:0] ImmSrc; 7 | wire [31:0] ImmExt; 8 | 9 | Extend dut ( 10 | .instruction(instruction), 11 | .ImmSrc(ImmSrc), 12 | .ImmExt(ImmExt) 13 | ); 14 | 15 | initial begin 16 | $dumpfile("dump.vcd"); 17 | $dumpvars(0, Extend_tb); 18 | 19 | instruction = 25'b0; 20 | ImmSrc = 2'b00; 21 | 22 | // Test case for I-type 23 | #10 instruction = 25'b1000000000000000000000000; ImmSrc = 2'b00; // Sign-extend a negative value 24 | #10 instruction = 25'b0000000000000000000000000; ImmSrc = 2'b00; // Sign-extend a positive value 25 | 26 | // Test case for S-type 27 | #10 instruction = 25'b1000000000000000000000000; ImmSrc = 2'b01; 28 | #10 instruction = 25'b0000000000000000000000000; ImmSrc = 2'b01; 29 | 30 | // Test case for B-type 31 | #10 instruction = 25'b1000000000000000000000000; ImmSrc = 2'b10; 32 | #10 instruction = 25'b0000000000000000000000000; ImmSrc = 2'b10; 33 | 34 | // Test case for J-type 35 | #10 instruction = 25'b1000000000000000000000000; ImmSrc = 2'b11; 36 | #10 instruction = 25'b0000000000000000000000000; ImmSrc = 2'b11; 37 | 38 | #10 $finish(); 39 | end 40 | endmodule 41 | -------------------------------------------------------------------------------- /RISC-V Main Modules Designs/Instruction Memory/Design.v: -------------------------------------------------------------------------------- 1 | //Design of Instruction Memory 2 | 3 | module Instruction_Memory( 4 | input [31:0]A, // Address input 5 | output reg [31:0]RD // Instruction output 6 | ); 7 | // Instruction memory array (ROM) 8 | reg [31:0] mem[63:0]; 9 | 10 | // Initialize the ROM with the program instructions 11 | initial begin 12 | mem[0] = 32'h00500093; // li x1, 5 (addi x1, x0, 5) 13 | mem[1] = 32'h00A00113; // li x2, 10 (addi x2, x0, 10) 14 | mem[2] = 32'h002081B3; // add x3, x1, x2 15 | mem[3] = 32'h00300023; // sw x3, 0(x0) 16 | end 17 | 18 | // Read operation 19 | always @(*) begin 20 | RD = mem[A[31:2]]; // Address decoding 21 | end 22 | endmodule 23 | 24 | 25 | -------------------------------------------------------------------------------- /RISC-V Main Modules Designs/Instruction Memory/Elaborated Design.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/EkthaReddy/RISC-V-Single-Cycle-Processor/1ce946ef061feb79c6e2539f8247bd11a78d83ac/RISC-V Main Modules Designs/Instruction Memory/Elaborated Design.png -------------------------------------------------------------------------------- /RISC-V Main Modules Designs/Instruction Memory/Implemented Design.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/EkthaReddy/RISC-V-Single-Cycle-Processor/1ce946ef061feb79c6e2539f8247bd11a78d83ac/RISC-V Main Modules Designs/Instruction Memory/Implemented Design.png -------------------------------------------------------------------------------- /RISC-V Main Modules Designs/Instruction Memory/Simulation Output.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/EkthaReddy/RISC-V-Single-Cycle-Processor/1ce946ef061feb79c6e2539f8247bd11a78d83ac/RISC-V Main Modules Designs/Instruction Memory/Simulation Output.png -------------------------------------------------------------------------------- /RISC-V Main Modules Designs/Instruction Memory/Testbench.v: -------------------------------------------------------------------------------- 1 | // Testbench for Instruction Memory 2 | 3 | module Instruction_Memory_tb; 4 | 5 | // Inputs 6 | reg [31:0] A; 7 | 8 | // Outputs 9 | wire [31:0] RD; 10 | 11 | // Instantiate the module under test 12 | Instruction_Memory dut ( 13 | .A(A), 14 | .RD(RD) 15 | ); 16 | 17 | // Testbench stimulus 18 | initial begin 19 | // Address initialization and read operations 20 | 21 | // Read instruction from address 0 22 | A = 32'h00000000; 23 | #10; // Wait for some time 24 | 25 | // Read instruction from address 1 26 | A = 32'h00000004; 27 | #10; // Wait for some time 28 | 29 | // Read instruction from address 2 30 | A = 32'h00000008; 31 | #10; // Wait for some time 32 | 33 | // Read instruction from address 3 34 | A = 32'h0000000C; 35 | #10; // Wait for some time 36 | 37 | // Add more test cases as needed 38 | 39 | // End simulation 40 | $finish; 41 | end 42 | 43 | endmodule 44 | -------------------------------------------------------------------------------- /RISC-V Main Modules Designs/Main Decoder/Design.v: -------------------------------------------------------------------------------- 1 | module MainDecoder( 2 | input [6:0] op, 3 | output reg RegWrite, 4 | output reg MemWrite, 5 | output reg Branch, 6 | output reg ALUSrc, 7 | output reg [1:0] ALUop, 8 | output reg [1:0] ImmSrc 9 | ); 10 | always @(*) begin 11 | case(op) 12 | 7'b0000011: begin // Load Word Instruction 13 | RegWrite <= 1; 14 | MemWrite <= 0; 15 | Branch <= 0; 16 | ALUSrc <= 1; 17 | ALUop <= 2'b00; 18 | ImmSrc <= 2'b00; 19 | end 20 | 7'b0100011: begin // Store Word Instruction 21 | RegWrite <= 0; 22 | MemWrite <= 1; 23 | Branch <= 0; 24 | ALUSrc <= 1; 25 | ALUop <= 2'b00; 26 | ImmSrc <= 2'b01; 27 | end 28 | 7'b1100011: begin // Branch Instruction 29 | RegWrite <= 0; 30 | MemWrite <= 0; 31 | Branch <= 1; 32 | ALUSrc <= 0; 33 | ALUop <= 2'b01; 34 | ImmSrc <= 2'b10; 35 | end 36 | 7'b0010011: begin // I-type Instruction 37 | RegWrite <= 1; 38 | MemWrite <= 0; 39 | Branch <= 0; 40 | ALUSrc <= 1; 41 | ALUop <= 2'b10; 42 | ImmSrc <= 2'b00; 43 | end 44 | default: begin 45 | RegWrite <= 0; 46 | MemWrite <= 0; 47 | Branch <= 0; 48 | ALUSrc <= 0; 49 | ALUop <= 2'b00; 50 | ImmSrc <= 2'b00; 51 | end 52 | endcase 53 | end 54 | endmodule 55 | -------------------------------------------------------------------------------- /RISC-V Main Modules Designs/Main Decoder/Elaborated Design.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/EkthaReddy/RISC-V-Single-Cycle-Processor/1ce946ef061feb79c6e2539f8247bd11a78d83ac/RISC-V Main Modules Designs/Main Decoder/Elaborated Design.png -------------------------------------------------------------------------------- /RISC-V Main Modules Designs/Main Decoder/Implemented Design.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/EkthaReddy/RISC-V-Single-Cycle-Processor/1ce946ef061feb79c6e2539f8247bd11a78d83ac/RISC-V Main Modules Designs/Main Decoder/Implemented Design.png -------------------------------------------------------------------------------- /RISC-V Main Modules Designs/Main Decoder/Simulation Output.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/EkthaReddy/RISC-V-Single-Cycle-Processor/1ce946ef061feb79c6e2539f8247bd11a78d83ac/RISC-V Main Modules Designs/Main Decoder/Simulation Output.png -------------------------------------------------------------------------------- /RISC-V Main Modules Designs/Main Decoder/Testbench.v: -------------------------------------------------------------------------------- 1 | module MainDecoder_tb; 2 | 3 | reg [6:0] op; 4 | wire RegWrite; 5 | wire MemWrite; 6 | wire Branch; 7 | wire ALUSrc; 8 | wire [1:0] ALUop; 9 | wire [1:0] ImmSrc; 10 | 11 | MainDecoder uut (op, RegWrite, MemWrite, Branch, ALUSrc, ALUop, ImmSrc); 12 | 13 | initial begin 14 | $dumpfile("dump.vcd"); 15 | $dumpvars(0); 16 | 17 | op<=1'b0; 18 | #10 $finish(); 19 | end 20 | 21 | always #2 op<=~op; 22 | endmodule 23 | -------------------------------------------------------------------------------- /RISC-V Main Modules Designs/Multiplexer for ALUSrc/Design.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module MUX_for_ALUSrc( 4 | input RD2, ImmExt, ALUSrc, 5 | output SrcB 6 | ); 7 | assign SrcB = ALUSrc?ImmExt:RD2; // ALUSrc is the select line which will select the output for SrcB. One indicates for ImmExt and zero indicates for RD2. 8 | endmodule 9 | -------------------------------------------------------------------------------- /RISC-V Main Modules Designs/Multiplexer for ALUSrc/Elaborated Design.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/EkthaReddy/RISC-V-Single-Cycle-Processor/1ce946ef061feb79c6e2539f8247bd11a78d83ac/RISC-V Main Modules Designs/Multiplexer for ALUSrc/Elaborated Design.png -------------------------------------------------------------------------------- /RISC-V Main Modules Designs/Multiplexer for ALUSrc/Implemented Design.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/EkthaReddy/RISC-V-Single-Cycle-Processor/1ce946ef061feb79c6e2539f8247bd11a78d83ac/RISC-V Main Modules Designs/Multiplexer for ALUSrc/Implemented Design.png -------------------------------------------------------------------------------- /RISC-V Main Modules Designs/Multiplexer for ALUSrc/Simulation Output.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/EkthaReddy/RISC-V-Single-Cycle-Processor/1ce946ef061feb79c6e2539f8247bd11a78d83ac/RISC-V Main Modules Designs/Multiplexer for ALUSrc/Simulation Output.png -------------------------------------------------------------------------------- /RISC-V Main Modules Designs/Multiplexer for ALUSrc/Testbench.v: -------------------------------------------------------------------------------- 1 | // Testbench 2 | 3 | module MUX_for_ALUSrc_tb; 4 | 5 | reg RD2, ImmExt, ALUSrc; 6 | wire SrcB; 7 | 8 | MUX_for_ALUSrc dut(RD2, ImmExt, ALUSrc, SrcB); 9 | 10 | initial begin 11 | $dumpfile("dump.file"); 12 | $dumpvars; 13 | 14 | RD2<=1'b0; 15 | ImmExt<=1'b0; 16 | ALUSrc<=1'b0; 17 | 18 | #10 $finish(); 19 | end 20 | 21 | always #2 RD2<=~RD2; 22 | always #1.2 ImmExt<=~ImmExt; 23 | always #3 ALUSrc<=~ALUSrc; 24 | 25 | endmodule 26 | -------------------------------------------------------------------------------- /RISC-V Main Modules Designs/Multiplexer for PCSrc/Design.v: -------------------------------------------------------------------------------- 1 | // Design Of Multiplexer for PCSrc Select Line 2 | `timescale 1ns / 1ps 3 | 4 | module MUX_for_PCSrc( 5 | input PCPlus4, PCTarget, PCSrc, 6 | output PCNext 7 | ); 8 | 9 | assign PCNext = PCSrc?PCTarget:PCPlus4; 10 | endmodule 11 | -------------------------------------------------------------------------------- /RISC-V Main Modules Designs/Multiplexer for PCSrc/Elaborated Design.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/EkthaReddy/RISC-V-Single-Cycle-Processor/1ce946ef061feb79c6e2539f8247bd11a78d83ac/RISC-V Main Modules Designs/Multiplexer for PCSrc/Elaborated Design.png -------------------------------------------------------------------------------- /RISC-V Main Modules Designs/Multiplexer for PCSrc/Implemented Design.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/EkthaReddy/RISC-V-Single-Cycle-Processor/1ce946ef061feb79c6e2539f8247bd11a78d83ac/RISC-V Main Modules Designs/Multiplexer for PCSrc/Implemented Design.png -------------------------------------------------------------------------------- /RISC-V Main Modules Designs/Multiplexer for PCSrc/Simulation Output.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/EkthaReddy/RISC-V-Single-Cycle-Processor/1ce946ef061feb79c6e2539f8247bd11a78d83ac/RISC-V Main Modules Designs/Multiplexer for PCSrc/Simulation Output.png -------------------------------------------------------------------------------- /RISC-V Main Modules Designs/Multiplexer for PCSrc/Testbench.v: -------------------------------------------------------------------------------- 1 | // Testbench 2 | 3 | `timescale 1ns / 1ps 4 | 5 | module MUX_for_PCSrc_tb; 6 | 7 | reg PCPlus4, PCTarget, PCSrc; 8 | wire PCNext; 9 | 10 | MUX_for_PCSrc dut(PCPlus4, PCTarget, PCSrc, PCNext); 11 | 12 | initial begin 13 | $dumpfile("dump.file"); 14 | $dumpvars; 15 | 16 | PCPlus4<=1'b0; 17 | PCTarget<=1'b0; 18 | PCSrc<=1'b0; 19 | 20 | #10 $finish(); 21 | end 22 | 23 | always #2 PCPlus4<=~PCPlus4; 24 | always #1.2 PCTarget<=~PCTarget; 25 | always #3 PCSrc<=~PCSrc; 26 | 27 | endmodule 28 | -------------------------------------------------------------------------------- /RISC-V Main Modules Designs/Multiplexer for ResultSrc/Design.v: -------------------------------------------------------------------------------- 1 | // Design of Multiplexer for ResultSrc 2 | 3 | module MUX_for_ResultSrc( 4 | input [31:0] ALUResult, 5 | input [31:0] RD, 6 | input [31:0] PCPlus4, 7 | input [1:0] ResultSrc, 8 | output reg [31:0] Result 9 | ); 10 | always @(*) begin 11 | case (ResultSrc) 12 | 2'b00: Result = ALUResult; // Select ALUResult 13 | 2'b01: Result = RD; // Select RD 14 | 2'b10: Result = PCPlus4; // Select PCPlus4 15 | default: Result = 32'b0; // Default case (can be defined as needed) 16 | endcase 17 | end 18 | endmodule 19 | -------------------------------------------------------------------------------- /RISC-V Main Modules Designs/Multiplexer for ResultSrc/Elaborated Design.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/EkthaReddy/RISC-V-Single-Cycle-Processor/1ce946ef061feb79c6e2539f8247bd11a78d83ac/RISC-V Main Modules Designs/Multiplexer for ResultSrc/Elaborated Design.png -------------------------------------------------------------------------------- /RISC-V Main Modules Designs/Multiplexer for ResultSrc/Implemented Design.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/EkthaReddy/RISC-V-Single-Cycle-Processor/1ce946ef061feb79c6e2539f8247bd11a78d83ac/RISC-V Main Modules Designs/Multiplexer for ResultSrc/Implemented Design.png -------------------------------------------------------------------------------- /RISC-V Main Modules Designs/Multiplexer for ResultSrc/Simulation Output.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/EkthaReddy/RISC-V-Single-Cycle-Processor/1ce946ef061feb79c6e2539f8247bd11a78d83ac/RISC-V Main Modules Designs/Multiplexer for ResultSrc/Simulation Output.png -------------------------------------------------------------------------------- /RISC-V Main Modules Designs/Multiplexer for ResultSrc/Testbench.v: -------------------------------------------------------------------------------- 1 | // Testbench 2 | 3 | module MUX_for_ResultSrc_tb; 4 | 5 | reg [31:0]ALUResult; 6 | reg [31:0]RD; 7 | reg [31:0] PCPlus4; 8 | reg [1:0] ResultSrc; 9 | wire [31:0]Result; 10 | 11 | MUX_for_ResultSrc dut(ALUResult, RD, PCPlus4, ResultSrc, Result); 12 | 13 | initial begin 14 | $dumpfile("dump.vcd"); 15 | $dumpvars(0); 16 | 17 | ALUResult=1'b0; 18 | RD=1'b0; 19 | PCPlus4=1'b0; 20 | ResultSrc=1'b0; 21 | 22 | #10 $finish(); 23 | end 24 | 25 | always #2 ALUResult<=~ALUResult; 26 | always #1.2 RD<=~RD; 27 | always #3 PCPlus4<=~PCPlus4; 28 | always #2.5 ResultSrc<=~ResultSrc; 29 | 30 | endmodule 31 | -------------------------------------------------------------------------------- /RISC-V Main Modules Designs/Program Counter/Close up of Implemented Design.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/EkthaReddy/RISC-V-Single-Cycle-Processor/1ce946ef061feb79c6e2539f8247bd11a78d83ac/RISC-V Main Modules Designs/Program Counter/Close up of Implemented Design.png -------------------------------------------------------------------------------- /RISC-V Main Modules Designs/Program Counter/Design.v: -------------------------------------------------------------------------------- 1 | // The Program Counter (PC) Design 2 | 3 | module program_counter( 4 | input clk, reset, 5 | input [31:0] pc_in, // Input Port 6 | output reg [31:0] pc_out // Output Port 7 | ); 8 | 9 | always@(posedge clk) 10 | if (reset) 11 | pc_out<=pc_in; // In initial Stage, output of PC will be the initial address i,e, 1000 12 | else 13 | pc_out<=pc_in + 4; // In the next cycle, output will be incremented to four of previous stage. Example: 1000 + 4= 1004, in next cycle it is 1008 14 | endmodule 15 | -------------------------------------------------------------------------------- /RISC-V Main Modules Designs/Program Counter/Elaborated Design.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/EkthaReddy/RISC-V-Single-Cycle-Processor/1ce946ef061feb79c6e2539f8247bd11a78d83ac/RISC-V Main Modules Designs/Program Counter/Elaborated Design.png -------------------------------------------------------------------------------- /RISC-V Main Modules Designs/Program Counter/Implemented Design.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/EkthaReddy/RISC-V-Single-Cycle-Processor/1ce946ef061feb79c6e2539f8247bd11a78d83ac/RISC-V Main Modules Designs/Program Counter/Implemented Design.png -------------------------------------------------------------------------------- /RISC-V Main Modules Designs/Program Counter/Simulation Output.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/EkthaReddy/RISC-V-Single-Cycle-Processor/1ce946ef061feb79c6e2539f8247bd11a78d83ac/RISC-V Main Modules Designs/Program Counter/Simulation Output.png -------------------------------------------------------------------------------- /RISC-V Main Modules Designs/Program Counter/Testbench.v: -------------------------------------------------------------------------------- 1 | // Testbench of Program Counter (PC) 2 | 3 | module program_counter_tb; 4 | 5 | // Inputs 6 | reg clk; 7 | reg reset; 8 | reg [31:0] pc_in; 9 | 10 | // Outputs 11 | wire [31:0] pc_out; 12 | 13 | // Instantiate the module under test 14 | program_counter dut ( 15 | .clk(clk), 16 | .reset(reset), 17 | .pc_in(pc_in), 18 | .pc_out(pc_out) 19 | ); 20 | 21 | // Clock generation 22 | always begin 23 | clk = 0; 24 | #5; // Adjust the delay as needed based on your clock period 25 | clk = 1; 26 | #5; // Adjust the delay as needed based on your clock period 27 | end 28 | 29 | // Testbench stimulus 30 | initial begin 31 | // Initialize inputs 32 | reset = 1; 33 | pc_in = 32'h00000000; // Initial PC value 34 | 35 | // Wait a few clock cycles 36 | #20; 37 | 38 | // Release reset 39 | reset = 0; 40 | 41 | // Wait a few clock cycles to observe PC update 42 | #20; 43 | 44 | // Example: Change pc_in to test PC update 45 | pc_in = 32'h00000004; 46 | #20; 47 | 48 | // Add more test cases as needed 49 | 50 | // End simulation 51 | $finish; 52 | end 53 | 54 | endmodule 55 | -------------------------------------------------------------------------------- /RISC-V Main Modules Designs/Register File/Design.v: -------------------------------------------------------------------------------- 1 | // Design of Register File 2 | 3 | module RegFile( 4 | input WE3, clk, 5 | input [4:0] A1, 6 | input [4:0] A2, 7 | input [4:0] A3, 8 | input [31:0] WD3, 9 | output reg [31:0] RD1, 10 | output reg [31:0] RD2 11 | ); 12 | 13 | reg [31:0] register_file[31:0]; 14 | 15 | always@(posedge clk) 16 | if (WE3) 17 | register_file[A3] <= WD3; 18 | 19 | always@(*) begin 20 | RD1 = (A1==1)? register_file[A1]:0; 21 | RD2 = (A2==1)? register_file[A2]:0; 22 | end 23 | 24 | endmodule 25 | -------------------------------------------------------------------------------- /RISC-V Main Modules Designs/Register File/Elaborated Design.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/EkthaReddy/RISC-V-Single-Cycle-Processor/1ce946ef061feb79c6e2539f8247bd11a78d83ac/RISC-V Main Modules Designs/Register File/Elaborated Design.png -------------------------------------------------------------------------------- /RISC-V Main Modules Designs/Register File/Implemented Design.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/EkthaReddy/RISC-V-Single-Cycle-Processor/1ce946ef061feb79c6e2539f8247bd11a78d83ac/RISC-V Main Modules Designs/Register File/Implemented Design.png -------------------------------------------------------------------------------- /RISC-V Main Modules Designs/Register File/Simulation Output.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/EkthaReddy/RISC-V-Single-Cycle-Processor/1ce946ef061feb79c6e2539f8247bd11a78d83ac/RISC-V Main Modules Designs/Register File/Simulation Output.png -------------------------------------------------------------------------------- /RISC-V Main Modules Designs/Register File/Testbench.v: -------------------------------------------------------------------------------- 1 | // Testbench of Register File 2 | 3 | `timescale 1ns / 1ps 4 | 5 | module RegFile_tb; 6 | reg WE3; 7 | reg clk; 8 | reg [4:0] A1; 9 | reg [4:0] A2; 10 | reg [4:0] A3; 11 | reg [31:0] WD3; 12 | wire [31:0] RD1; 13 | wire [31:0] RD2; 14 | 15 | RegFile uut (.WE3(WE3), .clk(clk), .A1(A1), .A2(A2), .A3(A3), .WD3(WD3), .RD1(RD1), .RD2(RD2)); 16 | 17 | initial begin 18 | $dumpfile("dump.vcd"); 19 | $dumpvars; 20 | clk = 1'b0; 21 | WE3 = 1'b0; 22 | A1 = 1'b0; 23 | A2 = 1'b0; 24 | A3 = 1'b0; 25 | WD3 = 1'b0; 26 | 27 | #10; 28 | $finish(); 29 | end 30 | 31 | always #1 clk<=~clk; 32 | always #1.2 WE3<=~WE3; 33 | always #2.2 A1<=~A1; 34 | always #2.6 A2<=~A2; 35 | always #2.6 A3<=~A3; 36 | always #3.2 WD3<=~WD3; 37 | 38 | 39 | endmodule 40 | --------------------------------------------------------------------------------