├── .gitignore ├── 65xx.jar ├── ALU.v ├── Makefile ├── NMAKE.EXE ├── README.license ├── README.md ├── REGFILE_INIT.COE ├── bin2coe.exe ├── bin2hex.exe ├── boot.asm ├── cpu.v └── supporting-macros.a65 /.gitignore: -------------------------------------------------------------------------------- 1 | # emacs-style backup files 2 | *~ 3 | # patch detritus 4 | *.orig 5 | *.rej 6 | # non-redistributable files 7 | i2cslave.v 8 | asm65Org16.py 9 | # xilinx FPGA derived files 10 | *.xml 11 | *.wdb 12 | *.bgn 13 | *.bit 14 | *.bld 15 | *.cfi 16 | *.drc 17 | *.map 18 | *.mcs 19 | *.mrp 20 | *.ncd 21 | *.ngc 22 | *.ngd 23 | *.ngm 24 | *.pad 25 | *.par 26 | *.pcf 27 | *.prm 28 | *.ptwx 29 | *.twr 30 | *.twx 31 | *.unroutes 32 | *.xpi 33 | *_annot.nlf 34 | *_annot.sdf 35 | *_annot.v 36 | *_annot_mhf_info.txt 37 | *_bitgen.xwbt 38 | *_ngdbuild.xrpt 39 | *_pad.csv 40 | *_pad.txt 41 | *_xst.xrpt 42 | *.xrpt 43 | make.log 44 | fuse.log 45 | isim.log 46 | x.exe 47 | usage_statistics_webtalk.html 48 | webtalk.log 49 | netlist.lst 50 | glbl.v 51 | -------------------------------------------------------------------------------- /65xx.jar: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ElEctric-EyE/verilog-6502/13e0c0459ec1d43ffe3fc01c3d50f0d2c489e908/65xx.jar -------------------------------------------------------------------------------- /ALU.v: -------------------------------------------------------------------------------- 1 | /* 2 | * parameterisable ALU for 6502 and 65Org16 3 | * 4 | * verilog-6502 project: verilog model of 6502 and 65Org16 CPU core 5 | * 6 | * (C) 2011 Arlet Ottens, 7 | * (C) 2011 Ed Spittles, 8 | * (C) 2011,2012,2013 Sam Gaskill, 9 | * Added BigEd's barrel shifter logic on port EI 10 | * 11 | * 12 | * This library is free software; you can redistribute it and/or 13 | * modify it under the terms of the GNU Lesser General Public 14 | * License version 2.1 as published by the Free Software Foundation. 15 | * 16 | * AI and BI are 8 bit inputs. Result in OUT. 17 | * CI is Carry In. 18 | * CO is Carry Out. 19 | * 20 | * op[3:0] is defined as follows: 21 | * 22 | * 0011 AI + BI 23 | * 0111 AI - BI 24 | * 1011 AI + AI 25 | * 1100 AI | BI 26 | * 1101 AI & BI 27 | * 1110 AI ^ BI 28 | * 1111 AI 29 | */ 30 | 31 | module ALU( input clk, 32 | input right, 33 | input rotate, 34 | input [3:0] op, // operation 35 | input [dw-1:0] AI, 36 | input [dw-1:0] BI, 37 | input [3:0] EI, // variable shift in 38 | input CI, 39 | output reg [dw-1:0] OUT, 40 | output reg CO, 41 | output V, 42 | output Z, 43 | output reg N, 44 | input RDY 45 | ); 46 | 47 | parameter dw = 16; // data width (8 for 6502, 16 for 65Org16) 48 | 49 | reg AI7; 50 | reg BI7; 51 | reg [dw:0] logical; 52 | reg [dw-1:0] temp_BI; 53 | reg [dw:0] temp; 54 | 55 | wire adder_CI = (right | (op[3:2] == 2'b11)) ? 0 : CI; 56 | 57 | // calculate the logic operations. The 'case' can be done in 1 LUT per 58 | // bit. The 'right' shift is a simple mux that can be implemented by 59 | // F5MUX. 60 | 61 | always @* begin 62 | case( op[1:0] ) 63 | 2'b00 : logical = AI | BI; 64 | 2'b01 : logical = AI & BI; 65 | 2'b10 : logical = AI ^ BI; 66 | 2'b11 : logical = AI; 67 | endcase 68 | 69 | if( right ) 70 | logical = { AI[0], CI, AI[dw-1:1] }; 71 | end 72 | 73 | // perform a long-distance shift 74 | 75 | wire [dw:0]tempshifted = right ? ({CI, AI, CI, AI} << (~EI)) >> (dw-1) 76 | : ({CI, AI, CI, AI} << EI ) >> (dw+1); 77 | 78 | // need to mask off incoming bits in the case of a shift rather than a rotate 79 | 80 | wire [dw-1:0]highmask = ~((1 << EI ) - 1); 81 | wire [dw-1:0]lowmask = ((2 << (~EI)) - 1); 82 | 83 | // rotate is easy, and left is just a masking. Sign extension is a bit more work. 84 | 85 | wire [dw:0]tempmasked = rotate ? tempshifted 86 | : right ? (tempshifted & lowmask) | ({dw{BI[dw-1]}} & ~lowmask) 87 | : tempshifted & highmask; 88 | 89 | // bypass the 6502-style ALU if we're doing OP_ROL or OP_A 90 | 91 | wire shiftrotate = (op[3] == 1'b1) & (op[1:0] == 2'b11); 92 | 93 | // Add logic result to BI input. This only makes sense when logic = AI. 94 | // This stage can be done in 1 LUT per bit, using carry chain logic. 95 | 96 | always @* begin 97 | case( op[3:2] ) 98 | 2'b00 : temp_BI = BI; // A+B 99 | 2'b01 : temp_BI = ~BI; // A-B 100 | 2'b10 : temp_BI = logical; // A+A 101 | 2'b11 : temp_BI = 0; // A+0 102 | endcase 103 | end 104 | 105 | // perform the addition as 2 separate nibble, so we get 106 | // access to the half carry flag 107 | 108 | //always @(logical or temp_BI or adder_CI) 109 | always @* 110 | temp = logical + temp_BI + adder_CI; 111 | 112 | //end 113 | 114 | // calculate the flags 115 | 116 | always @(posedge clk) 117 | if( RDY ) begin 118 | AI7 <= AI[7]; 119 | BI7 <= temp_BI[7]; 120 | OUT <= (shiftrotate ? tempmasked[dw-1:0] : temp[dw-1:0]); 121 | CO <= (shiftrotate ? tempshifted[dw] : temp[dw]); 122 | N <= temp[dw-1]; 123 | end 124 | 125 | assign V = AI7 ^ BI7 ^ CO ^ N; 126 | assign Z = ~|OUT; 127 | 128 | endmodule 129 | -------------------------------------------------------------------------------- /Makefile: -------------------------------------------------------------------------------- 1 | #=============================================================================== 2 | # Portable 6502/65C02/65816 Assembler Definitions 3 | #------------------------------------------------------------------------------- 4 | 5 | # Update the followiung line to reflect where you have installed the ZIP file 6 | # containing the JAVA classes. 7 | 8 | 65016_DIR = C:\Users\AV/\Desktop\65016PVBRAM5 9 | 10 | #=============================================================================== 11 | 12 | 65016_JAR = $(65016_DIR)/65xx.jar 13 | 14 | AS65_CLASS = org.x6502.x65016.As65016 15 | 16 | LK65_CLASS = org.x6502.x65016.Lk65016 17 | 18 | LB65_CLASS = org.x6502.x65016.Lb65016 19 | 20 | AS65 = java -cp $(65016_JAR) $(AS65_CLASS) 21 | 22 | LK65 = java -cp $(65016_JAR) $(LK65_CLASS) 23 | 24 | LB65 = java -cp $(65016_JAR) $(LB65_CLASS) 25 | 26 | RM = erase 27 | 28 | #=============================================================================== 29 | # Rules 30 | #------------------------------------------------------------------------------- 31 | 32 | .asm.obj: 33 | $(AS65) $(AS65_FLAGS) $< 34 | 35 | #=============================================================================== 36 | # Configuration 37 | #------------------------------------------------------------------------------- 38 | 39 | OBJS = \ 40 | boot.obj 41 | 42 | LK65_FLAGS = \ 43 | -bss $$00010000-$$EFFFFFFF -code $$FFFFF000-$$FFFFFFFF 44 | 45 | #=============================================================================== 46 | # Targets 47 | #------------------------------------------------------------------------------- 48 | 49 | all: boot.hex boot.bin boot.coe 50 | 51 | 52 | boot.hex: $(OBJS) 53 | $(LK65) $(LK65_FLAGS) -hex -output $@ $(OBJS) 54 | 55 | boot.bin: $(OBJS) 56 | $(LK65) $(LK65_FLAGS) -bin -output $@ $(OBJS) 57 | 58 | #=============================================================================== 59 | # Utilities 60 | #------------------------------------------------------------------------------- 61 | 62 | clean: 63 | $(RM) $(OBJS) 64 | $(RM) *.bin 65 | $(RM) *.s19 66 | $(RM) *.lst 67 | $(RM) *.map 68 | $(RM) *.hex 69 | $(RM) *.coe 70 | 71 | #=============================================================================== 72 | # Dependencies 73 | #------------------------------------------------------------------------------- 74 | 75 | boot.obj: \ 76 | boot.asm 77 | 78 | boot.coe: boot.bin 79 | bin2hex -2 boot -------------------------------------------------------------------------------- /NMAKE.EXE: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ElEctric-EyE/verilog-6502/13e0c0459ec1d43ffe3fc01c3d50f0d2c489e908/NMAKE.EXE -------------------------------------------------------------------------------- /README.license: -------------------------------------------------------------------------------- 1 | GNU LESSER GENERAL PUBLIC LICENSE 2 | Version 2.1, February 1999 3 | 4 | Copyright (C) 1991, 1999 Free Software Foundation, Inc. 5 | 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA 6 | Everyone is permitted to copy and distribute verbatim copies 7 | of this license document, but changing it is not allowed. 8 | 9 | [This is the first released version of the Lesser GPL. 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You can do so by permitting 465 | redistribution under these terms (or, alternatively, under the terms of the 466 | ordinary General Public License). 467 | 468 | To apply these terms, attach the following notices to the library. It is 469 | safest to attach them to the start of each source file to most effectively 470 | convey the exclusion of warranty; and each file should have at least the 471 | "copyright" line and a pointer to where the full notice is found. 472 | 473 | 474 | Copyright (C) 475 | 476 | This library is free software; you can redistribute it and/or 477 | modify it under the terms of the GNU Lesser General Public 478 | License as published by the Free Software Foundation; either 479 | version 2.1 of the License, or (at your option) any later version. 480 | 481 | This library is distributed in the hope that it will be useful, 482 | but WITHOUT ANY WARRANTY; without even the implied warranty of 483 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 484 | Lesser General Public License for more details. 485 | 486 | You should have received a copy of the GNU Lesser General Public 487 | License along with this library; if not, write to the Free Software 488 | Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA 489 | 490 | Also add information on how to contact you by electronic and paper mail. 491 | 492 | You should also get your employer (if you work as a programmer) or your 493 | school, if any, to sign a "copyright disclaimer" for the library, if 494 | necessary. Here is a sample; alter the names: 495 | 496 | Yoyodyne, Inc., hereby disclaims all copyright interest in the 497 | library `Frob' (a library for tweaking knobs) written by James Random Hacker. 498 | 499 | , 1 April 1990 500 | Ty Coon, President of Vice 501 | 502 | That's all there is to it! 503 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | A Verilog HDL project for CPU cores related to the old MOS 6502 CPU. 2 | 3 | This fork adds various features, see [this thread on the 6502.org forum](http://forum.6502.org/viewtopic.php?f=10&t=1842) 4 | 5 | The 65Org16-master branch is for a CPU core with: 6 | - 32-bit address space 7 | - by using 16-bit bytes 8 | - with no specific support for 8-bit bytes 9 | - with BCD mode as unspecified behaviour 10 | - and otherwise all opcodes and addressing modes like NMOS 6502 11 | 12 | Please use other branches and add a suffix to your core name for 13 | CPU cores with other goals. 14 | 15 | Please note: 16 | 17 | - The core has had extensive testing on a video project by ElEctric_EyE on multiple threads in the Programmable Logic Section of http://forum.6502.org 18 | 19 | - Some tools exist: see [this forum thread](http://forum.6502.org/viewtopic.php?f=1&t=1982) 20 | 21 | - The upstream fork by BigEd also contains support files for a small system on 22 | FPGA, intended for xilinx spartan 3 as found on OHO GOP 24-pin module. 23 | The system has a uart module for communication to a host computer, 24 | which is implemented over i2c. The i2c module is not included for 25 | copyright reasons. The system is absolutely minimal but is a work 26 | in progress, 27 | 28 | - LGPL license v2.1 is used for compatibility with opencores.org and to 29 | encourage redistribution of any source code improvements. 30 | (The license can be changed by agreement of all the copyright holders) 31 | 32 | Notes on the cpu core: 33 | 34 | - clk is active on the positive edge (is a phi1 clock) 35 | - reset, IRQ and NMI are active high 36 | - WE replaces, and is inverse sense of, read not write. 37 | - databus has separate DI and DO 38 | - RDY is implemented 39 | - external memory is assumed synchronous, so external pipelining is needed 40 | - `define SIM for extra simulation instrumentation 41 | - memory accesses may diverge from the original 42 | 43 | Website for the original: http://ladybug.xs4all.nl/arlet/fpga/6502/ 44 | 45 | Note on licensing: 46 | 47 | Relicensed to LGPL by kind permission of Arlet Ottens 48 | "If you want to distribute it under the LGPL license that's fine with me" 49 | 16 May 2011 12:08 50 | -------------------------------------------------------------------------------- /REGFILE_INIT.COE: -------------------------------------------------------------------------------- 1 | 0000 2 | 0000 3 | 0000 4 | 0000 5 | 0000 6 | 0000 7 | 0000 8 | 0000 9 | 0000 10 | 0000 11 | 0000 12 | 0000 13 | 0000 14 | 0000 15 | 0000 16 | 0000 17 | 0000 18 | 0000 19 | 0000 20 | FFFF 21 | 0000 22 | 0001 23 | 0000 24 | 0000 25 | 0000 26 | 0000 27 | 0000 28 | 0000 29 | 0000 30 | 0000 31 | 0000 32 | 0000 33 | -------------------------------------------------------------------------------- /bin2coe.exe: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ElEctric-EyE/verilog-6502/13e0c0459ec1d43ffe3fc01c3d50f0d2c489e908/bin2coe.exe -------------------------------------------------------------------------------- /bin2hex.exe: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ElEctric-EyE/verilog-6502/13e0c0459ec1d43ffe3fc01c3d50f0d2c489e908/bin2hex.exe -------------------------------------------------------------------------------- /cpu.v: -------------------------------------------------------------------------------- 1 | /*FILE: /relocatable stack and zero page/cpu.v DATE:02/12/2013 -- remember to uncomment 4 'ifdef/endif SIM' statements when not running simulation. -- 2 | * verilog-6502 project: verilog model of 6502 and 65OrgXX.x CPU cores 3 | * 4 | * (C) 2011 Arlet Ottens, 5 | * (C) 2011 Ed Spittles, 6 | * (C) 2012,2013 Sam Gaskill, 7 | * Removed BCD mode & SED,CLD opcodes 8 | * Added full 16-bit IR decoding 9 | * Added Arlet's updates 10 | * Added B thru Q accumulators http://forum.6502.org/viewtopic.php?f=10&t=1824&start=54 11 | * Added full accumulator to accumulator transfer opcodes 12 | * Added BigEd's 16-bit barrel shifter logic to A thru D Acc's 13 | * Added compatible WDC65C02 PHX,PHY,PLX,PLY opcodes 14 | * Added compatible WDC65C02 INC[A], DEC[A] opcodes, also INC[B..Q], DEC[B..Q] 15 | * Added W index register with same addressing modes as Y register 16 | * Added relocatable stack and zero page registers 17 | * Added transfer opcodes for stack and zero pages registers 18 | * Added transfer opcodes for index register W 19 | * That's it for .b CORE! 20 | * Added QAWXYS Register I/O Bus thanks to Michael A. Morris 21 | * Added ZPPout, SPPout signals for zeropage and stackpage address decoding 22 | * Optimized states ABSX and INDY per Arlet's suggestion: http://forum.6502.org/viewtopic.php?f=10&t=2500&start=26 23 | * 24 | * This library is free software; you can redistribute it and/or 25 | * modify it under the terms of the GNU Lesser General Public 26 | * License version 2.1 as published by the Free Software Foundation. 27 | * 28 | * This library is distributed in the hope that it will be useful, 29 | * but WITHOUT ANY WARRANTY; without even the implied warranty of 30 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 31 | * Lesser General Public License for more details. 32 | * 33 | * 34 | * You should have received a copy of the GNU Lesser General Public 35 | * License along with this library; if not, write to the Free Software 36 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA 37 | * 38 | * 39 | * Note that not all 6502 interface signals are supported (yet). The goal 40 | * is to create an Acorn Atom model, and the Atom didn't use all signals on 41 | * the main board. 42 | * 43 | * The data bus is implemented as separate read/write buses. Combine them 44 | * on the output pads if external memory is required. 45 | */ 46 | 47 | module CPU( input clk, // CPU clock 48 | input rst, // reset signal 49 | output reg [aw-1:0] addr, // address bus 50 | input [dw-1:0] din, // data in, read bus 51 | output reg [dw-1:0] dout, // data out, write bus 52 | output reg we, // write enable 53 | output [dw-1:0] ZPPout, //Zeropage pointer 54 | output [dw-1:0] SPPout, //Stackpage pointer 55 | input IRQ, // interrupt request 56 | input NMI, // non-maskable interrupt request 57 | input RDY // Ready signal. Pauses CPU when RDY=0 ); 58 | ); 59 | 60 | parameter dw = 16; // data width (8 for 6502, 16 for 65Org16) 61 | parameter aw = 32; // address width (16 for 6502, 32 for 65Org16) 62 | 63 | /* 64 | * internal signals 65 | */ 66 | 67 | reg [aw-1:0] PC; // Program Counter 68 | reg [dw-1:0] ABL; // Address Bus Register LSB 69 | reg [dw-1:0] ABH; // Address Bus Register MSB 70 | wire [dw-1:0] ADD; // Adder Hold Register (registered in ALU) 71 | 72 | reg [dw-1:0] DIHOLD; // Hold for Data In 73 | reg DIHOLD_valid; // 74 | wire [dw-1:0] DIMUX; // 75 | 76 | reg [dw-1:0] IRHOLD; // Hold for Instruction register 77 | reg IRHOLD_valid; // Valid instruction in IRHOLD 78 | 79 | reg C = 0; // carry flag (init at zero to avoid X's in ALU sim) 80 | reg Z = 0; // zero flag 81 | reg I = 0; // interrupt flag 82 | reg V = 0; // overflow flag 83 | reg N = 0; // negative flag 84 | wire AZ; // ALU Zero flag 85 | wire AV; // ALU overflow flag 86 | wire AN; // ALU negative flag 87 | 88 | reg [dw-1:0] AI; // ALU Input A 89 | reg [dw-1:0] BI; // ALU Input B 90 | reg [3:0] E_Reg; // Shift Distance Register 91 | wire [dw-1:0] IR; // Instruction register 92 | reg CI; // Carry In 93 | wire CO; // Carry Out 94 | wire [dw-1:0] PCH = PC[aw-1:dw]; 95 | wire [dw-1:0] PCL = PC[dw-1:0]; 96 | 97 | reg NMI_edge = 0; // captured NMI edge 98 | 99 | // Define register file components: address, RAM, data input/output busses 100 | 101 | reg [dw-1:0] QAWXYS[31:0]; // A thru Q, W, X, Y, Z, S, SPP, ZPP register file 102 | reg [4:0] regsel; // A thru Q, W, X, Y, Z, S, SPP, ZPP register select 103 | wire [dw-1:0] reg_di, reg_do; // Register file input/output data busses 104 | 105 | assign ZPPout = QAWXYS[20]; 106 | assign SPPout = QAWXYS[21]; 107 | 108 | parameter 109 | SEL_A = 5'd0, 110 | SEL_B = 5'd1, 111 | SEL_C = 5'd2, 112 | SEL_D = 5'd3, 113 | SEL_E = 5'd4, 114 | SEL_F = 5'd5, 115 | SEL_G = 5'd6, 116 | SEL_H = 5'd7, 117 | SEL_I = 5'd8, 118 | SEL_J = 5'd9, 119 | SEL_K = 5'd10, 120 | SEL_L = 5'd11, 121 | SEL_M = 5'd12, 122 | SEL_N = 5'd13, 123 | SEL_O = 5'd14, 124 | SEL_Q = 5'd15, //P = processor status 125 | SEL_X = 5'd16, 126 | SEL_Y = 5'd17, 127 | SEL_W = 5'd18, 128 | SEL_S = 5'd19, 129 | SEL_ZPP = 5'd20, 130 | SEL_SPP = 5'd21; 131 | 132 | /* 133 | * define some signals for watching in simulator output 134 | */ 135 | 136 | `ifdef SIM 137 | wire [dw-1:0] Qacc = QAWXYS[SEL_Q]; // Accumulator 138 | wire [dw-1:0] Oacc = QAWXYS[SEL_O]; // Accumulator 139 | wire [dw-1:0] Nacc = QAWXYS[SEL_N]; // Accumulator 140 | wire [dw-1:0] Macc = QAWXYS[SEL_M]; // Accumulator 141 | wire [dw-1:0] Lacc = QAWXYS[SEL_L]; // Accumulator 142 | wire [dw-1:0] Kacc = QAWXYS[SEL_K]; // Accumulator 143 | wire [dw-1:0] Jacc = QAWXYS[SEL_J]; // Accumulator 144 | wire [dw-1:0] Iacc = QAWXYS[SEL_I]; // Accumulator 145 | wire [dw-1:0] Hacc = QAWXYS[SEL_H]; // Accumulator 146 | wire [dw-1:0] Gacc = QAWXYS[SEL_G]; // Accumulator 147 | wire [dw-1:0] Facc = QAWXYS[SEL_F]; // Accumulator 148 | wire [dw-1:0] Eacc = QAWXYS[SEL_E]; // Accumulator 149 | wire [dw-1:0] Dacc = QAWXYS[SEL_D]; // Accumulator 150 | wire [dw-1:0] Cacc = QAWXYS[SEL_C]; // Accumulator 151 | wire [dw-1:0] Bacc = QAWXYS[SEL_B]; // Accumulator 152 | wire [dw-1:0] Aacc = QAWXYS[SEL_A]; // Accumulator 153 | wire [dw-1:0] X = QAWXYS[SEL_X]; // X register 154 | wire [dw-1:0] Y = QAWXYS[SEL_Y]; // Y register 155 | wire [dw-1:0] W = QAWXYS[SEL_W]; // W register 156 | wire [dw-1:0] S = QAWXYS[SEL_S]; // Stack pointer 157 | wire [dw-1:0] ZPP = QAWXYS[SEL_ZPP]; // Zero Page Pointer 158 | wire [dw-1:0] SPP = QAWXYS[SEL_SPP]; // Stack Page Pointer 159 | `endif 160 | 161 | wire [dw-1:0] P = { 8'b0, N, V, 3'b110, I, Z, C }; 162 | 163 | /* 164 | * instruction decoder/sequencer 165 | */ 166 | 167 | reg [5:0] state; 168 | 169 | /* 170 | * control signals 171 | */ 172 | 173 | reg PC_inc; // Increment PC 174 | reg [aw-1:0] PC_temp; // intermediate value of PC 175 | 176 | reg [4:0] src_reg; // source register index 177 | reg [4:0] dst_reg; // destination register index 178 | reg [dw-1:0] zp_reg; // shadow ZPP write register 179 | reg [dw-1:0] sp_reg; // shadow SPP write register http://forum.6502.org/viewtopic.php?f=10&t=1842&start=264 180 | reg index_y; // if set, then Y is index reg 181 | reg index_w; // if set, then W is index reg, otherwise X is index reg 182 | reg load_reg; // loading a register (A thru Q, W, X, Y, S) in this instruction 183 | reg inc; // increment 184 | reg write_back; // set if memory is read/modified/written 185 | reg load_only; // LD[A..Q]/LDW/LDX/LDY instruction 186 | reg store; // doing store (ST[A..Q]/STW/STX/STY) 187 | reg adc_sbc; // doing ADC/SBC 188 | reg compare; // doing CMP/CPY/CPX/CPW 189 | reg shift; // doing shift/rotate instruction 190 | reg rotate; // doing rotate (no shift) 191 | reg backwards; // backwards branch 192 | reg cond_true; // branch condition is true 193 | reg [2:0] cond_code; // condition code bits from instruction 194 | reg shift_right; // Instruction ALU shift/rotate right 195 | reg alu_shift_right; // Current cycle shift right enable 196 | reg [3:0] op; // Main ALU operation for instruction 197 | reg [3:0] alu_op; // Current cycle ALU operation 198 | 199 | /* 200 | * some flip flops to remember we're doing special instructions. These 201 | * get loaded at the DECODE state, and used later 202 | */ 203 | 204 | reg BIT; // doing BIT instruction 205 | reg plp; // doing PLP instruction 206 | reg php; // doing PHP instruction 207 | reg clc; // clear carry 208 | reg sec; // set carry 209 | reg cli; // clear interrupt 210 | reg sei; // set interrupt 211 | reg clv; // clear overflow 212 | reg brk; // doing BRK 213 | 214 | reg res; // in reset 215 | 216 | /* 217 | * ALU operations 218 | */ 219 | 220 | parameter 221 | OP_OR = 4'b1100, 222 | OP_AND = 4'b1101, 223 | OP_EOR = 4'b1110, 224 | OP_ADD = 4'b0011, 225 | OP_SUB = 4'b0111, 226 | OP_ROL = 4'b1011, 227 | OP_A = 4'b1111; 228 | 229 | /* 230 | * Microcode state machine. Basically, every addressing mode has its own 231 | * path through the state machine. Additional information, such as the 232 | * operation, source and destination registers are decoded in parallel, and 233 | * kept in separate flops. 234 | */ 235 | 236 | parameter 237 | ABS0 = 6'd0, // ABS - fetch LSB 238 | ABS1 = 6'd1, // ABS - fetch MSB 239 | ABSX0 = 6'd2, // ABS, X - fetch LSB and send to ALU (+X) 240 | ABSX1 = 6'd3, // ABS, X - fetch MSB and send to ALU (+Carry) 241 | BRA0 = 6'd4, // Branch - fetch offset and send to ALU (+PC[dw-1:0]) 242 | BRA1 = 6'd5, // Branch - fetch opcode, and send PC[aw-1:dw] to ALU 243 | BRA2 = 6'd6, // Branch - fetch opcode (if page boundary crossed) 244 | BRK0 = 6'd7, // BRK/IRQ - push PCH, send S to ALU (-1) 245 | BRK1 = 6'd8, // BRK/IRQ - push PCL, send S to ALU (-1) 246 | BRK2 = 6'd9, // BRK/IRQ - push P, send S to ALU (-1) 247 | BRK3 = 6'd10, // BRK/IRQ - write S, and fetch @ fffe 248 | DECODE = 6'd11, // IR is valid, decode instruction, and write prev reg 249 | FETCH = 6'd12, // fetch next opcode, and perform prev ALU op 250 | INDX0 = 6'd13, // (ZP,X) - fetch ZP address, and send to ALU (+X) 251 | INDX1 = 6'd14, // (ZP,X) - fetch LSB at ZP+X, calculate ZP+X+1 252 | INDX2 = 6'd15, // (ZP,X) - fetch MSB at ZP+X+1 253 | INDX3 = 6'd16, // (ZP,X) - fetch data 254 | INDY0 = 6'd17, // (ZP),Y - fetch ZP address, and send ZP to ALU (+1) 255 | INDY1 = 6'd18, // (ZP),Y - fetch at ZP+1, and send LSB to ALU (+Y) 256 | INDY2 = 6'd19, // (ZP),Y - fetch data, and send MSB to ALU (+Carry) 257 | JMP0 = 6'd20, // JMP - fetch PCL and hold 258 | JMP1 = 6'd21, // JMP - fetch PCH 259 | JMPI0 = 6'd22, // JMP IND - fetch LSB and send to ALU for delay (+0) 260 | JMPI1 = 6'd23, // JMP IND - fetch MSB, proceed with JMP0 state 261 | JSR0 = 6'd24, // JSR - push PCH, save LSB, send S to ALU (-1) 262 | JSR1 = 6'd25, // JSR - push PCL, send S to ALU (-1) 263 | JSR2 = 6'd26, // JSR - write S 264 | JSR3 = 6'd27, // JSR - fetch MSB 265 | PULL0 = 6'd28, // PLP/PLA - save next op in IRHOLD, send S to ALU (+1) 266 | PULL1 = 6'd29, // PLP/PLA - fetch data from stack, write S 267 | PULL2 = 6'd30, // PLP/PLA - prefetch op, but don't increment PC 268 | PUSH0 = 6'd31, // PHP/PHA - send A to ALU (+0) 269 | PUSH1 = 6'd32, // PHP/PHA - write A/P, send S to ALU (-1) 270 | READ = 6'd33, // Read memory for read/modify/write (INC, DEC, shift) 271 | REG = 6'd34, // Read register for reg-reg transfers 272 | RTI0 = 6'd35, // RTI - send S to ALU (+1) 273 | RTI1 = 6'd36, // RTI - read P from stack 274 | RTI2 = 6'd37, // RTI - read PCL from stack 275 | RTI3 = 6'd38, // RTI - read PCH from stack 276 | RTI4 = 6'd39, // RTI - read PCH from stack 277 | RTS0 = 6'd40, // RTS - send S to ALU (+1) 278 | RTS1 = 6'd41, // RTS - read PCL from stack 279 | RTS2 = 6'd42, // RTS - write PCL to ALU, read PCH 280 | RTS3 = 6'd43, // RTS - load PC and increment 281 | WRITE = 6'd44, // Write memory for read/modify/write 282 | ZP0 = 6'd45, // Z-page - fetch ZP address 283 | ZPX0 = 6'd46, // ZP, X - fetch ZP, and send to ALU (+X) 284 | ZPX1 = 6'd47; // ZP, X - load from memory 285 | 286 | `ifdef SIM 287 | 288 | /* 289 | * easy to read names in simulator output 290 | */ 291 | 292 | reg [8*6-1:0] statename; 293 | 294 | always @* 295 | case( state ) 296 | DECODE: statename = "DECODE"; 297 | REG: statename = "REG"; 298 | ZP0: statename = "ZP0"; 299 | ZPX0: statename = "ZPX0"; 300 | ZPX1: statename = "ZPX1"; 301 | ABS0: statename = "ABS0"; 302 | ABS1: statename = "ABS1"; 303 | ABSX0: statename = "ABSX0"; 304 | ABSX1: statename = "ABSX1"; 305 | INDX0: statename = "INDX0"; 306 | INDX1: statename = "INDX1"; 307 | INDX2: statename = "INDX2"; 308 | INDX3: statename = "INDX3"; 309 | INDY0: statename = "INDY0"; 310 | INDY1: statename = "INDY1"; 311 | INDY2: statename = "INDY2"; 312 | READ: statename = "READ"; 313 | WRITE: statename = "WRITE"; 314 | FETCH: statename = "FETCH"; 315 | PUSH0: statename = "PUSH0"; 316 | PUSH1: statename = "PUSH1"; 317 | PULL0: statename = "PULL0"; 318 | PULL1: statename = "PULL1"; 319 | PULL2: statename = "PULL2"; 320 | JSR0: statename = "JSR0"; 321 | JSR1: statename = "JSR1"; 322 | JSR2: statename = "JSR2"; 323 | JSR3: statename = "JSR3"; 324 | RTI0: statename = "RTI0"; 325 | RTI1: statename = "RTI1"; 326 | RTI2: statename = "RTI2"; 327 | RTI3: statename = "RTI3"; 328 | RTI4: statename = "RTI4"; 329 | RTS0: statename = "RTS0"; 330 | RTS1: statename = "RTS1"; 331 | RTS2: statename = "RTS2"; 332 | RTS3: statename = "RTS3"; 333 | BRK0: statename = "BRK0"; 334 | BRK1: statename = "BRK1"; 335 | BRK2: statename = "BRK2"; 336 | BRK3: statename = "BRK3"; 337 | BRA0: statename = "BRA0"; 338 | BRA1: statename = "BRA1"; 339 | BRA2: statename = "BRA2"; 340 | JMP0: statename = "JMP0"; 341 | JMP1: statename = "JMP1"; 342 | JMPI0: statename = "JMPI0"; 343 | JMPI1: statename = "JMPI1"; 344 | endcase 345 | 346 | `endif 347 | 348 | 349 | 350 | /* 351 | * Program Counter Increment/Load. First calculate the base value in 352 | * PC_temp. 353 | */ 354 | 355 | always @* 356 | case( state ) 357 | DECODE: if( (~I & IRQ) | NMI_edge ) 358 | PC_temp = { ABH, ABL }; 359 | else 360 | PC_temp = PC; 361 | 362 | 363 | JMP1, 364 | JMPI1, 365 | JSR3, 366 | RTS3, 367 | RTI4: PC_temp = { DIMUX, ADD }; 368 | 369 | BRA1: PC_temp = { ABH, ADD }; 370 | 371 | BRA2: PC_temp = { ADD, PCL }; 372 | 373 | BRK2: PC_temp = res ? 32'hffff_fffc : 374 | NMI_edge ? 32'hffff_fffa : 32'hffff_fffe; // width should be parameterised 375 | 376 | default: PC_temp = PC; 377 | endcase 378 | 379 | /* 380 | * Determine wether we need PC_temp, or PC_temp + 1 381 | */ 382 | 383 | always @* 384 | case( state ) 385 | DECODE: if( (~I & IRQ) | NMI_edge ) 386 | PC_inc = 0; 387 | else 388 | PC_inc = 1; 389 | 390 | ABS0, 391 | ABSX0, 392 | FETCH, 393 | BRA0, 394 | BRA2, 395 | BRK3, 396 | JMPI1, 397 | JMP1, 398 | RTI4, 399 | RTS3: PC_inc = 1; 400 | 401 | BRA1: PC_inc = CO ^~ backwards; 402 | 403 | default: PC_inc = 0; 404 | endcase 405 | 406 | /* 407 | * Set new PC 408 | */ 409 | 410 | always @(posedge clk) 411 | if( RDY ) 412 | PC <= PC_temp + PC_inc; 413 | 414 | /* 415 | * Address Generator 416 | */ 417 | 418 | always @* 419 | case( state ) 420 | ABSX1, 421 | INDY2: addr = { DIMUX + CO, ADD }; 422 | 423 | INDX3, 424 | JMP1, 425 | JMPI1, 426 | RTI4, 427 | ABS1: addr = { DIMUX, ADD }; 428 | 429 | BRA2: addr = { ADD, ABL }; 430 | 431 | BRA1: addr = { ABH, ADD }; 432 | 433 | JSR0, 434 | PUSH1, 435 | RTS0, 436 | RTI0, 437 | BRK0: addr = { sp_reg, reg_do }; 438 | 439 | BRK1, 440 | JSR1, 441 | PULL1, 442 | RTS1, 443 | RTS2, 444 | RTI1, 445 | RTI2, 446 | RTI3, 447 | BRK2: addr = { sp_reg, ADD }; 448 | 449 | INDY1, 450 | INDX1, 451 | ZPX1, 452 | INDX2: addr = { zp_reg, ADD }; 453 | 454 | ZP0, 455 | INDY0: addr = { zp_reg, DIMUX }; 456 | 457 | REG, 458 | READ, 459 | WRITE: addr = { ABH, ABL }; 460 | 461 | default: addr = PC; 462 | endcase 463 | 464 | /* 465 | * ABH/ABL pair is used for registering previous address bus state. 466 | * This can be used to keep the current address, freeing up the original 467 | * source of the address, such as the ALU or din. 468 | */ 469 | 470 | always @(posedge clk) begin 471 | if( state != PUSH0 && state != PUSH1 && RDY && state != PULL0 && state != PULL1 && state != PULL2 ) 472 | ABL <= addr[dw-1:0]; 473 | ABH <= addr[aw-1:dw]; 474 | end 475 | 476 | /* 477 | * Data Out MUX 478 | */ 479 | 480 | always @* 481 | case( state ) 482 | WRITE: dout = ADD; 483 | 484 | JSR0, 485 | BRK0: dout = PCH; 486 | 487 | JSR1, 488 | BRK1: dout = PCL; 489 | 490 | PUSH1: dout = php ? P : ADD; 491 | 492 | BRK2: dout = (IRQ | NMI_edge) ? (P & 16'b1111_1111_1110_1111) : P; // B bit should be parameterised 493 | 494 | default: dout = reg_do; 495 | endcase 496 | 497 | /* 498 | * Write Enable Generator 499 | */ 500 | 501 | always @* 502 | case( state ) 503 | BRK0, // writing to stack or memory 504 | BRK1, 505 | BRK2, 506 | JSR0, 507 | JSR1, 508 | PUSH1, 509 | WRITE: we = 1; 510 | 511 | INDX3, // only if doing a STA, STX or STY 512 | INDY2, 513 | ABSX1, 514 | ABS1, 515 | ZPX1, 516 | ZP0: we = store; 517 | 518 | default: we = 0; 519 | endcase 520 | 521 | /* 522 | * register file, contains A thru Q, W, X, Y and S (stack pointer) registers. At each 523 | * cycle only 1 of those registers needs to be accessed, so they combined 524 | * in a small memory, saving resources. 525 | */ 526 | 527 | reg write_register; // set when register file is written 528 | 529 | always @* 530 | case( state ) 531 | DECODE: write_register = load_reg & ~plp; 532 | 533 | PULL1, 534 | RTS2, 535 | RTI3, 536 | BRK3, 537 | JSR0, 538 | JSR2 : write_register = 1; 539 | 540 | default: write_register = 0; 541 | endcase 542 | 543 | /* 544 | * write to a register. Usually this is the output of the 545 | * ALU, but in case of the JSR0 we use the S register to temporarily store 546 | * the PCL. This is possible, because the S register itself is stored in 547 | * the ALU during those cycles. 548 | */ 549 | 550 | initial 551 | $readmemh("REGFILE_INIT.COE", QAWXYS, 0, 31); 552 | 553 | assign reg_di = (state == JSR0) ? DIMUX : ADD; 554 | 555 | always @(posedge clk) 556 | if( write_register & RDY ) 557 | QAWXYS[regsel] <= reg_di; 558 | 559 | assign reg_do = QAWXYS[regsel]; // Selected register output\par 560 | 561 | always @(posedge clk) 562 | if( write_register & RDY & (regsel == SEL_ZPP) ) 563 | zp_reg <= ADD; 564 | 565 | always @(posedge clk) 566 | if( write_register & RDY & (regsel == SEL_SPP) ) 567 | sp_reg <= ADD; 568 | 569 | /* 570 | * register select logic. This determines which of the A thru Q, W, X, Y or 571 | * S registers will be accessed. 572 | */ 573 | 574 | always @* 575 | case( state ) 576 | INDY1, 577 | INDX0, 578 | ZPX0, 579 | ABSX0 : regsel = index_w ? SEL_W : index_y ? SEL_Y : SEL_X; 580 | 581 | DECODE : regsel = dst_reg; 582 | 583 | BRK0, 584 | BRK3, 585 | JSR0, 586 | JSR2, 587 | PULL0, 588 | PULL1, 589 | PUSH1, 590 | RTI0, 591 | RTI3, 592 | RTS0, 593 | RTS2 : regsel = SEL_S; 594 | 595 | default: regsel = src_reg; 596 | endcase 597 | 598 | /* 599 | * ALU 600 | */ 601 | 602 | ALU #(.dw(dw)) _ALU( 603 | .clk(clk), 604 | .op(alu_op), 605 | .right(alu_shift_right), 606 | .rotate(rotate), 607 | .AI(AI), 608 | .BI(BI), 609 | .CI(CI), 610 | .EI(E_Reg), 611 | .CO(CO), 612 | .OUT(ADD), 613 | .V(AV), 614 | .Z(AZ), 615 | .N(AN), 616 | .RDY(RDY) ); 617 | 618 | /* 619 | * Select current ALU operation 620 | */ 621 | 622 | always @* 623 | case( state ) 624 | READ: alu_op = op; 625 | 626 | BRA1: alu_op = backwards ? OP_SUB : OP_ADD; 627 | 628 | FETCH, 629 | REG : alu_op = op; 630 | 631 | DECODE, 632 | ABS1: alu_op = 1'bx; 633 | 634 | PUSH1, 635 | BRK0, 636 | BRK1, 637 | BRK2, 638 | JSR0, 639 | JSR1: alu_op = OP_SUB; 640 | 641 | default: alu_op = OP_ADD; 642 | endcase 643 | 644 | /* 645 | * Determine shift right signal to ALU 646 | */ 647 | 648 | always @* 649 | if( state == FETCH || state == REG || state == READ ) 650 | alu_shift_right = shift_right; 651 | else 652 | alu_shift_right = 0; 653 | 654 | /* 655 | * Sign extend branch offset. 656 | */ 657 | 658 | always @(posedge clk) 659 | if( RDY ) 660 | backwards <= DIMUX[dw-1]; 661 | 662 | /* 663 | * ALU A Input MUX 664 | */ 665 | 666 | always @* 667 | case( state ) 668 | JSR1, 669 | RTS1, 670 | RTI1, 671 | RTI2, 672 | BRK1, 673 | BRK2, 674 | INDX1: AI = ADD; 675 | 676 | REG, 677 | ZPX0, 678 | INDX0, 679 | ABSX0, 680 | RTI0, 681 | RTS0, 682 | JSR0, 683 | JSR2, 684 | BRK0, 685 | PULL0, 686 | INDY1, 687 | PUSH0, 688 | PUSH1: AI = reg_do; 689 | 690 | BRA0, 691 | READ: AI = DIMUX; 692 | 693 | BRA1: AI = ABH; // don't use PCH in case we're 694 | 695 | FETCH: AI = load_only ? 0 : reg_do; 696 | 697 | DECODE, 698 | ABS1: AI = {dw{1'bx}}; // don't care 699 | 700 | default: AI = 0; 701 | endcase 702 | 703 | 704 | /* 705 | * ALU B Input mux 706 | */ 707 | 708 | always @* 709 | case( state ) 710 | BRA1, 711 | JSR1, 712 | RTS1, 713 | RTI0, 714 | RTI1, 715 | RTI2, 716 | INDX1, 717 | READ, 718 | REG, 719 | JSR0, 720 | JSR2, 721 | BRK0, 722 | BRK1, 723 | BRK2, 724 | PUSH0, 725 | PUSH1, 726 | PULL0, 727 | RTS0: BI = {dw{1'b0}}; 728 | 729 | BRA0: BI = PCL; 730 | 731 | DECODE, 732 | ABS1: BI = {dw{1'bx}}; // don't care 733 | 734 | default: BI = DIMUX; 735 | endcase 736 | 737 | /* 738 | * ALU CI (carry in) mux 739 | */ 740 | 741 | always @* 742 | case( state ) 743 | INDY2, 744 | BRA1, 745 | ABSX1: CI = CO; 746 | 747 | DECODE, 748 | ABS1: CI = 1'bx; 749 | 750 | READ, 751 | REG: CI = rotate ? C : 752 | shift ? 0 : inc; 753 | 754 | FETCH: CI = rotate ? C : 755 | compare ? 1 : 756 | (shift | load_only) ? 0 : C; 757 | 758 | PULL0, 759 | RTI0, 760 | RTI1, 761 | RTI2, 762 | RTS0, 763 | RTS1, 764 | INDY0, 765 | INDX1: CI = 1; 766 | 767 | default: CI = 0; 768 | endcase 769 | 770 | /* 771 | * Processor Status Register update 772 | * 773 | */ 774 | 775 | /* 776 | * Update C flag when doing ADC/SBC, shift/rotate, compare 777 | */ 778 | 779 | always @(posedge clk ) 780 | if( shift && state == WRITE ) 781 | C <= CO; 782 | else if( state == RTI2 ) 783 | C <= DIMUX[0]; 784 | else if( ~write_back && state == DECODE ) begin 785 | if( adc_sbc | shift | compare ) 786 | C <= CO; 787 | else if( plp ) 788 | C <= ADD[0]; 789 | else begin 790 | if( sec ) C <= 1; 791 | if( clc ) C <= 0; 792 | end 793 | end 794 | 795 | /* 796 | * Update Z, N flags when writing A thru Q, W, X, Y, Memory, or when doing compare 797 | */ 798 | 799 | always @(posedge clk) 800 | if( state == WRITE ) 801 | Z <= AZ; 802 | else if( state == RTI2 ) 803 | Z <= DIMUX[1]; 804 | else if( state == DECODE ) begin 805 | if( plp ) 806 | Z <= ADD[1]; 807 | else if( (load_reg & (regsel != SEL_S)) | compare | BIT ) 808 | Z <= AZ; 809 | end 810 | 811 | always @(posedge clk) 812 | if( state == WRITE ) 813 | N <= AN; 814 | else if( state == RTI2 ) 815 | N <= DIMUX[dw-1]; 816 | else if( state == DECODE ) begin 817 | if( plp ) 818 | N <= ADD[dw-1]; 819 | else if( (load_reg & (regsel != SEL_S)) | compare ) 820 | N <= AN; 821 | end else if( state == FETCH && BIT ) 822 | N <= DIMUX[dw-1]; 823 | 824 | /* 825 | * Update I flag 826 | */ 827 | 828 | always @(posedge clk) 829 | if( state == BRK3 ) 830 | I <= 1; 831 | else if( state == RTI2 ) 832 | I <= DIMUX[2]; 833 | else if( state == REG ) begin 834 | if( sei ) I <= 1; 835 | if( cli ) I <= 0; 836 | end 837 | else if( state == DECODE ) 838 | if( plp ) I <= ADD[2]; 839 | 840 | /* 841 | * Update V flag (next to top bit) 842 | */ 843 | 844 | always @(posedge clk ) 845 | if( state == RTI2 ) 846 | V <= DIMUX[dw-2]; 847 | else if( state == DECODE ) begin 848 | if( adc_sbc ) V <= AV; 849 | if( clv ) V <= 0; 850 | if( plp ) V <= ADD[dw-2]; 851 | end else if( state == FETCH && BIT ) 852 | V <= DIMUX[dw-2]; 853 | 854 | /* 855 | * Instruction decoder 856 | */ 857 | 858 | /* 859 | * IR register/mux. Hold previous din value in IRHOLD in PULL0 and PUSH0 860 | * states. In these states, the IR has been prefetched, and there is no 861 | * time to read the IR again before the next decode. 862 | */ 863 | 864 | reg RDY1 = 1; 865 | 866 | always @(posedge clk ) 867 | RDY1 <= RDY; 868 | 869 | always @(posedge clk ) 870 | if( ~RDY && RDY1 ) 871 | DIHOLD <= din; 872 | 873 | always @(posedge clk ) 874 | if( rst ) 875 | IRHOLD_valid <= 0; 876 | else if( RDY ) begin 877 | if( state == PULL0 || state == PUSH0 ) begin 878 | IRHOLD <= DIMUX; 879 | IRHOLD_valid <= 1; 880 | end else if( state == DECODE ) 881 | IRHOLD_valid <= 0; 882 | end 883 | 884 | assign IR = (IRQ & ~I) | NMI_edge ? {dw{1'b0}} : 885 | IRHOLD_valid ? IRHOLD : DIMUX; 886 | 887 | assign DIMUX = ~RDY1 ? DIHOLD : din; 888 | 889 | /* 890 | * Microcode state machine 891 | */ 892 | 893 | always @(posedge clk or posedge rst) 894 | if( rst ) 895 | state <= BRK0; 896 | else if( RDY ) 897 | case( state ) 898 | DECODE : 899 | casex ( IR[15:0] ) // decode all 16 bits: 900 | // 901 | // IR[15:12] used for reg [3:0] E_Reg (Shift Distance Register) on all opcodes only. 902 | // IR[15:8] 0000_0000 is NMOS 6502 compatible opcode. 903 | // IR[15:14,11:10] src_reg. 904 | // IR[13:12,9:8] dst_reg. 905 | // 906 | 16'b0000_0000_0000_0000: state <= BRK0; 907 | 16'b0000_0000_0010_0000: state <= JSR0; 908 | 16'bxxxx_xxxx_0010_1100: state <= ABS0; // BIT abs 909 | 16'b0000_0000_0100_0000: state <= RTI0; // 910 | 16'b0000_0000_0100_1100: state <= JMP0; 911 | 16'b0000_0000_0110_0000: state <= RTS0; 912 | 16'b0000_0000_0110_1100: state <= JMPI0; 913 | 914 | 16'bxx00_xx00_0x00_1000: state <= PUSH0; // PH[A..Q], PHP 915 | 16'b0000_0000_x101_1010: state <= PUSH0; // PHX, PHY 916 | 16'b0000_0000_0100_1011: state <= PUSH0; // PHW 917 | 918 | 16'b00xx_00xx_0x10_1000: state <= PULL0; // PL[A..Q], PLP 919 | 16'b0000_0000_x111_1010: state <= PULL0; // PLY, PLX 920 | 16'b0000_0000_0110_1011: state <= PULL0; // PLW 921 | 922 | 16'b0000_0000_0xx1_1000: state <= REG; // CLC, SEC, CLI, SEI 923 | 924 | 16'b0000_0000_1xx0_00x0: state <= FETCH; // IMM, row 8,A,C,E, column 0,2 925 | 926 | 16'bxxxx_xxxx_1xx0_11xx: state <= ABS0; // rows 8,A,C,E, column C,D,E,F 927 | 928 | 16'bxxxx_xxxx_1xxx_1000: state <= REG; // DEY, TY[A..Q], T[A..Q]Y, INY, INX, INW, DEW 929 | 930 | 16'bxxxx_xxxx_xxx0_0001: state <= INDX0; // even rows, column 1 --(zp,x) 931 | 932 | 16'bxxxx_xxxx_1xx0_01xx: state <= ZP0; // rows 8,A,C,E, column 4,5,6,7 933 | 16'bxxxx_xxxx_0xx0_010x: state <= ZP0; // rows 0,2,4,6, columns 4,5 934 | 16'bxxxx_0000_0xx0_0110: state <= ZP0; // rows 0,2,4,6, column 6 935 | 936 | 16'bxxxx_xxxx_xxx0_1001: state <= FETCH; // IMM, even rows, column 9 937 | 938 | 16'bxxxx_xxxx_0xx0_1101: state <= ABS0; // rows 0,2,4,6, column D 939 | 16'bxxxx_0000_0xx0_1110: state <= ABS0; // rows 0,2,4,6, column E 940 | 941 | 16'b0000_0000_xxx1_0000: state <= BRA0; // odd rows, column 0 942 | 943 | 16'bxxxx_xxxx_xxx1_0001: state <= INDY0; // odd rows, column 1 --(zp),y 944 | 16'bxxxx_xxxx_xxx1_0010: state <= INDY0; // odd rows, column 2 --(zp),w 945 | 946 | 16'b0000_0000_0111_0100: state <= ZPX0; // STW zpx 947 | 16'bxxxx_xxxx_0xx1_0101: state <= ZPX0; // odd rows, column 5 948 | 16'bxxxx_0000_0xx1_0110: state <= ZPX0; // odd rows, column 6 949 | 16'b00xx_00xx_1xx1_01xx: state <= ZPX0; // rows 9,B,D,F, columns 4,5,6,7 950 | 951 | 16'bxxxx_xxxx_xxx1_10x1: state <= ABSX0; // odd rows, column 9,B 952 | 16'bxxxx_xxxx_0xx1_1101: state <= ABSX0; // rows 1,3,5,7, column D 953 | 16'bxxxx_0000_0xx1_1110: state <= ABSX0; // rows 1,3,5,7, columnn E 954 | 16'bxxxx_xxxx_1xx1_11xx: state <= ABSX0; // rows 9,B,D,F, column C,D,E,F 955 | 956 | 16'bxxxx_xxxx_00xx_0111: state <= REG; // T[A..Q]Z, T[A..Q]S, TZ[A..Q], TS[A..Q] 957 | 16'bxxxx_xxxx_x0xx_1010: state <= REG; // [A..Q], TX[A..Q] 958 | 16'bxxxx_xxxx_x1x0_1010: state <= REG; // [A..Q], TX[A..Q] 959 | 16'bxxxx_xxxx_1xx0_1011: state <= REG; // T[A..Q][A..Q],TYX,TXY 960 | 16'bxxxx_xxxx_0xxx_1111: state <= REG; // TW[A..Q], T[A..Q]W, TWX, TWY, TXW, TYW 961 | endcase 962 | 963 | ZP0 : state <= write_back ? READ : FETCH; 964 | 965 | ZPX0 : state <= ZPX1; 966 | ZPX1 : state <= write_back ? READ : FETCH; 967 | 968 | ABS0 : state <= ABS1; 969 | ABS1 : state <= write_back ? READ : FETCH; 970 | 971 | ABSX0 : state <= ABSX1; 972 | ABSX1 : state <= write_back ? READ : FETCH; 973 | 974 | INDX0 : state <= INDX1; 975 | INDX1 : state <= INDX2; 976 | INDX2 : state <= INDX3; 977 | INDX3 : state <= FETCH; 978 | 979 | INDY0 : state <= INDY1; 980 | INDY1 : state <= INDY2; 981 | INDY2 : state <= FETCH; 982 | 983 | READ : state <= WRITE; 984 | WRITE : state <= FETCH; 985 | FETCH : state <= DECODE; 986 | 987 | REG : state <= DECODE; 988 | 989 | PUSH0 : state <= PUSH1; 990 | PUSH1 : state <= DECODE; 991 | 992 | PULL0 : state <= PULL1; 993 | PULL1 : state <= PULL2; 994 | PULL2 : state <= DECODE; 995 | 996 | JSR0 : state <= JSR1; 997 | JSR1 : state <= JSR2; 998 | JSR2 : state <= JSR3; 999 | JSR3 : state <= FETCH; 1000 | 1001 | RTI0 : state <= RTI1; 1002 | RTI1 : state <= RTI2; 1003 | RTI2 : state <= RTI3; 1004 | RTI3 : state <= RTI4; 1005 | RTI4 : state <= DECODE; 1006 | 1007 | RTS0 : state <= RTS1; 1008 | RTS1 : state <= RTS2; 1009 | RTS2 : state <= RTS3; 1010 | RTS3 : state <= FETCH; 1011 | 1012 | BRA0 : state <= cond_true ? BRA1 : DECODE; 1013 | BRA1 : state <= (CO ^ backwards) ? BRA2 : DECODE; 1014 | BRA2 : state <= DECODE; 1015 | 1016 | JMP0 : state <= JMP1; 1017 | JMP1 : state <= DECODE; 1018 | 1019 | JMPI0 : state <= JMPI1; 1020 | JMPI1 : state <= JMP0; 1021 | 1022 | BRK0 : state <= BRK1; 1023 | BRK1 : state <= BRK2; 1024 | BRK2 : state <= BRK3; 1025 | BRK3 : state <= JMP0; 1026 | endcase 1027 | 1028 | /* 1029 | * Additional control signals 1030 | */ 1031 | 1032 | always @(posedge clk) 1033 | if( rst ) 1034 | res <= 1; 1035 | else if( state == DECODE ) 1036 | res <= 0; 1037 | 1038 | always @(posedge clk) 1039 | if( state == DECODE && RDY ) 1040 | casex( IR[15:0] ) 1041 | 16'bxxxx_0000_0xxx_x110, // ASL, ROL, LSR, ROR (abs, absx, zpg, zpgx) 1042 | 16'bxxxx_xxxx_0xx0_1010 : // ASL[A..D]op[A..D], ROL[A..D]op[A..D], LSR[A..D]op[A..D], ROR[A..D]op[A..D] (acc) 1043 | E_Reg <= IR[15:12]+1; //note: no shift will occur when 'illegal' opcodes IR[15:12] = 1111. A +1 ensures compatibility with original NMOS6502 opcodes. 1044 | 1045 | default : E_Reg <= ADD; 1046 | endcase 1047 | 1048 | always @(posedge clk) 1049 | if( state == DECODE && RDY ) 1050 | casex( IR[15:0] ) 1051 | 16'b0000_0000_1010_0000, // LDY 1052 | 16'bxxxx_xxxx_0xxx_0001, 1053 | 16'bxxxx_xxxx_1x1x_0001, 1054 | 16'bxxxx_xxxx_0xx1_0010, 1055 | 16'bxxxx_xxxx_101x_0010, 1056 | 16'b0000_0000_1100_0010, // LDW i 1057 | 16'bxxxx_xxxx_1111_0010, // SBC[A..Q]op[A..Q] (zp)w 1058 | 16'b0000_0000_101x_0100, 1059 | 16'b0000_0000_1111_0100, 1060 | 16'bxxxx_xxxx_0xxx_0101, 1061 | 16'bxxxx_xxxx_1x1x_0101, 1062 | 16'b0000_0000_101x_0110, 1063 | 16'bxxxx_xxxx_00xx_0111, 1064 | 16'b0000_0000_101x_0111, 1065 | 1066 | 16'bxxxx_xxxx_xxx0_1000, 1067 | 16'b00xx_00xx_1001_1000, // TY[A..Q] 1068 | 16'b0000_0000_11x1_1000, 1069 | 16'bxxxx_xxxx_0xxx_1001, 1070 | 16'bxxxx_xxxx_1x1x_1001, 1071 | 16'bxxxx_xxxx_xxxx_1010, 1072 | 16'bxxxx_xxxx_0xxx_1011, 1073 | 16'bxxxx_xxxx_1000_1011, // T[A..Q][A..Q] 1074 | 16'bxxxx_xxxx_1x1x_1011, 1075 | 16'b0000_0000_1100_1011, // TXY 1076 | 16'b0000_0000_101x_1100, // LDY a, ax 1077 | 16'b0000_0000_1101_1100, // LDW ax 1078 | 16'bxxxx_xxxx_0xxx_1101, 1079 | 16'bxxxx_xxxx_1x1x_1101, 1080 | 16'b0000_0000_101x_1110, 1081 | 16'bxxxx_xxxx_0xxx_1111, 1082 | 16'b0000_0000_101x_1111: 1083 | load_reg <= 1; 1084 | 1085 | default: load_reg <= 0; 1086 | endcase 1087 | 1088 | always @(posedge clk) 1089 | if( state == DECODE && RDY ) 1090 | casex( IR[15:0] ) 1091 | 16'bxx00_xx00_0001_0111: // T[A..Q]Z 1092 | dst_reg <= SEL_ZPP; 1093 | 1094 | 16'bxx00_xx00_0011_0111: // T[A..Q]S 1095 | dst_reg <= SEL_SPP; 1096 | 1097 | 16'b0000_0000_1110_1000, // INX 1098 | 16'b0000_0000_1100_1010, // DEX 1099 | 16'bxx00_xx00_1010_xx10, // LDX, T[A..Q]X 1100 | 16'b0000_0000_1011_x11x, // LDX zpy/zpw, LDX ay,aw 1101 | 16'b0000_0000_1111_1010, // PLX 1102 | 16'b0000_0000_1010_1011, // TYX 1103 | 16'b0000_0000_1011_1010, 1104 | 16'b0000_0000_0010_1111: // TWX 1105 | dst_reg <= SEL_X; 1106 | 1107 | 16'bxx00_xx00_0100_1000, // PH[A..Q] 1108 | 16'b0000_0000_0000_1000, // PHP 1109 | 16'b0000_0000_x101_1010, // PHX, PHY 1110 | 16'b0000_0000_0100_1011, // PHW 1111 | 16'b0000_0000_1001_1010: // TXS 1112 | dst_reg <= SEL_S; 1113 | 1114 | 16'b0000_0000_1x00_1000, // DEY, INY 1115 | 16'b0000_0000_101x_x100, // LDY a,ax, zp,zpx 1116 | 16'bxx00_xx00_1010_x000, // LDY #imm, T[A..Q]Y 1117 | 16'b0000_0000_0111_1010, // PLY 1118 | 16'b0000_0000_1100_1011, // TXY 1119 | 16'b0000_0000_0100_1111: // TWY 1120 | dst_reg <= SEL_Y; 1121 | 1122 | 16'b0000_0000_11x1_1000, // INW, DEW 1123 | 16'b0000_0000_1100_0010, // LDW # 1124 | 16'b0000_0000_1111_0100, // LDW zpx 1125 | 16'b0000_0000_1101_1100, // LDW ax 1126 | 16'b0000_0000_1010_x111, // LDW a,zp 1127 | 16'b0000_0000_0110_1011, // PLW 1128 | 16'bxx00_xx00_0xx1_1111: // T[A..Q]W, TXW, TYW 1129 | dst_reg <= SEL_W; 1130 | 1131 | 16'b0000_0000_00x0_0111, // TZ[A], TS[A] 1132 | 16'bxx00_xx00_1000_1011, // T[A..Q][A] 1133 | 16'b0000_0000_00x1_1010, // INC[A], DEC[A] 1134 | 16'b0000_0000_0110_1000, // PL[A] 1135 | 16'b0000_0000_1000_1010, // TX[A] 1136 | 16'b0000_0000_1001_1000, // TY[A] 1137 | 16'b0000_0000_0000_1111, // TW[A] 1138 | 16'b0000_0000_101x_xx01, // LD[A]i, (zpx), (zp)y, zp, zpx, zpy, ay, a, ax 1139 | 16'b0000_0000_1011_1011, // LD[A]w 1140 | 16'b0000_0000_1011_0010, // LD[A](zp)w 1141 | 16'bxx00_xx00_0xxx_xx01, // ADC[A..Q]op[A], SBC[A..Q]op[A], AND[A..Q]op[A], ORA[A..Q]op[A], EOR[A..Q]op[A] 1142 | 16'bxx00_xx00_111x_xx01, // SBC[A..Q]op[A] 1143 | 16'bxx00_xx00_0xx1_0010, // ORA[A..Q]op[A] (zp)w, AND[A..Q]op[A] (zp)w, ADC[A..Q]op[A] (zp)w 1144 | 16'bxx00_xx00_0xx1_1011, // ORA[A..Q]op[A] aw, AND[A..Q]op[A] aw, ADC[A..Q]op[A] aw 1145 | 16'bxx00_xx00_1111_0010, // SBC[A..Q]op[A] (zp)y 1146 | 16'bxx00_xx00_1111_1011, // SBC[A..Q]op[A] aw 1147 | 16'bxxxx_xx00_0xx0_1010, // ASL[A..D]op[A], ROL[A..D]op[A], LSR[A..D]op[A], ROR[A..D]op[A] (acc) 1148 | 16'b0000_0000_0010_x100: // BIT[A] zp, a 1149 | dst_reg <= SEL_A; 1150 | 1151 | 16'b0000_0001_00x0_0111, // TZ[B], TS[B] 1152 | 16'bxx00_xx01_1000_1011, // T[A..Q][B] 1153 | 16'b0000_0101_00x1_1010, // INC[B], DEC[B] 1154 | 16'b0000_0001_0110_1000, // PL[B] 1155 | 16'b0000_0001_1000_1010, // TX[B] 1156 | 16'b0000_0001_1001_1000, // TY[B] 1157 | 16'b0000_0001_0000_1111, // TW[B] 1158 | 16'b0000_0001_101x_xx01, // LD[B]i, (zpx), (zp)y, zp, zpx, zpy, ay, a, ax 1159 | 16'b0000_0001_1011_1011, // LD[B]w 1160 | 16'b0000_0001_1011_0010, // LD[B](zp)w 1161 | 16'bxx00_xx01_0xxx_xx01, // ADC[A..Q]op[B], SBC[A..Q]op[B], AND[A..Q]op[B], ORA[A..Q]op[B], EOR[A..Q]op[B] 1162 | 16'bxx00_xx01_111x_xx01, // SBC[A..Q]op[B] 1163 | 16'bxx00_xx01_0xx1_0010, // ORA[A..Q]op[B] (zp)w, AND[A..Q]op[B] (zp)w, ADC[A..Q]op[B] (zp)w 1164 | 16'bxx00_xx01_0xx1_1011, // ORA[A..Q]op[B] aw, AND[A..Q]op[B] aw, ADC[A..Q]op[B] aw 1165 | 16'bxx00_xx01_1111_0010, // SBC[A..Q]op[B] (zp)y 1166 | 16'bxx00_xx01_1111_1011, // SBC[A..Q]op[B] aw 1167 | 16'bxxxx_xx01_0xx0_1010, // ASL[A..D]op[B], ROL[A..D]op[B], LSR[A..D]op[B], ROR[A..D]op[B] (acc) 1168 | 16'b0000_0101_0010_x100: // BIT[B] zp, a 1169 | dst_reg <= SEL_B; 1170 | 1171 | 16'b0000_0010_00x0_0111, // TZ[C], TS[C] 1172 | 16'bxx00_xx10_1000_1011, // T[A..Q][C] 1173 | 16'b0000_1010_00x1_1010, // INC[C], DEC[C] 1174 | 16'b0000_0010_0110_1000, // PL[C] 1175 | 16'b0000_0010_1000_1010, // TX[C] 1176 | 16'b0000_0010_1001_1000, // TY[C] 1177 | 16'b0000_0010_0000_1111, // TW[C] 1178 | 16'b0000_0010_101x_xx01, // LD[C]i, (zpx), (zp)y, zp, zpx, zpy, ay, a, ax 1179 | 16'b0000_0010_1011_1011, // LD[C]w 1180 | 16'b0000_0010_1011_0010, // LD[C](zp)w 1181 | 16'bxx00_xx10_0xxx_xx01, // ADC[A..Q]op[C], SBC[A..Q]op[C], AND[A..Q]op[C], ORA[A..Q]op[C], EOR[A..Q]op[C] 1182 | 16'bxx00_xx10_111x_xx01, // SBC[A..Q]op[C] 1183 | 16'bxx00_xx10_0xx1_0010, // ORA[A..Q]op[C] (zp)w, AND[A..Q]op[C] (zp)w, ADC[A..Q]op[C] (zp)w 1184 | 16'bxx00_xx10_0xx1_1011, // ORA[A..Q]op[C] aw, AND[A..Q]op[C] aw, ADC[A..Q]op[C] aw 1185 | 16'bxx00_xx10_1111_0010, // SBC[A..Q]op[C] (zp)y 1186 | 16'bxx00_xx10_1111_1011, // SBC[A..Q]op[C] aw 1187 | 16'bxxxx_xx10_0xx0_1010, // ASL[A..D]op[C], ROL[A..D]op[C], LSR[A..D]op[C], ROR[A..D]op[C] (acc) 1188 | 16'b0000_1010_0010_x100: // BIT[C] zp, a 1189 | dst_reg <= SEL_C; 1190 | 1191 | 16'b0000_0011_00x0_0111, // TZ[D], TS[D] 1192 | 16'bxx00_xx11_1000_1011, // T[A..Q][D] 1193 | 16'b0000_1111_00x1_1010, // INC[D], DEC[D] 1194 | 16'b0000_0011_0110_1000, // PL[D] 1195 | 16'b0000_0011_1000_1010, // TX[D] 1196 | 16'b0000_0011_1001_1000, // TY[D] 1197 | 16'b0000_0011_0000_1111, // TW[D] 1198 | 16'b0000_0011_101x_xx01, // LD[D]i, (zpx), (zp)y, zp, zpx, zpy, ay, a, ax 1199 | 16'b0000_0011_1011_1011, // LD[D]w 1200 | 16'b0000_0011_1011_0010, // LD[D](zp)w 1201 | 16'bxx00_xx11_0xxx_xx01, // ADC[A..Q]op[D], SBC[A..Q]op[D], AND[A..Q]op[D], ORA[A..Q]op[D], EOR[A..Q]op[D] 1202 | 16'bxx00_xx11_111x_xx01, // SBC[A..Q]op[D] 1203 | 16'bxx00_xx11_0xx1_0010, // ORA[A..Q]op[D] (zp)w, AND[A..Q]op[D] (zp)w, ADC[A..Q]op[D] (zp)w 1204 | 16'bxx00_xx11_0xx1_1011, // ORA[A..Q]op[D] aw, AND[A..Q]op[D] aw, ADC[A..Q]op[D] aw 1205 | 16'bxx00_xx11_1111_0010, // SBC[A..Q]op[D] (zp)y 1206 | 16'bxx00_xx11_1111_1011, // SBC[A..Q]op[D] aw 1207 | 16'bxxxx_xx11_0xx0_1010, // ASL[A..D]op[D], ROL[A..D]op[D], LSR[A..D]op[D], ROR[A..D]op[D] (acc) 1208 | 16'b0000_1111_0010_x100: // BIT[D] zp, a 1209 | dst_reg <= SEL_D; 1210 | 1211 | 16'b0001_0000_00x0_0111, // TZ[E], TS[E] 1212 | 16'bxx01_xx00_1000_1011, // T[A..Q][E] 1213 | 16'b0101_0000_00x1_1010, // INC[E], DEC[E] 1214 | 16'b0001_0000_0110_1000, // PL[E] 1215 | 16'b0001_0000_1000_1010, // TX[E] 1216 | 16'b0001_0000_1001_1000, // TY[E] 1217 | 16'b0001_0000_0000_1111, // TW[E] 1218 | 16'b0001_0000_101x_xx01, // LD[E]i, (zpx), (zp)y, zp, zpx, zpy, ay, a, ax 1219 | 16'b0001_0000_1011_1011, // LD[E]w 1220 | 16'b0001_0000_1011_0010, // LD[E](zp)w 1221 | 16'bxx01_xx00_0xxx_xx01, // ADC[A..Q]op[E], SBC[A..Q]op[E], AND[A..Q]op[E], ORA[A..Q]op[E], EOR[A..Q]op[E] 1222 | 16'bxx01_xx00_111x_xx01, // SBC[A..Q]op[E] 1223 | 16'bxx01_xx00_0xx1_0010, // ORA[A..Q]op[E] (zp)w, AND[A..Q]op[E] (zp)w, ADC[A..Q]op[E] (zp)w 1224 | 16'bxx01_xx00_0xx1_1011, // ORA[A..Q]op[E] aw, AND[A..Q]op[E] aw, ADC[A..Q]op[E] aw 1225 | 16'bxx01_xx00_1111_0010, // SBC[A..Q]op[E] (zp)y 1226 | 16'bxx01_xx00_1111_1011, // SBC[A..Q]op[E] aw 1227 | 16'b0101_0000_0010_x100: // BIT[E] zp, a 1228 | dst_reg <= SEL_E; 1229 | 1230 | 16'b0001_0001_00x0_0111, // TZ[F], TS[F] 1231 | 16'bxx01_xx01_1000_1011, // T[A..Q][F] 1232 | 16'b0101_0101_00x1_1010, // INC[F], DEC[F] 1233 | 16'b0001_0001_0110_1000, // PL[F] 1234 | 16'b0001_0001_1000_1010, // TX[F] 1235 | 16'b0001_0001_1001_1000, // TY[F] 1236 | 16'b0001_0001_0000_1111, // TW[F] 1237 | 16'b0001_0001_101x_xx01, // LD[F]i, (zpx), (zp)y, zp, zpx, zpy, ay, a, ax 1238 | 16'b0001_0001_1011_1011, // LD[F]w 1239 | 16'b0001_0001_1011_0010, // LD[F](zp)w 1240 | 16'bxx01_xx01_0xxx_xx01, // ADC[A..Q]op[F], SBC[A..Q]op[F], AND[A..Q]op[F], ORA[A..Q]op[F], EOR[A..Q]op[F] 1241 | 16'bxx01_xx01_111x_xx01, // SBC[A..Q]op[F] 1242 | 16'bxx01_xx01_0xx1_0010, // ORA[A..Q]op[F] (zp)w, AND[A..Q]op[F] (zp)w, ADC[A..Q]op[F] (zp)w 1243 | 16'bxx01_xx01_0xx1_1011, // ORA[A..Q]op[F] aw, AND[A..Q]op[F] aw, ADC[A..Q]op[F] aw 1244 | 16'bxx01_xx01_1111_0010, // SBC[A..Q]op[F] (zp)y 1245 | 16'bxx01_xx01_1111_1011, // SBC[A..Q]op[F] aw 1246 | 16'b0101_0101_0010_x100: // BIT[F] zp, a 1247 | dst_reg <= SEL_F; 1248 | 1249 | 16'b0001_0010_00x0_0111, // TZ[G], TS[G] 1250 | 16'bxx01_xx10_1000_1011, // T[A..Q][G] 1251 | 16'b0101_1010_00x1_1010, // INC[G], DEC[G] 1252 | 16'b0001_0010_0110_1000, // PL[G] 1253 | 16'b0001_0010_1000_1010, // TX[G] 1254 | 16'b0001_0010_1001_1000, // TY[G] 1255 | 16'b0001_0010_0000_1111, // TW[G] 1256 | 16'b0001_0010_101x_xx01, // LD[G]i, (zpx), (zp)y, zp, zpx, zpy, ay, a, ax 1257 | 16'b0001_0010_1011_1011, // LD[G]w 1258 | 16'b0001_0010_1011_0010, // LD[G](zp)w 1259 | 16'bxx01_xx10_0xxx_xx01, // ADC[A..Q]op[G], SBC[A..Q]op[G], AND[A..Q]op[G], ORA[A..Q]op[G], EOR[A..Q]op[G] 1260 | 16'bxx01_xx10_111x_xx01, // SBC[A..Q]op[G] 1261 | 16'bxx01_xx10_0xx1_0010, // ORA[A..Q]op[G] (zp)w, AND[A..Q]op[G] (zp)w, ADC[A..Q]op[G] (zp)w 1262 | 16'bxx01_xx10_0xx1_1011, // ORA[A..Q]op[G] aw, AND[A..Q]op[G] aw, ADC[A..Q]op[G] aw 1263 | 16'bxx01_xx10_1111_0010, // SBC[A..Q]op[G] (zp)y 1264 | 16'bxx01_xx10_1111_1011, // SBC[A..Q]op[G] aw 1265 | 16'b0101_1010_0010_x100: // BIT[G] zp, a 1266 | dst_reg <= SEL_G; 1267 | 1268 | 16'b0001_0011_00x0_0111, // TZ[H], TS[H] 1269 | 16'bxx01_xx11_1000_1011, // T[A..Q][H] 1270 | 16'b0101_1111_00x1_1010, // INC[H], DEC[H] 1271 | 16'b0001_0011_0110_1000, // PL[H] 1272 | 16'b0001_0011_1000_1010, // TX[H] 1273 | 16'b0001_0011_1001_1000, // TY[H] 1274 | 16'b0001_0011_0000_1111, // TW[H] 1275 | 16'b0001_0011_101x_xx01, // LD[H]i, (zpx), (zp)y, zp, zpx, zpy, ay, a, ax 1276 | 16'b0001_0011_1011_1011, // LD[H]w 1277 | 16'b0001_0011_1011_0010, // LD[H](zp)w 1278 | 16'bxx01_xx11_0xxx_xx01, // ADC[A..Q]op[H], SBC[A..Q]op[H], AND[A..Q]op[H], ORA[A..Q]op[H], EOR[A..Q]op[H] 1279 | 16'bxx01_xx11_111x_xx01, // SBC[A..Q]op[H] 1280 | 16'bxx01_xx11_0xx1_0010, // ORA[A..Q]op[H] (zp)w, AND[A..Q]op[H] (zp)w, ADC[A..Q]op[H] (zp)w 1281 | 16'bxx01_xx11_0xx1_1011, // ORA[A..Q]op[H] aw, AND[A..Q]op[H] aw, ADC[A..Q]op[H] aw 1282 | 16'bxx01_xx11_1111_0010, // SBC[A..Q]op[H] (zp)y 1283 | 16'bxx01_xx11_1111_1011, // SBC[A..Q]op[H] aw 1284 | 16'b0101_1111_0010_x100: // BIT[H] zp, a 1285 | dst_reg <= SEL_H; 1286 | 1287 | 16'b0010_0000_00x0_0111, // TZ[I], TS[I] 1288 | 16'bxx10_xx00_1000_1011, // T[A..Q][I] 1289 | 16'b1010_0000_00x1_1010, // INC[I], DEC[I] 1290 | 16'b0010_0000_0110_1000, // PL[I] 1291 | 16'b0010_0000_1000_1010, // TX[I] 1292 | 16'b0010_0000_1001_1000, // TY[I] 1293 | 16'b0010_0000_0000_1111, // TW[I] 1294 | 16'b0010_0000_101x_xx01, // LD[I]i, (zpx), (zp)y, zp, zpx, zpy, ay, a, ax 1295 | 16'b0010_0000_1011_1011, // LD[I]w 1296 | 16'b0010_0000_1011_0010, // LD[I](zp)w 1297 | 16'bxx10_xx00_0xxx_xx01, // ADC[A..Q]op[I], SBC[A..Q]op[I], AND[A..Q]op[I], ORA[A..Q]op[I], EOR[A..Q]op[I] 1298 | 16'bxx10_xx00_111x_xx01, // SBC[A..Q]op[I] 1299 | 16'bxx10_xx00_0xx1_0010, // ORA[A..Q]op[I] (zp)w, AND[A..Q]op[I] (zp)w, ADC[A..Q]op[I] (zp)w 1300 | 16'bxx10_xx00_0xx1_1011, // ORA[A..Q]op[I] aw, AND[A..Q]op[I] aw, ADC[A..Q]op[I] aw 1301 | 16'bxx10_xx00_1111_0010, // SBC[A..Q]op[I] (zp)y 1302 | 16'bxx10_xx00_1111_1011, // SBC[A..Q]op[I] aw 1303 | 16'b1010_0000_0010_x100: // BIT[I] zp, a 1304 | dst_reg <= SEL_I; 1305 | 1306 | 16'b0010_0001_00x0_0111, // TZ[J], TS[J] 1307 | 16'bxx10_xx01_1000_1011, // T[A..Q][J] 1308 | 16'b1010_0101_00x1_1010, // INC[J], DEC[J] 1309 | 16'b0010_0001_0110_1000, // PL[J] 1310 | 16'b0010_0001_1000_1010, // TX[J] 1311 | 16'b0010_0001_1001_1000, // TY[J] 1312 | 16'b0010_0001_0000_1111, // TW[J] 1313 | 16'b0010_0001_101x_xx01, // LD[J]i, (zpx), (zp)y, zp, zpx, zpy, ay, a, ax 1314 | 16'b0010_0001_1011_1011, // LD[J]w 1315 | 16'b0010_0001_1011_0010, // LD[J](zp)w 1316 | 16'bxx10_xx01_0xxx_xx01, // ADC[A..Q]op[J], SBC[A..Q]op[J], AND[A..Q]op[J], ORA[A..Q]op[J], EOR[A..Q]op[J] 1317 | 16'bxx10_xx01_111x_xx01, // SBC[A..Q]op[J] 1318 | 16'bxx10_xx01_0xx1_0010, // ORA[A..Q]op[J] (zp)w, AND[A..Q]op[J] (zp)w, ADC[A..Q]op[J] (zp)w 1319 | 16'bxx10_xx01_0xx1_1011, // ORA[A..Q]op[J] aw, AND[A..Q]op[J] aw, ADC[A..Q]op[J] aw 1320 | 16'bxx10_xx01_1111_0010, // SBC[A..Q]op[J] (zp)y 1321 | 16'bxx10_xx01_1111_1011, // SBC[A..Q]op[J] aw 1322 | 16'b1010_0101_0010_x100: // BIT[J] zp, a 1323 | dst_reg <= SEL_J; 1324 | 1325 | 16'b0010_0010_00x0_0111, // TZ[K], TS[K] 1326 | 16'bxx10_xx10_1000_1011, // T[A..Q][K] 1327 | 16'b1010_1010_00x1_1010, // INC[K], DEC[K] 1328 | 16'b0010_0010_0110_1000, // PL[K] 1329 | 16'b0010_0010_1000_1010, // TX[K] 1330 | 16'b0010_0010_1001_1000, // TY[K] 1331 | 16'b0010_0010_0000_1111, // TW[K] 1332 | 16'b0010_0010_101x_xx01, // LD[K]i, (zpx), (zp)y, zp, zpx, zpy, ay, a, ax 1333 | 16'b0010_0010_1011_1011, // LD[K]w 1334 | 16'b0010_0010_1011_0010, // LD[K](zp)w 1335 | 16'bxx10_xx10_0xxx_xx01, // ADC[A..Q]op[K], SBC[A..Q]op[K], AND[A..Q]op[K], ORA[A..Q]op[K], EOR[A..Q]op[K] 1336 | 16'bxx10_xx10_111x_xx01, // SBC[A..Q]op[K] 1337 | 16'bxx10_xx10_0xx1_0010, // ORA[A..Q]op[K] (zp)w, AND[A..Q]op[K] (zp)w, ADC[A..Q]op[K] (zp)w 1338 | 16'bxx10_xx10_0xx1_1011, // ORA[A..Q]op[K] aw, AND[A..Q]op[K] aw, ADC[A..Q]op[K] aw 1339 | 16'bxx10_xx10_1111_0010, // SBC[A..Q]op[K] (zp)y 1340 | 16'bxx10_xx10_1111_1011, // SBC[A..Q]op[K] aw 1341 | 16'b1010_1010_0010_x100: // BIT[K] zp, a 1342 | dst_reg <= SEL_K; 1343 | 1344 | 16'b0010_0011_00x0_0111, // TZ[L], TS[L] 1345 | 16'bxx10_xx11_1000_1011, // T[A..Q][L] 1346 | 16'b1010_1111_00x1_1010, // INC[L], DEC[L] 1347 | 16'b0010_0011_0110_1000, // PL[L] 1348 | 16'b0010_0011_1000_1010, // TX[L] 1349 | 16'b0010_0011_1001_1000, // TY[L] 1350 | 16'b0010_0011_0000_1111, // TW[L] 1351 | 16'b0010_0011_101x_xx01, // LD[L]i, (zpx), (zp)y, zp, zpx, zpy, ay, a, ax 1352 | 16'b0010_0011_1011_1011, // LD[L]w 1353 | 16'b0010_0011_1011_0010, // LD[L](zp)w 1354 | 16'bxx10_xx11_0xxx_xx01, // ADC[A..Q]op[L], SBC[A..Q]op[L], AND[A..Q]op[L], ORA[A..Q]op[L], EOR[A..Q]op[L] 1355 | 16'bxx10_xx11_111x_xx01, // SBC[A..Q]op[L] 1356 | 16'bxx10_xx11_0xx1_0010, // ORA[A..Q]op[L] (zp)w, AND[A..Q]op[L] (zp)w, ADC[A..Q]op[L] (zp)w 1357 | 16'bxx10_xx11_0xx1_1011, // ORA[A..Q]op[L] aw, AND[A..Q]op[L] aw, ADC[A..Q]op[L] aw 1358 | 16'bxx10_xx11_1111_0010, // SBC[A..Q]op[L] (zp)y 1359 | 16'bxx10_xx11_1111_1011, // SBC[A..Q]op[L] aw 1360 | 16'b1010_1111_0010_x100: // BIT[L] zp, a 1361 | dst_reg <= SEL_L; 1362 | 1363 | 16'b0011_0000_00x0_0111, // TZ[M], TS[M] 1364 | 16'bxx11_xx00_1000_1011, // T[A..Q][M] 1365 | 16'b1111_0000_00x1_1010, // INC[M], DEC[M] 1366 | 16'b0011_0000_0110_1000, // PL[M] 1367 | 16'b0011_0000_1000_1010, // TX[M] 1368 | 16'b0011_0000_1001_1000, // TY[M] 1369 | 16'b0011_0000_0000_1111, // TW[M] 1370 | 16'b0011_0000_101x_xx01, // LD[M]i, (zpx), (zp)y, zp, zpx, zpy, ay, a, ax 1371 | 16'b0011_0000_1011_1011, // LD[M]w 1372 | 16'b0011_0000_1011_0010, // LD[M](zp)w 1373 | 16'bxx11_xx00_0xxx_xx01, // ADC[A..Q]op[M], SBC[A..Q]op[M], AND[A..Q]op[M], ORA[A..Q]op[M], EOR[A..Q]op[M] 1374 | 16'bxx11_xx00_111x_xx01, // SBC[A..Q]op[M] 1375 | 16'bxx11_xx00_0xx1_0010, // ORA[A..Q]op[M] (zp)w, AND[A..Q]op[M] (zp)w, ADC[A..Q]op[M] (zp)w 1376 | 16'bxx11_xx00_0xx1_1011, // ORA[A..Q]op[M] aw, AND[A..Q]op[M] aw, ADC[A..Q]op[M] aw 1377 | 16'bxx11_xx00_1111_0010, // SBC[A..Q]op[M] (zp)y 1378 | 16'bxx11_xx00_1111_1011, // SBC[A..Q]op[M] aw 1379 | 16'b1111_0000_0010_x100: // BIT[M] zp, a 1380 | dst_reg <= SEL_M; 1381 | 1382 | 16'b0011_0001_00x0_0111, // TZ[N], TS[N] 1383 | 16'bxx11_xx01_1000_1011, // T[A..Q][N] 1384 | 16'b1111_0101_00x1_1010, // INC[N], DEC[N] 1385 | 16'b0011_0001_0110_1000, // PL[N] 1386 | 16'b0011_0001_1000_1010, // TX[N] 1387 | 16'b0011_0001_1001_1000, // TY[N] 1388 | 16'b0011_0001_0000_1111, // TW[N] 1389 | 16'b0011_0001_101x_xx01, // LD[N]i, (zpx), (zp)y, zp, zpx, zpy, ay, a, ax 1390 | 16'b0011_0001_1011_1011, // LD[N]w 1391 | 16'b0011_0001_1011_0010, // LD[N](zp)w 1392 | 16'bxx11_xx01_0xxx_xx01, // ADC[A..Q]op[N], SBC[A..Q]op[N], AND[A..Q]op[N], ORA[A..Q]op[N], EOR[A..Q]op[N] 1393 | 16'bxx11_xx01_111x_xx01, // SBC[A..Q]op[N] 1394 | 16'bxx11_xx01_0xx1_0010, // ORA[A..Q]op[N] (zp)w, AND[A..Q]op[N] (zp)w, ADC[A..Q]op[N] (zp)w 1395 | 16'bxx11_xx01_0xx1_1011, // ORA[A..Q]op[N] aw, AND[A..Q]op[N] aw, ADC[A..Q]op[N] aw 1396 | 16'bxx11_xx01_1111_0010, // SBC[A..Q]op[N] (zp)y 1397 | 16'bxx11_xx01_1111_1011, // SBC[A..Q]op[N] aw 1398 | 16'b1111_0101_0010_x100: // BIT[N] zp, a 1399 | dst_reg <= SEL_N; 1400 | 1401 | 16'b0011_0010_00x0_0111, // TZ[O], TS[O] 1402 | 16'bxx11_xx10_1000_1011, // T[A..Q][O] 1403 | 16'b1111_1010_00x1_1010, // INC[O], DEC[O] 1404 | 16'b0011_0010_0110_1000, // PL[O] 1405 | 16'b0011_0010_1000_1010, // TX[O] 1406 | 16'b0011_0010_1001_1000, // TY[O] 1407 | 16'b0011_0010_0000_1111, // TW[O] 1408 | 16'b0011_0010_101x_xx01, // LD[O]i, (zpx), (zp)y, zp, zpx, zpy, ay, a, ax 1409 | 16'b0011_0010_1011_1011, // LD[O]w 1410 | 16'b0011_0010_1011_0010, // LD[O](zp)w 1411 | 16'bxx11_xx10_0xxx_xx01, // ADC[A..Q]op[O], SBC[A..Q]op[O], AND[A..Q]op[O], ORA[A..Q]op[O], EOR[A..Q]op[O] 1412 | 16'bxx11_xx10_111x_xx01, // SBC[A..Q]op[O] 1413 | 16'bxx11_xx10_0xx1_0010, // ORA[A..Q]op[O] (zp)w, AND[A..Q]op[O] (zp)w, ADC[A..Q]op[O] (zp)w 1414 | 16'bxx11_xx10_0xx1_1011, // ORA[A..Q]op[O] aw, AND[A..Q]op[O] aw, ADC[A..Q]op[O] aw 1415 | 16'bxx11_xx10_1111_0010, // SBC[A..Q]op[O] (zp)y 1416 | 16'bxx11_xx10_1111_1011, // SBC[A..Q]op[O] aw 1417 | 16'b1111_1010_0010_x100: // BIT[O] zp, a 1418 | dst_reg <= SEL_O; 1419 | 1420 | 16'b0011_0011_00x0_0111, // TZ[Q], TS[Q] 1421 | 16'bxx11_xx11_1000_1011, // T[A..Q][Q] 1422 | 16'b1111_1111_00x1_1010, // INC[Q], DEC[Q] 1423 | 16'b0011_0011_0110_1000, // PL[Q] 1424 | 16'b0011_0011_1000_1010, // TX[Q] 1425 | 16'b0011_0011_1001_1000, // TY[Q] 1426 | 16'b0011_0011_0000_1111, // TW[Q] 1427 | 16'b0011_0011_101x_xx01, // LD[Q]i, (zpx), (zp)y, zp, zpx, zpy, ay, a, ax 1428 | 16'b0011_0011_1011_1011, // LD[Q]w 1429 | 16'b0011_0011_1011_0010, // LD[Q](zp)w 1430 | 16'bxx11_xx11_0xxx_xx01, // ADC[A..Q]op[Q], SBC[A..Q]op[Q], AND[A..Q]op[Q], ORA[A..Q]op[Q], EOR[A..Q]op[Q] 1431 | 16'bxx11_xx11_111x_xx01, // SBC[A..Q]op[Q] 1432 | 16'bxx11_xx11_0xx1_0010, // ORA[A..Q]op[Q] (zp)w, AND[A..Q]op[Q] (zp)w, ADC[A..Q]op[Q] (zp)w 1433 | 16'bxx11_xx11_0xx1_1011, // ORA[A..Q]op[Q] aw, AND[A..Q]op[Q] aw, ADC[A..Q]op[Q] aw 1434 | 16'bxx11_xx11_1111_0010, // SBC[A..Q]op[Q] (zp)y 1435 | 16'bxx11_xx11_1111_1011, // SBC[A..Q]op[Q] aw 1436 | 16'b1111_1111_0010_x100: // BIT[Q] zp, a 1437 | dst_reg <= SEL_Q; 1438 | 1439 | endcase 1440 | 1441 | always @(posedge clk) 1442 | if( state == DECODE && RDY ) 1443 | casex( IR[15:0] ) 1444 | 16'b00xx_00xx_0000_0111: // TZ[A..Q] 1445 | src_reg <= SEL_ZPP; 1446 | 1447 | 16'b00xx_00xx_0010_0111: // TS[A..Q] 1448 | src_reg <= SEL_SPP; 1449 | 1450 | 16'b00xx_00xx_0110_1000, // PL[A..Q] 1451 | 16'b0000_0000_x111_1010, // PLX, PLY 1452 | 16'b0000_0000_0110_1011, // PLW 1453 | 16'b0000_0000_0010_1000, // PLP 1454 | 16'b0000_0000_1011_1010: // TSX 1455 | src_reg <= SEL_S; 1456 | 1457 | 16'b0000_0000_100x_x110, // STX zp,zpy,a,ay 1458 | 16'b0000_0000_1001_x111, // STX zpw,aw 1459 | 16'b00xx_00xx_100x_1010, // TX[A..Q], TXS 1460 | 16'b0000_0000_1110_xx00, // INX, CPX 1461 | 16'b0000_0000_1100_1010, // DEX 1462 | 16'b0000_0000_1100_1011, // TXY 1463 | 16'b0000_0000_1101_1010, // PHX 1464 | 16'b0000_0000_0011_1111: // TXW 1465 | src_reg <= SEL_X; 1466 | 1467 | 16'b0000_0000_100x_x100, // STY zp,zpx,a 1468 | 16'b00xx_00xx_1001_1000, // TY[A..Q] 1469 | 16'b0000_0000_1100_0x00, // CPY imm,zp 1470 | 16'b0000_0000_1100_1100, // CPY a 1471 | 16'b0000_0000_1x00_1000, // DEY, INY 1472 | 16'b0000_0000_1010_1011, // TYX 1473 | 16'b0000_0000_0101_1010, // PHY 1474 | 16'b0000_0000_0101_1111: // TYW 1475 | src_reg <= SEL_Y; 1476 | 1477 | 16'b0000_0000_11x1_1000, // INW, DEW 1478 | 16'b0000_0000_1110_0010, // CPW imm 1479 | 16'b0000_0000_1100_x111, // CPW zp,a 1480 | 16'b0000_0000_1000_x111, // STW zp,a 1481 | 16'b0000_0000_0111_0100, // STW zpx 1482 | 16'b0000_0000_0100_1011, // PHW 1483 | 16'b00xx_00xx_0xx0_1111: // TW[A..Q], TWX, TWY 1484 | src_reg <= SEL_W; 1485 | 1486 | 16'b0000_0000_00x1_0111, // T[A]Z, T[A]S 1487 | 16'b00xx_00xx_1000_1011, // T[A][A..Q] 1488 | 16'b0000_0000_00x1_1010, // INC[A], DEC[A] 1489 | 16'b0000_0000_0100_1000, // PH[A] 1490 | 16'b0000_0000_1010_10x0, // T[A]X, T[A]Y 1491 | 16'b0000_0000_0001_1111, // T[A]W 1492 | 16'b0000_0000_100x_xx01, // ST[A]i, (zpx), (zp)y, zp, zpx, zpy, ay, a, ax 1493 | 16'b0000_0000_1001_0010, // ST[A] (zp)w 1494 | 16'b0000_0000_1001_1011, // ST[A] aw 1495 | 16'b0000_0000_110x_xx01, // CMP[A] i, (zpx), (zp)y, zp, zpx, ay, ax, a 1496 | 16'b0000_0000_1101_0010, // CMP[A] (zp)w 1497 | 16'b0000_0000_1101_1011, // CMP[A] aw 1498 | 16'b00xx_00xx_0xxx_xx01, // ADC[A]op[A..Q], SBC[A]op[A..Q], AND[A]op[A..Q], ORA[A]op[A..Q], EOR[A]op[A..Q] 1499 | 16'b00xx_00xx_111x_xx01, // SBC[A]op[A..Q] 1500 | 16'b00xx_00xx_0xx1_0010, // ORA[A]op[A..Q] (zp)w, AND[A]op[A..Q] (zp)w, ADC[A]op[A..Q] (zp)w 1501 | 16'b00xx_00xx_0xx1_1011, // ORA[A]op[A..Q] aw, AND[A]op[A..Q] aw, ADC[A]op[A..Q] aw 1502 | 16'b00xx_00xx_1111_0010, // SBC[A]op[A..Q] (zp)y 1503 | 16'b00xx_00xx_1111_1011, // SBC[A]op[A..Q] aw 1504 | 16'bxxxx_00xx_0xx0_1010, // ASL[A]op[A..D], ROL[A]op[A..D], LSR[A]op[A..D], ROR[A]op[A..D] (acc) 1505 | 16'b0000_0000_0010_x100: // BIT[A] zp, a 1506 | src_reg <= SEL_A; 1507 | 1508 | 16'b0000_0100_00x1_0111, // T[B]Z, T[B]S 1509 | 16'b00xx_01xx_1000_1011, // T[B][A..Q] 1510 | 16'b0000_0101_00x1_1010, // INC[B], DEC[B] 1511 | 16'b0000_0100_0100_1000, // PH[B] 1512 | 16'b0000_0100_1010_10x0, // T[B]X, T[B]Y 1513 | 16'b0000_0100_0001_1111, // T[B]W 1514 | 16'b0000_0100_100x_xx01, // ST[B] (zpx),(zp)y, zp, zpx, ay, a, ax 1515 | 16'b0000_0100_1001_0010, // ST[B] (zp)w 1516 | 16'b0000_0100_1001_1011, // ST[B] aw 1517 | 16'b0000_0100_110x_xx01, // CMP[B] i, (zpx), (zp)y, zp, zpx, ay, ax, a 1518 | 16'b0000_0100_1101_0010, // CMP[B] (zp)w 1519 | 16'b0000_0100_1101_1011, // CMP[B] aw 1520 | 16'b00xx_01xx_0xxx_xx01, // ADC[B]op[A..Q], SBC[B]op[A..Q], AND[B]op[A..Q], ORA[B]op[A..Q], EOR[B]op[A..Q] 1521 | 16'b00xx_01xx_111x_xx01, // SBC[B]op[A..Q] 1522 | 16'b00xx_01xx_0xx1_0010, // ORA[B]op[A..Q] (zp)w, AND[B]op[A..Q] (zp)w, ADC[B]op[A..Q] (zp)w 1523 | 16'b00xx_01xx_0xx1_1011, // ORA[B]op[A..Q] aw, AND[B]op[A..Q] aw, ADC[B]op[A..Q] aw 1524 | 16'b00xx_01xx_1111_0010, // SBC[B]op[A..Q] (zp)y 1525 | 16'b00xx_01xx_1111_1011, // SBC[B]op[A..Q] aw 1526 | 16'bxxxx_01xx_0xx0_1010, // ASL[B]op[A..D], ROL[B]op[A..D], LSR[B]op[A..D], ROR[B]op[A..D] (acc) 1527 | 16'b0000_0101_0010_x100: // BIT[B] zp, a 1528 | src_reg <= SEL_B; 1529 | 1530 | 16'b0000_1000_00x1_0111, // T[C]Z, T[C]S 1531 | 16'b00xx_10xx_1000_1011, // T[C][A..Q] 1532 | 16'b0000_1010_00x1_1010, // INC[C], DEC[C] 1533 | 16'b0000_1000_0100_1000, // PH[C] 1534 | 16'b0000_1000_1010_10x0, // T[C]X, T[C]Y 1535 | 16'b0000_1000_0001_1111, // T[C]W 1536 | 16'b0000_1000_100x_xx01, // ST[C] (zpx),(zp)y, zp, zpx, ay, a, ax 1537 | 16'b0000_1000_1001_0010, // ST[C] (zp)w 1538 | 16'b0000_1000_1001_1011, // ST[C] aw 1539 | 16'b0000_1000_110x_xx01, // CMP[C] i, (zpx), (zp)y, zp, zpx, ay, ax, a 1540 | 16'b0000_1000_1101_0010, // CMP[C] (zp)w 1541 | 16'b0000_1000_1101_1011, // CMP[C] aw 1542 | 16'b00xx_10xx_0xxx_xx01, // ADC[C]op[A..Q], SBC[C]op[A..Q], AND[C]op[A..Q], ORA[C]op[A..Q], EOR[C]op[A..Q] 1543 | 16'b00xx_10xx_111x_xx01, // SBC[C]op[A..Q] 1544 | 16'b00xx_10xx_0xx1_0010, // ORA[C]op[A..Q] (zp)w, AND[C]op[A..Q] (zp)w, ADC[C]op[A..Q] (zp)w 1545 | 16'b00xx_10xx_0xx1_1011, // ORA[C]op[A..Q] aw, AND[C]op[A..Q] aw, ADC[C]op[A..Q] aw 1546 | 16'b00xx_10xx_1111_0010, // SBC[C]op[A..Q] (zp)y 1547 | 16'b00xx_10xx_1111_1011, // SBC[C]op[A..Q] aw 1548 | 16'bxxxx_10xx_0xx0_1010, // ASL[C]op[A..D], ROL[C]op[A..D], LSR[C]op[A..D], ROR[C]op[A..D] (acc) 1549 | 16'b0000_1010_0010_x100: // BIT[C] zp, a 1550 | src_reg <= SEL_C; 1551 | 1552 | 16'b0000_1100_00x1_0111, // T[D]Z, T[D]S 1553 | 16'b00xx_11xx_1000_1011, // T[D][A..Q] 1554 | 16'b0000_1111_00x1_1010, // INC[D], DEC[D] 1555 | 16'b0000_1100_0100_1000, // PH[D] 1556 | 16'b0000_1100_1010_10x0, // T[D]X, T[D]Y 1557 | 16'b0000_1100_0001_1111, // T[D]W 1558 | 16'b0000_1100_100x_xx01, // ST[D] (zpx),(zp)y, zp, zpx, ay, a, ax 1559 | 16'b0000_1100_1001_0010, // ST[D] (zp)w 1560 | 16'b0000_1100_1001_1011, // ST[D] aw 1561 | 16'b0000_1100_110x_xx01, // CMP[D] i, (zpx), (zp)y, zp, zpx, ay, ax, a 1562 | 16'b0000_1100_1101_0010, // CMP[D] (zp)w 1563 | 16'b0000_1100_1101_1011, // CMP[D] aw 1564 | 16'b00xx_11xx_0xxx_xx01, // ADC[D]op[A..Q], SBC[D]op[A..Q], AND[D]op[A..Q], ORA[D]op[A..Q], EOR[D]op[A..Q] 1565 | 16'b00xx_11xx_111x_xx01, // SBC[D]op[A..Q] 1566 | 16'b00xx_11xx_0xx1_0010, // ORA[D]op[A..Q] (zp)w, AND[A]op[A..Q] (zp)w, ADC[D]op[A..Q] (zp)w 1567 | 16'b00xx_11xx_0xx1_1011, // ORA[D]op[A..Q] aw, AND[A]op[A..Q] aw, ADC[D]op[A..Q] aw 1568 | 16'b00xx_11xx_1111_0010, // SBC[D]op[A..Q] (zp)y 1569 | 16'b00xx_11xx_1111_1011, // SBC[D]op[A..Q] aw 1570 | 16'bxxxx_11xx_0xx0_1010, // ASL[D]op[A..D], ROL[D]op[A..D], LSR[D]op[A..D], ROR[D]op[A..D] (acc) 1571 | 16'b0000_1111_0010_x100: // BIT[D] zp, a 1572 | src_reg <= SEL_D; 1573 | 1574 | 16'b0100_0000_00x1_0111, // T[E]Z, T[E]S 1575 | 16'b01xx_00xx_1000_1011, // T[E][A..Q] 1576 | 16'b0101_0000_00x1_1010, // INC[E], DEC[E] 1577 | 16'b0100_0000_0100_1000, // PH[E] 1578 | 16'b0100_0000_1010_10x0, // T[E]X, T[E]Y 1579 | 16'b0100_0000_0001_1111, // T[E]W 1580 | 16'b0100_0000_100x_xx01, // ST[E] (zpx),(zp)y, zp, zpx, ay, a, ax 1581 | 16'b0100_0000_1001_0010, // ST[E] (zp)w 1582 | 16'b0100_0000_1001_1011, // ST[E] aw 1583 | 16'b0100_0000_110x_xx01, // CMP[E] i, (zpx), (zp)y, zp, zpx, ay, ax, a 1584 | 16'b0100_0000_1101_0010, // CMP[E] (zp)w 1585 | 16'b0100_0000_1101_1011, // CMP[E] aw 1586 | 16'b01xx_00xx_0xxx_xx01, // ADC[E]op[A..Q], SBC[E]op[A..Q], AND[E]op[A..Q], ORA[E]op[A..Q], EOR[E]op[A..Q] 1587 | 16'b01xx_00xx_111x_xx01, // SBC[E]op[A..Q] 1588 | 16'b01xx_00xx_0xx1_0010, // ORA[E]op[A..Q] (zp)w, AND[E]op[A..Q] (zp)w, ADC[E]op[A..Q] (zp)w 1589 | 16'b01xx_00xx_0xx1_1011, // ORA[E]op[A..Q] aw, AND[E]op[A..Q] aw, ADC[E]op[A..Q] aw 1590 | 16'b01xx_00xx_1111_0010, // SBC[E]op[A..Q] (zp)y 1591 | 16'b01xx_00xx_1111_1011, // SBC[E]op[A..Q] aw 1592 | 16'b0101_0000_0010_x100: // BIT[E] zp, a 1593 | src_reg <= SEL_E; 1594 | 1595 | 16'b0100_0100_00x1_0111, // T[F]Z, T[F]S 1596 | 16'b01xx_01xx_1000_1011, // T[F][A..Q] 1597 | 16'b0101_0101_00x1_1010, // INC[F], DEC[F] 1598 | 16'b0100_0100_0100_1000, // PH[F] 1599 | 16'b0100_0100_1010_10x0, // T[F]X, T[F]Y 1600 | 16'b0100_0100_0001_1111, // T[F]W 1601 | 16'b0100_0100_100x_xx01, // ST[F] (zpx),(zp)y, zp, zpx, ay, a, ax 1602 | 16'b0100_0100_1001_0010, // ST[F] (zp)w 1603 | 16'b0100_0100_1001_1011, // ST[F] aw 1604 | 16'b0100_0100_110x_xx01, // CMP[F] i, (zpx), (zp)y, zp, zpx, ay, ax, a 1605 | 16'b0100_0100_1101_0010, // CMP[F] (zp)w 1606 | 16'b0100_0100_1101_1011, // CMP[F] aw 1607 | 16'b01xx_01xx_0xxx_xx01, // ADC[F]op[A..Q], SBC[F]op[A..Q], AND[F]op[A..Q], ORA[F]op[A..Q], EOR[F]op[A..Q] 1608 | 16'b01xx_01xx_111x_xx01, // SBC[F]op[A..Q] 1609 | 16'b01xx_01xx_0xx1_0010, // ORA[F]op[A..Q] (zp)w, AND[F]op[A..Q] (zp)w, ADC[F]op[A..Q] (zp)w 1610 | 16'b01xx_01xx_0xx1_1011, // ORA[F]op[A..Q] aw, AND[F]op[A..Q] aw, ADC[F]op[A..Q] aw 1611 | 16'b01xx_01xx_1111_0010, // SBC[F]op[A..Q] (zp)y 1612 | 16'b01xx_01xx_1111_1011, // SBC[F]op[A..Q] aw 1613 | 16'b0101_0101_0010_x100: // BIT[F] zp, a 1614 | src_reg <= SEL_F; 1615 | 1616 | 16'b0100_1000_00x1_0111, // T[G]Z, T[G]S 1617 | 16'b01xx_10xx_1000_1011, // T[G][A..Q] 1618 | 16'b0101_1010_00x1_1010, // INC[G], DEC[G] 1619 | 16'b0100_1000_0100_1000, // PH[G] 1620 | 16'b0100_1000_1010_10x0, // T[G]X, T[G]Y 1621 | 16'b0100_1000_0001_1111, // T[G]W 1622 | 16'b0100_1000_100x_xx01, // ST[G] (zpx),(zp)y, zp, zpx, ay, a, ax 1623 | 16'b0100_1000_1001_0010, // ST[G] (zp)w 1624 | 16'b0100_1000_1001_1011, // ST[G] aw 1625 | 16'b0100_1000_110x_xx01, // CMP[G] i, (zpx), (zp)y, zp, zpx, ay, ax, a 1626 | 16'b0100_1000_1101_0010, // CMP[G] (zp)w 1627 | 16'b0100_1000_1101_1011, // CMP[G] aw 1628 | 16'b01xx_10xx_0xxx_xx01, // ADC[G]op[A..Q], SBC[G]op[A..Q], AND[G]op[A..Q], ORA[G]op[A..Q], EOR[G]op[A..Q] 1629 | 16'b01xx_10xx_111x_xx01, // SBC[G]op[A..Q] 1630 | 16'b01xx_10xx_0xx1_0010, // ORA[G]op[A..Q] (zp)w, AND[G]op[A..Q] (zp)w, ADC[G]op[A..Q] (zp)w 1631 | 16'b01xx_10xx_0xx1_1011, // ORA[G]op[A..Q] aw, AND[G]op[A..Q] aw, ADC[G]op[A..Q] aw 1632 | 16'b01xx_10xx_1111_0010, // SBC[G]op[A..Q] (zp)y 1633 | 16'b01xx_10xx_1111_1011, // SBC[G]op[A..Q] aw 1634 | 16'b0101_1010_0010_x100: // BIT[G] zp, a 1635 | src_reg <= SEL_G; 1636 | 1637 | 16'b0100_1100_00x1_0111, // T[H]Z, T[H]S 1638 | 16'b01xx_11xx_1000_1011, // T[H][A..Q] 1639 | 16'b0101_1111_00x1_1010, // INC[H], DEC[H] 1640 | 16'b0100_1100_0100_1000, // PH[H] 1641 | 16'b0100_1100_1010_10x0, // T[H]X, T[H]Y 1642 | 16'b0100_1100_0001_1111, // T[H]W 1643 | 16'b0100_1100_100x_xx01, // ST[H] (zpx),(zp)y, zp, zpx, ay, a, ax 1644 | 16'b0100_1100_1001_0010, // ST[H] (zp)w 1645 | 16'b0100_1100_1001_1011, // ST[H] aw 1646 | 16'b0100_1100_110x_xx01, // CMP[H] i, (zpx), (zp)y, zp, zpx, ay, ax, a 1647 | 16'b0100_1100_1101_0010, // CMP[H] (zp)w 1648 | 16'b0100_1100_1101_1011, // CMP[H] aw 1649 | 16'b01xx_11xx_0xxx_xx01, // ADC[H]op[A..Q], SBC[H]op[A..Q], AND[H]op[A..Q], ORA[H]op[A..Q], EOR[H]op[A..Q] 1650 | 16'b01xx_11xx_111x_xx01, // SBC[H]op[A..Q] 1651 | 16'b01xx_11xx_0xx1_0010, // ORA[H]op[A..Q] (zp)w, AND[H]op[A..Q] (zp)w, ADC[H]op[A..Q] (zp)w 1652 | 16'b01xx_11xx_0xx1_1011, // ORA[H]op[A..Q] aw, AND[H]op[A..Q] aw, ADC[H]op[A..Q] aw 1653 | 16'b01xx_11xx_1111_0010, // SBC[H]op[A..Q] (zp)y 1654 | 16'b01xx_11xx_1111_1011, // SBC[H]op[A..Q] aw 1655 | 16'b0101_1111_0010_x100: // BIT[H] zp, a 1656 | src_reg <= SEL_H; 1657 | 1658 | 16'b1000_0000_00x1_0111, // T[I]Z, T[I]S 1659 | 16'b10xx_00xx_1000_1011, // T[I][A..Q] 1660 | 16'b1010_0000_00x1_1010, // INC[I], DEC[I] 1661 | 16'b1000_0000_0100_1000, // PH[I] 1662 | 16'b1000_0000_1010_10x0, // T[I]X, T[I]Y 1663 | 16'b1000_0000_0001_1111, // T[I]W 1664 | 16'b1000_0000_100x_xx01, // ST[I] (zpx),(zp)y, zp, zpx, ay, a, ax 1665 | 16'b1000_0000_1001_0010, // ST[I] (zp)w 1666 | 16'b1000_0000_1001_1011, // ST[I] aw 1667 | 16'b1000_0000_110x_xx01, // CMP[I] i, (zpx), (zp)y, zp, zpx, ay, ax, a 1668 | 16'b1000_0000_1101_0010, // CMP[I] (zp)w 1669 | 16'b1000_0000_1101_1011, // CMP[I] aw 1670 | 16'b10xx_00xx_0xxx_xx01, // ADC[I]op[A..Q], SBC[I]op[A..Q], AND[I]op[A..Q], ORA[I]op[A..Q], EOR[I]op[A..Q] 1671 | 16'b10xx_00xx_111x_xx01, // SBC[I]op[A..Q] 1672 | 16'b10xx_00xx_0xx1_0010, // ORA[I]op[A..Q] (zp)w, AND[I]op[A..Q] (zp)w, ADC[I]op[A..Q] (zp)w 1673 | 16'b10xx_00xx_0xx1_1011, // ORA[I]op[A..Q] aw, AND[I]op[A..Q] aw, ADC[I]op[A..Q] aw 1674 | 16'b10xx_00xx_1111_0010, // SBC[I]op[A..Q] (zp)y 1675 | 16'b10xx_00xx_1111_1011, // SBC[I]op[A..Q] aw 1676 | 16'b1010_0000_0010_x100: // BIT[I] zp, a 1677 | src_reg <= SEL_I; 1678 | 1679 | 16'b1000_0100_00x1_0111, // T[J]Z, T[J]S 1680 | 16'b10xx_01xx_1000_1011, // T[J][A..Q] 1681 | 16'b1010_0101_00x1_1010, // INC[J], DEC[J] 1682 | 16'b1000_0100_0100_1000, // PH[J] 1683 | 16'b1000_0100_1010_10x0, // T[J]X, T[J]Y 1684 | 16'b1000_0100_0001_1111, // T[J]W 1685 | 16'b1000_0100_100x_xx01, // ST[J] (zpx),(zp)y, zp, zpx, ay, a, ax 1686 | 16'b1000_0100_1001_0010, // ST[J] (zp)w 1687 | 16'b1000_0100_1001_1011, // ST[J] aw 1688 | 16'b1000_0100_110x_xx01, // CMP[J] i, (zpx), (zp)y, zp, zpx, ay, ax, a 1689 | 16'b1000_0100_1101_0010, // CMP[J] (zp)w 1690 | 16'b1000_0100_1101_1011, // CMP[J] aw 1691 | 16'b10xx_01xx_0xxx_xx01, // ADC[J]op[A..Q], SBC[J]op[A..Q], AND[J]op[A..Q], ORA[J]op[A..Q], EOR[J]op[A..Q] 1692 | 16'b10xx_01xx_111x_xx01, // SBC[J]op[A..Q] 1693 | 16'b10xx_01xx_0xx1_0010, // ORA[J]op[A..Q] (zp)w, AND[J]op[A..Q] (zp)w, ADC[J]op[A..Q] (zp)w 1694 | 16'b10xx_01xx_0xx1_1011, // ORA[J]op[A..Q] aw, AND[J]op[A..Q] aw, ADC[J]op[A..Q] aw 1695 | 16'b10xx_01xx_1111_0010, // SBC[J]op[A..Q] (zp)y 1696 | 16'b10xx_01xx_1111_1011, // SBC[J]op[A..Q] aw 1697 | 16'b1010_0101_0010_x100: // BIT[J] zp, a 1698 | src_reg <= SEL_J; 1699 | 1700 | 16'b1000_1000_00x1_0111, // T[K]Z, T[K]S 1701 | 16'b10xx_10xx_1000_1011, // T[K][A..Q] 1702 | 16'b1010_1010_00x1_1010, // INC[K], DEC[K] 1703 | 16'b1000_1000_0100_1000, // PH[K] 1704 | 16'b1000_1000_1010_10x0, // T[K]X, T[K]Y 1705 | 16'b1000_1000_0001_1111, // T[K]W 1706 | 16'b1000_1000_100x_xx01, // ST[K] (zpx),(zp)y, zp, zpx, ay, a, ax 1707 | 16'b1000_1000_1001_0010, // ST[K] (zp)w 1708 | 16'b1000_1000_1001_1011, // ST[K] aw 1709 | 16'b1000_1000_110x_xx01, // CMP[K] i, (zpx), (zp)y, zp, zpx, ay, ax, a 1710 | 16'b1000_1000_1101_0010, // CMP[K] (zp)w 1711 | 16'b1000_1000_1101_1011, // CMP[K] aw 1712 | 16'b10xx_10xx_0xxx_xx01, // ADC[K]op[A..Q], SBC[K]op[A..Q], AND[K]op[A..Q], ORA[K]op[A..Q], EOR[K]op[A..Q] 1713 | 16'b10xx_10xx_111x_xx01, // SBC[K]op[A..Q] 1714 | 16'b10xx_10xx_0xx1_0010, // ORA[K]op[A..Q] (zp)w, AND[K]op[A..Q] (zp)w, ADC[K]op[A..Q] (zp)w 1715 | 16'b10xx_10xx_0xx1_1011, // ORA[K]op[A..Q] aw, AND[K]op[A..Q] aw, ADC[K]op[A..Q] aw 1716 | 16'b10xx_10xx_1111_0010, // SBC[K]op[A..Q] (zp)y 1717 | 16'b10xx_10xx_1111_1011, // SBC[K]op[A..Q] aw 1718 | 16'b1010_1010_0010_x100: // BIT[K] zp, a 1719 | src_reg <= SEL_K; 1720 | 1721 | 16'b1000_1100_00x1_0111, // T[L]Z, T[L]S 1722 | 16'b10xx_11xx_1000_1011, // T[L][A..Q] 1723 | 16'b1010_1111_00x1_1010, // INC[L], DEC[L] 1724 | 16'b1000_1100_0100_1000, // PH[L] 1725 | 16'b1000_1100_1010_10x0, // T[L]X, T[L]Y 1726 | 16'b1000_1100_0001_1111, // T[L]W 1727 | 16'b1000_1100_100x_xx01, // ST[L] (zpx),(zp)y, zp, zpx, ay, a, ax 1728 | 16'b1000_1100_1001_0010, // ST[L] (zp)w 1729 | 16'b1000_1100_1001_1011, // ST[L] aw 1730 | 16'b1000_1100_110x_xx01, // CMP[L] i, (zpx), (zp)y, zp, zpx, ay, ax, a 1731 | 16'b1000_1100_1101_0010, // CMP[L] (zp)w 1732 | 16'b1000_1100_1101_1011, // CMP[L] aw 1733 | 16'b10xx_11xx_0xxx_xx01, // ADC[L]op[A..Q], SBC[L]op[A..Q], AND[L]op[A..Q], ORA[L]op[A..Q], EOR[L]op[A..Q] 1734 | 16'b10xx_11xx_111x_xx01, // SBC[L]op[A..Q] 1735 | 16'b10xx_11xx_0xx1_0010, // ORA[L]op[A..Q] (zp)w, AND[L]op[A..Q] (zp)w, ADC[L]op[A..Q] (zp)w 1736 | 16'b10xx_11xx_0xx1_1011, // ORA[L]op[A..Q] aw, AND[L]op[A..Q] aw, ADC[L]op[A..Q] aw 1737 | 16'b10xx_11xx_1111_0010, // SBC[L]op[A..Q] (zp)y 1738 | 16'b10xx_11xx_1111_1011, // SBC[L]op[A..Q] aw 1739 | 16'b1010_1111_0010_x100: // BIT[L] zp, a 1740 | src_reg <= SEL_L; 1741 | 1742 | 16'b1100_0000_00x1_0111, // T[M]Z, T[M]S 1743 | 16'b11xx_00xx_1000_1011, // T[M][A..Q] 1744 | 16'b1111_0000_00x1_1010, // INC[M], DEC[M] 1745 | 16'b1100_0000_0100_1000, // PH[M] 1746 | 16'b1100_0000_1010_10x0, // T[M]X, T[M]Y 1747 | 16'b1100_0000_0001_1111, // T[M]W 1748 | 16'b1100_0000_100x_xx01, // ST[M] (zpx),(zp)y, zp, zpx, ay, a, ax 1749 | 16'b1100_0000_1001_0010, // ST[M] (zp)w 1750 | 16'b1100_0000_1001_1011, // ST[M] aw 1751 | 16'b1100_0000_110x_xx01, // CMP[M] i, (zpx), (zp)y, zp, zpx, ay, ax, a 1752 | 16'b1100_0000_1101_0010, // CMP[M] (zp)w 1753 | 16'b1100_0000_1101_1011, // CMP[M] aw 1754 | 16'b11xx_00xx_0xxx_xx01, // ADC[M]op[A..Q], SBC[M]op[A..Q], AND[M]op[A..Q], ORA[M]op[A..Q], EOR[M]op[A..Q] 1755 | 16'b11xx_00xx_111x_xx01, // SBC[M]op[A..Q] 1756 | 16'b11xx_00xx_0xx1_0010, // ORA[M]op[A..Q] (zp)w, AND[M]op[A..Q] (zp)w, ADC[M]op[A..Q] (zp)w 1757 | 16'b11xx_00xx_0xx1_1011, // ORA[M]op[A..Q] aw, AND[M]op[A..Q] aw, ADC[M]op[A..Q] aw 1758 | 16'b11xx_00xx_1111_0010, // SBC[M]op[A..Q] (zp)y 1759 | 16'b11xx_00xx_1111_1011, // SBC[M]op[A..Q] aw 1760 | 16'b1111_0000_0010_x100: // BIT[M] zp, a 1761 | src_reg <= SEL_M; 1762 | 1763 | 16'b1100_0100_00x1_0111, // T[N]Z, T[N]S 1764 | 16'b11xx_01xx_1000_1011, // T[N][A..Q] 1765 | 16'b1111_0101_00x1_1010, // INC[N], DEC[N] 1766 | 16'b1100_0100_0100_1000, // PH[N] 1767 | 16'b1100_0100_1010_10x0, // T[N]X, T[N]Y 1768 | 16'b1100_0100_0001_1111, // T[N]W 1769 | 16'b1100_0100_100x_xx01, // ST[N] (zpx),(zp)y, zp, zpx, ay, a, ax 1770 | 16'b1100_0100_1001_0010, // ST[N] (zp)w 1771 | 16'b1100_0100_1001_1011, // ST[N] aw 1772 | 16'b1100_0100_110x_xx01, // CMP[N] i, (zpx), (zp)y, zp, zpx, ay, ax, a 1773 | 16'b1100_0100_1101_0010, // CMP[N] (zp)w 1774 | 16'b1100_0100_1101_1011, // CMP[N] aw 1775 | 16'b11xx_01xx_0xxx_xx01, // ADC[N]op[A..Q], SBC[N]op[A..Q], AND[N]op[A..Q], ORA[N]op[A..Q], EOR[N]op[A..Q] 1776 | 16'b11xx_01xx_111x_xx01, // SBC[N]op[A..Q] 1777 | 16'b11xx_01xx_0xx1_0010, // ORA[N]op[A..Q] (zp)w, AND[N]op[A..Q] (zp)w, ADC[N]op[A..Q] (zp)w 1778 | 16'b11xx_01xx_0xx1_1011, // ORA[N]op[A..Q] aw, AND[N]op[A..Q] aw, ADC[N]op[A..Q] aw 1779 | 16'b11xx_01xx_1111_0010, // SBC[N]op[A..Q] (zp)y 1780 | 16'b11xx_01xx_1111_1011, // SBC[N]op[A..Q] aw 1781 | 16'b1111_0101_0010_x100: // BIT[N] zp, a 1782 | src_reg <= SEL_N; 1783 | 1784 | 16'b1100_1000_00x1_0111, // T[O]Z, T[O]S 1785 | 16'b11xx_10xx_1000_1011, // T[O][A..Q] 1786 | 16'b1111_1010_00x1_1010, // INC[O], DEC[O] 1787 | 16'b1100_1000_0100_1000, // PH[O] 1788 | 16'b1100_1000_1010_10x0, // T[O]X, T[O]Y 1789 | 16'b1100_1000_0001_1111, // T[O]W 1790 | 16'b1100_1000_100x_xx01, // ST[O] (zpx),(zp)y, zp, zpx, ay, a, ax 1791 | 16'b1100_1000_1001_0010, // ST[O] (zp)w 1792 | 16'b1100_1000_1001_1011, // ST[O] aw 1793 | 16'b1100_1000_110x_xx01, // CMP[O] i, (zpx), (zp)y, zp, zpx, ay, ax, a 1794 | 16'b1100_1000_1101_0010, // CMP[O] (zp)w 1795 | 16'b1100_1000_1101_1011, // CMP[O] aw 1796 | 16'b11xx_10xx_0xxx_xx01, // ADC[O]op[A..Q], SBC[O]op[A..Q], AND[O]op[A..Q], ORA[O]op[A..Q], EOR[O]op[A..Q] 1797 | 16'b11xx_10xx_111x_xx01, // SBC[O]op[A..Q] 1798 | 16'b11xx_10xx_0xx1_0010, // ORA[O]op[A..Q] (zp)w, AND[O]op[A..Q] (zp)w, ADC[O]op[A..Q] (zp)w 1799 | 16'b11xx_10xx_0xx1_1011, // ORA[O]op[A..Q] aw, AND[O]op[A..Q] aw, ADC[O]op[A..Q] aw 1800 | 16'b11xx_10xx_1111_0010, // SBC[O]op[A..Q] (zp)y 1801 | 16'b11xx_10xx_1111_1011, // SBC[O]op[A..Q] aw 1802 | 16'b1111_1010_0010_x100: // BIT[O] zp, a 1803 | src_reg <= SEL_O; 1804 | 1805 | 16'b1100_1100_00x1_0111, // T[Q]Z, T[Q]S 1806 | 16'b11xx_11xx_1000_1011, // T[Q][A..Q] 1807 | 16'b1111_1111_00x1_1010, // INC[Q], DEC[Q] 1808 | 16'b1100_1100_0100_1000, // PH[Q] 1809 | 16'b1100_1100_1010_10x0, // T[Q]X, T[Q]Y 1810 | 16'b1100_1100_0001_1111, // T[Q]W 1811 | 16'b1100_1100_100x_xx01, // ST[Q] (zpx),(zp)y, zp, zpx, ay, a, ax 1812 | 16'b1100_1100_1001_0010, // ST[Q] (zp)w 1813 | 16'b1100_1100_1001_1011, // ST[Q] aw 1814 | 16'b1100_1100_110x_xx01, // CMP[Q] i, (zpx), (zp)y, zp, zpx, ay, ax, a 1815 | 16'b1100_1100_1101_0010, // CMP[Q] (zp)w 1816 | 16'b1100_1100_1101_1011, // CMP[Q] aw 1817 | 16'b11xx_11xx_0xxx_xx01, // ADC[Q]op[A..Q], SBC[Q]op[A..Q], AND[Q]op[A..Q], ORA[Q]op[A..Q], EOR[Q]op[A..Q] 1818 | 16'b11xx_11xx_111x_xx01, // SBC[Q]op[A..Q] 1819 | 16'b11xx_11xx_0xx1_0010, // ORA[Q]op[A..Q] (zp)w, AND[Q]op[A..Q] (zp)w, ADC[Q]op[A..Q] (zp)w 1820 | 16'b11xx_11xx_0xx1_1011, // ORA[Q]op[A..Q] aw, AND[Q]op[A..Q] aw, ADC[Q]op[A..Q] aw 1821 | 16'b11xx_11xx_1111_0010, // SBC[Q]op[A..Q] (zp)y 1822 | 16'b11xx_11xx_1111_1011, // SBC[Q]op[A..Q] aw 1823 | 16'b1111_1111_0010_x100: // BIT[Q] zp, a 1824 | src_reg <= SEL_Q; 1825 | 1826 | endcase 1827 | 1828 | always @(posedge clk) 1829 | if( state == DECODE && RDY ) 1830 | casex( IR[15:0] ) 1831 | 16'bxxxx_xxxx_xxx1_0010, // INDW 1832 | 16'b0000_0000_10x1_x111, // LDX/STX zpw, aw 1833 | 16'bxxxx_xxxx_xxx1_1011: // abs, W 1834 | index_w <= 1; 1835 | 1836 | default: index_w <= 0; 1837 | endcase 1838 | 1839 | always @(posedge clk) 1840 | if( state == DECODE && RDY ) 1841 | casex( IR[15:0] ) 1842 | 16'bxxxx_xxxx_xxx1_0001, // INDY 1843 | 16'b0000_0000_10x1_x110, // LDX/STX zpy, ay 1844 | 16'bxxxx_xxxx_xxx1_1001: // abs, Y 1845 | index_y <= 1; 1846 | 1847 | default: index_y <= 0; 1848 | endcase 1849 | 1850 | always @(posedge clk) 1851 | if( state == DECODE && RDY ) 1852 | casex( IR[15:0] ) 1853 | 16'b0000_0000_0111_0100, // STW zpx 1854 | 16'bxx00_xx00_1000_01xx, // STY zp, ST[A..Q] zp, STX zp, STW zp 1855 | 16'bxx00_xx00_1001_x001, // ST[A..Q] (zp)y, ay 1856 | 16'bxx00_xx00_1001_0010, // ST[A..Q] (zp)w 1857 | 16'bxx00_xx00_1001_1011, // ST[A..Q] aw 1858 | 16'bxx00_xx00_1001_01xx, // STY zpx, ST[A..Q] zpx, STX zpy, STX zpw 1859 | 16'bxx00_xx00_100x_11xx: // ST[A..Q] ax, STX ay, STX aw, STX a, STY a, ST[A..Q] a, STW a 1860 | store <= 1; 1861 | 1862 | default: store <= 0; 1863 | 1864 | endcase 1865 | 1866 | always @(posedge clk ) 1867 | if( state == DECODE && RDY ) 1868 | casex( IR[15:0] ) 1869 | 16'bxxxx_0000_0xxx_x110, // ASL, ROL, LSR, ROR (abs, absx, zpg, zpgx) 1870 | 16'b0000_0000_11xx_x110: // DEC zp, zpx, a, ax, INC zp, zpx, a, ax 1871 | write_back <= 1; 1872 | 1873 | default: write_back <= 0; 1874 | endcase 1875 | 1876 | 1877 | always @(posedge clk ) 1878 | if( state == DECODE && RDY ) 1879 | casex( IR[15:0] ) 1880 | 16'b00xx_00xx_1010_0xxx, // LD[A..Q] zpx, zp, LDX #, zp, LDY #, zp, LDW zp 1881 | 16'b00xx_00xx_1010_1001, // LD[A..Q] # 1882 | 16'b00xx_00xx_1010_11xx, // LDY a, LD[A..Q] a, LDX a, LDW a 1883 | 16'b00xx_00xx_1011_xxx1, // LD[A..Q] (zp)y, zpx, ay, aw, ax, LDX zpw, aw 1884 | 16'b0000_0000_1011_01x0, // LDY zpx, LDX zpy 1885 | 16'b0000_0000_1011_11x0, // LDY ax, LDX ay 1886 | 16'b00xx_00xx_1011_0010, // LD[A..Q] zpw 1887 | 16'b0000_0000_1100_0010, // LDW # 1888 | 16'b0000_0000_1111_0100, // LDW zpx 1889 | 16'b0000_0000_1101_1100: // LDW ax 1890 | load_only <= 1; 1891 | default: load_only <= 0; 1892 | endcase 1893 | 1894 | always @(posedge clk ) 1895 | if( state == DECODE && RDY ) 1896 | casex( IR[15:0] ) 1897 | 16'b0000_0000_111x_x110, // INC zp, zpx, a, ax 1898 | 16'b0000_0000_11x0_1000, // INX, INY 1899 | 16'b0000_0000_1101_1000, // INW 1900 | 16'bxxxx_xxxx_0001_1010: // INC[A..Q] 1901 | inc <= 1; 1902 | 1903 | default: inc <= 0; 1904 | endcase 1905 | 1906 | always @(posedge clk ) 1907 | if( (state == DECODE || state == BRK0) && RDY ) 1908 | casex( IR[15:0] ) 1909 | 16'bxxxx_xxxx_011x_xx01, // ADC[A..Q]i, (zpx), (zp)y, zp, zpx, ay, ax, a op[A..Q] 1910 | 16'bxxxx_xxxx_0111_0010, // ADC[A..Q](zp)w op[A..Q] 1911 | 16'bxxxx_xxxx_0111_1011, // ADC[A..Q]aw op[A..Q] 1912 | 16'bxxxx_xxxx_111x_xx01, // SBC[A..Q]i, (zpx), (zp)y, zp, zpx, ay, ax, a op[A..Q] 1913 | 16'bxxxx_xxxx_1111_0010, // SBC[A..Q](zp)w op[A..Q] 1914 | 16'bxxxx_xxxx_1111_1011: // SBC[A..Q]aw op[A..Q] 1915 | adc_sbc <= 1; 1916 | 1917 | default: adc_sbc <= 0; 1918 | endcase 1919 | 1920 | always @(posedge clk ) 1921 | if( state == DECODE && RDY ) 1922 | casex( IR[15:0] ) 1923 | 16'bxxxx_0000_0xxx_x110, // ASL, ROL, LSR, ROR a, ax, zp, zpx 1924 | 16'bxxxx_xxxx_0xx0_1010: // ASL[A..D]op[A..D], ROL[A..D]op[A..D], LSR[A..D]op[A..D], ROR[A..D]op[A..D] acc 1925 | shift <= 1; 1926 | 1927 | default: shift <= 0; 1928 | endcase 1929 | 1930 | always @(posedge clk ) 1931 | if( state == DECODE && RDY ) 1932 | casex( IR[15:0] ) 1933 | 16'b0000_0000_11x0_0x00, // CPX, CPY (imm/zp) 1934 | 16'b0000_0000_11x0_1100, // CPX, CPY (abs) 1935 | 16'b0000_0000_1110_0010, // CPW # 1936 | 16'b0000_0000_1100_x111, // CPW zp,a 1937 | 16'bxx00_xx00_110x_xx01, // CMP[A..Q] i, (zpx), (zp)y, zp, zpx, ay, ax, a 1938 | 16'bxx00_xx00_1101_0010, // CMP[A..Q] (zp)w 1939 | 16'bxx00_xx00_1101_1011: // CMP[A..Q] aw 1940 | compare <= 1; 1941 | 1942 | default: compare <= 0; 1943 | endcase 1944 | 1945 | always @(posedge clk ) 1946 | if( state == DECODE && RDY ) 1947 | casex( IR[15:0] ) 1948 | 16'bxxxx_0000_01xx_x110, // ROR, LSR a, ax, zp, zpx 1949 | 16'bxxxx_xxxx_01x0_1010: // LSR[A..D]op[A..D], ROR[A..D]op[A..D] acc 1950 | shift_right <= 1; 1951 | 1952 | default: shift_right <= 0; 1953 | endcase 1954 | 1955 | always @(posedge clk ) 1956 | if( state == DECODE && RDY ) 1957 | casex( IR[15:0] ) 1958 | 16'bxxxx_xxxx_0x10_1010, // ROL[A..D]op[A..D], ROR[A..D]op[A..D] acc 1959 | 16'bxxxx_0000_0x1x_x110: // ROR, ROL a, ax, zp, zpx 1960 | rotate <= 1; 1961 | 1962 | default: rotate <= 0; 1963 | endcase 1964 | 1965 | always @(posedge clk ) 1966 | if( state == DECODE && RDY ) 1967 | casex( IR[15:0] ) 1968 | 16'bxxxx_0000_00xx_x110, // ROL, ASL a, ax, zp, zpx 1969 | 16'bxxxx_xxxx_00x0_1010: // ASL[A..D]op[A..D], ROL[A..D]op[A..D] acc 1970 | op <= OP_ROL; 1971 | 1972 | 16'bxxxx_xxxx_0010_x100: // BIT[A..Q] zp, a 1973 | op <= OP_AND; 1974 | 1975 | 16'bxxxx_0000_01xx_x110, // ROR, LSR a, ax, zp, zpx 1976 | 16'bxxxx_xxxx_01x0_1010: // LSR[A..D]op[A..D], ROR[A..D]op[A..D] acc 1977 | op <= OP_A; 1978 | 1979 | 16'b0000_0000_1111_1000, // DEW 1980 | 16'b0000_0000_1000_1000, // DEY 1981 | 16'b0000_0000_1100_1010, // DEX 1982 | 16'bxxxx_xxxx_0011_1010, // DEC[A..Q] 1983 | 16'b0000_0000_110x_x110, // DEC zp, zpx, a, ax 1984 | 16'bxxxx_xxxx_11xx_xx01, // CMP[A..Q]i, (zpx), (zp)y, zp, zpx, ay, a, ax, SBC[A..Q]i, (zpx), (zp)y, zp, zpx, ay, a, ax op[A..Q] 1985 | 16'bxxxx_xxxx_11x1_0010, // CMP[A..Q](zp)w, SBC[A..Q](zp)w op[A..Q] 1986 | 16'bxxxx_xxxx_11x1_1011, // CMP[A..Q]aw, SBC[A..Q]aw op[A..Q] 1987 | 16'b0000_0000_11x0_0x00, // CPX, CPY (imm, zpg) 1988 | 16'b0000_0000_11x0_1100, // CPX, CPY abs 1989 | 16'b0000_0000_1110_0010, // CPW i 1990 | 16'b0000_0000_1100_x111: // CPW zp,a 1991 | op <= OP_SUB; 1992 | 1993 | 16'bxxxx_xxxx_010x_xx01, // EOR[A..Q]op[A..Q] 1994 | 16'bxxxx_xxxx_0101_0010, // EOR[A..Q](zp)w op[A..Q] 1995 | 16'bxxxx_xxxx_0101_1011, // EOR[A..Q]aw op[A..Q] 1996 | 16'bxxxx_xxxx_00xx_xx01, // ORA[A..Q]i, (zpx), (zp)y, zp, zpx, ay, ax,a op[A..Q], AND[A..Q]i, (zpx), (zp)y, zp, zpx, ay, ax,a op[A..Q] 1997 | 16'bxxxx_xxxx_00x1_0010, // ORA[A..Q](zp)w op[A..Q], AND[A..Q](zp)w op[A..Q] 1998 | 16'bxxxx_xxxx_00x1_1011: // ORA[A..Q]aw op[A..Q], AND[A..Q]aw op[A..Q] 1999 | op <= { 2'b11, IR[6:5] }; 2000 | 2001 | default: op <= OP_ADD; 2002 | endcase 2003 | 2004 | always @(posedge clk ) 2005 | if( state == DECODE && RDY ) 2006 | casex( IR[15:0] ) 2007 | 16'bxxxx_xxxx_0010_x100: // BIT[A..Q]op[A..Q] zp, a 2008 | BIT <= 1; 2009 | 2010 | default: BIT <= 0; 2011 | endcase 2012 | 2013 | /* 2014 | * special instructions 2015 | */ 2016 | 2017 | always @(posedge clk ) 2018 | if( state == DECODE && RDY ) begin 2019 | php <= (IR[15:0] == 16'h0008); 2020 | clc <= (IR[15:0] == 16'h0018); 2021 | plp <= (IR[15:0] == 16'h0028); 2022 | sec <= (IR[15:0] == 16'h0038); 2023 | cli <= (IR[15:0] == 16'h0058); 2024 | sei <= (IR[15:0] == 16'h0078); 2025 | clv <= (IR[15:0] == 16'h00b8); 2026 | brk <= (IR[15:0] == 16'h0000); 2027 | end 2028 | 2029 | always @(posedge clk) 2030 | if( RDY ) 2031 | cond_code <= IR[7:5]; 2032 | 2033 | always @* 2034 | case( cond_code ) 2035 | 3'b000: cond_true <= ~N; 2036 | 3'b001: cond_true <= N; 2037 | 3'b010: cond_true <= ~V; 2038 | 3'b011: cond_true <= V; 2039 | 3'b100: cond_true <= ~C; 2040 | 3'b101: cond_true <= C; 2041 | 3'b110: cond_true <= ~Z; 2042 | 3'b111: cond_true <= Z; 2043 | endcase 2044 | 2045 | 2046 | reg NMI_1 = 0; // delayed NMI signal 2047 | 2048 | always @(posedge clk) 2049 | NMI_1 <= NMI; 2050 | 2051 | always @(posedge clk ) 2052 | if( NMI_edge && state == BRK3 ) 2053 | NMI_edge <= 0; 2054 | else if( NMI & ~NMI_1 ) 2055 | NMI_edge <= 1; 2056 | 2057 | endmodule 2058 | --------------------------------------------------------------------------------