├── .editor_defines ├── .gitignore ├── .gitlab-ci.yml ├── .project ├── .pydevproject ├── .settings ├── com.elphel.vdt.FPGA_project.prefs ├── com.elphel.vdt.ISExst.prefs ├── com.elphel.vdt.VivadoBitstream.prefs ├── com.elphel.vdt.VivadoPlace.prefs ├── com.elphel.vdt.VivadoSynthesis.prefs ├── com.elphel.vdt.VivadoTimimgSummaryReportSynthesis.prefs ├── com.elphel.vdt.VivadoTimingReportSynthesis.prefs ├── com.elphel.vdt.iverilog.prefs └── com.elphel.vdt.prefs ├── OSERDESE1.diff ├── README.md ├── axi ├── axibram.v ├── axibram_read.v ├── axibram_write.v └── macros393.v ├── ddr3 ├── 1024Mb_ddr3_parameters.vh ├── 2048Mb_ddr3_parameters.vh ├── 4096Mb_ddr3_parameters.vh ├── ddr3.v └── readme.txt ├── ddr_refresh.v ├── ddrc_control.v ├── ddrc_status.v ├── ddrc_test01.v ├── ddrc_test01.xcf ├── ddrc_test01.xdc ├── ddrc_test01_testbench.sav ├── ddrc_test01_testbench.tf ├── ddrc_test01_timing.xdc ├── glbl.v ├── hardware_tests └── eddr3_eye02.ods ├── phy ├── byte_lane.v ├── cmd_addr.v ├── cmda_single.v ├── ddrc_sequencer.v ├── dm_single.v ├── dq_single.v ├── dqs_single.v ├── dqs_single_nofine.v ├── phy_cmd.v ├── phy_top.v ├── test_dqs.v ├── test_dqs01.v ├── test_dqs01_placement.xdc ├── test_dqs02.v ├── test_dqs02_placement.xdc ├── test_dqs03.v ├── test_dqs03_placement.xdc ├── test_dqs04.v ├── test_dqs04_placement.xdc ├── test_dqs05.v ├── test_dqs05_placement.xdc ├── test_dqs06.v ├── test_dqs06_placement.xdc ├── test_dqs07.v ├── test_dqs07_placement.xdc └── test_phy_top_01.xdc ├── python ├── ddrtests.py ├── exp_gpio.py ├── mem.py ├── memdump.py └── mon_gpio.py ├── simulation_modules ├── simul_axi_fifo_out.v ├── simul_axi_master_rdaddr.v ├── simul_axi_master_wdata.v ├── simul_axi_master_wraddr.v ├── simul_axi_read.v ├── simul_axi_slow_ready.v └── simul_fifo.v ├── unisims_patches └── OSERDESE1.diff ├── util_modules ├── dly01_16.v ├── fifo_cross_clocks.v └── fifo_same_clock.v └── wrap ├── dci_reset.v ├── idelay_ctrl.v ├── idelay_fine_pipe.v ├── idelay_nofine.v ├── iserdes_mem.v ├── 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