├── quartus └── WAV_AUDIO_PLAYER_pdm_sdhc │ ├── rtl │ ├── fifo.qip │ ├── pll.qip │ ├── PLL │ │ ├── SD_fifo.qip │ │ ├── greybox_tmp │ │ │ └── cbx_args.txt │ │ ├── pll.qip │ │ ├── pll.ppf │ │ ├── pll_bb.v │ │ └── pll.v │ ├── IIS_ip │ │ ├── WM8731_IIS │ │ │ ├── fifo.qip │ │ │ ├── IIS_driver_top.v │ │ │ ├── IIS_driver_top.v.bak │ │ │ ├── fifo_bb.v │ │ │ └── fifo.v │ │ └── WM8731_init │ │ │ ├── SPI_INIT │ │ │ ├── device_init.v │ │ │ ├── SPI_send.v │ │ │ ├── device_init_reg.v │ │ │ └── device_init_reg.v.bak │ │ │ ├── WM8731_reg.v │ │ │ ├── WM8731_reg.v.bak │ │ │ ├── SCCB_top.v.bak │ │ │ ├── SCCB_send.v │ │ │ └── SCCB_top.v │ ├── wave │ │ ├── xx.png │ │ ├── 卡顿.png │ │ ├── 卡顿2.png │ │ ├── 无标题.png │ │ ├── 无标题2.png │ │ ├── 无标题3.png │ │ ├── 无标题4.png │ │ └── 无标题5.png │ ├── SDCard_ip │ │ ├── SD_fifo.qip │ │ ├── SD_read.v.bak │ │ ├── SD_fifo_bb.v │ │ ├── SD_fifo.v │ │ ├── SD_read.v │ │ ├── SD_initial.v.bak │ │ └── SD_initial.v │ ├── greybox_tmp │ │ └── cbx_args.txt │ └── WAV_PLAYER.v │ ├── WAV_PLAYER.qws │ ├── PLLJ_PLLSPE_INFO.txt │ ├── WAV_PLAYER.qpf │ ├── WAV_PLAYER.ipregen.rpt │ ├── SD_read.bsf │ └── WAV_PLAYER.qsf ├── sdm.png ├── run_iverilog.bat ├── README.md ├── tb_delta_sigma_adc.v ├── wave.gtkw ├── delta_sigma_adc.v └── pdm_audio.v /quartus/WAV_AUDIO_PLAYER_pdm_sdhc/rtl/fifo.qip: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /quartus/WAV_AUDIO_PLAYER_pdm_sdhc/rtl/pll.qip: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /quartus/WAV_AUDIO_PLAYER_pdm_sdhc/rtl/PLL/SD_fifo.qip: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /quartus/WAV_AUDIO_PLAYER_pdm_sdhc/rtl/IIS_ip/WM8731_IIS/fifo.qip: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /sdm.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Elrori/Delta-sigma-ADC-verilog/HEAD/sdm.png -------------------------------------------------------------------------------- /run_iverilog.bat: -------------------------------------------------------------------------------- 1 | iverilog.exe -y. -o tb_delta_sigma_adc.vvp .\tb_delta_sigma_adc.v 2 | vvp .\tb_delta_sigma_adc.vvp 3 | gtkwave.exe .\wave.gtkw -------------------------------------------------------------------------------- /quartus/WAV_AUDIO_PLAYER_pdm_sdhc/WAV_PLAYER.qws: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Elrori/Delta-sigma-ADC-verilog/HEAD/quartus/WAV_AUDIO_PLAYER_pdm_sdhc/WAV_PLAYER.qws -------------------------------------------------------------------------------- /quartus/WAV_AUDIO_PLAYER_pdm_sdhc/rtl/wave/xx.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Elrori/Delta-sigma-ADC-verilog/HEAD/quartus/WAV_AUDIO_PLAYER_pdm_sdhc/rtl/wave/xx.png -------------------------------------------------------------------------------- /quartus/WAV_AUDIO_PLAYER_pdm_sdhc/rtl/wave/卡顿.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Elrori/Delta-sigma-ADC-verilog/HEAD/quartus/WAV_AUDIO_PLAYER_pdm_sdhc/rtl/wave/卡顿.png -------------------------------------------------------------------------------- /quartus/WAV_AUDIO_PLAYER_pdm_sdhc/rtl/wave/卡顿2.png: -------------------------------------------------------------------------------- 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-------------------------------------------------------------------------------- 1 | # Delta-sigma ADC,PDM audio FPGA Implementation 2 | https://www.jianshu.com/p/f5e17ee2fd25 3 | ![Image](https://github.com/Elrori/Delta-sigma-ADC-verilog/blob/master/sdm.png) 4 | 5 | -------------------------------------------------------------------------------- /quartus/WAV_AUDIO_PLAYER_pdm_sdhc/PLLJ_PLLSPE_INFO.txt: -------------------------------------------------------------------------------- 1 | PLL_Name pll:pll_U1|altpll:altpll_component|pll_altpll:auto_generated|pll1 2 | PLLJITTER 30 3 | PLLSPEmax 84 4 | PLLSPEmin -53 5 | 6 | -------------------------------------------------------------------------------- /quartus/WAV_AUDIO_PLAYER_pdm_sdhc/rtl/SDCard_ip/SD_fifo.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "FIFO" 2 | set_global_assignment -name IP_TOOL_VERSION "17.1" 3 | set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}" 4 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "SD_fifo.v"] 5 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "SD_fifo_bb.v"] 6 | -------------------------------------------------------------------------------- /quartus/WAV_AUDIO_PLAYER_pdm_sdhc/rtl/PLL/greybox_tmp/cbx_args.txt: -------------------------------------------------------------------------------- 1 | INTENDED_DEVICE_FAMILY="Cyclone IV E" 2 | LPM_NUMWORDS=512 3 | LPM_SHOWAHEAD=ON 4 | LPM_TYPE=dcfifo 5 | LPM_WIDTH=32 6 | LPM_WIDTHU=9 7 | OVERFLOW_CHECKING=ON 8 | RDSYNC_DELAYPIPE=4 9 | UNDERFLOW_CHECKING=ON 10 | USE_EAB=ON 11 | WRSYNC_DELAYPIPE=4 12 | DEVICE_FAMILY="Cyclone IV E" 13 | data 14 | rdclk 15 | rdreq 16 | wrclk 17 | wrreq 18 | q 19 | rdempty 20 | wrusedw 21 | -------------------------------------------------------------------------------- /quartus/WAV_AUDIO_PLAYER_pdm_sdhc/rtl/PLL/pll.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "ALTPLL" 2 | set_global_assignment -name IP_TOOL_VERSION "17.1" 3 | set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}" 4 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "pll.v"] 5 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll_bb.v"] 6 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.ppf"] 7 | -------------------------------------------------------------------------------- /quartus/WAV_AUDIO_PLAYER_pdm_sdhc/rtl/PLL/pll.ppf: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | -------------------------------------------------------------------------------- /quartus/WAV_AUDIO_PLAYER_pdm_sdhc/rtl/SDCard_ip/SD_read.v.bak: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * Name : Stream SD_read 3 | * Origin : 171015 4 | * Important: SD_fifo 小于一半时读SD CARD 512 Bytes（128字）到SD_fifo 5 | * 另一边，控制器根据IIS_fifo 写允许，将数据从SD_fifo搬到IIS_fifo 6 | * Author : Helrori 7 | ******************************************************************************/ 8 | module SD_read// 9 | ( 10 | input SD_CLK_REF, 11 | input rst_n, 12 | //Ctrl port 13 | input SD_read_EN,//总开关 14 | input [31:0]Read_Sec_Addr, 15 | input [23:0]Read_Sec_Number, 16 | //SD Card Interface 17 | input SD_MISO, 18 | output reg SD_CS, 19 | output reg SD_MOSI, 20 | output SD_SCLK, 21 | 22 | //Read data port 23 | input FIFO_RD_CLK, 24 | input FIFO_RD_EN, 25 | output reg [31:0]SD_CARD_DAT//{L:R} 26 | ); 27 | SD_fifo SD_fifo_U1( 28 | .data(), 29 | .rdclk(FIFO_RD_CLK), 30 | .rdreq(FIFO_RD_EN), 31 | .wrclk(), 32 | .wrreq(), 33 | .q(SD_CARD_DAT), 34 | .rdempty(), 35 | .wrusedw() 36 | ); 37 | 38 | endmodule 39 | -------------------------------------------------------------------------------- /tb_delta_sigma_adc.v: -------------------------------------------------------------------------------- 1 | //~ `New testbench 2 | `timescale 1ns / 1ps 3 | 4 | module tb_delta_sigma_adc; 5 | 6 | // delta_sigma_adc Parameters 7 | parameter PERIOD = 10; 8 | parameter W = 16; 9 | parameter N = 1024;//量化位数 10 | 11 | // delta_sigma_adc Inputs 12 | reg clk = 0 ; 13 | reg rst_n = 0 ; 14 | reg signed [W-1:0] din = -32768 ; 15 | 16 | // delta_sigma_adc Outputs 17 | wire dout ; 18 | initial 19 | begin 20 | forever #(PERIOD/2) clk=~clk; 21 | end 22 | reg [31:0]cnt=0; 23 | always@(posedge clk)begin 24 | 25 | if(cnt == N-1) 26 | cnt <= 'd0; 27 | else 28 | cnt <= cnt + 1; 29 | if(cnt == N-1) 30 | din <= din + 1000; 31 | end 32 | delta_sigma_adc #( 33 | .W ( W )) 34 | u_delta_sigma_adc ( 35 | .clk ( clk ), 36 | .rst_n ( rst_n ), 37 | .din ( din [W-1:0] ), 38 | 39 | .dout ( dout ) 40 | ); 41 | initial 42 | begin 43 | $dumpfile("wave.vcd"); 44 | $dumpvars(0,tb_delta_sigma_adc); 45 | #(PERIOD*2) rst_n = 1; 46 | #(PERIOD*N*80)//65536 47 | $finish; 48 | end 49 | 50 | endmodule 51 | -------------------------------------------------------------------------------- /quartus/WAV_AUDIO_PLAYER_pdm_sdhc/rtl/IIS_ip/WM8731_init/SPI_INIT/device_init.v: -------------------------------------------------------------------------------- 1 | /*************************************************** 2 | * Name: WM8731 init 3 | * Origin: 171003 4 | * Author: Helrori 5 | * Important: 6 | USE SPI Mode to init device,so we should 7 | set pin: mode to High.wm8731 master dsp mode 8 | ****************************************************/ 9 | module device_init 10 | ( 11 | input clk_50M, //50M 12 | input rst_n, //触发一次初始化 13 | input init_device,//not use 14 | 15 | output CSB, 16 | output SCLK, 17 | output SDIN, 18 | output reg ALL_DONE 19 | ); 20 | wire [15:0]DATA; 21 | reg [3:0]addr; 22 | wire DONE; 23 | reg ENABLE; 24 | always@(posedge DONE or negedge rst_n) 25 | begin 26 | if(!rst_n) 27 | begin 28 | addr<=4'd0; 29 | ALL_DONE <= 0; 30 | ENABLE <= 1; 31 | end 32 | else if(addr == 11-1) 33 | begin 34 | ALL_DONE <= 1; 35 | ENABLE <= 0; 36 | addr<=4'd0; 37 | end 38 | else 39 | addr<=addr + 4'd1; 40 | end 41 | SPI_send SPI_send_U1 42 | ( 43 | .clk_50M(clk_50M), //50M 44 | .rst_n(rst_n), 45 | .ENABLE(ENABLE), 46 | .DATA(DATA), 47 | 48 | .CSB(CSB), 49 | .SCLK(SCLK), 50 | .SDIN(SDIN), 51 | .DONE(DONE) 52 | ); 53 | device_init_reg device_init_reg_U1 54 | ( 55 | .addr(addr), 56 | .DATA(DATA) 57 | ); 58 | endmodule 59 | -------------------------------------------------------------------------------- /quartus/WAV_AUDIO_PLAYER_pdm_sdhc/rtl/IIS_ip/WM8731_init/SPI_INIT/SPI_send.v: -------------------------------------------------------------------------------- 1 | /*************************************************** 2 | * Name : SPI_send 3 | * Origin : 171003 4 | * Important : Only for wm8731 5 | * Author : Helrori 6 | ****************************************************/ 7 | module SPI_send 8 | ( 9 | input clk_50M, //50M 10 | input rst_n, 11 | input ENABLE, 12 | input [15:0]DATA, 13 | 14 | output reg CSB, 15 | output SCLK, 16 | output SDIN, 17 | output DONE 18 | ); 19 | reg [12:0]Divide_Cnt; 20 | reg [3:0]Sel_Cnt; 21 | reg clk_10K; 22 | assign SCLK = (ENABLE)?clk_10K:0; 23 | assign SDIN = (ENABLE)?DATA[~Sel_Cnt]:0; 24 | assign DONE = CSB; 25 | always@(posedge clk_50M or negedge rst_n) 26 | begin 27 | if(!rst_n) 28 | CSB <= 1; 29 | else if(Sel_Cnt == 15 && ENABLE) 30 | CSB <= 0; 31 | else 32 | CSB <= 1; 33 | end 34 | always@(posedge clk_50M or negedge rst_n) 35 | begin 36 | if(!rst_n) 37 | Divide_Cnt <= 13'd0; 38 | else if(Divide_Cnt > 5000/2-1 && ENABLE)//10k 39 | begin 40 | Divide_Cnt <= 13'd0; 41 | clk_10K <= ~clk_10K; 42 | end 43 | else if(ENABLE) 44 | Divide_Cnt <= Divide_Cnt + 13'd1; 45 | end 46 | always@(negedge clk_10K or negedge rst_n) 47 | begin 48 | if(!rst_n) 49 | Sel_Cnt <= 4'd0; 50 | else 51 | Sel_Cnt <= Sel_Cnt + 4'd1; 52 | end 53 | 54 | endmodule 55 | -------------------------------------------------------------------------------- /wave.gtkw: -------------------------------------------------------------------------------- 1 | [*] 2 | [*] GTKWave Analyzer v3.3.71 (w)1999-2016 BSI 3 | [*] Sun Aug 11 12:37:57 2019 4 | [*] 5 | [dumpfile] "G:\VIVADO_WORK_SPACE\Delta-sigma-ADC\wave.vcd" 6 | [dumpfile_mtime] "Sun Aug 11 12:36:21 2019" 7 | [dumpfile_size] 1350347 8 | [savefile] "G:\VIVADO_WORK_SPACE\Delta-sigma-ADC\wave.gtkw" 9 | [timestart] 45738900 10 | [size] 1920 1001 11 | [pos] -1 -1 12 | *-16.000000 46071800 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 13 | [treeopen] tb_delta_sigma_adc. 14 | [sst_width] 239 15 | [signals_width] 180 16 | [sst_expanded] 1 17 | [sst_vpaned_height] 287 18 | @28 19 | tb_delta_sigma_adc.u_delta_sigma_adc.clk 20 | @24 21 | tb_delta_sigma_adc.cnt[31:0] 22 | @28 23 | tb_delta_sigma_adc.u_delta_sigma_adc.rst_n 24 | @420 25 | tb_delta_sigma_adc.u_delta_sigma_adc.adc1b_out[15:0] 26 | [color] 2 27 | tb_delta_sigma_adc.u_delta_sigma_adc.inte0[31:0] 28 | [color] 2 29 | tb_delta_sigma_adc.u_delta_sigma_adc.diff0[31:0] 30 | [color] 2 31 | tb_delta_sigma_adc.u_delta_sigma_adc.rd0[31:0] 32 | [color] 6 33 | tb_delta_sigma_adc.u_delta_sigma_adc.inte1[31:0] 34 | [color] 6 35 | tb_delta_sigma_adc.u_delta_sigma_adc.diff1[31:0] 36 | [color] 6 37 | tb_delta_sigma_adc.u_delta_sigma_adc.rd1[31:0] 38 | @28 39 | tb_delta_sigma_adc.u_delta_sigma_adc.comp 40 | @8421 41 | tb_delta_sigma_adc.u_delta_sigma_adc.din[15:0] 42 | @28 43 | tb_delta_sigma_adc.u_delta_sigma_adc.dout 44 | [pattern_trace] 1 45 | [pattern_trace] 0 46 | -------------------------------------------------------------------------------- /quartus/WAV_AUDIO_PLAYER_pdm_sdhc/WAV_PLAYER.qpf: -------------------------------------------------------------------------------- 1 | # -------------------------------------------------------------------------- # 2 | # 3 | # Copyright (C) 1991-2013 Altera Corporation 4 | # Your use of Altera Corporation's design tools, logic functions 5 | # and other software and tools, and its AMPP partner logic 6 | # functions, and any output files from any of the foregoing 7 | # (including device programming or simulation files), and any 8 | # associated documentation or information are expressly subject 9 | # to the terms and conditions of the Altera Program License 10 | # Subscription Agreement, Altera MegaCore Function License 11 | # Agreement, or other applicable license agreement, including, 12 | # without limitation, that your use is for the sole purpose of 13 | # programming logic devices manufactured by Altera and sold by 14 | # Altera or its authorized distributors. Please refer to the 15 | # applicable agreement for further details. 16 | # 17 | # -------------------------------------------------------------------------- # 18 | # 19 | # Quartus II 64-Bit 20 | # Version 13.1.0 Build 162 10/23/2013 SJ Full Version 21 | # Date created = 18:39:19 October 15, 2017 22 | # 23 | # -------------------------------------------------------------------------- # 24 | 25 | QUARTUS_VERSION = "13.1" 26 | DATE = "18:39:19 October 15, 2017" 27 | 28 | # Revisions 29 | 30 | PROJECT_REVISION = "WAV_PLAYER" 31 | -------------------------------------------------------------------------------- /quartus/WAV_AUDIO_PLAYER_pdm_sdhc/rtl/greybox_tmp/cbx_args.txt: -------------------------------------------------------------------------------- 1 | BANDWIDTH_TYPE=AUTO 2 | CLK0_DIVIDE_BY=1 3 | CLK0_DUTY_CYCLE=50 4 | CLK0_MULTIPLY_BY=1 5 | CLK0_PHASE_SHIFT=0 6 | COMPENSATE_CLOCK=CLK0 7 | INCLK0_INPUT_FREQUENCY=20000 8 | INTENDED_DEVICE_FAMILY="Cyclone IV E" 9 | LPM_TYPE=altpll 10 | OPERATION_MODE=NORMAL 11 | PLL_TYPE=AUTO 12 | PORT_ACTIVECLOCK=PORT_UNUSED 13 | PORT_ARESET=PORT_USED 14 | PORT_CLKBAD0=PORT_UNUSED 15 | PORT_CLKBAD1=PORT_UNUSED 16 | PORT_CLKLOSS=PORT_UNUSED 17 | PORT_CLKSWITCH=PORT_UNUSED 18 | PORT_CONFIGUPDATE=PORT_UNUSED 19 | PORT_FBIN=PORT_UNUSED 20 | PORT_INCLK0=PORT_USED 21 | PORT_INCLK1=PORT_UNUSED 22 | PORT_LOCKED=PORT_USED 23 | PORT_PFDENA=PORT_UNUSED 24 | PORT_PHASECOUNTERSELECT=PORT_UNUSED 25 | PORT_PHASEDONE=PORT_UNUSED 26 | PORT_PHASESTEP=PORT_UNUSED 27 | PORT_PHASEUPDOWN=PORT_UNUSED 28 | PORT_PLLENA=PORT_UNUSED 29 | PORT_SCANACLR=PORT_UNUSED 30 | PORT_SCANCLK=PORT_UNUSED 31 | PORT_SCANCLKENA=PORT_UNUSED 32 | PORT_SCANDATA=PORT_UNUSED 33 | PORT_SCANDATAOUT=PORT_UNUSED 34 | PORT_SCANDONE=PORT_UNUSED 35 | PORT_SCANREAD=PORT_UNUSED 36 | PORT_SCANWRITE=PORT_UNUSED 37 | PORT_clk0=PORT_USED 38 | PORT_clk1=PORT_UNUSED 39 | PORT_clk2=PORT_UNUSED 40 | PORT_clk3=PORT_UNUSED 41 | PORT_clk4=PORT_UNUSED 42 | PORT_clk5=PORT_UNUSED 43 | PORT_clkena0=PORT_UNUSED 44 | PORT_clkena1=PORT_UNUSED 45 | PORT_clkena2=PORT_UNUSED 46 | PORT_clkena3=PORT_UNUSED 47 | PORT_clkena4=PORT_UNUSED 48 | PORT_clkena5=PORT_UNUSED 49 | PORT_extclk0=PORT_UNUSED 50 | PORT_extclk1=PORT_UNUSED 51 | PORT_extclk2=PORT_UNUSED 52 | PORT_extclk3=PORT_UNUSED 53 | SELF_RESET_ON_LOSS_LOCK=OFF 54 | WIDTH_CLOCK=5 55 | DEVICE_FAMILY="Cyclone IV E" 56 | CBX_AUTO_BLACKBOX=ALL 57 | areset 58 | inclk 59 | inclk 60 | clk 61 | locked 62 | -------------------------------------------------------------------------------- /delta_sigma_adc.v: -------------------------------------------------------------------------------- 1 | /************************************************************************************ 2 | * Name :Delta sigma ADC 3 | * Description :2阶Delta sigma ADC,Generate PDM audio,din的采样率 应该比clk慢N倍, 4 | * N量化位数,N=32,64,128,256...,32bit以上时人耳听不出区别 5 | * Interface :N/A 6 | * Origin :190811 7 | * Author :helrori2011@gmail.com 8 | * Reference :https://www.cnblogs.com/sci-dev/p/10428042.html 9 | ************************************************************************************/ 10 | module delta_sigma_adc 11 | #( 12 | parameter W = 16//输入位宽 13 | ) 14 | ( 15 | input wire clk , 16 | input wire rst_n , 17 | 18 | input wire signed [W-1:0] din ,//signed analog signal 19 | output reg dout //PDM signal 20 | ); 21 | wire signed [W-1:0]adc1b_max = {1'b0,{(W-1){1'b1}}}; 22 | wire signed [W-1:0]adc1b_min = {1'b1,{(W-1){1'b0}}}; 23 | wire signed [W-1:0]adc1b_out = (dout == 1'b1)?adc1b_max: 24 | (dout == 1'b0)?adc1b_min: 25 | 'bx; 26 | reg signed [W*2-1:0]inte0,inte1; 27 | wire signed [W*2-1:0]diff0 = din - adc1b_out; 28 | wire signed [W*2-1:0]rd0 = diff0 + inte0; 29 | wire signed [W*2-1:0]diff1 = rd0 - adc1b_out; 30 | wire signed [W*2-1:0]rd1 = diff1 + inte1; 31 | wire comp = (rd1 > 0)?1'b1:1'b0; 32 | always@(posedge clk or negedge rst_n)begin 33 | if ( !rst_n ) begin 34 | dout <= 1'b0; 35 | inte0 <= 'b0; 36 | inte1 <= 'b0; 37 | end else begin 38 | dout <= comp; 39 | inte0 <= rd0; 40 | inte1 <= rd1; 41 | end 42 | end 43 | endmodule 44 | 45 | -------------------------------------------------------------------------------- /pdm_audio.v: -------------------------------------------------------------------------------- 1 | /************************************************************************************ 2 | * Name :PDM audio 3 | * Description :当音频采样率为48Khz,并选择量化位数为32时,clk频率=48Khz x 32 = 1.536Mhz 4 | * rdclk频率=48Khz,rddat数据速率与rdclk一样。rdclk可以由clk分频得到。 5 | * Interface :Native FIFO 6 | * Origin :190812 7 | * Author :helrori2011@gmail.com 8 | * Reference : 9 | ************************************************************************************/ 10 | module pdm_audio 11 | ( 12 | input wire clk ,// FREQ 13 | input wire rst_n , 14 | // connect to FIFO 15 | input wire rdaccess,// The FIFO data is ready,FIFO not empty 16 | input wire rdclk ,// FREQ/32=48Khz 17 | output reg rden , 18 | input wire [31:0] rddat ,// {L[31:16],R[15:0]},signed 19 | // microphone 20 | output wire pdm_r , 21 | output wire pdm_l 22 | ); 23 | reg [1:0]bf0; 24 | wire rdaccess_b = bf0[1]; 25 | always@(posedge rdclk or negedge rst_n)begin if(!rst_n)bf0<='b0;else bf0<={bf0,rdaccess};end 26 | always@(posedge rdclk or negedge rst_n)begin 27 | if ( !rst_n ) begin 28 | rden<=1'd0; 29 | end else begin 30 | if(rdaccess_b) 31 | rden<=1'd1; 32 | end 33 | end 34 | delta_sigma_adc #(.W ( 16 )) 35 | delta_sigma_adc_r ( 36 | .clk ( clk ), 37 | .rst_n ( rst_n ), 38 | .din ( rddat [15:0] ), 39 | .dout ( pdm_r ) 40 | ); 41 | delta_sigma_adc #(.W ( 16 )) 42 | delta_sigma_adc_l ( 43 | .clk ( clk ), 44 | .rst_n ( rst_n ), 45 | .din ( rddat [31:16] ), 46 | .dout ( pdm_l ) 47 | ); 48 | endmodule 49 | 50 | -------------------------------------------------------------------------------- /quartus/WAV_AUDIO_PLAYER_pdm_sdhc/rtl/IIS_ip/WM8731_init/WM8731_reg.v: -------------------------------------------------------------------------------- 1 | module WM8731_reg 2 | ( 3 | input clk, 4 | input [7:0] addr, 5 | output reg [7:0] reg_addr, 6 | output reg [7:0] value 7 | ); 8 | wire [15:0] rom[10:0]; 9 | always @(posedge clk) begin 10 | {reg_addr, value} = rom[addr]; 11 | end 12 | 13 | //--------------------------------------------------------------------------- 14 | // Paratameters 15 | //--------------------------------------------------------------------------- 16 | 17 | //Default volume (0dB), disable mute, disable simultaneous loading 18 | parameter LEFT_LINE_IN = 9'b000010111; //addr (00h) 19 | parameter RIGHT_LINE_IN = 9'b000010111; //addr (01h) 20 | 21 | //Default volume (0dB), No zero cross detection, disable simultaneous loading 22 | parameter LEFT_HEAD_OUT = 9'b001010001; //addr (02h) 23 | parameter RIGHT_HEAD_OUT = 9'b001010001; //addr (03h) 24 | 25 | // analog audio path control 26 | // bit 0: micboost disabled 27 | // bit 1: mute mic disabled 28 | // bit 2: INSEL (1: Mic in 0: Line in) line in selected. 29 | // bit 3: BYPASS disabled 30 | // bit 4: DACSEL (1: select, 0: Dont select) 31 | // bit 5: SIDETONE disabled 32 | // bit [7:6] sidetone antenuation 00 33 | parameter ANALOGUE_AUDIO_PATH_CONTROL = 9'b000010000; //addr (04h) 34 | 35 | // digital audio path control 36 | // bit 0: ADC High Pass Filter Enable (1: disable 0: enable) 37 | // bit[2:1]: De-emphasis Control 38 | // 11 = 48kHz 39 | // 10 = 44.1 kHz 40 | // 01 = 32kHz 41 | // 00 = Disable 42 | // bit3: DAC soft mute (1: enable, 0: disable) 43 | // bit4: Store dc offset when High pass Filter disabled (1: store, 0: clear offset) 44 | parameter DIGITAL_AUDIO_PATH_CONTROL = 9'b000000001; //addr (05h) 45 | 46 | // all power saving features are turned off. 47 | parameter POWER_DOWN_CONTROL = 9'b000000000; //addr (06h) 48 | 49 | // digital audio interface format 50 | // bit[1:0] DSP mode 11 51 | // bit[3:2] data length select 52 | // 11 = 32 bits 53 | // 10 = 24 bits 54 | // 01 = 20 bits 55 | // 00 = 16 bits 56 | // bit [4] select DSP mode A/B 57 | // 1: MSB on 2nd BCLK rising edge after DACLRC rising edge 58 | // 0: MSB on 1st " " 59 | // bit [5] Left Right Swap (1:enable 0: disable) 60 | // bit [6] Master/Slave (1:master, 0:slave) 61 | // bit [7] BCLK invert (1: invert, 0: don't) 62 | parameter DIGITAL_AUDIO_INTERFACE = 9'b001010011; //addr (07h)9'b001010011; 63 | 64 | // Normal mode 256fs No clock dividing 65 | // bit [0] 1=USB;0=Normal 66 | // bit [1] BOSR 67 | // bit [5:2] SR[3:0] 68 | parameter SAMPLING_CONTROL = 9'b000000000; //addr (08h) 69 | 70 | //bit [0]: activate interface (1: active, 0: inactive) 71 | parameter ACTIVE_CONTROL = 9'b000000001; //addr (09h) 72 | 73 | //writing all zeros resets the device. 74 | parameter RESET_ZEROS = 9'b000000000; //addr (0Fh) 75 | 76 | assign rom[0] = {7'h0F,RESET_ZEROS }; 77 | assign rom[1] = {7'h00,LEFT_LINE_IN }; 78 | assign rom[2] = {7'h01,RIGHT_LINE_IN }; 79 | assign rom[3] = {7'h02,LEFT_HEAD_OUT }; 80 | assign rom[4] = {7'h03,RIGHT_HEAD_OUT }; 81 | assign rom[5] = {7'h04,ANALOGUE_AUDIO_PATH_CONTROL }; 82 | assign rom[6] = {7'h05,DIGITAL_AUDIO_PATH_CONTROL }; 83 | assign rom[7] = {7'h06,POWER_DOWN_CONTROL }; 84 | assign rom[8] = {7'h07,DIGITAL_AUDIO_INTERFACE }; 85 | assign rom[9] = {7'h08,SAMPLING_CONTROL }; 86 | assign rom[10] = {7'h09,ACTIVE_CONTROL }; 87 | 88 | 89 | 90 | endmodule 91 | -------------------------------------------------------------------------------- /quartus/WAV_AUDIO_PLAYER_pdm_sdhc/rtl/IIS_ip/WM8731_init/WM8731_reg.v.bak: -------------------------------------------------------------------------------- 1 | module ov2640_reg 2 | ( 3 | input clk, 4 | input [7:0] addr, 5 | output reg [7:0] reg_addr, 6 | output reg [7:0] value 7 | ); 8 | wire [15:0] rom[10:0]; 9 | always @(posedge clk) begin 10 | {reg_addr, value} = rom[addr]; 11 | end 12 | 13 | //--------------------------------------------------------------------------- 14 | // Paratameters 15 | //--------------------------------------------------------------------------- 16 | 17 | //Default volume (0dB), disable mute, disable simultaneous loading 18 | parameter LEFT_LINE_IN = 9'b000010111; //addr (00h) 19 | parameter RIGHT_LINE_IN = 9'b000010111; //addr (01h) 20 | 21 | //Default volume (0dB), No zero cross detection, disable simultaneous loading 22 | parameter LEFT_HEAD_OUT = 9'b001111001; //addr (02h) 23 | parameter RIGHT_HEAD_OUT = 9'b001111001; //addr (03h) 24 | 25 | // analog audio path control 26 | // bit 0: micboost disabled 27 | // bit 1: mute mic disabled 28 | // bit 2: INSEL (1: Mic in 0: Line in) line in selected. 29 | // bit 3: BYPASS disabled 30 | // bit 4: DACSEL (1: select, 0: Dont select) 31 | // bit 5: SIDETONE disabled 32 | // bit [7:6] sidetone antenuation 00 33 | parameter ANALOGUE_AUDIO_PATH_CONTROL = 9'b000010000; //addr (04h) 34 | 35 | // digital audio path control 36 | // bit 0: ADC High Pass Filter Enable (1: disable 0: enable) 37 | // bit[2:1]: De-emphasis Control 38 | // 11 = 48kHz 39 | // 10 = 44.1 kHz 40 | // 01 = 32kHz 41 | // 00 = Disable 42 | // bit3: DAC soft mute (1: enable, 0: disable) 43 | // bit4: Store dc offset when High pass Filter disabled (1: store, 0: clear offset) 44 | parameter DIGITAL_AUDIO_PATH_CONTROL = 9'b000000001; //addr (05h) 45 | 46 | // all power saving features are turned off. 47 | parameter POWER_DOWN_CONTROL = 9'b000000000; //addr (06h) 48 | 49 | // digital audio interface format 50 | // bit[1:0] DSP mode 11 51 | // bit[3:2] data length select 52 | // 11 = 32 bits 53 | // 10 = 24 bits 54 | // 01 = 20 bits 55 | // 00 = 16 bits 56 | // bit [4] select DSP mode A/B 57 | // 1: MSB on 2nd BCLK rising edge after DACLRC rising edge 58 | // 0: MSB on 1st " " 59 | // bit [5] Left Right Swap (1:enable 0: disable) 60 | // bit [6] Master/Slave (1:master, 0:slave) 61 | // bit [7] BCLK invert (1: invert, 0: don't) 62 | parameter DIGITAL_AUDIO_INTERFACE = 9'b001010011; //addr (07h)9'b001010011; 63 | 64 | // Normal mode 256fs No clock dividing 65 | // bit [0] 1=USB;0=Normal 66 | // bit [1] BOSR 67 | // bit [5:2] SR[3:0] 68 | parameter SAMPLING_CONTROL = 9'b000000001; //addr (08h) 69 | 70 | //bit [0]: activate interface (1: active, 0: inactive) 71 | parameter ACTIVE_CONTROL = 9'b000000001; //addr (09h) 72 | 73 | //writing all zeros resets the device. 74 | parameter RESET_ZEROS = 9'b000000000; //addr (0Fh) 75 | 76 | assign rom[0] = {7'h0F,RESET_ZEROS }; 77 | assign rom[1] = {7'h00,LEFT_LINE_IN }; 78 | assign rom[2] = {7'h01,RIGHT_LINE_IN }; 79 | assign rom[3] = {7'h02,LEFT_HEAD_OUT }; 80 | assign rom[4] = {7'h03,RIGHT_HEAD_OUT }; 81 | assign rom[5] = {7'h04,ANALOGUE_AUDIO_PATH_CONTROL }; 82 | assign rom[6] = {7'h05,DIGITAL_AUDIO_PATH_CONTROL }; 83 | assign rom[7] = {7'h06,POWER_DOWN_CONTROL }; 84 | assign rom[8] = {7'h07,DIGITAL_AUDIO_INTERFACE }; 85 | assign rom[9] = {7'h08,SAMPLING_CONTROL }; 86 | assign rom[10] = {7'h09,ACTIVE_CONTROL }; 87 | 88 | 89 | 90 | endmodule -------------------------------------------------------------------------------- /quartus/WAV_AUDIO_PLAYER_pdm_sdhc/rtl/IIS_ip/WM8731_init/SPI_INIT/device_init_reg.v: -------------------------------------------------------------------------------- 1 | /*************************************************** 2 | * Name: WM8731 reg map 3 | * Origin: 171003 4 | * Author: Helrori 5 | ****************************************************/ 6 | module device_init_reg 7 | ( 8 | // input clk, 9 | input [7:0] addr, 10 | output [15:0]DATA 11 | ); 12 | wire [15:0] rom[10:0]; 13 | // always @(posedge clk) begin 14 | assign DATA = rom[addr]; 15 | // end 16 | 17 | //--------------------------------------------------------------------------- 18 | // Paratameters 19 | //--------------------------------------------------------------------------- 20 | 21 | //Default volume (0dB), disable mute, disable simultaneous loading 22 | parameter LEFT_LINE_IN = 9'b000010111; //addr (00h) 23 | parameter RIGHT_LINE_IN = 9'b000010111; //addr (01h) 24 | 25 | //Default volume (0dB), No zero cross detection, disable simultaneous loading 26 | parameter LEFT_HEAD_OUT = 9'b000110000; //addr (02h) 27 | parameter RIGHT_HEAD_OUT = 9'b000110000; //addr (03h) 28 | 29 | // analog audio path control 30 | // bit 0: micboost disabled 31 | // bit 1: mute mic disabled 32 | // bit 2: INSEL (1: Mic in 0: Line in) line in selected. 33 | // bit 3: BYPASS disabled 34 | // bit 4: DACSEL (1: select, 0: Dont select) 35 | // bit 5: SIDETONE disabled 36 | // bit [7:6] sidetone antenuation 00 37 | parameter ANALOGUE_AUDIO_PATH_CONTROL = 9'b000010000; //addr (04h) 38 | 39 | // digital audio path control 40 | // bit 0: ADC High Pass Filter Enable (1: disable 0: enable) 41 | // bit[2:1]: De-emphasis Control 42 | // 11 = 48kHz 43 | // 10 = 44.1 kHz 44 | // 01 = 32kHz 45 | // 00 = Disable 46 | // bit3: DAC soft mute (1: enable, 0: disable) 47 | // bit4: Store dc offset when High pass Filter disabled (1: store, 0: clear offset) 48 | parameter DIGITAL_AUDIO_PATH_CONTROL = 9'b000000001; //addr (05h) 49 | 50 | // all power saving features are turned off. 51 | parameter POWER_DOWN_CONTROL = 9'b000000000; //addr (06h) 52 | 53 | // digital audio interface format 54 | // bit[1:0] DSP mode 11 55 | // bit[3:2] data length select 56 | // 11 = 32 bits 57 | // 10 = 24 bits 58 | // 01 = 20 bits 59 | // 00 = 16 bits 60 | // bit [4] select DSP mode A/B 61 | // 1: MSB on 2nd BCLK rising edge after DACLRC rising edge 62 | // 0: MSB on 1st " " 63 | // bit [5] Left Right Swap (1:enable 0: disable) 64 | // bit [6] Master/Slave (1:master, 0:slave) 65 | // bit [7] BCLK invert (1: invert, 0: don't) 66 | parameter DIGITAL_AUDIO_INTERFACE = 9'b001010011; //addr (07h)9'b001010011; 67 | 68 | // Normal mode 256fs No clock dividing 69 | // bit [0] 1=USB;0=Normal 70 | // bit [1] BOSR 71 | // bit [5:2] SR[3:0] 72 | parameter SAMPLING_CONTROL = 9'b000000001; //addr (08h) 73 | 74 | //bit [0]: activate interface (1: active, 0: inactive) 75 | parameter ACTIVE_CONTROL = 9'b000000001; //addr (09h) 76 | 77 | //writing all zeros resets the device. 78 | parameter RESET_ZEROS = 9'b000000000; //addr (0Fh) 79 | 80 | assign rom[0] = {7'h0F,RESET_ZEROS }; 81 | assign rom[1] = {7'h00,LEFT_LINE_IN }; 82 | assign rom[2] = {7'h01,RIGHT_LINE_IN }; 83 | assign rom[3] = {7'h02,LEFT_HEAD_OUT }; 84 | assign rom[4] = {7'h03,RIGHT_HEAD_OUT }; 85 | assign rom[5] = {7'h04,ANALOGUE_AUDIO_PATH_CONTROL }; 86 | assign rom[6] = {7'h05,DIGITAL_AUDIO_PATH_CONTROL }; 87 | assign rom[7] = {7'h06,POWER_DOWN_CONTROL }; 88 | assign rom[8] = {7'h07,DIGITAL_AUDIO_INTERFACE }; 89 | assign rom[9] = {7'h08,SAMPLING_CONTROL }; 90 | assign rom[10] = {7'h09,ACTIVE_CONTROL }; 91 | 92 | 93 | 94 | endmodule -------------------------------------------------------------------------------- /quartus/WAV_AUDIO_PLAYER_pdm_sdhc/rtl/IIS_ip/WM8731_init/SPI_INIT/device_init_reg.v.bak: -------------------------------------------------------------------------------- 1 | /*************************************************** 2 | * Name: WM8731 reg map 3 | * Origin: 171003 4 | * Author: Helrori 5 | ****************************************************/ 6 | module device_init_reg 7 | ( 8 | // input clk, 9 | input [7:0] addr, 10 | output [15:0]DATA 11 | ); 12 | wire [15:0] rom[10:0]; 13 | // always @(posedge clk) begin 14 | assign DATA = rom[addr]; 15 | // end 16 | 17 | //--------------------------------------------------------------------------- 18 | // Paratameters 19 | //--------------------------------------------------------------------------- 20 | 21 | //Default volume (0dB), disable mute, disable simultaneous loading 22 | parameter LEFT_LINE_IN = 9'b000010111; //addr (00h) 23 | parameter RIGHT_LINE_IN = 9'b000010111; //addr (01h) 24 | 25 | //Default volume (0dB), No zero cross detection, disable simultaneous loading 26 | parameter LEFT_HEAD_OUT = 9'b001111001; //addr (02h) 27 | parameter RIGHT_HEAD_OUT = 9'b001111001; //addr (03h) 28 | 29 | // analog audio path control 30 | // bit 0: micboost disabled 31 | // bit 1: mute mic disabled 32 | // bit 2: INSEL (1: Mic in 0: Line in) line in selected. 33 | // bit 3: BYPASS disabled 34 | // bit 4: DACSEL (1: select, 0: Dont select) 35 | // bit 5: SIDETONE disabled 36 | // bit [7:6] sidetone antenuation 00 37 | parameter ANALOGUE_AUDIO_PATH_CONTROL = 9'b000010000; //addr (04h) 38 | 39 | // digital audio path control 40 | // bit 0: ADC High Pass Filter Enable (1: disable 0: enable) 41 | // bit[2:1]: De-emphasis Control 42 | // 11 = 48kHz 43 | // 10 = 44.1 kHz 44 | // 01 = 32kHz 45 | // 00 = Disable 46 | // bit3: DAC soft mute (1: enable, 0: disable) 47 | // bit4: Store dc offset when High pass Filter disabled (1: store, 0: clear offset) 48 | parameter DIGITAL_AUDIO_PATH_CONTROL = 9'b000000001; //addr (05h) 49 | 50 | // all power saving features are turned off. 51 | parameter POWER_DOWN_CONTROL = 9'b000000000; //addr (06h) 52 | 53 | // digital audio interface format 54 | // bit[1:0] DSP mode 11 55 | // bit[3:2] data length select 56 | // 11 = 32 bits 57 | // 10 = 24 bits 58 | // 01 = 20 bits 59 | // 00 = 16 bits 60 | // bit [4] select DSP mode A/B 61 | // 1: MSB on 2nd BCLK rising edge after DACLRC rising edge 62 | // 0: MSB on 1st " " 63 | // bit [5] Left Right Swap (1:enable 0: disable) 64 | // bit [6] Master/Slave (1:master, 0:slave) 65 | // bit [7] BCLK invert (1: invert, 0: don't) 66 | parameter DIGITAL_AUDIO_INTERFACE = 9'b001010011; //addr (07h)9'b001010011; 67 | 68 | // Normal mode 256fs No clock dividing 69 | // bit [0] 1=USB;0=Normal 70 | // bit [1] BOSR 71 | // bit [5:2] SR[3:0] 72 | parameter SAMPLING_CONTROL = 9'b000000001; //addr (08h) 73 | 74 | //bit [0]: activate interface (1: active, 0: inactive) 75 | parameter ACTIVE_CONTROL = 9'b000000001; //addr (09h) 76 | 77 | //writing all zeros resets the device. 78 | parameter RESET_ZEROS = 9'b000000000; //addr (0Fh) 79 | 80 | assign rom[0] = {7'h0F,RESET_ZEROS }; 81 | assign rom[1] = {7'h00,LEFT_LINE_IN }; 82 | assign rom[2] = {7'h01,RIGHT_LINE_IN }; 83 | assign rom[3] = {7'h02,LEFT_HEAD_OUT }; 84 | assign rom[4] = {7'h03,RIGHT_HEAD_OUT }; 85 | assign rom[5] = {7'h04,ANALOGUE_AUDIO_PATH_CONTROL }; 86 | assign rom[6] = {7'h05,DIGITAL_AUDIO_PATH_CONTROL }; 87 | assign rom[7] = {7'h06,POWER_DOWN_CONTROL }; 88 | assign rom[8] = {7'h07,DIGITAL_AUDIO_INTERFACE }; 89 | assign rom[9] = {7'h08,SAMPLING_CONTROL }; 90 | assign rom[10] = {7'h09,ACTIVE_CONTROL }; 91 | 92 | 93 | 94 | endmodule -------------------------------------------------------------------------------- /quartus/WAV_AUDIO_PLAYER_pdm_sdhc/WAV_PLAYER.ipregen.rpt: -------------------------------------------------------------------------------- 1 | IP Upgrade report for WAV_PLAYER 2 | Mon Aug 12 08:52:44 2019 3 | Quartus Prime Version 17.1.0 Build 590 10/25/2017 SJ Standard Edition 4 | 5 | 6 | --------------------- 7 | ; Table of Contents ; 8 | --------------------- 9 | 1. Legal Notice 10 | 2. IP Upgrade Summary 11 | 3. Successfully Upgraded IP Components 12 | 4. IP Upgrade Messages 13 | 14 | 15 | 16 | ---------------- 17 | ; Legal Notice ; 18 | ---------------- 19 | Copyright (C) 2017 Intel Corporation. All rights reserved. 20 | Your use of Intel Corporation's design tools, logic functions 21 | and other software and tools, and its AMPP partner logic 22 | functions, and any output files from any of the foregoing 23 | (including device programming or simulation files), and any 24 | associated documentation or information are expressly subject 25 | to the terms and conditions of the Intel Program License 26 | Subscription Agreement, the Intel Quartus Prime License Agreement, 27 | the Intel FPGA IP License Agreement, or other applicable license 28 | agreement, including, without limitation, that your use is for 29 | the sole purpose of programming logic devices manufactured by 30 | Intel and sold by Intel or its authorized distributors. Please 31 | refer to the applicable agreement for further details. 32 | 33 | 34 | 35 | +--------------------------------------------------------------------------------+ 36 | ; IP Upgrade Summary ; 37 | +------------------------------+-------------------------------------------------+ 38 | ; IP Components Upgrade Status ; Passed - Mon Aug 12 08:52:44 2019 ; 39 | ; Quartus Prime Version ; 17.1.0 Build 590 10/25/2017 SJ Standard Edition ; 40 | ; Revision Name ; WAV_PLAYER ; 41 | ; Top-level Entity Name ; WAV_PLAYER ; 42 | ; Family ; Cyclone IV E ; 43 | +------------------------------+-------------------------------------------------+ 44 | 45 | 46 | +------------------------------------------------------------------------------------------------------------------------------------+ 47 | ; Successfully Upgraded IP Components ; 48 | +-------------+----------------+---------+---------------------------+-------------------------+---------------------------+---------+ 49 | ; Entity Name ; Component Name ; Version ; Original Source File ; Generation File Path ; New Source File ; Message ; 50 | +-------------+----------------+---------+---------------------------+-------------------------+---------------------------+---------+ 51 | ; pll ; ALTPLL ; 16.1 ; rtl/PLL/pll.qip ; rtl/PLL/pll.v ; rtl/PLL/pll.qip ; ; 52 | ; SD_fifo ; FIFO ; 16.1 ; rtl/SDCard_ip/SD_fifo.qip ; rtl/SDCard_ip/SD_fifo.v ; rtl/SDCard_ip/SD_fifo.qip ; ; 53 | +-------------+----------------+---------+---------------------------+-------------------------+---------------------------+---------+ 54 | 55 | 56 | +---------------------+ 57 | ; IP Upgrade Messages ; 58 | +---------------------+ 59 | Info (11902): Backing up file "rtl/PLL/pll.v" to "rtl/PLL/pll.BAK.v" 60 | Info (11837): Started upgrading IP component ALTPLL with file "rtl/PLL/pll.v" 61 | Info (11902): Backing up file "rtl/SDCard_ip/SD_fifo.v" to "rtl/SDCard_ip/SD_fifo.BAK.v" 62 | Info (11837): Started upgrading IP component FIFO with file "rtl/SDCard_ip/SD_fifo.v" 63 | Info (11131): Completed upgrading IP component ALTPLL with file "rtl/PLL/pll.v" 64 | Info (11131): Completed upgrading IP component FIFO with file "rtl/SDCard_ip/SD_fifo.v" 65 | Info (23030): Evaluation of Tcl script d:/quartus_17.1/quartus/common/tcl/internal/ip_regen/ip_regen.tcl was successful 66 | Info: Quartus Prime Shell was successful. 0 errors, 0 warnings 67 | Info: Peak virtual memory: 4884 megabytes 68 | Info: Processing ended: Mon Aug 12 08:52:44 2019 69 | Info: Elapsed time: 00:00:19 70 | Info: Total CPU time (on all processors): 00:00:32 71 | 72 | 73 | -------------------------------------------------------------------------------- /quartus/WAV_AUDIO_PLAYER_pdm_sdhc/SD_read.bsf: -------------------------------------------------------------------------------- 1 | /* 2 | WARNING: Do NOT edit the input and output ports in this file in a text 3 | editor if you plan to continue editing the block that represents it in 4 | the Block Editor! File corruption is VERY likely to occur. 5 | */ 6 | /* 7 | Copyright (C) 1991-2013 Altera Corporation 8 | Your use of Altera Corporation's design tools, logic functions 9 | and other software and tools, and its AMPP partner logic 10 | functions, and any output files from any of the foregoing 11 | (including device programming or simulation files), and any 12 | associated documentation or information are expressly subject 13 | to the terms and conditions of the Altera Program License 14 | Subscription Agreement, Altera MegaCore Function License 15 | Agreement, or other applicable license agreement, including, 16 | without limitation, that your use is for the sole purpose of 17 | programming logic devices manufactured by Altera and sold by 18 | Altera or its authorized distributors. Please refer to the 19 | applicable agreement for further details. 20 | */ 21 | (header "symbol" (version "1.1")) 22 | (symbol 23 | (rect 16 16 328 192) 24 | (text "SD_read" (rect 5 0 41 12)(font "Arial" )) 25 | (text "inst" (rect 8 160 20 172)(font "Arial" )) 26 | (port 27 | (pt 0 32) 28 | (input) 29 | (text "SD_SCLK_REF" (rect 0 0 71 12)(font "Arial" )) 30 | (text "SD_SCLK_REF" (rect 21 27 92 39)(font "Arial" )) 31 | (line (pt 0 32)(pt 16 32)(line_width 1)) 32 | ) 33 | (port 34 | (pt 0 48) 35 | (input) 36 | (text "rst_n" (rect 0 0 21 12)(font "Arial" )) 37 | (text "rst_n" (rect 21 43 42 55)(font "Arial" )) 38 | (line (pt 0 48)(pt 16 48)(line_width 1)) 39 | ) 40 | (port 41 | (pt 0 64) 42 | (input) 43 | (text "SD_Read_EN" (rect 0 0 61 12)(font "Arial" )) 44 | (text "SD_Read_EN" (rect 21 59 82 71)(font "Arial" )) 45 | (line (pt 0 64)(pt 16 64)(line_width 1)) 46 | ) 47 | (port 48 | (pt 0 80) 49 | (input) 50 | (text "Read_Sec_Addr[31..0]" (rect 0 0 94 12)(font "Arial" )) 51 | (text "Read_Sec_Addr[31..0]" (rect 21 75 115 87)(font "Arial" )) 52 | (line (pt 0 80)(pt 16 80)(line_width 3)) 53 | ) 54 | (port 55 | (pt 0 96) 56 | (input) 57 | (text "Read_Sec_Number[23..0]" (rect 0 0 107 12)(font "Arial" )) 58 | (text "Read_Sec_Number[23..0]" (rect 21 91 128 103)(font "Arial" )) 59 | (line (pt 0 96)(pt 16 96)(line_width 3)) 60 | ) 61 | (port 62 | (pt 0 112) 63 | (input) 64 | (text "SD_MISO" (rect 0 0 42 12)(font "Arial" )) 65 | (text "SD_MISO" (rect 21 107 63 119)(font "Arial" )) 66 | (line (pt 0 112)(pt 16 112)(line_width 1)) 67 | ) 68 | (port 69 | (pt 0 128) 70 | (input) 71 | (text "FIFO_RD_CLK" (rect 0 0 68 12)(font "Arial" )) 72 | (text "FIFO_RD_CLK" (rect 21 123 89 135)(font "Arial" )) 73 | (line (pt 0 128)(pt 16 128)(line_width 1)) 74 | ) 75 | (port 76 | (pt 0 144) 77 | (input) 78 | (text "FIFO_RD_EN" (rect 0 0 62 12)(font "Arial" )) 79 | (text "FIFO_RD_EN" (rect 21 139 83 151)(font "Arial" )) 80 | (line (pt 0 144)(pt 16 144)(line_width 1)) 81 | ) 82 | (port 83 | (pt 312 32) 84 | (output) 85 | (text "SD_CS" (rect 0 0 31 12)(font "Arial" )) 86 | (text "SD_CS" (rect 260 27 291 39)(font "Arial" )) 87 | (line (pt 312 32)(pt 296 32)(line_width 1)) 88 | ) 89 | (port 90 | (pt 312 48) 91 | (output) 92 | (text "SD_MOSI" (rect 0 0 42 12)(font "Arial" )) 93 | (text "SD_MOSI" (rect 249 43 291 55)(font "Arial" )) 94 | (line (pt 312 48)(pt 296 48)(line_width 1)) 95 | ) 96 | (port 97 | (pt 312 64) 98 | (output) 99 | (text "SD_SCLK" (rect 0 0 44 12)(font "Arial" )) 100 | (text "SD_SCLK" (rect 247 59 291 71)(font "Arial" )) 101 | (line (pt 312 64)(pt 296 64)(line_width 1)) 102 | ) 103 | (port 104 | (pt 312 80) 105 | (output) 106 | (text "SD_CARD_DAT[31..0]" (rect 0 0 100 12)(font "Arial" )) 107 | (text "SD_CARD_DAT[31..0]" (rect 191 75 291 87)(font "Arial" )) 108 | (line (pt 312 80)(pt 296 80)(line_width 3)) 109 | ) 110 | (port 111 | (pt 312 96) 112 | (output) 113 | (text "error" (rect 0 0 20 12)(font "Arial" )) 114 | (text "error" (rect 271 91 291 103)(font "Arial" )) 115 | (line (pt 312 96)(pt 296 96)(line_width 1)) 116 | ) 117 | (drawing 118 | (rectangle (rect 16 16 296 160)(line_width 1)) 119 | ) 120 | ) 121 | -------------------------------------------------------------------------------- /quartus/WAV_AUDIO_PLAYER_pdm_sdhc/rtl/IIS_ip/WM8731_init/SCCB_top.v.bak: -------------------------------------------------------------------------------- 1 | module SCCB_top 2 | ( 3 | input init_ov, //上升沿或下降沿触发一次OV2640初始化 4 | input clk, //50Mhz 5 | input rst_n, //触发一次OV2640初始化 6 | 7 | output SCL, 8 | output SDA, 9 | output reg OV2640_PWDN, 10 | output reg OV2640_RST, 11 | 12 | output reg init_ov_done 13 | ); 14 | `define DELAY 5//00000 //发送两帧(软复位)后的延时2500000==50ms 15 | `define NUMBER_TO_SEND 10 //发送个数减一 16 | `define TA 50000 //OV_RST硬件复位时间 17 | /********************************************************************************************************************** 18 | * SCCB通信顶层；用于与ov摄像头的通信配置相关寄存器。DELAY为发送两个数据后必要的的延时。NUMBER_TO_SEND为要写配置寄存器的个数减一 19 | * TA 为OV2640_RST硬件复位时间。 20 | * by_helrori_170329 21 | * Interface N/A 22 | ***********************************************************************************************************************/ 23 | SCCB_send SCCB_send 24 | ( 25 | .clk(clk), //50Mhz 26 | .rst_n(rst_n), 27 | .send(send_), 28 | .address(address_), 29 | .value(value_), 30 | 31 | .SCL(SCL), 32 | .SDA(SDA), 33 | 34 | .busy(busy_), 35 | .time_counter() 36 | 37 | ); 38 | wire [7:0]address_,value_; 39 | wire busy_; 40 | reg [7:0]addr_; 41 | reg send_; 42 | WM8731_reg WM8731_reg 43 | ( 44 | .clk(clk), 45 | .addr(addr_), 46 | .reg_addr(address_), 47 | .value(value_) 48 | ); 49 | 50 | reg buff0,buff1,init_ov_buff; 51 | always @(posedge clk) 52 | begin 53 | buff0 <= init_ov; 54 | buff1 <= buff0; 55 | if(buff0^buff1) //posedge or negedge of init_ov 56 | init_ov_buff <= 1'b1; //next clk will set send_buff to 1 57 | else 58 | init_ov_buff <= 1'b0; 59 | end 60 | 61 | reg buff00,buff11,busy_buff; 62 | always @(posedge clk) 63 | begin 64 | buff00 <= busy_; 65 | buff11 <= buff00; 66 | if(buff11&~buff00) //negedge of busy_ 67 | busy_buff <= 1'b1; //next clk will set send_buff to 1 68 | else 69 | busy_buff <= 1'b0; 70 | end 71 | 72 | /************************************************************************************* 73 | *连续 三相写寄存器 状态机 74 | *************************************************************************************/ 75 | reg [31:0]time_counter1; 76 | reg [7:0]byte_counter; 77 | reg [2:0]state,next_state; 78 | parameter WAIT = 3'd1,START = 3'd0,WRITE = 3'd2,DONE = 3'd3,POINT0 = 3'd4,POINT1 = 3'd5,POINT2 = 3'd6; 79 | always @(posedge clk or negedge rst_n) 80 | if(!rst_n) 81 | state <= START; 82 | else 83 | state <= next_state; 84 | 85 | always @(*) 86 | if(!rst_n) 87 | next_state = START; 88 | else if(init_ov_buff) 89 | next_state = START; 90 | else 91 | case(state) 92 | WAIT: next_state = WAIT; 93 | START:begin 94 | if(time_counter1 >= `TA*3)//500000===10ms//50Mhz 95 | next_state = POINT0; 96 | else 97 | next_state = START; 98 | end 99 | POINT0:next_state = WRITE; 100 | WRITE: begin 101 | if(byte_counter >= `NUMBER_TO_SEND) 102 | next_state = DONE; 103 | else if(byte_counter == 1 && busy_buff == 1) 104 | next_state = POINT1; 105 | else 106 | next_state = WRITE; 107 | end 108 | POINT1: begin 109 | if(time_counter1 >= `DELAY) 110 | next_state = POINT2; 111 | else 112 | next_state = POINT1; 113 | end 114 | POINT2:next_state = POINT0; 115 | DONE:next_state = WAIT; 116 | default:next_state = WAIT; 117 | endcase 118 | 119 | always @(posedge clk or negedge rst_n) 120 | if(!rst_n)begin 121 | time_counter1 <= 32'd0 ; 122 | send_ <= 1'b0; 123 | byte_counter <= 1'b0; 124 | init_ov_done <= 1'b0; 125 | OV2640_RST <= 1'b1; 126 | OV2640_PWDN <= 0; 127 | end 128 | else 129 | case(next_state) 130 | WAIT: begin 131 | time_counter1 <= 32'd0 ; 132 | send_ <= 1'b0; 133 | byte_counter <= 1'b0; 134 | end 135 | START:begin 136 | time_counter1 <= time_counter1 + 1'd1; 137 | OV2640_PWDN <= 0; 138 | if(time_counter1 >= `TA && time_counter1 < `TA*2) 139 | OV2640_RST <= 0; 140 | else 141 | OV2640_RST <= 1'b1; 142 | end 143 | POINT0:begin time_counter1 <= 32'd0;send_ <= ~send_;end 144 | WRITE: begin 145 | if(busy_buff)begin 146 | byte_counter <= byte_counter + 8'd1;addr_ <= addr_ + 8'b1;send_ <= ~send_; 147 | end 148 | // if(byte_counter == 2)begin 149 | // send_ <= 1'b1; 150 | // end 151 | end 152 | POINT1: begin 153 | time_counter1 <= time_counter1 + 32'b1; 154 | end 155 | POINT2: begin addr_ <= addr_ + 8'b1;byte_counter <= byte_counter + 8'd1;end 156 | DONE: init_ov_done <= 1'b1; 157 | default:; 158 | endcase 159 | endmodule 160 | -------------------------------------------------------------------------------- /quartus/WAV_AUDIO_PLAYER_pdm_sdhc/rtl/IIS_ip/WM8731_init/SCCB_send.v: -------------------------------------------------------------------------------- 1 | module SCCB_send 2 | ( 3 | input clk, //50Mhz 4 | input rst_n, 5 | input send, //always at posedge or negedge send !! 6 | input [7:0]address, 7 | input [7:0]value, 8 | 9 | output reg SCL, 10 | output reg SDA, 11 | 12 | output reg busy, 13 | // output reg send_buff, 14 | output reg [15:0]time_counter 15 | 16 | ); 17 | /************************************************************************************* 18 | *实现SCCB三相写。即写三个字节，忽略ACK回应。周期100us(10KHZ) 19 | *************************************************************************************/ 20 | parameter [7:0]DEVICE_ID = 8'h34; //器件地址 21 | reg [26:0]DATA_3_BYTE; 22 | reg buff0,buff1, send_buff; 23 | always @(posedge clk) 24 | begin 25 | if(!rst_n)begin 26 | buff0 <= 1'b0; 27 | buff1 <= 1'b0; 28 | end 29 | else begin 30 | buff0 <= send; 31 | buff1 <= buff0; 32 | end 33 | if(buff0^buff1) //posedge or negedge of send 34 | send_buff <= 1'b1; //next clk will set send_buff to 1 35 | else 36 | send_buff <= 1'b0; 37 | end 38 | /************************************************************************************* 39 | *三相写状态机 40 | *************************************************************************************/ 41 | parameter WAIT = 4'd0,START = 4'd1,WRITE_BYTE = 4'd2,ACK = 4'd3,STOP = 4'd4;//,DELAY = 4'd5,; 42 | reg [3:0]state,next_state; 43 | reg [6:0]bit_counter; 44 | reg [3:0]byte_counter; 45 | always @(posedge clk or negedge rst_n) //同步转移 46 | begin 47 | if(!rst_n) 48 | state <= WAIT; 49 | else 50 | state <= next_state; 51 | end 52 | always @(*) //组合逻辑 53 | begin 54 | if(!rst_n) 55 | next_state = WAIT; 56 | else if(send_buff) 57 | next_state = START; 58 | else 59 | case(state) 60 | WAIT: begin 61 | next_state = WAIT; 62 | end 63 | START: begin 64 | if(time_counter >= 1250*4) 65 | begin 66 | next_state = WRITE_BYTE; 67 | end 68 | else 69 | next_state = START; 70 | end 71 | WRITE_BYTE: begin 72 | if(bit_counter >= 27) 73 | next_state = ACK; 74 | else 75 | next_state = WRITE_BYTE; 76 | end 77 | ACK: begin 78 | next_state = STOP; 79 | end 80 | STOP: begin 81 | if(time_counter > 0) 82 | next_state = STOP; 83 | else 84 | next_state = WAIT; 85 | 86 | end 87 | default:next_state = WAIT; 88 | endcase 89 | end 90 | 91 | always @(posedge clk or negedge rst_n) 92 | begin 93 | if(!rst_n) 94 | begin 95 | SCL <= 1'b1; 96 | //SDA_out <= 1'b1; 97 | bit_counter <= 7'b0; 98 | SDA <= 1'b1; 99 | time_counter <= 16'd0; 100 | busy <= 1'b0; 101 | end 102 | else 103 | case(next_state) 104 | WAIT: begin 105 | time_counter <= 16'b0; 106 | SCL <= 1'b1; 107 | //SDA_out <= 1'b1; 108 | SDA <= 1'b1; 109 | //output_en <= 1'b1; 110 | bit_counter <= 7'b0; 111 | busy <= 1'b0; 112 | end 113 | START: begin 114 | DATA_3_BYTE <= {DEVICE_ID,1'b0,address,1'b0,value,1'b0}; //ACK回应期间置0; 115 | time_counter <= time_counter + 1'b1; 116 | busy <= 1'b1; 117 | //output_en <= 1'b1; 118 | if(time_counter >= 1250*2) 119 | begin 120 | //SDA_out <= 1'b0; 121 | SDA <= 1'b0; 122 | if(time_counter >= 1250*3) 123 | SCL <= 1'b0; 124 | else 125 | SCL <= 1'b1; 126 | end 127 | else 128 | //SDA_out <= 1'b1; 129 | SDA <= 1'b1; 130 | end 131 | WRITE_BYTE: begin 132 | time_counter <= time_counter - 1'b1; 133 | //SDA_out <= DATA_3_BYTE[bit_counter]; 134 | SDA <= DATA_3_BYTE[26 - bit_counter]; 135 | if(time_counter == 0)begin 136 | time_counter <= 5000; 137 | bit_counter <= bit_counter + 1'b1; 138 | end 139 | if(time_counter <= 5000-1250 && time_counter >= 5000-1250*3) 140 | SCL <= 1'b1; 141 | else 142 | SCL <= 1'b0; 143 | end 144 | ACK: begin 145 | // time_counter <= time_counter - 1'b1; 146 | // output_en <= 1'b0; 147 | // if(time_counter <= 5000-1250 && time_counter >= 5000-1250*3) 148 | // SCL <= 1'b1; 149 | // else 150 | // SCL <= 1'b0; 151 | // 152 | end 153 | STOP: begin 154 | time_counter <= time_counter - 1'b1; 155 | if(time_counter <= 5000-1250 ) 156 | SCL <= 1'b1; 157 | if(time_counter <= 5000-1250*2) 158 | SDA <= 1'b1; 159 | end 160 | 161 | 162 | default:; 163 | endcase 164 | end 165 | endmodule 166 | -------------------------------------------------------------------------------- /quartus/WAV_AUDIO_PLAYER_pdm_sdhc/rtl/IIS_ip/WM8731_init/SCCB_top.v: -------------------------------------------------------------------------------- 1 | /************************************************************************************************************************ 2 | * Name : 此模块用于初始化WM8731,直接使用了初始化摄像头的代码. 3 | * Author : Helrori 4 | *************************************************************************************************************************/ 5 | module SCCB_top 6 | ( 7 | input init_ov, //上升沿或下降沿触发一次OV2640初始化 8 | input clk, //50Mhz 9 | input rst_n, //触发一次OV2640初始化 10 | 11 | output SCL, 12 | output SDA, 13 | output reg OV2640_PWDN, 14 | output reg OV2640_RST, 15 | 16 | output reg init_ov_done 17 | ); 18 | `define DELAY 5//00000 //发送两帧(软复位)后的延时2500000==50ms 19 | `define NUMBER_TO_SEND 10 //发送个数减一 20 | `define TA 50000 //OV_RST硬件复位时间 21 | /********************************************************************************************************************** 22 | * SCCB通信顶层；用于与ov摄像头的通信配置相关寄存器。DELAY为发送两个数据后必要的的延时。NUMBER_TO_SEND为要写配置寄存器的个数减一 23 | * TA 为OV2640_RST硬件复位时间。 24 | * by_helrori_170329 25 | * Interface N/A 26 | ***********************************************************************************************************************/ 27 | SCCB_send SCCB_send 28 | ( 29 | .clk(clk), //50Mhz 30 | .rst_n(rst_n), 31 | .send(send_), 32 | .address(address_), 33 | .value(value_), 34 | 35 | .SCL(SCL), 36 | .SDA(SDA), 37 | 38 | .busy(busy_), 39 | .time_counter() 40 | 41 | ); 42 | wire [7:0]address_,value_; 43 | wire busy_; 44 | reg [7:0]addr_; 45 | reg send_; 46 | WM8731_reg WM8731_reg 47 | ( 48 | .clk(clk), 49 | .addr(addr_), 50 | .reg_addr(address_), 51 | .value(value_) 52 | ); 53 | 54 | reg buff0,buff1,init_ov_buff; 55 | always @(posedge clk) 56 | begin 57 | buff0 <= init_ov; 58 | buff1 <= buff0; 59 | if(buff0^buff1) //posedge or negedge of init_ov 60 | init_ov_buff <= 1'b1; //next clk will set send_buff to 1 61 | else 62 | init_ov_buff <= 1'b0; 63 | end 64 | 65 | reg buff00,buff11,busy_buff; 66 | always @(posedge clk) 67 | begin 68 | buff00 <= busy_; 69 | buff11 <= buff00; 70 | if(buff11&~buff00) //negedge of busy_ 71 | busy_buff <= 1'b1; //next clk will set send_buff to 1 72 | else 73 | busy_buff <= 1'b0; 74 | end 75 | 76 | /************************************************************************************* 77 | *连续 三相写寄存器 状态机 78 | *************************************************************************************/ 79 | reg [31:0]time_counter1; 80 | reg [7:0]byte_counter; 81 | reg [2:0]state,next_state; 82 | parameter WAIT = 3'd1,START = 3'd0,WRITE = 3'd2,DONE = 3'd3,POINT0 = 3'd4,POINT1 = 3'd5,POINT2 = 3'd6; 83 | always @(posedge clk or negedge rst_n) 84 | if(!rst_n) 85 | state <= START; 86 | else 87 | state <= next_state; 88 | 89 | always @(*) 90 | if(!rst_n) 91 | next_state = START; 92 | else if(init_ov_buff) 93 | next_state = START; 94 | else 95 | case(state) 96 | WAIT: next_state = WAIT; 97 | START:begin 98 | if(time_counter1 >= `TA*3)//500000===10ms//50Mhz 99 | next_state = POINT0; 100 | else 101 | next_state = START; 102 | end 103 | POINT0:next_state = WRITE; 104 | WRITE: begin 105 | if(byte_counter >= `NUMBER_TO_SEND) 106 | next_state = DONE; 107 | else if(byte_counter == 1 && busy_buff == 1) 108 | next_state = POINT1; 109 | else 110 | next_state = WRITE; 111 | end 112 | POINT1: begin 113 | if(time_counter1 >= `DELAY) 114 | next_state = POINT2; 115 | else 116 | next_state = POINT1; 117 | end 118 | POINT2:next_state = POINT0; 119 | DONE:next_state = WAIT; 120 | default:next_state = WAIT; 121 | endcase 122 | 123 | always @(posedge clk or negedge rst_n) 124 | if(!rst_n)begin 125 | time_counter1 <= 32'd0 ; 126 | send_ <= 1'b0; 127 | byte_counter <= 1'b0; 128 | init_ov_done <= 1'b0; 129 | OV2640_RST <= 1'b1; 130 | OV2640_PWDN <= 0; 131 | end 132 | else 133 | case(next_state) 134 | WAIT: begin 135 | time_counter1 <= 32'd0 ; 136 | send_ <= 1'b0; 137 | byte_counter <= 1'b0; 138 | end 139 | START:begin 140 | time_counter1 <= time_counter1 + 1'd1; 141 | OV2640_PWDN <= 0; 142 | if(time_counter1 >= `TA && time_counter1 < `TA*2) 143 | OV2640_RST <= 0; 144 | else 145 | OV2640_RST <= 1'b1; 146 | end 147 | POINT0:begin time_counter1 <= 32'd0;send_ <= ~send_;end 148 | WRITE: begin 149 | if(busy_buff)begin 150 | byte_counter <= byte_counter + 8'd1;addr_ <= addr_ + 8'b1;send_ <= ~send_; 151 | end 152 | end 153 | POINT1: begin 154 | time_counter1 <= time_counter1 + 32'b1; 155 | end 156 | POINT2: begin addr_ <= addr_ + 8'b1;byte_counter <= byte_counter + 8'd1;end 157 | DONE: init_ov_done <= 1'b1; 158 | default:; 159 | endcase 160 | endmodule 161 | -------------------------------------------------------------------------------- /quartus/WAV_AUDIO_PLAYER_pdm_sdhc/rtl/IIS_ip/WM8731_IIS/IIS_driver_top.v: -------------------------------------------------------------------------------- 1 | /************************************************************************ 2 | * Name: 16bit IIS Driver 3 | * Diagram: __________ 4 | * rst_n ->|u o|<- IIS_BCLK 5 | * Write_Clk ->|s ____ u|<- IIS_DACLRC 6 | * Data_In =>|e-|fifo|-t|-> IIS_DACDAT 7 | * Write_Enable ->|r |512 | |<- IIS_ADCLRC(not use) 8 | * Write_Allow <-| |32b | |<- IIS_ADCDAT(not use) 9 | * 10 | * Important: when Write_Allow==1 that mean : 11 | * we can set Write_Enable and write data to fifo by Write_Clk. 12 | * IIS set mode for:Master,DSP模式且为首bit空模式 13 | * 写入FIFO 的PCM数据支持:16bit*2*(采样率由Master设备决定),48k以上未测. 14 | * [31:0]Data_In格式: {16'L,16'R},高16bit为Left. 15 | * Write_Clk > IIS_DACLRC,IIS_DACLRC频率即为采样率 16 | * Only used DAC yet. 17 | * Interface: N/A 18 | * Origin: 171002 19 | * Author: Helrori2011@gmail.com 20 | *************************************************************************/ 21 | module IIS_driver_top 22 | #( 23 | parameter DATA_WIDTH = 16//修改此数的同时也要手动修改FIFO宽度 24 | ) 25 | ( 26 | input rst_n, 27 | input Write_Clk, //IIS运作状态机参考时钟以及FIFO写时钟 28 | input [DATA_WIDTH*2-1:0]Data_In, //16bit*2,{L,R},24bit and 32bit 向高位对齐 29 | input Write_Enable, //when Write_Allow==1 that mean we can set Write_Enable and write data to fifo by Write_Clk. 30 | 31 | input IIS_BCLK, 32 | input IIS_DACLRC, 33 | input IIS_ADCLRC, //not use 34 | input IIS_ADCDAT, //not use 35 | output IIS_DACDAT, 36 | output reg Write_Allow, 37 | output [8:0]wrusedw 38 | ); 39 | reg IIS_DACLRC_Delay_1_IIS_BCLK; 40 | reg [1:0]CTRL_STATE; 41 | reg [5:0]Sel_Cnt; 42 | wire [DATA_WIDTH*2-1:0]q; 43 | //wire[9:0]wrusedw; 44 | reg IIS_DACDAT_OUT_EN; 45 | reg [7:0]cnt; 46 | initial 47 | begin 48 | CTRL_STATE = 2'd0; 49 | cnt = 8'd0; 50 | IIS_DACDAT_OUT_EN = 1; 51 | end 52 | fifo fifo_U1(//512*32bit{L,R} 53 | .aclr(~rst_n), 54 | .data(Data_In), 55 | .rdclk(IIS_DACLRC), 56 | .rdreq(1), //输出连续 57 | .wrclk(Write_Clk), 58 | .wrreq(Write_Enable), 59 | .q(q), 60 | .rdempty(), 61 | .wrusedw(wrusedw)); 62 | /******************************************************************** 63 | * input logic,小于一半连续写满 状态机 64 | *********************************************************************/ 65 | always@(negedge Write_Clk or negedge rst_n) 66 | begin 67 | if(!rst_n) 68 | CTRL_STATE <= 2'd0; 69 | else 70 | begin 71 | case(CTRL_STATE) 72 | 4'd0:begin//UNKNOW 73 | if(wrusedw[8] == 0) 74 | CTRL_STATE <= 2'd1;//fifo data less than half 75 | else 76 | CTRL_STATE <= 2'd2;//fifo data more than half 77 | Write_Allow <= 0; 78 | end 79 | 4'd1:begin//LESS_HALF_WRITE_OVER 80 | if(wrusedw == 512-4)//######该数至少要比满数小4 81 | CTRL_STATE <= 2'd2; 82 | else 83 | CTRL_STATE <= 2'd1; 84 | Write_Allow <= 1; 85 | end 86 | 4'd2:begin//MORE_HALF 87 | if(wrusedw[8] == 0) 88 | CTRL_STATE <= 2'd1;//fifo data less than half 89 | else 90 | CTRL_STATE <= 2'd2;//fifo data more than half 91 | Write_Allow <= 0; 92 | end 93 | default:CTRL_STATE <= 2'd0; 94 | endcase 95 | end 96 | end 97 | /******************************************************************** 98 | * output logic,以下为对应 DSP模式首bit空模式 99 | *********************************************************************/ 100 | assign IIS_DACDAT= (IIS_DACDAT_OUT_EN)?q[DATA_WIDTH*2-1-Sel_Cnt]:1'd0;//高位先 101 | always@(posedge IIS_BCLK) 102 | IIS_DACLRC_Delay_1_IIS_BCLK <= IIS_DACLRC; 103 | always@(negedge IIS_BCLK or negedge rst_n) 104 | begin 105 | if(!rst_n) 106 | Sel_Cnt <= 6'd0; 107 | else if(IIS_DACLRC_Delay_1_IIS_BCLK == 1)//在DSP模式首空bit处（DSP模式设置成首bit空模式），及时清零帧内计数器 108 | Sel_Cnt <= 6'd0; 109 | else 110 | Sel_Cnt <= Sel_Cnt + 6'd1; 111 | end 112 | always@(negedge IIS_BCLK or negedge rst_n) 113 | begin 114 | if(~rst_n)begin 115 | IIS_DACDAT_OUT_EN <= 1; 116 | cnt <= 7'd0; 117 | end 118 | else if(IIS_DACLRC_Delay_1_IIS_BCLK == 1) 119 | begin 120 | cnt <= 7'd0; 121 | IIS_DACDAT_OUT_EN <= 1; 122 | end 123 | else if(cnt == DATA_WIDTH*2-1) 124 | begin 125 | cnt <= 7'd0; 126 | IIS_DACDAT_OUT_EN <= 0; 127 | end 128 | else 129 | begin 130 | cnt <= cnt + 7'd1; 131 | IIS_DACDAT_OUT_EN <= IIS_DACDAT_OUT_EN; 132 | end 133 | end 134 | /******************************************************************** 135 | * output logic2,以下为对应 IIS模式 没完成 136 | *********************************************************************/ 137 | //reg buff0,buff1,IIS_DACLRC_; 138 | //always@(posedge IIS_BCLK or negedge rst_n) 139 | //begin 140 | // if(!rst_n) 141 | // begin 142 | // buff0 <= 0; 143 | // buff1 <= 0; 144 | // end 145 | // else 146 | // begin 147 | // buff0 <= IIS_DACLRC; 148 | // buff1 <= buff0; 149 | // if(buff0&~buff1)//buff0==0&&buff1==1;negedge of IIS_DACLRC 150 | // IIS_DACLRC_ <= 1; 151 | // else 152 | // IIS_DACLRC_ <= 0; 153 | // end 154 | //end 155 | endmodule 156 | -------------------------------------------------------------------------------- /quartus/WAV_AUDIO_PLAYER_pdm_sdhc/rtl/IIS_ip/WM8731_IIS/IIS_driver_top.v.bak: -------------------------------------------------------------------------------- 1 | /************************************************************************ 2 | * Name: 16bit IIS Driver 3 | * Diagram: __________ 4 | * rst_n ->|u o|<- IIS_BCLK 5 | * Write_Clk ->|s ____ u|<- IIS_DACLRC 6 | * Data_In =>|e-|fifo|-t|-> IIS_DACDAT 7 | * Write_Enable ->|r |512 | |<- IIS_ADCLRC(not use) 8 | * Write_Allow <-| |32b | |<- IIS_ADCDAT(not use) 9 | * 10 | * Important: when Write_Allow==1 that mean : 11 | * we can set Write_Enable and write data to fifo by Write_Clk. 12 | * IIS set mode for:Master,DSP模式且为首bit空模式 13 | * 写入FIFO 的PCM数据支持:16bit*2*(采样率由Master设备决定),48k以上未测. 14 | * [31:0]Data_In格式: {16'L,16'R},高16bit为Left. 15 | * Write_Clk > IIS_DACLRC,IIS_DACLRC频率即为采样率 16 | * Only used DAC yet. 17 | * Interface: N/A 18 | * Origin: 171002 19 | * Author: Helrori2011@gmail.com 20 | *************************************************************************/ 21 | module IIS_driver_top 22 | #( 23 | parameter DATA_WIDTH = 16//修改此数的同时也要手动修改FIFO宽度 24 | ) 25 | ( 26 | input rst_n, 27 | input Write_Clk, //IIS运作状态机参考时钟以及FIFO写时钟 28 | input [DATA_WIDTH*2-1:0]Data_In, //16bit*2,{L,R},24bit and 32bit 向高位对齐 29 | input Write_Enable, //when Write_Allow==1 that mean we can set Write_Enable and write data to fifo by Write_Clk. 30 | 31 | input IIS_BCLK, 32 | input IIS_DACLRC, 33 | input IIS_ADCLRC, //not use 34 | input IIS_ADCDAT, //not use 35 | output IIS_DACDAT, 36 | output reg Write_Allow, 37 | output [8:0]wrusedw 38 | ); 39 | reg IIS_DACLRC_Delay_1_IIS_BCLK; 40 | reg [1:0]CTRL_STATE; 41 | reg [5:0]Sel_Cnt; 42 | wire [DATA_WIDTH*2-1:0]q; 43 | //wire[9:0]wrusedw; 44 | reg IIS_DACDAT_OUT_EN; 45 | reg [7:0]cnt; 46 | initial 47 | begin 48 | CTRL_STATE = 2'd0; 49 | cnt = 8'd0; 50 | IIS_DACDAT_OUT_EN = 1; 51 | end 52 | fifo fifo_U1(//512*32bit{L,R} 53 | .aclr(~rst_n), 54 | .data(Data_In), 55 | .rdclk(IIS_DACLRC), 56 | .rdreq(1), //输出连续 57 | .wrclk(Write_Clk), 58 | .wrreq(Write_Enable), 59 | .q(q), 60 | .rdempty(), 61 | .wrusedw(wrusedw)); 62 | /******************************************************************** 63 | * input logic,小于一半连续写满 状态机 64 | *********************************************************************/ 65 | always@(posedge Write_Clk or negedge rst_n) 66 | begin 67 | if(!rst_n) 68 | CTRL_STATE <= 2'd0; 69 | else 70 | begin 71 | case(CTRL_STATE) 72 | 4'd0:begin//UNKNOW 73 | if(wrusedw[8] == 0) 74 | CTRL_STATE <= 2'd1;//fifo data less than half 75 | else 76 | CTRL_STATE <= 2'd2;//fifo data more than half 77 | Write_Allow <= 0; 78 | end 79 | 4'd1:begin//LESS_HALF_WRITE_OVER 80 | if(wrusedw == 512-4)//######该数至少要比满数小4 81 | CTRL_STATE <= 2'd2; 82 | else 83 | CTRL_STATE <= 2'd1; 84 | Write_Allow <= 1; 85 | end 86 | 4'd2:begin//MORE_HALF 87 | if(wrusedw[8] == 0) 88 | CTRL_STATE <= 2'd1;//fifo data less than half 89 | else 90 | CTRL_STATE <= 2'd2;//fifo data more than half 91 | Write_Allow <= 0; 92 | end 93 | default:CTRL_STATE <= 2'd0; 94 | endcase 95 | end 96 | end 97 | /******************************************************************** 98 | * output logic,以下为对应 DSP模式首bit空模式 99 | *********************************************************************/ 100 | assign IIS_DACDAT= (IIS_DACDAT_OUT_EN)?q[DATA_WIDTH*2-1-Sel_Cnt]:1'd0;//高位先 101 | always@(posedge IIS_BCLK) 102 | IIS_DACLRC_Delay_1_IIS_BCLK <= IIS_DACLRC; 103 | always@(negedge IIS_BCLK or negedge rst_n) 104 | begin 105 | if(!rst_n) 106 | Sel_Cnt <= 6'd0; 107 | else if(IIS_DACLRC_Delay_1_IIS_BCLK == 1)//在DSP模式首空bit处（DSP模式设置成首bit空模式），及时清零帧内计数器 108 | Sel_Cnt <= 6'd0; 109 | else 110 | Sel_Cnt <= Sel_Cnt + 6'd1; 111 | end 112 | always@(negedge IIS_BCLK or negedge rst_n) 113 | begin 114 | if(~rst_n)begin 115 | IIS_DACDAT_OUT_EN <= 1; 116 | cnt <= 7'd0; 117 | end 118 | else if(IIS_DACLRC_Delay_1_IIS_BCLK == 1) 119 | begin 120 | cnt <= 7'd0; 121 | IIS_DACDAT_OUT_EN <= 1; 122 | end 123 | else if(cnt == DATA_WIDTH*2-1) 124 | begin 125 | cnt <= 7'd0; 126 | IIS_DACDAT_OUT_EN <= 0; 127 | end 128 | else 129 | begin 130 | cnt <= cnt + 7'd1; 131 | IIS_DACDAT_OUT_EN <= IIS_DACDAT_OUT_EN; 132 | end 133 | end 134 | /******************************************************************** 135 | * output logic2,以下为对应 IIS模式 没完成 136 | *********************************************************************/ 137 | //reg buff0,buff1,IIS_DACLRC_; 138 | //always@(posedge IIS_BCLK or negedge rst_n) 139 | //begin 140 | // if(!rst_n) 141 | // begin 142 | // buff0 <= 0; 143 | // buff1 <= 0; 144 | // end 145 | // else 146 | // begin 147 | // buff0 <= IIS_DACLRC; 148 | // buff1 <= buff0; 149 | // if(buff0&~buff1)//buff0==0&&buff1==1;negedge of IIS_DACLRC 150 | // IIS_DACLRC_ <= 1; 151 | // else 152 | // IIS_DACLRC_ <= 0; 153 | // end 154 | //end 155 | endmodule 156 | -------------------------------------------------------------------------------- /quartus/WAV_AUDIO_PLAYER_pdm_sdhc/rtl/WAV_PLAYER.v: -------------------------------------------------------------------------------- 1 | /************************************************************************************************** 2 | * Name :wav player 3 | * Origin :171015 4 | * 171017 5 | * 171020 6 | * Important:通过SDHC CARD,WM8731播放WAV文件.Only 48k 16bit * 2 WAV file 7 | * 给出FAT文件系统下wav文件扇区地址,硬件会不停的播放,不会停止. 8 | * 硬件使用SDHC 8G CARD ;AUDIO CODEC WM8731. 9 | * Author :Helrori2011@gmail.com 10 | ***************************************************************************************************/ 11 | module WAV_PLAYER 12 | ( 13 | input _clk_50m, 14 | input _rst_n, 15 | //WM8731 IIC port 16 | output IIC_SDA, 17 | output IIC_SCL, 18 | //WM8731 IIS port (wm8731 is master) 19 | input IIS_BCLK, 20 | input IIS_DACLRC, 21 | input IIS_ADCLRC, //not use 22 | input IIS_ADCDAT, //not use 23 | output IIS_DACDAT, 24 | //PDM_audio 25 | output pdm_l, 26 | output pdm_r, 27 | //SDCard SPI port 28 | input SD_MISO, 29 | output SD_CS, 30 | output SD_MOSI, 31 | output SD_SCLK , 32 | 33 | output reg Sample_clk, 34 | output [31:0]WAV_FILE_LEN 35 | ); 36 | wire rst_n,clk_50m,clk_10m; 37 | reg [15:0]Cnt; 38 | reg [15:0]Cnt2; 39 | reg SD_SCLK_REF;//100k 40 | 41 | wire SD_INIT_DONE; 42 | reg _SD_MISO, __SD_MISO; 43 | wire _SD_CS, __SD_CS; 44 | wire _SD_MOSI, __SD_MOSI; 45 | wire _SD_SCLK, __SD_SCLK; 46 | 47 | wire E; 48 | wire [31:0]Data_In; 49 | wire clk_pdm; 50 | /************************************************************ 51 | * System pll 52 | *************************************************************/ 53 | pll pll_U1 54 | ( 55 | .areset(~_rst_n), 56 | .inclk0(_clk_50m), 57 | .c0(clk_50m), 58 | .c1(clk_10m), 59 | .c2(clk_pdm), 60 | .locked(rst_n) 61 | ); 62 | /************************************************************ 63 | * Init WM8731 as master and in dsp mode 64 | *************************************************************/ 65 | SCCB_top SCCB_top_U1 66 | ( 67 | .init_ov(), //上升沿或下降沿触发一次初始化 68 | .clk(clk_50m), //50Mhz 69 | .rst_n(rst_n), //触发一次初始化 70 | 71 | .SCL(IIC_SCL), 72 | .SDA(IIC_SDA), 73 | .OV2640_PWDN(), 74 | .OV2640_RST(), 75 | 76 | .init_ov_done() 77 | ); 78 | /************************************************************ 79 | * Init SDHC card as SPI mode and read SDHC 80 | * 当初始化完成后SD_XXX 口全部由SD_read模块管理 81 | *************************************************************/ 82 | always@(posedge clk_50m or negedge rst_n) 83 | begin 84 | if(!rst_n)begin 85 | SD_SCLK_REF <= 1'd1;; 86 | Cnt <= 16'd0; 87 | end 88 | else if(Cnt >= 500/2-1)///////////// 89 | begin 90 | Cnt <= 16'd0; 91 | SD_SCLK_REF <= ~SD_SCLK_REF; 92 | end 93 | else 94 | Cnt <= Cnt + 16'd1; 95 | end 96 | always@(posedge clk_50m or negedge rst_n) 97 | begin 98 | if(!rst_n)begin 99 | Sample_clk <= 1'd1;; 100 | Cnt2 <= 16'd0; 101 | end 102 | else if(Cnt2 >= 500/2-1)///////////// 103 | begin 104 | Cnt2 <= 16'd0; 105 | Sample_clk <= ~Sample_clk; 106 | end 107 | else 108 | Cnt2 <= Cnt2 + 16'd1; 109 | end 110 | SD_initial SD_initial_U1 111 | ( 112 | .rst_n(rst_n), //触发一次初始化 113 | .SD_SCLK_REF(SD_SCLK_REF), //100KHZ 114 | //SD Card Interface 115 | .SD_MISO (_SD_MISO), 116 | .SD_CS (_SD_CS ), 117 | .SD_MOSI (_SD_MOSI), 118 | .SD_SCLK (_SD_SCLK), 119 | //调试接口 120 | .DAT(), 121 | .INIT_DONE(SD_INIT_DONE), 122 | .STATE(), 123 | .DAT_valid() 124 | ); 125 | always@(*) 126 | if(SD_INIT_DONE) 127 | __SD_MISO = SD_MISO ; 128 | else 129 | _SD_MISO = SD_MISO ; 130 | assign SD_CS = (SD_INIT_DONE==1)?__SD_CS :_SD_CS ; 131 | assign SD_MOSI = (SD_INIT_DONE==1)?__SD_MOSI :_SD_MOSI ; 132 | assign SD_SCLK = (SD_INIT_DONE==1)?__SD_SCLK :_SD_SCLK ; 133 | wire rdaccess; 134 | 135 | 136 | localparam DIV = 256; 137 | reg [$clog2(DIV)-1:0]cnt='b0; 138 | always@(posedge clk_pdm)begin 139 | cnt <= cnt + 1'd1; 140 | end 141 | SD_read SD_read_U1 142 | ( 143 | .SD_SCLK_REF(clk_10m), //读SD 时钟 10Mhz 144 | .rst_n(rst_n), 145 | //Ctrl port 146 | .SD_Read_EN(SD_INIT_DONE), //SD INIT_DONE==1 后在使能该模块;使能后如果fifo小于一半 则开始读SD卡到SD_fifo 147 | .Read_Sec_Addr(32'd107576), //wav文件扇区地址 148 | .Read_Sec_Number(), //扇区个数 not use 149 | //SD Card Interface 150 | .SD_MISO(__SD_MISO), 151 | .SD_CS(__SD_CS), 152 | .SD_MOSI(__SD_MOSI), 153 | .SD_SCLK(__SD_SCLK), 154 | //Read data port 155 | .FIFO_RD_CLK(cnt[$clog2(DIV)-1]), 156 | .FIFO_RD_EN(E), 157 | .q(Data_In),//{L:R} 158 | .FIFO_PREFETCHED(rdaccess), 159 | 160 | .error(), 161 | .WAV_FILE_LEN(WAV_FILE_LEN) 162 | ); 163 | /************************************************************ 164 | * 165 | *************************************************************/ 166 | 167 | pdm_audio 168 | ( 169 | .clk ( clk_pdm),//1536Khz 170 | .rst_n ( rst_n ), 171 | 172 | .rdaccess( rdaccess), 173 | .rdclk ( cnt[$clog2(DIV)-1] ),//1536Khz/32=48Khz 174 | .rden ( E ), 175 | .rddat ( Data_In ), 176 | 177 | .pdm_r ( pdm_r ), 178 | .pdm_l ( pdm_l ) 179 | 180 | ); 181 | 182 | endmodule 183 | -------------------------------------------------------------------------------- /quartus/WAV_AUDIO_PLAYER_pdm_sdhc/WAV_PLAYER.qsf: -------------------------------------------------------------------------------- 1 | # -------------------------------------------------------------------------- # 2 | # 3 | # Copyright (C) 1991-2013 Altera Corporation 4 | # Your use of Altera Corporation's design tools, logic functions 5 | # and other software and tools, and its AMPP partner logic 6 | # functions, and any output files from any of the foregoing 7 | # (including device programming or simulation files), and any 8 | # associated documentation or information are expressly subject 9 | # to the terms and conditions of the Altera Program License 10 | # Subscription Agreement, Altera MegaCore Function License 11 | # Agreement, or other applicable license agreement, including, 12 | # without limitation, that your use is for the sole purpose of 13 | # programming logic devices manufactured by Altera and sold by 14 | # Altera or its authorized distributors. Please refer to the 15 | # applicable agreement for further details. 16 | # 17 | # -------------------------------------------------------------------------- # 18 | # 19 | # Quartus II 64-Bit 20 | # Version 13.1.0 Build 162 10/23/2013 SJ Full Version 21 | # Date created = 18:39:19 October 15, 2017 22 | # 23 | # -------------------------------------------------------------------------- # 24 | # 25 | # Notes: 26 | # 27 | # 1) The default values for assignments are stored in the file: 28 | # WAV_PLAYER_assignment_defaults.qdf 29 | # If this file doesn't exist, see file: 30 | # assignment_defaults.qdf 31 | # 32 | # 2) Altera recommends that you do not modify this file. This 33 | # file is updated automatically by the Quartus II software 34 | # and any changes you make may be lost or overwritten. 35 | # 36 | # -------------------------------------------------------------------------- # 37 | 38 | 39 | set_global_assignment -name FAMILY "Cyclone IV E" 40 | set_global_assignment -name DEVICE EP4CE10F17C8 41 | set_global_assignment -name TOP_LEVEL_ENTITY WAV_PLAYER 42 | set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1 43 | set_global_assignment -name PROJECT_CREATION_TIME_DATE "18:39:19 OCTOBER 15, 2017" 44 | set_global_assignment -name LAST_QUARTUS_VERSION "17.1.0 Standard Edition" 45 | set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files 46 | set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 47 | set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 48 | set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 49 | set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V 50 | set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (Verilog)" 51 | set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation 52 | set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top 53 | set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top 54 | set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top 55 | set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V" 56 | set_location_assignment PIN_T8 -to IIC_SCL 57 | set_location_assignment PIN_P8 -to IIC_SDA 58 | set_location_assignment PIN_M9 -to IIS_ADCDAT 59 | set_location_assignment PIN_P9 -to IIS_ADCLRC 60 | set_location_assignment PIN_N8 -to IIS_BCLK 61 | set_location_assignment PIN_L8 -to IIS_DACDAT 62 | set_location_assignment PIN_K9 -to IIS_DACLRC 63 | set_location_assignment PIN_T2 -to SD_CS 64 | set_location_assignment PIN_P2 -to SD_MISO 65 | set_location_assignment PIN_R1 -to SD_MOSI 66 | set_location_assignment PIN_M8 -to SD_SCLK 67 | set_location_assignment PIN_E1 -to _clk_50m 68 | set_location_assignment PIN_B3 -to _rst_n 69 | set_global_assignment -name ENABLE_SIGNALTAP OFF 70 | set_global_assignment -name USE_SIGNALTAP_FILE stp3.stp 71 | set_global_assignment -name VERILOG_FILE ../../pdm_audio.v 72 | set_global_assignment -name VERILOG_FILE ../../delta_sigma_adc.v 73 | set_global_assignment -name VERILOG_FILE rtl/IIS_ip/WM8731_init/SPI_INIT/SPI_send.v 74 | set_global_assignment -name VERILOG_FILE rtl/IIS_ip/WM8731_init/SPI_INIT/device_init_reg.v 75 | set_global_assignment -name VERILOG_FILE rtl/IIS_ip/WM8731_init/SPI_INIT/device_init.v 76 | set_global_assignment -name VERILOG_FILE rtl/SDCard_ip/SD_read.v 77 | set_global_assignment -name VERILOG_FILE rtl/SDCard_ip/SD_initial.v 78 | set_global_assignment -name VERILOG_FILE rtl/IIS_ip/WM8731_init/WM8731_reg.v 79 | set_global_assignment -name VERILOG_FILE rtl/IIS_ip/WM8731_init/SCCB_top.v 80 | set_global_assignment -name VERILOG_FILE rtl/IIS_ip/WM8731_init/SCCB_send.v 81 | set_global_assignment -name VERILOG_FILE rtl/IIS_ip/WM8731_IIS/IIS_driver_top.v 82 | set_global_assignment -name VERILOG_FILE rtl/IIS_ip/WM8731_IIS/fifo.v 83 | set_global_assignment -name VERILOG_FILE rtl/WAV_PLAYER.v 84 | set_global_assignment -name QIP_FILE rtl/PLL/pll.qip 85 | set_global_assignment -name SIGNALTAP_FILE stp3.stp 86 | set_global_assignment -name QIP_FILE rtl/SDCard_ip/SD_fifo.qip 87 | set_global_assignment -name CDF_FILE output_files/Chain1.cdf 88 | set_global_assignment -name CDF_FILE output_files/Chain2.cdf 89 | set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" 90 | set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" 91 | set_location_assignment PIN_L1 -to pdm_l 92 | set_location_assignment PIN_N1 -to pdm_r 93 | set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top -------------------------------------------------------------------------------- /quartus/WAV_AUDIO_PLAYER_pdm_sdhc/rtl/IIS_ip/WM8731_IIS/fifo_bb.v: -------------------------------------------------------------------------------- 1 | // megafunction wizard: %FIFO%VBB% 2 | // GENERATION: STANDARD 3 | // VERSION: WM1.0 4 | // MODULE: dcfifo 5 | 6 | // ============================================================ 7 | // File Name: fifo.v 8 | // Megafunction Name(s): 9 | // dcfifo 10 | // 11 | // Simulation Library Files(s): 12 | // altera_mf 13 | // ============================================================ 14 | // ************************************************************ 15 | // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! 16 | // 17 | // 13.0.0 Build 156 04/24/2013 SJ Full Version 18 | // ************************************************************ 19 | 20 | //Copyright (C) 1991-2013 Altera Corporation 21 | //Your use of Altera Corporation's design tools, logic functions 22 | //and other software and tools, and its AMPP partner logic 23 | //functions, and any output files from any of the foregoing 24 | //(including device programming or simulation files), and any 25 | //associated documentation or information are expressly subject 26 | //to the terms and conditions of the Altera Program License 27 | //Subscription Agreement, Altera MegaCore Function License 28 | //Agreement, or other applicable license agreement, including, 29 | //without limitation, that your use is for the sole purpose of 30 | //programming logic devices manufactured by Altera and sold by 31 | //Altera or its authorized distributors. Please refer to the 32 | //applicable agreement for further details. 33 | 34 | module fifo ( 35 | aclr, 36 | data, 37 | rdclk, 38 | rdreq, 39 | wrclk, 40 | wrreq, 41 | q, 42 | rdempty, 43 | wrusedw); 44 | 45 | input aclr; 46 | input [31:0] data; 47 | input rdclk; 48 | input rdreq; 49 | input wrclk; 50 | input wrreq; 51 | output [31:0] q; 52 | output rdempty; 53 | output [8:0] wrusedw; 54 | `ifndef ALTERA_RESERVED_QIS 55 | // synopsys translate_off 56 | `endif 57 | tri0 aclr; 58 | `ifndef ALTERA_RESERVED_QIS 59 | // synopsys translate_on 60 | `endif 61 | 62 | endmodule 63 | 64 | // ============================================================ 65 | // CNX file retrieval info 66 | // ============================================================ 67 | // Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0" 68 | // Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1" 69 | // Retrieval info: PRIVATE: AlmostFull NUMERIC "0" 70 | // Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1" 71 | // Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0" 72 | // Retrieval info: PRIVATE: Clock NUMERIC "4" 73 | // Retrieval info: PRIVATE: Depth NUMERIC "512" 74 | // Retrieval info: PRIVATE: Empty NUMERIC "1" 75 | // Retrieval info: PRIVATE: Full NUMERIC "1" 76 | // Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" 77 | // Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0" 78 | // Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0" 79 | // Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0" 80 | // Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0" 81 | // Retrieval info: PRIVATE: Optimize NUMERIC "2" 82 | // Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" 83 | // Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" 84 | // Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0" 85 | // Retrieval info: PRIVATE: UsedW NUMERIC "1" 86 | // Retrieval info: PRIVATE: Width NUMERIC "32" 87 | // Retrieval info: PRIVATE: dc_aclr NUMERIC "1" 88 | // Retrieval info: PRIVATE: diff_widths NUMERIC "0" 89 | // Retrieval info: PRIVATE: msb_usedw NUMERIC "0" 90 | // Retrieval info: PRIVATE: output_width NUMERIC "32" 91 | // Retrieval info: PRIVATE: rsEmpty NUMERIC "1" 92 | // Retrieval info: PRIVATE: rsFull NUMERIC "0" 93 | // Retrieval info: PRIVATE: rsUsedW NUMERIC "0" 94 | // Retrieval info: PRIVATE: sc_aclr NUMERIC "0" 95 | // Retrieval info: PRIVATE: sc_sclr NUMERIC "0" 96 | // Retrieval info: PRIVATE: wsEmpty NUMERIC "0" 97 | // Retrieval info: PRIVATE: wsFull NUMERIC "0" 98 | // Retrieval info: PRIVATE: wsUsedW NUMERIC "1" 99 | // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all 100 | // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" 101 | // Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "512" 102 | // Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON" 103 | // Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo" 104 | // Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "32" 105 | // Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "9" 106 | // Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON" 107 | // Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "4" 108 | // Retrieval info: CONSTANT: READ_ACLR_SYNCH STRING "OFF" 109 | // Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON" 110 | // Retrieval info: CONSTANT: USE_EAB STRING "ON" 111 | // Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "OFF" 112 | // Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "4" 113 | // Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND "aclr" 114 | // Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL "data[31..0]" 115 | // Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL "q[31..0]" 116 | // Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL "rdclk" 117 | // Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL "rdempty" 118 | // Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq" 119 | // Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL "wrclk" 120 | // Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq" 121 | // Retrieval info: USED_PORT: wrusedw 0 0 9 0 OUTPUT NODEFVAL "wrusedw[8..0]" 122 | // Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0 123 | // Retrieval info: CONNECT: @data 0 0 32 0 data 0 0 32 0 124 | // Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0 125 | // Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0 126 | // Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0 127 | // Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0 128 | // Retrieval info: CONNECT: q 0 0 32 0 @q 0 0 32 0 129 | // Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0 130 | // Retrieval info: CONNECT: wrusedw 0 0 9 0 @wrusedw 0 0 9 0 131 | // Retrieval info: GEN_FILE: TYPE_NORMAL fifo.v TRUE 132 | // Retrieval info: GEN_FILE: TYPE_NORMAL fifo.inc FALSE 133 | // Retrieval info: GEN_FILE: TYPE_NORMAL fifo.cmp FALSE 134 | // Retrieval info: GEN_FILE: TYPE_NORMAL fifo.bsf FALSE 135 | // Retrieval info: GEN_FILE: TYPE_NORMAL fifo_inst.v FALSE 136 | // Retrieval info: GEN_FILE: TYPE_NORMAL fifo_bb.v TRUE 137 | // Retrieval info: LIB_FILE: altera_mf 138 | -------------------------------------------------------------------------------- /quartus/WAV_AUDIO_PLAYER_pdm_sdhc/rtl/SDCard_ip/SD_fifo_bb.v: -------------------------------------------------------------------------------- 1 | // megafunction wizard: %FIFO%VBB% 2 | // GENERATION: STANDARD 3 | // VERSION: WM1.0 4 | // MODULE: dcfifo 5 | 6 | // ============================================================ 7 | // File Name: SD_fifo.v 8 | // Megafunction Name(s): 9 | // dcfifo 10 | // 11 | // Simulation Library Files(s): 12 | // 13 | // ============================================================ 14 | // ************************************************************ 15 | // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! 16 | // 17 | // 17.1.0 Build 590 10/25/2017 SJ Standard Edition 18 | // ************************************************************ 19 | 20 | //Copyright (C) 2017 Intel Corporation. All rights reserved. 21 | //Your use of Intel Corporation's design tools, logic functions 22 | //and other software and tools, and its AMPP partner logic 23 | //functions, and any output files from any of the foregoing 24 | //(including device programming or simulation files), and any 25 | //associated documentation or information are expressly subject 26 | //to the terms and conditions of the Intel Program License 27 | //Subscription Agreement, the Intel Quartus Prime License Agreement, 28 | //the Intel FPGA IP License Agreement, or other applicable license 29 | //agreement, including, without limitation, that your use is for 30 | //the sole purpose of programming logic devices manufactured by 31 | //Intel and sold by Intel or its authorized distributors. Please 32 | //refer to the applicable agreement for further details. 33 | 34 | module SD_fifo ( 35 | aclr, 36 | data, 37 | rdclk, 38 | rdreq, 39 | wrclk, 40 | wrreq, 41 | q, 42 | rdempty, 43 | wrusedw); 44 | 45 | input aclr; 46 | input [31:0] data; 47 | input rdclk; 48 | input rdreq; 49 | input wrclk; 50 | input wrreq; 51 | output [31:0] q; 52 | output rdempty; 53 | output [9:0] wrusedw; 54 | `ifndef ALTERA_RESERVED_QIS 55 | // synopsys translate_off 56 | `endif 57 | tri0 aclr; 58 | `ifndef ALTERA_RESERVED_QIS 59 | // synopsys translate_on 60 | `endif 61 | 62 | endmodule 63 | 64 | // ============================================================ 65 | // CNX file retrieval info 66 | // ============================================================ 67 | // Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0" 68 | // Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1" 69 | // Retrieval info: PRIVATE: AlmostFull NUMERIC "0" 70 | // Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1" 71 | // Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0" 72 | // Retrieval info: PRIVATE: Clock NUMERIC "4" 73 | // Retrieval info: PRIVATE: Depth NUMERIC "1024" 74 | // Retrieval info: PRIVATE: Empty NUMERIC "1" 75 | // Retrieval info: PRIVATE: Full NUMERIC "1" 76 | // Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" 77 | // Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0" 78 | // Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0" 79 | // Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0" 80 | // Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0" 81 | // Retrieval info: PRIVATE: Optimize NUMERIC "0" 82 | // Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" 83 | // Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" 84 | // Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0" 85 | // Retrieval info: PRIVATE: UsedW NUMERIC "1" 86 | // Retrieval info: PRIVATE: Width NUMERIC "32" 87 | // Retrieval info: PRIVATE: dc_aclr NUMERIC "1" 88 | // Retrieval info: PRIVATE: diff_widths NUMERIC "0" 89 | // Retrieval info: PRIVATE: msb_usedw NUMERIC "0" 90 | // Retrieval info: PRIVATE: output_width NUMERIC "32" 91 | // Retrieval info: PRIVATE: rsEmpty NUMERIC "1" 92 | // Retrieval info: PRIVATE: rsFull NUMERIC "0" 93 | // Retrieval info: PRIVATE: rsUsedW NUMERIC "0" 94 | // Retrieval info: PRIVATE: sc_aclr NUMERIC "0" 95 | // Retrieval info: PRIVATE: sc_sclr NUMERIC "0" 96 | // Retrieval info: PRIVATE: wsEmpty NUMERIC "0" 97 | // Retrieval info: PRIVATE: wsFull NUMERIC "0" 98 | // Retrieval info: PRIVATE: wsUsedW NUMERIC "1" 99 | // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all 100 | // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" 101 | // Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "1024" 102 | // Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON" 103 | // Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo" 104 | // Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "32" 105 | // Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "10" 106 | // Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON" 107 | // Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "4" 108 | // Retrieval info: CONSTANT: READ_ACLR_SYNCH STRING "OFF" 109 | // Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON" 110 | // Retrieval info: CONSTANT: USE_EAB STRING "ON" 111 | // Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "OFF" 112 | // Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "4" 113 | // Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND "aclr" 114 | // Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL "data[31..0]" 115 | // Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL "q[31..0]" 116 | // Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL "rdclk" 117 | // Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL "rdempty" 118 | // Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq" 119 | // Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL "wrclk" 120 | // Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq" 121 | // Retrieval info: USED_PORT: wrusedw 0 0 10 0 OUTPUT NODEFVAL "wrusedw[9..0]" 122 | // Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0 123 | // Retrieval info: CONNECT: @data 0 0 32 0 data 0 0 32 0 124 | // Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0 125 | // Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0 126 | // Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0 127 | // Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0 128 | // Retrieval info: CONNECT: q 0 0 32 0 @q 0 0 32 0 129 | // Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0 130 | // Retrieval info: CONNECT: wrusedw 0 0 10 0 @wrusedw 0 0 10 0 131 | // Retrieval info: GEN_FILE: TYPE_NORMAL SD_fifo.v TRUE 132 | // Retrieval info: GEN_FILE: TYPE_NORMAL SD_fifo.inc FALSE 133 | // Retrieval info: GEN_FILE: TYPE_NORMAL SD_fifo.cmp FALSE 134 | // Retrieval info: GEN_FILE: TYPE_NORMAL SD_fifo.bsf FALSE 135 | // Retrieval info: GEN_FILE: TYPE_NORMAL SD_fifo_inst.v FALSE 136 | // Retrieval info: GEN_FILE: TYPE_NORMAL SD_fifo_bb.v TRUE 137 | -------------------------------------------------------------------------------- /quartus/WAV_AUDIO_PLAYER_pdm_sdhc/rtl/IIS_ip/WM8731_IIS/fifo.v: -------------------------------------------------------------------------------- 1 | // megafunction wizard: %FIFO% 2 | // GENERATION: STANDARD 3 | // VERSION: WM1.0 4 | // MODULE: dcfifo 5 | 6 | // ============================================================ 7 | // File Name: fifo.v 8 | // Megafunction Name(s): 9 | // dcfifo 10 | // 11 | // Simulation Library Files(s): 12 | // altera_mf 13 | // ============================================================ 14 | // ************************************************************ 15 | // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! 16 | // 17 | // 13.0.0 Build 156 04/24/2013 SJ Full Version 18 | // ************************************************************ 19 | 20 | 21 | //Copyright (C) 1991-2013 Altera Corporation 22 | //Your use of Altera Corporation's design tools, logic functions 23 | //and other software and tools, and its AMPP partner logic 24 | //functions, and any output files from any of the foregoing 25 | //(including device programming or simulation files), and any 26 | //associated documentation or information are expressly subject 27 | //to the terms and conditions of the Altera Program License 28 | //Subscription Agreement, Altera MegaCore Function License 29 | //Agreement, or other applicable license agreement, including, 30 | //without limitation, that your use is for the sole purpose of 31 | //programming logic devices manufactured by Altera and sold by 32 | //Altera or its authorized distributors. Please refer to the 33 | //applicable agreement for further details. 34 | 35 | 36 | // synopsys translate_off 37 | `timescale 1 ps / 1 ps 38 | // synopsys translate_on 39 | module fifo ( 40 | aclr, 41 | data, 42 | rdclk, 43 | rdreq, 44 | wrclk, 45 | wrreq, 46 | q, 47 | rdempty, 48 | wrusedw); 49 | 50 | input aclr; 51 | input [31:0] data; 52 | input rdclk; 53 | input rdreq; 54 | input wrclk; 55 | input wrreq; 56 | output [31:0] q; 57 | output rdempty; 58 | output [8:0] wrusedw; 59 | `ifndef ALTERA_RESERVED_QIS 60 | // synopsys translate_off 61 | `endif 62 | tri0 aclr; 63 | `ifndef ALTERA_RESERVED_QIS 64 | // synopsys translate_on 65 | `endif 66 | 67 | wire [31:0] sub_wire0; 68 | wire sub_wire1; 69 | wire [8:0] sub_wire2; 70 | wire [31:0] q = sub_wire0[31:0]; 71 | wire rdempty = sub_wire1; 72 | wire [8:0] wrusedw = sub_wire2[8:0]; 73 | 74 | dcfifo dcfifo_component ( 75 | .rdclk (rdclk), 76 | .wrclk (wrclk), 77 | .wrreq (wrreq), 78 | .aclr (aclr), 79 | .data (data), 80 | .rdreq (rdreq), 81 | .q (sub_wire0), 82 | .rdempty (sub_wire1), 83 | .wrusedw (sub_wire2), 84 | .rdfull (), 85 | .rdusedw (), 86 | .wrempty (), 87 | .wrfull ()); 88 | defparam 89 | dcfifo_component.intended_device_family = "Cyclone IV E", 90 | dcfifo_component.lpm_numwords = 512, 91 | dcfifo_component.lpm_showahead = "ON", 92 | dcfifo_component.lpm_type = "dcfifo", 93 | dcfifo_component.lpm_width = 32, 94 | dcfifo_component.lpm_widthu = 9, 95 | dcfifo_component.overflow_checking = "ON", 96 | dcfifo_component.rdsync_delaypipe = 4, 97 | dcfifo_component.read_aclr_synch = "OFF", 98 | dcfifo_component.underflow_checking = "ON", 99 | dcfifo_component.use_eab = "ON", 100 | dcfifo_component.write_aclr_synch = "OFF", 101 | dcfifo_component.wrsync_delaypipe = 4; 102 | 103 | 104 | endmodule 105 | 106 | // ============================================================ 107 | // CNX file retrieval info 108 | // ============================================================ 109 | // Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0" 110 | // Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1" 111 | // Retrieval info: PRIVATE: AlmostFull NUMERIC "0" 112 | // Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1" 113 | // Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0" 114 | // Retrieval info: PRIVATE: Clock NUMERIC "4" 115 | // Retrieval info: PRIVATE: Depth NUMERIC "512" 116 | // Retrieval info: PRIVATE: Empty NUMERIC "1" 117 | // Retrieval info: PRIVATE: Full NUMERIC "1" 118 | // Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" 119 | // Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0" 120 | // Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0" 121 | // Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0" 122 | // Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0" 123 | // Retrieval info: PRIVATE: Optimize NUMERIC "2" 124 | // Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" 125 | // Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" 126 | // Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0" 127 | // Retrieval info: PRIVATE: UsedW NUMERIC "1" 128 | // Retrieval info: PRIVATE: Width NUMERIC "32" 129 | // Retrieval info: PRIVATE: dc_aclr NUMERIC "1" 130 | // Retrieval info: PRIVATE: diff_widths NUMERIC "0" 131 | // Retrieval info: PRIVATE: msb_usedw NUMERIC "0" 132 | // Retrieval info: PRIVATE: output_width NUMERIC "32" 133 | // Retrieval info: PRIVATE: rsEmpty NUMERIC "1" 134 | // Retrieval info: PRIVATE: rsFull NUMERIC "0" 135 | // Retrieval info: PRIVATE: rsUsedW NUMERIC "0" 136 | // Retrieval info: PRIVATE: sc_aclr NUMERIC "0" 137 | // Retrieval info: PRIVATE: sc_sclr NUMERIC "0" 138 | // Retrieval info: PRIVATE: wsEmpty NUMERIC "0" 139 | // Retrieval info: PRIVATE: wsFull NUMERIC "0" 140 | // Retrieval info: PRIVATE: wsUsedW NUMERIC "1" 141 | // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all 142 | // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" 143 | // Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "512" 144 | // Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON" 145 | // Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo" 146 | // Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "32" 147 | // Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "9" 148 | // Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON" 149 | // Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "4" 150 | // Retrieval info: CONSTANT: READ_ACLR_SYNCH STRING "OFF" 151 | // Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON" 152 | // Retrieval info: CONSTANT: USE_EAB STRING "ON" 153 | // Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "OFF" 154 | // Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "4" 155 | // Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND "aclr" 156 | // Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL "data[31..0]" 157 | // Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL "q[31..0]" 158 | // Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL "rdclk" 159 | // Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL "rdempty" 160 | // Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq" 161 | // Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL "wrclk" 162 | // Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq" 163 | // Retrieval info: USED_PORT: wrusedw 0 0 9 0 OUTPUT NODEFVAL "wrusedw[8..0]" 164 | // Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0 165 | // Retrieval info: CONNECT: @data 0 0 32 0 data 0 0 32 0 166 | // Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0 167 | // Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0 168 | // Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0 169 | // Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0 170 | // Retrieval info: CONNECT: q 0 0 32 0 @q 0 0 32 0 171 | // Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0 172 | // Retrieval info: CONNECT: wrusedw 0 0 9 0 @wrusedw 0 0 9 0 173 | // Retrieval info: GEN_FILE: TYPE_NORMAL fifo.v TRUE 174 | // Retrieval info: GEN_FILE: TYPE_NORMAL fifo.inc FALSE 175 | // Retrieval info: GEN_FILE: TYPE_NORMAL fifo.cmp FALSE 176 | // Retrieval info: GEN_FILE: TYPE_NORMAL fifo.bsf FALSE 177 | // Retrieval info: GEN_FILE: TYPE_NORMAL fifo_inst.v FALSE 178 | // Retrieval info: GEN_FILE: TYPE_NORMAL fifo_bb.v TRUE 179 | // Retrieval info: LIB_FILE: altera_mf 180 | -------------------------------------------------------------------------------- /quartus/WAV_AUDIO_PLAYER_pdm_sdhc/rtl/SDCard_ip/SD_fifo.v: -------------------------------------------------------------------------------- 1 | // megafunction wizard: %FIFO% 2 | // GENERATION: STANDARD 3 | // VERSION: WM1.0 4 | // MODULE: dcfifo 5 | 6 | // ============================================================ 7 | // File Name: SD_fifo.v 8 | // Megafunction Name(s): 9 | // dcfifo 10 | // 11 | // Simulation Library Files(s): 12 | // 13 | // ============================================================ 14 | // ************************************************************ 15 | // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! 16 | // 17 | // 17.1.0 Build 590 10/25/2017 SJ Standard Edition 18 | // ************************************************************ 19 | 20 | 21 | //Copyright (C) 2017 Intel Corporation. All rights reserved. 22 | //Your use of Intel Corporation's design tools, logic functions 23 | //and other software and tools, and its AMPP partner logic 24 | //functions, and any output files from any of the foregoing 25 | //(including device programming or simulation files), and any 26 | //associated documentation or information are expressly subject 27 | //to the terms and conditions of the Intel Program License 28 | //Subscription Agreement, the Intel Quartus Prime License Agreement, 29 | //the Intel FPGA IP License Agreement, or other applicable license 30 | //agreement, including, without limitation, that your use is for 31 | //the sole purpose of programming logic devices manufactured by 32 | //Intel and sold by Intel or its authorized distributors. Please 33 | //refer to the applicable agreement for further details. 34 | 35 | 36 | // synopsys translate_off 37 | `timescale 1 ps / 1 ps 38 | // synopsys translate_on 39 | module SD_fifo ( 40 | aclr, 41 | data, 42 | rdclk, 43 | rdreq, 44 | wrclk, 45 | wrreq, 46 | q, 47 | rdempty, 48 | wrusedw); 49 | 50 | input aclr; 51 | input [31:0] data; 52 | input rdclk; 53 | input rdreq; 54 | input wrclk; 55 | input wrreq; 56 | output [31:0] q; 57 | output rdempty; 58 | output [9:0] wrusedw; 59 | `ifndef ALTERA_RESERVED_QIS 60 | // synopsys translate_off 61 | `endif 62 | tri0 aclr; 63 | `ifndef ALTERA_RESERVED_QIS 64 | // synopsys translate_on 65 | `endif 66 | 67 | wire [31:0] sub_wire0; 68 | wire sub_wire1; 69 | wire [9:0] sub_wire2; 70 | wire [31:0] q = sub_wire0[31:0]; 71 | wire rdempty = sub_wire1; 72 | wire [9:0] wrusedw = sub_wire2[9:0]; 73 | 74 | dcfifo dcfifo_component ( 75 | .aclr (aclr), 76 | .data (data), 77 | .rdclk (rdclk), 78 | .rdreq (rdreq), 79 | .wrclk (wrclk), 80 | .wrreq (wrreq), 81 | .q (sub_wire0), 82 | .rdempty (sub_wire1), 83 | .wrusedw (sub_wire2), 84 | .eccstatus (), 85 | .rdfull (), 86 | .rdusedw (), 87 | .wrempty (), 88 | .wrfull ()); 89 | defparam 90 | dcfifo_component.intended_device_family = "Cyclone IV E", 91 | dcfifo_component.lpm_numwords = 1024, 92 | dcfifo_component.lpm_showahead = "ON", 93 | dcfifo_component.lpm_type = "dcfifo", 94 | dcfifo_component.lpm_width = 32, 95 | dcfifo_component.lpm_widthu = 10, 96 | dcfifo_component.overflow_checking = "ON", 97 | dcfifo_component.rdsync_delaypipe = 4, 98 | dcfifo_component.read_aclr_synch = "OFF", 99 | dcfifo_component.underflow_checking = "ON", 100 | dcfifo_component.use_eab = "ON", 101 | dcfifo_component.write_aclr_synch = "OFF", 102 | dcfifo_component.wrsync_delaypipe = 4; 103 | 104 | 105 | endmodule 106 | 107 | // ============================================================ 108 | // CNX file retrieval info 109 | // ============================================================ 110 | // Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0" 111 | // Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1" 112 | // Retrieval info: PRIVATE: AlmostFull NUMERIC "0" 113 | // Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1" 114 | // Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0" 115 | // Retrieval info: PRIVATE: Clock NUMERIC "4" 116 | // Retrieval info: PRIVATE: Depth NUMERIC "1024" 117 | // Retrieval info: PRIVATE: Empty NUMERIC "1" 118 | // Retrieval info: PRIVATE: Full NUMERIC "1" 119 | // Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" 120 | // Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0" 121 | // Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0" 122 | // Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0" 123 | // Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0" 124 | // Retrieval info: PRIVATE: Optimize NUMERIC "0" 125 | // Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" 126 | // Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" 127 | // Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0" 128 | // Retrieval info: PRIVATE: UsedW NUMERIC "1" 129 | // Retrieval info: PRIVATE: Width NUMERIC "32" 130 | // Retrieval info: PRIVATE: dc_aclr NUMERIC "1" 131 | // Retrieval info: PRIVATE: diff_widths NUMERIC "0" 132 | // Retrieval info: PRIVATE: msb_usedw NUMERIC "0" 133 | // Retrieval info: PRIVATE: output_width NUMERIC "32" 134 | // Retrieval info: PRIVATE: rsEmpty NUMERIC "1" 135 | // Retrieval info: PRIVATE: rsFull NUMERIC "0" 136 | // Retrieval info: PRIVATE: rsUsedW NUMERIC "0" 137 | // Retrieval info: PRIVATE: sc_aclr NUMERIC "0" 138 | // Retrieval info: PRIVATE: sc_sclr NUMERIC "0" 139 | // Retrieval info: PRIVATE: wsEmpty NUMERIC "0" 140 | // Retrieval info: PRIVATE: wsFull NUMERIC "0" 141 | // Retrieval info: PRIVATE: wsUsedW NUMERIC "1" 142 | // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all 143 | // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" 144 | // Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "1024" 145 | // Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON" 146 | // Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo" 147 | // Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "32" 148 | // Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "10" 149 | // Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON" 150 | // Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "4" 151 | // Retrieval info: CONSTANT: READ_ACLR_SYNCH STRING "OFF" 152 | // Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON" 153 | // Retrieval info: CONSTANT: USE_EAB STRING "ON" 154 | // Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "OFF" 155 | // Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "4" 156 | // Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND "aclr" 157 | // Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL "data[31..0]" 158 | // Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL "q[31..0]" 159 | // Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL "rdclk" 160 | // Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL "rdempty" 161 | // Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq" 162 | // Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL "wrclk" 163 | // Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq" 164 | // Retrieval info: USED_PORT: wrusedw 0 0 10 0 OUTPUT NODEFVAL "wrusedw[9..0]" 165 | // Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0 166 | // Retrieval info: CONNECT: @data 0 0 32 0 data 0 0 32 0 167 | // Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0 168 | // Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0 169 | // Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0 170 | // Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0 171 | // Retrieval info: CONNECT: q 0 0 32 0 @q 0 0 32 0 172 | // Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0 173 | // Retrieval info: CONNECT: wrusedw 0 0 10 0 @wrusedw 0 0 10 0 174 | // Retrieval info: GEN_FILE: TYPE_NORMAL SD_fifo.v TRUE 175 | // Retrieval info: GEN_FILE: TYPE_NORMAL SD_fifo.inc FALSE 176 | // Retrieval info: GEN_FILE: TYPE_NORMAL SD_fifo.cmp FALSE 177 | // Retrieval info: GEN_FILE: TYPE_NORMAL SD_fifo.bsf FALSE 178 | // Retrieval info: GEN_FILE: TYPE_NORMAL SD_fifo_inst.v FALSE 179 | // Retrieval info: GEN_FILE: TYPE_NORMAL SD_fifo_bb.v TRUE 180 | -------------------------------------------------------------------------------- /quartus/WAV_AUDIO_PLAYER_pdm_sdhc/rtl/SDCard_ip/SD_read.v: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * Name : Stream SD read 3 | * Origin : 171015 4 | * 171017 5 | * Important: SD_fifo 小于一半(<256)时,读SD CARD 512 Bytes（128字）到SD_fifo. 6 | * 另一边，控制器根据IIS_fifo 写允许，将数据从SD_fifo搬到IIS_fifo 7 | * Interface: N/A(SD_fifo)没有总线接口,也不建议添加接口. 8 | * 如有必要添加总线接口,请增加初始化时序发生器,不建议使用SD_initial.v. 9 | * Author : Helrori2011@gmail.com 10 | ******************************************************************************/ 11 | module SD_read// 12 | ( 13 | input SD_SCLK_REF, //读SD 时钟 10Mhz 14 | input rst_n, 15 | //Ctrl port 16 | input SD_Read_EN,//SD INIT_DONE==1 后在使能该模块;使能后如果fifo小于一半 则开始读SD卡到SD_fifo 17 | input [31:0]Read_Sec_Addr, //扇区地址 not use now 18 | input [23:0]Read_Sec_Number, //扇区个数 not use now 19 | //SD Card Interface 20 | input SD_MISO, 21 | output reg SD_CS , 22 | output reg SD_MOSI , 23 | output SD_SCLK, 24 | //Read data port 25 | input FIFO_RD_CLK, 26 | input FIFO_RD_EN, 27 | output [31:0]q, //{L:R} 28 | output reg FIFO_PREFETCHED, 29 | output reg error, 30 | output reg [31:0] WAV_FILE_LEN 31 | ); 32 | assign SD_SCLK=SD_SCLK_REF ; 33 | reg [31:0] _Read_Sec_Addr ; 34 | //reg [1:0] CTRL_STATE ; 35 | reg [3:0] MAIN_STATE ; 36 | reg [47:0] CMD ; 37 | wire[47:0] CMD17 = { 8'h51, _Read_Sec_Addr, 8'hff};//读取单个数据块(SDHC 512bytes) 38 | wire[47:0] CMD18 = { 8'h52, _Read_Sec_Addr, 8'hff}; 39 | wire[47:0] CMD12 = { 8'h4c, 32'd0, 8'hff}; 40 | reg [15:0] Time_Cnt ; 41 | reg [5:0] Send_Cnt ; 42 | reg [5:0] Recv_Cnt ; 43 | reg [5:0] Recv_Cnt_II ;//bit counter 44 | reg [7:0] Recv_Cnt_III ;//words counter 45 | reg DAT_VALID_EN ; 46 | reg DAT_valid ; 47 | reg [39:0] DAT ;//移位寄存器 48 | reg [31:0] DAT_32B ;//暂存32bit数据然后写入SD_fifo 49 | wire[9:0] wrusedw ; 50 | reg [31:0] data ; 51 | //reg [31:0] WAV_FILE_LEN ;//文件大小字节 52 | reg wrreq ; 53 | reg First_Frame ; 54 | SD_fifo SD_fifo_U1( 55 | .data(data), 56 | .rdclk(FIFO_RD_CLK), 57 | .rdreq(FIFO_RD_EN), 58 | .wrclk(SD_SCLK_REF), 59 | .wrreq(wrreq), 60 | .q(q), 61 | .rdempty(), 62 | .wrusedw(wrusedw), 63 | .aclr(~rst_n) 64 | ); 65 | /**************************************************************************** 66 | * Generate DAT_valid signal 67 | * 68 | * In SPI mode device always response with R1 or R7 and the MSB always zero. 69 | * This response always in 1(called R1) or 5(called R7) bytes. 70 | *****************************************************************************/ 71 | always@(posedge SD_SCLK_REF or negedge rst_n) 72 | begin 73 | if(!rst_n)begin 74 | DAT_VALID_EN <= 0; 75 | DAT_valid <= 0; 76 | Recv_Cnt <= 6'd0; 77 | end 78 | else if(SD_MISO == 0 && DAT_VALID_EN == 0) 79 | begin 80 | DAT_VALID_EN <= 1; 81 | DAT_valid <= 0; 82 | Recv_Cnt <= 6'd0; 83 | end 84 | else if(DAT_VALID_EN == 1) 85 | if(Recv_Cnt < 8-1-1) 86 | begin 87 | Recv_Cnt <= Recv_Cnt+6'd1; 88 | DAT_valid <= 0; 89 | end 90 | else 91 | begin 92 | Recv_Cnt <= 6'd0; 93 | DAT_VALID_EN <= 0; 94 | DAT_valid <= 1; 95 | end 96 | else 97 | begin 98 | DAT_valid <= 0; 99 | Recv_Cnt <= 6'd0; 100 | DAT_VALID_EN <= 0; 101 | end 102 | end 103 | /**************************************************************************** 104 | * 接收前40个数据bit,返回R1(8bit)时取DAT[7:0],返回R7(8bit + 32bit)时取DAT[39:0] 105 | *****************************************************************************/ 106 | always@(posedge SD_SCLK_REF) 107 | begin 108 | DAT[0] <= SD_MISO; 109 | DAT[39:1] <= DAT[38:0]; 110 | end 111 | /******************************************************************** 112 | * main state mechine 113 | * send CMD18 recv -> 0 114 | *********************************************************************/ 115 | always@(negedge SD_SCLK_REF or negedge rst_n) 116 | begin 117 | if(!rst_n) 118 | begin 119 | MAIN_STATE <= 4'd0; 120 | Time_Cnt <= 16'd0; 121 | Send_Cnt <= 6'd0; 122 | error <= 1'd0; 123 | Recv_Cnt_II <= 6'd0; 124 | Recv_Cnt_III<= 8'd0; 125 | wrreq <= 1'd0; 126 | SD_MOSI <= 1'd1; 127 | SD_CS <= 1'd1; 128 | _Read_Sec_Addr <= Read_Sec_Addr; 129 | First_Frame <= 1'd0; 130 | FIFO_PREFETCHED<=1'd0; 131 | end 132 | else 133 | begin 134 | case(MAIN_STATE) 135 | 4'd0://等待SD卡初始化完成 且 SD_fifo小于一半 136 | begin 137 | if(SD_Read_EN==1 && wrusedw < 1024-128-10)begin 138 | MAIN_STATE <= MAIN_STATE + 4'd1; 139 | CMD <= CMD17;//发送CMD需要3个状态,此处为第一个状态 140 | end 141 | else 142 | MAIN_STATE <= MAIN_STATE; 143 | wrreq <= 1'd0;//清零 144 | end 145 | 4'd1://延时一段时间并初始化寄存器 146 | begin 147 | if(Time_Cnt >= 15) 148 | begin 149 | SD_CS <= 0; 150 | SD_MOSI <= CMD[47]; 151 | CMD <= {CMD[46:0],1'd1}; 152 | Time_Cnt <= 16'd0; 153 | Send_Cnt <= 6'd0; 154 | MAIN_STATE <= MAIN_STATE + 4'd1; 155 | end 156 | else 157 | begin 158 | Time_Cnt <= Time_Cnt + 16'd1; 159 | SD_MOSI <= 1'd1; 160 | SD_CS <= 1'd1; 161 | MAIN_STATE <= MAIN_STATE; 162 | end 163 | end 164 | 4'd2://Send CMD17 165 | begin 166 | if(Send_Cnt >= 6'd48 - 1'd1) 167 | begin 168 | Send_Cnt <= 6'd0; 169 | SD_MOSI <= 1; 170 | MAIN_STATE <= MAIN_STATE + 4'd1; 171 | end 172 | else 173 | begin 174 | Send_Cnt <= Send_Cnt + 6'd1; 175 | SD_MOSI <= CMD[47]; 176 | CMD <= {CMD[46:0],1'd1}; 177 | MAIN_STATE <= MAIN_STATE; 178 | end 179 | end 180 | 4'd3://wait DAT_valid == 1; 181 | begin 182 | if(DAT_valid == 1&&DAT[7:0] == 8'h00) 183 | begin //成功接收到0x00 184 | MAIN_STATE <= MAIN_STATE + 4'd1; 185 | SD_CS <= 0; 186 | Time_Cnt <= 16'd0; 187 | end 188 | else if(DAT_valid == 1&&DAT[7:0] != 8'h00) 189 | begin 190 | SD_CS <= 1; 191 | MAIN_STATE <= 4'd15; //未收到0x00回应 失败 192 | Time_Cnt <= 16'd0; 193 | end 194 | else if(Time_Cnt <= 127) 195 | begin 196 | SD_CS <= 0; 197 | SD_MOSI <= 1; 198 | Time_Cnt <= Time_Cnt + 16'd1; 199 | end 200 | else 201 | begin 202 | Time_Cnt <= 16'd0; 203 | MAIN_STATE <= 4'd15; //回应超时 失败 204 | SD_CS <= 1; 205 | end 206 | 207 | end 208 | 4'd4://wait 0xfe 209 | begin 210 | if(DAT_VALID_EN==1) 211 | MAIN_STATE <= MAIN_STATE + 4'd1; 212 | else 213 | MAIN_STATE <= MAIN_STATE; 214 | end 215 | 4'd5://receive 32*128 bit and write to fifo 216 | begin 217 | if(Recv_Cnt_II >= 32-1 ) 218 | begin 219 | if(Recv_Cnt_III >= 128-1) 220 | begin 221 | // if(_Read_Sec_Addr < (WAV_FILE_LEN>>9)-1)begin 222 | // MAIN_STATE <= MAIN_STATE + 4'd1;//// 223 | // _Read_Sec_Addr <= _Read_Sec_Addr + 32'd1;end 224 | // else begin 225 | // MAIN_STATE <= 4'd0;//// 226 | // _Read_Sec_Addr <= Read_Sec_Addr; 227 | // end 228 | _Read_Sec_Addr <= _Read_Sec_Addr + 32'd1; 229 | MAIN_STATE <= MAIN_STATE + 4'd1;//// 230 | Recv_Cnt_III <= 8'd0; 231 | First_Frame <= 1; 232 | end 233 | else 234 | begin 235 | Recv_Cnt_III <= Recv_Cnt_III + 8'd1; 236 | MAIN_STATE <= MAIN_STATE ; 237 | end 238 | 239 | 240 | if(First_Frame==1||Recv_Cnt_III >=11)begin//避开WAV第一帧44字节描述符 241 | data <= {DAT_32B[22:15],DAT_32B[30:23],DAT_32B[6:0],DAT[0],DAT_32B[14:7]}; //FAT32小端模式;16bit内部两个字节之间交换 242 | wrreq <= 1'd1;//必须在下一状态清零 243 | end 244 | else if(First_Frame==0&&Recv_Cnt_III==10)//如果是第一帧第11个字 245 | begin 246 | WAV_FILE_LEN <= {DAT_32B[6:0],DAT[0],DAT_32B[14:7],DAT_32B[22:15],DAT_32B[30:23]};//FAT32小端模式 247 | end 248 | Recv_Cnt_II <= 6'd0; 249 | end 250 | else 251 | begin 252 | Recv_Cnt_II <= Recv_Cnt_II + 6'd1; 253 | DAT_32B[0] <= DAT[0]; 254 | DAT_32B[31:1] <= DAT_32B[30:0]; 255 | wrreq <= 1'd0;//清零 256 | MAIN_STATE <= MAIN_STATE; 257 | end 258 | end 259 | 4'd6://wait 16bit CRC 260 | begin 261 | wrreq <= 1'd0;//清零 262 | FIFO_PREFETCHED <= 1'd1; 263 | if(Recv_Cnt_III >= 16-1) 264 | begin 265 | Recv_Cnt_III <= 8'd0; 266 | MAIN_STATE <= 4'd0; 267 | end 268 | else 269 | Recv_Cnt_III <= Recv_Cnt_III + 8'd1; 270 | end 271 | 4'd15: 272 | begin 273 | error <= 1'd1; 274 | end 275 | endcase 276 | end 277 | end 278 | endmodule 279 | -------------------------------------------------------------------------------- /quartus/WAV_AUDIO_PLAYER_pdm_sdhc/rtl/PLL/pll_bb.v: -------------------------------------------------------------------------------- 1 | // megafunction wizard: %ALTPLL%VBB% 2 | // GENERATION: STANDARD 3 | // VERSION: WM1.0 4 | // MODULE: altpll 5 | 6 | // ============================================================ 7 | // File Name: pll.v 8 | // Megafunction Name(s): 9 | // altpll 10 | // 11 | // Simulation Library Files(s): 12 | // altera_mf 13 | // ============================================================ 14 | // ************************************************************ 15 | // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! 16 | // 17 | // 17.1.0 Build 590 10/25/2017 SJ Standard Edition 18 | // ************************************************************ 19 | 20 | //Copyright (C) 2017 Intel Corporation. All rights reserved. 21 | //Your use of Intel Corporation's design tools, logic functions 22 | //and other software and tools, and its AMPP partner logic 23 | //functions, and any output files from any of the foregoing 24 | //(including device programming or simulation files), and any 25 | //associated documentation or information are expressly subject 26 | //to the terms and conditions of the Intel Program License 27 | //Subscription Agreement, the Intel Quartus Prime License Agreement, 28 | //the Intel FPGA IP License Agreement, or other applicable license 29 | //agreement, including, without limitation, that your use is for 30 | //the sole purpose of programming logic devices manufactured by 31 | //Intel and sold by Intel or its authorized distributors. Please 32 | //refer to the applicable agreement for further details. 33 | 34 | module pll ( 35 | areset, 36 | inclk0, 37 | c0, 38 | c1, 39 | c2, 40 | locked); 41 | 42 | input areset; 43 | input inclk0; 44 | output c0; 45 | output c1; 46 | output c2; 47 | output locked; 48 | `ifndef ALTERA_RESERVED_QIS 49 | // synopsys translate_off 50 | `endif 51 | tri0 areset; 52 | `ifndef ALTERA_RESERVED_QIS 53 | // synopsys translate_on 54 | `endif 55 | 56 | endmodule 57 | 58 | // ============================================================ 59 | // CNX file retrieval info 60 | // ============================================================ 61 | // Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" 62 | // Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" 63 | // Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" 64 | // Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" 65 | // Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" 66 | // Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" 67 | // Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" 68 | // Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" 69 | // Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" 70 | // Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" 71 | // Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" 72 | // Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" 73 | // Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" 74 | // Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" 75 | // Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" 76 | // Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" 77 | // Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1" 78 | // Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1" 79 | // Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "1" 80 | // Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" 81 | // Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" 82 | // Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000" 83 | // Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "50.000000" 84 | // Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "10.000000" 85 | // Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "12.288000" 86 | // Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" 87 | // Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" 88 | // Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" 89 | // Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" 90 | // Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" 91 | // Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" 92 | // Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" 93 | // Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000" 94 | // Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" 95 | // Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" 96 | // Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" 97 | // Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" 98 | // Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" 99 | // Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" 100 | // Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" 101 | // Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1" 102 | // Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" 103 | // Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" 104 | // Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" 105 | // Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" 106 | // Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps" 107 | // Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps" 108 | // Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" 109 | // Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" 110 | // Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" 111 | // Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0" 112 | // Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1" 113 | // Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1" 114 | // Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "1" 115 | // Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" 116 | // Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "50.00000000" 117 | // Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "10.00000000" 118 | // Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "12.28800000" 119 | // Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1" 120 | // Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1" 121 | // Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "1" 122 | // Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" 123 | // Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" 124 | // Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz" 125 | // Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" 126 | // Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" 127 | // Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" 128 | // Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000" 129 | // Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000" 130 | // Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" 131 | // Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" 132 | // Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ps" 133 | // Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "ps" 134 | // Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" 135 | // Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1" 136 | // Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" 137 | // Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" 138 | // Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" 139 | // Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" 140 | // Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" 141 | // Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" 142 | // Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" 143 | // Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" 144 | // Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif" 145 | // Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" 146 | // Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" 147 | // Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" 148 | // Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" 149 | // Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" 150 | // Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" 151 | // Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" 152 | // Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" 153 | // Retrieval info: PRIVATE: SPREAD_USE STRING "0" 154 | // Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" 155 | // Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" 156 | // Retrieval info: PRIVATE: STICKY_CLK1 STRING "1" 157 | // Retrieval info: PRIVATE: STICKY_CLK2 STRING "1" 158 | // Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" 159 | // Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" 160 | // Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" 161 | // Retrieval info: PRIVATE: USE_CLK0 STRING "1" 162 | // Retrieval info: PRIVATE: USE_CLK1 STRING "1" 163 | // Retrieval info: PRIVATE: USE_CLK2 STRING "1" 164 | // Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" 165 | // Retrieval info: PRIVATE: USE_CLKENA1 STRING "0" 166 | // Retrieval info: PRIVATE: USE_CLKENA2 STRING "0" 167 | // Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" 168 | // Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" 169 | // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all 170 | // Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" 171 | // Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1" 172 | // Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" 173 | // Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1" 174 | // Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" 175 | // Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "5" 176 | // Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" 177 | // Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "1" 178 | // Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0" 179 | // Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "3125" 180 | // Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50" 181 | // Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "768" 182 | // Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0" 183 | // Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" 184 | // Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000" 185 | // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" 186 | // Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" 187 | // Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" 188 | // Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" 189 | // Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" 190 | // Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED" 191 | // Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" 192 | // Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" 193 | // Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" 194 | // Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" 195 | // Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" 196 | // Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" 197 | // Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" 198 | // Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" 199 | // Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED" 200 | // Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" 201 | // Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" 202 | // Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" 203 | // Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" 204 | // Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" 205 | // Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" 206 | // Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" 207 | // Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" 208 | // Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" 209 | // Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" 210 | // Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" 211 | // Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" 212 | // Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" 213 | // Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" 214 | // Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" 215 | // Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED" 216 | // Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED" 217 | // Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" 218 | // Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" 219 | // Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" 220 | // Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" 221 | // Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" 222 | // Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" 223 | // Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" 224 | // Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" 225 | // Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" 226 | // Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" 227 | // Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" 228 | // Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" 229 | // Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" 230 | // Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF" 231 | // Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" 232 | // Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" 233 | // Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset" 234 | // Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" 235 | // Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1" 236 | // Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2" 237 | // Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" 238 | // Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked" 239 | // Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0 240 | // Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 241 | // Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 242 | // Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 243 | // Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 244 | // Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2 245 | // Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0 246 | // Retrieval info: GEN_FILE: TYPE_NORMAL pll.v TRUE 247 | // Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE 248 | // Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE 249 | // Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE 250 | // Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE 251 | // Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.v FALSE 252 | // Retrieval info: GEN_FILE: TYPE_NORMAL pll_bb.v TRUE 253 | // Retrieval info: LIB_FILE: altera_mf 254 | // Retrieval info: CBX_MODULE_PREFIX: ON 255 | -------------------------------------------------------------------------------- /quartus/WAV_AUDIO_PLAYER_pdm_sdhc/rtl/PLL/pll.v: -------------------------------------------------------------------------------- 1 | // megafunction wizard: %ALTPLL% 2 | // GENERATION: STANDARD 3 | // VERSION: WM1.0 4 | // MODULE: altpll 5 | 6 | // ============================================================ 7 | // File Name: pll.v 8 | // Megafunction Name(s): 9 | // altpll 10 | // 11 | // Simulation Library Files(s): 12 | // altera_mf 13 | // ============================================================ 14 | // ************************************************************ 15 | // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! 16 | // 17 | // 17.1.0 Build 590 10/25/2017 SJ Standard Edition 18 | // ************************************************************ 19 | 20 | 21 | //Copyright (C) 2017 Intel Corporation. All rights reserved. 22 | //Your use of Intel Corporation's design tools, logic functions 23 | //and other software and tools, and its AMPP partner logic 24 | //functions, and any output files from any of the foregoing 25 | //(including device programming or simulation files), and any 26 | //associated documentation or information are expressly subject 27 | //to the terms and conditions of the Intel Program License 28 | //Subscription Agreement, the Intel Quartus Prime License Agreement, 29 | //the Intel FPGA IP License Agreement, or other applicable license 30 | //agreement, including, without limitation, that your use is for 31 | //the sole purpose of programming logic devices manufactured by 32 | //Intel and sold by Intel or its authorized distributors. Please 33 | //refer to the applicable agreement for further details. 34 | 35 | 36 | // synopsys translate_off 37 | `timescale 1 ps / 1 ps 38 | // synopsys translate_on 39 | module pll ( 40 | areset, 41 | inclk0, 42 | c0, 43 | c1, 44 | c2, 45 | locked); 46 | 47 | input areset; 48 | input inclk0; 49 | output c0; 50 | output c1; 51 | output c2; 52 | output locked; 53 | `ifndef ALTERA_RESERVED_QIS 54 | // synopsys translate_off 55 | `endif 56 | tri0 areset; 57 | `ifndef ALTERA_RESERVED_QIS 58 | // synopsys translate_on 59 | `endif 60 | 61 | wire [0:0] sub_wire2 = 1'h0; 62 | wire [4:0] sub_wire3; 63 | wire sub_wire7; 64 | wire sub_wire0 = inclk0; 65 | wire [1:0] sub_wire1 = {sub_wire2, sub_wire0}; 66 | wire [2:2] sub_wire6 = sub_wire3[2:2]; 67 | wire [1:1] sub_wire5 = sub_wire3[1:1]; 68 | wire [0:0] sub_wire4 = sub_wire3[0:0]; 69 | wire c0 = sub_wire4; 70 | wire c1 = sub_wire5; 71 | wire c2 = sub_wire6; 72 | wire locked = sub_wire7; 73 | 74 | altpll altpll_component ( 75 | .areset (areset), 76 | .inclk (sub_wire1), 77 | .clk (sub_wire3), 78 | .locked (sub_wire7), 79 | .activeclock (), 80 | .clkbad (), 81 | .clkena ({6{1'b1}}), 82 | .clkloss (), 83 | .clkswitch (1'b0), 84 | .configupdate (1'b0), 85 | .enable0 (), 86 | .enable1 (), 87 | .extclk (), 88 | .extclkena ({4{1'b1}}), 89 | .fbin (1'b1), 90 | .fbmimicbidir (), 91 | .fbout (), 92 | .fref (), 93 | .icdrclk (), 94 | .pfdena (1'b1), 95 | .phasecounterselect ({4{1'b1}}), 96 | .phasedone (), 97 | .phasestep (1'b1), 98 | .phaseupdown (1'b1), 99 | .pllena (1'b1), 100 | .scanaclr (1'b0), 101 | .scanclk (1'b0), 102 | .scanclkena (1'b1), 103 | .scandata (1'b0), 104 | .scandataout (), 105 | .scandone (), 106 | .scanread (1'b0), 107 | .scanwrite (1'b0), 108 | .sclkout0 (), 109 | .sclkout1 (), 110 | .vcooverrange (), 111 | .vcounderrange ()); 112 | defparam 113 | altpll_component.bandwidth_type = "AUTO", 114 | altpll_component.clk0_divide_by = 1, 115 | altpll_component.clk0_duty_cycle = 50, 116 | altpll_component.clk0_multiply_by = 1, 117 | altpll_component.clk0_phase_shift = "0", 118 | altpll_component.clk1_divide_by = 5, 119 | altpll_component.clk1_duty_cycle = 50, 120 | altpll_component.clk1_multiply_by = 1, 121 | altpll_component.clk1_phase_shift = "0", 122 | altpll_component.clk2_divide_by = 3125, 123 | altpll_component.clk2_duty_cycle = 50, 124 | altpll_component.clk2_multiply_by = 768, 125 | altpll_component.clk2_phase_shift = "0", 126 | altpll_component.compensate_clock = "CLK0", 127 | altpll_component.inclk0_input_frequency = 20000, 128 | altpll_component.intended_device_family = "Cyclone IV E", 129 | altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll", 130 | altpll_component.lpm_type = "altpll", 131 | altpll_component.operation_mode = "NORMAL", 132 | altpll_component.pll_type = "AUTO", 133 | altpll_component.port_activeclock = "PORT_UNUSED", 134 | altpll_component.port_areset = "PORT_USED", 135 | altpll_component.port_clkbad0 = "PORT_UNUSED", 136 | altpll_component.port_clkbad1 = "PORT_UNUSED", 137 | altpll_component.port_clkloss = "PORT_UNUSED", 138 | altpll_component.port_clkswitch = "PORT_UNUSED", 139 | altpll_component.port_configupdate = "PORT_UNUSED", 140 | altpll_component.port_fbin = "PORT_UNUSED", 141 | altpll_component.port_inclk0 = "PORT_USED", 142 | altpll_component.port_inclk1 = "PORT_UNUSED", 143 | altpll_component.port_locked = "PORT_USED", 144 | altpll_component.port_pfdena = "PORT_UNUSED", 145 | altpll_component.port_phasecounterselect = "PORT_UNUSED", 146 | altpll_component.port_phasedone = "PORT_UNUSED", 147 | altpll_component.port_phasestep = "PORT_UNUSED", 148 | altpll_component.port_phaseupdown = "PORT_UNUSED", 149 | altpll_component.port_pllena = "PORT_UNUSED", 150 | altpll_component.port_scanaclr = "PORT_UNUSED", 151 | altpll_component.port_scanclk = "PORT_UNUSED", 152 | altpll_component.port_scanclkena = "PORT_UNUSED", 153 | altpll_component.port_scandata = "PORT_UNUSED", 154 | altpll_component.port_scandataout = "PORT_UNUSED", 155 | altpll_component.port_scandone = "PORT_UNUSED", 156 | altpll_component.port_scanread = "PORT_UNUSED", 157 | altpll_component.port_scanwrite = "PORT_UNUSED", 158 | altpll_component.port_clk0 = "PORT_USED", 159 | altpll_component.port_clk1 = "PORT_USED", 160 | altpll_component.port_clk2 = "PORT_USED", 161 | altpll_component.port_clk3 = "PORT_UNUSED", 162 | altpll_component.port_clk4 = "PORT_UNUSED", 163 | altpll_component.port_clk5 = "PORT_UNUSED", 164 | altpll_component.port_clkena0 = "PORT_UNUSED", 165 | altpll_component.port_clkena1 = "PORT_UNUSED", 166 | altpll_component.port_clkena2 = "PORT_UNUSED", 167 | altpll_component.port_clkena3 = "PORT_UNUSED", 168 | altpll_component.port_clkena4 = "PORT_UNUSED", 169 | altpll_component.port_clkena5 = "PORT_UNUSED", 170 | altpll_component.port_extclk0 = "PORT_UNUSED", 171 | altpll_component.port_extclk1 = "PORT_UNUSED", 172 | altpll_component.port_extclk2 = "PORT_UNUSED", 173 | altpll_component.port_extclk3 = "PORT_UNUSED", 174 | altpll_component.self_reset_on_loss_lock = "OFF", 175 | altpll_component.width_clock = 5; 176 | 177 | 178 | endmodule 179 | 180 | // ============================================================ 181 | // CNX file retrieval info 182 | // ============================================================ 183 | // Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" 184 | // Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" 185 | // Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" 186 | // Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" 187 | // Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" 188 | // Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" 189 | // Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" 190 | // Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" 191 | // Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" 192 | // Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" 193 | // Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" 194 | // Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" 195 | // Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" 196 | // Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" 197 | // Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" 198 | // Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" 199 | // Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1" 200 | // Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1" 201 | // Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "1" 202 | // Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" 203 | // Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" 204 | // Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000" 205 | // Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "50.000000" 206 | // Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "10.000000" 207 | // Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "12.288000" 208 | // Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" 209 | // Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" 210 | // Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" 211 | // Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" 212 | // Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" 213 | // Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" 214 | // Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" 215 | // Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000" 216 | // Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" 217 | // Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" 218 | // Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" 219 | // Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" 220 | // Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" 221 | // Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" 222 | // Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" 223 | // Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1" 224 | // Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" 225 | // Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" 226 | // Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" 227 | // Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" 228 | // Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps" 229 | // Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps" 230 | // Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" 231 | // Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" 232 | // Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" 233 | // Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0" 234 | // Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1" 235 | // Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1" 236 | // Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "1" 237 | // Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" 238 | // Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "50.00000000" 239 | // Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "10.00000000" 240 | // Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "12.28800000" 241 | // Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1" 242 | // Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1" 243 | // Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "1" 244 | // Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" 245 | // Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" 246 | // Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz" 247 | // Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" 248 | // Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" 249 | // Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" 250 | // Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000" 251 | // Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000" 252 | // Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" 253 | // Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" 254 | // Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ps" 255 | // Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "ps" 256 | // Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" 257 | // Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1" 258 | // Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" 259 | // Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" 260 | // Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" 261 | // Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" 262 | // Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" 263 | // Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" 264 | // Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" 265 | // Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" 266 | // Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif" 267 | // Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" 268 | // Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" 269 | // Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" 270 | // Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" 271 | // Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" 272 | // Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" 273 | // Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" 274 | // Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" 275 | // Retrieval info: PRIVATE: SPREAD_USE STRING "0" 276 | // Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" 277 | // Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" 278 | // Retrieval info: PRIVATE: STICKY_CLK1 STRING "1" 279 | // Retrieval info: PRIVATE: STICKY_CLK2 STRING "1" 280 | // Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" 281 | // Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" 282 | // Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" 283 | // Retrieval info: PRIVATE: USE_CLK0 STRING "1" 284 | // Retrieval info: PRIVATE: USE_CLK1 STRING "1" 285 | // Retrieval info: PRIVATE: USE_CLK2 STRING "1" 286 | // Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" 287 | // Retrieval info: PRIVATE: USE_CLKENA1 STRING "0" 288 | // Retrieval info: PRIVATE: USE_CLKENA2 STRING "0" 289 | // Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" 290 | // Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" 291 | // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all 292 | // Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" 293 | // Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1" 294 | // Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" 295 | // Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1" 296 | // Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" 297 | // Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "5" 298 | // Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" 299 | // Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "1" 300 | // Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0" 301 | // Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "3125" 302 | // Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50" 303 | // Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "768" 304 | // Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0" 305 | // Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" 306 | // Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000" 307 | // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" 308 | // Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" 309 | // Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" 310 | // Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" 311 | // Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" 312 | // Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED" 313 | // Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" 314 | // Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" 315 | // Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" 316 | // Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" 317 | // Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" 318 | // Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" 319 | // Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" 320 | // Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" 321 | // Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED" 322 | // Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" 323 | // Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" 324 | // Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" 325 | // Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" 326 | // Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" 327 | // Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" 328 | // Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" 329 | // Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" 330 | // Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" 331 | // Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" 332 | // Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" 333 | // Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" 334 | // Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" 335 | // Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" 336 | // Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" 337 | // Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED" 338 | // Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED" 339 | // Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" 340 | // Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" 341 | // Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" 342 | // Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" 343 | // Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" 344 | // Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" 345 | // Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" 346 | // Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" 347 | // Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" 348 | // Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" 349 | // Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" 350 | // Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" 351 | // Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" 352 | // Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF" 353 | // Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" 354 | // Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" 355 | // Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset" 356 | // Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" 357 | // Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1" 358 | // Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2" 359 | // Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" 360 | // Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked" 361 | // Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0 362 | // Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 363 | // Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 364 | // Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 365 | // Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 366 | // Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2 367 | // Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0 368 | // Retrieval info: GEN_FILE: TYPE_NORMAL pll.v TRUE 369 | // Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE 370 | // Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE 371 | // Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE 372 | // Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE 373 | // Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.v FALSE 374 | // Retrieval info: GEN_FILE: TYPE_NORMAL pll_bb.v TRUE 375 | // Retrieval info: LIB_FILE: altera_mf 376 | // Retrieval info: CBX_MODULE_PREFIX: ON 377 | -------------------------------------------------------------------------------- /quartus/WAV_AUDIO_PLAYER_pdm_sdhc/rtl/SDCard_ip/SD_initial.v.bak: -------------------------------------------------------------------------------- 1 | /**************************************************************************** 2 | * Name: SDv2 Card initial 3 | * Origin: 171012 4 | * Author: Helrori 5 | *****************************************************************************/ 6 | module SD_initial( 7 | 8 | input rst_n, 9 | input SD_SCLK_REF,//100KHZ 10 | //SD Card Interface 11 | input SD_MISO, 12 | output reg SD_CS, 13 | output reg SD_MOSI, 14 | output SD_SCLK, 15 | 16 | output reg [39:0]DAT, 17 | output reg INIT_DONE, 18 | output reg [7:0]STATE, 19 | output reg DAT_valid 20 | ); 21 | reg [47:0] CMD; 22 | reg [31:0] Time_Cnt; 23 | reg [5:0] Recv_Cnt; 24 | reg [5:0] Send_Cnt; 25 | reg [5:0] Recv_Dat_Len; 26 | reg SD_SCLK_OUTPUT_EN; 27 | reg DAT_VALID_EN; 28 | assign SD_SCLK = (SD_SCLK_OUTPUT_EN)?SD_SCLK_REF:1; 29 | parameter CMD0 = { 8'h40, 32'd0, 8'h95 }; 30 | parameter CMD8 = { 8'h48, 16'd0, 8'h01, 8'haa, 8'h87 }; 31 | parameter CMD55 = { 8'h77, 32'd0, 8'hff }; 32 | parameter ACMD41 = { 8'h69, 8'h40, 24'd0, 8'hff }; 33 | parameter CMD58 = { 8'h7A, 32'd0, 8'h01 }; 34 | parameter CMD17 = { 8'h51, 8'h00, 8'h00, 8'h00, 8'h00, 8'hff};// 35 | /**************************************************************************** 36 | * Generate DAT_valid signal 37 | * 38 | * In SPI mode device always response with R1 or R7 and the MSB always zero. 39 | * This response always in 1(called R1) or 5(called R7) bytes. 40 | *****************************************************************************/ 41 | always@(posedge SD_SCLK_REF or negedge rst_n) 42 | begin 43 | if(!rst_n)begin 44 | DAT_VALID_EN <= 0; 45 | DAT_valid <= 0; 46 | Recv_Cnt <= 6'd0; 47 | end 48 | else if(SD_MISO == 0 && DAT_VALID_EN == 0) 49 | begin 50 | DAT_VALID_EN <= 1; 51 | DAT_valid <= 0; 52 | Recv_Cnt <= 6'd0; 53 | end 54 | else if(DAT_VALID_EN == 1) 55 | if(Recv_Cnt < Recv_Dat_Len-1-1)//////////////////Recv_Dat_Len bit后DAT_valid置1 56 | begin 57 | Recv_Cnt <= Recv_Cnt+6'd1; 58 | DAT_valid <= 0; 59 | end 60 | else 61 | begin 62 | Recv_Cnt <= 6'd0; 63 | DAT_VALID_EN <= 0; 64 | DAT_valid <= 1; 65 | end 66 | else 67 | begin 68 | DAT_valid <= 0; 69 | Recv_Cnt <= 6'd0; 70 | DAT_VALID_EN <= 0; 71 | end 72 | end 73 | /**************************************************************************** 74 | * 接收前40个数据bit,返回R1(8bit)时取DAT[7:0],返回R7(8bit + 32bit)时取DAT[39:0] 75 | *****************************************************************************/ 76 | always@(posedge SD_SCLK_REF) 77 | begin 78 | DAT[0] <= SD_MISO; 79 | DAT[39:1] <= DAT[38:0]; 80 | end 81 | /**************************************************************************** 82 | * Main STATE mechine 83 | * Send CDM0 return R1==8'h01 ? 84 | * Send CMD8 return R7 CHECK R1==8'h01 ? 85 | * Send CMD55 return R1==8'h01 ? 86 | * Send ACMD41 return R1==8'h00 ? 87 | * Send CMD58 return R3 88 | *****************************************************************************/ 89 | initial//初始化所有寄存器 90 | begin 91 | SD_CS <= 1; 92 | SD_MOSI <= 1; 93 | CMD <= CMD0; 94 | Time_Cnt <= 32'd0; 95 | SD_SCLK_OUTPUT_EN <= 0; 96 | Send_Cnt <= 6'd0; 97 | INIT_DONE <= 0; 98 | STATE <= 8'd0; 99 | end 100 | always@(negedge SD_SCLK_REF or negedge rst_n) 101 | begin 102 | if(!rst_n) 103 | begin 104 | SD_CS <= 1; 105 | SD_MOSI <= 1; 106 | CMD <= CMD0; 107 | Time_Cnt <= 32'd0; 108 | SD_SCLK_OUTPUT_EN <= 0; 109 | Send_Cnt <= 6'd0; 110 | INIT_DONE <= 0; 111 | STATE <= 8'd0; 112 | end 113 | else 114 | case(STATE) 115 | 0://初始化所有寄存器 116 | begin 117 | SD_CS <= 1; 118 | SD_MOSI <= 1; 119 | CMD <= CMD0; 120 | Time_Cnt <= 32'd0; 121 | SD_SCLK_OUTPUT_EN <= 0; 122 | Send_Cnt <= 6'd0; 123 | INIT_DONE <= 0; 124 | STATE <= STATE + 8'd1; 125 | end 126 | 1://delay 1ms without SD_SCLK 127 | begin 128 | if(Time_Cnt == 100-1)///////////////// 129 | begin 130 | Time_Cnt <= 32'd0; 131 | SD_SCLK_OUTPUT_EN <= 1; 132 | STATE <= STATE + 8'd1; 133 | end 134 | else 135 | Time_Cnt <= Time_Cnt +32'd1; 136 | end 137 | 2://send 100 SD_SCLK 138 | begin 139 | if(Time_Cnt == 100-1) 140 | begin 141 | Time_Cnt <= 32'd0; 142 | STATE <= STATE + 8'd1; 143 | end 144 | else 145 | Time_Cnt <= Time_Cnt +32'd1; 146 | end 147 | 3://选中SD卡准备好SD_MOSI数据，接收长度设置为8bit 148 | begin 149 | SD_CS <= 0;STATE <= STATE + 8'd1;SD_MOSI <= CMD[47];CMD <= {CMD[46:0],1'd1};Send_Cnt <= 6'd0;Recv_Dat_Len <= 8;////////!!!!!!!! 150 | end 151 | /*重复段*/ 152 | 4://Send CMD0{ 8'h40,32'd0,8'h95 } return R1==8'h01 153 | begin 154 | if(Send_Cnt >= 6'd48 - 1'd1) 155 | begin 156 | Send_Cnt <= 6'd0; 157 | SD_MOSI <= 1; 158 | STATE <= STATE + 8'd1; 159 | end 160 | else 161 | begin 162 | Send_Cnt <= Send_Cnt + 6'd1; 163 | SD_MOSI <= CMD[47]; 164 | CMD <= {CMD[46:0],1'd1}; 165 | STATE <= STATE; 166 | end 167 | end 168 | // 255: 169 | // begin 170 | // if(Time_Cnt <= 7-1) 171 | // Time_Cnt <= Time_Cnt + 32'd1; 172 | // else 173 | // begin 174 | // Time_Cnt <= 32'd0; 175 | // STATE <= 8'd5; 176 | // end 177 | // end 178 | 5://wait DAT_valid==1 179 | begin 180 | if(DAT_valid == 1&&DAT[7:0] == 8'h01) 181 | begin //成功接收到0x01 182 | STATE <= STATE + 8'd1; 183 | SD_CS <= 1; 184 | Time_Cnt <= 32'd0; 185 | end 186 | else if(DAT_valid == 1&&DAT[7:0] != 8'h01) 187 | begin 188 | // CMD <= { 8'h40,32'd0,8'h95 }; 189 | SD_CS <= 1; 190 | STATE <= 8'd0; //从头开始 191 | Time_Cnt <= 32'd0; 192 | end 193 | else if(Time_Cnt <= 127) 194 | begin 195 | SD_CS <= 0; 196 | SD_MOSI <= 1; 197 | Time_Cnt <= Time_Cnt + 32'd1; 198 | end 199 | else 200 | begin 201 | Time_Cnt <= 32'd0; 202 | STATE <= 8'd2;//回应超时 203 | CMD <= CMD0; 204 | SD_CS <= 1; 205 | end 206 | end 207 | 6://SD_CS拉高后给256个时钟 208 | begin 209 | if(Time_Cnt == 256-1) 210 | begin 211 | Time_Cnt <= 32'd0; 212 | CMD <= CMD8; 213 | STATE <= STATE + 8'd1; 214 | end 215 | else 216 | Time_Cnt <= Time_Cnt + 32'd1; 217 | end 218 | ////////Send CMD0 OVER!////////// 219 | 7://选中SD卡准备好SD_MOSI数据，接收长度设置为40bit 220 | begin 221 | SD_CS <= 0;STATE <= STATE + 8'd1;SD_MOSI <= CMD[47];CMD <= {CMD[46:0],1'd1};Send_Cnt <= 6'd0;Recv_Dat_Len <= 40;////////!!!!!!!! 222 | end 223 | /*重复段*/ 224 | 8: 225 | /********************************************************************************************************************************** 226 | Send CMD8{ 8'h48, 16'd0, 8'h01, 8'haa, 8'h87 } return {8'h R1,32'h CMD8 Argument}==R7==DAT[39:0] 227 | 228 | The lower 12 bits in the return value 0x1AA means that the 229 | card is SDC version 2 and it can work at voltage range of 2.7 to 3.6 volts. 230 | If not the case, the card should be rejected. 231 | ***********************************************************************************************************************************/ 232 | begin 233 | if(Send_Cnt >= 6'd48 - 1'd1) 234 | begin 235 | Send_Cnt <= 6'd0; 236 | SD_MOSI <= 1; 237 | STATE <= STATE + 8'd1; 238 | end 239 | else 240 | begin 241 | Send_Cnt <= Send_Cnt + 6'd1; 242 | SD_MOSI <= CMD[47]; 243 | CMD <= {CMD[46:0],1'd1}; 244 | STATE <= STATE; 245 | end 246 | 247 | end 248 | 9://wait DAT_valid==1;check if DAT[39:0]=={8'h01,16'h00,8'h01,8'haa}=={8'h R1,32'h CMD Argument}==R7 249 | begin 250 | if(DAT_valid == 1&&DAT[39:0]=={8'h01,16'h00,8'h01,8'haa}) 251 | begin 252 | STATE <= STATE + 8'd1; 253 | SD_CS <= 0; 254 | Time_Cnt <= 32'd0; 255 | end 256 | else if(DAT_valid == 1&&DAT[39:0]!={8'h01,16'h00,8'h01,8'haa}) 257 | begin //fail SDV1 CARD!! 258 | // CMD <= { 8'h40,32'd0,8'h95 }; 259 | SD_CS <= 1; 260 | STATE <= 8'd22; 261 | Time_Cnt <= 32'd0; 262 | end 263 | else if(Time_Cnt <= 127) 264 | begin 265 | SD_CS <= 0; 266 | SD_MOSI <= 1; 267 | Time_Cnt <= Time_Cnt + 32'd1; 268 | end 269 | else 270 | begin 271 | Time_Cnt <= 32'd0; 272 | STATE <= 8'd2;//回应超时 273 | CMD <= CMD0;SD_CS <= 1; 274 | end 275 | end 276 | 10://给8个时钟 277 | begin 278 | if(Time_Cnt == 8-1) 279 | begin 280 | Time_Cnt <= 32'd0; 281 | CMD <= CMD55; 282 | STATE <= STATE + 8'd1; 283 | end 284 | else 285 | Time_Cnt <= Time_Cnt + 32'd1; 286 | end 287 | ////////Send CMD8 OVER!//////// 288 | 11://选中SD卡准备好SD_MOSI数据，接收长度设置为8bit 289 | begin 290 | SD_CS <= 0;STATE <= STATE + 8'd1;SD_MOSI <= CMD[47];CMD <= {CMD[46:0],1'd1};Send_Cnt <= 6'd0;Recv_Dat_Len <= 6'd8;////////!!!!!!!! 291 | end 292 | /*重复段*/ 293 | 12://Send CMD55 294 | begin 295 | if(Send_Cnt >= 6'd48 - 1'd1) 296 | begin 297 | Send_Cnt <= 6'd0; 298 | SD_MOSI <= 1; 299 | STATE <= STATE + 8'd1; 300 | end 301 | else 302 | begin 303 | Send_Cnt <= Send_Cnt + 6'd1; 304 | SD_MOSI <= CMD[47]; 305 | CMD <= {CMD[46:0],1'd1}; 306 | STATE <= STATE; 307 | end 308 | 309 | end 310 | 13://CHECK CMD55 311 | begin 312 | 313 | if(DAT_valid == 1&&DAT[7:0]==8'h01) 314 | begin 315 | STATE <= STATE + 8'd1; 316 | SD_CS <= 0; 317 | CMD <= ACMD41; 318 | 319 | end 320 | else if(DAT_valid == 1&&DAT[7:0]!=8'h01) 321 | begin//fail 322 | // CMD <= { 8'h40,32'd0,8'h95 }; 323 | SD_CS <= 1; 324 | STATE <= 8'd0;//从头开始 325 | end 326 | else 327 | begin 328 | SD_CS <= 0; 329 | SD_MOSI <= 1; 330 | end 331 | 332 | end 333 | 14://Send ACMD41{ 8'h69, 8'h40, 24'd0,8'hff } 334 | begin 335 | SD_CS <= 0;STATE <= STATE + 8'd1;SD_MOSI <= CMD[47];CMD <= {CMD[46:0],1'd1};Send_Cnt <= 6'd0;Recv_Dat_Len <= 40;////////!!!!!!!! 336 | end 337 | 15://Send ACMD41{ 8'h69, 8'h40, 24'd0,8'hff } 338 | begin 339 | if(Send_Cnt >= 6'd48 - 1'd1) 340 | begin 341 | Send_Cnt <= 6'd0; 342 | SD_MOSI <= 1; 343 | STATE <= 8'd254; 344 | end 345 | else 346 | begin 347 | Send_Cnt <= Send_Cnt + 6'd1; 348 | SD_MOSI <= CMD[47]; 349 | CMD <= {CMD[46:0],1'd1}; 350 | STATE <= STATE; 351 | end 352 | 353 | end 354 | 254: 355 | begin 356 | if(Time_Cnt <= 6 -1) 357 | Time_Cnt <= Time_Cnt + 32'd1; 358 | else 359 | begin 360 | Time_Cnt <= 32'd0; 361 | STATE <= 8'd16; 362 | end 363 | end 364 | 16://check ACMD41 365 | begin 366 | if(DAT_valid == 1&&DAT[39:32]==8'h00) 367 | begin// 初始化完成 368 | STATE <= STATE + 8'd1; 369 | SD_CS <= 1; 370 | // CMD <= CMD58; 371 | end 372 | else if(DAT_valid == 1&&DAT[39:32]!=8'h00) 373 | begin//查询ACMD41 未完成初始化 374 | // CMD <= { 8'h77,32'd0,8'hff };//准备好CMD55 375 | SD_CS <= 1; 376 | STATE <= 8'd6;//重新发送CMD8 377 | end 378 | else 379 | begin 380 | SD_CS <= 0; 381 | SD_MOSI <= 1; 382 | end 383 | 384 | end 385 | 17://16->18 386 | begin 387 | STATE <= STATE + 8'd1; 388 | end 389 | 18: 390 | begin 391 | if(Time_Cnt == 280-1) 392 | begin 393 | Time_Cnt <= 32'd0; 394 | CMD <= CMD58;//准备好CMD58 395 | STATE <= STATE + 8'd1; 396 | end 397 | else 398 | Time_Cnt <= Time_Cnt + 32'd1; 399 | end 400 | 19: 401 | begin 402 | SD_CS <= 0;STATE <= STATE + 8'd1;Send_Cnt <= 6'd0;SD_MOSI <= CMD[47];CMD <= {CMD[46:0],1'd1};Recv_Dat_Len <= 40;////////!!!!!!!! 403 | end 404 | 20: 405 | begin 406 | if(Send_Cnt >= 6'd48 - 1'd1) 407 | begin 408 | Send_Cnt <= 6'd0; 409 | SD_MOSI <= 1; 410 | STATE <= STATE + 8'd1; 411 | end 412 | else 413 | begin 414 | Send_Cnt <= Send_Cnt + 6'd1; 415 | SD_MOSI <= CMD[47]; 416 | CMD <= {CMD[46:0],1'd1}; 417 | STATE <= STATE; 418 | end 419 | 420 | end 421 | 21: 422 | begin 423 | if(DAT_valid == 1&&DAT[39:24]==16'h00C0)//SDHC CARD 424 | begin// 425 | STATE <= STATE + 8'd2; 426 | SD_CS <= 1; 427 | // CMD <= { 8'h7A, 32'd0, 8'h01 };//准备好CMD58 428 | end 429 | else if(DAT_valid == 1&&DAT[39:24]!=16'h00C0)//NOT SDHC CARD 430 | begin// 431 | // CMD <= { 8'h77,32'd0,8'hff };//准备好CMD55 432 | SD_CS <= 0; 433 | STATE <= STATE + 8'd1;// 434 | end 435 | else 436 | begin 437 | SD_CS <= 0; 438 | SD_MOSI <= 1; 439 | end 440 | 441 | end 442 | 22: 443 | begin 444 | //SDV1 CARD(INIT_DONE==0) OR NOT SDHC CARD ,FAIL 445 | end 446 | 23 : 447 | begin 448 | INIT_DONE <= 1;//SDHC CARD init done 449 | end 450 | endcase 451 | end 452 | 453 | endmodule 454 | 455 | 456 | 457 | //`timescale 1ns / 1ps 458 | //////////////////////////////////////////////////////////////////////////////////// 459 | //// Module Name: SD_initial 460 | //////////////////////////////////////////////////////////////////////////////////// 461 | //module SD_initial( 462 | // 463 | // input rst_n, 464 | // input SD_SCLK_REF, 465 | // output reg SD_CS, 466 | // output reg SD_MOSI, 467 | // input SD_MISO, 468 | // output reg [47:0]DAT, 469 | // output INIT_DONE, 470 | // output reg [3:0] STATE, 471 | // output reg DAT_valid 472 | // 473 | //); 474 | //assign INIT_DONE=init; 475 | // 476 | //reg [7:0] CMD; 477 | // 478 | //reg [47:0] CMD8; 479 | // 480 | //reg [47:0] CMD55={8'h77,8'h00,8'h00,8'h00,8'h00,8'hff}; 481 | //reg [47:0] ACMD41={8'h69,8'h40,8'h00,8'h00,8'h00,8'hff}; 482 | // 483 | // 484 | //reg init; 485 | // 486 | //reg [9:0] counter=10'd0; 487 | //reg reset=1'b1; 488 | //reg [5:0] i; 489 | // 490 | // 491 | //parameter idle =4'd0; 492 | //parameter load_cmd40 =4'd1; 493 | //parameter send_40 =4'd2; 494 | //parameter send_00 =4'd3; 495 | //parameter send_95 =4'd4; 496 | //parameter wait_01 =4'd5; 497 | //parameter send_cmd48 =4'd6; 498 | //parameter send_00a =4'd7; 499 | //parameter waita =4'd8; 500 | //parameter init_done =4'd9; 501 | //parameter init_fail =4'd10; 502 | // 503 | //parameter waitb =4'd11; 504 | //parameter send_cmd55 =4'd12; 505 | //parameter send_ACMD41 =4'd13; 506 | //reg [9:0] cnt; 507 | // 508 | //reg [5:0]aa; 509 | ////reg DAT_valid; 510 | //reg en; 511 | // 512 | ////接收SD卡的数据 513 | //always @(posedge SD_SCLK_REF) 514 | //begin 515 | // DAT[0]<=SD_MISO; 516 | // DAT[47:1]<=DAT[46:0]; 517 | //end 518 | // 519 | ////产生DAT_valid信号 520 | //always @(posedge SD_SCLK_REF) 521 | //begin 522 | // if(!SD_MISO&&!en) begin //等待SD_MISO为低,SD_MISO为低,开始接收数据 523 | // DAT_valid<=1'b0; 524 | // aa<=1; 525 | // en<=1'b1; 526 | // end 527 | // else if(en) begin 528 | // if(aa<47) begin 529 | // aa<=aa+1'b1; 530 | // DAT_valid<=1'b0; 531 | // end 532 | // else begin 533 | // aa<=0; 534 | // en<=1'b0; 535 | // DAT_valid<=1'b1; //接收完第48bit后,DAT_valid信号开始有效 536 | // end 537 | // end 538 | // else begin 539 | // en<=1'b0; 540 | // aa<=0; 541 | // DAT_valid<=1'b0; 542 | // end 543 | //end 544 | // 545 | ////上电后延时计数，释放reset信号 546 | //always @(negedge SD_SCLK_REF) 547 | //begin 548 | // if(counter<10'd1023) begin 549 | // counter<=counter+1'b1; 550 | // reset<=1'b1; 551 | // end 552 | // else begin 553 | // reset<=1'b0; 554 | // end 555 | //end 556 | // 557 | ////SD卡初始化程序 558 | //always @(negedge SD_SCLK_REF) 559 | //begin 560 | // if(reset | ~rst_n) begin 561 | // if(counter<512) begin 562 | // SD_CS<=1'b0; //片选CS低电平选中SD卡 563 | // SD_MOSI<=1'b1; 564 | // init<=1'b0; 565 | // end 566 | // else begin 567 | // SD_CS<=1'b1; //片选CS高电平释放SD卡 568 | // SD_MOSI<=1'b1; 569 | // init<=1'b0; 570 | // end 571 | // end 572 | // else begin 573 | // case(STATE) 574 | // idle: begin // 0 575 | // init<=1'b0; 576 | // CMD<=8'h00; 577 | // SD_CS<=1'b1; 578 | // SD_MOSI<=1'b1; 579 | // STATE<=load_cmd40; 580 | // end 581 | // load_cmd40: begin //发送CMD0，命令字为40 1 582 | // init<=1'b0; 583 | // CMD<=8'h40; 584 | // SD_CS<=1'b1; 585 | // SD_MOSI<=1'b1; 586 | // STATE<=send_40; 587 | // end 588 | // send_40: begin // 2 589 | // init<=1'b0; 590 | // if(CMD!=8'hff) begin //如果CMD0还未发送完成 591 | // SD_CS<=1'b0; 592 | // SD_MOSI<=CMD[7]; 593 | // CMD<={CMD[6:0],1'b1}; 594 | // end 595 | // else begin 596 | // SD_CS<=1'b0; 597 | // SD_MOSI<=1'b0; 598 | // CMD<=8'h00; 599 | // STATE<=send_00; 600 | // i<=1; 601 | // end 602 | // end 603 | // send_00: begin //发送CMD0的32位的argument, 全0 3 604 | // init<=1'b0; 605 | // if(i<31) begin 606 | // i<=i+1'b1; 607 | // SD_CS<=1'b0; 608 | // SD_MOSI<=1'b0; 609 | // CMD<=8'h00; 610 | // STATE<=send_00; 611 | // end 612 | // else begin 613 | // i<=0; 614 | // SD_CS<=1'b0; 615 | // SD_MOSI<=1'b0; 616 | // CMD<=8'h95; 617 | // STATE<=send_95; 618 | // end 619 | // end 620 | // send_95: begin //发送last byte:CRC 95 4 621 | // init<=1'b0; 622 | // if(CMD!=8'h00) begin 623 | // SD_CS<=1'b0; 624 | // SD_MOSI<=CMD[7]; 625 | // CMD<={CMD[6:0],1'b0}; 626 | // end 627 | // else begin 628 | // SD_CS<=1'b0; 629 | // SD_MOSI<=1'b1; 630 | // CMD<=8'h00; 631 | // STATE<=wait_01; 632 | // end 633 | // end 634 | // wait_01:begin //等待SD卡回应0x01 5 635 | // init<=1'b0; 636 | // if(DAT_valid&&DAT[47:40]==8'h01) begin 637 | // SD_CS<=1'b1; 638 | // SD_MOSI<=1'b1; 639 | // CMD<=8'h48; 640 | // cnt<=0; 641 | // STATE<=waitb; 642 | // end 643 | // else if(DAT_valid&&DAT[47:40]!=8'h01) begin 644 | // SD_CS<=1'b1; 645 | // SD_MOSI<=1'b1; 646 | // CMD<=8'h48; 647 | // cnt<=0; 648 | // STATE<=idle; 649 | // end 650 | // else begin 651 | // SD_CS<=1'b0; 652 | // SD_MOSI<=1'b1; 653 | // CMD<=8'h00; 654 | // end 655 | // end 656 | // waitb: begin //等待一段时间 11 657 | // if(cnt<10'd1023) begin 658 | // SD_CS<=1'b1; 659 | // SD_MOSI<=1'b1; 660 | // CMD<=8'h48; 661 | // STATE<=waitb; 662 | // cnt<=cnt+1'b1; 663 | // CMD55<={8'h77,8'h00,8'h00,8'h00,8'h00,8'hff}; 664 | // ACMD41<={8'h69,8'h40,8'h00,8'h00,8'h00,8'hff}; 665 | // end 666 | // else begin 667 | // SD_CS<=1'b1; 668 | // SD_MOSI<=1'b1; 669 | // CMD<=8'h00; 670 | // CMD8<={8'h48,8'h00,8'h00,8'h01,8'haa,8'h87}; 671 | // cnt<=0; 672 | // STATE<=send_cmd48; 673 | // end 674 | // end 675 | // send_cmd48: begin //发送CMD8 6 676 | // if(CMD8!=48'd0) begin 677 | // SD_CS<=1'b0; 678 | // SD_MOSI<=CMD8[47]; 679 | // CMD8<={CMD8[46:0],1'b0}; 680 | // i<=0; 681 | // end 682 | // else begin 683 | // SD_CS<=1'b0; 684 | // SD_MOSI<=1'b1; 685 | // CMD8<={8'h48,8'h00,8'h00,8'h01,8'haa,8'h87}; 686 | // STATE<=waita; 687 | // cnt<=0; 688 | // i<=1; 689 | // end 690 | // end 691 | // waita: begin //等待CMD8应答, 8?? 692 | // i<=0; 693 | // SD_CS<=1'b0; 694 | // SD_MOSI<=1'b1; 695 | // if(DAT_valid&&DAT[19:16]==4'b0001) begin //SD2.0卡，　support 2.7V-3.6V supply voltage 696 | // STATE<=send_cmd55; 697 | // CMD55<={8'h77,8'h00,8'h00,8'h00,8'h00,8'hff}; 698 | // ACMD41<={8'h69,8'h40,8'h00,8'h00,8'h00,8'hff}; 699 | // end 700 | // else if(DAT_valid&&DAT[19:16]!=4'b0001) begin 701 | // STATE<=init_fail; 702 | // end 703 | // end 704 | // send_cmd55:begin //发送CMD55 12 ?? 705 | // if(CMD55!=48'd0)begin 706 | // SD_CS<=1'b0; 707 | // SD_MOSI<=CMD55[47]; 708 | // CMD55<={CMD55[46:0],1'b0}; 709 | // i<=0; 710 | // end 711 | // else begin 712 | // SD_CS<=1'b0; 713 | // SD_MOSI<=1'b1; 714 | // CMD55<=48'd0; 715 | // cnt<=0; 716 | // i<=1; 717 | // if(DAT_valid&&DAT[47:40]==8'h01) //等待应答信号01 718 | // STATE<=send_ACMD41; 719 | // else begin 720 | // if(cnt<10'd127) 721 | // cnt<=cnt+1'b1; 722 | // else begin 723 | // cnt<=10'd0; 724 | // STATE<=init_fail; 725 | // end 726 | // end 727 | // end 728 | // end //12->13 xxx 729 | // send_ACMD41: begin //发送ACMD41 13 730 | // if(ACMD41!=48'd0) begin 731 | // SD_CS<=1'b0; 732 | // SD_MOSI<=ACMD41[47]; 733 | // ACMD41<={ACMD41[46:0],1'b0}; 734 | // i<=0; 735 | // end 736 | // else begin 737 | // SD_CS<=1'b0; 738 | // SD_MOSI<=1'b1; 739 | // ACMD41<=48'd0; 740 | // cnt<=0; 741 | // i<=1; 742 | // if(DAT_valid&&DAT[47:40]==8'h00) 743 | // STATE<=init_done; 744 | // else begin 745 | // if(cnt<10'd127) 746 | // cnt<=cnt+1'b1; 747 | // else begin 748 | // cnt<=10'd0; 749 | // STATE<=init_fail; 750 | // end 751 | // end 752 | // end 753 | // end 754 | // init_done:begin init<=1'b1;SD_CS<=1'b1;SD_MOSI<=1'b1;cnt<=0;end //初始化完成 755 | // init_fail:begin init<=1'b0;SD_CS<=1'b1;SD_MOSI<=1'b1;cnt<=0;STATE<=waitb;end //初始化未成功,重新发送CMD8, CMD55 和CMD41 756 | // default: begin STATE<=idle; SD_CS<=1'b1; SD_MOSI<=1'b1;CMD<=8'h00;init<=1'b0;end 757 | // endcase 758 | // end 759 | //end 760 | // 761 | //endmodule 762 | -------------------------------------------------------------------------------- /quartus/WAV_AUDIO_PLAYER_pdm_sdhc/rtl/SDCard_ip/SD_initial.v: -------------------------------------------------------------------------------- 1 | /**************************************************************************** 2 | * Name : SDv2 Card initial 3 | * Origin : 171012 4 | * Important : 初始化SDHC卡为SPI模式. 5 | * Interface : 没有总线接口,也不建议添加接口. 6 | * Author : Helrori 7 | *****************************************************************************/ 8 | module SD_initial( 9 | 10 | input rst_n, 11 | input SD_SCLK_REF,//100KHZ 12 | //SD Card Interface 13 | input SD_MISO, 14 | output reg SD_CS, 15 | output reg SD_MOSI, 16 | output SD_SCLK, 17 | 18 | output reg [39:0]DAT, 19 | output reg INIT_DONE, 20 | output reg [7:0]STATE, 21 | output reg DAT_valid 22 | ); 23 | reg [47:0] CMD; 24 | reg [31:0] Time_Cnt; 25 | reg [5:0] Recv_Cnt; 26 | reg [5:0] Send_Cnt; 27 | reg [5:0] Recv_Dat_Len; 28 | reg SD_SCLK_OUTPUT_EN; 29 | reg DAT_VALID_EN; 30 | assign SD_SCLK = (SD_SCLK_OUTPUT_EN)?SD_SCLK_REF:1; 31 | parameter CMD0 = { 8'h40, 32'd0, 8'h95 }; 32 | parameter CMD8 = { 8'h48, 16'd0, 8'h01, 8'haa, 8'h87 }; 33 | parameter CMD55 = { 8'h77, 32'd0, 8'hff }; 34 | parameter ACMD41 = { 8'h69, 8'h40, 24'd0, 8'hff }; 35 | parameter CMD58 = { 8'h7A, 32'd0, 8'h01 }; 36 | parameter CMD17 = { 8'h51, 8'h00, 8'h00, 8'h00, 8'h00, 8'hff};// 37 | /**************************************************************************** 38 | * Generate DAT_valid signal 39 | * 40 | * In SPI mode device always response with R1 or R7 and the MSB always zero. 41 | * This response always in 1(called R1) or 5(called R7) bytes. 42 | *****************************************************************************/ 43 | always@(posedge SD_SCLK_REF or negedge rst_n) 44 | begin 45 | if(!rst_n)begin 46 | DAT_VALID_EN <= 0; 47 | DAT_valid <= 0; 48 | Recv_Cnt <= 6'd0; 49 | end 50 | else if(SD_MISO == 0 && DAT_VALID_EN == 0) 51 | begin 52 | DAT_VALID_EN <= 1; 53 | DAT_valid <= 0; 54 | Recv_Cnt <= 6'd0; 55 | end 56 | else if(DAT_VALID_EN == 1) 57 | if(Recv_Cnt < Recv_Dat_Len-1-1)//////////////////Recv_Dat_Len bit后DAT_valid置1 58 | begin 59 | Recv_Cnt <= Recv_Cnt+6'd1; 60 | DAT_valid <= 0; 61 | end 62 | else 63 | begin 64 | Recv_Cnt <= 6'd0; 65 | DAT_VALID_EN <= 0; 66 | DAT_valid <= 1; 67 | end 68 | else 69 | begin 70 | DAT_valid <= 0; 71 | Recv_Cnt <= 6'd0; 72 | DAT_VALID_EN <= 0; 73 | end 74 | end 75 | /**************************************************************************** 76 | * 接收前40个数据bit,返回R1(8bit)时取DAT[7:0],返回R7(8bit + 32bit)时取DAT[39:0] 77 | *****************************************************************************/ 78 | always@(posedge SD_SCLK_REF) 79 | begin 80 | DAT[0] <= SD_MISO; 81 | DAT[39:1] <= DAT[38:0]; 82 | end 83 | /**************************************************************************** 84 | * Main STATE mechine 85 | * Send CDM0 return R1==8'h01 ? 86 | * Send CMD8 return R7 CHECK R1==8'h01 ? 87 | * Send CMD55 return R1==8'h01 ? 88 | * Send ACMD41 return R1==8'h00 ? 89 | * Send CMD58 return R3 == R1+OCR[31:0] 90 | *****************************************************************************/ 91 | initial//初始化所有寄存器 92 | begin 93 | SD_CS <= 1; 94 | SD_MOSI <= 1; 95 | CMD <= CMD0; 96 | Time_Cnt <= 32'd0; 97 | SD_SCLK_OUTPUT_EN <= 0; 98 | Send_Cnt <= 6'd0; 99 | INIT_DONE <= 0; 100 | STATE <= 8'd0; 101 | end 102 | always@(negedge SD_SCLK_REF or negedge rst_n) 103 | begin 104 | if(!rst_n) 105 | begin 106 | SD_CS <= 1; 107 | SD_MOSI <= 1; 108 | CMD <= CMD0; 109 | Time_Cnt <= 32'd0; 110 | SD_SCLK_OUTPUT_EN <= 0; 111 | Send_Cnt <= 6'd0; 112 | INIT_DONE <= 0; 113 | STATE <= 8'd0; 114 | end 115 | else 116 | case(STATE) 117 | 0://初始化所有寄存器 118 | begin 119 | SD_CS <= 1; 120 | SD_MOSI <= 1; 121 | CMD <= CMD0; 122 | Time_Cnt <= 32'd0; 123 | SD_SCLK_OUTPUT_EN <= 0; 124 | Send_Cnt <= 6'd0; 125 | INIT_DONE <= 0; 126 | STATE <= STATE + 8'd1; 127 | end 128 | 1://delay 1ms without SD_SCLK 129 | begin 130 | if(Time_Cnt == 100-1)///////////////// 131 | begin 132 | Time_Cnt <= 32'd0; 133 | SD_SCLK_OUTPUT_EN <= 1; 134 | STATE <= STATE + 8'd1; 135 | end 136 | else 137 | Time_Cnt <= Time_Cnt +32'd1; 138 | end 139 | 2://send 100 SD_SCLK 140 | begin 141 | if(Time_Cnt == 100-1) 142 | begin 143 | Time_Cnt <= 32'd0; 144 | STATE <= STATE + 8'd1; 145 | end 146 | else 147 | Time_Cnt <= Time_Cnt +32'd1; 148 | end 149 | 3://选中SD卡准备好SD_MOSI数据，接收长度设置为8bit 150 | begin 151 | SD_CS <= 0;STATE <= STATE + 8'd1;SD_MOSI <= CMD[47];CMD <= {CMD[46:0],1'd1};Send_Cnt <= 6'd0;Recv_Dat_Len <= 8;////////!!!!!!!! 152 | end 153 | /*重复段*/ 154 | 4://Send CMD0{ 8'h40,32'd0,8'h95 } return R1==8'h01 155 | begin 156 | if(Send_Cnt >= 6'd48 - 1'd1) 157 | begin 158 | Send_Cnt <= 6'd0; 159 | SD_MOSI <= 1; 160 | STATE <= STATE + 8'd1; 161 | end 162 | else 163 | begin 164 | Send_Cnt <= Send_Cnt + 6'd1; 165 | SD_MOSI <= CMD[47]; 166 | CMD <= {CMD[46:0],1'd1}; 167 | STATE <= STATE; 168 | end 169 | end 170 | // 255: 171 | // begin 172 | // if(Time_Cnt <= 7-1) 173 | // Time_Cnt <= Time_Cnt + 32'd1; 174 | // else 175 | // begin 176 | // Time_Cnt <= 32'd0; 177 | // STATE <= 8'd5; 178 | // end 179 | // end 180 | 5://wait DAT_valid==1 181 | begin 182 | if(DAT_valid == 1&&DAT[7:0] == 8'h01) 183 | begin //成功接收到0x01 184 | STATE <= STATE + 8'd1; 185 | SD_CS <= 1; 186 | Time_Cnt <= 32'd0; 187 | end 188 | else if(DAT_valid == 1&&DAT[7:0] != 8'h01) 189 | begin 190 | // CMD <= { 8'h40,32'd0,8'h95 }; 191 | SD_CS <= 1; 192 | STATE <= 8'd0; //从头开始 193 | Time_Cnt <= 32'd0; 194 | end 195 | else if(Time_Cnt <= 127) 196 | begin 197 | SD_CS <= 0; 198 | SD_MOSI <= 1; 199 | Time_Cnt <= Time_Cnt + 32'd1; 200 | end 201 | else 202 | begin 203 | Time_Cnt <= 32'd0; 204 | STATE <= 8'd2;//回应超时 205 | CMD <= CMD0; 206 | SD_CS <= 1; 207 | end 208 | end 209 | 6://SD_CS拉高后给256个时钟 210 | begin 211 | if(Time_Cnt == 256-1) 212 | begin 213 | Time_Cnt <= 32'd0; 214 | CMD <= CMD8; 215 | STATE <= STATE + 8'd1; 216 | end 217 | else 218 | Time_Cnt <= Time_Cnt + 32'd1; 219 | end 220 | ////////Send CMD0 OVER!////////// 221 | 7://选中SD卡准备好SD_MOSI数据，接收长度设置为40bit 222 | begin 223 | SD_CS <= 0;STATE <= STATE + 8'd1;SD_MOSI <= CMD[47];CMD <= {CMD[46:0],1'd1};Send_Cnt <= 6'd0;Recv_Dat_Len <= 40;////////!!!!!!!! 224 | end 225 | /*重复段*/ 226 | 8: 227 | /********************************************************************************************************************************** 228 | Send CMD8{ 8'h48, 16'd0, 8'h01, 8'haa, 8'h87 } return {8'h R1,32'h CMD8 Argument}==R7==DAT[39:0] 229 | 230 | The lower 12 bits in the return value 0x1AA means that the 231 | card is SDC version 2 and it can work at voltage range of 2.7 to 3.6 volts. 232 | If not the case, the card should be rejected. 233 | ***********************************************************************************************************************************/ 234 | begin 235 | if(Send_Cnt >= 6'd48 - 1'd1) 236 | begin 237 | Send_Cnt <= 6'd0; 238 | SD_MOSI <= 1; 239 | STATE <= STATE + 8'd1; 240 | end 241 | else 242 | begin 243 | Send_Cnt <= Send_Cnt + 6'd1; 244 | SD_MOSI <= CMD[47]; 245 | CMD <= {CMD[46:0],1'd1}; 246 | STATE <= STATE; 247 | end 248 | 249 | end 250 | 9://wait DAT_valid==1;check if DAT[39:0]=={8'h01,16'h00,8'h01,8'haa}=={8'h R1,32'h CMD Argument}==R7 251 | begin 252 | if(DAT_valid == 1&&DAT[39:0]=={8'h01,16'h00,8'h01,8'haa}) 253 | begin 254 | STATE <= STATE + 8'd1; 255 | SD_CS <= 0; 256 | Time_Cnt <= 32'd0; 257 | end 258 | else if(DAT_valid == 1&&DAT[39:0]!={8'h01,16'h00,8'h01,8'haa}) 259 | begin //fail SDV1 CARD!! 260 | // CMD <= { 8'h40,32'd0,8'h95 }; 261 | SD_CS <= 1; 262 | STATE <= 8'd22; 263 | Time_Cnt <= 32'd0; 264 | end 265 | else if(Time_Cnt <= 127) 266 | begin 267 | SD_CS <= 0; 268 | SD_MOSI <= 1; 269 | Time_Cnt <= Time_Cnt + 32'd1; 270 | end 271 | else 272 | begin 273 | Time_Cnt <= 32'd0; 274 | STATE <= 8'd2;//回应超时 275 | CMD <= CMD0;SD_CS <= 1; 276 | end 277 | end 278 | 10://给8个时钟 279 | begin 280 | if(Time_Cnt == 8-1) 281 | begin 282 | Time_Cnt <= 32'd0; 283 | CMD <= CMD55; 284 | STATE <= STATE + 8'd1; 285 | end 286 | else 287 | Time_Cnt <= Time_Cnt + 32'd1; 288 | end 289 | ////////Send CMD8 OVER!//////// 290 | 11://选中SD卡准备好SD_MOSI数据，接收长度设置为8bit 291 | begin 292 | SD_CS <= 0;STATE <= STATE + 8'd1;SD_MOSI <= CMD[47];CMD <= {CMD[46:0],1'd1};Send_Cnt <= 6'd0;Recv_Dat_Len <= 6'd8;////////!!!!!!!! 293 | end 294 | /*重复段*/ 295 | 12://Send CMD55 296 | begin 297 | if(Send_Cnt >= 6'd48 - 1'd1) 298 | begin 299 | Send_Cnt <= 6'd0; 300 | SD_MOSI <= 1; 301 | STATE <= STATE + 8'd1; 302 | end 303 | else 304 | begin 305 | Send_Cnt <= Send_Cnt + 6'd1; 306 | SD_MOSI <= CMD[47]; 307 | CMD <= {CMD[46:0],1'd1}; 308 | STATE <= STATE; 309 | end 310 | 311 | end 312 | 13://CHECK CMD55 313 | begin 314 | 315 | if(DAT_valid == 1&&DAT[7:0]==8'h01) 316 | begin 317 | STATE <= STATE + 8'd1; 318 | SD_CS <= 0; 319 | CMD <= ACMD41; 320 | 321 | end 322 | else if(DAT_valid == 1&&DAT[7:0]!=8'h01) 323 | begin//fail 324 | // CMD <= { 8'h40,32'd0,8'h95 }; 325 | SD_CS <= 1; 326 | STATE <= 8'd0;//从头开始 327 | end 328 | else 329 | begin 330 | SD_CS <= 0; 331 | SD_MOSI <= 1; 332 | end 333 | 334 | end 335 | 14://Send ACMD41{ 8'h69, 8'h40, 24'd0,8'hff } 336 | begin 337 | SD_CS <= 0;STATE <= STATE + 8'd1;SD_MOSI <= CMD[47];CMD <= {CMD[46:0],1'd1};Send_Cnt <= 6'd0;Recv_Dat_Len <= 40;////////!!!!!!!! 338 | end 339 | 15://Send ACMD41{ 8'h69, 8'h40, 24'd0,8'hff } 340 | begin 341 | if(Send_Cnt >= 6'd48 - 1'd1) 342 | begin 343 | Send_Cnt <= 6'd0; 344 | SD_MOSI <= 1; 345 | STATE <= 8'd254; 346 | end 347 | else 348 | begin 349 | Send_Cnt <= Send_Cnt + 6'd1; 350 | SD_MOSI <= CMD[47]; 351 | CMD <= {CMD[46:0],1'd1}; 352 | STATE <= STATE; 353 | end 354 | 355 | end 356 | 254: 357 | begin 358 | if(Time_Cnt <= 6 -1) 359 | Time_Cnt <= Time_Cnt + 32'd1; 360 | else 361 | begin 362 | Time_Cnt <= 32'd0; 363 | STATE <= 8'd16; 364 | end 365 | end 366 | 16://check ACMD41 367 | begin 368 | if(DAT_valid == 1&&DAT[39:32]==8'h00) 369 | begin// 初始化完成 370 | STATE <= STATE + 8'd1; 371 | SD_CS <= 1; 372 | // CMD <= CMD58; 373 | end 374 | else if(DAT_valid == 1&&DAT[39:32]!=8'h00) 375 | begin//查询ACMD41 未完成初始化 376 | // CMD <= { 8'h77,32'd0,8'hff };//准备好CMD55 377 | SD_CS <= 1; 378 | STATE <= 8'd6;//重新发送CMD8 379 | end 380 | else 381 | begin 382 | SD_CS <= 0; 383 | SD_MOSI <= 1; 384 | end 385 | 386 | end 387 | 17://16->18 388 | begin 389 | STATE <= STATE + 8'd1; 390 | end 391 | 18: 392 | begin 393 | if(Time_Cnt == 280-1) 394 | begin 395 | Time_Cnt <= 32'd0; 396 | CMD <= CMD58;//准备好CMD58 397 | STATE <= STATE + 8'd1; 398 | end 399 | else 400 | Time_Cnt <= Time_Cnt + 32'd1; 401 | end 402 | 19: 403 | begin 404 | SD_CS <= 0;STATE <= STATE + 8'd1;Send_Cnt <= 6'd0;SD_MOSI <= CMD[47];CMD <= {CMD[46:0],1'd1};Recv_Dat_Len <= 40;////////!!!!!!!! 405 | end 406 | 20: 407 | begin 408 | if(Send_Cnt >= 6'd48 - 1'd1) 409 | begin 410 | Send_Cnt <= 6'd0; 411 | SD_MOSI <= 1; 412 | STATE <= STATE + 8'd1; 413 | end 414 | else 415 | begin 416 | Send_Cnt <= Send_Cnt + 6'd1; 417 | SD_MOSI <= CMD[47]; 418 | CMD <= {CMD[46:0],1'd1}; 419 | STATE <= STATE; 420 | end 421 | 422 | end 423 | 21: 424 | begin 425 | if(DAT_valid == 1&&DAT[39:24]==16'h00C0)//SDHC CARD 426 | begin// 427 | STATE <= STATE + 8'd2; 428 | SD_CS <= 1; 429 | // CMD <= { 8'h7A, 32'd0, 8'h01 };//准备好CMD58 430 | end 431 | else if(DAT_valid == 1&&DAT[39:24]!=16'h00C0)//NOT SDHC CARD 432 | begin// 433 | // CMD <= { 8'h77,32'd0,8'hff };//准备好CMD55 434 | SD_CS <= 0; 435 | STATE <= STATE + 8'd1;// 436 | end 437 | else 438 | begin 439 | SD_CS <= 0; 440 | SD_MOSI <= 1; 441 | end 442 | 443 | end 444 | 22: 445 | begin 446 | //SDV1 CARD(INIT_DONE==0) OR NOT SDHC CARD ,FAIL 447 | end 448 | 23 : 449 | begin 450 | INIT_DONE <= 1;//SDHC CARD init done 451 | end 452 | endcase 453 | end 454 | endmodule 455 | 456 | //`timescale 1ns / 1ps 457 | //////////////////////////////////////////////////////////////////////////////////// 458 | //// Module Name: SD_initial 459 | //////////////////////////////////////////////////////////////////////////////////// 460 | //module SD_initial( 461 | // 462 | // input rst_n, 463 | // input SD_SCLK_REF, 464 | // output reg SD_CS, 465 | // output reg SD_MOSI, 466 | // input SD_MISO, 467 | // output reg [47:0]DAT, 468 | // output INIT_DONE, 469 | // output reg [3:0] STATE, 470 | // output reg DAT_valid 471 | // 472 | //); 473 | //assign INIT_DONE=init; 474 | // 475 | //reg [7:0] CMD; 476 | // 477 | //reg [47:0] CMD8; 478 | // 479 | //reg [47:0] CMD55={8'h77,8'h00,8'h00,8'h00,8'h00,8'hff}; 480 | //reg [47:0] ACMD41={8'h69,8'h40,8'h00,8'h00,8'h00,8'hff}; 481 | // 482 | // 483 | //reg init; 484 | // 485 | //reg [9:0] counter=10'd0; 486 | //reg reset=1'b1; 487 | //reg [5:0] i; 488 | // 489 | // 490 | //parameter idle =4'd0; 491 | //parameter load_cmd40 =4'd1; 492 | //parameter send_40 =4'd2; 493 | //parameter send_00 =4'd3; 494 | //parameter send_95 =4'd4; 495 | //parameter wait_01 =4'd5; 496 | //parameter send_cmd48 =4'd6; 497 | //parameter send_00a =4'd7; 498 | //parameter waita =4'd8; 499 | //parameter init_done =4'd9; 500 | //parameter init_fail =4'd10; 501 | // 502 | //parameter waitb =4'd11; 503 | //parameter send_cmd55 =4'd12; 504 | //parameter send_ACMD41 =4'd13; 505 | //reg [9:0] cnt; 506 | // 507 | //reg [5:0]aa; 508 | ////reg DAT_valid; 509 | //reg en; 510 | // 511 | ////接收SD卡的数据 512 | //always @(posedge SD_SCLK_REF) 513 | //begin 514 | // DAT[0]<=SD_MISO; 515 | // DAT[47:1]<=DAT[46:0]; 516 | //end 517 | // 518 | ////产生DAT_valid信号 519 | //always @(posedge SD_SCLK_REF) 520 | //begin 521 | // if(!SD_MISO&&!en) begin //等待SD_MISO为低,SD_MISO为低,开始接收数据 522 | // DAT_valid<=1'b0; 523 | // aa<=1; 524 | // en<=1'b1; 525 | // end 526 | // else if(en) begin 527 | // if(aa<47) begin 528 | // aa<=aa+1'b1; 529 | // DAT_valid<=1'b0; 530 | // end 531 | // else begin 532 | // aa<=0; 533 | // en<=1'b0; 534 | // DAT_valid<=1'b1; //接收完第48bit后,DAT_valid信号开始有效 535 | // end 536 | // end 537 | // else begin 538 | // en<=1'b0; 539 | // aa<=0; 540 | // DAT_valid<=1'b0; 541 | // end 542 | //end 543 | // 544 | ////上电后延时计数，释放reset信号 545 | //always @(negedge SD_SCLK_REF) 546 | //begin 547 | // if(counter<10'd1023) begin 548 | // counter<=counter+1'b1; 549 | // reset<=1'b1; 550 | // end 551 | // else begin 552 | // reset<=1'b0; 553 | // end 554 | //end 555 | // 556 | ////SD卡初始化程序 557 | //always @(negedge SD_SCLK_REF) 558 | //begin 559 | // if(reset | ~rst_n) begin 560 | // if(counter<512) begin 561 | // SD_CS<=1'b0; //片选CS低电平选中SD卡 562 | // SD_MOSI<=1'b1; 563 | // init<=1'b0; 564 | // end 565 | // else begin 566 | // SD_CS<=1'b1; //片选CS高电平释放SD卡 567 | // SD_MOSI<=1'b1; 568 | // init<=1'b0; 569 | // end 570 | // end 571 | // else begin 572 | // case(STATE) 573 | // idle: begin // 0 574 | // init<=1'b0; 575 | // CMD<=8'h00; 576 | // SD_CS<=1'b1; 577 | // SD_MOSI<=1'b1; 578 | // STATE<=load_cmd40; 579 | // end 580 | // load_cmd40: begin //发送CMD0，命令字为40 1 581 | // init<=1'b0; 582 | // CMD<=8'h40; 583 | // SD_CS<=1'b1; 584 | // SD_MOSI<=1'b1; 585 | // STATE<=send_40; 586 | // end 587 | // send_40: begin // 2 588 | // init<=1'b0; 589 | // if(CMD!=8'hff) begin //如果CMD0还未发送完成 590 | // SD_CS<=1'b0; 591 | // SD_MOSI<=CMD[7]; 592 | // CMD<={CMD[6:0],1'b1}; 593 | // end 594 | // else begin 595 | // SD_CS<=1'b0; 596 | // SD_MOSI<=1'b0; 597 | // CMD<=8'h00; 598 | // STATE<=send_00; 599 | // i<=1; 600 | // end 601 | // end 602 | // send_00: begin //发送CMD0的32位的argument, 全0 3 603 | // init<=1'b0; 604 | // if(i<31) begin 605 | // i<=i+1'b1; 606 | // SD_CS<=1'b0; 607 | // SD_MOSI<=1'b0; 608 | // CMD<=8'h00; 609 | // STATE<=send_00; 610 | // end 611 | // else begin 612 | // i<=0; 613 | // SD_CS<=1'b0; 614 | // SD_MOSI<=1'b0; 615 | // CMD<=8'h95; 616 | // STATE<=send_95; 617 | // end 618 | // end 619 | // send_95: begin //发送last byte:CRC 95 4 620 | // init<=1'b0; 621 | // if(CMD!=8'h00) begin 622 | // SD_CS<=1'b0; 623 | // SD_MOSI<=CMD[7]; 624 | // CMD<={CMD[6:0],1'b0}; 625 | // end 626 | // else begin 627 | // SD_CS<=1'b0; 628 | // SD_MOSI<=1'b1; 629 | // CMD<=8'h00; 630 | // STATE<=wait_01; 631 | // end 632 | // end 633 | // wait_01:begin //等待SD卡回应0x01 5 634 | // init<=1'b0; 635 | // if(DAT_valid&&DAT[47:40]==8'h01) begin 636 | // SD_CS<=1'b1; 637 | // SD_MOSI<=1'b1; 638 | // CMD<=8'h48; 639 | // cnt<=0; 640 | // STATE<=waitb; 641 | // end 642 | // else if(DAT_valid&&DAT[47:40]!=8'h01) begin 643 | // SD_CS<=1'b1; 644 | // SD_MOSI<=1'b1; 645 | // CMD<=8'h48; 646 | // cnt<=0; 647 | // STATE<=idle; 648 | // end 649 | // else begin 650 | // SD_CS<=1'b0; 651 | // SD_MOSI<=1'b1; 652 | // CMD<=8'h00; 653 | // end 654 | // end 655 | // waitb: begin //等待一段时间 11 656 | // if(cnt<10'd1023) begin 657 | // SD_CS<=1'b1; 658 | // SD_MOSI<=1'b1; 659 | // CMD<=8'h48; 660 | // STATE<=waitb; 661 | // cnt<=cnt+1'b1; 662 | // CMD55<={8'h77,8'h00,8'h00,8'h00,8'h00,8'hff}; 663 | // ACMD41<={8'h69,8'h40,8'h00,8'h00,8'h00,8'hff}; 664 | // end 665 | // else begin 666 | // SD_CS<=1'b1; 667 | // SD_MOSI<=1'b1; 668 | // CMD<=8'h00; 669 | // CMD8<={8'h48,8'h00,8'h00,8'h01,8'haa,8'h87}; 670 | // cnt<=0; 671 | // STATE<=send_cmd48; 672 | // end 673 | // end 674 | // send_cmd48: begin //发送CMD8 6 675 | // if(CMD8!=48'd0) begin 676 | // SD_CS<=1'b0; 677 | // SD_MOSI<=CMD8[47]; 678 | // CMD8<={CMD8[46:0],1'b0}; 679 | // i<=0; 680 | // end 681 | // else begin 682 | // SD_CS<=1'b0; 683 | // SD_MOSI<=1'b1; 684 | // CMD8<={8'h48,8'h00,8'h00,8'h01,8'haa,8'h87}; 685 | // STATE<=waita; 686 | // cnt<=0; 687 | // i<=1; 688 | // end 689 | // end 690 | // waita: begin //等待CMD8应答, 8?? 691 | // i<=0; 692 | // SD_CS<=1'b0; 693 | // SD_MOSI<=1'b1; 694 | // if(DAT_valid&&DAT[19:16]==4'b0001) begin //SD2.0卡，　support 2.7V-3.6V supply voltage 695 | // STATE<=send_cmd55; 696 | // CMD55<={8'h77,8'h00,8'h00,8'h00,8'h00,8'hff}; 697 | // ACMD41<={8'h69,8'h40,8'h00,8'h00,8'h00,8'hff}; 698 | // end 699 | // else if(DAT_valid&&DAT[19:16]!=4'b0001) begin 700 | // STATE<=init_fail; 701 | // end 702 | // end 703 | // send_cmd55:begin //发送CMD55 12 ?? 704 | // if(CMD55!=48'd0)begin 705 | // SD_CS<=1'b0; 706 | // SD_MOSI<=CMD55[47]; 707 | // CMD55<={CMD55[46:0],1'b0}; 708 | // i<=0; 709 | // end 710 | // else begin 711 | // SD_CS<=1'b0; 712 | // SD_MOSI<=1'b1; 713 | // CMD55<=48'd0; 714 | // cnt<=0; 715 | // i<=1; 716 | // if(DAT_valid&&DAT[47:40]==8'h01) //等待应答信号01 717 | // STATE<=send_ACMD41; 718 | // else begin 719 | // if(cnt<10'd127) 720 | // cnt<=cnt+1'b1; 721 | // else begin 722 | // cnt<=10'd0; 723 | // STATE<=init_fail; 724 | // end 725 | // end 726 | // end 727 | // end //12->13 xxx 728 | // send_ACMD41: begin //发送ACMD41 13 729 | // if(ACMD41!=48'd0) begin 730 | // SD_CS<=1'b0; 731 | // SD_MOSI<=ACMD41[47]; 732 | // ACMD41<={ACMD41[46:0],1'b0}; 733 | // i<=0; 734 | // end 735 | // else begin 736 | // SD_CS<=1'b0; 737 | // SD_MOSI<=1'b1; 738 | // ACMD41<=48'd0; 739 | // cnt<=0; 740 | // i<=1; 741 | // if(DAT_valid&&DAT[47:40]==8'h00) 742 | // STATE<=init_done; 743 | // else begin 744 | // if(cnt<10'd127) 745 | // cnt<=cnt+1'b1; 746 | // else begin 747 | // cnt<=10'd0; 748 | // STATE<=init_fail; 749 | // end 750 | // end 751 | // end 752 | // end 753 | // init_done:begin init<=1'b1;SD_CS<=1'b1;SD_MOSI<=1'b1;cnt<=0;end //初始化完成 754 | // init_fail:begin init<=1'b0;SD_CS<=1'b1;SD_MOSI<=1'b1;cnt<=0;STATE<=waitb;end //初始化未成功,重新发送CMD8, CMD55 和CMD41 755 | // default: begin STATE<=idle; SD_CS<=1'b1; SD_MOSI<=1'b1;CMD<=8'h00;init<=1'b0;end 756 | // endcase 757 | // end 758 | //end 759 | // 760 | //endmodule 761 | --------------------------------------------------------------------------------