├── .vscode └── settings.json ├── Core └── Src │ └── system_stm32g0xx.c ├── Drivers └── CMSIS │ ├── Core │ ├── Include │ │ ├── cmsis_armcc.h │ │ ├── cmsis_armclang.h │ │ ├── cmsis_armclang_ltm.h │ │ ├── cmsis_compiler.h │ │ ├── cmsis_gcc.h │ │ ├── cmsis_iccarm.h │ │ ├── cmsis_version.h │ │ ├── core_armv81mml.h │ │ ├── core_armv8mbl.h │ │ ├── core_armv8mml.h │ │ ├── core_cm0.h │ │ ├── core_cm0plus.h │ │ ├── core_cm1.h │ │ ├── core_cm23.h │ │ ├── core_cm3.h │ │ ├── core_cm33.h │ │ ├── core_cm35p.h │ │ ├── core_cm4.h │ │ ├── core_cm7.h │ │ ├── core_sc000.h │ │ ├── core_sc300.h │ │ ├── mpu_armv7.h │ │ ├── mpu_armv8.h │ │ └── tz_context.h │ └── Template │ │ └── ARMv8-M │ │ ├── main_s.c │ │ └── tz_context.c │ ├── Device │ └── ST │ │ └── STM32G0xx │ │ ├── Include │ │ ├── stm32g030xx.h │ │ ├── stm32g031xx.h │ │ ├── stm32g041xx.h │ │ ├── stm32g050xx.h │ │ ├── stm32g051xx.h │ │ ├── stm32g061xx.h │ │ ├── stm32g070xx.h │ │ ├── stm32g071xx.h │ │ ├── stm32g081xx.h │ │ ├── stm32g0b0xx.h │ │ ├── stm32g0b1xx.h │ │ ├── stm32g0c1xx.h │ │ ├── stm32g0xx.h │ │ └── system_stm32g0xx.h │ │ ├── LICENSE.txt │ │ └── Source │ │ └── Templates │ │ ├── arm │ │ ├── startup_stm32g030xx.s │ │ ├── startup_stm32g031xx.s │ │ ├── startup_stm32g041xx.s │ │ ├── startup_stm32g050xx.s │ │ ├── startup_stm32g051xx.s │ │ ├── startup_stm32g061xx.s │ │ ├── startup_stm32g070xx.s │ │ ├── startup_stm32g071xx.s │ │ ├── startup_stm32g081xx.s │ │ ├── startup_stm32g0b0xx.s │ │ ├── startup_stm32g0b1xx.s │ │ └── startup_stm32g0c1xx.s │ │ ├── gcc │ │ ├── startup_stm32g030xx.s │ │ ├── startup_stm32g031xx.s │ │ ├── startup_stm32g041xx.s │ │ ├── startup_stm32g050xx.s │ │ ├── startup_stm32g051xx.s │ │ ├── startup_stm32g061xx.s │ │ ├── startup_stm32g070xx.s │ │ ├── startup_stm32g071xx.s │ │ ├── startup_stm32g081xx.s │ │ ├── startup_stm32g0b0xx.s │ │ ├── startup_stm32g0b1xx.s │ │ └── startup_stm32g0c1xx.s │ │ ├── iar │ │ ├── linker │ │ │ ├── stm32g030xx_flash.icf │ │ │ ├── stm32g030xx_sram.icf │ │ │ ├── stm32g031xx_flash.icf │ │ │ ├── stm32g031xx_sram.icf │ │ │ ├── stm32g041xx_flash.icf │ │ │ ├── stm32g041xx_sram.icf │ │ │ ├── stm32g050xx_flash.icf │ │ │ ├── stm32g050xx_sram.icf │ │ │ ├── stm32g051xx_flash.icf │ │ │ ├── stm32g051xx_sram.icf │ │ │ ├── stm32g061xx_flash.icf │ │ │ ├── stm32g061xx_sram.icf │ │ │ ├── stm32g070xx_flash.icf │ │ │ ├── stm32g070xx_sram.icf │ │ │ ├── stm32g071xx_flash.icf │ │ │ ├── stm32g071xx_sram.icf │ │ │ ├── stm32g081xx_flash.icf │ │ │ ├── stm32g081xx_sram.icf │ │ │ ├── stm32g0b0xx_flash.icf │ │ │ ├── stm32g0b0xx_sram.icf │ │ │ ├── stm32g0b1xx_flash.icf │ │ │ ├── stm32g0b1xx_sram.icf │ │ │ ├── stm32g0c1xx_flash.icf │ │ │ └── stm32g0c1xx_sram.icf │ │ ├── startup_stm32g030xx.s │ │ ├── startup_stm32g031xx.s │ │ ├── startup_stm32g041xx.s │ │ ├── startup_stm32g050xx.s │ │ ├── startup_stm32g051xx.s │ │ ├── startup_stm32g061xx.s │ │ ├── startup_stm32g070xx.s │ │ ├── startup_stm32g071xx.s │ │ ├── startup_stm32g081xx.s │ │ ├── startup_stm32g0b0xx.s │ │ ├── startup_stm32g0b1xx.s │ │ └── startup_stm32g0c1xx.s │ │ └── system_stm32g0xx.c │ ├── Include │ ├── cmsis_armcc.h │ ├── cmsis_armclang.h │ ├── cmsis_armclang_ltm.h │ ├── cmsis_compiler.h │ ├── cmsis_gcc.h │ ├── cmsis_iccarm.h │ ├── cmsis_version.h │ ├── core_armv81mml.h │ ├── core_armv8mbl.h │ ├── core_armv8mml.h │ ├── core_cm0.h │ ├── core_cm0plus.h │ ├── core_cm1.h │ ├── core_cm23.h │ ├── core_cm3.h │ ├── core_cm33.h │ ├── core_cm35p.h │ ├── core_cm4.h │ ├── core_cm7.h │ ├── core_sc000.h │ ├── core_sc300.h │ ├── mpu_armv7.h │ ├── mpu_armv8.h │ └── tz_context.h │ ├── LICENSE.txt │ └── docs │ └── General │ └── html │ └── LICENSE.txt ├── MDK-ARM ├── .vscode │ ├── c_cpp_properties.json │ ├── keil-assistant.log │ ├── settings.json │ └── uv4.log.lock ├── DebugConfig │ └── light_STM32G030F6Px_1.0.0.dbgconf ├── EventRecorderStub.scvd ├── RTE │ ├── Device │ │ └── STM32G030F6Px │ │ │ ├── startup_stm32g030xx.s │ │ │ └── system_stm32g0xx.c │ └── _light │ │ └── RTE_Components.h ├── light.uvguix.Defenver ├── light.uvoptx ├── light.uvprojx ├── light │ ├── adc.d │ ├── adc.o │ ├── delay.d │ ├── delay.o │ ├── dma.d │ ├── dma.o │ ├── gpio.d │ ├── gpio.o │ ├── lcd.d │ ├── lcd.o │ ├── lcd_init.d │ ├── lcd_init.o │ ├── light.axf │ ├── light.build_log.htm │ ├── light.hex │ ├── light.htm │ ├── light.lnp │ ├── light.map │ ├── light.sct │ ├── light_light.dep │ ├── main.d │ ├── main.o │ ├── osc.d │ ├── osc.o │ ├── spi.d │ ├── spi.o │ ├── startup_stm32g030xx.d │ ├── startup_stm32g030xx.o │ ├── sys.d │ ├── sys.o │ ├── system_stm32g0xx.d │ ├── system_stm32g0xx.o │ ├── timer.d │ ├── timer.o │ ├── uart.d │ └── uart.o ├── main.c ├── startup_stm32g030xx.lst └── startup_stm32g030xx.s ├── README.md ├── keilkill.bat └── user ├── adc.c ├── adc.h ├── delay.c ├── delay.h ├── dma.c ├── dma.h ├── gpio.c ├── gpio.h ├── lcd.c ├── lcd.h ├── lcd_font.h ├── lcd_init.c ├── lcd_init.h ├── osc.c ├── osc.h ├── per_conf.h ├── spi.c ├── spi.h ├── sys.c ├── sys.h ├── timer.c ├── timer.h ├── uart.c └── uart.h /.vscode/settings.json: -------------------------------------------------------------------------------- 1 | { 2 | "files.associations": { 3 | "gpio.h": "c" 4 | } 5 | } -------------------------------------------------------------------------------- /Drivers/CMSIS/Core/Include/cmsis_version.h: -------------------------------------------------------------------------------- 1 | /**************************************************************************//** 2 | * @file cmsis_version.h 3 | * @brief CMSIS Core(M) Version definitions 4 | * @version V5.0.3 5 | * @date 24. June 2019 6 | ******************************************************************************/ 7 | /* 8 | * Copyright (c) 2009-2019 ARM Limited. All rights reserved. 9 | * 10 | * SPDX-License-Identifier: Apache-2.0 11 | * 12 | * Licensed under the Apache License, Version 2.0 (the License); you may 13 | * not use this file except in compliance with the License. 14 | * You may obtain a copy of the License at 15 | * 16 | * www.apache.org/licenses/LICENSE-2.0 17 | * 18 | * Unless required by applicable law or agreed to in writing, software 19 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT 20 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21 | * See the License for the specific language governing permissions and 22 | * limitations under the License. 23 | */ 24 | 25 | #if defined ( __ICCARM__ ) 26 | #pragma system_include /* treat file as system include file for MISRA check */ 27 | #elif defined (__clang__) 28 | #pragma clang system_header /* treat file as system include file */ 29 | #endif 30 | 31 | #ifndef __CMSIS_VERSION_H 32 | #define __CMSIS_VERSION_H 33 | 34 | /* CMSIS Version definitions */ 35 | #define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */ 36 | #define __CM_CMSIS_VERSION_SUB ( 3U) /*!< [15:0] CMSIS Core(M) sub version */ 37 | #define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \ 38 | __CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */ 39 | #endif 40 | -------------------------------------------------------------------------------- /Drivers/CMSIS/Core/Include/tz_context.h: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * @file tz_context.h 3 | * @brief Context Management for Armv8-M TrustZone 4 | * @version V1.0.1 5 | * @date 10. January 2018 6 | ******************************************************************************/ 7 | /* 8 | * Copyright (c) 2017-2018 Arm Limited. All rights reserved. 9 | * 10 | * SPDX-License-Identifier: Apache-2.0 11 | * 12 | * Licensed under the Apache License, Version 2.0 (the License); you may 13 | * not use this file except in compliance with the License. 14 | * You may obtain a copy of the License at 15 | * 16 | * www.apache.org/licenses/LICENSE-2.0 17 | * 18 | * Unless required by applicable law or agreed to in writing, software 19 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT 20 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21 | * See the License for the specific language governing permissions and 22 | * limitations under the License. 23 | */ 24 | 25 | #if defined ( __ICCARM__ ) 26 | #pragma system_include /* treat file as system include file for MISRA check */ 27 | #elif defined (__clang__) 28 | #pragma clang system_header /* treat file as system include file */ 29 | #endif 30 | 31 | #ifndef TZ_CONTEXT_H 32 | #define TZ_CONTEXT_H 33 | 34 | #include 35 | 36 | #ifndef TZ_MODULEID_T 37 | #define TZ_MODULEID_T 38 | /// \details Data type that identifies secure software modules called by a process. 39 | typedef uint32_t TZ_ModuleId_t; 40 | #endif 41 | 42 | /// \details TZ Memory ID identifies an allocated memory slot. 43 | typedef uint32_t TZ_MemoryId_t; 44 | 45 | /// Initialize secure context memory system 46 | /// \return execution status (1: success, 0: error) 47 | uint32_t TZ_InitContextSystem_S (void); 48 | 49 | /// Allocate context memory for calling secure software modules in TrustZone 50 | /// \param[in] module identifies software modules called from non-secure mode 51 | /// \return value != 0 id TrustZone memory slot identifier 52 | /// \return value 0 no memory available or internal error 53 | TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module); 54 | 55 | /// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S 56 | /// \param[in] id TrustZone memory slot identifier 57 | /// \return execution status (1: success, 0: error) 58 | uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id); 59 | 60 | /// Load secure context (called on RTOS thread context switch) 61 | /// \param[in] id TrustZone memory slot identifier 62 | /// \return execution status (1: success, 0: error) 63 | uint32_t TZ_LoadContext_S (TZ_MemoryId_t id); 64 | 65 | /// Store secure context (called on RTOS thread context switch) 66 | /// \param[in] id TrustZone memory slot identifier 67 | /// \return execution status (1: success, 0: error) 68 | uint32_t TZ_StoreContext_S (TZ_MemoryId_t id); 69 | 70 | #endif // TZ_CONTEXT_H 71 | -------------------------------------------------------------------------------- /Drivers/CMSIS/Core/Template/ARMv8-M/main_s.c: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * @file main_s.c 3 | * @brief Code template for secure main function 4 | * @version V1.1.1 5 | * @date 10. January 2018 6 | ******************************************************************************/ 7 | /* 8 | * Copyright (c) 2013-2018 Arm Limited. All rights reserved. 9 | * 10 | * SPDX-License-Identifier: Apache-2.0 11 | * 12 | * Licensed under the Apache License, Version 2.0 (the License); you may 13 | * not use this file except in compliance with the License. 14 | * You may obtain a copy of the License at 15 | * 16 | * www.apache.org/licenses/LICENSE-2.0 17 | * 18 | * Unless required by applicable law or agreed to in writing, software 19 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT 20 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21 | * See the License for the specific language governing permissions and 22 | * limitations under the License. 23 | */ 24 | 25 | /* Use CMSE intrinsics */ 26 | #include 27 | 28 | #include "RTE_Components.h" 29 | #include CMSIS_device_header 30 | 31 | /* TZ_START_NS: Start address of non-secure application */ 32 | #ifndef TZ_START_NS 33 | #define TZ_START_NS (0x200000U) 34 | #endif 35 | 36 | /* typedef for non-secure callback functions */ 37 | typedef void (*funcptr_void) (void) __attribute__((cmse_nonsecure_call)); 38 | 39 | /* Secure main() */ 40 | int main(void) { 41 | funcptr_void NonSecure_ResetHandler; 42 | 43 | /* Add user setup code for secure part here*/ 44 | 45 | /* Set non-secure main stack (MSP_NS) */ 46 | __TZ_set_MSP_NS(*((uint32_t *)(TZ_START_NS))); 47 | 48 | /* Get non-secure reset handler */ 49 | NonSecure_ResetHandler = (funcptr_void)(*((uint32_t *)((TZ_START_NS) + 4U))); 50 | 51 | /* Start non-secure state software application */ 52 | NonSecure_ResetHandler(); 53 | 54 | /* Non-secure software does not return, this code is not executed */ 55 | while (1) { 56 | __NOP(); 57 | } 58 | } 59 | -------------------------------------------------------------------------------- /Drivers/CMSIS/Core/Template/ARMv8-M/tz_context.c: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * @file tz_context.c 3 | * @brief Context Management for Armv8-M TrustZone - Sample implementation 4 | * @version V1.1.1 5 | * @date 10. January 2018 6 | ******************************************************************************/ 7 | /* 8 | * Copyright (c) 2016-2018 Arm Limited. All rights reserved. 9 | * 10 | * SPDX-License-Identifier: Apache-2.0 11 | * 12 | * Licensed under the Apache License, Version 2.0 (the License); you may 13 | * not use this file except in compliance with the License. 14 | * You may obtain a copy of the License at 15 | * 16 | * www.apache.org/licenses/LICENSE-2.0 17 | * 18 | * Unless required by applicable law or agreed to in writing, software 19 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT 20 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21 | * See the License for the specific language governing permissions and 22 | * limitations under the License. 23 | */ 24 | 25 | #include "RTE_Components.h" 26 | #include CMSIS_device_header 27 | #include "tz_context.h" 28 | 29 | /// Number of process slots (threads may call secure library code) 30 | #ifndef TZ_PROCESS_STACK_SLOTS 31 | #define TZ_PROCESS_STACK_SLOTS 8U 32 | #endif 33 | 34 | /// Stack size of the secure library code 35 | #ifndef TZ_PROCESS_STACK_SIZE 36 | #define TZ_PROCESS_STACK_SIZE 256U 37 | #endif 38 | 39 | typedef struct { 40 | uint32_t sp_top; // stack space top 41 | uint32_t sp_limit; // stack space limit 42 | uint32_t sp; // current stack pointer 43 | } stack_info_t; 44 | 45 | static stack_info_t ProcessStackInfo [TZ_PROCESS_STACK_SLOTS]; 46 | static uint64_t ProcessStackMemory[TZ_PROCESS_STACK_SLOTS][TZ_PROCESS_STACK_SIZE/8U]; 47 | static uint32_t ProcessStackFreeSlot = 0xFFFFFFFFU; 48 | 49 | 50 | /// Initialize secure context memory system 51 | /// \return execution status (1: success, 0: error) 52 | __attribute__((cmse_nonsecure_entry)) 53 | uint32_t TZ_InitContextSystem_S (void) { 54 | uint32_t n; 55 | 56 | if (__get_IPSR() == 0U) { 57 | return 0U; // Thread Mode 58 | } 59 | 60 | for (n = 0U; n < TZ_PROCESS_STACK_SLOTS; n++) { 61 | ProcessStackInfo[n].sp = 0U; 62 | ProcessStackInfo[n].sp_limit = (uint32_t)&ProcessStackMemory[n]; 63 | ProcessStackInfo[n].sp_top = (uint32_t)&ProcessStackMemory[n] + TZ_PROCESS_STACK_SIZE; 64 | *((uint32_t *)ProcessStackMemory[n]) = n + 1U; 65 | } 66 | *((uint32_t *)ProcessStackMemory[--n]) = 0xFFFFFFFFU; 67 | 68 | ProcessStackFreeSlot = 0U; 69 | 70 | // Default process stack pointer and stack limit 71 | __set_PSPLIM((uint32_t)ProcessStackMemory); 72 | __set_PSP ((uint32_t)ProcessStackMemory); 73 | 74 | // Privileged Thread Mode using PSP 75 | __set_CONTROL(0x02U); 76 | 77 | return 1U; // Success 78 | } 79 | 80 | 81 | /// Allocate context memory for calling secure software modules in TrustZone 82 | /// \param[in] module identifies software modules called from non-secure mode 83 | /// \return value != 0 id TrustZone memory slot identifier 84 | /// \return value 0 no memory available or internal error 85 | __attribute__((cmse_nonsecure_entry)) 86 | TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module) { 87 | uint32_t slot; 88 | 89 | (void)module; // Ignore (fixed Stack size) 90 | 91 | if (__get_IPSR() == 0U) { 92 | return 0U; // Thread Mode 93 | } 94 | 95 | if (ProcessStackFreeSlot == 0xFFFFFFFFU) { 96 | return 0U; // No slot available 97 | } 98 | 99 | slot = ProcessStackFreeSlot; 100 | ProcessStackFreeSlot = *((uint32_t *)ProcessStackMemory[slot]); 101 | 102 | ProcessStackInfo[slot].sp = ProcessStackInfo[slot].sp_top; 103 | 104 | return (slot + 1U); 105 | } 106 | 107 | 108 | /// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S 109 | /// \param[in] id TrustZone memory slot identifier 110 | /// \return execution status (1: success, 0: error) 111 | __attribute__((cmse_nonsecure_entry)) 112 | uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id) { 113 | uint32_t slot; 114 | 115 | if (__get_IPSR() == 0U) { 116 | return 0U; // Thread Mode 117 | } 118 | 119 | if ((id == 0U) || (id > TZ_PROCESS_STACK_SLOTS)) { 120 | return 0U; // Invalid ID 121 | } 122 | 123 | slot = id - 1U; 124 | 125 | if (ProcessStackInfo[slot].sp == 0U) { 126 | return 0U; // Inactive slot 127 | } 128 | ProcessStackInfo[slot].sp = 0U; 129 | 130 | *((uint32_t *)ProcessStackMemory[slot]) = ProcessStackFreeSlot; 131 | ProcessStackFreeSlot = slot; 132 | 133 | return 1U; // Success 134 | } 135 | 136 | 137 | /// Load secure context (called on RTOS thread context switch) 138 | /// \param[in] id TrustZone memory slot identifier 139 | /// \return execution status (1: success, 0: error) 140 | __attribute__((cmse_nonsecure_entry)) 141 | uint32_t TZ_LoadContext_S (TZ_MemoryId_t id) { 142 | uint32_t slot; 143 | 144 | if ((__get_IPSR() == 0U) || ((__get_CONTROL() & 2U) == 0U)) { 145 | return 0U; // Thread Mode or using Main Stack for threads 146 | } 147 | 148 | if ((id == 0U) || (id > TZ_PROCESS_STACK_SLOTS)) { 149 | return 0U; // Invalid ID 150 | } 151 | 152 | slot = id - 1U; 153 | 154 | if (ProcessStackInfo[slot].sp == 0U) { 155 | return 0U; // Inactive slot 156 | } 157 | 158 | // Setup process stack pointer and stack limit 159 | __set_PSPLIM(ProcessStackInfo[slot].sp_limit); 160 | __set_PSP (ProcessStackInfo[slot].sp); 161 | 162 | return 1U; // Success 163 | } 164 | 165 | 166 | /// Store secure context (called on RTOS thread context switch) 167 | /// \param[in] id TrustZone memory slot identifier 168 | /// \return execution status (1: success, 0: error) 169 | __attribute__((cmse_nonsecure_entry)) 170 | uint32_t TZ_StoreContext_S (TZ_MemoryId_t id) { 171 | uint32_t slot; 172 | uint32_t sp; 173 | 174 | if ((__get_IPSR() == 0U) || ((__get_CONTROL() & 2U) == 0U)) { 175 | return 0U; // Thread Mode or using Main Stack for threads 176 | } 177 | 178 | if ((id == 0U) || (id > TZ_PROCESS_STACK_SLOTS)) { 179 | return 0U; // Invalid ID 180 | } 181 | 182 | slot = id - 1U; 183 | 184 | if (ProcessStackInfo[slot].sp == 0U) { 185 | return 0U; // Inactive slot 186 | } 187 | 188 | sp = __get_PSP(); 189 | if ((sp < ProcessStackInfo[slot].sp_limit) || 190 | (sp > ProcessStackInfo[slot].sp_top)) { 191 | return 0U; // SP out of range 192 | } 193 | ProcessStackInfo[slot].sp = sp; 194 | 195 | // Default process stack pointer and stack limit 196 | __set_PSPLIM((uint32_t)ProcessStackMemory); 197 | __set_PSP ((uint32_t)ProcessStackMemory); 198 | 199 | return 1U; // Success 200 | } 201 | -------------------------------------------------------------------------------- /Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g0xx.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32g0xx.h 4 | * @author MCD Application Team 5 | * @brief CMSIS STM32G0xx Device Peripheral Access Layer Header File. 6 | * 7 | * The file is the unique include file that the application programmer 8 | * is using in the C source code, usually in main.c. This file contains: 9 | * - Configuration section that allows to select: 10 | * - The STM32G0xx device used in the target application 11 | * - To use or not the peripherals drivers in application code(i.e. 12 | * code will be based on direct access to peripherals registers 13 | * rather than drivers API), this option is controlled by 14 | * "#define USE_HAL_DRIVER" 15 | * 16 | ****************************************************************************** 17 | * @attention 18 | * 19 | * Copyright (c) 2018-2021 STMicroelectronics. 20 | * All rights reserved. 21 | * 22 | * This software is licensed under terms that can be found in the LICENSE file 23 | * in the root directory of this software component. 24 | * If no LICENSE file comes with this software, it is provided AS-IS. 25 | * 26 | ****************************************************************************** 27 | */ 28 | /** @addtogroup CMSIS 29 | * @{ 30 | */ 31 | 32 | /** @addtogroup stm32g0xx 33 | * @{ 34 | */ 35 | 36 | #ifndef STM32G0xx_H 37 | #define STM32G0xx_H 38 | 39 | #ifdef __cplusplus 40 | extern "C" { 41 | #endif /* __cplusplus */ 42 | 43 | /** @addtogroup Library_configuration_section 44 | * @{ 45 | */ 46 | 47 | /** 48 | * @brief STM32 Family 49 | */ 50 | #if !defined (STM32G0) 51 | #define STM32G0 52 | #endif /* STM32G0 */ 53 | 54 | /* Uncomment the line below according to the target STM32G0 device used in your 55 | application 56 | */ 57 | 58 | #if !defined (STM32G071xx) && !defined (STM32G081xx) && !defined (STM32G070xx) \ 59 | && !defined (STM32G030xx) && !defined (STM32G031xx) && !defined (STM32G041xx) \ 60 | && !defined (STM32G0B0xx) && !defined (STM32G0B1xx) && !defined (STM32G0C1xx) \ 61 | && !defined (STM32G050xx) && !defined (STM32G051xx) && !defined (STM32G061xx) 62 | /* #define STM32G0B0xx */ /*!< STM32G0B0xx Devices */ 63 | /* #define STM32G0B1xx */ /*!< STM32G0B1xx Devices */ 64 | /* #define STM32G0C1xx */ /*!< STM32G0C1xx Devices */ 65 | /* #define STM32G070xx */ /*!< STM32G070xx Devices */ 66 | /* #define STM32G071xx */ /*!< STM32G071xx Devices */ 67 | /* #define STM32G081xx */ /*!< STM32G081xx Devices */ 68 | /* #define STM32G050xx */ /*!< STM32G050xx Devices */ 69 | /* #define STM32G051xx */ /*!< STM32G051xx Devices */ 70 | /* #define STM32G061xx */ /*!< STM32G061xx Devices */ 71 | /* #define STM32G030xx */ /*!< STM32G030xx Devices */ 72 | /* #define STM32G031xx */ /*!< STM32G031xx Devices */ 73 | /* #define STM32G041xx */ /*!< STM32G041xx Devices */ 74 | #endif 75 | 76 | /* Tip: To avoid modifying this file each time you need to switch between these 77 | devices, you can define the device in your toolchain compiler preprocessor. 78 | */ 79 | #if !defined (USE_HAL_DRIVER) 80 | /** 81 | * @brief Comment the line below if you will not use the peripherals drivers. 82 | In this case, these drivers will not be included and the application code will 83 | be based on direct access to peripherals registers 84 | */ 85 | /*#define USE_HAL_DRIVER */ 86 | #endif /* USE_HAL_DRIVER */ 87 | 88 | /** 89 | * @brief CMSIS Device version number $VERSION$ 90 | */ 91 | #define __STM32G0_CMSIS_VERSION_MAIN (0x01U) /*!< [31:24] main version */ 92 | #define __STM32G0_CMSIS_VERSION_SUB1 (0x04U) /*!< [23:16] sub1 version */ 93 | #define __STM32G0_CMSIS_VERSION_SUB2 (0x01U) /*!< [15:8] sub2 version */ 94 | #define __STM32G0_CMSIS_VERSION_RC (0x00U) /*!< [7:0] release candidate */ 95 | #define __STM32G0_CMSIS_VERSION ((__STM32G0_CMSIS_VERSION_MAIN << 24)\ 96 | |(__STM32G0_CMSIS_VERSION_SUB1 << 16)\ 97 | |(__STM32G0_CMSIS_VERSION_SUB2 << 8 )\ 98 | |(__STM32G0_CMSIS_VERSION_RC)) 99 | 100 | /** 101 | * @} 102 | */ 103 | 104 | /** @addtogroup Device_Included 105 | * @{ 106 | */ 107 | 108 | #if defined(STM32G0B1xx) 109 | #include "stm32g0b1xx.h" 110 | #elif defined(STM32G0C1xx) 111 | #include "stm32g0c1xx.h" 112 | #elif defined(STM32G0B0xx) 113 | #include "stm32g0b0xx.h" 114 | #elif defined(STM32G071xx) 115 | #include "stm32g071xx.h" 116 | #elif defined(STM32G081xx) 117 | #include "stm32g081xx.h" 118 | #elif defined(STM32G070xx) 119 | #include "stm32g070xx.h" 120 | #elif defined(STM32G031xx) 121 | #include "stm32g031xx.h" 122 | #elif defined(STM32G041xx) 123 | #include "stm32g041xx.h" 124 | #elif defined(STM32G030xx) 125 | #include "stm32g030xx.h" 126 | #elif defined(STM32G051xx) 127 | #include "stm32g051xx.h" 128 | #elif defined(STM32G061xx) 129 | #include "stm32g061xx.h" 130 | #elif defined(STM32G050xx) 131 | #include "stm32g050xx.h" 132 | #else 133 | #error "Please select first the target STM32G0xx device used in your application (in stm32g0xx.h file)" 134 | #endif 135 | 136 | /** 137 | * @} 138 | */ 139 | 140 | /** @addtogroup Exported_types 141 | * @{ 142 | */ 143 | typedef enum 144 | { 145 | RESET = 0, 146 | SET = !RESET 147 | } FlagStatus, ITStatus; 148 | 149 | typedef enum 150 | { 151 | DISABLE = 0, 152 | ENABLE = !DISABLE 153 | } FunctionalState; 154 | #define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) 155 | 156 | typedef enum 157 | { 158 | SUCCESS = 0, 159 | ERROR = !SUCCESS 160 | } ErrorStatus; 161 | 162 | /** 163 | * @} 164 | */ 165 | 166 | 167 | /** @addtogroup Exported_macros 168 | * @{ 169 | */ 170 | #define SET_BIT(REG, BIT) ((REG) |= (BIT)) 171 | 172 | #define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT)) 173 | 174 | #define READ_BIT(REG, BIT) ((REG) & (BIT)) 175 | 176 | #define CLEAR_REG(REG) ((REG) = (0x0)) 177 | 178 | #define WRITE_REG(REG, VAL) ((REG) = (VAL)) 179 | 180 | #define READ_REG(REG) ((REG)) 181 | 182 | #define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK))) 183 | 184 | /* Use of interrupt control for register exclusive access */ 185 | /* Atomic 32-bit register access macro to set one or several bits */ 186 | #define ATOMIC_SET_BIT(REG, BIT) \ 187 | do { \ 188 | uint32_t primask; \ 189 | primask = __get_PRIMASK(); \ 190 | __set_PRIMASK(1); \ 191 | SET_BIT((REG), (BIT)); \ 192 | __set_PRIMASK(primask); \ 193 | } while(0) 194 | 195 | /* Atomic 32-bit register access macro to clear one or several bits */ 196 | #define ATOMIC_CLEAR_BIT(REG, BIT) \ 197 | do { \ 198 | uint32_t primask; \ 199 | primask = __get_PRIMASK(); \ 200 | __set_PRIMASK(1); \ 201 | CLEAR_BIT((REG), (BIT)); \ 202 | __set_PRIMASK(primask); \ 203 | } while(0) 204 | 205 | /* Atomic 32-bit register access macro to clear and set one or several bits */ 206 | #define ATOMIC_MODIFY_REG(REG, CLEARMSK, SETMASK) \ 207 | do { \ 208 | uint32_t primask; \ 209 | primask = __get_PRIMASK(); \ 210 | __set_PRIMASK(1); \ 211 | MODIFY_REG((REG), (CLEARMSK), (SETMASK)); \ 212 | __set_PRIMASK(primask); \ 213 | } while(0) 214 | 215 | /* Atomic 16-bit register access macro to set one or several bits */ 216 | #define ATOMIC_SETH_BIT(REG, BIT) ATOMIC_SET_BIT(REG, BIT) \ 217 | 218 | /* Atomic 16-bit register access macro to clear one or several bits */ 219 | #define ATOMIC_CLEARH_BIT(REG, BIT) ATOMIC_CLEAR_BIT(REG, BIT) \ 220 | 221 | /* Atomic 16-bit register access macro to clear and set one or several bits */ 222 | #define ATOMIC_MODIFYH_REG(REG, CLEARMSK, SETMASK) ATOMIC_MODIFY_REG(REG, CLEARMSK, SETMASK) \ 223 | 224 | /*#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL)))*/ 225 | /** 226 | * @} 227 | */ 228 | 229 | #if defined (USE_HAL_DRIVER) 230 | #include "stm32g0xx_hal.h" 231 | #endif /* USE_HAL_DRIVER */ 232 | 233 | #ifdef __cplusplus 234 | } 235 | #endif /* __cplusplus */ 236 | 237 | #endif /* STM32G0xx_H */ 238 | /** 239 | * @} 240 | */ 241 | 242 | /** 243 | * @} 244 | */ 245 | 246 | 247 | 248 | 249 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 250 | -------------------------------------------------------------------------------- /Drivers/CMSIS/Device/ST/STM32G0xx/Include/system_stm32g0xx.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file system_stm32g0xx.h 4 | * @author MCD Application Team 5 | * @brief CMSIS Cortex-M0+ Device System Source File for STM32G0xx devices. 6 | ****************************************************************************** 7 | * @attention 8 | * 9 | * Copyright (c) 2018-2021 STMicroelectronics. 10 | * All rights reserved. 11 | * 12 | * This software is licensed under terms that can be found in the LICENSE file 13 | * in the root directory of this software component. 14 | * If no LICENSE file comes with this software, it is provided AS-IS. 15 | * 16 | ****************************************************************************** 17 | */ 18 | /** @addtogroup CMSIS 19 | * @{ 20 | */ 21 | 22 | /** @addtogroup stm32g0xx_system 23 | * @{ 24 | */ 25 | 26 | /** 27 | * @brief Define to prevent recursive inclusion 28 | */ 29 | #ifndef SYSTEM_STM32G0XX_H 30 | #define SYSTEM_STM32G0XX_H 31 | 32 | #ifdef __cplusplus 33 | extern "C" { 34 | #endif 35 | 36 | /** @addtogroup STM32G0xx_System_Includes 37 | * @{ 38 | */ 39 | 40 | /** 41 | * @} 42 | */ 43 | 44 | 45 | /** @addtogroup STM32G0xx_System_Exported_types 46 | * @{ 47 | */ 48 | /* This variable is updated in three ways: 49 | 1) by calling CMSIS function SystemCoreClockUpdate() 50 | 2) by calling HAL API function HAL_RCC_GetSysClockFreq() 51 | 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency 52 | Note: If you use this function to configure the system clock; then there 53 | is no need to call the 2 first functions listed above, since SystemCoreClock 54 | variable is updated automatically. 55 | */ 56 | extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ 57 | 58 | extern const uint32_t AHBPrescTable[16]; /*!< AHB prescalers table values */ 59 | extern const uint32_t APBPrescTable[8]; /*!< APB prescalers table values */ 60 | 61 | /** 62 | * @} 63 | */ 64 | 65 | /** @addtogroup STM32G0xx_System_Exported_Constants 66 | * @{ 67 | */ 68 | 69 | /** 70 | * @} 71 | */ 72 | 73 | /** @addtogroup STM32G0xx_System_Exported_Macros 74 | * @{ 75 | */ 76 | 77 | /** 78 | * @} 79 | */ 80 | 81 | /** @addtogroup STM32G0xx_System_Exported_Functions 82 | * @{ 83 | */ 84 | 85 | extern void SystemInit(void); 86 | extern void SystemCoreClockUpdate(void); 87 | /** 88 | * @} 89 | */ 90 | 91 | #ifdef __cplusplus 92 | } 93 | #endif 94 | 95 | #endif /*SYSTEM_STM32G0XX_H */ 96 | 97 | /** 98 | * @} 99 | */ 100 | 101 | /** 102 | * @} 103 | */ 104 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 105 | -------------------------------------------------------------------------------- /Drivers/CMSIS/Device/ST/STM32G0xx/LICENSE.txt: -------------------------------------------------------------------------------- 1 | This software component is provided to you as part of a software package and 2 | applicable license terms are in the Package_license file. If you received this 3 | software component outside of a package or without applicable license terms, 4 | the terms of the Apache-2.0 license shall apply. 5 | You may obtain a copy of the Apache-2.0 at: 6 | https://opensource.org/licenses/Apache-2.0 7 | -------------------------------------------------------------------------------- /Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/arm/startup_stm32g030xx.s: -------------------------------------------------------------------------------- 1 | ;****************************************************************************** 2 | ;* File Name : startup_stm32g030xx.s 3 | ;* Author : MCD Application Team 4 | ;* Description : STM32G030xx devices vector table for MDK-ARM toolchain. 5 | ;* This module performs: 6 | ;* - Set the initial SP 7 | ;* - Set the initial PC == Reset_Handler 8 | ;* - Set the vector table entries with the exceptions ISR address 9 | ;* - Branches to __main in the C library (which eventually 10 | ;* calls main()). 11 | ;* After Reset the CortexM0 processor is in Thread mode, 12 | ;* priority is Privileged, and the Stack is set to Main. 13 | ;* <<< Use Configuration Wizard in Context Menu >>> 14 | ;****************************************************************************** 15 | ;* @attention 16 | ;* 17 | ;* Copyright (c) 2018-2021 STMicroelectronics. 18 | ;* All rights reserved. 19 | ;* 20 | ;* This software is licensed under terms that can be found in the LICENSE file 21 | ;* in the root directory of this software component. 22 | ;* If no LICENSE file comes with this software, it is provided AS-IS. 23 | ;* 24 | ;****************************************************************************** 25 | ; Amount of memory (in bytes) allocated for Stack 26 | ; Tailor this value to your application needs 27 | ; Stack Configuration 28 | ; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> 29 | ; 30 | 31 | Stack_Size EQU 0x00000400 32 | 33 | AREA STACK, NOINIT, READWRITE, ALIGN=3 34 | Stack_Mem SPACE Stack_Size 35 | __initial_sp 36 | 37 | 38 | ; Heap Configuration 39 | ; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> 40 | ; 41 | 42 | Heap_Size EQU 0x00000200 43 | 44 | AREA HEAP, NOINIT, READWRITE, ALIGN=3 45 | __heap_base 46 | Heap_Mem SPACE Heap_Size 47 | __heap_limit 48 | 49 | PRESERVE8 50 | THUMB 51 | 52 | 53 | ; Vector Table Mapped to Address 0 at Reset 54 | AREA RESET, DATA, READONLY 55 | EXPORT __Vectors 56 | EXPORT __Vectors_End 57 | EXPORT __Vectors_Size 58 | 59 | __Vectors DCD __initial_sp ; Top of Stack 60 | DCD Reset_Handler ; Reset Handler 61 | DCD NMI_Handler ; NMI Handler 62 | DCD HardFault_Handler ; Hard Fault Handler 63 | DCD 0 ; Reserved 64 | DCD 0 ; Reserved 65 | DCD 0 ; Reserved 66 | DCD 0 ; Reserved 67 | DCD 0 ; Reserved 68 | DCD 0 ; Reserved 69 | DCD 0 ; Reserved 70 | DCD SVC_Handler ; SVCall Handler 71 | DCD 0 ; Reserved 72 | DCD 0 ; Reserved 73 | DCD PendSV_Handler ; PendSV Handler 74 | DCD SysTick_Handler ; SysTick Handler 75 | 76 | ; External Interrupts 77 | DCD WWDG_IRQHandler ; Window Watchdog 78 | DCD 0 ; Reserved 79 | DCD RTC_TAMP_IRQHandler ; RTC through EXTI Line 80 | DCD FLASH_IRQHandler ; FLASH 81 | DCD RCC_IRQHandler ; RCC 82 | DCD EXTI0_1_IRQHandler ; EXTI Line 0 and 1 83 | DCD EXTI2_3_IRQHandler ; EXTI Line 2 and 3 84 | DCD EXTI4_15_IRQHandler ; EXTI Line 4 to 15 85 | DCD 0 ; Reserved 86 | DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 87 | DCD DMA1_Channel2_3_IRQHandler ; DMA1 Channel 2 and Channel 3 88 | DCD DMA1_Ch4_5_DMAMUX1_OVR_IRQHandler ; DMA1 Channel 4 to Channel 5, DMAMUX1 overrun 89 | DCD ADC1_IRQHandler ; ADC1 90 | DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation 91 | DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare 92 | DCD 0 ; Reserved 93 | DCD TIM3_IRQHandler ; TIM3 94 | DCD 0 ; Reserved 95 | DCD 0 ; Reserved 96 | DCD TIM14_IRQHandler ; TIM14 97 | DCD 0 ; Reserved 98 | DCD TIM16_IRQHandler ; TIM16 99 | DCD TIM17_IRQHandler ; TIM17 100 | DCD I2C1_IRQHandler ; I2C1 101 | DCD I2C2_IRQHandler ; I2C2 102 | DCD SPI1_IRQHandler ; SPI1 103 | DCD SPI2_IRQHandler ; SPI2 104 | DCD USART1_IRQHandler ; USART1 105 | DCD USART2_IRQHandler ; USART2 106 | DCD 0 ; Reserved 107 | DCD 0 ; Reserved 108 | DCD 0 ; Reserved 109 | 110 | __Vectors_End 111 | 112 | __Vectors_Size EQU __Vectors_End - __Vectors 113 | 114 | AREA |.text|, CODE, READONLY 115 | 116 | ; Reset handler routine 117 | Reset_Handler PROC 118 | EXPORT Reset_Handler [WEAK] 119 | IMPORT __main 120 | IMPORT SystemInit 121 | LDR R0, =SystemInit 122 | BLX R0 123 | LDR R0, =__main 124 | BX R0 125 | ENDP 126 | 127 | ; Dummy Exception Handlers (infinite loops which can be modified) 128 | 129 | NMI_Handler PROC 130 | EXPORT NMI_Handler [WEAK] 131 | B . 132 | ENDP 133 | HardFault_Handler\ 134 | PROC 135 | EXPORT HardFault_Handler [WEAK] 136 | B . 137 | ENDP 138 | SVC_Handler PROC 139 | EXPORT SVC_Handler [WEAK] 140 | B . 141 | ENDP 142 | PendSV_Handler PROC 143 | EXPORT PendSV_Handler [WEAK] 144 | B . 145 | ENDP 146 | SysTick_Handler PROC 147 | EXPORT SysTick_Handler [WEAK] 148 | B . 149 | ENDP 150 | 151 | Default_Handler PROC 152 | 153 | EXPORT WWDG_IRQHandler [WEAK] 154 | EXPORT RTC_TAMP_IRQHandler [WEAK] 155 | EXPORT FLASH_IRQHandler [WEAK] 156 | EXPORT RCC_IRQHandler [WEAK] 157 | EXPORT EXTI0_1_IRQHandler [WEAK] 158 | EXPORT EXTI2_3_IRQHandler [WEAK] 159 | EXPORT EXTI4_15_IRQHandler [WEAK] 160 | EXPORT DMA1_Channel1_IRQHandler [WEAK] 161 | EXPORT DMA1_Channel2_3_IRQHandler [WEAK] 162 | EXPORT DMA1_Ch4_5_DMAMUX1_OVR_IRQHandler [WEAK] 163 | EXPORT ADC1_IRQHandler [WEAK] 164 | EXPORT TIM1_BRK_UP_TRG_COM_IRQHandler [WEAK] 165 | EXPORT TIM1_CC_IRQHandler [WEAK] 166 | EXPORT TIM3_IRQHandler [WEAK] 167 | EXPORT TIM14_IRQHandler [WEAK] 168 | EXPORT TIM16_IRQHandler [WEAK] 169 | EXPORT TIM17_IRQHandler [WEAK] 170 | EXPORT I2C1_IRQHandler [WEAK] 171 | EXPORT I2C2_IRQHandler [WEAK] 172 | EXPORT SPI1_IRQHandler [WEAK] 173 | EXPORT SPI2_IRQHandler [WEAK] 174 | EXPORT USART1_IRQHandler [WEAK] 175 | EXPORT USART2_IRQHandler [WEAK] 176 | 177 | 178 | WWDG_IRQHandler 179 | RTC_TAMP_IRQHandler 180 | FLASH_IRQHandler 181 | RCC_IRQHandler 182 | EXTI0_1_IRQHandler 183 | EXTI2_3_IRQHandler 184 | EXTI4_15_IRQHandler 185 | DMA1_Channel1_IRQHandler 186 | DMA1_Channel2_3_IRQHandler 187 | DMA1_Ch4_5_DMAMUX1_OVR_IRQHandler 188 | ADC1_IRQHandler 189 | TIM1_BRK_UP_TRG_COM_IRQHandler 190 | TIM1_CC_IRQHandler 191 | TIM3_IRQHandler 192 | TIM14_IRQHandler 193 | TIM16_IRQHandler 194 | TIM17_IRQHandler 195 | I2C1_IRQHandler 196 | I2C2_IRQHandler 197 | SPI1_IRQHandler 198 | SPI2_IRQHandler 199 | USART1_IRQHandler 200 | USART2_IRQHandler 201 | 202 | B . 203 | 204 | ENDP 205 | 206 | ALIGN 207 | 208 | ;******************************************************************************* 209 | ; User Stack and Heap initialization 210 | ;******************************************************************************* 211 | IF :DEF:__MICROLIB 212 | 213 | EXPORT __initial_sp 214 | EXPORT __heap_base 215 | EXPORT __heap_limit 216 | 217 | ELSE 218 | 219 | IMPORT __use_two_region_memory 220 | EXPORT __user_initial_stackheap 221 | 222 | __user_initial_stackheap 223 | 224 | LDR R0, = Heap_Mem 225 | LDR R1, =(Stack_Mem + Stack_Size) 226 | LDR R2, = (Heap_Mem + Heap_Size) 227 | LDR R3, = Stack_Mem 228 | BX LR 229 | 230 | ALIGN 231 | 232 | ENDIF 233 | 234 | END 235 | 236 | ;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** 237 | -------------------------------------------------------------------------------- /Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/arm/startup_stm32g050xx.s: -------------------------------------------------------------------------------- 1 | ;****************************************************************************** 2 | ;* File Name : startup_stm32g050xx.s 3 | ;* Author : MCD Application Team 4 | ;* Description : STM32G050xx devices vector table for MDK-ARM toolchain. 5 | ;* This module performs: 6 | ;* - Set the initial SP 7 | ;* - Set the initial PC == Reset_Handler 8 | ;* - Set the vector table entries with the exceptions ISR address 9 | ;* - Branches to __main in the C library (which eventually 10 | ;* calls main()). 11 | ;* After Reset the CortexM0 processor is in Thread mode, 12 | ;* priority is Privileged, and the Stack is set to Main. 13 | ;* <<< Use Configuration Wizard in Context Menu >>> 14 | ;****************************************************************************** 15 | ;* @attention 16 | ;* 17 | ;* Copyright (c) 2018-2021 STMicroelectronics. 18 | ;* All rights reserved. 19 | ;* 20 | ;* This software is licensed under terms that can be found in the LICENSE file 21 | ;* in the root directory of this software component. 22 | ;* If no LICENSE file comes with this software, it is provided AS-IS. 23 | ;* 24 | ;****************************************************************************** 25 | ; Amount of memory (in bytes) allocated for Stack 26 | ; Tailor this value to your application needs 27 | ; Stack Configuration 28 | ; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> 29 | ; 30 | 31 | Stack_Size EQU 0x00000400 32 | 33 | AREA STACK, NOINIT, READWRITE, ALIGN=3 34 | Stack_Mem SPACE Stack_Size 35 | __initial_sp 36 | 37 | 38 | ; Heap Configuration 39 | ; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> 40 | ; 41 | 42 | Heap_Size EQU 0x00000200 43 | 44 | AREA HEAP, NOINIT, READWRITE, ALIGN=3 45 | __heap_base 46 | Heap_Mem SPACE Heap_Size 47 | __heap_limit 48 | 49 | PRESERVE8 50 | THUMB 51 | 52 | 53 | ; Vector Table Mapped to Address 0 at Reset 54 | AREA RESET, DATA, READONLY 55 | EXPORT __Vectors 56 | EXPORT __Vectors_End 57 | EXPORT __Vectors_Size 58 | 59 | __Vectors DCD __initial_sp ; Top of Stack 60 | DCD Reset_Handler ; Reset Handler 61 | DCD NMI_Handler ; NMI Handler 62 | DCD HardFault_Handler ; Hard Fault Handler 63 | DCD 0 ; Reserved 64 | DCD 0 ; Reserved 65 | DCD 0 ; Reserved 66 | DCD 0 ; Reserved 67 | DCD 0 ; Reserved 68 | DCD 0 ; Reserved 69 | DCD 0 ; Reserved 70 | DCD SVC_Handler ; SVCall Handler 71 | DCD 0 ; Reserved 72 | DCD 0 ; Reserved 73 | DCD PendSV_Handler ; PendSV Handler 74 | DCD SysTick_Handler ; SysTick Handler 75 | 76 | ; External Interrupts 77 | DCD WWDG_IRQHandler ; Window Watchdog 78 | DCD 0 ; Reserved 79 | DCD RTC_TAMP_IRQHandler ; RTC through EXTI Line 80 | DCD FLASH_IRQHandler ; FLASH 81 | DCD RCC_IRQHandler ; RCC 82 | DCD EXTI0_1_IRQHandler ; EXTI Line 0 and 1 83 | DCD EXTI2_3_IRQHandler ; EXTI Line 2 and 3 84 | DCD EXTI4_15_IRQHandler ; EXTI Line 4 to 15 85 | DCD 0 ; Reserved 86 | DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 87 | DCD DMA1_Channel2_3_IRQHandler ; DMA1 Channel 2 and Channel 3 88 | DCD DMA1_Ch4_7_DMAMUX1_OVR_IRQHandler ; DMA1 Channel 4 to Channel 7, DMAMUX1 overrun 89 | DCD ADC1_IRQHandler ; ADC1 90 | DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation 91 | DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare 92 | DCD 0 ; Reserved 93 | DCD TIM3_IRQHandler ; TIM3 94 | DCD TIM6_IRQHandler ; TIM6 95 | DCD TIM7_IRQHandler ; TIM7 96 | DCD TIM14_IRQHandler ; TIM14 97 | DCD TIM15_IRQHandler ; TIM15 98 | DCD TIM16_IRQHandler ; TIM16 99 | DCD TIM17_IRQHandler ; TIM17 100 | DCD I2C1_IRQHandler ; I2C1 101 | DCD I2C2_IRQHandler ; I2C2 102 | DCD SPI1_IRQHandler ; SPI1 103 | DCD SPI2_IRQHandler ; SPI2 104 | DCD USART1_IRQHandler ; USART1 105 | DCD USART2_IRQHandler ; USART2 106 | 107 | __Vectors_End 108 | 109 | __Vectors_Size EQU __Vectors_End - __Vectors 110 | 111 | AREA |.text|, CODE, READONLY 112 | 113 | ; Reset handler routine 114 | Reset_Handler PROC 115 | EXPORT Reset_Handler [WEAK] 116 | IMPORT __main 117 | IMPORT SystemInit 118 | LDR R0, =SystemInit 119 | BLX R0 120 | LDR R0, =__main 121 | BX R0 122 | ENDP 123 | 124 | ; Dummy Exception Handlers (infinite loops which can be modified) 125 | 126 | NMI_Handler PROC 127 | EXPORT NMI_Handler [WEAK] 128 | B . 129 | ENDP 130 | HardFault_Handler\ 131 | PROC 132 | EXPORT HardFault_Handler [WEAK] 133 | B . 134 | ENDP 135 | SVC_Handler PROC 136 | EXPORT SVC_Handler [WEAK] 137 | B . 138 | ENDP 139 | PendSV_Handler PROC 140 | EXPORT PendSV_Handler [WEAK] 141 | B . 142 | ENDP 143 | SysTick_Handler PROC 144 | EXPORT SysTick_Handler [WEAK] 145 | B . 146 | ENDP 147 | 148 | Default_Handler PROC 149 | 150 | EXPORT WWDG_IRQHandler [WEAK] 151 | EXPORT RTC_TAMP_IRQHandler [WEAK] 152 | EXPORT FLASH_IRQHandler [WEAK] 153 | EXPORT RCC_IRQHandler [WEAK] 154 | EXPORT EXTI0_1_IRQHandler [WEAK] 155 | EXPORT EXTI2_3_IRQHandler [WEAK] 156 | EXPORT EXTI4_15_IRQHandler [WEAK] 157 | EXPORT DMA1_Channel1_IRQHandler [WEAK] 158 | EXPORT DMA1_Channel2_3_IRQHandler [WEAK] 159 | EXPORT DMA1_Ch4_7_DMAMUX1_OVR_IRQHandler [WEAK] 160 | EXPORT ADC1_IRQHandler [WEAK] 161 | EXPORT TIM1_BRK_UP_TRG_COM_IRQHandler [WEAK] 162 | EXPORT TIM1_CC_IRQHandler [WEAK] 163 | EXPORT TIM3_IRQHandler [WEAK] 164 | EXPORT TIM6_IRQHandler [WEAK] 165 | EXPORT TIM7_IRQHandler [WEAK] 166 | EXPORT TIM14_IRQHandler [WEAK] 167 | EXPORT TIM15_IRQHandler [WEAK] 168 | EXPORT TIM16_IRQHandler [WEAK] 169 | EXPORT TIM17_IRQHandler [WEAK] 170 | EXPORT I2C1_IRQHandler [WEAK] 171 | EXPORT I2C2_IRQHandler [WEAK] 172 | EXPORT SPI1_IRQHandler [WEAK] 173 | EXPORT SPI2_IRQHandler [WEAK] 174 | EXPORT USART1_IRQHandler [WEAK] 175 | EXPORT USART2_IRQHandler [WEAK] 176 | 177 | 178 | WWDG_IRQHandler 179 | RTC_TAMP_IRQHandler 180 | FLASH_IRQHandler 181 | RCC_IRQHandler 182 | EXTI0_1_IRQHandler 183 | EXTI2_3_IRQHandler 184 | EXTI4_15_IRQHandler 185 | DMA1_Channel1_IRQHandler 186 | DMA1_Channel2_3_IRQHandler 187 | DMA1_Ch4_7_DMAMUX1_OVR_IRQHandler 188 | ADC1_IRQHandler 189 | TIM1_BRK_UP_TRG_COM_IRQHandler 190 | TIM1_CC_IRQHandler 191 | TIM3_IRQHandler 192 | TIM6_IRQHandler 193 | TIM7_IRQHandler 194 | TIM14_IRQHandler 195 | TIM15_IRQHandler 196 | TIM16_IRQHandler 197 | TIM17_IRQHandler 198 | I2C1_IRQHandler 199 | I2C2_IRQHandler 200 | SPI1_IRQHandler 201 | SPI2_IRQHandler 202 | USART1_IRQHandler 203 | USART2_IRQHandler 204 | 205 | B . 206 | 207 | ENDP 208 | 209 | ALIGN 210 | 211 | ;******************************************************************************* 212 | ; User Stack and Heap initialization 213 | ;******************************************************************************* 214 | IF :DEF:__MICROLIB 215 | 216 | EXPORT __initial_sp 217 | EXPORT __heap_base 218 | EXPORT __heap_limit 219 | 220 | ELSE 221 | 222 | IMPORT __use_two_region_memory 223 | EXPORT __user_initial_stackheap 224 | 225 | __user_initial_stackheap 226 | 227 | LDR R0, = Heap_Mem 228 | LDR R1, =(Stack_Mem + Stack_Size) 229 | LDR R2, = (Heap_Mem + Heap_Size) 230 | LDR R3, = Stack_Mem 231 | BX LR 232 | 233 | ALIGN 234 | 235 | ENDIF 236 | 237 | END 238 | 239 | ;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** -------------------------------------------------------------------------------- /Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/arm/startup_stm32g070xx.s: -------------------------------------------------------------------------------- 1 | ;****************************************************************************** 2 | ;* File Name : startup_stm32g070xx.s 3 | ;* Author : MCD Application Team 4 | ;* Description : STM32G070xx devices vector table for MDK-ARM toolchain. 5 | ;* This module performs: 6 | ;* - Set the initial SP 7 | ;* - Set the initial PC == Reset_Handler 8 | ;* - Set the vector table entries with the exceptions ISR address 9 | ;* - Branches to __main in the C library (which eventually 10 | ;* calls main()). 11 | ;* After Reset the CortexM0 processor is in Thread mode, 12 | ;* priority is Privileged, and the Stack is set to Main. 13 | ;* <<< Use Configuration Wizard in Context Menu >>> 14 | ;****************************************************************************** 15 | ;* @attention 16 | ;* 17 | ;* Copyright (c) 2018-2021 STMicroelectronics. 18 | ;* All rights reserved. 19 | ;* 20 | ;* This software is licensed under terms that can be found in the LICENSE file 21 | ;* in the root directory of this software component. 22 | ;* If no LICENSE file comes with this software, it is provided AS-IS. 23 | ;* 24 | ;****************************************************************************** 25 | ; Amount of memory (in bytes) allocated for Stack 26 | ; Tailor this value to your application needs 27 | ; Stack Configuration 28 | ; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> 29 | ; 30 | 31 | Stack_Size EQU 0x00000400 32 | 33 | AREA STACK, NOINIT, READWRITE, ALIGN=3 34 | Stack_Mem SPACE Stack_Size 35 | __initial_sp 36 | 37 | 38 | ; Heap Configuration 39 | ; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> 40 | ; 41 | 42 | Heap_Size EQU 0x00000200 43 | 44 | AREA HEAP, NOINIT, READWRITE, ALIGN=3 45 | __heap_base 46 | Heap_Mem SPACE Heap_Size 47 | __heap_limit 48 | 49 | PRESERVE8 50 | THUMB 51 | 52 | 53 | ; Vector Table Mapped to Address 0 at Reset 54 | AREA RESET, DATA, READONLY 55 | EXPORT __Vectors 56 | EXPORT __Vectors_End 57 | EXPORT __Vectors_Size 58 | 59 | __Vectors DCD __initial_sp ; Top of Stack 60 | DCD Reset_Handler ; Reset Handler 61 | DCD NMI_Handler ; NMI Handler 62 | DCD HardFault_Handler ; Hard Fault Handler 63 | DCD 0 ; Reserved 64 | DCD 0 ; Reserved 65 | DCD 0 ; Reserved 66 | DCD 0 ; Reserved 67 | DCD 0 ; Reserved 68 | DCD 0 ; Reserved 69 | DCD 0 ; Reserved 70 | DCD SVC_Handler ; SVCall Handler 71 | DCD 0 ; Reserved 72 | DCD 0 ; Reserved 73 | DCD PendSV_Handler ; PendSV Handler 74 | DCD SysTick_Handler ; SysTick Handler 75 | 76 | ; External Interrupts 77 | DCD WWDG_IRQHandler ; Window Watchdog 78 | DCD 0 ; Reserved 79 | DCD RTC_TAMP_IRQHandler ; RTC through EXTI Line 80 | DCD FLASH_IRQHandler ; FLASH 81 | DCD RCC_IRQHandler ; RCC 82 | DCD EXTI0_1_IRQHandler ; EXTI Line 0 and 1 83 | DCD EXTI2_3_IRQHandler ; EXTI Line 2 and 3 84 | DCD EXTI4_15_IRQHandler ; EXTI Line 4 to 15 85 | DCD 0 ; Reserved 86 | DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 87 | DCD DMA1_Channel2_3_IRQHandler ; DMA1 Channel 2 and Channel 3 88 | DCD DMA1_Ch4_7_DMAMUX1_OVR_IRQHandler ; DMA1 Channel 4 to Channel 7, DMAMUX1 overrun 89 | DCD ADC1_IRQHandler ; ADC1 90 | DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation 91 | DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare 92 | DCD 0 ; Reserved 93 | DCD TIM3_IRQHandler ; TIM3 94 | DCD TIM6_IRQHandler ; TIM6 95 | DCD TIM7_IRQHandler ; TIM7 96 | DCD TIM14_IRQHandler ; TIM14 97 | DCD TIM15_IRQHandler ; TIM15 98 | DCD TIM16_IRQHandler ; TIM16 99 | DCD TIM17_IRQHandler ; TIM17 100 | DCD I2C1_IRQHandler ; I2C1 101 | DCD I2C2_IRQHandler ; I2C2 102 | DCD SPI1_IRQHandler ; SPI1 103 | DCD SPI2_IRQHandler ; SPI2 104 | DCD USART1_IRQHandler ; USART1 105 | DCD USART2_IRQHandler ; USART2 106 | DCD USART3_4_IRQHandler ; USART3, USART4 107 | 108 | __Vectors_End 109 | 110 | __Vectors_Size EQU __Vectors_End - __Vectors 111 | 112 | AREA |.text|, CODE, READONLY 113 | 114 | ; Reset handler routine 115 | Reset_Handler PROC 116 | EXPORT Reset_Handler [WEAK] 117 | IMPORT __main 118 | IMPORT SystemInit 119 | LDR R0, =SystemInit 120 | BLX R0 121 | LDR R0, =__main 122 | BX R0 123 | ENDP 124 | 125 | ; Dummy Exception Handlers (infinite loops which can be modified) 126 | 127 | NMI_Handler PROC 128 | EXPORT NMI_Handler [WEAK] 129 | B . 130 | ENDP 131 | HardFault_Handler\ 132 | PROC 133 | EXPORT HardFault_Handler [WEAK] 134 | B . 135 | ENDP 136 | SVC_Handler PROC 137 | EXPORT SVC_Handler [WEAK] 138 | B . 139 | ENDP 140 | PendSV_Handler PROC 141 | EXPORT PendSV_Handler [WEAK] 142 | B . 143 | ENDP 144 | SysTick_Handler PROC 145 | EXPORT SysTick_Handler [WEAK] 146 | B . 147 | ENDP 148 | 149 | Default_Handler PROC 150 | 151 | EXPORT WWDG_IRQHandler [WEAK] 152 | EXPORT RTC_TAMP_IRQHandler [WEAK] 153 | EXPORT FLASH_IRQHandler [WEAK] 154 | EXPORT RCC_IRQHandler [WEAK] 155 | EXPORT EXTI0_1_IRQHandler [WEAK] 156 | EXPORT EXTI2_3_IRQHandler [WEAK] 157 | EXPORT EXTI4_15_IRQHandler [WEAK] 158 | EXPORT DMA1_Channel1_IRQHandler [WEAK] 159 | EXPORT DMA1_Channel2_3_IRQHandler [WEAK] 160 | EXPORT DMA1_Ch4_7_DMAMUX1_OVR_IRQHandler [WEAK] 161 | EXPORT ADC1_IRQHandler [WEAK] 162 | EXPORT TIM1_BRK_UP_TRG_COM_IRQHandler [WEAK] 163 | EXPORT TIM1_CC_IRQHandler [WEAK] 164 | EXPORT TIM3_IRQHandler [WEAK] 165 | EXPORT TIM6_IRQHandler [WEAK] 166 | EXPORT TIM7_IRQHandler [WEAK] 167 | EXPORT TIM14_IRQHandler [WEAK] 168 | EXPORT TIM15_IRQHandler [WEAK] 169 | EXPORT TIM16_IRQHandler [WEAK] 170 | EXPORT TIM17_IRQHandler [WEAK] 171 | EXPORT I2C1_IRQHandler [WEAK] 172 | EXPORT I2C2_IRQHandler [WEAK] 173 | EXPORT SPI1_IRQHandler [WEAK] 174 | EXPORT SPI2_IRQHandler [WEAK] 175 | EXPORT USART1_IRQHandler [WEAK] 176 | EXPORT USART2_IRQHandler [WEAK] 177 | EXPORT USART3_4_IRQHandler [WEAK] 178 | 179 | 180 | WWDG_IRQHandler 181 | RTC_TAMP_IRQHandler 182 | FLASH_IRQHandler 183 | RCC_IRQHandler 184 | EXTI0_1_IRQHandler 185 | EXTI2_3_IRQHandler 186 | EXTI4_15_IRQHandler 187 | DMA1_Channel1_IRQHandler 188 | DMA1_Channel2_3_IRQHandler 189 | DMA1_Ch4_7_DMAMUX1_OVR_IRQHandler 190 | ADC1_IRQHandler 191 | TIM1_BRK_UP_TRG_COM_IRQHandler 192 | TIM1_CC_IRQHandler 193 | TIM3_IRQHandler 194 | TIM6_IRQHandler 195 | TIM7_IRQHandler 196 | TIM14_IRQHandler 197 | TIM15_IRQHandler 198 | TIM16_IRQHandler 199 | TIM17_IRQHandler 200 | I2C1_IRQHandler 201 | I2C2_IRQHandler 202 | SPI1_IRQHandler 203 | SPI2_IRQHandler 204 | USART1_IRQHandler 205 | USART2_IRQHandler 206 | USART3_4_IRQHandler 207 | 208 | B . 209 | 210 | ENDP 211 | 212 | ALIGN 213 | 214 | ;******************************************************************************* 215 | ; User Stack and Heap initialization 216 | ;******************************************************************************* 217 | IF :DEF:__MICROLIB 218 | 219 | EXPORT __initial_sp 220 | EXPORT __heap_base 221 | EXPORT __heap_limit 222 | 223 | ELSE 224 | 225 | IMPORT __use_two_region_memory 226 | EXPORT __user_initial_stackheap 227 | 228 | __user_initial_stackheap 229 | 230 | LDR R0, = Heap_Mem 231 | LDR R1, =(Stack_Mem + Stack_Size) 232 | LDR R2, = (Heap_Mem + Heap_Size) 233 | LDR R3, = Stack_Mem 234 | BX LR 235 | 236 | ALIGN 237 | 238 | ENDIF 239 | 240 | END 241 | 242 | ;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** 243 | -------------------------------------------------------------------------------- /Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/startup_stm32g030xx.s: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file startup_stm32g030xx.s 4 | * @author MCD Application Team 5 | * @brief STM32G030xx devices vector table GCC toolchain. 6 | * This module performs: 7 | * - Set the initial SP 8 | * - Set the initial PC == Reset_Handler, 9 | * - Set the vector table entries with the exceptions ISR address 10 | * - Branches to main in the C library (which eventually 11 | * calls main()). 12 | * After Reset the Cortex-M0+ processor is in Thread mode, 13 | * priority is Privileged, and the Stack is set to Main. 14 | ****************************************************************************** 15 | * @attention 16 | * 17 | * Copyright (c) 2018-2021 STMicroelectronics. 18 | * All rights reserved. 19 | * 20 | * This software is licensed under terms that can be found in the LICENSE file 21 | * in the root directory of this software component. 22 | * If no LICENSE file comes with this software, it is provided AS-IS. 23 | * 24 | ****************************************************************************** 25 | */ 26 | 27 | .syntax unified 28 | .cpu cortex-m0plus 29 | .fpu softvfp 30 | .thumb 31 | 32 | .global g_pfnVectors 33 | .global Default_Handler 34 | 35 | /* start address for the initialization values of the .data section. 36 | defined in linker script */ 37 | .word _sidata 38 | /* start address for the .data section. defined in linker script */ 39 | .word _sdata 40 | /* end address for the .data section. defined in linker script */ 41 | .word _edata 42 | /* start address for the .bss section. defined in linker script */ 43 | .word _sbss 44 | /* end address for the .bss section. defined in linker script */ 45 | .word _ebss 46 | 47 | /** 48 | * @brief This is the code that gets called when the processor first 49 | * starts execution following a reset event. Only the absolutely 50 | * necessary set is performed, after which the application 51 | * supplied main() routine is called. 52 | * @param None 53 | * @retval None 54 | */ 55 | 56 | .section .text.Reset_Handler 57 | .weak Reset_Handler 58 | .type Reset_Handler, %function 59 | Reset_Handler: 60 | ldr r0, =_estack 61 | mov sp, r0 /* set stack pointer */ 62 | 63 | /* Call the clock system initialization function.*/ 64 | bl SystemInit 65 | 66 | /* Copy the data segment initializers from flash to SRAM */ 67 | ldr r0, =_sdata 68 | ldr r1, =_edata 69 | ldr r2, =_sidata 70 | movs r3, #0 71 | b LoopCopyDataInit 72 | 73 | CopyDataInit: 74 | ldr r4, [r2, r3] 75 | str r4, [r0, r3] 76 | adds r3, r3, #4 77 | 78 | LoopCopyDataInit: 79 | adds r4, r0, r3 80 | cmp r4, r1 81 | bcc CopyDataInit 82 | 83 | /* Zero fill the bss segment. */ 84 | ldr r2, =_sbss 85 | ldr r4, =_ebss 86 | movs r3, #0 87 | b LoopFillZerobss 88 | 89 | FillZerobss: 90 | str r3, [r2] 91 | adds r2, r2, #4 92 | 93 | LoopFillZerobss: 94 | cmp r2, r4 95 | bcc FillZerobss 96 | 97 | /* Call static constructors */ 98 | bl __libc_init_array 99 | /* Call the application s entry point.*/ 100 | bl main 101 | 102 | LoopForever: 103 | b LoopForever 104 | 105 | .size Reset_Handler, .-Reset_Handler 106 | 107 | /** 108 | * @brief This is the code that gets called when the processor receives an 109 | * unexpected interrupt. This simply enters an infinite loop, preserving 110 | * the system state for examination by a debugger. 111 | * 112 | * @param None 113 | * @retval None 114 | */ 115 | .section .text.Default_Handler,"ax",%progbits 116 | Default_Handler: 117 | Infinite_Loop: 118 | b Infinite_Loop 119 | .size Default_Handler, .-Default_Handler 120 | 121 | /****************************************************************************** 122 | * 123 | * The minimal vector table for a Cortex M0. Note that the proper constructs 124 | * must be placed on this to ensure that it ends up at physical address 125 | * 0x0000.0000. 126 | * 127 | ******************************************************************************/ 128 | .section .isr_vector,"a",%progbits 129 | .type g_pfnVectors, %object 130 | .size g_pfnVectors, .-g_pfnVectors 131 | 132 | g_pfnVectors: 133 | .word _estack 134 | .word Reset_Handler 135 | .word NMI_Handler 136 | .word HardFault_Handler 137 | .word 0 138 | .word 0 139 | .word 0 140 | .word 0 141 | .word 0 142 | .word 0 143 | .word 0 144 | .word SVC_Handler 145 | .word 0 146 | .word 0 147 | .word PendSV_Handler 148 | .word SysTick_Handler 149 | .word WWDG_IRQHandler /* Window WatchDog */ 150 | .word 0 /* reserved */ 151 | .word RTC_TAMP_IRQHandler /* RTC through the EXTI line */ 152 | .word FLASH_IRQHandler /* FLASH */ 153 | .word RCC_IRQHandler /* RCC */ 154 | .word EXTI0_1_IRQHandler /* EXTI Line 0 and 1 */ 155 | .word EXTI2_3_IRQHandler /* EXTI Line 2 and 3 */ 156 | .word EXTI4_15_IRQHandler /* EXTI Line 4 to 15 */ 157 | .word 0 /* reserved */ 158 | .word DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */ 159 | .word DMA1_Channel2_3_IRQHandler /* DMA1 Channel 2 and Channel 3 */ 160 | .word DMA1_Ch4_5_DMAMUX1_OVR_IRQHandler /* DMA1 Channel 4 to Channel 5, DMAMUX1 overrun */ 161 | .word ADC1_IRQHandler /* ADC1 */ 162 | .word TIM1_BRK_UP_TRG_COM_IRQHandler /* TIM1 Break, Update, Trigger and Commutation */ 163 | .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ 164 | .word 0 /* reserved */ 165 | .word TIM3_IRQHandler /* TIM3 */ 166 | .word 0 /* reserved */ 167 | .word 0 /* reserved */ 168 | .word TIM14_IRQHandler /* TIM14 */ 169 | .word 0 /* reserved */ 170 | .word TIM16_IRQHandler /* TIM16 */ 171 | .word TIM17_IRQHandler /* TIM17 */ 172 | .word I2C1_IRQHandler /* I2C1 */ 173 | .word I2C2_IRQHandler /* I2C2 */ 174 | .word SPI1_IRQHandler /* SPI1 */ 175 | .word SPI2_IRQHandler /* SPI2 */ 176 | .word USART1_IRQHandler /* USART1 */ 177 | .word USART2_IRQHandler /* USART2 */ 178 | .word 0 /* reserved */ 179 | 180 | /******************************************************************************* 181 | * 182 | * Provide weak aliases for each Exception handler to the Default_Handler. 183 | * As they are weak aliases, any function with the same name will override 184 | * this definition. 185 | * 186 | *******************************************************************************/ 187 | 188 | .weak NMI_Handler 189 | .thumb_set NMI_Handler,Default_Handler 190 | 191 | .weak HardFault_Handler 192 | .thumb_set HardFault_Handler,Default_Handler 193 | 194 | .weak SVC_Handler 195 | .thumb_set SVC_Handler,Default_Handler 196 | 197 | .weak PendSV_Handler 198 | .thumb_set PendSV_Handler,Default_Handler 199 | 200 | .weak SysTick_Handler 201 | .thumb_set SysTick_Handler,Default_Handler 202 | 203 | .weak WWDG_IRQHandler 204 | .thumb_set WWDG_IRQHandler,Default_Handler 205 | 206 | .weak RTC_TAMP_IRQHandler 207 | .thumb_set RTC_TAMP_IRQHandler,Default_Handler 208 | 209 | .weak FLASH_IRQHandler 210 | .thumb_set FLASH_IRQHandler,Default_Handler 211 | 212 | .weak RCC_IRQHandler 213 | .thumb_set RCC_IRQHandler,Default_Handler 214 | 215 | .weak EXTI0_1_IRQHandler 216 | .thumb_set EXTI0_1_IRQHandler,Default_Handler 217 | 218 | .weak EXTI2_3_IRQHandler 219 | .thumb_set EXTI2_3_IRQHandler,Default_Handler 220 | 221 | .weak EXTI4_15_IRQHandler 222 | .thumb_set EXTI4_15_IRQHandler,Default_Handler 223 | 224 | .weak DMA1_Channel1_IRQHandler 225 | .thumb_set DMA1_Channel1_IRQHandler,Default_Handler 226 | 227 | .weak DMA1_Channel2_3_IRQHandler 228 | .thumb_set DMA1_Channel2_3_IRQHandler,Default_Handler 229 | 230 | .weak DMA1_Ch4_5_DMAMUX1_OVR_IRQHandler 231 | .thumb_set DMA1_Ch4_5_DMAMUX1_OVR_IRQHandler,Default_Handler 232 | 233 | .weak ADC1_IRQHandler 234 | .thumb_set ADC1_IRQHandler,Default_Handler 235 | 236 | .weak TIM1_BRK_UP_TRG_COM_IRQHandler 237 | .thumb_set TIM1_BRK_UP_TRG_COM_IRQHandler,Default_Handler 238 | 239 | .weak TIM1_CC_IRQHandler 240 | .thumb_set TIM1_CC_IRQHandler,Default_Handler 241 | 242 | .weak TIM3_IRQHandler 243 | .thumb_set TIM3_IRQHandler,Default_Handler 244 | 245 | .weak TIM14_IRQHandler 246 | .thumb_set TIM14_IRQHandler,Default_Handler 247 | 248 | .weak TIM16_IRQHandler 249 | .thumb_set TIM16_IRQHandler,Default_Handler 250 | 251 | .weak TIM17_IRQHandler 252 | .thumb_set TIM17_IRQHandler,Default_Handler 253 | 254 | .weak I2C1_IRQHandler 255 | .thumb_set I2C1_IRQHandler,Default_Handler 256 | 257 | .weak I2C2_IRQHandler 258 | .thumb_set I2C2_IRQHandler,Default_Handler 259 | 260 | .weak SPI1_IRQHandler 261 | .thumb_set SPI1_IRQHandler,Default_Handler 262 | 263 | .weak SPI2_IRQHandler 264 | .thumb_set SPI2_IRQHandler,Default_Handler 265 | 266 | .weak USART1_IRQHandler 267 | .thumb_set USART1_IRQHandler,Default_Handler 268 | 269 | .weak USART2_IRQHandler 270 | .thumb_set USART2_IRQHandler,Default_Handler 271 | 272 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 273 | 274 | -------------------------------------------------------------------------------- /Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/startup_stm32g050xx.s: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file startup_stm32g050xx.s 4 | * @author MCD Application Team 5 | * @brief STM32G050xx devices vector table GCC toolchain. 6 | * This module performs: 7 | * - Set the initial SP 8 | * - Set the initial PC == Reset_Handler, 9 | * - Set the vector table entries with the exceptions ISR address 10 | * - Branches to main in the C library (which eventually 11 | * calls main()). 12 | * After Reset the Cortex-M0+ processor is in Thread mode, 13 | * priority is Privileged, and the Stack is set to Main. 14 | ****************************************************************************** 15 | * @attention 16 | * 17 | * Copyright (c) 2018-2021 STMicroelectronics. 18 | * All rights reserved. 19 | * 20 | * This software is licensed under terms that can be found in the LICENSE file 21 | * in the root directory of this software component. 22 | * If no LICENSE file comes with this software, it is provided AS-IS. 23 | * 24 | ****************************************************************************** 25 | */ 26 | 27 | .syntax unified 28 | .cpu cortex-m0plus 29 | .fpu softvfp 30 | .thumb 31 | 32 | .global g_pfnVectors 33 | .global Default_Handler 34 | 35 | /* start address for the initialization values of the .data section. 36 | defined in linker script */ 37 | .word _sidata 38 | /* start address for the .data section. defined in linker script */ 39 | .word _sdata 40 | /* end address for the .data section. defined in linker script */ 41 | .word _edata 42 | /* start address for the .bss section. defined in linker script */ 43 | .word _sbss 44 | /* end address for the .bss section. defined in linker script */ 45 | .word _ebss 46 | 47 | /** 48 | * @brief This is the code that gets called when the processor first 49 | * starts execution following a reset event. Only the absolutely 50 | * necessary set is performed, after which the application 51 | * supplied main() routine is called. 52 | * @param None 53 | * @retval None 54 | */ 55 | 56 | .section .text.Reset_Handler 57 | .weak Reset_Handler 58 | .type Reset_Handler, %function 59 | Reset_Handler: 60 | ldr r0, =_estack 61 | mov sp, r0 /* set stack pointer */ 62 | 63 | /* Call the clock system initialization function.*/ 64 | bl SystemInit 65 | 66 | /* Copy the data segment initializers from flash to SRAM */ 67 | ldr r0, =_sdata 68 | ldr r1, =_edata 69 | ldr r2, =_sidata 70 | movs r3, #0 71 | b LoopCopyDataInit 72 | 73 | CopyDataInit: 74 | ldr r4, [r2, r3] 75 | str r4, [r0, r3] 76 | adds r3, r3, #4 77 | 78 | LoopCopyDataInit: 79 | adds r4, r0, r3 80 | cmp r4, r1 81 | bcc CopyDataInit 82 | 83 | /* Zero fill the bss segment. */ 84 | ldr r2, =_sbss 85 | ldr r4, =_ebss 86 | movs r3, #0 87 | b LoopFillZerobss 88 | 89 | FillZerobss: 90 | str r3, [r2] 91 | adds r2, r2, #4 92 | 93 | LoopFillZerobss: 94 | cmp r2, r4 95 | bcc FillZerobss 96 | 97 | /* Call static constructors */ 98 | bl __libc_init_array 99 | /* Call the application s entry point.*/ 100 | bl main 101 | 102 | LoopForever: 103 | b LoopForever 104 | 105 | .size Reset_Handler, .-Reset_Handler 106 | 107 | /** 108 | * @brief This is the code that gets called when the processor receives an 109 | * unexpected interrupt. This simply enters an infinite loop, preserving 110 | * the system state for examination by a debugger. 111 | * 112 | * @param None 113 | * @retval None 114 | */ 115 | .section .text.Default_Handler,"ax",%progbits 116 | Default_Handler: 117 | Infinite_Loop: 118 | b Infinite_Loop 119 | .size Default_Handler, .-Default_Handler 120 | 121 | /****************************************************************************** 122 | * 123 | * The minimal vector table for a Cortex M0. Note that the proper constructs 124 | * must be placed on this to ensure that it ends up at physical address 125 | * 0x0000.0000. 126 | * 127 | ******************************************************************************/ 128 | .section .isr_vector,"a",%progbits 129 | .type g_pfnVectors, %object 130 | .size g_pfnVectors, .-g_pfnVectors 131 | 132 | g_pfnVectors: 133 | .word _estack 134 | .word Reset_Handler 135 | .word NMI_Handler 136 | .word HardFault_Handler 137 | .word 0 138 | .word 0 139 | .word 0 140 | .word 0 141 | .word 0 142 | .word 0 143 | .word 0 144 | .word SVC_Handler 145 | .word 0 146 | .word 0 147 | .word PendSV_Handler 148 | .word SysTick_Handler 149 | .word WWDG_IRQHandler /* Window WatchDog */ 150 | .word 0 /* reserved */ 151 | .word RTC_TAMP_IRQHandler /* RTC through the EXTI line */ 152 | .word FLASH_IRQHandler /* FLASH */ 153 | .word RCC_IRQHandler /* RCC */ 154 | .word EXTI0_1_IRQHandler /* EXTI Line 0 and 1 */ 155 | .word EXTI2_3_IRQHandler /* EXTI Line 2 and 3 */ 156 | .word EXTI4_15_IRQHandler /* EXTI Line 4 to 15 */ 157 | .word 0 /* reserved */ 158 | .word DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */ 159 | .word DMA1_Channel2_3_IRQHandler /* DMA1 Channel 2 and Channel 3 */ 160 | .word DMA1_Ch4_7_DMAMUX1_OVR_IRQHandler /* DMA1 Channel 4 to Channel 7, DMAMUX1 overrun */ 161 | .word ADC1_IRQHandler /* ADC1 */ 162 | .word TIM1_BRK_UP_TRG_COM_IRQHandler /* TIM1 Break, Update, Trigger and Commutation */ 163 | .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ 164 | .word 0 /* reserved */ 165 | .word TIM3_IRQHandler /* TIM3 */ 166 | .word TIM6_IRQHandler /* TIM6 */ 167 | .word TIM7_IRQHandler /* TIM7 */ 168 | .word TIM14_IRQHandler /* TIM14 */ 169 | .word TIM15_IRQHandler /* TIM15 */ 170 | .word TIM16_IRQHandler /* TIM16 */ 171 | .word TIM17_IRQHandler /* TIM17 */ 172 | .word I2C1_IRQHandler /* I2C1 */ 173 | .word I2C2_IRQHandler /* I2C2 */ 174 | .word SPI1_IRQHandler /* SPI1 */ 175 | .word SPI2_IRQHandler /* SPI2 */ 176 | .word USART1_IRQHandler /* USART1 */ 177 | .word USART2_IRQHandler /* USART2 */ 178 | 179 | /******************************************************************************* 180 | * 181 | * Provide weak aliases for each Exception handler to the Default_Handler. 182 | * As they are weak aliases, any function with the same name will override 183 | * this definition. 184 | * 185 | *******************************************************************************/ 186 | 187 | .weak NMI_Handler 188 | .thumb_set NMI_Handler,Default_Handler 189 | 190 | .weak HardFault_Handler 191 | .thumb_set HardFault_Handler,Default_Handler 192 | 193 | .weak SVC_Handler 194 | .thumb_set SVC_Handler,Default_Handler 195 | 196 | .weak PendSV_Handler 197 | .thumb_set PendSV_Handler,Default_Handler 198 | 199 | .weak SysTick_Handler 200 | .thumb_set SysTick_Handler,Default_Handler 201 | 202 | .weak WWDG_IRQHandler 203 | .thumb_set WWDG_IRQHandler,Default_Handler 204 | 205 | .weak RTC_TAMP_IRQHandler 206 | .thumb_set RTC_TAMP_IRQHandler,Default_Handler 207 | 208 | .weak FLASH_IRQHandler 209 | .thumb_set FLASH_IRQHandler,Default_Handler 210 | 211 | .weak RCC_IRQHandler 212 | .thumb_set RCC_IRQHandler,Default_Handler 213 | 214 | .weak EXTI0_1_IRQHandler 215 | .thumb_set EXTI0_1_IRQHandler,Default_Handler 216 | 217 | .weak EXTI2_3_IRQHandler 218 | .thumb_set EXTI2_3_IRQHandler,Default_Handler 219 | 220 | .weak EXTI4_15_IRQHandler 221 | .thumb_set EXTI4_15_IRQHandler,Default_Handler 222 | 223 | .weak DMA1_Channel1_IRQHandler 224 | .thumb_set DMA1_Channel1_IRQHandler,Default_Handler 225 | 226 | .weak DMA1_Channel2_3_IRQHandler 227 | .thumb_set DMA1_Channel2_3_IRQHandler,Default_Handler 228 | 229 | .weak DMA1_Ch4_7_DMAMUX1_OVR_IRQHandler 230 | .thumb_set DMA1_Ch4_7_DMAMUX1_OVR_IRQHandler,Default_Handler 231 | 232 | .weak ADC1_IRQHandler 233 | .thumb_set ADC1_IRQHandler,Default_Handler 234 | 235 | .weak TIM1_BRK_UP_TRG_COM_IRQHandler 236 | .thumb_set TIM1_BRK_UP_TRG_COM_IRQHandler,Default_Handler 237 | 238 | .weak TIM1_CC_IRQHandler 239 | .thumb_set TIM1_CC_IRQHandler,Default_Handler 240 | 241 | .weak TIM3_IRQHandler 242 | .thumb_set TIM3_IRQHandler,Default_Handler 243 | 244 | .weak TIM6_IRQHandler 245 | .thumb_set TIM6_IRQHandler,Default_Handler 246 | 247 | .weak TIM7_IRQHandler 248 | .thumb_set TIM7_IRQHandler,Default_Handler 249 | 250 | .weak TIM14_IRQHandler 251 | .thumb_set TIM14_IRQHandler,Default_Handler 252 | 253 | .weak TIM15_IRQHandler 254 | .thumb_set TIM15_IRQHandler,Default_Handler 255 | 256 | .weak TIM16_IRQHandler 257 | .thumb_set TIM16_IRQHandler,Default_Handler 258 | 259 | .weak TIM17_IRQHandler 260 | .thumb_set TIM17_IRQHandler,Default_Handler 261 | 262 | .weak I2C1_IRQHandler 263 | .thumb_set I2C1_IRQHandler,Default_Handler 264 | 265 | .weak I2C2_IRQHandler 266 | .thumb_set I2C2_IRQHandler,Default_Handler 267 | 268 | .weak SPI1_IRQHandler 269 | .thumb_set SPI1_IRQHandler,Default_Handler 270 | 271 | .weak SPI2_IRQHandler 272 | .thumb_set SPI2_IRQHandler,Default_Handler 273 | 274 | .weak USART1_IRQHandler 275 | .thumb_set USART1_IRQHandler,Default_Handler 276 | 277 | .weak USART2_IRQHandler 278 | .thumb_set USART2_IRQHandler,Default_Handler 279 | 280 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 281 | 282 | -------------------------------------------------------------------------------- /Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/startup_stm32g070xx.s: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file startup_stm32g070xx.s 4 | * @author MCD Application Team 5 | * @brief STM32G070xx devices vector table GCC toolchain. 6 | * This module performs: 7 | * - Set the initial SP 8 | * - Set the initial PC == Reset_Handler, 9 | * - Set the vector table entries with the exceptions ISR address 10 | * - Branches to main in the C library (which eventually 11 | * calls main()). 12 | * After Reset the Cortex-M0+ processor is in Thread mode, 13 | * priority is Privileged, and the Stack is set to Main. 14 | ****************************************************************************** 15 | * @attention 16 | * 17 | * Copyright (c) 2018-2021 STMicroelectronics. 18 | * All rights reserved. 19 | * 20 | * This software is licensed under terms that can be found in the LICENSE file 21 | * in the root directory of this software component. 22 | * If no LICENSE file comes with this software, it is provided AS-IS. 23 | * 24 | ****************************************************************************** 25 | */ 26 | 27 | .syntax unified 28 | .cpu cortex-m0plus 29 | .fpu softvfp 30 | .thumb 31 | 32 | .global g_pfnVectors 33 | .global Default_Handler 34 | 35 | /* start address for the initialization values of the .data section. 36 | defined in linker script */ 37 | .word _sidata 38 | /* start address for the .data section. defined in linker script */ 39 | .word _sdata 40 | /* end address for the .data section. defined in linker script */ 41 | .word _edata 42 | /* start address for the .bss section. defined in linker script */ 43 | .word _sbss 44 | /* end address for the .bss section. defined in linker script */ 45 | .word _ebss 46 | 47 | /** 48 | * @brief This is the code that gets called when the processor first 49 | * starts execution following a reset event. Only the absolutely 50 | * necessary set is performed, after which the application 51 | * supplied main() routine is called. 52 | * @param None 53 | * @retval None 54 | */ 55 | 56 | .section .text.Reset_Handler 57 | .weak Reset_Handler 58 | .type Reset_Handler, %function 59 | Reset_Handler: 60 | ldr r0, =_estack 61 | mov sp, r0 /* set stack pointer */ 62 | 63 | /* Call the clock system initialization function.*/ 64 | bl SystemInit 65 | 66 | /* Copy the data segment initializers from flash to SRAM */ 67 | ldr r0, =_sdata 68 | ldr r1, =_edata 69 | ldr r2, =_sidata 70 | movs r3, #0 71 | b LoopCopyDataInit 72 | 73 | CopyDataInit: 74 | ldr r4, [r2, r3] 75 | str r4, [r0, r3] 76 | adds r3, r3, #4 77 | 78 | LoopCopyDataInit: 79 | adds r4, r0, r3 80 | cmp r4, r1 81 | bcc CopyDataInit 82 | 83 | /* Zero fill the bss segment. */ 84 | ldr r2, =_sbss 85 | ldr r4, =_ebss 86 | movs r3, #0 87 | b LoopFillZerobss 88 | 89 | FillZerobss: 90 | str r3, [r2] 91 | adds r2, r2, #4 92 | 93 | LoopFillZerobss: 94 | cmp r2, r4 95 | bcc FillZerobss 96 | 97 | /* Call static constructors */ 98 | bl __libc_init_array 99 | /* Call the application s entry point.*/ 100 | bl main 101 | 102 | LoopForever: 103 | b LoopForever 104 | 105 | .size Reset_Handler, .-Reset_Handler 106 | 107 | /** 108 | * @brief This is the code that gets called when the processor receives an 109 | * unexpected interrupt. This simply enters an infinite loop, preserving 110 | * the system state for examination by a debugger. 111 | * 112 | * @param None 113 | * @retval None 114 | */ 115 | .section .text.Default_Handler,"ax",%progbits 116 | Default_Handler: 117 | Infinite_Loop: 118 | b Infinite_Loop 119 | .size Default_Handler, .-Default_Handler 120 | 121 | /****************************************************************************** 122 | * 123 | * The minimal vector table for a Cortex M0. Note that the proper constructs 124 | * must be placed on this to ensure that it ends up at physical address 125 | * 0x0000.0000. 126 | * 127 | ******************************************************************************/ 128 | .section .isr_vector,"a",%progbits 129 | .type g_pfnVectors, %object 130 | .size g_pfnVectors, .-g_pfnVectors 131 | 132 | g_pfnVectors: 133 | .word _estack 134 | .word Reset_Handler 135 | .word NMI_Handler 136 | .word HardFault_Handler 137 | .word 0 138 | .word 0 139 | .word 0 140 | .word 0 141 | .word 0 142 | .word 0 143 | .word 0 144 | .word SVC_Handler 145 | .word 0 146 | .word 0 147 | .word PendSV_Handler 148 | .word SysTick_Handler 149 | .word WWDG_IRQHandler /* Window WatchDog */ 150 | .word 0 /* reserved */ 151 | .word RTC_TAMP_IRQHandler /* RTC through the EXTI line */ 152 | .word FLASH_IRQHandler /* FLASH */ 153 | .word RCC_IRQHandler /* RCC */ 154 | .word EXTI0_1_IRQHandler /* EXTI Line 0 and 1 */ 155 | .word EXTI2_3_IRQHandler /* EXTI Line 2 and 3 */ 156 | .word EXTI4_15_IRQHandler /* EXTI Line 4 to 15 */ 157 | .word 0 /* reserved */ 158 | .word DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */ 159 | .word DMA1_Channel2_3_IRQHandler /* DMA1 Channel 2 and Channel 3 */ 160 | .word DMA1_Ch4_7_DMAMUX1_OVR_IRQHandler /* DMA1 Channel 4 to Channel 7, DMAMUX1 overrun */ 161 | .word ADC1_IRQHandler /* ADC1 */ 162 | .word TIM1_BRK_UP_TRG_COM_IRQHandler /* TIM1 Break, Update, Trigger and Commutation */ 163 | .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ 164 | .word 0 /* reserved */ 165 | .word TIM3_IRQHandler /* TIM3 */ 166 | .word TIM6_IRQHandler /* TIM6 */ 167 | .word TIM7_IRQHandler /* TIM7 */ 168 | .word TIM14_IRQHandler /* TIM14 */ 169 | .word TIM15_IRQHandler /* TIM15 */ 170 | .word TIM16_IRQHandler /* TIM16 */ 171 | .word TIM17_IRQHandler /* TIM17 */ 172 | .word I2C1_IRQHandler /* I2C1 */ 173 | .word I2C2_IRQHandler /* I2C2 */ 174 | .word SPI1_IRQHandler /* SPI1 */ 175 | .word SPI2_IRQHandler /* SPI2 */ 176 | .word USART1_IRQHandler /* USART1 */ 177 | .word USART2_IRQHandler /* USART2 */ 178 | .word USART3_4_IRQHandler /* USART3, USART4 */ 179 | 180 | /******************************************************************************* 181 | * 182 | * Provide weak aliases for each Exception handler to the Default_Handler. 183 | * As they are weak aliases, any function with the same name will override 184 | * this definition. 185 | * 186 | *******************************************************************************/ 187 | 188 | .weak NMI_Handler 189 | .thumb_set NMI_Handler,Default_Handler 190 | 191 | .weak HardFault_Handler 192 | .thumb_set HardFault_Handler,Default_Handler 193 | 194 | .weak SVC_Handler 195 | .thumb_set SVC_Handler,Default_Handler 196 | 197 | .weak PendSV_Handler 198 | .thumb_set PendSV_Handler,Default_Handler 199 | 200 | .weak SysTick_Handler 201 | .thumb_set SysTick_Handler,Default_Handler 202 | 203 | .weak WWDG_IRQHandler 204 | .thumb_set WWDG_IRQHandler,Default_Handler 205 | 206 | .weak RTC_TAMP_IRQHandler 207 | .thumb_set RTC_TAMP_IRQHandler,Default_Handler 208 | 209 | .weak FLASH_IRQHandler 210 | .thumb_set FLASH_IRQHandler,Default_Handler 211 | 212 | .weak RCC_IRQHandler 213 | .thumb_set RCC_IRQHandler,Default_Handler 214 | 215 | .weak EXTI0_1_IRQHandler 216 | .thumb_set EXTI0_1_IRQHandler,Default_Handler 217 | 218 | .weak EXTI2_3_IRQHandler 219 | .thumb_set EXTI2_3_IRQHandler,Default_Handler 220 | 221 | .weak EXTI4_15_IRQHandler 222 | .thumb_set EXTI4_15_IRQHandler,Default_Handler 223 | 224 | .weak DMA1_Channel1_IRQHandler 225 | .thumb_set DMA1_Channel1_IRQHandler,Default_Handler 226 | 227 | .weak DMA1_Channel2_3_IRQHandler 228 | .thumb_set DMA1_Channel2_3_IRQHandler,Default_Handler 229 | 230 | .weak DMA1_Ch4_7_DMAMUX1_OVR_IRQHandler 231 | .thumb_set DMA1_Ch4_7_DMAMUX1_OVR_IRQHandler,Default_Handler 232 | 233 | .weak ADC1_IRQHandler 234 | .thumb_set ADC1_IRQHandler,Default_Handler 235 | 236 | .weak TIM1_BRK_UP_TRG_COM_IRQHandler 237 | .thumb_set TIM1_BRK_UP_TRG_COM_IRQHandler,Default_Handler 238 | 239 | .weak TIM1_CC_IRQHandler 240 | .thumb_set TIM1_CC_IRQHandler,Default_Handler 241 | 242 | .weak TIM3_IRQHandler 243 | .thumb_set TIM3_IRQHandler,Default_Handler 244 | 245 | .weak TIM6_IRQHandler 246 | .thumb_set TIM6_IRQHandler,Default_Handler 247 | 248 | .weak TIM7_IRQHandler 249 | .thumb_set TIM7_IRQHandler,Default_Handler 250 | 251 | .weak TIM14_IRQHandler 252 | .thumb_set TIM14_IRQHandler,Default_Handler 253 | 254 | .weak TIM15_IRQHandler 255 | .thumb_set TIM15_IRQHandler,Default_Handler 256 | 257 | .weak TIM16_IRQHandler 258 | .thumb_set TIM16_IRQHandler,Default_Handler 259 | 260 | .weak TIM17_IRQHandler 261 | .thumb_set TIM17_IRQHandler,Default_Handler 262 | 263 | .weak I2C1_IRQHandler 264 | .thumb_set I2C1_IRQHandler,Default_Handler 265 | 266 | .weak I2C2_IRQHandler 267 | .thumb_set I2C2_IRQHandler,Default_Handler 268 | 269 | .weak SPI1_IRQHandler 270 | .thumb_set SPI1_IRQHandler,Default_Handler 271 | 272 | .weak SPI2_IRQHandler 273 | .thumb_set SPI2_IRQHandler,Default_Handler 274 | 275 | .weak USART1_IRQHandler 276 | .thumb_set USART1_IRQHandler,Default_Handler 277 | 278 | .weak USART2_IRQHandler 279 | .thumb_set USART2_IRQHandler,Default_Handler 280 | 281 | .weak USART3_4_IRQHandler 282 | .thumb_set USART3_4_IRQHandler,Default_Handler 283 | 284 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 285 | 286 | -------------------------------------------------------------------------------- /Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g030xx_flash.icf: -------------------------------------------------------------------------------- 1 | /*###ICF### Section handled by ICF editor, don't touch! ****/ 2 | /*-Editor annotation file-*/ 3 | /* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ 4 | /*-Specials-*/ 5 | define symbol __ICFEDIT_intvec_start__ = 0x08000000; 6 | /*-Memory Regions-*/ 7 | define symbol __ICFEDIT_region_ROM_start__ = 0x08000000; 8 | define symbol __ICFEDIT_region_ROM_end__ = 0x0800FFFF; 9 | define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; 10 | define symbol __ICFEDIT_region_RAM_end__ = 0x20001FFF; 11 | /*-Sizes-*/ 12 | define symbol __ICFEDIT_size_cstack__ = 0x400; 13 | define symbol __ICFEDIT_size_heap__ = 0x200; 14 | /**** End of ICF editor section. ###ICF###*/ 15 | 16 | define memory mem with size = 4G; 17 | define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; 18 | define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; 19 | 20 | define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; 21 | define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; 22 | 23 | initialize by copy { readwrite }; 24 | do not initialize { section .noinit }; 25 | 26 | place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; 27 | 28 | place in ROM_region { readonly }; 29 | place in RAM_region { readwrite, 30 | block CSTACK, block HEAP }; 31 | 32 | export symbol __ICFEDIT_region_RAM_start__; 33 | export symbol __ICFEDIT_region_RAM_end__; -------------------------------------------------------------------------------- /Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g030xx_sram.icf: -------------------------------------------------------------------------------- 1 | /*###ICF### Section handled by ICF editor, don't touch! ****/ 2 | /*-Editor annotation file-*/ 3 | /* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ 4 | /*-Specials-*/ 5 | define symbol __ICFEDIT_intvec_start__ = 0x20000000; 6 | /*-Memory Regions-*/ 7 | define symbol __ICFEDIT_region_ROM_start__ = 0x20000000; 8 | define symbol __ICFEDIT_region_ROM_end__ = 0x20000FFF; 9 | define symbol __ICFEDIT_region_RAM_start__ = 0x20001000; 10 | define symbol __ICFEDIT_region_RAM_end__ = 0x20001FFF; 11 | 12 | /*-Sizes-*/ 13 | define symbol __ICFEDIT_size_cstack__ = 0x400; 14 | define symbol __ICFEDIT_size_heap__ = 0x200; 15 | /**** End of ICF editor section. ###ICF###*/ 16 | 17 | 18 | define memory mem with size = 4G; 19 | define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; 20 | define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; 21 | 22 | 23 | define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; 24 | define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; 25 | 26 | initialize by copy { readwrite }; 27 | do not initialize { section .noinit }; 28 | 29 | place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; 30 | 31 | place in ROM_region { readonly }; 32 | place in RAM_region { readwrite, 33 | block CSTACK, block HEAP }; -------------------------------------------------------------------------------- /Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g031xx_flash.icf: -------------------------------------------------------------------------------- 1 | /*###ICF### Section handled by ICF editor, don't touch! ****/ 2 | /*-Editor annotation file-*/ 3 | /* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ 4 | /*-Specials-*/ 5 | define symbol __ICFEDIT_intvec_start__ = 0x08000000; 6 | /*-Memory Regions-*/ 7 | define symbol __ICFEDIT_region_ROM_start__ = 0x08000000; 8 | define symbol __ICFEDIT_region_ROM_end__ = 0x0800FFFF; 9 | define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; 10 | define symbol __ICFEDIT_region_RAM_end__ = 0x20001FFF; 11 | /*-Sizes-*/ 12 | define symbol __ICFEDIT_size_cstack__ = 0x400; 13 | define symbol __ICFEDIT_size_heap__ = 0x200; 14 | /**** End of ICF editor section. ###ICF###*/ 15 | 16 | define memory mem with size = 4G; 17 | define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; 18 | define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; 19 | 20 | define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; 21 | define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; 22 | 23 | initialize by copy { readwrite }; 24 | do not initialize { section .noinit }; 25 | 26 | place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; 27 | 28 | place in ROM_region { readonly }; 29 | place in RAM_region { readwrite, 30 | block CSTACK, block HEAP }; 31 | 32 | export symbol __ICFEDIT_region_RAM_start__; 33 | export symbol __ICFEDIT_region_RAM_end__; -------------------------------------------------------------------------------- /Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g031xx_sram.icf: -------------------------------------------------------------------------------- 1 | /*###ICF### Section handled by ICF editor, don't touch! ****/ 2 | /*-Editor annotation file-*/ 3 | /* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ 4 | /*-Specials-*/ 5 | define symbol __ICFEDIT_intvec_start__ = 0x20000000; 6 | /*-Memory Regions-*/ 7 | define symbol __ICFEDIT_region_ROM_start__ = 0x20000000; 8 | define symbol __ICFEDIT_region_ROM_end__ = 0x20000FFF; 9 | define symbol __ICFEDIT_region_RAM_start__ = 0x20001000; 10 | define symbol __ICFEDIT_region_RAM_end__ = 0x20001FFF; 11 | 12 | /*-Sizes-*/ 13 | define symbol __ICFEDIT_size_cstack__ = 0x400; 14 | define symbol __ICFEDIT_size_heap__ = 0x200; 15 | /**** End of ICF editor section. ###ICF###*/ 16 | 17 | 18 | define memory mem with size = 4G; 19 | define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; 20 | define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; 21 | 22 | 23 | define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; 24 | define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; 25 | 26 | initialize by copy { readwrite }; 27 | do not initialize { section .noinit }; 28 | 29 | place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; 30 | 31 | place in ROM_region { readonly }; 32 | place in RAM_region { readwrite, 33 | block CSTACK, block HEAP }; -------------------------------------------------------------------------------- /Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g041xx_flash.icf: -------------------------------------------------------------------------------- 1 | /*###ICF### Section handled by ICF editor, don't touch! ****/ 2 | /*-Editor annotation file-*/ 3 | /* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ 4 | /*-Specials-*/ 5 | define symbol __ICFEDIT_intvec_start__ = 0x08000000; 6 | /*-Memory Regions-*/ 7 | define symbol __ICFEDIT_region_ROM_start__ = 0x08000000; 8 | define symbol __ICFEDIT_region_ROM_end__ = 0x0800FFFF; 9 | define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; 10 | define symbol __ICFEDIT_region_RAM_end__ = 0x20001FFF; 11 | /*-Sizes-*/ 12 | define symbol __ICFEDIT_size_cstack__ = 0x400; 13 | define symbol __ICFEDIT_size_heap__ = 0x200; 14 | /**** End of ICF editor section. ###ICF###*/ 15 | 16 | define memory mem with size = 4G; 17 | define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; 18 | define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; 19 | 20 | define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; 21 | define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; 22 | 23 | initialize by copy { readwrite }; 24 | do not initialize { section .noinit }; 25 | 26 | place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; 27 | 28 | place in ROM_region { readonly }; 29 | place in RAM_region { readwrite, 30 | block CSTACK, block HEAP }; 31 | 32 | export symbol __ICFEDIT_region_RAM_start__; 33 | export symbol __ICFEDIT_region_RAM_end__; -------------------------------------------------------------------------------- /Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g041xx_sram.icf: -------------------------------------------------------------------------------- 1 | /*###ICF### Section handled by ICF editor, don't touch! ****/ 2 | /*-Editor annotation file-*/ 3 | /* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ 4 | /*-Specials-*/ 5 | define symbol __ICFEDIT_intvec_start__ = 0x20000000; 6 | /*-Memory Regions-*/ 7 | define symbol __ICFEDIT_region_ROM_start__ = 0x20000000; 8 | define symbol __ICFEDIT_region_ROM_end__ = 0x20000FFF; 9 | define symbol __ICFEDIT_region_RAM_start__ = 0x20001000; 10 | define symbol __ICFEDIT_region_RAM_end__ = 0x20001FFF; 11 | 12 | /*-Sizes-*/ 13 | define symbol __ICFEDIT_size_cstack__ = 0x400; 14 | define symbol __ICFEDIT_size_heap__ = 0x200; 15 | /**** End of ICF editor section. ###ICF###*/ 16 | 17 | 18 | define memory mem with size = 4G; 19 | define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; 20 | define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; 21 | 22 | 23 | define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; 24 | define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; 25 | 26 | initialize by copy { readwrite }; 27 | do not initialize { section .noinit }; 28 | 29 | place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; 30 | 31 | place in ROM_region { readonly }; 32 | place in RAM_region { readwrite, 33 | block CSTACK, block HEAP }; -------------------------------------------------------------------------------- /Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g050xx_flash.icf: -------------------------------------------------------------------------------- 1 | /*###ICF### Section handled by ICF editor, don't touch! ****/ 2 | /*-Editor annotation file-*/ 3 | /* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ 4 | /*-Specials-*/ 5 | define symbol __ICFEDIT_intvec_start__ = 0x08000000; 6 | /*-Memory Regions-*/ 7 | define symbol __ICFEDIT_region_ROM_start__ = 0x08000000; 8 | define symbol __ICFEDIT_region_ROM_end__ = 0x0800FFFF; 9 | define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; 10 | define symbol __ICFEDIT_region_RAM_end__ = 0x20003FFF; 11 | /*-Sizes-*/ 12 | define symbol __ICFEDIT_size_cstack__ = 0x400; 13 | define symbol __ICFEDIT_size_heap__ = 0x200; 14 | /**** End of ICF editor section. ###ICF###*/ 15 | 16 | define memory mem with size = 4G; 17 | define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; 18 | define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; 19 | 20 | define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; 21 | define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; 22 | 23 | initialize by copy { readwrite }; 24 | do not initialize { section .noinit }; 25 | 26 | place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; 27 | 28 | place in ROM_region { readonly }; 29 | place in RAM_region { readwrite, 30 | block CSTACK, block HEAP }; 31 | 32 | export symbol __ICFEDIT_region_RAM_start__; 33 | export symbol __ICFEDIT_region_RAM_end__; -------------------------------------------------------------------------------- /Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g050xx_sram.icf: -------------------------------------------------------------------------------- 1 | /*###ICF### Section handled by ICF editor, don't touch! ****/ 2 | /*-Editor annotation file-*/ 3 | /* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ 4 | /*-Specials-*/ 5 | define symbol __ICFEDIT_intvec_start__ = 0x20000000; 6 | /*-Memory Regions-*/ 7 | define symbol __ICFEDIT_region_ROM_start__ = 0x20000000; 8 | define symbol __ICFEDIT_region_ROM_end__ = 0x20001FFF; 9 | define symbol __ICFEDIT_region_RAM_start__ = 0x20002000; 10 | define symbol __ICFEDIT_region_RAM_end__ = 0x20003FFF; 11 | 12 | /*-Sizes-*/ 13 | define symbol __ICFEDIT_size_cstack__ = 0x400; 14 | define symbol __ICFEDIT_size_heap__ = 0x200; 15 | /**** End of ICF editor section. ###ICF###*/ 16 | 17 | 18 | define memory mem with size = 4G; 19 | define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; 20 | define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; 21 | 22 | 23 | define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; 24 | define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; 25 | 26 | initialize by copy { readwrite }; 27 | do not initialize { section .noinit }; 28 | 29 | place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; 30 | 31 | place in ROM_region { readonly }; 32 | place in RAM_region { readwrite, 33 | block CSTACK, block HEAP }; -------------------------------------------------------------------------------- /Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g051xx_flash.icf: -------------------------------------------------------------------------------- 1 | /*###ICF### Section handled by ICF editor, don't touch! ****/ 2 | /*-Editor annotation file-*/ 3 | /* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ 4 | /*-Specials-*/ 5 | define symbol __ICFEDIT_intvec_start__ = 0x08000000; 6 | /*-Memory Regions-*/ 7 | define symbol __ICFEDIT_region_ROM_start__ = 0x08000000; 8 | define symbol __ICFEDIT_region_ROM_end__ = 0x0800FFFF; 9 | define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; 10 | define symbol __ICFEDIT_region_RAM_end__ = 0x20003FFF; 11 | /*-Sizes-*/ 12 | define symbol __ICFEDIT_size_cstack__ = 0x400; 13 | define symbol __ICFEDIT_size_heap__ = 0x200; 14 | /**** End of ICF editor section. ###ICF###*/ 15 | 16 | define memory mem with size = 4G; 17 | define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; 18 | define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; 19 | 20 | define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; 21 | define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; 22 | 23 | initialize by copy { readwrite }; 24 | do not initialize { section .noinit }; 25 | 26 | place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; 27 | 28 | place in ROM_region { readonly }; 29 | place in RAM_region { readwrite, 30 | block CSTACK, block HEAP }; 31 | 32 | export symbol __ICFEDIT_region_RAM_start__; 33 | export symbol __ICFEDIT_region_RAM_end__; -------------------------------------------------------------------------------- /Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g051xx_sram.icf: -------------------------------------------------------------------------------- 1 | /*###ICF### Section handled by ICF editor, don't touch! ****/ 2 | /*-Editor annotation file-*/ 3 | /* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ 4 | /*-Specials-*/ 5 | define symbol __ICFEDIT_intvec_start__ = 0x20000000; 6 | /*-Memory Regions-*/ 7 | define symbol __ICFEDIT_region_ROM_start__ = 0x20000000; 8 | define symbol __ICFEDIT_region_ROM_end__ = 0x20001FFF; 9 | define symbol __ICFEDIT_region_RAM_start__ = 0x20002000; 10 | define symbol __ICFEDIT_region_RAM_end__ = 0x20003FFF; 11 | 12 | /*-Sizes-*/ 13 | define symbol __ICFEDIT_size_cstack__ = 0x400; 14 | define symbol __ICFEDIT_size_heap__ = 0x200; 15 | /**** End of ICF editor section. ###ICF###*/ 16 | 17 | 18 | define memory mem with size = 4G; 19 | define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; 20 | define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; 21 | 22 | 23 | define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; 24 | define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; 25 | 26 | initialize by copy { readwrite }; 27 | do not initialize { section .noinit }; 28 | 29 | place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; 30 | 31 | place in ROM_region { readonly }; 32 | place in RAM_region { readwrite, 33 | block CSTACK, block HEAP }; -------------------------------------------------------------------------------- /Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g061xx_flash.icf: -------------------------------------------------------------------------------- 1 | /*###ICF### Section handled by ICF editor, don't touch! ****/ 2 | /*-Editor annotation file-*/ 3 | /* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ 4 | /*-Specials-*/ 5 | define symbol __ICFEDIT_intvec_start__ = 0x08000000; 6 | /*-Memory Regions-*/ 7 | define symbol __ICFEDIT_region_ROM_start__ = 0x08000000; 8 | define symbol __ICFEDIT_region_ROM_end__ = 0x0800FFFF; 9 | define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; 10 | define symbol __ICFEDIT_region_RAM_end__ = 0x20003FFF; 11 | /*-Sizes-*/ 12 | define symbol __ICFEDIT_size_cstack__ = 0x400; 13 | define symbol __ICFEDIT_size_heap__ = 0x200; 14 | /**** End of ICF editor section. ###ICF###*/ 15 | 16 | define memory mem with size = 4G; 17 | define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; 18 | define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; 19 | 20 | define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; 21 | define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; 22 | 23 | initialize by copy { readwrite }; 24 | do not initialize { section .noinit }; 25 | 26 | place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; 27 | 28 | place in ROM_region { readonly }; 29 | place in RAM_region { readwrite, 30 | block CSTACK, block HEAP }; 31 | 32 | export symbol __ICFEDIT_region_RAM_start__; 33 | export symbol __ICFEDIT_region_RAM_end__; -------------------------------------------------------------------------------- /Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g061xx_sram.icf: -------------------------------------------------------------------------------- 1 | /*###ICF### Section handled by ICF editor, don't touch! ****/ 2 | /*-Editor annotation file-*/ 3 | /* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ 4 | /*-Specials-*/ 5 | define symbol __ICFEDIT_intvec_start__ = 0x20000000; 6 | /*-Memory Regions-*/ 7 | define symbol __ICFEDIT_region_ROM_start__ = 0x20000000; 8 | define symbol __ICFEDIT_region_ROM_end__ = 0x20001FFF; 9 | define symbol __ICFEDIT_region_RAM_start__ = 0x20002000; 10 | define symbol __ICFEDIT_region_RAM_end__ = 0x20003FFF; 11 | 12 | /*-Sizes-*/ 13 | define symbol __ICFEDIT_size_cstack__ = 0x400; 14 | define symbol __ICFEDIT_size_heap__ = 0x200; 15 | /**** End of ICF editor section. ###ICF###*/ 16 | 17 | 18 | define memory mem with size = 4G; 19 | define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; 20 | define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; 21 | 22 | 23 | define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; 24 | define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; 25 | 26 | initialize by copy { readwrite }; 27 | do not initialize { section .noinit }; 28 | 29 | place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; 30 | 31 | place in ROM_region { readonly }; 32 | place in RAM_region { readwrite, 33 | block CSTACK, block HEAP }; -------------------------------------------------------------------------------- /Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g070xx_flash.icf: -------------------------------------------------------------------------------- 1 | /*###ICF### Section handled by ICF editor, don't touch! ****/ 2 | /*-Editor annotation file-*/ 3 | /* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ 4 | /*-Specials-*/ 5 | define symbol __ICFEDIT_intvec_start__ = 0x08000000; 6 | /*-Memory Regions-*/ 7 | define symbol __ICFEDIT_region_ROM_start__ = 0x08000000; 8 | define symbol __ICFEDIT_region_ROM_end__ = 0x0801FFFF; 9 | define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; 10 | define symbol __ICFEDIT_region_RAM_end__ = 0x20008FFF; 11 | /*-Sizes-*/ 12 | define symbol __ICFEDIT_size_cstack__ = 0x400; 13 | define symbol __ICFEDIT_size_heap__ = 0x200; 14 | /**** End of ICF editor section. ###ICF###*/ 15 | 16 | define memory mem with size = 4G; 17 | define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; 18 | define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; 19 | 20 | define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; 21 | define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; 22 | 23 | initialize by copy { readwrite }; 24 | do not initialize { section .noinit }; 25 | 26 | place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; 27 | 28 | place in ROM_region { readonly }; 29 | place in RAM_region { readwrite, 30 | block CSTACK, block HEAP }; 31 | 32 | export symbol __ICFEDIT_region_RAM_start__; 33 | export symbol __ICFEDIT_region_RAM_end__; -------------------------------------------------------------------------------- /Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g070xx_sram.icf: -------------------------------------------------------------------------------- 1 | /*###ICF### Section handled by ICF editor, don't touch! ****/ 2 | /*-Editor annotation file-*/ 3 | /* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ 4 | /*-Specials-*/ 5 | define symbol __ICFEDIT_intvec_start__ = 0x20000000; 6 | /*-Memory Regions-*/ 7 | define symbol __ICFEDIT_region_ROM_start__ = 0x20000000; 8 | define symbol __ICFEDIT_region_ROM_end__ = 0x20002FFF; 9 | define symbol __ICFEDIT_region_RAM_start__ = 0x20003000; 10 | define symbol __ICFEDIT_region_RAM_end__ = 0x20008FFF; 11 | 12 | /*-Sizes-*/ 13 | define symbol __ICFEDIT_size_cstack__ = 0x400; 14 | define symbol __ICFEDIT_size_heap__ = 0x200; 15 | /**** End of ICF editor section. ###ICF###*/ 16 | 17 | 18 | define memory mem with size = 4G; 19 | define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; 20 | define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; 21 | 22 | 23 | define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; 24 | define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; 25 | 26 | initialize by copy { readwrite }; 27 | do not initialize { section .noinit }; 28 | 29 | place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; 30 | 31 | place in ROM_region { readonly }; 32 | place in RAM_region { readwrite, 33 | block CSTACK, block HEAP }; -------------------------------------------------------------------------------- /Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g071xx_flash.icf: -------------------------------------------------------------------------------- 1 | /*###ICF### Section handled by ICF editor, don't touch! ****/ 2 | /*-Editor annotation file-*/ 3 | /* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ 4 | /*-Specials-*/ 5 | define symbol __ICFEDIT_intvec_start__ = 0x08000000; 6 | /*-Memory Regions-*/ 7 | define symbol __ICFEDIT_region_ROM_start__ = 0x08000000; 8 | define symbol __ICFEDIT_region_ROM_end__ = 0x0801FFFF; 9 | define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; 10 | define symbol __ICFEDIT_region_RAM_end__ = 0x20008FFF; 11 | /*-Sizes-*/ 12 | define symbol __ICFEDIT_size_cstack__ = 0x400; 13 | define symbol __ICFEDIT_size_heap__ = 0x200; 14 | /**** End of ICF editor section. ###ICF###*/ 15 | 16 | define memory mem with size = 4G; 17 | define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; 18 | define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; 19 | 20 | define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; 21 | define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; 22 | 23 | initialize by copy { readwrite }; 24 | do not initialize { section .noinit }; 25 | 26 | place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; 27 | 28 | place in ROM_region { readonly }; 29 | place in RAM_region { readwrite, 30 | block CSTACK, block HEAP }; 31 | 32 | export symbol __ICFEDIT_region_RAM_start__; 33 | export symbol __ICFEDIT_region_RAM_end__; -------------------------------------------------------------------------------- /Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g071xx_sram.icf: -------------------------------------------------------------------------------- 1 | /*###ICF### Section handled by ICF editor, don't touch! ****/ 2 | /*-Editor annotation file-*/ 3 | /* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ 4 | /*-Specials-*/ 5 | define symbol __ICFEDIT_intvec_start__ = 0x20000000; 6 | /*-Memory Regions-*/ 7 | define symbol __ICFEDIT_region_ROM_start__ = 0x20000000; 8 | define symbol __ICFEDIT_region_ROM_end__ = 0x20002FFF; 9 | define symbol __ICFEDIT_region_RAM_start__ = 0x20003000; 10 | define symbol __ICFEDIT_region_RAM_end__ = 0x20008FFF; 11 | 12 | /*-Sizes-*/ 13 | define symbol __ICFEDIT_size_cstack__ = 0x400; 14 | define symbol __ICFEDIT_size_heap__ = 0x200; 15 | /**** End of ICF editor section. ###ICF###*/ 16 | 17 | 18 | define memory mem with size = 4G; 19 | define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; 20 | define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; 21 | 22 | 23 | define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; 24 | define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; 25 | 26 | initialize by copy { readwrite }; 27 | do not initialize { section .noinit }; 28 | 29 | place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; 30 | 31 | place in ROM_region { readonly }; 32 | place in RAM_region { readwrite, 33 | block CSTACK, block HEAP }; -------------------------------------------------------------------------------- /Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g081xx_flash.icf: -------------------------------------------------------------------------------- 1 | /*###ICF### Section handled by ICF editor, don't touch! ****/ 2 | /*-Editor annotation file-*/ 3 | /* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ 4 | /*-Specials-*/ 5 | define symbol __ICFEDIT_intvec_start__ = 0x08000000; 6 | /*-Memory Regions-*/ 7 | define symbol __ICFEDIT_region_ROM_start__ = 0x08000000; 8 | define symbol __ICFEDIT_region_ROM_end__ = 0x0801FFFF; 9 | define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; 10 | define symbol __ICFEDIT_region_RAM_end__ = 0x20008FFF; 11 | /*-Sizes-*/ 12 | define symbol __ICFEDIT_size_cstack__ = 0x400; 13 | define symbol __ICFEDIT_size_heap__ = 0x200; 14 | /**** End of ICF editor section. ###ICF###*/ 15 | 16 | define memory mem with size = 4G; 17 | define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; 18 | define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; 19 | 20 | define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; 21 | define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; 22 | 23 | initialize by copy { readwrite }; 24 | do not initialize { section .noinit }; 25 | 26 | place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; 27 | 28 | place in ROM_region { readonly }; 29 | place in RAM_region { readwrite, 30 | block CSTACK, block HEAP }; 31 | 32 | export symbol __ICFEDIT_region_RAM_start__; 33 | export symbol __ICFEDIT_region_RAM_end__; -------------------------------------------------------------------------------- /Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g081xx_sram.icf: -------------------------------------------------------------------------------- 1 | /*###ICF### Section handled by ICF editor, don't touch! ****/ 2 | /*-Editor annotation file-*/ 3 | /* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ 4 | /*-Specials-*/ 5 | define symbol __ICFEDIT_intvec_start__ = 0x20000000; 6 | /*-Memory Regions-*/ 7 | define symbol __ICFEDIT_region_ROM_start__ = 0x20000000; 8 | define symbol __ICFEDIT_region_ROM_end__ = 0x20004FFF; 9 | define symbol __ICFEDIT_region_RAM_start__ = 0x20005000; 10 | define symbol __ICFEDIT_region_RAM_end__ = 0x20008FFF; 11 | 12 | /*-Sizes-*/ 13 | define symbol __ICFEDIT_size_cstack__ = 0x400; 14 | define symbol __ICFEDIT_size_heap__ = 0x200; 15 | /**** End of ICF editor section. ###ICF###*/ 16 | 17 | define memory mem with size = 4G; 18 | define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; 19 | define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; 20 | 21 | define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; 22 | define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; 23 | 24 | initialize by copy { readwrite }; 25 | do not initialize { section .noinit }; 26 | 27 | place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; 28 | 29 | place in ROM_region { readonly }; 30 | place in RAM_region { readwrite, 31 | block CSTACK, block HEAP }; -------------------------------------------------------------------------------- /Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g0b0xx_flash.icf: -------------------------------------------------------------------------------- 1 | /*###ICF### Section handled by ICF editor, don't touch! ****/ 2 | /*-Editor annotation file-*/ 3 | /* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ 4 | /*-Specials-*/ 5 | define symbol __ICFEDIT_intvec_start__ = 0x08000000; 6 | /*-Memory Regions-*/ 7 | define symbol __ICFEDIT_region_ROM_start__ = 0x08000000; 8 | define symbol __ICFEDIT_region_ROM_end__ = 0x0807FFFF; 9 | define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; 10 | define symbol __ICFEDIT_region_RAM_end__ = 0x20023FFF; 11 | 12 | /*-Sizes-*/ 13 | define symbol __ICFEDIT_size_cstack__ = 0x400; 14 | define symbol __ICFEDIT_size_heap__ = 0x200; 15 | /**** End of ICF editor section. ###ICF###*/ 16 | 17 | define memory mem with size = 4G; 18 | define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; 19 | define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; 20 | 21 | define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; 22 | define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; 23 | 24 | initialize by copy { readwrite }; 25 | do not initialize { section .noinit }; 26 | 27 | place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; 28 | 29 | place in ROM_region { readonly }; 30 | place in RAM_region { readwrite, 31 | block CSTACK, block HEAP }; 32 | 33 | export symbol __ICFEDIT_region_RAM_start__; 34 | export symbol __ICFEDIT_region_RAM_end__; -------------------------------------------------------------------------------- /Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g0b0xx_sram.icf: -------------------------------------------------------------------------------- 1 | /*###ICF### Section handled by ICF editor, don't touch! ****/ 2 | /*-Editor annotation file-*/ 3 | /* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ 4 | /*-Specials-*/ 5 | define symbol __ICFEDIT_intvec_start__ = 0x20000000; 6 | /*-Memory Regions-*/ 7 | define symbol __ICFEDIT_region_ROM_start__ = 0x20000000; 8 | define symbol __ICFEDIT_region_ROM_end__ = 0x20004FFF; 9 | define symbol __ICFEDIT_region_RAM_start__ = 0x20005000; 10 | define symbol __ICFEDIT_region_RAM_end__ = 0x20023FFF; 11 | 12 | /*-Sizes-*/ 13 | define symbol __ICFEDIT_size_cstack__ = 0x400; 14 | define symbol __ICFEDIT_size_heap__ = 0x200; 15 | /**** End of ICF editor section. ###ICF###*/ 16 | 17 | define memory mem with size = 4G; 18 | define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; 19 | define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; 20 | 21 | define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; 22 | define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; 23 | 24 | initialize by copy { readwrite }; 25 | do not initialize { section .noinit }; 26 | 27 | place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; 28 | 29 | place in ROM_region { readonly }; 30 | place in RAM_region { readwrite, 31 | block CSTACK, block HEAP }; -------------------------------------------------------------------------------- /Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g0b1xx_flash.icf: -------------------------------------------------------------------------------- 1 | /*###ICF### Section handled by ICF editor, don't touch! ****/ 2 | /*-Editor annotation file-*/ 3 | /* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ 4 | /*-Specials-*/ 5 | define symbol __ICFEDIT_intvec_start__ = 0x08000000; 6 | /*-Memory Regions-*/ 7 | define symbol __ICFEDIT_region_ROM_start__ = 0x08000000; 8 | define symbol __ICFEDIT_region_ROM_end__ = 0x0807FFFF; 9 | define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; 10 | define symbol __ICFEDIT_region_RAM_end__ = 0x20023FFF; 11 | 12 | /*-Sizes-*/ 13 | define symbol __ICFEDIT_size_cstack__ = 0x400; 14 | define symbol __ICFEDIT_size_heap__ = 0x200; 15 | /**** End of ICF editor section. ###ICF###*/ 16 | 17 | define memory mem with size = 4G; 18 | define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; 19 | define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; 20 | 21 | define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; 22 | define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; 23 | 24 | initialize by copy { readwrite }; 25 | do not initialize { section .noinit }; 26 | 27 | place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; 28 | 29 | place in ROM_region { readonly }; 30 | place in RAM_region { readwrite, 31 | block CSTACK, block HEAP }; 32 | 33 | export symbol __ICFEDIT_region_RAM_start__; 34 | export symbol __ICFEDIT_region_RAM_end__; -------------------------------------------------------------------------------- /Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g0b1xx_sram.icf: -------------------------------------------------------------------------------- 1 | /*###ICF### Section handled by ICF editor, don't touch! ****/ 2 | /*-Editor annotation file-*/ 3 | /* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ 4 | /*-Specials-*/ 5 | define symbol __ICFEDIT_intvec_start__ = 0x20000000; 6 | /*-Memory Regions-*/ 7 | define symbol __ICFEDIT_region_ROM_start__ = 0x20000000; 8 | define symbol __ICFEDIT_region_ROM_end__ = 0x20004FFF; 9 | define symbol __ICFEDIT_region_RAM_start__ = 0x20005000; 10 | define symbol __ICFEDIT_region_RAM_end__ = 0x20023FFF; 11 | 12 | /*-Sizes-*/ 13 | define symbol __ICFEDIT_size_cstack__ = 0x400; 14 | define symbol __ICFEDIT_size_heap__ = 0x200; 15 | /**** End of ICF editor section. ###ICF###*/ 16 | 17 | define memory mem with size = 4G; 18 | define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; 19 | define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; 20 | 21 | define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; 22 | define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; 23 | 24 | initialize by copy { readwrite }; 25 | do not initialize { section .noinit }; 26 | 27 | place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; 28 | 29 | place in ROM_region { readonly }; 30 | place in RAM_region { readwrite, 31 | block CSTACK, block HEAP }; -------------------------------------------------------------------------------- /Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g0c1xx_flash.icf: -------------------------------------------------------------------------------- 1 | /*###ICF### Section handled by ICF editor, don't touch! ****/ 2 | /*-Editor annotation file-*/ 3 | /* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ 4 | /*-Specials-*/ 5 | define symbol __ICFEDIT_intvec_start__ = 0x08000000; 6 | /*-Memory Regions-*/ 7 | define symbol __ICFEDIT_region_ROM_start__ = 0x08000000; 8 | define symbol __ICFEDIT_region_ROM_end__ = 0x0807FFFF; 9 | define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; 10 | define symbol __ICFEDIT_region_RAM_end__ = 0x20023FFF; 11 | 12 | /*-Sizes-*/ 13 | define symbol __ICFEDIT_size_cstack__ = 0x400; 14 | define symbol __ICFEDIT_size_heap__ = 0x200; 15 | /**** End of ICF editor section. ###ICF###*/ 16 | 17 | define memory mem with size = 4G; 18 | define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; 19 | define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; 20 | 21 | define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; 22 | define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; 23 | 24 | initialize by copy { readwrite }; 25 | do not initialize { section .noinit }; 26 | 27 | place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; 28 | 29 | place in ROM_region { readonly }; 30 | place in RAM_region { readwrite, 31 | block CSTACK, block HEAP }; 32 | 33 | export symbol __ICFEDIT_region_RAM_start__; 34 | export symbol __ICFEDIT_region_RAM_end__; -------------------------------------------------------------------------------- /Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/linker/stm32g0c1xx_sram.icf: -------------------------------------------------------------------------------- 1 | /*###ICF### Section handled by ICF editor, don't touch! ****/ 2 | /*-Editor annotation file-*/ 3 | /* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ 4 | /*-Specials-*/ 5 | define symbol __ICFEDIT_intvec_start__ = 0x20000000; 6 | /*-Memory Regions-*/ 7 | define symbol __ICFEDIT_region_ROM_start__ = 0x20000000; 8 | define symbol __ICFEDIT_region_ROM_end__ = 0x20004FFF; 9 | define symbol __ICFEDIT_region_RAM_start__ = 0x20005000; 10 | define symbol __ICFEDIT_region_RAM_end__ = 0x20023FFF; 11 | 12 | /*-Sizes-*/ 13 | define symbol __ICFEDIT_size_cstack__ = 0x400; 14 | define symbol __ICFEDIT_size_heap__ = 0x200; 15 | /**** End of ICF editor section. ###ICF###*/ 16 | 17 | define memory mem with size = 4G; 18 | define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; 19 | define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; 20 | 21 | define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; 22 | define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; 23 | 24 | initialize by copy { readwrite }; 25 | do not initialize { section .noinit }; 26 | 27 | place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; 28 | 29 | place in ROM_region { readonly }; 30 | place in RAM_region { readwrite, 31 | block CSTACK, block HEAP }; -------------------------------------------------------------------------------- /Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/startup_stm32g030xx.s: -------------------------------------------------------------------------------- 1 | ;****************************************************************************** 2 | ;* File Name : startup_stm32g030xx.s 3 | ;* Author : MCD Application Team 4 | ;* Description : STM32G030xx devices vector table for EWARM toolchain. 5 | ;* This module performs: 6 | ;* - Set the initial SP 7 | ;* - Set the initial PC == __iar_program_start, 8 | ;* - Set the vector table entries with the exceptions ISR 9 | ;* address 10 | ;* - Branches to main in the C library (which eventually 11 | ;* calls main()). 12 | ;* After Reset the Cortex-M0+ processor is in Thread mode, 13 | ;* priority is Privileged, and the Stack is set to Main. 14 | ;******************************************************************************** 15 | ;* 16 | ;* Copyright (c) 2018-2021 STMicroelectronics. 17 | ;* All rights reserved. 18 | ;* 19 | ;* This software is licensed under terms that can be found in the LICENSE file 20 | ;* in the root directory of this software component. 21 | ;* If no LICENSE file comes with this software, it is provided AS-IS. 22 | ; 23 | ;******************************************************************************* 24 | ; 25 | ; The modules in this file are included in the libraries, and may be replaced 26 | ; by any user-defined modules that define the PUBLIC symbol _program_start or 27 | ; a user defined start symbol. 28 | ; To override the cstartup defined in the library, simply add your modified 29 | ; version to the workbench project. 30 | ; 31 | ; The vector table is normally located at address 0. 32 | ; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. 33 | ; The name "__vector_table" has special meaning for C-SPY: 34 | ; it is where the SP start value is found, and the NVIC vector 35 | ; table register (VTOR) is initialized to this address if != 0. 36 | ; 37 | ; Cortex-M version 38 | ; 39 | 40 | MODULE ?cstartup 41 | 42 | ;; Forward declaration of sections. 43 | SECTION CSTACK:DATA:NOROOT(3) 44 | 45 | SECTION .intvec:CODE:NOROOT(2) 46 | 47 | EXTERN __iar_program_start 48 | EXTERN SystemInit 49 | PUBLIC __vector_table 50 | 51 | DATA 52 | __vector_table 53 | DCD sfe(CSTACK) 54 | DCD Reset_Handler ; Reset Handler 55 | 56 | DCD NMI_Handler ; NMI Handler 57 | DCD HardFault_Handler ; Hard Fault Handler 58 | DCD 0 ; Reserved 59 | DCD 0 ; Reserved 60 | DCD 0 ; Reserved 61 | DCD 0 ; Reserved 62 | DCD 0 ; Reserved 63 | DCD 0 ; Reserved 64 | DCD 0 ; Reserved 65 | DCD SVC_Handler ; SVCall Handler 66 | DCD 0 ; Reserved 67 | DCD 0 ; Reserved 68 | DCD PendSV_Handler ; PendSV Handler 69 | DCD SysTick_Handler ; SysTick Handler 70 | 71 | ; External Interrupts 72 | DCD WWDG_IRQHandler ; Window Watchdog 73 | DCD 0 ; Reserved 74 | DCD RTC_TAMP_IRQHandler ; RTC through EXTI Line 75 | DCD FLASH_IRQHandler ; FLASH 76 | DCD RCC_IRQHandler ; RCC 77 | DCD EXTI0_1_IRQHandler ; EXTI Line 0 and 1 78 | DCD EXTI2_3_IRQHandler ; EXTI Line 2 and 3 79 | DCD EXTI4_15_IRQHandler ; EXTI Line 4 to 15 80 | DCD 0 ; Reserved 81 | DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 82 | DCD DMA1_Channel2_3_IRQHandler ; DMA1 Channel 2 and Channel 3 83 | DCD DMA1_Ch4_5_DMAMUX1_OVR_IRQHandler ; DMA1 Channel 4 and Channel 5 DMAMUX1 overrun 84 | DCD ADC1_IRQHandler ; ADC1 85 | DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation 86 | DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare 87 | DCD 0 ; Reserved 88 | DCD TIM3_IRQHandler ; TIM3 89 | DCD 0 ; Reserved 90 | DCD 0 ; Reserved 91 | DCD TIM14_IRQHandler ; TIM14 92 | DCD 0 ; Reserved 93 | DCD TIM16_IRQHandler ; TIM16 94 | DCD TIM17_IRQHandler ; TIM17 95 | DCD I2C1_IRQHandler ; I2C1 96 | DCD I2C2_IRQHandler ; I2C2 97 | DCD SPI1_IRQHandler ; SPI1 98 | DCD SPI2_IRQHandler ; SPI2 99 | DCD USART1_IRQHandler ; USART1 100 | DCD USART2_IRQHandler ; USART2 101 | DCD 0 ; Reserved 102 | DCD 0 ; Reserved 103 | DCD 0 ; Reserved 104 | 105 | ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; 106 | ;; 107 | ;; Default interrupt handlers. 108 | ;; 109 | THUMB 110 | 111 | PUBWEAK Reset_Handler 112 | SECTION .text:CODE:NOROOT:REORDER(2) 113 | Reset_Handler 114 | LDR R0, =SystemInit 115 | BLX R0 116 | LDR R0, =__iar_program_start 117 | BX R0 118 | 119 | PUBWEAK NMI_Handler 120 | SECTION .text:CODE:NOROOT:REORDER(1) 121 | NMI_Handler 122 | B NMI_Handler 123 | 124 | PUBWEAK HardFault_Handler 125 | SECTION .text:CODE:NOROOT:REORDER(1) 126 | HardFault_Handler 127 | B HardFault_Handler 128 | 129 | PUBWEAK SVC_Handler 130 | SECTION .text:CODE:NOROOT:REORDER(1) 131 | SVC_Handler 132 | B SVC_Handler 133 | 134 | PUBWEAK PendSV_Handler 135 | SECTION .text:CODE:NOROOT:REORDER(1) 136 | PendSV_Handler 137 | B PendSV_Handler 138 | 139 | PUBWEAK SysTick_Handler 140 | SECTION .text:CODE:NOROOT:REORDER(1) 141 | SysTick_Handler 142 | B SysTick_Handler 143 | 144 | PUBWEAK WWDG_IRQHandler 145 | SECTION .text:CODE:NOROOT:REORDER(1) 146 | WWDG_IRQHandler 147 | B WWDG_IRQHandler 148 | 149 | PUBWEAK RTC_TAMP_IRQHandler 150 | SECTION .text:CODE:NOROOT:REORDER(1) 151 | RTC_TAMP_IRQHandler 152 | B RTC_TAMP_IRQHandler 153 | 154 | PUBWEAK FLASH_IRQHandler 155 | SECTION .text:CODE:NOROOT:REORDER(1) 156 | FLASH_IRQHandler 157 | B FLASH_IRQHandler 158 | 159 | PUBWEAK RCC_IRQHandler 160 | SECTION .text:CODE:NOROOT:REORDER(1) 161 | RCC_IRQHandler 162 | B RCC_IRQHandler 163 | 164 | PUBWEAK EXTI0_1_IRQHandler 165 | SECTION .text:CODE:NOROOT:REORDER(1) 166 | EXTI0_1_IRQHandler 167 | B EXTI0_1_IRQHandler 168 | 169 | PUBWEAK EXTI2_3_IRQHandler 170 | SECTION .text:CODE:NOROOT:REORDER(1) 171 | EXTI2_3_IRQHandler 172 | B EXTI2_3_IRQHandler 173 | 174 | PUBWEAK EXTI4_15_IRQHandler 175 | SECTION .text:CODE:NOROOT:REORDER(1) 176 | EXTI4_15_IRQHandler 177 | B EXTI4_15_IRQHandler 178 | 179 | PUBWEAK DMA1_Channel1_IRQHandler 180 | SECTION .text:CODE:NOROOT:REORDER(1) 181 | DMA1_Channel1_IRQHandler 182 | B DMA1_Channel1_IRQHandler 183 | 184 | PUBWEAK DMA1_Channel2_3_IRQHandler 185 | SECTION .text:CODE:NOROOT:REORDER(1) 186 | DMA1_Channel2_3_IRQHandler 187 | B DMA1_Channel2_3_IRQHandler 188 | 189 | PUBWEAK DMA1_Ch4_5_DMAMUX1_OVR_IRQHandler 190 | SECTION .text:CODE:NOROOT:REORDER(1) 191 | DMA1_Ch4_5_DMAMUX1_OVR_IRQHandler 192 | B DMA1_Ch4_5_DMAMUX1_OVR_IRQHandler 193 | 194 | PUBWEAK ADC1_IRQHandler 195 | SECTION .text:CODE:NOROOT:REORDER(1) 196 | ADC1_IRQHandler 197 | B ADC1_IRQHandler 198 | 199 | PUBWEAK TIM1_BRK_UP_TRG_COM_IRQHandler 200 | SECTION .text:CODE:NOROOT:REORDER(1) 201 | TIM1_BRK_UP_TRG_COM_IRQHandler 202 | B TIM1_BRK_UP_TRG_COM_IRQHandler 203 | 204 | PUBWEAK TIM1_CC_IRQHandler 205 | SECTION .text:CODE:NOROOT:REORDER(1) 206 | TIM1_CC_IRQHandler 207 | B TIM1_CC_IRQHandler 208 | 209 | PUBWEAK TIM3_IRQHandler 210 | SECTION .text:CODE:NOROOT:REORDER(1) 211 | TIM3_IRQHandler 212 | B TIM3_IRQHandler 213 | 214 | PUBWEAK TIM14_IRQHandler 215 | SECTION .text:CODE:NOROOT:REORDER(1) 216 | TIM14_IRQHandler 217 | B TIM14_IRQHandler 218 | 219 | PUBWEAK TIM16_IRQHandler 220 | SECTION .text:CODE:NOROOT:REORDER(1) 221 | TIM16_IRQHandler 222 | B TIM16_IRQHandler 223 | 224 | PUBWEAK TIM17_IRQHandler 225 | SECTION .text:CODE:NOROOT:REORDER(1) 226 | TIM17_IRQHandler 227 | B TIM17_IRQHandler 228 | 229 | PUBWEAK I2C1_IRQHandler 230 | SECTION .text:CODE:NOROOT:REORDER(1) 231 | I2C1_IRQHandler 232 | B I2C1_IRQHandler 233 | 234 | PUBWEAK I2C2_IRQHandler 235 | SECTION .text:CODE:NOROOT:REORDER(1) 236 | I2C2_IRQHandler 237 | B I2C2_IRQHandler 238 | 239 | PUBWEAK SPI1_IRQHandler 240 | SECTION .text:CODE:NOROOT:REORDER(1) 241 | SPI1_IRQHandler 242 | B SPI1_IRQHandler 243 | 244 | PUBWEAK SPI2_IRQHandler 245 | SECTION .text:CODE:NOROOT:REORDER(1) 246 | SPI2_IRQHandler 247 | B SPI2_IRQHandler 248 | 249 | PUBWEAK USART1_IRQHandler 250 | SECTION .text:CODE:NOROOT:REORDER(1) 251 | USART1_IRQHandler 252 | B USART1_IRQHandler 253 | 254 | PUBWEAK USART2_IRQHandler 255 | SECTION .text:CODE:NOROOT:REORDER(1) 256 | USART2_IRQHandler 257 | B USART2_IRQHandler 258 | 259 | END 260 | ;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** 261 | -------------------------------------------------------------------------------- /Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/iar/startup_stm32g050xx.s: -------------------------------------------------------------------------------- 1 | ;****************************************************************************** 2 | ;* File Name : startup_stm32g050xx.s 3 | ;* Author : MCD Application Team 4 | ;* Description : STM32G050xx devices vector table for EWARM toolchain. 5 | ;* This module performs: 6 | ;* - Set the initial SP 7 | ;* - Set the initial PC == __iar_program_start, 8 | ;* - Set the vector table entries with the exceptions ISR 9 | ;* address 10 | ;* - Branches to main in the C library (which eventually 11 | ;* calls main()). 12 | ;* After Reset the Cortex-M0+ processor is in Thread mode, 13 | ;* priority is Privileged, and the Stack is set to Main. 14 | ;******************************************************************************** 15 | ;* 16 | ;* Copyright (c) 2018-2021 STMicroelectronics. 17 | ;* All rights reserved. 18 | ;* 19 | ;* This software is licensed under terms that can be found in the LICENSE file 20 | ;* in the root directory of this software component. 21 | ;* If no LICENSE file comes with this software, it is provided AS-IS. 22 | ; 23 | ;******************************************************************************* 24 | ; 25 | ; The modules in this file are included in the libraries, and may be replaced 26 | ; by any user-defined modules that define the PUBLIC symbol _program_start or 27 | ; a user defined start symbol. 28 | ; To override the cstartup defined in the library, simply add your modified 29 | ; version to the workbench project. 30 | ; 31 | ; The vector table is normally located at address 0. 32 | ; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. 33 | ; The name "__vector_table" has special meaning for C-SPY: 34 | ; it is where the SP start value is found, and the NVIC vector 35 | ; table register (VTOR) is initialized to this address if != 0. 36 | ; 37 | ; Cortex-M version 38 | ; 39 | 40 | MODULE ?cstartup 41 | 42 | ;; Forward declaration of sections. 43 | SECTION CSTACK:DATA:NOROOT(3) 44 | 45 | SECTION .intvec:CODE:NOROOT(2) 46 | 47 | EXTERN __iar_program_start 48 | EXTERN SystemInit 49 | PUBLIC __vector_table 50 | 51 | DATA 52 | __vector_table 53 | DCD sfe(CSTACK) 54 | DCD Reset_Handler ; Reset Handler 55 | 56 | DCD NMI_Handler ; NMI Handler 57 | DCD HardFault_Handler ; Hard Fault Handler 58 | DCD 0 ; Reserved 59 | DCD 0 ; Reserved 60 | DCD 0 ; Reserved 61 | DCD 0 ; Reserved 62 | DCD 0 ; Reserved 63 | DCD 0 ; Reserved 64 | DCD 0 ; Reserved 65 | DCD SVC_Handler ; SVCall Handler 66 | DCD 0 ; Reserved 67 | DCD 0 ; Reserved 68 | DCD PendSV_Handler ; PendSV Handler 69 | DCD SysTick_Handler ; SysTick Handler 70 | 71 | ; External Interrupts 72 | DCD WWDG_IRQHandler ; Window Watchdog 73 | DCD 0 ; Reserved 74 | DCD RTC_TAMP_IRQHandler ; RTC through EXTI Line 75 | DCD FLASH_IRQHandler ; FLASH 76 | DCD RCC_IRQHandler ; RCC 77 | DCD EXTI0_1_IRQHandler ; EXTI Line 0 and 1 78 | DCD EXTI2_3_IRQHandler ; EXTI Line 2 and 3 79 | DCD EXTI4_15_IRQHandler ; EXTI Line 4 to 15 80 | DCD 0 ; Reserved 81 | DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 82 | DCD DMA1_Channel2_3_IRQHandler ; DMA1 Channel 2 and Channel 3 83 | DCD DMA1_Ch4_7_DMAMUX1_OVR_IRQHandler ; DMA1 Channel 4 to Channel 7, DMAMUX1 overrun 84 | DCD ADC1_IRQHandler ; ADC1 85 | DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation 86 | DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare 87 | DCD 0 ; Reserved 88 | DCD TIM3_IRQHandler ; TIM3 89 | DCD TIM6_IRQHandler ; TIM6 90 | DCD TIM7_IRQHandler ; TIM7 91 | DCD TIM14_IRQHandler ; TIM14 92 | DCD TIM15_IRQHandler ; TIM15 93 | DCD TIM16_IRQHandler ; TIM16 94 | DCD TIM17_IRQHandler ; TIM17 95 | DCD I2C1_IRQHandler ; I2C1 96 | DCD I2C2_IRQHandler ; I2C2 97 | DCD SPI1_IRQHandler ; SPI1 98 | DCD SPI2_IRQHandler ; SPI2 99 | DCD USART1_IRQHandler ; USART1 100 | DCD USART2_IRQHandler ; USART2 101 | DCD 0 ; Reserved 102 | DCD 0 ; Reserved 103 | DCD 0 ; Reserved 104 | 105 | ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; 106 | ;; 107 | ;; Default interrupt handlers. 108 | ;; 109 | THUMB 110 | 111 | PUBWEAK Reset_Handler 112 | SECTION .text:CODE:NOROOT:REORDER(2) 113 | Reset_Handler 114 | LDR R0, =SystemInit 115 | BLX R0 116 | LDR R0, =__iar_program_start 117 | BX R0 118 | 119 | PUBWEAK NMI_Handler 120 | SECTION .text:CODE:NOROOT:REORDER(1) 121 | NMI_Handler 122 | B NMI_Handler 123 | 124 | PUBWEAK HardFault_Handler 125 | SECTION .text:CODE:NOROOT:REORDER(1) 126 | HardFault_Handler 127 | B HardFault_Handler 128 | 129 | PUBWEAK SVC_Handler 130 | SECTION .text:CODE:NOROOT:REORDER(1) 131 | SVC_Handler 132 | B SVC_Handler 133 | 134 | PUBWEAK PendSV_Handler 135 | SECTION .text:CODE:NOROOT:REORDER(1) 136 | PendSV_Handler 137 | B PendSV_Handler 138 | 139 | PUBWEAK SysTick_Handler 140 | SECTION .text:CODE:NOROOT:REORDER(1) 141 | SysTick_Handler 142 | B SysTick_Handler 143 | 144 | PUBWEAK WWDG_IRQHandler 145 | SECTION .text:CODE:NOROOT:REORDER(1) 146 | WWDG_IRQHandler 147 | B WWDG_IRQHandler 148 | 149 | PUBWEAK RTC_TAMP_IRQHandler 150 | SECTION .text:CODE:NOROOT:REORDER(1) 151 | RTC_TAMP_IRQHandler 152 | B RTC_TAMP_IRQHandler 153 | 154 | PUBWEAK FLASH_IRQHandler 155 | SECTION .text:CODE:NOROOT:REORDER(1) 156 | FLASH_IRQHandler 157 | B FLASH_IRQHandler 158 | 159 | PUBWEAK RCC_IRQHandler 160 | SECTION .text:CODE:NOROOT:REORDER(1) 161 | RCC_IRQHandler 162 | B RCC_IRQHandler 163 | 164 | PUBWEAK EXTI0_1_IRQHandler 165 | SECTION .text:CODE:NOROOT:REORDER(1) 166 | EXTI0_1_IRQHandler 167 | B EXTI0_1_IRQHandler 168 | 169 | PUBWEAK EXTI2_3_IRQHandler 170 | SECTION .text:CODE:NOROOT:REORDER(1) 171 | EXTI2_3_IRQHandler 172 | B EXTI2_3_IRQHandler 173 | 174 | PUBWEAK EXTI4_15_IRQHandler 175 | SECTION .text:CODE:NOROOT:REORDER(1) 176 | EXTI4_15_IRQHandler 177 | B EXTI4_15_IRQHandler 178 | 179 | PUBWEAK DMA1_Channel1_IRQHandler 180 | SECTION .text:CODE:NOROOT:REORDER(1) 181 | DMA1_Channel1_IRQHandler 182 | B DMA1_Channel1_IRQHandler 183 | 184 | PUBWEAK DMA1_Channel2_3_IRQHandler 185 | SECTION .text:CODE:NOROOT:REORDER(1) 186 | DMA1_Channel2_3_IRQHandler 187 | B DMA1_Channel2_3_IRQHandler 188 | 189 | PUBWEAK DMA1_Ch4_7_DMAMUX1_OVR_IRQHandler 190 | SECTION .text:CODE:NOROOT:REORDER(1) 191 | DMA1_Ch4_7_DMAMUX1_OVR_IRQHandler 192 | B DMA1_Ch4_7_DMAMUX1_OVR_IRQHandler 193 | 194 | PUBWEAK ADC1_IRQHandler 195 | SECTION .text:CODE:NOROOT:REORDER(1) 196 | ADC1_IRQHandler 197 | B ADC1_IRQHandler 198 | 199 | PUBWEAK TIM1_BRK_UP_TRG_COM_IRQHandler 200 | SECTION .text:CODE:NOROOT:REORDER(1) 201 | TIM1_BRK_UP_TRG_COM_IRQHandler 202 | B TIM1_BRK_UP_TRG_COM_IRQHandler 203 | 204 | PUBWEAK TIM1_CC_IRQHandler 205 | SECTION .text:CODE:NOROOT:REORDER(1) 206 | TIM1_CC_IRQHandler 207 | B TIM1_CC_IRQHandler 208 | 209 | PUBWEAK TIM3_IRQHandler 210 | SECTION .text:CODE:NOROOT:REORDER(1) 211 | TIM3_IRQHandler 212 | B TIM3_IRQHandler 213 | 214 | PUBWEAK TIM6_IRQHandler 215 | SECTION .text:CODE:NOROOT:REORDER(1) 216 | TIM6_IRQHandler 217 | B TIM6_IRQHandler 218 | 219 | PUBWEAK TIM7_IRQHandler 220 | SECTION .text:CODE:NOROOT:REORDER(1) 221 | TIM7_IRQHandler 222 | B TIM7_IRQHandler 223 | 224 | PUBWEAK TIM14_IRQHandler 225 | SECTION .text:CODE:NOROOT:REORDER(1) 226 | TIM14_IRQHandler 227 | B TIM14_IRQHandler 228 | 229 | PUBWEAK TIM15_IRQHandler 230 | SECTION .text:CODE:NOROOT:REORDER(1) 231 | TIM15_IRQHandler 232 | B TIM15_IRQHandler 233 | 234 | PUBWEAK TIM16_IRQHandler 235 | SECTION .text:CODE:NOROOT:REORDER(1) 236 | TIM16_IRQHandler 237 | B TIM16_IRQHandler 238 | 239 | PUBWEAK TIM17_IRQHandler 240 | SECTION .text:CODE:NOROOT:REORDER(1) 241 | TIM17_IRQHandler 242 | B TIM17_IRQHandler 243 | 244 | PUBWEAK I2C1_IRQHandler 245 | SECTION .text:CODE:NOROOT:REORDER(1) 246 | I2C1_IRQHandler 247 | B I2C1_IRQHandler 248 | 249 | PUBWEAK I2C2_IRQHandler 250 | SECTION .text:CODE:NOROOT:REORDER(1) 251 | I2C2_IRQHandler 252 | B I2C2_IRQHandler 253 | 254 | PUBWEAK SPI1_IRQHandler 255 | SECTION .text:CODE:NOROOT:REORDER(1) 256 | SPI1_IRQHandler 257 | B SPI1_IRQHandler 258 | 259 | PUBWEAK SPI2_IRQHandler 260 | SECTION .text:CODE:NOROOT:REORDER(1) 261 | SPI2_IRQHandler 262 | B SPI2_IRQHandler 263 | 264 | PUBWEAK USART1_IRQHandler 265 | SECTION .text:CODE:NOROOT:REORDER(1) 266 | USART1_IRQHandler 267 | B USART1_IRQHandler 268 | 269 | PUBWEAK USART2_IRQHandler 270 | SECTION .text:CODE:NOROOT:REORDER(1) 271 | USART2_IRQHandler 272 | B USART2_IRQHandler 273 | 274 | END 275 | ;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** 276 | -------------------------------------------------------------------------------- /Drivers/CMSIS/Include/cmsis_version.h: -------------------------------------------------------------------------------- 1 | /**************************************************************************//** 2 | * @file cmsis_version.h 3 | * @brief CMSIS Core(M) Version definitions 4 | * @version V5.0.3 5 | * @date 24. June 2019 6 | ******************************************************************************/ 7 | /* 8 | * Copyright (c) 2009-2019 ARM Limited. All rights reserved. 9 | * 10 | * SPDX-License-Identifier: Apache-2.0 11 | * 12 | * Licensed under the Apache License, Version 2.0 (the License); you may 13 | * not use this file except in compliance with the License. 14 | * You may obtain a copy of the License at 15 | * 16 | * www.apache.org/licenses/LICENSE-2.0 17 | * 18 | * Unless required by applicable law or agreed to in writing, software 19 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT 20 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21 | * See the License for the specific language governing permissions and 22 | * limitations under the License. 23 | */ 24 | 25 | #if defined ( __ICCARM__ ) 26 | #pragma system_include /* treat file as system include file for MISRA check */ 27 | #elif defined (__clang__) 28 | #pragma clang system_header /* treat file as system include file */ 29 | #endif 30 | 31 | #ifndef __CMSIS_VERSION_H 32 | #define __CMSIS_VERSION_H 33 | 34 | /* CMSIS Version definitions */ 35 | #define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */ 36 | #define __CM_CMSIS_VERSION_SUB ( 3U) /*!< [15:0] CMSIS Core(M) sub version */ 37 | #define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \ 38 | __CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */ 39 | #endif 40 | -------------------------------------------------------------------------------- /Drivers/CMSIS/Include/tz_context.h: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * @file tz_context.h 3 | * @brief Context Management for Armv8-M TrustZone 4 | * @version V1.0.1 5 | * @date 10. January 2018 6 | ******************************************************************************/ 7 | /* 8 | * Copyright (c) 2017-2018 Arm Limited. All rights reserved. 9 | * 10 | * SPDX-License-Identifier: Apache-2.0 11 | * 12 | * Licensed under the Apache License, Version 2.0 (the License); you may 13 | * not use this file except in compliance with the License. 14 | * You may obtain a copy of the License at 15 | * 16 | * www.apache.org/licenses/LICENSE-2.0 17 | * 18 | * Unless required by applicable law or agreed to in writing, software 19 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT 20 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21 | * See the License for the specific language governing permissions and 22 | * limitations under the License. 23 | */ 24 | 25 | #if defined ( __ICCARM__ ) 26 | #pragma system_include /* treat file as system include file for MISRA check */ 27 | #elif defined (__clang__) 28 | #pragma clang system_header /* treat file as system include file */ 29 | #endif 30 | 31 | #ifndef TZ_CONTEXT_H 32 | #define TZ_CONTEXT_H 33 | 34 | #include 35 | 36 | #ifndef TZ_MODULEID_T 37 | #define TZ_MODULEID_T 38 | /// \details Data type that identifies secure software modules called by a process. 39 | typedef uint32_t TZ_ModuleId_t; 40 | #endif 41 | 42 | /// \details TZ Memory ID identifies an allocated memory slot. 43 | typedef uint32_t TZ_MemoryId_t; 44 | 45 | /// Initialize secure context memory system 46 | /// \return execution status (1: success, 0: error) 47 | uint32_t TZ_InitContextSystem_S (void); 48 | 49 | /// Allocate context memory for calling secure software modules in TrustZone 50 | /// \param[in] module identifies software modules called from non-secure mode 51 | /// \return value != 0 id TrustZone memory slot identifier 52 | /// \return value 0 no memory available or internal error 53 | TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module); 54 | 55 | /// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S 56 | /// \param[in] id TrustZone memory slot identifier 57 | /// \return execution status (1: success, 0: error) 58 | uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id); 59 | 60 | /// Load secure context (called on RTOS thread context switch) 61 | /// \param[in] id TrustZone memory slot identifier 62 | /// \return execution status (1: success, 0: error) 63 | uint32_t TZ_LoadContext_S (TZ_MemoryId_t id); 64 | 65 | /// Store secure context (called on RTOS thread context switch) 66 | /// \param[in] id TrustZone memory slot identifier 67 | /// \return execution status (1: success, 0: error) 68 | uint32_t TZ_StoreContext_S (TZ_MemoryId_t id); 69 | 70 | #endif // TZ_CONTEXT_H 71 | -------------------------------------------------------------------------------- /MDK-ARM/.vscode/keil-assistant.log: -------------------------------------------------------------------------------- 1 | [info] Log at : 2022/5/21|15:31:01|GMT+0800 2 | 3 | [info] Log at : 2022/5/21|15:38:49|GMT+0800 4 | 5 | [info] Log at : 2022/5/21|15:40:49|GMT+0800 6 | 7 | [info] Log at : 2022/5/21|15:40:53|GMT+0800 8 | 9 | [info] Log at : 2022/5/22|09:57:24|GMT+0800 10 | 11 | [info] Log at : 2022/5/22|22:58:35|GMT+0800 12 | 13 | [info] Log at : 2022/5/23|10:25:57|GMT+0800 14 | 15 | [info] Log at : 2022/5/25|17:18:09|GMT+0800 16 | 17 | [info] Log at : 2022/5/29|00:36:53|GMT+0800 18 | 19 | [info] Log at : 2022/5/29|10:10:07|GMT+0800 20 | 21 | [info] Log at : 2022/6/8|16:56:05|GMT+0800 22 | 23 | [info] Log at : 2022/6/8|17:08:30|GMT+0800 24 | 25 | [info] Log at : 2022/6/12|18:51:25|GMT+0800 26 | 27 | [info] Log at : 2022/6/12|18:51:32|GMT+0800 28 | 29 | [info] Log at : 2022/6/14|10:29:59|GMT+0800 30 | 31 | [info] Log at : 2022/6/21|08:33:41|GMT+0800 32 | 33 | [info] Log at : 2022/6/21|08:33:54|GMT+0800 34 | 35 | [info] Log at : 2022/6/21|15:43:55|GMT+0800 36 | 37 | [info] Log at : 2022/6/22|10:01:37|GMT+0800 38 | 39 | [info] Log at : 2022/6/24|18:12:11|GMT+0800 40 | 41 | [info] Log at : 2022/7/5|18:41:46|GMT+0800 42 | 43 | [info] Log at : 2022/7/6|09:49:33|GMT+0800 44 | 45 | [info] Log at : 2022/7/6|12:17:33|GMT+0800 46 | 47 | [info] Log at : 2022/7/7|11:23:11|GMT+0800 48 | 49 | [info] Log at : 2022/7/8|10:47:10|GMT+0800 50 | 51 | [info] Log at : 2022/7/9|09:50:24|GMT+0800 52 | 53 | [info] Log at : 2022/7/9|18:21:25|GMT+0800 54 | 55 | [info] Log at : 2022/7/10|11:42:38|GMT+0800 56 | 57 | [info] Log at : 2022/7/13|16:04:35|GMT+0800 58 | 59 | [info] Log at : 2022/7/14|10:06:53|GMT+0800 60 | 61 | [info] Log at : 2022/7/14|10:58:18|GMT+0800 62 | 63 | [info] Log at : 2022/7/14|10:58:23|GMT+0800 64 | 65 | [info] Log at : 2022/7/16|23:38:56|GMT+0800 66 | 67 | -------------------------------------------------------------------------------- /MDK-ARM/.vscode/settings.json: -------------------------------------------------------------------------------- 1 | { 2 | "files.associations": { 3 | "uart.h": "c", 4 | "sys.h": "c", 5 | "gpio.h": "c", 6 | "spi.h": "c", 7 | "per_conf.h": "c", 8 | "timer.h": "c", 9 | "lcd_init.h": "c", 10 | "lcd.h": "c", 11 | "lcd_font.h": "c", 12 | "adc.h": "c", 13 | "dma.h": "c", 14 | "stm32g0xx.h": "c", 15 | "stm32g030xx.h": "c", 16 | "osc.h": "c", 17 | "GUI.C": "cpp", 18 | "delay.h": "c" 19 | } 20 | } -------------------------------------------------------------------------------- /MDK-ARM/.vscode/uv4.log.lock: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Eltecz/STM32G0_OSC/e14b962a4d484ad32d7ee06078c8bbb59055c97d/MDK-ARM/.vscode/uv4.log.lock -------------------------------------------------------------------------------- /MDK-ARM/DebugConfig/light_STM32G030F6Px_1.0.0.dbgconf: -------------------------------------------------------------------------------- 1 | // File: STM32G0x0.dbgconf 2 | // Version: 1.0.0 3 | // Note: refer to STM32G0x0 reference manual (RM0454) 4 | 5 | // <<< Use Configuration Wizard in Context Menu >>> 6 | 7 | // Debug MCU configuration register (DBGMCU_CR) 8 | // Reserved bits must be kept at reset value 9 | // DBG_STANDBY Debug Standby Mode 10 | // DBG_STOP Debug Stop Mode 11 | // 12 | DbgMCU_CR = 0x00000006; 13 | 14 | // Debug MCU APB freeze register 1 (DBGMCU_APB_FZ1) 15 | // Reserved bits must be kept at reset value 16 | // DBG_I2C1_SMBUS_TIMEOUT I2C1 SMBUS timeout is frozen 17 | // DBG_IWDG_STOP Debug independent watchdog stopped when core is halted 18 | // DBG_WWDG_STOP Debug window watchdog stopped when core is halted 19 | // DBG_RTC_STOP Debug RTC stopped when core is halted 20 | // DBG_TIM7_STOP TIM7 counter stopped when core is halted 21 | // DBG_TIM6_STOP TIM6 counter stopped when core is halted 22 | // DBG_TIM3_STOP TIM3 counter stopped when core is halted 23 | // 24 | DbgMCU_APB_Fz1 = 0x00000000; 25 | 26 | // Debug MCU APB freeze register 2 (DBGMCU_APB_FZ2) 27 | // Reserved bits must be kept at reset value 28 | // DBG_TIM17_STOP TIM17 counter stopped when core is halted 29 | // DBG_TIM16_STOP TIM16 counter stopped when core is halted 30 | // DBG_TIM15_STOP TIM15 counter stopped when core is halted 31 | // DBG_TIM1_STOP TIM1 counter stopped when core is halted 32 | // 33 | DbgMCU_APB_Fz2 = 0x00000000; 34 | 35 | // <<< end of configuration section >>> 36 | -------------------------------------------------------------------------------- /MDK-ARM/EventRecorderStub.scvd: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | -------------------------------------------------------------------------------- /MDK-ARM/RTE/Device/STM32G030F6Px/startup_stm32g030xx.s: -------------------------------------------------------------------------------- 1 | ;****************************************************************************** 2 | ;* File Name : startup_stm32g030xx.s 3 | ;* Author : MCD Application Team 4 | ;* Description : STM32G030xx devices vector table for MDK-ARM toolchain. 5 | ;* This module performs: 6 | ;* - Set the initial SP 7 | ;* - Set the initial PC == Reset_Handler 8 | ;* - Set the vector table entries with the exceptions ISR address 9 | ;* - Branches to __main in the C library (which eventually 10 | ;* calls main()). 11 | ;* After Reset the CortexM0 processor is in Thread mode, 12 | ;* priority is Privileged, and the Stack is set to Main. 13 | ;* <<< Use Configuration Wizard in Context Menu >>> 14 | ;****************************************************************************** 15 | ;* @attention 16 | ;* 17 | ;* Copyright (c) 2019 STMicroelectronics. All rights reserved. 18 | ;* 19 | ;* This software component is licensed by ST under Apache License, Version 2.0, 20 | ;* the "License"; You may not use this file except in compliance with the 21 | ;* License. You may obtain a copy of the License at: 22 | ;* opensource.org/licenses/Apache-2.0 23 | ;* 24 | ;****************************************************************************** 25 | 26 | ; Amount of memory (in bytes) allocated for Stack 27 | ; Tailor this value to your application needs 28 | ; Stack Configuration 29 | ; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> 30 | ; 31 | 32 | Stack_Size EQU 0x00000400 33 | 34 | AREA STACK, NOINIT, READWRITE, ALIGN=3 35 | Stack_Mem SPACE Stack_Size 36 | __initial_sp 37 | 38 | 39 | ; Heap Configuration 40 | ; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> 41 | ; 42 | 43 | Heap_Size EQU 0x00000200 44 | 45 | AREA HEAP, NOINIT, READWRITE, ALIGN=3 46 | __heap_base 47 | Heap_Mem SPACE Heap_Size 48 | __heap_limit 49 | 50 | PRESERVE8 51 | THUMB 52 | 53 | 54 | ; Vector Table Mapped to Address 0 at Reset 55 | AREA RESET, DATA, READONLY 56 | EXPORT __Vectors 57 | EXPORT __Vectors_End 58 | EXPORT __Vectors_Size 59 | 60 | __Vectors DCD __initial_sp ; Top of Stack 61 | DCD Reset_Handler ; Reset Handler 62 | DCD NMI_Handler ; NMI Handler 63 | DCD HardFault_Handler ; Hard Fault Handler 64 | DCD 0 ; Reserved 65 | DCD 0 ; Reserved 66 | DCD 0 ; Reserved 67 | DCD 0 ; Reserved 68 | DCD 0 ; Reserved 69 | DCD 0 ; Reserved 70 | DCD 0 ; Reserved 71 | DCD SVC_Handler ; SVCall Handler 72 | DCD 0 ; Reserved 73 | DCD 0 ; Reserved 74 | DCD PendSV_Handler ; PendSV Handler 75 | DCD SysTick_Handler ; SysTick Handler 76 | 77 | ; External Interrupts 78 | DCD WWDG_IRQHandler ; Window Watchdog 79 | DCD 0 ; Reserved 80 | DCD RTC_TAMP_IRQHandler ; RTC through EXTI Line 81 | DCD FLASH_IRQHandler ; FLASH 82 | DCD RCC_IRQHandler ; RCC 83 | DCD EXTI0_1_IRQHandler ; EXTI Line 0 and 1 84 | DCD EXTI2_3_IRQHandler ; EXTI Line 2 and 3 85 | DCD EXTI4_15_IRQHandler ; EXTI Line 4 to 15 86 | DCD 0 ; Reserved 87 | DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 88 | DCD DMA1_Channel2_3_IRQHandler ; DMA1 Channel 2 and Channel 3 89 | DCD DMA1_Ch4_5_DMAMUX1_OVR_IRQHandler ; DMA1 Channel 4 to Channel 5, DMAMUX1 overrun 90 | DCD ADC1_IRQHandler ; ADC1 91 | DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation 92 | DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare 93 | DCD 0 ; Reserved 94 | DCD TIM3_IRQHandler ; TIM3 95 | DCD 0 ; Reserved 96 | DCD 0 ; Reserved 97 | DCD TIM14_IRQHandler ; TIM14 98 | DCD 0 ; Reserved 99 | DCD TIM16_IRQHandler ; TIM16 100 | DCD TIM17_IRQHandler ; TIM17 101 | DCD I2C1_IRQHandler ; I2C1 102 | DCD I2C2_IRQHandler ; I2C2 103 | DCD SPI1_IRQHandler ; SPI1 104 | DCD SPI2_IRQHandler ; SPI2 105 | DCD USART1_IRQHandler ; USART1 106 | DCD USART2_IRQHandler ; USART2 107 | DCD 0 ; Reserved 108 | DCD 0 ; Reserved 109 | DCD 0 ; Reserved 110 | 111 | __Vectors_End 112 | 113 | __Vectors_Size EQU __Vectors_End - __Vectors 114 | 115 | AREA |.text|, CODE, READONLY 116 | 117 | ; Reset handler routine 118 | Reset_Handler PROC 119 | EXPORT Reset_Handler [WEAK] 120 | IMPORT __main 121 | IMPORT SystemInit 122 | LDR R0, =SystemInit 123 | BLX R0 124 | LDR R0, =__main 125 | BX R0 126 | ENDP 127 | 128 | ; Dummy Exception Handlers (infinite loops which can be modified) 129 | 130 | NMI_Handler PROC 131 | EXPORT NMI_Handler [WEAK] 132 | B . 133 | ENDP 134 | HardFault_Handler\ 135 | PROC 136 | EXPORT HardFault_Handler [WEAK] 137 | B . 138 | ENDP 139 | SVC_Handler PROC 140 | EXPORT SVC_Handler [WEAK] 141 | B . 142 | ENDP 143 | PendSV_Handler PROC 144 | EXPORT PendSV_Handler [WEAK] 145 | B . 146 | ENDP 147 | SysTick_Handler PROC 148 | EXPORT SysTick_Handler [WEAK] 149 | B . 150 | ENDP 151 | 152 | Default_Handler PROC 153 | 154 | EXPORT WWDG_IRQHandler [WEAK] 155 | EXPORT RTC_TAMP_IRQHandler [WEAK] 156 | EXPORT FLASH_IRQHandler [WEAK] 157 | EXPORT RCC_IRQHandler [WEAK] 158 | EXPORT EXTI0_1_IRQHandler [WEAK] 159 | EXPORT EXTI2_3_IRQHandler [WEAK] 160 | EXPORT EXTI4_15_IRQHandler [WEAK] 161 | EXPORT DMA1_Channel1_IRQHandler [WEAK] 162 | EXPORT DMA1_Channel2_3_IRQHandler [WEAK] 163 | EXPORT DMA1_Ch4_5_DMAMUX1_OVR_IRQHandler [WEAK] 164 | EXPORT ADC1_IRQHandler [WEAK] 165 | EXPORT TIM1_BRK_UP_TRG_COM_IRQHandler [WEAK] 166 | EXPORT TIM1_CC_IRQHandler [WEAK] 167 | EXPORT TIM3_IRQHandler [WEAK] 168 | EXPORT TIM14_IRQHandler [WEAK] 169 | EXPORT TIM16_IRQHandler [WEAK] 170 | EXPORT TIM17_IRQHandler [WEAK] 171 | EXPORT I2C1_IRQHandler [WEAK] 172 | EXPORT I2C2_IRQHandler [WEAK] 173 | EXPORT SPI1_IRQHandler [WEAK] 174 | EXPORT SPI2_IRQHandler [WEAK] 175 | EXPORT USART1_IRQHandler [WEAK] 176 | EXPORT USART2_IRQHandler [WEAK] 177 | 178 | 179 | WWDG_IRQHandler 180 | RTC_TAMP_IRQHandler 181 | FLASH_IRQHandler 182 | RCC_IRQHandler 183 | EXTI0_1_IRQHandler 184 | EXTI2_3_IRQHandler 185 | EXTI4_15_IRQHandler 186 | DMA1_Channel1_IRQHandler 187 | DMA1_Channel2_3_IRQHandler 188 | DMA1_Ch4_5_DMAMUX1_OVR_IRQHandler 189 | ADC1_IRQHandler 190 | TIM1_BRK_UP_TRG_COM_IRQHandler 191 | TIM1_CC_IRQHandler 192 | TIM3_IRQHandler 193 | TIM14_IRQHandler 194 | TIM16_IRQHandler 195 | TIM17_IRQHandler 196 | I2C1_IRQHandler 197 | I2C2_IRQHandler 198 | SPI1_IRQHandler 199 | SPI2_IRQHandler 200 | USART1_IRQHandler 201 | USART2_IRQHandler 202 | 203 | B . 204 | 205 | ENDP 206 | 207 | ALIGN 208 | 209 | ;******************************************************************************* 210 | ; User Stack and Heap initialization 211 | ;******************************************************************************* 212 | IF :DEF:__MICROLIB 213 | 214 | EXPORT __initial_sp 215 | EXPORT __heap_base 216 | EXPORT __heap_limit 217 | 218 | ELSE 219 | 220 | IMPORT __use_two_region_memory 221 | EXPORT __user_initial_stackheap 222 | 223 | __user_initial_stackheap 224 | 225 | LDR R0, = Heap_Mem 226 | LDR R1, =(Stack_Mem + Stack_Size) 227 | LDR R2, = (Heap_Mem + Heap_Size) 228 | LDR R3, = Stack_Mem 229 | BX LR 230 | 231 | ALIGN 232 | 233 | ENDIF 234 | 235 | END 236 | 237 | ;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** 238 | -------------------------------------------------------------------------------- /MDK-ARM/RTE/_light/RTE_Components.h: -------------------------------------------------------------------------------- 1 | 2 | /* 3 | * Auto generated Run-Time-Environment Configuration File 4 | * *** Do not modify ! *** 5 | * 6 | * Project: 'light' 7 | * Target: 'light' 8 | */ 9 | 10 | #ifndef RTE_COMPONENTS_H 11 | #define RTE_COMPONENTS_H 12 | 13 | 14 | /* 15 | * Define the Device Header File: 16 | */ 17 | #define CMSIS_device_header "stm32g0xx.h" 18 | 19 | 20 | 21 | #endif /* RTE_COMPONENTS_H */ 22 | -------------------------------------------------------------------------------- /MDK-ARM/light/adc.d: -------------------------------------------------------------------------------- 1 | light/adc.o: ..\user\adc.c ..\user\adc.h ..\user\per_conf.h ..\user\sys.h \ 2 | ..\Drivers\CMSIS\Device\ST\STM32G0xx\Include\stm32g0xx.h \ 3 | ..\Drivers\CMSIS\Device\ST\STM32G0xx\Include\stm32g030xx.h \ 4 | ..\Drivers\CMSIS\Include\core_cm0plus.h \ 5 | d:\APP\Keil_v5\ARM\ARMCLANG\Bin\..\include\stdint.h \ 6 | ..\Drivers\CMSIS\Include\cmsis_version.h \ 7 | ..\Drivers\CMSIS\Include\cmsis_compiler.h \ 8 | ..\Drivers\CMSIS\Include\cmsis_armclang.h \ 9 | d:\APP\Keil_v5\ARM\ARMCLANG\Bin\..\include\arm_compat.h \ 10 | d:\APP\Keil_v5\ARM\ARMCLANG\Bin\..\include\arm_acle.h \ 11 | ..\Drivers\CMSIS\Include\mpu_armv7.h \ 12 | ..\Drivers\CMSIS\Device\ST\STM32G0xx\Include\system_stm32g0xx.h \ 13 | ..\user\gpio.h ..\user\delay.h ..\user\sys.h \ 14 | d:\APP\Keil_v5\ARM\ARMCLANG\Bin\..\include\string.h \ 15 | d:\APP\Keil_v5\ARM\ARMCLANG\Bin\..\include\stdio.h ..\user\uart.h \ 16 | ..\user\osc.h ..\user\timer.h ..\user\spi.h ..\user\lcd.h \ 17 | ..\user\lcd_init.h ..\user\dma.h 18 | -------------------------------------------------------------------------------- /MDK-ARM/light/adc.o: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Eltecz/STM32G0_OSC/e14b962a4d484ad32d7ee06078c8bbb59055c97d/MDK-ARM/light/adc.o -------------------------------------------------------------------------------- /MDK-ARM/light/delay.d: -------------------------------------------------------------------------------- 1 | light/delay.o: ..\user\delay.c ..\user\delay.h ..\user\sys.h \ 2 | ..\Drivers\CMSIS\Device\ST\STM32G0xx\Include\stm32g0xx.h \ 3 | ..\Drivers\CMSIS\Device\ST\STM32G0xx\Include\stm32g030xx.h \ 4 | ..\Drivers\CMSIS\Include\core_cm0plus.h \ 5 | d:\APP\Keil_v5\ARM\ARMCLANG\Bin\..\include\stdint.h \ 6 | ..\Drivers\CMSIS\Include\cmsis_version.h \ 7 | ..\Drivers\CMSIS\Include\cmsis_compiler.h \ 8 | ..\Drivers\CMSIS\Include\cmsis_armclang.h \ 9 | d:\APP\Keil_v5\ARM\ARMCLANG\Bin\..\include\arm_compat.h \ 10 | d:\APP\Keil_v5\ARM\ARMCLANG\Bin\..\include\arm_acle.h \ 11 | ..\Drivers\CMSIS\Include\mpu_armv7.h \ 12 | ..\Drivers\CMSIS\Device\ST\STM32G0xx\Include\system_stm32g0xx.h \ 13 | ..\user\sys.h 14 | -------------------------------------------------------------------------------- /MDK-ARM/light/delay.o: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Eltecz/STM32G0_OSC/e14b962a4d484ad32d7ee06078c8bbb59055c97d/MDK-ARM/light/delay.o -------------------------------------------------------------------------------- /MDK-ARM/light/dma.d: -------------------------------------------------------------------------------- 1 | light/dma.o: ..\user\dma.c ..\user\dma.h ..\user\per_conf.h ..\user\sys.h \ 2 | ..\Drivers\CMSIS\Device\ST\STM32G0xx\Include\stm32g0xx.h \ 3 | ..\Drivers\CMSIS\Device\ST\STM32G0xx\Include\stm32g030xx.h \ 4 | ..\Drivers\CMSIS\Include\core_cm0plus.h \ 5 | d:\APP\Keil_v5\ARM\ARMCLANG\Bin\..\include\stdint.h \ 6 | ..\Drivers\CMSIS\Include\cmsis_version.h \ 7 | ..\Drivers\CMSIS\Include\cmsis_compiler.h \ 8 | ..\Drivers\CMSIS\Include\cmsis_armclang.h \ 9 | d:\APP\Keil_v5\ARM\ARMCLANG\Bin\..\include\arm_compat.h \ 10 | d:\APP\Keil_v5\ARM\ARMCLANG\Bin\..\include\arm_acle.h \ 11 | ..\Drivers\CMSIS\Include\mpu_armv7.h \ 12 | ..\Drivers\CMSIS\Device\ST\STM32G0xx\Include\system_stm32g0xx.h \ 13 | ..\user\gpio.h ..\user\delay.h ..\user\sys.h \ 14 | d:\APP\Keil_v5\ARM\ARMCLANG\Bin\..\include\string.h \ 15 | d:\APP\Keil_v5\ARM\ARMCLANG\Bin\..\include\stdio.h ..\user\uart.h \ 16 | ..\user\osc.h ..\user\adc.h ..\user\timer.h ..\user\spi.h \ 17 | ..\user\lcd.h ..\user\lcd_init.h 18 | -------------------------------------------------------------------------------- /MDK-ARM/light/dma.o: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Eltecz/STM32G0_OSC/e14b962a4d484ad32d7ee06078c8bbb59055c97d/MDK-ARM/light/dma.o -------------------------------------------------------------------------------- /MDK-ARM/light/gpio.d: -------------------------------------------------------------------------------- 1 | light/gpio.o: ..\user\gpio.c ..\user\gpio.h ..\user\per_conf.h \ 2 | ..\user\sys.h ..\Drivers\CMSIS\Device\ST\STM32G0xx\Include\stm32g0xx.h \ 3 | ..\Drivers\CMSIS\Device\ST\STM32G0xx\Include\stm32g030xx.h \ 4 | ..\Drivers\CMSIS\Include\core_cm0plus.h \ 5 | d:\APP\Keil_v5\ARM\ARMCLANG\Bin\..\include\stdint.h \ 6 | ..\Drivers\CMSIS\Include\cmsis_version.h \ 7 | ..\Drivers\CMSIS\Include\cmsis_compiler.h \ 8 | ..\Drivers\CMSIS\Include\cmsis_armclang.h \ 9 | d:\APP\Keil_v5\ARM\ARMCLANG\Bin\..\include\arm_compat.h \ 10 | d:\APP\Keil_v5\ARM\ARMCLANG\Bin\..\include\arm_acle.h \ 11 | ..\Drivers\CMSIS\Include\mpu_armv7.h \ 12 | ..\Drivers\CMSIS\Device\ST\STM32G0xx\Include\system_stm32g0xx.h \ 13 | ..\user\delay.h ..\user\sys.h \ 14 | d:\APP\Keil_v5\ARM\ARMCLANG\Bin\..\include\string.h \ 15 | d:\APP\Keil_v5\ARM\ARMCLANG\Bin\..\include\stdio.h ..\user\uart.h \ 16 | ..\user\osc.h ..\user\adc.h ..\user\timer.h ..\user\spi.h \ 17 | ..\user\lcd.h ..\user\lcd_init.h ..\user\dma.h 18 | -------------------------------------------------------------------------------- /MDK-ARM/light/gpio.o: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Eltecz/STM32G0_OSC/e14b962a4d484ad32d7ee06078c8bbb59055c97d/MDK-ARM/light/gpio.o -------------------------------------------------------------------------------- /MDK-ARM/light/lcd.d: -------------------------------------------------------------------------------- 1 | light/lcd.o: ..\user\lcd.c ..\user\lcd.h ..\user\per_conf.h ..\user\sys.h \ 2 | ..\Drivers\CMSIS\Device\ST\STM32G0xx\Include\stm32g0xx.h \ 3 | ..\Drivers\CMSIS\Device\ST\STM32G0xx\Include\stm32g030xx.h \ 4 | ..\Drivers\CMSIS\Include\core_cm0plus.h \ 5 | d:\APP\Keil_v5\ARM\ARMCLANG\Bin\..\include\stdint.h \ 6 | ..\Drivers\CMSIS\Include\cmsis_version.h \ 7 | ..\Drivers\CMSIS\Include\cmsis_compiler.h \ 8 | ..\Drivers\CMSIS\Include\cmsis_armclang.h \ 9 | d:\APP\Keil_v5\ARM\ARMCLANG\Bin\..\include\arm_compat.h \ 10 | d:\APP\Keil_v5\ARM\ARMCLANG\Bin\..\include\arm_acle.h \ 11 | ..\Drivers\CMSIS\Include\mpu_armv7.h \ 12 | ..\Drivers\CMSIS\Device\ST\STM32G0xx\Include\system_stm32g0xx.h \ 13 | ..\user\gpio.h ..\user\delay.h ..\user\sys.h \ 14 | d:\APP\Keil_v5\ARM\ARMCLANG\Bin\..\include\string.h \ 15 | d:\APP\Keil_v5\ARM\ARMCLANG\Bin\..\include\stdio.h ..\user\uart.h \ 16 | ..\user\osc.h ..\user\adc.h ..\user\timer.h ..\user\spi.h \ 17 | ..\user\lcd_init.h ..\user\dma.h ..\user\lcd_font.h 18 | -------------------------------------------------------------------------------- /MDK-ARM/light/lcd.o: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Eltecz/STM32G0_OSC/e14b962a4d484ad32d7ee06078c8bbb59055c97d/MDK-ARM/light/lcd.o -------------------------------------------------------------------------------- /MDK-ARM/light/lcd_init.d: -------------------------------------------------------------------------------- 1 | light/lcd_init.o: ..\user\lcd_init.c ..\user\lcd_init.h \ 2 | ..\user\per_conf.h ..\user\sys.h \ 3 | ..\Drivers\CMSIS\Device\ST\STM32G0xx\Include\stm32g0xx.h \ 4 | ..\Drivers\CMSIS\Device\ST\STM32G0xx\Include\stm32g030xx.h \ 5 | ..\Drivers\CMSIS\Include\core_cm0plus.h \ 6 | d:\APP\Keil_v5\ARM\ARMCLANG\Bin\..\include\stdint.h \ 7 | ..\Drivers\CMSIS\Include\cmsis_version.h \ 8 | ..\Drivers\CMSIS\Include\cmsis_compiler.h \ 9 | ..\Drivers\CMSIS\Include\cmsis_armclang.h \ 10 | d:\APP\Keil_v5\ARM\ARMCLANG\Bin\..\include\arm_compat.h \ 11 | d:\APP\Keil_v5\ARM\ARMCLANG\Bin\..\include\arm_acle.h \ 12 | ..\Drivers\CMSIS\Include\mpu_armv7.h \ 13 | ..\Drivers\CMSIS\Device\ST\STM32G0xx\Include\system_stm32g0xx.h \ 14 | ..\user\gpio.h ..\user\delay.h ..\user\sys.h \ 15 | d:\APP\Keil_v5\ARM\ARMCLANG\Bin\..\include\string.h \ 16 | d:\APP\Keil_v5\ARM\ARMCLANG\Bin\..\include\stdio.h ..\user\uart.h \ 17 | ..\user\osc.h ..\user\adc.h ..\user\timer.h ..\user\spi.h \ 18 | ..\user\lcd.h ..\user\dma.h 19 | -------------------------------------------------------------------------------- /MDK-ARM/light/lcd_init.o: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Eltecz/STM32G0_OSC/e14b962a4d484ad32d7ee06078c8bbb59055c97d/MDK-ARM/light/lcd_init.o -------------------------------------------------------------------------------- /MDK-ARM/light/light.axf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Eltecz/STM32G0_OSC/e14b962a4d484ad32d7ee06078c8bbb59055c97d/MDK-ARM/light/light.axf -------------------------------------------------------------------------------- /MDK-ARM/light/light.build_log.htm: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Eltecz/STM32G0_OSC/e14b962a4d484ad32d7ee06078c8bbb59055c97d/MDK-ARM/light/light.build_log.htm -------------------------------------------------------------------------------- /MDK-ARM/light/light.lnp: -------------------------------------------------------------------------------- 1 | --cpu Cortex-M0+ 2 | "light\startup_stm32g030xx.o" 3 | "light\sys.o" 4 | "light\delay.o" 5 | "light\uart.o" 6 | "light\adc.o" 7 | "light\timer.o" 8 | "light\gpio.o" 9 | "light\spi.o" 10 | "light\lcd.o" 11 | "light\lcd_init.o" 12 | "light\dma.o" 13 | "light\osc.o" 14 | "light\main.o" 15 | "light\system_stm32g0xx.o" 16 | --library_type=microlib --strict --scatter "light\light.sct" 17 | --summary_stderr --info summarysizes --map --load_addr_map_info --xref --callgraph --symbols 18 | --info sizes --info totals --info unused --info veneers 19 | --list "light.map" -o light\light.axf -------------------------------------------------------------------------------- /MDK-ARM/light/light.sct: -------------------------------------------------------------------------------- 1 | ; ************************************************************* 2 | ; *** Scatter-Loading Description File generated by uVision *** 3 | ; ************************************************************* 4 | 5 | LR_IROM1 0x08000000 0x00008000 { ; load region size_region 6 | ER_IROM1 0x08000000 0x00008000 { ; load address = execution address 7 | *.o (RESET, +First) 8 | *(InRoot$$Sections) 9 | .ANY (+RO) 10 | .ANY (+XO) 11 | } 12 | RW_IRAM1 0x20000000 0x00002000 { ; RW data 13 | .ANY (+RW +ZI) 14 | } 15 | } 16 | 17 | -------------------------------------------------------------------------------- /MDK-ARM/light/main.d: -------------------------------------------------------------------------------- 1 | light/main.o: main.c ..\user\sys.h \ 2 | ..\Drivers\CMSIS\Device\ST\STM32G0xx\Include\stm32g0xx.h \ 3 | ..\Drivers\CMSIS\Device\ST\STM32G0xx\Include\stm32g030xx.h \ 4 | ..\Drivers\CMSIS\Include\core_cm0plus.h \ 5 | d:\APP\Keil_v5\ARM\ARMCLANG\Bin\..\include\stdint.h \ 6 | ..\Drivers\CMSIS\Include\cmsis_version.h \ 7 | ..\Drivers\CMSIS\Include\cmsis_compiler.h \ 8 | ..\Drivers\CMSIS\Include\cmsis_armclang.h \ 9 | d:\APP\Keil_v5\ARM\ARMCLANG\Bin\..\include\arm_compat.h \ 10 | d:\APP\Keil_v5\ARM\ARMCLANG\Bin\..\include\arm_acle.h \ 11 | ..\Drivers\CMSIS\Include\mpu_armv7.h \ 12 | ..\Drivers\CMSIS\Device\ST\STM32G0xx\Include\system_stm32g0xx.h \ 13 | ..\user\per_conf.h ..\user\sys.h ..\user\gpio.h ..\user\per_conf.h \ 14 | ..\user\delay.h d:\APP\Keil_v5\ARM\ARMCLANG\Bin\..\include\string.h \ 15 | d:\APP\Keil_v5\ARM\ARMCLANG\Bin\..\include\stdio.h ..\user\uart.h \ 16 | ..\user\osc.h ..\user\adc.h ..\user\timer.h ..\user\spi.h \ 17 | ..\user\lcd.h ..\user\lcd_init.h ..\user\dma.h 18 | -------------------------------------------------------------------------------- /MDK-ARM/light/main.o: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Eltecz/STM32G0_OSC/e14b962a4d484ad32d7ee06078c8bbb59055c97d/MDK-ARM/light/main.o -------------------------------------------------------------------------------- /MDK-ARM/light/osc.d: -------------------------------------------------------------------------------- 1 | light/osc.o: ..\user\osc.c ..\user\osc.h ..\user\per_conf.h ..\user\sys.h \ 2 | ..\Drivers\CMSIS\Device\ST\STM32G0xx\Include\stm32g0xx.h \ 3 | ..\Drivers\CMSIS\Device\ST\STM32G0xx\Include\stm32g030xx.h \ 4 | ..\Drivers\CMSIS\Include\core_cm0plus.h \ 5 | d:\APP\Keil_v5\ARM\ARMCLANG\Bin\..\include\stdint.h \ 6 | ..\Drivers\CMSIS\Include\cmsis_version.h \ 7 | ..\Drivers\CMSIS\Include\cmsis_compiler.h \ 8 | ..\Drivers\CMSIS\Include\cmsis_armclang.h \ 9 | d:\APP\Keil_v5\ARM\ARMCLANG\Bin\..\include\arm_compat.h \ 10 | d:\APP\Keil_v5\ARM\ARMCLANG\Bin\..\include\arm_acle.h \ 11 | ..\Drivers\CMSIS\Include\mpu_armv7.h \ 12 | ..\Drivers\CMSIS\Device\ST\STM32G0xx\Include\system_stm32g0xx.h \ 13 | ..\user\gpio.h ..\user\delay.h ..\user\sys.h \ 14 | d:\APP\Keil_v5\ARM\ARMCLANG\Bin\..\include\string.h \ 15 | d:\APP\Keil_v5\ARM\ARMCLANG\Bin\..\include\stdio.h ..\user\uart.h \ 16 | ..\user\adc.h ..\user\timer.h ..\user\spi.h ..\user\lcd.h \ 17 | ..\user\lcd_init.h ..\user\dma.h 18 | -------------------------------------------------------------------------------- /MDK-ARM/light/osc.o: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Eltecz/STM32G0_OSC/e14b962a4d484ad32d7ee06078c8bbb59055c97d/MDK-ARM/light/osc.o -------------------------------------------------------------------------------- /MDK-ARM/light/spi.d: -------------------------------------------------------------------------------- 1 | light/spi.o: ..\user\spi.c ..\user\spi.h ..\user\per_conf.h ..\user\sys.h \ 2 | ..\Drivers\CMSIS\Device\ST\STM32G0xx\Include\stm32g0xx.h \ 3 | ..\Drivers\CMSIS\Device\ST\STM32G0xx\Include\stm32g030xx.h \ 4 | ..\Drivers\CMSIS\Include\core_cm0plus.h \ 5 | d:\APP\Keil_v5\ARM\ARMCLANG\Bin\..\include\stdint.h \ 6 | ..\Drivers\CMSIS\Include\cmsis_version.h \ 7 | ..\Drivers\CMSIS\Include\cmsis_compiler.h \ 8 | ..\Drivers\CMSIS\Include\cmsis_armclang.h \ 9 | d:\APP\Keil_v5\ARM\ARMCLANG\Bin\..\include\arm_compat.h \ 10 | d:\APP\Keil_v5\ARM\ARMCLANG\Bin\..\include\arm_acle.h \ 11 | ..\Drivers\CMSIS\Include\mpu_armv7.h \ 12 | ..\Drivers\CMSIS\Device\ST\STM32G0xx\Include\system_stm32g0xx.h \ 13 | ..\user\gpio.h ..\user\delay.h ..\user\sys.h \ 14 | d:\APP\Keil_v5\ARM\ARMCLANG\Bin\..\include\string.h \ 15 | d:\APP\Keil_v5\ARM\ARMCLANG\Bin\..\include\stdio.h ..\user\uart.h \ 16 | ..\user\osc.h ..\user\adc.h ..\user\timer.h ..\user\lcd.h \ 17 | ..\user\lcd_init.h ..\user\dma.h 18 | -------------------------------------------------------------------------------- /MDK-ARM/light/spi.o: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Eltecz/STM32G0_OSC/e14b962a4d484ad32d7ee06078c8bbb59055c97d/MDK-ARM/light/spi.o -------------------------------------------------------------------------------- /MDK-ARM/light/startup_stm32g030xx.d: -------------------------------------------------------------------------------- 1 | light\startup_stm32g030xx.o: startup_stm32g030xx.s 2 | -------------------------------------------------------------------------------- /MDK-ARM/light/startup_stm32g030xx.o: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Eltecz/STM32G0_OSC/e14b962a4d484ad32d7ee06078c8bbb59055c97d/MDK-ARM/light/startup_stm32g030xx.o -------------------------------------------------------------------------------- /MDK-ARM/light/sys.d: -------------------------------------------------------------------------------- 1 | light/sys.o: ..\user\sys.c ..\user\sys.h \ 2 | ..\Drivers\CMSIS\Device\ST\STM32G0xx\Include\stm32g0xx.h \ 3 | ..\Drivers\CMSIS\Device\ST\STM32G0xx\Include\stm32g030xx.h \ 4 | ..\Drivers\CMSIS\Include\core_cm0plus.h \ 5 | d:\APP\Keil_v5\ARM\ARMCLANG\Bin\..\include\stdint.h \ 6 | ..\Drivers\CMSIS\Include\cmsis_version.h \ 7 | ..\Drivers\CMSIS\Include\cmsis_compiler.h \ 8 | ..\Drivers\CMSIS\Include\cmsis_armclang.h \ 9 | d:\APP\Keil_v5\ARM\ARMCLANG\Bin\..\include\arm_compat.h \ 10 | d:\APP\Keil_v5\ARM\ARMCLANG\Bin\..\include\arm_acle.h \ 11 | ..\Drivers\CMSIS\Include\mpu_armv7.h \ 12 | ..\Drivers\CMSIS\Device\ST\STM32G0xx\Include\system_stm32g0xx.h 13 | -------------------------------------------------------------------------------- /MDK-ARM/light/sys.o: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Eltecz/STM32G0_OSC/e14b962a4d484ad32d7ee06078c8bbb59055c97d/MDK-ARM/light/sys.o -------------------------------------------------------------------------------- /MDK-ARM/light/system_stm32g0xx.d: -------------------------------------------------------------------------------- 1 | light/system_stm32g0xx.o: ..\Core\Src\system_stm32g0xx.c \ 2 | ..\Drivers\CMSIS\Device\ST\STM32G0xx\Include\stm32g0xx.h \ 3 | ..\Drivers\CMSIS\Device\ST\STM32G0xx\Include\stm32g030xx.h \ 4 | ..\Drivers\CMSIS\Include\core_cm0plus.h \ 5 | d:\APP\Keil_v5\ARM\ARMCLANG\Bin\..\include\stdint.h \ 6 | ..\Drivers\CMSIS\Include\cmsis_version.h \ 7 | ..\Drivers\CMSIS\Include\cmsis_compiler.h \ 8 | ..\Drivers\CMSIS\Include\cmsis_armclang.h \ 9 | d:\APP\Keil_v5\ARM\ARMCLANG\Bin\..\include\arm_compat.h \ 10 | d:\APP\Keil_v5\ARM\ARMCLANG\Bin\..\include\arm_acle.h \ 11 | ..\Drivers\CMSIS\Include\mpu_armv7.h \ 12 | ..\Drivers\CMSIS\Device\ST\STM32G0xx\Include\system_stm32g0xx.h 13 | -------------------------------------------------------------------------------- /MDK-ARM/light/system_stm32g0xx.o: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Eltecz/STM32G0_OSC/e14b962a4d484ad32d7ee06078c8bbb59055c97d/MDK-ARM/light/system_stm32g0xx.o -------------------------------------------------------------------------------- /MDK-ARM/light/timer.d: -------------------------------------------------------------------------------- 1 | light/timer.o: ..\user\timer.c ..\user\timer.h ..\user\per_conf.h \ 2 | ..\user\sys.h ..\Drivers\CMSIS\Device\ST\STM32G0xx\Include\stm32g0xx.h \ 3 | ..\Drivers\CMSIS\Device\ST\STM32G0xx\Include\stm32g030xx.h \ 4 | ..\Drivers\CMSIS\Include\core_cm0plus.h \ 5 | d:\APP\Keil_v5\ARM\ARMCLANG\Bin\..\include\stdint.h \ 6 | ..\Drivers\CMSIS\Include\cmsis_version.h \ 7 | ..\Drivers\CMSIS\Include\cmsis_compiler.h \ 8 | ..\Drivers\CMSIS\Include\cmsis_armclang.h \ 9 | d:\APP\Keil_v5\ARM\ARMCLANG\Bin\..\include\arm_compat.h \ 10 | d:\APP\Keil_v5\ARM\ARMCLANG\Bin\..\include\arm_acle.h \ 11 | ..\Drivers\CMSIS\Include\mpu_armv7.h \ 12 | ..\Drivers\CMSIS\Device\ST\STM32G0xx\Include\system_stm32g0xx.h \ 13 | ..\user\gpio.h ..\user\delay.h ..\user\sys.h \ 14 | d:\APP\Keil_v5\ARM\ARMCLANG\Bin\..\include\string.h \ 15 | d:\APP\Keil_v5\ARM\ARMCLANG\Bin\..\include\stdio.h ..\user\uart.h \ 16 | ..\user\osc.h ..\user\adc.h ..\user\spi.h ..\user\lcd.h \ 17 | ..\user\lcd_init.h ..\user\dma.h 18 | -------------------------------------------------------------------------------- /MDK-ARM/light/timer.o: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Eltecz/STM32G0_OSC/e14b962a4d484ad32d7ee06078c8bbb59055c97d/MDK-ARM/light/timer.o -------------------------------------------------------------------------------- /MDK-ARM/light/uart.d: -------------------------------------------------------------------------------- 1 | light/uart.o: ..\user\uart.c ..\user\uart.h ..\user\per_conf.h \ 2 | ..\user\sys.h ..\Drivers\CMSIS\Device\ST\STM32G0xx\Include\stm32g0xx.h \ 3 | ..\Drivers\CMSIS\Device\ST\STM32G0xx\Include\stm32g030xx.h \ 4 | ..\Drivers\CMSIS\Include\core_cm0plus.h \ 5 | d:\APP\Keil_v5\ARM\ARMCLANG\Bin\..\include\stdint.h \ 6 | ..\Drivers\CMSIS\Include\cmsis_version.h \ 7 | ..\Drivers\CMSIS\Include\cmsis_compiler.h \ 8 | ..\Drivers\CMSIS\Include\cmsis_armclang.h \ 9 | d:\APP\Keil_v5\ARM\ARMCLANG\Bin\..\include\arm_compat.h \ 10 | d:\APP\Keil_v5\ARM\ARMCLANG\Bin\..\include\arm_acle.h \ 11 | ..\Drivers\CMSIS\Include\mpu_armv7.h \ 12 | ..\Drivers\CMSIS\Device\ST\STM32G0xx\Include\system_stm32g0xx.h \ 13 | ..\user\gpio.h ..\user\delay.h ..\user\sys.h \ 14 | d:\APP\Keil_v5\ARM\ARMCLANG\Bin\..\include\string.h \ 15 | d:\APP\Keil_v5\ARM\ARMCLANG\Bin\..\include\stdio.h ..\user\osc.h \ 16 | ..\user\adc.h ..\user\timer.h ..\user\spi.h ..\user\lcd.h \ 17 | ..\user\lcd_init.h ..\user\dma.h 18 | -------------------------------------------------------------------------------- /MDK-ARM/light/uart.o: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Eltecz/STM32G0_OSC/e14b962a4d484ad32d7ee06078c8bbb59055c97d/MDK-ARM/light/uart.o -------------------------------------------------------------------------------- /MDK-ARM/main.c: -------------------------------------------------------------------------------- 1 | /* 2 | * @Description: 3 | * @FilePath: \MDK-ARM\main.c 4 | * @Version: 2.0 5 | * @Autor: Eltecz 6 | * @Date: 2022-05-21 15:30:46 7 | * @LastEditors: Eltecz 8 | * @LastEditTime: 2022-07-14 19:45:55 9 | */ 10 | 11 | #include "sys.h" 12 | #include "per_conf.h" 13 | 14 | int main(void) 15 | { 16 | u8 i; 17 | u32 t; 18 | Stm32_Clock_Init(MAIN_FOSC, 4, 4, 4); 19 | delay_init(MAIN_FOSC); 20 | en_rcc(); 21 | PWM0_Init(6,7); 22 | PWM1_Init(6,7); 23 | Adc_DMA_Init(0,0); 24 | gpio_init(); 25 | SPI1_Init(); 26 | LCD_Init(); 27 | LCD_Clear(BLACK); 28 | osc_init(); 29 | while (1) 30 | { 31 | osc_app(); 32 | } 33 | 34 | } -------------------------------------------------------------------------------- /MDK-ARM/startup_stm32g030xx.s: -------------------------------------------------------------------------------- 1 | ;****************************************************************************** 2 | ;* File Name : startup_stm32g030xx.s 3 | ;* Author : MCD Application Team 4 | ;* Description : STM32G030xx devices vector table for MDK-ARM toolchain. 5 | ;* This module performs: 6 | ;* - Set the initial SP 7 | ;* - Set the initial PC == Reset_Handler 8 | ;* - Set the vector table entries with the exceptions ISR address 9 | ;* - Branches to __main in the C library (which eventually 10 | ;* calls main()). 11 | ;* After Reset the CortexM0 processor is in Thread mode, 12 | ;* priority is Privileged, and the Stack is set to Main. 13 | ;* <<< Use Configuration Wizard in Context Menu >>> 14 | ;****************************************************************************** 15 | ;* @attention 16 | ;* 17 | ;* Copyright (c) 2018-2021 STMicroelectronics. 18 | ;* All rights reserved. 19 | ;* 20 | ;* This software is licensed under terms that can be found in the LICENSE file 21 | ;* in the root directory of this software component. 22 | ;* If no LICENSE file comes with this software, it is provided AS-IS. 23 | ;* 24 | ;****************************************************************************** 25 | ; Amount of memory (in bytes) allocated for Stack 26 | ; Tailor this value to your application needs 27 | ; Stack Configuration 28 | ; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> 29 | ; 30 | 31 | Stack_Size EQU 0x800 32 | 33 | AREA STACK, NOINIT, READWRITE, ALIGN=3 34 | Stack_Mem SPACE Stack_Size 35 | __initial_sp 36 | 37 | 38 | ; Heap Configuration 39 | ; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> 40 | ; 41 | 42 | Heap_Size EQU 0x800 43 | 44 | AREA HEAP, NOINIT, READWRITE, ALIGN=3 45 | __heap_base 46 | Heap_Mem SPACE Heap_Size 47 | __heap_limit 48 | 49 | PRESERVE8 50 | THUMB 51 | 52 | 53 | ; Vector Table Mapped to Address 0 at Reset 54 | AREA RESET, DATA, READONLY 55 | EXPORT __Vectors 56 | EXPORT __Vectors_End 57 | EXPORT __Vectors_Size 58 | 59 | __Vectors DCD __initial_sp ; Top of Stack 60 | DCD Reset_Handler ; Reset Handler 61 | DCD NMI_Handler ; NMI Handler 62 | DCD HardFault_Handler ; Hard Fault Handler 63 | DCD 0 ; Reserved 64 | DCD 0 ; Reserved 65 | DCD 0 ; Reserved 66 | DCD 0 ; Reserved 67 | DCD 0 ; Reserved 68 | DCD 0 ; Reserved 69 | DCD 0 ; Reserved 70 | DCD SVC_Handler ; SVCall Handler 71 | DCD 0 ; Reserved 72 | DCD 0 ; Reserved 73 | DCD PendSV_Handler ; PendSV Handler 74 | DCD SysTick_Handler ; SysTick Handler 75 | 76 | ; External Interrupts 77 | DCD WWDG_IRQHandler ; Window Watchdog 78 | DCD 0 ; Reserved 79 | DCD RTC_TAMP_IRQHandler ; RTC through EXTI Line 80 | DCD FLASH_IRQHandler ; FLASH 81 | DCD RCC_IRQHandler ; RCC 82 | DCD EXTI0_1_IRQHandler ; EXTI Line 0 and 1 83 | DCD EXTI2_3_IRQHandler ; EXTI Line 2 and 3 84 | DCD EXTI4_15_IRQHandler ; EXTI Line 4 to 15 85 | DCD 0 ; Reserved 86 | DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 87 | DCD DMA1_Channel2_3_IRQHandler ; DMA1 Channel 2 and Channel 3 88 | DCD DMA1_Ch4_5_DMAMUX1_OVR_IRQHandler ; DMA1 Channel 4 to Channel 5, DMAMUX1 overrun 89 | DCD ADC1_IRQHandler ; ADC1 90 | DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation 91 | DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare 92 | DCD 0 ; Reserved 93 | DCD TIM3_IRQHandler ; TIM3 94 | DCD 0 ; Reserved 95 | DCD 0 ; Reserved 96 | DCD TIM14_IRQHandler ; TIM14 97 | DCD 0 ; Reserved 98 | DCD TIM16_IRQHandler ; TIM16 99 | DCD TIM17_IRQHandler ; TIM17 100 | DCD I2C1_IRQHandler ; I2C1 101 | DCD I2C2_IRQHandler ; I2C2 102 | DCD SPI1_IRQHandler ; SPI1 103 | DCD SPI2_IRQHandler ; SPI2 104 | DCD USART1_IRQHandler ; USART1 105 | DCD USART2_IRQHandler ; USART2 106 | DCD 0 ; Reserved 107 | DCD 0 ; Reserved 108 | DCD 0 ; Reserved 109 | 110 | __Vectors_End 111 | 112 | __Vectors_Size EQU __Vectors_End - __Vectors 113 | 114 | AREA |.text|, CODE, READONLY 115 | 116 | ; Reset handler routine 117 | Reset_Handler PROC 118 | EXPORT Reset_Handler [WEAK] 119 | IMPORT __main 120 | IMPORT SystemInit 121 | LDR R0, =SystemInit 122 | BLX R0 123 | LDR R0, =__main 124 | BX R0 125 | ENDP 126 | 127 | ; Dummy Exception Handlers (infinite loops which can be modified) 128 | 129 | NMI_Handler PROC 130 | EXPORT NMI_Handler [WEAK] 131 | B . 132 | ENDP 133 | HardFault_Handler\ 134 | PROC 135 | EXPORT HardFault_Handler [WEAK] 136 | B . 137 | ENDP 138 | SVC_Handler PROC 139 | EXPORT SVC_Handler [WEAK] 140 | B . 141 | ENDP 142 | PendSV_Handler PROC 143 | EXPORT PendSV_Handler [WEAK] 144 | B . 145 | ENDP 146 | SysTick_Handler PROC 147 | EXPORT SysTick_Handler [WEAK] 148 | B . 149 | ENDP 150 | 151 | Default_Handler PROC 152 | 153 | EXPORT WWDG_IRQHandler [WEAK] 154 | EXPORT RTC_TAMP_IRQHandler [WEAK] 155 | EXPORT FLASH_IRQHandler [WEAK] 156 | EXPORT RCC_IRQHandler [WEAK] 157 | EXPORT EXTI0_1_IRQHandler [WEAK] 158 | EXPORT EXTI2_3_IRQHandler [WEAK] 159 | EXPORT EXTI4_15_IRQHandler [WEAK] 160 | EXPORT DMA1_Channel1_IRQHandler [WEAK] 161 | EXPORT DMA1_Channel2_3_IRQHandler [WEAK] 162 | EXPORT DMA1_Ch4_5_DMAMUX1_OVR_IRQHandler [WEAK] 163 | EXPORT ADC1_IRQHandler [WEAK] 164 | EXPORT TIM1_BRK_UP_TRG_COM_IRQHandler [WEAK] 165 | EXPORT TIM1_CC_IRQHandler [WEAK] 166 | EXPORT TIM3_IRQHandler [WEAK] 167 | EXPORT TIM14_IRQHandler [WEAK] 168 | EXPORT TIM16_IRQHandler [WEAK] 169 | EXPORT TIM17_IRQHandler [WEAK] 170 | EXPORT I2C1_IRQHandler [WEAK] 171 | EXPORT I2C2_IRQHandler [WEAK] 172 | EXPORT SPI1_IRQHandler [WEAK] 173 | EXPORT SPI2_IRQHandler [WEAK] 174 | EXPORT USART1_IRQHandler [WEAK] 175 | EXPORT USART2_IRQHandler [WEAK] 176 | 177 | 178 | WWDG_IRQHandler 179 | RTC_TAMP_IRQHandler 180 | FLASH_IRQHandler 181 | RCC_IRQHandler 182 | EXTI0_1_IRQHandler 183 | EXTI2_3_IRQHandler 184 | EXTI4_15_IRQHandler 185 | DMA1_Channel1_IRQHandler 186 | DMA1_Channel2_3_IRQHandler 187 | DMA1_Ch4_5_DMAMUX1_OVR_IRQHandler 188 | ADC1_IRQHandler 189 | TIM1_BRK_UP_TRG_COM_IRQHandler 190 | TIM1_CC_IRQHandler 191 | TIM3_IRQHandler 192 | TIM14_IRQHandler 193 | TIM16_IRQHandler 194 | TIM17_IRQHandler 195 | I2C1_IRQHandler 196 | I2C2_IRQHandler 197 | SPI1_IRQHandler 198 | SPI2_IRQHandler 199 | USART1_IRQHandler 200 | USART2_IRQHandler 201 | 202 | B . 203 | 204 | ENDP 205 | 206 | ALIGN 207 | 208 | ;******************************************************************************* 209 | ; User Stack and Heap initialization 210 | ;******************************************************************************* 211 | IF :DEF:__MICROLIB 212 | 213 | EXPORT __initial_sp 214 | EXPORT __heap_base 215 | EXPORT __heap_limit 216 | 217 | ELSE 218 | 219 | IMPORT __use_two_region_memory 220 | EXPORT __user_initial_stackheap 221 | 222 | __user_initial_stackheap 223 | 224 | LDR R0, = Heap_Mem 225 | LDR R1, =(Stack_Mem + Stack_Size) 226 | LDR R2, = (Heap_Mem + Heap_Size) 227 | LDR R3, = Stack_Mem 228 | BX LR 229 | 230 | ALIGN 231 | 232 | ENDIF 233 | 234 | END 235 | 236 | ;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** 237 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # STM32G0_OSC 2 | 3 | #### 介绍 4 | STM32示波器基础版开源代码 5 | 6 | #### 介绍 7 | 见[LCEDA](https://oshwhub.com/eltecz/xing-huo-ji-hua-STM32shi-bo-bi-2) 8 | 本仓库仅保存工程代码，其他见LCEDA 9 | 一般不注释代码，后续讲解见LCEDA 10 | 11 | #### 安装教程 12 | 13 | keil编译工程即可，注意本项目工程使用AC6编译器 14 | 注意事项请移步立创EDA开源链接查询 15 | 16 | #### 使用说明 17 | 18 | **禁止商用！！！** 19 | 20 | #### 更新记录 21 | 22 | 22/7/16 初次上传 23 | -------------------------------------------------------------------------------- /keilkill.bat: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Eltecz/STM32G0_OSC/e14b962a4d484ad32d7ee06078c8bbb59055c97d/keilkill.bat -------------------------------------------------------------------------------- /user/adc.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Eltecz/STM32G0_OSC/e14b962a4d484ad32d7ee06078c8bbb59055c97d/user/adc.c -------------------------------------------------------------------------------- /user/adc.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Eltecz/STM32G0_OSC/e14b962a4d484ad32d7ee06078c8bbb59055c97d/user/adc.h -------------------------------------------------------------------------------- /user/delay.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Eltecz/STM32G0_OSC/e14b962a4d484ad32d7ee06078c8bbb59055c97d/user/delay.c -------------------------------------------------------------------------------- /user/delay.h: -------------------------------------------------------------------------------- 1 | #ifndef __DELAY_H 2 | #define __DELAY_H 3 | #include 4 | 5 | void delay_init(u16 SYSCLK); 6 | void delay_ms(u16 nms); 7 | void delay_us(u32 nus); 8 | 9 | #endif 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 | 39 | -------------------------------------------------------------------------------- /user/dma.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Eltecz/STM32G0_OSC/e14b962a4d484ad32d7ee06078c8bbb59055c97d/user/dma.c -------------------------------------------------------------------------------- /user/dma.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Eltecz/STM32G0_OSC/e14b962a4d484ad32d7ee06078c8bbb59055c97d/user/dma.h -------------------------------------------------------------------------------- /user/gpio.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Eltecz/STM32G0_OSC/e14b962a4d484ad32d7ee06078c8bbb59055c97d/user/gpio.c -------------------------------------------------------------------------------- /user/gpio.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Eltecz/STM32G0_OSC/e14b962a4d484ad32d7ee06078c8bbb59055c97d/user/gpio.h -------------------------------------------------------------------------------- /user/lcd.c: -------------------------------------------------------------------------------- 1 | #include "lcd.h" 2 | #include "lcd_font.h" 3 | 4 | u16 fill_color_buf; 5 | #if defined(__dma_h__) && defined(HARDSPI) 6 | 7 | 8 | 9 | void LCD_Fill(u8 xsta, u8 ysta, u8 xend, u8 yend, u16 color) 10 | { 11 | u8 i, j,xs,ys; 12 | u16 pix_num; 13 | xs=xend-xsta; 14 | ys=yend-ysta; 15 | pix_num=xs*ys; 16 | LCD_Address_Set(xsta, ysta, xend - 1, yend - 1); 17 | fill_color_buf=color; 18 | SPI1->CR2|=1<<1; 19 | #ifdef AUTO_CHANGE_SPI_LENGTH 20 | SPI1->CR2|=1<<11; 21 | SPI1_DMA_START(pix_num); 22 | #else 23 | SPI1_DMA_START(pix_num<<1); 24 | #endif 25 | while(!(DMA1->ISR&(1<<1))); 26 | DMA1->IFCR|=1<<0; 27 | SPI1->CR2-=1<<1; 28 | #ifdef AUTO_CHANGE_SPI_LENGTH 29 | SPI1->CR2-=1<<11; 30 | #endif 31 | } 32 | 33 | #else 34 | void LCD_Fill(u8 xsta, u8 ysta, u8 xend, u8 yend, u16 color) 35 | { 36 | u8 i, j,xs,ys; 37 | xs=xend-xsta; 38 | ys=yend-ysta; 39 | LCD_Address_Set(xsta, ysta, xend - 1, yend - 1); 40 | for (i = ysta; i < yend; i++) 41 | { 42 | for (j = xsta; j < xend; j++) 43 | { 44 | LCD_WR_DATA(color); 45 | } 46 | } 47 | } 48 | #endif 49 | void LCD_DrawPoint(u8 x, u8 y, u16 color) 50 | { 51 | LCD_Address_Set(x, y, x, y); 52 | LCD_WR_DATA(color); 53 | } 54 | 55 | void LCD_DrawLine(u8 x1, u8 y1, u8 x2, u8 y2, u16 color) 56 | { 57 | u8 t; 58 | int xerr = 0, yerr = 0, delta_x, delta_y, distance; 59 | char incx, incy, uRow, uCol; 60 | delta_x = x2 - x1; 61 | delta_y = y2 - y1; 62 | uRow = x1; 63 | uCol = y1; 64 | if (delta_x > 0) 65 | incx = 1; 66 | else if (delta_x == 0) 67 | incx = 0; 68 | else 69 | { 70 | incx = -1; 71 | delta_x = -delta_x; 72 | } 73 | if (delta_y > 0) 74 | incy = 1; 75 | else if (delta_y == 0) 76 | incy = 0; 77 | else 78 | { 79 | incy = -1; 80 | delta_y = -delta_y; 81 | } 82 | if (delta_x > delta_y) 83 | distance = delta_x; 84 | else 85 | distance = delta_y; 86 | for (t = 0; t < distance + 1; t++) 87 | { 88 | LCD_DrawPoint(uRow, uCol, color); 89 | xerr += delta_x; 90 | yerr += delta_y; 91 | if (xerr > distance) 92 | { 93 | xerr -= distance; 94 | uRow += incx; 95 | } 96 | if (yerr > distance) 97 | { 98 | yerr -= distance; 99 | uCol += incy; 100 | } 101 | } 102 | } 103 | 104 | u32 mypow(u8 m, u8 n) 105 | { 106 | u32 result = 1; 107 | while (n--) 108 | result *= m; 109 | return result; 110 | } 111 | 112 | void LCD_ShowChar(u8 x, u8 y, u8 num, u16 fc, u16 bc, u8 mode) 113 | { 114 | u8 temp, t, m, i; 115 | u8 x0 = x; 116 | m = 0; 117 | num = num - ' '; 118 | LCD_Address_Set(x, y, x + 5, y + 11); 119 | 120 | for (i = 0; i < 12; i++) 121 | { 122 | temp = ascii_1206[num][i]; 123 | for (t = 0; t < 8; t++) 124 | { 125 | if (!mode) 126 | { 127 | if (temp & (0x01 << t)) 128 | LCD_WR_DATA(fc); 129 | else 130 | LCD_WR_DATA(bc); 131 | m++; 132 | if (m % 6 == 0) 133 | { 134 | m = 0; 135 | break; 136 | } 137 | } 138 | else 139 | { 140 | if (temp & (0x01 << t)) 141 | LCD_DrawPoint(x, y, fc); 142 | x++; 143 | if ((x - x0) == 6) 144 | { 145 | x = x0; 146 | y++; 147 | break; 148 | } 149 | } 150 | } 151 | } 152 | } 153 | 154 | void LCD_ShowString(u8 x, u8 y, const u8 *p, u16 fc, u16 bc, u8 mode) 155 | { 156 | while (*p != '\0') 157 | { 158 | LCD_ShowChar(x, y, *p, fc, bc, mode); 159 | x += 6; 160 | p++; 161 | } 162 | } 163 | void LCD_ShowIntNum(u8 x, u8 y, u16 num, u8 len, u16 fc, u16 bc) 164 | { 165 | u8 t, temp; 166 | u8 enshow = 0; 167 | for (t = 0; t < len; t++) 168 | { 169 | temp = (num / mypow(10, len - t - 1)) % 10; 170 | if (enshow == 0 && t < (len - 1)) 171 | { 172 | if (temp == 0) 173 | { 174 | LCD_ShowChar(x + t * 6, y, ' ', fc, bc, 0); 175 | continue; 176 | } 177 | else 178 | enshow = 1; 179 | } 180 | LCD_ShowChar(x + t * 6, y, temp + 48, fc, bc, 0); 181 | } 182 | } 183 | 184 | void LCD_ShowFloatNum1(u8 x, u8 y, float num, u8 len, u16 fc, u16 bc) 185 | { 186 | u8 t, temp; 187 | u16 num1; 188 | num1 = num * 100; 189 | for (t = 0; t < len; t++) 190 | { 191 | temp = (num1 / mypow(10, len - t - 1)) % 10; 192 | if (t == (len - 2)) 193 | { 194 | LCD_ShowChar(x + (len - 2) * 6, y, '.', fc, bc, 0); 195 | t++; 196 | len += 1; 197 | } 198 | LCD_ShowChar(x + t * 6, y, temp + 48, fc, bc, 0); 199 | } 200 | } 201 | 202 | void LCD_Clear(u16 color) 203 | { 204 | 205 | LCD_Address_Set(0, 0, LCD_W - 1, LCD_H - 1); 206 | fill_color_buf=color; 207 | SPI1->CR2|=1<<1; 208 | #ifdef AUTO_CHANGE_SPI_LENGTH 209 | SPI1->CR2|=1<<11; 210 | SPI1_DMA_START(LCD_PIX_NUM); 211 | #else 212 | SPI1_DMA_START(LCD_PIX_NUM<<1); 213 | #endif 214 | while(!(DMA1->ISR&(1<<1))); 215 | DMA1->IFCR|=1<<0; 216 | SPI1->CR2-=1<<1; 217 | #ifdef AUTO_CHANGE_SPI_LENGTH 218 | SPI1->CR2-=1<<11; 219 | #endif 220 | } 221 | void LCD_Test_u(float t) 222 | { 223 | LCD_ShowString(10,20,"LCD_W:",RED,WHITE,0); 224 | LCD_ShowIntNum(58,20,LCD_W,3,RED,WHITE); 225 | LCD_ShowString(10,40,"LCD_H:",RED,WHITE,0); 226 | LCD_ShowIntNum(58,40,LCD_H,3,RED,WHITE); 227 | LCD_ShowFloatNum1(10,60,t,4,RED,WHITE); 228 | } 229 | 230 | /***************************************************************************** 231 | * @name :void LCD_DrawRectangle(u16 x1, u16 y1, u16 x2, u16 y2) 232 | * @date :2018-08-09 233 | * @function :Draw a rectangle 234 | * @parameters :x1:the bebinning x coordinate of the rectangle 235 | y1:the bebinning y coordinate of the rectangle 236 | x2:the ending x coordinate of the rectangle 237 | y2:the ending y coordinate of the rectangle 238 | * @retvalue :None 239 | ******************************************************************************/ 240 | void LCD_DrawRectangle(u16 x1, u16 y1, u16 x2, u16 y2,u16 color) 241 | { 242 | LCD_DrawLine(x1,y1,x2,y1,color); 243 | LCD_DrawLine(x1,y1,x1,y2,color); 244 | LCD_DrawLine(x1,y2,x2,y2,color); 245 | LCD_DrawLine(x2,y1,x2,y2,color); 246 | } -------------------------------------------------------------------------------- /user/lcd.h: -------------------------------------------------------------------------------- 1 | /* 2 | * @Description: 3 | * @FilePath: \MDK-ARMd:\工程\STM32\32\g0\osc_v1\user\lcd.h 4 | * @Version: 2.0 5 | * @Autor: Eltecz 6 | * @Date: 2022-05-21 21:15:41 7 | * @LastEditors: Eltecz 8 | * @LastEditTime: 2022-06-21 15:54:11 9 | */ 10 | #ifndef __lcd_h__ 11 | #define __lcd_h__ 12 | 13 | #include "per_conf.h" 14 | 15 | #ifdef __dma_h__ 16 | extern u16 fill_color_buf; 17 | #endif 18 | 19 | void LCD_Fill(u8 xsta, u8 ysta, u8 xend, u8 yend, u16 color); //指定区域填充颜色 20 | void LCD_DrawPoint(u8 x, u8 y, u16 color); //在指定位置画一个点 21 | void LCD_DrawLine(u8 x1, u8 y1, u8 x2, u8 y2, u16 color); //在指定位置画一条线 22 | 23 | void LCD_ShowChar(u8 x, u8 y, u8 num, u16 fc, u16 bc, u8 mode); 24 | void LCD_ShowString(u8 x, u8 y, const u8 *p, u16 fc, u16 bc, u8 mode); //显示字符串 25 | void LCD_ShowIntNum(u8 x, u8 y, u16 num, u8 len, u16 fc, u16 bc); //显示整数变量 26 | void LCD_ShowFloatNum1(u8 x, u8 y, float num, u8 len, u16 fc, u16 bc); //显示两位小数变量 27 | void LCD_Clear(u16 color); 28 | void LCD_Test_u(float t); 29 | void LCD_DrawRectangle(u16 x1, u16 y1, u16 x2, u16 y2,u16 color); 30 | u32 mypow(u8 m, u8 n); //求幂 31 | //void LCD_ShowPicture(u16 x,u16 y,u16 length,u16 width,const u8 pic[]);//显示图片 32 | 33 | //画笔颜色 34 | #ifdef OLD_SCREEN 35 | #define WHITE (0xffff - 0xFFFF) 36 | #define BLACK (0xffff - 0x0000) 37 | #define BLUE (0xffff - 0x001F) 38 | #define BRED (0xffff - 0xF81F) 39 | #define GRED (0xffff - 0xFFE0) 40 | #define GBLUE (0xffff - 0x07FF) 41 | #define RED (0xffff - 0xF800) 42 | #define MAGENTA (0xffff - 0xF81F) 43 | #define GREEN (0xffff - 0x07E0) 44 | #define CYAN (0xffff - 0x7FFF) 45 | #define YELLOW (0xffff - 0xFFE0) 46 | #define BROWN (0xffff - 0xBC40) //棕色 47 | #define BRRED (0xffff - 0xFC07) //棕红色 48 | #define GRAY (0xffff - 0x8430) //灰色 49 | #define DARKBLUE (0xffff - 0x01CF) //深蓝色 50 | #define LIGHTBLUE (0xffff - 0x7D7C) //浅蓝色 51 | #define GRAYBLUE (0xffff - 0x5458) //灰蓝色 52 | #define LIGHTGREEN (0xffff - 0x841F) //浅绿色 53 | #define LGRAY (0xffff - 0xC618) //浅灰色(PANNEL),窗体背景色 54 | #define LGRAYBLUE (0xffff - 0xA651) //浅灰蓝色(中间层颜色) 55 | #define LBBLUE (0xffff - 0x2B12) //浅棕蓝色(选择条目的反色) 56 | #else 57 | #define WHITE 0xFFFF 58 | #define BLACK 0x0000 59 | #define BLUE 0x001F 60 | #define BRED 0xF81F 61 | #define GRED 0xFFE0 62 | #define GBLUE 0x07FF 63 | #define RED 0xF800 64 | #define MAGENTA 0xF81F 65 | #define GREEN 0x07E0 66 | #define CYAN 0x7FFF 67 | #define YELLOW 0xFFE0 68 | #define BROWN 0xBC40 //棕色 69 | #define BRRED 0xFC07 //棕红色 70 | #define GRAY 0x8430 //灰色 71 | #define DARKBLUE 0x01CF //深蓝色 72 | #define LIGHTBLUE 0x7D7C //浅蓝色 73 | #define GRAYBLUE 0x5458 //灰蓝色 74 | #define LIGHTGREEN 0x841F //浅绿色 75 | #define LGRAY 0xC618 //浅灰色(PANNEL,窗体背景色 76 | #define LGRAYBLUE 0xA651 //浅灰蓝色(中间层颜色 77 | #define LBBLUE 0x2B12 //浅棕蓝色(选择条目的反色 78 | #endif 79 | 80 | #endif 81 | -------------------------------------------------------------------------------- /user/lcd_font.h: -------------------------------------------------------------------------------- 1 | #ifndef __LCD_FONT_H 2 | #define __LCD_FONT_H 3 | 4 | const unsigned char ascii_1206[][12]={ 5 | 6 | {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*" ",0*/ 7 | {0x00,0x00,0x04,0x04,0x04,0x04,0x04,0x00,0x00,0x04,0x00,0x00},/*"!",1*/ 8 | {0x14,0x14,0x0A,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*""",2*/ 9 | {0x00,0x00,0x0A,0x0A,0x1F,0x0A,0x0A,0x1F,0x0A,0x0A,0x00,0x00},/*"#",3*/ 10 | {0x00,0x04,0x0E,0x15,0x05,0x06,0x0C,0x14,0x15,0x0E,0x04,0x00},/*"$",4*/ 11 | {0x00,0x00,0x12,0x15,0x0D,0x15,0x2E,0x2C,0x2A,0x12,0x00,0x00},/*"%",5*/ 12 | {0x00,0x00,0x04,0x0A,0x0A,0x36,0x15,0x15,0x29,0x16,0x00,0x00},/*"&",6*/ 13 | {0x02,0x02,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"'",7*/ 14 | {0x10,0x08,0x08,0x04,0x04,0x04,0x04,0x04,0x08,0x08,0x10,0x00},/*"(",8*/ 15 | {0x02,0x04,0x04,0x08,0x08,0x08,0x08,0x08,0x04,0x04,0x02,0x00},/*")",9*/ 16 | {0x00,0x00,0x00,0x04,0x15,0x0E,0x0E,0x15,0x04,0x00,0x00,0x00},/*"*",10*/ 17 | {0x00,0x00,0x00,0x08,0x08,0x3E,0x08,0x08,0x00,0x00,0x00,0x00},/*"+",11*/ 18 | {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x02,0x02,0x01,0x00},/*",",12*/ 19 | {0x00,0x00,0x00,0x00,0x00,0x3F,0x00,0x00,0x00,0x00,0x00,0x00},/*"-",13*/ 20 | {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x02,0x00,0x00},/*".",14*/ 21 | {0x00,0x20,0x10,0x10,0x08,0x08,0x04,0x04,0x02,0x02,0x01,0x00},/*"/",15*/ 22 | {0x00,0x00,0x0E,0x11,0x11,0x11,0x11,0x11,0x11,0x0E,0x00,0x00},/*"0",16*/ 23 | {0x00,0x00,0x04,0x06,0x04,0x04,0x04,0x04,0x04,0x0E,0x00,0x00},/*"1",17*/ 24 | {0x00,0x00,0x0E,0x11,0x11,0x08,0x04,0x02,0x01,0x1F,0x00,0x00},/*"2",18*/ 25 | {0x00,0x00,0x0E,0x11,0x10,0x0C,0x10,0x10,0x11,0x0E,0x00,0x00},/*"3",19*/ 26 | {0x00,0x00,0x08,0x0C,0x0C,0x0A,0x09,0x1F,0x08,0x1C,0x00,0x00},/*"4",20*/ 27 | {0x00,0x00,0x1F,0x01,0x01,0x0F,0x11,0x10,0x11,0x0E,0x00,0x00},/*"5",21*/ 28 | {0x00,0x00,0x0C,0x12,0x01,0x0D,0x13,0x11,0x11,0x0E,0x00,0x00},/*"6",22*/ 29 | {0x00,0x00,0x1E,0x10,0x08,0x08,0x04,0x04,0x04,0x04,0x00,0x00},/*"7",23*/ 30 | {0x00,0x00,0x0E,0x11,0x11,0x0E,0x11,0x11,0x11,0x0E,0x00,0x00},/*"8",24*/ 31 | {0x00,0x00,0x0E,0x11,0x11,0x19,0x16,0x10,0x09,0x06,0x00,0x00},/*"9",25*/ 32 | {0x00,0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x00,0x04,0x00,0x00},/*":",26*/ 33 | {0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x04,0x04,0x00},/*";",27*/ 34 | {0x00,0x00,0x10,0x08,0x04,0x02,0x02,0x04,0x08,0x10,0x00,0x00},/*"<",28*/ 35 | {0x00,0x00,0x00,0x00,0x3F,0x00,0x3F,0x00,0x00,0x00,0x00,0x00},/*"=",29*/ 36 | {0x00,0x00,0x02,0x04,0x08,0x10,0x10,0x08,0x04,0x02,0x00,0x00},/*">",30*/ 37 | {0x00,0x00,0x0E,0x11,0x11,0x08,0x04,0x04,0x00,0x04,0x00,0x00},/*"?",31*/ 38 | {0x00,0x00,0x1C,0x22,0x29,0x2D,0x2D,0x1D,0x22,0x1C,0x00,0x00},/*"@",32*/ 39 | {0x00,0x00,0x04,0x04,0x0C,0x0A,0x0A,0x1E,0x12,0x33,0x00,0x00},/*"A",33*/ 40 | {0x00,0x00,0x0F,0x12,0x12,0x0E,0x12,0x12,0x12,0x0F,0x00,0x00},/*"B",34*/ 41 | {0x00,0x00,0x1E,0x11,0x01,0x01,0x01,0x01,0x11,0x0E,0x00,0x00},/*"C",35*/ 42 | {0x00,0x00,0x0F,0x12,0x12,0x12,0x12,0x12,0x12,0x0F,0x00,0x00},/*"D",36*/ 43 | {0x00,0x00,0x1F,0x12,0x0A,0x0E,0x0A,0x02,0x12,0x1F,0x00,0x00},/*"E",37*/ 44 | {0x00,0x00,0x1F,0x12,0x0A,0x0E,0x0A,0x02,0x02,0x07,0x00,0x00},/*"F",38*/ 45 | {0x00,0x00,0x1C,0x12,0x01,0x01,0x39,0x11,0x12,0x0C,0x00,0x00},/*"G",39*/ 46 | {0x00,0x00,0x33,0x12,0x12,0x1E,0x12,0x12,0x12,0x33,0x00,0x00},/*"H",40*/ 47 | {0x00,0x00,0x1F,0x04,0x04,0x04,0x04,0x04,0x04,0x1F,0x00,0x00},/*"I",41*/ 48 | {0x00,0x00,0x3E,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x09,0x07},/*"J",42*/ 49 | {0x00,0x00,0x37,0x12,0x0A,0x06,0x0A,0x12,0x12,0x37,0x00,0x00},/*"K",43*/ 50 | {0x00,0x00,0x07,0x02,0x02,0x02,0x02,0x02,0x22,0x3F,0x00,0x00},/*"L",44*/ 51 | {0x00,0x00,0x3B,0x1B,0x1B,0x1B,0x15,0x15,0x15,0x35,0x00,0x00},/*"M",45*/ 52 | {0x00,0x00,0x3B,0x12,0x16,0x16,0x1A,0x1A,0x12,0x17,0x00,0x00},/*"N",46*/ 53 | {0x00,0x00,0x0E,0x11,0x11,0x11,0x11,0x11,0x11,0x0E,0x00,0x00},/*"O",47*/ 54 | {0x00,0x00,0x0F,0x12,0x12,0x0E,0x02,0x02,0x02,0x07,0x00,0x00},/*"P",48*/ 55 | {0x00,0x00,0x0E,0x11,0x11,0x11,0x11,0x17,0x19,0x0E,0x18,0x00},/*"Q",49*/ 56 | {0x00,0x00,0x0F,0x12,0x12,0x0E,0x0A,0x12,0x12,0x37,0x00,0x00},/*"R",50*/ 57 | {0x00,0x00,0x1E,0x11,0x01,0x06,0x08,0x10,0x11,0x0F,0x00,0x00},/*"S",51*/ 58 | {0x00,0x00,0x1F,0x15,0x04,0x04,0x04,0x04,0x04,0x0E,0x00,0x00},/*"T",52*/ 59 | {0x00,0x00,0x33,0x12,0x12,0x12,0x12,0x12,0x12,0x0C,0x00,0x00},/*"U",53*/ 60 | {0x00,0x00,0x33,0x12,0x12,0x0A,0x0A,0x0C,0x04,0x04,0x00,0x00},/*"V",54*/ 61 | {0x00,0x00,0x15,0x15,0x15,0x15,0x0E,0x0A,0x0A,0x0A,0x00,0x00},/*"W",55*/ 62 | {0x00,0x00,0x1B,0x0A,0x0A,0x04,0x04,0x0A,0x0A,0x1B,0x00,0x00},/*"X",56*/ 63 | {0x00,0x00,0x1B,0x0A,0x0A,0x0A,0x04,0x04,0x04,0x0E,0x00,0x00},/*"Y",57*/ 64 | {0x00,0x00,0x1F,0x09,0x08,0x04,0x04,0x02,0x12,0x1F,0x00,0x00},/*"Z",58*/ 65 | {0x1C,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x1C,0x00},/*"[",59*/ 66 | {0x00,0x02,0x02,0x04,0x04,0x04,0x08,0x08,0x08,0x10,0x10,0x00},/*"\",60*/ 67 | {0x0E,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x0E,0x00},/*"]",61*/ 68 | {0x04,0x0A,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"^",62*/ 69 | {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x3F},/*"_",63*/ 70 | {0x02,0x04,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"`",64*/ 71 | {0x00,0x00,0x00,0x00,0x00,0x0C,0x12,0x1C,0x12,0x3C,0x00,0x00},/*"a",65*/ 72 | {0x00,0x03,0x02,0x02,0x02,0x0E,0x12,0x12,0x12,0x0E,0x00,0x00},/*"b",66*/ 73 | {0x00,0x00,0x00,0x00,0x00,0x1C,0x12,0x02,0x12,0x0C,0x00,0x00},/*"c",67*/ 74 | {0x00,0x18,0x10,0x10,0x10,0x1C,0x12,0x12,0x12,0x3C,0x00,0x00},/*"d",68*/ 75 | {0x00,0x00,0x00,0x00,0x00,0x0C,0x12,0x1E,0x02,0x1C,0x00,0x00},/*"e",69*/ 76 | {0x00,0x18,0x24,0x04,0x04,0x1E,0x04,0x04,0x04,0x1E,0x00,0x00},/*"f",70*/ 77 | {0x00,0x00,0x00,0x00,0x00,0x3C,0x12,0x0C,0x02,0x1C,0x22,0x1C},/*"g",71*/ 78 | {0x00,0x03,0x02,0x02,0x02,0x0E,0x12,0x12,0x12,0x37,0x00,0x00},/*"h",72*/ 79 | {0x00,0x04,0x04,0x00,0x00,0x06,0x04,0x04,0x04,0x0E,0x00,0x00},/*"i",73*/ 80 | {0x00,0x08,0x08,0x00,0x00,0x0C,0x08,0x08,0x08,0x08,0x08,0x07},/*"j",74*/ 81 | {0x00,0x03,0x02,0x02,0x02,0x1A,0x0A,0x06,0x0A,0x13,0x00,0x00},/*"k",75*/ 82 | {0x00,0x07,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x1F,0x00,0x00},/*"l",76*/ 83 | {0x00,0x00,0x00,0x00,0x00,0x0F,0x15,0x15,0x15,0x15,0x00,0x00},/*"m",77*/ 84 | {0x00,0x00,0x00,0x00,0x00,0x0F,0x12,0x12,0x12,0x37,0x00,0x00},/*"n",78*/ 85 | {0x00,0x00,0x00,0x00,0x00,0x0C,0x12,0x12,0x12,0x0C,0x00,0x00},/*"o",79*/ 86 | {0x00,0x00,0x00,0x00,0x00,0x0F,0x12,0x12,0x12,0x0E,0x02,0x07},/*"p",80*/ 87 | {0x00,0x00,0x00,0x00,0x00,0x1C,0x12,0x12,0x12,0x1C,0x10,0x38},/*"q",81*/ 88 | {0x00,0x00,0x00,0x00,0x00,0x1B,0x06,0x02,0x02,0x07,0x00,0x00},/*"r",82*/ 89 | {0x00,0x00,0x00,0x00,0x00,0x1E,0x02,0x0C,0x10,0x1E,0x00,0x00},/*"s",83*/ 90 | {0x00,0x00,0x00,0x04,0x04,0x1E,0x04,0x04,0x04,0x1C,0x00,0x00},/*"t",84*/ 91 | {0x00,0x00,0x00,0x00,0x00,0x1B,0x12,0x12,0x12,0x3C,0x00,0x00},/*"u",85*/ 92 | {0x00,0x00,0x00,0x00,0x00,0x1B,0x0A,0x0A,0x04,0x04,0x00,0x00},/*"v",86*/ 93 | {0x00,0x00,0x00,0x00,0x00,0x15,0x15,0x0E,0x0A,0x0A,0x00,0x00},/*"w",87*/ 94 | {0x00,0x00,0x00,0x00,0x00,0x1B,0x0A,0x04,0x0A,0x1B,0x00,0x00},/*"x",88*/ 95 | {0x00,0x00,0x00,0x00,0x00,0x33,0x12,0x12,0x0C,0x08,0x04,0x03},/*"y",89*/ 96 | {0x00,0x00,0x00,0x00,0x00,0x1E,0x08,0x04,0x04,0x1E,0x00,0x00},/*"z",90*/ 97 | {0x18,0x08,0x08,0x08,0x08,0x0C,0x08,0x08,0x08,0x08,0x18,0x00},/*"{",91*/ 98 | {0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08},/*"|",92*/ 99 | {0x06,0x04,0x04,0x04,0x04,0x08,0x04,0x04,0x04,0x04,0x06,0x00},/*"}",93*/ 100 | {0x16,0x09,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"~",94*/ 101 | //{0x00,0x3E,0x06,0x3A,0x12,0x22,0x02,0x02,0x02,0x02,0x3E,0x00}, 102 | //{0x00,0x1F,0x10,0x17,0x11,0x11,0x11,0x13,0x15,0x19,0x1F,0x00}, 103 | 104 | //{0x00,0x3E,0x02,0x3A,0x02,0x22,0x12,0x0A,0x02,0x02,0x3E,0x00}, 105 | //{0x00,0x1F,0x10,0x11,0x11,0x13,0x15,0x11,0x17,0x10,0x1F,0x00},/*"???????t",0*/ 106 | 107 | 108 | {0x00,0xFE,0x02,0x0A,0x92,0x62,0x62,0x92,0x0A,0x02,0xFE,0x00}, 109 | {0x00,0x1F,0x10,0x14,0x12,0x11,0x11,0x12,0x14,0x10,0x1F,0x00},/*"???????t",0*/ 110 | 111 | {0x00,0x3E,0x02,0x3A,0x02,0x0A,0x12,0x22,0x02,0x02,0x3E,0x00}, 112 | {0x00,0x1F,0x10,0x11,0x11,0x15,0x13,0x11,0x17,0x10,0x1F,0x00}, 113 | {0x00,0x3E,0x02,0x22,0x22,0x32,0x2A,0x22,0x3A,0x02,0x3E,0x00}, 114 | {0x00,0x1F,0x10,0x17,0x11,0x12,0x14,0x10,0x10,0x10,0x1F,0x00}, 115 | 116 | }; 117 | #endif 118 | 119 | 120 | -------------------------------------------------------------------------------- /user/lcd_init.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Eltecz/STM32G0_OSC/e14b962a4d484ad32d7ee06078c8bbb59055c97d/user/lcd_init.c -------------------------------------------------------------------------------- /user/lcd_init.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Eltecz/STM32G0_OSC/e14b962a4d484ad32d7ee06078c8bbb59055c97d/user/lcd_init.h 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