├── .gitignore
├── .gitmodules
├── README.md
├── desktop
├── main.py
└── requirements.txt
├── nucleo-f446re
├── .cproject
├── .mxproject
├── .project
├── .settings
│ └── language.settings.xml
├── Core
│ ├── Inc
│ │ ├── UartReadBuffer.h
│ │ ├── UartWriteBuffer.h
│ │ ├── main.h
│ │ ├── stm32f4xx_hal_conf.h
│ │ └── stm32f4xx_it.h
│ ├── Src
│ │ ├── UartReadBuffer.cpp
│ │ ├── UartWriteBuffer.cpp
│ │ ├── main.cpp
│ │ ├── stm32f4xx_hal_msp.c
│ │ ├── stm32f4xx_it.c
│ │ ├── syscalls.c
│ │ ├── sysmem.c
│ │ └── system_stm32f4xx.c
│ └── Startup
│ │ └── startup_stm32f446retx.s
├── Drivers
│ ├── CMSIS
│ │ ├── Device
│ │ │ └── ST
│ │ │ │ └── STM32F4xx
│ │ │ │ └── Include
│ │ │ │ ├── stm32f446xx.h
│ │ │ │ ├── stm32f4xx.h
│ │ │ │ └── system_stm32f4xx.h
│ │ └── Include
│ │ │ ├── cmsis_armcc.h
│ │ │ ├── cmsis_armclang.h
│ │ │ ├── cmsis_compiler.h
│ │ │ ├── cmsis_gcc.h
│ │ │ ├── cmsis_iccarm.h
│ │ │ ├── cmsis_version.h
│ │ │ ├── core_armv8mbl.h
│ │ │ ├── core_armv8mml.h
│ │ │ ├── core_cm0.h
│ │ │ ├── core_cm0plus.h
│ │ │ ├── core_cm1.h
│ │ │ ├── core_cm23.h
│ │ │ ├── core_cm3.h
│ │ │ ├── core_cm33.h
│ │ │ ├── core_cm4.h
│ │ │ ├── core_cm7.h
│ │ │ ├── core_sc000.h
│ │ │ ├── core_sc300.h
│ │ │ ├── mpu_armv7.h
│ │ │ ├── mpu_armv8.h
│ │ │ └── tz_context.h
│ └── STM32F4xx_HAL_Driver
│ │ ├── Inc
│ │ ├── Legacy
│ │ │ └── stm32_hal_legacy.h
│ │ ├── stm32f4xx_hal.h
│ │ ├── stm32f4xx_hal_cortex.h
│ │ ├── stm32f4xx_hal_def.h
│ │ ├── stm32f4xx_hal_dma.h
│ │ ├── stm32f4xx_hal_dma_ex.h
│ │ ├── stm32f4xx_hal_exti.h
│ │ ├── stm32f4xx_hal_flash.h
│ │ ├── stm32f4xx_hal_flash_ex.h
│ │ ├── stm32f4xx_hal_flash_ramfunc.h
│ │ ├── stm32f4xx_hal_gpio.h
│ │ ├── stm32f4xx_hal_gpio_ex.h
│ │ ├── stm32f4xx_hal_pwr.h
│ │ ├── stm32f4xx_hal_pwr_ex.h
│ │ ├── stm32f4xx_hal_rcc.h
│ │ ├── stm32f4xx_hal_rcc_ex.h
│ │ ├── stm32f4xx_hal_tim.h
│ │ ├── stm32f4xx_hal_tim_ex.h
│ │ └── stm32f4xx_hal_uart.h
│ │ └── Src
│ │ ├── stm32f4xx_hal.c
│ │ ├── stm32f4xx_hal_cortex.c
│ │ ├── stm32f4xx_hal_dma.c
│ │ ├── stm32f4xx_hal_dma_ex.c
│ │ ├── stm32f4xx_hal_exti.c
│ │ ├── stm32f4xx_hal_flash.c
│ │ ├── stm32f4xx_hal_flash_ex.c
│ │ ├── stm32f4xx_hal_flash_ramfunc.c
│ │ ├── stm32f4xx_hal_gpio.c
│ │ ├── stm32f4xx_hal_pwr.c
│ │ ├── stm32f4xx_hal_pwr_ex.c
│ │ ├── stm32f4xx_hal_rcc.c
│ │ ├── stm32f4xx_hal_rcc_ex.c
│ │ ├── stm32f4xx_hal_tim.c
│ │ ├── stm32f4xx_hal_tim_ex.c
│ │ └── stm32f4xx_hal_uart.c
├── STM32F446RETX_FLASH.ld
├── STM32F446RETX_RAM.ld
└── stm32-uart.ioc
├── proto
└── uart_messages.proto
└── setup.py
/.gitignore:
--------------------------------------------------------------------------------
1 | # Ignore the generated source code.
2 | nucleo-f446re/generated
3 | desktop/generated
4 |
5 | # Ignore build results
6 | nucleo-f446re/Debug
7 | nucleo-f446re/Release
8 |
9 | # Ignore the python virtualenv folder
10 | desktop/venv
11 |
12 | # Ignore the pycharm project folder.
13 | desktop/.idea
14 |
--------------------------------------------------------------------------------
/.gitmodules:
--------------------------------------------------------------------------------
1 | [submodule "EmbeddedProto"]
2 | path = EmbeddedProto
3 | url = https://github.com/Embedded-AMS/EmbeddedProto.git
4 |
--------------------------------------------------------------------------------
/README.md:
--------------------------------------------------------------------------------
1 |
2 | 
3 |
4 |
5 | Copyrights 2020-2024 Embedded AMS B.V. Hoorn, [www.EmbeddedAMS.nl](https://www.EmbeddedAMS.nl), [info@EmbeddedAMS.nl](mailto:info@EmbeddedAMS.nl)
6 |
7 |
8 | Looking for a more elaborate description of this example? Please visit: https://embeddedproto.com/a-simple-uart-example-with-embedded-proto/
9 |
10 |
11 | # Introduction
12 |
13 | This repository hosts example code for Embedded Proto, the embedded implementation of Google Protocol Buffers. It is a simple example showing how a micro controller and desktop pc can communicate over UART. Command messages are send from a desktop script over an UART comport to the MCU.
14 |
15 | 
16 |
17 | This example mimics a fun fair game. Move the claw around and see if you can catch the price!
18 |
19 | 
20 |
21 | This example makes use of a NUCLEO-F446RE board made by ST Microelectronics. This board holds an ARM Cortex-M4. To build the source code and program the hardware STM32CubeIDE has been used.
22 |
23 | The desktop program is a simple terminal python script. You can use the keys as stated when you start the application to move around and grab your price.
24 |
25 |
26 | # Installation
27 |
28 | 1. Install STM32CubeIDE if you have not already.
29 | 2. Install the dependencies required by Embedded Proto. They are listed [here](https://github.com/Embedded-AMS/EmbeddedProto).
30 | 3. Checkout this example repository including the submodule of Embedded Proto: `git clone --recursive https://github.com/Embedded-AMS/EmbeddedProto_Example_STM32_UART.git`.
31 | 4. Setup the environment required for Embedded Proto and the desktop script by running the setup script: `python setup.py`.
32 |
33 | The setup script already does it for you but you can regenerate the source code using the `python setup.py --generate` parameter. This is required when you have changed the \*.proto file.
34 |
35 |
36 | # Running the code
37 |
38 | Connect the NUCLEO via the usb programmer and use STM32CubeIDE to build and program the micro controller on it. Next find out which comport has been allocated for the NUCLEO. In the example code below it was ttyACM0. Next go to the desktop folder, activate the virtual environment and run the script.
39 |
40 | On Linux:
41 | ```bash
42 | cd desktop
43 | source venv/bin/activate
44 | python3 main.py --com /dev/ttyACM0
45 | ```
46 |
47 | On Windows PowerShell:
48 | ```bash
49 | cd desktop
50 | .\venv\Script\Activate.ps1
51 | python main.py --com COM1
52 | ```
53 |
54 | Have fun!
55 |
--------------------------------------------------------------------------------
/desktop/main.py:
--------------------------------------------------------------------------------
1 | #
2 | # Copyright (C) 2020-2024 Embedded AMS B.V. - All Rights Reserved
3 | #
4 | # This file is part of Embedded Proto.
5 | #
6 | # Embedded Proto is open source software: you can redistribute it and/or
7 | # modify it under the terms of the GNU General Public License as published
8 | # by the Free Software Foundation, version 3 of the license.
9 | #
10 | # Embedded Proto is distributed in the hope that it will be useful,
11 | # but WITHOUT ANY WARRANTY; without even the implied warranty of
12 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 | # GNU General Public License for more details.
14 | #
15 | # You should have received a copy of the GNU General Public License
16 | # along with Embedded Proto. If not, see .
17 | #
18 | # For commercial and closed source application please visit:
19 | # .
20 | #
21 | # Embedded AMS B.V.
22 | # Info:
23 | # info at EmbeddedProto dot com
24 | #
25 | # Postal address:
26 | # Atoomweg 2
27 | # 1627 LE, Hoorn
28 | # the Netherlands
29 | #
30 |
31 | import serial
32 | import argparse
33 | from generated import uart_messages_pb2
34 |
35 |
36 | def print_control_keys():
37 | print("Command keys are:")
38 | print("To move around press:")
39 | print(" w")
40 | print("a s d")
41 | print("")
42 | print("To try to grab your price press \"g\"")
43 | print("If your done press \"Q\"")
44 |
45 |
46 | def process_cmd_input():
47 | send_command = True
48 | quit = False
49 | msg = uart_messages_pb2.Command()
50 | msg.value = 1
51 |
52 | char = input("Next command: ")
53 | if "w" == char:
54 | msg.button = uart_messages_pb2.Command.Up
55 | elif "s" == char:
56 | msg.button = uart_messages_pb2.Command.Down
57 | elif "a" == char:
58 | msg.button = uart_messages_pb2.Command.Left
59 | elif "d" == char:
60 | msg.button = uart_messages_pb2.Command.Right
61 | elif "g" == char:
62 | msg.button = uart_messages_pb2.Command.Grab
63 | elif "Q" == char:
64 | msg.button = uart_messages_pb2.Command.Stop
65 | # Stop the loop
66 | quit = True
67 | else:
68 | send_command = False
69 | print_control_keys()
70 |
71 | if send_command:
72 | return msg, quit
73 | else:
74 | return None, quit
75 |
76 |
77 | if __name__ == "__main__":
78 | parser = argparse.ArgumentParser()
79 | parser.add_argument('-c', '--com', default="/dev/ttyACM0", help='The desired comport to open')
80 | args = parser.parse_args()
81 |
82 | # Try to open the serial port with the default baud rate.
83 | with serial.Serial(args.com, 115200, timeout=1) as ser:
84 | print_control_keys()
85 |
86 | running = True
87 |
88 | while running:
89 | command, quit = process_cmd_input()
90 | running = not quit
91 |
92 | if command:
93 | b = bytearray()
94 |
95 | # Serialize the command message and send it over uart.
96 | command_str = command.SerializeToString()
97 | # First send the length of the message.
98 | l = len(command_str)
99 | b.extend(l.to_bytes(1, byteorder='little'))
100 | # Next send the actual data
101 | b.extend(command_str)
102 | ser.write(b)
103 |
104 | # Await a reply.
105 | # First the length of the message.
106 | length_bytes = ser.read(1)
107 | length = int.from_bytes(length_bytes, byteorder="little")
108 | if 0 < length:
109 | # Next the actual data
110 | bytes = ser.read(length)
111 |
112 | # Check if we have received all bytes.
113 | if length == len(bytes):
114 | reply = uart_messages_pb2.Reply()
115 | reply.ParseFromString(bytes)
116 |
117 | # Do something with the reply.
118 | if reply.price:
119 | print("We have a winner!")
120 | else:
121 | print("x pos: " + str(reply.x_pos))
122 | print("y pos: " + str(reply.y_pos))
123 |
124 |
--------------------------------------------------------------------------------
/desktop/requirements.txt:
--------------------------------------------------------------------------------
1 | protobuf==4.21.6
2 | pyserial==3.4
3 | six==1.15.0
4 |
--------------------------------------------------------------------------------
/nucleo-f446re/.mxproject:
--------------------------------------------------------------------------------
1 | [PreviousLibFiles]
2 | LibFiles=Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h;Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h;Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h;Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h;Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h;Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h;Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/system_stm32f4xx.c;Drivers/CMSIS/Include/mpu_armv8.h;Drivers/CMSIS/Include/tz_context.h;Drivers/CMSIS/Include/core_cm4.h;Drivers/CMSIS/Include/cmsis_armcc.h;Drivers/CMSIS/Include/core_sc300.h;Drivers/CMSIS/Include/cmsis_gcc.h;Drivers/CMSIS/Include/core_cm33.h;Drivers/CMSIS/Include/core_cm3.h;Drivers/CMSIS/Include/core_sc000.h;Drivers/CMSIS/Include/cmsis_compiler.h;Drivers/CMSIS/Include/core_cm0.h;Drivers/CMSIS/Include/mpu_armv7.h;Drivers/CMSIS/Include/core_armv8mbl.h;Drivers/CMSIS/Include/core_cm7.h;Drivers/CMSIS/Include/core_cm23.h;Drivers/CMSIS/Include/cmsis_armclang.h;Drivers/CMSIS/Include/core_armv8mml.h;Drivers/CMSIS/Include/core_cm0plus.h;Drivers/CMSIS/Include/cmsis_version.h;Drivers/CMSIS/Include/core_cm1.h;Drivers/CMSIS/Include/cmsis_iccarm.h;
3 |
4 | [PreviousUsedCubeIDEFiles]
5 | SourceFiles=Core/Src/main.c;Core/Src/stm32f4xx_it.c;Core/Src/stm32f4xx_hal_msp.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c;Core/Src/system_stm32f4xx.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c;Core/Src/system_stm32f4xx.c;Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/system_stm32f4xx.c;;
6 | HeaderPath=Drivers/STM32F4xx_HAL_Driver/Inc;Drivers/STM32F4xx_HAL_Driver/Inc/Legacy;Drivers/CMSIS/Device/ST/STM32F4xx/Include;Drivers/CMSIS/Include;Core/Inc;
7 | CDefines=USE_HAL_DRIVER;STM32F446xx;USE_HAL_DRIVER;USE_HAL_DRIVER;
8 |
9 | [PreviousGenFiles]
10 | AdvancedFolderStructure=true
11 | HeaderFileListSize=3
12 | HeaderFiles#0=/home/bart/EAMS/EmbeddedProto_Example_STM32_UART/nucleo-f446re/Core/Inc/stm32f4xx_it.h
13 | HeaderFiles#1=/home/bart/EAMS/EmbeddedProto_Example_STM32_UART/nucleo-f446re/Core/Inc/stm32f4xx_hal_conf.h
14 | HeaderFiles#2=/home/bart/EAMS/EmbeddedProto_Example_STM32_UART/nucleo-f446re/Core/Inc/main.h
15 | HeaderFolderListSize=1
16 | HeaderPath#0=/home/bart/EAMS/EmbeddedProto_Example_STM32_UART/nucleo-f446re/Core/Inc
17 | HeaderFiles=;
18 | SourceFileListSize=3
19 | SourceFiles#0=/home/bart/EAMS/EmbeddedProto_Example_STM32_UART/nucleo-f446re/Core/Src/stm32f4xx_it.c
20 | SourceFiles#1=/home/bart/EAMS/EmbeddedProto_Example_STM32_UART/nucleo-f446re/Core/Src/stm32f4xx_hal_msp.c
21 | SourceFiles#2=/home/bart/EAMS/EmbeddedProto_Example_STM32_UART/nucleo-f446re/Core/Src/main.c
22 | SourceFolderListSize=1
23 | SourcePath#0=/home/bart/EAMS/EmbeddedProto_Example_STM32_UART/nucleo-f446re/Core/Src
24 | SourceFiles=;
25 |
26 |
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/nucleo-f446re/.project:
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1 |
2 |
3 | stm32-uart
4 |
5 |
6 |
7 |
8 |
9 | org.eclipse.cdt.managedbuilder.core.genmakebuilder
10 | clean,full,incremental,
11 |
12 |
13 |
14 |
15 | org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder
16 | full,incremental,
17 |
18 |
19 |
20 |
21 |
22 | com.st.stm32cube.ide.mcu.MCUProjectNature
23 | com.st.stm32cube.ide.mcu.MCUCubeProjectNature
24 | org.eclipse.cdt.core.cnature
25 | org.eclipse.cdt.core.ccnature
26 | com.st.stm32cube.ide.mcu.MCUCubeIdeServicesRevAProjectNature
27 | com.st.stm32cube.ide.mcu.MCUAdvancedStructureProjectNature
28 | com.st.stm32cube.ide.mcu.MCUEndUserDisabledTrustZoneProjectNature
29 | com.st.stm32cube.ide.mcu.MCUSingleCpuProjectNature
30 | com.st.stm32cube.ide.mcu.MCURootProjectNature
31 | org.eclipse.cdt.managedbuilder.core.managedBuildNature
32 | org.eclipse.cdt.managedbuilder.core.ScannerConfigNature
33 |
34 |
35 |
36 | EmbeddedProtoSrc
37 | 2
38 | $%7BPARENT-1-PROJECT_LOC%7D/EmbeddedProto/src
39 |
40 |
41 |
42 |
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/nucleo-f446re/.settings/language.settings.xml:
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/nucleo-f446re/Core/Inc/UartReadBuffer.h:
--------------------------------------------------------------------------------
1 | /*
2 | * Copyright (C) 2020-2022 Embedded AMS B.V. - All Rights Reserved
3 | *
4 | * This file is part of Embedded Proto.
5 | *
6 | * Embedded Proto is open source software: you can redistribute it and/or
7 | * modify it under the terms of the GNU General Public License as published
8 | * by the Free Software Foundation, version 3 of the license.
9 | *
10 | * Embedded Proto is distributed in the hope that it will be useful,
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 | * GNU General Public License for more details.
14 | *
15 | * You should have received a copy of the GNU General Public License
16 | * along with Embedded Proto. If not, see .
17 | *
18 | * For commercial and closed source application please visit:
19 | * .
20 | *
21 | * Embedded AMS B.V.
22 | * Info:
23 | * info at EmbeddedProto dot com
24 | *
25 | * Postal adress:
26 | * Johan Huizingalaan 763a
27 | * 1066 VH, Amsterdam
28 | * the Netherlands
29 | */
30 |
31 | #ifndef INC_UARTREADBUFFER_H_
32 | #define INC_UARTREADBUFFER_H_
33 |
34 | #include
35 | #include
36 |
37 | class UartReadBuffer : public ::EmbeddedProto::ReadBufferInterface
38 | {
39 | //! Store a maximum of MAX_SIZE bytes in the buffer
40 | static constexpr uint32_t MAX_SIZE = 50;
41 |
42 | public:
43 | UartReadBuffer();
44 | ~UartReadBuffer() override = default;
45 |
46 | /** \see ::EmbeddedProto::ReadBufferInterface::get_size() */
47 | uint32_t get_size() const override;
48 |
49 | /** \see ::EmbeddedProto::ReadBufferInterface::get_max_size() */
50 | uint32_t get_max_size() const override;
51 |
52 | /** \see ::EmbeddedProto::ReadBufferInterface::peak() */
53 | bool peek(uint8_t& byte) const override;
54 |
55 | /** \see ::EmbeddedProto::ReadBufferInterface::advance() */
56 | bool advance() override;
57 |
58 | /** \see ::EmbeddedProto::ReadBufferInterface::advance(const uint32_t N) */
59 | bool advance(const uint32_t N) override;
60 |
61 | /** \see ::EmbeddedProto::ReadBufferInterface::pop() */
62 | bool pop(uint8_t& byte) override;
63 |
64 | //! Return a pointer to the data array
65 | uint8_t* get_data_array();
66 |
67 | //! Return a non constant reference to the number of bytes written to the data array.
68 | uint32_t& get_bytes_written();
69 |
70 | //! Clear all indices, in effect allowing the data to be overwritten.
71 | void clear();
72 |
73 | //! Push new data into the buffer.
74 | bool push(uint8_t& byte);
75 |
76 | private:
77 |
78 | //! The array in which the data received over uart is stored.
79 | uint8_t data_[MAX_SIZE];
80 |
81 | //! The number of bytes currently received and stored in the data array.
82 | uint32_t write_index_;
83 |
84 | //! The number of bytes read from the data array.
85 | uint32_t read_index_;
86 | };
87 |
88 |
89 | #endif /* INC_UARTREADBUFFER_H_ */
90 |
--------------------------------------------------------------------------------
/nucleo-f446re/Core/Inc/UartWriteBuffer.h:
--------------------------------------------------------------------------------
1 | /*
2 | * Copyright (C) 2020-2022 Embedded AMS B.V. - All Rights Reserved
3 | *
4 | * This file is part of Embedded Proto.
5 | *
6 | * Embedded Proto is open source software: you can redistribute it and/or
7 | * modify it under the terms of the GNU General Public License as published
8 | * by the Free Software Foundation, version 3 of the license.
9 | *
10 | * Embedded Proto is distributed in the hope that it will be useful,
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 | * GNU General Public License for more details.
14 | *
15 | * You should have received a copy of the GNU General Public License
16 | * along with Embedded Proto. If not, see .
17 | *
18 | * For commercial and closed source application please visit:
19 | * .
20 | *
21 | * Embedded AMS B.V.
22 | * Info:
23 | * info at EmbeddedProto dot com
24 | *
25 | * Postal adress:
26 | * Johan Huizingalaan 763a
27 | * 1066 VH, Amsterdam
28 | * the Netherlands
29 | */
30 |
31 | #ifndef INC_UARTWRITEBUFFER_H_
32 | #define INC_UARTWRITEBUFFER_H_
33 |
34 | #include
35 | #include
36 |
37 | class UartWriteBuffer : public ::EmbeddedProto::WriteBufferInterface
38 | {
39 | //! Store a maximum of MAX_SIZE bytes in the buffer
40 | static constexpr uint32_t MAX_SIZE = 50;
41 |
42 | public:
43 | UartWriteBuffer() = default;
44 | ~UartWriteBuffer() override = default;
45 |
46 | //! \see ::EmbeddedProto::WriteBufferInterface::clear()
47 | virtual void clear() override;
48 |
49 | //! \see ::EmbeddedProto::WriteBufferInterface::get_size()
50 | virtual uint32_t get_size() const override;
51 |
52 | //! \see ::EmbeddedProto::WriteBufferInterface::get_max_size()
53 | virtual uint32_t get_max_size() const override;
54 |
55 | //! \see ::EmbeddedProto::WriteBufferInterface::get_available_size()
56 | virtual uint32_t get_available_size() const override;
57 |
58 | //! \see ::EmbeddedProto::WriteBufferInterface::push()
59 | virtual bool push(const uint8_t byte) override;
60 |
61 | //! \see ::EmbeddedProto::WriteBufferInterface::push()
62 | virtual bool push(const uint8_t* bytes, const uint32_t length) override;
63 |
64 | //! Return a pointer to the data array.
65 | uint8_t* get_data();
66 |
67 | private:
68 |
69 | //! The array in which the serialized data is stored.
70 | uint8_t data_[MAX_SIZE];
71 |
72 | //! The number of bytes currently serialized in the array.
73 | uint32_t write_index_;
74 |
75 | };
76 |
77 |
78 | #endif /* INC_UARTWRITEBUFFER_H_ */
79 |
--------------------------------------------------------------------------------
/nucleo-f446re/Core/Inc/main.h:
--------------------------------------------------------------------------------
1 | /* USER CODE BEGIN Header */
2 | /**
3 | ******************************************************************************
4 | * @file : main.h
5 | * @brief : Header for main.c file.
6 | * This file contains the common defines of the application.
7 | ******************************************************************************
8 | * @attention
9 | *
10 | * © Copyright (c) 2020 STMicroelectronics.
11 | * All rights reserved.
12 | *
13 | * This software component is licensed by ST under BSD 3-Clause license,
14 | * the "License"; You may not use this file except in compliance with the
15 | * License. You may obtain a copy of the License at:
16 | * opensource.org/licenses/BSD-3-Clause
17 | *
18 | ******************************************************************************
19 | */
20 | /* USER CODE END Header */
21 |
22 | /* Define to prevent recursive inclusion -------------------------------------*/
23 | #ifndef __MAIN_H
24 | #define __MAIN_H
25 |
26 | #ifdef __cplusplus
27 | extern "C" {
28 | #endif
29 |
30 | /* Includes ------------------------------------------------------------------*/
31 | #include "stm32f4xx_hal.h"
32 |
33 | /* Private includes ----------------------------------------------------------*/
34 | /* USER CODE BEGIN Includes */
35 |
36 | /* USER CODE END Includes */
37 |
38 | /* Exported types ------------------------------------------------------------*/
39 | /* USER CODE BEGIN ET */
40 |
41 | /* USER CODE END ET */
42 |
43 | /* Exported constants --------------------------------------------------------*/
44 | /* USER CODE BEGIN EC */
45 |
46 | /* USER CODE END EC */
47 |
48 | /* Exported macro ------------------------------------------------------------*/
49 | /* USER CODE BEGIN EM */
50 |
51 | /* USER CODE END EM */
52 |
53 | /* Exported functions prototypes ---------------------------------------------*/
54 | void Error_Handler(void);
55 |
56 | /* USER CODE BEGIN EFP */
57 |
58 | /* USER CODE END EFP */
59 |
60 | /* Private defines -----------------------------------------------------------*/
61 | #define B1_Pin GPIO_PIN_13
62 | #define B1_GPIO_Port GPIOC
63 | #define USART_TX_Pin GPIO_PIN_2
64 | #define USART_TX_GPIO_Port GPIOA
65 | #define USART_RX_Pin GPIO_PIN_3
66 | #define USART_RX_GPIO_Port GPIOA
67 | #define LD2_Pin GPIO_PIN_5
68 | #define LD2_GPIO_Port GPIOA
69 | #define TMS_Pin GPIO_PIN_13
70 | #define TMS_GPIO_Port GPIOA
71 | #define TCK_Pin GPIO_PIN_14
72 | #define TCK_GPIO_Port GPIOA
73 | #define SWO_Pin GPIO_PIN_3
74 | #define SWO_GPIO_Port GPIOB
75 | /* USER CODE BEGIN Private defines */
76 |
77 | /* USER CODE END Private defines */
78 |
79 | #ifdef __cplusplus
80 | }
81 | #endif
82 |
83 | #endif /* __MAIN_H */
84 |
85 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
86 |
--------------------------------------------------------------------------------
/nucleo-f446re/Core/Inc/stm32f4xx_it.h:
--------------------------------------------------------------------------------
1 | /* USER CODE BEGIN Header */
2 | /**
3 | ******************************************************************************
4 | * @file stm32f4xx_it.h
5 | * @brief This file contains the headers of the interrupt handlers.
6 | ******************************************************************************
7 | * @attention
8 | *
9 | * © Copyright (c) 2020 STMicroelectronics.
10 | * All rights reserved.
11 | *
12 | * This software component is licensed by ST under BSD 3-Clause license,
13 | * the "License"; You may not use this file except in compliance with the
14 | * License. You may obtain a copy of the License at:
15 | * opensource.org/licenses/BSD-3-Clause
16 | *
17 | ******************************************************************************
18 | */
19 | /* USER CODE END Header */
20 |
21 | /* Define to prevent recursive inclusion -------------------------------------*/
22 | #ifndef __STM32F4xx_IT_H
23 | #define __STM32F4xx_IT_H
24 |
25 | #ifdef __cplusplus
26 | extern "C" {
27 | #endif
28 |
29 | /* Private includes ----------------------------------------------------------*/
30 | /* USER CODE BEGIN Includes */
31 |
32 | /* USER CODE END Includes */
33 |
34 | /* Exported types ------------------------------------------------------------*/
35 | /* USER CODE BEGIN ET */
36 |
37 | /* USER CODE END ET */
38 |
39 | /* Exported constants --------------------------------------------------------*/
40 | /* USER CODE BEGIN EC */
41 |
42 | /* USER CODE END EC */
43 |
44 | /* Exported macro ------------------------------------------------------------*/
45 | /* USER CODE BEGIN EM */
46 |
47 | /* USER CODE END EM */
48 |
49 | /* Exported functions prototypes ---------------------------------------------*/
50 | void NMI_Handler(void);
51 | void HardFault_Handler(void);
52 | void MemManage_Handler(void);
53 | void BusFault_Handler(void);
54 | void UsageFault_Handler(void);
55 | void SVC_Handler(void);
56 | void DebugMon_Handler(void);
57 | void PendSV_Handler(void);
58 | void SysTick_Handler(void);
59 | /* USER CODE BEGIN EFP */
60 |
61 | /* USER CODE END EFP */
62 |
63 | #ifdef __cplusplus
64 | }
65 | #endif
66 |
67 | #endif /* __STM32F4xx_IT_H */
68 |
69 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
70 |
--------------------------------------------------------------------------------
/nucleo-f446re/Core/Src/UartReadBuffer.cpp:
--------------------------------------------------------------------------------
1 | /*
2 | * Copyright (C) 2020-2024 Embedded AMS B.V. - All Rights Reserved
3 | *
4 | * This file is part of Embedded Proto.
5 | *
6 | * Embedded Proto is open source software: you can redistribute it and/or
7 | * modify it under the terms of the GNU General Public License as published
8 | * by the Free Software Foundation, version 3 of the license.
9 | *
10 | * Embedded Proto is distributed in the hope that it will be useful,
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 | * GNU General Public License for more details.
14 | *
15 | * You should have received a copy of the GNU General Public License
16 | * along with Embedded Proto. If not, see .
17 | *
18 | * For commercial and closed source application please visit:
19 | * .
20 | *
21 | * Embedded AMS B.V.
22 | * Info:
23 | * info at EmbeddedProto dot com
24 | *
25 | * Postal adress:
26 | * Atoomweg 2
27 | * 1627 LE, Hoorn
28 | * the Netherlands
29 | */
30 |
31 | #include "UartReadBuffer.h"
32 |
33 | UartReadBuffer::UartReadBuffer()
34 | : data_{0},
35 | write_index_(0),
36 | read_index_(0)
37 | {
38 |
39 | }
40 |
41 | uint32_t UartReadBuffer::get_size() const
42 | {
43 | return write_index_;
44 | }
45 |
46 | uint32_t UartReadBuffer::get_max_size() const
47 | {
48 | return MAX_SIZE;
49 | }
50 |
51 | bool UartReadBuffer::peek(uint8_t& byte) const
52 | {
53 | const bool return_value = write_index_ > read_index_;
54 | if(return_value)
55 | {
56 | byte = data_[read_index_];
57 | }
58 | return return_value;
59 | }
60 |
61 | bool UartReadBuffer::advance()
62 | {
63 | const bool return_value = write_index_ > read_index_;
64 | if(return_value)
65 | {
66 | ++read_index_;
67 | }
68 | return return_value;
69 | }
70 |
71 | bool UartReadBuffer::advance(const uint32_t N)
72 | {
73 | const uint32_t new_read_index = read_index_ + N;
74 | const bool return_value = write_index_ > new_read_index;
75 | if(return_value)
76 | {
77 | read_index_ = new_read_index;
78 | }
79 | return return_value;
80 | }
81 |
82 | bool UartReadBuffer::pop(uint8_t& byte)
83 | {
84 | const bool return_value = write_index_ > read_index_;
85 | if(return_value) {
86 | byte = data_[read_index_];
87 | ++read_index_;
88 | }
89 | return return_value;
90 | }
91 |
92 | uint8_t* UartReadBuffer::get_data_array()
93 | {
94 | return data_;
95 | }
96 |
97 | uint32_t& UartReadBuffer::get_bytes_written()
98 | {
99 | return write_index_;
100 | }
101 |
102 | void UartReadBuffer::clear()
103 | {
104 | read_index_ = 0;
105 | write_index_ = 0;
106 | }
107 |
108 | bool UartReadBuffer::push(uint8_t& byte)
109 | {
110 | const bool return_value = MAX_SIZE > write_index_;
111 | if(return_value)
112 | {
113 | data_[write_index_] = byte;
114 | ++write_index_;
115 | }
116 | return return_value;
117 | }
118 |
119 |
--------------------------------------------------------------------------------
/nucleo-f446re/Core/Src/UartWriteBuffer.cpp:
--------------------------------------------------------------------------------
1 | /*
2 | * Copyright (C) 2020-2024 Embedded AMS B.V. - All Rights Reserved
3 | *
4 | * This file is part of Embedded Proto.
5 | *
6 | * Embedded Proto is open source software: you can redistribute it and/or
7 | * modify it under the terms of the GNU General Public License as published
8 | * by the Free Software Foundation, version 3 of the license.
9 | *
10 | * Embedded Proto is distributed in the hope that it will be useful,
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 | * GNU General Public License for more details.
14 | *
15 | * You should have received a copy of the GNU General Public License
16 | * along with Embedded Proto. If not, see .
17 | *
18 | * For commercial and closed source application please visit:
19 | * .
20 | *
21 | * Embedded AMS B.V.
22 | * Info:
23 | * info at EmbeddedProto dot com
24 | *
25 | * Postal adress:
26 | * Atoomweg 2
27 | * 1627 LE, Hoorn
28 | * the Netherlands
29 | */
30 |
31 | #include "UartWriteBuffer.h"
32 |
33 | #include
34 |
35 | void UartWriteBuffer::clear()
36 | {
37 | write_index_ = 0;
38 | }
39 |
40 | uint32_t UartWriteBuffer::get_size() const
41 | {
42 | return write_index_;
43 | }
44 |
45 | uint32_t UartWriteBuffer::get_max_size() const
46 | {
47 | return MAX_SIZE;
48 | }
49 |
50 | uint32_t UartWriteBuffer::get_available_size() const
51 | {
52 | return MAX_SIZE - write_index_;
53 | }
54 |
55 | bool UartWriteBuffer::push(const uint8_t byte)
56 | {
57 | bool return_value = MAX_SIZE > write_index_;
58 | if(return_value)
59 | {
60 | data_[write_index_] = byte;
61 | ++write_index_;
62 | }
63 | return return_value;
64 | }
65 |
66 | bool UartWriteBuffer::push(const uint8_t* bytes, const uint32_t length)
67 | {
68 | bool return_value = MAX_SIZE > (write_index_ + length);
69 | if(return_value)
70 | {
71 | memcpy(data_ + write_index_, bytes, length);
72 | write_index_ += length;
73 | }
74 | return return_value;
75 | }
76 |
77 | uint8_t* UartWriteBuffer::get_data()
78 | {
79 | return data_;
80 | }
81 |
--------------------------------------------------------------------------------
/nucleo-f446re/Core/Src/main.cpp:
--------------------------------------------------------------------------------
1 | /* USER CODE BEGIN Header */
2 | /**
3 | ******************************************************************************
4 | * @file : main.c
5 | * @brief : Main program body
6 | ******************************************************************************
7 | * @attention
8 | *
9 | * © Copyright (c) 2020 STMicroelectronics.
10 | * All rights reserved.
11 | *
12 | * This software component is licensed by ST under BSD 3-Clause license,
13 | * the "License"; You may not use this file except in compliance with the
14 | * License. You may obtain a copy of the License at:
15 | * opensource.org/licenses/BSD-3-Clause
16 | *
17 | ******************************************************************************
18 | */
19 | /* USER CODE END Header */
20 |
21 | /* Includes ------------------------------------------------------------------*/
22 | #include "main.h"
23 |
24 | /* Private includes ----------------------------------------------------------*/
25 | /* USER CODE BEGIN Includes */
26 | #include "uart_messages.h"
27 | #include "UartReadBuffer.h"
28 | #include "UartWriteBuffer.h"
29 | #include
30 | /* USER CODE END Includes */
31 |
32 | /* Private typedef -----------------------------------------------------------*/
33 | /* USER CODE BEGIN PTD */
34 |
35 | /* USER CODE END PTD */
36 |
37 | /* Private define ------------------------------------------------------------*/
38 | /* USER CODE BEGIN PD */
39 | /* USER CODE END PD */
40 |
41 | /* Private macro -------------------------------------------------------------*/
42 | /* USER CODE BEGIN PM */
43 |
44 | /* USER CODE END PM */
45 |
46 | /* Private variables ---------------------------------------------------------*/
47 | UART_HandleTypeDef huart2;
48 |
49 | /* USER CODE BEGIN PV */
50 | UartReadBuffer read_buffer;
51 | UartWriteBuffer write_buffer;
52 | HAL_StatusTypeDef receive_status;
53 | Command received_command;
54 | Reply outgoing_reply;
55 | /* USER CODE END PV */
56 |
57 | /* Private function prototypes -----------------------------------------------*/
58 | void SystemClock_Config(void);
59 | static void MX_GPIO_Init(void);
60 | static void MX_USART2_UART_Init(void);
61 | /* USER CODE BEGIN PFP */
62 |
63 | void process_command(const Command& command, Reply& reply);
64 |
65 | /* USER CODE END PFP */
66 |
67 | /* Private user code ---------------------------------------------------------*/
68 | /* USER CODE BEGIN 0 */
69 |
70 | /* USER CODE END 0 */
71 |
72 | /**
73 | * @brief The application entry point.
74 | * @retval int
75 | */
76 | int main(void)
77 | {
78 | /* USER CODE BEGIN 1 */
79 |
80 | /* USER CODE END 1 */
81 |
82 | /* MCU Configuration--------------------------------------------------------*/
83 |
84 | /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
85 | HAL_Init();
86 |
87 | /* USER CODE BEGIN Init */
88 |
89 | /* USER CODE END Init */
90 |
91 | /* Configure the system clock */
92 | SystemClock_Config();
93 |
94 | /* USER CODE BEGIN SysInit */
95 |
96 | /* USER CODE END SysInit */
97 |
98 | /* Initialize all configured peripherals */
99 | MX_GPIO_Init();
100 | MX_USART2_UART_Init();
101 | /* USER CODE BEGIN 2 */
102 |
103 | /* USER CODE END 2 */
104 |
105 | /* Infinite loop */
106 | /* USER CODE BEGIN WHILE */
107 | while (1)
108 | {
109 | /* USER CODE END WHILE */
110 |
111 | // Read the first byte from uart. The first byte indicates how many bytes will follow.
112 | uint8_t n_bytes = 0;
113 | receive_status = HAL_UART_Receive(&huart2, &n_bytes, 1, 100);
114 | if(HAL_OK == receive_status)
115 | {
116 | // Read the actual data to be deserialized.
117 | uint8_t byte;
118 | for(uint8_t i = 0; (i < n_bytes) && (HAL_OK == receive_status); ++i)
119 | {
120 | receive_status = HAL_UART_Receive(&huart2, &byte, 1, 100);
121 | read_buffer.push(byte);
122 | }
123 |
124 | if(HAL_OK == receive_status)
125 | {
126 | // Deserialize the data received.
127 | auto deserialize_status = received_command.deserialize(read_buffer);
128 | if(::EmbeddedProto::Error::NO_ERRORS == deserialize_status) {
129 | // Process the command.
130 | process_command(received_command, outgoing_reply);
131 | // Serialize the data.
132 | auto serialization_status = outgoing_reply.serialize(write_buffer);
133 | if(::EmbeddedProto::Error::NO_ERRORS == serialization_status)
134 | {
135 | // first transmit the number of bytes in the message.
136 | n_bytes = write_buffer.get_size();
137 | HAL_UART_Transmit(&huart2, &n_bytes, 1, 50);
138 | // Now transmit the actual data.
139 | HAL_UART_Transmit(&huart2, write_buffer.get_data(), write_buffer.get_size(), 50);
140 | }
141 | }
142 | // Clear the buffers after we are done.
143 | read_buffer.clear();
144 | write_buffer.clear();
145 |
146 | }
147 | }
148 |
149 | /* USER CODE BEGIN 3 */
150 | }
151 | /* USER CODE END 3 */
152 | }
153 |
154 | /**
155 | * @brief System Clock Configuration
156 | * @retval None
157 | */
158 | void SystemClock_Config(void)
159 | {
160 | RCC_OscInitTypeDef RCC_OscInitStruct = {0};
161 | RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
162 |
163 | /** Configure the main internal regulator output voltage
164 | */
165 | __HAL_RCC_PWR_CLK_ENABLE();
166 | __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE3);
167 | /** Initializes the CPU, AHB and APB busses clocks
168 | */
169 | RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
170 | RCC_OscInitStruct.HSIState = RCC_HSI_ON;
171 | RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
172 | RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
173 | RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
174 | RCC_OscInitStruct.PLL.PLLM = 16;
175 | RCC_OscInitStruct.PLL.PLLN = 336;
176 | RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV4;
177 | RCC_OscInitStruct.PLL.PLLQ = 2;
178 | RCC_OscInitStruct.PLL.PLLR = 2;
179 | if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
180 | {
181 | Error_Handler();
182 | }
183 | /** Initializes the CPU, AHB and APB busses clocks
184 | */
185 | RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
186 | |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
187 | RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
188 | RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
189 | RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
190 | RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
191 |
192 | if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK)
193 | {
194 | Error_Handler();
195 | }
196 | }
197 |
198 | /**
199 | * @brief USART2 Initialization Function
200 | * @param None
201 | * @retval None
202 | */
203 | static void MX_USART2_UART_Init(void)
204 | {
205 |
206 | /* USER CODE BEGIN USART2_Init 0 */
207 |
208 | /* USER CODE END USART2_Init 0 */
209 |
210 | /* USER CODE BEGIN USART2_Init 1 */
211 |
212 | /* USER CODE END USART2_Init 1 */
213 | huart2.Instance = USART2;
214 | huart2.Init.BaudRate = 115200;
215 | huart2.Init.WordLength = UART_WORDLENGTH_8B;
216 | huart2.Init.StopBits = UART_STOPBITS_1;
217 | huart2.Init.Parity = UART_PARITY_NONE;
218 | huart2.Init.Mode = UART_MODE_TX_RX;
219 | huart2.Init.HwFlowCtl = UART_HWCONTROL_NONE;
220 | huart2.Init.OverSampling = UART_OVERSAMPLING_16;
221 | if (HAL_UART_Init(&huart2) != HAL_OK)
222 | {
223 | Error_Handler();
224 | }
225 | /* USER CODE BEGIN USART2_Init 2 */
226 |
227 | /* USER CODE END USART2_Init 2 */
228 |
229 | }
230 |
231 | /**
232 | * @brief GPIO Initialization Function
233 | * @param None
234 | * @retval None
235 | */
236 | static void MX_GPIO_Init(void)
237 | {
238 | GPIO_InitTypeDef GPIO_InitStruct = {0};
239 |
240 | /* GPIO Ports Clock Enable */
241 | __HAL_RCC_GPIOC_CLK_ENABLE();
242 | __HAL_RCC_GPIOH_CLK_ENABLE();
243 | __HAL_RCC_GPIOA_CLK_ENABLE();
244 | __HAL_RCC_GPIOB_CLK_ENABLE();
245 |
246 | /*Configure GPIO pin Output Level */
247 | HAL_GPIO_WritePin(LD2_GPIO_Port, LD2_Pin, GPIO_PIN_RESET);
248 |
249 | /*Configure GPIO pin : B1_Pin */
250 | GPIO_InitStruct.Pin = B1_Pin;
251 | GPIO_InitStruct.Mode = GPIO_MODE_IT_FALLING;
252 | GPIO_InitStruct.Pull = GPIO_NOPULL;
253 | HAL_GPIO_Init(B1_GPIO_Port, &GPIO_InitStruct);
254 |
255 | /*Configure GPIO pin : LD2_Pin */
256 | GPIO_InitStruct.Pin = LD2_Pin;
257 | GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
258 | GPIO_InitStruct.Pull = GPIO_NOPULL;
259 | GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
260 | HAL_GPIO_Init(LD2_GPIO_Port, &GPIO_InitStruct);
261 |
262 | }
263 |
264 | /* USER CODE BEGIN 4 */
265 |
266 | //! The functions takes a command and responds to it.
267 | /*!
268 | * \param[in] command The received command.
269 | * \param[out] reply The reply to be send over uart.
270 | */
271 | void process_command(const Command& command, Reply& reply)
272 | {
273 | switch(command.get_button())
274 | {
275 | case Command::Buttons::Stop:
276 | // After we are done clear the current state.
277 | reply.clear();
278 | break;
279 |
280 | // With the following commands move the grappling hook.
281 |
282 | case Command::Buttons::Up:
283 | {
284 | auto new_y = reply.y_pos() + command.value();
285 | reply.set_y_pos(new_y);
286 | break;
287 | }
288 |
289 | case Command::Buttons::Down:
290 | {
291 | auto new_y = reply.y_pos() - command.value();
292 | reply.set_y_pos(new_y);
293 | break;
294 | }
295 |
296 | case Command::Buttons::Right:
297 | {
298 | auto new_x = reply.x_pos() + command.value();
299 | reply.set_x_pos(new_x);
300 | break;
301 | }
302 |
303 | case Command::Buttons::Left:
304 | {
305 | auto new_x = reply.x_pos() - command.value();
306 | reply.set_x_pos(new_x);
307 | break;
308 | }
309 |
310 | // Try to see if we have a winner.
311 | case Command::Buttons::Grab:
312 | {
313 | // You win on every even position
314 | auto remainder = (reply.x_pos() + reply.y_pos()) % 2;
315 | reply.set_price(0 == remainder);
316 | break;
317 | }
318 |
319 | default:
320 | // By default send back the current state.
321 | break;
322 | }
323 |
324 | }
325 |
326 |
327 | /* USER CODE END 4 */
328 |
329 | /**
330 | * @brief This function is executed in case of error occurrence.
331 | * @retval None
332 | */
333 | void Error_Handler(void)
334 | {
335 | /* USER CODE BEGIN Error_Handler_Debug */
336 | /* User can add his own implementation to report the HAL error return state */
337 |
338 | /* USER CODE END Error_Handler_Debug */
339 | }
340 |
341 | #ifdef USE_FULL_ASSERT
342 | /**
343 | * @brief Reports the name of the source file and the source line number
344 | * where the assert_param error has occurred.
345 | * @param file: pointer to the source file name
346 | * @param line: assert_param error line source number
347 | * @retval None
348 | */
349 | void assert_failed(uint8_t *file, uint32_t line)
350 | {
351 | /* USER CODE BEGIN 6 */
352 | /* User can add his own implementation to report the file name and line number,
353 | tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
354 | /* USER CODE END 6 */
355 | }
356 | #endif /* USE_FULL_ASSERT */
357 |
358 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
359 |
--------------------------------------------------------------------------------
/nucleo-f446re/Core/Src/stm32f4xx_hal_msp.c:
--------------------------------------------------------------------------------
1 | /* USER CODE BEGIN Header */
2 | /**
3 | ******************************************************************************
4 | * File Name : stm32f4xx_hal_msp.c
5 | * Description : This file provides code for the MSP Initialization
6 | * and de-Initialization codes.
7 | ******************************************************************************
8 | * @attention
9 | *
10 | * © Copyright (c) 2020 STMicroelectronics.
11 | * All rights reserved.
12 | *
13 | * This software component is licensed by ST under BSD 3-Clause license,
14 | * the "License"; You may not use this file except in compliance with the
15 | * License. You may obtain a copy of the License at:
16 | * opensource.org/licenses/BSD-3-Clause
17 | *
18 | ******************************************************************************
19 | */
20 | /* USER CODE END Header */
21 |
22 | /* Includes ------------------------------------------------------------------*/
23 | #include "main.h"
24 | /* USER CODE BEGIN Includes */
25 |
26 | /* USER CODE END Includes */
27 |
28 | /* Private typedef -----------------------------------------------------------*/
29 | /* USER CODE BEGIN TD */
30 |
31 | /* USER CODE END TD */
32 |
33 | /* Private define ------------------------------------------------------------*/
34 | /* USER CODE BEGIN Define */
35 |
36 | /* USER CODE END Define */
37 |
38 | /* Private macro -------------------------------------------------------------*/
39 | /* USER CODE BEGIN Macro */
40 |
41 | /* USER CODE END Macro */
42 |
43 | /* Private variables ---------------------------------------------------------*/
44 | /* USER CODE BEGIN PV */
45 |
46 | /* USER CODE END PV */
47 |
48 | /* Private function prototypes -----------------------------------------------*/
49 | /* USER CODE BEGIN PFP */
50 |
51 | /* USER CODE END PFP */
52 |
53 | /* External functions --------------------------------------------------------*/
54 | /* USER CODE BEGIN ExternalFunctions */
55 |
56 | /* USER CODE END ExternalFunctions */
57 |
58 | /* USER CODE BEGIN 0 */
59 |
60 | /* USER CODE END 0 */
61 | /**
62 | * Initializes the Global MSP.
63 | */
64 | void HAL_MspInit(void)
65 | {
66 | /* USER CODE BEGIN MspInit 0 */
67 |
68 | /* USER CODE END MspInit 0 */
69 |
70 | __HAL_RCC_SYSCFG_CLK_ENABLE();
71 | __HAL_RCC_PWR_CLK_ENABLE();
72 |
73 | HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_0);
74 |
75 | /* System interrupt init*/
76 |
77 | /* USER CODE BEGIN MspInit 1 */
78 |
79 | /* USER CODE END MspInit 1 */
80 | }
81 |
82 | /**
83 | * @brief UART MSP Initialization
84 | * This function configures the hardware resources used in this example
85 | * @param huart: UART handle pointer
86 | * @retval None
87 | */
88 | void HAL_UART_MspInit(UART_HandleTypeDef* huart)
89 | {
90 | GPIO_InitTypeDef GPIO_InitStruct = {0};
91 | if(huart->Instance==USART2)
92 | {
93 | /* USER CODE BEGIN USART2_MspInit 0 */
94 |
95 | /* USER CODE END USART2_MspInit 0 */
96 | /* Peripheral clock enable */
97 | __HAL_RCC_USART2_CLK_ENABLE();
98 |
99 | __HAL_RCC_GPIOA_CLK_ENABLE();
100 | /**USART2 GPIO Configuration
101 | PA2 ------> USART2_TX
102 | PA3 ------> USART2_RX
103 | */
104 | GPIO_InitStruct.Pin = USART_TX_Pin|USART_RX_Pin;
105 | GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
106 | GPIO_InitStruct.Pull = GPIO_NOPULL;
107 | GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
108 | GPIO_InitStruct.Alternate = GPIO_AF7_USART2;
109 | HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
110 |
111 | /* USER CODE BEGIN USART2_MspInit 1 */
112 |
113 | /* USER CODE END USART2_MspInit 1 */
114 | }
115 |
116 | }
117 |
118 | /**
119 | * @brief UART MSP De-Initialization
120 | * This function freeze the hardware resources used in this example
121 | * @param huart: UART handle pointer
122 | * @retval None
123 | */
124 | void HAL_UART_MspDeInit(UART_HandleTypeDef* huart)
125 | {
126 | if(huart->Instance==USART2)
127 | {
128 | /* USER CODE BEGIN USART2_MspDeInit 0 */
129 |
130 | /* USER CODE END USART2_MspDeInit 0 */
131 | /* Peripheral clock disable */
132 | __HAL_RCC_USART2_CLK_DISABLE();
133 |
134 | /**USART2 GPIO Configuration
135 | PA2 ------> USART2_TX
136 | PA3 ------> USART2_RX
137 | */
138 | HAL_GPIO_DeInit(GPIOA, USART_TX_Pin|USART_RX_Pin);
139 |
140 | /* USER CODE BEGIN USART2_MspDeInit 1 */
141 |
142 | /* USER CODE END USART2_MspDeInit 1 */
143 | }
144 |
145 | }
146 |
147 | /* USER CODE BEGIN 1 */
148 |
149 | /* USER CODE END 1 */
150 |
151 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
152 |
--------------------------------------------------------------------------------
/nucleo-f446re/Core/Src/stm32f4xx_it.c:
--------------------------------------------------------------------------------
1 | /* USER CODE BEGIN Header */
2 | /**
3 | ******************************************************************************
4 | * @file stm32f4xx_it.c
5 | * @brief Interrupt Service Routines.
6 | ******************************************************************************
7 | * @attention
8 | *
9 | * © Copyright (c) 2020 STMicroelectronics.
10 | * All rights reserved.
11 | *
12 | * This software component is licensed by ST under BSD 3-Clause license,
13 | * the "License"; You may not use this file except in compliance with the
14 | * License. You may obtain a copy of the License at:
15 | * opensource.org/licenses/BSD-3-Clause
16 | *
17 | ******************************************************************************
18 | */
19 | /* USER CODE END Header */
20 |
21 | /* Includes ------------------------------------------------------------------*/
22 | #include "main.h"
23 | #include "stm32f4xx_it.h"
24 | /* Private includes ----------------------------------------------------------*/
25 | /* USER CODE BEGIN Includes */
26 | /* USER CODE END Includes */
27 |
28 | /* Private typedef -----------------------------------------------------------*/
29 | /* USER CODE BEGIN TD */
30 |
31 | /* USER CODE END TD */
32 |
33 | /* Private define ------------------------------------------------------------*/
34 | /* USER CODE BEGIN PD */
35 |
36 | /* USER CODE END PD */
37 |
38 | /* Private macro -------------------------------------------------------------*/
39 | /* USER CODE BEGIN PM */
40 |
41 | /* USER CODE END PM */
42 |
43 | /* Private variables ---------------------------------------------------------*/
44 | /* USER CODE BEGIN PV */
45 |
46 | /* USER CODE END PV */
47 |
48 | /* Private function prototypes -----------------------------------------------*/
49 | /* USER CODE BEGIN PFP */
50 |
51 | /* USER CODE END PFP */
52 |
53 | /* Private user code ---------------------------------------------------------*/
54 | /* USER CODE BEGIN 0 */
55 |
56 | /* USER CODE END 0 */
57 |
58 | /* External variables --------------------------------------------------------*/
59 |
60 | /* USER CODE BEGIN EV */
61 |
62 | /* USER CODE END EV */
63 |
64 | /******************************************************************************/
65 | /* Cortex-M4 Processor Interruption and Exception Handlers */
66 | /******************************************************************************/
67 | /**
68 | * @brief This function handles Non maskable interrupt.
69 | */
70 | void NMI_Handler(void)
71 | {
72 | /* USER CODE BEGIN NonMaskableInt_IRQn 0 */
73 |
74 | /* USER CODE END NonMaskableInt_IRQn 0 */
75 | /* USER CODE BEGIN NonMaskableInt_IRQn 1 */
76 |
77 | /* USER CODE END NonMaskableInt_IRQn 1 */
78 | }
79 |
80 | /**
81 | * @brief This function handles Hard fault interrupt.
82 | */
83 | void HardFault_Handler(void)
84 | {
85 | /* USER CODE BEGIN HardFault_IRQn 0 */
86 |
87 | /* USER CODE END HardFault_IRQn 0 */
88 | while (1)
89 | {
90 | /* USER CODE BEGIN W1_HardFault_IRQn 0 */
91 | /* USER CODE END W1_HardFault_IRQn 0 */
92 | }
93 | }
94 |
95 | /**
96 | * @brief This function handles Memory management fault.
97 | */
98 | void MemManage_Handler(void)
99 | {
100 | /* USER CODE BEGIN MemoryManagement_IRQn 0 */
101 |
102 | /* USER CODE END MemoryManagement_IRQn 0 */
103 | while (1)
104 | {
105 | /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */
106 | /* USER CODE END W1_MemoryManagement_IRQn 0 */
107 | }
108 | }
109 |
110 | /**
111 | * @brief This function handles Pre-fetch fault, memory access fault.
112 | */
113 | void BusFault_Handler(void)
114 | {
115 | /* USER CODE BEGIN BusFault_IRQn 0 */
116 |
117 | /* USER CODE END BusFault_IRQn 0 */
118 | while (1)
119 | {
120 | /* USER CODE BEGIN W1_BusFault_IRQn 0 */
121 | /* USER CODE END W1_BusFault_IRQn 0 */
122 | }
123 | }
124 |
125 | /**
126 | * @brief This function handles Undefined instruction or illegal state.
127 | */
128 | void UsageFault_Handler(void)
129 | {
130 | /* USER CODE BEGIN UsageFault_IRQn 0 */
131 |
132 | /* USER CODE END UsageFault_IRQn 0 */
133 | while (1)
134 | {
135 | /* USER CODE BEGIN W1_UsageFault_IRQn 0 */
136 | /* USER CODE END W1_UsageFault_IRQn 0 */
137 | }
138 | }
139 |
140 | /**
141 | * @brief This function handles System service call via SWI instruction.
142 | */
143 | void SVC_Handler(void)
144 | {
145 | /* USER CODE BEGIN SVCall_IRQn 0 */
146 |
147 | /* USER CODE END SVCall_IRQn 0 */
148 | /* USER CODE BEGIN SVCall_IRQn 1 */
149 |
150 | /* USER CODE END SVCall_IRQn 1 */
151 | }
152 |
153 | /**
154 | * @brief This function handles Debug monitor.
155 | */
156 | void DebugMon_Handler(void)
157 | {
158 | /* USER CODE BEGIN DebugMonitor_IRQn 0 */
159 |
160 | /* USER CODE END DebugMonitor_IRQn 0 */
161 | /* USER CODE BEGIN DebugMonitor_IRQn 1 */
162 |
163 | /* USER CODE END DebugMonitor_IRQn 1 */
164 | }
165 |
166 | /**
167 | * @brief This function handles Pendable request for system service.
168 | */
169 | void PendSV_Handler(void)
170 | {
171 | /* USER CODE BEGIN PendSV_IRQn 0 */
172 |
173 | /* USER CODE END PendSV_IRQn 0 */
174 | /* USER CODE BEGIN PendSV_IRQn 1 */
175 |
176 | /* USER CODE END PendSV_IRQn 1 */
177 | }
178 |
179 | /**
180 | * @brief This function handles System tick timer.
181 | */
182 | void SysTick_Handler(void)
183 | {
184 | /* USER CODE BEGIN SysTick_IRQn 0 */
185 |
186 | /* USER CODE END SysTick_IRQn 0 */
187 | HAL_IncTick();
188 | /* USER CODE BEGIN SysTick_IRQn 1 */
189 |
190 | /* USER CODE END SysTick_IRQn 1 */
191 | }
192 |
193 | /******************************************************************************/
194 | /* STM32F4xx Peripheral Interrupt Handlers */
195 | /* Add here the Interrupt Handlers for the used peripherals. */
196 | /* For the available peripheral interrupt handler names, */
197 | /* please refer to the startup file (startup_stm32f4xx.s). */
198 | /******************************************************************************/
199 |
200 | /* USER CODE BEGIN 1 */
201 |
202 | /* USER CODE END 1 */
203 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
204 |
--------------------------------------------------------------------------------
/nucleo-f446re/Core/Src/syscalls.c:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file syscalls.c
4 | * @author Auto-generated by STM32CubeIDE
5 | * @brief STM32CubeIDE Minimal System calls file
6 | *
7 | * For more information about which c-functions
8 | * need which of these lowlevel functions
9 | * please consult the Newlib libc-manual
10 | ******************************************************************************
11 | * @attention
12 | *
13 | * © Copyright (c) 2020 STMicroelectronics.
14 | * All rights reserved.
15 | *
16 | * This software component is licensed by ST under BSD 3-Clause license,
17 | * the "License"; You may not use this file except in compliance with the
18 | * License. You may obtain a copy of the License at:
19 | * opensource.org/licenses/BSD-3-Clause
20 | *
21 | ******************************************************************************
22 | */
23 |
24 | /* Includes */
25 | #include
26 | #include
27 | #include
28 | #include
29 | #include
30 | #include
31 | #include
32 | #include
33 |
34 |
35 | /* Variables */
36 | //#undef errno
37 | extern int errno;
38 | extern int __io_putchar(int ch) __attribute__((weak));
39 | extern int __io_getchar(void) __attribute__((weak));
40 |
41 | register char * stack_ptr asm("sp");
42 |
43 | char *__env[1] = { 0 };
44 | char **environ = __env;
45 |
46 |
47 | /* Functions */
48 | void initialise_monitor_handles()
49 | {
50 | }
51 |
52 | int _getpid(void)
53 | {
54 | return 1;
55 | }
56 |
57 | int _kill(int pid, int sig)
58 | {
59 | errno = EINVAL;
60 | return -1;
61 | }
62 |
63 | void _exit (int status)
64 | {
65 | _kill(status, -1);
66 | while (1) {} /* Make sure we hang here */
67 | }
68 |
69 | __attribute__((weak)) int _read(int file, char *ptr, int len)
70 | {
71 | int DataIdx;
72 |
73 | for (DataIdx = 0; DataIdx < len; DataIdx++)
74 | {
75 | *ptr++ = __io_getchar();
76 | }
77 |
78 | return len;
79 | }
80 |
81 | __attribute__((weak)) int _write(int file, char *ptr, int len)
82 | {
83 | int DataIdx;
84 |
85 | for (DataIdx = 0; DataIdx < len; DataIdx++)
86 | {
87 | __io_putchar(*ptr++);
88 | }
89 | return len;
90 | }
91 |
92 | int _close(int file)
93 | {
94 | return -1;
95 | }
96 |
97 |
98 | int _fstat(int file, struct stat *st)
99 | {
100 | st->st_mode = S_IFCHR;
101 | return 0;
102 | }
103 |
104 | int _isatty(int file)
105 | {
106 | return 1;
107 | }
108 |
109 | int _lseek(int file, int ptr, int dir)
110 | {
111 | return 0;
112 | }
113 |
114 | int _open(char *path, int flags, ...)
115 | {
116 | /* Pretend like we always fail */
117 | return -1;
118 | }
119 |
120 | int _wait(int *status)
121 | {
122 | errno = ECHILD;
123 | return -1;
124 | }
125 |
126 | int _unlink(char *name)
127 | {
128 | errno = ENOENT;
129 | return -1;
130 | }
131 |
132 | int _times(struct tms *buf)
133 | {
134 | return -1;
135 | }
136 |
137 | int _stat(char *file, struct stat *st)
138 | {
139 | st->st_mode = S_IFCHR;
140 | return 0;
141 | }
142 |
143 | int _link(char *old, char *new)
144 | {
145 | errno = EMLINK;
146 | return -1;
147 | }
148 |
149 | int _fork(void)
150 | {
151 | errno = EAGAIN;
152 | return -1;
153 | }
154 |
155 | int _execve(char *name, char **argv, char **env)
156 | {
157 | errno = ENOMEM;
158 | return -1;
159 | }
160 |
--------------------------------------------------------------------------------
/nucleo-f446re/Core/Src/sysmem.c:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file sysmem.c
4 | * @author Auto-generated by STM32CubeIDE
5 | * @brief STM32CubeIDE Minimal System Memory calls file
6 | *
7 | * For more information about which c-functions
8 | * need which of these lowlevel functions
9 | * please consult the Newlib libc-manual
10 | ******************************************************************************
11 | * @attention
12 | *
13 | * © Copyright (c) 2020 STMicroelectronics.
14 | * All rights reserved.
15 | *
16 | * This software component is licensed by ST under BSD 3-Clause license,
17 | * the "License"; You may not use this file except in compliance with the
18 | * License. You may obtain a copy of the License at:
19 | * opensource.org/licenses/BSD-3-Clause
20 | *
21 | ******************************************************************************
22 | */
23 |
24 | /* Includes */
25 | #include
26 | #include
27 |
28 | /* Variables */
29 | extern int errno;
30 | register char * stack_ptr asm("sp");
31 |
32 | /* Functions */
33 |
34 | /**
35 | _sbrk
36 | Increase program data space. Malloc and related functions depend on this
37 | **/
38 | caddr_t _sbrk(int incr)
39 | {
40 | extern char end asm("end");
41 | static char *heap_end;
42 | char *prev_heap_end;
43 |
44 | if (heap_end == 0)
45 | heap_end = &end;
46 |
47 | prev_heap_end = heap_end;
48 | if (heap_end + incr > stack_ptr)
49 | {
50 | errno = ENOMEM;
51 | return (caddr_t) -1;
52 | }
53 |
54 | heap_end += incr;
55 |
56 | return (caddr_t) prev_heap_end;
57 | }
58 |
59 |
--------------------------------------------------------------------------------
/nucleo-f446re/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h:
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https://raw.githubusercontent.com/Embedded-AMS/EmbeddedProto_Example_STM32_UART/e112fc203cfe4eab70e14064114c4418bbcf9c71/nucleo-f446re/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h
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/nucleo-f446re/Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file system_stm32f4xx.h
4 | * @author MCD Application Team
5 | * @brief CMSIS Cortex-M4 Device System Source File for STM32F4xx devices.
6 | ******************************************************************************
7 | * @attention
8 | *
9 | * © COPYRIGHT(c) 2017 STMicroelectronics
10 | *
11 | * Redistribution and use in source and binary forms, with or without modification,
12 | * are permitted provided that the following conditions are met:
13 | * 1. Redistributions of source code must retain the above copyright notice,
14 | * this list of conditions and the following disclaimer.
15 | * 2. Redistributions in binary form must reproduce the above copyright notice,
16 | * this list of conditions and the following disclaimer in the documentation
17 | * and/or other materials provided with the distribution.
18 | * 3. Neither the name of STMicroelectronics nor the names of its contributors
19 | * may be used to endorse or promote products derived from this software
20 | * without specific prior written permission.
21 | *
22 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
23 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
25 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
26 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
27 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
28 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
29 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
30 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 | *
33 | ******************************************************************************
34 | */
35 |
36 | /** @addtogroup CMSIS
37 | * @{
38 | */
39 |
40 | /** @addtogroup stm32f4xx_system
41 | * @{
42 | */
43 |
44 | /**
45 | * @brief Define to prevent recursive inclusion
46 | */
47 | #ifndef __SYSTEM_STM32F4XX_H
48 | #define __SYSTEM_STM32F4XX_H
49 |
50 | #ifdef __cplusplus
51 | extern "C" {
52 | #endif
53 |
54 | /** @addtogroup STM32F4xx_System_Includes
55 | * @{
56 | */
57 |
58 | /**
59 | * @}
60 | */
61 |
62 |
63 | /** @addtogroup STM32F4xx_System_Exported_types
64 | * @{
65 | */
66 | /* This variable is updated in three ways:
67 | 1) by calling CMSIS function SystemCoreClockUpdate()
68 | 2) by calling HAL API function HAL_RCC_GetSysClockFreq()
69 | 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
70 | Note: If you use this function to configure the system clock; then there
71 | is no need to call the 2 first functions listed above, since SystemCoreClock
72 | variable is updated automatically.
73 | */
74 | extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
75 |
76 | extern const uint8_t AHBPrescTable[16]; /*!< AHB prescalers table values */
77 | extern const uint8_t APBPrescTable[8]; /*!< APB prescalers table values */
78 |
79 | /**
80 | * @}
81 | */
82 |
83 | /** @addtogroup STM32F4xx_System_Exported_Constants
84 | * @{
85 | */
86 |
87 | /**
88 | * @}
89 | */
90 |
91 | /** @addtogroup STM32F4xx_System_Exported_Macros
92 | * @{
93 | */
94 |
95 | /**
96 | * @}
97 | */
98 |
99 | /** @addtogroup STM32F4xx_System_Exported_Functions
100 | * @{
101 | */
102 |
103 | extern void SystemInit(void);
104 | extern void SystemCoreClockUpdate(void);
105 | /**
106 | * @}
107 | */
108 |
109 | #ifdef __cplusplus
110 | }
111 | #endif
112 |
113 | #endif /*__SYSTEM_STM32F4XX_H */
114 |
115 | /**
116 | * @}
117 | */
118 |
119 | /**
120 | * @}
121 | */
122 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
123 |
--------------------------------------------------------------------------------
/nucleo-f446re/Drivers/CMSIS/Include/cmsis_compiler.h:
--------------------------------------------------------------------------------
1 | /**************************************************************************//**
2 | * @file cmsis_compiler.h
3 | * @brief CMSIS compiler generic header file
4 | * @version V5.0.4
5 | * @date 10. January 2018
6 | ******************************************************************************/
7 | /*
8 | * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
9 | *
10 | * SPDX-License-Identifier: Apache-2.0
11 | *
12 | * Licensed under the Apache License, Version 2.0 (the License); you may
13 | * not use this file except in compliance with the License.
14 | * You may obtain a copy of the License at
15 | *
16 | * www.apache.org/licenses/LICENSE-2.0
17 | *
18 | * Unless required by applicable law or agreed to in writing, software
19 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT
20 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
21 | * See the License for the specific language governing permissions and
22 | * limitations under the License.
23 | */
24 |
25 | #ifndef __CMSIS_COMPILER_H
26 | #define __CMSIS_COMPILER_H
27 |
28 | #include
29 |
30 | /*
31 | * Arm Compiler 4/5
32 | */
33 | #if defined ( __CC_ARM )
34 | #include "cmsis_armcc.h"
35 |
36 |
37 | /*
38 | * Arm Compiler 6 (armclang)
39 | */
40 | #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
41 | #include "cmsis_armclang.h"
42 |
43 |
44 | /*
45 | * GNU Compiler
46 | */
47 | #elif defined ( __GNUC__ )
48 | #include "cmsis_gcc.h"
49 |
50 |
51 | /*
52 | * IAR Compiler
53 | */
54 | #elif defined ( __ICCARM__ )
55 | #include
56 |
57 |
58 | /*
59 | * TI Arm Compiler
60 | */
61 | #elif defined ( __TI_ARM__ )
62 | #include
63 |
64 | #ifndef __ASM
65 | #define __ASM __asm
66 | #endif
67 | #ifndef __INLINE
68 | #define __INLINE inline
69 | #endif
70 | #ifndef __STATIC_INLINE
71 | #define __STATIC_INLINE static inline
72 | #endif
73 | #ifndef __STATIC_FORCEINLINE
74 | #define __STATIC_FORCEINLINE __STATIC_INLINE
75 | #endif
76 | #ifndef __NO_RETURN
77 | #define __NO_RETURN __attribute__((noreturn))
78 | #endif
79 | #ifndef __USED
80 | #define __USED __attribute__((used))
81 | #endif
82 | #ifndef __WEAK
83 | #define __WEAK __attribute__((weak))
84 | #endif
85 | #ifndef __PACKED
86 | #define __PACKED __attribute__((packed))
87 | #endif
88 | #ifndef __PACKED_STRUCT
89 | #define __PACKED_STRUCT struct __attribute__((packed))
90 | #endif
91 | #ifndef __PACKED_UNION
92 | #define __PACKED_UNION union __attribute__((packed))
93 | #endif
94 | #ifndef __UNALIGNED_UINT32 /* deprecated */
95 | struct __attribute__((packed)) T_UINT32 { uint32_t v; };
96 | #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
97 | #endif
98 | #ifndef __UNALIGNED_UINT16_WRITE
99 | __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
100 | #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
101 | #endif
102 | #ifndef __UNALIGNED_UINT16_READ
103 | __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
104 | #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
105 | #endif
106 | #ifndef __UNALIGNED_UINT32_WRITE
107 | __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
108 | #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
109 | #endif
110 | #ifndef __UNALIGNED_UINT32_READ
111 | __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
112 | #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
113 | #endif
114 | #ifndef __ALIGNED
115 | #define __ALIGNED(x) __attribute__((aligned(x)))
116 | #endif
117 | #ifndef __RESTRICT
118 | #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
119 | #define __RESTRICT
120 | #endif
121 |
122 |
123 | /*
124 | * TASKING Compiler
125 | */
126 | #elif defined ( __TASKING__ )
127 | /*
128 | * The CMSIS functions have been implemented as intrinsics in the compiler.
129 | * Please use "carm -?i" to get an up to date list of all intrinsics,
130 | * Including the CMSIS ones.
131 | */
132 |
133 | #ifndef __ASM
134 | #define __ASM __asm
135 | #endif
136 | #ifndef __INLINE
137 | #define __INLINE inline
138 | #endif
139 | #ifndef __STATIC_INLINE
140 | #define __STATIC_INLINE static inline
141 | #endif
142 | #ifndef __STATIC_FORCEINLINE
143 | #define __STATIC_FORCEINLINE __STATIC_INLINE
144 | #endif
145 | #ifndef __NO_RETURN
146 | #define __NO_RETURN __attribute__((noreturn))
147 | #endif
148 | #ifndef __USED
149 | #define __USED __attribute__((used))
150 | #endif
151 | #ifndef __WEAK
152 | #define __WEAK __attribute__((weak))
153 | #endif
154 | #ifndef __PACKED
155 | #define __PACKED __packed__
156 | #endif
157 | #ifndef __PACKED_STRUCT
158 | #define __PACKED_STRUCT struct __packed__
159 | #endif
160 | #ifndef __PACKED_UNION
161 | #define __PACKED_UNION union __packed__
162 | #endif
163 | #ifndef __UNALIGNED_UINT32 /* deprecated */
164 | struct __packed__ T_UINT32 { uint32_t v; };
165 | #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
166 | #endif
167 | #ifndef __UNALIGNED_UINT16_WRITE
168 | __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
169 | #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
170 | #endif
171 | #ifndef __UNALIGNED_UINT16_READ
172 | __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
173 | #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
174 | #endif
175 | #ifndef __UNALIGNED_UINT32_WRITE
176 | __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
177 | #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
178 | #endif
179 | #ifndef __UNALIGNED_UINT32_READ
180 | __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
181 | #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
182 | #endif
183 | #ifndef __ALIGNED
184 | #define __ALIGNED(x) __align(x)
185 | #endif
186 | #ifndef __RESTRICT
187 | #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
188 | #define __RESTRICT
189 | #endif
190 |
191 |
192 | /*
193 | * COSMIC Compiler
194 | */
195 | #elif defined ( __CSMC__ )
196 | #include
197 |
198 | #ifndef __ASM
199 | #define __ASM _asm
200 | #endif
201 | #ifndef __INLINE
202 | #define __INLINE inline
203 | #endif
204 | #ifndef __STATIC_INLINE
205 | #define __STATIC_INLINE static inline
206 | #endif
207 | #ifndef __STATIC_FORCEINLINE
208 | #define __STATIC_FORCEINLINE __STATIC_INLINE
209 | #endif
210 | #ifndef __NO_RETURN
211 | // NO RETURN is automatically detected hence no warning here
212 | #define __NO_RETURN
213 | #endif
214 | #ifndef __USED
215 | #warning No compiler specific solution for __USED. __USED is ignored.
216 | #define __USED
217 | #endif
218 | #ifndef __WEAK
219 | #define __WEAK __weak
220 | #endif
221 | #ifndef __PACKED
222 | #define __PACKED @packed
223 | #endif
224 | #ifndef __PACKED_STRUCT
225 | #define __PACKED_STRUCT @packed struct
226 | #endif
227 | #ifndef __PACKED_UNION
228 | #define __PACKED_UNION @packed union
229 | #endif
230 | #ifndef __UNALIGNED_UINT32 /* deprecated */
231 | @packed struct T_UINT32 { uint32_t v; };
232 | #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
233 | #endif
234 | #ifndef __UNALIGNED_UINT16_WRITE
235 | __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
236 | #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
237 | #endif
238 | #ifndef __UNALIGNED_UINT16_READ
239 | __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
240 | #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
241 | #endif
242 | #ifndef __UNALIGNED_UINT32_WRITE
243 | __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
244 | #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
245 | #endif
246 | #ifndef __UNALIGNED_UINT32_READ
247 | __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
248 | #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
249 | #endif
250 | #ifndef __ALIGNED
251 | #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
252 | #define __ALIGNED(x)
253 | #endif
254 | #ifndef __RESTRICT
255 | #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
256 | #define __RESTRICT
257 | #endif
258 |
259 |
260 | #else
261 | #error Unknown compiler.
262 | #endif
263 |
264 |
265 | #endif /* __CMSIS_COMPILER_H */
266 |
267 |
--------------------------------------------------------------------------------
/nucleo-f446re/Drivers/CMSIS/Include/cmsis_version.h:
--------------------------------------------------------------------------------
1 | /**************************************************************************//**
2 | * @file cmsis_version.h
3 | * @brief CMSIS Core(M) Version definitions
4 | * @version V5.0.2
5 | * @date 19. April 2017
6 | ******************************************************************************/
7 | /*
8 | * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
9 | *
10 | * SPDX-License-Identifier: Apache-2.0
11 | *
12 | * Licensed under the Apache License, Version 2.0 (the License); you may
13 | * not use this file except in compliance with the License.
14 | * You may obtain a copy of the License at
15 | *
16 | * www.apache.org/licenses/LICENSE-2.0
17 | *
18 | * Unless required by applicable law or agreed to in writing, software
19 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT
20 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
21 | * See the License for the specific language governing permissions and
22 | * limitations under the License.
23 | */
24 |
25 | #if defined ( __ICCARM__ )
26 | #pragma system_include /* treat file as system include file for MISRA check */
27 | #elif defined (__clang__)
28 | #pragma clang system_header /* treat file as system include file */
29 | #endif
30 |
31 | #ifndef __CMSIS_VERSION_H
32 | #define __CMSIS_VERSION_H
33 |
34 | /* CMSIS Version definitions */
35 | #define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */
36 | #define __CM_CMSIS_VERSION_SUB ( 1U) /*!< [15:0] CMSIS Core(M) sub version */
37 | #define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \
38 | __CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */
39 | #endif
40 |
--------------------------------------------------------------------------------
/nucleo-f446re/Drivers/CMSIS/Include/mpu_armv7.h:
--------------------------------------------------------------------------------
1 | /******************************************************************************
2 | * @file mpu_armv7.h
3 | * @brief CMSIS MPU API for Armv7-M MPU
4 | * @version V5.0.4
5 | * @date 10. January 2018
6 | ******************************************************************************/
7 | /*
8 | * Copyright (c) 2017-2018 Arm Limited. All rights reserved.
9 | *
10 | * SPDX-License-Identifier: Apache-2.0
11 | *
12 | * Licensed under the Apache License, Version 2.0 (the License); you may
13 | * not use this file except in compliance with the License.
14 | * You may obtain a copy of the License at
15 | *
16 | * www.apache.org/licenses/LICENSE-2.0
17 | *
18 | * Unless required by applicable law or agreed to in writing, software
19 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT
20 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
21 | * See the License for the specific language governing permissions and
22 | * limitations under the License.
23 | */
24 |
25 | #if defined ( __ICCARM__ )
26 | #pragma system_include /* treat file as system include file for MISRA check */
27 | #elif defined (__clang__)
28 | #pragma clang system_header /* treat file as system include file */
29 | #endif
30 |
31 | #ifndef ARM_MPU_ARMV7_H
32 | #define ARM_MPU_ARMV7_H
33 |
34 | #define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes
35 | #define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes
36 | #define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes
37 | #define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes
38 | #define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes
39 | #define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte
40 | #define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes
41 | #define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes
42 | #define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes
43 | #define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes
44 | #define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes
45 | #define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes
46 | #define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes
47 | #define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes
48 | #define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes
49 | #define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte
50 | #define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes
51 | #define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes
52 | #define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes
53 | #define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes
54 | #define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes
55 | #define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes
56 | #define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes
57 | #define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes
58 | #define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes
59 | #define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte
60 | #define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes
61 | #define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes
62 |
63 | #define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access
64 | #define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only
65 | #define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only
66 | #define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access
67 | #define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only
68 | #define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access
69 |
70 | /** MPU Region Base Address Register Value
71 | *
72 | * \param Region The region to be configured, number 0 to 15.
73 | * \param BaseAddress The base address for the region.
74 | */
75 | #define ARM_MPU_RBAR(Region, BaseAddress) \
76 | (((BaseAddress) & MPU_RBAR_ADDR_Msk) | \
77 | ((Region) & MPU_RBAR_REGION_Msk) | \
78 | (MPU_RBAR_VALID_Msk))
79 |
80 | /**
81 | * MPU Memory Access Attributes
82 | *
83 | * \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
84 | * \param IsShareable Region is shareable between multiple bus masters.
85 | * \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
86 | * \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
87 | */
88 | #define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \
89 | ((((TypeExtField ) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \
90 | (((IsShareable ) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \
91 | (((IsCacheable ) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \
92 | (((IsBufferable ) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk))
93 |
94 | /**
95 | * MPU Region Attribute and Size Register Value
96 | *
97 | * \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
98 | * \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
99 | * \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_.
100 | * \param SubRegionDisable Sub-region disable field.
101 | * \param Size Region size of the region to be configured, for example 4K, 8K.
102 | */
103 | #define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \
104 | ((((DisableExec ) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \
105 | (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \
106 | (((AccessAttributes) ) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk)))
107 |
108 | /**
109 | * MPU Region Attribute and Size Register Value
110 | *
111 | * \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
112 | * \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
113 | * \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
114 | * \param IsShareable Region is shareable between multiple bus masters.
115 | * \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
116 | * \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
117 | * \param SubRegionDisable Sub-region disable field.
118 | * \param Size Region size of the region to be configured, for example 4K, 8K.
119 | */
120 | #define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \
121 | ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size)
122 |
123 | /**
124 | * MPU Memory Access Attribute for strongly ordered memory.
125 | * - TEX: 000b
126 | * - Shareable
127 | * - Non-cacheable
128 | * - Non-bufferable
129 | */
130 | #define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U)
131 |
132 | /**
133 | * MPU Memory Access Attribute for device memory.
134 | * - TEX: 000b (if non-shareable) or 010b (if shareable)
135 | * - Shareable or non-shareable
136 | * - Non-cacheable
137 | * - Bufferable (if shareable) or non-bufferable (if non-shareable)
138 | *
139 | * \param IsShareable Configures the device memory as shareable or non-shareable.
140 | */
141 | #define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U))
142 |
143 | /**
144 | * MPU Memory Access Attribute for normal memory.
145 | * - TEX: 1BBb (reflecting outer cacheability rules)
146 | * - Shareable or non-shareable
147 | * - Cacheable or non-cacheable (reflecting inner cacheability rules)
148 | * - Bufferable or non-bufferable (reflecting inner cacheability rules)
149 | *
150 | * \param OuterCp Configures the outer cache policy.
151 | * \param InnerCp Configures the inner cache policy.
152 | * \param IsShareable Configures the memory as shareable or non-shareable.
153 | */
154 | #define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) & 2U), ((InnerCp) & 1U))
155 |
156 | /**
157 | * MPU Memory Access Attribute non-cacheable policy.
158 | */
159 | #define ARM_MPU_CACHEP_NOCACHE 0U
160 |
161 | /**
162 | * MPU Memory Access Attribute write-back, write and read allocate policy.
163 | */
164 | #define ARM_MPU_CACHEP_WB_WRA 1U
165 |
166 | /**
167 | * MPU Memory Access Attribute write-through, no write allocate policy.
168 | */
169 | #define ARM_MPU_CACHEP_WT_NWA 2U
170 |
171 | /**
172 | * MPU Memory Access Attribute write-back, no write allocate policy.
173 | */
174 | #define ARM_MPU_CACHEP_WB_NWA 3U
175 |
176 |
177 | /**
178 | * Struct for a single MPU Region
179 | */
180 | typedef struct {
181 | uint32_t RBAR; //!< The region base address register value (RBAR)
182 | uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR
183 | } ARM_MPU_Region_t;
184 |
185 | /** Enable the MPU.
186 | * \param MPU_Control Default access permissions for unconfigured regions.
187 | */
188 | __STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
189 | {
190 | __DSB();
191 | __ISB();
192 | MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
193 | #ifdef SCB_SHCSR_MEMFAULTENA_Msk
194 | SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
195 | #endif
196 | }
197 |
198 | /** Disable the MPU.
199 | */
200 | __STATIC_INLINE void ARM_MPU_Disable(void)
201 | {
202 | __DSB();
203 | __ISB();
204 | #ifdef SCB_SHCSR_MEMFAULTENA_Msk
205 | SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
206 | #endif
207 | MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
208 | }
209 |
210 | /** Clear and disable the given MPU region.
211 | * \param rnr Region number to be cleared.
212 | */
213 | __STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
214 | {
215 | MPU->RNR = rnr;
216 | MPU->RASR = 0U;
217 | }
218 |
219 | /** Configure an MPU region.
220 | * \param rbar Value for RBAR register.
221 | * \param rsar Value for RSAR register.
222 | */
223 | __STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr)
224 | {
225 | MPU->RBAR = rbar;
226 | MPU->RASR = rasr;
227 | }
228 |
229 | /** Configure the given MPU region.
230 | * \param rnr Region number to be configured.
231 | * \param rbar Value for RBAR register.
232 | * \param rsar Value for RSAR register.
233 | */
234 | __STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr)
235 | {
236 | MPU->RNR = rnr;
237 | MPU->RBAR = rbar;
238 | MPU->RASR = rasr;
239 | }
240 |
241 | /** Memcopy with strictly ordered memory access, e.g. for register targets.
242 | * \param dst Destination data is copied to.
243 | * \param src Source data is copied from.
244 | * \param len Amount of data words to be copied.
245 | */
246 | __STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
247 | {
248 | uint32_t i;
249 | for (i = 0U; i < len; ++i)
250 | {
251 | dst[i] = src[i];
252 | }
253 | }
254 |
255 | /** Load the given number of MPU regions from a table.
256 | * \param table Pointer to the MPU configuration table.
257 | * \param cnt Amount of regions to be configured.
258 | */
259 | __STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt)
260 | {
261 | const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
262 | while (cnt > MPU_TYPE_RALIASES) {
263 | orderedCpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize);
264 | table += MPU_TYPE_RALIASES;
265 | cnt -= MPU_TYPE_RALIASES;
266 | }
267 | orderedCpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize);
268 | }
269 |
270 | #endif
271 |
--------------------------------------------------------------------------------
/nucleo-f446re/Drivers/CMSIS/Include/mpu_armv8.h:
--------------------------------------------------------------------------------
1 | /******************************************************************************
2 | * @file mpu_armv8.h
3 | * @brief CMSIS MPU API for Armv8-M MPU
4 | * @version V5.0.4
5 | * @date 10. January 2018
6 | ******************************************************************************/
7 | /*
8 | * Copyright (c) 2017-2018 Arm Limited. All rights reserved.
9 | *
10 | * SPDX-License-Identifier: Apache-2.0
11 | *
12 | * Licensed under the Apache License, Version 2.0 (the License); you may
13 | * not use this file except in compliance with the License.
14 | * You may obtain a copy of the License at
15 | *
16 | * www.apache.org/licenses/LICENSE-2.0
17 | *
18 | * Unless required by applicable law or agreed to in writing, software
19 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT
20 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
21 | * See the License for the specific language governing permissions and
22 | * limitations under the License.
23 | */
24 |
25 | #if defined ( __ICCARM__ )
26 | #pragma system_include /* treat file as system include file for MISRA check */
27 | #elif defined (__clang__)
28 | #pragma clang system_header /* treat file as system include file */
29 | #endif
30 |
31 | #ifndef ARM_MPU_ARMV8_H
32 | #define ARM_MPU_ARMV8_H
33 |
34 | /** \brief Attribute for device memory (outer only) */
35 | #define ARM_MPU_ATTR_DEVICE ( 0U )
36 |
37 | /** \brief Attribute for non-cacheable, normal memory */
38 | #define ARM_MPU_ATTR_NON_CACHEABLE ( 4U )
39 |
40 | /** \brief Attribute for normal memory (outer and inner)
41 | * \param NT Non-Transient: Set to 1 for non-transient data.
42 | * \param WB Write-Back: Set to 1 to use write-back update policy.
43 | * \param RA Read Allocation: Set to 1 to use cache allocation on read miss.
44 | * \param WA Write Allocation: Set to 1 to use cache allocation on write miss.
45 | */
46 | #define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \
47 | (((NT & 1U) << 3U) | ((WB & 1U) << 2U) | ((RA & 1U) << 1U) | (WA & 1U))
48 |
49 | /** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */
50 | #define ARM_MPU_ATTR_DEVICE_nGnRnE (0U)
51 |
52 | /** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */
53 | #define ARM_MPU_ATTR_DEVICE_nGnRE (1U)
54 |
55 | /** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */
56 | #define ARM_MPU_ATTR_DEVICE_nGRE (2U)
57 |
58 | /** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */
59 | #define ARM_MPU_ATTR_DEVICE_GRE (3U)
60 |
61 | /** \brief Memory Attribute
62 | * \param O Outer memory attributes
63 | * \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes
64 | */
65 | #define ARM_MPU_ATTR(O, I) (((O & 0xFU) << 4U) | (((O & 0xFU) != 0U) ? (I & 0xFU) : ((I & 0x3U) << 2U)))
66 |
67 | /** \brief Normal memory non-shareable */
68 | #define ARM_MPU_SH_NON (0U)
69 |
70 | /** \brief Normal memory outer shareable */
71 | #define ARM_MPU_SH_OUTER (2U)
72 |
73 | /** \brief Normal memory inner shareable */
74 | #define ARM_MPU_SH_INNER (3U)
75 |
76 | /** \brief Memory access permissions
77 | * \param RO Read-Only: Set to 1 for read-only memory.
78 | * \param NP Non-Privileged: Set to 1 for non-privileged memory.
79 | */
80 | #define ARM_MPU_AP_(RO, NP) (((RO & 1U) << 1U) | (NP & 1U))
81 |
82 | /** \brief Region Base Address Register value
83 | * \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned.
84 | * \param SH Defines the Shareability domain for this memory region.
85 | * \param RO Read-Only: Set to 1 for a read-only memory region.
86 | * \param NP Non-Privileged: Set to 1 for a non-privileged memory region.
87 | * \oaram XN eXecute Never: Set to 1 for a non-executable memory region.
88 | */
89 | #define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \
90 | ((BASE & MPU_RBAR_BASE_Msk) | \
91 | ((SH << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \
92 | ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \
93 | ((XN << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk))
94 |
95 | /** \brief Region Limit Address Register value
96 | * \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
97 | * \param IDX The attribute index to be associated with this memory region.
98 | */
99 | #define ARM_MPU_RLAR(LIMIT, IDX) \
100 | ((LIMIT & MPU_RLAR_LIMIT_Msk) | \
101 | ((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
102 | (MPU_RLAR_EN_Msk))
103 |
104 | /**
105 | * Struct for a single MPU Region
106 | */
107 | typedef struct {
108 | uint32_t RBAR; /*!< Region Base Address Register value */
109 | uint32_t RLAR; /*!< Region Limit Address Register value */
110 | } ARM_MPU_Region_t;
111 |
112 | /** Enable the MPU.
113 | * \param MPU_Control Default access permissions for unconfigured regions.
114 | */
115 | __STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
116 | {
117 | __DSB();
118 | __ISB();
119 | MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
120 | #ifdef SCB_SHCSR_MEMFAULTENA_Msk
121 | SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
122 | #endif
123 | }
124 |
125 | /** Disable the MPU.
126 | */
127 | __STATIC_INLINE void ARM_MPU_Disable(void)
128 | {
129 | __DSB();
130 | __ISB();
131 | #ifdef SCB_SHCSR_MEMFAULTENA_Msk
132 | SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
133 | #endif
134 | MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
135 | }
136 |
137 | #ifdef MPU_NS
138 | /** Enable the Non-secure MPU.
139 | * \param MPU_Control Default access permissions for unconfigured regions.
140 | */
141 | __STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control)
142 | {
143 | __DSB();
144 | __ISB();
145 | MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
146 | #ifdef SCB_SHCSR_MEMFAULTENA_Msk
147 | SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
148 | #endif
149 | }
150 |
151 | /** Disable the Non-secure MPU.
152 | */
153 | __STATIC_INLINE void ARM_MPU_Disable_NS(void)
154 | {
155 | __DSB();
156 | __ISB();
157 | #ifdef SCB_SHCSR_MEMFAULTENA_Msk
158 | SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
159 | #endif
160 | MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk;
161 | }
162 | #endif
163 |
164 | /** Set the memory attribute encoding to the given MPU.
165 | * \param mpu Pointer to the MPU to be configured.
166 | * \param idx The attribute index to be set [0-7]
167 | * \param attr The attribute value to be set.
168 | */
169 | __STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr)
170 | {
171 | const uint8_t reg = idx / 4U;
172 | const uint32_t pos = ((idx % 4U) * 8U);
173 | const uint32_t mask = 0xFFU << pos;
174 |
175 | if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) {
176 | return; // invalid index
177 | }
178 |
179 | mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask));
180 | }
181 |
182 | /** Set the memory attribute encoding.
183 | * \param idx The attribute index to be set [0-7]
184 | * \param attr The attribute value to be set.
185 | */
186 | __STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr)
187 | {
188 | ARM_MPU_SetMemAttrEx(MPU, idx, attr);
189 | }
190 |
191 | #ifdef MPU_NS
192 | /** Set the memory attribute encoding to the Non-secure MPU.
193 | * \param idx The attribute index to be set [0-7]
194 | * \param attr The attribute value to be set.
195 | */
196 | __STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr)
197 | {
198 | ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr);
199 | }
200 | #endif
201 |
202 | /** Clear and disable the given MPU region of the given MPU.
203 | * \param mpu Pointer to MPU to be used.
204 | * \param rnr Region number to be cleared.
205 | */
206 | __STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr)
207 | {
208 | mpu->RNR = rnr;
209 | mpu->RLAR = 0U;
210 | }
211 |
212 | /** Clear and disable the given MPU region.
213 | * \param rnr Region number to be cleared.
214 | */
215 | __STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
216 | {
217 | ARM_MPU_ClrRegionEx(MPU, rnr);
218 | }
219 |
220 | #ifdef MPU_NS
221 | /** Clear and disable the given Non-secure MPU region.
222 | * \param rnr Region number to be cleared.
223 | */
224 | __STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr)
225 | {
226 | ARM_MPU_ClrRegionEx(MPU_NS, rnr);
227 | }
228 | #endif
229 |
230 | /** Configure the given MPU region of the given MPU.
231 | * \param mpu Pointer to MPU to be used.
232 | * \param rnr Region number to be configured.
233 | * \param rbar Value for RBAR register.
234 | * \param rlar Value for RLAR register.
235 | */
236 | __STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar)
237 | {
238 | mpu->RNR = rnr;
239 | mpu->RBAR = rbar;
240 | mpu->RLAR = rlar;
241 | }
242 |
243 | /** Configure the given MPU region.
244 | * \param rnr Region number to be configured.
245 | * \param rbar Value for RBAR register.
246 | * \param rlar Value for RLAR register.
247 | */
248 | __STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar)
249 | {
250 | ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar);
251 | }
252 |
253 | #ifdef MPU_NS
254 | /** Configure the given Non-secure MPU region.
255 | * \param rnr Region number to be configured.
256 | * \param rbar Value for RBAR register.
257 | * \param rlar Value for RLAR register.
258 | */
259 | __STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar)
260 | {
261 | ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar);
262 | }
263 | #endif
264 |
265 | /** Memcopy with strictly ordered memory access, e.g. for register targets.
266 | * \param dst Destination data is copied to.
267 | * \param src Source data is copied from.
268 | * \param len Amount of data words to be copied.
269 | */
270 | __STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
271 | {
272 | uint32_t i;
273 | for (i = 0U; i < len; ++i)
274 | {
275 | dst[i] = src[i];
276 | }
277 | }
278 |
279 | /** Load the given number of MPU regions from a table to the given MPU.
280 | * \param mpu Pointer to the MPU registers to be used.
281 | * \param rnr First region number to be configured.
282 | * \param table Pointer to the MPU configuration table.
283 | * \param cnt Amount of regions to be configured.
284 | */
285 | __STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
286 | {
287 | const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
288 | if (cnt == 1U) {
289 | mpu->RNR = rnr;
290 | orderedCpy(&(mpu->RBAR), &(table->RBAR), rowWordSize);
291 | } else {
292 | uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U);
293 | uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES;
294 |
295 | mpu->RNR = rnrBase;
296 | while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) {
297 | uint32_t c = MPU_TYPE_RALIASES - rnrOffset;
298 | orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize);
299 | table += c;
300 | cnt -= c;
301 | rnrOffset = 0U;
302 | rnrBase += MPU_TYPE_RALIASES;
303 | mpu->RNR = rnrBase;
304 | }
305 |
306 | orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize);
307 | }
308 | }
309 |
310 | /** Load the given number of MPU regions from a table.
311 | * \param rnr First region number to be configured.
312 | * \param table Pointer to the MPU configuration table.
313 | * \param cnt Amount of regions to be configured.
314 | */
315 | __STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
316 | {
317 | ARM_MPU_LoadEx(MPU, rnr, table, cnt);
318 | }
319 |
320 | #ifdef MPU_NS
321 | /** Load the given number of MPU regions from a table to the Non-secure MPU.
322 | * \param rnr First region number to be configured.
323 | * \param table Pointer to the MPU configuration table.
324 | * \param cnt Amount of regions to be configured.
325 | */
326 | __STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
327 | {
328 | ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt);
329 | }
330 | #endif
331 |
332 | #endif
333 |
334 |
--------------------------------------------------------------------------------
/nucleo-f446re/Drivers/CMSIS/Include/tz_context.h:
--------------------------------------------------------------------------------
1 | /******************************************************************************
2 | * @file tz_context.h
3 | * @brief Context Management for Armv8-M TrustZone
4 | * @version V1.0.1
5 | * @date 10. January 2018
6 | ******************************************************************************/
7 | /*
8 | * Copyright (c) 2017-2018 Arm Limited. All rights reserved.
9 | *
10 | * SPDX-License-Identifier: Apache-2.0
11 | *
12 | * Licensed under the Apache License, Version 2.0 (the License); you may
13 | * not use this file except in compliance with the License.
14 | * You may obtain a copy of the License at
15 | *
16 | * www.apache.org/licenses/LICENSE-2.0
17 | *
18 | * Unless required by applicable law or agreed to in writing, software
19 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT
20 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
21 | * See the License for the specific language governing permissions and
22 | * limitations under the License.
23 | */
24 |
25 | #if defined ( __ICCARM__ )
26 | #pragma system_include /* treat file as system include file for MISRA check */
27 | #elif defined (__clang__)
28 | #pragma clang system_header /* treat file as system include file */
29 | #endif
30 |
31 | #ifndef TZ_CONTEXT_H
32 | #define TZ_CONTEXT_H
33 |
34 | #include
35 |
36 | #ifndef TZ_MODULEID_T
37 | #define TZ_MODULEID_T
38 | /// \details Data type that identifies secure software modules called by a process.
39 | typedef uint32_t TZ_ModuleId_t;
40 | #endif
41 |
42 | /// \details TZ Memory ID identifies an allocated memory slot.
43 | typedef uint32_t TZ_MemoryId_t;
44 |
45 | /// Initialize secure context memory system
46 | /// \return execution status (1: success, 0: error)
47 | uint32_t TZ_InitContextSystem_S (void);
48 |
49 | /// Allocate context memory for calling secure software modules in TrustZone
50 | /// \param[in] module identifies software modules called from non-secure mode
51 | /// \return value != 0 id TrustZone memory slot identifier
52 | /// \return value 0 no memory available or internal error
53 | TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module);
54 |
55 | /// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S
56 | /// \param[in] id TrustZone memory slot identifier
57 | /// \return execution status (1: success, 0: error)
58 | uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id);
59 |
60 | /// Load secure context (called on RTOS thread context switch)
61 | /// \param[in] id TrustZone memory slot identifier
62 | /// \return execution status (1: success, 0: error)
63 | uint32_t TZ_LoadContext_S (TZ_MemoryId_t id);
64 |
65 | /// Store secure context (called on RTOS thread context switch)
66 | /// \param[in] id TrustZone memory slot identifier
67 | /// \return execution status (1: success, 0: error)
68 | uint32_t TZ_StoreContext_S (TZ_MemoryId_t id);
69 |
70 | #endif // TZ_CONTEXT_H
71 |
--------------------------------------------------------------------------------
/nucleo-f446re/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file stm32f4xx_hal.h
4 | * @author MCD Application Team
5 | * @brief This file contains all the functions prototypes for the HAL
6 | * module driver.
7 | ******************************************************************************
8 | * @attention
9 | *
10 | * © Copyright (c) 2017 STMicroelectronics.
11 | * All rights reserved.
12 | *
13 | * This software component is licensed by ST under BSD 3-Clause license,
14 | * the "License"; You may not use this file except in compliance with the
15 | * License. You may obtain a copy of the License at:
16 | * opensource.org/licenses/BSD-3-Clause
17 | *
18 | ******************************************************************************
19 | */
20 |
21 | /* Define to prevent recursive inclusion -------------------------------------*/
22 | #ifndef __STM32F4xx_HAL_H
23 | #define __STM32F4xx_HAL_H
24 |
25 | #ifdef __cplusplus
26 | extern "C" {
27 | #endif
28 |
29 | /* Includes ------------------------------------------------------------------*/
30 | #include "stm32f4xx_hal_conf.h"
31 |
32 | /** @addtogroup STM32F4xx_HAL_Driver
33 | * @{
34 | */
35 |
36 | /** @addtogroup HAL
37 | * @{
38 | */
39 |
40 | /* Exported types ------------------------------------------------------------*/
41 | /* Exported constants --------------------------------------------------------*/
42 |
43 | /** @defgroup HAL_Exported_Constants HAL Exported Constants
44 | * @{
45 | */
46 |
47 | /** @defgroup HAL_TICK_FREQ Tick Frequency
48 | * @{
49 | */
50 | typedef enum
51 | {
52 | HAL_TICK_FREQ_10HZ = 100U,
53 | HAL_TICK_FREQ_100HZ = 10U,
54 | HAL_TICK_FREQ_1KHZ = 1U,
55 | HAL_TICK_FREQ_DEFAULT = HAL_TICK_FREQ_1KHZ
56 | } HAL_TickFreqTypeDef;
57 | /**
58 | * @}
59 | */
60 |
61 | /**
62 | * @}
63 | */
64 |
65 | /* Exported macro ------------------------------------------------------------*/
66 | /** @defgroup HAL_Exported_Macros HAL Exported Macros
67 | * @{
68 | */
69 |
70 | /** @brief Freeze/Unfreeze Peripherals in Debug mode
71 | */
72 | #define __HAL_DBGMCU_FREEZE_TIM2() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM2_STOP))
73 | #define __HAL_DBGMCU_FREEZE_TIM3() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM3_STOP))
74 | #define __HAL_DBGMCU_FREEZE_TIM4() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM4_STOP))
75 | #define __HAL_DBGMCU_FREEZE_TIM5() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM5_STOP))
76 | #define __HAL_DBGMCU_FREEZE_TIM6() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM6_STOP))
77 | #define __HAL_DBGMCU_FREEZE_TIM7() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM7_STOP))
78 | #define __HAL_DBGMCU_FREEZE_TIM12() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM12_STOP))
79 | #define __HAL_DBGMCU_FREEZE_TIM13() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM13_STOP))
80 | #define __HAL_DBGMCU_FREEZE_TIM14() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM14_STOP))
81 | #define __HAL_DBGMCU_FREEZE_RTC() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_RTC_STOP))
82 | #define __HAL_DBGMCU_FREEZE_WWDG() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_WWDG_STOP))
83 | #define __HAL_DBGMCU_FREEZE_IWDG() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_IWDG_STOP))
84 | #define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT))
85 | #define __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT))
86 | #define __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT))
87 | #define __HAL_DBGMCU_FREEZE_CAN1() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_CAN1_STOP))
88 | #define __HAL_DBGMCU_FREEZE_CAN2() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_CAN2_STOP))
89 | #define __HAL_DBGMCU_FREEZE_TIM1() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM1_STOP))
90 | #define __HAL_DBGMCU_FREEZE_TIM8() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM8_STOP))
91 | #define __HAL_DBGMCU_FREEZE_TIM9() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM9_STOP))
92 | #define __HAL_DBGMCU_FREEZE_TIM10() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM10_STOP))
93 | #define __HAL_DBGMCU_FREEZE_TIM11() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM11_STOP))
94 |
95 | #define __HAL_DBGMCU_UNFREEZE_TIM2() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM2_STOP))
96 | #define __HAL_DBGMCU_UNFREEZE_TIM3() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM3_STOP))
97 | #define __HAL_DBGMCU_UNFREEZE_TIM4() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM4_STOP))
98 | #define __HAL_DBGMCU_UNFREEZE_TIM5() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM5_STOP))
99 | #define __HAL_DBGMCU_UNFREEZE_TIM6() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM6_STOP))
100 | #define __HAL_DBGMCU_UNFREEZE_TIM7() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM7_STOP))
101 | #define __HAL_DBGMCU_UNFREEZE_TIM12() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM12_STOP))
102 | #define __HAL_DBGMCU_UNFREEZE_TIM13() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM13_STOP))
103 | #define __HAL_DBGMCU_UNFREEZE_TIM14() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM14_STOP))
104 | #define __HAL_DBGMCU_UNFREEZE_RTC() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_RTC_STOP))
105 | #define __HAL_DBGMCU_UNFREEZE_WWDG() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_WWDG_STOP))
106 | #define __HAL_DBGMCU_UNFREEZE_IWDG() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_IWDG_STOP))
107 | #define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT))
108 | #define __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT))
109 | #define __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT))
110 | #define __HAL_DBGMCU_UNFREEZE_CAN1() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_CAN1_STOP))
111 | #define __HAL_DBGMCU_UNFREEZE_CAN2() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_CAN2_STOP))
112 | #define __HAL_DBGMCU_UNFREEZE_TIM1() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM1_STOP))
113 | #define __HAL_DBGMCU_UNFREEZE_TIM8() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM8_STOP))
114 | #define __HAL_DBGMCU_UNFREEZE_TIM9() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM9_STOP))
115 | #define __HAL_DBGMCU_UNFREEZE_TIM10() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM10_STOP))
116 | #define __HAL_DBGMCU_UNFREEZE_TIM11() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM11_STOP))
117 |
118 | /** @brief Main Flash memory mapped at 0x00000000
119 | */
120 | #define __HAL_SYSCFG_REMAPMEMORY_FLASH() (SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_MEM_MODE))
121 |
122 | /** @brief System Flash memory mapped at 0x00000000
123 | */
124 | #define __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH() do {SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_MEM_MODE);\
125 | SYSCFG->MEMRMP |= SYSCFG_MEMRMP_MEM_MODE_0;\
126 | }while(0);
127 |
128 | /** @brief Embedded SRAM mapped at 0x00000000
129 | */
130 | #define __HAL_SYSCFG_REMAPMEMORY_SRAM() do {SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_MEM_MODE);\
131 | SYSCFG->MEMRMP |= (SYSCFG_MEMRMP_MEM_MODE_0 | SYSCFG_MEMRMP_MEM_MODE_1);\
132 | }while(0);
133 |
134 | #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)
135 | /** @brief FSMC Bank1 (NOR/PSRAM 1 and 2) mapped at 0x00000000
136 | */
137 | #define __HAL_SYSCFG_REMAPMEMORY_FSMC() do {SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_MEM_MODE);\
138 | SYSCFG->MEMRMP |= (SYSCFG_MEMRMP_MEM_MODE_1);\
139 | }while(0);
140 | #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
141 |
142 | #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\
143 | defined(STM32F469xx) || defined(STM32F479xx)
144 | /** @brief FMC Bank1 (NOR/PSRAM 1 and 2) mapped at 0x00000000
145 | */
146 | #define __HAL_SYSCFG_REMAPMEMORY_FMC() do {SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_MEM_MODE);\
147 | SYSCFG->MEMRMP |= (SYSCFG_MEMRMP_MEM_MODE_1);\
148 | }while(0);
149 |
150 | /** @brief FMC/SDRAM Bank 1 and 2 mapped at 0x00000000
151 | */
152 | #define __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM() do {SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_MEM_MODE);\
153 | SYSCFG->MEMRMP |= (SYSCFG_MEMRMP_MEM_MODE_2);\
154 | }while(0);
155 | #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
156 |
157 | #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F413xx) || defined(STM32F423xx)
158 | /** @defgroup Cortex_Lockup_Enable Cortex Lockup Enable
159 | * @{
160 | */
161 | /** @brief SYSCFG Break Lockup lock
162 | * Enables and locks the connection of Cortex-M4 LOCKUP (Hardfault) output to TIM1/8 input
163 | * @note The selected configuration is locked and can be unlocked by system reset
164 | */
165 | #define __HAL_SYSCFG_BREAK_PVD_LOCK() do {SYSCFG->CFGR2 &= ~(SYSCFG_CFGR2_PVD_LOCK); \
166 | SYSCFG->CFGR2 |= SYSCFG_CFGR2_PVD_LOCK; \
167 | }while(0)
168 | /**
169 | * @}
170 | */
171 |
172 | /** @defgroup PVD_Lock_Enable PVD Lock
173 | * @{
174 | */
175 | /** @brief SYSCFG Break PVD lock
176 | * Enables and locks the PVD connection with Timer1/8 Break Input, , as well as the PVDE and PLS[2:0] in the PWR_CR register
177 | * @note The selected configuration is locked and can be unlocked by system reset
178 | */
179 | #define __HAL_SYSCFG_BREAK_LOCKUP_LOCK() do {SYSCFG->CFGR2 &= ~(SYSCFG_CFGR2_LOCKUP_LOCK); \
180 | SYSCFG->CFGR2 |= SYSCFG_CFGR2_LOCKUP_LOCK; \
181 | }while(0)
182 | /**
183 | * @}
184 | */
185 | #endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx || STM32F413xx || STM32F423xx */
186 | /**
187 | * @}
188 | */
189 |
190 | /** @defgroup HAL_Private_Macros HAL Private Macros
191 | * @{
192 | */
193 | #define IS_TICKFREQ(FREQ) (((FREQ) == HAL_TICK_FREQ_10HZ) || \
194 | ((FREQ) == HAL_TICK_FREQ_100HZ) || \
195 | ((FREQ) == HAL_TICK_FREQ_1KHZ))
196 | /**
197 | * @}
198 | */
199 |
200 | /* Exported variables --------------------------------------------------------*/
201 |
202 | /** @addtogroup HAL_Exported_Variables
203 | * @{
204 | */
205 | extern __IO uint32_t uwTick;
206 | extern uint32_t uwTickPrio;
207 | extern HAL_TickFreqTypeDef uwTickFreq;
208 | /**
209 | * @}
210 | */
211 |
212 | /* Exported functions --------------------------------------------------------*/
213 | /** @addtogroup HAL_Exported_Functions
214 | * @{
215 | */
216 | /** @addtogroup HAL_Exported_Functions_Group1
217 | * @{
218 | */
219 | /* Initialization and Configuration functions ******************************/
220 | HAL_StatusTypeDef HAL_Init(void);
221 | HAL_StatusTypeDef HAL_DeInit(void);
222 | void HAL_MspInit(void);
223 | void HAL_MspDeInit(void);
224 | HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority);
225 | /**
226 | * @}
227 | */
228 |
229 | /** @addtogroup HAL_Exported_Functions_Group2
230 | * @{
231 | */
232 | /* Peripheral Control functions ************************************************/
233 | void HAL_IncTick(void);
234 | void HAL_Delay(uint32_t Delay);
235 | uint32_t HAL_GetTick(void);
236 | uint32_t HAL_GetTickPrio(void);
237 | HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq);
238 | HAL_TickFreqTypeDef HAL_GetTickFreq(void);
239 | void HAL_SuspendTick(void);
240 | void HAL_ResumeTick(void);
241 | uint32_t HAL_GetHalVersion(void);
242 | uint32_t HAL_GetREVID(void);
243 | uint32_t HAL_GetDEVID(void);
244 | void HAL_DBGMCU_EnableDBGSleepMode(void);
245 | void HAL_DBGMCU_DisableDBGSleepMode(void);
246 | void HAL_DBGMCU_EnableDBGStopMode(void);
247 | void HAL_DBGMCU_DisableDBGStopMode(void);
248 | void HAL_DBGMCU_EnableDBGStandbyMode(void);
249 | void HAL_DBGMCU_DisableDBGStandbyMode(void);
250 | void HAL_EnableCompensationCell(void);
251 | void HAL_DisableCompensationCell(void);
252 | uint32_t HAL_GetUIDw0(void);
253 | uint32_t HAL_GetUIDw1(void);
254 | uint32_t HAL_GetUIDw2(void);
255 | #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\
256 | defined(STM32F469xx) || defined(STM32F479xx)
257 | void HAL_EnableMemorySwappingBank(void);
258 | void HAL_DisableMemorySwappingBank(void);
259 | #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
260 | /**
261 | * @}
262 | */
263 |
264 | /**
265 | * @}
266 | */
267 | /* Private types -------------------------------------------------------------*/
268 | /* Private variables ---------------------------------------------------------*/
269 | /** @defgroup HAL_Private_Variables HAL Private Variables
270 | * @{
271 | */
272 | /**
273 | * @}
274 | */
275 | /* Private constants ---------------------------------------------------------*/
276 | /** @defgroup HAL_Private_Constants HAL Private Constants
277 | * @{
278 | */
279 | /**
280 | * @}
281 | */
282 | /* Private macros ------------------------------------------------------------*/
283 | /* Private functions ---------------------------------------------------------*/
284 | /**
285 | * @}
286 | */
287 |
288 | /**
289 | * @}
290 | */
291 |
292 | #ifdef __cplusplus
293 | }
294 | #endif
295 |
296 | #endif /* __STM32F4xx_HAL_H */
297 |
298 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
299 |
--------------------------------------------------------------------------------
/nucleo-f446re/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file stm32f4xx_hal_def.h
4 | * @author MCD Application Team
5 | * @brief This file contains HAL common defines, enumeration, macros and
6 | * structures definitions.
7 | ******************************************************************************
8 | * @attention
9 | *
10 | * © Copyright (c) 2017 STMicroelectronics.
11 | * All rights reserved.
12 | *
13 | * This software component is licensed by ST under BSD 3-Clause license,
14 | * the "License"; You may not use this file except in compliance with the
15 | * License. You may obtain a copy of the License at:
16 | * opensource.org/licenses/BSD-3-Clause
17 | *
18 | ******************************************************************************
19 | */
20 |
21 | /* Define to prevent recursive inclusion -------------------------------------*/
22 | #ifndef __STM32F4xx_HAL_DEF
23 | #define __STM32F4xx_HAL_DEF
24 |
25 | #ifdef __cplusplus
26 | extern "C" {
27 | #endif
28 |
29 | /* Includes ------------------------------------------------------------------*/
30 | #include "stm32f4xx.h"
31 | #include "Legacy/stm32_hal_legacy.h"
32 | #include
33 |
34 | /* Exported types ------------------------------------------------------------*/
35 |
36 | /**
37 | * @brief HAL Status structures definition
38 | */
39 | typedef enum
40 | {
41 | HAL_OK = 0x00U,
42 | HAL_ERROR = 0x01U,
43 | HAL_BUSY = 0x02U,
44 | HAL_TIMEOUT = 0x03U
45 | } HAL_StatusTypeDef;
46 |
47 | /**
48 | * @brief HAL Lock structures definition
49 | */
50 | typedef enum
51 | {
52 | HAL_UNLOCKED = 0x00U,
53 | HAL_LOCKED = 0x01U
54 | } HAL_LockTypeDef;
55 |
56 | /* Exported macro ------------------------------------------------------------*/
57 |
58 | #define UNUSED(X) (void)X /* To avoid gcc/g++ warnings */
59 |
60 | #define HAL_MAX_DELAY 0xFFFFFFFFU
61 |
62 | #define HAL_IS_BIT_SET(REG, BIT) (((REG) & (BIT)) == (BIT))
63 | #define HAL_IS_BIT_CLR(REG, BIT) (((REG) & (BIT)) == 0U)
64 |
65 | #define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD__, __DMA_HANDLE__) \
66 | do{ \
67 | (__HANDLE__)->__PPP_DMA_FIELD__ = &(__DMA_HANDLE__); \
68 | (__DMA_HANDLE__).Parent = (__HANDLE__); \
69 | } while(0U)
70 |
71 | /** @brief Reset the Handle's State field.
72 | * @param __HANDLE__ specifies the Peripheral Handle.
73 | * @note This macro can be used for the following purpose:
74 | * - When the Handle is declared as local variable; before passing it as parameter
75 | * to HAL_PPP_Init() for the first time, it is mandatory to use this macro
76 | * to set to 0 the Handle's "State" field.
77 | * Otherwise, "State" field may have any random value and the first time the function
78 | * HAL_PPP_Init() is called, the low level hardware initialization will be missed
79 | * (i.e. HAL_PPP_MspInit() will not be executed).
80 | * - When there is a need to reconfigure the low level hardware: instead of calling
81 | * HAL_PPP_DeInit() then HAL_PPP_Init(), user can make a call to this macro then HAL_PPP_Init().
82 | * In this later function, when the Handle's "State" field is set to 0, it will execute the function
83 | * HAL_PPP_MspInit() which will reconfigure the low level hardware.
84 | * @retval None
85 | */
86 | #define __HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0U)
87 |
88 | #if (USE_RTOS == 1U)
89 | /* Reserved for future use */
90 | #error "USE_RTOS should be 0 in the current HAL release"
91 | #else
92 | #define __HAL_LOCK(__HANDLE__) \
93 | do{ \
94 | if((__HANDLE__)->Lock == HAL_LOCKED) \
95 | { \
96 | return HAL_BUSY; \
97 | } \
98 | else \
99 | { \
100 | (__HANDLE__)->Lock = HAL_LOCKED; \
101 | } \
102 | }while (0U)
103 |
104 | #define __HAL_UNLOCK(__HANDLE__) \
105 | do{ \
106 | (__HANDLE__)->Lock = HAL_UNLOCKED; \
107 | }while (0U)
108 | #endif /* USE_RTOS */
109 |
110 | #if defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */
111 | #ifndef __weak
112 | #define __weak __attribute__((weak))
113 | #endif /* __weak */
114 | #ifndef __packed
115 | #define __packed __attribute__((__packed__))
116 | #endif /* __packed */
117 | #endif /* __GNUC__ */
118 |
119 |
120 | /* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */
121 | #if defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */
122 | #ifndef __ALIGN_END
123 | #define __ALIGN_END __attribute__ ((aligned (4)))
124 | #endif /* __ALIGN_END */
125 | #ifndef __ALIGN_BEGIN
126 | #define __ALIGN_BEGIN
127 | #endif /* __ALIGN_BEGIN */
128 | #else
129 | #ifndef __ALIGN_END
130 | #define __ALIGN_END
131 | #endif /* __ALIGN_END */
132 | #ifndef __ALIGN_BEGIN
133 | #if defined (__CC_ARM) /* ARM Compiler */
134 | #define __ALIGN_BEGIN __align(4)
135 | #elif defined (__ICCARM__) /* IAR Compiler */
136 | #define __ALIGN_BEGIN
137 | #endif /* __CC_ARM */
138 | #endif /* __ALIGN_BEGIN */
139 | #endif /* __GNUC__ */
140 |
141 |
142 | /**
143 | * @brief __RAM_FUNC definition
144 | */
145 | #if defined ( __CC_ARM )
146 | /* ARM Compiler
147 | ------------
148 | RAM functions are defined using the toolchain options.
149 | Functions that are executed in RAM should reside in a separate source module.
150 | Using the 'Options for File' dialog you can simply change the 'Code / Const'
151 | area of a module to a memory space in physical RAM.
152 | Available memory areas are declared in the 'Target' tab of the 'Options for Target'
153 | dialog.
154 | */
155 | #define __RAM_FUNC
156 |
157 | #elif defined ( __ICCARM__ )
158 | /* ICCARM Compiler
159 | ---------------
160 | RAM functions are defined using a specific toolchain keyword "__ramfunc".
161 | */
162 | #define __RAM_FUNC __ramfunc
163 |
164 | #elif defined ( __GNUC__ )
165 | /* GNU Compiler
166 | ------------
167 | RAM functions are defined using a specific toolchain attribute
168 | "__attribute__((section(".RamFunc")))".
169 | */
170 | #define __RAM_FUNC __attribute__((section(".RamFunc")))
171 |
172 | #endif
173 |
174 | /**
175 | * @brief __NOINLINE definition
176 | */
177 | #if defined ( __CC_ARM ) || defined ( __GNUC__ )
178 | /* ARM & GNUCompiler
179 | ----------------
180 | */
181 | #define __NOINLINE __attribute__ ( (noinline) )
182 |
183 | #elif defined ( __ICCARM__ )
184 | /* ICCARM Compiler
185 | ---------------
186 | */
187 | #define __NOINLINE _Pragma("optimize = no_inline")
188 |
189 | #endif
190 |
191 | #ifdef __cplusplus
192 | }
193 | #endif
194 |
195 | #endif /* ___STM32F4xx_HAL_DEF */
196 |
197 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
198 |
--------------------------------------------------------------------------------
/nucleo-f446re/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file stm32f4xx_hal_dma_ex.h
4 | * @author MCD Application Team
5 | * @brief Header file of DMA HAL extension module.
6 | ******************************************************************************
7 | * @attention
8 | *
9 | * © Copyright (c) 2017 STMicroelectronics.
10 | * All rights reserved.
11 | *
12 | * This software component is licensed by ST under BSD 3-Clause license,
13 | * the "License"; You may not use this file except in compliance with the
14 | * License. You may obtain a copy of the License at:
15 | * opensource.org/licenses/BSD-3-Clause
16 | *
17 | ******************************************************************************
18 | */
19 |
20 | /* Define to prevent recursive inclusion -------------------------------------*/
21 | #ifndef __STM32F4xx_HAL_DMA_EX_H
22 | #define __STM32F4xx_HAL_DMA_EX_H
23 |
24 | #ifdef __cplusplus
25 | extern "C" {
26 | #endif
27 |
28 | /* Includes ------------------------------------------------------------------*/
29 | #include "stm32f4xx_hal_def.h"
30 |
31 | /** @addtogroup STM32F4xx_HAL_Driver
32 | * @{
33 | */
34 |
35 | /** @addtogroup DMAEx
36 | * @{
37 | */
38 |
39 | /* Exported types ------------------------------------------------------------*/
40 | /** @defgroup DMAEx_Exported_Types DMAEx Exported Types
41 | * @brief DMAEx Exported types
42 | * @{
43 | */
44 |
45 | /**
46 | * @brief HAL DMA Memory definition
47 | */
48 | typedef enum
49 | {
50 | MEMORY0 = 0x00U, /*!< Memory 0 */
51 | MEMORY1 = 0x01U /*!< Memory 1 */
52 | }HAL_DMA_MemoryTypeDef;
53 |
54 | /**
55 | * @}
56 | */
57 |
58 | /* Exported functions --------------------------------------------------------*/
59 | /** @defgroup DMAEx_Exported_Functions DMAEx Exported Functions
60 | * @brief DMAEx Exported functions
61 | * @{
62 | */
63 |
64 | /** @defgroup DMAEx_Exported_Functions_Group1 Extended features functions
65 | * @brief Extended features functions
66 | * @{
67 | */
68 |
69 | /* IO operation functions *******************************************************/
70 | HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength);
71 | HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength);
72 | HAL_StatusTypeDef HAL_DMAEx_ChangeMemory(DMA_HandleTypeDef *hdma, uint32_t Address, HAL_DMA_MemoryTypeDef memory);
73 |
74 | /**
75 | * @}
76 | */
77 | /**
78 | * @}
79 | */
80 |
81 | /* Private functions ---------------------------------------------------------*/
82 | /** @defgroup DMAEx_Private_Functions DMAEx Private Functions
83 | * @brief DMAEx Private functions
84 | * @{
85 | */
86 | /**
87 | * @}
88 | */
89 |
90 | /**
91 | * @}
92 | */
93 |
94 | /**
95 | * @}
96 | */
97 |
98 | #ifdef __cplusplus
99 | }
100 | #endif
101 |
102 | #endif /*__STM32F4xx_HAL_DMA_EX_H*/
103 |
104 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
105 |
--------------------------------------------------------------------------------
/nucleo-f446re/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file stm32f4xx_hal_exti.h
4 | * @author MCD Application Team
5 | * @brief Header file of EXTI HAL module.
6 | ******************************************************************************
7 | * @attention
8 | *
9 | * © Copyright (c) 2018 STMicroelectronics.
10 | * All rights reserved.
11 | *
12 | * This software component is licensed by ST under BSD 3-Clause license,
13 | * the "License"; You may not use this file except in compliance with the
14 | * License. You may obtain a copy of the License at:
15 | * opensource.org/licenses/BSD-3-Clause
16 | *
17 | ******************************************************************************
18 | */
19 |
20 | /* Define to prevent recursive inclusion -------------------------------------*/
21 | #ifndef STM32f4xx_HAL_EXTI_H
22 | #define STM32f4xx_HAL_EXTI_H
23 |
24 | #ifdef __cplusplus
25 | extern "C" {
26 | #endif
27 |
28 | /* Includes ------------------------------------------------------------------*/
29 | #include "stm32f4xx_hal_def.h"
30 |
31 | /** @addtogroup STM32F4xx_HAL_Driver
32 | * @{
33 | */
34 |
35 | /** @defgroup EXTI EXTI
36 | * @brief EXTI HAL module driver
37 | * @{
38 | */
39 |
40 | /* Exported types ------------------------------------------------------------*/
41 |
42 | /** @defgroup EXTI_Exported_Types EXTI Exported Types
43 | * @{
44 | */
45 | typedef enum
46 | {
47 | HAL_EXTI_COMMON_CB_ID = 0x00U
48 | } EXTI_CallbackIDTypeDef;
49 |
50 | /**
51 | * @brief EXTI Handle structure definition
52 | */
53 | typedef struct
54 | {
55 | uint32_t Line; /*!< Exti line number */
56 | void (* PendingCallback)(void); /*!< Exti pending callback */
57 | } EXTI_HandleTypeDef;
58 |
59 | /**
60 | * @brief EXTI Configuration structure definition
61 | */
62 | typedef struct
63 | {
64 | uint32_t Line; /*!< The Exti line to be configured. This parameter
65 | can be a value of @ref EXTI_Line */
66 | uint32_t Mode; /*!< The Exit Mode to be configured for a core.
67 | This parameter can be a combination of @ref EXTI_Mode */
68 | uint32_t Trigger; /*!< The Exti Trigger to be configured. This parameter
69 | can be a value of @ref EXTI_Trigger */
70 | uint32_t GPIOSel; /*!< The Exti GPIO multiplexer selection to be configured.
71 | This parameter is only possible for line 0 to 15. It
72 | can be a value of @ref EXTI_GPIOSel */
73 | } EXTI_ConfigTypeDef;
74 |
75 | /**
76 | * @}
77 | */
78 |
79 | /* Exported constants --------------------------------------------------------*/
80 | /** @defgroup EXTI_Exported_Constants EXTI Exported Constants
81 | * @{
82 | */
83 |
84 | /** @defgroup EXTI_Line EXTI Line
85 | * @{
86 | */
87 | #define EXTI_LINE_0 (EXTI_GPIO | 0x00u) /*!< External interrupt line 0 */
88 | #define EXTI_LINE_1 (EXTI_GPIO | 0x01u) /*!< External interrupt line 1 */
89 | #define EXTI_LINE_2 (EXTI_GPIO | 0x02u) /*!< External interrupt line 2 */
90 | #define EXTI_LINE_3 (EXTI_GPIO | 0x03u) /*!< External interrupt line 3 */
91 | #define EXTI_LINE_4 (EXTI_GPIO | 0x04u) /*!< External interrupt line 4 */
92 | #define EXTI_LINE_5 (EXTI_GPIO | 0x05u) /*!< External interrupt line 5 */
93 | #define EXTI_LINE_6 (EXTI_GPIO | 0x06u) /*!< External interrupt line 6 */
94 | #define EXTI_LINE_7 (EXTI_GPIO | 0x07u) /*!< External interrupt line 7 */
95 | #define EXTI_LINE_8 (EXTI_GPIO | 0x08u) /*!< External interrupt line 8 */
96 | #define EXTI_LINE_9 (EXTI_GPIO | 0x09u) /*!< External interrupt line 9 */
97 | #define EXTI_LINE_10 (EXTI_GPIO | 0x0Au) /*!< External interrupt line 10 */
98 | #define EXTI_LINE_11 (EXTI_GPIO | 0x0Bu) /*!< External interrupt line 11 */
99 | #define EXTI_LINE_12 (EXTI_GPIO | 0x0Cu) /*!< External interrupt line 12 */
100 | #define EXTI_LINE_13 (EXTI_GPIO | 0x0Du) /*!< External interrupt line 13 */
101 | #define EXTI_LINE_14 (EXTI_GPIO | 0x0Eu) /*!< External interrupt line 14 */
102 | #define EXTI_LINE_15 (EXTI_GPIO | 0x0Fu) /*!< External interrupt line 15 */
103 | #define EXTI_LINE_16 (EXTI_CONFIG | 0x10u) /*!< External interrupt line 16 Connected to the PVD Output */
104 | #define EXTI_LINE_17 (EXTI_CONFIG | 0x11u) /*!< External interrupt line 17 Connected to the RTC Alarm event */
105 | #if defined(EXTI_IMR_IM18)
106 | #define EXTI_LINE_18 (EXTI_CONFIG | 0x12u) /*!< External interrupt line 18 Connected to the USB OTG FS Wakeup from suspend event */
107 | #else
108 | #define EXTI_LINE_18 (EXTI_RESERVED | 0x12u) /*!< No interrupt supported in this line */
109 | #endif /* EXTI_IMR_IM18 */
110 | #if defined(EXTI_IMR_IM19)
111 | #define EXTI_LINE_19 (EXTI_CONFIG | 0x13u) /*!< External interrupt line 19 Connected to the Ethernet Wakeup event */
112 | #else
113 | #define EXTI_LINE_19 (EXTI_RESERVED | 0x13u) /*!< No interrupt supported in this line */
114 | #endif /* EXTI_IMR_IM19 */
115 | #if defined(EXTI_IMR_IM20)
116 | #define EXTI_LINE_20 (EXTI_CONFIG | 0x14u) /*!< External interrupt line 20 Connected to the USB OTG HS (configured in FS) Wakeup event */
117 | #else
118 | #define EXTI_LINE_20 (EXTI_RESERVED | 0x14u) /*!< No interrupt supported in this line */
119 | #endif /* EXTI_IMR_IM20 */
120 | #define EXTI_LINE_21 (EXTI_CONFIG | 0x15u) /*!< External interrupt line 21 Connected to the RTC Tamper and Time Stamp events */
121 | #define EXTI_LINE_22 (EXTI_CONFIG | 0x16u) /*!< External interrupt line 22 Connected to the RTC Wakeup event */
122 | #if defined(EXTI_IMR_IM23)
123 | #define EXTI_LINE_23 (EXTI_CONFIG | 0x17u) /*!< External interrupt line 23 Connected to the LPTIM1 asynchronous event */
124 | #endif /* EXTI_IMR_IM23 */
125 |
126 | /**
127 | * @}
128 | */
129 |
130 | /** @defgroup EXTI_Mode EXTI Mode
131 | * @{
132 | */
133 | #define EXTI_MODE_NONE 0x00000000u
134 | #define EXTI_MODE_INTERRUPT 0x00000001u
135 | #define EXTI_MODE_EVENT 0x00000002u
136 | /**
137 | * @}
138 | */
139 |
140 | /** @defgroup EXTI_Trigger EXTI Trigger
141 | * @{
142 | */
143 |
144 | #define EXTI_TRIGGER_NONE 0x00000000u
145 | #define EXTI_TRIGGER_RISING 0x00000001u
146 | #define EXTI_TRIGGER_FALLING 0x00000002u
147 | #define EXTI_TRIGGER_RISING_FALLING (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING)
148 | /**
149 | * @}
150 | */
151 |
152 | /** @defgroup EXTI_GPIOSel EXTI GPIOSel
153 | * @brief
154 | * @{
155 | */
156 | #define EXTI_GPIOA 0x00000000u
157 | #define EXTI_GPIOB 0x00000001u
158 | #define EXTI_GPIOC 0x00000002u
159 | #if defined (GPIOD)
160 | #define EXTI_GPIOD 0x00000003u
161 | #endif /* GPIOD */
162 | #if defined (GPIOE)
163 | #define EXTI_GPIOE 0x00000004u
164 | #endif /* GPIOE */
165 | #if defined (GPIOF)
166 | #define EXTI_GPIOF 0x00000005u
167 | #endif /* GPIOF */
168 | #if defined (GPIOG)
169 | #define EXTI_GPIOG 0x00000006u
170 | #endif /* GPIOG */
171 | #if defined (GPIOH)
172 | #define EXTI_GPIOH 0x00000007u
173 | #endif /* GPIOH */
174 | #if defined (GPIOI)
175 | #define EXTI_GPIOI 0x00000008u
176 | #endif /* GPIOI */
177 | #if defined (GPIOJ)
178 | #define EXTI_GPIOJ 0x00000009u
179 | #endif /* GPIOJ */
180 | #if defined (GPIOK)
181 | #define EXTI_GPIOK 0x0000000Au
182 | #endif /* GPIOK */
183 |
184 | /**
185 | * @}
186 | */
187 |
188 | /**
189 | * @}
190 | */
191 |
192 | /* Exported macro ------------------------------------------------------------*/
193 | /** @defgroup EXTI_Exported_Macros EXTI Exported Macros
194 | * @{
195 | */
196 |
197 | /**
198 | * @}
199 | */
200 |
201 | /* Private constants --------------------------------------------------------*/
202 | /** @defgroup EXTI_Private_Constants EXTI Private Constants
203 | * @{
204 | */
205 | /**
206 | * @brief EXTI Line property definition
207 | */
208 | #define EXTI_PROPERTY_SHIFT 24u
209 | #define EXTI_CONFIG (0x02uL << EXTI_PROPERTY_SHIFT)
210 | #define EXTI_GPIO ((0x04uL << EXTI_PROPERTY_SHIFT) | EXTI_CONFIG)
211 | #define EXTI_RESERVED (0x08uL << EXTI_PROPERTY_SHIFT)
212 | #define EXTI_PROPERTY_MASK (EXTI_CONFIG | EXTI_GPIO)
213 |
214 | /**
215 | * @brief EXTI bit usage
216 | */
217 | #define EXTI_PIN_MASK 0x0000001Fu
218 |
219 | /**
220 | * @brief EXTI Mask for interrupt & event mode
221 | */
222 | #define EXTI_MODE_MASK (EXTI_MODE_EVENT | EXTI_MODE_INTERRUPT)
223 |
224 | /**
225 | * @brief EXTI Mask for trigger possibilities
226 | */
227 | #define EXTI_TRIGGER_MASK (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING)
228 |
229 | /**
230 | * @brief EXTI Line number
231 | */
232 | #if defined(EXTI_IMR_IM23)
233 | #define EXTI_LINE_NB 24UL
234 | #else
235 | #define EXTI_LINE_NB 23UL
236 | #endif /* EXTI_IMR_IM23 */
237 |
238 | /**
239 | * @}
240 | */
241 |
242 | /* Private macros ------------------------------------------------------------*/
243 | /** @defgroup EXTI_Private_Macros EXTI Private Macros
244 | * @{
245 | */
246 | #define IS_EXTI_LINE(__LINE__) ((((__LINE__) & ~(EXTI_PROPERTY_MASK | EXTI_PIN_MASK)) == 0x00u) && \
247 | ((((__LINE__) & EXTI_PROPERTY_MASK) == EXTI_CONFIG) || \
248 | (((__LINE__) & EXTI_PROPERTY_MASK) == EXTI_GPIO)) && \
249 | (((__LINE__) & EXTI_PIN_MASK) < EXTI_LINE_NB))
250 |
251 | #define IS_EXTI_MODE(__LINE__) ((((__LINE__) & EXTI_MODE_MASK) != 0x00u) && \
252 | (((__LINE__) & ~EXTI_MODE_MASK) == 0x00u))
253 |
254 | #define IS_EXTI_TRIGGER(__LINE__) (((__LINE__) & ~EXTI_TRIGGER_MASK) == 0x00u)
255 |
256 | #define IS_EXTI_PENDING_EDGE(__LINE__) ((__LINE__) == EXTI_TRIGGER_RISING_FALLING)
257 |
258 | #define IS_EXTI_CONFIG_LINE(__LINE__) (((__LINE__) & EXTI_CONFIG) != 0x00u)
259 |
260 | #if !defined (GPIOD)
261 | #define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \
262 | ((__PORT__) == EXTI_GPIOB) || \
263 | ((__PORT__) == EXTI_GPIOC) || \
264 | ((__PORT__) == EXTI_GPIOH))
265 | #elif !defined (GPIOE)
266 | #define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \
267 | ((__PORT__) == EXTI_GPIOB) || \
268 | ((__PORT__) == EXTI_GPIOC) || \
269 | ((__PORT__) == EXTI_GPIOD) || \
270 | ((__PORT__) == EXTI_GPIOH))
271 | #elif !defined (GPIOF)
272 | #define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \
273 | ((__PORT__) == EXTI_GPIOB) || \
274 | ((__PORT__) == EXTI_GPIOC) || \
275 | ((__PORT__) == EXTI_GPIOD) || \
276 | ((__PORT__) == EXTI_GPIOE) || \
277 | ((__PORT__) == EXTI_GPIOH))
278 | #elif !defined (GPIOI)
279 | #define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \
280 | ((__PORT__) == EXTI_GPIOB) || \
281 | ((__PORT__) == EXTI_GPIOC) || \
282 | ((__PORT__) == EXTI_GPIOD) || \
283 | ((__PORT__) == EXTI_GPIOE) || \
284 | ((__PORT__) == EXTI_GPIOF) || \
285 | ((__PORT__) == EXTI_GPIOG) || \
286 | ((__PORT__) == EXTI_GPIOH))
287 | #elif !defined (GPIOJ)
288 | #define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \
289 | ((__PORT__) == EXTI_GPIOB) || \
290 | ((__PORT__) == EXTI_GPIOC) || \
291 | ((__PORT__) == EXTI_GPIOD) || \
292 | ((__PORT__) == EXTI_GPIOE) || \
293 | ((__PORT__) == EXTI_GPIOF) || \
294 | ((__PORT__) == EXTI_GPIOG) || \
295 | ((__PORT__) == EXTI_GPIOH) || \
296 | ((__PORT__) == EXTI_GPIOI))
297 | #else
298 | #define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \
299 | ((__PORT__) == EXTI_GPIOB) || \
300 | ((__PORT__) == EXTI_GPIOC) || \
301 | ((__PORT__) == EXTI_GPIOD) || \
302 | ((__PORT__) == EXTI_GPIOE) || \
303 | ((__PORT__) == EXTI_GPIOF) || \
304 | ((__PORT__) == EXTI_GPIOG) || \
305 | ((__PORT__) == EXTI_GPIOH) || \
306 | ((__PORT__) == EXTI_GPIOI) || \
307 | ((__PORT__) == EXTI_GPIOJ) || \
308 | ((__PORT__) == EXTI_GPIOK))
309 | #endif /* GPIOD */
310 |
311 | #define IS_EXTI_GPIO_PIN(__PIN__) ((__PIN__) < 16U)
312 | /**
313 | * @}
314 | */
315 |
316 | /* Exported functions --------------------------------------------------------*/
317 | /** @defgroup EXTI_Exported_Functions EXTI Exported Functions
318 | * @brief EXTI Exported Functions
319 | * @{
320 | */
321 |
322 | /** @defgroup EXTI_Exported_Functions_Group1 Configuration functions
323 | * @brief Configuration functions
324 | * @{
325 | */
326 | /* Configuration functions ****************************************************/
327 | HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig);
328 | HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig);
329 | HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti);
330 | HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, void (*pPendingCbfn)(void));
331 | HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine);
332 | /**
333 | * @}
334 | */
335 |
336 | /** @defgroup EXTI_Exported_Functions_Group2 IO operation functions
337 | * @brief IO operation functions
338 | * @{
339 | */
340 | /* IO operation functions *****************************************************/
341 | void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti);
342 | uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge);
343 | void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge);
344 | void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti);
345 |
346 | /**
347 | * @}
348 | */
349 |
350 | /**
351 | * @}
352 | */
353 |
354 | /**
355 | * @}
356 | */
357 |
358 | /**
359 | * @}
360 | */
361 |
362 | #ifdef __cplusplus
363 | }
364 | #endif
365 |
366 | #endif /* STM32f4xx_HAL_EXTI_H */
367 |
368 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
369 |
--------------------------------------------------------------------------------
/nucleo-f446re/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file stm32f4xx_hal_flash_ramfunc.h
4 | * @author MCD Application Team
5 | * @brief Header file of FLASH RAMFUNC driver.
6 | ******************************************************************************
7 | * @attention
8 | *
9 | * © Copyright (c) 2017 STMicroelectronics.
10 | * All rights reserved.
11 | *
12 | * This software component is licensed by ST under BSD 3-Clause license,
13 | * the "License"; You may not use this file except in compliance with the
14 | * License. You may obtain a copy of the License at:
15 | * opensource.org/licenses/BSD-3-Clause
16 | *
17 | ******************************************************************************
18 | */
19 |
20 | /* Define to prevent recursive inclusion -------------------------------------*/
21 | #ifndef __STM32F4xx_FLASH_RAMFUNC_H
22 | #define __STM32F4xx_FLASH_RAMFUNC_H
23 |
24 | #ifdef __cplusplus
25 | extern "C" {
26 | #endif
27 | #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) ||\
28 | defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx)
29 |
30 | /* Includes ------------------------------------------------------------------*/
31 | #include "stm32f4xx_hal_def.h"
32 |
33 | /** @addtogroup STM32F4xx_HAL_Driver
34 | * @{
35 | */
36 |
37 | /** @addtogroup FLASH_RAMFUNC
38 | * @{
39 | */
40 |
41 | /* Exported types ------------------------------------------------------------*/
42 | /* Exported macro ------------------------------------------------------------*/
43 | /* Exported functions --------------------------------------------------------*/
44 | /** @addtogroup FLASH_RAMFUNC_Exported_Functions
45 | * @{
46 | */
47 |
48 | /** @addtogroup FLASH_RAMFUNC_Exported_Functions_Group1
49 | * @{
50 | */
51 | __RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_StopFlashInterfaceClk(void);
52 | __RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_StartFlashInterfaceClk(void);
53 | __RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_EnableFlashSleepMode(void);
54 | __RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_DisableFlashSleepMode(void);
55 | /**
56 | * @}
57 | */
58 |
59 | /**
60 | * @}
61 | */
62 |
63 | /**
64 | * @}
65 | */
66 |
67 | /**
68 | * @}
69 | */
70 |
71 | #endif /* STM32F410xx || STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
72 | #ifdef __cplusplus
73 | }
74 | #endif
75 |
76 |
77 | #endif /* __STM32F4xx_FLASH_RAMFUNC_H */
78 |
79 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
80 |
--------------------------------------------------------------------------------
/nucleo-f446re/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file stm32f4xx_hal_gpio.h
4 | * @author MCD Application Team
5 | * @brief Header file of GPIO HAL module.
6 | ******************************************************************************
7 | * @attention
8 | *
9 | * © Copyright (c) 2017 STMicroelectronics.
10 | * All rights reserved.
11 | *
12 | * This software component is licensed by ST under BSD 3-Clause license,
13 | * the "License"; You may not use this file except in compliance with the
14 | * License. You may obtain a copy of the License at:
15 | * opensource.org/licenses/BSD-3-Clause
16 | *
17 | ******************************************************************************
18 | */
19 |
20 | /* Define to prevent recursive inclusion -------------------------------------*/
21 | #ifndef __STM32F4xx_HAL_GPIO_H
22 | #define __STM32F4xx_HAL_GPIO_H
23 |
24 | #ifdef __cplusplus
25 | extern "C" {
26 | #endif
27 |
28 | /* Includes ------------------------------------------------------------------*/
29 | #include "stm32f4xx_hal_def.h"
30 |
31 | /** @addtogroup STM32F4xx_HAL_Driver
32 | * @{
33 | */
34 |
35 | /** @addtogroup GPIO
36 | * @{
37 | */
38 |
39 | /* Exported types ------------------------------------------------------------*/
40 | /** @defgroup GPIO_Exported_Types GPIO Exported Types
41 | * @{
42 | */
43 |
44 | /**
45 | * @brief GPIO Init structure definition
46 | */
47 | typedef struct
48 | {
49 | uint32_t Pin; /*!< Specifies the GPIO pins to be configured.
50 | This parameter can be any value of @ref GPIO_pins_define */
51 |
52 | uint32_t Mode; /*!< Specifies the operating mode for the selected pins.
53 | This parameter can be a value of @ref GPIO_mode_define */
54 |
55 | uint32_t Pull; /*!< Specifies the Pull-up or Pull-Down activation for the selected pins.
56 | This parameter can be a value of @ref GPIO_pull_define */
57 |
58 | uint32_t Speed; /*!< Specifies the speed for the selected pins.
59 | This parameter can be a value of @ref GPIO_speed_define */
60 |
61 | uint32_t Alternate; /*!< Peripheral to be connected to the selected pins.
62 | This parameter can be a value of @ref GPIO_Alternate_function_selection */
63 | }GPIO_InitTypeDef;
64 |
65 | /**
66 | * @brief GPIO Bit SET and Bit RESET enumeration
67 | */
68 | typedef enum
69 | {
70 | GPIO_PIN_RESET = 0,
71 | GPIO_PIN_SET
72 | }GPIO_PinState;
73 | /**
74 | * @}
75 | */
76 |
77 | /* Exported constants --------------------------------------------------------*/
78 |
79 | /** @defgroup GPIO_Exported_Constants GPIO Exported Constants
80 | * @{
81 | */
82 |
83 | /** @defgroup GPIO_pins_define GPIO pins define
84 | * @{
85 | */
86 | #define GPIO_PIN_0 ((uint16_t)0x0001) /* Pin 0 selected */
87 | #define GPIO_PIN_1 ((uint16_t)0x0002) /* Pin 1 selected */
88 | #define GPIO_PIN_2 ((uint16_t)0x0004) /* Pin 2 selected */
89 | #define GPIO_PIN_3 ((uint16_t)0x0008) /* Pin 3 selected */
90 | #define GPIO_PIN_4 ((uint16_t)0x0010) /* Pin 4 selected */
91 | #define GPIO_PIN_5 ((uint16_t)0x0020) /* Pin 5 selected */
92 | #define GPIO_PIN_6 ((uint16_t)0x0040) /* Pin 6 selected */
93 | #define GPIO_PIN_7 ((uint16_t)0x0080) /* Pin 7 selected */
94 | #define GPIO_PIN_8 ((uint16_t)0x0100) /* Pin 8 selected */
95 | #define GPIO_PIN_9 ((uint16_t)0x0200) /* Pin 9 selected */
96 | #define GPIO_PIN_10 ((uint16_t)0x0400) /* Pin 10 selected */
97 | #define GPIO_PIN_11 ((uint16_t)0x0800) /* Pin 11 selected */
98 | #define GPIO_PIN_12 ((uint16_t)0x1000) /* Pin 12 selected */
99 | #define GPIO_PIN_13 ((uint16_t)0x2000) /* Pin 13 selected */
100 | #define GPIO_PIN_14 ((uint16_t)0x4000) /* Pin 14 selected */
101 | #define GPIO_PIN_15 ((uint16_t)0x8000) /* Pin 15 selected */
102 | #define GPIO_PIN_All ((uint16_t)0xFFFF) /* All pins selected */
103 |
104 | #define GPIO_PIN_MASK 0x0000FFFFU /* PIN mask for assert test */
105 | /**
106 | * @}
107 | */
108 |
109 | /** @defgroup GPIO_mode_define GPIO mode define
110 | * @brief GPIO Configuration Mode
111 | * Elements values convention: 0xX0yz00YZ
112 | * - X : GPIO mode or EXTI Mode
113 | * - y : External IT or Event trigger detection
114 | * - z : IO configuration on External IT or Event
115 | * - Y : Output type (Push Pull or Open Drain)
116 | * - Z : IO Direction mode (Input, Output, Alternate or Analog)
117 | * @{
118 | */
119 | #define GPIO_MODE_INPUT 0x00000000U /*!< Input Floating Mode */
120 | #define GPIO_MODE_OUTPUT_PP 0x00000001U /*!< Output Push Pull Mode */
121 | #define GPIO_MODE_OUTPUT_OD 0x00000011U /*!< Output Open Drain Mode */
122 | #define GPIO_MODE_AF_PP 0x00000002U /*!< Alternate Function Push Pull Mode */
123 | #define GPIO_MODE_AF_OD 0x00000012U /*!< Alternate Function Open Drain Mode */
124 |
125 | #define GPIO_MODE_ANALOG 0x00000003U /*!< Analog Mode */
126 |
127 | #define GPIO_MODE_IT_RISING 0x10110000U /*!< External Interrupt Mode with Rising edge trigger detection */
128 | #define GPIO_MODE_IT_FALLING 0x10210000U /*!< External Interrupt Mode with Falling edge trigger detection */
129 | #define GPIO_MODE_IT_RISING_FALLING 0x10310000U /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
130 |
131 | #define GPIO_MODE_EVT_RISING 0x10120000U /*!< External Event Mode with Rising edge trigger detection */
132 | #define GPIO_MODE_EVT_FALLING 0x10220000U /*!< External Event Mode with Falling edge trigger detection */
133 | #define GPIO_MODE_EVT_RISING_FALLING 0x10320000U /*!< External Event Mode with Rising/Falling edge trigger detection */
134 | /**
135 | * @}
136 | */
137 |
138 | /** @defgroup GPIO_speed_define GPIO speed define
139 | * @brief GPIO Output Maximum frequency
140 | * @{
141 | */
142 | #define GPIO_SPEED_FREQ_LOW 0x00000000U /*!< IO works at 2 MHz, please refer to the product datasheet */
143 | #define GPIO_SPEED_FREQ_MEDIUM 0x00000001U /*!< range 12,5 MHz to 50 MHz, please refer to the product datasheet */
144 | #define GPIO_SPEED_FREQ_HIGH 0x00000002U /*!< range 25 MHz to 100 MHz, please refer to the product datasheet */
145 | #define GPIO_SPEED_FREQ_VERY_HIGH 0x00000003U /*!< range 50 MHz to 200 MHz, please refer to the product datasheet */
146 | /**
147 | * @}
148 | */
149 |
150 | /** @defgroup GPIO_pull_define GPIO pull define
151 | * @brief GPIO Pull-Up or Pull-Down Activation
152 | * @{
153 | */
154 | #define GPIO_NOPULL 0x00000000U /*!< No Pull-up or Pull-down activation */
155 | #define GPIO_PULLUP 0x00000001U /*!< Pull-up activation */
156 | #define GPIO_PULLDOWN 0x00000002U /*!< Pull-down activation */
157 | /**
158 | * @}
159 | */
160 |
161 | /**
162 | * @}
163 | */
164 |
165 | /* Exported macro ------------------------------------------------------------*/
166 | /** @defgroup GPIO_Exported_Macros GPIO Exported Macros
167 | * @{
168 | */
169 |
170 | /**
171 | * @brief Checks whether the specified EXTI line flag is set or not.
172 | * @param __EXTI_LINE__ specifies the EXTI line flag to check.
173 | * This parameter can be GPIO_PIN_x where x can be(0..15)
174 | * @retval The new state of __EXTI_LINE__ (SET or RESET).
175 | */
176 | #define __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__))
177 |
178 | /**
179 | * @brief Clears the EXTI's line pending flags.
180 | * @param __EXTI_LINE__ specifies the EXTI lines flags to clear.
181 | * This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
182 | * @retval None
183 | */
184 | #define __HAL_GPIO_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__))
185 |
186 | /**
187 | * @brief Checks whether the specified EXTI line is asserted or not.
188 | * @param __EXTI_LINE__ specifies the EXTI line to check.
189 | * This parameter can be GPIO_PIN_x where x can be(0..15)
190 | * @retval The new state of __EXTI_LINE__ (SET or RESET).
191 | */
192 | #define __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__))
193 |
194 | /**
195 | * @brief Clears the EXTI's line pending bits.
196 | * @param __EXTI_LINE__ specifies the EXTI lines to clear.
197 | * This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
198 | * @retval None
199 | */
200 | #define __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__))
201 |
202 | /**
203 | * @brief Generates a Software interrupt on selected EXTI line.
204 | * @param __EXTI_LINE__ specifies the EXTI line to check.
205 | * This parameter can be GPIO_PIN_x where x can be(0..15)
206 | * @retval None
207 | */
208 | #define __HAL_GPIO_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER |= (__EXTI_LINE__))
209 | /**
210 | * @}
211 | */
212 |
213 | /* Include GPIO HAL Extension module */
214 | #include "stm32f4xx_hal_gpio_ex.h"
215 |
216 | /* Exported functions --------------------------------------------------------*/
217 | /** @addtogroup GPIO_Exported_Functions
218 | * @{
219 | */
220 |
221 | /** @addtogroup GPIO_Exported_Functions_Group1
222 | * @{
223 | */
224 | /* Initialization and de-initialization functions *****************************/
225 | void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init);
226 | void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin);
227 | /**
228 | * @}
229 | */
230 |
231 | /** @addtogroup GPIO_Exported_Functions_Group2
232 | * @{
233 | */
234 | /* IO operation functions *****************************************************/
235 | GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
236 | void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState);
237 | void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
238 | HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
239 | void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin);
240 | void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin);
241 |
242 | /**
243 | * @}
244 | */
245 |
246 | /**
247 | * @}
248 | */
249 | /* Private types -------------------------------------------------------------*/
250 | /* Private variables ---------------------------------------------------------*/
251 | /* Private constants ---------------------------------------------------------*/
252 | /** @defgroup GPIO_Private_Constants GPIO Private Constants
253 | * @{
254 | */
255 |
256 | /**
257 | * @}
258 | */
259 |
260 | /* Private macros ------------------------------------------------------------*/
261 | /** @defgroup GPIO_Private_Macros GPIO Private Macros
262 | * @{
263 | */
264 | #define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET))
265 | #define IS_GPIO_PIN(PIN) (((((uint32_t)PIN) & GPIO_PIN_MASK ) != 0x00U) && ((((uint32_t)PIN) & ~GPIO_PIN_MASK) == 0x00U))
266 | #define IS_GPIO_MODE(MODE) (((MODE) == GPIO_MODE_INPUT) ||\
267 | ((MODE) == GPIO_MODE_OUTPUT_PP) ||\
268 | ((MODE) == GPIO_MODE_OUTPUT_OD) ||\
269 | ((MODE) == GPIO_MODE_AF_PP) ||\
270 | ((MODE) == GPIO_MODE_AF_OD) ||\
271 | ((MODE) == GPIO_MODE_IT_RISING) ||\
272 | ((MODE) == GPIO_MODE_IT_FALLING) ||\
273 | ((MODE) == GPIO_MODE_IT_RISING_FALLING) ||\
274 | ((MODE) == GPIO_MODE_EVT_RISING) ||\
275 | ((MODE) == GPIO_MODE_EVT_FALLING) ||\
276 | ((MODE) == GPIO_MODE_EVT_RISING_FALLING) ||\
277 | ((MODE) == GPIO_MODE_ANALOG))
278 | #define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_SPEED_FREQ_LOW) || ((SPEED) == GPIO_SPEED_FREQ_MEDIUM) || \
279 | ((SPEED) == GPIO_SPEED_FREQ_HIGH) || ((SPEED) == GPIO_SPEED_FREQ_VERY_HIGH))
280 | #define IS_GPIO_PULL(PULL) (((PULL) == GPIO_NOPULL) || ((PULL) == GPIO_PULLUP) || \
281 | ((PULL) == GPIO_PULLDOWN))
282 | /**
283 | * @}
284 | */
285 |
286 | /* Private functions ---------------------------------------------------------*/
287 | /** @defgroup GPIO_Private_Functions GPIO Private Functions
288 | * @{
289 | */
290 |
291 | /**
292 | * @}
293 | */
294 |
295 | /**
296 | * @}
297 | */
298 |
299 | /**
300 | * @}
301 | */
302 |
303 | #ifdef __cplusplus
304 | }
305 | #endif
306 |
307 | #endif /* __STM32F4xx_HAL_GPIO_H */
308 |
309 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
310 |
--------------------------------------------------------------------------------
/nucleo-f446re/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file stm32f4xx_hal_pwr.h
4 | * @author MCD Application Team
5 | * @brief Header file of PWR HAL module.
6 | ******************************************************************************
7 | * @attention
8 | *
9 | * © Copyright (c) 2017 STMicroelectronics.
10 | * All rights reserved.
11 | *
12 | * This software component is licensed by ST under BSD 3-Clause license,
13 | * the "License"; You may not use this file except in compliance with the
14 | * License. You may obtain a copy of the License at:
15 | * opensource.org/licenses/BSD-3-Clause
16 | *
17 | ******************************************************************************
18 | */
19 |
20 | /* Define to prevent recursive inclusion -------------------------------------*/
21 | #ifndef __STM32F4xx_HAL_PWR_H
22 | #define __STM32F4xx_HAL_PWR_H
23 |
24 | #ifdef __cplusplus
25 | extern "C" {
26 | #endif
27 |
28 | /* Includes ------------------------------------------------------------------*/
29 | #include "stm32f4xx_hal_def.h"
30 |
31 | /** @addtogroup STM32F4xx_HAL_Driver
32 | * @{
33 | */
34 |
35 | /** @addtogroup PWR
36 | * @{
37 | */
38 |
39 | /* Exported types ------------------------------------------------------------*/
40 |
41 | /** @defgroup PWR_Exported_Types PWR Exported Types
42 | * @{
43 | */
44 |
45 | /**
46 | * @brief PWR PVD configuration structure definition
47 | */
48 | typedef struct
49 | {
50 | uint32_t PVDLevel; /*!< PVDLevel: Specifies the PVD detection level.
51 | This parameter can be a value of @ref PWR_PVD_detection_level */
52 |
53 | uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins.
54 | This parameter can be a value of @ref PWR_PVD_Mode */
55 | }PWR_PVDTypeDef;
56 |
57 | /**
58 | * @}
59 | */
60 |
61 | /* Exported constants --------------------------------------------------------*/
62 | /** @defgroup PWR_Exported_Constants PWR Exported Constants
63 | * @{
64 | */
65 |
66 | /** @defgroup PWR_WakeUp_Pins PWR WakeUp Pins
67 | * @{
68 | */
69 | #define PWR_WAKEUP_PIN1 0x00000100U
70 | /**
71 | * @}
72 | */
73 |
74 | /** @defgroup PWR_PVD_detection_level PWR PVD detection level
75 | * @{
76 | */
77 | #define PWR_PVDLEVEL_0 PWR_CR_PLS_LEV0
78 | #define PWR_PVDLEVEL_1 PWR_CR_PLS_LEV1
79 | #define PWR_PVDLEVEL_2 PWR_CR_PLS_LEV2
80 | #define PWR_PVDLEVEL_3 PWR_CR_PLS_LEV3
81 | #define PWR_PVDLEVEL_4 PWR_CR_PLS_LEV4
82 | #define PWR_PVDLEVEL_5 PWR_CR_PLS_LEV5
83 | #define PWR_PVDLEVEL_6 PWR_CR_PLS_LEV6
84 | #define PWR_PVDLEVEL_7 PWR_CR_PLS_LEV7/* External input analog voltage
85 | (Compare internally to VREFINT) */
86 | /**
87 | * @}
88 | */
89 |
90 | /** @defgroup PWR_PVD_Mode PWR PVD Mode
91 | * @{
92 | */
93 | #define PWR_PVD_MODE_NORMAL 0x00000000U /*!< basic mode is used */
94 | #define PWR_PVD_MODE_IT_RISING 0x00010001U /*!< External Interrupt Mode with Rising edge trigger detection */
95 | #define PWR_PVD_MODE_IT_FALLING 0x00010002U /*!< External Interrupt Mode with Falling edge trigger detection */
96 | #define PWR_PVD_MODE_IT_RISING_FALLING 0x00010003U /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
97 | #define PWR_PVD_MODE_EVENT_RISING 0x00020001U /*!< Event Mode with Rising edge trigger detection */
98 | #define PWR_PVD_MODE_EVENT_FALLING 0x00020002U /*!< Event Mode with Falling edge trigger detection */
99 | #define PWR_PVD_MODE_EVENT_RISING_FALLING 0x00020003U /*!< Event Mode with Rising/Falling edge trigger detection */
100 | /**
101 | * @}
102 | */
103 |
104 |
105 | /** @defgroup PWR_Regulator_state_in_STOP_mode PWR Regulator state in SLEEP/STOP mode
106 | * @{
107 | */
108 | #define PWR_MAINREGULATOR_ON 0x00000000U
109 | #define PWR_LOWPOWERREGULATOR_ON PWR_CR_LPDS
110 | /**
111 | * @}
112 | */
113 |
114 | /** @defgroup PWR_SLEEP_mode_entry PWR SLEEP mode entry
115 | * @{
116 | */
117 | #define PWR_SLEEPENTRY_WFI ((uint8_t)0x01)
118 | #define PWR_SLEEPENTRY_WFE ((uint8_t)0x02)
119 | /**
120 | * @}
121 | */
122 |
123 | /** @defgroup PWR_STOP_mode_entry PWR STOP mode entry
124 | * @{
125 | */
126 | #define PWR_STOPENTRY_WFI ((uint8_t)0x01)
127 | #define PWR_STOPENTRY_WFE ((uint8_t)0x02)
128 | /**
129 | * @}
130 | */
131 |
132 | /** @defgroup PWR_Flag PWR Flag
133 | * @{
134 | */
135 | #define PWR_FLAG_WU PWR_CSR_WUF
136 | #define PWR_FLAG_SB PWR_CSR_SBF
137 | #define PWR_FLAG_PVDO PWR_CSR_PVDO
138 | #define PWR_FLAG_BRR PWR_CSR_BRR
139 | #define PWR_FLAG_VOSRDY PWR_CSR_VOSRDY
140 | /**
141 | * @}
142 | */
143 |
144 | /**
145 | * @}
146 | */
147 |
148 | /* Exported macro ------------------------------------------------------------*/
149 | /** @defgroup PWR_Exported_Macro PWR Exported Macro
150 | * @{
151 | */
152 |
153 | /** @brief Check PWR flag is set or not.
154 | * @param __FLAG__ specifies the flag to check.
155 | * This parameter can be one of the following values:
156 | * @arg PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup event
157 | * was received from the WKUP pin or from the RTC alarm (Alarm A
158 | * or Alarm B), RTC Tamper event, RTC TimeStamp event or RTC Wakeup.
159 | * An additional wakeup event is detected if the WKUP pin is enabled
160 | * (by setting the EWUP bit) when the WKUP pin level is already high.
161 | * @arg PWR_FLAG_SB: StandBy flag. This flag indicates that the system was
162 | * resumed from StandBy mode.
163 | * @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled
164 | * by the HAL_PWR_EnablePVD() function. The PVD is stopped by Standby mode
165 | * For this reason, this bit is equal to 0 after Standby or reset
166 | * until the PVDE bit is set.
167 | * @arg PWR_FLAG_BRR: Backup regulator ready flag. This bit is not reset
168 | * when the device wakes up from Standby mode or by a system reset
169 | * or power reset.
170 | * @arg PWR_FLAG_VOSRDY: This flag indicates that the Regulator voltage
171 | * scaling output selection is ready.
172 | * @retval The new state of __FLAG__ (TRUE or FALSE).
173 | */
174 | #define __HAL_PWR_GET_FLAG(__FLAG__) ((PWR->CSR & (__FLAG__)) == (__FLAG__))
175 |
176 | /** @brief Clear the PWR's pending flags.
177 | * @param __FLAG__ specifies the flag to clear.
178 | * This parameter can be one of the following values:
179 | * @arg PWR_FLAG_WU: Wake Up flag
180 | * @arg PWR_FLAG_SB: StandBy flag
181 | */
182 | #define __HAL_PWR_CLEAR_FLAG(__FLAG__) (PWR->CR |= (__FLAG__) << 2U)
183 |
184 | /**
185 | * @brief Enable the PVD Exti Line 16.
186 | * @retval None.
187 | */
188 | #define __HAL_PWR_PVD_EXTI_ENABLE_IT() (EXTI->IMR |= (PWR_EXTI_LINE_PVD))
189 |
190 | /**
191 | * @brief Disable the PVD EXTI Line 16.
192 | * @retval None.
193 | */
194 | #define __HAL_PWR_PVD_EXTI_DISABLE_IT() (EXTI->IMR &= ~(PWR_EXTI_LINE_PVD))
195 |
196 | /**
197 | * @brief Enable event on PVD Exti Line 16.
198 | * @retval None.
199 | */
200 | #define __HAL_PWR_PVD_EXTI_ENABLE_EVENT() (EXTI->EMR |= (PWR_EXTI_LINE_PVD))
201 |
202 | /**
203 | * @brief Disable event on PVD Exti Line 16.
204 | * @retval None.
205 | */
206 | #define __HAL_PWR_PVD_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~(PWR_EXTI_LINE_PVD))
207 |
208 | /**
209 | * @brief Enable the PVD Extended Interrupt Rising Trigger.
210 | * @retval None.
211 | */
212 | #define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD)
213 |
214 | /**
215 | * @brief Disable the PVD Extended Interrupt Rising Trigger.
216 | * @retval None.
217 | */
218 | #define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD)
219 |
220 | /**
221 | * @brief Enable the PVD Extended Interrupt Falling Trigger.
222 | * @retval None.
223 | */
224 | #define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD)
225 |
226 |
227 | /**
228 | * @brief Disable the PVD Extended Interrupt Falling Trigger.
229 | * @retval None.
230 | */
231 | #define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD)
232 |
233 |
234 | /**
235 | * @brief PVD EXTI line configuration: set rising & falling edge trigger.
236 | * @retval None.
237 | */
238 | #define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() do{__HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();\
239 | __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();\
240 | }while(0U)
241 |
242 | /**
243 | * @brief Disable the PVD Extended Interrupt Rising & Falling Trigger.
244 | * This parameter can be:
245 | * @retval None.
246 | */
247 | #define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE() do{__HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();\
248 | __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();\
249 | }while(0U)
250 |
251 | /**
252 | * @brief checks whether the specified PVD Exti interrupt flag is set or not.
253 | * @retval EXTI PVD Line Status.
254 | */
255 | #define __HAL_PWR_PVD_EXTI_GET_FLAG() (EXTI->PR & (PWR_EXTI_LINE_PVD))
256 |
257 | /**
258 | * @brief Clear the PVD Exti flag.
259 | * @retval None.
260 | */
261 | #define __HAL_PWR_PVD_EXTI_CLEAR_FLAG() (EXTI->PR = (PWR_EXTI_LINE_PVD))
262 |
263 | /**
264 | * @brief Generates a Software interrupt on PVD EXTI line.
265 | * @retval None
266 | */
267 | #define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() (EXTI->SWIER |= (PWR_EXTI_LINE_PVD))
268 |
269 | /**
270 | * @}
271 | */
272 |
273 | /* Include PWR HAL Extension module */
274 | #include "stm32f4xx_hal_pwr_ex.h"
275 |
276 | /* Exported functions --------------------------------------------------------*/
277 | /** @addtogroup PWR_Exported_Functions PWR Exported Functions
278 | * @{
279 | */
280 |
281 | /** @addtogroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions
282 | * @{
283 | */
284 | /* Initialization and de-initialization functions *****************************/
285 | void HAL_PWR_DeInit(void);
286 | void HAL_PWR_EnableBkUpAccess(void);
287 | void HAL_PWR_DisableBkUpAccess(void);
288 | /**
289 | * @}
290 | */
291 |
292 | /** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control functions
293 | * @{
294 | */
295 | /* Peripheral Control functions **********************************************/
296 | /* PVD configuration */
297 | void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD);
298 | void HAL_PWR_EnablePVD(void);
299 | void HAL_PWR_DisablePVD(void);
300 |
301 | /* WakeUp pins configuration */
302 | void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx);
303 | void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx);
304 |
305 | /* Low Power modes entry */
306 | void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry);
307 | void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry);
308 | void HAL_PWR_EnterSTANDBYMode(void);
309 |
310 | /* Power PVD IRQ Handler */
311 | void HAL_PWR_PVD_IRQHandler(void);
312 | void HAL_PWR_PVDCallback(void);
313 |
314 | /* Cortex System Control functions *******************************************/
315 | void HAL_PWR_EnableSleepOnExit(void);
316 | void HAL_PWR_DisableSleepOnExit(void);
317 | void HAL_PWR_EnableSEVOnPend(void);
318 | void HAL_PWR_DisableSEVOnPend(void);
319 | /**
320 | * @}
321 | */
322 |
323 | /**
324 | * @}
325 | */
326 |
327 | /* Private types -------------------------------------------------------------*/
328 | /* Private variables ---------------------------------------------------------*/
329 | /* Private constants ---------------------------------------------------------*/
330 | /** @defgroup PWR_Private_Constants PWR Private Constants
331 | * @{
332 | */
333 |
334 | /** @defgroup PWR_PVD_EXTI_Line PWR PVD EXTI Line
335 | * @{
336 | */
337 | #define PWR_EXTI_LINE_PVD ((uint32_t)EXTI_IMR_MR16) /*!< External interrupt line 16 Connected to the PVD EXTI Line */
338 | /**
339 | * @}
340 | */
341 |
342 | /** @defgroup PWR_register_alias_address PWR Register alias address
343 | * @{
344 | */
345 | /* ------------- PWR registers bit address in the alias region ---------------*/
346 | #define PWR_OFFSET (PWR_BASE - PERIPH_BASE)
347 | #define PWR_CR_OFFSET 0x00U
348 | #define PWR_CSR_OFFSET 0x04U
349 | #define PWR_CR_OFFSET_BB (PWR_OFFSET + PWR_CR_OFFSET)
350 | #define PWR_CSR_OFFSET_BB (PWR_OFFSET + PWR_CSR_OFFSET)
351 | /**
352 | * @}
353 | */
354 |
355 | /** @defgroup PWR_CR_register_alias PWR CR Register alias address
356 | * @{
357 | */
358 | /* --- CR Register ---*/
359 | /* Alias word address of DBP bit */
360 | #define DBP_BIT_NUMBER PWR_CR_DBP_Pos
361 | #define CR_DBP_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (DBP_BIT_NUMBER * 4U))
362 |
363 | /* Alias word address of PVDE bit */
364 | #define PVDE_BIT_NUMBER PWR_CR_PVDE_Pos
365 | #define CR_PVDE_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (PVDE_BIT_NUMBER * 4U))
366 |
367 | /* Alias word address of VOS bit */
368 | #define VOS_BIT_NUMBER PWR_CR_VOS_Pos
369 | #define CR_VOS_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (VOS_BIT_NUMBER * 4U))
370 | /**
371 | * @}
372 | */
373 |
374 | /** @defgroup PWR_CSR_register_alias PWR CSR Register alias address
375 | * @{
376 | */
377 | /* --- CSR Register ---*/
378 | /* Alias word address of EWUP bit */
379 | #define EWUP_BIT_NUMBER PWR_CSR_EWUP_Pos
380 | #define CSR_EWUP_BB (PERIPH_BB_BASE + (PWR_CSR_OFFSET_BB * 32U) + (EWUP_BIT_NUMBER * 4U))
381 | /**
382 | * @}
383 | */
384 |
385 | /**
386 | * @}
387 | */
388 | /* Private macros ------------------------------------------------------------*/
389 | /** @defgroup PWR_Private_Macros PWR Private Macros
390 | * @{
391 | */
392 |
393 | /** @defgroup PWR_IS_PWR_Definitions PWR Private macros to check input parameters
394 | * @{
395 | */
396 | #define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1)|| \
397 | ((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3)|| \
398 | ((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5)|| \
399 | ((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7))
400 | #define IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_PVD_MODE_IT_RISING)|| ((MODE) == PWR_PVD_MODE_IT_FALLING) || \
401 | ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING) || \
402 | ((MODE) == PWR_PVD_MODE_EVENT_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING) || \
403 | ((MODE) == PWR_PVD_MODE_NORMAL))
404 | #define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON) || \
405 | ((REGULATOR) == PWR_LOWPOWERREGULATOR_ON))
406 | #define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE))
407 | #define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE))
408 | /**
409 | * @}
410 | */
411 |
412 | /**
413 | * @}
414 | */
415 |
416 | /**
417 | * @}
418 | */
419 |
420 | /**
421 | * @}
422 | */
423 |
424 | #ifdef __cplusplus
425 | }
426 | #endif
427 |
428 |
429 | #endif /* __STM32F4xx_HAL_PWR_H */
430 |
431 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
432 |
--------------------------------------------------------------------------------
/nucleo-f446re/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file stm32f4xx_hal_dma_ex.c
4 | * @author MCD Application Team
5 | * @brief DMA Extension HAL module driver
6 | * This file provides firmware functions to manage the following
7 | * functionalities of the DMA Extension peripheral:
8 | * + Extended features functions
9 | *
10 | @verbatim
11 | ==============================================================================
12 | ##### How to use this driver #####
13 | ==============================================================================
14 | [..]
15 | The DMA Extension HAL driver can be used as follows:
16 | (#) Start a multi buffer transfer using the HAL_DMA_MultiBufferStart() function
17 | for polling mode or HAL_DMA_MultiBufferStart_IT() for interrupt mode.
18 |
19 | -@- In Memory-to-Memory transfer mode, Multi (Double) Buffer mode is not allowed.
20 | -@- When Multi (Double) Buffer mode is enabled the, transfer is circular by default.
21 | -@- In Multi (Double) buffer mode, it is possible to update the base address for
22 | the AHB memory port on the fly (DMA_SxM0AR or DMA_SxM1AR) when the stream is enabled.
23 |
24 | @endverbatim
25 | ******************************************************************************
26 | * @attention
27 | *
28 | * © Copyright (c) 2017 STMicroelectronics.
29 | * All rights reserved.
30 | *
31 | * This software component is licensed by ST under BSD 3-Clause license,
32 | * the "License"; You may not use this file except in compliance with the
33 | * License. You may obtain a copy of the License at:
34 | * opensource.org/licenses/BSD-3-Clause
35 | *
36 | ******************************************************************************
37 | */
38 |
39 | /* Includes ------------------------------------------------------------------*/
40 | #include "stm32f4xx_hal.h"
41 |
42 | /** @addtogroup STM32F4xx_HAL_Driver
43 | * @{
44 | */
45 |
46 | /** @defgroup DMAEx DMAEx
47 | * @brief DMA Extended HAL module driver
48 | * @{
49 | */
50 |
51 | #ifdef HAL_DMA_MODULE_ENABLED
52 |
53 | /* Private types -------------------------------------------------------------*/
54 | /* Private variables ---------------------------------------------------------*/
55 | /* Private Constants ---------------------------------------------------------*/
56 | /* Private macros ------------------------------------------------------------*/
57 | /* Private functions ---------------------------------------------------------*/
58 | /** @addtogroup DMAEx_Private_Functions
59 | * @{
60 | */
61 | static void DMA_MultiBufferSetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
62 | /**
63 | * @}
64 | */
65 |
66 | /* Exported functions ---------------------------------------------------------*/
67 |
68 | /** @addtogroup DMAEx_Exported_Functions
69 | * @{
70 | */
71 |
72 |
73 | /** @addtogroup DMAEx_Exported_Functions_Group1
74 | *
75 | @verbatim
76 | ===============================================================================
77 | ##### Extended features functions #####
78 | ===============================================================================
79 | [..] This section provides functions allowing to:
80 | (+) Configure the source, destination address and data length and
81 | Start MultiBuffer DMA transfer
82 | (+) Configure the source, destination address and data length and
83 | Start MultiBuffer DMA transfer with interrupt
84 | (+) Change on the fly the memory0 or memory1 address.
85 |
86 | @endverbatim
87 | * @{
88 | */
89 |
90 |
91 | /**
92 | * @brief Starts the multi_buffer DMA Transfer.
93 | * @param hdma pointer to a DMA_HandleTypeDef structure that contains
94 | * the configuration information for the specified DMA Stream.
95 | * @param SrcAddress The source memory Buffer address
96 | * @param DstAddress The destination memory Buffer address
97 | * @param SecondMemAddress The second memory Buffer address in case of multi buffer Transfer
98 | * @param DataLength The length of data to be transferred from source to destination
99 | * @retval HAL status
100 | */
101 | HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength)
102 | {
103 | HAL_StatusTypeDef status = HAL_OK;
104 |
105 | /* Check the parameters */
106 | assert_param(IS_DMA_BUFFER_SIZE(DataLength));
107 |
108 | /* Memory-to-memory transfer not supported in double buffering mode */
109 | if (hdma->Init.Direction == DMA_MEMORY_TO_MEMORY)
110 | {
111 | hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED;
112 | status = HAL_ERROR;
113 | }
114 | else
115 | {
116 | /* Process Locked */
117 | __HAL_LOCK(hdma);
118 |
119 | if(HAL_DMA_STATE_READY == hdma->State)
120 | {
121 | /* Change DMA peripheral state */
122 | hdma->State = HAL_DMA_STATE_BUSY;
123 |
124 | /* Enable the double buffer mode */
125 | hdma->Instance->CR |= (uint32_t)DMA_SxCR_DBM;
126 |
127 | /* Configure DMA Stream destination address */
128 | hdma->Instance->M1AR = SecondMemAddress;
129 |
130 | /* Configure the source, destination address and the data length */
131 | DMA_MultiBufferSetConfig(hdma, SrcAddress, DstAddress, DataLength);
132 |
133 | /* Enable the peripheral */
134 | __HAL_DMA_ENABLE(hdma);
135 | }
136 | else
137 | {
138 | /* Return error status */
139 | status = HAL_BUSY;
140 | }
141 | }
142 | return status;
143 | }
144 |
145 | /**
146 | * @brief Starts the multi_buffer DMA Transfer with interrupt enabled.
147 | * @param hdma pointer to a DMA_HandleTypeDef structure that contains
148 | * the configuration information for the specified DMA Stream.
149 | * @param SrcAddress The source memory Buffer address
150 | * @param DstAddress The destination memory Buffer address
151 | * @param SecondMemAddress The second memory Buffer address in case of multi buffer Transfer
152 | * @param DataLength The length of data to be transferred from source to destination
153 | * @retval HAL status
154 | */
155 | HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength)
156 | {
157 | HAL_StatusTypeDef status = HAL_OK;
158 |
159 | /* Check the parameters */
160 | assert_param(IS_DMA_BUFFER_SIZE(DataLength));
161 |
162 | /* Memory-to-memory transfer not supported in double buffering mode */
163 | if (hdma->Init.Direction == DMA_MEMORY_TO_MEMORY)
164 | {
165 | hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED;
166 | return HAL_ERROR;
167 | }
168 |
169 | /* Check callback functions */
170 | if ((NULL == hdma->XferCpltCallback) || (NULL == hdma->XferM1CpltCallback) || (NULL == hdma->XferErrorCallback))
171 | {
172 | hdma->ErrorCode = HAL_DMA_ERROR_PARAM;
173 | return HAL_ERROR;
174 | }
175 |
176 | /* Process locked */
177 | __HAL_LOCK(hdma);
178 |
179 | if(HAL_DMA_STATE_READY == hdma->State)
180 | {
181 | /* Change DMA peripheral state */
182 | hdma->State = HAL_DMA_STATE_BUSY;
183 |
184 | /* Initialize the error code */
185 | hdma->ErrorCode = HAL_DMA_ERROR_NONE;
186 |
187 | /* Enable the Double buffer mode */
188 | hdma->Instance->CR |= (uint32_t)DMA_SxCR_DBM;
189 |
190 | /* Configure DMA Stream destination address */
191 | hdma->Instance->M1AR = SecondMemAddress;
192 |
193 | /* Configure the source, destination address and the data length */
194 | DMA_MultiBufferSetConfig(hdma, SrcAddress, DstAddress, DataLength);
195 |
196 | /* Clear all flags */
197 | __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma));
198 | __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
199 | __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma));
200 | __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma));
201 | __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma));
202 |
203 | /* Enable Common interrupts*/
204 | hdma->Instance->CR |= DMA_IT_TC | DMA_IT_TE | DMA_IT_DME;
205 | hdma->Instance->FCR |= DMA_IT_FE;
206 |
207 | if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL))
208 | {
209 | hdma->Instance->CR |= DMA_IT_HT;
210 | }
211 |
212 | /* Enable the peripheral */
213 | __HAL_DMA_ENABLE(hdma);
214 | }
215 | else
216 | {
217 | /* Process unlocked */
218 | __HAL_UNLOCK(hdma);
219 |
220 | /* Return error status */
221 | status = HAL_BUSY;
222 | }
223 | return status;
224 | }
225 |
226 | /**
227 | * @brief Change the memory0 or memory1 address on the fly.
228 | * @param hdma pointer to a DMA_HandleTypeDef structure that contains
229 | * the configuration information for the specified DMA Stream.
230 | * @param Address The new address
231 | * @param memory the memory to be changed, This parameter can be one of
232 | * the following values:
233 | * MEMORY0 /
234 | * MEMORY1
235 | * @note The MEMORY0 address can be changed only when the current transfer use
236 | * MEMORY1 and the MEMORY1 address can be changed only when the current
237 | * transfer use MEMORY0.
238 | * @retval HAL status
239 | */
240 | HAL_StatusTypeDef HAL_DMAEx_ChangeMemory(DMA_HandleTypeDef *hdma, uint32_t Address, HAL_DMA_MemoryTypeDef memory)
241 | {
242 | if(memory == MEMORY0)
243 | {
244 | /* change the memory0 address */
245 | hdma->Instance->M0AR = Address;
246 | }
247 | else
248 | {
249 | /* change the memory1 address */
250 | hdma->Instance->M1AR = Address;
251 | }
252 |
253 | return HAL_OK;
254 | }
255 |
256 | /**
257 | * @}
258 | */
259 |
260 | /**
261 | * @}
262 | */
263 |
264 | /** @addtogroup DMAEx_Private_Functions
265 | * @{
266 | */
267 |
268 | /**
269 | * @brief Set the DMA Transfer parameter.
270 | * @param hdma pointer to a DMA_HandleTypeDef structure that contains
271 | * the configuration information for the specified DMA Stream.
272 | * @param SrcAddress The source memory Buffer address
273 | * @param DstAddress The destination memory Buffer address
274 | * @param DataLength The length of data to be transferred from source to destination
275 | * @retval HAL status
276 | */
277 | static void DMA_MultiBufferSetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
278 | {
279 | /* Configure DMA Stream data length */
280 | hdma->Instance->NDTR = DataLength;
281 |
282 | /* Peripheral to Memory */
283 | if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
284 | {
285 | /* Configure DMA Stream destination address */
286 | hdma->Instance->PAR = DstAddress;
287 |
288 | /* Configure DMA Stream source address */
289 | hdma->Instance->M0AR = SrcAddress;
290 | }
291 | /* Memory to Peripheral */
292 | else
293 | {
294 | /* Configure DMA Stream source address */
295 | hdma->Instance->PAR = SrcAddress;
296 |
297 | /* Configure DMA Stream destination address */
298 | hdma->Instance->M0AR = DstAddress;
299 | }
300 | }
301 |
302 | /**
303 | * @}
304 | */
305 |
306 | #endif /* HAL_DMA_MODULE_ENABLED */
307 | /**
308 | * @}
309 | */
310 |
311 | /**
312 | * @}
313 | */
314 |
315 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
316 |
--------------------------------------------------------------------------------
/nucleo-f446re/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file stm32f4xx_hal_flash_ramfunc.c
4 | * @author MCD Application Team
5 | * @brief FLASH RAMFUNC module driver.
6 | * This file provides a FLASH firmware functions which should be
7 | * executed from internal SRAM
8 | * + Stop/Start the flash interface while System Run
9 | * + Enable/Disable the flash sleep while System Run
10 | @verbatim
11 | ==============================================================================
12 | ##### APIs executed from Internal RAM #####
13 | ==============================================================================
14 | [..]
15 | *** ARM Compiler ***
16 | --------------------
17 | [..] RAM functions are defined using the toolchain options.
18 | Functions that are be executed in RAM should reside in a separate
19 | source module. Using the 'Options for File' dialog you can simply change
20 | the 'Code / Const' area of a module to a memory space in physical RAM.
21 | Available memory areas are declared in the 'Target' tab of the
22 | Options for Target' dialog.
23 |
24 | *** ICCARM Compiler ***
25 | -----------------------
26 | [..] RAM functions are defined using a specific toolchain keyword "__ramfunc".
27 |
28 | *** GNU Compiler ***
29 | --------------------
30 | [..] RAM functions are defined using a specific toolchain attribute
31 | "__attribute__((section(".RamFunc")))".
32 |
33 | @endverbatim
34 | ******************************************************************************
35 | * @attention
36 | *
37 | * © Copyright (c) 2017 STMicroelectronics.
38 | * All rights reserved.
39 | *
40 | * This software component is licensed by ST under BSD 3-Clause license,
41 | * the "License"; You may not use this file except in compliance with the
42 | * License. You may obtain a copy of the License at:
43 | * opensource.org/licenses/BSD-3-Clause
44 | *
45 | ******************************************************************************
46 | */
47 |
48 | /* Includes ------------------------------------------------------------------*/
49 | #include "stm32f4xx_hal.h"
50 |
51 | /** @addtogroup STM32F4xx_HAL_Driver
52 | * @{
53 | */
54 |
55 | /** @defgroup FLASH_RAMFUNC FLASH RAMFUNC
56 | * @brief FLASH functions executed from RAM
57 | * @{
58 | */
59 | #ifdef HAL_FLASH_MODULE_ENABLED
60 | #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
61 | defined(STM32F412Rx) || defined(STM32F412Cx)
62 |
63 | /* Private typedef -----------------------------------------------------------*/
64 | /* Private define ------------------------------------------------------------*/
65 | /* Private macro -------------------------------------------------------------*/
66 | /* Private variables ---------------------------------------------------------*/
67 | /* Private function prototypes -----------------------------------------------*/
68 | /* Exported functions --------------------------------------------------------*/
69 | /** @defgroup FLASH_RAMFUNC_Exported_Functions FLASH RAMFUNC Exported Functions
70 | * @{
71 | */
72 |
73 | /** @defgroup FLASH_RAMFUNC_Exported_Functions_Group1 Peripheral features functions executed from internal RAM
74 | * @brief Peripheral Extended features functions
75 | *
76 | @verbatim
77 |
78 | ===============================================================================
79 | ##### ramfunc functions #####
80 | ===============================================================================
81 | [..]
82 | This subsection provides a set of functions that should be executed from RAM
83 | transfers.
84 |
85 | @endverbatim
86 | * @{
87 | */
88 |
89 | /**
90 | * @brief Stop the flash interface while System Run
91 | * @note This mode is only available for STM32F41xxx/STM32F446xx devices.
92 | * @note This mode couldn't be set while executing with the flash itself.
93 | * It should be done with specific routine executed from RAM.
94 | * @retval HAL status
95 | */
96 | __RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_StopFlashInterfaceClk(void)
97 | {
98 | /* Enable Power ctrl clock */
99 | __HAL_RCC_PWR_CLK_ENABLE();
100 | /* Stop the flash interface while System Run */
101 | SET_BIT(PWR->CR, PWR_CR_FISSR);
102 |
103 | return HAL_OK;
104 | }
105 |
106 | /**
107 | * @brief Start the flash interface while System Run
108 | * @note This mode is only available for STM32F411xx/STM32F446xx devices.
109 | * @note This mode couldn't be set while executing with the flash itself.
110 | * It should be done with specific routine executed from RAM.
111 | * @retval HAL status
112 | */
113 | __RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_StartFlashInterfaceClk(void)
114 | {
115 | /* Enable Power ctrl clock */
116 | __HAL_RCC_PWR_CLK_ENABLE();
117 | /* Start the flash interface while System Run */
118 | CLEAR_BIT(PWR->CR, PWR_CR_FISSR);
119 |
120 | return HAL_OK;
121 | }
122 |
123 | /**
124 | * @brief Enable the flash sleep while System Run
125 | * @note This mode is only available for STM32F41xxx/STM32F446xx devices.
126 | * @note This mode could n't be set while executing with the flash itself.
127 | * It should be done with specific routine executed from RAM.
128 | * @retval HAL status
129 | */
130 | __RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_EnableFlashSleepMode(void)
131 | {
132 | /* Enable Power ctrl clock */
133 | __HAL_RCC_PWR_CLK_ENABLE();
134 | /* Enable the flash sleep while System Run */
135 | SET_BIT(PWR->CR, PWR_CR_FMSSR);
136 |
137 | return HAL_OK;
138 | }
139 |
140 | /**
141 | * @brief Disable the flash sleep while System Run
142 | * @note This mode is only available for STM32F41xxx/STM32F446xx devices.
143 | * @note This mode couldn't be set while executing with the flash itself.
144 | * It should be done with specific routine executed from RAM.
145 | * @retval HAL status
146 | */
147 | __RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_DisableFlashSleepMode(void)
148 | {
149 | /* Enable Power ctrl clock */
150 | __HAL_RCC_PWR_CLK_ENABLE();
151 | /* Disable the flash sleep while System Run */
152 | CLEAR_BIT(PWR->CR, PWR_CR_FMSSR);
153 |
154 | return HAL_OK;
155 | }
156 |
157 | /**
158 | * @}
159 | */
160 |
161 | /**
162 | * @}
163 | */
164 |
165 | #endif /* STM32F410xx || STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
166 | #endif /* HAL_FLASH_MODULE_ENABLED */
167 | /**
168 | * @}
169 | */
170 |
171 | /**
172 | * @}
173 | */
174 |
175 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
176 |
--------------------------------------------------------------------------------
/nucleo-f446re/STM32F446RETX_FLASH.ld:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file LinkerScript.ld
4 | * @author Auto-generated by STM32CubeIDE
5 | * Abstract : Linker script for NUCLEO-F446RE Board embedding STM32F446RETx Device from stm32f4 series
6 | * 512Kbytes FLASH
7 | * 128Kbytes RAM
8 | *
9 | * Set heap size, stack size and stack location according
10 | * to application requirements.
11 | *
12 | * Set memory bank area and size if external memory is used
13 | ******************************************************************************
14 | * @attention
15 | *
16 | * © Copyright (c) 2020 STMicroelectronics.
17 | * All rights reserved.
18 | *
19 | * This software component is licensed by ST under BSD 3-Clause license,
20 | * the "License"; You may not use this file except in compliance with the
21 | * License. You may obtain a copy of the License at:
22 | * opensource.org/licenses/BSD-3-Clause
23 | *
24 | ******************************************************************************
25 | */
26 |
27 | /* Entry Point */
28 | ENTRY(Reset_Handler)
29 |
30 | /* Highest address of the user mode stack */
31 | _estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */
32 |
33 | _Min_Heap_Size = 0x200 ; /* required amount of heap */
34 | _Min_Stack_Size = 0x400 ; /* required amount of stack */
35 |
36 | /* Memories definition */
37 | MEMORY
38 | {
39 | RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 128K
40 | FLASH (rx) : ORIGIN = 0x8000000, LENGTH = 512K
41 | }
42 |
43 | /* Sections */
44 | SECTIONS
45 | {
46 | /* The startup code into "FLASH" Rom type memory */
47 | .isr_vector :
48 | {
49 | . = ALIGN(4);
50 | KEEP(*(.isr_vector)) /* Startup code */
51 | . = ALIGN(4);
52 | } >FLASH
53 |
54 | /* The program code and other data into "FLASH" Rom type memory */
55 | .text :
56 | {
57 | . = ALIGN(4);
58 | *(.text) /* .text sections (code) */
59 | *(.text*) /* .text* sections (code) */
60 | *(.glue_7) /* glue arm to thumb code */
61 | *(.glue_7t) /* glue thumb to arm code */
62 | *(.eh_frame)
63 |
64 | KEEP (*(.init))
65 | KEEP (*(.fini))
66 |
67 | . = ALIGN(4);
68 | _etext = .; /* define a global symbols at end of code */
69 | } >FLASH
70 |
71 | /* Constant data into "FLASH" Rom type memory */
72 | .rodata :
73 | {
74 | . = ALIGN(4);
75 | *(.rodata) /* .rodata sections (constants, strings, etc.) */
76 | *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
77 | . = ALIGN(4);
78 | } >FLASH
79 |
80 | .ARM.extab : {
81 | . = ALIGN(4);
82 | *(.ARM.extab* .gnu.linkonce.armextab.*)
83 | . = ALIGN(4);
84 | } >FLASH
85 |
86 | .ARM : {
87 | . = ALIGN(4);
88 | __exidx_start = .;
89 | *(.ARM.exidx*)
90 | __exidx_end = .;
91 | . = ALIGN(4);
92 | } >FLASH
93 |
94 | .preinit_array :
95 | {
96 | . = ALIGN(4);
97 | PROVIDE_HIDDEN (__preinit_array_start = .);
98 | KEEP (*(.preinit_array*))
99 | PROVIDE_HIDDEN (__preinit_array_end = .);
100 | . = ALIGN(4);
101 | } >FLASH
102 |
103 | .init_array :
104 | {
105 | . = ALIGN(4);
106 | PROVIDE_HIDDEN (__init_array_start = .);
107 | KEEP (*(SORT(.init_array.*)))
108 | KEEP (*(.init_array*))
109 | PROVIDE_HIDDEN (__init_array_end = .);
110 | . = ALIGN(4);
111 | } >FLASH
112 |
113 | .fini_array :
114 | {
115 | . = ALIGN(4);
116 | PROVIDE_HIDDEN (__fini_array_start = .);
117 | KEEP (*(SORT(.fini_array.*)))
118 | KEEP (*(.fini_array*))
119 | PROVIDE_HIDDEN (__fini_array_end = .);
120 | . = ALIGN(4);
121 | } >FLASH
122 |
123 | /* Used by the startup to initialize data */
124 | _sidata = LOADADDR(.data);
125 |
126 | /* Initialized data sections into "RAM" Ram type memory */
127 | .data :
128 | {
129 | . = ALIGN(4);
130 | _sdata = .; /* create a global symbol at data start */
131 | *(.data) /* .data sections */
132 | *(.data*) /* .data* sections */
133 |
134 | . = ALIGN(4);
135 | _edata = .; /* define a global symbol at data end */
136 |
137 | } >RAM AT> FLASH
138 |
139 | /* Uninitialized data section into "RAM" Ram type memory */
140 | . = ALIGN(4);
141 | .bss :
142 | {
143 | /* This is used by the startup in order to initialize the .bss section */
144 | _sbss = .; /* define a global symbol at bss start */
145 | __bss_start__ = _sbss;
146 | *(.bss)
147 | *(.bss*)
148 | *(COMMON)
149 |
150 | . = ALIGN(4);
151 | _ebss = .; /* define a global symbol at bss end */
152 | __bss_end__ = _ebss;
153 | } >RAM
154 |
155 | /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */
156 | ._user_heap_stack :
157 | {
158 | . = ALIGN(8);
159 | PROVIDE ( end = . );
160 | PROVIDE ( _end = . );
161 | . = . + _Min_Heap_Size;
162 | . = . + _Min_Stack_Size;
163 | . = ALIGN(8);
164 | } >RAM
165 |
166 | /* Remove information from the compiler libraries */
167 | /DISCARD/ :
168 | {
169 | libc.a ( * )
170 | libm.a ( * )
171 | libgcc.a ( * )
172 | }
173 |
174 | .ARM.attributes 0 : { *(.ARM.attributes) }
175 | }
176 |
--------------------------------------------------------------------------------
/nucleo-f446re/STM32F446RETX_RAM.ld:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file LinkerScript.ld
4 | * @author Auto-generated by STM32CubeIDE
5 | * Abstract : Linker script for NUCLEO-F446RE Board embedding STM32F446RETx Device from stm32f4 series
6 | * 512Kbytes FLASH
7 | * 128Kbytes RAM
8 | *
9 | * Set heap size, stack size and stack location according
10 | * to application requirements.
11 | *
12 | * Set memory bank area and size if external memory is used
13 | ******************************************************************************
14 | * @attention
15 | *
16 | * © Copyright (c) 2020 STMicroelectronics.
17 | * All rights reserved.
18 | *
19 | * This software component is licensed by ST under BSD 3-Clause license,
20 | * the "License"; You may not use this file except in compliance with the
21 | * License. You may obtain a copy of the License at:
22 | * opensource.org/licenses/BSD-3-Clause
23 | *
24 | ******************************************************************************
25 | */
26 |
27 | /* Entry Point */
28 | ENTRY(Reset_Handler)
29 |
30 | /* Highest address of the user mode stack */
31 | _estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */
32 |
33 | _Min_Heap_Size = 0x200; /* required amount of heap */
34 | _Min_Stack_Size = 0x400; /* required amount of stack */
35 |
36 | /* Memories definition */
37 | MEMORY
38 | {
39 | RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 128K
40 | FLASH (rx) : ORIGIN = 0x8000000, LENGTH = 512K
41 | }
42 |
43 | /* Sections */
44 | SECTIONS
45 | {
46 | /* The startup code into "RAM" Ram type memory */
47 | .isr_vector :
48 | {
49 | . = ALIGN(4);
50 | KEEP(*(.isr_vector)) /* Startup code */
51 | . = ALIGN(4);
52 | } >RAM
53 |
54 | /* The program code and other data into "RAM" Ram type memory */
55 | .text :
56 | {
57 | . = ALIGN(4);
58 | *(.text) /* .text sections (code) */
59 | *(.text*) /* .text* sections (code) */
60 | *(.glue_7) /* glue arm to thumb code */
61 | *(.glue_7t) /* glue thumb to arm code */
62 | *(.eh_frame)
63 |
64 | KEEP (*(.init))
65 | KEEP (*(.fini))
66 |
67 | . = ALIGN(4);
68 | _etext = .; /* define a global symbols at end of code */
69 | } >RAM
70 |
71 | /* Constant data into "RAM" Ram type memory */
72 | .rodata :
73 | {
74 | . = ALIGN(4);
75 | *(.rodata) /* .rodata sections (constants, strings, etc.) */
76 | *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
77 | . = ALIGN(4);
78 | } >RAM
79 |
80 | .ARM.extab : {
81 | . = ALIGN(4);
82 | *(.ARM.extab* .gnu.linkonce.armextab.*)
83 | . = ALIGN(4);
84 | } >RAM
85 |
86 | .ARM : {
87 | . = ALIGN(4);
88 | __exidx_start = .;
89 | *(.ARM.exidx*)
90 | __exidx_end = .;
91 | . = ALIGN(4);
92 | } >RAM
93 |
94 | .preinit_array :
95 | {
96 | . = ALIGN(4);
97 | PROVIDE_HIDDEN (__preinit_array_start = .);
98 | KEEP (*(.preinit_array*))
99 | PROVIDE_HIDDEN (__preinit_array_end = .);
100 | . = ALIGN(4);
101 | } >RAM
102 |
103 | .init_array :
104 | {
105 | . = ALIGN(4);
106 | PROVIDE_HIDDEN (__init_array_start = .);
107 | KEEP (*(SORT(.init_array.*)))
108 | KEEP (*(.init_array*))
109 | PROVIDE_HIDDEN (__init_array_end = .);
110 | . = ALIGN(4);
111 | } >RAM
112 |
113 | .fini_array :
114 | {
115 | . = ALIGN(4);
116 | PROVIDE_HIDDEN (__fini_array_start = .);
117 | KEEP (*(SORT(.fini_array.*)))
118 | KEEP (*(.fini_array*))
119 | PROVIDE_HIDDEN (__fini_array_end = .);
120 | . = ALIGN(4);
121 | } >RAM
122 |
123 | /* Used by the startup to initialize data */
124 | _sidata = LOADADDR(.data);
125 |
126 | /* Initialized data sections into "RAM" Ram type memory */
127 | .data :
128 | {
129 | . = ALIGN(4);
130 | _sdata = .; /* create a global symbol at data start */
131 | *(.data) /* .data sections */
132 | *(.data*) /* .data* sections */
133 |
134 | . = ALIGN(4);
135 | _edata = .; /* define a global symbol at data end */
136 |
137 | } >RAM
138 |
139 | /* Uninitialized data section into "RAM" Ram type memory */
140 | . = ALIGN(4);
141 | .bss :
142 | {
143 | /* This is used by the startup in order to initialize the .bss section */
144 | _sbss = .; /* define a global symbol at bss start */
145 | __bss_start__ = _sbss;
146 | *(.bss)
147 | *(.bss*)
148 | *(COMMON)
149 |
150 | . = ALIGN(4);
151 | _ebss = .; /* define a global symbol at bss end */
152 | __bss_end__ = _ebss;
153 | } >RAM
154 |
155 | /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */
156 | ._user_heap_stack :
157 | {
158 | . = ALIGN(8);
159 | PROVIDE ( end = . );
160 | PROVIDE ( _end = . );
161 | . = . + _Min_Heap_Size;
162 | . = . + _Min_Stack_Size;
163 | . = ALIGN(8);
164 | } >RAM
165 |
166 | /* Remove information from the compiler libraries */
167 | /DISCARD/ :
168 | {
169 | libc.a ( * )
170 | libm.a ( * )
171 | libgcc.a ( * )
172 | }
173 |
174 | .ARM.attributes 0 : { *(.ARM.attributes) }
175 | }
176 |
--------------------------------------------------------------------------------
/nucleo-f446re/stm32-uart.ioc:
--------------------------------------------------------------------------------
1 | #MicroXplorer Configuration settings - do not modify
2 | File.Version=6
3 | KeepUserPlacement=false
4 | Mcu.Family=STM32F4
5 | Mcu.IP0=NVIC
6 | Mcu.IP1=RCC
7 | Mcu.IP2=SYS
8 | Mcu.IP3=USART2
9 | Mcu.IPNb=4
10 | Mcu.Name=STM32F446R(C-E)Tx
11 | Mcu.Package=LQFP64
12 | Mcu.Pin0=PC13
13 | Mcu.Pin1=PC14-OSC32_IN
14 | Mcu.Pin10=PB3
15 | Mcu.Pin11=VP_SYS_VS_Systick
16 | Mcu.Pin2=PC15-OSC32_OUT
17 | Mcu.Pin3=PH0-OSC_IN
18 | Mcu.Pin4=PH1-OSC_OUT
19 | Mcu.Pin5=PA2
20 | Mcu.Pin6=PA3
21 | Mcu.Pin7=PA5
22 | Mcu.Pin8=PA13
23 | Mcu.Pin9=PA14
24 | Mcu.PinsNb=12
25 | Mcu.ThirdPartyNb=0
26 | Mcu.UserConstants=
27 | Mcu.UserName=STM32F446RETx
28 | MxCube.Version=5.6.0
29 | MxDb.Version=DB.5.0.60
30 | NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:true\:false
31 | NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:true\:false
32 | NVIC.ForceEnableDMAVector=true
33 | NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:true\:false
34 | NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:true\:false
35 | NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:true\:false
36 | NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false\:false
37 | NVIC.PriorityGroup=NVIC_PRIORITYGROUP_0
38 | NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false\:false
39 | NVIC.SysTick_IRQn=true\:0\:0\:true\:false\:true\:true\:true
40 | NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:true\:false
41 | PA13.GPIOParameters=GPIO_Label
42 | PA13.GPIO_Label=TMS
43 | PA13.Locked=true
44 | PA13.Mode=Serial_Wire
45 | PA13.Signal=SYS_JTMS-SWDIO
46 | PA14.GPIOParameters=GPIO_Label
47 | PA14.GPIO_Label=TCK
48 | PA14.Locked=true
49 | PA14.Mode=Serial_Wire
50 | PA14.Signal=SYS_JTCK-SWCLK
51 | PA2.GPIOParameters=GPIO_Label
52 | PA2.GPIO_Label=USART_TX
53 | PA2.Locked=true
54 | PA2.Mode=Asynchronous
55 | PA2.Signal=USART2_TX
56 | PA3.GPIOParameters=GPIO_Label
57 | PA3.GPIO_Label=USART_RX
58 | PA3.Locked=true
59 | PA3.Mode=Asynchronous
60 | PA3.Signal=USART2_RX
61 | PA5.GPIOParameters=GPIO_Label
62 | PA5.GPIO_Label=LD2 [Green Led]
63 | PA5.Locked=true
64 | PA5.Signal=GPIO_Output
65 | PB3.GPIOParameters=GPIO_Label
66 | PB3.GPIO_Label=SWO
67 | PB3.Locked=true
68 | PB3.Signal=SYS_JTDO-SWO
69 | PC13.GPIOParameters=GPIO_Label,GPIO_ModeDefaultEXTI
70 | PC13.GPIO_Label=B1 [Blue PushButton]
71 | PC13.GPIO_ModeDefaultEXTI=GPIO_MODE_IT_FALLING
72 | PC13.Locked=true
73 | PC13.Signal=GPXTI13
74 | PC14-OSC32_IN.Locked=true
75 | PC14-OSC32_IN.Mode=LSE-External-Oscillator
76 | PC14-OSC32_IN.Signal=RCC_OSC32_IN
77 | PC15-OSC32_OUT.Locked=true
78 | PC15-OSC32_OUT.Mode=LSE-External-Oscillator
79 | PC15-OSC32_OUT.Signal=RCC_OSC32_OUT
80 | PH0-OSC_IN.Locked=true
81 | PH0-OSC_IN.Mode=HSE-External-Oscillator
82 | PH0-OSC_IN.Signal=RCC_OSC_IN
83 | PH1-OSC_OUT.Locked=true
84 | PH1-OSC_OUT.Mode=HSE-External-Oscillator
85 | PH1-OSC_OUT.Signal=RCC_OSC_OUT
86 | PinOutPanel.RotationAngle=0
87 | ProjectManager.AskForMigrate=true
88 | ProjectManager.BackupPrevious=false
89 | ProjectManager.CompilerOptimize=6
90 | ProjectManager.ComputerToolchain=false
91 | ProjectManager.CoupleFile=false
92 | ProjectManager.CustomerFirmwarePackage=
93 | ProjectManager.DefaultFWLocation=true
94 | ProjectManager.DeletePrevious=true
95 | ProjectManager.DeviceId=STM32F446RETx
96 | ProjectManager.FirmwarePackage=STM32Cube FW_F4 V1.25.0
97 | ProjectManager.FreePins=false
98 | ProjectManager.HalAssertFull=false
99 | ProjectManager.HeapSize=0x200
100 | ProjectManager.KeepUserCode=true
101 | ProjectManager.LastFirmware=true
102 | ProjectManager.LibraryCopy=1
103 | ProjectManager.MainLocation=Core/Src
104 | ProjectManager.NoMain=false
105 | ProjectManager.PreviousToolchain=
106 | ProjectManager.ProjectBuild=false
107 | ProjectManager.ProjectFileName=stm32-uart.ioc
108 | ProjectManager.ProjectName=stm32-uart
109 | ProjectManager.StackSize=0x400
110 | ProjectManager.TargetToolchain=STM32CubeIDE
111 | ProjectManager.ToolChainLocation=
112 | ProjectManager.UnderRoot=true
113 | ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-SystemClock_Config-RCC-false-HAL-false,3-MX_USART2_UART_Init-USART2-false-HAL-true
114 | RCC.48MHZClocksFreq_Value=84000000
115 | RCC.AHBFreq_Value=84000000
116 | RCC.APB1CLKDivider=RCC_HCLK_DIV2
117 | RCC.APB1Freq_Value=42000000
118 | RCC.APB1TimFreq_Value=84000000
119 | RCC.APB2Freq_Value=84000000
120 | RCC.APB2TimFreq_Value=84000000
121 | RCC.CECFreq_Value=32786.88524590164
122 | RCC.CortexFreq_Value=84000000
123 | RCC.EthernetFreq_Value=84000000
124 | RCC.FCLKCortexFreq_Value=84000000
125 | RCC.FLatency-AdvancedSettings=FLASH_LATENCY_2
126 | RCC.FMPI2C1Freq_Value=42000000
127 | RCC.FamilyName=M
128 | RCC.HCLKFreq_Value=84000000
129 | RCC.HSE_VALUE=8000000
130 | RCC.HSI_VALUE=16000000
131 | RCC.I2SClocksFreq_Value=96000000
132 | RCC.IPParameters=48MHZClocksFreq_Value,AHBFreq_Value,APB1CLKDivider,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,CECFreq_Value,CortexFreq_Value,EthernetFreq_Value,FCLKCortexFreq_Value,FLatency-AdvancedSettings,FMPI2C1Freq_Value,FamilyName,HCLKFreq_Value,HSE_VALUE,HSI_VALUE,I2SClocksFreq_Value,LSI_VALUE,MCO2PinFreq_Value,PLLCLKFreq_Value,PLLI2SPCLKFreq_Value,PLLI2SQCLKFreq_Value,PLLI2SRCLKFreq_Value,PLLN,PLLP,PLLQCLKFreq_Value,PLLRCLKFreq_Value,PLLSAIPCLKFreq_Value,PLLSAIQCLKFreq_Value,PWRFreq_Value,RTCFreq_Value,RTCHSEDivFreq_Value,SAIAFreq_Value,SAIBFreq_Value,SDIOFreq_Value,SPDIFRXFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,USBFreq_Value,VCOI2SInputFreq_Value,VCOI2SOutputFreq_Value,VCOInputFreq_Value,VCOInputMFreq_Value,VCOOutputFreq_Value,VCOSAIInputFreq_Value,VCOSAIOutputFreq_Value,VcooutputI2S
133 | RCC.LSI_VALUE=32000
134 | RCC.MCO2PinFreq_Value=84000000
135 | RCC.PLLCLKFreq_Value=84000000
136 | RCC.PLLI2SPCLKFreq_Value=96000000
137 | RCC.PLLI2SQCLKFreq_Value=96000000
138 | RCC.PLLI2SRCLKFreq_Value=96000000
139 | RCC.PLLN=336
140 | RCC.PLLP=RCC_PLLP_DIV4
141 | RCC.PLLQCLKFreq_Value=168000000
142 | RCC.PLLRCLKFreq_Value=168000000
143 | RCC.PLLSAIPCLKFreq_Value=96000000
144 | RCC.PLLSAIQCLKFreq_Value=96000000
145 | RCC.PWRFreq_Value=84000000
146 | RCC.RTCFreq_Value=32000
147 | RCC.RTCHSEDivFreq_Value=4000000
148 | RCC.SAIAFreq_Value=96000000
149 | RCC.SAIBFreq_Value=96000000
150 | RCC.SDIOFreq_Value=168000000
151 | RCC.SPDIFRXFreq_Value=168000000
152 | RCC.SYSCLKFreq_VALUE=84000000
153 | RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK
154 | RCC.USBFreq_Value=168000000
155 | RCC.VCOI2SInputFreq_Value=1000000
156 | RCC.VCOI2SOutputFreq_Value=192000000
157 | RCC.VCOInputFreq_Value=1000000
158 | RCC.VCOInputMFreq_Value=1000000
159 | RCC.VCOOutputFreq_Value=336000000
160 | RCC.VCOSAIInputFreq_Value=1000000
161 | RCC.VCOSAIOutputFreq_Value=192000000
162 | RCC.VcooutputI2S=96000000
163 | SH.GPXTI13.0=GPIO_EXTI13
164 | SH.GPXTI13.ConfNb=1
165 | USART2.IPParameters=VirtualMode
166 | USART2.VirtualMode=VM_ASYNC
167 | VP_SYS_VS_Systick.Mode=SysTick
168 | VP_SYS_VS_Systick.Signal=SYS_VS_Systick
169 | board=NUCLEO-F446RE
170 | boardIOC=true
171 | isbadioc=false
172 |
--------------------------------------------------------------------------------
/proto/uart_messages.proto:
--------------------------------------------------------------------------------
1 | /*
2 | * Copyright (C) 2020-2024 Embedded AMS B.V. - All Rights Reserved
3 | *
4 | * This file is part of Embedded Proto.
5 | *
6 | * Embedded Proto is open source software: you can redistribute it and/or
7 | * modify it under the terms of the GNU General Public License as published
8 | * by the Free Software Foundation, version 3 of the license.
9 | *
10 | * Embedded Proto is distributed in the hope that it will be useful,
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 | * GNU General Public License for more details.
14 | *
15 | * You should have received a copy of the GNU General Public License
16 | * along with Embedded Proto. If not, see .
17 | *
18 | * For commercial and closed source application please visit:
19 | * .
20 | *
21 | * Embedded AMS B.V.
22 | * Info:
23 | * info at EmbeddedProto dot com
24 | *
25 | * Postal address:
26 | * Atoomweg 2
27 | * 1627 LE, Hoorn
28 | * the Netherlands
29 | */
30 |
31 | // This file listes the protobuffer messages used in the example to make a simple uart communcation protocol.
32 | // Commands are send from the desktop to the microctontroller which in turn sends a reply.
33 |
34 | syntax = "proto3";
35 |
36 | message Command
37 | {
38 | enum Buttons
39 | {
40 | DoNothing = 0;
41 | Up = 1;
42 | Down = 2;
43 | Right = 4;
44 | Left = 3;
45 | Grab = 5;
46 | Stop = 6;
47 | }
48 |
49 | Buttons button = 1;
50 | uint32 value = 2;
51 | }
52 |
53 | message Reply
54 | {
55 | // Mark the x and y coordinates as optional to also send and display the zero position.
56 | optional int32 x_pos = 1;
57 | optional int32 y_pos = 2;
58 |
59 | bool price = 3;
60 | }
61 |
62 |
--------------------------------------------------------------------------------
/setup.py:
--------------------------------------------------------------------------------
1 | #
2 | # Copyright (C) 2020-2024 Embedded AMS B.V. - All Rights Reserved
3 | #
4 | # This file is part of Embedded Proto.
5 | #
6 | # Embedded Proto is open source software: you can redistribute it and/or
7 | # modify it under the terms of the GNU General Public License as published
8 | # by the Free Software Foundation, version 3 of the license.
9 | #
10 | # Embedded Proto is distributed in the hope that it will be useful,
11 | # but WITHOUT ANY WARRANTY; without even the implied warranty of
12 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 | # GNU General Public License for more details.
14 | #
15 | # You should have received a copy of the GNU General Public License
16 | # along with Embedded Proto. If not, see .
17 | #
18 | # For commercial and closed source application please visit:
19 | # .
20 | #
21 | # Embedded AMS B.V.
22 | # Info:
23 | # info at EmbeddedProto dot com
24 | #
25 | # Postal address:
26 | # Atoomweg 2
27 | # 1627 LE, Hoorn
28 | # the Netherlands
29 | #
30 |
31 | import subprocess
32 | import argparse
33 | import os
34 | import venv
35 | import platform
36 | from sys import stderr
37 | import shutil
38 |
39 | # Perform a system call to beable to display colors on windows
40 | os.system("")
41 |
42 | CGREEN = '\33[92m'
43 | CRED = '\33[91m'
44 | CYELLOW = '\33[93m'
45 | CEND = '\33[0m'
46 |
47 | print("Update the submodule Embedded Proto before importing its setup script.", end='')
48 | try:
49 | result = subprocess.run(["git", "submodule", "init"], check=False, capture_output=True)
50 | if result.returncode:
51 | print(" [Fail]")
52 | print(result.stderr.decode("utf-8"), end='', file=stderr)
53 | exit(1)
54 |
55 | result = subprocess.run(["git", "submodule", "update"], check=False, capture_output=True)
56 | if result.returncode:
57 | print(" [Fail]")
58 | print(result.stderr.decode("utf-8"), end='', file=stderr)
59 | exit(1)
60 | else:
61 | print(" [Success]")
62 | except OSError:
63 | print(" [Fail]")
64 | print("Unable to find git in your path.")
65 | print("Stopping the setup.")
66 | exit(1)
67 | except Exception as e:
68 | print(" [Fail]")
69 | print("Error: " + str(e), file=stderr)
70 | exit(1)
71 |
72 | from EmbeddedProto import setup as EPSetup
73 |
74 |
75 | ####################################################################################
76 |
77 | def setup_desktop_script():
78 | try:
79 | # ---------------------------------------
80 | print("Setup the virtual environment for the desktop Python script.", end='')
81 | os.chdir("./desktop")
82 | venv.create("venv", with_pip=True)
83 | print(" [" + CGREEN + "Success" + CEND + "]")
84 |
85 | # ---------------------------------------
86 | print("Installing requirement for the desktop Python script.", end='')
87 | on_windows = "Windows" == platform.system()
88 | command = []
89 | if on_windows:
90 | command.append("./venv/Scripts/pip")
91 | else:
92 | command.append("./venv/bin/pip")
93 | command.extend(["install", "-r", "requirements.txt"])
94 | result = subprocess.run(command, check=False, capture_output=True)
95 | if result.returncode:
96 | print(" [" + CRED + "Fail" + CEND + "]")
97 | print(result.stderr.decode("utf-8"), end='', file=stderr)
98 | exit(1)
99 | else:
100 | print(" [" + CGREEN + "Success" + CEND + "]")
101 |
102 | os.chdir("..")
103 |
104 | except Exception as e:
105 | print(" [" + CRED + "Fail" + CEND + "]")
106 | print("Error: " + str(e), file=stderr)
107 | exit(1)
108 |
109 |
110 | ####################################################################################
111 |
112 | def generate_source_code():
113 |
114 | print("Generate the source file based on uart_messages.proto.", end='')
115 | try:
116 | os.chdir("EmbeddedProto")
117 |
118 | command = ["protoc", "-I../proto", "--eams_out=../nucleo-f446re/generated",
119 | "../proto/uart_messages.proto"]
120 | if "Windows" == platform.system():
121 | command.append("--plugin=protoc-gen-eams=protoc-gen-eams.bat")
122 | else:
123 | command.append("--plugin=protoc-gen-eams=protoc-gen-eams")
124 |
125 | result = subprocess.run(command, check=False, capture_output=True)
126 | if result.returncode:
127 | print(" [" + CRED + "Fail" + CEND + "]")
128 | print(result.stderr.decode("utf-8"), end='', file=stderr)
129 | exit(1)
130 |
131 | os.chdir("..")
132 |
133 | result = subprocess.run(["protoc", "-I./proto", "--python_out=./desktop/generated",
134 | "./proto/uart_messages.proto"], check=False, capture_output=True)
135 | if result.returncode:
136 | print(" [" + CRED + "Fail" + CEND + "]")
137 | print(result.stderr.decode("utf-8"), end='', file=stderr)
138 | exit(1)
139 | else:
140 | print(" [" + CGREEN + "Success" + CEND + "]")
141 |
142 | except Exception as e:
143 | print(" [" + CRED + "Fail" + CEND + "]")
144 | print("Error: " + str(e), file=stderr)
145 | exit(1)
146 |
147 |
148 |
149 | ####################################################################################
150 |
151 | if __name__ == "__main__":
152 |
153 | parser = argparse.ArgumentParser(description="This script will setup the environment to generate Embedded Proto "
154 | "code in your project.")
155 |
156 | parser.add_argument("-g", "--generate", action="store_true",
157 | help="Do not run the Embedded Proto setup. Only generate the source based on *.proto files. "
158 | "Use this after changing uart_messages.proto.")
159 |
160 | EPSetup.add_parser_arguments(parser)
161 | EPSetup.display_feedback()
162 | args = parser.parse_args()
163 |
164 | # ---------------------------------------
165 | # Create destination folders if not present.
166 | newpath = r"./nucleo-f446re/generated"
167 | if not os.path.exists(newpath):
168 | os.makedirs(newpath)
169 | newpath = r"./desktop/generated"
170 | if not os.path.exists(newpath):
171 | os.makedirs(newpath)
172 |
173 |
174 | # ---------------------------------------
175 | # Clean excisting venv and other generated files.
176 | if args.clean:
177 | shutil.rmtree("./desktop/venv", ignore_errors=True)
178 |
179 | try:
180 | os.remove("./desktop/generated/uart_messages_pb2.py")
181 | except FileNotFoundError:
182 | # This exception we can safely ignore as it means the file was not there. In that case we do not have to remove
183 | # it.
184 | pass
185 |
186 | try:
187 | os.remove("./nucleo-f446re/generated/uart_messages.h")
188 | except FileNotFoundError:
189 | # This exception we can safely ignore as it means the file was not there. In that case we do not have to remove
190 | # it.
191 | pass
192 |
193 |
194 | # ---------------------------------------
195 | if not args.generate:
196 | os.chdir("./EmbeddedProto")
197 |
198 | # Run the setup script of Embedded Proto it self.
199 | EPSetup.run(args)
200 |
201 | os.chdir("..")
202 |
203 | # ---------------------------------------
204 | setup_desktop_script()
205 |
206 | # ---------------------------------------
207 | generate_source_code()
208 |
209 | # ---------------------------------------
210 | # If the script did not exit before here we have completed it with success.
211 | print("Setup completed with success!")
212 |
--------------------------------------------------------------------------------