├── 2022.11版_系统硬件综合设计报告模板.docx ├── README.md ├── openriscv ├── openriscv.srcs │ ├── constrs_1 │ │ ├── imports │ │ │ └── HardwareDesign │ │ │ │ └── EGo1.xdc │ │ └── new │ │ │ └── debug.xdc │ └── sources_1 │ │ ├── imports │ │ ├── 7-seg │ │ │ ├── x7seg.v │ │ │ └── x7seg_top.v │ │ └── code │ │ │ ├── ctrl.v │ │ │ ├── data_ram.v │ │ │ ├── define.v │ │ │ ├── ex.v │ │ │ ├── ex_mem.v │ │ │ ├── id.v │ │ │ ├── id_ex.v │ │ │ ├── if_id.v │ │ │ ├── inst_rom.txt │ │ │ ├── inst_rom.v │ │ │ ├── mem.v │ │ │ ├── mem_wb.v │ │ │ ├── openriscv.v │ │ │ ├── openriscv_min_sopc.v │ │ │ ├── openriscv_min_sopc_tb.v │ │ │ ├── pc_reg.v │ │ │ └── regfile.v │ │ └── new │ │ └── display_buffer.v ├── openriscv.xpr └── openriscv_min_sopc_tb_behav.wcfg └── 自述 ├── images ├── 4_cda.jpg ├── asm.jpg ├── cpu_sche.png ├── schematic.png ├── simu.png └── timing_check.png └── 自述.md /2022.11版_系统硬件综合设计报告模板.docx: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Eslzzyl/riscv-pipeline-cpu/HEAD/2022.11版_系统硬件综合设计报告模板.docx -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Eslzzyl/riscv-pipeline-cpu/HEAD/README.md -------------------------------------------------------------------------------- /openriscv/openriscv.srcs/constrs_1/imports/HardwareDesign/EGo1.xdc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Eslzzyl/riscv-pipeline-cpu/HEAD/openriscv/openriscv.srcs/constrs_1/imports/HardwareDesign/EGo1.xdc -------------------------------------------------------------------------------- /openriscv/openriscv.srcs/constrs_1/new/debug.xdc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Eslzzyl/riscv-pipeline-cpu/HEAD/openriscv/openriscv.srcs/constrs_1/new/debug.xdc -------------------------------------------------------------------------------- /openriscv/openriscv.srcs/sources_1/imports/7-seg/x7seg.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Eslzzyl/riscv-pipeline-cpu/HEAD/openriscv/openriscv.srcs/sources_1/imports/7-seg/x7seg.v -------------------------------------------------------------------------------- /openriscv/openriscv.srcs/sources_1/imports/7-seg/x7seg_top.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Eslzzyl/riscv-pipeline-cpu/HEAD/openriscv/openriscv.srcs/sources_1/imports/7-seg/x7seg_top.v -------------------------------------------------------------------------------- /openriscv/openriscv.srcs/sources_1/imports/code/ctrl.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Eslzzyl/riscv-pipeline-cpu/HEAD/openriscv/openriscv.srcs/sources_1/imports/code/ctrl.v -------------------------------------------------------------------------------- /openriscv/openriscv.srcs/sources_1/imports/code/data_ram.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Eslzzyl/riscv-pipeline-cpu/HEAD/openriscv/openriscv.srcs/sources_1/imports/code/data_ram.v -------------------------------------------------------------------------------- /openriscv/openriscv.srcs/sources_1/imports/code/define.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Eslzzyl/riscv-pipeline-cpu/HEAD/openriscv/openriscv.srcs/sources_1/imports/code/define.v -------------------------------------------------------------------------------- /openriscv/openriscv.srcs/sources_1/imports/code/ex.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Eslzzyl/riscv-pipeline-cpu/HEAD/openriscv/openriscv.srcs/sources_1/imports/code/ex.v -------------------------------------------------------------------------------- /openriscv/openriscv.srcs/sources_1/imports/code/ex_mem.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Eslzzyl/riscv-pipeline-cpu/HEAD/openriscv/openriscv.srcs/sources_1/imports/code/ex_mem.v -------------------------------------------------------------------------------- /openriscv/openriscv.srcs/sources_1/imports/code/id.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Eslzzyl/riscv-pipeline-cpu/HEAD/openriscv/openriscv.srcs/sources_1/imports/code/id.v -------------------------------------------------------------------------------- /openriscv/openriscv.srcs/sources_1/imports/code/id_ex.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Eslzzyl/riscv-pipeline-cpu/HEAD/openriscv/openriscv.srcs/sources_1/imports/code/id_ex.v -------------------------------------------------------------------------------- /openriscv/openriscv.srcs/sources_1/imports/code/if_id.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Eslzzyl/riscv-pipeline-cpu/HEAD/openriscv/openriscv.srcs/sources_1/imports/code/if_id.v -------------------------------------------------------------------------------- /openriscv/openriscv.srcs/sources_1/imports/code/inst_rom.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Eslzzyl/riscv-pipeline-cpu/HEAD/openriscv/openriscv.srcs/sources_1/imports/code/inst_rom.txt -------------------------------------------------------------------------------- /openriscv/openriscv.srcs/sources_1/imports/code/inst_rom.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Eslzzyl/riscv-pipeline-cpu/HEAD/openriscv/openriscv.srcs/sources_1/imports/code/inst_rom.v -------------------------------------------------------------------------------- /openriscv/openriscv.srcs/sources_1/imports/code/mem.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Eslzzyl/riscv-pipeline-cpu/HEAD/openriscv/openriscv.srcs/sources_1/imports/code/mem.v -------------------------------------------------------------------------------- /openriscv/openriscv.srcs/sources_1/imports/code/mem_wb.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Eslzzyl/riscv-pipeline-cpu/HEAD/openriscv/openriscv.srcs/sources_1/imports/code/mem_wb.v -------------------------------------------------------------------------------- /openriscv/openriscv.srcs/sources_1/imports/code/openriscv.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Eslzzyl/riscv-pipeline-cpu/HEAD/openriscv/openriscv.srcs/sources_1/imports/code/openriscv.v -------------------------------------------------------------------------------- /openriscv/openriscv.srcs/sources_1/imports/code/openriscv_min_sopc.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Eslzzyl/riscv-pipeline-cpu/HEAD/openriscv/openriscv.srcs/sources_1/imports/code/openriscv_min_sopc.v -------------------------------------------------------------------------------- /openriscv/openriscv.srcs/sources_1/imports/code/openriscv_min_sopc_tb.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Eslzzyl/riscv-pipeline-cpu/HEAD/openriscv/openriscv.srcs/sources_1/imports/code/openriscv_min_sopc_tb.v -------------------------------------------------------------------------------- /openriscv/openriscv.srcs/sources_1/imports/code/pc_reg.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Eslzzyl/riscv-pipeline-cpu/HEAD/openriscv/openriscv.srcs/sources_1/imports/code/pc_reg.v -------------------------------------------------------------------------------- /openriscv/openriscv.srcs/sources_1/imports/code/regfile.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Eslzzyl/riscv-pipeline-cpu/HEAD/openriscv/openriscv.srcs/sources_1/imports/code/regfile.v -------------------------------------------------------------------------------- /openriscv/openriscv.srcs/sources_1/new/display_buffer.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Eslzzyl/riscv-pipeline-cpu/HEAD/openriscv/openriscv.srcs/sources_1/new/display_buffer.v -------------------------------------------------------------------------------- /openriscv/openriscv.xpr: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Eslzzyl/riscv-pipeline-cpu/HEAD/openriscv/openriscv.xpr -------------------------------------------------------------------------------- /openriscv/openriscv_min_sopc_tb_behav.wcfg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Eslzzyl/riscv-pipeline-cpu/HEAD/openriscv/openriscv_min_sopc_tb_behav.wcfg -------------------------------------------------------------------------------- /自述/images/4_cda.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Eslzzyl/riscv-pipeline-cpu/HEAD/自述/images/4_cda.jpg -------------------------------------------------------------------------------- /自述/images/asm.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Eslzzyl/riscv-pipeline-cpu/HEAD/自述/images/asm.jpg -------------------------------------------------------------------------------- /自述/images/cpu_sche.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Eslzzyl/riscv-pipeline-cpu/HEAD/自述/images/cpu_sche.png -------------------------------------------------------------------------------- /自述/images/schematic.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Eslzzyl/riscv-pipeline-cpu/HEAD/自述/images/schematic.png -------------------------------------------------------------------------------- /自述/images/simu.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Eslzzyl/riscv-pipeline-cpu/HEAD/自述/images/simu.png -------------------------------------------------------------------------------- /自述/images/timing_check.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Eslzzyl/riscv-pipeline-cpu/HEAD/自述/images/timing_check.png -------------------------------------------------------------------------------- /自述/自述.md: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Eslzzyl/riscv-pipeline-cpu/HEAD/自述/自述.md --------------------------------------------------------------------------------