├── .gitignore ├── README.md ├── doc ├── Always@.pdf ├── basys-3.png ├── cpu-pipeline-graph.png ├── implementation-circuit-cpu.png ├── implementation-circuit-overview-captioned.png ├── implementation-circuit-overview.png ├── implementation-graph.png ├── implementation-on-device-part-1.png ├── implementation-on-device-part-2.png ├── implementation-on-device.png ├── implementation-summary.png ├── inst-supported.md ├── pc-cartoon.jpg ├── project-report.pdf ├── project-report.tex ├── riscv-spec-v2.2.pdf ├── riscv-toolchain-installation-usage.md ├── structure-graph.pptx ├── test-bench-wave.png └── uart-simulate-memory.png ├── src ├── cpu │ ├── cache.v │ ├── cpu.v │ ├── ctrl.v │ ├── defines.v │ ├── library │ │ ├── clk_wiz_0_tmp.vhd │ │ ├── fifo.v │ │ ├── mfifo.v │ │ └── multichan_trans.v │ ├── mem_ctrl.v │ ├── no use │ │ ├── inst_rom.v │ │ ├── ram.v │ │ └── riscv_min_sopc.v │ ├── reg_ex_mem.v │ ├── reg_id_ex.v │ ├── reg_if_id.v │ ├── reg_mem_wb.v │ ├── reg_pc.v │ ├── regfile.v │ ├── riscv_cpu.v │ ├── simple_ram.v │ ├── stage_ex.v │ ├── stage_id.v │ ├── stage_if.v │ ├── stage_mem.v │ ├── uart_trans.v │ └── utility.v └── memory │ ├── adapter.cpp │ ├── adapter.h │ ├── build.sh │ ├── env_iface.h │ ├── environment.cpp │ ├── environment.h │ ├── main.cpp │ ├── memory-simulator.exe │ ├── simulator.cpp │ └── simulator.h └── test ├── Makefile ├── bin-tail.py ├── bin2ascii.py ├── example.bin ├── example.data ├── inst.S ├── inst.data ├── memory-simulator.exe ├── memory.ld ├── runtime.txt ├── sim_cpu.v ├── sim_mem.v ├── test.S ├── test.data └── test_bench.v /.gitignore: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Evensgn/RISC-V-CPU/HEAD/.gitignore -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Evensgn/RISC-V-CPU/HEAD/README.md -------------------------------------------------------------------------------- /doc/Always@.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Evensgn/RISC-V-CPU/HEAD/doc/Always@.pdf -------------------------------------------------------------------------------- /doc/basys-3.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Evensgn/RISC-V-CPU/HEAD/doc/basys-3.png -------------------------------------------------------------------------------- /doc/cpu-pipeline-graph.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Evensgn/RISC-V-CPU/HEAD/doc/cpu-pipeline-graph.png -------------------------------------------------------------------------------- /doc/implementation-circuit-cpu.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Evensgn/RISC-V-CPU/HEAD/doc/implementation-circuit-cpu.png -------------------------------------------------------------------------------- /doc/implementation-circuit-overview-captioned.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Evensgn/RISC-V-CPU/HEAD/doc/implementation-circuit-overview-captioned.png -------------------------------------------------------------------------------- /doc/implementation-circuit-overview.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Evensgn/RISC-V-CPU/HEAD/doc/implementation-circuit-overview.png -------------------------------------------------------------------------------- /doc/implementation-graph.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Evensgn/RISC-V-CPU/HEAD/doc/implementation-graph.png -------------------------------------------------------------------------------- /doc/implementation-on-device-part-1.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Evensgn/RISC-V-CPU/HEAD/doc/implementation-on-device-part-1.png -------------------------------------------------------------------------------- /doc/implementation-on-device-part-2.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Evensgn/RISC-V-CPU/HEAD/doc/implementation-on-device-part-2.png -------------------------------------------------------------------------------- /doc/implementation-on-device.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Evensgn/RISC-V-CPU/HEAD/doc/implementation-on-device.png -------------------------------------------------------------------------------- /doc/implementation-summary.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Evensgn/RISC-V-CPU/HEAD/doc/implementation-summary.png -------------------------------------------------------------------------------- /doc/inst-supported.md: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Evensgn/RISC-V-CPU/HEAD/doc/inst-supported.md -------------------------------------------------------------------------------- /doc/pc-cartoon.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Evensgn/RISC-V-CPU/HEAD/doc/pc-cartoon.jpg -------------------------------------------------------------------------------- /doc/project-report.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Evensgn/RISC-V-CPU/HEAD/doc/project-report.pdf -------------------------------------------------------------------------------- /doc/project-report.tex: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Evensgn/RISC-V-CPU/HEAD/doc/project-report.tex -------------------------------------------------------------------------------- /doc/riscv-spec-v2.2.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Evensgn/RISC-V-CPU/HEAD/doc/riscv-spec-v2.2.pdf -------------------------------------------------------------------------------- /doc/riscv-toolchain-installation-usage.md: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Evensgn/RISC-V-CPU/HEAD/doc/riscv-toolchain-installation-usage.md -------------------------------------------------------------------------------- /doc/structure-graph.pptx: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Evensgn/RISC-V-CPU/HEAD/doc/structure-graph.pptx -------------------------------------------------------------------------------- /doc/test-bench-wave.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Evensgn/RISC-V-CPU/HEAD/doc/test-bench-wave.png -------------------------------------------------------------------------------- /doc/uart-simulate-memory.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Evensgn/RISC-V-CPU/HEAD/doc/uart-simulate-memory.png -------------------------------------------------------------------------------- /src/cpu/cache.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Evensgn/RISC-V-CPU/HEAD/src/cpu/cache.v -------------------------------------------------------------------------------- /src/cpu/cpu.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Evensgn/RISC-V-CPU/HEAD/src/cpu/cpu.v -------------------------------------------------------------------------------- /src/cpu/ctrl.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Evensgn/RISC-V-CPU/HEAD/src/cpu/ctrl.v -------------------------------------------------------------------------------- /src/cpu/defines.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Evensgn/RISC-V-CPU/HEAD/src/cpu/defines.v -------------------------------------------------------------------------------- /src/cpu/library/clk_wiz_0_tmp.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Evensgn/RISC-V-CPU/HEAD/src/cpu/library/clk_wiz_0_tmp.vhd -------------------------------------------------------------------------------- /src/cpu/library/fifo.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Evensgn/RISC-V-CPU/HEAD/src/cpu/library/fifo.v -------------------------------------------------------------------------------- /src/cpu/library/mfifo.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Evensgn/RISC-V-CPU/HEAD/src/cpu/library/mfifo.v -------------------------------------------------------------------------------- /src/cpu/library/multichan_trans.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Evensgn/RISC-V-CPU/HEAD/src/cpu/library/multichan_trans.v -------------------------------------------------------------------------------- /src/cpu/mem_ctrl.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Evensgn/RISC-V-CPU/HEAD/src/cpu/mem_ctrl.v -------------------------------------------------------------------------------- /src/cpu/no use/inst_rom.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Evensgn/RISC-V-CPU/HEAD/src/cpu/no use/inst_rom.v -------------------------------------------------------------------------------- /src/cpu/no use/ram.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Evensgn/RISC-V-CPU/HEAD/src/cpu/no use/ram.v -------------------------------------------------------------------------------- /src/cpu/no use/riscv_min_sopc.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Evensgn/RISC-V-CPU/HEAD/src/cpu/no use/riscv_min_sopc.v -------------------------------------------------------------------------------- /src/cpu/reg_ex_mem.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Evensgn/RISC-V-CPU/HEAD/src/cpu/reg_ex_mem.v -------------------------------------------------------------------------------- /src/cpu/reg_id_ex.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Evensgn/RISC-V-CPU/HEAD/src/cpu/reg_id_ex.v -------------------------------------------------------------------------------- /src/cpu/reg_if_id.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Evensgn/RISC-V-CPU/HEAD/src/cpu/reg_if_id.v -------------------------------------------------------------------------------- /src/cpu/reg_mem_wb.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Evensgn/RISC-V-CPU/HEAD/src/cpu/reg_mem_wb.v -------------------------------------------------------------------------------- /src/cpu/reg_pc.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Evensgn/RISC-V-CPU/HEAD/src/cpu/reg_pc.v -------------------------------------------------------------------------------- /src/cpu/regfile.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Evensgn/RISC-V-CPU/HEAD/src/cpu/regfile.v -------------------------------------------------------------------------------- /src/cpu/riscv_cpu.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Evensgn/RISC-V-CPU/HEAD/src/cpu/riscv_cpu.v -------------------------------------------------------------------------------- /src/cpu/simple_ram.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Evensgn/RISC-V-CPU/HEAD/src/cpu/simple_ram.v -------------------------------------------------------------------------------- /src/cpu/stage_ex.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Evensgn/RISC-V-CPU/HEAD/src/cpu/stage_ex.v -------------------------------------------------------------------------------- /src/cpu/stage_id.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Evensgn/RISC-V-CPU/HEAD/src/cpu/stage_id.v -------------------------------------------------------------------------------- /src/cpu/stage_if.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Evensgn/RISC-V-CPU/HEAD/src/cpu/stage_if.v -------------------------------------------------------------------------------- /src/cpu/stage_mem.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Evensgn/RISC-V-CPU/HEAD/src/cpu/stage_mem.v -------------------------------------------------------------------------------- /src/cpu/uart_trans.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Evensgn/RISC-V-CPU/HEAD/src/cpu/uart_trans.v -------------------------------------------------------------------------------- /src/cpu/utility.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Evensgn/RISC-V-CPU/HEAD/src/cpu/utility.v -------------------------------------------------------------------------------- /src/memory/adapter.cpp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Evensgn/RISC-V-CPU/HEAD/src/memory/adapter.cpp -------------------------------------------------------------------------------- /src/memory/adapter.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Evensgn/RISC-V-CPU/HEAD/src/memory/adapter.h -------------------------------------------------------------------------------- /src/memory/build.sh: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Evensgn/RISC-V-CPU/HEAD/src/memory/build.sh -------------------------------------------------------------------------------- /src/memory/env_iface.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Evensgn/RISC-V-CPU/HEAD/src/memory/env_iface.h -------------------------------------------------------------------------------- /src/memory/environment.cpp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Evensgn/RISC-V-CPU/HEAD/src/memory/environment.cpp -------------------------------------------------------------------------------- /src/memory/environment.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Evensgn/RISC-V-CPU/HEAD/src/memory/environment.h -------------------------------------------------------------------------------- /src/memory/main.cpp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Evensgn/RISC-V-CPU/HEAD/src/memory/main.cpp -------------------------------------------------------------------------------- /src/memory/memory-simulator.exe: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Evensgn/RISC-V-CPU/HEAD/src/memory/memory-simulator.exe -------------------------------------------------------------------------------- /src/memory/simulator.cpp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Evensgn/RISC-V-CPU/HEAD/src/memory/simulator.cpp -------------------------------------------------------------------------------- /src/memory/simulator.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Evensgn/RISC-V-CPU/HEAD/src/memory/simulator.h -------------------------------------------------------------------------------- /test/Makefile: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Evensgn/RISC-V-CPU/HEAD/test/Makefile -------------------------------------------------------------------------------- /test/bin-tail.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Evensgn/RISC-V-CPU/HEAD/test/bin-tail.py -------------------------------------------------------------------------------- /test/bin2ascii.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Evensgn/RISC-V-CPU/HEAD/test/bin2ascii.py -------------------------------------------------------------------------------- /test/example.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Evensgn/RISC-V-CPU/HEAD/test/example.bin -------------------------------------------------------------------------------- /test/example.data: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Evensgn/RISC-V-CPU/HEAD/test/example.data -------------------------------------------------------------------------------- /test/inst.S: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Evensgn/RISC-V-CPU/HEAD/test/inst.S -------------------------------------------------------------------------------- /test/inst.data: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Evensgn/RISC-V-CPU/HEAD/test/inst.data -------------------------------------------------------------------------------- /test/memory-simulator.exe: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Evensgn/RISC-V-CPU/HEAD/test/memory-simulator.exe -------------------------------------------------------------------------------- /test/memory.ld: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Evensgn/RISC-V-CPU/HEAD/test/memory.ld -------------------------------------------------------------------------------- /test/runtime.txt: -------------------------------------------------------------------------------- 1 | 0 2 | -------------------------------------------------------------------------------- /test/sim_cpu.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Evensgn/RISC-V-CPU/HEAD/test/sim_cpu.v -------------------------------------------------------------------------------- /test/sim_mem.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Evensgn/RISC-V-CPU/HEAD/test/sim_mem.v -------------------------------------------------------------------------------- /test/test.S: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Evensgn/RISC-V-CPU/HEAD/test/test.S -------------------------------------------------------------------------------- /test/test.data: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /test/test_bench.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Evensgn/RISC-V-CPU/HEAD/test/test_bench.v --------------------------------------------------------------------------------