├── .gitignore ├── LICENSE ├── Makefile_sc1 ├── Makefile_sc10 ├── Makefile_sc11 ├── Makefile_sc12 ├── Makefile_sc13 ├── Makefile_sc14 ├── Makefile_sc15 ├── Makefile_sc16 ├── Makefile_sc17 ├── Makefile_sc18 ├── Makefile_sc2 ├── Makefile_sc3 ├── Makefile_sc4 ├── Makefile_sc5 ├── Makefile_sc6 ├── Makefile_sc7 ├── Makefile_sc8 ├── Makefile_sc9 ├── README.md ├── devtools ├── FIFO_rollback_transaction_flow.png ├── FIFO_transaction_flow.png ├── REG_transaction_flow.png ├── SFTREG_transaction_flow.png ├── Scenario11_packet_arbiter_join3.png ├── Scenario18_fifo_with_rollback_schematics.png ├── console_fix.py ├── stringtounicode.py └── unicode_symb.txt ├── hdl ├── scenario1 │ ├── ff_fifo_pow2_depth.sv │ ├── rtl.sv │ └── tb.sv ├── scenario10 │ ├── check.sv │ ├── custom_logic_join.sv │ ├── ff_fifo_pow2_depth.sv │ ├── model.sv │ ├── rtl.sv │ └── tb.sv ├── scenario11 │ ├── check.sv │ ├── custom_logic_join.sv │ ├── custom_logic_join_1.sv.bkp │ ├── custom_logic_join_2.sv.bkp │ ├── custom_logic_join_3.sv.bkp │ ├── ff_fifo_pow2_depth.sv │ ├── model.sv │ ├── rtl.sv │ └── tb.sv ├── scenario12 │ ├── rtl.sv │ ├── shiftreg_4depth.sv │ └── tb.sv ├── scenario13 │ ├── check.sv │ ├── custom_logic.sv │ ├── model.sv │ ├── rtl.sv │ ├── shiftreg_4depth.sv │ └── tb.sv ├── scenario14 │ ├── check.sv │ ├── custom_logic.sv │ ├── ff_fifo_pow2_depth.sv │ ├── model.sv │ ├── rtl.sv │ ├── shiftreg_4depth.sv │ └── tb.sv ├── scenario15 │ ├── ff_fifo_pow2_depth.sv │ ├── rtl.sv │ ├── shiftreg_4depth.sv │ └── tb.sv ├── scenario16 │ ├── check.sv │ ├── credbasedfc_44.sv │ ├── custom_param.sv │ ├── ff_fifo_credret_pow2_depth.sv │ ├── model.sv │ ├── rtl.sv │ └── tb.sv ├── scenario17 │ ├── check.sv │ ├── custom_logic.sv │ ├── model.sv │ ├── rtl.sv │ └── tb.sv ├── scenario18 │ ├── check.sv │ ├── ff_fifo_rollback_pow2_depth.sv │ ├── model.sv │ ├── rtl.sv │ └── tb.sv ├── scenario2 │ ├── check.sv │ ├── ff_fifo_pow2_depth.sv │ ├── model.sv │ ├── rtl.sv │ └── tb.sv ├── scenario3 │ ├── ff_fifo_pow2_depth.sv │ ├── rtl.sv │ └── tb.sv ├── scenario4 │ ├── custom_logic.sv │ ├── ff_fifo_pow2_depth.sv │ ├── rtl.sv │ └── tb.sv ├── scenario5 │ ├── check.sv │ ├── custom_logic.sv │ ├── ff_fifo_pow2_depth.sv │ ├── model.sv │ ├── rtl.sv │ └── tb.sv ├── scenario6 │ ├── check.sv │ ├── ff_fifo_pow2_depth.sv │ ├── model.sv │ ├── rtl.sv │ └── tb.sv ├── scenario7 │ ├── custom_logic_fork.sv │ ├── ff_fifo_pow2_depth.sv │ ├── rtl.sv │ └── tb.sv ├── scenario8 │ ├── check.sv │ ├── custom_logic_fork.sv │ ├── ff_fifo_pow2_depth.sv │ ├── model.sv │ ├── rtl.sv │ └── tb.sv └── scenario9 │ ├── custom_logic_join.sv │ ├── ff_fifo_pow2_depth.sv │ ├── rtl.sv │ └── tb.sv ├── init_scenario1.py ├── init_scenario10.py ├── init_scenario11.py ├── init_scenario12.py ├── init_scenario13.py ├── init_scenario14.py ├── init_scenario15.py ├── init_scenario16.py ├── init_scenario17.py ├── init_scenario18.py ├── init_scenario2.py ├── init_scenario3.py ├── init_scenario4.py ├── init_scenario5.py ├── init_scenario6.py ├── init_scenario7.py ├── init_scenario8.py ├── init_scenario9.py ├── lib ├── __init__.py ├── common │ ├── gadgettop_class.py │ ├── helper_class.py │ ├── program_class.py │ └── scenariotop_class.py ├── gadgets │ ├── gadget_check_arbiter_class.py │ ├── gadget_check_class.py │ ├── gadget_control_arbiter_class.py │ ├── gadget_control_class.py │ ├── gadget_control_fork_class.py │ ├── gadget_control_join_class.py │ ├── gadget_credbasedfc44_class.py │ ├── gadget_credbasedfc4Xtr_class.py │ ├── gadget_credbasedfcX4tr_class.py │ ├── gadget_custlogic_alone_class.py │ ├── gadget_custlogic_class.py │ ├── gadget_custlogic_xl_class.py │ ├── gadget_fifo_class.py │ ├── gadget_fifobase_class.py │ ├── gadget_fifocreditreturn_class.py │ ├── gadget_fiforollback_class.py │ ├── gadget_fiforollbacktr_class.py │ ├── gadget_fifotr_class.py │ ├── gadget_fplate_sc10_class.py │ ├── gadget_fplate_sc11_class.py │ ├── gadget_fplate_sc12_class.py │ ├── gadget_fplate_sc13_class.py │ ├── gadget_fplate_sc14_class.py │ ├── gadget_fplate_sc15_class.py │ ├── gadget_fplate_sc16_class.py │ ├── gadget_fplate_sc17_class.py │ ├── gadget_fplate_sc18_class.py │ ├── gadget_fplate_sc1_class.py │ ├── gadget_fplate_sc2_class.py │ ├── gadget_fplate_sc3_class.py │ ├── gadget_fplate_sc4_class.py │ ├── gadget_fplate_sc5_class.py │ ├── gadget_fplate_sc6_class.py │ ├── gadget_fplate_sc7_class.py │ ├── gadget_fplate_sc8_class.py │ ├── gadget_fplate_sc9_class.py │ ├── gadget_modelqueue_class.py │ ├── gadget_modelqueuea_class.py │ ├── gadget_modelqueueb_class.py │ ├── gadget_modelqueuebase_class.py │ ├── gadget_shiftreg_class.py │ └── gadget_shiftregtr_class.py ├── scenario10_class.py ├── scenario11_class.py ├── scenario12_class.py ├── scenario13_class.py ├── scenario14_class.py ├── scenario15_class.py ├── scenario16_class.py ├── scenario17_class.py ├── scenario18_class.py ├── scenario1_class.py ├── scenario2_class.py ├── scenario3_class.py ├── scenario4_class.py ├── scenario5_class.py ├── scenario6_class.py ├── scenario7_class.py ├── scenario8_class.py └── scenario9_class.py ├── sim_build └── .gitignore └── start.bash /.gitignore: -------------------------------------------------------------------------------- 1 | __pycache__/ 2 | *.py[cod] 3 | *$py.class 4 | /results.xml 5 | /logfile.txt 6 | -------------------------------------------------------------------------------- /LICENSE: -------------------------------------------------------------------------------- 1 | MIT License 2 | 3 | Copyright (c) 2023 Vladimir Efimov 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in all 13 | copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 | SOFTWARE. 22 | -------------------------------------------------------------------------------- /Makefile_sc1: -------------------------------------------------------------------------------- 1 | # Makefile 2 | 3 | # defaults 4 | SIM ?= icarus 5 | TOPLEVEL_LANG ?= verilog 6 | 7 | 8 | VERILOG_SOURCES += $(PWD)/hdl/scenario1/tb.sv 9 | VERILOG_SOURCES += $(PWD)/hdl/scenario1/rtl.sv 10 | VERILOG_SOURCES += $(PWD)/hdl/scenario1/ff_fifo_pow2_depth.sv 11 | # use VHDL_SOURCES for VHDL files 12 | 13 | # TOPLEVEL is the name of the toplevel module in your Verilog or VHDL file 14 | TOPLEVEL = tb 15 | 16 | # MODULE is the basename of the Python test file 17 | MODULE = init_scenario1 18 | 19 | # include cocotb's make rules to take care of the simulator setup 20 | include $(shell cocotb-config --makefiles)/Makefile.sim 21 | 22 | -------------------------------------------------------------------------------- /Makefile_sc10: -------------------------------------------------------------------------------- 1 | # Makefile 2 | 3 | # defaults 4 | SIM ?= icarus 5 | TOPLEVEL_LANG ?= verilog 6 | 7 | 8 | VERILOG_SOURCES += $(PWD)/hdl/scenario10/tb.sv 9 | VERILOG_SOURCES += $(PWD)/hdl/scenario10/rtl.sv 10 | VERILOG_SOURCES += $(PWD)/hdl/scenario10/ff_fifo_pow2_depth.sv 11 | VERILOG_SOURCES += $(PWD)/hdl/scenario10/custom_logic_join.sv 12 | VERILOG_SOURCES += $(PWD)/hdl/scenario10/model.sv 13 | VERILOG_SOURCES += $(PWD)/hdl/scenario10/check.sv 14 | # use VHDL_SOURCES for VHDL files 15 | 16 | # TOPLEVEL is the name of the toplevel module in your Verilog or VHDL file 17 | TOPLEVEL = tb 18 | 19 | # MODULE is the basename of the Python test file 20 | MODULE = init_scenario10 21 | 22 | # include cocotb's make rules to take care of the simulator setup 23 | include $(shell cocotb-config --makefiles)/Makefile.sim 24 | 25 | -------------------------------------------------------------------------------- /Makefile_sc11: -------------------------------------------------------------------------------- 1 | # Makefile 2 | 3 | # defaults 4 | SIM ?= icarus 5 | TOPLEVEL_LANG ?= verilog 6 | 7 | 8 | VERILOG_SOURCES += $(PWD)/hdl/scenario11/tb.sv 9 | VERILOG_SOURCES += $(PWD)/hdl/scenario11/rtl.sv 10 | VERILOG_SOURCES += $(PWD)/hdl/scenario11/ff_fifo_pow2_depth.sv 11 | VERILOG_SOURCES += $(PWD)/hdl/scenario11/custom_logic_join.sv 12 | VERILOG_SOURCES += $(PWD)/hdl/scenario11/model.sv 13 | VERILOG_SOURCES += $(PWD)/hdl/scenario11/check.sv 14 | # use VHDL_SOURCES for VHDL files 15 | 16 | # TOPLEVEL is the name of the toplevel module in your Verilog or VHDL file 17 | TOPLEVEL = tb 18 | 19 | # MODULE is the basename of the Python test file 20 | MODULE = init_scenario11 21 | 22 | # include cocotb's make rules to take care of the simulator setup 23 | include $(shell cocotb-config --makefiles)/Makefile.sim 24 | 25 | -------------------------------------------------------------------------------- /Makefile_sc12: -------------------------------------------------------------------------------- 1 | # Makefile 2 | 3 | # defaults 4 | SIM ?= icarus 5 | TOPLEVEL_LANG ?= verilog 6 | 7 | 8 | VERILOG_SOURCES += $(PWD)/hdl/scenario12/tb.sv 9 | VERILOG_SOURCES += $(PWD)/hdl/scenario12/rtl.sv 10 | VERILOG_SOURCES += $(PWD)/hdl/scenario12/shiftreg_4depth.sv 11 | # use VHDL_SOURCES for VHDL files 12 | 13 | # TOPLEVEL is the name of the toplevel module in your Verilog or VHDL file 14 | TOPLEVEL = tb 15 | 16 | # MODULE is the basename of the Python test file 17 | MODULE = init_scenario12 18 | 19 | # include cocotb's make rules to take care of the simulator setup 20 | include $(shell cocotb-config --makefiles)/Makefile.sim 21 | 22 | -------------------------------------------------------------------------------- /Makefile_sc13: -------------------------------------------------------------------------------- 1 | # Makefile 2 | 3 | # defaults 4 | SIM ?= icarus 5 | TOPLEVEL_LANG ?= verilog 6 | 7 | 8 | VERILOG_SOURCES += $(PWD)/hdl/scenario13/tb.sv 9 | VERILOG_SOURCES += $(PWD)/hdl/scenario13/rtl.sv 10 | VERILOG_SOURCES += $(PWD)/hdl/scenario13/shiftreg_4depth.sv 11 | VERILOG_SOURCES += $(PWD)/hdl/scenario13/custom_logic.sv 12 | VERILOG_SOURCES += $(PWD)/hdl/scenario13/model.sv 13 | VERILOG_SOURCES += $(PWD)/hdl/scenario13/check.sv 14 | # use VHDL_SOURCES for VHDL files 15 | 16 | # TOPLEVEL is the name of the toplevel module in your Verilog or VHDL file 17 | TOPLEVEL = tb 18 | 19 | # MODULE is the basename of the Python test file 20 | MODULE = init_scenario13 21 | 22 | # include cocotb's make rules to take care of the simulator setup 23 | include $(shell cocotb-config --makefiles)/Makefile.sim 24 | 25 | -------------------------------------------------------------------------------- /Makefile_sc14: -------------------------------------------------------------------------------- 1 | # Makefile 2 | 3 | # defaults 4 | SIM ?= icarus 5 | TOPLEVEL_LANG ?= verilog 6 | 7 | 8 | VERILOG_SOURCES += $(PWD)/hdl/scenario14/tb.sv 9 | VERILOG_SOURCES += $(PWD)/hdl/scenario14/rtl.sv 10 | VERILOG_SOURCES += $(PWD)/hdl/scenario14/shiftreg_4depth.sv 11 | VERILOG_SOURCES += $(PWD)/hdl/scenario14/ff_fifo_pow2_depth.sv 12 | VERILOG_SOURCES += $(PWD)/hdl/scenario14/custom_logic.sv 13 | VERILOG_SOURCES += $(PWD)/hdl/scenario14/model.sv 14 | VERILOG_SOURCES += $(PWD)/hdl/scenario14/check.sv 15 | # use VHDL_SOURCES for VHDL files 16 | 17 | # TOPLEVEL is the name of the toplevel module in your Verilog or VHDL file 18 | TOPLEVEL = tb 19 | 20 | # MODULE is the basename of the Python test file 21 | MODULE = init_scenario14 22 | 23 | # include cocotb's make rules to take care of the simulator setup 24 | include $(shell cocotb-config --makefiles)/Makefile.sim 25 | 26 | -------------------------------------------------------------------------------- /Makefile_sc15: -------------------------------------------------------------------------------- 1 | # Makefile 2 | 3 | # defaults 4 | SIM ?= icarus 5 | TOPLEVEL_LANG ?= verilog 6 | 7 | 8 | VERILOG_SOURCES += $(PWD)/hdl/scenario15/tb.sv 9 | VERILOG_SOURCES += $(PWD)/hdl/scenario15/rtl.sv 10 | VERILOG_SOURCES += $(PWD)/hdl/scenario15/shiftreg_4depth.sv 11 | VERILOG_SOURCES += $(PWD)/hdl/scenario15/ff_fifo_pow2_depth.sv 12 | 13 | # use VHDL_SOURCES for VHDL files 14 | 15 | # TOPLEVEL is the name of the toplevel module in your Verilog or VHDL file 16 | TOPLEVEL = tb 17 | 18 | # MODULE is the basename of the Python test file 19 | MODULE = init_scenario15 20 | 21 | # include cocotb's make rules to take care of the simulator setup 22 | include $(shell cocotb-config --makefiles)/Makefile.sim 23 | 24 | -------------------------------------------------------------------------------- /Makefile_sc16: -------------------------------------------------------------------------------- 1 | # Makefile 2 | 3 | # defaults 4 | SIM ?= icarus 5 | TOPLEVEL_LANG ?= verilog 6 | 7 | 8 | VERILOG_SOURCES += $(PWD)/hdl/scenario16/tb.sv 9 | VERILOG_SOURCES += $(PWD)/hdl/scenario16/rtl.sv 10 | VERILOG_SOURCES += $(PWD)/hdl/scenario16/credbasedfc_44.sv 11 | VERILOG_SOURCES += $(PWD)/hdl/scenario16/ff_fifo_credret_pow2_depth.sv 12 | VERILOG_SOURCES += $(PWD)/hdl/scenario16/custom_param.sv 13 | VERILOG_SOURCES += $(PWD)/hdl/scenario16/model.sv 14 | VERILOG_SOURCES += $(PWD)/hdl/scenario16/check.sv 15 | # use VHDL_SOURCES for VHDL files 16 | 17 | # TOPLEVEL is the name of the toplevel module in your Verilog or VHDL file 18 | TOPLEVEL = tb 19 | 20 | # MODULE is the basename of the Python test file 21 | MODULE = init_scenario16 22 | 23 | # include cocotb's make rules to take care of the simulator setup 24 | include $(shell cocotb-config --makefiles)/Makefile.sim 25 | 26 | -------------------------------------------------------------------------------- /Makefile_sc17: -------------------------------------------------------------------------------- 1 | # Makefile 2 | 3 | # defaults 4 | SIM ?= icarus 5 | TOPLEVEL_LANG ?= verilog 6 | 7 | 8 | VERILOG_SOURCES += $(PWD)/hdl/scenario17/tb.sv 9 | VERILOG_SOURCES += $(PWD)/hdl/scenario17/rtl.sv 10 | VERILOG_SOURCES += $(PWD)/hdl/scenario17/custom_logic.sv 11 | VERILOG_SOURCES += $(PWD)/hdl/scenario17/model.sv 12 | VERILOG_SOURCES += $(PWD)/hdl/scenario17/check.sv 13 | # use VHDL_SOURCES for VHDL files 14 | 15 | # TOPLEVEL is the name of the toplevel module in your Verilog or VHDL file 16 | TOPLEVEL = tb 17 | 18 | # MODULE is the basename of the Python test file 19 | MODULE = init_scenario17 20 | 21 | # include cocotb's make rules to take care of the simulator setup 22 | include $(shell cocotb-config --makefiles)/Makefile.sim 23 | 24 | -------------------------------------------------------------------------------- /Makefile_sc18: -------------------------------------------------------------------------------- 1 | # Makefile 2 | 3 | # defaults 4 | SIM ?= icarus 5 | TOPLEVEL_LANG ?= verilog 6 | 7 | 8 | VERILOG_SOURCES += $(PWD)/hdl/scenario18/tb.sv 9 | VERILOG_SOURCES += $(PWD)/hdl/scenario18/rtl.sv 10 | VERILOG_SOURCES += $(PWD)/hdl/scenario18/ff_fifo_rollback_pow2_depth.sv 11 | VERILOG_SOURCES += $(PWD)/hdl/scenario18/model.sv 12 | VERILOG_SOURCES += $(PWD)/hdl/scenario18/check.sv 13 | # use VHDL_SOURCES for VHDL files 14 | 15 | # TOPLEVEL is the name of the toplevel module in your Verilog or VHDL file 16 | TOPLEVEL = tb 17 | 18 | # MODULE is the basename of the Python test file 19 | MODULE = init_scenario18 20 | 21 | # include cocotb's make rules to take care of the simulator setup 22 | include $(shell cocotb-config --makefiles)/Makefile.sim 23 | 24 | -------------------------------------------------------------------------------- /Makefile_sc2: -------------------------------------------------------------------------------- 1 | # Makefile 2 | 3 | # defaults 4 | SIM ?= icarus 5 | TOPLEVEL_LANG ?= verilog 6 | 7 | 8 | VERILOG_SOURCES += $(PWD)/hdl/scenario2/tb.sv 9 | VERILOG_SOURCES += $(PWD)/hdl/scenario2/rtl.sv 10 | VERILOG_SOURCES += $(PWD)/hdl/scenario2/ff_fifo_pow2_depth.sv 11 | VERILOG_SOURCES += $(PWD)/hdl/scenario2/model.sv 12 | VERILOG_SOURCES += $(PWD)/hdl/scenario2/check.sv 13 | # use VHDL_SOURCES for VHDL files 14 | 15 | # TOPLEVEL is the name of the toplevel module in your Verilog or VHDL file 16 | TOPLEVEL = tb 17 | 18 | # MODULE is the basename of the Python test file 19 | MODULE = init_scenario2 20 | 21 | # include cocotb's make rules to take care of the simulator setup 22 | include $(shell cocotb-config --makefiles)/Makefile.sim 23 | 24 | -------------------------------------------------------------------------------- /Makefile_sc3: -------------------------------------------------------------------------------- 1 | # Makefile 2 | 3 | # defaults 4 | SIM ?= icarus 5 | TOPLEVEL_LANG ?= verilog 6 | 7 | 8 | VERILOG_SOURCES += $(PWD)/hdl/scenario3/tb.sv 9 | VERILOG_SOURCES += $(PWD)/hdl/scenario3/rtl.sv 10 | VERILOG_SOURCES += $(PWD)/hdl/scenario3/ff_fifo_pow2_depth.sv 11 | # use VHDL_SOURCES for VHDL files 12 | 13 | # TOPLEVEL is the name of the toplevel module in your Verilog or VHDL file 14 | TOPLEVEL = tb 15 | 16 | # MODULE is the basename of the Python test file 17 | MODULE = init_scenario3 18 | 19 | # include cocotb's make rules to take care of the simulator setup 20 | include $(shell cocotb-config --makefiles)/Makefile.sim 21 | 22 | -------------------------------------------------------------------------------- /Makefile_sc4: -------------------------------------------------------------------------------- 1 | # Makefile 2 | 3 | # defaults 4 | SIM ?= icarus 5 | TOPLEVEL_LANG ?= verilog 6 | 7 | 8 | VERILOG_SOURCES += $(PWD)/hdl/scenario4/tb.sv 9 | VERILOG_SOURCES += $(PWD)/hdl/scenario4/rtl.sv 10 | VERILOG_SOURCES += $(PWD)/hdl/scenario4/ff_fifo_pow2_depth.sv 11 | VERILOG_SOURCES += $(PWD)/hdl/scenario4/custom_logic.sv 12 | # use VHDL_SOURCES for VHDL files 13 | 14 | # TOPLEVEL is the name of the toplevel module in your Verilog or VHDL file 15 | TOPLEVEL = tb 16 | 17 | # MODULE is the basename of the Python test file 18 | MODULE = init_scenario4 19 | 20 | # include cocotb's make rules to take care of the simulator setup 21 | include $(shell cocotb-config --makefiles)/Makefile.sim 22 | 23 | -------------------------------------------------------------------------------- /Makefile_sc5: -------------------------------------------------------------------------------- 1 | # Makefile 2 | 3 | # defaults 4 | SIM ?= icarus 5 | TOPLEVEL_LANG ?= verilog 6 | 7 | 8 | VERILOG_SOURCES += $(PWD)/hdl/scenario5/tb.sv 9 | VERILOG_SOURCES += $(PWD)/hdl/scenario5/rtl.sv 10 | VERILOG_SOURCES += $(PWD)/hdl/scenario5/ff_fifo_pow2_depth.sv 11 | VERILOG_SOURCES += $(PWD)/hdl/scenario5/custom_logic.sv 12 | VERILOG_SOURCES += $(PWD)/hdl/scenario5/model.sv 13 | VERILOG_SOURCES += $(PWD)/hdl/scenario5/check.sv 14 | # use VHDL_SOURCES for VHDL files 15 | 16 | # TOPLEVEL is the name of the toplevel module in your Verilog or VHDL file 17 | TOPLEVEL = tb 18 | 19 | # MODULE is the basename of the Python test file 20 | MODULE = init_scenario5 21 | 22 | # include cocotb's make rules to take care of the simulator setup 23 | include $(shell cocotb-config --makefiles)/Makefile.sim 24 | 25 | -------------------------------------------------------------------------------- /Makefile_sc6: -------------------------------------------------------------------------------- 1 | # Makefile 2 | 3 | # defaults 4 | SIM ?= icarus 5 | TOPLEVEL_LANG ?= verilog 6 | 7 | 8 | VERILOG_SOURCES += $(PWD)/hdl/scenario6/tb.sv 9 | VERILOG_SOURCES += $(PWD)/hdl/scenario6/rtl.sv 10 | VERILOG_SOURCES += $(PWD)/hdl/scenario6/ff_fifo_pow2_depth.sv 11 | VERILOG_SOURCES += $(PWD)/hdl/scenario6/model.sv 12 | VERILOG_SOURCES += $(PWD)/hdl/scenario6/check.sv 13 | # use VHDL_SOURCES for VHDL files 14 | 15 | # TOPLEVEL is the name of the toplevel module in your Verilog or VHDL file 16 | TOPLEVEL = tb 17 | 18 | # MODULE is the basename of the Python test file 19 | MODULE = init_scenario6 20 | 21 | # include cocotb's make rules to take care of the simulator setup 22 | include $(shell cocotb-config --makefiles)/Makefile.sim 23 | 24 | -------------------------------------------------------------------------------- /Makefile_sc7: -------------------------------------------------------------------------------- 1 | # Makefile 2 | 3 | # defaults 4 | SIM ?= icarus 5 | TOPLEVEL_LANG ?= verilog 6 | 7 | 8 | VERILOG_SOURCES += $(PWD)/hdl/scenario7/tb.sv 9 | VERILOG_SOURCES += $(PWD)/hdl/scenario7/rtl.sv 10 | VERILOG_SOURCES += $(PWD)/hdl/scenario7/ff_fifo_pow2_depth.sv 11 | VERILOG_SOURCES += $(PWD)/hdl/scenario7/custom_logic_fork.sv 12 | # use VHDL_SOURCES for VHDL files 13 | 14 | # TOPLEVEL is the name of the toplevel module in your Verilog or VHDL file 15 | TOPLEVEL = tb 16 | 17 | # MODULE is the basename of the Python test file 18 | MODULE = init_scenario7 19 | 20 | # include cocotb's make rules to take care of the simulator setup 21 | include $(shell cocotb-config --makefiles)/Makefile.sim 22 | 23 | -------------------------------------------------------------------------------- /Makefile_sc8: -------------------------------------------------------------------------------- 1 | # Makefile 2 | 3 | # defaults 4 | SIM ?= icarus 5 | TOPLEVEL_LANG ?= verilog 6 | 7 | 8 | VERILOG_SOURCES += $(PWD)/hdl/scenario8/tb.sv 9 | VERILOG_SOURCES += $(PWD)/hdl/scenario8/rtl.sv 10 | VERILOG_SOURCES += $(PWD)/hdl/scenario8/ff_fifo_pow2_depth.sv 11 | VERILOG_SOURCES += $(PWD)/hdl/scenario8/custom_logic_fork.sv 12 | VERILOG_SOURCES += $(PWD)/hdl/scenario8/model.sv 13 | VERILOG_SOURCES += $(PWD)/hdl/scenario8/check.sv 14 | # use VHDL_SOURCES for VHDL files 15 | 16 | # TOPLEVEL is the name of the toplevel module in your Verilog or VHDL file 17 | TOPLEVEL = tb 18 | 19 | # MODULE is the basename of the Python test file 20 | MODULE = init_scenario8 21 | 22 | # include cocotb's make rules to take care of the simulator setup 23 | include $(shell cocotb-config --makefiles)/Makefile.sim 24 | 25 | -------------------------------------------------------------------------------- /Makefile_sc9: -------------------------------------------------------------------------------- 1 | # Makefile 2 | 3 | # defaults 4 | SIM ?= icarus 5 | TOPLEVEL_LANG ?= verilog 6 | 7 | 8 | VERILOG_SOURCES += $(PWD)/hdl/scenario9/tb.sv 9 | VERILOG_SOURCES += $(PWD)/hdl/scenario9/rtl.sv 10 | VERILOG_SOURCES += $(PWD)/hdl/scenario9/ff_fifo_pow2_depth.sv 11 | VERILOG_SOURCES += $(PWD)/hdl/scenario9/custom_logic_join.sv 12 | # use VHDL_SOURCES for VHDL files 13 | 14 | # TOPLEVEL is the name of the toplevel module in your Verilog or VHDL file 15 | TOPLEVEL = tb 16 | 17 | # MODULE is the basename of the Python test file 18 | MODULE = init_scenario9 19 | 20 | # include cocotb's make rules to take care of the simulator setup 21 | include $(shell cocotb-config --makefiles)/Makefile.sim 22 | 23 | -------------------------------------------------------------------------------- /devtools/FIFO_rollback_transaction_flow.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/FPGA-InsideOut/hdlgadgets/6dc2ae8860b647fd0beb402263973db8f6b506e4/devtools/FIFO_rollback_transaction_flow.png -------------------------------------------------------------------------------- /devtools/FIFO_transaction_flow.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/FPGA-InsideOut/hdlgadgets/6dc2ae8860b647fd0beb402263973db8f6b506e4/devtools/FIFO_transaction_flow.png -------------------------------------------------------------------------------- /devtools/REG_transaction_flow.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/FPGA-InsideOut/hdlgadgets/6dc2ae8860b647fd0beb402263973db8f6b506e4/devtools/REG_transaction_flow.png -------------------------------------------------------------------------------- /devtools/SFTREG_transaction_flow.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/FPGA-InsideOut/hdlgadgets/6dc2ae8860b647fd0beb402263973db8f6b506e4/devtools/SFTREG_transaction_flow.png -------------------------------------------------------------------------------- /devtools/Scenario11_packet_arbiter_join3.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/FPGA-InsideOut/hdlgadgets/6dc2ae8860b647fd0beb402263973db8f6b506e4/devtools/Scenario11_packet_arbiter_join3.png -------------------------------------------------------------------------------- /devtools/Scenario18_fifo_with_rollback_schematics.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/FPGA-InsideOut/hdlgadgets/6dc2ae8860b647fd0beb402263973db8f6b506e4/devtools/Scenario18_fifo_with_rollback_schematics.png -------------------------------------------------------------------------------- /devtools/console_fix.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env python3 2 | import curses 3 | 4 | ctx = curses.initscr() 5 | curses.cbreak() 6 | curses.noecho() 7 | curses.curs_set(0) 8 | ctx.keypad(True) 9 | 10 | curses.nocbreak() 11 | ctx.keypad(0) 12 | curses.echo() 13 | curses.curs_set(1) 14 | curses.endwin() 15 | 16 | del ctx 17 | -------------------------------------------------------------------------------- /devtools/unicode_symb.txt: -------------------------------------------------------------------------------- 1 | ─ ━ │ ┃ ┄ ┅ ┆ ┇ ┈ ┉ ┊ ┋ ┌ ┍ ┎ ┏ ┐ ┑ ┒ ┓ └ ┕ ┖ ┗ ┘ ┙ ┚ ┛ 2 | 3 | 4 | ├ ┝ ┞ ┟ ┠ ┡ ┢ ┣ ┤ ┥ ┦ ┧ ┨ ┩ ┪ ╇ ╈ ╉ ╊ ╋ ╌ ╍ ╎ ╏ ═ ║ ╒ ╓ ╔ ╕ ╖ ╗ 5 | 6 | ╘ ╙ ╚ ╛ ╜ ╝ ╞ ╟ ╠ ╡ ╢ ╣ ╤ ╥ ╦ ╧ ╨ ╩ ╪ ╫ ╬ ╭ ╮ ╯ ╰ ╱ ╲ ╳ ╴ ╵ ╶ ╷ ╸ ╹ ╺ ╻ ╼ ╽ ╾ ╿ 7 | 8 | ▀ ▁ ▂ ▃ ▄ ▅ ▆ ▇ █ ▉ ▊ ▋ ▌ ▍ ▎ ▏ ▐ ░ ▒ ▓ ▔ ▕ 9 | 10 | ▖ ▗ ▘ ▙ ▚ ▛ ▜ ▝ ▞ ▟ ■ ▯ ▰ ▱ ▲ △ ▴ ▵ ▶ ▷ ▸ ▹ ► ▻ ▼ ▽ ▾ ▿ 11 | 12 | ◀ ◁ ◂ ◃ ◄ ◅ ◆ ◇ ◈ ◉ ◊ ○ ◌ ◍ ◎ ● ◐ ◑ ◒ ❮❯ ❰❱ ❬❭ 13 | 14 | ╶╶╶ ─── ⑅⑅⑅⑅⑅ ╶╶╶ ─── ⑅⑅⑅⑅⑅ ⸳⸳⸳⸳⸳⸳ ×××××× 15 | ┓┛━┯┷│┏┗┃ 16 | 17 | ☒ 18 | 19 | ┯━━━━━━━━┓ 20 | │ xxxxxx ┃ 21 | ┷━━━━━━━━┛ 22 | 23 | ┏━━━━━━━━━━━━┓ ┏━━━━━━━━━━━━┓ 24 | ╭─❱┃ xxxxxx ◉ ┃──╮ ╭─❱┃ xxxxxx ◉ ┃──╮ 25 | │ ┃────────────┃ │ │ ┃────────────┃ │ 26 | │ ┃ xxxxxx ◉ ┃ │ │ ┃ xxxxxx ◉ ┃ │ 27 | ━━━━000000━◉╾╯ ┃────────────┃ ╰╼━━000000━━━❱━━━━000000━◉╾╯ ┃────────────┃ ╰╼━━000000━━━❱ 28 | ┃ xxxxxx ○ ┃ ┃ xxxxxx ○ ┃ 29 | ┃────────────┃ ┃────────────┃ 30 | ┃ xxxxxx ○ ┃ ┃ xxxxxx ○ ┃ 31 | ┡━━━━━━━━━━━━┩ ┡━━━━━━━━━━━━┩ 32 | │000 000│ │000 000│ 33 | ┄┄┄┄valid┄┄┄┄┄┄❭│ empty│┄┄┄┄┄┄┄valid┄┄┄❭┄┄┄┄valid┄┄┄┄┄┄❭│ empty│┄┄┄┄┄┄┄valid┄┄┄❭ 34 | ❬┄┄┄ready┄┄┄┄┄┄┄│full │❬┄┄┄┄┄┄ready┄┄┄┄❬┄┄┄ready┄┄┄┄┄┄┄│full │❬┄┄┄┄┄┄ready┄┄┄┄ 35 | └────────────┘ └────────────┘ 36 | 37 | ┏━━━━━━━━━━━━┓ 38 | ╭─❱┃ xxxxxx ◉ ┃──╮ 39 | │ ┃────────────┃ │ 40 | │ ┃ xxxxxx ◉ ┃ │ 41 | ━━━━000000━◉╾╯ ┃────────────┃ ╰╼━━000000━━━❱ 42 | ┃ xxxxxx ○ ┃ 43 | ┃────────────┃ 44 | ┃ xxxxxx ○ ┃ 45 | ┡━━━━━━━━━━━━┩ 46 | │000 000│ 47 | ┄┄┄┄valid┄┄┄┄┄┄❭│ empty│┄┄┄┄┄┄┄valid┄┄┄❭ 48 | ❬┄┄┄ready┄┄┄┄┄┄┄│full │❬┄┄┄┄┄┄ready┄┄┄┄ 49 | └────────────┘ 50 | 51 | 52 | reset ○ - "R-key" 53 | up_valid ○ - "A-key" 54 | up_data ◉◉◉◉◉◉◉ - "Z,X,C,V,B,N-keys" 55 | down_ready ○ - "S-key" 56 | Clock - "ENTER-key" 57 | Quit - "ESC-key" -------------------------------------------------------------------------------- /hdl/scenario1/ff_fifo_pow2_depth.sv: -------------------------------------------------------------------------------- 1 | //---AXI-STREAM FLOP-BASED FIFO WITH DEPTH OF PWR OF 2---// 2 | //Valid/Rready flags generation is based on comparison of write & read counters 3 | //and their MSBs that indicate "Wrap-around", as per Clifford_E_Cummings. 4 | 5 | module ff_fifo_pow2_depth #(parameter D_WIDTH = 6, A_WIDTH = 2) 6 | ( 7 | input clk, 8 | input rst, 9 | input [(D_WIDTH-1):0] up_data, 10 | input up_valid, 11 | output up_ready, 12 | output [(D_WIDTH-1):0] down_data, 13 | output down_valid, 14 | input down_ready 15 | ); 16 | 17 | wire push, pop; 18 | wire empty, full; 19 | wire [(A_WIDTH-1):0] wr_ptr, rd_ptr; 20 | 21 | reg [(A_WIDTH):0] fullwidth_wr_ptr, fullwidth_rd_ptr; 22 | reg [(D_WIDTH-1):0] ram[2**A_WIDTH-1:0]; 23 | 24 | 25 | always @ (posedge clk) 26 | begin 27 | if (push) 28 | ram[wr_ptr] <= up_data; 29 | end 30 | 31 | //WR_COUNTER 32 | always @(posedge clk) 33 | if (rst) begin 34 | fullwidth_wr_ptr <= {(A_WIDTH+1){1'b0}}; 35 | end else if (push) begin 36 | fullwidth_wr_ptr <= fullwidth_wr_ptr + 1; 37 | end 38 | 39 | //RD_COUNTER 40 | always @(posedge clk) 41 | if (rst) begin 42 | fullwidth_rd_ptr <= {(A_WIDTH+1){1'b0}}; 43 | end else if (pop) begin 44 | fullwidth_rd_ptr <= fullwidth_rd_ptr + 1; 45 | end 46 | 47 | //Generate push and pop signals 48 | assign push = up_valid & up_ready; 49 | assign pop = down_valid & down_ready; 50 | 51 | //output LSBits out of full_wr_ptr 52 | assign wr_ptr = fullwidth_wr_ptr[(A_WIDTH-1):0]; 53 | //output LSBits out of full_rd_ptr 54 | assign rd_ptr = fullwidth_rd_ptr[(A_WIDTH-1):0]; 55 | 56 | //"empty" 57 | //It is "1" when MSBits and other bits of "full_rd_ptr" and "full_wr_ptr" are equal 58 | assign empty = ((fullwidth_wr_ptr[(A_WIDTH)] == fullwidth_rd_ptr[(A_WIDTH)]) && 59 | (fullwidth_wr_ptr[(A_WIDTH-1):0] == fullwidth_rd_ptr[(A_WIDTH-1):0])) ? 1'b1 : 1'b0; 60 | //"valid" aka "not_empty" 61 | assign down_valid = ~empty; 62 | 63 | //"full" 64 | //It is "1" when MSBits of "full_rd_ptr" and "full_wr_ptr" are not equal but other bits equal 65 | assign full = ((fullwidth_wr_ptr[(A_WIDTH)] != fullwidth_rd_ptr[(A_WIDTH)]) && 66 | (fullwidth_wr_ptr[(A_WIDTH-1):0] == fullwidth_rd_ptr[(A_WIDTH-1):0])) ? 1'b1 : 1'b0; 67 | //"ready" aka "not_full" 68 | assign up_ready = ~full; 69 | 70 | assign down_data = ram[rd_ptr]; 71 | 72 | endmodule 73 | -------------------------------------------------------------------------------- /hdl/scenario1/rtl.sv: -------------------------------------------------------------------------------- 1 | //---TOP MODULE FOR RTL DESIGN---// 2 | 3 | module rtl #(parameter D_WIDTH = 6, A_WIDTH = 2) 4 | ( 5 | input clk, 6 | input rst, 7 | input [(D_WIDTH-1):0] up_data, 8 | input up_valid, 9 | output up_ready, 10 | output [(D_WIDTH-1):0] down_data, 11 | output down_valid, 12 | input down_ready 13 | ); 14 | 15 | ff_fifo_pow2_depth # (.D_WIDTH (D_WIDTH), .A_WIDTH (A_WIDTH)) 16 | FIFO1 17 | ( .clk(clk), 18 | .rst(rst), 19 | .up_data(up_data), 20 | .up_valid(up_valid), 21 | .up_ready(up_ready), 22 | .down_data(down_data), 23 | .down_valid(down_valid), 24 | .down_ready(down_ready)); 25 | 26 | endmodule 27 | -------------------------------------------------------------------------------- /hdl/scenario1/tb.sv: -------------------------------------------------------------------------------- 1 | module tb 2 | # ( 3 | parameter D_WIDTH = 6, A_WIDTH = 2 4 | ); 5 | 6 | //-------------------------------------------------------------------------- 7 | // Signals to drive Device Under Test - DUT 8 | 9 | logic clk; 10 | wire rst; 11 | 12 | // Upstream 13 | 14 | wire up_valid; 15 | wire up_ready; 16 | wire [(D_WIDTH-1):0] up_data; 17 | 18 | // Downstream 19 | 20 | wire down_valid; 21 | wire down_ready; 22 | wire [(D_WIDTH-1):0] down_data; 23 | 24 | //-------------------------------------------------------------------------- 25 | // DUT instantiation 26 | 27 | rtl # (.D_WIDTH (D_WIDTH), .A_WIDTH (A_WIDTH)) 28 | RTL1 29 | ( .clk(clk), 30 | .rst(rst), 31 | .up_data(up_data), 32 | .up_valid(up_valid), 33 | .up_ready(up_ready), 34 | .down_data(down_data), 35 | .down_valid(down_valid), 36 | .down_ready(down_ready)); 37 | 38 | //-------------------------------------------------------------------------- 39 | // Driving clock 40 | 41 | initial 42 | begin 43 | forever #5 clk = ~ clk; 44 | end 45 | 46 | //-------------------------------------------------------------------------- 47 | //Initialization and driving simulation 48 | initial 49 | begin 50 | clk = 0; 51 | forever @ (posedge clk); 52 | end 53 | 54 | endmodule 55 | -------------------------------------------------------------------------------- /hdl/scenario10/check.sv: -------------------------------------------------------------------------------- 1 | module check #(parameter D_WIDTH = 6) 2 | ( 3 | input [(D_WIDTH-1):0] rtl_data, 4 | input rtl_valid, 5 | input [(D_WIDTH-1):0] model_data 6 | ); 7 | 8 | //This is a BLACKBOX MODULE 9 | //All input ports are not used inside the module because they will be accessed externally from python 10 | //using hierarchical references and used in "post_process_logic_state" call of "check_gadget". 11 | 12 | endmodule 13 | -------------------------------------------------------------------------------- /hdl/scenario10/custom_logic_join.sv: -------------------------------------------------------------------------------- 1 | module custom_logic_join #(parameter D_WIDTH = 6) 2 | ( 3 | input clk, 4 | input rst, 5 | input [(D_WIDTH-1):0] up_data_a, 6 | input up_valid_a, 7 | output up_ready_a, 8 | input [(D_WIDTH-1):0] up_data_b, 9 | input up_valid_b, 10 | output up_ready_b, 11 | output [(D_WIDTH-1):0] down_data, 12 | output down_valid, 13 | input down_ready 14 | ); 15 | 16 | //Connect signals to the debug vector for visualisation 17 | wire [7:0] debug; 18 | 19 | 20 | //REASSIGN DEBUG SIGNALS AS NEEDED 21 | assign debug[7] = 1'bx; 22 | assign debug[6] = 1'bx; 23 | assign debug[5] = 1'bx; 24 | assign debug[4] = 1'bx; 25 | assign debug[3] = 1'bx; 26 | assign debug[2] = 1'bx; 27 | assign debug[1] = 1'bx; 28 | assign debug[0] = 1'bx; 29 | 30 | 31 | //BEGIN CUSTOM LOGIC BLOCK 32 | 33 | assign down_data = up_data_a + up_data_b; 34 | assign down_valid = up_valid_a & up_valid_b; 35 | assign up_ready_a = down_valid & down_ready; 36 | assign up_ready_b = down_valid & down_ready; 37 | 38 | //END CUSTOM LOGIC BLOCK 39 | 40 | endmodule 41 | -------------------------------------------------------------------------------- /hdl/scenario10/ff_fifo_pow2_depth.sv: -------------------------------------------------------------------------------- 1 | //---AXI-STREAM FLOP-BASED FIFO WITH DEPTH OF PWR OF 2---// 2 | //Valid/Rready flags generation is based on comparison of write & read counters 3 | //and their MSBs that indicate "Wrap-around", as per Clifford_E_Cummings. 4 | 5 | module ff_fifo_pow2_depth #(parameter D_WIDTH = 6, A_WIDTH = 2) 6 | ( 7 | input clk, 8 | input rst, 9 | input [(D_WIDTH-1):0] up_data, 10 | input up_valid, 11 | output up_ready, 12 | output [(D_WIDTH-1):0] down_data, 13 | output down_valid, 14 | input down_ready 15 | ); 16 | 17 | wire push, pop; 18 | wire empty, full; 19 | wire [(A_WIDTH-1):0] wr_ptr, rd_ptr; 20 | 21 | reg [(A_WIDTH):0] fullwidth_wr_ptr, fullwidth_rd_ptr; 22 | reg [(D_WIDTH-1):0] ram[2**A_WIDTH-1:0]; 23 | 24 | 25 | always @ (posedge clk) 26 | begin 27 | if (push) 28 | ram[wr_ptr] <= up_data; 29 | end 30 | 31 | //WR_COUNTER 32 | always @(posedge clk) 33 | if (rst) begin 34 | fullwidth_wr_ptr <= {(A_WIDTH+1){1'b0}}; 35 | end else if (push) begin 36 | fullwidth_wr_ptr <= fullwidth_wr_ptr + 1; 37 | end 38 | 39 | //RD_COUNTER 40 | always @(posedge clk) 41 | if (rst) begin 42 | fullwidth_rd_ptr <= {(A_WIDTH+1){1'b0}}; 43 | end else if (pop) begin 44 | fullwidth_rd_ptr <= fullwidth_rd_ptr + 1; 45 | end 46 | 47 | //Generate push and pop signals 48 | assign push = up_valid & up_ready; 49 | assign pop = down_valid & down_ready; 50 | 51 | //output LSBits out of full_wr_ptr 52 | assign wr_ptr = fullwidth_wr_ptr[(A_WIDTH-1):0]; 53 | //output LSBits out of full_rd_ptr 54 | assign rd_ptr = fullwidth_rd_ptr[(A_WIDTH-1):0]; 55 | 56 | //"empty" 57 | //It is "1" when MSBits and other bits of "full_rd_ptr" and "full_wr_ptr" are equal 58 | assign empty = ((fullwidth_wr_ptr[(A_WIDTH)] == fullwidth_rd_ptr[(A_WIDTH)]) && 59 | (fullwidth_wr_ptr[(A_WIDTH-1):0] == fullwidth_rd_ptr[(A_WIDTH-1):0])) ? 1'b1 : 1'b0; 60 | //"valid" aka "not_empty" 61 | assign down_valid = ~empty; 62 | 63 | //"full" 64 | //It is "1" when MSBits of "full_rd_ptr" and "full_wr_ptr" are not equal but other bits equal 65 | assign full = ((fullwidth_wr_ptr[(A_WIDTH)] != fullwidth_rd_ptr[(A_WIDTH)]) && 66 | (fullwidth_wr_ptr[(A_WIDTH-1):0] == fullwidth_rd_ptr[(A_WIDTH-1):0])) ? 1'b1 : 1'b0; 67 | //"ready" aka "not_full" 68 | assign up_ready = ~full; 69 | 70 | assign down_data = ram[rd_ptr]; 71 | 72 | endmodule 73 | -------------------------------------------------------------------------------- /hdl/scenario10/model.sv: -------------------------------------------------------------------------------- 1 | //---MODEL---// 2 | 3 | module model #(parameter D_WIDTH = 6) 4 | ( 5 | input clk, 6 | input rst, 7 | input [(D_WIDTH-1):0] up_data_a, 8 | input [(D_WIDTH-1):0] up_data_b, 9 | input push_a, 10 | input push_b, 11 | output logic [(D_WIDTH-1):0] down_data, 12 | input pop 13 | ); 14 | 15 | // Modeling 16 | int unsigned qsize; 17 | logic [(D_WIDTH-1):0] queue_a [$], queue_b [$], queue [$]; 18 | logic [(D_WIDTH-1):0] queue0, queue1, queue2; 19 | logic [(D_WIDTH-1):0] sum_a_and_b; 20 | 21 | 22 | ////START OF QUEUE MODEL//// 23 | always @ (posedge clk) 24 | begin 25 | if (rst) 26 | begin 27 | queue_a = {}; 28 | queue_b = {}; 29 | queue = {}; 30 | end 31 | else 32 | ////DO MODELLING HERE//// 33 | begin 34 | if (push_a) 35 | begin //blocking assignments and function calls can be used between these begin and end 36 | queue_a.push_back (up_data_a); 37 | end 38 | if (push_b) 39 | begin //blocking assignments and function calls can be used between these begin and end 40 | queue_b.push_back (up_data_b); 41 | end 42 | if ((queue_a.size () != 0) & (queue_b.size () != 0)) 43 | begin 44 | sum_a_and_b = queue_a [0] + queue_b [0]; 45 | queue.push_back (sum_a_and_b); 46 | queue_a.delete (0); 47 | queue_b.delete (0); 48 | end 49 | if (pop) 50 | begin 51 | if (queue.size () != 0) 52 | begin 53 | queue.delete (0); // queue.delete(0) is used because "queue.pop_front()" method doesn't work in IcarusVerilog 54 | end 55 | end 56 | end 57 | 58 | //The Model doesn't interact with RTL but let's use non-blocking assigments for final model values, 59 | //it is just a good parctice that will help avoid races between RTL and Model 60 | qsize <= queue.size (); 61 | //Cocotb cannot access queue[$] via hierarchical reference but can access queue0, queue1, queue2 with constant indexes 62 | queue0 <= queue [0]; 63 | queue1 <= queue [1]; 64 | queue2 <= queue [2]; 65 | down_data <= queue [0]; 66 | 67 | end 68 | ////END OF QUEUE MODEL//// 69 | 70 | endmodule 71 | -------------------------------------------------------------------------------- /hdl/scenario10/rtl.sv: -------------------------------------------------------------------------------- 1 | //---TOP MODULE FOR RTL DESIGN---// 2 | 3 | module rtl #(parameter D_WIDTH = 6, A_WIDTH = 2) 4 | ( 5 | input clk, 6 | input rst, 7 | input [(D_WIDTH-1):0] up_data_a, 8 | input up_valid_a, 9 | output up_ready_a, 10 | input [(D_WIDTH-1):0] up_data_b, 11 | input up_valid_b, 12 | output up_ready_b, 13 | output [(D_WIDTH-1):0] down_data, 14 | output down_valid, 15 | input down_ready 16 | ); 17 | 18 | wire [(D_WIDTH-1):0] w_fifo1_down_data_a; 19 | wire w_fifo1_down_valid_a; 20 | wire w_clgk1_up_ready_a; 21 | wire [(D_WIDTH-1):0] w_fifo2_down_data_b; 22 | wire w_fifo2_down_valid_b; 23 | wire w_clgk1_up_ready_b; 24 | wire [(D_WIDTH-1):0] w_clgk1_down_data; 25 | wire w_clgk1_down_valid; 26 | wire w_fifo3_up_ready; 27 | 28 | ff_fifo_pow2_depth # (.D_WIDTH (D_WIDTH), .A_WIDTH (A_WIDTH)) 29 | FIFO1 30 | ( .clk(clk), 31 | .rst(rst), 32 | .up_data(up_data_a), 33 | .up_valid(up_valid_a), 34 | .up_ready(up_ready_a), 35 | .down_data(w_fifo1_down_data_a), 36 | .down_valid(w_fifo1_down_valid_a), 37 | .down_ready(w_clgk1_up_ready_a)); 38 | 39 | ff_fifo_pow2_depth # (.D_WIDTH (D_WIDTH), .A_WIDTH (A_WIDTH)) 40 | FIFO2 41 | ( .clk(clk), 42 | .rst(rst), 43 | .up_data(up_data_b), 44 | .up_valid(up_valid_b), 45 | .up_ready(up_ready_b), 46 | .down_data(w_fifo2_down_data_b), 47 | .down_valid(w_fifo2_down_valid_b), 48 | .down_ready(w_clgk1_up_ready_b)); 49 | 50 | custom_logic_join # (.D_WIDTH (D_WIDTH)) 51 | CLGC1 52 | ( .clk(clk), 53 | .rst(rst), 54 | .up_data_a(w_fifo1_down_data_a), 55 | .up_valid_a(w_fifo1_down_valid_a), 56 | .up_ready_a(w_clgk1_up_ready_a), 57 | .up_data_b(w_fifo2_down_data_b), 58 | .up_valid_b(w_fifo2_down_valid_b), 59 | .up_ready_b(w_clgk1_up_ready_b), 60 | .down_data(w_clgk1_down_data), 61 | .down_valid(w_clgk1_down_valid), 62 | .down_ready(w_fifo3_up_ready)); 63 | 64 | ff_fifo_pow2_depth # (.D_WIDTH (D_WIDTH), .A_WIDTH (A_WIDTH)) 65 | FIFO3 66 | ( .clk(clk), 67 | .rst(rst), 68 | .up_data(w_clgk1_down_data), 69 | .up_valid(w_clgk1_down_valid), 70 | .up_ready(w_fifo3_up_ready), 71 | .down_data(down_data), 72 | .down_valid(down_valid), 73 | .down_ready(down_ready)); 74 | 75 | endmodule 76 | -------------------------------------------------------------------------------- /hdl/scenario10/tb.sv: -------------------------------------------------------------------------------- 1 | module tb 2 | # ( 3 | parameter D_WIDTH = 6, A_WIDTH = 2 4 | ); 5 | 6 | //-------------------------------------------------------------------------- 7 | // Signals to drive Device Under Test - DUT 8 | 9 | logic clk; 10 | wire rst; 11 | 12 | // Upstream 13 | 14 | wire up_valid_a; 15 | wire up_ready_a; 16 | wire [(D_WIDTH-1):0] up_data_a; 17 | 18 | wire up_valid_b; 19 | wire up_ready_b; 20 | wire [(D_WIDTH-1):0] up_data_b; 21 | 22 | // Downstream 23 | 24 | wire down_valid; 25 | wire down_ready; 26 | wire [(D_WIDTH-1):0] down_data; 27 | 28 | // Model 29 | 30 | wire [(D_WIDTH-1):0] model_data; 31 | 32 | //-------------------------------------------------------------------------- 33 | // DUT instantiation 34 | 35 | rtl # (.D_WIDTH (D_WIDTH), .A_WIDTH (A_WIDTH)) 36 | RTL1 37 | ( .clk(clk), 38 | .rst(rst), 39 | .up_data_a(up_data_a), 40 | .up_valid_a(up_valid_a), 41 | .up_ready_a(up_ready_a), 42 | .up_data_b(up_data_b), 43 | .up_valid_b(up_valid_b), 44 | .up_ready_b(up_ready_b), 45 | .down_data(down_data), 46 | .down_valid(down_valid), 47 | .down_ready(down_ready)); 48 | 49 | //-------------------------------------------------------------------------- 50 | // MODEL instantiation 51 | 52 | wire push_a; 53 | wire push_b; 54 | wire pop; 55 | 56 | assign push_a = up_valid_a & up_ready_a; 57 | assign push_b = up_valid_b & up_ready_b; 58 | assign pop = down_valid & down_ready; 59 | 60 | model # (.D_WIDTH (D_WIDTH)) 61 | MDL1 62 | ( .clk(clk), 63 | .rst(rst), 64 | .up_data_a(up_data_a), 65 | .up_data_b(up_data_b), 66 | .push_a(push_a), 67 | .push_b(push_b), 68 | .down_data(model_data), 69 | .pop(pop)); 70 | 71 | //-------------------------------------------------------------------------- 72 | // CHECKING modules instantiation 73 | 74 | check # (.D_WIDTH (D_WIDTH)) 75 | CHK1 76 | ( 77 | .rtl_data(down_data), 78 | .rtl_valid(down_valid), 79 | .model_data(model_data)); 80 | 81 | //-------------------------------------------------------------------------- 82 | // Driving clock 83 | 84 | initial 85 | begin 86 | forever #5 clk = ~ clk; 87 | end 88 | 89 | //-------------------------------------------------------------------------- 90 | //Initialization and driving simulation 91 | initial 92 | begin 93 | clk = 0; 94 | forever @ (posedge clk); 95 | end 96 | 97 | endmodule 98 | -------------------------------------------------------------------------------- /hdl/scenario11/check.sv: -------------------------------------------------------------------------------- 1 | module check #(parameter D_WIDTH = 6) 2 | ( 3 | input [(D_WIDTH-1):0] rtl_data, 4 | input rtl_valid, 5 | input [(D_WIDTH-1):0] model_data_a, 6 | input [(D_WIDTH-1):0] model_data_b 7 | ); 8 | 9 | //This is a BLACKBOX MODULE 10 | //All input ports are not used inside the module because they will be accessed externally from python 11 | //using hierarchical references and used in "post_process_logic_state" call of "check_gadget". 12 | 13 | endmodule 14 | -------------------------------------------------------------------------------- /hdl/scenario11/custom_logic_join_1.sv.bkp: -------------------------------------------------------------------------------- 1 | module custom_logic_join #(parameter D_WIDTH = 6) 2 | ( 3 | input clk, 4 | input rst, 5 | input [(D_WIDTH-1):0] up_data_a, 6 | input up_valid_a, 7 | output up_ready_a, 8 | input [(D_WIDTH-1):0] up_data_b, 9 | input up_valid_b, 10 | output up_ready_b, 11 | output [(D_WIDTH-1):0] down_data, 12 | output down_valid, 13 | input down_ready 14 | ); 15 | 16 | //Connect signals to the debug vector for visualisation 17 | wire [7:0] debug; 18 | 19 | 20 | //REASSIGN DEBUG SIGNALS AS NEEDED 21 | assign debug[7] = sel; 22 | assign debug[6] = en; 23 | assign debug[5] = 1'bx; 24 | assign debug[4] = 1'bx; 25 | assign debug[3] = 1'bx; 26 | assign debug[2] = 1'bx; 27 | assign debug[1] = 1'bx; 28 | assign debug[0] = 1'bx; 29 | 30 | 31 | //BEGIN CUSTOM LOGIC BLOCK 32 | //THIS IS IMPLEMENTATION OF ROUND-ROBIN FLIT MULTIPLEXOR (BLOCKING) 33 | reg sel; 34 | wire en; 35 | 36 | //Round robin multiplexing using 1bit counter 37 | always @(posedge clk) 38 | if (rst) begin 39 | sel <= 1'b0; 40 | end else if (en) begin 41 | sel <= sel + 1; 42 | end 43 | 44 | assign en = down_valid & down_ready; 45 | 46 | //Mux for assigning down_valid and down_data 47 | assign down_data = (sel) ? up_data_b : up_data_a; 48 | assign down_valid = (sel) ? up_valid_b : up_valid_a; 49 | //Demux for up_ready_a and up_ready_b 50 | assign up_ready_a = (~sel & down_ready); 51 | assign up_ready_b = (sel & down_ready); 52 | 53 | //END CUSTOM LOGIC BLOCK 54 | 55 | endmodule 56 | -------------------------------------------------------------------------------- /hdl/scenario11/custom_logic_join_2.sv.bkp: -------------------------------------------------------------------------------- 1 | module custom_logic_join #(parameter D_WIDTH = 6) 2 | ( 3 | input clk, 4 | input rst, 5 | input [(D_WIDTH-1):0] up_data_a, 6 | input up_valid_a, 7 | output up_ready_a, 8 | input [(D_WIDTH-1):0] up_data_b, 9 | input up_valid_b, 10 | output up_ready_b, 11 | output [(D_WIDTH-1):0] down_data, 12 | output down_valid, 13 | input down_ready 14 | ); 15 | 16 | //Connect signals to the debug vector for visualisation 17 | wire [7:0] debug; 18 | 19 | 20 | //REASSIGN DEBUG SIGNALS AS NEEDED 21 | assign debug[7] = sel; 22 | assign debug[6] = en; 23 | assign debug[5] = 1'bx; 24 | assign debug[4] = 1'bx; 25 | assign debug[3] = 1'bx; 26 | assign debug[2] = 1'bx; 27 | assign debug[1] = 1'bx; 28 | assign debug[0] = 1'bx; 29 | 30 | 31 | //BEGIN CUSTOM LOGIC BLOCK 32 | //THIS IS IMPLEMENTATION OF ROUND-ROBIN PACKET MULTIPLEXOR (BLOCKING) 33 | reg sel; 34 | wire en; 35 | wire tlast; 36 | 37 | //Round robin multiplexing using 1bit counter 38 | always @(posedge clk) 39 | if (rst) begin 40 | sel <= 1'b0; 41 | end else if (en) begin 42 | sel <= sel + 1; 43 | end 44 | 45 | assign en = down_valid & down_ready & tlast; 46 | 47 | assign tlast = down_data[(D_WIDTH-1)]; //tlast is the most significant bit in data vector. Packet multiplexing is based on tlast 48 | //Mux for assigning down_valid and down_data 49 | assign down_data = (sel) ? up_data_b : up_data_a; 50 | assign down_valid = (sel) ? up_valid_b : up_valid_a; 51 | //Demux for up_ready_a and up_ready_b 52 | assign up_ready_a = (~sel & down_ready); 53 | assign up_ready_b = (sel & down_ready); 54 | 55 | //END CUSTOM LOGIC BLOCK 56 | 57 | endmodule 58 | -------------------------------------------------------------------------------- /hdl/scenario11/ff_fifo_pow2_depth.sv: -------------------------------------------------------------------------------- 1 | //---AXI-STREAM FLOP-BASED FIFO WITH DEPTH OF PWR OF 2---// 2 | //Valid/Rready flags generation is based on comparison of write & read counters 3 | //and their MSBs that indicate "Wrap-around", as per Clifford_E_Cummings. 4 | 5 | module ff_fifo_pow2_depth #(parameter D_WIDTH = 6, A_WIDTH = 2) 6 | ( 7 | input clk, 8 | input rst, 9 | input [(D_WIDTH-1):0] up_data, 10 | input up_valid, 11 | output up_ready, 12 | output [(D_WIDTH-1):0] down_data, 13 | output down_valid, 14 | input down_ready 15 | ); 16 | 17 | wire push, pop; 18 | wire empty, full; 19 | wire [(A_WIDTH-1):0] wr_ptr, rd_ptr; 20 | 21 | reg [(A_WIDTH):0] fullwidth_wr_ptr, fullwidth_rd_ptr; 22 | reg [(D_WIDTH-1):0] ram[2**A_WIDTH-1:0]; 23 | 24 | 25 | always @ (posedge clk) 26 | begin 27 | if (push) 28 | ram[wr_ptr] <= up_data; 29 | end 30 | 31 | //WR_COUNTER 32 | always @(posedge clk) 33 | if (rst) begin 34 | fullwidth_wr_ptr <= {(A_WIDTH+1){1'b0}}; 35 | end else if (push) begin 36 | fullwidth_wr_ptr <= fullwidth_wr_ptr + 1; 37 | end 38 | 39 | //RD_COUNTER 40 | always @(posedge clk) 41 | if (rst) begin 42 | fullwidth_rd_ptr <= {(A_WIDTH+1){1'b0}}; 43 | end else if (pop) begin 44 | fullwidth_rd_ptr <= fullwidth_rd_ptr + 1; 45 | end 46 | 47 | //Generate push and pop signals 48 | assign push = up_valid & up_ready; 49 | assign pop = down_valid & down_ready; 50 | 51 | //output LSBits out of full_wr_ptr 52 | assign wr_ptr = fullwidth_wr_ptr[(A_WIDTH-1):0]; 53 | //output LSBits out of full_rd_ptr 54 | assign rd_ptr = fullwidth_rd_ptr[(A_WIDTH-1):0]; 55 | 56 | //"empty" 57 | //It is "1" when MSBits and other bits of "full_rd_ptr" and "full_wr_ptr" are equal 58 | assign empty = ((fullwidth_wr_ptr[(A_WIDTH)] == fullwidth_rd_ptr[(A_WIDTH)]) && 59 | (fullwidth_wr_ptr[(A_WIDTH-1):0] == fullwidth_rd_ptr[(A_WIDTH-1):0])) ? 1'b1 : 1'b0; 60 | //"valid" aka "not_empty" 61 | assign down_valid = ~empty; 62 | 63 | //"full" 64 | //It is "1" when MSBits of "full_rd_ptr" and "full_wr_ptr" are not equal but other bits equal 65 | assign full = ((fullwidth_wr_ptr[(A_WIDTH)] != fullwidth_rd_ptr[(A_WIDTH)]) && 66 | (fullwidth_wr_ptr[(A_WIDTH-1):0] == fullwidth_rd_ptr[(A_WIDTH-1):0])) ? 1'b1 : 1'b0; 67 | //"ready" aka "not_full" 68 | assign up_ready = ~full; 69 | 70 | assign down_data = ram[rd_ptr]; 71 | 72 | endmodule 73 | -------------------------------------------------------------------------------- /hdl/scenario11/model.sv: -------------------------------------------------------------------------------- 1 | //---MODEL---// 2 | 3 | module model #(parameter D_WIDTH = 6) 4 | ( 5 | input clk, 6 | input rst, 7 | input [(D_WIDTH-1):0] up_data_a, 8 | input [(D_WIDTH-1):0] up_data_b, 9 | input push_a, 10 | input push_b, 11 | output logic [(D_WIDTH-1):0] down_data_a, 12 | output logic [(D_WIDTH-1):0] down_data_b, 13 | input pop_a, 14 | input pop_b 15 | ); 16 | 17 | // Modeling 18 | int unsigned qsize_a, qsize_b; 19 | logic [(D_WIDTH-1):0] queue_a [$], queue_b [$]; 20 | logic [(D_WIDTH-1):0] queue0_a, queue1_a, queue2_a, queue0_b, queue1_b, queue2_b; 21 | 22 | ////START OF QUEUE MODEL//// 23 | always @ (posedge clk) 24 | begin 25 | if (rst) 26 | begin 27 | queue_a = {}; 28 | queue_b = {}; 29 | end 30 | else 31 | ////DO MODELLING HERE//// 32 | begin 33 | if (push_a) 34 | begin //blocking assignments and function calls can be used between these begin and end 35 | queue_a.push_back (up_data_a); 36 | end 37 | if (push_b) 38 | begin //blocking assignments and function calls can be used between these begin and end 39 | queue_b.push_back (up_data_b); 40 | end 41 | if (pop_a) 42 | begin 43 | if (queue_a.size () != 0) 44 | begin 45 | queue_a.delete (0); // queue.delete(0) is used because "queue.pop_front()" method doesn't work in IcarusVerilog 46 | end 47 | end 48 | if (pop_b) 49 | begin 50 | if (queue_b.size () != 0) 51 | begin 52 | queue_b.delete (0); // queue.delete(0) is used because "queue.pop_front()" method doesn't work in IcarusVerilog 53 | end 54 | end 55 | end 56 | 57 | //The Model doesn't interact with RTL but let's use non-blocking assigments for final model values, 58 | //it is just a good parctice that will help avoid races between RTL and Model 59 | qsize_a <= queue_a.size (); 60 | qsize_b <= queue_b.size (); 61 | //Cocotb cannot access queue[$] via hierarchical reference but can access queue0, queue1, queue2 with constant indexes 62 | queue0_a <= queue_a [0]; 63 | queue1_a <= queue_a [1]; 64 | queue2_a <= queue_a [2]; 65 | down_data_a <= queue_a [0]; 66 | queue0_b <= queue_b [0]; 67 | queue1_b <= queue_b [1]; 68 | queue2_b <= queue_b [2]; 69 | down_data_b <= queue_b [0]; 70 | 71 | end 72 | ////END OF QUEUE MODEL//// 73 | 74 | endmodule 75 | -------------------------------------------------------------------------------- /hdl/scenario11/rtl.sv: -------------------------------------------------------------------------------- 1 | //---TOP MODULE FOR RTL DESIGN---// 2 | 3 | module rtl #(parameter D_WIDTH = 6, A_WIDTH = 2) 4 | ( 5 | input clk, 6 | input rst, 7 | input [(D_WIDTH-1):0] up_data_a, 8 | input up_valid_a, 9 | output up_ready_a, 10 | input [(D_WIDTH-1):0] up_data_b, 11 | input up_valid_b, 12 | output up_ready_b, 13 | output [(D_WIDTH-1):0] down_data, 14 | output down_valid, 15 | input down_ready 16 | ); 17 | 18 | wire [(D_WIDTH-1):0] w_fifo1_down_data_a; 19 | wire w_fifo1_down_valid_a; 20 | wire w_clgk1_up_ready_a; 21 | wire [(D_WIDTH-1):0] w_fifo2_down_data_b; 22 | wire w_fifo2_down_valid_b; 23 | wire w_clgk1_up_ready_b; 24 | wire [(D_WIDTH-1):0] w_clgk1_down_data; 25 | wire w_clgk1_down_valid; 26 | wire w_fifo3_up_ready; 27 | 28 | ff_fifo_pow2_depth # (.D_WIDTH (D_WIDTH), .A_WIDTH (A_WIDTH)) 29 | FIFO1 30 | ( .clk(clk), 31 | .rst(rst), 32 | .up_data(up_data_a), 33 | .up_valid(up_valid_a), 34 | .up_ready(up_ready_a), 35 | .down_data(w_fifo1_down_data_a), 36 | .down_valid(w_fifo1_down_valid_a), 37 | .down_ready(w_clgk1_up_ready_a)); 38 | 39 | ff_fifo_pow2_depth # (.D_WIDTH (D_WIDTH), .A_WIDTH (A_WIDTH)) 40 | FIFO2 41 | ( .clk(clk), 42 | .rst(rst), 43 | .up_data(up_data_b), 44 | .up_valid(up_valid_b), 45 | .up_ready(up_ready_b), 46 | .down_data(w_fifo2_down_data_b), 47 | .down_valid(w_fifo2_down_valid_b), 48 | .down_ready(w_clgk1_up_ready_b)); 49 | 50 | custom_logic_join # (.D_WIDTH (D_WIDTH)) 51 | CLGC1 52 | ( .clk(clk), 53 | .rst(rst), 54 | .up_data_a(w_fifo1_down_data_a), 55 | .up_valid_a(w_fifo1_down_valid_a), 56 | .up_ready_a(w_clgk1_up_ready_a), 57 | .up_data_b(w_fifo2_down_data_b), 58 | .up_valid_b(w_fifo2_down_valid_b), 59 | .up_ready_b(w_clgk1_up_ready_b), 60 | .down_data(w_clgk1_down_data), 61 | .down_valid(w_clgk1_down_valid), 62 | .down_ready(w_fifo3_up_ready)); 63 | 64 | ff_fifo_pow2_depth # (.D_WIDTH (D_WIDTH), .A_WIDTH (A_WIDTH)) 65 | FIFO3 66 | ( .clk(clk), 67 | .rst(rst), 68 | .up_data(w_clgk1_down_data), 69 | .up_valid(w_clgk1_down_valid), 70 | .up_ready(w_fifo3_up_ready), 71 | .down_data(down_data), 72 | .down_valid(down_valid), 73 | .down_ready(down_ready)); 74 | 75 | endmodule 76 | -------------------------------------------------------------------------------- /hdl/scenario12/rtl.sv: -------------------------------------------------------------------------------- 1 | //---TOP MODULE FOR RTL DESIGN---// 2 | 3 | module rtl #(parameter D_WIDTH = 6) 4 | ( 5 | input clk, 6 | input rst, 7 | input [(D_WIDTH-1):0] up_data, 8 | input up_valid, 9 | output up_ready, 10 | output [(D_WIDTH-1):0] down_data, 11 | output down_valid, 12 | input down_ready 13 | ); 14 | 15 | shiftreg_4depth # (.D_WIDTH (D_WIDTH)) 16 | SFTREG1 17 | ( .clk(clk), 18 | .rst(rst), 19 | .up_data(up_data), 20 | .up_valid(up_valid), 21 | .up_ready(up_ready), 22 | .down_data(down_data), 23 | .down_valid(down_valid), 24 | .down_ready(down_ready)); 25 | 26 | endmodule 27 | -------------------------------------------------------------------------------- /hdl/scenario12/shiftreg_4depth.sv: -------------------------------------------------------------------------------- 1 | module shiftreg_4depth #(parameter D_WIDTH = 6) 2 | ( 3 | input clk, 4 | input rst, 5 | input [(D_WIDTH-1):0] up_data, 6 | input up_valid, 7 | output up_ready, 8 | output [(D_WIDTH-1):0] down_data, 9 | output down_valid, 10 | input down_ready 11 | ); 12 | 13 | reg valid0, valid1, valid2, valid3; 14 | reg [(D_WIDTH-1):0] data0, data1, data2, data3; 15 | 16 | //Data 17 | always @(posedge clk) 18 | if (down_ready) begin 19 | data0 <= up_data; 20 | data1 <= data0; 21 | data2 <= data1; 22 | data3 <= data2; 23 | end 24 | 25 | //Valid 26 | always @(posedge clk) 27 | if (rst) begin 28 | valid0 <= 1'b0; 29 | valid1 <= 1'b0; 30 | valid2 <= 1'b0; 31 | valid3 <= 1'b0; 32 | end else if (down_ready) begin 33 | valid0 <= up_valid; 34 | valid1 <= valid0; 35 | valid2 <= valid1; 36 | valid3 <= valid2; 37 | end 38 | 39 | assign down_valid = valid3; 40 | assign down_data = data3; 41 | assign up_ready = down_ready; 42 | 43 | endmodule 44 | -------------------------------------------------------------------------------- /hdl/scenario12/tb.sv: -------------------------------------------------------------------------------- 1 | module tb 2 | # ( 3 | parameter D_WIDTH = 6 4 | ); 5 | 6 | //-------------------------------------------------------------------------- 7 | // Signals to drive Device Under Test - DUT 8 | 9 | logic clk; 10 | wire rst; 11 | 12 | // Upstream 13 | 14 | wire up_valid; 15 | wire up_ready; 16 | wire [(D_WIDTH-1):0] up_data; 17 | 18 | // Downstream 19 | 20 | wire down_valid; 21 | wire down_ready; 22 | wire [(D_WIDTH-1):0] down_data; 23 | 24 | //-------------------------------------------------------------------------- 25 | // DUT instantiation 26 | 27 | rtl # (.D_WIDTH (D_WIDTH)) 28 | RTL1 29 | ( .clk(clk), 30 | .rst(rst), 31 | .up_data(up_data), 32 | .up_valid(up_valid), 33 | .up_ready(up_ready), 34 | .down_data(down_data), 35 | .down_valid(down_valid), 36 | .down_ready(down_ready)); 37 | 38 | //-------------------------------------------------------------------------- 39 | // Driving clock 40 | 41 | initial 42 | begin 43 | forever #5 clk = ~ clk; 44 | end 45 | 46 | //-------------------------------------------------------------------------- 47 | //Initialization and driving simulation 48 | initial 49 | begin 50 | clk = 0; 51 | forever @ (posedge clk); 52 | end 53 | 54 | endmodule 55 | -------------------------------------------------------------------------------- /hdl/scenario13/check.sv: -------------------------------------------------------------------------------- 1 | module check #(parameter D_WIDTH = 6) 2 | ( 3 | input [(D_WIDTH-1):0] rtl_data, 4 | input rtl_valid, 5 | input [(D_WIDTH-1):0] model_data 6 | ); 7 | 8 | //This is a BLACKBOX MODULE 9 | //All input ports are not used inside the module because they will be accessed externally from python 10 | //using hierarchical references and used in "post_process_logic_state" call of "check_gadget". 11 | 12 | endmodule 13 | -------------------------------------------------------------------------------- /hdl/scenario13/custom_logic.sv: -------------------------------------------------------------------------------- 1 | module custom_logic #(parameter D_WIDTH = 6) 2 | ( 3 | input clk, 4 | input rst, 5 | input [(D_WIDTH-1):0] up_data, 6 | input up_valid, 7 | output up_ready, 8 | output [(D_WIDTH-1):0] down_data, 9 | output down_valid, 10 | input down_ready 11 | ); 12 | 13 | //Connect signals to the debug vector for visualisation 14 | wire [7:0] debug; 15 | 16 | 17 | //REASSIGN DEBUG SIGNALS AS NEEDED 18 | assign debug[7] = 1'bx; 19 | assign debug[6] = 1'bx; 20 | assign debug[5] = 1'bx; 21 | assign debug[4] = 1'bx; 22 | assign debug[3] = 1'bx; 23 | assign debug[2] = 1'bx; 24 | assign debug[1] = 1'bx; 25 | assign debug[0] = 1'bx; 26 | 27 | 28 | //BEGIN CUSTOM LOGIC BLOCK 29 | 30 | assign down_data = up_data; 31 | assign down_valid = up_valid; 32 | assign up_ready = down_ready; 33 | //END CUSTOM LOGIC BLOCK 34 | 35 | endmodule 36 | -------------------------------------------------------------------------------- /hdl/scenario13/model.sv: -------------------------------------------------------------------------------- 1 | //---MODEL---// 2 | 3 | module model #(parameter D_WIDTH = 6) 4 | ( 5 | input clk, 6 | input rst, 7 | input [(D_WIDTH-1):0] up_data, 8 | input push, 9 | output logic [(D_WIDTH-1):0] down_data, 10 | input pop 11 | ); 12 | 13 | // Modeling 14 | int unsigned qsize; 15 | logic [(D_WIDTH-1):0] queue [$]; 16 | logic [(D_WIDTH-1):0] queue0, queue1, queue2; 17 | 18 | ////START OF QUEUE MODEL//// 19 | always @ (posedge clk) 20 | begin 21 | if (rst) 22 | begin 23 | queue = {}; 24 | end 25 | else 26 | ////DO MODELLING HERE//// 27 | begin 28 | if (push) 29 | begin //blocking assignments and function calls can be used between these begin and end 30 | queue.push_back (up_data); 31 | end 32 | if (pop) 33 | begin 34 | if (queue.size () != 0) 35 | begin 36 | queue.delete (0); // queue.delete(0) is used because "queue.pop_front()" method doesn't work in IcarusVerilog 37 | end 38 | end 39 | end 40 | 41 | //The Model doesn't interact with RTL but let's use non-blocking assigments for final model values, 42 | //it is just a good parctice that will help avoid races between RTL and Model 43 | qsize <= queue.size (); 44 | //Cocotb cannot access queue[$] via hierarchical reference but can access queue0, queue1, queue2 with constant indexes 45 | queue0 <= queue [0]; 46 | queue1 <= queue [1]; 47 | queue2 <= queue [2]; 48 | down_data <= queue [0]; 49 | 50 | end 51 | ////END OF QUEUE MODEL//// 52 | 53 | endmodule 54 | -------------------------------------------------------------------------------- /hdl/scenario13/rtl.sv: -------------------------------------------------------------------------------- 1 | //---TOP MODULE FOR RTL DESIGN---// 2 | 3 | module rtl #(parameter D_WIDTH = 6) 4 | ( 5 | input clk, 6 | input rst, 7 | input [(D_WIDTH-1):0] up_data, 8 | input up_valid, 9 | output up_ready, 10 | output [(D_WIDTH-1):0] down_data, 11 | output down_valid, 12 | input down_ready 13 | ); 14 | 15 | wire [(D_WIDTH-1):0] w_sftreg1_down_data; 16 | wire w_sftreg1_down_valid; 17 | wire w_clgk1_up_ready; 18 | wire [(D_WIDTH-1):0] w_clgk1_down_data; 19 | wire w_clgk1_down_valid; 20 | wire w_sftreg2_up_ready; 21 | 22 | shiftreg_4depth # (.D_WIDTH (D_WIDTH)) 23 | SFTREG1 24 | ( .clk(clk), 25 | .rst(rst), 26 | .up_data(up_data), 27 | .up_valid(up_valid), 28 | .up_ready(up_ready), 29 | .down_data(w_sftreg1_down_data), 30 | .down_valid(w_sftreg1_down_valid), 31 | .down_ready(w_clgk1_up_ready)); 32 | 33 | custom_logic # (.D_WIDTH (D_WIDTH)) 34 | CLGC1 35 | ( .clk(clk), 36 | .rst(rst), 37 | .up_data(w_sftreg1_down_data), 38 | .up_valid(w_sftreg1_down_valid), 39 | .up_ready(w_clgk1_up_ready), 40 | .down_data(w_clgk1_down_data), 41 | .down_valid(w_clgk1_down_valid), 42 | .down_ready(w_sftreg2_up_ready)); 43 | 44 | shiftreg_4depth # (.D_WIDTH (D_WIDTH)) 45 | SFTREG2 46 | ( .clk(clk), 47 | .rst(rst), 48 | .up_data(w_clgk1_down_data), 49 | .up_valid(w_clgk1_down_valid), 50 | .up_ready(w_sftreg2_up_ready), 51 | .down_data(down_data), 52 | .down_valid(down_valid), 53 | .down_ready(down_ready)); 54 | 55 | endmodule 56 | -------------------------------------------------------------------------------- /hdl/scenario13/shiftreg_4depth.sv: -------------------------------------------------------------------------------- 1 | module shiftreg_4depth #(parameter D_WIDTH = 6) 2 | ( 3 | input clk, 4 | input rst, 5 | input [(D_WIDTH-1):0] up_data, 6 | input up_valid, 7 | output up_ready, 8 | output [(D_WIDTH-1):0] down_data, 9 | output down_valid, 10 | input down_ready 11 | ); 12 | 13 | reg valid0, valid1, valid2, valid3; 14 | reg [(D_WIDTH-1):0] data0, data1, data2, data3; 15 | 16 | //Data 17 | always @(posedge clk) 18 | if (down_ready) begin 19 | data0 <= up_data; 20 | data1 <= data0; 21 | data2 <= data1; 22 | data3 <= data2; 23 | end 24 | 25 | //Valid 26 | always @(posedge clk) 27 | if (rst) begin 28 | valid0 <= 1'b0; 29 | valid1 <= 1'b0; 30 | valid2 <= 1'b0; 31 | valid3 <= 1'b0; 32 | end else if (down_ready) begin 33 | valid0 <= up_valid; 34 | valid1 <= valid0; 35 | valid2 <= valid1; 36 | valid3 <= valid2; 37 | end 38 | 39 | assign down_valid = valid3; 40 | assign down_data = data3; 41 | assign up_ready = down_ready; 42 | 43 | endmodule 44 | -------------------------------------------------------------------------------- /hdl/scenario13/tb.sv: -------------------------------------------------------------------------------- 1 | module tb 2 | # ( 3 | parameter D_WIDTH = 6 4 | ); 5 | 6 | //-------------------------------------------------------------------------- 7 | // Signals to drive Device Under Test - DUT 8 | 9 | logic clk; 10 | wire rst; 11 | 12 | // Upstream 13 | 14 | wire up_valid; 15 | wire up_ready; 16 | wire [(D_WIDTH-1):0] up_data; 17 | 18 | // Downstream 19 | 20 | wire down_valid; 21 | wire down_ready; 22 | wire [(D_WIDTH-1):0] down_data; 23 | 24 | // Model 25 | 26 | wire [(D_WIDTH-1):0] model_data; 27 | 28 | //-------------------------------------------------------------------------- 29 | // DUT instantiation 30 | 31 | rtl # (.D_WIDTH (D_WIDTH)) 32 | RTL1 33 | ( .clk(clk), 34 | .rst(rst), 35 | .up_data(up_data), 36 | .up_valid(up_valid), 37 | .up_ready(up_ready), 38 | .down_data(down_data), 39 | .down_valid(down_valid), 40 | .down_ready(down_ready)); 41 | 42 | //-------------------------------------------------------------------------- 43 | // MODEL instantiation 44 | 45 | wire push; 46 | wire pop; 47 | 48 | assign push = up_valid & up_ready; 49 | assign pop = down_valid & down_ready; 50 | 51 | model # (.D_WIDTH (D_WIDTH)) 52 | MDL1 53 | ( .clk(clk), 54 | .rst(rst), 55 | .up_data(up_data), 56 | .push(push), 57 | .down_data(model_data), 58 | .pop(pop)); 59 | 60 | //-------------------------------------------------------------------------- 61 | // CHECKING module instantiation 62 | 63 | check # (.D_WIDTH (D_WIDTH)) 64 | CHK1 65 | ( 66 | .rtl_data(down_data), 67 | .rtl_valid(down_valid), 68 | .model_data(model_data)); 69 | 70 | //-------------------------------------------------------------------------- 71 | // Driving clock 72 | 73 | initial 74 | begin 75 | forever #5 clk = ~ clk; 76 | end 77 | 78 | //-------------------------------------------------------------------------- 79 | //Initialization and driving simulation 80 | initial 81 | begin 82 | clk = 0; 83 | forever @ (posedge clk); 84 | end 85 | 86 | endmodule 87 | -------------------------------------------------------------------------------- /hdl/scenario14/check.sv: -------------------------------------------------------------------------------- 1 | module check #(parameter D_WIDTH = 6) 2 | ( 3 | input [(D_WIDTH-1):0] rtl_data, 4 | input rtl_valid, 5 | input [(D_WIDTH-1):0] model_data 6 | ); 7 | 8 | //This is a BLACKBOX MODULE 9 | //All input ports are not used inside the module because they will be accessed externally from python 10 | //using hierarchical references and used in "post_process_logic_state" call of "check_gadget". 11 | 12 | endmodule 13 | -------------------------------------------------------------------------------- /hdl/scenario14/custom_logic.sv: -------------------------------------------------------------------------------- 1 | module custom_logic #(parameter D_WIDTH = 6) 2 | ( 3 | input clk, 4 | input rst, 5 | input [(D_WIDTH-1):0] up_data, 6 | input up_valid, 7 | output up_ready, 8 | output [(D_WIDTH-1):0] down_data, 9 | output down_valid, 10 | input down_ready 11 | ); 12 | 13 | //Connect signals to the debug vector for visualisation 14 | wire [7:0] debug; 15 | 16 | 17 | //REASSIGN DEBUG SIGNALS AS NEEDED 18 | assign debug[7] = 1'bx; 19 | assign debug[6] = 1'bx; 20 | assign debug[5] = 1'bx; 21 | assign debug[4] = 1'bx; 22 | assign debug[3] = 1'bx; 23 | assign debug[2] = 1'bx; 24 | assign debug[1] = 1'bx; 25 | assign debug[0] = 1'bx; 26 | 27 | 28 | //BEGIN CUSTOM LOGIC BLOCK 29 | 30 | assign down_data = up_data; 31 | assign down_valid = up_valid; 32 | assign up_ready = down_ready; 33 | 34 | //END CUSTOM LOGIC BLOCK 35 | 36 | endmodule 37 | -------------------------------------------------------------------------------- /hdl/scenario14/ff_fifo_pow2_depth.sv: -------------------------------------------------------------------------------- 1 | //---AXI-STREAM FLOP-BASED FIFO WITH DEPTH OF PWR OF 2---// 2 | //Valid/Rready flags generation is based on comparison of write & read counters 3 | //and their MSBs that indicate "Wrap-around", as per Clifford_E_Cummings. 4 | 5 | module ff_fifo_pow2_depth #(parameter D_WIDTH = 6, A_WIDTH = 2) 6 | ( 7 | input clk, 8 | input rst, 9 | input [(D_WIDTH-1):0] up_data, 10 | input up_valid, 11 | output up_ready, 12 | output [(D_WIDTH-1):0] down_data, 13 | output down_valid, 14 | input down_ready 15 | ); 16 | 17 | wire push, pop; 18 | wire empty, full; 19 | wire [(A_WIDTH-1):0] wr_ptr, rd_ptr; 20 | 21 | reg [(A_WIDTH):0] fullwidth_wr_ptr, fullwidth_rd_ptr; 22 | reg [(D_WIDTH-1):0] ram[2**A_WIDTH-1:0]; 23 | 24 | 25 | always @ (posedge clk) 26 | begin 27 | if (push) 28 | ram[wr_ptr] <= up_data; 29 | end 30 | 31 | //WR_COUNTER 32 | always @(posedge clk) 33 | if (rst) begin 34 | fullwidth_wr_ptr <= {(A_WIDTH+1){1'b0}}; 35 | end else if (push) begin 36 | fullwidth_wr_ptr <= fullwidth_wr_ptr + 1; 37 | end 38 | 39 | //RD_COUNTER 40 | always @(posedge clk) 41 | if (rst) begin 42 | fullwidth_rd_ptr <= {(A_WIDTH+1){1'b0}}; 43 | end else if (pop) begin 44 | fullwidth_rd_ptr <= fullwidth_rd_ptr + 1; 45 | end 46 | 47 | //Generate push and pop signals 48 | assign push = up_valid & up_ready; 49 | assign pop = down_valid & down_ready; 50 | 51 | //output LSBits out of full_wr_ptr 52 | assign wr_ptr = fullwidth_wr_ptr[(A_WIDTH-1):0]; 53 | //output LSBits out of full_rd_ptr 54 | assign rd_ptr = fullwidth_rd_ptr[(A_WIDTH-1):0]; 55 | 56 | //"empty" 57 | //It is "1" when MSBits and other bits of "full_rd_ptr" and "full_wr_ptr" are equal 58 | assign empty = ((fullwidth_wr_ptr[(A_WIDTH)] == fullwidth_rd_ptr[(A_WIDTH)]) && 59 | (fullwidth_wr_ptr[(A_WIDTH-1):0] == fullwidth_rd_ptr[(A_WIDTH-1):0])) ? 1'b1 : 1'b0; 60 | //"valid" aka "not_empty" 61 | assign down_valid = ~empty; 62 | 63 | //"full" 64 | //It is "1" when MSBits of "full_rd_ptr" and "full_wr_ptr" are not equal but other bits equal 65 | assign full = ((fullwidth_wr_ptr[(A_WIDTH)] != fullwidth_rd_ptr[(A_WIDTH)]) && 66 | (fullwidth_wr_ptr[(A_WIDTH-1):0] == fullwidth_rd_ptr[(A_WIDTH-1):0])) ? 1'b1 : 1'b0; 67 | //"ready" aka "not_full" 68 | assign up_ready = ~full; 69 | 70 | assign down_data = ram[rd_ptr]; 71 | 72 | endmodule 73 | -------------------------------------------------------------------------------- /hdl/scenario14/model.sv: -------------------------------------------------------------------------------- 1 | //---MODEL---// 2 | 3 | module model #(parameter D_WIDTH = 6) 4 | ( 5 | input clk, 6 | input rst, 7 | input [(D_WIDTH-1):0] up_data, 8 | input push, 9 | output logic [(D_WIDTH-1):0] down_data, 10 | input pop 11 | ); 12 | 13 | // Modeling 14 | int unsigned qsize; 15 | logic [(D_WIDTH-1):0] queue [$]; 16 | logic [(D_WIDTH-1):0] queue0, queue1, queue2; 17 | 18 | ////START OF QUEUE MODEL//// 19 | always @ (posedge clk) 20 | begin 21 | if (rst) 22 | begin 23 | queue = {}; 24 | end 25 | else 26 | ////DO MODELLING HERE//// 27 | begin 28 | if (push) 29 | begin //blocking assignments and function calls can be used between these begin and end 30 | queue.push_back (up_data); 31 | end 32 | if (pop) 33 | begin 34 | if (queue.size () != 0) 35 | begin 36 | queue.delete (0); // queue.delete(0) is used because "queue.pop_front()" method doesn't work in IcarusVerilog 37 | end 38 | end 39 | end 40 | 41 | //The Model doesn't interact with RTL but let's use non-blocking assigments for final model values, 42 | //it is just a good parctice that will help avoid races between RTL and Model 43 | qsize <= queue.size (); 44 | //Cocotb cannot access queue[$] via hierarchical reference but can access queue0, queue1, queue2 with constant indexes 45 | queue0 <= queue [0]; 46 | queue1 <= queue [1]; 47 | queue2 <= queue [2]; 48 | down_data <= queue [0]; 49 | 50 | end 51 | ////END OF QUEUE MODEL//// 52 | 53 | endmodule 54 | -------------------------------------------------------------------------------- /hdl/scenario14/rtl.sv: -------------------------------------------------------------------------------- 1 | //---TOP MODULE FOR RTL DESIGN---// 2 | 3 | module rtl #(parameter D_WIDTH = 6, A_WIDTH = 2) 4 | ( 5 | input clk, 6 | input rst, 7 | input [(D_WIDTH-1):0] up_data, 8 | input up_valid, 9 | output up_ready, 10 | output [(D_WIDTH-1):0] down_data, 11 | output down_valid, 12 | input down_ready 13 | ); 14 | 15 | wire [(D_WIDTH-1):0] w_sftreg1_down_data; 16 | wire w_sftreg1_down_valid; 17 | wire w_clgk1_up_ready; 18 | wire [(D_WIDTH-1):0] w_clgk1_down_data; 19 | wire w_clgk1_down_valid; 20 | wire w_fifo1_up_ready; 21 | 22 | shiftreg_4depth # (.D_WIDTH (D_WIDTH)) 23 | SFTREG1 24 | ( .clk(clk), 25 | .rst(rst), 26 | .up_data(up_data), 27 | .up_valid(up_valid), 28 | .up_ready(up_ready), 29 | .down_data(w_sftreg1_down_data), 30 | .down_valid(w_sftreg1_down_valid), 31 | .down_ready(w_clgk1_up_ready)); 32 | 33 | custom_logic # (.D_WIDTH (D_WIDTH)) 34 | CLGC1 35 | ( .clk(clk), 36 | .rst(rst), 37 | .up_data(w_sftreg1_down_data), 38 | .up_valid(w_sftreg1_down_valid), 39 | .up_ready(w_clgk1_up_ready), 40 | .down_data(w_clgk1_down_data), 41 | .down_valid(w_clgk1_down_valid), 42 | .down_ready(w_fifo1_up_ready)); 43 | 44 | ff_fifo_pow2_depth # (.D_WIDTH (D_WIDTH), .A_WIDTH (A_WIDTH)) 45 | FIFO1 46 | ( .clk(clk), 47 | .rst(rst), 48 | .up_data(w_clgk1_down_data), 49 | .up_valid(w_clgk1_down_valid), 50 | .up_ready(w_fifo1_up_ready), 51 | .down_data(down_data), 52 | .down_valid(down_valid), 53 | .down_ready(down_ready)); 54 | 55 | endmodule 56 | -------------------------------------------------------------------------------- /hdl/scenario14/shiftreg_4depth.sv: -------------------------------------------------------------------------------- 1 | module shiftreg_4depth #(parameter D_WIDTH = 6) 2 | ( 3 | input clk, 4 | input rst, 5 | input [(D_WIDTH-1):0] up_data, 6 | input up_valid, 7 | output up_ready, 8 | output [(D_WIDTH-1):0] down_data, 9 | output down_valid, 10 | input down_ready 11 | ); 12 | 13 | reg valid0, valid1, valid2, valid3; 14 | reg [(D_WIDTH-1):0] data0, data1, data2, data3; 15 | 16 | //Data 17 | always @(posedge clk) 18 | if (down_ready) begin 19 | data0 <= up_data; 20 | data1 <= data0; 21 | data2 <= data1; 22 | data3 <= data2; 23 | end 24 | 25 | //Valid 26 | always @(posedge clk) 27 | if (rst) begin 28 | valid0 <= 1'b0; 29 | valid1 <= 1'b0; 30 | valid2 <= 1'b0; 31 | valid3 <= 1'b0; 32 | end else if (down_ready) begin 33 | valid0 <= up_valid; 34 | valid1 <= valid0; 35 | valid2 <= valid1; 36 | valid3 <= valid2; 37 | end 38 | 39 | assign down_valid = valid3; 40 | assign down_data = data3; 41 | assign up_ready = down_ready; 42 | 43 | endmodule 44 | -------------------------------------------------------------------------------- /hdl/scenario14/tb.sv: -------------------------------------------------------------------------------- 1 | module tb 2 | # ( 3 | parameter D_WIDTH = 6, A_WIDTH = 2 4 | ); 5 | 6 | //-------------------------------------------------------------------------- 7 | // Signals to drive Device Under Test - DUT 8 | 9 | logic clk; 10 | wire rst; 11 | 12 | // Upstream 13 | 14 | wire up_valid; 15 | wire up_ready; 16 | wire [(D_WIDTH-1):0] up_data; 17 | 18 | // Downstream 19 | 20 | wire down_valid; 21 | wire down_ready; 22 | wire [(D_WIDTH-1):0] down_data; 23 | 24 | // Model 25 | 26 | wire [(D_WIDTH-1):0] model_data; 27 | 28 | //-------------------------------------------------------------------------- 29 | // DUT instantiation 30 | 31 | rtl # (.D_WIDTH (D_WIDTH), .A_WIDTH (A_WIDTH)) 32 | RTL1 33 | ( .clk(clk), 34 | .rst(rst), 35 | .up_data(up_data), 36 | .up_valid(up_valid), 37 | .up_ready(up_ready), 38 | .down_data(down_data), 39 | .down_valid(down_valid), 40 | .down_ready(down_ready)); 41 | 42 | //-------------------------------------------------------------------------- 43 | // MODEL instantiation 44 | 45 | wire push; 46 | wire pop; 47 | 48 | assign push = up_valid & up_ready; 49 | assign pop = down_valid & down_ready; 50 | 51 | model # (.D_WIDTH (D_WIDTH)) 52 | MDL1 53 | ( .clk(clk), 54 | .rst(rst), 55 | .up_data(up_data), 56 | .push(push), 57 | .down_data(model_data), 58 | .pop(pop)); 59 | 60 | //-------------------------------------------------------------------------- 61 | // CHECKING module instantiation 62 | 63 | check # (.D_WIDTH (D_WIDTH)) 64 | CHK1 65 | ( 66 | .rtl_data(down_data), 67 | .rtl_valid(down_valid), 68 | .model_data(model_data)); 69 | 70 | //-------------------------------------------------------------------------- 71 | // Driving clock 72 | 73 | initial 74 | begin 75 | forever #5 clk = ~ clk; 76 | end 77 | 78 | //-------------------------------------------------------------------------- 79 | //Initialization and driving simulation 80 | initial 81 | begin 82 | clk = 0; 83 | forever @ (posedge clk); 84 | end 85 | 86 | endmodule 87 | -------------------------------------------------------------------------------- /hdl/scenario15/ff_fifo_pow2_depth.sv: -------------------------------------------------------------------------------- 1 | //---AXI-STREAM FLOP-BASED FIFO WITH DEPTH OF PWR OF 2---// 2 | //Valid/Rready flags generation is based on comparison of write & read counters 3 | //and their MSBs that indicate "Wrap-around", as per Clifford_E_Cummings. 4 | 5 | module ff_fifo_pow2_depth #(parameter D_WIDTH = 6, A_WIDTH = 2) 6 | ( 7 | input clk, 8 | input rst, 9 | input [(D_WIDTH-1):0] up_data, 10 | input up_valid, 11 | output up_ready, 12 | output [(D_WIDTH-1):0] down_data, 13 | output down_valid, 14 | input down_ready 15 | ); 16 | 17 | wire push, pop; 18 | wire empty, full; 19 | wire [(A_WIDTH-1):0] wr_ptr, rd_ptr; 20 | 21 | reg [(A_WIDTH):0] fullwidth_wr_ptr, fullwidth_rd_ptr; 22 | reg [(D_WIDTH-1):0] ram[2**A_WIDTH-1:0]; 23 | 24 | 25 | always @ (posedge clk) 26 | begin 27 | if (push) 28 | ram[wr_ptr] <= up_data; 29 | end 30 | 31 | //WR_COUNTER 32 | always @(posedge clk) 33 | if (rst) begin 34 | fullwidth_wr_ptr <= {(A_WIDTH+1){1'b0}}; 35 | end else if (push) begin 36 | fullwidth_wr_ptr <= fullwidth_wr_ptr + 1; 37 | end 38 | 39 | //RD_COUNTER 40 | always @(posedge clk) 41 | if (rst) begin 42 | fullwidth_rd_ptr <= {(A_WIDTH+1){1'b0}}; 43 | end else if (pop) begin 44 | fullwidth_rd_ptr <= fullwidth_rd_ptr + 1; 45 | end 46 | 47 | //Generate push and pop signals 48 | assign push = up_valid & up_ready; 49 | assign pop = down_valid & down_ready; 50 | 51 | //output LSBits out of full_wr_ptr 52 | assign wr_ptr = fullwidth_wr_ptr[(A_WIDTH-1):0]; 53 | //output LSBits out of full_rd_ptr 54 | assign rd_ptr = fullwidth_rd_ptr[(A_WIDTH-1):0]; 55 | 56 | //"empty" 57 | //It is "1" when MSBits and other bits of "full_rd_ptr" and "full_wr_ptr" are equal 58 | assign empty = ((fullwidth_wr_ptr[(A_WIDTH)] == fullwidth_rd_ptr[(A_WIDTH)]) && 59 | (fullwidth_wr_ptr[(A_WIDTH-1):0] == fullwidth_rd_ptr[(A_WIDTH-1):0])) ? 1'b1 : 1'b0; 60 | //"valid" aka "not_empty" 61 | assign down_valid = ~empty; 62 | 63 | //"full" 64 | //It is "1" when MSBits of "full_rd_ptr" and "full_wr_ptr" are not equal but other bits equal 65 | assign full = ((fullwidth_wr_ptr[(A_WIDTH)] != fullwidth_rd_ptr[(A_WIDTH)]) && 66 | (fullwidth_wr_ptr[(A_WIDTH-1):0] == fullwidth_rd_ptr[(A_WIDTH-1):0])) ? 1'b1 : 1'b0; 67 | //"ready" aka "not_full" 68 | assign up_ready = ~full; 69 | 70 | assign down_data = ram[rd_ptr]; 71 | 72 | endmodule 73 | -------------------------------------------------------------------------------- /hdl/scenario15/rtl.sv: -------------------------------------------------------------------------------- 1 | //---TOP MODULE FOR RTL DESIGN---// 2 | 3 | module rtl #(parameter D_WIDTH = 6, A_WIDTH = 2) 4 | ( 5 | input clk, 6 | input rst, 7 | input [(D_WIDTH-1):0] up_data, 8 | input up_valid, 9 | output up_ready, 10 | output [(D_WIDTH-1):0] down_data, 11 | output down_valid, 12 | input down_ready 13 | ); 14 | 15 | wire [(D_WIDTH-1):0] w_sftreg1_down_data; 16 | wire w_sftreg1_down_valid; 17 | wire w_fifo1_up_ready; 18 | 19 | shiftreg_4depth # (.D_WIDTH (D_WIDTH)) 20 | SFTREG1 21 | ( .clk(clk), 22 | .rst(rst), 23 | .up_data(up_data), 24 | .up_valid(up_valid), 25 | .up_ready(up_ready), 26 | .down_data(w_sftreg1_down_data), 27 | .down_valid(w_sftreg1_down_valid), 28 | .down_ready(w_fifo1_up_ready)); 29 | 30 | ff_fifo_pow2_depth # (.D_WIDTH (D_WIDTH), .A_WIDTH (A_WIDTH)) 31 | FIFO1 32 | ( .clk(clk), 33 | .rst(rst), 34 | .up_data(w_sftreg1_down_data), 35 | .up_valid(w_sftreg1_down_valid), 36 | .up_ready(w_fifo1_up_ready), 37 | .down_data(down_data), 38 | .down_valid(down_valid), 39 | .down_ready(down_ready)); 40 | 41 | endmodule 42 | -------------------------------------------------------------------------------- /hdl/scenario15/shiftreg_4depth.sv: -------------------------------------------------------------------------------- 1 | module shiftreg_4depth #(parameter D_WIDTH = 6) 2 | ( 3 | input clk, 4 | input rst, 5 | input [(D_WIDTH-1):0] up_data, 6 | input up_valid, 7 | output up_ready, 8 | output [(D_WIDTH-1):0] down_data, 9 | output down_valid, 10 | input down_ready 11 | ); 12 | 13 | reg valid0, valid1, valid2, valid3; 14 | reg [(D_WIDTH-1):0] data0, data1, data2, data3; 15 | 16 | //Data 17 | always @(posedge clk) 18 | if (down_ready) begin 19 | data0 <= up_data; 20 | data1 <= data0; 21 | data2 <= data1; 22 | data3 <= data2; 23 | end 24 | 25 | //Valid 26 | always @(posedge clk) 27 | if (rst) begin 28 | valid0 <= 1'b0; 29 | valid1 <= 1'b0; 30 | valid2 <= 1'b0; 31 | valid3 <= 1'b0; 32 | end else if (down_ready) begin 33 | valid0 <= up_valid; 34 | valid1 <= valid0; 35 | valid2 <= valid1; 36 | valid3 <= valid2; 37 | end 38 | 39 | assign down_valid = valid3; 40 | assign down_data = data3; 41 | assign up_ready = down_ready; 42 | 43 | endmodule 44 | -------------------------------------------------------------------------------- /hdl/scenario15/tb.sv: -------------------------------------------------------------------------------- 1 | module tb 2 | # ( 3 | parameter D_WIDTH = 6, A_WIDTH = 2 4 | ); 5 | 6 | //-------------------------------------------------------------------------- 7 | // Signals to drive Device Under Test - DUT 8 | 9 | logic clk; 10 | wire rst; 11 | 12 | // Upstream 13 | 14 | wire up_valid; 15 | wire up_ready; 16 | wire [(D_WIDTH-1):0] up_data; 17 | 18 | // Downstream 19 | 20 | wire down_valid; 21 | wire down_ready; 22 | wire [(D_WIDTH-1):0] down_data; 23 | 24 | //-------------------------------------------------------------------------- 25 | // DUT instantiation 26 | 27 | rtl # (.D_WIDTH (D_WIDTH), .A_WIDTH (A_WIDTH)) 28 | RTL1 29 | ( .clk(clk), 30 | .rst(rst), 31 | .up_data(up_data), 32 | .up_valid(up_valid), 33 | .up_ready(up_ready), 34 | .down_data(down_data), 35 | .down_valid(down_valid), 36 | .down_ready(down_ready)); 37 | 38 | //-------------------------------------------------------------------------- 39 | // Driving clock 40 | 41 | initial 42 | begin 43 | forever #5 clk = ~ clk; 44 | end 45 | 46 | //-------------------------------------------------------------------------- 47 | //Initialization and driving simulation 48 | initial 49 | begin 50 | clk = 0; 51 | forever @ (posedge clk); 52 | end 53 | 54 | endmodule 55 | -------------------------------------------------------------------------------- /hdl/scenario16/check.sv: -------------------------------------------------------------------------------- 1 | module check #(parameter D_WIDTH = 6) 2 | ( 3 | input [(D_WIDTH-1):0] rtl_data, 4 | input rtl_valid, 5 | input [(D_WIDTH-1):0] model_data 6 | ); 7 | 8 | //This is a BLACKBOX MODULE 9 | //All input ports are not used inside the module because they will be accessed externally from python 10 | //using hierarchical references and used in "post_process_logic_state" call of "check_gadget". 11 | 12 | endmodule 13 | -------------------------------------------------------------------------------- /hdl/scenario16/credbasedfc_44.sv: -------------------------------------------------------------------------------- 1 | module credbasedfc_44 #(parameter D_WIDTH = 6, CREDIT_WIDTH = 3) 2 | ( 3 | input clk, 4 | input rst, 5 | input [(D_WIDTH-1):0] up_data, 6 | input up_valid, 7 | output up_ready, 8 | output [(D_WIDTH-1):0] down_data, 9 | output down_valid, 10 | input down_credit, 11 | input [(CREDIT_WIDTH-1):0] credit_initval 12 | ); 13 | 14 | //localparam INITVAL = 3'b100; 15 | 16 | reg valid0, valid1, valid2, valid3; 17 | reg [(D_WIDTH-1):0] data0, data1, data2, data3; 18 | reg credit0, credit1, credit2, credit3; 19 | reg [(CREDIT_WIDTH-1):0] creditcounter; 20 | 21 | wire [(CREDIT_WIDTH-1):0] addend, creditcounter_d; 22 | wire creditplus, creditminus; 23 | wire valid_pipeline; 24 | 25 | //Data 26 | always @(posedge clk) 27 | begin 28 | data0 <= up_data; 29 | data1 <= data0; 30 | data2 <= data1; 31 | data3 <= data2; 32 | end 33 | 34 | //Valid 35 | always @(posedge clk) 36 | if (rst) begin 37 | valid0 <= 1'b0; 38 | valid1 <= 1'b0; 39 | valid2 <= 1'b0; 40 | valid3 <= 1'b0; 41 | end else begin 42 | valid0 <= valid_pipeline; 43 | valid1 <= valid0; 44 | valid2 <= valid1; 45 | valid3 <= valid2; 46 | end 47 | 48 | //Credit delay 49 | always @(posedge clk) 50 | if (rst) begin 51 | credit0 <= 1'b0; 52 | credit1 <= 1'b0; 53 | credit2 <= 1'b0; 54 | credit3 <= 1'b0; 55 | end else begin 56 | credit0 <= down_credit; 57 | credit1 <= credit0; 58 | credit2 <= credit1; 59 | credit3 <= credit2; 60 | end 61 | 62 | 63 | //Credit counter using two's complement addition 64 | always @(posedge clk) 65 | if (rst) 66 | creditcounter <= credit_initval; 67 | else 68 | creditcounter <= creditcounter_d; 69 | 70 | //Two complements arithmetics 71 | //creditplus creditminus addend 72 | // 1 1 0 73 | // 1 0 1 74 | // 0 1 11..1 - this is "minus-one" 75 | // 0 0 0 76 | //assign addend = creditplus ? (creditminus ? 0 : 1) : (creditminus ? 111 : 0) 77 | 78 | 79 | assign down_valid = valid3; 80 | assign down_data = data3; 81 | assign valid_pipeline = up_valid & up_ready; 82 | assign up_ready = (| creditcounter); 83 | assign creditplus = credit3; 84 | assign creditminus = up_valid & up_ready; 85 | assign addend = creditplus ? (creditminus ? 0 : 1) : (creditminus ? {(CREDIT_WIDTH){1'b1}} : 0); 86 | assign creditcounter_d = creditcounter + addend; 87 | 88 | 89 | endmodule 90 | -------------------------------------------------------------------------------- /hdl/scenario16/custom_param.sv: -------------------------------------------------------------------------------- 1 | module custom_param #(parameter CREDIT_WIDTH = 3) 2 | ( 3 | output [(CREDIT_WIDTH-1):0] credit_initval 4 | ); 5 | 6 | 7 | //BEGIN CHANGE CUSTOM PARAMETERS HERE 8 | assign credit_initval = 3'b100; 9 | 10 | //END CHANGE CUSTOM PARAMETERS HERE 11 | 12 | endmodule 13 | -------------------------------------------------------------------------------- /hdl/scenario16/ff_fifo_credret_pow2_depth.sv: -------------------------------------------------------------------------------- 1 | //---AXI-STREAM FLOP-BASED FIFO WITH CREDIT RETURN UPSTREAM SIGNAL WITH DEPTH OF PWR OF 2---// 2 | //Valid/Rready flags generation is based on comparison of write & read counters 3 | //and their MSBs that indicate "Wrap-around", as per Clifford_E_Cummings. 4 | 5 | module ff_fifo_credret_pow2_depth #(parameter D_WIDTH = 6, A_WIDTH = 2) 6 | ( 7 | input clk, 8 | input rst, 9 | input [(D_WIDTH-1):0] up_data, 10 | input up_valid, 11 | output up_ready, 12 | output up_credit, 13 | output [(D_WIDTH-1):0] down_data, 14 | output down_valid, 15 | input down_ready 16 | ); 17 | 18 | wire push, pop; 19 | wire empty, full; 20 | wire [(A_WIDTH-1):0] wr_ptr, rd_ptr; 21 | 22 | reg [(A_WIDTH):0] fullwidth_wr_ptr, fullwidth_rd_ptr; 23 | reg [(D_WIDTH-1):0] ram[2**A_WIDTH-1:0]; 24 | 25 | 26 | always @ (posedge clk) 27 | begin 28 | if (push) 29 | ram[wr_ptr] <= up_data; 30 | end 31 | 32 | //WR_COUNTER 33 | always @(posedge clk) 34 | if (rst) begin 35 | fullwidth_wr_ptr <= {(A_WIDTH+1){1'b0}}; 36 | end else if (push) begin 37 | fullwidth_wr_ptr <= fullwidth_wr_ptr + 1; 38 | end 39 | 40 | //RD_COUNTER 41 | always @(posedge clk) 42 | if (rst) begin 43 | fullwidth_rd_ptr <= {(A_WIDTH+1){1'b0}}; 44 | end else if (pop) begin 45 | fullwidth_rd_ptr <= fullwidth_rd_ptr + 1; 46 | end 47 | 48 | //Generate push and pop signals 49 | assign push = up_valid & up_ready; 50 | assign pop = down_valid & down_ready; 51 | 52 | //output LSBits out of full_wr_ptr 53 | assign wr_ptr = fullwidth_wr_ptr[(A_WIDTH-1):0]; 54 | //output LSBits out of full_rd_ptr 55 | assign rd_ptr = fullwidth_rd_ptr[(A_WIDTH-1):0]; 56 | 57 | //"empty" 58 | //It is "1" when MSBits and other bits of "full_rd_ptr" and "full_wr_ptr" are equal 59 | assign empty = ((fullwidth_wr_ptr[(A_WIDTH)] == fullwidth_rd_ptr[(A_WIDTH)]) && 60 | (fullwidth_wr_ptr[(A_WIDTH-1):0] == fullwidth_rd_ptr[(A_WIDTH-1):0])) ? 1'b1 : 1'b0; 61 | //"valid" aka "not_empty" 62 | assign down_valid = ~empty; 63 | 64 | //"full" 65 | //It is "1" when MSBits of "full_rd_ptr" and "full_wr_ptr" are not equal but other bits equal 66 | assign full = ((fullwidth_wr_ptr[(A_WIDTH)] != fullwidth_rd_ptr[(A_WIDTH)]) && 67 | (fullwidth_wr_ptr[(A_WIDTH-1):0] == fullwidth_rd_ptr[(A_WIDTH-1):0])) ? 1'b1 : 1'b0; 68 | //"ready" aka "not_full" 69 | assign up_ready = ~full; 70 | 71 | assign down_data = ram[rd_ptr]; 72 | 73 | //"credit return" when "pop" 74 | assign up_credit = pop; 75 | 76 | endmodule 77 | -------------------------------------------------------------------------------- /hdl/scenario16/model.sv: -------------------------------------------------------------------------------- 1 | //---MODEL---// 2 | 3 | module model #(parameter D_WIDTH = 6) 4 | ( 5 | input clk, 6 | input rst, 7 | input [(D_WIDTH-1):0] up_data, 8 | input push, 9 | output logic [(D_WIDTH-1):0] down_data, 10 | input pop 11 | ); 12 | 13 | // Modeling 14 | int unsigned qsize; 15 | logic [(D_WIDTH-1):0] queue [$]; 16 | logic [(D_WIDTH-1):0] queue0, queue1, queue2; 17 | 18 | ////START OF QUEUE MODEL//// 19 | always @ (posedge clk) 20 | begin 21 | if (rst) 22 | begin 23 | queue = {}; 24 | end 25 | else 26 | ////DO MODELLING HERE//// 27 | begin 28 | if (push) 29 | begin //blocking assignments and function calls can be used between these begin and end 30 | queue.push_back (up_data); 31 | end 32 | if (pop) 33 | begin 34 | if (queue.size () != 0) 35 | begin 36 | queue.delete (0); // queue.delete(0) is used because "queue.pop_front()" method doesn't work in IcarusVerilog 37 | end 38 | end 39 | end 40 | 41 | //The Model doesn't interact with RTL but let's use non-blocking assigments for final model values, 42 | //it is just a good parctice that will help avoid races between RTL and Model 43 | qsize <= queue.size (); 44 | //Cocotb cannot access queue[$] via hierarchical reference but can access queue0, queue1, queue2 with constant indexes 45 | queue0 <= queue [0]; 46 | queue1 <= queue [1]; 47 | queue2 <= queue [2]; 48 | down_data <= queue [0]; 49 | 50 | end 51 | ////END OF QUEUE MODEL//// 52 | 53 | endmodule 54 | -------------------------------------------------------------------------------- /hdl/scenario16/rtl.sv: -------------------------------------------------------------------------------- 1 | //---TOP MODULE FOR RTL DESIGN---// 2 | 3 | module rtl #(parameter D_WIDTH = 6, A_WIDTH = 2, CREDIT_WIDTH = 3) 4 | ( 5 | input clk, 6 | input rst, 7 | input [(D_WIDTH-1):0] up_data, 8 | input up_valid, 9 | output up_ready, 10 | output [(D_WIDTH-1):0] down_data, 11 | output down_valid, 12 | input down_ready 13 | ); 14 | 15 | wire [(D_WIDTH-1):0] w_cbfc1_down_data; 16 | wire w_cbfc1_down_valid; 17 | wire w_fifocr1_up_ready; 18 | wire w_fifocr1_up_credit; 19 | wire [(CREDIT_WIDTH-1):0] w_cprm1_credit_initval_w; 20 | 21 | 22 | custom_param #(.CREDIT_WIDTH (CREDIT_WIDTH)) 23 | CPRM1 24 | ( 25 | .credit_initval(w_cprm1_credit_initval_w)); 26 | 27 | 28 | credbasedfc_44 # (.D_WIDTH (D_WIDTH), .CREDIT_WIDTH (CREDIT_WIDTH)) 29 | CBFC1 30 | ( .clk(clk), 31 | .rst(rst), 32 | .up_data(up_data), 33 | .up_valid(up_valid), 34 | .up_ready(up_ready), 35 | .down_data(w_cbfc1_down_data), 36 | .down_valid(w_cbfc1_down_valid), 37 | .down_credit(w_fifocr1_up_credit), 38 | .credit_initval(w_cprm1_credit_initval_w)); 39 | 40 | ff_fifo_credret_pow2_depth # (.D_WIDTH (D_WIDTH), .A_WIDTH (A_WIDTH)) 41 | FIFOCR1 42 | ( .clk(clk), 43 | .rst(rst), 44 | .up_data(w_cbfc1_down_data), 45 | .up_valid(w_cbfc1_down_valid), 46 | .up_ready(w_fifocr1_up_ready), 47 | .up_credit(w_fifocr1_up_credit), 48 | .down_data(down_data), 49 | .down_valid(down_valid), 50 | .down_ready(down_ready)); 51 | 52 | endmodule 53 | -------------------------------------------------------------------------------- /hdl/scenario16/tb.sv: -------------------------------------------------------------------------------- 1 | module tb 2 | # ( 3 | parameter D_WIDTH = 6, A_WIDTH = 2, CREDIT_WIDTH = 3 4 | ); 5 | 6 | //-------------------------------------------------------------------------- 7 | // Signals to drive Device Under Test - DUT 8 | 9 | logic clk; 10 | wire rst; 11 | 12 | // Upstream 13 | 14 | wire up_valid; 15 | wire up_ready; 16 | wire [(D_WIDTH-1):0] up_data; 17 | 18 | // Downstream 19 | 20 | wire down_valid; 21 | wire down_ready; 22 | wire [(D_WIDTH-1):0] down_data; 23 | 24 | // Model 25 | 26 | wire [(D_WIDTH-1):0] model_data; 27 | 28 | //-------------------------------------------------------------------------- 29 | // DUT instantiation 30 | 31 | rtl # (.D_WIDTH (D_WIDTH), .A_WIDTH (A_WIDTH), .CREDIT_WIDTH(CREDIT_WIDTH)) 32 | RTL1 33 | ( .clk(clk), 34 | .rst(rst), 35 | .up_data(up_data), 36 | .up_valid(up_valid), 37 | .up_ready(up_ready), 38 | .down_data(down_data), 39 | .down_valid(down_valid), 40 | .down_ready(down_ready)); 41 | 42 | //-------------------------------------------------------------------------- 43 | // MODEL instantiation 44 | 45 | wire push; 46 | wire pop; 47 | 48 | assign push = up_valid & up_ready; 49 | assign pop = down_valid & down_ready; 50 | 51 | model # (.D_WIDTH (D_WIDTH)) 52 | MDL1 53 | ( .clk(clk), 54 | .rst(rst), 55 | .up_data(up_data), 56 | .push(push), 57 | .down_data(model_data), 58 | .pop(pop)); 59 | 60 | //-------------------------------------------------------------------------- 61 | // CHECKING module instantiation 62 | 63 | check # (.D_WIDTH (D_WIDTH)) 64 | CHK1 65 | ( 66 | .rtl_data(down_data), 67 | .rtl_valid(down_valid), 68 | .model_data(model_data)); 69 | 70 | //-------------------------------------------------------------------------- 71 | // Driving clock 72 | 73 | initial 74 | begin 75 | forever #5 clk = ~ clk; 76 | end 77 | 78 | //-------------------------------------------------------------------------- 79 | //Initialization and driving simulation 80 | initial 81 | begin 82 | clk = 0; 83 | forever @ (posedge clk); 84 | end 85 | 86 | endmodule 87 | -------------------------------------------------------------------------------- /hdl/scenario17/check.sv: -------------------------------------------------------------------------------- 1 | module check #(parameter D_WIDTH = 6) 2 | ( 3 | input [(D_WIDTH-1):0] rtl_data, 4 | input rtl_valid, 5 | input [(D_WIDTH-1):0] model_data 6 | ); 7 | 8 | //This is a BLACKBOX MODULE 9 | //All input ports are not used inside the module because they will be accessed externally from python 10 | //using hierarchical references and used in "post_process_logic_state" call of "check_gadget". 11 | 12 | endmodule 13 | -------------------------------------------------------------------------------- /hdl/scenario17/model.sv: -------------------------------------------------------------------------------- 1 | //---MODEL---// 2 | 3 | module model #(parameter D_WIDTH = 6) 4 | ( 5 | input clk, 6 | input rst, 7 | input [(D_WIDTH-1):0] up_data, 8 | input push, 9 | output logic [(D_WIDTH-1):0] down_data, 10 | input pop 11 | ); 12 | 13 | // Modeling 14 | int unsigned qsize_a, qsize_b; 15 | logic [(D_WIDTH-1):0] queue_a [$], queue_b [$]; 16 | logic [(D_WIDTH-1):0] queue0_a, queue1_a, queue2_a, queue0_b, queue1_b, queue2_b; 17 | 18 | ////START OF QUEUE MODEL//// 19 | logic [(D_WIDTH-1):0] queue_temp_data; 20 | //Queue_A - output queue; Queue_B - uncommited queue 21 | always @ (posedge clk) 22 | begin 23 | if (rst) 24 | begin 25 | queue_a = {}; //Committed queue 26 | queue_b = {}; //Uncommitted queue 27 | end 28 | else 29 | ////DO MODELLING HERE//// 30 | begin 31 | if (push) 32 | begin //blocking assignments and function calls can be used between these begin and end 33 | if ((up_data[(D_WIDTH-1)] == 1) & (up_data[(D_WIDTH-2)] == 1)) begin //tlast & tuser 34 | //flush queue_uncommitted 35 | queue_b = {}; 36 | end else if ((up_data[(D_WIDTH-1)] == 0) & (up_data[(D_WIDTH-2)] == 1)) begin //tlast & ~tuser 37 | //push into queue_uncommitted 38 | queue_b.push_back (up_data); 39 | //move all uncommitted_queue content to queue 40 | while(queue_b.size() != 0) 41 | begin 42 | queue_temp_data = queue_b [0]; 43 | queue_b.delete (0); 44 | queue_a.push_back(queue_temp_data); 45 | end 46 | end else begin //~tlast 47 | //push into queue_uncommitted 48 | queue_b.push_back (up_data); 49 | end 50 | end 51 | if (pop) 52 | begin 53 | if (queue_a.size () != 0) 54 | begin 55 | queue_a.delete (0); // queue.delete(0) is used because "queue.pop_front()" method doesn't work in IcarusVerilog 56 | end 57 | end 58 | end 59 | 60 | //The Model doesn't interact with RTL but let's use non-blocking assigments for final model values, 61 | //it is just a good parctice that will help avoid races between RTL and Model 62 | qsize_a <= queue_a.size (); 63 | qsize_b <= queue_b.size (); 64 | //Cocotb cannot access queue[$] via hierarchical reference but can access queue0, queue1, queue2 with constant indexes 65 | queue0_a <= queue_a [0]; 66 | queue1_a <= queue_a [1]; 67 | queue2_a <= queue_a [2]; 68 | queue0_b <= queue_b [0]; 69 | queue1_b <= queue_b [1]; 70 | queue2_b <= queue_b [2]; 71 | down_data <= queue_a [0]; 72 | 73 | end 74 | ////END OF QUEUE MODEL//// 75 | 76 | endmodule 77 | -------------------------------------------------------------------------------- /hdl/scenario17/rtl.sv: -------------------------------------------------------------------------------- 1 | //---TOP MODULE FOR RTL DESIGN---// 2 | 3 | module rtl #(parameter D_WIDTH = 6, A_WIDTH = 2) 4 | ( 5 | input clk, 6 | input rst, 7 | input [(D_WIDTH-1):0] up_data, 8 | input up_valid, 9 | output up_ready, 10 | output [(D_WIDTH-1):0] down_data, 11 | output down_valid, 12 | input down_ready 13 | ); 14 | 15 | custom_logic # (.D_WIDTH (D_WIDTH)) 16 | CLGC1 17 | ( .clk(clk), 18 | .rst(rst), 19 | .up_data(up_data), 20 | .up_valid(up_valid), 21 | .up_ready(up_ready), 22 | .down_data(down_data), 23 | .down_valid(down_valid), 24 | .down_ready(down_ready)); 25 | 26 | endmodule 27 | -------------------------------------------------------------------------------- /hdl/scenario17/tb.sv: -------------------------------------------------------------------------------- 1 | module tb 2 | # ( 3 | parameter D_WIDTH = 6, A_WIDTH = 2 4 | ); 5 | 6 | //-------------------------------------------------------------------------- 7 | // Signals to drive Device Under Test - DUT 8 | 9 | logic clk; 10 | wire rst; 11 | 12 | // Upstream 13 | 14 | wire up_valid; 15 | wire up_ready; 16 | wire [(D_WIDTH-1):0] up_data; 17 | 18 | // Downstream 19 | 20 | wire down_valid; 21 | wire down_ready; 22 | wire [(D_WIDTH-1):0] down_data; 23 | 24 | // Model 25 | 26 | wire [(D_WIDTH-1):0] model_data; 27 | 28 | //-------------------------------------------------------------------------- 29 | // DUT instantiation 30 | 31 | rtl # (.D_WIDTH (D_WIDTH), .A_WIDTH (A_WIDTH)) 32 | RTL1 33 | ( .clk(clk), 34 | .rst(rst), 35 | .up_data(up_data), 36 | .up_valid(up_valid), 37 | .up_ready(up_ready), 38 | .down_data(down_data), 39 | .down_valid(down_valid), 40 | .down_ready(down_ready)); 41 | 42 | //-------------------------------------------------------------------------- 43 | // MODEL instantiation 44 | 45 | wire push; 46 | wire pop; 47 | 48 | assign push = up_valid & up_ready; 49 | assign pop = down_valid & down_ready; 50 | 51 | model # (.D_WIDTH (D_WIDTH)) 52 | MDL1 53 | ( .clk(clk), 54 | .rst(rst), 55 | .up_data(up_data), 56 | .push(push), 57 | .down_data(model_data), 58 | .pop(pop)); 59 | 60 | //-------------------------------------------------------------------------- 61 | // CHECKING module instantiation 62 | 63 | check # (.D_WIDTH (D_WIDTH)) 64 | CHK1 65 | ( 66 | .rtl_data(down_data), 67 | .rtl_valid(down_valid), 68 | .model_data(model_data)); 69 | 70 | //-------------------------------------------------------------------------- 71 | // Driving clock 72 | 73 | initial 74 | begin 75 | forever #5 clk = ~ clk; 76 | end 77 | 78 | //-------------------------------------------------------------------------- 79 | //Initialization and driving simulation 80 | initial 81 | begin 82 | clk = 0; 83 | forever @ (posedge clk); 84 | end 85 | 86 | endmodule 87 | -------------------------------------------------------------------------------- /hdl/scenario18/check.sv: -------------------------------------------------------------------------------- 1 | module check #(parameter D_WIDTH = 6) 2 | ( 3 | input [(D_WIDTH-1):0] rtl_data, 4 | input rtl_valid, 5 | input [(D_WIDTH-1):0] model_data 6 | ); 7 | 8 | //This is a BLACKBOX MODULE 9 | //All input ports are not used inside the module because they will be accessed externally from python 10 | //using hierarchical references and used in "post_process_logic_state" call of "check_gadget". 11 | 12 | endmodule 13 | -------------------------------------------------------------------------------- /hdl/scenario18/model.sv: -------------------------------------------------------------------------------- 1 | //---MODEL---// 2 | 3 | module model #(parameter D_WIDTH = 6) 4 | ( 5 | input clk, 6 | input rst, 7 | input [(D_WIDTH-1):0] up_data, 8 | input push, 9 | output logic [(D_WIDTH-1):0] down_data, 10 | input pop 11 | ); 12 | 13 | // Modeling 14 | int unsigned qsize_a, qsize_b; 15 | logic [(D_WIDTH-1):0] queue_a [$], queue_b [$]; 16 | logic [(D_WIDTH-1):0] queue0_a, queue1_a, queue2_a, queue0_b, queue1_b, queue2_b; 17 | 18 | ////START OF QUEUE MODEL//// 19 | logic [(D_WIDTH-1):0] queue_temp_data; 20 | //Queue_A - output queue; Queue_B - uncommited queue 21 | always @ (posedge clk) 22 | begin 23 | if (rst) 24 | begin 25 | queue_a = {}; //Committed queue 26 | queue_b = {}; //Uncommitted queue 27 | end 28 | else 29 | ////DO MODELLING HERE//// 30 | begin 31 | if (push) 32 | begin //blocking assignments and function calls can be used between these begin and end 33 | if ((up_data[(D_WIDTH-1)] == 1) & (up_data[(D_WIDTH-2)] == 1)) begin //tlast & tuser 34 | //flush queue_uncommitted 35 | queue_b = {}; 36 | end else if ((up_data[(D_WIDTH-1)] == 0) & (up_data[(D_WIDTH-2)] == 1)) begin //tlast & ~tuser 37 | //push into queue_uncommitted 38 | queue_b.push_back (up_data); 39 | //move all uncommitted_queue content to queue 40 | while(queue_b.size() != 0) 41 | begin 42 | queue_temp_data = queue_b [0]; 43 | queue_b.delete (0); 44 | queue_a.push_back(queue_temp_data); 45 | end 46 | end else begin //~tlast 47 | //push into queue_uncommitted 48 | queue_b.push_back (up_data); 49 | end 50 | end 51 | if (pop) 52 | begin 53 | if (queue_a.size () != 0) 54 | begin 55 | queue_a.delete (0); // queue.delete(0) is used because "queue.pop_front()" method doesn't work in IcarusVerilog 56 | end 57 | end 58 | end 59 | 60 | //The Model doesn't interact with RTL but let's use non-blocking assigments for final model values, 61 | //it is just a good parctice that will help avoid races between RTL and Model 62 | qsize_a <= queue_a.size (); 63 | qsize_b <= queue_b.size (); 64 | //Cocotb cannot access queue[$] via hierarchical reference but can access queue0, queue1, queue2 with constant indexes 65 | queue0_a <= queue_a [0]; 66 | queue1_a <= queue_a [1]; 67 | queue2_a <= queue_a [2]; 68 | queue0_b <= queue_b [0]; 69 | queue1_b <= queue_b [1]; 70 | queue2_b <= queue_b [2]; 71 | down_data <= queue_a [0]; 72 | 73 | end 74 | ////END OF QUEUE MODEL//// 75 | 76 | endmodule 77 | -------------------------------------------------------------------------------- /hdl/scenario18/rtl.sv: -------------------------------------------------------------------------------- 1 | //---TOP MODULE FOR RTL DESIGN---// 2 | 3 | module rtl #(parameter D_WIDTH = 6, A_WIDTH = 3) 4 | ( 5 | input clk, 6 | input rst, 7 | input [(D_WIDTH-1):0] up_data, 8 | input up_valid, 9 | output up_ready, 10 | output [(D_WIDTH-1):0] down_data, 11 | output down_valid, 12 | input down_ready 13 | ); 14 | 15 | ff_fifo_rollback_pow2_depth # (.D_WIDTH (D_WIDTH), .A_WIDTH(A_WIDTH)) 16 | FIFORLB1 17 | ( .clk(clk), 18 | .rst(rst), 19 | .up_data(up_data), 20 | .up_valid(up_valid), 21 | .up_ready(up_ready), 22 | .down_data(down_data), 23 | .down_valid(down_valid), 24 | .down_ready(down_ready)); 25 | 26 | endmodule 27 | -------------------------------------------------------------------------------- /hdl/scenario18/tb.sv: -------------------------------------------------------------------------------- 1 | module tb 2 | # ( 3 | parameter D_WIDTH = 6, A_WIDTH = 3 4 | ); 5 | 6 | //-------------------------------------------------------------------------- 7 | // Signals to drive Device Under Test - DUT 8 | 9 | logic clk; 10 | wire rst; 11 | 12 | // Upstream 13 | 14 | wire up_valid; 15 | wire up_ready; 16 | wire [(D_WIDTH-1):0] up_data; 17 | 18 | // Downstream 19 | 20 | wire down_valid; 21 | wire down_ready; 22 | wire [(D_WIDTH-1):0] down_data; 23 | 24 | // Model 25 | 26 | wire [(D_WIDTH-1):0] model_data; 27 | 28 | //-------------------------------------------------------------------------- 29 | // DUT instantiation 30 | 31 | rtl # (.D_WIDTH (D_WIDTH), .A_WIDTH (A_WIDTH)) 32 | RTL1 33 | ( .clk(clk), 34 | .rst(rst), 35 | .up_data(up_data), 36 | .up_valid(up_valid), 37 | .up_ready(up_ready), 38 | .down_data(down_data), 39 | .down_valid(down_valid), 40 | .down_ready(down_ready)); 41 | 42 | //-------------------------------------------------------------------------- 43 | // MODEL instantiation 44 | 45 | wire push; 46 | wire pop; 47 | 48 | assign push = up_valid & up_ready; 49 | assign pop = down_valid & down_ready; 50 | 51 | model # (.D_WIDTH (D_WIDTH)) 52 | MDL1 53 | ( .clk(clk), 54 | .rst(rst), 55 | .up_data(up_data), 56 | .push(push), 57 | .down_data(model_data), 58 | .pop(pop)); 59 | 60 | //-------------------------------------------------------------------------- 61 | // CHECKING module instantiation 62 | 63 | check # (.D_WIDTH (D_WIDTH)) 64 | CHK1 65 | ( 66 | .rtl_data(down_data), 67 | .rtl_valid(down_valid), 68 | .model_data(model_data)); 69 | 70 | //-------------------------------------------------------------------------- 71 | // Driving clock 72 | 73 | initial 74 | begin 75 | forever #5 clk = ~ clk; 76 | end 77 | 78 | //-------------------------------------------------------------------------- 79 | //Initialization and driving simulation 80 | initial 81 | begin 82 | clk = 0; 83 | forever @ (posedge clk); 84 | end 85 | 86 | endmodule 87 | -------------------------------------------------------------------------------- /hdl/scenario2/check.sv: -------------------------------------------------------------------------------- 1 | module check #(parameter D_WIDTH = 6) 2 | ( 3 | input [(D_WIDTH-1):0] rtl_data, 4 | input rtl_valid, 5 | input [(D_WIDTH-1):0] model_data 6 | ); 7 | 8 | //This is a BLACKBOX MODULE 9 | //All input ports are not used inside the module because they will be accessed externally from python 10 | //using hierarchical references and used in "post_process_logic_state" call of "check_gadget". 11 | 12 | endmodule 13 | -------------------------------------------------------------------------------- /hdl/scenario2/ff_fifo_pow2_depth.sv: -------------------------------------------------------------------------------- 1 | //---AXI-STREAM FLOP-BASED FIFO WITH DEPTH OF PWR OF 2---// 2 | //Valid/Rready flags generation is based on comparison of write & read counters 3 | //and their MSBs that indicate "Wrap-around", as per Clifford_E_Cummings. 4 | 5 | module ff_fifo_pow2_depth #(parameter D_WIDTH = 6, A_WIDTH = 2) 6 | ( 7 | input clk, 8 | input rst, 9 | input [(D_WIDTH-1):0] up_data, 10 | input up_valid, 11 | output up_ready, 12 | output [(D_WIDTH-1):0] down_data, 13 | output down_valid, 14 | input down_ready 15 | ); 16 | 17 | wire push, pop; 18 | wire empty, full; 19 | wire [(A_WIDTH-1):0] wr_ptr, rd_ptr; 20 | 21 | reg [(A_WIDTH):0] fullwidth_wr_ptr, fullwidth_rd_ptr; 22 | reg [(D_WIDTH-1):0] ram[2**A_WIDTH-1:0]; 23 | 24 | 25 | always @ (posedge clk) 26 | begin 27 | if (push) 28 | ram[wr_ptr] <= up_data; 29 | end 30 | 31 | //WR_COUNTER 32 | always @(posedge clk) 33 | if (rst) begin 34 | fullwidth_wr_ptr <= {(A_WIDTH+1){1'b0}}; 35 | end else if (push) begin 36 | fullwidth_wr_ptr <= fullwidth_wr_ptr + 1; 37 | end 38 | 39 | //RD_COUNTER 40 | always @(posedge clk) 41 | if (rst) begin 42 | fullwidth_rd_ptr <= {(A_WIDTH+1){1'b0}}; 43 | end else if (pop) begin 44 | fullwidth_rd_ptr <= fullwidth_rd_ptr + 1; 45 | end 46 | 47 | //Generate push and pop signals 48 | assign push = up_valid & up_ready; 49 | assign pop = down_valid & down_ready; 50 | 51 | //output LSBits out of full_wr_ptr 52 | assign wr_ptr = fullwidth_wr_ptr[(A_WIDTH-1):0]; 53 | //output LSBits out of full_rd_ptr 54 | assign rd_ptr = fullwidth_rd_ptr[(A_WIDTH-1):0]; 55 | 56 | //"empty" 57 | //It is "1" when MSBits and other bits of "full_rd_ptr" and "full_wr_ptr" are equal 58 | assign empty = ((fullwidth_wr_ptr[(A_WIDTH)] == fullwidth_rd_ptr[(A_WIDTH)]) && 59 | (fullwidth_wr_ptr[(A_WIDTH-1):0] == fullwidth_rd_ptr[(A_WIDTH-1):0])) ? 1'b1 : 1'b0; 60 | //"valid" aka "not_empty" 61 | assign down_valid = ~empty; 62 | 63 | //"full" 64 | //It is "1" when MSBits of "full_rd_ptr" and "full_wr_ptr" are not equal but other bits equal 65 | assign full = ((fullwidth_wr_ptr[(A_WIDTH)] != fullwidth_rd_ptr[(A_WIDTH)]) && 66 | (fullwidth_wr_ptr[(A_WIDTH-1):0] == fullwidth_rd_ptr[(A_WIDTH-1):0])) ? 1'b1 : 1'b0; 67 | //"ready" aka "not_full" 68 | assign up_ready = ~full; 69 | 70 | assign down_data = ram[rd_ptr]; 71 | 72 | endmodule 73 | -------------------------------------------------------------------------------- /hdl/scenario2/model.sv: -------------------------------------------------------------------------------- 1 | //---MODEL---// 2 | 3 | module model #(parameter D_WIDTH = 6) 4 | ( 5 | input clk, 6 | input rst, 7 | input [(D_WIDTH-1):0] up_data, 8 | input push, 9 | output logic [(D_WIDTH-1):0] down_data, 10 | input pop 11 | ); 12 | 13 | // Modeling 14 | int unsigned qsize; 15 | logic [(D_WIDTH-1):0] queue [$]; 16 | logic [(D_WIDTH-1):0] queue0, queue1, queue2; 17 | 18 | ////START OF QUEUE MODEL//// 19 | always @ (posedge clk) 20 | begin 21 | if (rst) 22 | begin 23 | queue = {}; 24 | end 25 | else 26 | ////DO MODELLING HERE//// 27 | begin 28 | if (push) 29 | begin //blocking assignments and function calls can be used between these begin and end 30 | queue.push_back (up_data); 31 | end 32 | if (pop) 33 | begin 34 | if (queue.size () != 0) 35 | begin 36 | queue.delete (0); // queue.delete(0) is used because "queue.pop_front()" method doesn't work in IcarusVerilog 37 | end 38 | end 39 | end 40 | 41 | //The Model doesn't interact with RTL but let's use non-blocking assigments for final model values, 42 | //it is just a good parctice that will help avoid races between RTL and Model 43 | qsize <= queue.size (); 44 | //Cocotb cannot access queue[$] via hierarchical reference but can access queue0, queue1, queue2 with constant indexes 45 | queue0 <= queue [0]; 46 | queue1 <= queue [1]; 47 | queue2 <= queue [2]; 48 | down_data <= queue [0]; 49 | 50 | end 51 | ////END OF QUEUE MODEL//// 52 | 53 | endmodule 54 | -------------------------------------------------------------------------------- /hdl/scenario2/rtl.sv: -------------------------------------------------------------------------------- 1 | //---TOP MODULE FOR RTL DESIGN---// 2 | 3 | module rtl #(parameter D_WIDTH = 6, A_WIDTH = 2) 4 | ( 5 | input clk, 6 | input rst, 7 | input [(D_WIDTH-1):0] up_data, 8 | input up_valid, 9 | output up_ready, 10 | output [(D_WIDTH-1):0] down_data, 11 | output down_valid, 12 | input down_ready 13 | ); 14 | 15 | ff_fifo_pow2_depth # (.D_WIDTH (D_WIDTH), .A_WIDTH (A_WIDTH)) 16 | FIFO1 17 | ( .clk(clk), 18 | .rst(rst), 19 | .up_data(up_data), 20 | .up_valid(up_valid), 21 | .up_ready(up_ready), 22 | .down_data(down_data), 23 | .down_valid(down_valid), 24 | .down_ready(down_ready)); 25 | 26 | endmodule 27 | -------------------------------------------------------------------------------- /hdl/scenario2/tb.sv: -------------------------------------------------------------------------------- 1 | module tb 2 | # ( 3 | parameter D_WIDTH = 6, A_WIDTH = 2 4 | ); 5 | 6 | //-------------------------------------------------------------------------- 7 | // Signals to drive Device Under Test - DUT 8 | 9 | logic clk; 10 | wire rst; 11 | 12 | // Upstream 13 | 14 | wire up_valid; 15 | wire up_ready; 16 | wire [(D_WIDTH-1):0] up_data; 17 | 18 | // Downstream 19 | 20 | wire down_valid; 21 | wire down_ready; 22 | wire [(D_WIDTH-1):0] down_data; 23 | 24 | // Model 25 | 26 | wire [(D_WIDTH-1):0] model_data; 27 | 28 | //-------------------------------------------------------------------------- 29 | // DUT instantiation 30 | 31 | rtl # (.D_WIDTH (D_WIDTH), .A_WIDTH (A_WIDTH)) 32 | RTL1 33 | ( .clk(clk), 34 | .rst(rst), 35 | .up_data(up_data), 36 | .up_valid(up_valid), 37 | .up_ready(up_ready), 38 | .down_data(down_data), 39 | .down_valid(down_valid), 40 | .down_ready(down_ready)); 41 | 42 | //-------------------------------------------------------------------------- 43 | // MODEL instantiation 44 | 45 | wire push; 46 | wire pop; 47 | 48 | assign push = up_valid & up_ready; 49 | assign pop = down_valid & down_ready; 50 | 51 | model # (.D_WIDTH (D_WIDTH)) 52 | MDL1 53 | ( .clk(clk), 54 | .rst(rst), 55 | .up_data(up_data), 56 | .push(push), 57 | .down_data(model_data), 58 | .pop(pop)); 59 | 60 | //-------------------------------------------------------------------------- 61 | // CHECKING module instantiation 62 | 63 | check # (.D_WIDTH (D_WIDTH)) 64 | CHK1 65 | ( 66 | .rtl_data(down_data), 67 | .rtl_valid(down_valid), 68 | .model_data(model_data)); 69 | 70 | //-------------------------------------------------------------------------- 71 | // Driving clock 72 | 73 | initial 74 | begin 75 | forever #5 clk = ~ clk; 76 | end 77 | 78 | //-------------------------------------------------------------------------- 79 | //Initialization and driving simulation 80 | initial 81 | begin 82 | clk = 0; 83 | forever @ (posedge clk); 84 | end 85 | 86 | endmodule 87 | -------------------------------------------------------------------------------- /hdl/scenario3/ff_fifo_pow2_depth.sv: -------------------------------------------------------------------------------- 1 | //---AXI-STREAM FLOP-BASED FIFO WITH DEPTH OF PWR OF 2---// 2 | //Valid/Rready flags generation is based on comparison of write & read counters 3 | //and their MSBs that indicate "Wrap-around", as per Clifford_E_Cummings. 4 | 5 | module ff_fifo_pow2_depth #(parameter D_WIDTH = 6, A_WIDTH = 2) 6 | ( 7 | input clk, 8 | input rst, 9 | input [(D_WIDTH-1):0] up_data, 10 | input up_valid, 11 | output up_ready, 12 | output [(D_WIDTH-1):0] down_data, 13 | output down_valid, 14 | input down_ready 15 | ); 16 | 17 | wire push, pop; 18 | wire empty, full; 19 | wire [(A_WIDTH-1):0] wr_ptr, rd_ptr; 20 | 21 | reg [(A_WIDTH):0] fullwidth_wr_ptr, fullwidth_rd_ptr; 22 | reg [(D_WIDTH-1):0] ram[2**A_WIDTH-1:0]; 23 | 24 | 25 | always @ (posedge clk) 26 | begin 27 | if (push) 28 | ram[wr_ptr] <= up_data; 29 | end 30 | 31 | //WR_COUNTER 32 | always @(posedge clk) 33 | if (rst) begin 34 | fullwidth_wr_ptr <= {(A_WIDTH+1){1'b0}}; 35 | end else if (push) begin 36 | fullwidth_wr_ptr <= fullwidth_wr_ptr + 1; 37 | end 38 | 39 | //RD_COUNTER 40 | always @(posedge clk) 41 | if (rst) begin 42 | fullwidth_rd_ptr <= {(A_WIDTH+1){1'b0}}; 43 | end else if (pop) begin 44 | fullwidth_rd_ptr <= fullwidth_rd_ptr + 1; 45 | end 46 | 47 | //Generate push and pop signals 48 | assign push = up_valid & up_ready; 49 | assign pop = down_valid & down_ready; 50 | 51 | //output LSBits out of full_wr_ptr 52 | assign wr_ptr = fullwidth_wr_ptr[(A_WIDTH-1):0]; 53 | //output LSBits out of full_rd_ptr 54 | assign rd_ptr = fullwidth_rd_ptr[(A_WIDTH-1):0]; 55 | 56 | //"empty" 57 | //It is "1" when MSBits and other bits of "full_rd_ptr" and "full_wr_ptr" are equal 58 | assign empty = ((fullwidth_wr_ptr[(A_WIDTH)] == fullwidth_rd_ptr[(A_WIDTH)]) && 59 | (fullwidth_wr_ptr[(A_WIDTH-1):0] == fullwidth_rd_ptr[(A_WIDTH-1):0])) ? 1'b1 : 1'b0; 60 | //"valid" aka "not_empty" 61 | assign down_valid = ~empty; 62 | 63 | //"full" 64 | //It is "1" when MSBits of "full_rd_ptr" and "full_wr_ptr" are not equal but other bits equal 65 | assign full = ((fullwidth_wr_ptr[(A_WIDTH)] != fullwidth_rd_ptr[(A_WIDTH)]) && 66 | (fullwidth_wr_ptr[(A_WIDTH-1):0] == fullwidth_rd_ptr[(A_WIDTH-1):0])) ? 1'b1 : 1'b0; 67 | //"ready" aka "not_full" 68 | assign up_ready = ~full; 69 | 70 | assign down_data = ram[rd_ptr]; 71 | 72 | endmodule 73 | -------------------------------------------------------------------------------- /hdl/scenario3/rtl.sv: -------------------------------------------------------------------------------- 1 | //---TOP MODULE FOR RTL DESIGN---// 2 | 3 | module rtl #(parameter D_WIDTH = 6, A_WIDTH = 2) 4 | ( 5 | input clk, 6 | input rst, 7 | input [(D_WIDTH-1):0] up_data, 8 | input up_valid, 9 | output up_ready, 10 | output [(D_WIDTH-1):0] down_data, 11 | output down_valid, 12 | input down_ready 13 | ); 14 | 15 | wire [(D_WIDTH-1):0] w_fifo1_down_data; 16 | wire w_fifo1_down_valid; 17 | wire w_fifo2_up_ready; 18 | 19 | ff_fifo_pow2_depth # (.D_WIDTH (D_WIDTH), .A_WIDTH (A_WIDTH)) 20 | FIFO1 21 | ( .clk(clk), 22 | .rst(rst), 23 | .up_data(up_data), 24 | .up_valid(up_valid), 25 | .up_ready(up_ready), 26 | .down_data(w_fifo1_down_data), 27 | .down_valid(w_fifo1_down_valid), 28 | .down_ready(w_fifo2_up_ready)); 29 | 30 | ff_fifo_pow2_depth # (.D_WIDTH (D_WIDTH), .A_WIDTH (A_WIDTH)) 31 | FIFO2 32 | ( .clk(clk), 33 | .rst(rst), 34 | .up_data(w_fifo1_down_data), 35 | .up_valid(w_fifo1_down_valid), 36 | .up_ready(w_fifo2_up_ready), 37 | .down_data(down_data), 38 | .down_valid(down_valid), 39 | .down_ready(down_ready)); 40 | 41 | endmodule 42 | -------------------------------------------------------------------------------- /hdl/scenario3/tb.sv: -------------------------------------------------------------------------------- 1 | module tb 2 | # ( 3 | parameter D_WIDTH = 6, A_WIDTH = 2 4 | ); 5 | 6 | //-------------------------------------------------------------------------- 7 | // Signals to drive Device Under Test - DUT 8 | 9 | logic clk; 10 | wire rst; 11 | 12 | // Upstream 13 | 14 | wire up_valid; 15 | wire up_ready; 16 | wire [(D_WIDTH-1):0] up_data; 17 | 18 | // Downstream 19 | 20 | wire down_valid; 21 | wire down_ready; 22 | wire [(D_WIDTH-1):0] down_data; 23 | 24 | //-------------------------------------------------------------------------- 25 | // DUT instantiation 26 | 27 | rtl # (.D_WIDTH (D_WIDTH), .A_WIDTH (A_WIDTH)) 28 | RTL1 29 | ( .clk(clk), 30 | .rst(rst), 31 | .up_data(up_data), 32 | .up_valid(up_valid), 33 | .up_ready(up_ready), 34 | .down_data(down_data), 35 | .down_valid(down_valid), 36 | .down_ready(down_ready)); 37 | 38 | //-------------------------------------------------------------------------- 39 | // Driving clock 40 | 41 | initial 42 | begin 43 | forever #5 clk = ~ clk; 44 | end 45 | 46 | //-------------------------------------------------------------------------- 47 | //Initialization and driving simulation 48 | initial 49 | begin 50 | clk = 0; 51 | forever @ (posedge clk); 52 | end 53 | 54 | endmodule 55 | -------------------------------------------------------------------------------- /hdl/scenario4/custom_logic.sv: -------------------------------------------------------------------------------- 1 | module custom_logic #(parameter D_WIDTH = 6) 2 | ( 3 | input clk, 4 | input rst, 5 | input [(D_WIDTH-1):0] up_data, 6 | input up_valid, 7 | output up_ready, 8 | output [(D_WIDTH-1):0] down_data, 9 | output down_valid, 10 | input down_ready 11 | ); 12 | 13 | //Connect signals to the debug vector for visualisation 14 | wire [7:0] debug; 15 | 16 | 17 | //REASSIGN DEBUG SIGNALS AS NEEDED 18 | assign debug[7] = 1'bx; 19 | assign debug[6] = 1'bx; 20 | assign debug[5] = 1'bx; 21 | assign debug[4] = 1'bx; 22 | assign debug[3] = 1'bx; 23 | assign debug[2] = 1'bx; 24 | assign debug[1] = 1'bx; 25 | assign debug[0] = 1'bx; 26 | 27 | 28 | //BEGIN CUSTOM LOGIC BLOCK 29 | 30 | assign down_data = up_data; 31 | assign down_valid = up_valid; 32 | assign up_ready = down_ready; 33 | 34 | //END CUSTOM LOGIC BLOCK 35 | 36 | endmodule 37 | -------------------------------------------------------------------------------- /hdl/scenario4/ff_fifo_pow2_depth.sv: -------------------------------------------------------------------------------- 1 | //---AXI-STREAM FLOP-BASED FIFO WITH DEPTH OF PWR OF 2---// 2 | //Valid/Rready flags generation is based on comparison of write & read counters 3 | //and their MSBs that indicate "Wrap-around", as per Clifford_E_Cummings. 4 | 5 | module ff_fifo_pow2_depth #(parameter D_WIDTH = 6, A_WIDTH = 2) 6 | ( 7 | input clk, 8 | input rst, 9 | input [(D_WIDTH-1):0] up_data, 10 | input up_valid, 11 | output up_ready, 12 | output [(D_WIDTH-1):0] down_data, 13 | output down_valid, 14 | input down_ready 15 | ); 16 | 17 | wire push, pop; 18 | wire empty, full; 19 | wire [(A_WIDTH-1):0] wr_ptr, rd_ptr; 20 | 21 | reg [(A_WIDTH):0] fullwidth_wr_ptr, fullwidth_rd_ptr; 22 | reg [(D_WIDTH-1):0] ram[2**A_WIDTH-1:0]; 23 | 24 | 25 | always @ (posedge clk) 26 | begin 27 | if (push) 28 | ram[wr_ptr] <= up_data; 29 | end 30 | 31 | //WR_COUNTER 32 | always @(posedge clk) 33 | if (rst) begin 34 | fullwidth_wr_ptr <= {(A_WIDTH+1){1'b0}}; 35 | end else if (push) begin 36 | fullwidth_wr_ptr <= fullwidth_wr_ptr + 1; 37 | end 38 | 39 | //RD_COUNTER 40 | always @(posedge clk) 41 | if (rst) begin 42 | fullwidth_rd_ptr <= {(A_WIDTH+1){1'b0}}; 43 | end else if (pop) begin 44 | fullwidth_rd_ptr <= fullwidth_rd_ptr + 1; 45 | end 46 | 47 | //Generate push and pop signals 48 | assign push = up_valid & up_ready; 49 | assign pop = down_valid & down_ready; 50 | 51 | //output LSBits out of full_wr_ptr 52 | assign wr_ptr = fullwidth_wr_ptr[(A_WIDTH-1):0]; 53 | //output LSBits out of full_rd_ptr 54 | assign rd_ptr = fullwidth_rd_ptr[(A_WIDTH-1):0]; 55 | 56 | //"empty" 57 | //It is "1" when MSBits and other bits of "full_rd_ptr" and "full_wr_ptr" are equal 58 | assign empty = ((fullwidth_wr_ptr[(A_WIDTH)] == fullwidth_rd_ptr[(A_WIDTH)]) && 59 | (fullwidth_wr_ptr[(A_WIDTH-1):0] == fullwidth_rd_ptr[(A_WIDTH-1):0])) ? 1'b1 : 1'b0; 60 | //"valid" aka "not_empty" 61 | assign down_valid = ~empty; 62 | 63 | //"full" 64 | //It is "1" when MSBits of "full_rd_ptr" and "full_wr_ptr" are not equal but other bits equal 65 | assign full = ((fullwidth_wr_ptr[(A_WIDTH)] != fullwidth_rd_ptr[(A_WIDTH)]) && 66 | (fullwidth_wr_ptr[(A_WIDTH-1):0] == fullwidth_rd_ptr[(A_WIDTH-1):0])) ? 1'b1 : 1'b0; 67 | //"ready" aka "not_full" 68 | assign up_ready = ~full; 69 | 70 | assign down_data = ram[rd_ptr]; 71 | 72 | endmodule 73 | -------------------------------------------------------------------------------- /hdl/scenario4/rtl.sv: -------------------------------------------------------------------------------- 1 | //---TOP MODULE FOR RTL DESIGN---// 2 | 3 | module rtl #(parameter D_WIDTH = 6, A_WIDTH = 2) 4 | ( 5 | input clk, 6 | input rst, 7 | input [(D_WIDTH-1):0] up_data, 8 | input up_valid, 9 | output up_ready, 10 | output [(D_WIDTH-1):0] down_data, 11 | output down_valid, 12 | input down_ready 13 | ); 14 | 15 | wire [(D_WIDTH-1):0] w_fifo1_down_data; 16 | wire w_fifo1_down_valid; 17 | wire w_clgk1_up_ready; 18 | wire [(D_WIDTH-1):0] w_clgk1_down_data; 19 | wire w_clgk1_down_valid; 20 | wire w_fifo2_up_ready; 21 | 22 | ff_fifo_pow2_depth # (.D_WIDTH (D_WIDTH), .A_WIDTH (A_WIDTH)) 23 | FIFO1 24 | ( .clk(clk), 25 | .rst(rst), 26 | .up_data(up_data), 27 | .up_valid(up_valid), 28 | .up_ready(up_ready), 29 | .down_data(w_fifo1_down_data), 30 | .down_valid(w_fifo1_down_valid), 31 | .down_ready(w_clgk1_up_ready)); 32 | 33 | custom_logic # (.D_WIDTH (D_WIDTH)) 34 | CLGC1 35 | ( .clk(clk), 36 | .rst(rst), 37 | .up_data(w_fifo1_down_data), 38 | .up_valid(w_fifo1_down_valid), 39 | .up_ready(w_clgk1_up_ready), 40 | .down_data(w_clgk1_down_data), 41 | .down_valid(w_clgk1_down_valid), 42 | .down_ready(w_fifo2_up_ready)); 43 | 44 | ff_fifo_pow2_depth # (.D_WIDTH (D_WIDTH), .A_WIDTH (A_WIDTH)) 45 | FIFO2 46 | ( .clk(clk), 47 | .rst(rst), 48 | .up_data(w_clgk1_down_data), 49 | .up_valid(w_clgk1_down_valid), 50 | .up_ready(w_fifo2_up_ready), 51 | .down_data(down_data), 52 | .down_valid(down_valid), 53 | .down_ready(down_ready)); 54 | 55 | endmodule 56 | -------------------------------------------------------------------------------- /hdl/scenario4/tb.sv: -------------------------------------------------------------------------------- 1 | module tb 2 | # ( 3 | parameter D_WIDTH = 6, A_WIDTH = 2 4 | ); 5 | 6 | //-------------------------------------------------------------------------- 7 | // Signals to drive Device Under Test - DUT 8 | 9 | logic clk; 10 | wire rst; 11 | 12 | // Upstream 13 | 14 | wire up_valid; 15 | wire up_ready; 16 | wire [(D_WIDTH-1):0] up_data; 17 | 18 | // Downstream 19 | 20 | wire down_valid; 21 | wire down_ready; 22 | wire [(D_WIDTH-1):0] down_data; 23 | 24 | //-------------------------------------------------------------------------- 25 | // DUT instantiation 26 | 27 | rtl # (.D_WIDTH (D_WIDTH), .A_WIDTH (A_WIDTH)) 28 | RTL1 29 | ( .clk(clk), 30 | .rst(rst), 31 | .up_data(up_data), 32 | .up_valid(up_valid), 33 | .up_ready(up_ready), 34 | .down_data(down_data), 35 | .down_valid(down_valid), 36 | .down_ready(down_ready)); 37 | 38 | //-------------------------------------------------------------------------- 39 | // Driving clock 40 | 41 | initial 42 | begin 43 | forever #5 clk = ~ clk; 44 | end 45 | 46 | //-------------------------------------------------------------------------- 47 | //Initialization and driving simulation 48 | initial 49 | begin 50 | clk = 0; 51 | forever @ (posedge clk); 52 | end 53 | 54 | endmodule 55 | -------------------------------------------------------------------------------- /hdl/scenario5/check.sv: -------------------------------------------------------------------------------- 1 | module check #(parameter D_WIDTH = 6) 2 | ( 3 | input [(D_WIDTH-1):0] rtl_data, 4 | input rtl_valid, 5 | input [(D_WIDTH-1):0] model_data 6 | ); 7 | 8 | //This is a BLACKBOX MODULE 9 | //All input ports are not used inside the module because they will be accessed externally from python 10 | //using hierarchical references and used in "post_process_logic_state" call of "check_gadget". 11 | 12 | endmodule 13 | -------------------------------------------------------------------------------- /hdl/scenario5/custom_logic.sv: -------------------------------------------------------------------------------- 1 | module custom_logic #(parameter D_WIDTH = 6) 2 | ( 3 | input clk, 4 | input rst, 5 | input [(D_WIDTH-1):0] up_data, 6 | input up_valid, 7 | output up_ready, 8 | output [(D_WIDTH-1):0] down_data, 9 | output down_valid, 10 | input down_ready 11 | ); 12 | 13 | //Connect signals to the debug vector for visualisation 14 | wire [7:0] debug; 15 | 16 | 17 | //REASSIGN DEBUG SIGNALS AS NEEDED 18 | assign debug[7] = 1'bx; 19 | assign debug[6] = 1'bx; 20 | assign debug[5] = 1'bx; 21 | assign debug[4] = 1'bx; 22 | assign debug[3] = 1'bx; 23 | assign debug[2] = 1'bx; 24 | assign debug[1] = 1'bx; 25 | assign debug[0] = 1'bx; 26 | 27 | 28 | //BEGIN CUSTOM LOGIC BLOCK 29 | 30 | assign down_data = up_data; 31 | assign down_valid = up_valid; 32 | assign up_ready = down_ready; 33 | 34 | //END CUSTOM LOGIC BLOCK 35 | 36 | endmodule 37 | -------------------------------------------------------------------------------- /hdl/scenario5/ff_fifo_pow2_depth.sv: -------------------------------------------------------------------------------- 1 | //---AXI-STREAM FLOP-BASED FIFO WITH DEPTH OF PWR OF 2---// 2 | //Valid/Rready flags generation is based on comparison of write & read counters 3 | //and their MSBs that indicate "Wrap-around", as per Clifford_E_Cummings. 4 | 5 | module ff_fifo_pow2_depth #(parameter D_WIDTH = 6, A_WIDTH = 2) 6 | ( 7 | input clk, 8 | input rst, 9 | input [(D_WIDTH-1):0] up_data, 10 | input up_valid, 11 | output up_ready, 12 | output [(D_WIDTH-1):0] down_data, 13 | output down_valid, 14 | input down_ready 15 | ); 16 | 17 | wire push, pop; 18 | wire empty, full; 19 | wire [(A_WIDTH-1):0] wr_ptr, rd_ptr; 20 | 21 | reg [(A_WIDTH):0] fullwidth_wr_ptr, fullwidth_rd_ptr; 22 | reg [(D_WIDTH-1):0] ram[2**A_WIDTH-1:0]; 23 | 24 | 25 | always @ (posedge clk) 26 | begin 27 | if (push) 28 | ram[wr_ptr] <= up_data; 29 | end 30 | 31 | //WR_COUNTER 32 | always @(posedge clk) 33 | if (rst) begin 34 | fullwidth_wr_ptr <= {(A_WIDTH+1){1'b0}}; 35 | end else if (push) begin 36 | fullwidth_wr_ptr <= fullwidth_wr_ptr + 1; 37 | end 38 | 39 | //RD_COUNTER 40 | always @(posedge clk) 41 | if (rst) begin 42 | fullwidth_rd_ptr <= {(A_WIDTH+1){1'b0}}; 43 | end else if (pop) begin 44 | fullwidth_rd_ptr <= fullwidth_rd_ptr + 1; 45 | end 46 | 47 | //Generate push and pop signals 48 | assign push = up_valid & up_ready; 49 | assign pop = down_valid & down_ready; 50 | 51 | //output LSBits out of full_wr_ptr 52 | assign wr_ptr = fullwidth_wr_ptr[(A_WIDTH-1):0]; 53 | //output LSBits out of full_rd_ptr 54 | assign rd_ptr = fullwidth_rd_ptr[(A_WIDTH-1):0]; 55 | 56 | //"empty" 57 | //It is "1" when MSBits and other bits of "full_rd_ptr" and "full_wr_ptr" are equal 58 | assign empty = ((fullwidth_wr_ptr[(A_WIDTH)] == fullwidth_rd_ptr[(A_WIDTH)]) && 59 | (fullwidth_wr_ptr[(A_WIDTH-1):0] == fullwidth_rd_ptr[(A_WIDTH-1):0])) ? 1'b1 : 1'b0; 60 | //"valid" aka "not_empty" 61 | assign down_valid = ~empty; 62 | 63 | //"full" 64 | //It is "1" when MSBits of "full_rd_ptr" and "full_wr_ptr" are not equal but other bits equal 65 | assign full = ((fullwidth_wr_ptr[(A_WIDTH)] != fullwidth_rd_ptr[(A_WIDTH)]) && 66 | (fullwidth_wr_ptr[(A_WIDTH-1):0] == fullwidth_rd_ptr[(A_WIDTH-1):0])) ? 1'b1 : 1'b0; 67 | //"ready" aka "not_full" 68 | assign up_ready = ~full; 69 | 70 | assign down_data = ram[rd_ptr]; 71 | 72 | endmodule 73 | -------------------------------------------------------------------------------- /hdl/scenario5/model.sv: -------------------------------------------------------------------------------- 1 | //---MODEL---// 2 | 3 | module model #(parameter D_WIDTH = 6) 4 | ( 5 | input clk, 6 | input rst, 7 | input [(D_WIDTH-1):0] up_data, 8 | input push, 9 | output logic [(D_WIDTH-1):0] down_data, 10 | input pop 11 | ); 12 | 13 | // Modeling 14 | int unsigned qsize; 15 | logic [(D_WIDTH-1):0] queue [$]; 16 | logic [(D_WIDTH-1):0] queue0, queue1, queue2; 17 | 18 | ////START OF QUEUE MODEL//// 19 | always @ (posedge clk) 20 | begin 21 | if (rst) 22 | begin 23 | queue = {}; 24 | end 25 | else 26 | ////DO MODELLING HERE//// 27 | begin 28 | if (push) 29 | begin //blocking assignments and function calls can be used between these begin and end 30 | queue.push_back (up_data); 31 | end 32 | if (pop) 33 | begin 34 | if (queue.size () != 0) 35 | begin 36 | queue.delete (0); // queue.delete(0) is used because "queue.pop_front()" method doesn't work in IcarusVerilog 37 | end 38 | end 39 | end 40 | 41 | //The Model doesn't interact with RTL but let's use non-blocking assigments for final model values, 42 | //it is just a good parctice that will help avoid races between RTL and Model 43 | qsize <= queue.size (); 44 | //Cocotb cannot access queue[$] via hierarchical reference but can access queue0, queue1, queue2 with constant indexes 45 | queue0 <= queue [0]; 46 | queue1 <= queue [1]; 47 | queue2 <= queue [2]; 48 | down_data <= queue [0]; 49 | 50 | end 51 | ////END OF QUEUE MODEL//// 52 | 53 | endmodule 54 | -------------------------------------------------------------------------------- /hdl/scenario5/rtl.sv: -------------------------------------------------------------------------------- 1 | //---TOP MODULE FOR RTL DESIGN---// 2 | 3 | module rtl #(parameter D_WIDTH = 6, A_WIDTH = 2) 4 | ( 5 | input clk, 6 | input rst, 7 | input [(D_WIDTH-1):0] up_data, 8 | input up_valid, 9 | output up_ready, 10 | output [(D_WIDTH-1):0] down_data, 11 | output down_valid, 12 | input down_ready 13 | ); 14 | 15 | wire [(D_WIDTH-1):0] w_fifo1_down_data; 16 | wire w_fifo1_down_valid; 17 | wire w_clgk1_up_ready; 18 | wire [(D_WIDTH-1):0] w_clgk1_down_data; 19 | wire w_clgk1_down_valid; 20 | wire w_fifo2_up_ready; 21 | 22 | ff_fifo_pow2_depth # (.D_WIDTH (D_WIDTH), .A_WIDTH (A_WIDTH)) 23 | FIFO1 24 | ( .clk(clk), 25 | .rst(rst), 26 | .up_data(up_data), 27 | .up_valid(up_valid), 28 | .up_ready(up_ready), 29 | .down_data(w_fifo1_down_data), 30 | .down_valid(w_fifo1_down_valid), 31 | .down_ready(w_clgk1_up_ready)); 32 | 33 | custom_logic # (.D_WIDTH (D_WIDTH)) 34 | CLGC1 35 | ( .clk(clk), 36 | .rst(rst), 37 | .up_data(w_fifo1_down_data), 38 | .up_valid(w_fifo1_down_valid), 39 | .up_ready(w_clgk1_up_ready), 40 | .down_data(w_clgk1_down_data), 41 | .down_valid(w_clgk1_down_valid), 42 | .down_ready(w_fifo2_up_ready)); 43 | 44 | ff_fifo_pow2_depth # (.D_WIDTH (D_WIDTH), .A_WIDTH (A_WIDTH)) 45 | FIFO2 46 | ( .clk(clk), 47 | .rst(rst), 48 | .up_data(w_clgk1_down_data), 49 | .up_valid(w_clgk1_down_valid), 50 | .up_ready(w_fifo2_up_ready), 51 | .down_data(down_data), 52 | .down_valid(down_valid), 53 | .down_ready(down_ready)); 54 | 55 | endmodule 56 | -------------------------------------------------------------------------------- /hdl/scenario5/tb.sv: -------------------------------------------------------------------------------- 1 | module tb 2 | # ( 3 | parameter D_WIDTH = 6, A_WIDTH = 2 4 | ); 5 | 6 | //-------------------------------------------------------------------------- 7 | // Signals to drive Device Under Test - DUT 8 | 9 | logic clk; 10 | wire rst; 11 | 12 | // Upstream 13 | 14 | wire up_valid; 15 | wire up_ready; 16 | wire [(D_WIDTH-1):0] up_data; 17 | 18 | // Downstream 19 | 20 | wire down_valid; 21 | wire down_ready; 22 | wire [(D_WIDTH-1):0] down_data; 23 | 24 | // Model 25 | 26 | wire [(D_WIDTH-1):0] model_data; 27 | 28 | //-------------------------------------------------------------------------- 29 | // DUT instantiation 30 | 31 | rtl # (.D_WIDTH (D_WIDTH), .A_WIDTH (A_WIDTH)) 32 | RTL1 33 | ( .clk(clk), 34 | .rst(rst), 35 | .up_data(up_data), 36 | .up_valid(up_valid), 37 | .up_ready(up_ready), 38 | .down_data(down_data), 39 | .down_valid(down_valid), 40 | .down_ready(down_ready)); 41 | 42 | //-------------------------------------------------------------------------- 43 | // MODEL instantiation 44 | 45 | wire push; 46 | wire pop; 47 | 48 | assign push = up_valid & up_ready; 49 | assign pop = down_valid & down_ready; 50 | 51 | model # (.D_WIDTH (D_WIDTH)) 52 | MDL1 53 | ( .clk(clk), 54 | .rst(rst), 55 | .up_data(up_data), 56 | .push(push), 57 | .down_data(model_data), 58 | .pop(pop)); 59 | 60 | //-------------------------------------------------------------------------- 61 | // CHECKING module instantiation 62 | 63 | check # (.D_WIDTH (D_WIDTH)) 64 | CHK1 65 | ( 66 | .rtl_data(down_data), 67 | .rtl_valid(down_valid), 68 | .model_data(model_data)); 69 | 70 | //-------------------------------------------------------------------------- 71 | // Driving clock 72 | 73 | initial 74 | begin 75 | forever #5 clk = ~ clk; 76 | end 77 | 78 | //-------------------------------------------------------------------------- 79 | //Initialization and driving simulation 80 | initial 81 | begin 82 | clk = 0; 83 | forever @ (posedge clk); 84 | end 85 | 86 | endmodule 87 | -------------------------------------------------------------------------------- /hdl/scenario6/check.sv: -------------------------------------------------------------------------------- 1 | module check #(parameter D_WIDTH = 6) 2 | ( 3 | input [(D_WIDTH-1):0] rtl_data, 4 | input rtl_valid, 5 | input [(D_WIDTH-1):0] model_data 6 | ); 7 | 8 | //This is a BLACKBOX MODULE 9 | //All input ports are not used inside the module because they will be accessed externally from python 10 | //using hierarchical references and used in "post_process_logic_state" call of "check_gadget". 11 | 12 | endmodule 13 | -------------------------------------------------------------------------------- /hdl/scenario6/ff_fifo_pow2_depth.sv: -------------------------------------------------------------------------------- 1 | //---AXI-STREAM FLOP-BASED FIFO WITH DEPTH OF PWR OF 2---// 2 | //Valid/Rready flags generation is based on comparison of write & read counters 3 | //and their MSBs that indicate "Wrap-around", as per Clifford_E_Cummings. 4 | 5 | module ff_fifo_pow2_depth #(parameter D_WIDTH = 6, A_WIDTH = 2) 6 | ( 7 | input clk, 8 | input rst, 9 | input [(D_WIDTH-1):0] up_data, 10 | input up_valid, 11 | output up_ready, 12 | output [(D_WIDTH-1):0] down_data, 13 | output down_valid, 14 | input down_ready 15 | ); 16 | 17 | wire push, pop; 18 | wire empty, full; 19 | wire [(A_WIDTH-1):0] wr_ptr, rd_ptr; 20 | 21 | reg [(A_WIDTH):0] fullwidth_wr_ptr, fullwidth_rd_ptr; 22 | reg [(D_WIDTH-1):0] ram[2**A_WIDTH-1:0]; 23 | 24 | 25 | always @ (posedge clk) 26 | begin 27 | if (push) 28 | ram[wr_ptr] <= up_data; 29 | end 30 | 31 | //WR_COUNTER 32 | always @(posedge clk) 33 | if (rst) begin 34 | fullwidth_wr_ptr <= {(A_WIDTH+1){1'b0}}; 35 | end else if (push) begin 36 | fullwidth_wr_ptr <= fullwidth_wr_ptr + 1; 37 | end 38 | 39 | //RD_COUNTER 40 | always @(posedge clk) 41 | if (rst) begin 42 | fullwidth_rd_ptr <= {(A_WIDTH+1){1'b0}}; 43 | end else if (pop) begin 44 | fullwidth_rd_ptr <= fullwidth_rd_ptr + 1; 45 | end 46 | 47 | //Generate push and pop signals 48 | assign push = up_valid & up_ready; 49 | assign pop = down_valid & down_ready; 50 | 51 | //output LSBits out of full_wr_ptr 52 | assign wr_ptr = fullwidth_wr_ptr[(A_WIDTH-1):0]; 53 | //output LSBits out of full_rd_ptr 54 | assign rd_ptr = fullwidth_rd_ptr[(A_WIDTH-1):0]; 55 | 56 | //"empty" 57 | //It is "1" when MSBits and other bits of "full_rd_ptr" and "full_wr_ptr" are equal 58 | assign empty = ((fullwidth_wr_ptr[(A_WIDTH)] == fullwidth_rd_ptr[(A_WIDTH)]) && 59 | (fullwidth_wr_ptr[(A_WIDTH-1):0] == fullwidth_rd_ptr[(A_WIDTH-1):0])) ? 1'b1 : 1'b0; 60 | //"valid" aka "not_empty" 61 | assign down_valid = ~empty; 62 | 63 | //"full" 64 | //It is "1" when MSBits of "full_rd_ptr" and "full_wr_ptr" are not equal but other bits equal 65 | assign full = ((fullwidth_wr_ptr[(A_WIDTH)] != fullwidth_rd_ptr[(A_WIDTH)]) && 66 | (fullwidth_wr_ptr[(A_WIDTH-1):0] == fullwidth_rd_ptr[(A_WIDTH-1):0])) ? 1'b1 : 1'b0; 67 | //"ready" aka "not_full" 68 | assign up_ready = ~full; 69 | 70 | assign down_data = ram[rd_ptr]; 71 | 72 | endmodule 73 | -------------------------------------------------------------------------------- /hdl/scenario6/model.sv: -------------------------------------------------------------------------------- 1 | //---MODEL---// 2 | 3 | module model #(parameter D_WIDTH = 6) 4 | ( 5 | input clk, 6 | input rst, 7 | input [(D_WIDTH-1):0] up_data, 8 | input push, 9 | output logic [(D_WIDTH-1):0] down_data, 10 | input pop 11 | ); 12 | 13 | // Modeling 14 | int unsigned qsize; 15 | logic [(D_WIDTH-1):0] queue [$]; 16 | logic [(D_WIDTH-1):0] queue0, queue1, queue2; 17 | 18 | ////START OF QUEUE MODEL//// 19 | always @ (posedge clk) 20 | begin 21 | if (rst) 22 | begin 23 | queue = {}; 24 | end 25 | else 26 | ////DO MODELLING HERE//// 27 | begin 28 | if (push) 29 | begin //blocking assignments and function calls can be used between these begin and end 30 | queue.push_back (up_data); 31 | end 32 | if (pop) 33 | begin 34 | if (queue.size () != 0) 35 | begin 36 | queue.delete (0); // queue.delete(0) is used because "queue.pop_front()" method doesn't work in IcarusVerilog 37 | end 38 | end 39 | end 40 | 41 | //The Model doesn't interact with RTL but let's use non-blocking assigments for final model values, 42 | //it is just a good parctice that will help avoid races between RTL and Model 43 | qsize <= queue.size (); 44 | //Cocotb cannot access queue[$] via hierarchical reference but can access queue0, queue1, queue2 with constant indexes 45 | queue0 <= queue [0]; 46 | queue1 <= queue [1]; 47 | queue2 <= queue [2]; 48 | down_data <= queue [0]; 49 | 50 | end 51 | ////END OF QUEUE MODEL//// 52 | 53 | endmodule 54 | -------------------------------------------------------------------------------- /hdl/scenario6/rtl.sv: -------------------------------------------------------------------------------- 1 | //---TOP MODULE FOR RTL DESIGN---// 2 | 3 | module rtl #(parameter D_WIDTH = 6, A_WIDTH = 2) 4 | ( 5 | input clk, 6 | input rst, 7 | input [(D_WIDTH-1):0] up_data, 8 | input up_valid, 9 | output up_ready, 10 | output [(D_WIDTH-1):0] down_data, 11 | output down_valid, 12 | input down_ready 13 | ); 14 | 15 | wire [(D_WIDTH-1):0] w_fifo1_down_data; 16 | wire w_fifo1_down_valid; 17 | wire w_fifo2_up_ready; 18 | 19 | ff_fifo_pow2_depth # (.D_WIDTH (D_WIDTH), .A_WIDTH (A_WIDTH)) 20 | FIFO1 21 | ( .clk(clk), 22 | .rst(rst), 23 | .up_data(up_data), 24 | .up_valid(up_valid), 25 | .up_ready(up_ready), 26 | .down_data(w_fifo1_down_data), 27 | .down_valid(w_fifo1_down_valid), 28 | .down_ready(w_fifo2_up_ready)); 29 | 30 | ff_fifo_pow2_depth # (.D_WIDTH (D_WIDTH), .A_WIDTH (A_WIDTH)) 31 | FIFO2 32 | ( .clk(clk), 33 | .rst(rst), 34 | .up_data(w_fifo1_down_data), 35 | .up_valid(w_fifo1_down_valid), 36 | .up_ready(w_fifo2_up_ready), 37 | .down_data(down_data), 38 | .down_valid(down_valid), 39 | .down_ready(down_ready)); 40 | 41 | endmodule 42 | -------------------------------------------------------------------------------- /hdl/scenario6/tb.sv: -------------------------------------------------------------------------------- 1 | module tb 2 | # ( 3 | parameter D_WIDTH = 6, A_WIDTH = 2 4 | ); 5 | 6 | //-------------------------------------------------------------------------- 7 | // Signals to drive Device Under Test - DUT 8 | 9 | logic clk; 10 | wire rst; 11 | 12 | // Upstream 13 | 14 | wire up_valid; 15 | wire up_ready; 16 | wire [(D_WIDTH-1):0] up_data; 17 | 18 | // Downstream 19 | 20 | wire down_valid; 21 | wire down_ready; 22 | wire [(D_WIDTH-1):0] down_data; 23 | 24 | // Model 25 | 26 | wire [(D_WIDTH-1):0] model_data; 27 | 28 | //-------------------------------------------------------------------------- 29 | // DUT instantiation 30 | 31 | rtl # (.D_WIDTH (D_WIDTH), .A_WIDTH (A_WIDTH)) 32 | RTL1 33 | ( .clk(clk), 34 | .rst(rst), 35 | .up_data(up_data), 36 | .up_valid(up_valid), 37 | .up_ready(up_ready), 38 | .down_data(down_data), 39 | .down_valid(down_valid), 40 | .down_ready(down_ready)); 41 | 42 | //-------------------------------------------------------------------------- 43 | // MODEL instantiation 44 | 45 | wire push; 46 | wire pop; 47 | 48 | assign push = up_valid & up_ready; 49 | assign pop = down_valid & down_ready; 50 | 51 | model # (.D_WIDTH (D_WIDTH)) 52 | MDL1 53 | ( .clk(clk), 54 | .rst(rst), 55 | .up_data(up_data), 56 | .push(push), 57 | .down_data(model_data), 58 | .pop(pop)); 59 | 60 | //-------------------------------------------------------------------------- 61 | // CHECKING module instantiation 62 | 63 | check # (.D_WIDTH (D_WIDTH)) 64 | CHK1 65 | ( 66 | .rtl_data(down_data), 67 | .rtl_valid(down_valid), 68 | .model_data(model_data)); 69 | 70 | //-------------------------------------------------------------------------- 71 | // Driving clock 72 | 73 | initial 74 | begin 75 | forever #5 clk = ~ clk; 76 | end 77 | 78 | //-------------------------------------------------------------------------- 79 | //Initialization and driving simulation 80 | initial 81 | begin 82 | clk = 0; 83 | forever @ (posedge clk); 84 | end 85 | 86 | endmodule 87 | -------------------------------------------------------------------------------- /hdl/scenario7/custom_logic_fork.sv: -------------------------------------------------------------------------------- 1 | module custom_logic_fork #(parameter D_WIDTH = 6) 2 | ( 3 | input clk, 4 | input rst, 5 | input [(D_WIDTH-1):0] up_data, 6 | input up_valid, 7 | output up_ready, 8 | output [(D_WIDTH-1):0] down_data_a, 9 | output down_valid_a, 10 | input down_ready_a, 11 | output [(D_WIDTH-1):0] down_data_b, 12 | output down_valid_b, 13 | input down_ready_b 14 | ); 15 | 16 | //Connect signals to the debug vector for visualisation 17 | wire [7:0] debug; 18 | 19 | 20 | //REASSIGN DEBUG SIGNALS AS NEEDED 21 | assign debug[7] = 1'bx; 22 | assign debug[6] = 1'bx; 23 | assign debug[5] = 1'bx; 24 | assign debug[4] = 1'bx; 25 | assign debug[3] = 1'bx; 26 | assign debug[2] = 1'bx; 27 | assign debug[1] = 1'bx; 28 | assign debug[0] = 1'bx; 29 | 30 | 31 | //BEGIN CUSTOM LOGIC BLOCK 32 | 33 | assign down_data_a = up_data; 34 | assign down_data_b = up_data; 35 | assign down_valid_a = up_valid & down_ready_a & down_ready_b; 36 | assign down_valid_b = up_valid & down_ready_a & down_ready_b; 37 | assign up_ready = down_ready_a & down_ready_b; 38 | 39 | //END CUSTOM LOGIC BLOCK 40 | 41 | endmodule 42 | -------------------------------------------------------------------------------- /hdl/scenario7/ff_fifo_pow2_depth.sv: -------------------------------------------------------------------------------- 1 | //---AXI-STREAM FLOP-BASED FIFO WITH DEPTH OF PWR OF 2---// 2 | //Valid/Rready flags generation is based on comparison of write & read counters 3 | //and their MSBs that indicate "Wrap-around", as per Clifford_E_Cummings. 4 | 5 | module ff_fifo_pow2_depth #(parameter D_WIDTH = 6, A_WIDTH = 2) 6 | ( 7 | input clk, 8 | input rst, 9 | input [(D_WIDTH-1):0] up_data, 10 | input up_valid, 11 | output up_ready, 12 | output [(D_WIDTH-1):0] down_data, 13 | output down_valid, 14 | input down_ready 15 | ); 16 | 17 | wire push, pop; 18 | wire empty, full; 19 | wire [(A_WIDTH-1):0] wr_ptr, rd_ptr; 20 | 21 | reg [(A_WIDTH):0] fullwidth_wr_ptr, fullwidth_rd_ptr; 22 | reg [(D_WIDTH-1):0] ram[2**A_WIDTH-1:0]; 23 | 24 | 25 | always @ (posedge clk) 26 | begin 27 | if (push) 28 | ram[wr_ptr] <= up_data; 29 | end 30 | 31 | //WR_COUNTER 32 | always @(posedge clk) 33 | if (rst) begin 34 | fullwidth_wr_ptr <= {(A_WIDTH+1){1'b0}}; 35 | end else if (push) begin 36 | fullwidth_wr_ptr <= fullwidth_wr_ptr + 1; 37 | end 38 | 39 | //RD_COUNTER 40 | always @(posedge clk) 41 | if (rst) begin 42 | fullwidth_rd_ptr <= {(A_WIDTH+1){1'b0}}; 43 | end else if (pop) begin 44 | fullwidth_rd_ptr <= fullwidth_rd_ptr + 1; 45 | end 46 | 47 | //Generate push and pop signals 48 | assign push = up_valid & up_ready; 49 | assign pop = down_valid & down_ready; 50 | 51 | //output LSBits out of full_wr_ptr 52 | assign wr_ptr = fullwidth_wr_ptr[(A_WIDTH-1):0]; 53 | //output LSBits out of full_rd_ptr 54 | assign rd_ptr = fullwidth_rd_ptr[(A_WIDTH-1):0]; 55 | 56 | //"empty" 57 | //It is "1" when MSBits and other bits of "full_rd_ptr" and "full_wr_ptr" are equal 58 | assign empty = ((fullwidth_wr_ptr[(A_WIDTH)] == fullwidth_rd_ptr[(A_WIDTH)]) && 59 | (fullwidth_wr_ptr[(A_WIDTH-1):0] == fullwidth_rd_ptr[(A_WIDTH-1):0])) ? 1'b1 : 1'b0; 60 | //"valid" aka "not_empty" 61 | assign down_valid = ~empty; 62 | 63 | //"full" 64 | //It is "1" when MSBits of "full_rd_ptr" and "full_wr_ptr" are not equal but other bits equal 65 | assign full = ((fullwidth_wr_ptr[(A_WIDTH)] != fullwidth_rd_ptr[(A_WIDTH)]) && 66 | (fullwidth_wr_ptr[(A_WIDTH-1):0] == fullwidth_rd_ptr[(A_WIDTH-1):0])) ? 1'b1 : 1'b0; 67 | //"ready" aka "not_full" 68 | assign up_ready = ~full; 69 | 70 | assign down_data = ram[rd_ptr]; 71 | 72 | endmodule 73 | -------------------------------------------------------------------------------- /hdl/scenario7/rtl.sv: -------------------------------------------------------------------------------- 1 | //---TOP MODULE FOR RTL DESIGN---// 2 | 3 | module rtl #(parameter D_WIDTH = 6, A_WIDTH = 2) 4 | ( 5 | input clk, 6 | input rst, 7 | input [(D_WIDTH-1):0] up_data, 8 | input up_valid, 9 | output up_ready, 10 | output [(D_WIDTH-1):0] down_data_a, 11 | output down_valid_a, 12 | input down_ready_a, 13 | output [(D_WIDTH-1):0] down_data_b, 14 | output down_valid_b, 15 | input down_ready_b 16 | ); 17 | 18 | wire [(D_WIDTH-1):0] w_fifo1_down_data; 19 | wire w_fifo1_down_valid; 20 | wire w_clgk1_up_ready; 21 | wire [(D_WIDTH-1):0] w_clgk1_down_data_a; 22 | wire w_clgk1_down_valid_a; 23 | wire w_fifo2_up_ready; 24 | wire [(D_WIDTH-1):0] w_clgk1_down_data_b; 25 | wire w_clgk1_down_valid_b; 26 | wire w_fifo3_up_ready; 27 | 28 | ff_fifo_pow2_depth # (.D_WIDTH (D_WIDTH), .A_WIDTH (A_WIDTH)) 29 | FIFO1 30 | ( .clk(clk), 31 | .rst(rst), 32 | .up_data(up_data), 33 | .up_valid(up_valid), 34 | .up_ready(up_ready), 35 | .down_data(w_fifo1_down_data), 36 | .down_valid(w_fifo1_down_valid), 37 | .down_ready(w_clgk1_up_ready)); 38 | 39 | custom_logic_fork # (.D_WIDTH (D_WIDTH)) 40 | CLGC1 41 | ( .clk(clk), 42 | .rst(rst), 43 | .up_data(w_fifo1_down_data), 44 | .up_valid(w_fifo1_down_valid), 45 | .up_ready(w_clgk1_up_ready), 46 | .down_data_a(w_clgk1_down_data_a), 47 | .down_valid_a(w_clgk1_down_valid_a), 48 | .down_ready_a(w_fifo2_up_ready), 49 | .down_data_b(w_clgk1_down_data_b), 50 | .down_valid_b(w_clgk1_down_valid_b), 51 | .down_ready_b(w_fifo3_up_ready)); 52 | 53 | ff_fifo_pow2_depth # (.D_WIDTH (D_WIDTH), .A_WIDTH (A_WIDTH)) 54 | FIFO2 55 | ( .clk(clk), 56 | .rst(rst), 57 | .up_data(w_clgk1_down_data_a), 58 | .up_valid(w_clgk1_down_valid_a), 59 | .up_ready(w_fifo2_up_ready), 60 | .down_data(down_data_a), 61 | .down_valid(down_valid_a), 62 | .down_ready(down_ready_a)); 63 | 64 | ff_fifo_pow2_depth # (.D_WIDTH (D_WIDTH), .A_WIDTH (A_WIDTH)) 65 | FIFO3 66 | ( .clk(clk), 67 | .rst(rst), 68 | .up_data(w_clgk1_down_data_b), 69 | .up_valid(w_clgk1_down_valid_b), 70 | .up_ready(w_fifo3_up_ready), 71 | .down_data(down_data_b), 72 | .down_valid(down_valid_b), 73 | .down_ready(down_ready_b)); 74 | 75 | endmodule 76 | -------------------------------------------------------------------------------- /hdl/scenario7/tb.sv: -------------------------------------------------------------------------------- 1 | module tb 2 | # ( 3 | parameter D_WIDTH = 6, A_WIDTH = 2 4 | ); 5 | 6 | //-------------------------------------------------------------------------- 7 | // Signals to drive Device Under Test - DUT 8 | 9 | logic clk; 10 | wire rst; 11 | 12 | // Upstream 13 | 14 | wire up_valid; 15 | wire up_ready; 16 | wire [(D_WIDTH-1):0] up_data; 17 | 18 | // Downstream 19 | 20 | wire down_valid_a; 21 | wire down_ready_a; 22 | wire [(D_WIDTH-1):0] down_data_a; 23 | 24 | wire down_valid_b; 25 | wire down_ready_b; 26 | wire [(D_WIDTH-1):0] down_data_b; 27 | 28 | //-------------------------------------------------------------------------- 29 | // DUT instantiation 30 | 31 | rtl # (.D_WIDTH (D_WIDTH), .A_WIDTH (A_WIDTH)) 32 | RTL1 33 | ( .clk(clk), 34 | .rst(rst), 35 | .up_data(up_data), 36 | .up_valid(up_valid), 37 | .up_ready(up_ready), 38 | .down_data_a(down_data_a), 39 | .down_valid_a(down_valid_a), 40 | .down_ready_a(down_ready_a), 41 | .down_data_b(down_data_b), 42 | .down_valid_b(down_valid_b), 43 | .down_ready_b(down_ready_b)); 44 | 45 | //-------------------------------------------------------------------------- 46 | // Driving clock 47 | 48 | initial 49 | begin 50 | forever #5 clk = ~ clk; 51 | end 52 | 53 | //-------------------------------------------------------------------------- 54 | //Initialization and driving simulation 55 | initial 56 | begin 57 | clk = 0; 58 | forever @ (posedge clk); 59 | end 60 | 61 | endmodule 62 | -------------------------------------------------------------------------------- /hdl/scenario8/check.sv: -------------------------------------------------------------------------------- 1 | module check #(parameter D_WIDTH = 6) 2 | ( 3 | input [(D_WIDTH-1):0] rtl_data, 4 | input rtl_valid, 5 | input [(D_WIDTH-1):0] model_data 6 | ); 7 | 8 | //This is a BLACKBOX MODULE 9 | //All input ports are not used inside the module because they will be accessed externally from python 10 | //using hierarchical references and used in "post_process_logic_state" call of "check_gadget". 11 | 12 | endmodule 13 | -------------------------------------------------------------------------------- /hdl/scenario8/custom_logic_fork.sv: -------------------------------------------------------------------------------- 1 | module custom_logic_fork #(parameter D_WIDTH = 6) 2 | ( 3 | input clk, 4 | input rst, 5 | input [(D_WIDTH-1):0] up_data, 6 | input up_valid, 7 | output up_ready, 8 | output [(D_WIDTH-1):0] down_data_a, 9 | output down_valid_a, 10 | input down_ready_a, 11 | output [(D_WIDTH-1):0] down_data_b, 12 | output down_valid_b, 13 | input down_ready_b 14 | ); 15 | 16 | //Connect signals to the debug vector for visualisation 17 | wire [7:0] debug; 18 | 19 | 20 | //REASSIGN DEBUG SIGNALS AS NEEDED 21 | assign debug[7] = 1'bx; 22 | assign debug[6] = 1'bx; 23 | assign debug[5] = 1'bx; 24 | assign debug[4] = 1'bx; 25 | assign debug[3] = 1'bx; 26 | assign debug[2] = 1'bx; 27 | assign debug[1] = 1'bx; 28 | assign debug[0] = 1'bx; 29 | 30 | 31 | //BEGIN CUSTOM LOGIC BLOCK 32 | 33 | assign down_data_a = up_data; 34 | assign down_data_b = up_data; 35 | assign down_valid_a = up_valid & down_ready_a & down_ready_b; 36 | assign down_valid_b = up_valid & down_ready_a & down_ready_b; 37 | assign up_ready = down_ready_a & down_ready_b; 38 | 39 | //END CUSTOM LOGIC BLOCK 40 | 41 | endmodule 42 | -------------------------------------------------------------------------------- /hdl/scenario8/ff_fifo_pow2_depth.sv: -------------------------------------------------------------------------------- 1 | //---AXI-STREAM FLOP-BASED FIFO WITH DEPTH OF PWR OF 2---// 2 | //Valid/Rready flags generation is based on comparison of write & read counters 3 | //and their MSBs that indicate "Wrap-around", as per Clifford_E_Cummings. 4 | 5 | module ff_fifo_pow2_depth #(parameter D_WIDTH = 6, A_WIDTH = 2) 6 | ( 7 | input clk, 8 | input rst, 9 | input [(D_WIDTH-1):0] up_data, 10 | input up_valid, 11 | output up_ready, 12 | output [(D_WIDTH-1):0] down_data, 13 | output down_valid, 14 | input down_ready 15 | ); 16 | 17 | wire push, pop; 18 | wire empty, full; 19 | wire [(A_WIDTH-1):0] wr_ptr, rd_ptr; 20 | 21 | reg [(A_WIDTH):0] fullwidth_wr_ptr, fullwidth_rd_ptr; 22 | reg [(D_WIDTH-1):0] ram[2**A_WIDTH-1:0]; 23 | 24 | 25 | always @ (posedge clk) 26 | begin 27 | if (push) 28 | ram[wr_ptr] <= up_data; 29 | end 30 | 31 | //WR_COUNTER 32 | always @(posedge clk) 33 | if (rst) begin 34 | fullwidth_wr_ptr <= {(A_WIDTH+1){1'b0}}; 35 | end else if (push) begin 36 | fullwidth_wr_ptr <= fullwidth_wr_ptr + 1; 37 | end 38 | 39 | //RD_COUNTER 40 | always @(posedge clk) 41 | if (rst) begin 42 | fullwidth_rd_ptr <= {(A_WIDTH+1){1'b0}}; 43 | end else if (pop) begin 44 | fullwidth_rd_ptr <= fullwidth_rd_ptr + 1; 45 | end 46 | 47 | //Generate push and pop signals 48 | assign push = up_valid & up_ready; 49 | assign pop = down_valid & down_ready; 50 | 51 | //output LSBits out of full_wr_ptr 52 | assign wr_ptr = fullwidth_wr_ptr[(A_WIDTH-1):0]; 53 | //output LSBits out of full_rd_ptr 54 | assign rd_ptr = fullwidth_rd_ptr[(A_WIDTH-1):0]; 55 | 56 | //"empty" 57 | //It is "1" when MSBits and other bits of "full_rd_ptr" and "full_wr_ptr" are equal 58 | assign empty = ((fullwidth_wr_ptr[(A_WIDTH)] == fullwidth_rd_ptr[(A_WIDTH)]) && 59 | (fullwidth_wr_ptr[(A_WIDTH-1):0] == fullwidth_rd_ptr[(A_WIDTH-1):0])) ? 1'b1 : 1'b0; 60 | //"valid" aka "not_empty" 61 | assign down_valid = ~empty; 62 | 63 | //"full" 64 | //It is "1" when MSBits of "full_rd_ptr" and "full_wr_ptr" are not equal but other bits equal 65 | assign full = ((fullwidth_wr_ptr[(A_WIDTH)] != fullwidth_rd_ptr[(A_WIDTH)]) && 66 | (fullwidth_wr_ptr[(A_WIDTH-1):0] == fullwidth_rd_ptr[(A_WIDTH-1):0])) ? 1'b1 : 1'b0; 67 | //"ready" aka "not_full" 68 | assign up_ready = ~full; 69 | 70 | assign down_data = ram[rd_ptr]; 71 | 72 | endmodule 73 | -------------------------------------------------------------------------------- /hdl/scenario8/model.sv: -------------------------------------------------------------------------------- 1 | //---MODEL---// 2 | 3 | module model #(parameter D_WIDTH = 6) 4 | ( 5 | input clk, 6 | input rst, 7 | input [(D_WIDTH-1):0] up_data, 8 | input push, 9 | output logic [(D_WIDTH-1):0] down_data_a, 10 | output logic [(D_WIDTH-1):0] down_data_b, 11 | input pop_a, 12 | input pop_b 13 | ); 14 | 15 | // Modeling 16 | int unsigned qsize_a, qsize_b; 17 | logic [(D_WIDTH-1):0] queue_a [$], queue_b [$]; 18 | logic [(D_WIDTH-1):0] queue0_a, queue1_a, queue2_a, queue0_b, queue1_b, queue2_b; 19 | 20 | ////START OF QUEUE MODEL//// 21 | always @ (posedge clk) 22 | begin 23 | if (rst) 24 | begin 25 | queue_a = {}; 26 | queue_b = {}; 27 | end 28 | else 29 | ////DO MODELLING HERE//// 30 | begin 31 | if (push) 32 | begin //blocking assignments and function calls can be used between these begin and end 33 | queue_a.push_back (up_data); 34 | queue_b.push_back (up_data); 35 | end 36 | if (pop_a) 37 | begin 38 | if (queue_a.size () != 0) 39 | begin 40 | queue_a.delete (0); // queue.delete(0) is used because "queue.pop_front()" method doesn't work in IcarusVerilog 41 | end 42 | end 43 | if (pop_b) 44 | begin 45 | if (queue_b.size () != 0) 46 | begin 47 | queue_b.delete (0); // queue.delete(0) is used because "queue.pop_front()" method doesn't work in IcarusVerilog 48 | end 49 | end 50 | end 51 | 52 | //The Model doesn't interact with RTL but let's use non-blocking assigments for final model values, 53 | //it is just a good parctice that will help avoid races between RTL and Model 54 | qsize_a <= queue_a.size (); 55 | qsize_b <= queue_b.size (); 56 | //Cocotb cannot access queue[$] via hierarchical reference but can access queue0, queue1, queue2 with constant indexes 57 | queue0_a <= queue_a [0]; 58 | queue1_a <= queue_a [1]; 59 | queue2_a <= queue_a [2]; 60 | down_data_a <= queue_a [0]; 61 | queue0_b <= queue_b [0]; 62 | queue1_b <= queue_b [1]; 63 | queue2_b <= queue_b [2]; 64 | down_data_b <= queue_b [0]; 65 | 66 | end 67 | ////END OF QUEUE MODEL//// 68 | 69 | endmodule 70 | -------------------------------------------------------------------------------- /hdl/scenario8/rtl.sv: -------------------------------------------------------------------------------- 1 | //---TOP MODULE FOR RTL DESIGN---// 2 | 3 | module rtl #(parameter D_WIDTH = 6, parameter A_WIDTH = 2) 4 | ( 5 | input clk, 6 | input rst, 7 | input [(D_WIDTH-1):0] up_data, 8 | input up_valid, 9 | output up_ready, 10 | output [(D_WIDTH-1):0] down_data_a, 11 | output down_valid_a, 12 | input down_ready_a, 13 | output [(D_WIDTH-1):0] down_data_b, 14 | output down_valid_b, 15 | input down_ready_b 16 | ); 17 | 18 | wire [(D_WIDTH-1):0] w_fifo1_down_data; 19 | wire w_fifo1_down_valid; 20 | wire w_clgk1_up_ready; 21 | wire [(D_WIDTH-1):0] w_clgk1_down_data_a; 22 | wire w_clgk1_down_valid_a; 23 | wire w_fifo2_up_ready; 24 | wire [(D_WIDTH-1):0] w_clgk1_down_data_b; 25 | wire w_clgk1_down_valid_b; 26 | wire w_fifo3_up_ready; 27 | 28 | ff_fifo_pow2_depth # (.D_WIDTH (D_WIDTH), .A_WIDTH (A_WIDTH)) 29 | FIFO1 30 | ( .clk(clk), 31 | .rst(rst), 32 | .up_data(up_data), 33 | .up_valid(up_valid), 34 | .up_ready(up_ready), 35 | .down_data(w_fifo1_down_data), 36 | .down_valid(w_fifo1_down_valid), 37 | .down_ready(w_clgk1_up_ready)); 38 | 39 | custom_logic_fork # (.D_WIDTH (D_WIDTH)) 40 | CLGC1 41 | ( .clk(clk), 42 | .rst(rst), 43 | .up_data(w_fifo1_down_data), 44 | .up_valid(w_fifo1_down_valid), 45 | .up_ready(w_clgk1_up_ready), 46 | .down_data_a(w_clgk1_down_data_a), 47 | .down_valid_a(w_clgk1_down_valid_a), 48 | .down_ready_a(w_fifo2_up_ready), 49 | .down_data_b(w_clgk1_down_data_b), 50 | .down_valid_b(w_clgk1_down_valid_b), 51 | .down_ready_b(w_fifo3_up_ready)); 52 | 53 | ff_fifo_pow2_depth # (.D_WIDTH (D_WIDTH), .A_WIDTH (A_WIDTH)) 54 | FIFO2 55 | ( .clk(clk), 56 | .rst(rst), 57 | .up_data(w_clgk1_down_data_a), 58 | .up_valid(w_clgk1_down_valid_a), 59 | .up_ready(w_fifo2_up_ready), 60 | .down_data(down_data_a), 61 | .down_valid(down_valid_a), 62 | .down_ready(down_ready_a)); 63 | 64 | ff_fifo_pow2_depth # (.D_WIDTH (D_WIDTH), .A_WIDTH (A_WIDTH)) 65 | FIFO3 66 | ( .clk(clk), 67 | .rst(rst), 68 | .up_data(w_clgk1_down_data_b), 69 | .up_valid(w_clgk1_down_valid_b), 70 | .up_ready(w_fifo3_up_ready), 71 | .down_data(down_data_b), 72 | .down_valid(down_valid_b), 73 | .down_ready(down_ready_b)); 74 | 75 | endmodule 76 | -------------------------------------------------------------------------------- /hdl/scenario8/tb.sv: -------------------------------------------------------------------------------- 1 | module tb 2 | # ( 3 | parameter D_WIDTH = 6, A_WIDTH = 2 4 | ); 5 | 6 | //-------------------------------------------------------------------------- 7 | // Signals to drive Device Under Test - DUT 8 | 9 | logic clk; 10 | wire rst; 11 | 12 | // Upstream 13 | 14 | wire up_valid; 15 | wire up_ready; 16 | wire [(D_WIDTH-1):0] up_data; 17 | 18 | // Downstream 19 | 20 | wire down_valid_a; 21 | wire down_ready_a; 22 | wire [(D_WIDTH-1):0] down_data_a; 23 | 24 | wire down_valid_b; 25 | wire down_ready_b; 26 | wire [(D_WIDTH-1):0] down_data_b; 27 | 28 | // Model 29 | 30 | wire [(D_WIDTH-1):0] model_data_a; 31 | wire [(D_WIDTH-1):0] model_data_b; 32 | 33 | //-------------------------------------------------------------------------- 34 | // DUT instantiation 35 | 36 | rtl # (.D_WIDTH (D_WIDTH), .A_WIDTH (A_WIDTH)) 37 | RTL1 38 | ( .clk(clk), 39 | .rst(rst), 40 | .up_data(up_data), 41 | .up_valid(up_valid), 42 | .up_ready(up_ready), 43 | .down_data_a(down_data_a), 44 | .down_valid_a(down_valid_a), 45 | .down_ready_a(down_ready_a), 46 | .down_data_b(down_data_b), 47 | .down_valid_b(down_valid_b), 48 | .down_ready_b(down_ready_b)); 49 | 50 | //-------------------------------------------------------------------------- 51 | // MODEL instantiation 52 | 53 | wire push; 54 | wire pop_a; 55 | wire pop_b; 56 | 57 | assign push = up_valid & up_ready; 58 | assign pop_a = down_valid_a & down_ready_a; 59 | assign pop_b = down_valid_b & down_ready_b; 60 | 61 | model # (.D_WIDTH (D_WIDTH)) 62 | MDL1 63 | ( .clk(clk), 64 | .rst(rst), 65 | .up_data(up_data), 66 | .push(push), 67 | .down_data_a(model_data_a), 68 | .down_data_b(model_data_b), 69 | .pop_a(pop_a), 70 | .pop_b(pop_b)); 71 | 72 | //-------------------------------------------------------------------------- 73 | // CHECKING modules instantiation 74 | 75 | check # (.D_WIDTH (D_WIDTH)) 76 | CHK1 77 | ( 78 | .rtl_data(down_data_a), 79 | .rtl_valid(down_valid_a), 80 | .model_data(model_data_a)); 81 | 82 | check # (.D_WIDTH (D_WIDTH)) 83 | CHK2 84 | ( 85 | .rtl_data(down_data_b), 86 | .rtl_valid(down_valid_b), 87 | .model_data(model_data_b)); 88 | 89 | //-------------------------------------------------------------------------- 90 | // Driving clock 91 | 92 | initial 93 | begin 94 | forever #5 clk = ~ clk; 95 | end 96 | 97 | //-------------------------------------------------------------------------- 98 | //Initialization and driving simulation 99 | initial 100 | begin 101 | clk = 0; 102 | forever @ (posedge clk); 103 | end 104 | 105 | endmodule 106 | -------------------------------------------------------------------------------- /hdl/scenario9/custom_logic_join.sv: -------------------------------------------------------------------------------- 1 | module custom_logic_join #(parameter D_WIDTH = 6) 2 | ( 3 | input clk, 4 | input rst, 5 | input [(D_WIDTH-1):0] up_data_a, 6 | input up_valid_a, 7 | output up_ready_a, 8 | input [(D_WIDTH-1):0] up_data_b, 9 | input up_valid_b, 10 | output up_ready_b, 11 | output [(D_WIDTH-1):0] down_data, 12 | output down_valid, 13 | input down_ready 14 | ); 15 | 16 | //Connect signals to the debug vector for visualisation 17 | wire [7:0] debug; 18 | 19 | 20 | //REASSIGN DEBUG SIGNALS AS NEEDED 21 | assign debug[7] = 1'bx; 22 | assign debug[6] = 1'bx; 23 | assign debug[5] = 1'bx; 24 | assign debug[4] = 1'bx; 25 | assign debug[3] = 1'bx; 26 | assign debug[2] = 1'bx; 27 | assign debug[1] = 1'bx; 28 | assign debug[0] = 1'bx; 29 | 30 | 31 | //BEGIN CUSTOM LOGIC BLOCK 32 | 33 | assign down_data = up_data_a + up_data_b; 34 | assign down_valid = up_valid_a & up_valid_b; 35 | assign up_ready_a = down_valid & down_ready; 36 | assign up_ready_b = down_valid & down_ready; 37 | 38 | //END CUSTOM LOGIC BLOCK 39 | 40 | endmodule 41 | -------------------------------------------------------------------------------- /hdl/scenario9/ff_fifo_pow2_depth.sv: -------------------------------------------------------------------------------- 1 | //---AXI-STREAM FLOP-BASED FIFO WITH DEPTH OF PWR OF 2---// 2 | //Valid/Rready flags generation is based on comparison of write & read counters 3 | //and their MSBs that indicate "Wrap-around", as per Clifford_E_Cummings. 4 | 5 | module ff_fifo_pow2_depth #(parameter D_WIDTH = 6, A_WIDTH = 2) 6 | ( 7 | input clk, 8 | input rst, 9 | input [(D_WIDTH-1):0] up_data, 10 | input up_valid, 11 | output up_ready, 12 | output [(D_WIDTH-1):0] down_data, 13 | output down_valid, 14 | input down_ready 15 | ); 16 | 17 | wire push, pop; 18 | wire empty, full; 19 | wire [(A_WIDTH-1):0] wr_ptr, rd_ptr; 20 | 21 | reg [(A_WIDTH):0] fullwidth_wr_ptr, fullwidth_rd_ptr; 22 | reg [(D_WIDTH-1):0] ram[2**A_WIDTH-1:0]; 23 | 24 | 25 | always @ (posedge clk) 26 | begin 27 | if (push) 28 | ram[wr_ptr] <= up_data; 29 | end 30 | 31 | //WR_COUNTER 32 | always @(posedge clk) 33 | if (rst) begin 34 | fullwidth_wr_ptr <= {(A_WIDTH+1){1'b0}}; 35 | end else if (push) begin 36 | fullwidth_wr_ptr <= fullwidth_wr_ptr + 1; 37 | end 38 | 39 | //RD_COUNTER 40 | always @(posedge clk) 41 | if (rst) begin 42 | fullwidth_rd_ptr <= {(A_WIDTH+1){1'b0}}; 43 | end else if (pop) begin 44 | fullwidth_rd_ptr <= fullwidth_rd_ptr + 1; 45 | end 46 | 47 | //Generate push and pop signals 48 | assign push = up_valid & up_ready; 49 | assign pop = down_valid & down_ready; 50 | 51 | //output LSBits out of full_wr_ptr 52 | assign wr_ptr = fullwidth_wr_ptr[(A_WIDTH-1):0]; 53 | //output LSBits out of full_rd_ptr 54 | assign rd_ptr = fullwidth_rd_ptr[(A_WIDTH-1):0]; 55 | 56 | //"empty" 57 | //It is "1" when MSBits and other bits of "full_rd_ptr" and "full_wr_ptr" are equal 58 | assign empty = ((fullwidth_wr_ptr[(A_WIDTH)] == fullwidth_rd_ptr[(A_WIDTH)]) && 59 | (fullwidth_wr_ptr[(A_WIDTH-1):0] == fullwidth_rd_ptr[(A_WIDTH-1):0])) ? 1'b1 : 1'b0; 60 | //"valid" aka "not_empty" 61 | assign down_valid = ~empty; 62 | 63 | //"full" 64 | //It is "1" when MSBits of "full_rd_ptr" and "full_wr_ptr" are not equal but other bits equal 65 | assign full = ((fullwidth_wr_ptr[(A_WIDTH)] != fullwidth_rd_ptr[(A_WIDTH)]) && 66 | (fullwidth_wr_ptr[(A_WIDTH-1):0] == fullwidth_rd_ptr[(A_WIDTH-1):0])) ? 1'b1 : 1'b0; 67 | //"ready" aka "not_full" 68 | assign up_ready = ~full; 69 | 70 | assign down_data = ram[rd_ptr]; 71 | 72 | endmodule 73 | -------------------------------------------------------------------------------- /hdl/scenario9/rtl.sv: -------------------------------------------------------------------------------- 1 | //---TOP MODULE FOR RTL DESIGN---// 2 | 3 | module rtl #(parameter D_WIDTH = 6, A_WIDTH = 2) 4 | ( 5 | input clk, 6 | input rst, 7 | input [(D_WIDTH-1):0] up_data_a, 8 | input up_valid_a, 9 | output up_ready_a, 10 | input [(D_WIDTH-1):0] up_data_b, 11 | input up_valid_b, 12 | output up_ready_b, 13 | output [(D_WIDTH-1):0] down_data, 14 | output down_valid, 15 | input down_ready 16 | ); 17 | 18 | wire [(D_WIDTH-1):0] w_fifo1_down_data_a; 19 | wire w_fifo1_down_valid_a; 20 | wire w_clgk1_up_ready_a; 21 | wire [(D_WIDTH-1):0] w_fifo2_down_data_b; 22 | wire w_fifo2_down_valid_b; 23 | wire w_clgk1_up_ready_b; 24 | wire [(D_WIDTH-1):0] w_clgk1_down_data; 25 | wire w_clgk1_down_valid; 26 | wire w_fifo3_up_ready; 27 | 28 | ff_fifo_pow2_depth # (.D_WIDTH (D_WIDTH), .A_WIDTH (A_WIDTH)) 29 | FIFO1 30 | ( .clk(clk), 31 | .rst(rst), 32 | .up_data(up_data_a), 33 | .up_valid(up_valid_a), 34 | .up_ready(up_ready_a), 35 | .down_data(w_fifo1_down_data_a), 36 | .down_valid(w_fifo1_down_valid_a), 37 | .down_ready(w_clgk1_up_ready_a)); 38 | 39 | ff_fifo_pow2_depth # (.D_WIDTH (D_WIDTH), .A_WIDTH (A_WIDTH)) 40 | FIFO2 41 | ( .clk(clk), 42 | .rst(rst), 43 | .up_data(up_data_b), 44 | .up_valid(up_valid_b), 45 | .up_ready(up_ready_b), 46 | .down_data(w_fifo2_down_data_b), 47 | .down_valid(w_fifo2_down_valid_b), 48 | .down_ready(w_clgk1_up_ready_b)); 49 | 50 | custom_logic_join # (.D_WIDTH (D_WIDTH)) 51 | CLGC1 52 | ( .clk(clk), 53 | .rst(rst), 54 | .up_data_a(w_fifo1_down_data_a), 55 | .up_valid_a(w_fifo1_down_valid_a), 56 | .up_ready_a(w_clgk1_up_ready_a), 57 | .up_data_b(w_fifo2_down_data_b), 58 | .up_valid_b(w_fifo2_down_valid_b), 59 | .up_ready_b(w_clgk1_up_ready_b), 60 | .down_data(w_clgk1_down_data), 61 | .down_valid(w_clgk1_down_valid), 62 | .down_ready(w_fifo3_up_ready)); 63 | 64 | ff_fifo_pow2_depth # (.D_WIDTH (D_WIDTH), .A_WIDTH (A_WIDTH)) 65 | FIFO3 66 | ( .clk(clk), 67 | .rst(rst), 68 | .up_data(w_clgk1_down_data), 69 | .up_valid(w_clgk1_down_valid), 70 | .up_ready(w_fifo3_up_ready), 71 | .down_data(down_data), 72 | .down_valid(down_valid), 73 | .down_ready(down_ready)); 74 | 75 | endmodule 76 | -------------------------------------------------------------------------------- /hdl/scenario9/tb.sv: -------------------------------------------------------------------------------- 1 | module tb 2 | # ( 3 | parameter D_WIDTH = 6, A_WIDTH = 2 4 | ); 5 | 6 | //-------------------------------------------------------------------------- 7 | // Signals to drive Device Under Test - DUT 8 | 9 | logic clk; 10 | wire rst; 11 | 12 | // Upstream 13 | 14 | wire up_valid_a; 15 | wire up_ready_a; 16 | wire [(D_WIDTH-1):0] up_data_a; 17 | 18 | wire up_valid_b; 19 | wire up_ready_b; 20 | wire [(D_WIDTH-1):0] up_data_b; 21 | 22 | // Downstream 23 | 24 | wire down_valid; 25 | wire down_ready; 26 | wire [(D_WIDTH-1):0] down_data; 27 | 28 | //-------------------------------------------------------------------------- 29 | // DUT instantiation 30 | 31 | rtl # (.D_WIDTH (D_WIDTH), .A_WIDTH (A_WIDTH)) 32 | RTL1 33 | ( .clk(clk), 34 | .rst(rst), 35 | .up_data_a(up_data_a), 36 | .up_valid_a(up_valid_a), 37 | .up_ready_a(up_ready_a), 38 | .up_data_b(up_data_b), 39 | .up_valid_b(up_valid_b), 40 | .up_ready_b(up_ready_b), 41 | .down_data(down_data), 42 | .down_valid(down_valid), 43 | .down_ready(down_ready)); 44 | 45 | //-------------------------------------------------------------------------- 46 | // Driving clock 47 | 48 | initial 49 | begin 50 | forever #5 clk = ~ clk; 51 | end 52 | 53 | //-------------------------------------------------------------------------- 54 | //Initialization and driving simulation 55 | initial 56 | begin 57 | clk = 0; 58 | forever @ (posedge clk); 59 | end 60 | 61 | endmodule 62 | -------------------------------------------------------------------------------- /init_scenario1.py: -------------------------------------------------------------------------------- 1 | import cocotb 2 | from lib.common.program_class import program 3 | from lib.scenario1_class import scenario1 4 | 5 | @cocotb.test() 6 | async def my_first_test(hdl): 7 | scenario = scenario1() 8 | prog = program(hdl, scenario) 9 | #prog.logtofile("logfile.txt") 10 | await prog.run() 11 | del prog 12 | del scenario 13 | -------------------------------------------------------------------------------- /init_scenario10.py: -------------------------------------------------------------------------------- 1 | import cocotb 2 | from lib.common.program_class import program 3 | from lib.scenario10_class import scenario10 4 | 5 | @cocotb.test() 6 | async def my_first_test(hdl): 7 | scenario = scenario10() 8 | prog = program(hdl, scenario) 9 | #prog.logtofile("logfile.txt") 10 | await prog.run() 11 | del prog 12 | del scenario 13 | -------------------------------------------------------------------------------- /init_scenario11.py: -------------------------------------------------------------------------------- 1 | import cocotb 2 | from lib.common.program_class import program 3 | from lib.scenario11_class import scenario11 4 | 5 | @cocotb.test() 6 | async def my_first_test(hdl): 7 | scenario = scenario11() 8 | prog = program(hdl, scenario) 9 | #prog.logtofile("logfile.txt") 10 | await prog.run() 11 | del prog 12 | del scenario 13 | -------------------------------------------------------------------------------- /init_scenario12.py: -------------------------------------------------------------------------------- 1 | import cocotb 2 | from lib.common.program_class import program 3 | from lib.scenario12_class import scenario12 4 | 5 | @cocotb.test() 6 | async def my_first_test(hdl): 7 | scenario = scenario12() 8 | prog = program(hdl, scenario) 9 | #prog.logtofile("logfile.txt") 10 | await prog.run() 11 | del prog 12 | del scenario 13 | -------------------------------------------------------------------------------- /init_scenario13.py: -------------------------------------------------------------------------------- 1 | import cocotb 2 | from lib.common.program_class import program 3 | from lib.scenario13_class import scenario13 4 | 5 | @cocotb.test() 6 | async def my_first_test(hdl): 7 | scenario = scenario13() 8 | prog = program(hdl, scenario) 9 | #prog.logtofile("logfile.txt") 10 | await prog.run() 11 | del prog 12 | del scenario 13 | -------------------------------------------------------------------------------- /init_scenario14.py: -------------------------------------------------------------------------------- 1 | import cocotb 2 | from lib.common.program_class import program 3 | from lib.scenario14_class import scenario14 4 | 5 | @cocotb.test() 6 | async def my_first_test(hdl): 7 | scenario = scenario14() 8 | prog = program(hdl, scenario) 9 | #prog.logtofile("logfile.txt") 10 | await prog.run() 11 | del prog 12 | del scenario 13 | -------------------------------------------------------------------------------- /init_scenario15.py: -------------------------------------------------------------------------------- 1 | import cocotb 2 | from lib.common.program_class import program 3 | from lib.scenario15_class import scenario15 4 | 5 | @cocotb.test() 6 | async def my_first_test(hdl): 7 | scenario = scenario15() 8 | prog = program(hdl, scenario) 9 | #prog.logtofile("logfile.txt") 10 | await prog.run() 11 | del prog 12 | del scenario 13 | -------------------------------------------------------------------------------- /init_scenario16.py: -------------------------------------------------------------------------------- 1 | import cocotb 2 | from lib.common.program_class import program 3 | from lib.scenario16_class import scenario16 4 | 5 | @cocotb.test() 6 | async def my_first_test(hdl): 7 | scenario = scenario16() 8 | prog = program(hdl, scenario) 9 | #prog.logtofile("logfile.txt") 10 | await prog.run() 11 | del prog 12 | del scenario 13 | -------------------------------------------------------------------------------- /init_scenario17.py: -------------------------------------------------------------------------------- 1 | import cocotb 2 | from lib.common.program_class import program 3 | from lib.scenario17_class import scenario17 4 | 5 | @cocotb.test() 6 | async def my_first_test(hdl): 7 | scenario = scenario17() 8 | prog = program(hdl, scenario) 9 | #prog.logtofile("logfile.txt") 10 | await prog.run() 11 | del prog 12 | del scenario 13 | -------------------------------------------------------------------------------- /init_scenario18.py: -------------------------------------------------------------------------------- 1 | import cocotb 2 | from lib.common.program_class import program 3 | from lib.scenario18_class import scenario18 4 | 5 | @cocotb.test() 6 | async def my_first_test(hdl): 7 | scenario = scenario18() 8 | prog = program(hdl, scenario) 9 | #prog.logtofile("logfile.txt") 10 | await prog.run() 11 | del prog 12 | del scenario 13 | -------------------------------------------------------------------------------- /init_scenario2.py: -------------------------------------------------------------------------------- 1 | import cocotb 2 | from lib.common.program_class import program 3 | from lib.scenario2_class import scenario2 4 | 5 | @cocotb.test() 6 | async def my_first_test(hdl): 7 | scenario = scenario2() 8 | prog = program(hdl, scenario) 9 | #prog.logtofile("logfile.txt") 10 | await prog.run() 11 | del prog 12 | del scenario 13 | -------------------------------------------------------------------------------- /init_scenario3.py: -------------------------------------------------------------------------------- 1 | import cocotb 2 | from lib.common.program_class import program 3 | from lib.scenario3_class import scenario3 4 | 5 | @cocotb.test() 6 | async def my_first_test(hdl): 7 | scenario = scenario3() 8 | prog = program(hdl, scenario) 9 | #prog.logtofile("logfile.txt") 10 | await prog.run() 11 | del prog 12 | del scenario 13 | -------------------------------------------------------------------------------- /init_scenario4.py: -------------------------------------------------------------------------------- 1 | import cocotb 2 | from lib.common.program_class import program 3 | from lib.scenario4_class import scenario4 4 | 5 | @cocotb.test() 6 | async def my_first_test(hdl): 7 | scenario = scenario4() 8 | prog = program(hdl, scenario) 9 | #prog.logtofile("logfile.txt") 10 | await prog.run() 11 | del prog 12 | del scenario 13 | -------------------------------------------------------------------------------- /init_scenario5.py: -------------------------------------------------------------------------------- 1 | import cocotb 2 | from lib.common.program_class import program 3 | from lib.scenario5_class import scenario5 4 | 5 | @cocotb.test() 6 | async def my_first_test(hdl): 7 | scenario = scenario5() 8 | prog = program(hdl, scenario) 9 | #prog.logtofile("logfile.txt") 10 | await prog.run() 11 | del prog 12 | del scenario 13 | -------------------------------------------------------------------------------- /init_scenario6.py: -------------------------------------------------------------------------------- 1 | import cocotb 2 | from lib.common.program_class import program 3 | from lib.scenario6_class import scenario6 4 | 5 | @cocotb.test() 6 | async def my_first_test(hdl): 7 | scenario = scenario6() 8 | prog = program(hdl, scenario) 9 | #prog.logtofile("logfile.txt") 10 | await prog.run() 11 | del prog 12 | del scenario 13 | -------------------------------------------------------------------------------- /init_scenario7.py: -------------------------------------------------------------------------------- 1 | import cocotb 2 | from lib.common.program_class import program 3 | from lib.scenario7_class import scenario7 4 | 5 | @cocotb.test() 6 | async def my_first_test(hdl): 7 | scenario = scenario7() 8 | prog = program(hdl, scenario) 9 | #prog.logtofile("logfile.txt") 10 | await prog.run() 11 | del prog 12 | del scenario 13 | -------------------------------------------------------------------------------- /init_scenario8.py: -------------------------------------------------------------------------------- 1 | import cocotb 2 | from lib.common.program_class import program 3 | from lib.scenario8_class import scenario8 4 | 5 | @cocotb.test() 6 | async def my_first_test(hdl): 7 | scenario = scenario8() 8 | prog = program(hdl, scenario) 9 | #prog.logtofile("logfile.txt") 10 | await prog.run() 11 | del prog 12 | del scenario 13 | -------------------------------------------------------------------------------- /init_scenario9.py: -------------------------------------------------------------------------------- 1 | import cocotb 2 | from lib.common.program_class import program 3 | from lib.scenario9_class import scenario9 4 | 5 | @cocotb.test() 6 | async def my_first_test(hdl): 7 | scenario = scenario9() 8 | prog = program(hdl, scenario) 9 | #prog.logtofile("logfile.txt") 10 | await prog.run() 11 | del prog 12 | del scenario 13 | -------------------------------------------------------------------------------- /lib/__init__.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/FPGA-InsideOut/hdlgadgets/6dc2ae8860b647fd0beb402263973db8f6b506e4/lib/__init__.py -------------------------------------------------------------------------------- /lib/common/gadgettop_class.py: -------------------------------------------------------------------------------- 1 | class gadgettop(): 2 | 3 | def __init__(self): 4 | self._wctx = None 5 | 6 | def __del__(self): 7 | del self._wctx 8 | -------------------------------------------------------------------------------- /lib/common/helper_class.py: -------------------------------------------------------------------------------- 1 | class helper(): 2 | 3 | @staticmethod 4 | def dictcopy (srcdict, dstdict): #Copy one dictionary into another 5 | for vectorname, vectorvalue in srcdict.items(): 6 | for vectorunit in range(len(vectorvalue)): 7 | dstdict[vectorname][vectorunit] = srcdict[vectorname][vectorunit] 8 | 9 | @staticmethod 10 | def put_hdl_vector_to_dict (dstdictvectorname, hdlstrvectorvalue): #write logic vector into dictionary 11 | for vectorindex, vectorunit in enumerate(hdlstrvectorvalue): 12 | dstdictvectorname[vectorindex] = vectorunit 13 | 14 | @staticmethod 15 | def show_dict_charlist_as_string (srcdictcharlist): #convert list of chars into a string 16 | outstr = '' 17 | for ch in srcdictcharlist: 18 | outstr += ch 19 | return outstr 20 | 21 | @staticmethod 22 | def check_transaction_of_some_state_exists (dictvectorname, matchingstate): #check that element exists in the list 23 | vectorindex = 0 24 | while vectorindex < len(dictvectorname): 25 | if (dictvectorname[vectorindex] == matchingstate): 26 | return True 27 | else: 28 | vectorindex = vectorindex + 1 29 | return False 30 | 31 | @staticmethod 32 | def convert_single_transaction_of_some_state (dictvectorname, matchingstate, newstate): #find one element in a list and convert it 33 | vectorindex = 0 34 | while vectorindex < len(dictvectorname): 35 | if (dictvectorname[vectorindex] == matchingstate): 36 | dictvectorname[vectorindex] = newstate 37 | vectorindex = len(dictvectorname) 38 | else: 39 | vectorindex = vectorindex + 1 40 | 41 | -------------------------------------------------------------------------------- /lib/common/scenariotop_class.py: -------------------------------------------------------------------------------- 1 | class scenariotop(): 2 | 3 | def __init__(self): 4 | self._ctx = None 5 | 6 | def __del__(self): 7 | del self._ctx 8 | -------------------------------------------------------------------------------- /lib/gadgets/gadget_fifobase_class.py: -------------------------------------------------------------------------------- 1 | import curses 2 | from lib.common.gadgettop_class import gadgettop 3 | 4 | class gadget_fifobase(gadgettop): 5 | 6 | def __init__(self): 7 | super().__init__() 8 | 9 | def __del__(self): 10 | super().__del__() 11 | 12 | def setup_2d_model (self, wctx): 13 | self._wctx = wctx 14 | self._wctx.erase() 15 | self._wctx.bkgd(' ', curses.color_pair(1)) 16 | self._wctx.refresh() 17 | 18 | def process_input_stimulus (self, hdlpath, key): 19 | pass 20 | 21 | def post_process_logic_state (self, phase): 22 | pass 23 | 24 | def write_to_log (self, strprefix, logfile): 25 | logfile.write(strprefix + ", logicstate_pre:" + str(self.logicstate_pre) + "\n") 26 | logfile.write(strprefix + ", logicstate_post:" + str(self.logicstate_post) + "\n") 27 | 28 | -------------------------------------------------------------------------------- /lib/gadgets/gadget_fplate_sc10_class.py: -------------------------------------------------------------------------------- 1 | import curses 2 | from lib.common.gadgettop_class import gadgettop 3 | 4 | class gadget_fplate_sc10(gadgettop): 5 | 6 | def __init__(self): 7 | super().__init__() 8 | 9 | def __del__(self): 10 | super().__del__() 11 | 12 | def setup_2d_model (self, wctx): 13 | self._wctx = wctx 14 | self._wctx.erase() 15 | self._wctx.bkgd(' ', curses.color_pair(1)) 16 | self._wctx.refresh() 17 | 18 | def process_input_stimulus (self, hdlpath, key): 19 | pass 20 | 21 | def get_logic_state_data_from_simulator (self, hdlpath): 22 | pass 23 | 24 | def post_process_logic_state (self, phase): 25 | pass 26 | 27 | def write_to_log (self, strprefix, logfile): 28 | pass 29 | 30 | def drive_2d_model (self): 31 | self._wctx.addstr(1,21, u'\u0020\u0046\u0049\u0046\u004F\u005F\u0041\u0020'.encode('utf-8'), curses.color_pair(3)) 32 | self._wctx.addstr(16,21, u'\u0020\u0046\u0049\u0046\u004F\u005F\u0042\u0020'.encode('utf-8'), curses.color_pair(3)) 33 | self._wctx.addstr(1,77, u'\u0020\u0020\u0046\u0049\u0046\u004F\u0020\u0020'.encode('utf-8'), curses.color_pair(3)) 34 | self._wctx.addstr(3,49, u'\u0020\u0043\u0055\u0053\u0054\u004F\u004D\u0020'.encode('utf-8'), curses.color_pair(3)) 35 | self._wctx.addstr(4,49, u'\u0020\u004C\u004F\u0047\u0049\u0043\u0020\u0020'.encode('utf-8'), curses.color_pair(3)) 36 | self._wctx.addstr(18,78, u'\u0020\u0020\u0043\u004F\u004E\u0054\u0052\u004F\u004C\u0020\u0020'.encode('utf-8'), curses.color_pair(3)) 37 | self._wctx.addstr(30,65, u'\u0020\u004D\u004F\u0044\u0045\u004C\u005F\u0051\u0055\u0045\u0055\u0045\u0020'.encode('utf-8'), curses.color_pair(3)) 38 | self._wctx.addstr(30,93, u'\u0052\u0054\u004C\u005F\u004D\u004F\u0044\u0045\u004C\u005F\u0045\u0052\u0052'.encode('utf-8'), curses.color_pair(3)) 39 | 40 | self._wctx.refresh() 41 | -------------------------------------------------------------------------------- /lib/gadgets/gadget_fplate_sc11_class.py: -------------------------------------------------------------------------------- 1 | import curses 2 | from lib.common.gadgettop_class import gadgettop 3 | 4 | class gadget_fplate_sc11(gadgettop): 5 | 6 | def __init__(self): 7 | super().__init__() 8 | 9 | def __del__(self): 10 | super().__del__() 11 | 12 | def setup_2d_model (self, wctx): 13 | self._wctx = wctx 14 | self._wctx.erase() 15 | self._wctx.bkgd(' ', curses.color_pair(1)) 16 | self._wctx.refresh() 17 | 18 | def process_input_stimulus (self, hdlpath, key): 19 | pass 20 | 21 | def get_logic_state_data_from_simulator (self, hdlpath): 22 | pass 23 | 24 | def post_process_logic_state (self, phase): 25 | pass 26 | 27 | def write_to_log (self, strprefix, logfile): 28 | pass 29 | 30 | def drive_2d_model (self): 31 | self._wctx.addstr(1,21, u'\u0020\u0046\u0049\u0046\u004F\u005F\u0041\u0020'.encode('utf-8'), curses.color_pair(3)) 32 | self._wctx.addstr(16,21, u'\u0020\u0046\u0049\u0046\u004F\u005F\u0042\u0020'.encode('utf-8'), curses.color_pair(3)) 33 | self._wctx.addstr(1,77, u'\u0020\u0020\u0046\u0049\u0046\u004F\u0020\u0020'.encode('utf-8'), curses.color_pair(3)) 34 | self._wctx.addstr(3,49, u'\u0020\u0043\u0055\u0053\u0054\u004F\u004D\u0020'.encode('utf-8'), curses.color_pair(3)) 35 | self._wctx.addstr(4,49, u'\u0020\u004C\u004F\u0047\u0049\u0043\u0020\u0020'.encode('utf-8'), curses.color_pair(3)) 36 | self._wctx.addstr(18,78, u'\u0020\u0020\u0043\u004F\u004E\u0054\u0052\u004F\u004C\u0020\u0020'.encode('utf-8'), curses.color_pair(3)) 37 | self._wctx.addstr(31,26, u'\u0020\u004D\u004F\u0044\u0045\u004C\u005F\u0051\u0055\u0045\u0055\u0045\u005F\u0041\u0020'.encode('utf-8'), curses.color_pair(3)) 38 | self._wctx.addstr(31,64, u'\u0020\u004D\u004F\u0044\u0045\u004C\u005F\u0051\u0055\u0045\u0055\u0045\u005F\u0042\u0020'.encode('utf-8'), curses.color_pair(3)) 39 | self._wctx.addstr(31,93, u'\u0052\u0054\u004C\u005F\u004D\u004F\u0044\u0045\u004C\u005F\u0045\u0052\u0052'.encode('utf-8'), curses.color_pair(3)) 40 | 41 | self._wctx.refresh() 42 | -------------------------------------------------------------------------------- /lib/gadgets/gadget_fplate_sc12_class.py: -------------------------------------------------------------------------------- 1 | import curses 2 | from lib.common.gadgettop_class import gadgettop 3 | 4 | class gadget_fplate_sc12(gadgettop): 5 | 6 | def __init__(self): 7 | super().__init__() 8 | 9 | def __del__(self): 10 | super().__del__() 11 | 12 | def setup_2d_model (self, wctx): 13 | self._wctx = wctx 14 | self._wctx.erase() 15 | self._wctx.bkgd(' ', curses.color_pair(1)) 16 | self._wctx.refresh() 17 | 18 | def process_input_stimulus (self, hdlpath, key): 19 | pass 20 | 21 | def get_logic_state_data_from_simulator (self, hdlpath): 22 | pass 23 | 24 | def post_process_logic_state (self, phase): 25 | pass 26 | 27 | def write_to_log (self, strprefix, logfile): 28 | pass 29 | 30 | def drive_2d_model (self): 31 | self._wctx.addstr(2,24, u'\u0020\u0053\u0046\u0054\u0052\u0045\u0047\u0020'.encode('utf-8'), curses.color_pair(3)) 32 | self._wctx.addstr(19,22, u'\u0020\u0020\u0043\u004F\u004E\u0054\u0052\u004F\u004C\u0020\u0020'.encode('utf-8'), curses.color_pair(3)) 33 | 34 | self._wctx.refresh() 35 | -------------------------------------------------------------------------------- /lib/gadgets/gadget_fplate_sc13_class.py: -------------------------------------------------------------------------------- 1 | import curses 2 | from lib.common.gadgettop_class import gadgettop 3 | 4 | class gadget_fplate_sc13(gadgettop): 5 | 6 | def __init__(self): 7 | super().__init__() 8 | 9 | def __del__(self): 10 | super().__del__() 11 | 12 | def setup_2d_model (self, wctx): 13 | self._wctx = wctx 14 | self._wctx.erase() 15 | self._wctx.bkgd(' ', curses.color_pair(1)) 16 | self._wctx.refresh() 17 | 18 | def process_input_stimulus (self, hdlpath, key): 19 | pass 20 | 21 | def get_logic_state_data_from_simulator (self, hdlpath): 22 | pass 23 | 24 | def post_process_logic_state (self, phase): 25 | pass 26 | 27 | def write_to_log (self, strprefix, logfile): 28 | pass 29 | 30 | def drive_2d_model (self): 31 | self._wctx.addstr(2,24, u'\u0020\u0053\u0046\u0054\u0052\u0045\u0047\u0020'.encode('utf-8'), curses.color_pair(3)) 32 | self._wctx.addstr(2,80, u'\u0020\u0053\u0046\u0054\u0052\u0045\u0047\u0020'.encode('utf-8'), curses.color_pair(3)) 33 | self._wctx.addstr(4,52, u'\u0020\u0043\u0055\u0053\u0054\u004F\u004D\u0020'.encode('utf-8'), curses.color_pair(3)) 34 | self._wctx.addstr(5,52, u'\u0020\u004C\u004F\u0047\u0049\u0043\u0020\u0020'.encode('utf-8'), curses.color_pair(3)) 35 | self._wctx.addstr(19,64, u'\u0020\u0020\u004D\u004F\u0044\u0045\u004C\u005F\u0051\u0055\u0045\u0055\u0045\u0020\u0020'.encode('utf-8'), curses.color_pair(3)) 36 | self._wctx.addstr(19,94, u'\u0052\u0054\u004C\u005F\u004D\u004F\u0044\u0045\u004C\u005F\u0045\u0052\u0052'.encode('utf-8'), curses.color_pair(3)) 37 | self._wctx.addstr(19,22, u'\u0020\u0020\u0043\u004F\u004E\u0054\u0052\u004F\u004C\u0020\u0020'.encode('utf-8'), curses.color_pair(3)) 38 | 39 | self._wctx.refresh() 40 | -------------------------------------------------------------------------------- /lib/gadgets/gadget_fplate_sc14_class.py: -------------------------------------------------------------------------------- 1 | import curses 2 | from lib.common.gadgettop_class import gadgettop 3 | 4 | class gadget_fplate_sc14(gadgettop): 5 | 6 | def __init__(self): 7 | super().__init__() 8 | 9 | def __del__(self): 10 | super().__del__() 11 | 12 | def setup_2d_model (self, wctx): 13 | self._wctx = wctx 14 | self._wctx.erase() 15 | self._wctx.bkgd(' ', curses.color_pair(1)) 16 | self._wctx.refresh() 17 | 18 | def process_input_stimulus (self, hdlpath, key): 19 | pass 20 | 21 | def get_logic_state_data_from_simulator (self, hdlpath): 22 | pass 23 | 24 | def post_process_logic_state (self, phase): 25 | pass 26 | 27 | def write_to_log (self, strprefix, logfile): 28 | pass 29 | 30 | def drive_2d_model (self): 31 | self._wctx.addstr(2,24, u'\u0020\u0053\u0046\u0054\u0052\u0045\u0047\u0020'.encode('utf-8'), curses.color_pair(3)) 32 | self._wctx.addstr(2,80, u'\u0020\u0020\u0046\u0049\u0046\u004F\u0020\u0020'.encode('utf-8'), curses.color_pair(3)) 33 | self._wctx.addstr(4,52, u'\u0020\u0043\u0055\u0053\u0054\u004F\u004D\u0020'.encode('utf-8'), curses.color_pair(3)) 34 | self._wctx.addstr(5,52, u'\u0020\u004C\u004F\u0047\u0049\u0043\u0020\u0020'.encode('utf-8'), curses.color_pair(3)) 35 | self._wctx.addstr(19,64, u'\u0020\u0020\u004D\u004F\u0044\u0045\u004C\u005F\u0051\u0055\u0045\u0055\u0045\u0020\u0020'.encode('utf-8'), curses.color_pair(3)) 36 | self._wctx.addstr(19,94, u'\u0052\u0054\u004C\u005F\u004D\u004F\u0044\u0045\u004C\u005F\u0045\u0052\u0052'.encode('utf-8'), curses.color_pair(3)) 37 | self._wctx.addstr(19,22, u'\u0020\u0020\u0043\u004F\u004E\u0054\u0052\u004F\u004C\u0020\u0020'.encode('utf-8'), curses.color_pair(3)) 38 | 39 | self._wctx.refresh() 40 | -------------------------------------------------------------------------------- /lib/gadgets/gadget_fplate_sc15_class.py: -------------------------------------------------------------------------------- 1 | import curses 2 | from lib.common.gadgettop_class import gadgettop 3 | 4 | class gadget_fplate_sc15(gadgettop): 5 | 6 | def __init__(self): 7 | super().__init__() 8 | 9 | def __del__(self): 10 | super().__del__() 11 | 12 | def setup_2d_model (self, wctx): 13 | self._wctx = wctx 14 | self._wctx.erase() 15 | self._wctx.bkgd(' ', curses.color_pair(1)) 16 | self._wctx.refresh() 17 | 18 | def process_input_stimulus (self, hdlpath, key): 19 | pass 20 | 21 | def get_logic_state_data_from_simulator (self, hdlpath): 22 | pass 23 | 24 | def post_process_logic_state (self, phase): 25 | pass 26 | 27 | def write_to_log (self, strprefix, logfile): 28 | pass 29 | 30 | def drive_2d_model (self): 31 | self._wctx.addstr(2,24, u'\u0020\u0053\u0046\u0054\u0052\u0045\u0047\u0020'.encode('utf-8'), curses.color_pair(3)) 32 | self._wctx.addstr(2,70, u'\u0020\u0020\u0046\u0049\u0046\u004F\u0020\u0020'.encode('utf-8'), curses.color_pair(3)) 33 | self._wctx.addstr(19,22, u'\u0020\u0020\u0043\u004F\u004E\u0054\u0052\u004F\u004C\u0020\u0020'.encode('utf-8'), curses.color_pair(3)) 34 | 35 | self._wctx.refresh() 36 | -------------------------------------------------------------------------------- /lib/gadgets/gadget_fplate_sc16_class.py: -------------------------------------------------------------------------------- 1 | import curses 2 | from lib.common.gadgettop_class import gadgettop 3 | 4 | class gadget_fplate_sc16(gadgettop): 5 | 6 | def __init__(self): 7 | super().__init__() 8 | 9 | def __del__(self): 10 | super().__del__() 11 | 12 | def setup_2d_model (self, wctx): 13 | self._wctx = wctx 14 | self._wctx.erase() 15 | self._wctx.bkgd(' ', curses.color_pair(1)) 16 | self._wctx.refresh() 17 | 18 | def process_input_stimulus (self, hdlpath, key): 19 | pass 20 | 21 | def get_logic_state_data_from_simulator (self, hdlpath): 22 | pass 23 | 24 | def post_process_logic_state (self, phase): 25 | pass 26 | 27 | def write_to_log (self, strprefix, logfile): 28 | pass 29 | 30 | def drive_2d_model (self): 31 | self._wctx.addstr(1,25, u'\u0020\u0043\u0042\u0046\u0043\u0020'.encode('utf-8'), curses.color_pair(3)) 32 | self._wctx.addstr(2,70, u'\u0020\u0020\u0046\u0049\u0046\u004F\u0020\u0020'.encode('utf-8'), curses.color_pair(3)) 33 | self._wctx.addstr(21,64, u'\u0020\u0020\u004D\u004F\u0044\u0045\u004C\u005F\u0051\u0055\u0045\u0055\u0045\u0020\u0020'.encode('utf-8'), curses.color_pair(3)) 34 | self._wctx.addstr(21,94, u'\u0052\u0054\u004C\u005F\u004D\u004F\u0044\u0045\u004C\u005F\u0045\u0052\u0052'.encode('utf-8'), curses.color_pair(3)) 35 | self._wctx.addstr(21,22, u'\u0020\u0020\u0043\u004F\u004E\u0054\u0052\u004F\u004C\u0020\u0020'.encode('utf-8'), curses.color_pair(3)) 36 | 37 | self._wctx.refresh() 38 | -------------------------------------------------------------------------------- /lib/gadgets/gadget_fplate_sc17_class.py: -------------------------------------------------------------------------------- 1 | import curses 2 | from lib.common.gadgettop_class import gadgettop 3 | 4 | class gadget_fplate_sc17(gadgettop): 5 | 6 | def __init__(self): 7 | super().__init__() 8 | 9 | def __del__(self): 10 | super().__del__() 11 | 12 | def setup_2d_model (self, wctx): 13 | self._wctx = wctx 14 | self._wctx.erase() 15 | self._wctx.bkgd(' ', curses.color_pair(1)) 16 | self._wctx.refresh() 17 | 18 | def process_input_stimulus (self, hdlpath, key): 19 | pass 20 | 21 | def get_logic_state_data_from_simulator (self, hdlpath): 22 | pass 23 | 24 | def post_process_logic_state (self, phase): 25 | pass 26 | 27 | def write_to_log (self, strprefix, logfile): 28 | pass 29 | 30 | def drive_2d_model (self): 31 | self._wctx.addstr(2,22, u'\u0020\u0043\u0055\u0053\u0054\u004F\u004D\u0020'.encode('utf-8'), curses.color_pair(3)) 32 | self._wctx.addstr(3,22, u'\u0020\u004C\u004F\u0047\u0049\u0043\u0020\u0020'.encode('utf-8'), curses.color_pair(3)) 33 | self._wctx.addstr(17,64, u'\u0020\u004D\u004F\u0044\u0045\u004C\u005F\u0051\u0055\u0045\u0055\u0045\u005F\u0041\u0020'.encode('utf-8'), curses.color_pair(3)) 34 | self._wctx.addstr(25,64, u'\u0020\u004D\u004F\u0044\u0045\u004C\u005F\u0051\u0055\u0045\u0055\u0045\u005F\u0042\u0020'.encode('utf-8'), curses.color_pair(3)) 35 | self._wctx.addstr(17,94, u'\u0052\u0054\u004C\u005F\u004D\u004F\u0044\u0045\u004C\u005F\u0045\u0052\u0052'.encode('utf-8'), curses.color_pair(3)) 36 | self._wctx.addstr(17,22, u'\u0020\u0020\u0043\u004F\u004E\u0054\u0052\u004F\u004C\u0020\u0020'.encode('utf-8'), curses.color_pair(3)) 37 | 38 | self._wctx.refresh() 39 | -------------------------------------------------------------------------------- /lib/gadgets/gadget_fplate_sc18_class.py: -------------------------------------------------------------------------------- 1 | import curses 2 | from lib.common.gadgettop_class import gadgettop 3 | 4 | class gadget_fplate_sc18(gadgettop): 5 | 6 | def __init__(self): 7 | super().__init__() 8 | 9 | def __del__(self): 10 | super().__del__() 11 | 12 | def setup_2d_model (self, wctx): 13 | self._wctx = wctx 14 | self._wctx.erase() 15 | self._wctx.bkgd(' ', curses.color_pair(1)) 16 | self._wctx.refresh() 17 | 18 | def process_input_stimulus (self, hdlpath, key): 19 | pass 20 | 21 | def get_logic_state_data_from_simulator (self, hdlpath): 22 | pass 23 | 24 | def post_process_logic_state (self, phase): 25 | pass 26 | 27 | def write_to_log (self, strprefix, logfile): 28 | pass 29 | 30 | def drive_2d_model (self): 31 | self._wctx.addstr(1,23, u'\u0046\u0049\u0046\u004F\u005F\u0052\u004C\u0042\u004B'.encode('utf-8'), curses.color_pair(3)) 32 | self._wctx.addstr(1,64, u'\u0020\u004D\u004F\u0044\u0045\u004C\u005F\u0051\u0055\u0045\u0055\u0045\u005F\u0041\u0020'.encode('utf-8'), curses.color_pair(3)) 33 | self._wctx.addstr(9,64, u'\u0020\u004D\u004F\u0044\u0045\u004C\u005F\u0051\u0055\u0045\u0055\u0045\u005F\u0042\u0020'.encode('utf-8'), curses.color_pair(3)) 34 | self._wctx.addstr(19,65, u'\u0052\u0054\u004C\u005F\u004D\u004F\u0044\u0045\u004C\u005F\u0045\u0052\u0052'.encode('utf-8'), curses.color_pair(3)) 35 | self._wctx.addstr(25,22, u'\u0020\u0020\u0043\u004F\u004E\u0054\u0052\u004F\u004C\u0020\u0020'.encode('utf-8'), curses.color_pair(3)) 36 | 37 | self._wctx.refresh() 38 | -------------------------------------------------------------------------------- /lib/gadgets/gadget_fplate_sc1_class.py: -------------------------------------------------------------------------------- 1 | import curses 2 | from lib.common.gadgettop_class import gadgettop 3 | 4 | class gadget_fplate_sc1(gadgettop): 5 | 6 | def __init__(self): 7 | super().__init__() 8 | 9 | def __del__(self): 10 | super().__del__() 11 | 12 | def setup_2d_model (self, wctx): 13 | self._wctx = wctx 14 | self._wctx.erase() 15 | self._wctx.bkgd(' ', curses.color_pair(1)) 16 | self._wctx.refresh() 17 | 18 | def process_input_stimulus (self, hdlpath, key): 19 | pass 20 | 21 | def get_logic_state_data_from_simulator (self, hdlpath): 22 | pass 23 | 24 | def post_process_logic_state (self, phase): 25 | pass 26 | 27 | def write_to_log (self, strprefix, logfile): 28 | pass 29 | 30 | def drive_2d_model (self): 31 | self._wctx.addstr(2,24, u'\u0020\u0020\u0046\u0049\u0046\u004F\u0020\u0020'.encode('utf-8'), curses.color_pair(3)) 32 | self._wctx.addstr(19,22, u'\u0020\u0020\u0043\u004F\u004E\u0054\u0052\u004F\u004C\u0020\u0020'.encode('utf-8'), curses.color_pair(3)) 33 | 34 | self._wctx.refresh() 35 | -------------------------------------------------------------------------------- /lib/gadgets/gadget_fplate_sc2_class.py: -------------------------------------------------------------------------------- 1 | import curses 2 | from lib.common.gadgettop_class import gadgettop 3 | 4 | class gadget_fplate_sc2(gadgettop): 5 | 6 | def __init__(self): 7 | super().__init__() 8 | 9 | def __del__(self): 10 | super().__del__() 11 | 12 | def setup_2d_model (self, wctx): 13 | self._wctx = wctx 14 | self._wctx.erase() 15 | self._wctx.bkgd(' ', curses.color_pair(1)) 16 | self._wctx.refresh() 17 | 18 | def process_input_stimulus (self, hdlpath, key): 19 | pass 20 | 21 | def get_logic_state_data_from_simulator (self, hdlpath): 22 | pass 23 | 24 | def post_process_logic_state (self, phase): 25 | pass 26 | 27 | def write_to_log (self, strprefix, logfile): 28 | pass 29 | 30 | def drive_2d_model (self): 31 | self._wctx.addstr(2,24, u'\u0020\u0020\u0046\u0049\u0046\u004F\u0020\u0020'.encode('utf-8'), curses.color_pair(3)) 32 | self._wctx.addstr(2,70, u'\u0020\u0020\u004D\u004F\u0044\u0045\u004C\u005F\u0051\u0055\u0045\u0055\u0045\u0020\u0020'.encode('utf-8'), curses.color_pair(3)) 33 | self._wctx.addstr(19,22, u'\u0020\u0020\u0043\u004F\u004E\u0054\u0052\u004F\u004C\u0020\u0020'.encode('utf-8'), curses.color_pair(3)) 34 | self._wctx.addstr(15,72, u'\u0052\u0054\u004C\u005F\u004D\u004F\u0044\u0045\u004C\u005F\u0045\u0052\u0052'.encode('utf-8'), curses.color_pair(3)) 35 | 36 | self._wctx.refresh() 37 | -------------------------------------------------------------------------------- /lib/gadgets/gadget_fplate_sc3_class.py: -------------------------------------------------------------------------------- 1 | import curses 2 | from lib.common.gadgettop_class import gadgettop 3 | 4 | class gadget_fplate_sc3(gadgettop): 5 | 6 | def __init__(self): 7 | super().__init__() 8 | 9 | def __del__(self): 10 | super().__del__() 11 | 12 | def setup_2d_model (self, wctx): 13 | self._wctx = wctx 14 | self._wctx.erase() 15 | self._wctx.bkgd(' ', curses.color_pair(1)) 16 | self._wctx.refresh() 17 | 18 | def process_input_stimulus (self, hdlpath, key): 19 | pass 20 | 21 | def get_logic_state_data_from_simulator (self, hdlpath): 22 | pass 23 | 24 | def post_process_logic_state (self, phase): 25 | pass 26 | 27 | def write_to_log (self, strprefix, logfile): 28 | pass 29 | 30 | def drive_2d_model (self): 31 | self._wctx.addstr(2,24, u'\u0020\u0020\u0046\u0049\u0046\u004F\u0020\u0020'.encode('utf-8'), curses.color_pair(3)) 32 | self._wctx.addstr(2,70, u'\u0020\u0020\u0046\u0049\u0046\u004F\u0020\u0020'.encode('utf-8'), curses.color_pair(3)) 33 | self._wctx.addstr(19,22, u'\u0020\u0020\u0043\u004F\u004E\u0054\u0052\u004F\u004C\u0020\u0020'.encode('utf-8'), curses.color_pair(3)) 34 | 35 | self._wctx.refresh() 36 | -------------------------------------------------------------------------------- /lib/gadgets/gadget_fplate_sc4_class.py: -------------------------------------------------------------------------------- 1 | import curses 2 | from lib.common.gadgettop_class import gadgettop 3 | 4 | class gadget_fplate_sc4(gadgettop): 5 | 6 | def __init__(self): 7 | super().__init__() 8 | 9 | def __del__(self): 10 | super().__del__() 11 | 12 | def setup_2d_model (self, wctx): 13 | self._wctx = wctx 14 | self._wctx.erase() 15 | self._wctx.bkgd(' ', curses.color_pair(1)) 16 | self._wctx.refresh() 17 | 18 | def process_input_stimulus (self, hdlpath, key): 19 | pass 20 | 21 | def get_logic_state_data_from_simulator (self, hdlpath): 22 | pass 23 | 24 | def post_process_logic_state (self, phase): 25 | pass 26 | 27 | def write_to_log (self, strprefix, logfile): 28 | pass 29 | 30 | def drive_2d_model (self): 31 | self._wctx.addstr(2,24, u'\u0020\u0020\u0046\u0049\u0046\u004F\u0020\u0020'.encode('utf-8'), curses.color_pair(3)) 32 | self._wctx.addstr(2,80, u'\u0020\u0020\u0046\u0049\u0046\u004F\u0020\u0020'.encode('utf-8'), curses.color_pair(3)) 33 | self._wctx.addstr(4,52, u'\u0020\u0043\u0055\u0053\u0054\u004F\u004D\u0020'.encode('utf-8'), curses.color_pair(3)) 34 | self._wctx.addstr(5,52, u'\u0020\u004C\u004F\u0047\u0049\u0043\u0020\u0020'.encode('utf-8'), curses.color_pair(3)) 35 | self._wctx.addstr(19,22, u'\u0020\u0020\u0043\u004F\u004E\u0054\u0052\u004F\u004C\u0020\u0020'.encode('utf-8'), curses.color_pair(3)) 36 | 37 | self._wctx.refresh() 38 | -------------------------------------------------------------------------------- /lib/gadgets/gadget_fplate_sc5_class.py: -------------------------------------------------------------------------------- 1 | import curses 2 | from lib.common.gadgettop_class import gadgettop 3 | 4 | class gadget_fplate_sc5(gadgettop): 5 | 6 | def __init__(self): 7 | super().__init__() 8 | 9 | def __del__(self): 10 | super().__del__() 11 | 12 | def setup_2d_model (self, wctx): 13 | self._wctx = wctx 14 | self._wctx.erase() 15 | self._wctx.bkgd(' ', curses.color_pair(1)) 16 | self._wctx.refresh() 17 | 18 | def process_input_stimulus (self, hdlpath, key): 19 | pass 20 | 21 | def get_logic_state_data_from_simulator (self, hdlpath): 22 | pass 23 | 24 | def post_process_logic_state (self, phase): 25 | pass 26 | 27 | def write_to_log (self, strprefix, logfile): 28 | pass 29 | 30 | def drive_2d_model (self): 31 | self._wctx.addstr(2,24, u'\u0020\u0020\u0046\u0049\u0046\u004F\u0020\u0020'.encode('utf-8'), curses.color_pair(3)) 32 | self._wctx.addstr(2,80, u'\u0020\u0020\u0046\u0049\u0046\u004F\u0020\u0020'.encode('utf-8'), curses.color_pair(3)) 33 | self._wctx.addstr(4,52, u'\u0020\u0043\u0055\u0053\u0054\u004F\u004D\u0020'.encode('utf-8'), curses.color_pair(3)) 34 | self._wctx.addstr(5,52, u'\u0020\u004C\u004F\u0047\u0049\u0043\u0020\u0020'.encode('utf-8'), curses.color_pair(3)) 35 | self._wctx.addstr(19,64, u'\u0020\u0020\u004D\u004F\u0044\u0045\u004C\u005F\u0051\u0055\u0045\u0055\u0045\u0020\u0020'.encode('utf-8'), curses.color_pair(3)) 36 | self._wctx.addstr(19,94, u'\u0052\u0054\u004C\u005F\u004D\u004F\u0044\u0045\u004C\u005F\u0045\u0052\u0052'.encode('utf-8'), curses.color_pair(3)) 37 | self._wctx.addstr(19,22, u'\u0020\u0020\u0043\u004F\u004E\u0054\u0052\u004F\u004C\u0020\u0020'.encode('utf-8'), curses.color_pair(3)) 38 | 39 | self._wctx.refresh() 40 | -------------------------------------------------------------------------------- /lib/gadgets/gadget_fplate_sc6_class.py: -------------------------------------------------------------------------------- 1 | import curses 2 | from lib.common.gadgettop_class import gadgettop 3 | 4 | class gadget_fplate_sc6(gadgettop): 5 | 6 | def __init__(self): 7 | super().__init__() 8 | 9 | def __del__(self): 10 | super().__del__() 11 | 12 | def setup_2d_model (self, wctx): 13 | self._wctx = wctx 14 | self._wctx.erase() 15 | self._wctx.bkgd(' ', curses.color_pair(1)) 16 | self._wctx.refresh() 17 | 18 | def process_input_stimulus (self, hdlpath, key): 19 | pass 20 | 21 | def get_logic_state_data_from_simulator (self, hdlpath): 22 | pass 23 | 24 | def post_process_logic_state (self, phase): 25 | pass 26 | 27 | def write_to_log (self, strprefix, logfile): 28 | pass 29 | 30 | def drive_2d_model (self): 31 | self._wctx.addstr(2,24, u'\u0020\u0020\u0046\u0049\u0046\u004F\u0020\u0020'.encode('utf-8'), curses.color_pair(3)) 32 | self._wctx.addstr(2,70, u'\u0020\u0020\u0046\u0049\u0046\u004F\u0020\u0020'.encode('utf-8'), curses.color_pair(3)) 33 | self._wctx.addstr(19,64, u'\u0020\u0020\u004D\u004F\u0044\u0045\u004C\u005F\u0051\u0055\u0045\u0055\u0045\u0020\u0020'.encode('utf-8'), curses.color_pair(3)) 34 | self._wctx.addstr(19,94, u'\u0052\u0054\u004C\u005F\u004D\u004F\u0044\u0045\u004C\u005F\u0045\u0052\u0052'.encode('utf-8'), curses.color_pair(3)) 35 | self._wctx.addstr(19,22, u'\u0020\u0020\u0043\u004F\u004E\u0054\u0052\u004F\u004C\u0020\u0020'.encode('utf-8'), curses.color_pair(3)) 36 | 37 | self._wctx.refresh() 38 | -------------------------------------------------------------------------------- /lib/gadgets/gadget_fplate_sc7_class.py: -------------------------------------------------------------------------------- 1 | import curses 2 | from lib.common.gadgettop_class import gadgettop 3 | 4 | class gadget_fplate_sc7(gadgettop): 5 | 6 | def __init__(self): 7 | super().__init__() 8 | 9 | def __del__(self): 10 | super().__del__() 11 | 12 | def setup_2d_model (self, wctx): 13 | self._wctx = wctx 14 | self._wctx.erase() 15 | self._wctx.bkgd(' ', curses.color_pair(1)) 16 | self._wctx.refresh() 17 | 18 | def process_input_stimulus (self, hdlpath, key): 19 | pass 20 | 21 | def get_logic_state_data_from_simulator (self, hdlpath): 22 | pass 23 | 24 | def post_process_logic_state (self, phase): 25 | pass 26 | 27 | def write_to_log (self, strprefix, logfile): 28 | pass 29 | 30 | def drive_2d_model (self): 31 | self._wctx.addstr(1,24, u'\u0020\u0020\u0046\u0049\u0046\u004F\u0020\u0020'.encode('utf-8'), curses.color_pair(3)) 32 | self._wctx.addstr(1,80, u'\u0020\u0046\u0049\u0046\u004F\u005F\u0041\u0020'.encode('utf-8'), curses.color_pair(3)) 33 | self._wctx.addstr(16,80, u'\u0020\u0046\u0049\u0046\u004F\u005F\u0042\u0020'.encode('utf-8'), curses.color_pair(3)) 34 | self._wctx.addstr(3,52, u'\u0020\u0043\u0055\u0053\u0054\u004F\u004D\u0020'.encode('utf-8'), curses.color_pair(3)) 35 | self._wctx.addstr(4,52, u'\u0020\u004C\u004F\u0047\u0049\u0043\u0020\u0020'.encode('utf-8'), curses.color_pair(3)) 36 | self._wctx.addstr(18,18, u'\u0020\u0020\u0043\u004F\u004E\u0054\u0052\u004F\u004C\u0020\u0020'.encode('utf-8'), curses.color_pair(3)) 37 | 38 | self._wctx.refresh() 39 | -------------------------------------------------------------------------------- /lib/gadgets/gadget_fplate_sc8_class.py: -------------------------------------------------------------------------------- 1 | import curses 2 | from lib.common.gadgettop_class import gadgettop 3 | 4 | class gadget_fplate_sc8(gadgettop): 5 | 6 | def __init__(self): 7 | super().__init__() 8 | 9 | def __del__(self): 10 | super().__del__() 11 | 12 | def setup_2d_model (self, wctx): 13 | self._wctx = wctx 14 | self._wctx.erase() 15 | self._wctx.bkgd(' ', curses.color_pair(1)) 16 | self._wctx.refresh() 17 | 18 | def process_input_stimulus (self, hdlpath, key): 19 | pass 20 | 21 | def get_logic_state_data_from_simulator (self, hdlpath): 22 | pass 23 | 24 | def post_process_logic_state (self, phase): 25 | pass 26 | 27 | def write_to_log (self, strprefix, logfile): 28 | pass 29 | 30 | def drive_2d_model (self): 31 | self._wctx.addstr(1,24, u'\u0020\u0020\u0046\u0049\u0046\u004F\u0020\u0020'.encode('utf-8'), curses.color_pair(3)) 32 | self._wctx.addstr(1,80, u'\u0020\u0046\u0049\u0046\u004F\u005F\u0041\u0020'.encode('utf-8'), curses.color_pair(3)) 33 | self._wctx.addstr(16,80, u'\u0020\u0046\u0049\u0046\u004F\u005F\u0042\u0020'.encode('utf-8'), curses.color_pair(3)) 34 | self._wctx.addstr(3,52, u'\u0020\u0043\u0055\u0053\u0054\u004F\u004D\u0020'.encode('utf-8'), curses.color_pair(3)) 35 | self._wctx.addstr(4,52, u'\u0020\u004C\u004F\u0047\u0049\u0043\u0020\u0020'.encode('utf-8'), curses.color_pair(3)) 36 | self._wctx.addstr(18,18, u'\u0020\u0020\u0043\u004F\u004E\u0054\u0052\u004F\u004C\u0020\u0020'.encode('utf-8'), curses.color_pair(3)) 37 | self._wctx.addstr(31,26, u'\u0020\u004D\u004F\u0044\u0045\u004C\u005F\u0051\u0055\u0045\u0055\u0045\u005F\u0041\u0020'.encode('utf-8'), curses.color_pair(3)) 38 | self._wctx.addstr(31,64, u'\u0020\u004D\u004F\u0044\u0045\u004C\u005F\u0051\u0055\u0045\u0055\u0045\u005F\u0042\u0020'.encode('utf-8'), curses.color_pair(3)) 39 | self._wctx.addstr(31,92, u'\u0052\u0054\u004C\u005F\u004D\u004F\u0044\u0045\u004C\u005F\u0045\u0052\u0052\u005F\u0041'.encode('utf-8'), curses.color_pair(3)) 40 | self._wctx.addstr(35,92, u'\u0052\u0054\u004C\u005F\u004D\u004F\u0044\u0045\u004C\u005F\u0045\u0052\u0052\u005F\u0042'.encode('utf-8'), curses.color_pair(3)) 41 | 42 | self._wctx.refresh() 43 | -------------------------------------------------------------------------------- /lib/gadgets/gadget_fplate_sc9_class.py: -------------------------------------------------------------------------------- 1 | import curses 2 | from lib.common.gadgettop_class import gadgettop 3 | 4 | class gadget_fplate_sc9(gadgettop): 5 | 6 | def __init__(self): 7 | super().__init__() 8 | 9 | def __del__(self): 10 | super().__del__() 11 | 12 | def setup_2d_model (self, wctx): 13 | self._wctx = wctx 14 | self._wctx.erase() 15 | self._wctx.bkgd(' ', curses.color_pair(1)) 16 | self._wctx.refresh() 17 | 18 | def process_input_stimulus (self, hdlpath, key): 19 | pass 20 | 21 | def get_logic_state_data_from_simulator (self, hdlpath): 22 | pass 23 | 24 | def post_process_logic_state (self, phase): 25 | pass 26 | 27 | def write_to_log (self, strprefix, logfile): 28 | pass 29 | 30 | def drive_2d_model (self): 31 | self._wctx.addstr(1,21, u'\u0020\u0046\u0049\u0046\u004F\u005F\u0041\u0020'.encode('utf-8'), curses.color_pair(3)) 32 | self._wctx.addstr(16,21, u'\u0020\u0046\u0049\u0046\u004F\u005F\u0042\u0020'.encode('utf-8'), curses.color_pair(3)) 33 | self._wctx.addstr(1,77, u'\u0020\u0020\u0046\u0049\u0046\u004F\u0020\u0020'.encode('utf-8'), curses.color_pair(3)) 34 | self._wctx.addstr(3,49, u'\u0020\u0043\u0055\u0053\u0054\u004F\u004D\u0020'.encode('utf-8'), curses.color_pair(3)) 35 | self._wctx.addstr(4,49, u'\u0020\u004C\u004F\u0047\u0049\u0043\u0020\u0020'.encode('utf-8'), curses.color_pair(3)) 36 | self._wctx.addstr(18,78, u'\u0020\u0020\u0043\u004F\u004E\u0054\u0052\u004F\u004C\u0020\u0020'.encode('utf-8'), curses.color_pair(3)) 37 | 38 | self._wctx.refresh() 39 | -------------------------------------------------------------------------------- /lib/gadgets/gadget_modelqueue_class.py: -------------------------------------------------------------------------------- 1 | from lib.gadgets.gadget_modelqueuebase_class import gadget_modelqueuebase 2 | from lib.common.helper_class import helper 3 | 4 | class gadget_modelqueue(gadget_modelqueuebase): 5 | 6 | def __init__(self): 7 | super().__init__() 8 | 9 | def __del__(self): 10 | super().__del__() 11 | 12 | def get_logic_state_data_from_simulator (self, hdlpath): 13 | #Copy post logic state into pre logic state 14 | helper.dictcopy(self.logicstate_post, self.logicstate_pre) 15 | 16 | helper.put_hdl_vector_to_dict(self.logicstate_post['queue0'], hdlpath.queue0.value.binstr) 17 | helper.put_hdl_vector_to_dict(self.logicstate_post['queue1'], hdlpath.queue1.value.binstr) 18 | helper.put_hdl_vector_to_dict(self.logicstate_post['queue2'], hdlpath.queue2.value.binstr) 19 | self.logicstate_post['qsize'][0] = hdlpath.qsize.value.integer 20 | -------------------------------------------------------------------------------- /lib/gadgets/gadget_modelqueuea_class.py: -------------------------------------------------------------------------------- 1 | from lib.gadgets.gadget_modelqueuebase_class import gadget_modelqueuebase 2 | from lib.common.helper_class import helper 3 | 4 | class gadget_modelqueuea(gadget_modelqueuebase): 5 | 6 | def __init__(self): 7 | super().__init__() 8 | 9 | def __del__(self): 10 | super().__del__() 11 | 12 | def get_logic_state_data_from_simulator (self, hdlpath): 13 | #Copy post logic state into pre logic state 14 | helper.dictcopy(self.logicstate_post, self.logicstate_pre) 15 | 16 | helper.put_hdl_vector_to_dict(self.logicstate_post['queue0'], hdlpath.queue0_a.value.binstr) 17 | helper.put_hdl_vector_to_dict(self.logicstate_post['queue1'], hdlpath.queue1_a.value.binstr) 18 | helper.put_hdl_vector_to_dict(self.logicstate_post['queue2'], hdlpath.queue2_a.value.binstr) 19 | self.logicstate_post['qsize'][0] = hdlpath.qsize_a.value.integer 20 | -------------------------------------------------------------------------------- /lib/gadgets/gadget_modelqueueb_class.py: -------------------------------------------------------------------------------- 1 | from lib.gadgets.gadget_modelqueuebase_class import gadget_modelqueuebase 2 | from lib.common.helper_class import helper 3 | 4 | class gadget_modelqueueb(gadget_modelqueuebase): 5 | 6 | def __init__(self): 7 | super().__init__() 8 | 9 | def __del__(self): 10 | super().__del__() 11 | 12 | def get_logic_state_data_from_simulator (self, hdlpath): 13 | #Copy post logic state into pre logic state 14 | helper.dictcopy(self.logicstate_post, self.logicstate_pre) 15 | 16 | helper.put_hdl_vector_to_dict(self.logicstate_post['queue0'], hdlpath.queue0_b.value.binstr) 17 | helper.put_hdl_vector_to_dict(self.logicstate_post['queue1'], hdlpath.queue1_b.value.binstr) 18 | helper.put_hdl_vector_to_dict(self.logicstate_post['queue2'], hdlpath.queue2_b.value.binstr) 19 | self.logicstate_post['qsize'][0] = hdlpath.qsize_b.value.integer 20 | -------------------------------------------------------------------------------- /lib/scenario1_class.py: -------------------------------------------------------------------------------- 1 | import curses 2 | from lib.common.scenariotop_class import scenariotop 3 | from lib.gadgets.gadget_fifo_class import gadget_fifo 4 | from lib.gadgets.gadget_fifotr_class import gadget_fifotr 5 | from lib.gadgets.gadget_control_class import gadget_control 6 | from lib.gadgets.gadget_fplate_sc1_class import gadget_fplate_sc1 7 | 8 | class scenario1(scenariotop): 9 | 10 | def __init__(self): 11 | super().__init__() 12 | self._fifo = gadget_fifo() 13 | self._fifotr = gadget_fifotr() 14 | self._control = gadget_control() 15 | self._fplate = gadget_fplate_sc1() 16 | 17 | def __del__(self): 18 | del self._fifo 19 | del self._fifotr 20 | del self._control 21 | del self._fplate 22 | super().__del__() 23 | 24 | def setup_2d_model (self, ctx): 25 | #IN 3D VERSION THIS METHOD WILL BE USED TO PROVIDE 3D MODEL MESH, IN 2D THERE IS ONLY SUBWINDOW LAYOUTS 26 | self._ctx = ctx 27 | 28 | self._fifo.setup_2d_model(self._ctx.subwin(3, 5)) 29 | self._fifotr.setup_2d_model(self._ctx.subwin(3, 5)) 30 | self._control.setup_2d_model(self._ctx.subwin(20, 5)) 31 | self._fplate.setup_2d_model(self._ctx.subwin(0, 0)) 32 | 33 | def process_input_stimulus (self, hdl, key): 34 | self._fifo.process_input_stimulus (hdl, key) 35 | self._fifotr.process_input_stimulus (hdl, key) 36 | self._control.process_input_stimulus (hdl, key) 37 | self._fplate.process_input_stimulus (hdl, key) 38 | 39 | def get_logic_state_data_from_simulator (self, hdl): 40 | self._fifo.get_logic_state_data_from_simulator (hdl.RTL1.FIFO1) 41 | self._fifotr.get_logic_state_data_from_simulator (hdl.RTL1.FIFO1) 42 | self._control.get_logic_state_data_from_simulator (hdl) 43 | self._fplate.get_logic_state_data_from_simulator (hdl) 44 | 45 | def post_process_logic_state (self, phase): 46 | self._fifo.post_process_logic_state (phase) 47 | self._fifotr.post_process_logic_state (phase) 48 | self._control.post_process_logic_state (phase) 49 | self._fplate.post_process_logic_state (phase) 50 | 51 | def write_to_log (self, logfile): 52 | self._fifo.write_to_log ("FIFO1", logfile) 53 | self._fifotr.write_to_log ("FIFOTR1", logfile) 54 | self._control.write_to_log ("CONTROL", logfile) 55 | self._fplate.write_to_log ("FPLATE", logfile) 56 | 57 | def drive_2d_model (self): 58 | self._fifo.drive_2d_model () 59 | self._fifotr.drive_2d_model () 60 | self._control.drive_2d_model () 61 | self._fplate.drive_2d_model () 62 | -------------------------------------------------------------------------------- /sim_build/.gitignore: -------------------------------------------------------------------------------- 1 | * 2 | !.gitignore 3 | --------------------------------------------------------------------------------