├── Parallel CRC implementation └── MATLAB │ ├── README.md │ ├── W_ln_computation.m │ └── n_power_of_T.m ├── Pipelining go back algorithm ├── MATLAB │ ├── README.md │ ├── crc_go_back_new.m │ └── formatrix_new.m └── Verilog │ ├── go_back_pipe.v │ ├── go_back_stage.v │ └── lut_xor.v ├── README.md ├── Reprogramming by HWICAP ├── Python │ ├── lut_pin_map.py │ ├── map_SliceL.py │ ├── map_SliceM.py │ └── rbt_translation.py ├── TCL │ ├── Read │ │ ├── read_frame_510521.tcl │ │ ├── read_frame_510622.tcl │ │ ├── read_frame_510723.tcl │ │ └── read_frame_510824.tcl │ └── Write │ │ ├── source_write_all.tcl │ │ ├── write_frame_510521.tcl │ │ ├── write_frame_510622.tcl │ │ ├── write_frame_510723.tcl │ │ └── write_frame_510824.tcl ├── Verilog │ ├── cnt.v │ ├── ipcores │ │ ├── axi_hwicap_0.xci │ │ ├── clk_wiz_0.xci │ │ ├── ila_0.xci │ │ ├── jtag_axi_0.xci │ │ └── rst_vio.xci │ ├── jtag_axi_icap_top.v │ ├── xdc │ │ └── jtag_axi_icap.xdc │ └── xor_lut.v ├── bitstream │ ├── jtag_axi_icap_top.bit │ └── jtag_axi_icap_top.ltx └── doc │ ├── AX7103_FPGA_Board_UG.pdf │ ├── Single LUT reprogramming user guide(Chinese).pdf │ └── Single LUT reprogramming user guide(English).pdf ├── Segmented Architecture ├── rtl │ ├── crc_and_goback │ │ ├── c_xor_and_go_back.v │ │ ├── c_xor_and_go_back_top.v │ │ ├── crc_pipe_new │ │ │ ├── c_xor_lut.v │ │ │ ├── c_xor_lut_top.v │ │ │ ├── layer_1_new.v │ │ │ ├── layer_xor_new.v │ │ │ ├── layer_xor_rtl.v │ │ │ ├── lut_pipe_multi.v │ │ │ └── lut_pipe_top_new.v │ │ ├── go_back │ │ │ ├── go_back_pipe.v │ │ │ ├── go_back_stage.v │ │ │ └── lut_xor.v │ │ ├── go_back_top.v │ │ └── merge │ │ │ ├── ahead_4096.v │ │ │ ├── merge_corssbar_element.v │ │ │ ├── merge_crossbar.v │ │ │ ├── merge_element.v │ │ │ ├── merge_layer.v │ │ │ └── merge_top.v │ ├── go_back_lut5_and_stride_8 │ │ ├── go_back_lut5.v │ │ └── go_back_lut5_stride_8.v │ ├── reverse_crc.v │ └── top_64.v └── tb │ ├── crc_gen.v │ ├── data_1518bytes.v │ ├── data_512bytes.v │ ├── data_64bytes.v │ ├── data_65bytes.v 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