├── 10 Verilog Projects Book ├── Section_1 │ ├── d_ff.v │ ├── d_ff_TB.v │ ├── seq_det_101_TB.v │ ├── seq_det_101b.v │ ├── seq_det_101b_TB.v │ ├── seq_det_101c.v │ ├── seq_det_101c_TB.v │ └── sequence_detector_101.v ├── Section_10 │ ├── traffic_controller.v │ └── traffic_controller_TB.v ├── Section_2 │ ├── bin2bcd.v │ ├── bin2bcd_TB.v │ ├── byte2bcd.v │ └── byte2bcd_TB.v ├── Section_3 │ ├── fibonacci.v │ ├── fibonacci_TB.v │ ├── fibonacci_p.v │ └── fibonacci_p_TB.v ├── Section_4 │ ├── gray_counter.v │ ├── gray_counter2.v │ ├── gray_counter2_TB.v │ └── gray_counter_TB.v ├── Section_5 │ ├── alu.v │ └── alu_TB.v ├── Section_6 │ ├── rom.v │ └── rom_TB.v ├── Section_7 │ ├── ram.v │ ├── ram_TB.v │ ├── ram_p.v │ └── ram_p_TB.v ├── Section_8 │ ├── reg_file.v │ ├── reg_file_TB.v │ ├── reg_file_p.v │ └── reg_file_p_TB.v └── Section_9 │ ├── candy_machine.v │ └── candy_machine_TB.v ├── College Coursework ├── Advanced Computer Architecture Final Project │ ├── Final_Paper.docx │ ├── ISR.png │ ├── LEG_microP.png │ ├── Screenshot (146).png │ ├── Screenshot (147).png │ ├── Screenshot (158).png │ └── verilog CPU │ │ ├── ALU.v │ │ ├── bit_selector.v │ │ ├── control_unit.v │ │ ├── ram.v │ │ ├── register.v │ │ ├── register_mux.v │ │ ├── register_selector.v │ │ ├── register_set.v │ │ └── shifter.v ├── Digital Design II Final Project │ ├── Marion_traffic_controller.bat │ ├── READ_ME.txt │ ├── counter1.v │ ├── counter1_TB.v │ ├── counter2.v │ ├── counter2_TB.v │ ├── counter3.v │ ├── counter3_TB.v │ ├── counter4.v │ ├── counter5.v │ ├── counter6.v │ ├── decoder_TB.v │ ├── light_control.v │ ├── light_control_TB.v │ ├── light_decoder.v │ ├── light_decoder2.v │ ├── light_fsm.v │ ├── light_fsm2.v │ ├── light_fsm2_TB.v │ ├── light_fsm_TB.v │ ├── ms_dff.v │ ├── schematics_tc.pdf │ ├── sensor_mode.v │ ├── sensor_mode_TB.v │ ├── srl.v │ ├── srl_TB.v │ ├── timer_mode.v │ ├── timer_mode_TB.v │ ├── traffic_controller.pptx │ ├── traffic_controller.v │ ├── traffic_controller_TB.v │ ├── wdws_decoder.v │ ├── wdwt_decoder_Maj.v │ └── wdwt_decoder_min.v ├── candy_machine.v ├── ms_dff.v ├── ms_dff_TB.v ├── seq_det101s.v └── seq_det101s_TB.v ├── Digital Systems Information ├── ADT7420.pdf ├── ADXL362.pdf ├── CheatSheetCollection.pdf ├── DF_Player_Mini_Datasheet.pdf ├── HDMI_Demystified_rev_1_02.pdf ├── SSD1306.pdf ├── W65C816SXB.pdf ├── WDC 65c02SXB │ ├── TIDE Users Guide.pdf │ ├── W65C02SXB.pdf │ ├── w65c02s.pdf │ ├── w65c21.pdf │ ├── w65c22.pdf │ └── w65c51n.pdf ├── i2c_master_design.pdf ├── i2c_spec.pdf ├── spi_spec.pdf └── uart_spec.pdf ├── FPGA Projects ├── Arduino to Basys 3 Test │ ├── Arduino2FPGA_blink_test.ino │ ├── const_ard2fpga.xdc │ └── top.v ├── Basys3_PmodTMP2_Temp_Sensor │ ├── add_32.v │ ├── clkgen_200KHz.v │ ├── const_temp_sensor.xdc │ ├── divide_by_5.v │ ├── i2c_master.v │ ├── multiply_by_9.v │ ├── seg7.v │ ├── temp_converter.v │ └── top.v ├── Binary Clock(leds on breadboard) │ ├── README.txt │ ├── btn_debouncer.v │ ├── const_binary_clock.xdc │ ├── hours.v │ ├── minutes.v │ ├── oneHz_generator.v │ ├── seconds.v │ └── top_clock.v ├── Byte Calculator │ ├── README.txt │ ├── btn_debouncer.v │ ├── byte_calculator.v │ ├── const_byte_calulator.xdc │ └── top.v ├── Candy_Machine_Basys3 │ ├── btn_debounce.v │ ├── const_candy_machine.xdc │ ├── conv2bcd.v │ ├── led_driver.v │ ├── seg7_control.v │ ├── state_machine.v │ ├── tenHz_gen.v │ ├── tenHz_generator.v │ ├── top.v │ └── twoHz_gen.v ├── Coffee Machine No 2(upgraded) │ ├── Coffee_Machine_on_BASYS3.pptx │ ├── README.txt │ ├── btn_debouncer.v │ ├── const_cm.xdc │ ├── mux2x1.v │ ├── oneHz_gen.v │ ├── seg7_control.v │ ├── state_machine.v │ └── top.v ├── Coffee Machine Simulator(Keurig) │ ├── README.txt │ ├── btn_debouncer.v │ ├── const_sm.xdc │ ├── oneHz_gen.v │ ├── seg7_control.v │ ├── state_machine.v │ └── top.v ├── Cora Z7 RGB w PWM │ ├── const_cora_rgbs.xdc │ └── rgb_driver.v ├── D Flip Flop Basys 3 │ ├── const_d_ff.xdc │ ├── d_ff.v │ └── sim_d_ff.v ├── Decoder 4x16 │ ├── decoder4x16.v │ └── decoder4x16_constraints.xdc ├── Encoder 16bit │ ├── encoder16.v │ └── encoder16_constraints.xdc ├── FIFO │ ├── const_fifo_test.xdc │ ├── debounce_explicit.v │ ├── fifo.v │ └── fifo_test.v ├── Gray Code Counter │ ├── const_gray.xdc │ ├── gray_counter.v │ ├── oneHz_gen.v │ ├── sim_gray.v │ └── top.v ├── How to Control 7 Segment Display on Basys 3 │ ├── const_learn_7seg.xdc │ ├── digits.v │ ├── seg7_control.v │ ├── tenHz_gen.v │ └── top.v ├── How to Control PMOD KYPD Basys 3 │ ├── const_keypad.xdc │ ├── decoder.v │ ├── seg7_control.v │ └── top.v ├── Improved I2C Nexys A7 Temperature Sensor │ ├── add_32.v │ ├── clkgen_200KHz.v │ ├── const_temp_sensor_improved.xdc │ ├── divide_by_5.v │ ├── i2c_master.v │ ├── multiply_by_9.v │ ├── seg7c.v │ ├── temp_converter.v │ └── top.v ├── Johnson Counter 4-bit │ ├── const_johnson_counter.xdc │ ├── johnson_counter.v │ ├── oneHz_gen.v │ └── top.v ├── LFSR 4-bit │ ├── const_lfsr4.xdc │ ├── lfsr4.v │ ├── lfsr_top.v │ └── oneHz_gen.v ├── NEW 7 Segment Clock with NEW Binary Clock Core │ ├── binary_clock.v │ ├── const_new_7seg_clk.xdc │ ├── seg_control.v │ └── top.v ├── Nexys A7 3-Axis Accelerometer SPI │ ├── const_accelerometer.xdc │ ├── iclk_gen.v │ ├── seg7_control.v │ ├── spi_master.v │ └── top.v ├── Nexys to Basys Test 1(ROM to RAM) │ ├── Basys3 part │ │ ├── const_ram.xdc │ │ └── ram.v │ └── Nexys Video part │ │ ├── const_rom.xdc │ │ ├── nexys_top.v │ │ ├── oneHz_gen.v │ │ ├── rom.v │ │ └── rom_control.v ├── NexysA7_Temp_Sensor_I2C │ ├── clkgen_200kHz.v │ ├── const_temp_sensor.xdc │ ├── i2c_master.v │ ├── i2c_master_TB.v │ ├── seg7.v │ └── top.v ├── PicoBlaze Microcontroller │ ├── Intro to PicoBlaze │ │ ├── First_PicoBlaze_assembly_program.psm │ │ ├── const_first_picoblaze.xdc │ │ └── p_blaze_top.v │ └── Sum of Squares │ │ ├── const_square.xdc │ │ ├── square.psm │ │ └── squares_top.v ├── PmodENC │ ├── const_encoder.xdc │ ├── debounce.v │ ├── encoder.v │ ├── seg7_control.v │ └── top.v ├── RGB LED Controller │ ├── README.txt │ ├── RGB_controller.v │ └── RGB_controller_constraints.xdc ├── Seven Segment Clock Basys 3(segs on basys3) │ ├── bin2bcd.v │ ├── btn_debouncer.v │ ├── const_7seg_clock.xdc │ ├── hours.v │ ├── minutes.v │ ├── oneHz_generator.v │ ├── seconds.v │ ├── seg7_control.v │ ├── top_7seg_clock.v │ └── top_bin_clock.v ├── Seven Segment Clock Basys 3(segs on breadboard) │ ├── README.txt │ ├── btn_debouncer.v │ ├── const_clock.xdc │ ├── hours.v │ ├── minutes.v │ ├── mux2x1.v │ ├── oneHz_generator.v │ ├── seconds.v │ ├── seg_control.v │ ├── seg_decoder.v │ ├── seg_demux.v │ ├── seg_hr0.v │ ├── seg_hr1.v │ ├── seg_min0.v │ ├── seg_min1.v │ ├── seg_mux.v │ └── top_clock.v ├── Star Wars Imperial March Song │ ├── a_440Hz.v │ ├── cH_523Hz.v │ ├── const_song.xdc │ ├── eH_659Hz.v │ ├── fH_698Hz.v │ ├── f_349Hz.v │ ├── gS_415Hz.v │ └── song_top.v ├── Stopwatch_Timer on Nexys A7 │ ├── const_stop_watch.xdc │ ├── seg_display_driver.v │ ├── stop_watch.v │ └── top.v ├── Traffic_Controller_Basys3 │ ├── README.txt │ ├── const_traffic_controller.xdc │ ├── oneHz_gen.v │ ├── state_machine.v │ ├── sw_debounce.v │ └── traffic_controller.v ├── UART │ ├── baud_rate_generator.v │ ├── debounce_explicit.v │ ├── fifo.v │ ├── uart_const.xdc │ ├── uart_receiver.v │ ├── uart_test.v │ ├── uart_top.v │ └── uart_transmitter.v ├── VGA Projects │ ├── Frogger_pt1 │ │ ├── const_frogger1.xdc │ │ ├── debounce.v │ │ ├── pixel_gen.v │ │ ├── top.v │ │ └── vga_controller.v │ ├── Pong pt1 │ │ ├── ball_rom.v │ │ ├── const_pong1.xdc │ │ ├── debounce.v │ │ ├── pixel_gen.v │ │ ├── top.v │ │ └── vga_controller.v │ ├── Pong pt2 │ │ ├── ascii_rom.v │ │ ├── const_pong2.xdc │ │ ├── m100_counter.v │ │ ├── pong_graph.v │ │ ├── pong_text.v │ │ ├── pong_top.v │ │ ├── timer.v │ │ └── vga_controller.v │ ├── Pong pt3 │ │ ├── ascii_rom.v │ │ ├── const_pong3.xdc │ │ ├── m100_counter.v │ │ ├── nes_controller.v │ │ ├── pong_graph.v │ │ ├── pong_text.v │ │ ├── pong_top.v │ │ ├── timer.v │ │ └── vga_controller.v │ ├── VGA Bouncing Square │ │ ├── const_rgb_square.xdc │ │ ├── pixel_generation.v │ │ ├── top.v │ │ └── vga_controller.v │ ├── VGA Clock and Calendar │ │ ├── calendar.v │ │ ├── clock_digit_rom.v │ │ ├── const_vga_clk_cal.xdc │ │ ├── design_top.v │ │ ├── new_binary_clock.v │ │ ├── pixel_gen.v │ │ ├── top_clk_cal.v │ │ └── vga_controller.v │ ├── VGA Controller │ │ ├── const_vga.xdc │ │ ├── vga_controller.v │ │ └── vga_test.v │ ├── VGA Digital Clock │ │ ├── clock_digit_rom.v │ │ ├── const_vga_clock.xdc │ │ ├── new_binary_clock.v │ │ ├── pixel_clk_gen.v │ │ ├── top.v │ │ └── vga_controller.v │ ├── VGA Full Screen Text Editor │ │ ├── ascii_rom.v │ │ ├── const_text_gen.xdc │ │ ├── debounce.v │ │ ├── simple_dual_one_clock.v │ │ ├── text_screen_gen.v │ │ ├── top.v │ │ └── vga_controller.v │ ├── VGA No Signal Screen │ │ ├── const_vga_no_sig.xdc │ │ ├── pixel_generation.v │ │ ├── top.v │ │ └── vga_controller.v │ ├── VGA PmodENC │ │ ├── const_encoder.xdc │ │ ├── debounce.v │ │ ├── encoder.v │ │ ├── pixel_gen.v │ │ ├── seg7_control.v │ │ ├── top.v │ │ └── vga_controller.v │ ├── VGA Text Generation │ │ ├── ascii_rom.v │ │ ├── ascii_test.v │ │ ├── const_ascii_test.xdc │ │ ├── top.v │ │ └── vga_controller.v │ ├── VGA_std_800x600_72Hz │ │ └── vga_controller800x600.v │ └── frogger_pt2 │ │ ├── btn_debounce.v │ │ ├── const_frogger_pt2.xdc │ │ ├── frog_down.bmp │ │ ├── frog_down_rom.v │ │ ├── frog_left.bmp │ │ ├── frog_left_rom.v │ │ ├── frog_right.bmp │ │ ├── frog_right_rom.v │ │ ├── frog_up.bmp │ │ ├── frog_up_rom.v │ │ ├── pixel_gen.v │ │ ├── python_image2verilog.py │ │ ├── top.v │ │ └── vga_controller.v └── Voting Machine Basys3 │ ├── bin2bcd.v │ ├── btn_debounce.v │ ├── const_voting_machine.xdc │ ├── led_driver.v │ ├── oneHz_gen.v │ ├── seg7_control.v │ ├── state_machine.v │ ├── top_voting_machine.v │ └── twoHz_gen.v ├── IEEE.1364-2005.pdf ├── LICENSE ├── Learning VHDL ├── BASYS_3_FPGA │ ├── const_decoder3x8.xdc │ ├── const_decoder3x8_cond.xdc │ ├── const_decoder3x8_sel.xdc │ ├── decoder3x8.vhd │ ├── decoder3x8_conditional.vhd │ └── decoder3x8_selected.vhd └── Logic Gates Module │ ├── README.txt │ ├── and_gate.vhd │ ├── const_VHDL_gates.xdc │ ├── nand_gate.vhd │ ├── nor_gate.vhd │ ├── or_gate.vhd │ ├── top_gates.vhd │ ├── xnor_gate.vhd │ └── xor_gate.vhd ├── Master XDCs and Reference Manuals ├── BASYS3_MasterXDC.xdc ├── CORA_Master_XDC.xdc ├── Cmod-A7-Master.xdc ├── Nexys-A7-50T-Master.xdc ├── Nexys_Video_MasterXDC.xdc ├── Reference Manuals and User Guides │ ├── FPGAs │ │ ├── ZyboXADC_tutorial.pdf │ │ ├── basys3_rm.pdf │ │ ├── cmod_a7_rm.pdf │ │ ├── nexys-a7-sch.pdf │ │ ├── nexys-a7_rm.pdf │ │ ├── nexys_video_rm.pdf │ │ └── zybo-z7_rm.pdf │ ├── Microblaze Processor │ │ ├── microblaze-product-brief.pdf │ │ └── microblaze-quick-start-guide-with-vitis.pdf │ ├── PMODs │ │ ├── pmodacl2_rm.pdf │ │ ├── pmodals_rm.pdf │ │ ├── pmodbt2_rm.pdf │ │ ├── pmodcon3_rm.pdf │ │ ├── pmodenc_rm.pdf │ │ ├── pmodkypd_rm.pdf │ │ ├── pmodoled_rm.pdf │ │ ├── pmodstep_rm.pdf │ │ ├── pmodtmp2_rm.pdf │ │ ├── pmodtmp3_rm.pdf │ │ └── pmodwifi_rm.pdf │ ├── Picoblaze Microcontroller │ │ ├── picoblaze_productbrief.pdf │ │ ├── ug129_PicoBlaze.pdf │ │ └── usingPicoblazeinFPGA.pdf │ ├── VIVADO_USER_GUIDE_2021.2.pdf │ ├── gs0001-xilinx-ch-4-hdl-coding-techniques.pdf │ ├── state_machines.pdf │ ├── ug480_7Series_XADC.pdf │ ├── ug900-vivado-logic-simulation.pdf │ ├── ug901-Vivado-Synthesis.pdf │ ├── ug903-vivado-using-constraints.pdf │ └── ug904-Vivado-Implementation.pdf └── Zybo-Z7-Master.xdc ├── Microprocessor CPU Series └── 7 Step Processor │ ├── ASM_BIN_ROM_Files │ ├── INSTRUCTIONS.txt │ ├── bin2rom.py │ ├── fibonacci.asm │ ├── fibonacci.bin │ ├── fibonacci_rom.v │ ├── rom_TB.v │ ├── sum5.asm │ ├── sum5.bin │ └── sum5_rom.v │ ├── Assembler │ ├── AssemblyLanguage1.png │ ├── AssemblyLanguage2.png │ ├── AssemblyLanguage3.png │ ├── Makefile │ ├── asmbl.exe │ ├── asmbl.h │ ├── asmbl.l │ ├── asmbl.tab.c │ ├── asmbl.tab.h │ ├── asmbl.txt │ ├── asmbl.y │ ├── assembly.links.text │ └── lex.yy.c │ ├── CPU_Information │ ├── CPU_A.jpg │ ├── CPU_B_Design.png │ ├── Control_image_marked_up.jpg │ ├── InstructionSet.jpg │ ├── instruction_set.txt │ └── programming_language.txt │ ├── Test_Benches │ ├── acc_TB.v │ ├── alu_TB.v │ ├── bus1_TB.v │ ├── clock_gen_TB.v │ ├── control_TB.v │ ├── data_bus_TB.v │ ├── flags_TB.v │ ├── fsm_load_ram_TB.v │ ├── gpr_file_TB.v │ ├── iar_TB.v │ ├── io_TB.v │ ├── ir_TB.v │ ├── ram_TB.v │ ├── rom_TB.v │ ├── stepper_TB.v │ └── tmp_TB.v │ ├── acc.v │ ├── alu.v │ ├── bus1.v │ ├── clock_gen.v │ ├── control.v │ ├── control_init.v │ ├── cpu_b.v │ ├── cpu_b_init.v │ ├── cpu_b_test.v │ ├── cpu_b_test_list.txt │ ├── cpu_init.v │ ├── data_bus.v │ ├── dec2x4.v │ ├── dec3x8.v │ ├── flags.v │ ├── fsm_load_ram.v │ ├── gpr.v │ ├── gpr_file.v │ ├── iar.v │ ├── io.v │ ├── ir.v │ ├── ram.v │ ├── stepper.v │ └── tmp.v ├── Modules with Simulations ├── Binary to BCD Converter │ ├── byte2bcd.v │ └── sim_byte2bcd.v ├── Fibonacci Sequence Generator │ ├── Fibonacci in Logisim │ │ └── Fibonacci_Sequence_Generator_Circuit.circ │ ├── fibonacci.v │ └── sim_fibonacci.v ├── Multiplexer 4x1 Parameterized │ ├── mux4x1.v │ └── sim_4x1mux.v ├── PWM Generator │ ├── pwm_gen.v │ └── sim_pwm_gen.v ├── Register File │ ├── reg_file.v │ └── sim_reg_file.v ├── SR Latch │ ├── sim_sr_latch.v │ └── sr_latch.v ├── Sequence Detector D-Flip Flops │ ├── d_ff.v │ ├── seq_det_101.v │ └── seq_det_101_TB.v ├── Sequence Detector Shift Register │ ├── seq_det_101.v │ └── seq_det_101_TB.v ├── Sequence Detector State Machine │ ├── seq_det_101_fsm.v │ └── seq_det_101_fsm_TB.v ├── Simple ALU │ ├── alu.v │ └── sim_alu.v └── Verilog Switch Level Modeling │ ├── cmos_gates.v │ └── sim_cmos.v ├── On_My_Bookshelf.txt ├── Other Projects ├── Daily Countdown Timer Arduino │ └── day_countdown_timer3.ino ├── Star Trek Clock │ ├── 0001.mp3 │ ├── 0002.mp3 │ ├── 0003.mp3 │ ├── 0004.mp3 │ ├── Star_Trek_Clock_ONE_NANO │ │ └── Star_Trek_Clock_ONE_NANO.ino │ ├── Star_Trek_Clock_Schematic.fzz │ ├── parts_list.xlsx │ ├── speaker_bottom-Body.stl │ ├── speaker_bottom.FCStd │ ├── speaker_top-Body.stl │ ├── speaker_top.FCStd │ ├── star_trek_clock_bottom-Body.stl │ ├── star_trek_clock_bottom.FCStd │ ├── star_trek_clock_top-Body.stl │ └── star_trek_clock_top.FCStd └── basic_binary_clock │ ├── basic_arduino_binary_clock.png │ └── basic_binary_clock.ino ├── README.md ├── University Senior Class Design Project ├── README.txt ├── clock_source.v ├── counter32.v ├── oversampler_DFF.v ├── pwm_generator.v ├── shift_reg184.v └── shift_reg376.v └── Verilog Introductory Tutorial Book ├── AND_gate.v ├── D_ff.v ├── D_ff_TB.v ├── D_ff_beh.v ├── D_ff_beh_TB.v ├── NAND_gate.v ├── NAND_gate2.v ├── NAND_gate2_TB.v ├── NAND_gate_TB.v ├── OR_gate.v ├── binary_counter3.v ├── binary_counter3_TB.v ├── decoder_3x8.v ├── decoder_3x8_TB.v ├── mod100_counter.v ├── mod100_counterEX.v ├── mod100_counter_TB.v ├── modular_verilog.v ├── modular_verilog_TB.v ├── mux_4x1.v ├── mux_4x1_TB.v ├── your_phone.v └── your_phone2.v /10 Verilog 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