├── 10 Verilog Projects Book ├── Section_1 │ ├── d_ff.v │ ├── d_ff_TB.v │ ├── seq_det_101_TB.v │ ├── seq_det_101b.v │ ├── seq_det_101b_TB.v │ ├── seq_det_101c.v │ ├── seq_det_101c_TB.v │ └── sequence_detector_101.v ├── Section_10 │ ├── traffic_controller.v │ └── traffic_controller_TB.v ├── Section_2 │ ├── bin2bcd.v │ ├── bin2bcd_TB.v │ ├── byte2bcd.v │ └── byte2bcd_TB.v ├── Section_3 │ ├── fibonacci.v │ ├── fibonacci_TB.v │ ├── fibonacci_p.v │ └── fibonacci_p_TB.v ├── Section_4 │ ├── gray_counter.v │ ├── gray_counter2.v │ ├── gray_counter2_TB.v │ └── gray_counter_TB.v ├── Section_5 │ ├── alu.v │ └── alu_TB.v ├── Section_6 │ ├── rom.v │ └── rom_TB.v ├── Section_7 │ ├── ram.v │ ├── ram_TB.v │ ├── ram_p.v │ └── ram_p_TB.v ├── Section_8 │ ├── reg_file.v │ ├── reg_file_TB.v │ ├── reg_file_p.v │ └── reg_file_p_TB.v └── Section_9 │ ├── candy_machine.v │ └── candy_machine_TB.v ├── College Coursework ├── Advanced Computer Architecture Final Project │ ├── Final_Paper.docx │ ├── ISR.png │ ├── LEG_microP.png │ ├── Screenshot (146).png │ ├── Screenshot (147).png │ ├── Screenshot (158).png │ └── verilog CPU │ │ ├── ALU.v │ │ ├── bit_selector.v │ │ ├── control_unit.v │ │ ├── ram.v │ │ ├── register.v │ │ ├── register_mux.v │ │ ├── register_selector.v │ │ ├── register_set.v │ │ └── shifter.v ├── Digital Design II Final Project │ ├── Marion_traffic_controller.bat │ ├── READ_ME.txt │ ├── counter1.v │ ├── counter1_TB.v │ ├── counter2.v │ ├── counter2_TB.v │ ├── counter3.v │ ├── counter3_TB.v │ ├── counter4.v │ ├── counter5.v │ ├── counter6.v │ ├── decoder_TB.v │ ├── light_control.v │ ├── light_control_TB.v │ ├── light_decoder.v │ ├── light_decoder2.v │ ├── light_fsm.v │ ├── light_fsm2.v │ ├── light_fsm2_TB.v │ ├── light_fsm_TB.v │ ├── ms_dff.v │ ├── schematics_tc.pdf │ ├── sensor_mode.v │ ├── sensor_mode_TB.v │ ├── srl.v │ ├── srl_TB.v │ ├── timer_mode.v │ ├── timer_mode_TB.v │ ├── traffic_controller.pptx │ ├── traffic_controller.v │ ├── traffic_controller_TB.v │ ├── wdws_decoder.v │ ├── wdwt_decoder_Maj.v │ └── wdwt_decoder_min.v ├── candy_machine.v ├── ms_dff.v ├── ms_dff_TB.v ├── seq_det101s.v └── seq_det101s_TB.v ├── Digital Systems Information ├── ADT7420.pdf ├── ADXL362.pdf ├── CheatSheetCollection.pdf ├── DF_Player_Mini_Datasheet.pdf ├── HDMI_Demystified_rev_1_02.pdf ├── SSD1306.pdf ├── W65C816SXB.pdf ├── WDC 65c02SXB │ ├── TIDE Users Guide.pdf │ ├── W65C02SXB.pdf │ ├── w65c02s.pdf │ ├── w65c21.pdf │ ├── w65c22.pdf │ └── w65c51n.pdf ├── i2c_master_design.pdf ├── i2c_spec.pdf ├── spi_spec.pdf └── uart_spec.pdf ├── FPGA Projects ├── Arduino to Basys 3 Test │ ├── Arduino2FPGA_blink_test.ino │ ├── const_ard2fpga.xdc │ └── top.v ├── Basys3_PmodTMP2_Temp_Sensor │ ├── add_32.v │ ├── clkgen_200KHz.v │ ├── const_temp_sensor.xdc │ ├── divide_by_5.v │ ├── i2c_master.v │ ├── multiply_by_9.v │ ├── seg7.v │ ├── temp_converter.v │ └── top.v ├── Binary Clock(leds on breadboard) │ ├── README.txt │ ├── btn_debouncer.v │ ├── const_binary_clock.xdc │ ├── hours.v │ ├── minutes.v │ ├── oneHz_generator.v │ ├── seconds.v │ └── top_clock.v ├── Byte Calculator │ ├── README.txt │ ├── btn_debouncer.v │ ├── byte_calculator.v │ ├── const_byte_calulator.xdc │ └── top.v ├── Candy_Machine_Basys3 │ ├── btn_debounce.v │ ├── const_candy_machine.xdc │ ├── conv2bcd.v │ ├── led_driver.v │ ├── seg7_control.v │ ├── state_machine.v │ ├── tenHz_gen.v │ ├── tenHz_generator.v │ ├── top.v │ └── twoHz_gen.v ├── Coffee Machine No 2(upgraded) │ ├── Coffee_Machine_on_BASYS3.pptx │ ├── README.txt │ ├── btn_debouncer.v │ ├── const_cm.xdc │ ├── mux2x1.v │ ├── oneHz_gen.v │ ├── seg7_control.v │ ├── state_machine.v │ └── top.v ├── Coffee Machine Simulator(Keurig) │ ├── README.txt │ ├── btn_debouncer.v │ ├── const_sm.xdc │ ├── oneHz_gen.v │ ├── seg7_control.v │ ├── state_machine.v │ └── top.v ├── Cora Z7 RGB w PWM │ ├── const_cora_rgbs.xdc │ └── rgb_driver.v ├── D Flip Flop Basys 3 │ ├── const_d_ff.xdc │ ├── d_ff.v │ └── sim_d_ff.v ├── Decoder 4x16 │ ├── decoder4x16.v │ └── decoder4x16_constraints.xdc ├── Encoder 16bit │ ├── encoder16.v │ └── encoder16_constraints.xdc ├── FIFO │ ├── const_fifo_test.xdc │ ├── debounce_explicit.v │ ├── fifo.v │ └── fifo_test.v ├── Gray Code Counter │ ├── const_gray.xdc │ ├── gray_counter.v │ ├── oneHz_gen.v │ ├── sim_gray.v │ └── top.v ├── How to Control 7 Segment Display on Basys 3 │ ├── const_learn_7seg.xdc │ ├── digits.v │ ├── seg7_control.v │ ├── tenHz_gen.v │ └── top.v ├── How to Control PMOD KYPD Basys 3 │ ├── const_keypad.xdc │ ├── decoder.v │ ├── seg7_control.v │ └── top.v ├── Improved I2C Nexys A7 Temperature Sensor │ ├── add_32.v │ ├── clkgen_200KHz.v │ ├── const_temp_sensor_improved.xdc │ ├── divide_by_5.v │ ├── i2c_master.v │ ├── multiply_by_9.v │ ├── seg7c.v │ ├── temp_converter.v │ └── top.v ├── Johnson Counter 4-bit │ ├── const_johnson_counter.xdc │ ├── johnson_counter.v │ ├── oneHz_gen.v │ └── top.v ├── LFSR 4-bit │ ├── const_lfsr4.xdc │ ├── lfsr4.v │ ├── lfsr_top.v │ └── oneHz_gen.v ├── NEW 7 Segment Clock with NEW Binary Clock Core │ ├── binary_clock.v │ ├── const_new_7seg_clk.xdc │ ├── seg_control.v │ └── top.v ├── Nexys A7 3-Axis Accelerometer SPI │ ├── const_accelerometer.xdc │ ├── iclk_gen.v │ ├── seg7_control.v │ ├── spi_master.v │ └── top.v ├── Nexys to Basys Test 1(ROM to RAM) │ ├── Basys3 part │ │ ├── const_ram.xdc │ │ └── ram.v │ └── Nexys Video part │ │ ├── const_rom.xdc │ │ ├── nexys_top.v │ │ ├── oneHz_gen.v │ │ ├── rom.v │ │ └── rom_control.v ├── NexysA7_Temp_Sensor_I2C │ ├── clkgen_200kHz.v │ ├── const_temp_sensor.xdc │ ├── i2c_master.v │ ├── i2c_master_TB.v │ ├── seg7.v │ └── top.v ├── PicoBlaze Microcontroller │ ├── Intro to PicoBlaze │ │ ├── First_PicoBlaze_assembly_program.psm │ │ ├── const_first_picoblaze.xdc │ │ └── p_blaze_top.v │ └── Sum of Squares │ │ ├── const_square.xdc │ │ ├── square.psm │ │ └── squares_top.v ├── PmodENC │ ├── const_encoder.xdc │ ├── debounce.v │ ├── encoder.v │ ├── seg7_control.v │ └── top.v ├── RGB LED Controller │ ├── README.txt │ ├── RGB_controller.v │ └── RGB_controller_constraints.xdc ├── Seven Segment Clock Basys 3(segs on basys3) │ ├── bin2bcd.v │ ├── btn_debouncer.v │ ├── const_7seg_clock.xdc │ ├── hours.v │ ├── minutes.v │ ├── oneHz_generator.v │ ├── seconds.v │ ├── seg7_control.v │ ├── top_7seg_clock.v │ └── top_bin_clock.v ├── Seven Segment Clock Basys 3(segs on breadboard) │ ├── README.txt │ ├── btn_debouncer.v │ ├── const_clock.xdc │ ├── hours.v │ ├── minutes.v │ ├── mux2x1.v │ ├── oneHz_generator.v │ ├── seconds.v │ ├── seg_control.v │ ├── seg_decoder.v │ ├── seg_demux.v │ ├── seg_hr0.v │ ├── seg_hr1.v │ ├── seg_min0.v │ ├── seg_min1.v │ ├── seg_mux.v │ └── top_clock.v ├── Star Wars Imperial March Song │ ├── a_440Hz.v │ ├── cH_523Hz.v │ ├── const_song.xdc │ ├── eH_659Hz.v │ ├── fH_698Hz.v │ ├── f_349Hz.v │ ├── gS_415Hz.v │ └── song_top.v ├── Stopwatch_Timer on Nexys A7 │ ├── const_stop_watch.xdc │ ├── seg_display_driver.v │ ├── stop_watch.v │ └── top.v ├── Traffic_Controller_Basys3 │ ├── README.txt │ ├── const_traffic_controller.xdc │ ├── oneHz_gen.v │ ├── state_machine.v │ ├── sw_debounce.v │ └── traffic_controller.v ├── UART │ ├── baud_rate_generator.v │ ├── debounce_explicit.v │ ├── fifo.v │ ├── uart_const.xdc │ ├── uart_receiver.v │ ├── uart_test.v │ ├── uart_top.v │ └── uart_transmitter.v ├── VGA Projects │ ├── Frogger_pt1 │ │ ├── const_frogger1.xdc │ │ ├── debounce.v │ │ ├── pixel_gen.v │ │ ├── top.v │ │ └── vga_controller.v │ ├── Pong pt1 │ │ ├── ball_rom.v │ │ ├── const_pong1.xdc │ │ ├── debounce.v │ │ ├── pixel_gen.v │ │ ├── top.v │ │ └── vga_controller.v │ ├── Pong pt2 │ │ ├── ascii_rom.v │ │ ├── const_pong2.xdc │ │ ├── m100_counter.v │ │ ├── pong_graph.v │ │ ├── pong_text.v │ │ ├── pong_top.v │ │ ├── timer.v │ │ └── vga_controller.v │ ├── Pong pt3 │ │ ├── ascii_rom.v │ │ ├── const_pong3.xdc │ │ ├── m100_counter.v │ │ ├── nes_controller.v │ │ ├── pong_graph.v │ │ ├── pong_text.v │ │ ├── pong_top.v │ │ ├── timer.v │ │ └── vga_controller.v │ ├── VGA Bouncing Square │ │ ├── const_rgb_square.xdc │ │ ├── pixel_generation.v │ │ ├── top.v │ │ └── vga_controller.v │ ├── VGA Clock and Calendar │ │ ├── calendar.v │ │ ├── clock_digit_rom.v │ │ ├── const_vga_clk_cal.xdc │ │ ├── design_top.v │ │ ├── new_binary_clock.v │ │ ├── pixel_gen.v │ │ ├── top_clk_cal.v │ │ └── vga_controller.v │ ├── VGA Controller │ │ ├── const_vga.xdc │ │ ├── vga_controller.v │ │ └── vga_test.v │ ├── VGA Digital Clock │ │ ├── clock_digit_rom.v │ │ ├── const_vga_clock.xdc │ │ ├── new_binary_clock.v │ │ ├── pixel_clk_gen.v │ │ ├── top.v │ │ └── vga_controller.v │ ├── VGA Full Screen Text Editor │ │ ├── ascii_rom.v │ │ ├── const_text_gen.xdc │ │ ├── debounce.v │ │ ├── simple_dual_one_clock.v │ │ ├── text_screen_gen.v │ │ ├── top.v │ │ └── vga_controller.v │ ├── VGA No Signal Screen │ │ ├── const_vga_no_sig.xdc │ │ ├── pixel_generation.v │ │ ├── top.v │ │ └── vga_controller.v │ ├── VGA PmodENC │ │ ├── const_encoder.xdc │ │ ├── debounce.v │ │ ├── encoder.v │ │ ├── pixel_gen.v │ │ ├── seg7_control.v │ │ ├── top.v │ │ └── vga_controller.v │ ├── VGA Text Generation │ │ ├── ascii_rom.v │ │ ├── ascii_test.v │ │ ├── const_ascii_test.xdc │ │ ├── top.v │ │ └── vga_controller.v │ ├── VGA_std_800x600_72Hz │ │ └── vga_controller800x600.v │ └── frogger_pt2 │ │ ├── btn_debounce.v │ │ ├── const_frogger_pt2.xdc │ │ ├── frog_down.bmp │ │ ├── frog_down_rom.v │ │ ├── frog_left.bmp │ │ ├── frog_left_rom.v │ │ ├── frog_right.bmp │ │ ├── frog_right_rom.v │ │ ├── frog_up.bmp │ │ ├── frog_up_rom.v │ │ ├── pixel_gen.v │ │ ├── python_image2verilog.py │ │ ├── top.v │ │ └── vga_controller.v └── Voting Machine Basys3 │ ├── bin2bcd.v │ ├── btn_debounce.v │ ├── const_voting_machine.xdc │ ├── led_driver.v │ ├── oneHz_gen.v │ ├── seg7_control.v │ ├── state_machine.v │ ├── top_voting_machine.v │ └── twoHz_gen.v ├── IEEE.1364-2005.pdf ├── LICENSE ├── Learning VHDL ├── BASYS_3_FPGA │ ├── const_decoder3x8.xdc │ ├── const_decoder3x8_cond.xdc │ ├── const_decoder3x8_sel.xdc │ ├── decoder3x8.vhd │ ├── decoder3x8_conditional.vhd │ └── decoder3x8_selected.vhd └── Logic Gates Module │ ├── README.txt │ ├── and_gate.vhd │ ├── const_VHDL_gates.xdc │ ├── nand_gate.vhd │ ├── nor_gate.vhd │ ├── or_gate.vhd │ ├── top_gates.vhd │ ├── xnor_gate.vhd │ └── xor_gate.vhd ├── Master XDCs and Reference Manuals ├── BASYS3_MasterXDC.xdc ├── CORA_Master_XDC.xdc ├── Cmod-A7-Master.xdc ├── Nexys-A7-50T-Master.xdc ├── Nexys_Video_MasterXDC.xdc ├── Reference Manuals and User Guides │ ├── FPGAs │ │ ├── ZyboXADC_tutorial.pdf │ │ ├── basys3_rm.pdf │ │ ├── cmod_a7_rm.pdf │ │ ├── nexys-a7-sch.pdf │ │ ├── nexys-a7_rm.pdf │ │ ├── nexys_video_rm.pdf │ │ └── zybo-z7_rm.pdf │ ├── Microblaze Processor │ │ ├── microblaze-product-brief.pdf │ │ └── microblaze-quick-start-guide-with-vitis.pdf │ ├── PMODs │ │ ├── pmodacl2_rm.pdf │ │ ├── pmodals_rm.pdf │ │ ├── pmodbt2_rm.pdf │ │ ├── pmodcon3_rm.pdf │ │ ├── pmodenc_rm.pdf │ │ ├── pmodkypd_rm.pdf │ │ ├── pmodoled_rm.pdf │ │ ├── pmodstep_rm.pdf │ │ ├── pmodtmp2_rm.pdf │ │ ├── pmodtmp3_rm.pdf │ │ └── pmodwifi_rm.pdf │ ├── Picoblaze Microcontroller │ │ ├── picoblaze_productbrief.pdf │ │ ├── ug129_PicoBlaze.pdf │ │ └── usingPicoblazeinFPGA.pdf │ ├── VIVADO_USER_GUIDE_2021.2.pdf │ ├── gs0001-xilinx-ch-4-hdl-coding-techniques.pdf │ ├── state_machines.pdf │ ├── ug480_7Series_XADC.pdf │ ├── ug900-vivado-logic-simulation.pdf │ ├── ug901-Vivado-Synthesis.pdf │ ├── ug903-vivado-using-constraints.pdf │ └── ug904-Vivado-Implementation.pdf └── Zybo-Z7-Master.xdc ├── Microprocessor CPU Series └── 7 Step Processor │ ├── ASM_BIN_ROM_Files │ ├── INSTRUCTIONS.txt │ ├── bin2rom.py │ ├── fibonacci.asm │ ├── fibonacci.bin │ ├── fibonacci_rom.v │ ├── rom_TB.v │ ├── sum5.asm │ ├── sum5.bin │ └── sum5_rom.v │ ├── Assembler │ ├── AssemblyLanguage1.png │ ├── AssemblyLanguage2.png │ ├── AssemblyLanguage3.png │ ├── Makefile │ ├── asmbl.exe │ ├── asmbl.h │ ├── asmbl.l │ ├── asmbl.tab.c │ ├── asmbl.tab.h │ ├── asmbl.txt │ ├── asmbl.y │ ├── assembly.links.text │ └── lex.yy.c │ ├── CPU_Information │ ├── CPU_A.jpg │ ├── CPU_B_Design.png │ ├── Control_image_marked_up.jpg │ ├── InstructionSet.jpg │ ├── instruction_set.txt │ └── programming_language.txt │ ├── Test_Benches │ ├── acc_TB.v │ ├── alu_TB.v │ ├── bus1_TB.v │ ├── clock_gen_TB.v │ ├── control_TB.v │ ├── data_bus_TB.v │ ├── flags_TB.v │ ├── fsm_load_ram_TB.v │ ├── gpr_file_TB.v │ ├── iar_TB.v │ ├── io_TB.v │ ├── ir_TB.v │ ├── ram_TB.v │ ├── rom_TB.v │ ├── stepper_TB.v │ └── tmp_TB.v │ ├── acc.v │ ├── alu.v │ ├── bus1.v │ ├── clock_gen.v │ ├── control.v │ ├── control_init.v │ ├── cpu_b.v │ ├── cpu_b_init.v │ ├── cpu_b_test.v │ ├── cpu_b_test_list.txt │ ├── cpu_init.v │ ├── data_bus.v │ ├── dec2x4.v │ ├── dec3x8.v │ ├── flags.v │ ├── fsm_load_ram.v │ ├── gpr.v │ ├── gpr_file.v │ ├── iar.v │ ├── io.v │ ├── ir.v │ ├── ram.v │ ├── stepper.v │ └── tmp.v ├── Modules with Simulations ├── Binary to BCD Converter │ ├── byte2bcd.v │ └── sim_byte2bcd.v ├── Fibonacci Sequence Generator │ ├── Fibonacci in Logisim │ │ └── Fibonacci_Sequence_Generator_Circuit.circ │ ├── fibonacci.v │ └── sim_fibonacci.v ├── Multiplexer 4x1 Parameterized │ ├── mux4x1.v │ └── sim_4x1mux.v ├── PWM Generator │ ├── pwm_gen.v │ └── sim_pwm_gen.v ├── Register File │ ├── reg_file.v │ └── sim_reg_file.v ├── SR Latch │ ├── sim_sr_latch.v │ └── sr_latch.v ├── Sequence Detector D-Flip Flops │ ├── d_ff.v │ ├── seq_det_101.v │ └── seq_det_101_TB.v ├── Sequence Detector Shift Register │ ├── seq_det_101.v │ └── seq_det_101_TB.v ├── Sequence Detector State Machine │ ├── seq_det_101_fsm.v │ └── seq_det_101_fsm_TB.v ├── Simple ALU │ ├── alu.v │ └── sim_alu.v └── Verilog Switch Level Modeling │ ├── cmos_gates.v │ └── sim_cmos.v ├── On_My_Bookshelf.txt ├── Other Projects ├── Daily Countdown Timer Arduino │ └── day_countdown_timer3.ino ├── Star Trek Clock │ ├── 0001.mp3 │ ├── 0002.mp3 │ ├── 0003.mp3 │ ├── 0004.mp3 │ ├── Star_Trek_Clock_ONE_NANO │ │ └── Star_Trek_Clock_ONE_NANO.ino │ ├── Star_Trek_Clock_Schematic.fzz │ ├── parts_list.xlsx │ ├── speaker_bottom-Body.stl │ ├── speaker_bottom.FCStd │ ├── speaker_top-Body.stl │ ├── speaker_top.FCStd │ ├── star_trek_clock_bottom-Body.stl │ ├── star_trek_clock_bottom.FCStd │ ├── star_trek_clock_top-Body.stl │ └── star_trek_clock_top.FCStd └── basic_binary_clock │ ├── basic_arduino_binary_clock.png │ └── basic_binary_clock.ino ├── README.md ├── University Senior Class Design Project ├── README.txt ├── clock_source.v ├── counter32.v ├── oversampler_DFF.v ├── pwm_generator.v ├── shift_reg184.v └── shift_reg376.v └── Verilog Introductory Tutorial Book ├── AND_gate.v ├── D_ff.v ├── D_ff_TB.v ├── D_ff_beh.v ├── D_ff_beh_TB.v ├── NAND_gate.v ├── NAND_gate2.v ├── NAND_gate2_TB.v ├── NAND_gate_TB.v ├── OR_gate.v ├── binary_counter3.v ├── binary_counter3_TB.v ├── decoder_3x8.v ├── decoder_3x8_TB.v ├── mod100_counter.v ├── mod100_counterEX.v ├── mod100_counter_TB.v ├── modular_verilog.v ├── modular_verilog_TB.v ├── mux_4x1.v ├── mux_4x1_TB.v ├── your_phone.v └── your_phone2.v /10 Verilog Projects Book/Section_1/d_ff.v: -------------------------------------------------------------------------------- 1 | 2 | module d_ff( 3 | input clock, 4 | input reset, 5 | input data_in, 6 | output reg q 7 | ); 8 | 9 | always @(posedge clock or negedge reset) 10 | if(~reset) 11 | q <= 0; 12 | else 13 | q <= data_in; 14 | 15 | endmodule 16 | 17 | -------------------------------------------------------------------------------- /10 Verilog Projects Book/Section_1/d_ff_TB.v: -------------------------------------------------------------------------------- 1 | 2 | module d_ff_TB; 3 | reg clock; 4 | reg reset; 5 | reg data_in; 6 | wire q; 7 | 8 | d_ff DUT(.clock(clock), .reset(reset), 9 | .data_in(data_in), .q(q)); 10 | 11 | always #2 clock = ~clock; 12 | 13 | initial begin 14 | $dumpfile("d_ff_TB.vcd"); 15 | $dumpvars(0, d_ff_TB); 16 | end 17 | 18 | initial begin 19 | clock = 0; 20 | reset = 0; 21 | data_in = 0; 22 | 23 | #9 reset = 1; 24 | data_in = 1; 25 | 26 | #4 data_in = 0; 27 | #4 data_in = 1; 28 | #4 reset = 0; 29 | #4 reset = 1; 30 | 31 | #4 $finish; 32 | end 33 | 34 | endmodule 35 | 36 | 37 | -------------------------------------------------------------------------------- /10 Verilog Projects Book/Section_1/seq_det_101_TB.v: -------------------------------------------------------------------------------- 1 | 2 | module seq_det_101_TB; 3 | reg clock; 4 | reg reset; 5 | reg serial_in; 6 | wire detect_101; 7 | 8 | sequence_detector_101 DUT(.clock(clock), .reset(reset), 9 | .serial_in(serial_in), 10 | .detect_101(detect_101)); 11 | 12 | always #2 clock = ~clock; 13 | 14 | initial begin 15 | $dumpfile("seq_det_101_TB.vcd"); 16 | $dumpvars(0, seq_det_101_TB); 17 | end 18 | 19 | reg [15:0] data = 16'b0100_1010_0101_1011; 20 | 21 | integer i; 22 | 23 | initial begin 24 | clock = 0; 25 | reset = 0; 26 | serial_in = 0; 27 | #9 reset = 1; 28 | 29 | for(i = 0; i < 16; i = i + 1) begin 30 | serial_in = data[i]; 31 | #4; 32 | end 33 | 34 | #4 $finish; 35 | end 36 | 37 | endmodule 38 | 39 | 40 | -------------------------------------------------------------------------------- /10 Verilog Projects Book/Section_1/seq_det_101b.v: -------------------------------------------------------------------------------- 1 | 2 | module seq_det_101b( 3 | input clock, 4 | input reset, 5 | input serial_in, 6 | output detect_101 7 | ); 8 | 9 | reg [2:0] shift_reg; 10 | 11 | always @(posedge clock or negedge reset) 12 | if(~reset) 13 | shift_reg <= 0; 14 | else 15 | shift_reg <= {shift_reg[1:0], serial_in}; 16 | 17 | assign detect_101 = (shift_reg == 3'b101) ? 1 : 0; 18 | 19 | endmodule 20 | 21 | 22 | -------------------------------------------------------------------------------- /10 Verilog Projects Book/Section_1/seq_det_101b_TB.v: -------------------------------------------------------------------------------- 1 | 2 | module seq_det_101b_TB; 3 | reg clock; 4 | reg reset; 5 | reg serial_in; 6 | wire detect_101; 7 | 8 | seq_det_101b DUT(.clock(clock), .reset(reset), 9 | .serial_in(serial_in), 10 | .detect_101(detect_101)); 11 | 12 | always #2 clock = ~clock; 13 | 14 | initial begin 15 | $dumpfile("seq_det_101b_TB.vcd"); 16 | $dumpvars(0, seq_det_101b_TB); 17 | end 18 | 19 | reg [15:0] data = 16'b0100_1010_0101_1011; 20 | 21 | integer i; 22 | 23 | initial begin 24 | clock = 0; 25 | reset = 0; 26 | serial_in = 0; 27 | #9 reset = 1; 28 | 29 | for(i = 0; i < 16; i = i + 1) begin 30 | serial_in = data[i]; 31 | #4; 32 | end 33 | 34 | #4 $finish; 35 | end 36 | 37 | endmodule 38 | 39 | 40 | -------------------------------------------------------------------------------- /10 Verilog Projects Book/Section_1/seq_det_101c.v: -------------------------------------------------------------------------------- 1 | 2 | module seq_det_101c( 3 | input clock, 4 | input reset, 5 | input serial_in, 6 | output detect_101 7 | ); 8 | 9 | parameter S0 = 2'b00; 10 | parameter S1 = 2'b01; 11 | parameter S2 = 2'b10; 12 | parameter S3 = 2'b11; 13 | 14 | reg [1:0] current_state, next_state; 15 | 16 | always @(posedge clock or negedge reset) 17 | if(~reset) 18 | current_state <= S0; 19 | else 20 | current_state <= next_state; 21 | 22 | always @(*) 23 | case(current_state) 24 | S0 : next_state = (serial_in == 1) ? S1 : S0; 25 | S1 : next_state = (serial_in == 0) ? S2 : S1; 26 | S2 : next_state = (serial_in == 1) ? S3 : S0; 27 | S3 : next_state = (serial_in == 1) ? S1 : S2; 28 | endcase 29 | 30 | assign detect_101 = (current_state == S3) ? 1 : 0; 31 | 32 | endmodule 33 | 34 | 35 | -------------------------------------------------------------------------------- /10 Verilog Projects Book/Section_1/seq_det_101c_TB.v: -------------------------------------------------------------------------------- 1 | 2 | module seq_det_101c_TB; 3 | reg clock; 4 | reg reset; 5 | reg serial_in; 6 | wire detect_101; 7 | 8 | seq_det_101c DUT(.clock(clock), .reset(reset), 9 | .serial_in(serial_in), 10 | .detect_101(detect_101)); 11 | 12 | always #2 clock = ~clock; 13 | 14 | initial begin 15 | $dumpfile("seq_det_101c_TB.vcd"); 16 | $dumpvars(0, seq_det_101c_TB); 17 | end 18 | 19 | reg [15:0] data = 16'b0100_1010_0101_1011; 20 | 21 | integer i; 22 | 23 | initial begin 24 | clock = 0; 25 | reset = 0; 26 | serial_in = 0; 27 | #9 reset = 1; 28 | 29 | for(i = 0; i < 16; i = i + 1) begin 30 | serial_in = data[i]; 31 | #4; 32 | end 33 | 34 | #4 $finish; 35 | end 36 | 37 | endmodule 38 | 39 | -------------------------------------------------------------------------------- /10 Verilog Projects Book/Section_1/sequence_detector_101.v: -------------------------------------------------------------------------------- 1 | module sequence_detector_101( 2 | input clock, 3 | input reset, 4 | input serial_in, 5 | output detect_101 6 | ); 7 | 8 | wire a2b, b2c, c; 9 | 10 | d_ff DFFa(.clock(clock), .reset(reset), 11 | .data_in(serial_in), .q(a2b)); 12 | d_ff DFFb(.clock(clock), .reset(reset), 13 | .data_in(a2b), .q(b2c)); 14 | d_ff DFFc(.clock(clock), .reset(reset), 15 | .data_in(b2c), .q(c)); 16 | 17 | assign detect_101 = a2b & ~b2c & c; 18 | 19 | endmodule 20 | 21 | 22 | 23 | -------------------------------------------------------------------------------- /10 Verilog Projects Book/Section_10/traffic_controller_TB.v: -------------------------------------------------------------------------------- 1 | 2 | module traffic_controller_TB; 3 | reg clock; 4 | reg reset; 5 | reg sensor; 6 | wire [2:0] major; 7 | wire [2:0] minor; 8 | 9 | traffic_controller DUT(.clock(clock), .reset(reset), 10 | .sensor(sensor), 11 | .major(major), .minor(minor)); 12 | 13 | always #2 clock = ~clock; 14 | 15 | initial begin 16 | $dumpfile("traffic_controller_TB.vcd"); 17 | $dumpvars(0, traffic_controller_TB); 18 | end 19 | 20 | initial begin 21 | clock = 0; 22 | reset = 0; 23 | sensor = 0; 24 | 25 | #5 reset = 1; 26 | 27 | #4 sensor = 1; 28 | #20 sensor = 0; 29 | 30 | #50 $finish; 31 | end 32 | 33 | endmodule 34 | 35 | 36 | 37 | -------------------------------------------------------------------------------- /10 Verilog Projects Book/Section_2/bin2bcd.v: -------------------------------------------------------------------------------- 1 | module bin2bcd( 2 | input [7:0] bin_in, 3 | output [7:0] bcd_out 4 | ); 5 | 6 | reg [3:0] tens, ones; 7 | 8 | always @(*) begin 9 | tens = bin_in / 10; 10 | ones = bin_in % 10; 11 | end 12 | 13 | assign bcd_out = {tens, ones}; 14 | 15 | endmodule 16 | 17 | 18 | -------------------------------------------------------------------------------- /10 Verilog Projects Book/Section_2/bin2bcd_TB.v: -------------------------------------------------------------------------------- 1 | module bin2bcd_TB; 2 | 3 | reg [7:0] bin_in; 4 | wire [7:0] bcd_out; 5 | 6 | bin2bcd DUT(.bin_in(bin_in), .bcd_out(bcd_out)); 7 | 8 | integer i; 9 | 10 | initial begin 11 | for(i = 0; i < 60; i = i + 1) begin 12 | bin_in = i; 13 | #2; 14 | end 15 | end 16 | 17 | initial begin 18 | $dumpfile("bin2bcd_TB.vcd") ; 19 | $dumpvars(0, bin2bcd_TB) ; 20 | end 21 | 22 | endmodule 23 | 24 | 25 | -------------------------------------------------------------------------------- /10 Verilog Projects Book/Section_2/byte2bcd.v: -------------------------------------------------------------------------------- 1 | module byte2bcd( 2 | input [7:0] bin_in, 3 | output [11:0] bcd_out 4 | ); 5 | 6 | reg [3:0] hundreds, tens, ones; 7 | reg [6:0] temp_reg; 8 | 9 | always @(*) begin 10 | hundreds = bin_in / 100; 11 | temp_reg = bin_in % 100; 12 | tens = temp_reg / 10; 13 | ones = temp_reg % 10; 14 | end 15 | 16 | assign bcd_out = {hundreds, tens, ones}; 17 | 18 | endmodule 19 | 20 | -------------------------------------------------------------------------------- /10 Verilog Projects Book/Section_2/byte2bcd_TB.v: -------------------------------------------------------------------------------- 1 | module byte2bcd_TB; 2 | 3 | reg [7:0] bin_in; 4 | wire [11:0] bcd_out; 5 | 6 | byte2bcd DUT(.bin_in(bin_in), .bcd_out(bcd_out)); 7 | 8 | integer i; 9 | 10 | initial begin 11 | for(i = 0; i < 256; i = i + 1) begin 12 | bin_in = i; 13 | #2; 14 | end 15 | end 16 | 17 | initial begin 18 | $dumpfile("byte2bcd_TB.vcd") ; 19 | $dumpvars(0, byte2bcd_TB) ; 20 | end 21 | 22 | endmodule 23 | 24 | 25 | -------------------------------------------------------------------------------- /10 Verilog Projects Book/Section_3/fibonacci.v: -------------------------------------------------------------------------------- 1 | 2 | module fibonacci( 3 | input clock, 4 | input reset, 5 | output [15:0] fib_out 6 | ); 7 | 8 | reg [15:0] num0, num1; 9 | 10 | always @(posedge clock or negedge reset) begin 11 | if(~reset) begin 12 | num0 <= 0; 13 | num1 <= 1; 14 | end 15 | else begin 16 | num0 <= num1; 17 | num1 <= fib_out; 18 | end 19 | end 20 | 21 | assign fib_out = num0 + num1; 22 | 23 | endmodule 24 | 25 | 26 | -------------------------------------------------------------------------------- /10 Verilog Projects Book/Section_3/fibonacci_TB.v: -------------------------------------------------------------------------------- 1 | 2 | module fibonacci_TB; 3 | reg clock; 4 | reg reset; 5 | wire [15:0] fib_out; 6 | 7 | fibonacci DUT(.clock(clock), .reset(reset), 8 | .fib_out(fib_out)); 9 | 10 | always #2 clock = ~clock; 11 | 12 | initial begin 13 | clock = 0; 14 | reset = 0; 15 | #9 reset = 1; 16 | 17 | #100 $finish; 18 | end 19 | 20 | initial begin 21 | $dumpfile("fibonacci_TB.vcd"); 22 | $dumpvars(0, fibonacci_TB); 23 | end 24 | 25 | endmodule 26 | 27 | 28 | -------------------------------------------------------------------------------- /10 Verilog Projects Book/Section_3/fibonacci_p.v: -------------------------------------------------------------------------------- 1 | 2 | module fibonacci_p #(parameter W = 16)( 3 | input clock, 4 | input reset, 5 | output [W-1:0] fib_out 6 | ); 7 | 8 | reg [W-1:0] num0, num1; 9 | 10 | always @(posedge clock or negedge reset) begin 11 | if(~reset) begin 12 | num0 <= 0; 13 | num1 <= 1; 14 | end 15 | else begin 16 | num0 <= num1; 17 | num1 <= fib_out; 18 | end 19 | end 20 | 21 | assign fib_out = num0 + num1; 22 | 23 | endmodule 24 | 25 | -------------------------------------------------------------------------------- /10 Verilog Projects Book/Section_3/fibonacci_p_TB.v: -------------------------------------------------------------------------------- 1 | 2 | module fibonacci_p_TB; 3 | parameter W = 32; 4 | reg clock; 5 | reg reset; 6 | wire [W-1:0] fib_out; 7 | 8 | fibonacci_p #(.W(W)) DUT(.clock(clock), .reset(reset), 9 | .fib_out(fib_out)); 10 | 11 | always #2 clock = ~clock; 12 | 13 | initial begin 14 | clock = 0; 15 | reset = 0; 16 | #9 reset = 1; 17 | 18 | #500 $finish; 19 | end 20 | 21 | initial begin 22 | $dumpfile("fibonacci_p_TB.vcd"); 23 | $dumpvars(0, fibonacci_p_TB); 24 | end 25 | 26 | endmodule 27 | 28 | -------------------------------------------------------------------------------- /10 Verilog Projects Book/Section_4/gray_counter.v: -------------------------------------------------------------------------------- 1 | 2 | module gray_counter( 3 | input clock, 4 | input reset, 5 | output reg [2:0] gray_out 6 | ); 7 | 8 | reg [2:0] bin_counter; 9 | 10 | always @(posedge clock or negedge reset) begin 11 | if(~reset) 12 | bin_counter <= 0; 13 | else 14 | bin_counter <= bin_counter + 1; 15 | end 16 | 17 | always @(bin_counter) begin 18 | case(bin_counter) 19 | 3'b000 : gray_out = 3'b000; 20 | 3'b001 : gray_out = 3'b001; 21 | 3'b010 : gray_out = 3'b011; 22 | 3'b011 : gray_out = 3'b010; 23 | 3'b100 : gray_out = 3'b110; 24 | 3'b101 : gray_out = 3'b111; 25 | 3'b110 : gray_out = 3'b101; 26 | 3'b111 : gray_out = 3'b100; 27 | endcase 28 | end 29 | 30 | endmodule 31 | 32 | -------------------------------------------------------------------------------- /10 Verilog Projects Book/Section_4/gray_counter2.v: -------------------------------------------------------------------------------- 1 | 2 | module gray_counter2( 3 | input clock, 4 | input reset, 5 | output [2:0] gray_out 6 | ); 7 | 8 | reg [2:0] bin_counter; 9 | 10 | always @(posedge clock or negedge reset) begin 11 | if(~reset) 12 | bin_counter <= 0; 13 | else 14 | bin_counter <= bin_counter + 1; 15 | end 16 | 17 | assign gray_out[2] = bin_counter[2]; 18 | assign gray_out[1] = bin_counter[2] ^ bin_counter[1]; 19 | assign gray_out[0] = bin_counter[1] ^ bin_counter[0]; 20 | 21 | endmodule 22 | 23 | 24 | -------------------------------------------------------------------------------- /10 Verilog Projects Book/Section_4/gray_counter2_TB.v: -------------------------------------------------------------------------------- 1 | 2 | module gray_counter2_TB; 3 | reg clock; 4 | reg reset; 5 | wire [2:0] gray_out; 6 | 7 | gray_counter2 DUT(.clock(clock), .reset(reset), 8 | .gray_out(gray_out)); 9 | 10 | always #2 clock = ~clock; 11 | 12 | initial begin 13 | clock = 0; 14 | reset = 0; 15 | #9 reset = 1; 16 | 17 | #60 $finish; 18 | end 19 | 20 | initial begin 21 | $dumpfile("gray_counter2_TB.vcd"); 22 | $dumpvars(0, gray_counter2_TB); 23 | end 24 | 25 | endmodule 26 | 27 | 28 | -------------------------------------------------------------------------------- /10 Verilog Projects Book/Section_4/gray_counter_TB.v: -------------------------------------------------------------------------------- 1 | 2 | module gray_counter_TB; 3 | reg clock; 4 | reg reset; 5 | wire [2:0] gray_out; 6 | 7 | gray_counter DUT(.clock(clock), .reset(reset), 8 | .gray_out(gray_out)); 9 | 10 | always #2 clock = ~clock; 11 | 12 | initial begin 13 | clock = 0; 14 | reset = 0; 15 | #9 reset = 1; 16 | 17 | #60 $finish; 18 | end 19 | 20 | initial begin 21 | $dumpfile("gray_counter_TB.vcd"); 22 | $dumpvars(0, gray_counter_TB); 23 | end 24 | 25 | endmodule 26 | 27 | 28 | -------------------------------------------------------------------------------- /10 Verilog Projects Book/Section_5/alu.v: -------------------------------------------------------------------------------- 1 | 2 | module alu #(parameter W = 32)( 3 | input [1:0] opcode, 4 | input [W-1:0] operand_A, 5 | input [W-1:0] operand_B, 6 | output reg [W-1:0] alu_result, 7 | output [2:0] flags 8 | ); 9 | 10 | wire N, Z, C; 11 | wire [W:0] carry_check; 12 | 13 | always @(*) begin 14 | case(opcode) 15 | 2'b00 : alu_result = operand_A + operand_B; 16 | 2'b01 : alu_result = operand_A - operand_B; 17 | 2'b10 : alu_result = operand_A & operand_B; 18 | 2'b11 : alu_result = operand_A | operand_B; 19 | endcase 20 | end 21 | 22 | assign carry_check = operand_A + operand_B; 23 | 24 | assign N = alu_result[W-1]; 25 | assign Z = ~|alu_result; 26 | assign C = carry_check[W]; 27 | 28 | assign flags = {N, Z, C}; 29 | 30 | endmodule 31 | 32 | 33 | 34 | -------------------------------------------------------------------------------- /10 Verilog Projects Book/Section_5/alu_TB.v: -------------------------------------------------------------------------------- 1 | 2 | module alu_TB; 3 | parameter W = 8; 4 | reg [1:0] opcode; 5 | reg [W-1:0] operand_A; 6 | reg [W-1:0] operand_B; 7 | wire [W-1:0] alu_result; 8 | wire [2:0] flags; 9 | 10 | alu #(.W(W)) DUT(.opcode(opcode), 11 | .operand_A(operand_A), .operand_B(operand_B), 12 | .alu_result(alu_result), .flags(flags)); 13 | 14 | initial begin 15 | operand_A = 8'd32; 16 | operand_B = 8'd32; 17 | opcode = 2'b00; // ADD 18 | #2 opcode = 2'b01; // SUB, check for Z flag 19 | #2; 20 | operand_A = 8'b1010_1010; 21 | operand_B = 8'b0101_0101; 22 | opcode = 2'b10; // AND, check for Z flag 23 | #2 opcode = 2'b11; // OR, check for N flag 24 | #2; 25 | operand_A = 8'b1111_1111; 26 | operand_B = 8'b0000_0001; 27 | opcode = 2'b00; // ADD, check for C flag 28 | #2; 29 | operand_A = 8'd0; 30 | operand_B = 8'd0; 31 | opcode = 2'b00; // ADD, check for Z flag 32 | #2; 33 | operand_A = 8'b0111_1111; 34 | operand_B = 8'b1111_1111; 35 | opcode = 2'b01; // SUB, check for N flag 36 | 37 | #2 $finish; 38 | end 39 | 40 | initial begin 41 | $dumpfile("alu_TB.vcd"); 42 | $dumpvars(0, alu_TB); 43 | end 44 | 45 | endmodule 46 | 47 | 48 | 49 | -------------------------------------------------------------------------------- /10 Verilog Projects Book/Section_6/rom.v: -------------------------------------------------------------------------------- 1 | 2 | module rom( 3 | input [3:0] address, 4 | output reg [7:0] data 5 | ); 6 | 7 | always @(*) 8 | case(address) 9 | 4'h0 : data = 8'h00; 10 | 4'h1 : data = 8'h11; 11 | 4'h2 : data = 8'h22; 12 | 4'h3 : data = 8'h33; 13 | 4'h4 : data = 8'h44; 14 | 4'h5 : data = 8'h55; 15 | 4'h6 : data = 8'h66; 16 | 4'h7 : data = 8'h77; 17 | 4'h8 : data = 8'h88; 18 | 4'h9 : data = 8'h99; 19 | 4'ha : data = 8'haa; 20 | 4'hb : data = 8'hbb; 21 | 4'hc : data = 8'hcc; 22 | 4'hd : data = 8'hdd; 23 | 4'he : data = 8'hee; 24 | 4'hf : data = 8'hff; 25 | endcase 26 | 27 | endmodule 28 | 29 | 30 | -------------------------------------------------------------------------------- /10 Verilog Projects Book/Section_6/rom_TB.v: -------------------------------------------------------------------------------- 1 | 2 | module rom_TB; 3 | reg [3:0] address; 4 | wire [7:0] data; 5 | 6 | rom DUT(.address(address), .data(data)); 7 | 8 | integer i; 9 | initial begin 10 | for(i = 0; i < 16; i = i + 1) begin 11 | address = i; 12 | #2; 13 | end 14 | end 15 | 16 | initial begin 17 | $dumpfile("rom_TB.vcd"); 18 | $dumpvars(0, rom_TB); 19 | end 20 | 21 | endmodule 22 | 23 | 24 | 25 | -------------------------------------------------------------------------------- /10 Verilog Projects Book/Section_7/ram.v: -------------------------------------------------------------------------------- 1 | 2 | module ram( 3 | input clock, 4 | input write_enable, 5 | input [3:0] address, 6 | input [7:0] data_in, 7 | output [7:0] data_out 8 | ); 9 | 10 | reg [7:0] ram [15:0]; 11 | 12 | always @(posedge clock) 13 | if(write_enable) 14 | ram[address] <= data_in; 15 | 16 | assign data_out = ram[address]; 17 | 18 | endmodule 19 | 20 | 21 | -------------------------------------------------------------------------------- /10 Verilog Projects Book/Section_7/ram_TB.v: -------------------------------------------------------------------------------- 1 | 2 | module ram_TB; 3 | reg clock; 4 | reg write_enable; 5 | reg [3:0] address; 6 | reg [7:0] data_in; 7 | wire [7:0] data_out; 8 | 9 | ram DUT(.clock(clock), .write_enable(write_enable), 10 | .address(address), 11 | .data_in(data_in), .data_out(data_out)); 12 | 13 | always #2 clock = ~clock; 14 | 15 | initial begin 16 | $dumpfile("ram_TB.vcd"); 17 | $dumpvars(0, ram_TB); 18 | end 19 | 20 | integer i; 21 | 22 | initial begin 23 | clock = 0; 24 | write_enable = 0; 25 | address = 4'h0; 26 | data_in = 8'h00; 27 | #9 write_enable = 1; 28 | 29 | for(i = 0; i < 16; i = i + 1) begin 30 | address = i; 31 | data_in = i * 16; 32 | #4; 33 | end 34 | 35 | write_enable = 0; 36 | 37 | for(i = 0; i < 16; i = i + 1) begin 38 | address = i; 39 | #4; 40 | end 41 | 42 | #4 $finish; 43 | 44 | end 45 | 46 | endmodule 47 | 48 | 49 | 50 | -------------------------------------------------------------------------------- /10 Verilog Projects Book/Section_7/ram_p.v: -------------------------------------------------------------------------------- 1 | 2 | module ram_p #(parameter ADDR_WIDTH = 4, 3 | DATA_WIDTH = 8) 4 | ( 5 | input clock, 6 | input write_enable, 7 | input [ADDR_WIDTH-1:0] address, 8 | input [DATA_WIDTH-1:0] data_in, 9 | output [DATA_WIDTH-1:0] data_out 10 | ); 11 | 12 | reg [DATA_WIDTH-1:0] ram [2**ADDR_WIDTH-1:0]; 13 | 14 | always @(posedge clock) 15 | if(write_enable) 16 | ram[address] <= data_in; 17 | 18 | assign data_out = ram[address]; 19 | 20 | endmodule 21 | 22 | 23 | 24 | -------------------------------------------------------------------------------- /10 Verilog Projects Book/Section_7/ram_p_TB.v: -------------------------------------------------------------------------------- 1 | 2 | module ram_p_TB; 3 | parameter ADDR_WIDTH = 8, DATA_WIDTH = 16; 4 | reg clock; 5 | reg write_enable; 6 | reg [ADDR_WIDTH-1:0] address; 7 | reg [DATA_WIDTH-1:0] data_in; 8 | wire [DATA_WIDTH-1:0] data_out; 9 | 10 | ram_p #(.ADDR_WIDTH(ADDR_WIDTH), .DATA_WIDTH(DATA_WIDTH)) 11 | DUT(.clock(clock), .write_enable(write_enable), 12 | .address(address), 13 | .data_in(data_in), .data_out(data_out)); 14 | 15 | always #2 clock = ~clock; 16 | 17 | initial begin 18 | $dumpfile("ram_p_TB.vcd"); 19 | $dumpvars(0, ram_p_TB); 20 | end 21 | 22 | integer i; 23 | 24 | initial begin 25 | clock = 0; 26 | write_enable = 0; 27 | address = 0; 28 | data_in = 0; 29 | #9 write_enable = 1; 30 | 31 | for(i = 0; i < (2**ADDR_WIDTH); i = i + 1) begin 32 | address = i; 33 | data_in = i * (2**ADDR_WIDTH); 34 | #4; 35 | end 36 | 37 | write_enable = 0; 38 | 39 | for(i = 0; i < (2**ADDR_WIDTH); i = i + 1) begin 40 | address = i; 41 | #4; 42 | end 43 | 44 | #4 $finish; 45 | end 46 | endmodule 47 | 48 | -------------------------------------------------------------------------------- /10 Verilog Projects Book/Section_8/reg_file.v: -------------------------------------------------------------------------------- 1 | 2 | module reg_file( 3 | input clock, 4 | input write_enable, 5 | input [2:0] write_address, 6 | input [2:0] read_address, 7 | input [7:0] write_data, 8 | output [7:0] read_data 9 | ); 10 | 11 | reg [7:0] reg_file [7:0]; 12 | 13 | always @(posedge clock ) 14 | if(write_enable) 15 | reg_file[write_address] <= write_data; 16 | 17 | assign read_data = reg_file[read_address]; 18 | 19 | endmodule 20 | 21 | 22 | -------------------------------------------------------------------------------- /10 Verilog Projects Book/Section_8/reg_file_TB.v: -------------------------------------------------------------------------------- 1 | 2 | module reg_file_TB; 3 | reg clock; 4 | reg write_enable; 5 | reg [2:0] write_address; 6 | reg [2:0] read_address; 7 | reg [7:0] write_data; 8 | wire [7:0] read_data; 9 | 10 | reg_file DUT(.clock(clock), .write_enable(write_enable), 11 | .write_address(write_address), 12 | .read_address(read_address), 13 | .write_data(write_data), .read_data(read_data)); 14 | 15 | always #2 clock = ~clock; 16 | 17 | initial begin 18 | $dumpfile("reg_file_TB.vcd"); 19 | $dumpvars(0, reg_file_TB); 20 | end 21 | 22 | integer i; 23 | 24 | initial begin 25 | clock = 0; 26 | write_enable = 1'b0; 27 | write_address = 3'b000; 28 | read_address = 3'b000; 29 | write_data = 8'h00; 30 | 31 | #5 write_enable = 1'b1; 32 | for(i = 0; i < 8; i = i + 1) begin 33 | write_address = i; 34 | write_data = i * 16; 35 | #4; 36 | end 37 | 38 | #8 write_enable = 1'b0; 39 | for(i = 0; i < 8; i = i + 1) begin 40 | read_address = i; 41 | #4; 42 | end 43 | 44 | $finish; 45 | end 46 | endmodule 47 | 48 | 49 | 50 | -------------------------------------------------------------------------------- /10 Verilog Projects Book/Section_8/reg_file_p.v: -------------------------------------------------------------------------------- 1 | 2 | module reg_file_p #(parameter ADDR_WIDTH = 3, 3 | DATA_WIDTH = 8) 4 | ( 5 | input clock, 6 | input write_enable, 7 | input [ADDR_WIDTH-1:0] write_address, 8 | input [ADDR_WIDTH-1:0] read_address, 9 | input [DATA_WIDTH-1:0] write_data, 10 | output [DATA_WIDTH-1:0] read_data 11 | ); 12 | 13 | reg [DATA_WIDTH-1:0] reg_file [2**ADDR_WIDTH-1:0]; 14 | 15 | always @(posedge clock) 16 | if(write_enable) 17 | reg_file[write_address] <= write_data; 18 | 19 | assign read_data = reg_file[read_address]; 20 | 21 | endmodule 22 | 23 | 24 | -------------------------------------------------------------------------------- /College Coursework/Advanced Computer Architecture Final Project/Final_Paper.docx: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/FPGADude/Digital-Design/4cb93eeaba434eb02c2e200060921fe0e5aebf03/College Coursework/Advanced Computer Architecture Final Project/Final_Paper.docx -------------------------------------------------------------------------------- /College Coursework/Advanced Computer Architecture Final Project/ISR.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/FPGADude/Digital-Design/4cb93eeaba434eb02c2e200060921fe0e5aebf03/College Coursework/Advanced Computer Architecture Final Project/ISR.png -------------------------------------------------------------------------------- /College Coursework/Advanced Computer Architecture Final Project/LEG_microP.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/FPGADude/Digital-Design/4cb93eeaba434eb02c2e200060921fe0e5aebf03/College Coursework/Advanced Computer Architecture Final Project/LEG_microP.png -------------------------------------------------------------------------------- /College Coursework/Advanced Computer Architecture Final Project/Screenshot (146).png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/FPGADude/Digital-Design/4cb93eeaba434eb02c2e200060921fe0e5aebf03/College Coursework/Advanced Computer Architecture Final Project/Screenshot (146).png -------------------------------------------------------------------------------- /College Coursework/Advanced Computer Architecture Final Project/Screenshot (147).png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/FPGADude/Digital-Design/4cb93eeaba434eb02c2e200060921fe0e5aebf03/College Coursework/Advanced Computer Architecture Final Project/Screenshot (147).png -------------------------------------------------------------------------------- /College Coursework/Advanced Computer Architecture Final Project/Screenshot (158).png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/FPGADude/Digital-Design/4cb93eeaba434eb02c2e200060921fe0e5aebf03/College Coursework/Advanced Computer Architecture Final Project/Screenshot (158).png -------------------------------------------------------------------------------- /College Coursework/Advanced Computer Architecture Final Project/verilog CPU/bit_selector.v: -------------------------------------------------------------------------------- 1 | module bit_selector( y, shift_value ); 2 | 3 | input [15:0] y; 4 | output reg [3:0] shift_value; 5 | 6 | always @* 7 | begin 8 | output <= y[3:0]; 9 | end 10 | 11 | endmodule -------------------------------------------------------------------------------- /College Coursework/Advanced Computer Architecture Final Project/verilog CPU/control_unit.v: -------------------------------------------------------------------------------- 1 | 2 | 3 | module control_unit( instr_reg, fam, opcode, src1_reg, src2_dest_reg, sys_enable, data_out ); 4 | 5 | input reg [31:0] instr_reg; 6 | 7 | output [1:0] fam = instr_reg[31:30]; // 2 bits for family operation 8 | output [2:0] opcode = instr_reg[29:27]; // 3 bits for opcode (ALU select, shifter select) 9 | output [2:0] src1_reg = instr_reg[26:24]; // 3 bits select which register 10 | output [2:0] src2_dest_reg = instr_reg[23:21]; // 3 bits select which register 11 | output [0] sys_enable = instr_reg[20]; // 0 = no operation, 1 = enable system ops 12 | output [0] = instr_reg[19]; // 13 | output [0] = instr_reg[18]; 14 | output [0] = instr_reg[17]; 15 | output [0] = instr_reg[16]; 16 | 17 | 18 | output [15:0] data_out = instr_reg[15:0]; 19 | 20 | 21 | endmodule 22 | -------------------------------------------------------------------------------- /College Coursework/Advanced Computer Architecture Final Project/verilog CPU/ram.v: -------------------------------------------------------------------------------- 1 | module ram( data_out, data_in, address, write, select, clock ); 2 | output[31:0] data_out; 3 | input [31:0] data_in; 4 | input [15:0] address; 5 | input write; 6 | input select; 7 | input clock; 8 | 9 | reg [31:0] mem [65535:0]; //memory 10 | reg [31:0] data_out; 11 | 12 | always @ ( data_in, address, write, select ) 13 | begin 14 | if ( write && select ) 15 | begin 16 | mem[address] = data_in; 17 | //$display( "write %8X into DM[%3X]", data_in, address ); 18 | end 19 | assign data_out = select ? mem[address] : 32'hzzzzzzzz; 20 | end 21 | 22 | endmodule -------------------------------------------------------------------------------- /College Coursework/Advanced Computer Architecture Final Project/verilog CPU/register.v: -------------------------------------------------------------------------------- 1 | module register(clock, enable, data_in, data_out); 2 | input clock; 3 | input enable; 4 | input [15:0] data_in; 5 | output reg [15:0] data_out; 6 | 7 | always @(negedge clock) 8 | begin 9 | if( enable ) 10 | begin 11 | data_out <= data_in; 12 | end 13 | end 14 | 15 | endmodule -------------------------------------------------------------------------------- /College Coursework/Advanced Computer Architecture Final Project/verilog CPU/register_mux.v: -------------------------------------------------------------------------------- 1 | module register_mux( mux_out, in0, in1, in2, in3, in4, in5, in6, in7, select); 2 | output reg [15:0] mux_out; 3 | input [15:0] in0, in1, in2, in3, in4, in5, in6, in7; 4 | input [2:0] select; 5 | 6 | 7 | always @* 8 | begin 9 | case( select) 10 | 3'b000: mux_out = in0; 11 | 3'b001: mux_out = in1; 12 | 3'b010: mux_out = in2; 13 | 3'b011: mux_out = in3; 14 | 3'b100: mux_out = in4; 15 | 3'b101: mux_out = in5; 16 | 3'b110: mux_out = in6; 17 | 3'b111: mux_out = in7; 18 | endcase 19 | end 20 | endmodule 21 | -------------------------------------------------------------------------------- /College Coursework/Advanced Computer Architecture Final Project/verilog CPU/register_selector.v: -------------------------------------------------------------------------------- 1 | // Decoder for register file 2 | 3 | module reg_selector(enable, select_reg, reg_en,); 4 | 5 | input enable; // enables writing to a register (vs. RAM) 6 | input [2:0] select_reg; // selects the register to enable 7 | output [7:0] reg_en; 8 | 9 | always @* 10 | begin 11 | if( enable ) 12 | begin 13 | case( select ) 14 | 3'b000: reg_en = 8'b0000_0001; 15 | 3'b001: reg_en = 8'b0000_0010; 16 | 3'b010: reg_en = 8'b0000_0100; 17 | 3'b011: reg_en = 8'b0000_1000; 18 | 3'b100: reg_en = 8'b0001_0000; 19 | 3'b101: reg_en = 8'b0010_0000; 20 | 3'b110: reg_en = 8'b0100_0000; 21 | 3'b111: reg_en = 8'b1000_0000; 22 | endcase 23 | end 24 | end 25 | 26 | endmodule 27 | 28 | -------------------------------------------------------------------------------- /College Coursework/Advanced Computer Architecture Final Project/verilog CPU/shifter.v: -------------------------------------------------------------------------------- 1 | `include bit_selector.v 2 | 3 | module shifter( shifter_select, shifter_enable, x_input, y_input, shifter_output ); 4 | input [2:0] shifter_select; 5 | input shifter_enable; 6 | input [15:0] x_input; 7 | input [3:0] y_input; 8 | output [15:0] shifter_output; 9 | 10 | 11 | always @* 12 | begin 13 | if( shifter_enable ) 14 | begin 15 | case( shifter_select ) 16 | 3'b000: shifter_output = x_input >> y_input; //LSR shifter_output=x_input << y_input; 17 | 3'b001: shifter_output = x_input << y_input; //LSL shifter_output=x_input >> y_input; 18 | 3'b010: shifter_output = {15, x_input[15:1]}; //ASR shifter_output=x_input >>> y_input; 19 | 3'b011: shifter_output = {x_input[14:0], x_input[15]}; //ROTL shifter_output=x_input rot> y_input; 20 | 3'b100: shifter_output = {x_input[0], x_input[15:1]}; //ROTR shifter_output=x_input = 10) ? 1 : 0; 21 | 22 | endmodule 23 | 24 | 25 | -------------------------------------------------------------------------------- /FPGA Projects/Seven Segment Clock Basys 3(segs on breadboard)/seg_decoder.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | // For 7-segment display clock 4 | // Authored by David J Marion 5 | 6 | module seg_decoder( 7 | input [3:0] count_in, 8 | output [6:0] decode_out 9 | ); 10 | 11 | reg [6:0] decoder = 7'b000_0000; 12 | 13 | always @(*) begin 14 | case(count_in) 15 | 4'b0000 : decoder = 7'b111_1110; // 0 16 | 4'b0001 : decoder = 7'b001_1000; // 1 17 | 4'b0010 : decoder = 7'b110_1101; // 2 18 | 4'b0011 : decoder = 7'b011_1101; // 3 19 | 4'b0100 : decoder = 7'b001_1011; // 4 20 | 4'b0101 : decoder = 7'b011_0111; // 5 21 | 4'b0110 : decoder = 7'b111_0111; // 6 22 | 4'b0111 : decoder = 7'b001_1100; // 7 23 | 4'b1000 : decoder = 7'b111_1111; // 8 24 | 4'b1001 : decoder = 7'b001_1111; // 9 25 | default : decoder = 7'b111_1001; // d 26 | endcase 27 | end 28 | 29 | assign decode_out = decoder; 30 | 31 | endmodule 32 | 33 | -------------------------------------------------------------------------------- /FPGA Projects/Seven Segment Clock Basys 3(segs on breadboard)/seg_hr0.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | // For 7-segment display clock 4 | // Authored by David J Marion 5 | 6 | module seg_hr0( 7 | input [3:0] hours, 8 | output reg [3:0] hr0 9 | ); 10 | 11 | always @(hours) begin 12 | case(hours) 13 | 1 : hr0 = 1; 14 | 2 : hr0 = 2; 15 | 3 : hr0 = 3; 16 | 4 : hr0 = 4; 17 | 5 : hr0 = 5; 18 | 6 : hr0 = 6; 19 | 7 : hr0 = 7; 20 | 8 : hr0 = 8; 21 | 9 : hr0 = 9; 22 | 10 : hr0 = 0; 23 | 11 : hr0 = 1; 24 | 12 : hr0 = 2; 25 | endcase 26 | end 27 | endmodule 28 | 29 | 30 | -------------------------------------------------------------------------------- /FPGA Projects/Seven Segment Clock Basys 3(segs on breadboard)/seg_hr1.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | // For 7-segment display clock 4 | // Authored by David J Marion 5 | 6 | module seg_hr1( 7 | input [3:0] hours, 8 | output reg [3:0] hr1 9 | ); 10 | 11 | always @(hours) begin 12 | case(hours) 13 | 1 : hr1 = 0; 14 | 2 : hr1 = 0; 15 | 3 : hr1 = 0; 16 | 4 : hr1 = 0; 17 | 5 : hr1 = 0; 18 | 6 : hr1 = 0; 19 | 7 : hr1 = 0; 20 | 8 : hr1 = 0; 21 | 9 : hr1 = 0; 22 | 10 : hr1 = 1; 23 | 11 : hr1 = 1; 24 | 12 : hr1 = 1; 25 | endcase 26 | end 27 | endmodule 28 | 29 | 30 | -------------------------------------------------------------------------------- /FPGA Projects/Seven Segment Clock Basys 3(segs on breadboard)/seg_mux.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | // For 7-segment display clock 4 | // Authored by David J Marion 5 | 6 | module seg_mux( 7 | input [6:0] in0, 8 | input [6:0] in1, 9 | input [6:0] in2, 10 | input [6:0] in3, 11 | input [1:0] select, 12 | output [6:0] mux_out 13 | ); 14 | 15 | assign mux_out = (select == 2'b00) ? in0 : 16 | (select == 2'b01) ? in1 : 17 | (select == 2'b10) ? in2 : in3; 18 | endmodule 19 | 20 | 21 | -------------------------------------------------------------------------------- /FPGA Projects/Star Wars Imperial March Song/a_440Hz.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Authored by David J. Marion aka FPGA Dude 4 | // Created on 4/29/2022 5 | // Using Vivado 2021.2 6 | // Generating 440Hz signal for music tone 'a' 7 | ////////////////////////////////////////////////////////////////////////////////// 8 | 9 | module a_440Hz( 10 | input clk_100MHz, 11 | output o_440Hz 12 | ); 13 | 14 | // 100MHz / 113,636 / 2 = 440.0014Hz 15 | reg r_440Hz; 16 | reg [16:0] r_counter = 0; 17 | 18 | always @(posedge clk_100MHz) 19 | if(r_counter == 17'd113_636) begin 20 | r_counter <= 0; 21 | r_440Hz <= ~r_440Hz; 22 | end 23 | else 24 | r_counter <= r_counter + 1; 25 | 26 | assign o_440Hz = r_440Hz; 27 | 28 | endmodule 29 | -------------------------------------------------------------------------------- /FPGA Projects/Star Wars Imperial March Song/cH_523Hz.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Authored by David J. Marion aka FPGA Dude 4 | // Created on 4/29/2022 5 | // Using Vivado 2021.2 6 | // Generating 523Hz signal for music tone 'cH' 7 | ////////////////////////////////////////////////////////////////////////////////// 8 | 9 | module cH_523Hz( 10 | input clk_100MHz, 11 | output o_523Hz // PMOD JB[0] 12 | ); 13 | 14 | // 100MHz / 95,602 / 2 = 523.0016Hz 15 | reg r_523Hz; 16 | reg [16:0] r_counter = 0; 17 | 18 | always @(posedge clk_100MHz) 19 | if(r_counter == 17'd95_602) begin 20 | r_counter <= 0; 21 | r_523Hz <= ~r_523Hz; 22 | end 23 | else 24 | r_counter <= r_counter + 1; 25 | 26 | assign o_523Hz = r_523Hz; 27 | 28 | endmodule 29 | 30 | -------------------------------------------------------------------------------- /FPGA Projects/Star Wars Imperial March Song/const_song.xdc: -------------------------------------------------------------------------------- 1 | # Clock signal 2 | set_property PACKAGE_PIN W5 [get_ports clk_100MHz] 3 | set_property IOSTANDARD LVCMOS33 [get_ports clk_100MHz] 4 | create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports clk_100MHz] 5 | 6 | ##Buttons 7 | ## btnD 8 | set_property PACKAGE_PIN U17 [get_ports play] 9 | set_property IOSTANDARD LVCMOS33 [get_ports play] 10 | 11 | ##Pmod Header JB 12 | ##Sch name = JB1 13 | set_property PACKAGE_PIN A14 [get_ports {speaker}] 14 | set_property IOSTANDARD LVCMOS33 [get_ports {speaker}] -------------------------------------------------------------------------------- /FPGA Projects/Star Wars Imperial March Song/eH_659Hz.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Authored by David J. Marion aka FPGA Dude 4 | // Created on 4/29/2022 5 | // Using Vivado 2021.2 6 | // Generating 659Hz signal for music tone 'eH' 7 | ////////////////////////////////////////////////////////////////////////////////// 8 | 9 | module eH_659Hz( 10 | input clk_100MHz, 11 | output o_659Hz 12 | ); 13 | 14 | // 100MHz / 75,872 / 2 = 659.0046Hz 15 | reg r_659Hz; 16 | reg [16:0] r_counter = 0; 17 | 18 | always @(posedge clk_100MHz) 19 | if(r_counter == 17'd75_872) begin 20 | r_counter <= 0; 21 | r_659Hz <= ~r_659Hz; 22 | end 23 | else 24 | r_counter <= r_counter + 1; 25 | 26 | assign o_659Hz = r_659Hz; 27 | 28 | endmodule 29 | 30 | -------------------------------------------------------------------------------- /FPGA Projects/Star Wars Imperial March Song/fH_698Hz.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Authored by David J. Marion aka FPGA Dude 4 | // Created on 4/29/2022 5 | // Using Vivado 2021.2 6 | // Generating 698Hz signal for music tone 'fH' 7 | ////////////////////////////////////////////////////////////////////////////////// 8 | 9 | module fH_698Hz( 10 | input clk_100MHz, 11 | output o_698Hz 12 | ); 13 | 14 | // 100MHz / 71,633 / 2 = 698.0023Hz 15 | reg r_698Hz; 16 | reg [16:0] r_counter = 0; 17 | 18 | always @(posedge clk_100MHz) 19 | if(r_counter == 17'd71_633) begin 20 | r_counter <= 0; 21 | r_698Hz <= ~r_698Hz; 22 | end 23 | else 24 | r_counter <= r_counter + 1; 25 | 26 | assign o_698Hz = r_698Hz; 27 | 28 | endmodule 29 | -------------------------------------------------------------------------------- /FPGA Projects/Star Wars Imperial March Song/f_349Hz.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Authored by David J. Marion aka FPGA Dude 4 | // Created on 4/29/2022 5 | // Using Vivado 2021.2 6 | // Generating 349Hz signal for music tone 'f' 7 | ////////////////////////////////////////////////////////////////////////////////// 8 | 9 | module f_349Hz( 10 | input clk_100MHz, 11 | output o_349Hz 12 | ); 13 | 14 | // 100MHz / 143,266 / 2 = 349.0012Hz 15 | reg r_349Hz; 16 | reg [17:0] r_counter = 0; 17 | 18 | always @(posedge clk_100MHz) 19 | if(r_counter == 18'd143_266) begin 20 | r_counter <= 0; 21 | r_349Hz <= ~r_349Hz; 22 | end 23 | else 24 | r_counter <= r_counter + 1; 25 | 26 | assign o_349Hz = r_349Hz; 27 | 28 | endmodule 29 | 30 | -------------------------------------------------------------------------------- /FPGA Projects/Star Wars Imperial March Song/gS_415Hz.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Authored by David J. Marion aka FPGA Dude 4 | // Created on 4/29/2022 5 | // Using Vivado 2021.2 6 | // Generating 415Hz signal for music tone 'gS' 7 | ////////////////////////////////////////////////////////////////////////////////// 8 | 9 | module gS_415Hz( 10 | input clk_100MHz, 11 | output o_415Hz 12 | ); 13 | 14 | // 100MHz / 120,481 / 2 = 415.0032Hz 15 | reg r_415Hz; 16 | reg [17:0] r_counter = 0; 17 | 18 | always @(posedge clk_100MHz) 19 | if(r_counter == 18'd120_481) begin 20 | r_counter <= 0; 21 | r_415Hz <= ~r_415Hz; 22 | end 23 | else 24 | r_counter <= r_counter + 1; 25 | 26 | assign o_415Hz = r_415Hz; 27 | 28 | endmodule 29 | -------------------------------------------------------------------------------- /FPGA Projects/Traffic_Controller_Basys3/README.txt: -------------------------------------------------------------------------------- 1 | * The LEDs that are the traffic lights for this project, are set into a 2 | breadboard with resistors and driven by the Basys 3 PMODs. -------------------------------------------------------------------------------- /FPGA Projects/Traffic_Controller_Basys3/oneHz_gen.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module oneHz_gen( 4 | input clk_100MHz, // from BASYS 3 5 | input reset, // btnC on BASYS 3 6 | output clk_1Hz 7 | ); 8 | 9 | reg clk_1Hz_reg = 0; 10 | reg [25:0] counter_reg; 11 | 12 | always @(posedge clk_100MHz or posedge reset) begin 13 | if(reset) 14 | counter_reg <= 0; 15 | else 16 | if(counter_reg == 49_999_999) begin 17 | counter_reg <= 0; 18 | clk_1Hz_reg <= ~clk_1Hz_reg; 19 | end 20 | else 21 | counter_reg <= counter_reg + 1; 22 | end 23 | 24 | assign clk_1Hz = clk_1Hz_reg; 25 | 26 | endmodule 27 | -------------------------------------------------------------------------------- /FPGA Projects/Traffic_Controller_Basys3/sw_debounce.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module sw_debounce( 4 | input clk, 5 | input btn_in, // using a button, not switch, works the same 6 | output btn_out 7 | ); 8 | 9 | reg t0, t1, t2; 10 | 11 | always @(posedge clk) begin 12 | t0 <= btn_in; 13 | t1 <= t0; 14 | t2 <= t1; 15 | end 16 | 17 | assign btn_out = t2; 18 | 19 | endmodule 20 | -------------------------------------------------------------------------------- /FPGA Projects/Traffic_Controller_Basys3/traffic_controller.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module traffic_controller( 4 | input reset, // button 5 | input clk_100MHz, 6 | output [2:0] main_st, // LEDs 7 | output [2:0] cross_st // LEDs 8 | ); 9 | 10 | wire w_1Hz, w_reset; 11 | 12 | state_machine sm(.reset(w_reset), .clk_1Hz(w_1Hz), 13 | .main_st(main_st), .cross_st(cross_st)); 14 | oneHz_gen uno(.clk_100MHz(clk_100MHz), .reset(w_reset), .clk_1Hz(w_1Hz)); 15 | sw_debounce db(.clk(clk_100MHz), .btn_in(reset), .btn_out(w_reset) ); 16 | 17 | endmodule 18 | -------------------------------------------------------------------------------- /FPGA Projects/VGA Projects/Frogger_pt1/debounce.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module debounce( 4 | input clk, 5 | input btn_in, 6 | output btn_out 7 | ); 8 | 9 | reg r1, r2, r3; 10 | 11 | always @(posedge clk) begin 12 | r1 <= btn_in; 13 | r2 <= r1; 14 | r3 <= r2; 15 | end 16 | 17 | assign btn_out = r3; 18 | 19 | endmodule 20 | -------------------------------------------------------------------------------- /FPGA Projects/VGA Projects/Pong pt1/ball_rom.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module ball_rom( 4 | input [2:0] addr, // 3-bit address 5 | output reg [7:0] data // 8-bit data 6 | ); 7 | 8 | always @* 9 | case(addr) 10 | 3'b000 : data = 8'b00111100; // **** 11 | 3'b001 : data = 8'b01111110; // ****** 12 | 3'b010 : data = 8'b11111111; // ******** 13 | 3'b011 : data = 8'b11111111; // ******** 14 | 3'b100 : data = 8'b11111111; // ******** 15 | 3'b101 : data = 8'b11111111; // ******** 16 | 3'b110 : data = 8'b01111110; // ****** 17 | 3'b111 : data = 8'b00111100; // **** 18 | endcase 19 | 20 | endmodule 21 | -------------------------------------------------------------------------------- /FPGA Projects/VGA Projects/Pong pt1/debounce.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module debounce( 4 | input clk, // 100MHz 5 | input btn_in, 6 | output btn_out 7 | ); 8 | 9 | reg r1, r2, r3; 10 | 11 | always @(posedge clk) begin 12 | r1 <= btn_in; 13 | r2 <= r1; 14 | r3 <= r2; 15 | end 16 | 17 | assign btn_out = r3; 18 | 19 | endmodule 20 | -------------------------------------------------------------------------------- /FPGA Projects/VGA Projects/VGA Bouncing Square/top.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module top( 4 | input clk_100MHz, // from Basys 3 5 | input reset, // btnC on Basys 3 6 | output hsync, // VGA port on Basys 3 7 | output vsync, // VGA port on Basys 3 8 | output [11:0] rgb // to DAC, 3 bits to VGA port on Basys 3 9 | ); 10 | 11 | wire w_video_on, w_p_tick; 12 | wire [9:0] w_x, w_y; 13 | reg [11:0] rgb_reg; 14 | wire[11:0] rgb_next; 15 | 16 | vga_controller vc(.clk_100MHz(clk_100MHz), .reset(reset), .video_on(w_video_on), .hsync(hsync), 17 | .vsync(vsync), .p_tick(w_p_tick), .x(w_x), .y(w_y)); 18 | pixel_generation pg(.clk(clk_100MHz), .reset(reset), .video_on(w_video_on), 19 | .x(w_x), .y(w_y), .rgb(rgb_next)); 20 | 21 | always @(posedge clk_100MHz) 22 | if(w_p_tick) 23 | rgb_reg <= rgb_next; 24 | 25 | assign rgb = rgb_reg; 26 | 27 | endmodule 28 | -------------------------------------------------------------------------------- /FPGA Projects/VGA Projects/VGA Full Screen Text Editor/simple_dual_one_clock.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module dual_port_ram 4 | #( 5 | parameter DATA_SIZE = 7, 6 | parameter ADDR_SIZE = 12 7 | ) 8 | ( 9 | input clk, 10 | input we, 11 | input [ADDR_SIZE-1:0] addr_a, addr_b, 12 | input [DATA_SIZE-1:0] din_a, 13 | output [DATA_SIZE-1:0] dout_a, dout_b 14 | ); 15 | 16 | // Infer the RAM as block ram 17 | (* ram_style = "block" *) reg [DATA_SIZE-1:0] ram [2**ADDR_SIZE-1:0]; 18 | 19 | reg [ADDR_SIZE-1:0] addr_a_reg, addr_b_reg; 20 | 21 | // body 22 | always @(posedge clk) begin 23 | if(we) // write operation 24 | ram[addr_a] <= din_a; 25 | addr_a_reg <= addr_a; 26 | addr_b_reg <= addr_b; 27 | end 28 | 29 | // two read operations 30 | assign dout_a = ram[addr_a_reg]; 31 | assign dout_b = ram[addr_b_reg]; 32 | 33 | endmodule 34 | -------------------------------------------------------------------------------- /FPGA Projects/VGA Projects/VGA No Signal Screen/top.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module top( 4 | input clk_100MHz, // from Basys 3 5 | input reset, // btnC on Basys 3 6 | output hsync, // to VGA connector 7 | output vsync, // to VGA connector 8 | output [11:0] rgb // to DAC, 3 RGB bits to VGA connector 9 | ); 10 | 11 | wire w_video_on, w_p_tick; 12 | wire [9:0] w_x, w_y; 13 | reg [11:0] rgb_reg; 14 | wire [11:0] rgb_next; 15 | 16 | vga_controller vc(.clk_100MHz(clk_100MHz), .reset(reset), .video_on(w_video_on), 17 | .hsync(hsync), .vsync(vsync), .p_tick(w_p_tick), .x(w_x), .y(w_y)); 18 | pixel_generation pg(.video_on(w_video_on), .x(w_x), .y(w_y), .rgb(rgb_next)); 19 | 20 | // Buffer RGB 21 | always @(posedge clk_100MHz) 22 | if(w_p_tick) 23 | rgb_reg <= rgb_next; 24 | 25 | assign rgb = rgb_reg; 26 | 27 | endmodule 28 | -------------------------------------------------------------------------------- /FPGA Projects/VGA Projects/VGA Text Generation/top.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module top( 4 | input clk, // 100MHz on Basys 3 5 | input reset, // btnC on Basys 3 6 | output hsync, // to VGA connector 7 | output vsync, // to VGA connector 8 | output [11:0] rgb // to DAC, to VGA connector 9 | ); 10 | 11 | // signals 12 | wire [9:0] w_x, w_y; 13 | wire w_video_on, w_p_tick; 14 | reg [11:0] rgb_reg; 15 | wire [11:0] rgb_next; 16 | 17 | // VGA Controller 18 | vga_controller vga(.clk_100MHz(clk), .reset(reset), .hsync(hsync), .vsync(vsync), 19 | .video_on(w_video_on), .p_tick(w_p_tick), .x(w_x), .y(w_y)); 20 | // Text Generation Circuit 21 | ascii_test at(.clk(clk), .video_on(w_video_on), .x(w_x), .y(w_y), .rgb(rgb_next)); 22 | 23 | // rgb buffer 24 | always @(posedge clk) 25 | if(w_p_tick) 26 | rgb_reg <= rgb_next; 27 | 28 | // output 29 | assign rgb = rgb_reg; 30 | 31 | endmodule 32 | -------------------------------------------------------------------------------- /FPGA Projects/VGA Projects/frogger_pt2/btn_debounce.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module btn_debounce( 4 | input clk, 5 | input btn_in, 6 | output btn_out 7 | ); 8 | 9 | reg a, b, c; 10 | 11 | always @(posedge clk) begin 12 | a <= btn_in; 13 | b <= a; 14 | c <= b; 15 | end 16 | 17 | assign btn_out = c; 18 | 19 | endmodule 20 | -------------------------------------------------------------------------------- /FPGA Projects/VGA Projects/frogger_pt2/frog_down.bmp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/FPGADude/Digital-Design/4cb93eeaba434eb02c2e200060921fe0e5aebf03/FPGA Projects/VGA Projects/frogger_pt2/frog_down.bmp -------------------------------------------------------------------------------- /FPGA Projects/VGA Projects/frogger_pt2/frog_left.bmp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/FPGADude/Digital-Design/4cb93eeaba434eb02c2e200060921fe0e5aebf03/FPGA Projects/VGA Projects/frogger_pt2/frog_left.bmp -------------------------------------------------------------------------------- /FPGA Projects/VGA Projects/frogger_pt2/frog_right.bmp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/FPGADude/Digital-Design/4cb93eeaba434eb02c2e200060921fe0e5aebf03/FPGA Projects/VGA Projects/frogger_pt2/frog_right.bmp -------------------------------------------------------------------------------- /FPGA Projects/VGA Projects/frogger_pt2/frog_up.bmp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/FPGADude/Digital-Design/4cb93eeaba434eb02c2e200060921fe0e5aebf03/FPGA Projects/VGA Projects/frogger_pt2/frog_up.bmp -------------------------------------------------------------------------------- /FPGA Projects/Voting Machine Basys3/bin2bcd.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module bin2bcd( 4 | input [3:0] bin_in, 5 | output reg tens, 6 | output reg [3:0] ones 7 | ); 8 | 9 | always @* begin 10 | tens = bin_in / 10; 11 | ones = bin_in % 10; 12 | end 13 | 14 | endmodule 15 | -------------------------------------------------------------------------------- /FPGA Projects/Voting Machine Basys3/btn_debounce.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module btn_debounce( 4 | input clk, 5 | input btn_in, 6 | output btn_out 7 | ); 8 | 9 | reg t0, t1, t2; 10 | 11 | always @(posedge clk) begin 12 | t0 <= btn_in; 13 | t1 <= t0; 14 | t2 <= t1; 15 | end 16 | 17 | assign btn_out = t2; 18 | 19 | endmodule 20 | -------------------------------------------------------------------------------- /FPGA Projects/Voting Machine Basys3/led_driver.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module led_driver( 4 | input clk_2Hz, 5 | input enable, // enabled during open voting 6 | output reg [15:0] LED 7 | ); 8 | 9 | parameter S0 = 16'h5555; 10 | parameter S1 = 16'hAAAA; 11 | 12 | reg ctr = 0; 13 | 14 | always @(posedge clk_2Hz) 15 | ctr <= ~ctr; 16 | 17 | always @(posedge clk_2Hz) 18 | if(enable) 19 | if(ctr == 0) 20 | LED = S0; 21 | else 22 | LED = S1; 23 | else 24 | LED = 16'h8001; 25 | 26 | endmodule 27 | -------------------------------------------------------------------------------- /FPGA Projects/Voting Machine Basys3/oneHz_gen.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module oneHz_gen( 4 | input clk_100MHz, // from Basys 3 5 | output clk_1Hz 6 | ); 7 | 8 | reg [25:0] counter_reg = 0; 9 | reg clk_reg = 0; 10 | 11 | always @(posedge clk_100MHz) begin 12 | if(counter_reg == 49_999_999) begin 13 | counter_reg <= 0; 14 | clk_reg <= ~clk_reg; 15 | end 16 | else 17 | counter_reg <= counter_reg + 1; 18 | end 19 | 20 | assign clk_1Hz = clk_reg; 21 | 22 | endmodule 23 | -------------------------------------------------------------------------------- /FPGA Projects/Voting Machine Basys3/twoHz_gen.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module twoHz_gen( 4 | input clk_100MHz, // from Basys 3 5 | output clk_2Hz 6 | ); 7 | 8 | reg [24:0] counter_reg = 0; 9 | reg clk_reg = 0; 10 | 11 | always @(posedge clk_100MHz) begin 12 | if(counter_reg == 24_999_999) begin 13 | counter_reg <= 0; 14 | clk_reg <= ~clk_reg; 15 | end 16 | else 17 | counter_reg <= counter_reg + 1; 18 | end 19 | 20 | assign clk_2Hz = clk_reg; 21 | 22 | endmodule 23 | -------------------------------------------------------------------------------- /IEEE.1364-2005.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/FPGADude/Digital-Design/4cb93eeaba434eb02c2e200060921fe0e5aebf03/IEEE.1364-2005.pdf -------------------------------------------------------------------------------- /Learning VHDL/BASYS_3_FPGA/const_decoder3x8.xdc: -------------------------------------------------------------------------------- 1 | # Switches 2 | set_property PACKAGE_PIN V17 [get_ports {C}] 3 | set_property IOSTANDARD LVCMOS33 [get_ports {C}] 4 | set_property PACKAGE_PIN V16 [get_ports {B}] 5 | set_property IOSTANDARD LVCMOS33 [get_ports {B}] 6 | set_property PACKAGE_PIN W16 [get_ports {A}] 7 | set_property IOSTANDARD LVCMOS33 [get_ports {A}] 8 | 9 | # LEDs 10 | set_property PACKAGE_PIN U16 [get_ports {F0}] 11 | set_property IOSTANDARD LVCMOS33 [get_ports {F0}] 12 | set_property PACKAGE_PIN E19 [get_ports {F1}] 13 | set_property IOSTANDARD LVCMOS33 [get_ports {F1}] 14 | set_property PACKAGE_PIN U19 [get_ports {F2}] 15 | set_property IOSTANDARD LVCMOS33 [get_ports {F2}] 16 | set_property PACKAGE_PIN V19 [get_ports {F3}] 17 | set_property IOSTANDARD LVCMOS33 [get_ports {F3}] 18 | set_property PACKAGE_PIN W18 [get_ports {F4}] 19 | set_property IOSTANDARD LVCMOS33 [get_ports {F4}] 20 | set_property PACKAGE_PIN U15 [get_ports {F5}] 21 | set_property IOSTANDARD LVCMOS33 [get_ports {F5}] 22 | set_property PACKAGE_PIN U14 [get_ports {F6}] 23 | set_property IOSTANDARD LVCMOS33 [get_ports {F6}] 24 | set_property PACKAGE_PIN V14 [get_ports {F7}] 25 | set_property IOSTANDARD LVCMOS33 [get_ports {F7}] -------------------------------------------------------------------------------- /Learning VHDL/BASYS_3_FPGA/decoder3x8.vhd: -------------------------------------------------------------------------------- 1 | library IEEE; 2 | use IEEE.STD_LOGIC_1164.ALL; 3 | 4 | entity decoder3x8 is 5 | Port (A, B, C : in bit; 6 | F0, F1, F2, F3, F4, F5, F6, F7 : out bit 7 | ); 8 | end decoder3x8; 9 | 10 | architecture Behavioral of decoder3x8 is 11 | begin 12 | F0 <= (not A) and (not B) and (not C); 13 | F1 <= (not A) and (not B) and C; 14 | F2 <= (not A) and B and (not C); 15 | F3 <= (not A) and B and C; 16 | F4 <= A and (not B) and (not C); 17 | F5 <= A and (not B) and C; 18 | F6 <= A and B and (not C); 19 | F7 <= A and B and C; 20 | 21 | end Behavioral; 22 | -------------------------------------------------------------------------------- /Learning VHDL/BASYS_3_FPGA/decoder3x8_conditional.vhd: -------------------------------------------------------------------------------- 1 | library IEEE; 2 | use IEEE.STD_LOGIC_1164.ALL; 3 | 4 | entity decoder3x8_conditional is 5 | Port (ABC : in bit_vector(2 downto 0); 6 | F : out bit_vector(7 downto 0) 7 | ); 8 | end decoder3x8_conditional; 9 | 10 | architecture Behavioral of decoder3x8_conditional is 11 | begin 12 | F <= "00000001" when (ABC = "000") else 13 | "00000010" when (ABC = "001") else 14 | "00000100" when (ABC = "010") else 15 | "00001000" when (ABC = "011") else 16 | "00010000" when (ABC = "100") else 17 | "00100000" when (ABC = "101") else 18 | "01000000" when (ABC = "110") else 19 | "10000000" when (ABC = "111"); 20 | 21 | end Behavioral; 22 | -------------------------------------------------------------------------------- /Learning VHDL/BASYS_3_FPGA/decoder3x8_selected.vhd: -------------------------------------------------------------------------------- 1 | library IEEE; 2 | use IEEE.STD_LOGIC_1164.ALL; 3 | 4 | entity decoder3x8_selected is 5 | Port (ABC : in bit_vector(2 downto 0); 6 | F : out bit_vector(7 downto 0) 7 | ); 8 | end decoder3x8_selected; 9 | 10 | architecture Behavioral of decoder3x8_selected is 11 | begin 12 | with (ABC) select 13 | F <= "00000001" when "000", 14 | "00000010" when "001", 15 | "00000100" when "010", 16 | "00001000" when "011", 17 | "00010000" when "100", 18 | "00100000" when "101", 19 | "01000000" when "110", 20 | "10000000" when "111"; 21 | 22 | end Behavioral; 23 | -------------------------------------------------------------------------------- /Learning VHDL/Logic Gates Module/README.txt: -------------------------------------------------------------------------------- 1 | *** MY FIRST VHDL MODULAR DESIGN *** 2 | 3 | Implement 6 different basic logic gates on BASYS 3 FPGA board in one top module. 4 | 5 | 12 switches, 6 LEDs 6 | 7 | These are my first ever VHDL files. 8 | 9 | David J Marion -------------------------------------------------------------------------------- /Learning VHDL/Logic Gates Module/and_gate.vhd: -------------------------------------------------------------------------------- 1 | library IEEE; 2 | use IEEE.STD_LOGIC_1164.ALL; 3 | 4 | entity and_gate is 5 | Port ( 6 | in_1 : in std_logic; 7 | in_2 : in std_logic; 8 | y_out : out std_logic 9 | ); 10 | end and_gate; 11 | 12 | architecture Behavioral of and_gate is 13 | 14 | begin 15 | y_out <= in_1 and in_2; 16 | 17 | end Behavioral; 18 | -------------------------------------------------------------------------------- /Learning VHDL/Logic Gates Module/nand_gate.vhd: -------------------------------------------------------------------------------- 1 | library IEEE; 2 | use IEEE.STD_LOGIC_1164.ALL; 3 | 4 | entity nand_gate is 5 | Port ( 6 | in_1 : in std_logic; 7 | in_2 : in std_logic; 8 | y_out : out std_logic 9 | ); 10 | end nand_gate; 11 | 12 | architecture Behavioral of nand_gate is 13 | 14 | begin 15 | y_out <= in_1 nand in_2; 16 | 17 | end Behavioral; 18 | -------------------------------------------------------------------------------- /Learning VHDL/Logic Gates Module/nor_gate.vhd: -------------------------------------------------------------------------------- 1 | library IEEE; 2 | use IEEE.STD_LOGIC_1164.ALL; 3 | 4 | entity nor_gate is 5 | Port ( 6 | in_1 : in std_logic; 7 | in_2 : in std_logic; 8 | y_out : out std_logic 9 | ); 10 | end nor_gate; 11 | 12 | architecture Behavioral of nor_gate is 13 | 14 | begin 15 | y_out <= in_1 nor in_2; 16 | 17 | end Behavioral; 18 | -------------------------------------------------------------------------------- /Learning VHDL/Logic Gates Module/or_gate.vhd: -------------------------------------------------------------------------------- 1 | library IEEE; 2 | use IEEE.STD_LOGIC_1164.ALL; 3 | 4 | entity or_gate is 5 | Port ( 6 | in_1 : in std_logic; 7 | in_2 : in std_logic; 8 | y_out : out std_logic 9 | ); 10 | end or_gate; 11 | 12 | architecture Behavioral of or_gate is 13 | 14 | begin 15 | y_out <= in_1 or in_2; 16 | 17 | end Behavioral; 18 | -------------------------------------------------------------------------------- /Learning VHDL/Logic Gates Module/xnor_gate.vhd: -------------------------------------------------------------------------------- 1 | library IEEE; 2 | use IEEE.STD_LOGIC_1164.ALL; 3 | 4 | entity xnor_gate is 5 | Port ( 6 | in_1 : in std_logic; 7 | in_2 : in std_logic; 8 | y_out : out std_logic 9 | ); 10 | end xnor_gate; 11 | 12 | architecture Behavioral of xnor_gate is 13 | 14 | begin 15 | y_out <= in_1 xnor in_2; 16 | 17 | end Behavioral; 18 | -------------------------------------------------------------------------------- /Learning VHDL/Logic Gates Module/xor_gate.vhd: -------------------------------------------------------------------------------- 1 | library IEEE; 2 | use IEEE.STD_LOGIC_1164.ALL; 3 | 4 | entity xor_gate is 5 | Port ( 6 | in_1 : in std_logic; 7 | in_2 : in std_logic; 8 | y_out : out std_logic 9 | ); 10 | end xor_gate; 11 | 12 | architecture Behavioral of xor_gate is 13 | 14 | begin 15 | y_out <= in_1 xor in_2; 16 | 17 | end Behavioral; 18 | -------------------------------------------------------------------------------- /Master XDCs and Reference Manuals/Reference Manuals and User Guides/FPGAs/ZyboXADC_tutorial.pdf: -------------------------------------------------------------------------------- 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DUT( 10 | .addr(addr), 11 | .set_addr(set_addr), 12 | .en_data(en_data), 13 | .noi(noi), 14 | .data(data) 15 | ); 16 | 17 | initial begin 18 | $dumpfile("rom.vcd"); 19 | $dumpvars(0, rom_TB); 20 | end 21 | 22 | initial begin 23 | addr = 8'h00; 24 | set_addr = 1'b0; 25 | en_data = 1'b0; 26 | 27 | for(i = 0; i < noi; i = i + 1) begin 28 | addr = i; 29 | #20; 30 | set_addr = 1'b1; 31 | #20; 32 | set_addr = 1'b0; 33 | #20; 34 | en_data = 1'b1; 35 | #20; 36 | en_data = 1'b0; 37 | #20; 38 | end 39 | 40 | $finish; 41 | end 42 | 43 | endmodule -------------------------------------------------------------------------------- /Microprocessor CPU Series/7 Step Processor/ASM_BIN_ROM_Files/sum5.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/FPGADude/Digital-Design/4cb93eeaba434eb02c2e200060921fe0e5aebf03/Microprocessor CPU Series/7 Step Processor/ASM_BIN_ROM_Files/sum5.bin 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Processor/CPU_Information/InstructionSet.jpg -------------------------------------------------------------------------------- /Microprocessor CPU Series/7 Step Processor/Test_Benches/acc_TB.v: -------------------------------------------------------------------------------- 1 | // TEST BENCH for acc.v 2 | // 3 | // 4 | `timescale 1ns / 1ps 5 | module acc_TB; 6 | 7 | reg s, e; 8 | reg [7:0] d_in; 9 | wire [7:0] d_out; 10 | 11 | acc DUT( 12 | .s(s), 13 | .e(e), 14 | .d_in(d_in), 15 | .d_out(d_out) 16 | ); 17 | 18 | initial begin 19 | $dumpfile("acc.vcd"); 20 | $dumpvars(0, acc_TB); 21 | end 22 | 23 | initial begin 24 | s = 1'b0; 25 | e = 1'b0; 26 | d_in = 8'h55; 27 | #20; 28 | 29 | e = 1'b1; 30 | #20; 31 | e = 1'b0; 32 | #20; 33 | 34 | s = 1'b1; 35 | #20; 36 | s = 1'b0; 37 | #20; 38 | 39 | e = 1'b1; 40 | #20; 41 | e = 1'b0; 42 | #20; 43 | 44 | $finish; 45 | end 46 | 47 | endmodule -------------------------------------------------------------------------------- /Microprocessor CPU Series/7 Step Processor/Test_Benches/bus1_TB.v: -------------------------------------------------------------------------------- 1 | // Test bench for bus1.v 2 | // *** TEST GOOD *** 3 | 4 | module bus1_TB; 5 | reg [7:0] d_in; 6 | reg b1; 7 | wire [7:0] d_out; 8 | 9 | bus1 DUT( 10 | .d_in(d_in), 11 | .e_b1(b1), 12 | .d_out(d_out) 13 | ); 14 | 15 | initial begin 16 | $dumpfile("bus1.vcd"); 17 | $dumpvars(0, bus1_TB); 18 | end 19 | 20 | initial begin 21 | d_in = 8'haa; 22 | b1 = 0; 23 | #20 b1 = 1; 24 | #20 b1 = 0; 25 | #20 d_in = 8'h66; 26 | #20 b1 = 1; 27 | #20 b1 = 0; 28 | #20 $finish; 29 | end 30 | 31 | endmodule -------------------------------------------------------------------------------- /Microprocessor CPU Series/7 Step Processor/Test_Benches/clock_gen_TB.v: -------------------------------------------------------------------------------- 1 | // From the book: "But How Do It Know?" pg. 96, 97 2 | // Written by: J. Clark Scott 3 | // 4 | // Verilog HDL implementation of the computer described in the book. 5 | // Created by: David J. Marion 6 | // Date: 11.15.2022 7 | // 8 | // TEST BENCH for Clock Module 9 | `timescale 1ns / 1ps 10 | module clock_gen_TB; 11 | 12 | reg sys_clk; 13 | wire clk, clk_e, clk_s; 14 | 15 | clock_gen DUT( 16 | .sys_clk(sys_clk), 17 | .clk(clk), 18 | .clk_e(clk_e), 19 | .clk_s(clk_s) 20 | ); 21 | 22 | always #1 sys_clk = ~sys_clk; 23 | 24 | initial begin 25 | $dumpfile("clk_gen.vcd"); 26 | $dumpvars(0, clock_gen_TB); 27 | end 28 | 29 | initial begin 30 | sys_clk = 1'b1; // Initialize system clock 31 | #40 $finish; 32 | end 33 | 34 | endmodule -------------------------------------------------------------------------------- /Microprocessor CPU Series/7 Step Processor/Test_Benches/flags_TB.v: -------------------------------------------------------------------------------- 1 | // Test bench for flags.v 2 | 3 | module flags_TB; 4 | reg s; 5 | reg [3:0] data_driver; 6 | wire [3:0] data_receiver; 7 | 8 | flags DUT( 9 | .s(s), 10 | .caez_in(data_driver), 11 | .caez_out(data_receiver) 12 | ); 13 | initial begin 14 | $dumpfile("flags.vcd"); 15 | $dumpvars(0, flags_TB); 16 | end 17 | 18 | initial begin 19 | s = 0; 20 | data_driver = 4'h1; 21 | #1 s = 1; 22 | #1 s = 0; 23 | #1; 24 | data_driver = 4'h6; 25 | #1 s = 1; 26 | #1 s = 0; 27 | #1; 28 | data_driver = 4'ha; 29 | #1 s = 1; 30 | #1 s = 0; 31 | 32 | #1 $finish; 33 | end 34 | 35 | endmodule -------------------------------------------------------------------------------- /Microprocessor CPU Series/7 Step Processor/Test_Benches/iar_TB.v: -------------------------------------------------------------------------------- 1 | // TEST BENCH for iar.v 2 | // Comments: Device Under Test (iar.v) is (** VERIFIED **) 3 | // -------------------------------------------------------------------------------------- 4 | `timescale 1ns / 1ps 5 | module iar_TB; 6 | 7 | reg reset; 8 | reg s, e; 9 | reg [7:0] a_in; 10 | wire [7:0] a_out; 11 | 12 | iar DUT(.reset(reset), .s(s), .e(e), .a_in(a_in), .a_out(a_out)); 13 | 14 | initial begin 15 | $dumpfile("iar.vcd"); 16 | $dumpvars(0, iar_TB); 17 | end 18 | 19 | initial begin 20 | reset = 1'b0; 21 | s = 1'b0; 22 | e = 1'b0; 23 | a_in = 8'haa; 24 | #20; 25 | s = 1'b1; 26 | #20; 27 | s = 1'b0; 28 | #20; 29 | e = 1'b1; 30 | #20; 31 | e = 1'b0; 32 | #20; 33 | 34 | reset = 1'b1; 35 | #20; 36 | reset = 1'b0; 37 | e = 1'b1; 38 | #20; 39 | e = 1'b0; 40 | 41 | #20 $finish; 42 | end 43 | 44 | endmodule -------------------------------------------------------------------------------- /Microprocessor CPU Series/7 Step Processor/Test_Benches/ir_TB.v: -------------------------------------------------------------------------------- 1 | // TEST BENCH for ir.v 2 | // Comments: Device Under Test (ir.v) is (** VERIFIED **) 3 | // -------------------------------------------------------------------------------------- 4 | `timescale 1ns / 1ps 5 | module ir_TB; 6 | 7 | reg s; 8 | reg [7:0] i_in; 9 | wire [7:0] i_out; 10 | 11 | ir DUT(.s(s), .i_in(i_in), .i_out(i_out)); 12 | 13 | initial begin 14 | $dumpfile("ir.vcd"); 15 | $dumpvars(0, ir_TB); 16 | end 17 | 18 | initial begin 19 | s = 1'b0; 20 | i_in = 8'haa; 21 | #20; 22 | s = 1'b1; 23 | #20; 24 | s = 1'b0; 25 | #20; 26 | 27 | i_in = 8'h55; 28 | #20; 29 | s = 1'b1; 30 | #20; 31 | s = 1'b0; 32 | 33 | #20 $finish; 34 | end 35 | 36 | endmodule -------------------------------------------------------------------------------- /Microprocessor CPU Series/7 Step Processor/Test_Benches/rom_TB.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | module rom_TB; 3 | 4 | reg [7:0] addr; 5 | reg set_addr, en_data; 6 | wire [7:0] noi, data; 7 | integer i; 8 | 9 | sum5_rom DUT( 10 | .addr(addr), 11 | .set_addr(set_addr), 12 | .en_data(en_data), 13 | .noi(noi), 14 | .data(data) 15 | ); 16 | 17 | initial begin 18 | $dumpfile("rom.vcd"); 19 | $dumpvars(0, rom_TB); 20 | end 21 | 22 | initial begin 23 | addr = 8'h00; 24 | set_addr = 1'b0; 25 | en_data = 1'b0; 26 | 27 | for(i = 0; i < noi; i = i + 1) begin 28 | addr = i; 29 | #20; 30 | set_addr = 1'b1; 31 | #20; 32 | set_addr = 1'b0; 33 | #20; 34 | en_data = 1'b1; 35 | #20; 36 | en_data = 1'b0; 37 | #20; 38 | end 39 | 40 | $finish; 41 | end 42 | 43 | endmodule -------------------------------------------------------------------------------- /Microprocessor CPU Series/7 Step Processor/Test_Benches/stepper_TB.v: -------------------------------------------------------------------------------- 1 | // From the book: "But How Do It Know?" pg. 102 2 | // Written by: J. Clark Scott 3 | // 4 | // Verilog HDL implementation of the computer described in the book. 5 | // Created by: David J. Marion 6 | // Date: 11.15.2022 7 | // 8 | // TEST BENCH for Stepper Module 9 | `timescale 1ns / 1ps 10 | module stepper_TB; 11 | 12 | reg clk; 13 | reg reset; 14 | wire [5:0] step; 15 | 16 | stepper STEPPER( 17 | .clk(clk), 18 | .reset(reset), 19 | .step(step) 20 | ); 21 | 22 | always #1 clk = ~clk; 23 | 24 | initial begin 25 | $dumpfile("stepper.vcd"); 26 | $dumpvars(0, stepper_TB); 27 | end 28 | 29 | initial begin 30 | clk = 0; // Initialize clock 31 | reset = 1; 32 | #10 reset = 0; 33 | 34 | #50 reset = 1; 35 | #20 reset = 0; 36 | 37 | #50 $finish; 38 | end 39 | 40 | 41 | endmodule -------------------------------------------------------------------------------- /Microprocessor CPU Series/7 Step Processor/Test_Benches/tmp_TB.v: -------------------------------------------------------------------------------- 1 | // TEST BENCH for tmp.v 2 | // Comments: Device Under Test (tmp.v) is (** VERIFIED **) 3 | // -------------------------------------------------------------------------------------- 4 | `timescale 1ns / 1ps 5 | module tmp_TB; 6 | reg s; 7 | reg [7:0] t_in; 8 | wire [7:0] t_out; 9 | 10 | tmp DUT(.s(s), .t_in(t_in), .t_out(t_out)); 11 | 12 | initial begin 13 | $dumpfile("tmp.vcd"); 14 | $dumpvars(0, tmp_TB); 15 | end 16 | 17 | initial begin 18 | s = 1'b0; 19 | 20 | t_in = 8'h11; 21 | #20; 22 | s = 1'b1; 23 | #20; 24 | s = 1'b0; 25 | #20; 26 | 27 | t_in = 8'h55; 28 | s = 1'b1; 29 | #20; 30 | s = 1'b0; 31 | #20; 32 | 33 | t_in = 8'haa; 34 | s = 1'b1; 35 | #20; 36 | s = 1'b0; 37 | #20; 38 | 39 | t_in = 8'hff; 40 | s = 1'b1; 41 | #20; 42 | s = 1'b0; 43 | #20; 44 | 45 | 46 | $finish; 47 | end 48 | 49 | endmodule -------------------------------------------------------------------------------- /Microprocessor CPU Series/7 Step Processor/acc.v: -------------------------------------------------------------------------------- 1 | // From the book: "But How Do It Know?" pg. 67 2 | // Written by: J. Clark Scott 3 | // 4 | // Verilog HDL implementation of the computer described in the book. 5 | // Created by: David J. Marion 6 | // Date: 11.15.2022 7 | // 8 | // Accumulator Register 9 | // 10 | // * No changes required for CPU_B 11 | // 12 | // * Changed output assignment from 8'bz to 8'b0 13 | // *********************************************************************** 14 | 15 | `timescale 1ns / 1ps 16 | module acc( 17 | input s, 18 | input e, 19 | input [7:0] d_in, 20 | output [7:0] d_out 21 | ); 22 | 23 | reg [7:0] data_reg = 8'h00; 24 | 25 | always @(*) 26 | if(s == 1'b1) 27 | data_reg = d_in; 28 | 29 | assign d_out = e ? data_reg : 8'b0; 30 | 31 | endmodule -------------------------------------------------------------------------------- /Microprocessor CPU Series/7 Step Processor/bus1.v: -------------------------------------------------------------------------------- 1 | // From the book: "But How Do It Know?" pg. 90 2 | // Written by: J. Clark Scott 3 | // 4 | // Verilog HDL implementation of the computer described in the book. 5 | // Created by: David J. Marion 6 | // Date: 11.15.2022 7 | // 8 | // Provides 0000_0001 at B input to ALU 9 | // Bus 1 10 | // 11 | // * No changes required for CPU_B 12 | // ***************************************************************************** 13 | 14 | `timescale 1ns / 1ps 15 | module bus1( 16 | input e_b1, 17 | input [7:0] d_in, 18 | output [7:0] d_out 19 | ); 20 | 21 | assign d_out = e_b1 ? 8'h01 : d_in; 22 | 23 | endmodule -------------------------------------------------------------------------------- /Microprocessor CPU Series/7 Step Processor/cpu_b_test_list.txt: -------------------------------------------------------------------------------- 1 | acc.v 2 | alu.v 3 | bus1.v 4 | clock_gen.v 5 | control.v 6 | data_bus.v 7 | dec2x4.v 8 | dec3x8.v 9 | flags.v 10 | gpr.v 11 | gpr_file.v 12 | iar.v 13 | io.v 14 | ir.v 15 | ram.v 16 | stepper.v 17 | tmp.v 18 | cpu_b.v 19 | fsm_load_ram.v 20 | fibonacci_rom.v 21 | cpu_init.v 22 | cpu_b_test.v 23 | -------------------------------------------------------------------------------- /Microprocessor CPU Series/7 Step Processor/dec2x4.v: -------------------------------------------------------------------------------- 1 | // From the book: "But How Do It Know?" pg. 102 2 | // Written by: J. Clark Scott 3 | // 4 | // Verilog HDL implementation of the computer described in the book. 5 | // Created by: David J. Marion 6 | // Date: 11.15.2022 7 | // 8 | // 2 to 4 Decoder in the Control Unit 9 | // 10 | // * No changes required for CPU_B 11 | // ****************************************************************************** 12 | `timescale 1ns / 1ps 13 | module dec2x4( 14 | input [1:0] dec_in, // 2-bit select 15 | output [3:0] dec_out // 4 output bits 16 | ); 17 | 18 | assign dec_out[3] = (dec_in == 2'b11) ? 1'b1 : 1'b0; 19 | assign dec_out[2] = (dec_in == 2'b10) ? 1'b1 : 1'b0; 20 | assign dec_out[1] = (dec_in == 2'b01) ? 1'b1 : 1'b0; 21 | assign dec_out[0] = (dec_in == 2'b00) ? 1'b1 : 1'b0; 22 | 23 | endmodule -------------------------------------------------------------------------------- /Microprocessor CPU Series/7 Step Processor/dec3x8.v: -------------------------------------------------------------------------------- 1 | // From the book: "But How Do It Know?" pg. 102 2 | // Written by: J. Clark Scott 3 | // 4 | // Verilog HDL implementation of the computer described in the book. 5 | // Created by: David J. Marion 6 | // Date: 11.15.2022 7 | // 8 | // 3 to 8 Decoder in the Control Unit 9 | // 10 | // * No changes required for CPU_B 11 | // ****************************************************************************** 12 | `timescale 1ns / 1ps 13 | module dec3x8( 14 | input [2:0] dec_in, // 3-bit select 15 | output [7:0] dec_out // 8 output bits 16 | ); 17 | 18 | assign dec_out[7] = (dec_in == 3'b111) ? 1'b1 : 1'b0; 19 | assign dec_out[6] = (dec_in == 3'b110) ? 1'b1 : 1'b0; 20 | assign dec_out[5] = (dec_in == 3'b101) ? 1'b1 : 1'b0; 21 | assign dec_out[4] = (dec_in == 3'b100) ? 1'b1 : 1'b0; 22 | assign dec_out[3] = (dec_in == 3'b011) ? 1'b1 : 1'b0; 23 | assign dec_out[2] = (dec_in == 3'b010) ? 1'b1 : 1'b0; 24 | assign dec_out[1] = (dec_in == 3'b001) ? 1'b1 : 1'b0; 25 | assign dec_out[0] = (dec_in == 3'b000) ? 1'b1 : 1'b0; 26 | 27 | endmodule -------------------------------------------------------------------------------- /Microprocessor CPU Series/7 Step Processor/flags.v: -------------------------------------------------------------------------------- 1 | // From the book: "But How Do It Know?" pg. 112 2 | // Written by: J. Clark Scott 3 | // 4 | // Verilog HDL implementation of the computer described in the book. 5 | // Created by: David J. Marion 6 | // Date: 11.16.2022 7 | // 8 | // Flags Register 9 | // 10 | // * No changes required for CPU_B 11 | // ****************************************************************************** 12 | 13 | `timescale 1ns / 1ps 14 | module flags( 15 | input s, 16 | input [3:0] caez_in, 17 | output reg [3:0] caez_out = 4'h0 18 | ); 19 | 20 | always @(*) 21 | if(s == 1'b1) 22 | caez_out <= caez_in; 23 | 24 | endmodule -------------------------------------------------------------------------------- /Microprocessor CPU Series/7 Step Processor/gpr.v: -------------------------------------------------------------------------------- 1 | // From the book: "But How Do It Know?" pg. 67 2 | // Written by: J. Clark Scott 3 | // 4 | // Verilog HDL implementation of the computer described in the book. 5 | // Created by: David J. Marion 6 | // Date: 6.3.2023 7 | // 8 | // General Purpose Register 9 | // 10 | // * Changes required for CPU_B: 11 | // - remove inout port and change to have input and output ports 12 | // ******************************************************************************************* 13 | 14 | `timescale 1ns / 1ps 15 | module gpr( 16 | input s, // set 17 | input e, // enable 18 | input [7:0] d_in, // data in 19 | output [7:0] d_out // data out 20 | ); 21 | 22 | reg [7:0] data_reg = 8'h00; 23 | 24 | always @(*) 25 | if(s == 1'b1) 26 | data_reg <= d_in; 27 | 28 | assign d_out = e ? data_reg : 8'h00; 29 | 30 | endmodule -------------------------------------------------------------------------------- /Microprocessor CPU Series/7 Step Processor/gpr_file.v: -------------------------------------------------------------------------------- 1 | // Created for CPU_B 2 | // Written by David J. Marion 3 | // Date: 6.2.2023 4 | // Purpose: 5 | // Group all general purpose registers into one module that 6 | // will be a register file, for the CPU_B implementation. 7 | // ******************************************************************* 8 | 9 | `timescale 1ns / 1ps 10 | module gpr_file( 11 | input [7:0] d_in, // data in 12 | input s_r0, s_r1, s_r2, s_r3, // gpr set signals 13 | input e_r0, e_r1, e_r2, e_r3, // gpr enable signals 14 | output [7:0] d_out // data out 15 | ); 16 | wire [7:0] o_r0, o_r1, o_r2, o_r3; 17 | 18 | gpr R0(.s(s_r0), .e(e_r0), .d_in(d_in), .d_out(o_r0)); 19 | gpr R1(.s(s_r1), .e(e_r1), .d_in(d_in), .d_out(o_r1)); 20 | gpr R2(.s(s_r2), .e(e_r2), .d_in(d_in), .d_out(o_r2)); 21 | gpr R3(.s(s_r3), .e(e_r3), .d_in(d_in), .d_out(o_r3)); 22 | 23 | assign d_out = e_r0 ? o_r0 : e_r1 ? o_r1 : 24 | e_r2 ? o_r2 : e_r3 ? o_r3 : 8'h00; 25 | 26 | endmodule -------------------------------------------------------------------------------- /Microprocessor CPU Series/7 Step Processor/iar.v: -------------------------------------------------------------------------------- 1 | // From the book: "But How Do It Know?" pg. 112 2 | // Written by: J. Clark Scott 3 | // 4 | // Verilog HDL implementation of the computer described in the book. 5 | // Created by: David J. Marion 6 | // Date: 11.15.2022 7 | // Edited: 6.3.23 8 | // Instruction Address Register (IAR) 9 | // * Changes required for CPU_B: 10 | // - remove inout port and change to have input and output ports 11 | // ******************************************************************************************* 12 | 13 | `timescale 1ns / 1ps 14 | module iar( 15 | input reset, // system reset 16 | input s, // set 17 | input e, // enable 18 | input [7:0] a_in, // address in 19 | output [7:0] a_out // address out 20 | ); 21 | 22 | reg [7:0] addr_reg = 8'h00; // initialize IAR to beginning of RAM memory space 23 | 24 | always @(*) begin 25 | if(reset) 26 | addr_reg = 8'h00; // reset instruction address to the beginning of memory space 27 | else if(s) 28 | addr_reg = a_in; // set IAR with input address 29 | end 30 | 31 | assign a_out = e ? addr_reg : 8'h00; 32 | 33 | endmodule -------------------------------------------------------------------------------- /Microprocessor CPU Series/7 Step Processor/ir.v: -------------------------------------------------------------------------------- 1 | // From the book: "But How Do It Know?" pg. 112 2 | // Written by: J. Clark Scott 3 | // 4 | // Verilog HDL implementation of the computer described in the book. 5 | // Created by: David J. Marion 6 | // Date: 11.15.2022 7 | // 8 | // Instruction Register (IR) 9 | // 10 | // * No changes required for CPU_B 11 | // ************************************************************************************** 12 | 13 | `timescale 1ns / 1ps 14 | module ir( 15 | input s, // set 16 | input [7:0] i_in, // instruction in 17 | output reg [7:0] i_out = 8'h00 // instruction out 18 | ); 19 | 20 | always @(*) 21 | if(s == 1'b1) 22 | i_out <= i_in; 23 | 24 | endmodule -------------------------------------------------------------------------------- /Microprocessor CPU Series/7 Step Processor/stepper.v: -------------------------------------------------------------------------------- 1 | // From the book: "But How Do It Know?" pg. 102 2 | // Written by: J. Clark Scott 3 | // 4 | // Verilog HDL implementation of the computer described in the book. 5 | // Created by: David J. Marion 6 | // Date: 4.18.2023 7 | // Edited: 6.14.23 8 | // Stepper Module 9 | // 10 | // * Adding a step 0 for a reset state. 11 | // * Now the CPU is a 7-Step Processor again. 12 | // ************************************************************************************** 13 | `timescale 1ns / 1ps 14 | module stepper( 15 | input clk, // stepper clock 16 | input reset, // system reset 17 | output [5:0] step // control unit signals 18 | ); 19 | 20 | reg [6:0] step_reg = 7'b100_0000; // start at step 0 21 | 22 | always @(posedge clk or posedge reset) begin 23 | if (reset) 24 | step_reg <= 7'b100_0000; // system reset back to step 0 25 | else 26 | if (step_reg == 7'b000_0001) // when we get to step 6 27 | step_reg <= 7'b010_0000; // go back to step 1, not step 0 28 | else 29 | step_reg <= step_reg >> 1; // otherwise, shift right by 1 to next step 30 | end 31 | 32 | assign step = step_reg[5:0]; // Only output 6/7 steps 33 | 34 | endmodule 35 | -------------------------------------------------------------------------------- /Microprocessor CPU Series/7 Step Processor/tmp.v: -------------------------------------------------------------------------------- 1 | // From the book: "But How Do It Know?" pg. 67 2 | // Written by: J. Clark Scott 3 | // 4 | // Verilog HDL implementation of the computer described in the book. 5 | // Created by: David J. Marion 6 | // Date: 11.15.2022 7 | // 8 | // Temporary Register 9 | // 10 | // * No changes required for CPU_B 11 | // ************************************************************************************** 12 | 13 | `timescale 1ns / 1ps 14 | module tmp( 15 | input s, 16 | input [7:0] t_in, 17 | output reg [7:0] t_out = 8'h00 18 | ); 19 | 20 | always @(*) 21 | if(s == 1'b1) 22 | t_out <= t_in; 23 | 24 | endmodule -------------------------------------------------------------------------------- /Modules with Simulations/Binary to BCD Converter/byte2bcd.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | // Binary byte to binary coded decimal(BCD) converter 4 | // Authored by David J Marion 5 | 6 | module byte2bcd( 7 | input [7:0] byte_in, // 8 bits, value 0 - 255 8 | output [11:0] bcd_out // 12 bits of 3 nibbles 9 | ); 10 | 11 | reg [3:0] hundreds, tens, ones; // 3 nibbles 12 | reg [6:0] temp_reg; // temp storage for value up to 99 13 | 14 | always @(*) begin // Ex. using 255 as value 15 | hundreds = byte_in / 100; // = 2, the rest is truncated 16 | temp_reg = byte_in % 100; // = 55, the remainder 17 | tens = temp_reg / 10; // = 5, the rest is truncated 18 | ones = temp_reg % 10; // = 5, the remainder 19 | end 20 | 21 | assign bcd_out = {hundreds, tens, ones}; // = 255, 0010 0101 0101 22 | 23 | endmodule 24 | -------------------------------------------------------------------------------- /Modules with Simulations/Binary to BCD Converter/sim_byte2bcd.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | // Test bench for the byte2bcd module 4 | // Authored by David J Marion 5 | 6 | module sim_byte2bcd; 7 | 8 | reg [7:0] byte_in; 9 | wire [11:0] bcd_out; 10 | integer i; 11 | 12 | byte2bcd DUT(.byte_in(byte_in), .bcd_out(bcd_out)); 13 | 14 | initial begin 15 | for(i = 0; i < 256; i = i + 1) begin 16 | byte_in = i; 17 | #3; 18 | end 19 | end 20 | endmodule 21 | -------------------------------------------------------------------------------- /Modules with Simulations/Fibonacci Sequence Generator/fibonacci.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | // Parameterized Fibonacci sequence generator 4 | // Authored by David J Marion 5 | 6 | module fibonacci 7 | #(parameter W = 16) 8 | ( 9 | input clk, 10 | input reset, 11 | output [W-1:0] fib_out 12 | ); 13 | 14 | reg [W-1:0] num1, num2; 15 | 16 | always @(posedge clk or negedge reset) begin 17 | if(~reset) begin 18 | num1 <= 0; 19 | num2 <= 1; 20 | end 21 | else begin 22 | num1 <= num2; 23 | num2 <= fib_out; 24 | end 25 | end 26 | 27 | assign fib_out = num1 + num2; 28 | 29 | endmodule 30 | -------------------------------------------------------------------------------- /Modules with Simulations/Fibonacci Sequence Generator/sim_fibonacci.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | // Test bench for the parameterized Fibonacci sequence generator 4 | // Authored by David J Marion 5 | 6 | module sim_fibonacci; 7 | 8 | parameter N = 32; // Only need to change this to resize output width 9 | reg clk, reset; 10 | wire [N-1:0] fib_out; 11 | 12 | fibonacci #(.W(N)) DUT(.clk(clk), .reset(reset), .fib_out(fib_out)); 13 | 14 | always #2 clk = ~clk; 15 | 16 | initial begin 17 | clk = 0; 18 | reset = 0; 19 | #4 reset = 1; 20 | 21 | #500 $finish; 22 | end 23 | 24 | endmodule 25 | -------------------------------------------------------------------------------- /Modules with Simulations/Multiplexer 4x1 Parameterized/mux4x1.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | // This Verilog module contains a parameterized 4x1 multiplexer 4 | // Authored by David J Marion 5 | 6 | module mux4x1 7 | #(parameter W = 4) // choose the bit width 8 | ( 9 | input [W-1:0] A, 10 | input [W-1:0] B, 11 | input [W-1:0] C, 12 | input [W-1:0] D, 13 | input [1:0] select, 14 | output reg [W-1:0] mux_out 15 | ); 16 | 17 | always @(select) begin 18 | case(select) 19 | 2'b00 : mux_out = A; 20 | 2'b01 : mux_out = B; 21 | 2'b10 : mux_out = C; 22 | 2'b11 : mux_out = D; 23 | default : mux_out = 'b0; 24 | endcase 25 | end 26 | 27 | endmodule 28 | -------------------------------------------------------------------------------- /Modules with Simulations/Multiplexer 4x1 Parameterized/sim_4x1mux.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | // Test bench for the parameterized 4x1 multiplexer 4 | // Authored by David J Marion 5 | 6 | module sim_4x1mux; 7 | 8 | reg [3:0] A, B, C, D; 9 | reg [1:0] select; 10 | wire [3:0] mux_out; 11 | 12 | // Instantiate device under test 13 | mux4x1 DUT(.A(A), .B(B), .C(C), .D(D), .select(select), .mux_out(mux_out)); 14 | 15 | initial begin 16 | A = 4'b0000; // 0 17 | B = 4'b0101; // 5 18 | C = 4'b1010; // 10 19 | D = 4'b1111; // 15 20 | select = 2'b00; 21 | #2 select = 2'b01; 22 | #2 select = 2'b10; 23 | #2 select = 2'b11; 24 | #2 select = 2'b00; 25 | 26 | #2 $finish; 27 | end 28 | 29 | endmodule 30 | -------------------------------------------------------------------------------- /Modules with Simulations/PWM Generator/pwm_gen.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | // Verilog module to generate a pulse width modulated signal 4 | // Authored by David J Marion 5 | 6 | module pwm_gen( 7 | input clk, 8 | output pwm30, 9 | output pwm50, 10 | output pwm70, 11 | output pwm90 12 | ); 13 | 14 | reg [6:0] counter = 0; // to hold the value of 99 15 | 16 | always @(posedge clk) begin 17 | if (counter < 100) 18 | counter <= counter + 1; 19 | else 20 | counter <= 0; 21 | end 22 | 23 | 24 | assign pwm30 = (counter < 30) ? 1 : 0; // Create a 30% duty cycle 25 | 26 | assign pwm50 = (counter < 50) ? 1 : 0; // Create a 50% duty cycle 27 | 28 | assign pwm70 = (counter < 70) ? 1 : 0; // Create a 70% duty cycle 29 | 30 | assign pwm90 = (counter < 90) ? 1 : 0; // Create a 90% duty cycle 31 | 32 | endmodule 33 | -------------------------------------------------------------------------------- /Modules with Simulations/PWM Generator/sim_pwm_gen.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | // Test bench for pwm generator 4 | // Authored by David J Marion 5 | 6 | module sim_pwm_gen; 7 | 8 | reg clk = 0; 9 | wire pwm30, pwm50, pwm70, pwm90; 10 | 11 | pwm_gen1 DUT( 12 | .clk(clk), 13 | .pwm30(pwm30), 14 | .pwm50(pwm50), 15 | .pwm70(pwm70), 16 | .pwm90(pwm90)); 17 | 18 | always #10 clk = ~clk; 19 | 20 | endmodule 21 | -------------------------------------------------------------------------------- /Modules with Simulations/Register File/reg_file.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Authored by David J. Marion aka FPGA Dude 4 | // Created on 4/20/2022 5 | // 6 | // Description: This module contains a parameterized register file. 7 | // 8 | ////////////////////////////////////////////////////////////////////////////////// 9 | 10 | module register_file 11 | #( parameter W_ADDR = 3, 12 | W_DATA = 8 13 | ) 14 | ( 15 | input clk, 16 | input we, // write enable 17 | input [W_ADDR-1:0] w_address, // write address 18 | input [W_ADDR-1:0] r_address, // read address 19 | input [W_DATA-1:0] w_data, // data to write to reg 20 | output [W_DATA-1:0] r_data // data read from reg 21 | ); 22 | 23 | reg [W_DATA-1:0] reg_file [2**W_ADDR-1:0]; // create the register file 24 | 25 | always @(posedge clk) 26 | if(we) // if write enabled 27 | reg_file[w_address] <= w_data; 28 | 29 | assign r_data = reg_file[r_address]; 30 | 31 | endmodule 32 | -------------------------------------------------------------------------------- /Modules with Simulations/SR Latch/sim_sr_latch.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module sim_sr_latch; 4 | 5 | reg set, reset; // regs to drive inputs 6 | wire q; // wire to capture output 7 | 8 | sr_latch DUT(.s(set), .r(reset), .q(q)); 9 | 10 | initial begin 11 | set = 0; 12 | reset = 1; // reset q to 0 13 | #1 14 | reset = 0; 15 | #5 16 | set = 1; 17 | #1 18 | set = 0; 19 | #5 20 | reset = 1; 21 | #1 22 | reset = 0; 23 | // Driving set and reset at same time 24 | #5 25 | set = 1; 26 | reset = 1; 27 | #2 28 | set = 0; 29 | reset = 0; 30 | #5 31 | reset = 1; 32 | set = 1; 33 | #1 $finish; 34 | end 35 | 36 | endmodule 37 | -------------------------------------------------------------------------------- /Modules with Simulations/SR Latch/sr_latch.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | // S R input combinations: 4 | // 0 0 -> no change to q 5 | // 0 1 -> q = 0 6 | // 1 0 -> q = 1 7 | // 1 1 -> should not be allowed to happen. what should the value of q be? 8 | 9 | module sr_latch( 10 | input s, // set 11 | input r, // reset 12 | output reg q // latched value 13 | ); 14 | 15 | always @* 16 | if(s) 17 | q = 1; 18 | else if(r) 19 | q = 0; 20 | 21 | endmodule 22 | -------------------------------------------------------------------------------- /Modules with Simulations/Sequence Detector D-Flip Flops/d_ff.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module d_ff( 4 | input clock, 5 | input reset, 6 | input d, 7 | output reg q 8 | ); 9 | 10 | always @(posedge clock or negedge reset) begin 11 | if(~reset) 12 | q <= 0; 13 | else 14 | q <= d; 15 | end 16 | 17 | endmodule 18 | -------------------------------------------------------------------------------- /Modules with Simulations/Sequence Detector D-Flip Flops/seq_det_101.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module seq_det_101( 4 | input clock, 5 | input reset, 6 | input data, 7 | output detected_101 8 | ); 9 | 10 | wire a2b, b2c, c; 11 | 12 | d_ff dA(.clock(clock), .reset(reset), .d(data), .q(a2b)); 13 | d_ff dB(.clock(clock), .reset(reset), .d(a2b), .q(b2c)); 14 | d_ff dC(.clock(clock), .reset(reset), .d(b2c), .q(c)); 15 | 16 | assign detected_101 = a2b & ~b2c & c; 17 | 18 | endmodule 19 | -------------------------------------------------------------------------------- /Modules with Simulations/Sequence Detector D-Flip Flops/seq_det_101_TB.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module seq_det_101_TB; 4 | reg clock; 5 | reg reset; 6 | reg data; 7 | wire detected_101; 8 | integer i; 9 | 10 | seq_det_101 DUT(.clock(clock), .reset(reset), 11 | .data(data), .detected_101(detected_101)); 12 | 13 | reg [15:0] data_reg = 16'b1010_0110_1011_0101; 14 | 15 | always #2 clock = ~clock; 16 | 17 | initial begin 18 | clock = 0; 19 | reset = 0; 20 | data = 0; 21 | i = 0; 22 | #5 reset = 1; 23 | 24 | for(i = 0; i < 16; i = i + 1) begin 25 | data = data_reg[i]; 26 | #4; 27 | end 28 | 29 | #4 $finish; 30 | end 31 | 32 | endmodule 33 | -------------------------------------------------------------------------------- /Modules with Simulations/Sequence Detector Shift Register/seq_det_101.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module seq_det_101( 4 | input clk, 5 | input reset, 6 | input serial_in, 7 | output detected_101 8 | ); 9 | 10 | reg [2:0] seq_reg; 11 | 12 | always @(posedge clk or posedge reset) begin 13 | if(reset) 14 | seq_reg <= 0; 15 | else 16 | seq_reg <= {seq_reg[1:0], serial_in}; 17 | end 18 | 19 | assign detected_101 = (seq_reg == 3'b101) ? 1 : 0; 20 | 21 | endmodule 22 | -------------------------------------------------------------------------------- /Modules with Simulations/Sequence Detector Shift Register/seq_det_101_TB.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | module seq_det_101_TB; 3 | reg clk; 4 | reg reset; 5 | reg serial_in; 6 | wire detected_101; 7 | integer i; 8 | 9 | reg [15:0] data = 16'b0101_0010_1001_1101; 10 | 11 | seq_det_101 sd(.clk(clk), .reset(reset), .serial_in(serial_in), .detected_101(detected_101)); 12 | 13 | always #2 clk = ~clk; 14 | 15 | initial begin 16 | clk = 0; 17 | reset = 1; 18 | serial_in = 0; 19 | i = 0; 20 | #9 reset = 0; 21 | for(i = 0; i < 16; i = i + 1) begin 22 | serial_in = data[i]; 23 | #4; 24 | end 25 | 26 | #4 $finish; 27 | end 28 | endmodule 29 | -------------------------------------------------------------------------------- /Modules with Simulations/Sequence Detector State Machine/seq_det_101_fsm.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module seq_det_101_fsm( 4 | input clock, 5 | input reset, 6 | input data, 7 | output detected_101 8 | ); 9 | 10 | parameter ZERO = 2'b00; 11 | parameter DET_1 = 2'b01; 12 | parameter DET_10 = 2'b10; 13 | parameter DET_101 = 2'b11; 14 | 15 | reg [1:0] state = ZERO; 16 | 17 | always @(posedge clock or negedge reset) begin 18 | if(~reset) 19 | state <= ZERO; 20 | else 21 | case(state) 22 | ZERO : if(data == 1) state <= DET_1; 23 | DET_1 : if(data == 0) state <= DET_10; 24 | DET_10 : if(data == 1) state <= DET_101; 25 | else state <= ZERO; 26 | DET_101 : if(data == 0) state <= DET_10; 27 | else state <= DET_1; 28 | endcase 29 | end 30 | 31 | assign detected_101 = (state == DET_101) ? 1 : 0; 32 | 33 | endmodule 34 | -------------------------------------------------------------------------------- /Modules with Simulations/Sequence Detector State Machine/seq_det_101_fsm_TB.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module seq_det_101_fsm_TB; 4 | reg clock; 5 | reg reset; 6 | reg data; 7 | wire detected_101; 8 | integer i; 9 | 10 | seq_det_101_fsm DUT(.clock(clock), .reset(reset), .data(data), .detected_101(detected_101)); 11 | 12 | reg [15:0] data_reg = 16'b0110_1001_0101_1010; 13 | 14 | always #2 clock = ~clock; 15 | 16 | initial begin 17 | clock = 0; 18 | reset = 0; 19 | data = 0; 20 | i = 0; 21 | #5 reset = 1; 22 | 23 | for(i = 0; i < 16; i = i + 1) begin 24 | data = data_reg[i]; 25 | #4; 26 | end 27 | 28 | $finish; 29 | end 30 | 31 | endmodule 32 | -------------------------------------------------------------------------------- /Modules with Simulations/Simple ALU/alu.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Authored by David J. Marion aka FPGA Dude 4 | // Created on 4/13/2022 5 | // 6 | // Description: simple alu 7 | ////////////////////////////////////////////////////////////////////////////////// 8 | module alu #(parameter W = 32)( 9 | input [1:0] opcode, 10 | input [W-1:0] operand_A, 11 | input [W-1:0] operand_B, 12 | output reg [W-1:0] alu_result, 13 | output [2:0] flags 14 | ); 15 | 16 | wire N, Z, C; 17 | wire [W:0] carry_check; 18 | 19 | always @* begin 20 | case(opcode) 21 | 2'b00 : alu_result = operand_A + operand_B; // add 22 | 2'b01 : alu_result = operand_A - operand_B; // sub 23 | 2'b10 : alu_result = operand_A & operand_B; // AND 24 | 2'b11 : alu_result = operand_A | operand_B; // OR 25 | endcase 26 | end 27 | 28 | assign carry_check = operand_A + operand_B; 29 | assign N = alu_result[W-1]; 30 | assign Z = ~|alu_result; 31 | assign C = carry_check[W]; 32 | assign flags = {N, Z, C}; 33 | 34 | endmodule 35 | -------------------------------------------------------------------------------- /Modules with Simulations/Verilog Switch Level Modeling/cmos_gates.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | // instantiate PMOS: pmos instance_name(out, data, control) 3 | // instantiate NMOS: nmos instance_name(out, data, control) 4 | // instantiate CMOS: cmos instance_name(out, data, ncontrol, pcontrol) 5 | // Since pmos, nmos, and cmos are Verilog primitives an instance name is optional 6 | 7 | module cmos_gates( 8 | input a, b, c, d, e, 9 | output x, y, z 10 | ); 11 | 12 | wire w1, w2; 13 | 14 | supply1 pwr; // Needed for switch level circuits 15 | supply0 gnd; 16 | 17 | // NAND gate, assign x = ~(a & b); or nand (x, a, b); 18 | pmos (x, pwr, a); 19 | pmos (x, pwr, b); 20 | nmos (x, w1, a); 21 | nmos (w1, gnd, b); 22 | 23 | // NOR gate, assign y = ~(c + d); or nor (y, c, d); 24 | pmos (w2, pwr, c); 25 | pmos (y, w2, d); 26 | nmos (y, gnd, c); 27 | nmos (y, gnd, d); 28 | 29 | // NOT gate, assign z = ~e; or not (z, e); 30 | pmos (z, pwr, e); 31 | nmos (z, gnd, e); 32 | 33 | endmodule 34 | -------------------------------------------------------------------------------- /Modules with Simulations/Verilog Switch Level Modeling/sim_cmos.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | // Test Bench for cmos_gates.v 4 | 5 | module sim_cmos; 6 | 7 | reg a, b, c, d, e; 8 | wire x, y, z; 9 | 10 | cmos_gates DUT(.a(a), .b(b), .c(c), .d(d), .e(e), .x(x), .y(y), .z(z)); 11 | 12 | initial begin 13 | a = 0; 14 | b = 0; 15 | c = 0; 16 | d = 0; 17 | e = 0; 18 | #1 19 | a = 0; 20 | b = 1; 21 | c = 0; 22 | d = 1; 23 | #1 24 | a = 1; 25 | b = 0; 26 | c = 1; 27 | d = 0; 28 | e = 1; 29 | #1 30 | a = 1; 31 | b = 1; 32 | c = 1; 33 | d = 1; 34 | #1 35 | 36 | $finish; 37 | end 38 | 39 | endmodule 40 | -------------------------------------------------------------------------------- /Other Projects/Star Trek Clock/0001.mp3: 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https://raw.githubusercontent.com/FPGADude/Digital-Design/4cb93eeaba434eb02c2e200060921fe0e5aebf03/Other Projects/Star Trek Clock/star_trek_clock_top.FCStd -------------------------------------------------------------------------------- /Other Projects/basic_binary_clock/basic_arduino_binary_clock.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/FPGADude/Digital-Design/4cb93eeaba434eb02c2e200060921fe0e5aebf03/Other Projects/basic_binary_clock/basic_arduino_binary_clock.png -------------------------------------------------------------------------------- /University Senior Class Design Project/clock_source.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | // LiDAR data receiver clock source 4 | // LiDAR data transmits @ 230,400 baud 5 | // Clock source -> 230,400 x 25 = 5.76 MHz 6 | // Authored by David J Marion 7 | 8 | module clock_source( 9 | input clk_in, 10 | output clk_out 11 | ); 12 | 13 | // Instaniate clocking wizard clock 5.76 MHz 14 | clk_wiz_0 instance_name( 15 | .clk_100MHz(clk_in), // Input clock of 100 MHz 16 | .clk_25x(clk_out) // Output clock of 5.76 MHz 17 | ); 18 | 19 | endmodule 20 | -------------------------------------------------------------------------------- /University Senior Class Design Project/counter32.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | // LiDAR data receiver counter32 4 | // Produces enabling signals for oversampler and shift reg 5 | // Authored by David J Marion 6 | 7 | module counter32( 8 | input sig_in, // Synchronous clock input 9 | input reset, // Asynchronous system reset 10 | output reg tick12, // Enable oversampler data capture 11 | output reg tick24 // Enable data shift from oversampler to shift_reg376 12 | ); 13 | 14 | reg [4:0] counter; // 5-bit register 15 | 16 | always @(posedge sig_in or posedge reset) begin 17 | if(reset) 18 | counter <= 5'b0_0000; 19 | else if(counter == 5'b1_1000) //24 20 | counter <= 5'b0_0000; 21 | else 22 | counter <= counter + 1; 23 | end 24 | 25 | always @(posedge sig_in) begin 26 | if(counter == 5'b0_1100) //12 27 | tick12 <= 1'b1; 28 | else 29 | tick12 <= 1'b0; 30 | end 31 | 32 | always @(posedge sig_in) begin 33 | if(counter == 5'b1_1000) //24 34 | tick24 <= 1'b1; 35 | else 36 | tick24 <= 1'b0; 37 | end 38 | 39 | endmodule 40 | -------------------------------------------------------------------------------- /University Senior Class Design Project/oversampler_DFF.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | // LiDAR data receiver oversampler D-type flip flop 4 | // Authored by David J Marion 5 | 6 | module oversampler_DFF( 7 | input data_in, // Data bit coming in from LD06 LiDAR sensor 8 | input latch, // Enable data bit capture, tick12 signal from counter32 9 | input reset, // Asynchronous system reset signal 10 | output reg data_out // Data bit to be sent to shift_reg376 11 | ); 12 | 13 | always @(posedge latch or posedge reset) begin 14 | if(reset) 15 | data_out <= 1'b0; 16 | else 17 | data_out <= data_in; 18 | end 19 | 20 | endmodule 21 | -------------------------------------------------------------------------------- /University Senior Class Design Project/pwm_generator.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | // LiDAR data receiver PWM LiDAR motor control signal generator 4 | // Authored by David J Marion 5 | 6 | module pwm_generator( 7 | input clk_in, // Clocked input signal from tick24 8 | input reset, // Asynchronous system reset 9 | output pwm_out // PWM generated output signal to LiDAR 10 | ); 11 | 12 | reg [6:0] counter; // 7-bit register 13 | 14 | always @(posedge clk_in or posedge reset) begin 15 | if(reset) 16 | counter <= 0; 17 | else 18 | if(counter < 100) 19 | counter <= counter + 1; 20 | else 21 | counter <= 0; 22 | end 23 | 24 | assign pwm_out = (counter < 30) ? 1 : 0; // 30% duty cycle 25 | 26 | endmodule 27 | -------------------------------------------------------------------------------- /University Senior Class Design Project/shift_reg184.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | // LiDAR data receiver output shift register 4 | // Parallel-In to Serial-Out 5 | // Authored by David J Marion 6 | 7 | module shift_reg184( 8 | input [183:0] data_in, // 184-bit parallel in from shift_reg376 9 | input reset, // Asynchronous system reset 10 | input load, // Set 184-bit data received 11 | input clk, // Synchronous shifting signal 12 | output data_out // Serial data out 13 | ); 14 | 15 | reg [183:0] data_packet; // 184-bit internal register 16 | 17 | always @(posedge clk or posedge reset or posedge load) begin 18 | if(reset) 19 | data_packet <= 184'd0; 20 | else 21 | if(load) 22 | data_packet <= data_in; 23 | else 24 | data_packet <= {data_packet[182:0], 1'b0}; 25 | end 26 | 27 | assign data_out = data_packet[183]; 28 | 29 | endmodule 30 | -------------------------------------------------------------------------------- /Verilog Introductory Tutorial Book/AND_gate.v: -------------------------------------------------------------------------------- 1 | 2 | 3 | /******************************************************************** 4 | Title : AND_gate.v 5 | Design : A simple AND logic gate 6 | Author : David J. Marion 7 | Func. Check : Complete 8 | Information : This module contains a 2-input AND gate 9 | *********************************************************************/ 10 | 11 | //5. Tell Verilog how to determine the output O 12 | 13 | //Begin a module description 14 | module AND_gate(input A, input B, output O); 15 | 16 | wire A; //Declare a wire that is input A 17 | wire B; //Declare a wire that is input B 18 | 19 | wire O; //Declare a wire that is output O 20 | 21 | assign O = A & B; //Tell Verilog what the value of O should be 22 | 23 | endmodule //End of module description -------------------------------------------------------------------------------- /Verilog Introductory Tutorial Book/D_ff.v: -------------------------------------------------------------------------------- 1 | 2 | 3 | /******************************************************************** 4 | Title : D_ff.v 5 | Design : A D-Type Flip-Flop 6 | Author : David J. Marion 7 | Incl. Mods : NAND_gate.v 8 | Func. Check : Good 9 | Information : This module contains a D Type Flip Flop 10 | *********************************************************************/ 11 | 12 | module D_ff( 13 | input CLOCK, 14 | input D, 15 | 16 | output Q, 17 | output Q_not 18 | ); 19 | 20 | wire CLOCK, D, D_not, Q, Q_not, temp1, temp2; 21 | 22 | assign D_not = !D; //This takes care of the NOT gate 23 | 24 | NAND_gate N1( 25 | .A(D), 26 | .B(CLOCK), 27 | .O(temp1) 28 | ); 29 | NAND_gate N2( 30 | .A(CLOCK), 31 | .B(D_not), 32 | .O(temp2) 33 | ); 34 | NAND_gate N3( 35 | .A(temp1), 36 | .B(Q_not), 37 | .O(Q) 38 | ); 39 | NAND_gate N4( 40 | .A(Q), 41 | .B(temp2), 42 | .O(Q_not) 43 | ); 44 | 45 | endmodule -------------------------------------------------------------------------------- /Verilog Introductory Tutorial Book/D_ff_TB.v: -------------------------------------------------------------------------------- 1 | 2 | 3 | /******************************************************************** 4 | Title : D_ff_TB.v 5 | Design : ***Stimulus*** 6 | Author : David J. Marion 7 | MUT : D_ff.v 8 | Incl. Mods. : NAND_gate.v 9 | *********************************************************************/ 10 | 11 | module D_ff_TB(); 12 | 13 | reg CLOCK, D; 14 | 15 | wire Q, Q_not; 16 | 17 | //Instantiate module under test 18 | D_ff D1( 19 | .CLOCK(CLOCK), 20 | .D(D), 21 | .Q(Q), 22 | .Q_not(Q_not) 23 | ); 24 | 25 | //Create the CLOCK 26 | always begin 27 | #10 CLOCK = !CLOCK; 28 | end 29 | 30 | //Simulation stimulation timeline 31 | initial begin 32 | CLOCK = 0; //Initialize both registers 33 | D = 0; 34 | 35 | #50 36 | D = 1; 37 | 38 | #100 39 | D = 0; 40 | 41 | #20 42 | D = 1; 43 | 44 | #40 45 | D = 0; 46 | 47 | #1000 $finish; 48 | end 49 | 50 | //Set up output files for GTKWave 51 | initial begin 52 | $dumpfile("D_ff_TB.vcd"); 53 | $dumpvars(0, D_ff_TB); 54 | end 55 | 56 | endmodule -------------------------------------------------------------------------------- /Verilog Introductory Tutorial Book/D_ff_beh.v: -------------------------------------------------------------------------------- 1 | 2 | 3 | /******************************************************************** 4 | Title : D_ff_beh.v 5 | Design : A D-Type Flip-Flop 6 | Author : David J. Marion 7 | Func. Check : None 8 | Information : This module contains a D Type Flip Flop 9 | *********************************************************************/ 10 | 11 | module D_ff_beh( 12 | input CLOCK, 13 | input D, 14 | 15 | output Q, 16 | output Q_not 17 | 18 | ); 19 | 20 | wire CLOCK, D, Q_not; 21 | reg Q; 22 | 23 | assign Q_not = !Q; 24 | 25 | always@ (posedge CLOCK) begin 26 | Q <= D; 27 | end 28 | 29 | endmodule -------------------------------------------------------------------------------- /Verilog Introductory Tutorial Book/D_ff_beh_TB.v: -------------------------------------------------------------------------------- 1 | 2 | /******************************************************************** 3 | Title : D_ff_beh_TB.v 4 | Design : ***Stimulus*** 5 | Author : David J. Marion 6 | MUT : D_ff_beh.v 7 | Incl. Mods. : None 8 | *********************************************************************/ 9 | 10 | module D_ff_beh_TB(); 11 | 12 | reg CLOCK, D; 13 | 14 | wire Q, Q_not; 15 | 16 | //Instantiate module under test 17 | D_ff_beh D1( 18 | .CLOCK(CLOCK), 19 | .D(D), 20 | .Q(Q), 21 | .Q_not(Q_not) 22 | ); 23 | 24 | //Create the CLOCK 25 | always begin 26 | #10 CLOCK = !CLOCK; 27 | end 28 | 29 | //Simulation stimulation timeline 30 | initial begin 31 | CLOCK = 0; //Initialize both registers 32 | D = 0; 33 | 34 | #50 35 | D = 1; 36 | 37 | #100 38 | D = 0; 39 | 40 | #20 41 | D = 1; 42 | 43 | #40 44 | D = 0; 45 | 46 | #1000 $finish; 47 | end 48 | 49 | //Set up output files for GTKWave 50 | initial begin 51 | $dumpfile("D_ff_beh_TB.vcd"); 52 | $dumpvars(0, D_ff_beh_TB); 53 | end 54 | 55 | endmodule -------------------------------------------------------------------------------- /Verilog Introductory Tutorial Book/NAND_gate.v: -------------------------------------------------------------------------------- 1 | 2 | 3 | /******************************************************************** 4 | Title : NAND_gate.v 5 | Design : A simple NAND logic gate 6 | Author : David J. Marion 7 | Func. Check : Complete 8 | Information : This module contains a 2-input NAND gate 9 | *********************************************************************/ 10 | 11 | module NAND_gate(input A, input B, output O); 12 | 13 | wire A; 14 | wire B; 15 | 16 | wire O; 17 | 18 | assign O = !(A & B); 19 | 20 | endmodule -------------------------------------------------------------------------------- /Verilog Introductory Tutorial Book/NAND_gate2.v: -------------------------------------------------------------------------------- 1 | 2 | 3 | /******************************************************************** 4 | Title : NAND_gate2.v 5 | Design : A simple NAND logic gate 6 | Author : David J. Marion 7 | Func. Check : Complete 8 | Information : This module contains a 2-input NAND gate. The function 9 | is obtained by using DeMorgan's Law 10 | !(A & B) == !A | !B 11 | *********************************************************************/ 12 | 13 | module NAND_gate2(input A, input B, output O); 14 | 15 | wire A; 16 | wire B; 17 | 18 | wire O; 19 | 20 | assign O = !A | !B; 21 | 22 | endmodule -------------------------------------------------------------------------------- /Verilog Introductory Tutorial Book/NAND_gate2_TB.v: -------------------------------------------------------------------------------- 1 | 2 | /******************************************************************** 3 | Title : NAND_gate2_TB.v 4 | Design : ***Stimulus*** 5 | Author : David J. Marion 6 | MUT : NAND_gate2.v 7 | *********************************************************************/ 8 | 9 | module NAND_gate2_TB(); 10 | 11 | reg A; 12 | reg B; 13 | 14 | wire O; 15 | 16 | //Instantiate module under test: 17 | NAND_gate2 N1( 18 | .A(A), 19 | .B(B), 20 | .O(O) 21 | ); 22 | 23 | //Simulation stimulation timeline 24 | initial begin 25 | 26 | //Row1 of truth table 27 | A = 0; 28 | B = 0; 29 | #50 30 | 31 | //Row2 of truth table 32 | A = 0; 33 | B = 1; 34 | #50 35 | 36 | //Row3 of truth table 37 | A= 1; 38 | B = 0; 39 | #50 40 | 41 | //Row4 of truth table 42 | A = 1; 43 | B = 1; 44 | #50 45 | 46 | //Set time out for simulation 47 | #500 $finish; 48 | 49 | end 50 | 51 | //Set up output files for GTKWave 52 | initial begin 53 | $dumpfile("NAND_gate2_TB.vcd"); 54 | $dumpvars(0, NAND_gate2_TB); 55 | end 56 | 57 | endmodule -------------------------------------------------------------------------------- /Verilog Introductory Tutorial Book/NAND_gate_TB.v: -------------------------------------------------------------------------------- 1 | 2 | 3 | /******************************************************************** 4 | Title : NAND_gate_TB.v 5 | Design : ***Stimulus*** 6 | Author : David J. Marion 7 | MUT : NAND_gate.v 8 | *********************************************************************/ 9 | 10 | module NAND_gate_TB(); 11 | 12 | reg A; 13 | reg B; 14 | 15 | wire O; 16 | 17 | //Instantiate module under test: 18 | NAND_gate N1( 19 | .A(A), 20 | .B(B), 21 | .O(O) 22 | ); 23 | 24 | //Simulation stimulation timeline 25 | initial begin 26 | 27 | //Row1 of truth table 28 | A = 0; 29 | B = 0; 30 | #50 31 | 32 | //Row2 of truth table 33 | A = 0; 34 | B = 1; 35 | #50 36 | 37 | //Row3 of truth table 38 | A= 1; 39 | B = 0; 40 | #50 41 | 42 | //Row4 of truth table 43 | A = 1; 44 | B = 1; 45 | #50 46 | 47 | //Set time out for simulation 48 | #500 $finish; 49 | 50 | end 51 | 52 | //Set up output files for GTKWave 53 | initial begin 54 | $dumpfile("NAND_gate_TB.vcd"); 55 | $dumpvars(0, NAND_gate_TB); 56 | end 57 | 58 | endmodule -------------------------------------------------------------------------------- /Verilog Introductory Tutorial Book/OR_gate.v: -------------------------------------------------------------------------------- 1 | 2 | 3 | /******************************************************************** 4 | Title : OR_gate.v 5 | Design : A simple OR logic gate 6 | Author : David J. Marion 7 | Func. Check : None 8 | Information : This module contains a 2-input OR gate 9 | *********************************************************************/ 10 | 11 | //Begin a module description 12 | module OR_gate(input A, input B, output O); 13 | 14 | wire A; //Declare a wire that is input A 15 | wire B; //Declare a wire that is input B 16 | 17 | wire O; //Declare a wire that is output O 18 | 19 | assign O = A | B; //Tell Verilog what the value of O should be 20 | 21 | endmodule //End of module description -------------------------------------------------------------------------------- /Verilog Introductory Tutorial Book/binary_counter3.v: -------------------------------------------------------------------------------- 1 | /******************************************************************** 2 | Title : binary_counter3.v 3 | Design : 3-bit Binary Counter 4 | Author : David J. Marion 5 | Func. Check : None 6 | Information : This module contains a 3-bit binary counter 7 | *********************************************************************/ 8 | 9 | module binary_counter3( 10 | //Inputs 11 | input CLOCK, 12 | input ENABLE, 13 | //Outputs 14 | output reg [2:0] ctr3 = 3'b000 15 | ); 16 | 17 | always @ (posedge CLOCK) begin 18 | if (!ENABLE) begin 19 | ctr3 <= ctr3; 20 | end 21 | else begin 22 | ctr3 <= ctr3 + 1; 23 | end 24 | end 25 | 26 | endmodule -------------------------------------------------------------------------------- /Verilog Introductory Tutorial Book/binary_counter3_TB.v: -------------------------------------------------------------------------------- 1 | /******************************************************************** 2 | Title : binary_counter3_TB.v 3 | Design : ***Stimulus*** 4 | Author : David J. Marion 5 | MUT : binary_counter3.v 6 | Incl. Mods. : None 7 | *********************************************************************/ 8 | module binary_counter3_TB; 9 | reg CLOCK, ENABLE; 10 | wire [2:0] OUT; 11 | 12 | //Instantiate module under test 13 | binary_counter3 BC3(.CLOCK(CLOCK), .ENABLE(ENABLE), .ctr3(OUT)); 14 | 15 | //Create the clock 16 | always #10 CLOCK = !CLOCK; 17 | 18 | //Simulation stimulation timeline 19 | initial begin 20 | CLOCK = 0; 21 | ENABLE = 0; 22 | #50 ENABLE = 1; 23 | #200 ENABLE = 0; 24 | #400 $finish; 25 | end 26 | 27 | //Set up output files for GTKWave 28 | initial begin 29 | $dumpfile("binary_counter3_TB.vcd"); 30 | $dumpvars(0, binary_counter3_TB); 31 | end 32 | 33 | endmodule 34 | -------------------------------------------------------------------------------- /Verilog Introductory Tutorial Book/mod100_counter.v: -------------------------------------------------------------------------------- 1 | /******************************************************************** 2 | Title : mod100_counter.v 3 | Design : 1/100th Clock Generator 4 | Author : David J. Marion 5 | Func. Check : None 6 | Include Mods: None 7 | *********************************************************************/ 8 | module mod100_counter( 9 | //Inputs 10 | input CLOCK, 11 | input RESET, 12 | //Ouputs 13 | output reg sig100 = 1'b0 // Initialize to zero 14 | ); 15 | 16 | reg [6:0] counter100 = 0; // 7 bits needed --> (2^7 = 128) & (128 > 100) 17 | 18 | // Counter control 19 | always @ (posedge CLOCK) begin 20 | if (RESET) 21 | counter100 <= 0; 22 | else 23 | if (counter100 == 99) // Counting from 0 to 99 equals 100 ticks 24 | counter100 <= 0; 25 | else 26 | counter100 <= counter100 + 1; 27 | end 28 | 29 | // Output signal control 30 | always @ (posedge CLOCK) begin 31 | if (counter100 == 98) 32 | sig100 <= 1; 33 | else 34 | sig100 <= 0; 35 | end 36 | 37 | endmodule 38 | -------------------------------------------------------------------------------- /Verilog Introductory Tutorial Book/mod100_counterEX.v: -------------------------------------------------------------------------------- 1 | 2 | /******************************************************************** 3 | Title : mod100_counter.v 4 | Design : 1/100th Clock Generator 5 | Author : David J. Marion 6 | Func. Check : None 7 | Include Mods: None 8 | *********************************************************************/ 9 | module mod100_counter( 10 | //Inputs 11 | input CLOCK, 12 | input RESET, 13 | //Ouputs 14 | output reg sig100 = 1'b0 // Initialize to zero 15 | ); 16 | 17 | reg [6:0] counter100 = 0; // 7 bits needed --> (2^7 = 128) & (128 > 100) 18 | 19 | // Counter control 20 | always @ (posedge CLOCK) begin 21 | if (RESET) 22 | counter100 <= 0; 23 | else 24 | if (counter100 == 99) // Counting from 0 to 99 equals 100 ticks 25 | counter100 <= 0; 26 | else 27 | counter100 <= counter100 + 1; 28 | end 29 | 30 | // Output signal control 31 | always @ (posedge CLOCK) begin 32 | if (counter100 == 98) 33 | sig100 <= 1; 34 | else 35 | sig100 <= 0; 36 | end 37 | 38 | endmodule -------------------------------------------------------------------------------- /Verilog Introductory Tutorial Book/mod100_counter_TB.v: -------------------------------------------------------------------------------- 1 | /******************************************************************** 2 | Title : mod100_counter_TB.v 3 | Design : ***Stimulus*** 4 | Author : David J. Marion 5 | MUT : mod100_counter.v 6 | Incl. Mods. : None 7 | *********************************************************************/ 8 | module mod100_counter_TB; 9 | 10 | reg CLOCK, RESET; 11 | wire sig100; 12 | 13 | //Instantiate the Module Under Test(MUT) 14 | mod100_counter ctr100(.CLOCK(CLOCK), .RESET(RESET), .sig100(sig100)); 15 | 16 | always #5 CLOCK = ~CLOCK; //Create the clock 17 | 18 | //Test sequence 19 | initial begin 20 | CLOCK = 0; 21 | RESET = 0; 22 | 23 | #100 RESET = 1; 24 | #50 RESET = 0; 25 | 26 | #5000 $finish; 27 | end 28 | 29 | //Set up file for GTKWave 30 | initial begin 31 | $dumpfile("mod100_counter_TB.vcd"); 32 | $dumpvars(0, mod100_counter_TB); 33 | end 34 | 35 | endmodule -------------------------------------------------------------------------------- /Verilog Introductory Tutorial Book/modular_verilog.v: -------------------------------------------------------------------------------- 1 | /******************************************************************** 2 | Title : modular_verilog.v 3 | Design : Modular Verilog Design 4 | Author : David J. Marion 5 | Func. Check : None 6 | Include Mods: binary_counter3.v, decoder_3x8.v 7 | *********************************************************************/ 8 | module modular_verilog( 9 | //Inputs 10 | input CLOCK, 11 | input ENABLE, 12 | //Outputs 13 | output [7:0] OUT // 8-bit output from decoder 14 | ); 15 | 16 | wire [2:0] connection; // 3-bit wire connecting counter to decoder 17 | 18 | //Instantiate including modules 19 | binary_counter3 BC3( 20 | .CLOCK(CLOCK), 21 | .ENABLE(ENABLE), 22 | .ctr3(connection) 23 | ); 24 | 25 | decoder_3x8 DEC( 26 | .x(connection[2]), 27 | .y(connection[1]), 28 | .z(connection[0]), 29 | .F0(OUT[0]), 30 | .F1(OUT[1]), 31 | .F2(OUT[2]), 32 | .F3(OUT[3]), 33 | .F4(OUT[4]), 34 | .F5(OUT[5]), 35 | .F6(OUT[6]), 36 | .F7(OUT[7]) 37 | ); 38 | 39 | endmodule 40 | 41 | -------------------------------------------------------------------------------- /Verilog Introductory Tutorial Book/modular_verilog_TB.v: -------------------------------------------------------------------------------- 1 | /******************************************************************** 2 | Title : modular_verilog_TB.v 3 | Design : ***Stimulus*** 4 | Author : David J. Marion 5 | MUT : modular_verilog.v 6 | Include Mods: binary_counter3.v, decoder_3x8.v 7 | *********************************************************************/ 8 | module modular_verilog_TB; 9 | 10 | reg CLOCK, ENABLE; 11 | wire [7:0] OUT; 12 | 13 | //Instantiate module under test 14 | modular_verilog MV1(.CLOCK(CLOCK), .ENABLE(ENABLE), .OUT(OUT)); 15 | 16 | //Create the clock 17 | always #10 CLOCK = !CLOCK; 18 | 19 | //Simulation stimulation timeline 20 | initial begin 21 | CLOCK = 0; 22 | ENABLE = 0; 23 | #50 ENABLE = 1; 24 | 25 | #500 $finish; 26 | end 27 | 28 | //Set up output files for GTKWave 29 | initial begin 30 | $dumpfile("modular_verilog_TB.vcd"); 31 | $dumpvars(0, modular_verilog_TB); 32 | end 33 | 34 | endmodule 35 | 36 | -------------------------------------------------------------------------------- /Verilog Introductory Tutorial Book/mux_4x1.v: -------------------------------------------------------------------------------- 1 | /******************************************************************** 2 | Title : mux_4x1.v 3 | Design : 4-to-1 Multiplexer 4 | Author : David J. Marion 5 | Func. Check : None 6 | Include Mods: None 7 | *********************************************************************/ 8 | module mux_4x1( 9 | //Inputs 10 | input [3:0] D, // 4-bit data input 11 | input [1:0] AB, // 2-bit selector input 12 | //Ouputs 13 | output reg Y // Data output 14 | ); 15 | 16 | always @ (*) begin 17 | case (AB) 18 | 2'b00 : Y = D[0]; 19 | 2'b01 : Y = D[1]; 20 | 2'b10 : Y = D[2]; 21 | 2'b11 : Y = D[3]; 22 | default : Y = D[0]; 23 | endcase 24 | end 25 | 26 | endmodule 27 | 28 | --------------------------------------------------------------------------------