├── .gitignore ├── Collection └── riscv.svg ├── Demo ├── Images │ ├── 01-linux.png │ ├── 02-linux.png │ ├── 03-linux.png │ ├── 04-linux.png │ ├── 05-linux.png │ ├── 06-linux.png │ ├── 07-linux.png │ ├── 08-linux.png │ ├── Radiona-ULX3S-12F-2.jpg │ └── Radiona-ULX3S-12F.jpg ├── Linux │ ├── boot.bin │ ├── kernel.bin │ └── kianv32mb.dtb ├── README.md └── Soc-Kianv-ULX3S-12F.bit ├── Firmware └── 01-rars-asm │ ├── 01-leds-on.s │ ├── build.sh │ └── flash.sh ├── Hardware ├── KianV-Apio │ ├── Images │ │ ├── 01-apio.png │ │ ├── 02-apio.png │ │ ├── 03-apio.png │ │ └── 04-apio.png │ ├── README.md │ ├── alu.v │ ├── alu_decoder.v │ ├── apio.ini │ ├── bram.v │ ├── clint.v │ ├── control_unit.v │ ├── csr_decoder.v │ ├── csr_exception_handler.v │ ├── csr_utilities.vh │ ├── datapath_unit.v │ ├── defines_soc.vh │ ├── design_elements.v │ ├── divider.v │ ├── divider_decoder.v │ ├── extend.v │ ├── fifo.v │ ├── kianv_harris_mc_edition.v │ ├── load_alignment.v │ ├── load_decoder.v │ ├── main_fsm.v │ ├── mcause.vh │ ├── misa.vh │ ├── mt48lc16m16a2_ctrl.v │ ├── multiplier.v │ ├── multiplier_decoder.v │ ├── multiplier_extension_decoder.v │ ├── pll.v │ ├── qqspi.v │ ├── register_file.v │ ├── riscv_defines.vh │ ├── riscv_priv_csr_status.vh │ ├── rv32_amo_opcodes.vh │ ├── rx_uart.v │ ├── soc-top.v │ ├── store_alignment.v │ ├── store_decoder.v │ ├── tx_uart.v │ └── ulx3s_v20.lpf └── KianV-Icestudio │ ├── Blinky.ice │ ├── Level-00 │ ├── Linux-soc-KianV-00.ice │ ├── alu.v │ ├── alu_decoder.v │ ├── bram.v │ ├── clint.v │ ├── control_unit.v │ ├── csr_decoder.v │ ├── csr_exception_handler.v │ ├── csr_utilities.vh │ ├── datapath_unit.v │ ├── defines_soc.vh │ ├── design_elements.v │ ├── divider.v │ ├── divider_decoder.v │ ├── extend.v │ ├── fifo.v │ ├── flash.sh │ ├── kianv_harris_mc_edition.v │ ├── load_alignment.v │ ├── load_decoder.v │ ├── main_fsm.v │ ├── mcause.vh │ ├── misa.vh │ ├── mt48lc16m16a2_ctrl.v │ ├── multiplier.v │ ├── multiplier_decoder.v │ ├── multiplier_extension_decoder.v │ ├── pll.v │ ├── qqspi.v │ ├── register_file.v │ ├── riscv_defines.vh │ ├── riscv_priv_csr_status.vh │ ├── rv32_amo_opcodes.vh │ ├── rx_uart.v │ ├── soc-top.v │ ├── store_alignment.v │ ├── store_decoder.v │ └── tx_uart.v │ ├── Level-01 │ ├── Linux-soc-KianV-01.ice │ ├── alu.v │ ├── alu_decoder.v │ ├── bram.v │ ├── clint.v │ ├── control_unit.v │ ├── csr_decoder.v │ ├── csr_exception_handler.v │ ├── csr_utilities.vh │ ├── datapath_unit.v │ ├── design_elements.v │ ├── divider.v │ ├── divider_decoder.v │ ├── extend.v │ ├── fifo.v │ ├── flash.sh │ ├── kianv_harris_mc_edition.v │ ├── load_alignment.v │ ├── load_decoder.v │ ├── main_fsm.v │ ├── mcause.vh │ ├── misa.vh │ ├── mt48lc16m16a2_ctrl.v │ ├── multiplier.v │ ├── multiplier_decoder.v │ ├── multiplier_extension_decoder.v │ ├── pll.v │ ├── qqspi.v │ ├── register_file.v │ ├── riscv_defines.vh │ ├── riscv_priv_csr_status.vh │ ├── rv32_amo_opcodes.vh │ ├── rx_uart.v │ ├── store_alignment.v │ ├── store_decoder.v │ └── tx_uart.v │ ├── Level-02 │ ├── Linux-soc-KianV-02.ice │ ├── alu.v │ ├── alu_decoder.v │ ├── bram.v │ ├── clint.v │ ├── control_unit.v │ ├── csr_decoder.v │ ├── csr_exception_handler.v │ ├── csr_utilities.vh │ ├── datapath_unit.v │ ├── design_elements.v │ ├── divider.v │ ├── divider_decoder.v │ ├── extend.v │ ├── fifo.v │ ├── flash.sh │ ├── kianv_harris_mc_edition.v │ ├── load_alignment.v │ ├── load_decoder.v │ ├── main_fsm.v │ ├── mcause.vh │ ├── misa.vh │ ├── mt48lc16m16a2_ctrl.v │ ├── multiplier.v │ ├── multiplier_decoder.v │ ├── multiplier_extension_decoder.v │ ├── pll.v │ ├── qqspi.v │ ├── register_file.v │ ├── riscv_defines.vh │ ├── riscv_priv_csr_status.vh │ ├── rv32_amo_opcodes.vh │ ├── rx_uart.v │ ├── store_alignment.v │ ├── store_decoder.v │ └── tx_uart.v │ └── flash.sh ├── Images └── Linux-anim-1.gif ├── LICENSE └── README.md /.gitignore: -------------------------------------------------------------------------------- 1 | .sconsign.dblite 2 | hardware.bit 3 | hardware.json 4 | hardware.config 5 | ice-build 6 | rars1_5.jar 7 | firmware.bin 8 | -------------------------------------------------------------------------------- /Collection/riscv.svg: -------------------------------------------------------------------------------- 1 | Fritzing breadboard generated by brd2svg -------------------------------------------------------------------------------- /Demo/Images/01-linux.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/FPGAwars/FLIX-V/d8c229dc90be4a3b2e37252a53767d06c394f755/Demo/Images/01-linux.png -------------------------------------------------------------------------------- /Demo/Images/02-linux.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/FPGAwars/FLIX-V/d8c229dc90be4a3b2e37252a53767d06c394f755/Demo/Images/02-linux.png -------------------------------------------------------------------------------- /Demo/Images/03-linux.png: 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that are written into the flash memory at different addresses 16 | 17 | * **0x100000** (1024\*1024, 1MB). **Boot**. File: `boot.bin` 18 | * **0x200000** (1024\*1024\*2, 2MB), **Kernel**. File: `kernel.bin` 19 | * **0x700000** (1024\*1024\*7), 7MB), **DTB**. File: `kianv32mb.dtb` 20 | 21 | ## Step 1.1: Flash the Bootloader 22 | 23 | This program is in charge of preparing and initilizing the system for running the linux kernel 24 | 25 | * Command: 26 | 27 | ``` 28 | apio raw "fujprog -l 4 -j FLASH -f $((1024*1024*1)) Linux/boot.bin" 29 | ``` 30 | ![Screenshot](Images/01-linux.png) 31 | 32 | ## Step 1.2: Flash the Kernel 33 | 34 | * Command: 35 | 36 | ``` 37 | apio raw "fujprog -l 10 -j FLASH -f $((1024*1024*2)) kernel.bin" 38 | ``` 39 | 40 | ![Screenshot](Images/02-linux.png) 41 | 42 | ![Screenshot](Images/03-linux.png) 43 | 44 | This process takes around 4 minutes 45 | 46 | ## Step 1.3: Flash the DTB Image 47 | 48 | The DTB (Device Tree Blob) is a binary that contains information about the hardware configuration: devices, system resources, peripherals.... 49 | 50 | ``` 51 | apio raw "fujprog -l 4 -j FLASH -f $((1024*1024*7)) kianv32mb.dtb" 52 | ``` 53 | 54 | ![Screenshot](Images/04-linux.png) 55 | 56 | 57 | # Step 2: Flashing the KianV bitstream 58 | 59 | Finally, let's add the KianV Risc-v soc 60 | 61 | * Command: 62 | 63 | ``` 64 | apio raw "fujprog -l 4 -j FLASH Soc-Kianv-ULX3S-12F.bit" 65 | ``` 66 | 67 | ![Screenshot](Images/05-linux.png) 68 | 69 | # Step 3: Running Linux! 70 | 71 | After flashing the Kianv soc, Linux will boot. 72 | 73 | ![Screenshot](Images/Radiona-ULX3S-12F-2.jpg) 74 | 75 | Open a serial terminal configured for the custom speed of **3000000 bauds** 76 | 77 | A very simple and useful terminal for linux is [tio](https://github.com/tio/tio) 78 | 79 | * Command: 80 | 81 | ``` 82 | tio -m INLCRNL /dev/ttyUSB0 -b 3000000 83 | ``` 84 | 85 | ![Screenshot](Images/06-linux.png) 86 | 87 | 88 | ![Screenshot](Images/07-linux.png) 89 | 90 | Now log in as root: 91 | 92 | ![Alt text](Images/08-linux.png) 93 | 94 | ... and you are now ready to feel the power of Linux running on the FPGA... 95 | 96 | * Youtube videos: 97 | 98 | [![Click to see the youtube video](http://img.youtube.com/vi/X3PfOpjIHhs/0.jpg)](https://www.youtube.com/watch?v=X3PfOpjIHhs) 99 | 100 | [![Click to see the youtube video](http://img.youtube.com/vi/F4EDP8qkS5s/0.jpg)](https://www.youtube.com/watch?v=X3PfOpjIHhs) 101 | 102 | -------------------------------------------------------------------------------- /Demo/Soc-Kianv-ULX3S-12F.bit: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/FPGAwars/FLIX-V/d8c229dc90be4a3b2e37252a53767d06c394f755/Demo/Soc-Kianv-ULX3S-12F.bit -------------------------------------------------------------------------------- /Firmware/01-rars-asm/01-leds-on.s: -------------------------------------------------------------------------------- 1 | #-- Write a value to the LEDs 2 | 3 | #-- Addres were LEDs are mapped 4 | .eqv LEDS 0x12000000 5 | 6 | #-- Value to write to the LEDs 7 | .eqv VALUE 0x03 8 | 9 | .text 10 | 11 | #-- Pointer for accessing leds 12 | li t0, LEDS 13 | 14 | #-- Send VALUE to LEDs 15 | li t1, VALUE 16 | sw t1, 0(t0) 17 | 18 | #-- Stop! 19 | inf: b inf 20 | 21 | 22 | -------------------------------------------------------------------------------- /Firmware/01-rars-asm/build.sh: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | 3 | FILE=01-leds-on.s 4 | 5 | rm -f firmware.bin 6 | java -jar rars1_5.jar a mc CompactTextAtZero dump .text Binary firmware.bin dump .data Binary data.bin $FILE 7 | cat data.bin >> firmware.bin -------------------------------------------------------------------------------- /Firmware/01-rars-asm/flash.sh: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | 3 | # source /home/obijuan/Bin/oss-cad-suite/environment 4 | 5 | apio raw "fujprog -j FLASH -f $((1024*1024*1)) firmware.bin" 6 | #apio raw "openFPGALoader -f -o $((1024*1024*1)) --board=ulx3s firmware.bin" 7 | #openFPGALoader -f -o $((1024*1024*1)) --board=ulx3s firmware.bin 8 | -------------------------------------------------------------------------------- /Hardware/KianV-Apio/Images/01-apio.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/FPGAwars/FLIX-V/d8c229dc90be4a3b2e37252a53767d06c394f755/Hardware/KianV-Apio/Images/01-apio.png -------------------------------------------------------------------------------- /Hardware/KianV-Apio/Images/02-apio.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/FPGAwars/FLIX-V/d8c229dc90be4a3b2e37252a53767d06c394f755/Hardware/KianV-Apio/Images/02-apio.png -------------------------------------------------------------------------------- /Hardware/KianV-Apio/Images/03-apio.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/FPGAwars/FLIX-V/d8c229dc90be4a3b2e37252a53767d06c394f755/Hardware/KianV-Apio/Images/03-apio.png -------------------------------------------------------------------------------- /Hardware/KianV-Apio/Images/04-apio.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/FPGAwars/FLIX-V/d8c229dc90be4a3b2e37252a53767d06c394f755/Hardware/KianV-Apio/Images/04-apio.png -------------------------------------------------------------------------------- /Hardware/KianV-Apio/README.md: -------------------------------------------------------------------------------- 1 | # Synthesizing KianV with apio 2 | 3 | * Default board: Radiona ULX3S-12F board 4 | 5 | 1. **Install** [Apio](https://github.com/FPGAwars/apio/wiki) 6 | 2. It has been tested with Apio 0.8.1: 7 | 8 | * Command: 9 | 10 | ``` 11 | apio --version 12 | ``` 13 | 14 | ![Screenshot](Images/01-apio.png) 15 | 16 | 3. **Synthesize the KianV processor** 17 | 18 | * Command: 19 | 20 | ``` 21 | apio build 22 | ``` 23 | 24 | ![Screenshot](Images/02-apio.png) 25 | 26 | It takes around 50 seconds (on my machine). When it is done, the bitstream is generated in the file `hardware.bit` 27 | 28 | 4. **Upload the bitstream to the FPGA** 29 | 30 | * Command: 31 | 32 | ``` 33 | apio upload 34 | ``` 35 | 36 | ![Screenshot](Images/03-apio.png) 37 | 38 | It uploads the bitstream and configures the FPGA. This configuration is temporal (if the board is power off the configuration is lost) 39 | 40 | 5. **Upload the bitstream to the Flash** (optional) 41 | 42 | If you want to make it persistent, execute the following command: 43 | 44 | ``` 45 | apio raw "fujprog -l 4 -j FLASH hardware.bit" 46 | ``` 47 | 48 | ![Screenshot](Images/04-apio.png) 49 | -------------------------------------------------------------------------------- /Hardware/KianV-Apio/alu.v: -------------------------------------------------------------------------------- 1 | /* 2 | * kianv harris multicycle RISC-V rv32im 3 | * 4 | * copyright (c) 2022 hirosh dabui 5 | * 6 | * permission to use, copy, modify, and/or distribute this software for any 7 | * purpose with or without fee is hereby granted, provided that the above 8 | * copyright notice and this permission notice appear in all copies. 9 | * 10 | * the software is provided "as is" and the author disclaims all warranties 11 | * with regard to this software including all implied warranties of 12 | * merchantability and fitness. in no event shall the author be liable for 13 | * any special, direct, indirect, or consequential damages or any damages 14 | * whatsoever resulting from loss of use, data or profits, whether in an 15 | * action of contract, negligence or other tortious action, arising out of 16 | * or in connection with the use or performance of this software. 17 | * 18 | */ 19 | `default_nettype none `timescale 1 ns / 100 ps 20 | `include "riscv_defines.vh" 21 | 22 | module alu ( 23 | input wire [ 31:0] a, 24 | input wire [ 31:0] b, 25 | input wire [`ALU_CTRL_WIDTH -1:0] alucontrol, 26 | output reg [ 31:0] result, 27 | output wire zero 28 | ); 29 | 30 | 31 | wire is_beq = alucontrol == `ALU_CTRL_BEQ; 32 | wire is_bne = alucontrol == `ALU_CTRL_BNE; 33 | wire is_blt = alucontrol == `ALU_CTRL_BLT; 34 | wire is_bge = alucontrol == `ALU_CTRL_BGE; 35 | wire is_bltu = alucontrol == `ALU_CTRL_BLTU; 36 | wire is_bgeu = alucontrol == `ALU_CTRL_BGEU; 37 | wire is_slt_slti = alucontrol == `ALU_CTRL_SLT_SLTI; 38 | wire is_sltu_sltiu = alucontrol == `ALU_CTRL_SLTU_SLTIU; 39 | wire is_sub_ctrl = alucontrol == `ALU_CTRL_SUB; 40 | wire is_amo_min_max = alucontrol == `ALU_CTRL_MIN || alucontrol == `ALU_CTRL_MAX || 41 | alucontrol == `ALU_CTRL_MINU || alucontrol == `ALU_CTRL_MAXU; 42 | 43 | wire is_sub = is_sub_ctrl || is_beq || is_bne || is_blt || is_bge || 44 | is_bltu || is_bgeu || is_slt_slti || is_amo_min_max || is_sltu_sltiu; 45 | 46 | 47 | wire [31:0] condinv = is_sub ? ~b : b; 48 | 49 | // seen 33 Bit sum from Bruno's Levy 50 | // with that approach I could map all branch to LT, LTU 51 | wire [32:0] sum = {1'b1, condinv} + {1'b0, a} + {32'b0, is_sub}; 52 | wire LT = (a[31] ^ b[31]) ? a[31] : sum[32]; 53 | wire LTU = sum[32]; 54 | 55 | wire [31:0] sltx_sltux_rslt = {31'b0, is_slt_slti ? LT : LTU}; 56 | wire [63:0] sext_rs1 = {{32{a[31]}}, a}; 57 | wire [63:0] sra_srai_rslt = sext_rs1 >> b[4:0]; 58 | 59 | wire is_sum_zero = sum[31:0] == 32'b0; 60 | 61 | always @* begin 62 | case (alucontrol) 63 | `ALU_CTRL_ADD_ADDI: result = sum[31:0]; 64 | `ALU_CTRL_SUB: result = sum[31:0]; 65 | `ALU_CTRL_XOR_XORI: result = a ^ b; 66 | `ALU_CTRL_OR_ORI: result = a | b; 67 | `ALU_CTRL_AND_ANDI: result = a & b; 68 | `ALU_CTRL_SLL_SLLI: result = a << b[4:0]; 69 | `ALU_CTRL_SRL_SRLI: result = a >> b[4:0]; 70 | `ALU_CTRL_SRA_SRAI: result = sra_srai_rslt[31:0]; 71 | `ALU_CTRL_SLT_SLTI: result = (a[31] == b[31]) ? sltx_sltux_rslt : {31'b0, a[31]}; 72 | `ALU_CTRL_SLTU_SLTIU: result = sltx_sltux_rslt; 73 | `ALU_CTRL_MIN: result = LT ? a : b; 74 | `ALU_CTRL_MAX: result = !LT ? a : b; 75 | `ALU_CTRL_MINU: result = LTU ? a : b; 76 | `ALU_CTRL_MAXU: result = !LTU ? a : b; 77 | `ALU_CTRL_LUI: result = b; 78 | `ALU_CTRL_AUIPC: result = sum[31:0]; 79 | default: begin 80 | case (1'b1) 81 | is_beq: result = {31'b0, is_sum_zero}; 82 | is_bne: result = {31'b0, !is_sum_zero}; 83 | is_blt: result = {31'b0, LT}; 84 | is_bge: result = {31'b0, !LT}; 85 | is_bltu: result = {31'b0, LTU}; 86 | is_bgeu: result = {31'b0, !LTU}; 87 | default: result = 32'b0; 88 | endcase 89 | end 90 | endcase 91 | end 92 | 93 | assign zero = result == 32'b0; 94 | endmodule 95 | -------------------------------------------------------------------------------- /Hardware/KianV-Apio/apio.ini: -------------------------------------------------------------------------------- 1 | [env] 2 | board = ulx3s-12f 3 | 4 | -------------------------------------------------------------------------------- /Hardware/KianV-Apio/bram.v: -------------------------------------------------------------------------------- 1 | /* 2 | * kianv.v - a simple RISC-V rv32i 3 | * 4 | * copyright (c) 2022 hirosh dabui 5 | * 6 | * permission to use, copy, modify, and/or distribute this software for any 7 | * purpose with or without fee is hereby granted, provided that the above 8 | * copyright notice and this permission notice appear in all copies. 9 | * 10 | * the software is provided "as is" and the author disclaims all warranties 11 | * with regard to this software including all implied warranties of 12 | * merchantability and fitness. in no event shall the author be liable for 13 | * any special, direct, indirect, or consequential damages or any damages 14 | * whatsoever resulting from loss of use, data or profits, whether in an 15 | * action of contract, negligence or other tortious action, arising out of 16 | * or in connection with the use or performance of this software. 17 | * 18 | */ 19 | `default_nettype none `timescale 1 ns / 100 ps 20 | module bram #( 21 | parameter integer WIDTH = 8, 22 | parameter INIT_FILE = "", 23 | parameter SHOW_FIRMWARE = 0 24 | ) ( 25 | input wire clk, 26 | input wire [WIDTH -1:0] addr, 27 | input wire [31:0] wdata, 28 | output reg [31:0] rdata, 29 | input wire [3:0] wmask 30 | ); 31 | reg [31:0] mem[0:(1< 5 | * 6 | * permission to use, copy, modify, and/or distribute this software for any 7 | * purpose with or without fee is hereby granted, provided that the above 8 | * copyright notice and this permission notice appear in all copies. 9 | * 10 | * the software is provided "as is" and the author disclaims all warranties 11 | * with regard to this software including all implied warranties of 12 | * merchantability and fitness. in no event shall the author be liable for 13 | * any special, direct, indirect, or consequential damages or any damages 14 | * whatsoever resulting from loss of use, data or profits, whether in an 15 | * action of contract, negligence or other tortious action, arising out of 16 | * or in connection with the use or performance of this software. 17 | * 18 | */ 19 | `default_nettype none `timescale 1 ns / 100 ps 20 | module clint #( 21 | parameter SYSTEM_CLK = 25_000_000, 22 | parameter CLOCK_TICK = 1000 23 | ) ( 24 | input wire clk, 25 | input wire resetn, 26 | input wire valid, 27 | input wire [31:0] addr, 28 | input wire [3:0] wmask, 29 | input wire [31:0] wdata, 30 | output reg [31:0] rdata, 31 | output wire is_valid, 32 | output reg ready, 33 | output wire IRQ3, 34 | output wire IRQ7 35 | ); 36 | 37 | /* verilator lint_off WIDTHTRUNC */ 38 | localparam CLOCK_TICK_BIT_WIDTH = $clog2(CLOCK_TICK); 39 | localparam [CLOCK_TICK_BIT_WIDTH -1:0] CYCLES_TO_TICK = ($rtoi(SYSTEM_CLK / CLOCK_TICK)); 40 | /* verilator lint_on WIDTHTRUNC */ 41 | wire is_msip = (addr == 32'h1100_0000); 42 | wire is_mtimecmpl = (addr == 32'h1100_4000); 43 | wire is_mtimecmph = (addr == 32'h1100_4004); 44 | wire is_mtimeh = (addr == 32'h1100_bffc); 45 | wire is_mtimel = (addr == 32'h1100_bff8); 46 | 47 | assign is_valid = valid && (is_msip || is_mtimecmpl || is_mtimecmph || is_mtimel || is_mtimeh); 48 | always @(posedge clk) ready <= !resetn ? 1'b0 : is_valid; 49 | 50 | reg [63:0] mtime; 51 | always @(posedge clk) mtime <= !resetn ? 0 : (tick) ? mtime + 1 : mtime; 52 | 53 | wire is_we = |wmask; 54 | 55 | reg [63:0] mtimecmp; 56 | reg msip; 57 | 58 | always @(posedge clk) 59 | if (!resetn) begin 60 | mtimecmp <= 0; 61 | msip <= 0; 62 | end else if (is_mtimecmpl && is_valid) begin 63 | if (wmask[0]) mtimecmp[7:0] <= wdata[7:0]; 64 | if (wmask[1]) mtimecmp[15:8] <= wdata[15:8]; 65 | if (wmask[2]) mtimecmp[23:16] <= wdata[23:16]; 66 | if (wmask[3]) mtimecmp[31:24] <= wdata[31:24]; 67 | end else if (is_mtimecmph && is_valid) begin 68 | if (wmask[0]) mtimecmp[39:32] <= wdata[7:0]; 69 | if (wmask[1]) mtimecmp[47:40] <= wdata[15:8]; 70 | if (wmask[2]) mtimecmp[55:48] <= wdata[23:16]; 71 | if (wmask[3]) mtimecmp[63:56] <= wdata[31:24]; 72 | end else if (is_msip && is_valid) begin 73 | if (wmask[0]) msip <= wdata[0]; 74 | end 75 | 76 | always @(*) begin 77 | case (1'b1) 78 | is_mtimecmpl: rdata = mtimecmp[31:0]; 79 | is_mtimecmph: rdata = mtimecmp[63:32]; 80 | is_mtimel: rdata = mtime[31:0]; 81 | is_mtimeh: rdata = mtime[63:32]; 82 | is_msip: rdata = {31'b0, msip}; 83 | default: rdata = 0; 84 | endcase 85 | end 86 | 87 | 88 | reg [CLOCK_TICK_BIT_WIDTH -1:0] tick_cnt; 89 | wire tick = tick_cnt == (CYCLES_TO_TICK - 1); 90 | always @(posedge clk) begin 91 | if (!resetn) begin 92 | tick_cnt <= 0; 93 | end else begin 94 | if (tick) begin 95 | tick_cnt <= 0; 96 | end else begin 97 | tick_cnt <= tick_cnt + 1; 98 | end 99 | end 100 | end 101 | 102 | assign IRQ3 = msip; 103 | assign IRQ7 = (mtime >= mtimecmp); 104 | 105 | endmodule 106 | 107 | -------------------------------------------------------------------------------- /Hardware/KianV-Apio/csr_utilities.vh: -------------------------------------------------------------------------------- 1 | /* 2 | * kianv.v - RISC-V rv32ima 3 | * 4 | * copyright (c) 2023 hirosh dabui 5 | * 6 | * permission to use, copy, modify, and/or distribute this software for any 7 | * purpose with or without fee is hereby granted, provided that the above 8 | * copyright notice and this permission notice appear in all copies. 9 | * 10 | * the software is provided "as is" and the author disclaims all warranties 11 | * with regard to this software including all implied warranties of 12 | * merchantability and fitness. in no event shall the author be liable for 13 | * any special, direct, indirect, or consequential damages or any damages 14 | * whatsoever resulting from loss of use, data or profits, whether in an 15 | * action of contract, negligence or other tortious action, arising out of 16 | * or in connection with the use or performance of this software. 17 | * 18 | */ 19 | `ifndef CSR_UTILITIES_VH 20 | `define CSR_UTILITIES_VH 21 | 22 | // Unprivileged Counter/Timers 23 | `define CSR_REG_CYCLE 12'h C00 24 | `define CSR_REG_CYCLEH 12'h C80 25 | `define CSR_REG_INSTRET 12'h C02 26 | `define CSR_REG_INSTRETH 12'h C82 27 | `define CSR_REG_TIME 12'h C01 28 | `define CSR_REG_TIMEH 12'h C81 29 | 30 | // Machine Trap Setup 31 | `define CSR_REG_MSTATUS 12'h 300 32 | `define CSR_REG_MISA 12'h 301 33 | `define CSR_REG_MIE 12'h 304 34 | `define CSR_REG_MTVEC 12'h 305 35 | 36 | // Machine Trap Handling 37 | `define CSR_REG_MSCRATCH 12'h 340 38 | `define CSR_REG_MEPC 12'h 341 39 | `define CSR_REG_MCAUSE 12'h 342 40 | `define CSR_REG_MTVAL 12'h 343 41 | `define CSR_REG_MIP 12'h 344 42 | 43 | `define CSR_REG_MCOUNTEREN 12'h 306 44 | 45 | `define CSR_REG_MHARTID 12'h f14 46 | `define CSR_REG_MVENDORID 12'h f11 47 | 48 | // Machine-Level CSRs 49 | // custrom read-only 50 | `define CSR_PRIVILEGE_MODE 12'h fc0 // machine privilege mode 51 | 52 | 53 | // RISC-V CSR instruction opcodes (7-bit) and funct3 (3-bit) 54 | `define CSR_OPCODE `SYSTEM_OPCODE 55 | `define CSR_FUNCT3_RW 3'b001 56 | `define CSR_FUNCT3_RS 3'b010 57 | `define CSR_FUNCT3_RC 3'b011 58 | `define CSR_FUNCT3_RWI 3'b101 59 | `define CSR_FUNCT3_RSI 3'b110 60 | `define CSR_FUNCT3_RCI 3'b111 61 | 62 | `include "riscv_priv_csr_status.vh" 63 | `include "misa.vh" 64 | `endif 65 | -------------------------------------------------------------------------------- /Hardware/KianV-Apio/defines_soc.vh: -------------------------------------------------------------------------------- 1 | /* 2 | * kianv harris multicycle RISC-V rv32im 3 | * 4 | * copyright (c) 2023 hirosh dabui 5 | * 6 | * permission to use, copy, modify, and/or distribute this software for any 7 | * purpose with or without fee is hereby granted, provided that the above 8 | * copyright notice and this permission notice appear in all copies. 9 | * 10 | * the software is provided "as is" and the author disclaims all warranties 11 | * with regard to this software including all implied warranties of 12 | * merchantability and fitness. in no event shall the author be liable for 13 | * any special, direct, indirect, or consequential damages or any damages 14 | * whatsoever resulting from loss of use, data or profits, whether in an 15 | * action of contract, negligence or other tortious action, arising out of 16 | * or in connection with the use or performance of this software. 17 | * 18 | */ 19 | `ifndef KIANV_SOC 20 | `define KIANV_SOC 21 | 22 | `define CPU_FREQ_REG_ADDR 32'h 30_000_010 23 | `define BAUDRATE 3_000_000 24 | 25 | `define UART_TX_ADDR 32'h 10_000_000 26 | `define UART_RX_ADDR 32'h 10_000_000 27 | `define UART_LSR_ADDR 32'h 10_000_005 28 | 29 | 30 | `define RV32M 31 | `define FAKE_MULTIPLIER 32 | `define LED_ULX3S 33 | 34 | `define QUAD_SPI_FLASH_MODE 1'b1 35 | 36 | `define UART_TX 37 | `define UART_RX 38 | 39 | `define SDRAM_MEM_ADDR_START 32'h 80_000_000 40 | `define SDRAM_SIZE (1024*1024*32) 41 | `define SDRAM_MEM_ADDR_END ((`SDRAM_MEM_ADDR_START) + (`SDRAM_SIZE)) 42 | 43 | `define SYSTEM_CLK 70_000_000 44 | `define SYSTEM_CLK_MHZ (`SYSTEM_CLK / 1_000_000) 45 | 46 | `define SPI_NOR_MEM_ADDR_START 32'h 20_000_000 47 | 48 | `define SPI_MEMORY_OFFSET (1024*1024) 49 | `define SPI_NOR_MEM_ADDR_END ((`SPI_NOR_MEM_ADDR_START) + (16*1024*1024)) 50 | 51 | `define RESET_ADDR (`SPI_NOR_MEM_ADDR_START + `SPI_MEMORY_OFFSET) 52 | `define FIRMWARE_BRAM "" 53 | `define BRAM_WORDS (1024*16) 54 | 55 | `endif 56 | -------------------------------------------------------------------------------- /Hardware/KianV-Apio/design_elements.v: -------------------------------------------------------------------------------- 1 | /* 2 | * kianv harris multicycle RISC-V rv32im 3 | * 4 | * copyright (c) 2022/23 hirosh dabui 5 | * 6 | * permission to use, copy, modify, and/or distribute this software for any 7 | * purpose with or without fee is hereby granted, provided that the above 8 | * copyright notice and this permission notice appear in all copies. 9 | * 10 | * the software is provided "as is" and the author disclaims all warranties 11 | * with regard to this software including all implied warranties of 12 | * merchantability and fitness. in no event shall the author be liable for 13 | * any special, direct, indirect, or consequential damages or any damages 14 | * whatsoever resulting from loss of use, data or profits, whether in an 15 | * action of contract, negligence or other tortious action, arising out of 16 | * or in connection with the use or performance of this software. 17 | * 18 | */ 19 | `default_nettype none `timescale 1 ns / 100 ps 20 | /* verilator lint_off MULTITOP */ 21 | 22 | module mux2 #( 23 | parameter WIDTH = 32 24 | ) ( 25 | input wire [WIDTH -1:0] d0, 26 | d1, 27 | input wire s, 28 | output wire [WIDTH -1:0] y 29 | ); 30 | 31 | assign y = s ? d1 : d0; 32 | endmodule 33 | 34 | module mux3 #( 35 | parameter WIDTH = 32 36 | ) ( 37 | input wire [WIDTH -1:0] d0, 38 | d1, 39 | d2, 40 | input wire [ 1:0] s, 41 | output wire [WIDTH -1:0] y 42 | ); 43 | 44 | assign y = s[1] ? d2 : (s[0] ? d1 : d0); 45 | endmodule 46 | 47 | module mux4 #( 48 | parameter WIDTH = 32 49 | ) ( 50 | input wire [WIDTH -1:0] d0, 51 | d1, 52 | d2, 53 | d3, 54 | input wire [ 1:0] s, 55 | output wire [WIDTH -1:0] y 56 | ); 57 | 58 | wire [WIDTH -1:0] low, high; 59 | 60 | mux2 lowmux ( 61 | d0, 62 | d1, 63 | s[0], 64 | low 65 | ); 66 | mux2 highmux ( 67 | d2, 68 | d3, 69 | s[0], 70 | high 71 | ); 72 | mux2 finalmux ( 73 | low, 74 | high, 75 | s[1], 76 | y 77 | ); 78 | endmodule 79 | 80 | module mux5 #( 81 | parameter WIDTH = 32 82 | ) ( 83 | input wire [WIDTH -1:0] d0, 84 | d1, 85 | d2, 86 | d3, 87 | d4, 88 | input wire [ 2:0] s, 89 | output wire [WIDTH -1:0] y 90 | 91 | ); 92 | 93 | assign y = (s == 0) ? d0 : (s == 1) ? d1 : (s == 2) ? d2 : (s == 3) ? d3 : d4; 94 | 95 | endmodule 96 | 97 | module mux6 #( 98 | parameter WIDTH = 32 99 | ) ( 100 | input wire [WIDTH -1:0] d0, 101 | d1, 102 | d2, 103 | d3, 104 | d4, 105 | d5, 106 | input wire [ 2:0] s, 107 | output wire [WIDTH -1:0] y 108 | 109 | ); 110 | 111 | assign y = (s == 0) ? d0 : (s == 1) ? d1 : (s == 2) ? d2 : (s == 3) ? d3 : (s == 4) ? d4 : d5; 112 | 113 | endmodule 114 | 115 | module dlatch #( 116 | parameter WIDTH = 32 117 | ) ( 118 | input wire clk, 119 | input wire [WIDTH -1:0] d, 120 | output reg [WIDTH -1:0] q 121 | ); 122 | always @(posedge clk) q <= d; 123 | endmodule 124 | 125 | module dff #( 126 | parameter WIDTH = 32, 127 | parameter PRESET = 0 128 | ) ( 129 | input wire resetn, 130 | input wire clk, 131 | input wire en, 132 | input wire [WIDTH -1:0] d, 133 | output reg [WIDTH -1:0] q 134 | ); 135 | always @(posedge clk) 136 | if (!resetn) q <= PRESET; 137 | else if (en) q <= d; 138 | 139 | endmodule 140 | module counter #( 141 | parameter WIDTH = 32 142 | ) ( 143 | input wire resetn, 144 | input wire clk, 145 | input wire inc, 146 | output reg [WIDTH -1:0] q 147 | ); 148 | always @(posedge clk) 149 | if (!resetn) q <= 0; 150 | else if (inc) q <= q + 1; 151 | 152 | endmodule 153 | /* verilator lint_on MULTITOP */ 154 | -------------------------------------------------------------------------------- /Hardware/KianV-Apio/divider_decoder.v: -------------------------------------------------------------------------------- 1 | /* 2 | * kianv harris multicycle RISC-V rv32im 3 | * 4 | * copyright (c) 2022 hirosh dabui 5 | * 6 | * permission to use, copy, modify, and/or distribute this software for any 7 | * purpose with or without fee is hereby granted, provided that the above 8 | * copyright notice and this permission notice appear in all copies. 9 | * 10 | * the software is provided "as is" and the author disclaims all warranties 11 | * with regard to this software including all implied warranties of 12 | * merchantability and fitness. in no event shall the author be liable for 13 | * any special, direct, indirect, or consequential damages or any damages 14 | * whatsoever resulting from loss of use, data or profits, whether in an 15 | * action of contract, negligence or other tortious action, arising out of 16 | * or in connection with the use or performance of this software. 17 | * 18 | */ 19 | `default_nettype none `timescale 1 ns / 100 ps 20 | `include "riscv_defines.vh" 21 | module divider_decoder ( 22 | input wire [ 2:0] funct3, 23 | output reg [`DIV_OP_WIDTH -1:0] DIVop, 24 | input wire mul_ext_valid, 25 | output wire div_valid 26 | ); 27 | 28 | wire is_div = funct3 == 3'b100; 29 | wire is_divu = funct3 == 3'b101; 30 | wire is_rem = funct3 == 3'b110; 31 | wire is_remu = funct3 == 3'b111; 32 | reg valid; 33 | 34 | assign div_valid = valid & mul_ext_valid; 35 | 36 | always @(*) begin 37 | valid = 1'b1; 38 | case (1'b1) 39 | is_div: DIVop = `DIV_OP_DIV; 40 | is_divu: DIVop = `DIV_OP_DIVU; 41 | is_rem: DIVop = `DIV_OP_REM; 42 | is_remu: DIVop = `DIV_OP_REMU; 43 | default: begin 44 | /* verilator lint_off WIDTH */ 45 | DIVop = 'hxx; 46 | /* verilator lint_on WIDTH */ 47 | valid = 1'b0; 48 | end 49 | endcase 50 | end 51 | 52 | endmodule 53 | -------------------------------------------------------------------------------- /Hardware/KianV-Apio/extend.v: -------------------------------------------------------------------------------- 1 | /* 2 | * kianv harris multicycle RISC-V rv32im 3 | * 4 | * copyright (c) 2022 hirosh dabui 5 | * 6 | * permission to use, copy, modify, and/or distribute this software for any 7 | * purpose with or without fee is hereby granted, provided that the above 8 | * copyright notice and this permission notice appear in all copies. 9 | * 10 | * the software is provided "as is" and the author disclaims all warranties 11 | * with regard to this software including all implied warranties of 12 | * merchantability and fitness. in no event shall the author be liable for 13 | * any special, direct, indirect, or consequential damages or any damages 14 | * whatsoever resulting from loss of use, data or profits, whether in an 15 | * action of contract, negligence or other tortious action, arising out of 16 | * or in connection with the use or performance of this software. 17 | * 18 | */ 19 | `default_nettype none `timescale 1 ns / 100 ps 20 | `include "riscv_defines.vh" 21 | module extend ( 22 | input wire [31:7] instr, 23 | input wire [ 2:0] immsrc, 24 | output reg [31:0] immext 25 | ); 26 | 27 | always @(*) begin 28 | case (immsrc) 29 | `IMMSRC_ITYPE: immext = {{20{instr[31]}}, instr[31:20]}; 30 | `IMMSRC_STYPE: immext = {{20{instr[31]}}, instr[31:25], instr[11:7]}; 31 | `IMMSRC_BTYPE: immext = {{20{instr[31]}}, instr[7:7], instr[30:25], instr[11:8], 1'b0}; 32 | `IMMSRC_JTYPE: immext = {{12{instr[31]}}, instr[19:12], instr[20], instr[30:21], 1'b0}; 33 | `IMMSRC_UTYPE: immext = {instr[31:12], 12'b0}; 34 | default: immext = 32'b0; 35 | endcase 36 | end 37 | endmodule 38 | -------------------------------------------------------------------------------- /Hardware/KianV-Apio/fifo.v: -------------------------------------------------------------------------------- 1 | /* 2 | * fifo.v 3 | * 4 | * copyright (c) 2021 hirosh dabui 5 | * 6 | * permission to use, copy, modify, and/or distribute this software for any 7 | * purpose with or without fee is hereby granted, provided that the above 8 | * copyright notice and this permission notice appear in all copies. 9 | * 10 | * the software is provided "as is" and the author disclaims all warranties 11 | * with regard to this software including all implied warranties of 12 | * merchantability and fitness. in no event shall the author be liable for 13 | * any special, direct, indirect, or consequential damages or any damages 14 | * whatsoever resulting from loss of use, data or profits, whether in an 15 | * action of contract, negligence or other tortious action, arising out of 16 | * or in connection with the use or performance of this software. 17 | * 18 | */ 19 | 20 | `default_nettype none `timescale 1 ns / 100 ps 21 | module fifo #( 22 | parameter DATA_WIDTH = 8, 23 | parameter DEPTH = 4 24 | ) ( 25 | input wire clk, 26 | input wire resetn, 27 | input wire [DATA_WIDTH-1:0] din, 28 | output wire [DATA_WIDTH-1:0] dout, 29 | input wire push, 30 | input wire pop, 31 | output wire full, 32 | output wire empty 33 | ); 34 | 35 | reg [DATA_WIDTH-1:0] ram[0:DEPTH-1]; 36 | 37 | reg [$clog2(DEPTH):0] cnt; 38 | reg [$clog2(DEPTH)-1:0] rd_ptr; 39 | reg [$clog2(DEPTH)-1:0] wr_ptr; 40 | 41 | reg [$clog2(DEPTH):0] cnt_next; 42 | reg [$clog2(DEPTH)-1:0] rd_ptr_next; 43 | reg [$clog2(DEPTH)-1:0] wr_ptr_next; 44 | 45 | assign empty = cnt == 0; 46 | assign full = cnt == DEPTH; 47 | 48 | always @(posedge clk) begin 49 | if (~resetn) begin 50 | rd_ptr <= 0; 51 | wr_ptr <= 0; 52 | cnt <= 0; 53 | end else begin 54 | rd_ptr <= rd_ptr_next; 55 | wr_ptr <= wr_ptr_next; 56 | cnt <= cnt_next; 57 | end 58 | end 59 | 60 | always @(*) begin 61 | rd_ptr_next = rd_ptr; 62 | wr_ptr_next = wr_ptr; 63 | cnt_next = cnt; 64 | 65 | if (push) begin 66 | wr_ptr_next = wr_ptr + 1; 67 | cnt_next = (!pop || empty) ? cnt + 1 : cnt_next; 68 | end 69 | 70 | if (pop) begin 71 | rd_ptr_next = rd_ptr + 1; 72 | cnt_next = (!push || full) ? cnt - 1 : cnt_next; 73 | end 74 | 75 | end 76 | 77 | always @(posedge clk) begin 78 | if (push) ram[wr_ptr] <= din; 79 | end 80 | 81 | assign dout = ram[rd_ptr]; 82 | 83 | endmodule 84 | -------------------------------------------------------------------------------- /Hardware/KianV-Apio/load_alignment.v: -------------------------------------------------------------------------------- 1 | /* 2 | * kianv harris multicycle RISC-V rv32ima 3 | * 4 | * copyright (c) 2023 hirosh dabui 5 | * 6 | * permission to use, copy, modify, and/or distribute this software for any 7 | * purpose with or without fee is hereby granted, provided that the above 8 | * copyright notice and this permission notice appear in all copies. 9 | * 10 | * the software is provided "as is" and the author disclaims all warranties 11 | * with regard to this software including all implied warranties of 12 | * merchantability and fitness. in no event shall the author be liable for 13 | * any special, direct, indirect, or consequential damages or any damages 14 | * whatsoever resulting from loss of use, data or profits, whether in an 15 | * action of contract, negligence or other tortious action, arising out of 16 | * or in connection with the use or performance of this software. 17 | * 18 | */ 19 | `default_nettype none `timescale 1 ns / 100 ps 20 | `include "riscv_defines.vh" 21 | module load_alignment ( 22 | input wire [ 1:0] addr, 23 | input wire [`LOAD_OP_WIDTH -1:0] LOADop, 24 | input wire [ 31:0] data, 25 | output reg [ 31:0] result, 26 | output reg unaligned_access 27 | ); 28 | 29 | wire is_lb = `LOAD_OP_LB == LOADop; 30 | wire is_lbu = `LOAD_OP_LBU == LOADop; 31 | 32 | wire is_lh = `LOAD_OP_LH == LOADop; 33 | wire is_lhu = `LOAD_OP_LHU == LOADop; 34 | 35 | wire is_lw = `LOAD_OP_LW == LOADop; 36 | 37 | always @* begin 38 | result = 'hx; 39 | unaligned_access = 1'b0; 40 | if (is_lb | is_lbu) begin 41 | result[7:0] = 42 | addr[1:0] == 2'b00 ? data[7 :0] : 43 | addr[1:0] == 2'b01 ? data[15 :8] : 44 | addr[1:0] == 2'b10 ? data[23:16] : 45 | addr[1:0] == 2'b11 ? data[31:24] : 8'hx; 46 | result = {is_lbu ? 24'b0 : {24{result[7]}}, result[7:0]}; 47 | unaligned_access = 1'b0; 48 | end 49 | 50 | if (is_lh | is_lhu) begin 51 | result[15:0] = ~addr[1] ? data[15 : 0] : addr[1] ? data[31 : 16] : 16'hx; 52 | result = {is_lhu ? 16'b0 : {16{result[15]}}, result[15:0]}; 53 | unaligned_access = addr[0]; 54 | end 55 | 56 | if (is_lw) begin 57 | result = data; 58 | unaligned_access = addr[1:0] != 2'b00; 59 | end 60 | end 61 | 62 | endmodule 63 | -------------------------------------------------------------------------------- /Hardware/KianV-Apio/load_decoder.v: -------------------------------------------------------------------------------- 1 | /* 2 | * kianv harris multicycle RISC-V rv32im 3 | * 4 | * copyright (c) 2022 hirosh dabui 5 | * 6 | * permission to use, copy, modify, and/or distribute this software for any 7 | * purpose with or without fee is hereby granted, provided that the above 8 | * copyright notice and this permission notice appear in all copies. 9 | * 10 | * the software is provided "as is" and the author disclaims all warranties 11 | * with regard to this software including all implied warranties of 12 | * merchantability and fitness. in no event shall the author be liable for 13 | * any special, direct, indirect, or consequential damages or any damages 14 | * whatsoever resulting from loss of use, data or profits, whether in an 15 | * action of contract, negligence or other tortious action, arising out of 16 | * or in connection with the use or performance of this software. 17 | * 18 | */ 19 | `default_nettype none 20 | `timescale 1 ns/100 ps 21 | `include "riscv_defines.vh" 22 | module load_decoder 23 | ( 24 | input wire [ 2: 0] funct3, 25 | input wire amo_data_load, 26 | output reg [`LOAD_OP_WIDTH -1: 0] LOADop 27 | ); 28 | wire is_lb = funct3 == 3'b 000; 29 | wire is_lh = funct3 == 3'b 001; 30 | wire is_lw = funct3 == 3'b 010; 31 | wire is_lbu = funct3 == 3'b 100; 32 | wire is_lhu = funct3 == 3'b 101; 33 | 34 | always @(*) begin 35 | if (!amo_data_load) begin 36 | case (1'b1) 37 | is_lb : LOADop = `LOAD_OP_LB; 38 | is_lh : LOADop = `LOAD_OP_LH; 39 | is_lw : LOADop = `LOAD_OP_LW; 40 | is_lbu : LOADop = `LOAD_OP_LBU; 41 | is_lhu : LOADop = `LOAD_OP_LHU; 42 | default: 43 | /* verilator lint_off WIDTH */ 44 | LOADop = 'hxx; 45 | /* verilator lint_on WIDTH */ 46 | endcase 47 | end else begin 48 | LOADop = `LOAD_OP_LW; 49 | end 50 | end 51 | 52 | endmodule 53 | -------------------------------------------------------------------------------- /Hardware/KianV-Apio/mcause.vh: -------------------------------------------------------------------------------- 1 | /* 2 | * kianv.v - RISC-V rv32ima 3 | * 4 | * copyright (c) 2023 hirosh dabui 5 | * 6 | * permission to use, copy, modify, and/or distribute this software for any 7 | * purpose with or without fee is hereby granted, provided that the above 8 | * copyright notice and this permission notice appear in all copies. 9 | * 10 | * the software is provided "as is" and the author disclaims all warranties 11 | * with regard to this software including all implied warranties of 12 | * merchantability and fitness. in no event shall the author be liable for 13 | * any special, direct, indirect, or consequential damages or any damages 14 | * whatsoever resulting from loss of use, data or profits, whether in an 15 | * action of contract, negligence or other tortious action, arising out of 16 | * or in connection with the use or performance of this software. 17 | * 18 | */ 19 | `ifndef MCAUSE_VH 20 | `define MCAUSE_VH 21 | // Exception codes 22 | `define EXC_INSTR_ADDR_MISALIGNED 32'h00000000 23 | `define EXC_INSTR_ACCESS_FAULT 32'h00000001 24 | `define EXC_ILLEGAL_INSTRUCTION 32'h00000002 25 | `define EXC_BREAKPOINT 32'h00000003 26 | `define EXC_LOAD_AMO_ADDR_MISALIGNED 32'h00000004 27 | `define EXC_LOAD_AMO_ACCESS_FAULT 32'h00000005 28 | `define EXC_STORE_AMO_ADDR_MISALIGNED 32'h00000006 29 | `define EXC_STORE_AMO_ACCESS_FAULT 32'h00000007 30 | `define EXC_ECALL_FROM_UMODE 32'h00000008 31 | `define EXC_ECALL_FROM_SMODE 32'h00000009 32 | `define EXC_ECALL_FROM_MMODE 32'h0000000B 33 | `define EXC_INSTR_PAGE_FAULT 32'h0000000C 34 | `define EXC_LOAD_PAGE_FAULT 32'h0000000D 35 | `define EXC_STORE_AMO_PAGE_FAULT 32'h0000000F 36 | 37 | // Interrupt codes 38 | `define INTERRUPT_USER_SOFTWARE 32'h80000000 39 | `define INTERRUPT_SUPERVISOR_SOFTWARE 32'h80000001 40 | `define INTERRUPT_MACHINE_SOFTWARE 32'h80000003 41 | `define INTERRUPT_USER_TIMER 32'h80000004 42 | `define INTERRUPT_SUPERVISOR_TIMER 32'h80000005 43 | `define INTERRUPT_MACHINE_TIMER 32'h80000007 44 | `define INTERRUPT_USER_EXTERNAL 32'h80000008 45 | `define INTERRUPT_SUPERVISOR_EXTERNAL 32'h80000009 46 | `define INTERRUPT_MACHINE_EXTERNAL 32'h8000000B 47 | `endif 48 | -------------------------------------------------------------------------------- /Hardware/KianV-Apio/misa.vh: -------------------------------------------------------------------------------- 1 | /* 2 | * kianv.v - RISC-V rv32ima 3 | * 4 | * copyright (c) 2023 hirosh dabui 5 | * 6 | * permission to use, copy, modify, and/or distribute this software for any 7 | * purpose with or without fee is hereby granted, provided that the above 8 | * copyright notice and this permission notice appear in all copies. 9 | * 10 | * the software is provided "as is" and the author disclaims all warranties 11 | * with regard to this software including all implied warranties of 12 | * merchantability and fitness. in no event shall the author be liable for 13 | * any special, direct, indirect, or consequential damages or any damages 14 | * whatsoever resulting from loss of use, data or profits, whether in an 15 | * action of contract, negligence or other tortious action, arising out of 16 | * or in connection with the use or performance of this software. 17 | * 18 | */ 19 | `ifndef MISA_VH 20 | `define MISA_VH 21 | 22 | `define MISA_MXL_RV32 2'b01 23 | `define MISA_EXTENSION_A 5'd0 24 | `define MISA_EXTENSION_B 5'd1 25 | `define MISA_EXTENSION_C 5'd2 26 | `define MISA_EXTENSION_D 5'd3 27 | `define MISA_EXTENSION_E 5'd4 28 | `define MISA_EXTENSION_F 5'd5 29 | `define MISA_EXTENSION_G 5'd6 30 | `define MISA_EXTENSION_H 5'd7 31 | `define MISA_EXTENSION_I 5'd8 32 | `define MISA_EXTENSION_J 5'd9 33 | `define MISA_EXTENSION_K 5'd10 34 | `define MISA_EXTENSION_L 5'd11 35 | `define MISA_EXTENSION_M 5'd12 36 | `define MISA_EXTENSION_N 5'd13 37 | `define MISA_EXTENSION_O 5'd14 38 | `define MISA_EXTENSION_P 5'd15 39 | `define MISA_EXTENSION_Q 5'd16 40 | `define MISA_EXTENSION_R 5'd17 41 | `define MISA_EXTENSION_S 5'd18 42 | `define MISA_EXTENSION_T 5'd19 43 | `define MISA_EXTENSION_U 5'd20 44 | `define MISA_EXTENSION_V 5'd21 45 | `define MISA_EXTENSION_W 5'd22 46 | `define MISA_EXTENSION_X 5'd23 47 | `define MISA_EXTENSION_Y 5'd24 48 | `define MISA_EXTENSION_Z 5'd25 49 | 50 | `define IS_EXTENSION_SUPPORTED(MXL, Extensions, Ext_To_Check) \ 51 | ((MXL) == `MISA_MXL_RV32) && (((Extensions) >> (Ext_To_Check)) & 1'b1) 52 | `define SET_MISA_VALUE(MXL) (MXL << 30) 53 | `define MISA_EXTENSION_BIT(extension) (1 << extension) 54 | 55 | `endif 56 | -------------------------------------------------------------------------------- /Hardware/KianV-Apio/multiplier.v: -------------------------------------------------------------------------------- 1 | /* 2 | * kianv harris multicycle RISC-V rv32im 3 | * 4 | * copyright (c) 2022 hirosh dabui 5 | * 6 | * permission to use, copy, modify, and/or distribute this software for any 7 | * purpose with or without fee is hereby granted, provided that the above 8 | * copyright notice and this permission notice appear in all copies. 9 | * 10 | * the software is provided "as is" and the author disclaims all warranties 11 | * with regard to this software including all implied warranties of 12 | * merchantability and fitness. in no event shall the author be liable for 13 | * any special, direct, indirect, or consequential damages or any damages 14 | * whatsoever resulting from loss of use, data or profits, whether in an 15 | * action of contract, negligence or other tortious action, arising out of 16 | * or in connection with the use or performance of this software. 17 | * 18 | */ 19 | `default_nettype none `timescale 1 ns / 100 ps 20 | 21 | `include "riscv_defines.vh" 22 | module multiplier ( 23 | input wire clk, 24 | input wire resetn, 25 | input wire [ 31 : 0] factor1, 26 | input wire [ 31 : 0] factor2, 27 | input wire [`MUL_OP_WIDTH -1 : 0] MULop, 28 | output wire [ 31 : 0] product, 29 | input wire valid, 30 | output reg ready 31 | ); 32 | 33 | wire is_mulh = MULop == `MUL_OP_MULH; 34 | wire is_mulsu = MULop == `MUL_OP_MULSU; 35 | wire is_mulu = MULop == `MUL_OP_MULU; 36 | 37 | wire factor1_is_signed = is_mulh | is_mulsu; 38 | wire factor2_is_signed = is_mulh; 39 | 40 | // multiplication 41 | reg [63:0] rslt; 42 | reg [31:0] factor1_abs; 43 | reg [31:0] factor2_abs; 44 | reg [4:0] bit_idx; 45 | 46 | localparam IDLE_BIT = 0; 47 | localparam CALC_BIT = 1; 48 | localparam READY_BIT = 2; 49 | 50 | localparam IDLE = 1 << IDLE_BIT; 51 | localparam CALC = 1 << CALC_BIT; 52 | localparam READY = 1 << READY_BIT; 53 | 54 | localparam NR_STATES = 3; 55 | 56 | (* onehot *) 57 | reg [NR_STATES-1:0] state; 58 | 59 | wire [31:0] rslt_upper_low = (is_mulh | is_mulu | is_mulsu) ? rslt[63:32] : rslt[31:0]; 60 | always @(posedge clk) begin 61 | if (!resetn) begin 62 | state <= IDLE; 63 | ready <= 1'b0; 64 | bit_idx <= 0; 65 | end else begin 66 | 67 | (* parallel_case, full_case *) 68 | case (1'b1) 69 | 70 | state[IDLE_BIT]: begin 71 | ready <= 1'b0; 72 | if (!ready && valid) begin 73 | factor1_abs <= (factor1_is_signed & factor1[31]) ? ~factor1 + 1 : factor1; 74 | factor2_abs <= (factor2_is_signed & factor2[31]) ? ~factor2 + 1 : factor2; 75 | bit_idx <= 0; 76 | rslt <= 0; 77 | state <= CALC; 78 | end 79 | end 80 | 81 | state[CALC_BIT]: begin 82 | `ifndef FAKE_MULTIPLIER 83 | /* verilator lint_off WIDTH */ 84 | rslt <= rslt + ((factor1_abs & {32{factor2_abs[bit_idx]}}) << bit_idx); 85 | /* verilator lint_on WIDTH */ 86 | bit_idx <= bit_idx + 1'b1; 87 | if (&bit_idx) begin 88 | state <= READY; 89 | end 90 | `else 91 | rslt <= factor1_abs * factor2_abs; 92 | state <= READY; 93 | `endif 94 | end 95 | 96 | state[READY_BIT]: begin 97 | /* verilator lint_off WIDTH */ 98 | rslt <= ((factor1[31] & factor1_is_signed ^ factor2[31] & factor2_is_signed)) ? ~rslt + 1 : rslt; 99 | /* verilator lint_on WIDTH */ 100 | 101 | ready <= 1'b1; 102 | state <= IDLE; 103 | end 104 | 105 | endcase 106 | 107 | end 108 | 109 | end 110 | 111 | assign product = rslt_upper_low; 112 | 113 | endmodule 114 | -------------------------------------------------------------------------------- /Hardware/KianV-Apio/multiplier_decoder.v: -------------------------------------------------------------------------------- 1 | /* 2 | * kianv harris multicycle RISC-V rv32im 3 | * 4 | * copyright (c) 2022 hirosh dabui 5 | * 6 | * permission to use, copy, modify, and/or distribute this software for any 7 | * purpose with or without fee is hereby granted, provided that the above 8 | * copyright notice and this permission notice appear in all copies. 9 | * 10 | * the software is provided "as is" and the author disclaims all warranties 11 | * with regard to this software including all implied warranties of 12 | * merchantability and fitness. in no event shall the author be liable for 13 | * any special, direct, indirect, or consequential damages or any damages 14 | * whatsoever resulting from loss of use, data or profits, whether in an 15 | * action of contract, negligence or other tortious action, arising out of 16 | * or in connection with the use or performance of this software. 17 | * 18 | */ 19 | `default_nettype none `timescale 1 ns / 100 ps 20 | `include "riscv_defines.vh" 21 | module multiplier_decoder ( 22 | input wire [ 2:0] funct3, 23 | output reg [`MUL_OP_WIDTH -1:0] MULop, 24 | input wire mul_ext_valid, 25 | output wire mul_valid 26 | ); 27 | 28 | wire is_mul = funct3 == 3'b000; 29 | wire is_mulh = funct3 == 3'b001; 30 | wire is_mulsu = funct3 == 3'b010; 31 | wire is_mulu = funct3 == 3'b011; 32 | reg valid; 33 | 34 | assign mul_valid = valid & mul_ext_valid; 35 | always @(*) begin 36 | valid = 1'b1; 37 | case (1'b1) 38 | is_mul: MULop = `MUL_OP_MUL; 39 | is_mulh: MULop = `MUL_OP_MULH; 40 | is_mulsu: MULop = `MUL_OP_MULSU; 41 | is_mulu: MULop = `MUL_OP_MULU; 42 | default: begin 43 | /* verilator lint_off WIDTH */ 44 | MULop = 'hxx; 45 | /* verilator lint_on WIDTH */ 46 | valid = 1'b0; 47 | end 48 | endcase 49 | end 50 | 51 | endmodule 52 | -------------------------------------------------------------------------------- /Hardware/KianV-Apio/multiplier_extension_decoder.v: -------------------------------------------------------------------------------- 1 | /* 2 | * kianv harris multicycle RISC-V rv32im 3 | * 4 | * copyright (c) 2022 hirosh dabui 5 | * 6 | * permission to use, copy, modify, and/or distribute this software for any 7 | * purpose with or without fee is hereby granted, provided that the above 8 | * copyright notice and this permission notice appear in all copies. 9 | * 10 | * the software is provided "as is" and the author disclaims all warranties 11 | * with regard to this software including all implied warranties of 12 | * merchantability and fitness. in no event shall the author be liable for 13 | * any special, direct, indirect, or consequential damages or any damages 14 | * whatsoever resulting from loss of use, data or profits, whether in an 15 | * action of contract, negligence or other tortious action, arising out of 16 | * or in connection with the use or performance of this software. 17 | * 18 | */ 19 | `default_nettype none `timescale 1 ns / 100 ps 20 | `include "riscv_defines.vh" 21 | module multiplier_extension_decoder ( 22 | input wire [ 2:0] funct3, 23 | output wire [`MUL_OP_WIDTH -1:0] MULop, 24 | output wire [`DIV_OP_WIDTH -1:0] DIVop, 25 | input wire mul_ext_valid, 26 | output wire mul_valid, 27 | output wire div_valid 28 | ); 29 | 30 | multiplier_decoder multiplier_I ( 31 | funct3, 32 | MULop, 33 | mul_ext_valid, 34 | mul_valid 35 | ); 36 | divider_decoder divider_decoder_I ( 37 | funct3, 38 | DIVop, 39 | mul_ext_valid, 40 | div_valid 41 | ); 42 | 43 | endmodule 44 | -------------------------------------------------------------------------------- /Hardware/KianV-Apio/register_file.v: -------------------------------------------------------------------------------- 1 | /* 2 | * kianv harris multicycle RISC-V rv32ima 3 | * 4 | * copyright (c) 2023 hirosh dabui 5 | * 6 | * permission to use, copy, modify, and/or distribute this software for any 7 | * purpose with or without fee is hereby granted, provided that the above 8 | * copyright notice and this permission notice appear in all copies. 9 | * 10 | * the software is provided "as is" and the author disclaims all warranties 11 | * with regard to this software including all implied warranties of 12 | * merchantability and fitness. in no event shall the author be liable for 13 | * any special, direct, indirect, or consequential damages or any damages 14 | * whatsoever resulting from loss of use, data or profits, whether in an 15 | * action of contract, negligence or other tortious action, arising out of 16 | * or in connection with the use or performance of this software. 17 | * 18 | */ 19 | `default_nettype none `timescale 1 ns / 100 ps 20 | 21 | module register_file #( 22 | parameter REGISTER_DEPTH = 32, // rv32e = 16; rv32i = 32 23 | parameter STACKADDR = 32'hffff_ffff 24 | ) ( 25 | input wire clk, 26 | input wire we, 27 | input wire [ 4:0] A1, 28 | input wire [ 4:0] A2, 29 | input wire [ 4:0] A3, 30 | input wire [31:0] wd, 31 | output wire [31:0] rd1, 32 | output wire [31:0] rd2 33 | ); 34 | reg [31:0] bank0[0:REGISTER_DEPTH -1]; 35 | integer i; 36 | 37 | localparam X2 = 2; 38 | initial begin 39 | bank0[10] = 'h00; // hartid 40 | bank0[11] = 32'h80_000_000 + ((1024 * 1024 * 32) - 2048); // 32'h81fffa00; // dtb 41 | end 42 | 43 | 44 | always @(posedge clk) begin 45 | 46 | if (we && A3 != 0) begin 47 | bank0[A3] <= wd; 48 | end 49 | end 50 | 51 | assign rd1 = A1 != 0 ? bank0[A1] : 32'b0; 52 | assign rd2 = A2 != 0 ? bank0[A2] : 32'b0; 53 | 54 | endmodule 55 | -------------------------------------------------------------------------------- /Hardware/KianV-Apio/riscv_priv_csr_status.vh: -------------------------------------------------------------------------------- 1 | /* 2 | * kianv harris multicycle RISC-V rv32im 3 | * 4 | * copyright (c) 2023 hirosh dabui 5 | * 6 | * permission to use, copy, modify, and/or distribute this software for any 7 | * purpose with or without fee is hereby granted, provided that the above 8 | * copyright notice and this permission notice appear in all copies. 9 | * 10 | * the software is provided "as is" and the author disclaims all warranties 11 | * with regard to this software including all implied warranties of 12 | * merchantability and fitness. in no event shall the author be liable for 13 | * any special, direct, indirect, or consequential damages or any damages 14 | * whatsoever resulting from loss of use, data or profits, whether in an 15 | * action of contract, negligence or other tortious action, arising out of 16 | * or in connection with the use or performance of this software. 17 | */ 18 | /* verilog_format: off */ 19 | `ifndef RISCV_PRIV_CSR_STATUS_VH 20 | `define RISCV_PRIV_CSR_STATUS_VH 21 | // RISC-V privilege levels 22 | // M -> Simple embedded systems 23 | // M, U -> Secure embedded systems 24 | // M, S, U -> System running Unix-like operating systems 25 | // RISC-V privilege levels 26 | `define PRIVILEGE_MODE_USER 0 27 | `define PRIVILEGE_MODE_SUPERVISOR 1 28 | `define PRIVILEGE_MODE_RESERVED 2 29 | `define PRIVILEGE_MODE_MACHINE 3 30 | `define IS_USER(privilege) (privilege == `PRIVILEGE_MODE_USER) 31 | `define IS_SUPERVISOR(privilege) (privilege == `PRIVILEGE_MODE_SUPERVISOR) 32 | `define IS_MACHINE(privilege) (privilege == `PRIVILEGE_MODE_MACHINE) 33 | 34 | `define MIP_MTIP_BIT 7 35 | `define MIE_MTIP_BIT 7 36 | 37 | `define MIP_MTIP_MASK (1<< `MIP_MTIP_BIT) 38 | `define MIE_MTIP_MASK (1<< `MIE_MTIP_BIT) 39 | 40 | `define MIP_MSIP_BIT 3 41 | `define MIE_MSIP_BIT 3 42 | 43 | `define MIP_MSIP_MASK (1<< `MIP_MSIP_BIT) 44 | `define MIE_MSIP_MASK (1<< `MIE_MSIP_BIT) 45 | 46 | `define MSTATUS_MPP_BIT 11 47 | `define MSTATUS_MPP_WIDTH 2 48 | `define MSTATUS_MPIE_BIT 7 49 | `define MSTATUS_MIE_BIT 3 50 | `define MSTATUS_MPRV_BIT 17 51 | 52 | `define MSTATUS_MIE_MASK (1 << `MSTATUS_MIE_BIT) 53 | `define MSTATUS_MPIE_MASK (1 << `MSTATUS_MPIE_BIT) 54 | `define MSTATUS_MPP_MASK (((1 << `MSTATUS_MPP_WIDTH) - 1) << `MSTATUS_MPP_BIT) 55 | `define MSTATUS_MPRV_MASK (1 << `MSTATUS_MPRV_BIT) 56 | 57 | `define GET_MIE_MTIP(mie) ((mie >> `MIE_MTIP_BIT) & 1) 58 | `define GET_MIE_MSIP(mie) ((mie >> `MIE_MTIP_BIT) & 1) 59 | 60 | `define GET_MIP_MSIP(mip) ((mip) >> `MIP_MSIP_BIT) & 1'b1 61 | `define GET_MIP_MTIP(mip) ((mip) >> `MIP_MTIP_BIT) & 1'b1 62 | `define SET_MIP_MSIP(mip, value) ((mip) & ~(1 << `MIP_MSIP_BIT)) | ((value) << `MIP_MSIP_BIT) 63 | `define SET_MIP_MTIP(mip, value) ((mip) & ~(1 << `MIP_MTIP_BIT)) | ((value) << `MIP_MTIP_BIT) 64 | `define SET_MIP_MEIP(mip, value) ((mip) & ~(1 << `MIP_MEIP_BIT)) | ((value) << `MIP_MEIP_BIT) 65 | 66 | 67 | `define SET_MSTATUS_MPP(mstatus, new_privilege_mode) ((mstatus) & ~`MSTATUS_MPP_MASK) | (((new_privilege_mode) & 2'b11) << `MSTATUS_MPP_BIT) 68 | `define GET_MSTATUS_MPP(mstatus) ((mstatus) >> `MSTATUS_MPP_BIT) & 2'b11 69 | 70 | `define SET_MSTATUS_MPIE(mstatus, mpi_value) ((mstatus) & ~`MSTATUS_MPIE_MASK) | (((mpi_value) & 1'b1) << `MSTATUS_MPIE_BIT) 71 | `define GET_MSTATUS_MPIE(mstatus) ((mstatus) >> `MSTATUS_MPIE_BIT) & 1'b1 72 | 73 | `define SET_MSTATUS_MIE(mstatus, value) ((mstatus) & ~`MSTATUS_MIE_MASK) | (((value) & 1'b1) << `MSTATUS_MIE_BIT) 74 | `define GET_MSTATUS_MIE(mstatus) ((mstatus) >> `MSTATUS_MIE_BIT) & 1'b1 75 | 76 | `define SET_MSTATUS_MPRV(mstatus, mprv_value) ((mstatus) & ~`MSTATUS_MPRV_MASK) | (((mprv_value) & 1'b1) << `MSTATUS_MPRV_BIT) 77 | `define GET_MSTATUS_MPRV(mstatus) ((mstatus) >> `MSTATUS_MPRV_BIT) & 1'b1 78 | 79 | `define IS_EBREAK(opcode, funct3, funct7, rs1, rs2, rd) ({funct7, rs2, rs1, funct3, rd, opcode} == 32'h00100073) 80 | `define IS_ECALL(opcode, funct3, funct7, rs1, rs2, rd) ({funct7, rs2, rs1, funct3, rd, opcode} == 32'h00000073) 81 | `define IS_MRET(opcode, funct3, funct7, rs1, rs2, rd) ({funct7, rs2, rs1, funct3, rd, opcode} == 32'h30200073) 82 | `define IS_WFI(opcode, funct3, funct7, rs1, rs2, rd) ({funct7, rs2, rs1, funct3, rd, opcode} == 32'h10500073) 83 | 84 | `define IRQ_M_TIMER 7 85 | `include "mcause.vh" 86 | 87 | `endif 88 | /* verilog_format: on */ 89 | -------------------------------------------------------------------------------- /Hardware/KianV-Apio/rv32_amo_opcodes.vh: -------------------------------------------------------------------------------- 1 | /* 2 | * kianv harris multicycle RISC-V rv32im 3 | * 4 | * copyright (c) 2023 hirosh dabui 5 | * 6 | * permission to use, copy, modify, and/or distribute this software for any 7 | * purpose with or without fee is hereby granted, provided that the above 8 | * copyright notice and this permission notice appear in all copies. 9 | * 10 | * the software is provided "as is" and the author disclaims all warranties 11 | * with regard to this software including all implied warranties of 12 | * merchantability and fitness. in no event shall the author be liable for 13 | * any special, direct, indirect, or consequential damages or any damages 14 | * whatsoever resulting from loss of use, data or profits, whether in an 15 | * action of contract, negligence or other tortious action, arising out of 16 | * or in connection with the use or performance of this software. 17 | */ 18 | `define RV32_AMO_OPCODE 7'h2F 19 | `define RV32_AMO_FUNCT3 3'h2 20 | `define RV32_AMOADD_W 5'h00 21 | `define RV32_AMOSWAP_W 5'h01 22 | `define RV32_LR_W 5'h02 23 | `define RV32_SC_W 5'h03 24 | `define RV32_AMOXOR_W 5'h04 25 | `define RV32_AMOAND_W 5'h0C 26 | `define RV32_AMOOR_W 5'h08 27 | `define RV32_AMOMIN_W 5'h10 28 | `define RV32_AMOMAX_W 5'h14 29 | `define RV32_AMOMINU_W 5'h18 30 | `define RV32_AMOMAXU_W 5'h1c 31 | `define RV32_FENCE_OPCODE 7'b0001111 32 | 33 | /* verilog_format: off */ 34 | `define RV32_IS_AMO_INSTRUCTION(opcode, funct3) (opcode == `RV32_AMO_OPCODE && funct3 == `RV32_AMO_FUNCT3) 35 | `define RV32_IS_AMOADD_W(funct5) (funct5 == `RV32_AMOADD_W) 36 | `define RV32_IS_AMOSWAP_W(funct5) (funct5 == `RV32_AMOSWAP_W) 37 | `define RV32_IS_LR_W(funct5) (funct5 == `RV32_LR_W) 38 | `define RV32_IS_SC_W(funct5) (funct5 == `RV32_SC_W) 39 | `define RV32_IS_AMOXOR_W(funct5) ( funct5 == `RV32_AMOXOR_W) 40 | `define RV32_IS_AMOAND_W(funct5) ( funct5 == `RV32_AMOAND_W) 41 | `define RV32_IS_AMOOR_W(funct5) ( funct5 == `RV32_AMOOR_W) 42 | `define RV32_IS_AMOMIN_W(funct5) ( funct5 == `RV32_AMOMIN_W) 43 | `define RV32_IS_AMOMAX_W(funct5) ( funct5 == `RV32_AMOMAX_W) 44 | `define RV32_IS_AMOMINU_W(funct5) ( funct5 == `RV32_AMOMINU_W) 45 | `define RV32_IS_AMOMAXU_W(funct5) ( funct5 == `RV32_AMOMAXU_W) 46 | `define RV32_IS_FENCE(opcode) ( opcode == `RV32_FENCE_OPCODE) 47 | /* verilog_format: on */ 48 | -------------------------------------------------------------------------------- /Hardware/KianV-Apio/store_alignment.v: -------------------------------------------------------------------------------- 1 | /* 2 | * kianv harris multicycle RISC-V rv32im 3 | * 4 | * copyright (c) 2022 hirosh dabui 5 | * 6 | * permission to use, copy, modify, and/or distribute this software for any 7 | * purpose with or without fee is hereby granted, provided that the above 8 | * copyright notice and this permission notice appear in all copies. 9 | * 10 | * the software is provided "as is" and the author disclaims all warranties 11 | * with regard to this software including all implied warranties of 12 | * merchantability and fitness. in no event shall the author be liable for 13 | * any special, direct, indirect, or consequential damages or any damages 14 | * whatsoever resulting from loss of use, data or profits, whether in an 15 | * action of contract, negligence or other tortious action, arising out of 16 | * or in connection with the use or performance of this software. 17 | * 18 | */ 19 | `default_nettype none `timescale 1 ns / 100 ps 20 | 21 | `include "riscv_defines.vh" 22 | 23 | module store_alignment ( 24 | input wire [ 1:0] addr, 25 | input wire [`STORE_OP_WIDTH -1:0] STOREop, 26 | input wire [ 31:0] data, 27 | output reg [ 31:0] result, 28 | output reg [ 3:0] wmask, 29 | output reg unaligned_access 30 | ); 31 | 32 | always @* begin 33 | unaligned_access = 1'b0; 34 | wmask = 0; 35 | result = 'hx; 36 | 37 | case (STOREop) 38 | (`STORE_OP_SB): begin 39 | result[7:0] = addr[1:0] == 2'b00 ? data[7:0] : 8'hx; 40 | result[15:8] = addr[1:0] == 2'b01 ? data[7:0] : 8'hx; 41 | result[23:16] = addr[1:0] == 2'b10 ? data[7:0] : 8'hx; 42 | result[31:24] = addr[1:0] == 2'b11 ? data[7:0] : 8'hx; 43 | wmask = addr[1:0] == 2'b00 ? 4'b 0001 : 44 | addr[1:0] == 2'b01 ? 4'b 0010 : 45 | addr[1:0] == 2'b10 ? 4'b 0100 : 4'b 1000; 46 | unaligned_access = 1'b0; 47 | end 48 | (`STORE_OP_SH): begin 49 | result[15:0] = ~addr[1] ? data[15:0] : 16'hx; 50 | result[31:16] = addr[1] ? data[15:0] : 16'hx; 51 | wmask = addr[1] ? 4'b1100 : 4'b0011; 52 | unaligned_access = addr[0]; 53 | end 54 | (`STORE_OP_SW): begin 55 | result = data; 56 | wmask = 4'b1111; 57 | unaligned_access = addr[1:0] != 2'b00; 58 | end 59 | default: begin 60 | result = 'hx; 61 | wmask = 4'b0000; 62 | unaligned_access = 1'b0; 63 | end 64 | endcase 65 | 66 | end 67 | endmodule 68 | -------------------------------------------------------------------------------- /Hardware/KianV-Apio/store_decoder.v: -------------------------------------------------------------------------------- 1 | /* 2 | * kianv harris multicycle RISC-V rv32im 3 | * 4 | * copyright (c) 2022 hirosh dabui 5 | * 6 | * permission to use, copy, modify, and/or distribute this software for any 7 | * purpose with or without fee is hereby granted, provided that the above 8 | * copyright notice and this permission notice appear in all copies. 9 | * 10 | * the software is provided "as is" and the author disclaims all warranties 11 | * with regard to this software including all implied warranties of 12 | * merchantability and fitness. in no event shall the author be liable for 13 | * any special, direct, indirect, or consequential damages or any damages 14 | * whatsoever resulting from loss of use, data or profits, whether in an 15 | * action of contract, negligence or other tortious action, arising out of 16 | * or in connection with the use or performance of this software. 17 | * 18 | */ 19 | `default_nettype none 20 | `timescale 1 ns/100 ps 21 | `include "riscv_defines.vh" 22 | module store_decoder 23 | ( 24 | input wire [ 2: 0] funct3, 25 | input wire amo_operation_store, 26 | output reg [`STORE_OP_WIDTH -1: 0] STOREop 27 | ); 28 | wire is_sb = funct3[1:0] == 2'b 00; 29 | wire is_sh = funct3[1:0] == 2'b 01; 30 | wire is_sw = funct3[1:0] == 2'b 10; 31 | 32 | always @(*) begin 33 | if (!amo_operation_store) begin 34 | case (1'b1) 35 | is_sb : STOREop = `STORE_OP_SB; 36 | is_sh : STOREop = `STORE_OP_SH; 37 | is_sw : STOREop = `STORE_OP_SW; 38 | default: 39 | /* verilator lint_off WIDTH */ 40 | STOREop = 'hxx; 41 | /* verilator lint_on WIDTH */ 42 | endcase 43 | end else begin 44 | STOREop = `STORE_OP_SW; 45 | end 46 | end 47 | endmodule 48 | -------------------------------------------------------------------------------- /Hardware/KianV-Icestudio/Level-00/alu.v: -------------------------------------------------------------------------------- 1 | /* 2 | * kianv harris multicycle RISC-V rv32im 3 | * 4 | * copyright (c) 2022 hirosh dabui 5 | * 6 | * permission to use, copy, modify, and/or distribute this software for any 7 | * purpose with or without fee is hereby granted, provided that the above 8 | * copyright notice and this permission notice appear in all copies. 9 | * 10 | * the software is provided "as is" and the author disclaims all warranties 11 | * with regard to this software including all implied warranties of 12 | * merchantability and fitness. in no event shall the author be liable for 13 | * any special, direct, indirect, or consequential damages or any damages 14 | * whatsoever resulting from loss of use, data or profits, whether in an 15 | * action of contract, negligence or other tortious action, arising out of 16 | * or in connection with the use or performance of this software. 17 | * 18 | */ 19 | `default_nettype none `timescale 1 ns / 100 ps 20 | `include "riscv_defines.vh" 21 | 22 | module alu ( 23 | input wire [ 31:0] a, 24 | input wire [ 31:0] b, 25 | input wire [`ALU_CTRL_WIDTH -1:0] alucontrol, 26 | output reg [ 31:0] result, 27 | output wire zero 28 | ); 29 | 30 | 31 | wire is_beq = alucontrol == `ALU_CTRL_BEQ; 32 | wire is_bne = alucontrol == `ALU_CTRL_BNE; 33 | wire is_blt = alucontrol == `ALU_CTRL_BLT; 34 | wire is_bge = alucontrol == `ALU_CTRL_BGE; 35 | wire is_bltu = alucontrol == `ALU_CTRL_BLTU; 36 | wire is_bgeu = alucontrol == `ALU_CTRL_BGEU; 37 | wire is_slt_slti = alucontrol == `ALU_CTRL_SLT_SLTI; 38 | wire is_sltu_sltiu = alucontrol == `ALU_CTRL_SLTU_SLTIU; 39 | wire is_sub_ctrl = alucontrol == `ALU_CTRL_SUB; 40 | wire is_amo_min_max = alucontrol == `ALU_CTRL_MIN || alucontrol == `ALU_CTRL_MAX || 41 | alucontrol == `ALU_CTRL_MINU || alucontrol == `ALU_CTRL_MAXU; 42 | 43 | wire is_sub = is_sub_ctrl || is_beq || is_bne || is_blt || is_bge || 44 | is_bltu || is_bgeu || is_slt_slti || is_amo_min_max || is_sltu_sltiu; 45 | 46 | 47 | wire [31:0] condinv = is_sub ? ~b : b; 48 | 49 | // seen 33 Bit sum from Bruno's Levy 50 | // with that approach I could map all branch to LT, LTU 51 | wire [32:0] sum = {1'b1, condinv} + {1'b0, a} + {32'b0, is_sub}; 52 | wire LT = (a[31] ^ b[31]) ? a[31] : sum[32]; 53 | wire LTU = sum[32]; 54 | 55 | wire [31:0] sltx_sltux_rslt = {31'b0, is_slt_slti ? LT : LTU}; 56 | wire [63:0] sext_rs1 = {{32{a[31]}}, a}; 57 | wire [63:0] sra_srai_rslt = sext_rs1 >> b[4:0]; 58 | 59 | wire is_sum_zero = sum[31:0] == 32'b0; 60 | 61 | always @* begin 62 | case (alucontrol) 63 | `ALU_CTRL_ADD_ADDI: result = sum[31:0]; 64 | `ALU_CTRL_SUB: result = sum[31:0]; 65 | `ALU_CTRL_XOR_XORI: result = a ^ b; 66 | `ALU_CTRL_OR_ORI: result = a | b; 67 | `ALU_CTRL_AND_ANDI: result = a & b; 68 | `ALU_CTRL_SLL_SLLI: result = a << b[4:0]; 69 | `ALU_CTRL_SRL_SRLI: result = a >> b[4:0]; 70 | `ALU_CTRL_SRA_SRAI: result = sra_srai_rslt[31:0]; 71 | `ALU_CTRL_SLT_SLTI: result = (a[31] == b[31]) ? sltx_sltux_rslt : {31'b0, a[31]}; 72 | `ALU_CTRL_SLTU_SLTIU: result = sltx_sltux_rslt; 73 | `ALU_CTRL_MIN: result = LT ? a : b; 74 | `ALU_CTRL_MAX: result = !LT ? a : b; 75 | `ALU_CTRL_MINU: result = LTU ? a : b; 76 | `ALU_CTRL_MAXU: result = !LTU ? a : b; 77 | `ALU_CTRL_LUI: result = b; 78 | `ALU_CTRL_AUIPC: result = sum[31:0]; 79 | default: begin 80 | case (1'b1) 81 | is_beq: result = {31'b0, is_sum_zero}; 82 | is_bne: result = {31'b0, !is_sum_zero}; 83 | is_blt: result = {31'b0, LT}; 84 | is_bge: result = {31'b0, !LT}; 85 | is_bltu: result = {31'b0, LTU}; 86 | is_bgeu: result = {31'b0, !LTU}; 87 | default: result = 32'b0; 88 | endcase 89 | end 90 | endcase 91 | end 92 | 93 | assign zero = result == 32'b0; 94 | endmodule 95 | -------------------------------------------------------------------------------- /Hardware/KianV-Icestudio/Level-00/bram.v: -------------------------------------------------------------------------------- 1 | /* 2 | * kianv.v - a simple RISC-V rv32i 3 | * 4 | * copyright (c) 2022 hirosh dabui 5 | * 6 | * permission to use, copy, modify, and/or distribute this software for any 7 | * purpose with or without fee is hereby granted, provided that the above 8 | * copyright notice and this permission notice appear in all copies. 9 | * 10 | * the software is provided "as is" and the author disclaims all warranties 11 | * with regard to this software including all implied warranties of 12 | * merchantability and fitness. in no event shall the author be liable for 13 | * any special, direct, indirect, or consequential damages or any damages 14 | * whatsoever resulting from loss of use, data or profits, whether in an 15 | * action of contract, negligence or other tortious action, arising out of 16 | * or in connection with the use or performance of this software. 17 | * 18 | */ 19 | `default_nettype none `timescale 1 ns / 100 ps 20 | module bram #( 21 | parameter integer WIDTH = 8, 22 | parameter INIT_FILE = "", 23 | parameter SHOW_FIRMWARE = 0 24 | ) ( 25 | input wire clk, 26 | input wire [WIDTH -1:0] addr, 27 | input wire [31:0] wdata, 28 | output reg [31:0] rdata, 29 | input wire [3:0] wmask 30 | ); 31 | reg [31:0] mem[0:(1< 5 | * 6 | * permission to use, copy, modify, and/or distribute this software for any 7 | * purpose with or without fee is hereby granted, provided that the above 8 | * copyright notice and this permission notice appear in all copies. 9 | * 10 | * the software is provided "as is" and the author disclaims all warranties 11 | * with regard to this software including all implied warranties of 12 | * merchantability and fitness. in no event shall the author be liable for 13 | * any special, direct, indirect, or consequential damages or any damages 14 | * whatsoever resulting from loss of use, data or profits, whether in an 15 | * action of contract, negligence or other tortious action, arising out of 16 | * or in connection with the use or performance of this software. 17 | * 18 | */ 19 | `default_nettype none `timescale 1 ns / 100 ps 20 | module clint #( 21 | parameter SYSTEM_CLK = 25_000_000, 22 | parameter CLOCK_TICK = 1000 23 | ) ( 24 | input wire clk, 25 | input wire resetn, 26 | input wire valid, 27 | input wire [31:0] addr, 28 | input wire [3:0] wmask, 29 | input wire [31:0] wdata, 30 | output reg [31:0] rdata, 31 | output wire is_valid, 32 | output reg ready, 33 | output wire IRQ3, 34 | output wire IRQ7 35 | ); 36 | 37 | /* verilator lint_off WIDTHTRUNC */ 38 | localparam CLOCK_TICK_BIT_WIDTH = $clog2(CLOCK_TICK); 39 | localparam [CLOCK_TICK_BIT_WIDTH -1:0] CYCLES_TO_TICK = ($rtoi(SYSTEM_CLK / CLOCK_TICK)); 40 | /* verilator lint_on WIDTHTRUNC */ 41 | wire is_msip = (addr == 32'h1100_0000); 42 | wire is_mtimecmpl = (addr == 32'h1100_4000); 43 | wire is_mtimecmph = (addr == 32'h1100_4004); 44 | wire is_mtimeh = (addr == 32'h1100_bffc); 45 | wire is_mtimel = (addr == 32'h1100_bff8); 46 | 47 | assign is_valid = valid && (is_msip || is_mtimecmpl || is_mtimecmph || is_mtimel || is_mtimeh); 48 | always @(posedge clk) ready <= !resetn ? 1'b0 : is_valid; 49 | 50 | reg [63:0] mtime; 51 | always @(posedge clk) mtime <= !resetn ? 0 : (tick) ? mtime + 1 : mtime; 52 | 53 | wire is_we = |wmask; 54 | 55 | reg [63:0] mtimecmp; 56 | reg msip; 57 | 58 | always @(posedge clk) 59 | if (!resetn) begin 60 | mtimecmp <= 0; 61 | msip <= 0; 62 | end else if (is_mtimecmpl && is_valid) begin 63 | if (wmask[0]) mtimecmp[7:0] <= wdata[7:0]; 64 | if (wmask[1]) mtimecmp[15:8] <= wdata[15:8]; 65 | if (wmask[2]) mtimecmp[23:16] <= wdata[23:16]; 66 | if (wmask[3]) mtimecmp[31:24] <= wdata[31:24]; 67 | end else if (is_mtimecmph && is_valid) begin 68 | if (wmask[0]) mtimecmp[39:32] <= wdata[7:0]; 69 | if (wmask[1]) mtimecmp[47:40] <= wdata[15:8]; 70 | if (wmask[2]) mtimecmp[55:48] <= wdata[23:16]; 71 | if (wmask[3]) mtimecmp[63:56] <= wdata[31:24]; 72 | end else if (is_msip && is_valid) begin 73 | if (wmask[0]) msip <= wdata[0]; 74 | end 75 | 76 | always @(*) begin 77 | case (1'b1) 78 | is_mtimecmpl: rdata = mtimecmp[31:0]; 79 | is_mtimecmph: rdata = mtimecmp[63:32]; 80 | is_mtimel: rdata = mtime[31:0]; 81 | is_mtimeh: rdata = mtime[63:32]; 82 | is_msip: rdata = {31'b0, msip}; 83 | default: rdata = 0; 84 | endcase 85 | end 86 | 87 | 88 | reg [CLOCK_TICK_BIT_WIDTH -1:0] tick_cnt; 89 | wire tick = tick_cnt == (CYCLES_TO_TICK - 1); 90 | always @(posedge clk) begin 91 | if (!resetn) begin 92 | tick_cnt <= 0; 93 | end else begin 94 | if (tick) begin 95 | tick_cnt <= 0; 96 | end else begin 97 | tick_cnt <= tick_cnt + 1; 98 | end 99 | end 100 | end 101 | 102 | assign IRQ3 = msip; 103 | assign IRQ7 = (mtime >= mtimecmp); 104 | 105 | endmodule 106 | 107 | -------------------------------------------------------------------------------- /Hardware/KianV-Icestudio/Level-00/csr_utilities.vh: -------------------------------------------------------------------------------- 1 | /* 2 | * kianv.v - RISC-V rv32ima 3 | * 4 | * copyright (c) 2023 hirosh dabui 5 | * 6 | * permission to use, copy, modify, and/or distribute this software for any 7 | * purpose with or without fee is hereby granted, provided that the above 8 | * copyright notice and this permission notice appear in all copies. 9 | * 10 | * the software is provided "as is" and the author disclaims all warranties 11 | * with regard to this software including all implied warranties of 12 | * merchantability and fitness. in no event shall the author be liable for 13 | * any special, direct, indirect, or consequential damages or any damages 14 | * whatsoever resulting from loss of use, data or profits, whether in an 15 | * action of contract, negligence or other tortious action, arising out of 16 | * or in connection with the use or performance of this software. 17 | * 18 | */ 19 | `ifndef CSR_UTILITIES_VH 20 | `define CSR_UTILITIES_VH 21 | 22 | // Unprivileged Counter/Timers 23 | `define CSR_REG_CYCLE 12'h C00 24 | `define CSR_REG_CYCLEH 12'h C80 25 | `define CSR_REG_INSTRET 12'h C02 26 | `define CSR_REG_INSTRETH 12'h C82 27 | `define CSR_REG_TIME 12'h C01 28 | `define CSR_REG_TIMEH 12'h C81 29 | 30 | // Machine Trap Setup 31 | `define CSR_REG_MSTATUS 12'h 300 32 | `define CSR_REG_MISA 12'h 301 33 | `define CSR_REG_MIE 12'h 304 34 | `define CSR_REG_MTVEC 12'h 305 35 | 36 | // Machine Trap Handling 37 | `define CSR_REG_MSCRATCH 12'h 340 38 | `define CSR_REG_MEPC 12'h 341 39 | `define CSR_REG_MCAUSE 12'h 342 40 | `define CSR_REG_MTVAL 12'h 343 41 | `define CSR_REG_MIP 12'h 344 42 | 43 | `define CSR_REG_MCOUNTEREN 12'h 306 44 | 45 | `define CSR_REG_MHARTID 12'h f14 46 | `define CSR_REG_MVENDORID 12'h f11 47 | 48 | // Machine-Level CSRs 49 | // custrom read-only 50 | `define CSR_PRIVILEGE_MODE 12'h fc0 // machine privilege mode 51 | 52 | 53 | // RISC-V CSR instruction opcodes (7-bit) and funct3 (3-bit) 54 | `define CSR_OPCODE `SYSTEM_OPCODE 55 | `define CSR_FUNCT3_RW 3'b001 56 | `define CSR_FUNCT3_RS 3'b010 57 | `define CSR_FUNCT3_RC 3'b011 58 | `define CSR_FUNCT3_RWI 3'b101 59 | `define CSR_FUNCT3_RSI 3'b110 60 | `define CSR_FUNCT3_RCI 3'b111 61 | 62 | `include "riscv_priv_csr_status.vh" 63 | `include "misa.vh" 64 | `endif 65 | -------------------------------------------------------------------------------- /Hardware/KianV-Icestudio/Level-00/defines_soc.vh: -------------------------------------------------------------------------------- 1 | /* 2 | * kianv harris multicycle RISC-V rv32im 3 | * 4 | * copyright (c) 2023 hirosh dabui 5 | * 6 | * permission to use, copy, modify, and/or distribute this software for any 7 | * purpose with or without fee is hereby granted, provided that the above 8 | * copyright notice and this permission notice appear in all copies. 9 | * 10 | * the software is provided "as is" and the author disclaims all warranties 11 | * with regard to this software including all implied warranties of 12 | * merchantability and fitness. in no event shall the author be liable for 13 | * any special, direct, indirect, or consequential damages or any damages 14 | * whatsoever resulting from loss of use, data or profits, whether in an 15 | * action of contract, negligence or other tortious action, arising out of 16 | * or in connection with the use or performance of this software. 17 | * 18 | */ 19 | `ifndef KIANV_SOC 20 | `define KIANV_SOC 21 | 22 | `define CPU_FREQ_REG_ADDR 32'h 30_000_010 23 | `define BAUDRATE 3_000_000 24 | 25 | `define UART_TX_ADDR 32'h 10_000_000 26 | `define UART_RX_ADDR 32'h 10_000_000 27 | `define UART_LSR_ADDR 32'h 10_000_005 28 | 29 | 30 | `define RV32M 31 | `define FAKE_MULTIPLIER 32 | `define LED_ULX3S 33 | 34 | `define QUAD_SPI_FLASH_MODE 1'b1 35 | 36 | `define UART_TX 37 | `define UART_RX 38 | 39 | `define SDRAM_MEM_ADDR_START 32'h 80_000_000 40 | `define SDRAM_SIZE (1024*1024*32) 41 | `define SDRAM_MEM_ADDR_END ((`SDRAM_MEM_ADDR_START) + (`SDRAM_SIZE)) 42 | 43 | `define SYSTEM_CLK 70_000_000 44 | `define SYSTEM_CLK_MHZ (`SYSTEM_CLK / 1_000_000) 45 | 46 | `define SPI_NOR_MEM_ADDR_START 32'h 20_000_000 47 | 48 | `define SPI_MEMORY_OFFSET (1024*1024) 49 | `define SPI_NOR_MEM_ADDR_END ((`SPI_NOR_MEM_ADDR_START) + (16*1024*1024)) 50 | 51 | `define RESET_ADDR (`SPI_NOR_MEM_ADDR_START + `SPI_MEMORY_OFFSET) 52 | `define FIRMWARE_BRAM "" 53 | `define BRAM_WORDS (1024*16) 54 | 55 | `endif 56 | -------------------------------------------------------------------------------- /Hardware/KianV-Icestudio/Level-00/design_elements.v: -------------------------------------------------------------------------------- 1 | /* 2 | * kianv harris multicycle RISC-V rv32im 3 | * 4 | * copyright (c) 2022/23 hirosh dabui 5 | * 6 | * permission to use, copy, modify, and/or distribute this software for any 7 | * purpose with or without fee is hereby granted, provided that the above 8 | * copyright notice and this permission notice appear in all copies. 9 | * 10 | * the software is provided "as is" and the author disclaims all warranties 11 | * with regard to this software including all implied warranties of 12 | * merchantability and fitness. in no event shall the author be liable for 13 | * any special, direct, indirect, or consequential damages or any damages 14 | * whatsoever resulting from loss of use, data or profits, whether in an 15 | * action of contract, negligence or other tortious action, arising out of 16 | * or in connection with the use or performance of this software. 17 | * 18 | */ 19 | `default_nettype none `timescale 1 ns / 100 ps 20 | /* verilator lint_off MULTITOP */ 21 | 22 | module mux2 #( 23 | parameter WIDTH = 32 24 | ) ( 25 | input wire [WIDTH -1:0] d0, 26 | d1, 27 | input wire s, 28 | output wire [WIDTH -1:0] y 29 | ); 30 | 31 | assign y = s ? d1 : d0; 32 | endmodule 33 | 34 | module mux3 #( 35 | parameter WIDTH = 32 36 | ) ( 37 | input wire [WIDTH -1:0] d0, 38 | d1, 39 | d2, 40 | input wire [ 1:0] s, 41 | output wire [WIDTH -1:0] y 42 | ); 43 | 44 | assign y = s[1] ? d2 : (s[0] ? d1 : d0); 45 | endmodule 46 | 47 | module mux4 #( 48 | parameter WIDTH = 32 49 | ) ( 50 | input wire [WIDTH -1:0] d0, 51 | d1, 52 | d2, 53 | d3, 54 | input wire [ 1:0] s, 55 | output wire [WIDTH -1:0] y 56 | ); 57 | 58 | wire [WIDTH -1:0] low, high; 59 | 60 | mux2 lowmux ( 61 | d0, 62 | d1, 63 | s[0], 64 | low 65 | ); 66 | mux2 highmux ( 67 | d2, 68 | d3, 69 | s[0], 70 | high 71 | ); 72 | mux2 finalmux ( 73 | low, 74 | high, 75 | s[1], 76 | y 77 | ); 78 | endmodule 79 | 80 | module mux5 #( 81 | parameter WIDTH = 32 82 | ) ( 83 | input wire [WIDTH -1:0] d0, 84 | d1, 85 | d2, 86 | d3, 87 | d4, 88 | input wire [ 2:0] s, 89 | output wire [WIDTH -1:0] y 90 | 91 | ); 92 | 93 | assign y = (s == 0) ? d0 : (s == 1) ? d1 : (s == 2) ? d2 : (s == 3) ? d3 : d4; 94 | 95 | endmodule 96 | 97 | module mux6 #( 98 | parameter WIDTH = 32 99 | ) ( 100 | input wire [WIDTH -1:0] d0, 101 | d1, 102 | d2, 103 | d3, 104 | d4, 105 | d5, 106 | input wire [ 2:0] s, 107 | output wire [WIDTH -1:0] y 108 | 109 | ); 110 | 111 | assign y = (s == 0) ? d0 : (s == 1) ? d1 : (s == 2) ? d2 : (s == 3) ? d3 : (s == 4) ? d4 : d5; 112 | 113 | endmodule 114 | 115 | module dlatch #( 116 | parameter WIDTH = 32 117 | ) ( 118 | input wire clk, 119 | input wire [WIDTH -1:0] d, 120 | output reg [WIDTH -1:0] q 121 | ); 122 | always @(posedge clk) q <= d; 123 | endmodule 124 | 125 | module dff #( 126 | parameter WIDTH = 32, 127 | parameter PRESET = 0 128 | ) ( 129 | input wire resetn, 130 | input wire clk, 131 | input wire en, 132 | input wire [WIDTH -1:0] d, 133 | output reg [WIDTH -1:0] q 134 | ); 135 | always @(posedge clk) 136 | if (!resetn) q <= PRESET; 137 | else if (en) q <= d; 138 | 139 | endmodule 140 | module counter #( 141 | parameter WIDTH = 32 142 | ) ( 143 | input wire resetn, 144 | input wire clk, 145 | input wire inc, 146 | output reg [WIDTH -1:0] q 147 | ); 148 | always @(posedge clk) 149 | if (!resetn) q <= 0; 150 | else if (inc) q <= q + 1; 151 | 152 | endmodule 153 | /* verilator lint_on MULTITOP */ 154 | -------------------------------------------------------------------------------- /Hardware/KianV-Icestudio/Level-00/divider_decoder.v: -------------------------------------------------------------------------------- 1 | /* 2 | * kianv harris multicycle RISC-V rv32im 3 | * 4 | * copyright (c) 2022 hirosh dabui 5 | * 6 | * permission to use, copy, modify, and/or distribute this software for any 7 | * purpose with or without fee is hereby granted, provided that the above 8 | * copyright notice and this permission notice appear in all copies. 9 | * 10 | * the software is provided "as is" and the author disclaims all warranties 11 | * with regard to this software including all implied warranties of 12 | * merchantability and fitness. in no event shall the author be liable for 13 | * any special, direct, indirect, or consequential damages or any damages 14 | * whatsoever resulting from loss of use, data or profits, whether in an 15 | * action of contract, negligence or other tortious action, arising out of 16 | * or in connection with the use or performance of this software. 17 | * 18 | */ 19 | `default_nettype none `timescale 1 ns / 100 ps 20 | `include "riscv_defines.vh" 21 | module divider_decoder ( 22 | input wire [ 2:0] funct3, 23 | output reg [`DIV_OP_WIDTH -1:0] DIVop, 24 | input wire mul_ext_valid, 25 | output wire div_valid 26 | ); 27 | 28 | wire is_div = funct3 == 3'b100; 29 | wire is_divu = funct3 == 3'b101; 30 | wire is_rem = funct3 == 3'b110; 31 | wire is_remu = funct3 == 3'b111; 32 | reg valid; 33 | 34 | assign div_valid = valid & mul_ext_valid; 35 | 36 | always @(*) begin 37 | valid = 1'b1; 38 | case (1'b1) 39 | is_div: DIVop = `DIV_OP_DIV; 40 | is_divu: DIVop = `DIV_OP_DIVU; 41 | is_rem: DIVop = `DIV_OP_REM; 42 | is_remu: DIVop = `DIV_OP_REMU; 43 | default: begin 44 | /* verilator lint_off WIDTH */ 45 | DIVop = 'hxx; 46 | /* verilator lint_on WIDTH */ 47 | valid = 1'b0; 48 | end 49 | endcase 50 | end 51 | 52 | endmodule 53 | -------------------------------------------------------------------------------- /Hardware/KianV-Icestudio/Level-00/extend.v: -------------------------------------------------------------------------------- 1 | /* 2 | * kianv harris multicycle RISC-V rv32im 3 | * 4 | * copyright (c) 2022 hirosh dabui 5 | * 6 | * permission to use, copy, modify, and/or distribute this software for any 7 | * purpose with or without fee is hereby granted, provided that the above 8 | * copyright notice and this permission notice appear in all copies. 9 | * 10 | * the software is provided "as is" and the author disclaims all warranties 11 | * with regard to this software including all implied warranties of 12 | * merchantability and fitness. in no event shall the author be liable for 13 | * any special, direct, indirect, or consequential damages or any damages 14 | * whatsoever resulting from loss of use, data or profits, whether in an 15 | * action of contract, negligence or other tortious action, arising out of 16 | * or in connection with the use or performance of this software. 17 | * 18 | */ 19 | `default_nettype none `timescale 1 ns / 100 ps 20 | `include "riscv_defines.vh" 21 | module extend ( 22 | input wire [31:7] instr, 23 | input wire [ 2:0] immsrc, 24 | output reg [31:0] immext 25 | ); 26 | 27 | always @(*) begin 28 | case (immsrc) 29 | `IMMSRC_ITYPE: immext = {{20{instr[31]}}, instr[31:20]}; 30 | `IMMSRC_STYPE: immext = {{20{instr[31]}}, instr[31:25], instr[11:7]}; 31 | `IMMSRC_BTYPE: immext = {{20{instr[31]}}, instr[7:7], instr[30:25], instr[11:8], 1'b0}; 32 | `IMMSRC_JTYPE: immext = {{12{instr[31]}}, instr[19:12], instr[20], instr[30:21], 1'b0}; 33 | `IMMSRC_UTYPE: immext = {instr[31:12], 12'b0}; 34 | default: immext = 32'b0; 35 | endcase 36 | end 37 | endmodule 38 | -------------------------------------------------------------------------------- /Hardware/KianV-Icestudio/Level-00/fifo.v: -------------------------------------------------------------------------------- 1 | /* 2 | * fifo.v 3 | * 4 | * copyright (c) 2021 hirosh dabui 5 | * 6 | * permission to use, copy, modify, and/or distribute this software for any 7 | * purpose with or without fee is hereby granted, provided that the above 8 | * copyright notice and this permission notice appear in all copies. 9 | * 10 | * the software is provided "as is" and the author disclaims all warranties 11 | * with regard to this software including all implied warranties of 12 | * merchantability and fitness. in no event shall the author be liable for 13 | * any special, direct, indirect, or consequential damages or any damages 14 | * whatsoever resulting from loss of use, data or profits, whether in an 15 | * action of contract, negligence or other tortious action, arising out of 16 | * or in connection with the use or performance of this software. 17 | * 18 | */ 19 | 20 | `default_nettype none `timescale 1 ns / 100 ps 21 | module fifo #( 22 | parameter DATA_WIDTH = 8, 23 | parameter DEPTH = 4 24 | ) ( 25 | input wire clk, 26 | input wire resetn, 27 | input wire [DATA_WIDTH-1:0] din, 28 | output wire [DATA_WIDTH-1:0] dout, 29 | input wire push, 30 | input wire pop, 31 | output wire full, 32 | output wire empty 33 | ); 34 | 35 | reg [DATA_WIDTH-1:0] ram[0:DEPTH-1]; 36 | 37 | reg [$clog2(DEPTH):0] cnt; 38 | reg [$clog2(DEPTH)-1:0] rd_ptr; 39 | reg [$clog2(DEPTH)-1:0] wr_ptr; 40 | 41 | reg [$clog2(DEPTH):0] cnt_next; 42 | reg [$clog2(DEPTH)-1:0] rd_ptr_next; 43 | reg [$clog2(DEPTH)-1:0] wr_ptr_next; 44 | 45 | assign empty = cnt == 0; 46 | assign full = cnt == DEPTH; 47 | 48 | always @(posedge clk) begin 49 | if (~resetn) begin 50 | rd_ptr <= 0; 51 | wr_ptr <= 0; 52 | cnt <= 0; 53 | end else begin 54 | rd_ptr <= rd_ptr_next; 55 | wr_ptr <= wr_ptr_next; 56 | cnt <= cnt_next; 57 | end 58 | end 59 | 60 | always @(*) begin 61 | rd_ptr_next = rd_ptr; 62 | wr_ptr_next = wr_ptr; 63 | cnt_next = cnt; 64 | 65 | if (push) begin 66 | wr_ptr_next = wr_ptr + 1; 67 | cnt_next = (!pop || empty) ? cnt + 1 : cnt_next; 68 | end 69 | 70 | if (pop) begin 71 | rd_ptr_next = rd_ptr + 1; 72 | cnt_next = (!push || full) ? cnt - 1 : cnt_next; 73 | end 74 | 75 | end 76 | 77 | always @(posedge clk) begin 78 | if (push) ram[wr_ptr] <= din; 79 | end 80 | 81 | assign dout = ram[rd_ptr]; 82 | 83 | endmodule 84 | -------------------------------------------------------------------------------- /Hardware/KianV-Icestudio/Level-00/flash.sh: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | 3 | apio raw "fujprog -l 4 -j FLASH ice-build/Linux-soc-KianV-00/hardware.bit" -------------------------------------------------------------------------------- /Hardware/KianV-Icestudio/Level-00/load_alignment.v: -------------------------------------------------------------------------------- 1 | /* 2 | * kianv harris multicycle RISC-V rv32ima 3 | * 4 | * copyright (c) 2023 hirosh dabui 5 | * 6 | * permission to use, copy, modify, and/or distribute this software for any 7 | * purpose with or without fee is hereby granted, provided that the above 8 | * copyright notice and this permission notice appear in all copies. 9 | * 10 | * the software is provided "as is" and the author disclaims all warranties 11 | * with regard to this software including all implied warranties of 12 | * merchantability and fitness. in no event shall the author be liable for 13 | * any special, direct, indirect, or consequential damages or any damages 14 | * whatsoever resulting from loss of use, data or profits, whether in an 15 | * action of contract, negligence or other tortious action, arising out of 16 | * or in connection with the use or performance of this software. 17 | * 18 | */ 19 | `default_nettype none `timescale 1 ns / 100 ps 20 | `include "riscv_defines.vh" 21 | module load_alignment ( 22 | input wire [ 1:0] addr, 23 | input wire [`LOAD_OP_WIDTH -1:0] LOADop, 24 | input wire [ 31:0] data, 25 | output reg [ 31:0] result, 26 | output reg unaligned_access 27 | ); 28 | 29 | wire is_lb = `LOAD_OP_LB == LOADop; 30 | wire is_lbu = `LOAD_OP_LBU == LOADop; 31 | 32 | wire is_lh = `LOAD_OP_LH == LOADop; 33 | wire is_lhu = `LOAD_OP_LHU == LOADop; 34 | 35 | wire is_lw = `LOAD_OP_LW == LOADop; 36 | 37 | always @* begin 38 | result = 'hx; 39 | unaligned_access = 1'b0; 40 | if (is_lb | is_lbu) begin 41 | result[7:0] = 42 | addr[1:0] == 2'b00 ? data[7 :0] : 43 | addr[1:0] == 2'b01 ? data[15 :8] : 44 | addr[1:0] == 2'b10 ? data[23:16] : 45 | addr[1:0] == 2'b11 ? data[31:24] : 8'hx; 46 | result = {is_lbu ? 24'b0 : {24{result[7]}}, result[7:0]}; 47 | unaligned_access = 1'b0; 48 | end 49 | 50 | if (is_lh | is_lhu) begin 51 | result[15:0] = ~addr[1] ? data[15 : 0] : addr[1] ? data[31 : 16] : 16'hx; 52 | result = {is_lhu ? 16'b0 : {16{result[15]}}, result[15:0]}; 53 | unaligned_access = addr[0]; 54 | end 55 | 56 | if (is_lw) begin 57 | result = data; 58 | unaligned_access = addr[1:0] != 2'b00; 59 | end 60 | end 61 | 62 | endmodule 63 | -------------------------------------------------------------------------------- /Hardware/KianV-Icestudio/Level-00/load_decoder.v: -------------------------------------------------------------------------------- 1 | /* 2 | * kianv harris multicycle RISC-V rv32im 3 | * 4 | * copyright (c) 2022 hirosh dabui 5 | * 6 | * permission to use, copy, modify, and/or distribute this software for any 7 | * purpose with or without fee is hereby granted, provided that the above 8 | * copyright notice and this permission notice appear in all copies. 9 | * 10 | * the software is provided "as is" and the author disclaims all warranties 11 | * with regard to this software including all implied warranties of 12 | * merchantability and fitness. in no event shall the author be liable for 13 | * any special, direct, indirect, or consequential damages or any damages 14 | * whatsoever resulting from loss of use, data or profits, whether in an 15 | * action of contract, negligence or other tortious action, arising out of 16 | * or in connection with the use or performance of this software. 17 | * 18 | */ 19 | `default_nettype none 20 | `timescale 1 ns/100 ps 21 | `include "riscv_defines.vh" 22 | module load_decoder 23 | ( 24 | input wire [ 2: 0] funct3, 25 | input wire amo_load, 26 | output reg [`LOAD_OP_WIDTH -1: 0] LOADop 27 | ); 28 | wire is_lb = funct3 == 3'b 000; 29 | wire is_lh = funct3 == 3'b 001; 30 | wire is_lw = funct3 == 3'b 010; 31 | wire is_lbu = funct3 == 3'b 100; 32 | wire is_lhu = funct3 == 3'b 101; 33 | 34 | always @(*) begin 35 | if (!amo_load) begin 36 | case (1'b1) 37 | is_lb : LOADop = `LOAD_OP_LB; 38 | is_lh : LOADop = `LOAD_OP_LH; 39 | is_lw : LOADop = `LOAD_OP_LW; 40 | is_lbu : LOADop = `LOAD_OP_LBU; 41 | is_lhu : LOADop = `LOAD_OP_LHU; 42 | default: 43 | /* verilator lint_off WIDTH */ 44 | LOADop = 'hxx; 45 | /* verilator lint_on WIDTH */ 46 | endcase 47 | end else begin 48 | LOADop = `LOAD_OP_LW; 49 | end 50 | end 51 | 52 | endmodule 53 | -------------------------------------------------------------------------------- /Hardware/KianV-Icestudio/Level-00/mcause.vh: -------------------------------------------------------------------------------- 1 | /* 2 | * kianv.v - RISC-V rv32ima 3 | * 4 | * copyright (c) 2023 hirosh dabui 5 | * 6 | * permission to use, copy, modify, and/or distribute this software for any 7 | * purpose with or without fee is hereby granted, provided that the above 8 | * copyright notice and this permission notice appear in all copies. 9 | * 10 | * the software is provided "as is" and the author disclaims all warranties 11 | * with regard to this software including all implied warranties of 12 | * merchantability and fitness. in no event shall the author be liable for 13 | * any special, direct, indirect, or consequential damages or any damages 14 | * whatsoever resulting from loss of use, data or profits, whether in an 15 | * action of contract, negligence or other tortious action, arising out of 16 | * or in connection with the use or performance of this software. 17 | * 18 | */ 19 | `ifndef MCAUSE_VH 20 | `define MCAUSE_VH 21 | // Exception codes 22 | `define EXC_INSTR_ADDR_MISALIGNED 32'h00000000 23 | `define EXC_INSTR_ACCESS_FAULT 32'h00000001 24 | `define EXC_ILLEGAL_INSTRUCTION 32'h00000002 25 | `define EXC_BREAKPOINT 32'h00000003 26 | `define EXC_LOAD_AMO_ADDR_MISALIGNED 32'h00000004 27 | `define EXC_LOAD_AMO_ACCESS_FAULT 32'h00000005 28 | `define EXC_STORE_AMO_ADDR_MISALIGNED 32'h00000006 29 | `define EXC_STORE_AMO_ACCESS_FAULT 32'h00000007 30 | `define EXC_ECALL_FROM_UMODE 32'h00000008 31 | `define EXC_ECALL_FROM_SMODE 32'h00000009 32 | `define EXC_ECALL_FROM_MMODE 32'h0000000B 33 | `define EXC_INSTR_PAGE_FAULT 32'h0000000C 34 | `define EXC_LOAD_PAGE_FAULT 32'h0000000D 35 | `define EXC_STORE_AMO_PAGE_FAULT 32'h0000000F 36 | 37 | // Interrupt codes 38 | `define INTERRUPT_USER_SOFTWARE 32'h80000000 39 | `define INTERRUPT_SUPERVISOR_SOFTWARE 32'h80000001 40 | `define INTERRUPT_MACHINE_SOFTWARE 32'h80000003 41 | `define INTERRUPT_USER_TIMER 32'h80000004 42 | `define INTERRUPT_SUPERVISOR_TIMER 32'h80000005 43 | `define INTERRUPT_MACHINE_TIMER 32'h80000007 44 | `define INTERRUPT_USER_EXTERNAL 32'h80000008 45 | `define INTERRUPT_SUPERVISOR_EXTERNAL 32'h80000009 46 | `define INTERRUPT_MACHINE_EXTERNAL 32'h8000000B 47 | `endif 48 | -------------------------------------------------------------------------------- /Hardware/KianV-Icestudio/Level-00/misa.vh: -------------------------------------------------------------------------------- 1 | /* 2 | * kianv.v - RISC-V rv32ima 3 | * 4 | * copyright (c) 2023 hirosh dabui 5 | * 6 | * permission to use, copy, modify, and/or distribute this software for any 7 | * purpose with or without fee is hereby granted, provided that the above 8 | * copyright notice and this permission notice appear in all copies. 9 | * 10 | * the software is provided "as is" and the author disclaims all warranties 11 | * with regard to this software including all implied warranties of 12 | * merchantability and fitness. in no event shall the author be liable for 13 | * any special, direct, indirect, or consequential damages or any damages 14 | * whatsoever resulting from loss of use, data or profits, whether in an 15 | * action of contract, negligence or other tortious action, arising out of 16 | * or in connection with the use or performance of this software. 17 | * 18 | */ 19 | `ifndef MISA_VH 20 | `define MISA_VH 21 | 22 | `define MISA_MXL_RV32 2'b01 23 | `define MISA_EXTENSION_A 5'd0 24 | `define MISA_EXTENSION_B 5'd1 25 | `define MISA_EXTENSION_C 5'd2 26 | `define MISA_EXTENSION_D 5'd3 27 | `define MISA_EXTENSION_E 5'd4 28 | `define MISA_EXTENSION_F 5'd5 29 | `define MISA_EXTENSION_G 5'd6 30 | `define MISA_EXTENSION_H 5'd7 31 | `define MISA_EXTENSION_I 5'd8 32 | `define MISA_EXTENSION_J 5'd9 33 | `define MISA_EXTENSION_K 5'd10 34 | `define MISA_EXTENSION_L 5'd11 35 | `define MISA_EXTENSION_M 5'd12 36 | `define MISA_EXTENSION_N 5'd13 37 | `define MISA_EXTENSION_O 5'd14 38 | `define MISA_EXTENSION_P 5'd15 39 | `define MISA_EXTENSION_Q 5'd16 40 | `define MISA_EXTENSION_R 5'd17 41 | `define MISA_EXTENSION_S 5'd18 42 | `define MISA_EXTENSION_T 5'd19 43 | `define MISA_EXTENSION_U 5'd20 44 | `define MISA_EXTENSION_V 5'd21 45 | `define MISA_EXTENSION_W 5'd22 46 | `define MISA_EXTENSION_X 5'd23 47 | `define MISA_EXTENSION_Y 5'd24 48 | `define MISA_EXTENSION_Z 5'd25 49 | 50 | `define IS_EXTENSION_SUPPORTED(MXL, Extensions, Ext_To_Check) \ 51 | ((MXL) == `MISA_MXL_RV32) && (((Extensions) >> (Ext_To_Check)) & 1'b1) 52 | `define SET_MISA_VALUE(MXL) (MXL << 30) 53 | `define MISA_EXTENSION_BIT(extension) (1 << extension) 54 | 55 | `endif 56 | -------------------------------------------------------------------------------- /Hardware/KianV-Icestudio/Level-00/multiplier.v: -------------------------------------------------------------------------------- 1 | /* 2 | * kianv harris multicycle RISC-V rv32im 3 | * 4 | * copyright (c) 2022 hirosh dabui 5 | * 6 | * permission to use, copy, modify, and/or distribute this software for any 7 | * purpose with or without fee is hereby granted, provided that the above 8 | * copyright notice and this permission notice appear in all copies. 9 | * 10 | * the software is provided "as is" and the author disclaims all warranties 11 | * with regard to this software including all implied warranties of 12 | * merchantability and fitness. in no event shall the author be liable for 13 | * any special, direct, indirect, or consequential damages or any damages 14 | * whatsoever resulting from loss of use, data or profits, whether in an 15 | * action of contract, negligence or other tortious action, arising out of 16 | * or in connection with the use or performance of this software. 17 | * 18 | */ 19 | `default_nettype none `timescale 1 ns / 100 ps 20 | 21 | `include "riscv_defines.vh" 22 | module multiplier ( 23 | input wire clk, 24 | input wire resetn, 25 | input wire [ 31 : 0] factor1, 26 | input wire [ 31 : 0] factor2, 27 | input wire [`MUL_OP_WIDTH -1 : 0] MULop, 28 | output wire [ 31 : 0] product, 29 | input wire valid, 30 | output reg ready 31 | ); 32 | 33 | wire is_mulh = MULop == `MUL_OP_MULH; 34 | wire is_mulsu = MULop == `MUL_OP_MULSU; 35 | wire is_mulu = MULop == `MUL_OP_MULU; 36 | 37 | wire factor1_is_signed = is_mulh | is_mulsu; 38 | wire factor2_is_signed = is_mulh; 39 | 40 | // multiplication 41 | reg [63:0] rslt; 42 | reg [31:0] factor1_abs; 43 | reg [31:0] factor2_abs; 44 | reg [4:0] bit_idx; 45 | 46 | localparam IDLE_BIT = 0; 47 | localparam CALC_BIT = 1; 48 | localparam READY_BIT = 2; 49 | 50 | localparam IDLE = 1 << IDLE_BIT; 51 | localparam CALC = 1 << CALC_BIT; 52 | localparam READY = 1 << READY_BIT; 53 | 54 | localparam NR_STATES = 3; 55 | 56 | (* onehot *) 57 | reg [NR_STATES-1:0] state; 58 | 59 | wire [31:0] rslt_upper_low = (is_mulh | is_mulu | is_mulsu) ? rslt[63:32] : rslt[31:0]; 60 | always @(posedge clk) begin 61 | if (!resetn) begin 62 | state <= IDLE; 63 | ready <= 1'b0; 64 | bit_idx <= 0; 65 | end else begin 66 | 67 | (* parallel_case, full_case *) 68 | case (1'b1) 69 | 70 | state[IDLE_BIT]: begin 71 | ready <= 1'b0; 72 | if (!ready && valid) begin 73 | factor1_abs <= (factor1_is_signed & factor1[31]) ? ~factor1 + 1 : factor1; 74 | factor2_abs <= (factor2_is_signed & factor2[31]) ? ~factor2 + 1 : factor2; 75 | bit_idx <= 0; 76 | rslt <= 0; 77 | state <= CALC; 78 | end 79 | end 80 | 81 | state[CALC_BIT]: begin 82 | `ifndef FAKE_MULTIPLIER 83 | /* verilator lint_off WIDTH */ 84 | rslt <= rslt + ((factor1_abs & {32{factor2_abs[bit_idx]}}) << bit_idx); 85 | /* verilator lint_on WIDTH */ 86 | bit_idx <= bit_idx + 1'b1; 87 | if (&bit_idx) begin 88 | state <= READY; 89 | end 90 | `else 91 | rslt <= factor1_abs * factor2_abs; 92 | state <= READY; 93 | `endif 94 | end 95 | 96 | state[READY_BIT]: begin 97 | /* verilator lint_off WIDTH */ 98 | rslt <= ((factor1[31] & factor1_is_signed ^ factor2[31] & factor2_is_signed)) ? ~rslt + 1 : rslt; 99 | /* verilator lint_on WIDTH */ 100 | 101 | ready <= 1'b1; 102 | state <= IDLE; 103 | end 104 | 105 | endcase 106 | 107 | end 108 | 109 | end 110 | 111 | assign product = rslt_upper_low; 112 | 113 | endmodule 114 | -------------------------------------------------------------------------------- /Hardware/KianV-Icestudio/Level-00/multiplier_decoder.v: -------------------------------------------------------------------------------- 1 | /* 2 | * kianv harris multicycle RISC-V rv32im 3 | * 4 | * copyright (c) 2022 hirosh dabui 5 | * 6 | * permission to use, copy, modify, and/or distribute this software for any 7 | * purpose with or without fee is hereby granted, provided that the above 8 | * copyright notice and this permission notice appear in all copies. 9 | * 10 | * the software is provided "as is" and the author disclaims all warranties 11 | * with regard to this software including all implied warranties of 12 | * merchantability and fitness. in no event shall the author be liable for 13 | * any special, direct, indirect, or consequential damages or any damages 14 | * whatsoever resulting from loss of use, data or profits, whether in an 15 | * action of contract, negligence or other tortious action, arising out of 16 | * or in connection with the use or performance of this software. 17 | * 18 | */ 19 | `default_nettype none `timescale 1 ns / 100 ps 20 | `include "riscv_defines.vh" 21 | module multiplier_decoder ( 22 | input wire [ 2:0] funct3, 23 | output reg [`MUL_OP_WIDTH -1:0] MULop, 24 | input wire mul_ext_valid, 25 | output wire mul_valid 26 | ); 27 | 28 | wire is_mul = funct3 == 3'b000; 29 | wire is_mulh = funct3 == 3'b001; 30 | wire is_mulsu = funct3 == 3'b010; 31 | wire is_mulu = funct3 == 3'b011; 32 | reg valid; 33 | 34 | assign mul_valid = valid & mul_ext_valid; 35 | always @(*) begin 36 | valid = 1'b1; 37 | case (1'b1) 38 | is_mul: MULop = `MUL_OP_MUL; 39 | is_mulh: MULop = `MUL_OP_MULH; 40 | is_mulsu: MULop = `MUL_OP_MULSU; 41 | is_mulu: MULop = `MUL_OP_MULU; 42 | default: begin 43 | /* verilator lint_off WIDTH */ 44 | MULop = 'hxx; 45 | /* verilator lint_on WIDTH */ 46 | valid = 1'b0; 47 | end 48 | endcase 49 | end 50 | 51 | endmodule 52 | -------------------------------------------------------------------------------- /Hardware/KianV-Icestudio/Level-00/multiplier_extension_decoder.v: -------------------------------------------------------------------------------- 1 | /* 2 | * kianv harris multicycle RISC-V rv32im 3 | * 4 | * copyright (c) 2022 hirosh dabui 5 | * 6 | * permission to use, copy, modify, and/or distribute this software for any 7 | * purpose with or without fee is hereby granted, provided that the above 8 | * copyright notice and this permission notice appear in all copies. 9 | * 10 | * the software is provided "as is" and the author disclaims all warranties 11 | * with regard to this software including all implied warranties of 12 | * merchantability and fitness. in no event shall the author be liable for 13 | * any special, direct, indirect, or consequential damages or any damages 14 | * whatsoever resulting from loss of use, data or profits, whether in an 15 | * action of contract, negligence or other tortious action, arising out of 16 | * or in connection with the use or performance of this software. 17 | * 18 | */ 19 | `default_nettype none `timescale 1 ns / 100 ps 20 | `include "riscv_defines.vh" 21 | module multiplier_extension_decoder ( 22 | input wire [ 2:0] funct3, 23 | output wire [`MUL_OP_WIDTH -1:0] MULop, 24 | output wire [`DIV_OP_WIDTH -1:0] DIVop, 25 | input wire mul_ext_valid, 26 | output wire mul_valid, 27 | output wire div_valid 28 | ); 29 | 30 | multiplier_decoder multiplier_I ( 31 | funct3, 32 | MULop, 33 | mul_ext_valid, 34 | mul_valid 35 | ); 36 | divider_decoder divider_decoder_I ( 37 | funct3, 38 | DIVop, 39 | mul_ext_valid, 40 | div_valid 41 | ); 42 | 43 | endmodule 44 | -------------------------------------------------------------------------------- /Hardware/KianV-Icestudio/Level-00/register_file.v: -------------------------------------------------------------------------------- 1 | /* 2 | * kianv harris multicycle RISC-V rv32ima 3 | * 4 | * copyright (c) 2023 hirosh dabui 5 | * 6 | * permission to use, copy, modify, and/or distribute this software for any 7 | * purpose with or without fee is hereby granted, provided that the above 8 | * copyright notice and this permission notice appear in all copies. 9 | * 10 | * the software is provided "as is" and the author disclaims all warranties 11 | * with regard to this software including all implied warranties of 12 | * merchantability and fitness. in no event shall the author be liable for 13 | * any special, direct, indirect, or consequential damages or any damages 14 | * whatsoever resulting from loss of use, data or profits, whether in an 15 | * action of contract, negligence or other tortious action, arising out of 16 | * or in connection with the use or performance of this software. 17 | * 18 | */ 19 | `default_nettype none `timescale 1 ns / 100 ps 20 | 21 | module register_file #( 22 | parameter REGISTER_DEPTH = 32, // rv32e = 16; rv32i = 32 23 | parameter STACKADDR = 32'hffff_ffff 24 | ) ( 25 | input wire clk, 26 | input wire we, 27 | input wire [ 4:0] A1, 28 | input wire [ 4:0] A2, 29 | input wire [ 4:0] A3, 30 | input wire [31:0] wd, 31 | output wire [31:0] rd1, 32 | output wire [31:0] rd2 33 | ); 34 | reg [31:0] bank0[0:REGISTER_DEPTH -1]; 35 | integer i; 36 | 37 | localparam X2 = 2; 38 | initial begin 39 | bank0[10] = 'h00; // hartid 40 | bank0[11] = 32'h80_000_000 + ((1024*1024*32)-2048);// 32'h81fffa00; // dtb 41 | end 42 | 43 | 44 | always @(posedge clk) begin 45 | 46 | if (we && A3 != 0) begin 47 | bank0[A3] <= wd; 48 | end 49 | end 50 | 51 | assign rd1 = A1 != 0 ? bank0[A1] : 32'b0; 52 | assign rd2 = A2 != 0 ? bank0[A2] : 32'b0; 53 | 54 | endmodule 55 | -------------------------------------------------------------------------------- /Hardware/KianV-Icestudio/Level-00/riscv_priv_csr_status.vh: -------------------------------------------------------------------------------- 1 | /* 2 | * kianv harris multicycle RISC-V rv32im 3 | * 4 | * copyright (c) 2023 hirosh dabui 5 | * 6 | * permission to use, copy, modify, and/or distribute this software for any 7 | * purpose with or without fee is hereby granted, provided that the above 8 | * copyright notice and this permission notice appear in all copies. 9 | * 10 | * the software is provided "as is" and the author disclaims all warranties 11 | * with regard to this software including all implied warranties of 12 | * merchantability and fitness. in no event shall the author be liable for 13 | * any special, direct, indirect, or consequential damages or any damages 14 | * whatsoever resulting from loss of use, data or profits, whether in an 15 | * action of contract, negligence or other tortious action, arising out of 16 | * or in connection with the use or performance of this software. 17 | */ 18 | /* verilog_format: off */ 19 | `ifndef RISCV_PRIV_CSR_STATUS_VH 20 | `define RISCV_PRIV_CSR_STATUS_VH 21 | // RISC-V privilege levels 22 | // M -> Simple embedded systems 23 | // M, U -> Secure embedded systems 24 | // M, S, U -> System running Unix-like operating systems 25 | // RISC-V privilege levels 26 | `define PRIVILEGE_MODE_USER 0 27 | `define PRIVILEGE_MODE_SUPERVISOR 1 28 | `define PRIVILEGE_MODE_RESERVED 2 29 | `define PRIVILEGE_MODE_MACHINE 3 30 | `define IS_USER(privilege) (privilege == `PRIVILEGE_MODE_USER) 31 | `define IS_SUPERVISOR(privilege) (privilege == `PRIVILEGE_MODE_SUPERVISOR) 32 | `define IS_MACHINE(privilege) (privilege == `PRIVILEGE_MODE_MACHINE) 33 | 34 | `define MIP_MTIP_BIT 7 35 | `define MIE_MTIP_BIT 7 36 | 37 | `define MIP_MTIP_MASK (1<< `MIP_MTIP_BIT) 38 | `define MIE_MTIP_MASK (1<< `MIE_MTIP_BIT) 39 | 40 | `define MIP_MSIP_BIT 3 41 | `define MIE_MSIP_BIT 3 42 | 43 | `define MIP_MSIP_MASK (1<< `MIP_MSIP_BIT) 44 | `define MIE_MSIP_MASK (1<< `MIE_MSIP_BIT) 45 | 46 | `define MSTATUS_MPP_BIT 11 47 | `define MSTATUS_MPP_WIDTH 2 48 | `define MSTATUS_MPIE_BIT 7 49 | `define MSTATUS_MIE_BIT 3 50 | `define MSTATUS_MPRV_BIT 17 51 | 52 | `define MSTATUS_MIE_MASK (1 << `MSTATUS_MIE_BIT) 53 | `define MSTATUS_MPIE_MASK (1 << `MSTATUS_MPIE_BIT) 54 | `define MSTATUS_MPP_MASK (((1 << `MSTATUS_MPP_WIDTH) - 1) << `MSTATUS_MPP_BIT) 55 | `define MSTATUS_MPRV_MASK (1 << `MSTATUS_MPRV_BIT) 56 | 57 | `define GET_MIE_MTIP(mie) ((mie >> `MIE_MTIP_BIT) & 1) 58 | `define GET_MIE_MSIP(mie) ((mie >> `MIE_MTIP_BIT) & 1) 59 | 60 | `define GET_MIP_MSIP(mip) ((mip) >> `MIP_MSIP_BIT) & 1'b1 61 | `define GET_MIP_MTIP(mip) ((mip) >> `MIP_MTIP_BIT) & 1'b1 62 | `define SET_MIP_MSIP(mip, value) ((mip) & ~(1 << `MIP_MSIP_BIT)) | ((value) << `MIP_MSIP_BIT) 63 | `define SET_MIP_MTIP(mip, value) ((mip) & ~(1 << `MIP_MTIP_BIT)) | ((value) << `MIP_MTIP_BIT) 64 | `define SET_MIP_MEIP(mip, value) ((mip) & ~(1 << `MIP_MEIP_BIT)) | ((value) << `MIP_MEIP_BIT) 65 | 66 | 67 | `define SET_MSTATUS_MPP(mstatus, new_privilege_mode) ((mstatus) & ~`MSTATUS_MPP_MASK) | (((new_privilege_mode) & 2'b11) << `MSTATUS_MPP_BIT) 68 | `define GET_MSTATUS_MPP(mstatus) ((mstatus) >> `MSTATUS_MPP_BIT) & 2'b11 69 | 70 | `define SET_MSTATUS_MPIE(mstatus, mpi_value) ((mstatus) & ~`MSTATUS_MPIE_MASK) | (((mpi_value) & 1'b1) << `MSTATUS_MPIE_BIT) 71 | `define GET_MSTATUS_MPIE(mstatus) ((mstatus) >> `MSTATUS_MPIE_BIT) & 1'b1 72 | 73 | `define SET_MSTATUS_MIE(mstatus, value) ((mstatus) & ~`MSTATUS_MIE_MASK) | (((value) & 1'b1) << `MSTATUS_MIE_BIT) 74 | `define GET_MSTATUS_MIE(mstatus) ((mstatus) >> `MSTATUS_MIE_BIT) & 1'b1 75 | 76 | `define SET_MSTATUS_MPRV(mstatus, mprv_value) ((mstatus) & ~`MSTATUS_MPRV_MASK) | (((mprv_value) & 1'b1) << `MSTATUS_MPRV_BIT) 77 | `define GET_MSTATUS_MPRV(mstatus) ((mstatus) >> `MSTATUS_MPRV_BIT) & 1'b1 78 | 79 | `define IS_EBREAK(opcode, funct3, funct7, rs1, rs2, rd) ({funct7, rs2, rs1, funct3, rd, opcode} == 32'h00100073) 80 | `define IS_ECALL(opcode, funct3, funct7, rs1, rs2, rd) ({funct7, rs2, rs1, funct3, rd, opcode} == 32'h00000073) 81 | `define IS_MRET(opcode, funct3, funct7, rs1, rs2, rd) ({funct7, rs2, rs1, funct3, rd, opcode} == 32'h30200073) 82 | `define IS_WFI(opcode, funct3, funct7, rs1, rs2, rd) ({funct7, rs2, rs1, funct3, rd, opcode} == 32'h10500073) 83 | 84 | `define IRQ_M_TIMER 7 85 | `include "mcause.vh" 86 | 87 | `endif 88 | /* verilog_format: on */ 89 | -------------------------------------------------------------------------------- /Hardware/KianV-Icestudio/Level-00/rv32_amo_opcodes.vh: -------------------------------------------------------------------------------- 1 | /* 2 | * kianv harris multicycle RISC-V rv32im 3 | * 4 | * copyright (c) 2023 hirosh dabui 5 | * 6 | * permission to use, copy, modify, and/or distribute this software for any 7 | * purpose with or without fee is hereby granted, provided that the above 8 | * copyright notice and this permission notice appear in all copies. 9 | * 10 | * the software is provided "as is" and the author disclaims all warranties 11 | * with regard to this software including all implied warranties of 12 | * merchantability and fitness. in no event shall the author be liable for 13 | * any special, direct, indirect, or consequential damages or any damages 14 | * whatsoever resulting from loss of use, data or profits, whether in an 15 | * action of contract, negligence or other tortious action, arising out of 16 | * or in connection with the use or performance of this software. 17 | */ 18 | `define RV32_AMO_OPCODE 7'h2F 19 | `define RV32_AMO_FUNCT3 3'h2 20 | `define RV32_AMOADD_W 5'h00 21 | `define RV32_AMOSWAP_W 5'h01 22 | `define RV32_LR_W 5'h02 23 | `define RV32_SC_W 5'h03 24 | `define RV32_AMOXOR_W 5'h04 25 | `define RV32_AMOAND_W 5'h0C 26 | `define RV32_AMOOR_W 5'h08 27 | `define RV32_AMOMIN_W 5'h10 28 | `define RV32_AMOMAX_W 5'h14 29 | `define RV32_AMOMINU_W 5'h18 30 | `define RV32_AMOMAXU_W 5'h1c 31 | `define RV32_FENCE_OPCODE 7'b0001111 32 | 33 | /* verilog_format: off */ 34 | `define RV32_IS_AMO_INSTRUCTION(opcode, funct3) (opcode == `RV32_AMO_OPCODE && funct3 == `RV32_AMO_FUNCT3) 35 | `define RV32_IS_AMOADD_W(funct5) (funct5 == `RV32_AMOADD_W) 36 | `define RV32_IS_AMOSWAP_W(funct5) (funct5 == `RV32_AMOSWAP_W) 37 | `define RV32_IS_LR_W(funct5) (funct5 == `RV32_LR_W) 38 | `define RV32_IS_SC_W(funct5) (funct5 == `RV32_SC_W) 39 | `define RV32_IS_AMOXOR_W(funct5) ( funct5 == `RV32_AMOXOR_W) 40 | `define RV32_IS_AMOAND_W(funct5) ( funct5 == `RV32_AMOAND_W) 41 | `define RV32_IS_AMOOR_W(funct5) ( funct5 == `RV32_AMOOR_W) 42 | `define RV32_IS_AMOMIN_W(funct5) ( funct5 == `RV32_AMOMIN_W) 43 | `define RV32_IS_AMOMAX_W(funct5) ( funct5 == `RV32_AMOMAX_W) 44 | `define RV32_IS_AMOMINU_W(funct5) ( funct5 == `RV32_AMOMINU_W) 45 | `define RV32_IS_AMOMAXU_W(funct5) ( funct5 == `RV32_AMOMAXU_W) 46 | `define RV32_IS_FENCE(opcode) ( opcode == `RV32_FENCE_OPCODE) 47 | /* verilog_format: on */ 48 | -------------------------------------------------------------------------------- /Hardware/KianV-Icestudio/Level-00/store_alignment.v: -------------------------------------------------------------------------------- 1 | /* 2 | * kianv harris multicycle RISC-V rv32im 3 | * 4 | * copyright (c) 2022 hirosh dabui 5 | * 6 | * permission to use, copy, modify, and/or distribute this software for any 7 | * purpose with or without fee is hereby granted, provided that the above 8 | * copyright notice and this permission notice appear in all copies. 9 | * 10 | * the software is provided "as is" and the author disclaims all warranties 11 | * with regard to this software including all implied warranties of 12 | * merchantability and fitness. in no event shall the author be liable for 13 | * any special, direct, indirect, or consequential damages or any damages 14 | * whatsoever resulting from loss of use, data or profits, whether in an 15 | * action of contract, negligence or other tortious action, arising out of 16 | * or in connection with the use or performance of this software. 17 | * 18 | */ 19 | `default_nettype none `timescale 1 ns / 100 ps 20 | 21 | `include "riscv_defines.vh" 22 | 23 | module store_alignment ( 24 | input wire [ 1:0] addr, 25 | input wire [`STORE_OP_WIDTH -1:0] STOREop, 26 | input wire [ 31:0] data, 27 | output reg [ 31:0] result, 28 | output reg [ 3:0] wmask, 29 | output reg unaligned_access 30 | ); 31 | 32 | always @* begin 33 | unaligned_access = 1'b0; 34 | wmask = 0; 35 | result = 'hx; 36 | 37 | case (STOREop) 38 | (`STORE_OP_SB): begin 39 | result[7:0] = addr[1:0] == 2'b00 ? data[7:0] : 8'hx; 40 | result[15:8] = addr[1:0] == 2'b01 ? data[7:0] : 8'hx; 41 | result[23:16] = addr[1:0] == 2'b10 ? data[7:0] : 8'hx; 42 | result[31:24] = addr[1:0] == 2'b11 ? data[7:0] : 8'hx; 43 | wmask = addr[1:0] == 2'b00 ? 4'b 0001 : 44 | addr[1:0] == 2'b01 ? 4'b 0010 : 45 | addr[1:0] == 2'b10 ? 4'b 0100 : 4'b 1000; 46 | unaligned_access = 1'b0; 47 | end 48 | (`STORE_OP_SH): begin 49 | result[15:0] = ~addr[1] ? data[15:0] : 16'hx; 50 | result[31:16] = addr[1] ? data[15:0] : 16'hx; 51 | wmask = addr[1] ? 4'b1100 : 4'b0011; 52 | unaligned_access = addr[0]; 53 | end 54 | (`STORE_OP_SW): begin 55 | result = data; 56 | wmask = 4'b1111; 57 | unaligned_access = addr[1:0] != 2'b00; 58 | end 59 | default: begin 60 | result = 'hx; 61 | wmask = 4'b0000; 62 | unaligned_access = 1'b0; 63 | end 64 | endcase 65 | 66 | end 67 | endmodule 68 | -------------------------------------------------------------------------------- /Hardware/KianV-Icestudio/Level-00/store_decoder.v: -------------------------------------------------------------------------------- 1 | /* 2 | * kianv harris multicycle RISC-V rv32im 3 | * 4 | * copyright (c) 2022 hirosh dabui 5 | * 6 | * permission to use, copy, modify, and/or distribute this software for any 7 | * purpose with or without fee is hereby granted, provided that the above 8 | * copyright notice and this permission notice appear in all copies. 9 | * 10 | * the software is provided "as is" and the author disclaims all warranties 11 | * with regard to this software including all implied warranties of 12 | * merchantability and fitness. in no event shall the author be liable for 13 | * any special, direct, indirect, or consequential damages or any damages 14 | * whatsoever resulting from loss of use, data or profits, whether in an 15 | * action of contract, negligence or other tortious action, arising out of 16 | * or in connection with the use or performance of this software. 17 | * 18 | */ 19 | `default_nettype none 20 | `timescale 1 ns/100 ps 21 | `include "riscv_defines.vh" 22 | module store_decoder 23 | ( 24 | input wire [ 2: 0] funct3, 25 | input wire amo_store_op, 26 | output reg [`STORE_OP_WIDTH -1: 0] STOREop 27 | ); 28 | wire is_sb = funct3[1:0] == 2'b 00; 29 | wire is_sh = funct3[1:0] == 2'b 01; 30 | wire is_sw = funct3[1:0] == 2'b 10; 31 | 32 | always @(*) begin 33 | if (!amo_store_op) begin 34 | case (1'b1) 35 | is_sb : STOREop = `STORE_OP_SB; 36 | is_sh : STOREop = `STORE_OP_SH; 37 | is_sw : STOREop = `STORE_OP_SW; 38 | default: 39 | /* verilator lint_off WIDTH */ 40 | STOREop = 'hxx; 41 | /* verilator lint_on WIDTH */ 42 | endcase 43 | end else begin 44 | STOREop = `STORE_OP_SW; 45 | end 46 | end 47 | 48 | endmodule 49 | -------------------------------------------------------------------------------- /Hardware/KianV-Icestudio/Level-01/alu.v: -------------------------------------------------------------------------------- 1 | /* 2 | * kianv harris multicycle RISC-V rv32im 3 | * 4 | * copyright (c) 2022 hirosh dabui 5 | * 6 | * permission to use, copy, modify, and/or distribute this software for any 7 | * purpose with or without fee is hereby granted, provided that the above 8 | * copyright notice and this permission notice appear in all copies. 9 | * 10 | * the software is provided "as is" and the author disclaims all warranties 11 | * with regard to this software including all implied warranties of 12 | * merchantability and fitness. in no event shall the author be liable for 13 | * any special, direct, indirect, or consequential damages or any damages 14 | * whatsoever resulting from loss of use, data or profits, whether in an 15 | * action of contract, negligence or other tortious action, arising out of 16 | * or in connection with the use or performance of this software. 17 | * 18 | */ 19 | `default_nettype none `timescale 1 ns / 100 ps 20 | `include "riscv_defines.vh" 21 | 22 | module alu ( 23 | input wire [ 31:0] a, 24 | input wire [ 31:0] b, 25 | input wire [`ALU_CTRL_WIDTH -1:0] alucontrol, 26 | output reg [ 31:0] result, 27 | output wire zero 28 | ); 29 | 30 | 31 | wire is_beq = alucontrol == `ALU_CTRL_BEQ; 32 | wire is_bne = alucontrol == `ALU_CTRL_BNE; 33 | wire is_blt = alucontrol == `ALU_CTRL_BLT; 34 | wire is_bge = alucontrol == `ALU_CTRL_BGE; 35 | wire is_bltu = alucontrol == `ALU_CTRL_BLTU; 36 | wire is_bgeu = alucontrol == `ALU_CTRL_BGEU; 37 | wire is_slt_slti = alucontrol == `ALU_CTRL_SLT_SLTI; 38 | wire is_sltu_sltiu = alucontrol == `ALU_CTRL_SLTU_SLTIU; 39 | wire is_sub_ctrl = alucontrol == `ALU_CTRL_SUB; 40 | wire is_amo_min_max = alucontrol == `ALU_CTRL_MIN || alucontrol == `ALU_CTRL_MAX || 41 | alucontrol == `ALU_CTRL_MINU || alucontrol == `ALU_CTRL_MAXU; 42 | 43 | wire is_sub = is_sub_ctrl || is_beq || is_bne || is_blt || is_bge || 44 | is_bltu || is_bgeu || is_slt_slti || is_amo_min_max || is_sltu_sltiu; 45 | 46 | 47 | wire [31:0] condinv = is_sub ? ~b : b; 48 | 49 | // seen 33 Bit sum from Bruno's Levy 50 | // with that approach I could map all branch to LT, LTU 51 | wire [32:0] sum = {1'b1, condinv} + {1'b0, a} + {32'b0, is_sub}; 52 | wire LT = (a[31] ^ b[31]) ? a[31] : sum[32]; 53 | wire LTU = sum[32]; 54 | 55 | wire [31:0] sltx_sltux_rslt = {31'b0, is_slt_slti ? LT : LTU}; 56 | wire [63:0] sext_rs1 = {{32{a[31]}}, a}; 57 | wire [63:0] sra_srai_rslt = sext_rs1 >> b[4:0]; 58 | 59 | wire is_sum_zero = sum[31:0] == 32'b0; 60 | 61 | always @* begin 62 | case (alucontrol) 63 | `ALU_CTRL_ADD_ADDI: result = sum[31:0]; 64 | `ALU_CTRL_SUB: result = sum[31:0]; 65 | `ALU_CTRL_XOR_XORI: result = a ^ b; 66 | `ALU_CTRL_OR_ORI: result = a | b; 67 | `ALU_CTRL_AND_ANDI: result = a & b; 68 | `ALU_CTRL_SLL_SLLI: result = a << b[4:0]; 69 | `ALU_CTRL_SRL_SRLI: result = a >> b[4:0]; 70 | `ALU_CTRL_SRA_SRAI: result = sra_srai_rslt[31:0]; 71 | `ALU_CTRL_SLT_SLTI: result = (a[31] == b[31]) ? sltx_sltux_rslt : {31'b0, a[31]}; 72 | `ALU_CTRL_SLTU_SLTIU: result = sltx_sltux_rslt; 73 | `ALU_CTRL_MIN: result = LT ? a : b; 74 | `ALU_CTRL_MAX: result = !LT ? a : b; 75 | `ALU_CTRL_MINU: result = LTU ? a : b; 76 | `ALU_CTRL_MAXU: result = !LTU ? a : b; 77 | `ALU_CTRL_LUI: result = b; 78 | `ALU_CTRL_AUIPC: result = sum[31:0]; 79 | default: begin 80 | case (1'b1) 81 | is_beq: result = {31'b0, is_sum_zero}; 82 | is_bne: result = {31'b0, !is_sum_zero}; 83 | is_blt: result = {31'b0, LT}; 84 | is_bge: result = {31'b0, !LT}; 85 | is_bltu: result = {31'b0, LTU}; 86 | is_bgeu: result = {31'b0, !LTU}; 87 | default: result = 32'b0; 88 | endcase 89 | end 90 | endcase 91 | end 92 | 93 | assign zero = result == 32'b0; 94 | endmodule 95 | -------------------------------------------------------------------------------- /Hardware/KianV-Icestudio/Level-01/bram.v: -------------------------------------------------------------------------------- 1 | /* 2 | * kianv.v - a simple RISC-V rv32i 3 | * 4 | * copyright (c) 2022 hirosh dabui 5 | * 6 | * permission to use, copy, modify, and/or distribute this software for any 7 | * purpose with or without fee is hereby granted, provided that the above 8 | * copyright notice and this permission notice appear in all copies. 9 | * 10 | * the software is provided "as is" and the author disclaims all warranties 11 | * with regard to this software including all implied warranties of 12 | * merchantability and fitness. in no event shall the author be liable for 13 | * any special, direct, indirect, or consequential damages or any damages 14 | * whatsoever resulting from loss of use, data or profits, whether in an 15 | * action of contract, negligence or other tortious action, arising out of 16 | * or in connection with the use or performance of this software. 17 | * 18 | */ 19 | `default_nettype none `timescale 1 ns / 100 ps 20 | module bram #( 21 | parameter integer WIDTH = 8, 22 | parameter INIT_FILE = "", 23 | parameter SHOW_FIRMWARE = 0 24 | ) ( 25 | input wire clk, 26 | input wire [WIDTH -1:0] addr, 27 | input wire [31:0] wdata, 28 | output reg [31:0] rdata, 29 | input wire [3:0] wmask 30 | ); 31 | reg [31:0] mem[0:(1< 5 | * 6 | * permission to use, copy, modify, and/or distribute this software for any 7 | * purpose with or without fee is hereby granted, provided that the above 8 | * copyright notice and this permission notice appear in all copies. 9 | * 10 | * the software is provided "as is" and the author disclaims all warranties 11 | * with regard to this software including all implied warranties of 12 | * merchantability and fitness. in no event shall the author be liable for 13 | * any special, direct, indirect, or consequential damages or any damages 14 | * whatsoever resulting from loss of use, data or profits, whether in an 15 | * action of contract, negligence or other tortious action, arising out of 16 | * or in connection with the use or performance of this software. 17 | * 18 | */ 19 | `default_nettype none `timescale 1 ns / 100 ps 20 | module clint #( 21 | parameter SYSTEM_CLK = 25_000_000, 22 | parameter CLOCK_TICK = 1000 23 | ) ( 24 | input wire clk, 25 | input wire resetn, 26 | input wire valid, 27 | input wire [31:0] addr, 28 | input wire [3:0] wmask, 29 | input wire [31:0] wdata, 30 | output reg [31:0] rdata, 31 | output wire is_valid, 32 | output reg ready, 33 | output wire IRQ3, 34 | output wire IRQ7 35 | ); 36 | 37 | /* verilator lint_off WIDTHTRUNC */ 38 | localparam CLOCK_TICK_BIT_WIDTH = $clog2(CLOCK_TICK); 39 | localparam [CLOCK_TICK_BIT_WIDTH -1:0] CYCLES_TO_TICK = ($rtoi(SYSTEM_CLK / CLOCK_TICK)); 40 | /* verilator lint_on WIDTHTRUNC */ 41 | wire is_msip = (addr == 32'h1100_0000); 42 | wire is_mtimecmpl = (addr == 32'h1100_4000); 43 | wire is_mtimecmph = (addr == 32'h1100_4004); 44 | wire is_mtimeh = (addr == 32'h1100_bffc); 45 | wire is_mtimel = (addr == 32'h1100_bff8); 46 | 47 | assign is_valid = valid && (is_msip || is_mtimecmpl || is_mtimecmph || is_mtimel || is_mtimeh); 48 | always @(posedge clk) ready <= !resetn ? 1'b0 : is_valid; 49 | 50 | reg [63:0] mtime; 51 | always @(posedge clk) mtime <= !resetn ? 0 : (tick) ? mtime + 1 : mtime; 52 | 53 | wire is_we = |wmask; 54 | 55 | reg [63:0] mtimecmp; 56 | reg msip; 57 | 58 | always @(posedge clk) 59 | if (!resetn) begin 60 | mtimecmp <= 0; 61 | msip <= 0; 62 | end else if (is_mtimecmpl && is_valid) begin 63 | if (wmask[0]) mtimecmp[7:0] <= wdata[7:0]; 64 | if (wmask[1]) mtimecmp[15:8] <= wdata[15:8]; 65 | if (wmask[2]) mtimecmp[23:16] <= wdata[23:16]; 66 | if (wmask[3]) mtimecmp[31:24] <= wdata[31:24]; 67 | end else if (is_mtimecmph && is_valid) begin 68 | if (wmask[0]) mtimecmp[39:32] <= wdata[7:0]; 69 | if (wmask[1]) mtimecmp[47:40] <= wdata[15:8]; 70 | if (wmask[2]) mtimecmp[55:48] <= wdata[23:16]; 71 | if (wmask[3]) mtimecmp[63:56] <= wdata[31:24]; 72 | end else if (is_msip && is_valid) begin 73 | if (wmask[0]) msip <= wdata[0]; 74 | end 75 | 76 | always @(*) begin 77 | case (1'b1) 78 | is_mtimecmpl: rdata = mtimecmp[31:0]; 79 | is_mtimecmph: rdata = mtimecmp[63:32]; 80 | is_mtimel: rdata = mtime[31:0]; 81 | is_mtimeh: rdata = mtime[63:32]; 82 | is_msip: rdata = {31'b0, msip}; 83 | default: rdata = 0; 84 | endcase 85 | end 86 | 87 | 88 | reg [CLOCK_TICK_BIT_WIDTH -1:0] tick_cnt; 89 | wire tick = tick_cnt == (CYCLES_TO_TICK - 1); 90 | always @(posedge clk) begin 91 | if (!resetn) begin 92 | tick_cnt <= 0; 93 | end else begin 94 | if (tick) begin 95 | tick_cnt <= 0; 96 | end else begin 97 | tick_cnt <= tick_cnt + 1; 98 | end 99 | end 100 | end 101 | 102 | assign IRQ3 = msip; 103 | assign IRQ7 = (mtime >= mtimecmp); 104 | 105 | endmodule 106 | 107 | -------------------------------------------------------------------------------- /Hardware/KianV-Icestudio/Level-01/csr_utilities.vh: -------------------------------------------------------------------------------- 1 | /* 2 | * kianv.v - RISC-V rv32ima 3 | * 4 | * copyright (c) 2023 hirosh dabui 5 | * 6 | * permission to use, copy, modify, and/or distribute this software for any 7 | * purpose with or without fee is hereby granted, provided that the above 8 | * copyright notice and this permission notice appear in all copies. 9 | * 10 | * the software is provided "as is" and the author disclaims all warranties 11 | * with regard to this software including all implied warranties of 12 | * merchantability and fitness. in no event shall the author be liable for 13 | * any special, direct, indirect, or consequential damages or any damages 14 | * whatsoever resulting from loss of use, data or profits, whether in an 15 | * action of contract, negligence or other tortious action, arising out of 16 | * or in connection with the use or performance of this software. 17 | * 18 | */ 19 | `ifndef CSR_UTILITIES_VH 20 | `define CSR_UTILITIES_VH 21 | 22 | // Unprivileged Counter/Timers 23 | `define CSR_REG_CYCLE 12'h C00 24 | `define CSR_REG_CYCLEH 12'h C80 25 | `define CSR_REG_INSTRET 12'h C02 26 | `define CSR_REG_INSTRETH 12'h C82 27 | `define CSR_REG_TIME 12'h C01 28 | `define CSR_REG_TIMEH 12'h C81 29 | 30 | // Machine Trap Setup 31 | `define CSR_REG_MSTATUS 12'h 300 32 | `define CSR_REG_MISA 12'h 301 33 | `define CSR_REG_MIE 12'h 304 34 | `define CSR_REG_MTVEC 12'h 305 35 | 36 | // Machine Trap Handling 37 | `define CSR_REG_MSCRATCH 12'h 340 38 | `define CSR_REG_MEPC 12'h 341 39 | `define CSR_REG_MCAUSE 12'h 342 40 | `define CSR_REG_MTVAL 12'h 343 41 | `define CSR_REG_MIP 12'h 344 42 | 43 | `define CSR_REG_MCOUNTEREN 12'h 306 44 | 45 | `define CSR_REG_MHARTID 12'h f14 46 | `define CSR_REG_MVENDORID 12'h f11 47 | 48 | // Machine-Level CSRs 49 | // custrom read-only 50 | `define CSR_PRIVILEGE_MODE 12'h fc0 // machine privilege mode 51 | 52 | 53 | // RISC-V CSR instruction opcodes (7-bit) and funct3 (3-bit) 54 | `define CSR_OPCODE `SYSTEM_OPCODE 55 | `define CSR_FUNCT3_RW 3'b001 56 | `define CSR_FUNCT3_RS 3'b010 57 | `define CSR_FUNCT3_RC 3'b011 58 | `define CSR_FUNCT3_RWI 3'b101 59 | `define CSR_FUNCT3_RSI 3'b110 60 | `define CSR_FUNCT3_RCI 3'b111 61 | 62 | `include "riscv_priv_csr_status.vh" 63 | `include "misa.vh" 64 | `endif 65 | -------------------------------------------------------------------------------- /Hardware/KianV-Icestudio/Level-01/design_elements.v: -------------------------------------------------------------------------------- 1 | /* 2 | * kianv harris multicycle RISC-V rv32im 3 | * 4 | * copyright (c) 2022/23 hirosh dabui 5 | * 6 | * permission to use, copy, modify, and/or distribute this software for any 7 | * purpose with or without fee is hereby granted, provided that the above 8 | * copyright notice and this permission notice appear in all copies. 9 | * 10 | * the software is provided "as is" and the author disclaims all warranties 11 | * with regard to this software including all implied warranties of 12 | * merchantability and fitness. in no event shall the author be liable for 13 | * any special, direct, indirect, or consequential damages or any damages 14 | * whatsoever resulting from loss of use, data or profits, whether in an 15 | * action of contract, negligence or other tortious action, arising out of 16 | * or in connection with the use or performance of this software. 17 | * 18 | */ 19 | `default_nettype none `timescale 1 ns / 100 ps 20 | /* verilator lint_off MULTITOP */ 21 | 22 | module mux2 #( 23 | parameter WIDTH = 32 24 | ) ( 25 | input wire [WIDTH -1:0] d0, 26 | d1, 27 | input wire s, 28 | output wire [WIDTH -1:0] y 29 | ); 30 | 31 | assign y = s ? d1 : d0; 32 | endmodule 33 | 34 | module mux3 #( 35 | parameter WIDTH = 32 36 | ) ( 37 | input wire [WIDTH -1:0] d0, 38 | d1, 39 | d2, 40 | input wire [ 1:0] s, 41 | output wire [WIDTH -1:0] y 42 | ); 43 | 44 | assign y = s[1] ? d2 : (s[0] ? d1 : d0); 45 | endmodule 46 | 47 | module mux4 #( 48 | parameter WIDTH = 32 49 | ) ( 50 | input wire [WIDTH -1:0] d0, 51 | d1, 52 | d2, 53 | d3, 54 | input wire [ 1:0] s, 55 | output wire [WIDTH -1:0] y 56 | ); 57 | 58 | wire [WIDTH -1:0] low, high; 59 | 60 | mux2 lowmux ( 61 | d0, 62 | d1, 63 | s[0], 64 | low 65 | ); 66 | mux2 highmux ( 67 | d2, 68 | d3, 69 | s[0], 70 | high 71 | ); 72 | mux2 finalmux ( 73 | low, 74 | high, 75 | s[1], 76 | y 77 | ); 78 | endmodule 79 | 80 | module mux5 #( 81 | parameter WIDTH = 32 82 | ) ( 83 | input wire [WIDTH -1:0] d0, 84 | d1, 85 | d2, 86 | d3, 87 | d4, 88 | input wire [ 2:0] s, 89 | output wire [WIDTH -1:0] y 90 | 91 | ); 92 | 93 | assign y = (s == 0) ? d0 : (s == 1) ? d1 : (s == 2) ? d2 : (s == 3) ? d3 : d4; 94 | 95 | endmodule 96 | 97 | module mux6 #( 98 | parameter WIDTH = 32 99 | ) ( 100 | input wire [WIDTH -1:0] d0, 101 | d1, 102 | d2, 103 | d3, 104 | d4, 105 | d5, 106 | input wire [ 2:0] s, 107 | output wire [WIDTH -1:0] y 108 | 109 | ); 110 | 111 | assign y = (s == 0) ? d0 : (s == 1) ? d1 : (s == 2) ? d2 : (s == 3) ? d3 : (s == 4) ? d4 : d5; 112 | 113 | endmodule 114 | 115 | module dlatch #( 116 | parameter WIDTH = 32 117 | ) ( 118 | input wire clk, 119 | input wire [WIDTH -1:0] d, 120 | output reg [WIDTH -1:0] q 121 | ); 122 | always @(posedge clk) q <= d; 123 | endmodule 124 | 125 | module dff #( 126 | parameter WIDTH = 32, 127 | parameter PRESET = 0 128 | ) ( 129 | input wire resetn, 130 | input wire clk, 131 | input wire en, 132 | input wire [WIDTH -1:0] d, 133 | output reg [WIDTH -1:0] q 134 | ); 135 | always @(posedge clk) 136 | if (!resetn) q <= PRESET; 137 | else if (en) q <= d; 138 | 139 | endmodule 140 | module counter #( 141 | parameter WIDTH = 32 142 | ) ( 143 | input wire resetn, 144 | input wire clk, 145 | input wire inc, 146 | output reg [WIDTH -1:0] q 147 | ); 148 | always @(posedge clk) 149 | if (!resetn) q <= 0; 150 | else if (inc) q <= q + 1; 151 | 152 | endmodule 153 | /* verilator lint_on MULTITOP */ 154 | -------------------------------------------------------------------------------- /Hardware/KianV-Icestudio/Level-01/divider_decoder.v: -------------------------------------------------------------------------------- 1 | /* 2 | * kianv harris multicycle RISC-V rv32im 3 | * 4 | * copyright (c) 2022 hirosh dabui 5 | * 6 | * permission to use, copy, modify, and/or distribute this software for any 7 | * purpose with or without fee is hereby granted, provided that the above 8 | * copyright notice and this permission notice appear in all copies. 9 | * 10 | * the software is provided "as is" and the author disclaims all warranties 11 | * with regard to this software including all implied warranties of 12 | * merchantability and fitness. in no event shall the author be liable for 13 | * any special, direct, indirect, or consequential damages or any damages 14 | * whatsoever resulting from loss of use, data or profits, whether in an 15 | * action of contract, negligence or other tortious action, arising out of 16 | * or in connection with the use or performance of this software. 17 | * 18 | */ 19 | `default_nettype none `timescale 1 ns / 100 ps 20 | `include "riscv_defines.vh" 21 | module divider_decoder ( 22 | input wire [ 2:0] funct3, 23 | output reg [`DIV_OP_WIDTH -1:0] DIVop, 24 | input wire mul_ext_valid, 25 | output wire div_valid 26 | ); 27 | 28 | wire is_div = funct3 == 3'b100; 29 | wire is_divu = funct3 == 3'b101; 30 | wire is_rem = funct3 == 3'b110; 31 | wire is_remu = funct3 == 3'b111; 32 | reg valid; 33 | 34 | assign div_valid = valid & mul_ext_valid; 35 | 36 | always @(*) begin 37 | valid = 1'b1; 38 | case (1'b1) 39 | is_div: DIVop = `DIV_OP_DIV; 40 | is_divu: DIVop = `DIV_OP_DIVU; 41 | is_rem: DIVop = `DIV_OP_REM; 42 | is_remu: DIVop = `DIV_OP_REMU; 43 | default: begin 44 | /* verilator lint_off WIDTH */ 45 | DIVop = 'hxx; 46 | /* verilator lint_on WIDTH */ 47 | valid = 1'b0; 48 | end 49 | endcase 50 | end 51 | 52 | endmodule 53 | -------------------------------------------------------------------------------- /Hardware/KianV-Icestudio/Level-01/extend.v: -------------------------------------------------------------------------------- 1 | /* 2 | * kianv harris multicycle RISC-V rv32im 3 | * 4 | * copyright (c) 2022 hirosh dabui 5 | * 6 | * permission to use, copy, modify, and/or distribute this software for any 7 | * purpose with or without fee is hereby granted, provided that the above 8 | * copyright notice and this permission notice appear in all copies. 9 | * 10 | * the software is provided "as is" and the author disclaims all warranties 11 | * with regard to this software including all implied warranties of 12 | * merchantability and fitness. in no event shall the author be liable for 13 | * any special, direct, indirect, or consequential damages or any damages 14 | * whatsoever resulting from loss of use, data or profits, whether in an 15 | * action of contract, negligence or other tortious action, arising out of 16 | * or in connection with the use or performance of this software. 17 | * 18 | */ 19 | `default_nettype none `timescale 1 ns / 100 ps 20 | `include "riscv_defines.vh" 21 | module extend ( 22 | input wire [31:7] instr, 23 | input wire [ 2:0] immsrc, 24 | output reg [31:0] immext 25 | ); 26 | 27 | always @(*) begin 28 | case (immsrc) 29 | `IMMSRC_ITYPE: immext = {{20{instr[31]}}, instr[31:20]}; 30 | `IMMSRC_STYPE: immext = {{20{instr[31]}}, instr[31:25], instr[11:7]}; 31 | `IMMSRC_BTYPE: immext = {{20{instr[31]}}, instr[7:7], instr[30:25], instr[11:8], 1'b0}; 32 | `IMMSRC_JTYPE: immext = {{12{instr[31]}}, instr[19:12], instr[20], instr[30:21], 1'b0}; 33 | `IMMSRC_UTYPE: immext = {instr[31:12], 12'b0}; 34 | default: immext = 32'b0; 35 | endcase 36 | end 37 | endmodule 38 | -------------------------------------------------------------------------------- /Hardware/KianV-Icestudio/Level-01/fifo.v: -------------------------------------------------------------------------------- 1 | /* 2 | * fifo.v 3 | * 4 | * copyright (c) 2021 hirosh dabui 5 | * 6 | * permission to use, copy, modify, and/or distribute this software for any 7 | * purpose with or without fee is hereby granted, provided that the above 8 | * copyright notice and this permission notice appear in all copies. 9 | * 10 | * the software is provided "as is" and the author disclaims all warranties 11 | * with regard to this software including all implied warranties of 12 | * merchantability and fitness. in no event shall the author be liable for 13 | * any special, direct, indirect, or consequential damages or any damages 14 | * whatsoever resulting from loss of use, data or profits, whether in an 15 | * action of contract, negligence or other tortious action, arising out of 16 | * or in connection with the use or performance of this software. 17 | * 18 | */ 19 | 20 | `default_nettype none `timescale 1 ns / 100 ps 21 | module fifo #( 22 | parameter DATA_WIDTH = 8, 23 | parameter DEPTH = 4 24 | ) ( 25 | input wire clk, 26 | input wire resetn, 27 | input wire [DATA_WIDTH-1:0] din, 28 | output wire [DATA_WIDTH-1:0] dout, 29 | input wire push, 30 | input wire pop, 31 | output wire full, 32 | output wire empty 33 | ); 34 | 35 | reg [DATA_WIDTH-1:0] ram[0:DEPTH-1]; 36 | 37 | reg [$clog2(DEPTH):0] cnt; 38 | reg [$clog2(DEPTH)-1:0] rd_ptr; 39 | reg [$clog2(DEPTH)-1:0] wr_ptr; 40 | 41 | reg [$clog2(DEPTH):0] cnt_next; 42 | reg [$clog2(DEPTH)-1:0] rd_ptr_next; 43 | reg [$clog2(DEPTH)-1:0] wr_ptr_next; 44 | 45 | assign empty = cnt == 0; 46 | assign full = cnt == DEPTH; 47 | 48 | always @(posedge clk) begin 49 | if (~resetn) begin 50 | rd_ptr <= 0; 51 | wr_ptr <= 0; 52 | cnt <= 0; 53 | end else begin 54 | rd_ptr <= rd_ptr_next; 55 | wr_ptr <= wr_ptr_next; 56 | cnt <= cnt_next; 57 | end 58 | end 59 | 60 | always @(*) begin 61 | rd_ptr_next = rd_ptr; 62 | wr_ptr_next = wr_ptr; 63 | cnt_next = cnt; 64 | 65 | if (push) begin 66 | wr_ptr_next = wr_ptr + 1; 67 | cnt_next = (!pop || empty) ? cnt + 1 : cnt_next; 68 | end 69 | 70 | if (pop) begin 71 | rd_ptr_next = rd_ptr + 1; 72 | cnt_next = (!push || full) ? cnt - 1 : cnt_next; 73 | end 74 | 75 | end 76 | 77 | always @(posedge clk) begin 78 | if (push) ram[wr_ptr] <= din; 79 | end 80 | 81 | assign dout = ram[rd_ptr]; 82 | 83 | endmodule 84 | -------------------------------------------------------------------------------- /Hardware/KianV-Icestudio/Level-01/flash.sh: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | 3 | apio raw "fujprog -l 4 -j FLASH ice-build/Linux-soc-KianV-00/hardware.bit" -------------------------------------------------------------------------------- /Hardware/KianV-Icestudio/Level-01/load_alignment.v: -------------------------------------------------------------------------------- 1 | /* 2 | * kianv harris multicycle RISC-V rv32ima 3 | * 4 | * copyright (c) 2023 hirosh dabui 5 | * 6 | * permission to use, copy, modify, and/or distribute this software for any 7 | * purpose with or without fee is hereby granted, provided that the above 8 | * copyright notice and this permission notice appear in all copies. 9 | * 10 | * the software is provided "as is" and the author disclaims all warranties 11 | * with regard to this software including all implied warranties of 12 | * merchantability and fitness. in no event shall the author be liable for 13 | * any special, direct, indirect, or consequential damages or any damages 14 | * whatsoever resulting from loss of use, data or profits, whether in an 15 | * action of contract, negligence or other tortious action, arising out of 16 | * or in connection with the use or performance of this software. 17 | * 18 | */ 19 | `default_nettype none `timescale 1 ns / 100 ps 20 | `include "riscv_defines.vh" 21 | module load_alignment ( 22 | input wire [ 1:0] addr, 23 | input wire [`LOAD_OP_WIDTH -1:0] LOADop, 24 | input wire [ 31:0] data, 25 | output reg [ 31:0] result, 26 | output reg unaligned_access 27 | ); 28 | 29 | wire is_lb = `LOAD_OP_LB == LOADop; 30 | wire is_lbu = `LOAD_OP_LBU == LOADop; 31 | 32 | wire is_lh = `LOAD_OP_LH == LOADop; 33 | wire is_lhu = `LOAD_OP_LHU == LOADop; 34 | 35 | wire is_lw = `LOAD_OP_LW == LOADop; 36 | 37 | always @* begin 38 | result = 'hx; 39 | unaligned_access = 1'b0; 40 | if (is_lb | is_lbu) begin 41 | result[7:0] = 42 | addr[1:0] == 2'b00 ? data[7 :0] : 43 | addr[1:0] == 2'b01 ? data[15 :8] : 44 | addr[1:0] == 2'b10 ? data[23:16] : 45 | addr[1:0] == 2'b11 ? data[31:24] : 8'hx; 46 | result = {is_lbu ? 24'b0 : {24{result[7]}}, result[7:0]}; 47 | unaligned_access = 1'b0; 48 | end 49 | 50 | if (is_lh | is_lhu) begin 51 | result[15:0] = ~addr[1] ? data[15 : 0] : addr[1] ? data[31 : 16] : 16'hx; 52 | result = {is_lhu ? 16'b0 : {16{result[15]}}, result[15:0]}; 53 | unaligned_access = addr[0]; 54 | end 55 | 56 | if (is_lw) begin 57 | result = data; 58 | unaligned_access = addr[1:0] != 2'b00; 59 | end 60 | end 61 | 62 | endmodule 63 | -------------------------------------------------------------------------------- /Hardware/KianV-Icestudio/Level-01/load_decoder.v: -------------------------------------------------------------------------------- 1 | /* 2 | * kianv harris multicycle RISC-V rv32im 3 | * 4 | * copyright (c) 2022 hirosh dabui 5 | * 6 | * permission to use, copy, modify, and/or distribute this software for any 7 | * purpose with or without fee is hereby granted, provided that the above 8 | * copyright notice and this permission notice appear in all copies. 9 | * 10 | * the software is provided "as is" and the author disclaims all warranties 11 | * with regard to this software including all implied warranties of 12 | * merchantability and fitness. in no event shall the author be liable for 13 | * any special, direct, indirect, or consequential damages or any damages 14 | * whatsoever resulting from loss of use, data or profits, whether in an 15 | * action of contract, negligence or other tortious action, arising out of 16 | * or in connection with the use or performance of this software. 17 | * 18 | */ 19 | `default_nettype none 20 | `timescale 1 ns/100 ps 21 | `include "riscv_defines.vh" 22 | module load_decoder 23 | ( 24 | input wire [ 2: 0] funct3, 25 | input wire amo_load, 26 | output reg [`LOAD_OP_WIDTH -1: 0] LOADop 27 | ); 28 | wire is_lb = funct3 == 3'b 000; 29 | wire is_lh = funct3 == 3'b 001; 30 | wire is_lw = funct3 == 3'b 010; 31 | wire is_lbu = funct3 == 3'b 100; 32 | wire is_lhu = funct3 == 3'b 101; 33 | 34 | always @(*) begin 35 | if (!amo_load) begin 36 | case (1'b1) 37 | is_lb : LOADop = `LOAD_OP_LB; 38 | is_lh : LOADop = `LOAD_OP_LH; 39 | is_lw : LOADop = `LOAD_OP_LW; 40 | is_lbu : LOADop = `LOAD_OP_LBU; 41 | is_lhu : LOADop = `LOAD_OP_LHU; 42 | default: 43 | /* verilator lint_off WIDTH */ 44 | LOADop = 'hxx; 45 | /* verilator lint_on WIDTH */ 46 | endcase 47 | end else begin 48 | LOADop = `LOAD_OP_LW; 49 | end 50 | end 51 | 52 | endmodule 53 | -------------------------------------------------------------------------------- /Hardware/KianV-Icestudio/Level-01/mcause.vh: -------------------------------------------------------------------------------- 1 | /* 2 | * kianv.v - RISC-V rv32ima 3 | * 4 | * copyright (c) 2023 hirosh dabui 5 | * 6 | * permission to use, copy, modify, and/or distribute this software for any 7 | * purpose with or without fee is hereby granted, provided that the above 8 | * copyright notice and this permission notice appear in all copies. 9 | * 10 | * the software is provided "as is" and the author disclaims all warranties 11 | * with regard to this software including all implied warranties of 12 | * merchantability and fitness. in no event shall the author be liable for 13 | * any special, direct, indirect, or consequential damages or any damages 14 | * whatsoever resulting from loss of use, data or profits, whether in an 15 | * action of contract, negligence or other tortious action, arising out of 16 | * or in connection with the use or performance of this software. 17 | * 18 | */ 19 | `ifndef MCAUSE_VH 20 | `define MCAUSE_VH 21 | // Exception codes 22 | `define EXC_INSTR_ADDR_MISALIGNED 32'h00000000 23 | `define EXC_INSTR_ACCESS_FAULT 32'h00000001 24 | `define EXC_ILLEGAL_INSTRUCTION 32'h00000002 25 | `define EXC_BREAKPOINT 32'h00000003 26 | `define EXC_LOAD_AMO_ADDR_MISALIGNED 32'h00000004 27 | `define EXC_LOAD_AMO_ACCESS_FAULT 32'h00000005 28 | `define EXC_STORE_AMO_ADDR_MISALIGNED 32'h00000006 29 | `define EXC_STORE_AMO_ACCESS_FAULT 32'h00000007 30 | `define EXC_ECALL_FROM_UMODE 32'h00000008 31 | `define EXC_ECALL_FROM_SMODE 32'h00000009 32 | `define EXC_ECALL_FROM_MMODE 32'h0000000B 33 | `define EXC_INSTR_PAGE_FAULT 32'h0000000C 34 | `define EXC_LOAD_PAGE_FAULT 32'h0000000D 35 | `define EXC_STORE_AMO_PAGE_FAULT 32'h0000000F 36 | 37 | // Interrupt codes 38 | `define INTERRUPT_USER_SOFTWARE 32'h80000000 39 | `define INTERRUPT_SUPERVISOR_SOFTWARE 32'h80000001 40 | `define INTERRUPT_MACHINE_SOFTWARE 32'h80000003 41 | `define INTERRUPT_USER_TIMER 32'h80000004 42 | `define INTERRUPT_SUPERVISOR_TIMER 32'h80000005 43 | `define INTERRUPT_MACHINE_TIMER 32'h80000007 44 | `define INTERRUPT_USER_EXTERNAL 32'h80000008 45 | `define INTERRUPT_SUPERVISOR_EXTERNAL 32'h80000009 46 | `define INTERRUPT_MACHINE_EXTERNAL 32'h8000000B 47 | `endif 48 | -------------------------------------------------------------------------------- /Hardware/KianV-Icestudio/Level-01/misa.vh: -------------------------------------------------------------------------------- 1 | /* 2 | * kianv.v - RISC-V rv32ima 3 | * 4 | * copyright (c) 2023 hirosh dabui 5 | * 6 | * permission to use, copy, modify, and/or distribute this software for any 7 | * purpose with or without fee is hereby granted, provided that the above 8 | * copyright notice and this permission notice appear in all copies. 9 | * 10 | * the software is provided "as is" and the author disclaims all warranties 11 | * with regard to this software including all implied warranties of 12 | * merchantability and fitness. in no event shall the author be liable for 13 | * any special, direct, indirect, or consequential damages or any damages 14 | * whatsoever resulting from loss of use, data or profits, whether in an 15 | * action of contract, negligence or other tortious action, arising out of 16 | * or in connection with the use or performance of this software. 17 | * 18 | */ 19 | `ifndef MISA_VH 20 | `define MISA_VH 21 | 22 | `define MISA_MXL_RV32 2'b01 23 | `define MISA_EXTENSION_A 5'd0 24 | `define MISA_EXTENSION_B 5'd1 25 | `define MISA_EXTENSION_C 5'd2 26 | `define MISA_EXTENSION_D 5'd3 27 | `define MISA_EXTENSION_E 5'd4 28 | `define MISA_EXTENSION_F 5'd5 29 | `define MISA_EXTENSION_G 5'd6 30 | `define MISA_EXTENSION_H 5'd7 31 | `define MISA_EXTENSION_I 5'd8 32 | `define MISA_EXTENSION_J 5'd9 33 | `define MISA_EXTENSION_K 5'd10 34 | `define MISA_EXTENSION_L 5'd11 35 | `define MISA_EXTENSION_M 5'd12 36 | `define MISA_EXTENSION_N 5'd13 37 | `define MISA_EXTENSION_O 5'd14 38 | `define MISA_EXTENSION_P 5'd15 39 | `define MISA_EXTENSION_Q 5'd16 40 | `define MISA_EXTENSION_R 5'd17 41 | `define MISA_EXTENSION_S 5'd18 42 | `define MISA_EXTENSION_T 5'd19 43 | `define MISA_EXTENSION_U 5'd20 44 | `define MISA_EXTENSION_V 5'd21 45 | `define MISA_EXTENSION_W 5'd22 46 | `define MISA_EXTENSION_X 5'd23 47 | `define MISA_EXTENSION_Y 5'd24 48 | `define MISA_EXTENSION_Z 5'd25 49 | 50 | `define IS_EXTENSION_SUPPORTED(MXL, Extensions, Ext_To_Check) \ 51 | ((MXL) == `MISA_MXL_RV32) && (((Extensions) >> (Ext_To_Check)) & 1'b1) 52 | `define SET_MISA_VALUE(MXL) (MXL << 30) 53 | `define MISA_EXTENSION_BIT(extension) (1 << extension) 54 | 55 | `endif 56 | -------------------------------------------------------------------------------- /Hardware/KianV-Icestudio/Level-01/multiplier.v: -------------------------------------------------------------------------------- 1 | /* 2 | * kianv harris multicycle RISC-V rv32im 3 | * 4 | * copyright (c) 2022 hirosh dabui 5 | * 6 | * permission to use, copy, modify, and/or distribute this software for any 7 | * purpose with or without fee is hereby granted, provided that the above 8 | * copyright notice and this permission notice appear in all copies. 9 | * 10 | * the software is provided "as is" and the author disclaims all warranties 11 | * with regard to this software including all implied warranties of 12 | * merchantability and fitness. in no event shall the author be liable for 13 | * any special, direct, indirect, or consequential damages or any damages 14 | * whatsoever resulting from loss of use, data or profits, whether in an 15 | * action of contract, negligence or other tortious action, arising out of 16 | * or in connection with the use or performance of this software. 17 | * 18 | */ 19 | `default_nettype none `timescale 1 ns / 100 ps 20 | 21 | `include "riscv_defines.vh" 22 | module multiplier ( 23 | input wire clk, 24 | input wire resetn, 25 | input wire [ 31 : 0] factor1, 26 | input wire [ 31 : 0] factor2, 27 | input wire [`MUL_OP_WIDTH -1 : 0] MULop, 28 | output wire [ 31 : 0] product, 29 | input wire valid, 30 | output reg ready 31 | ); 32 | 33 | wire is_mulh = MULop == `MUL_OP_MULH; 34 | wire is_mulsu = MULop == `MUL_OP_MULSU; 35 | wire is_mulu = MULop == `MUL_OP_MULU; 36 | 37 | wire factor1_is_signed = is_mulh | is_mulsu; 38 | wire factor2_is_signed = is_mulh; 39 | 40 | // multiplication 41 | reg [63:0] rslt; 42 | reg [31:0] factor1_abs; 43 | reg [31:0] factor2_abs; 44 | reg [4:0] bit_idx; 45 | 46 | localparam IDLE_BIT = 0; 47 | localparam CALC_BIT = 1; 48 | localparam READY_BIT = 2; 49 | 50 | localparam IDLE = 1 << IDLE_BIT; 51 | localparam CALC = 1 << CALC_BIT; 52 | localparam READY = 1 << READY_BIT; 53 | 54 | localparam NR_STATES = 3; 55 | 56 | (* onehot *) 57 | reg [NR_STATES-1:0] state; 58 | 59 | wire [31:0] rslt_upper_low = (is_mulh | is_mulu | is_mulsu) ? rslt[63:32] : rslt[31:0]; 60 | always @(posedge clk) begin 61 | if (!resetn) begin 62 | state <= IDLE; 63 | ready <= 1'b0; 64 | bit_idx <= 0; 65 | end else begin 66 | 67 | (* parallel_case, full_case *) 68 | case (1'b1) 69 | 70 | state[IDLE_BIT]: begin 71 | ready <= 1'b0; 72 | if (!ready && valid) begin 73 | factor1_abs <= (factor1_is_signed & factor1[31]) ? ~factor1 + 1 : factor1; 74 | factor2_abs <= (factor2_is_signed & factor2[31]) ? ~factor2 + 1 : factor2; 75 | bit_idx <= 0; 76 | rslt <= 0; 77 | state <= CALC; 78 | end 79 | end 80 | 81 | state[CALC_BIT]: begin 82 | `ifndef FAKE_MULTIPLIER 83 | /* verilator lint_off WIDTH */ 84 | rslt <= rslt + ((factor1_abs & {32{factor2_abs[bit_idx]}}) << bit_idx); 85 | /* verilator lint_on WIDTH */ 86 | bit_idx <= bit_idx + 1'b1; 87 | if (&bit_idx) begin 88 | state <= READY; 89 | end 90 | `else 91 | rslt <= factor1_abs * factor2_abs; 92 | state <= READY; 93 | `endif 94 | end 95 | 96 | state[READY_BIT]: begin 97 | /* verilator lint_off WIDTH */ 98 | rslt <= ((factor1[31] & factor1_is_signed ^ factor2[31] & factor2_is_signed)) ? ~rslt + 1 : rslt; 99 | /* verilator lint_on WIDTH */ 100 | 101 | ready <= 1'b1; 102 | state <= IDLE; 103 | end 104 | 105 | endcase 106 | 107 | end 108 | 109 | end 110 | 111 | assign product = rslt_upper_low; 112 | 113 | endmodule 114 | -------------------------------------------------------------------------------- /Hardware/KianV-Icestudio/Level-01/multiplier_decoder.v: -------------------------------------------------------------------------------- 1 | /* 2 | * kianv harris multicycle RISC-V rv32im 3 | * 4 | * copyright (c) 2022 hirosh dabui 5 | * 6 | * permission to use, copy, modify, and/or distribute this software for any 7 | * purpose with or without fee is hereby granted, provided that the above 8 | * copyright notice and this permission notice appear in all copies. 9 | * 10 | * the software is provided "as is" and the author disclaims all warranties 11 | * with regard to this software including all implied warranties of 12 | * merchantability and fitness. in no event shall the author be liable for 13 | * any special, direct, indirect, or consequential damages or any damages 14 | * whatsoever resulting from loss of use, data or profits, whether in an 15 | * action of contract, negligence or other tortious action, arising out of 16 | * or in connection with the use or performance of this software. 17 | * 18 | */ 19 | `default_nettype none `timescale 1 ns / 100 ps 20 | `include "riscv_defines.vh" 21 | module multiplier_decoder ( 22 | input wire [ 2:0] funct3, 23 | output reg [`MUL_OP_WIDTH -1:0] MULop, 24 | input wire mul_ext_valid, 25 | output wire mul_valid 26 | ); 27 | 28 | wire is_mul = funct3 == 3'b000; 29 | wire is_mulh = funct3 == 3'b001; 30 | wire is_mulsu = funct3 == 3'b010; 31 | wire is_mulu = funct3 == 3'b011; 32 | reg valid; 33 | 34 | assign mul_valid = valid & mul_ext_valid; 35 | always @(*) begin 36 | valid = 1'b1; 37 | case (1'b1) 38 | is_mul: MULop = `MUL_OP_MUL; 39 | is_mulh: MULop = `MUL_OP_MULH; 40 | is_mulsu: MULop = `MUL_OP_MULSU; 41 | is_mulu: MULop = `MUL_OP_MULU; 42 | default: begin 43 | /* verilator lint_off WIDTH */ 44 | MULop = 'hxx; 45 | /* verilator lint_on WIDTH */ 46 | valid = 1'b0; 47 | end 48 | endcase 49 | end 50 | 51 | endmodule 52 | -------------------------------------------------------------------------------- /Hardware/KianV-Icestudio/Level-01/multiplier_extension_decoder.v: -------------------------------------------------------------------------------- 1 | /* 2 | * kianv harris multicycle RISC-V rv32im 3 | * 4 | * copyright (c) 2022 hirosh dabui 5 | * 6 | * permission to use, copy, modify, and/or distribute this software for any 7 | * purpose with or without fee is hereby granted, provided that the above 8 | * copyright notice and this permission notice appear in all copies. 9 | * 10 | * the software is provided "as is" and the author disclaims all warranties 11 | * with regard to this software including all implied warranties of 12 | * merchantability and fitness. in no event shall the author be liable for 13 | * any special, direct, indirect, or consequential damages or any damages 14 | * whatsoever resulting from loss of use, data or profits, whether in an 15 | * action of contract, negligence or other tortious action, arising out of 16 | * or in connection with the use or performance of this software. 17 | * 18 | */ 19 | `default_nettype none `timescale 1 ns / 100 ps 20 | `include "riscv_defines.vh" 21 | module multiplier_extension_decoder ( 22 | input wire [ 2:0] funct3, 23 | output wire [`MUL_OP_WIDTH -1:0] MULop, 24 | output wire [`DIV_OP_WIDTH -1:0] DIVop, 25 | input wire mul_ext_valid, 26 | output wire mul_valid, 27 | output wire div_valid 28 | ); 29 | 30 | multiplier_decoder multiplier_I ( 31 | funct3, 32 | MULop, 33 | mul_ext_valid, 34 | mul_valid 35 | ); 36 | divider_decoder divider_decoder_I ( 37 | funct3, 38 | DIVop, 39 | mul_ext_valid, 40 | div_valid 41 | ); 42 | 43 | endmodule 44 | -------------------------------------------------------------------------------- /Hardware/KianV-Icestudio/Level-01/register_file.v: -------------------------------------------------------------------------------- 1 | /* 2 | * kianv harris multicycle RISC-V rv32ima 3 | * 4 | * copyright (c) 2023 hirosh dabui 5 | * 6 | * permission to use, copy, modify, and/or distribute this software for any 7 | * purpose with or without fee is hereby granted, provided that the above 8 | * copyright notice and this permission notice appear in all copies. 9 | * 10 | * the software is provided "as is" and the author disclaims all warranties 11 | * with regard to this software including all implied warranties of 12 | * merchantability and fitness. in no event shall the author be liable for 13 | * any special, direct, indirect, or consequential damages or any damages 14 | * whatsoever resulting from loss of use, data or profits, whether in an 15 | * action of contract, negligence or other tortious action, arising out of 16 | * or in connection with the use or performance of this software. 17 | * 18 | */ 19 | `default_nettype none `timescale 1 ns / 100 ps 20 | 21 | module register_file #( 22 | parameter REGISTER_DEPTH = 32, // rv32e = 16; rv32i = 32 23 | parameter STACKADDR = 32'hffff_ffff 24 | ) ( 25 | input wire clk, 26 | input wire we, 27 | input wire [ 4:0] A1, 28 | input wire [ 4:0] A2, 29 | input wire [ 4:0] A3, 30 | input wire [31:0] wd, 31 | output wire [31:0] rd1, 32 | output wire [31:0] rd2 33 | ); 34 | reg [31:0] bank0[0:REGISTER_DEPTH -1]; 35 | integer i; 36 | 37 | localparam X2 = 2; 38 | initial begin 39 | bank0[10] = 'h00; // hartid 40 | bank0[11] = 32'h80_000_000 + ((1024*1024*32)-2048);// 32'h81fffa00; // dtb 41 | end 42 | 43 | 44 | always @(posedge clk) begin 45 | 46 | if (we && A3 != 0) begin 47 | bank0[A3] <= wd; 48 | end 49 | end 50 | 51 | assign rd1 = A1 != 0 ? bank0[A1] : 32'b0; 52 | assign rd2 = A2 != 0 ? bank0[A2] : 32'b0; 53 | 54 | endmodule 55 | -------------------------------------------------------------------------------- /Hardware/KianV-Icestudio/Level-01/rv32_amo_opcodes.vh: -------------------------------------------------------------------------------- 1 | /* 2 | * kianv harris multicycle RISC-V rv32im 3 | * 4 | * copyright (c) 2023 hirosh dabui 5 | * 6 | * permission to use, copy, modify, and/or distribute this software for any 7 | * purpose with or without fee is hereby granted, provided that the above 8 | * copyright notice and this permission notice appear in all copies. 9 | * 10 | * the software is provided "as is" and the author disclaims all warranties 11 | * with regard to this software including all implied warranties of 12 | * merchantability and fitness. in no event shall the author be liable for 13 | * any special, direct, indirect, or consequential damages or any damages 14 | * whatsoever resulting from loss of use, data or profits, whether in an 15 | * action of contract, negligence or other tortious action, arising out of 16 | * or in connection with the use or performance of this software. 17 | */ 18 | `define RV32_AMO_OPCODE 7'h2F 19 | `define RV32_AMO_FUNCT3 3'h2 20 | `define RV32_AMOADD_W 5'h00 21 | `define RV32_AMOSWAP_W 5'h01 22 | `define RV32_LR_W 5'h02 23 | `define RV32_SC_W 5'h03 24 | `define RV32_AMOXOR_W 5'h04 25 | `define RV32_AMOAND_W 5'h0C 26 | `define RV32_AMOOR_W 5'h08 27 | `define RV32_AMOMIN_W 5'h10 28 | `define RV32_AMOMAX_W 5'h14 29 | `define RV32_AMOMINU_W 5'h18 30 | `define RV32_AMOMAXU_W 5'h1c 31 | `define RV32_FENCE_OPCODE 7'b0001111 32 | 33 | /* verilog_format: off */ 34 | `define RV32_IS_AMO_INSTRUCTION(opcode, funct3) (opcode == `RV32_AMO_OPCODE && funct3 == `RV32_AMO_FUNCT3) 35 | `define RV32_IS_AMOADD_W(funct5) (funct5 == `RV32_AMOADD_W) 36 | `define RV32_IS_AMOSWAP_W(funct5) (funct5 == `RV32_AMOSWAP_W) 37 | `define RV32_IS_LR_W(funct5) (funct5 == `RV32_LR_W) 38 | `define RV32_IS_SC_W(funct5) (funct5 == `RV32_SC_W) 39 | `define RV32_IS_AMOXOR_W(funct5) ( funct5 == `RV32_AMOXOR_W) 40 | `define RV32_IS_AMOAND_W(funct5) ( funct5 == `RV32_AMOAND_W) 41 | `define RV32_IS_AMOOR_W(funct5) ( funct5 == `RV32_AMOOR_W) 42 | `define RV32_IS_AMOMIN_W(funct5) ( funct5 == `RV32_AMOMIN_W) 43 | `define RV32_IS_AMOMAX_W(funct5) ( funct5 == `RV32_AMOMAX_W) 44 | `define RV32_IS_AMOMINU_W(funct5) ( funct5 == `RV32_AMOMINU_W) 45 | `define RV32_IS_AMOMAXU_W(funct5) ( funct5 == `RV32_AMOMAXU_W) 46 | `define RV32_IS_FENCE(opcode) ( opcode == `RV32_FENCE_OPCODE) 47 | /* verilog_format: on */ 48 | -------------------------------------------------------------------------------- /Hardware/KianV-Icestudio/Level-01/store_alignment.v: -------------------------------------------------------------------------------- 1 | /* 2 | * kianv harris multicycle RISC-V rv32im 3 | * 4 | * copyright (c) 2022 hirosh dabui 5 | * 6 | * permission to use, copy, modify, and/or distribute this software for any 7 | * purpose with or without fee is hereby granted, provided that the above 8 | * copyright notice and this permission notice appear in all copies. 9 | * 10 | * the software is provided "as is" and the author disclaims all warranties 11 | * with regard to this software including all implied warranties of 12 | * merchantability and fitness. in no event shall the author be liable for 13 | * any special, direct, indirect, or consequential damages or any damages 14 | * whatsoever resulting from loss of use, data or profits, whether in an 15 | * action of contract, negligence or other tortious action, arising out of 16 | * or in connection with the use or performance of this software. 17 | * 18 | */ 19 | `default_nettype none `timescale 1 ns / 100 ps 20 | 21 | `include "riscv_defines.vh" 22 | 23 | module store_alignment ( 24 | input wire [ 1:0] addr, 25 | input wire [`STORE_OP_WIDTH -1:0] STOREop, 26 | input wire [ 31:0] data, 27 | output reg [ 31:0] result, 28 | output reg [ 3:0] wmask, 29 | output reg unaligned_access 30 | ); 31 | 32 | always @* begin 33 | unaligned_access = 1'b0; 34 | wmask = 0; 35 | result = 'hx; 36 | 37 | case (STOREop) 38 | (`STORE_OP_SB): begin 39 | result[7:0] = addr[1:0] == 2'b00 ? data[7:0] : 8'hx; 40 | result[15:8] = addr[1:0] == 2'b01 ? data[7:0] : 8'hx; 41 | result[23:16] = addr[1:0] == 2'b10 ? data[7:0] : 8'hx; 42 | result[31:24] = addr[1:0] == 2'b11 ? data[7:0] : 8'hx; 43 | wmask = addr[1:0] == 2'b00 ? 4'b 0001 : 44 | addr[1:0] == 2'b01 ? 4'b 0010 : 45 | addr[1:0] == 2'b10 ? 4'b 0100 : 4'b 1000; 46 | unaligned_access = 1'b0; 47 | end 48 | (`STORE_OP_SH): begin 49 | result[15:0] = ~addr[1] ? data[15:0] : 16'hx; 50 | result[31:16] = addr[1] ? data[15:0] : 16'hx; 51 | wmask = addr[1] ? 4'b1100 : 4'b0011; 52 | unaligned_access = addr[0]; 53 | end 54 | (`STORE_OP_SW): begin 55 | result = data; 56 | wmask = 4'b1111; 57 | unaligned_access = addr[1:0] != 2'b00; 58 | end 59 | default: begin 60 | result = 'hx; 61 | wmask = 4'b0000; 62 | unaligned_access = 1'b0; 63 | end 64 | endcase 65 | 66 | end 67 | endmodule 68 | -------------------------------------------------------------------------------- /Hardware/KianV-Icestudio/Level-01/store_decoder.v: -------------------------------------------------------------------------------- 1 | /* 2 | * kianv harris multicycle RISC-V rv32im 3 | * 4 | * copyright (c) 2022 hirosh dabui 5 | * 6 | * permission to use, copy, modify, and/or distribute this software for any 7 | * purpose with or without fee is hereby granted, provided that the above 8 | * copyright notice and this permission notice appear in all copies. 9 | * 10 | * the software is provided "as is" and the author disclaims all warranties 11 | * with regard to this software including all implied warranties of 12 | * merchantability and fitness. in no event shall the author be liable for 13 | * any special, direct, indirect, or consequential damages or any damages 14 | * whatsoever resulting from loss of use, data or profits, whether in an 15 | * action of contract, negligence or other tortious action, arising out of 16 | * or in connection with the use or performance of this software. 17 | * 18 | */ 19 | `default_nettype none 20 | `timescale 1 ns/100 ps 21 | `include "riscv_defines.vh" 22 | module store_decoder 23 | ( 24 | input wire [ 2: 0] funct3, 25 | input wire amo_store_op, 26 | output reg [`STORE_OP_WIDTH -1: 0] STOREop 27 | ); 28 | wire is_sb = funct3[1:0] == 2'b 00; 29 | wire is_sh = funct3[1:0] == 2'b 01; 30 | wire is_sw = funct3[1:0] == 2'b 10; 31 | 32 | always @(*) begin 33 | if (!amo_store_op) begin 34 | case (1'b1) 35 | is_sb : STOREop = `STORE_OP_SB; 36 | is_sh : STOREop = `STORE_OP_SH; 37 | is_sw : STOREop = `STORE_OP_SW; 38 | default: 39 | /* verilator lint_off WIDTH */ 40 | STOREop = 'hxx; 41 | /* verilator lint_on WIDTH */ 42 | endcase 43 | end else begin 44 | STOREop = `STORE_OP_SW; 45 | end 46 | end 47 | 48 | endmodule 49 | -------------------------------------------------------------------------------- /Hardware/KianV-Icestudio/Level-02/alu.v: -------------------------------------------------------------------------------- 1 | /* 2 | * kianv harris multicycle RISC-V rv32im 3 | * 4 | * copyright (c) 2022 hirosh dabui 5 | * 6 | * permission to use, copy, modify, and/or distribute this software for any 7 | * purpose with or without fee is hereby granted, provided that the above 8 | * copyright notice and this permission notice appear in all copies. 9 | * 10 | * the software is provided "as is" and the author disclaims all warranties 11 | * with regard to this software including all implied warranties of 12 | * merchantability and fitness. in no event shall the author be liable for 13 | * any special, direct, indirect, or consequential damages or any damages 14 | * whatsoever resulting from loss of use, data or profits, whether in an 15 | * action of contract, negligence or other tortious action, arising out of 16 | * or in connection with the use or performance of this software. 17 | * 18 | */ 19 | `default_nettype none `timescale 1 ns / 100 ps 20 | `include "riscv_defines.vh" 21 | 22 | module alu ( 23 | input wire [ 31:0] a, 24 | input wire [ 31:0] b, 25 | input wire [`ALU_CTRL_WIDTH -1:0] alucontrol, 26 | output reg [ 31:0] result, 27 | output wire zero 28 | ); 29 | 30 | 31 | wire is_beq = alucontrol == `ALU_CTRL_BEQ; 32 | wire is_bne = alucontrol == `ALU_CTRL_BNE; 33 | wire is_blt = alucontrol == `ALU_CTRL_BLT; 34 | wire is_bge = alucontrol == `ALU_CTRL_BGE; 35 | wire is_bltu = alucontrol == `ALU_CTRL_BLTU; 36 | wire is_bgeu = alucontrol == `ALU_CTRL_BGEU; 37 | wire is_slt_slti = alucontrol == `ALU_CTRL_SLT_SLTI; 38 | wire is_sltu_sltiu = alucontrol == `ALU_CTRL_SLTU_SLTIU; 39 | wire is_sub_ctrl = alucontrol == `ALU_CTRL_SUB; 40 | wire is_amo_min_max = alucontrol == `ALU_CTRL_MIN || alucontrol == `ALU_CTRL_MAX || 41 | alucontrol == `ALU_CTRL_MINU || alucontrol == `ALU_CTRL_MAXU; 42 | 43 | wire is_sub = is_sub_ctrl || is_beq || is_bne || is_blt || is_bge || 44 | is_bltu || is_bgeu || is_slt_slti || is_amo_min_max || is_sltu_sltiu; 45 | 46 | 47 | wire [31:0] condinv = is_sub ? ~b : b; 48 | 49 | // seen 33 Bit sum from Bruno's Levy 50 | // with that approach I could map all branch to LT, LTU 51 | wire [32:0] sum = {1'b1, condinv} + {1'b0, a} + {32'b0, is_sub}; 52 | wire LT = (a[31] ^ b[31]) ? a[31] : sum[32]; 53 | wire LTU = sum[32]; 54 | 55 | wire [31:0] sltx_sltux_rslt = {31'b0, is_slt_slti ? LT : LTU}; 56 | wire [63:0] sext_rs1 = {{32{a[31]}}, a}; 57 | wire [63:0] sra_srai_rslt = sext_rs1 >> b[4:0]; 58 | 59 | wire is_sum_zero = sum[31:0] == 32'b0; 60 | 61 | always @* begin 62 | case (alucontrol) 63 | `ALU_CTRL_ADD_ADDI: result = sum[31:0]; 64 | `ALU_CTRL_SUB: result = sum[31:0]; 65 | `ALU_CTRL_XOR_XORI: result = a ^ b; 66 | `ALU_CTRL_OR_ORI: result = a | b; 67 | `ALU_CTRL_AND_ANDI: result = a & b; 68 | `ALU_CTRL_SLL_SLLI: result = a << b[4:0]; 69 | `ALU_CTRL_SRL_SRLI: result = a >> b[4:0]; 70 | `ALU_CTRL_SRA_SRAI: result = sra_srai_rslt[31:0]; 71 | `ALU_CTRL_SLT_SLTI: result = (a[31] == b[31]) ? sltx_sltux_rslt : {31'b0, a[31]}; 72 | `ALU_CTRL_SLTU_SLTIU: result = sltx_sltux_rslt; 73 | `ALU_CTRL_MIN: result = LT ? a : b; 74 | `ALU_CTRL_MAX: result = !LT ? a : b; 75 | `ALU_CTRL_MINU: result = LTU ? a : b; 76 | `ALU_CTRL_MAXU: result = !LTU ? a : b; 77 | `ALU_CTRL_LUI: result = b; 78 | `ALU_CTRL_AUIPC: result = sum[31:0]; 79 | default: begin 80 | case (1'b1) 81 | is_beq: result = {31'b0, is_sum_zero}; 82 | is_bne: result = {31'b0, !is_sum_zero}; 83 | is_blt: result = {31'b0, LT}; 84 | is_bge: result = {31'b0, !LT}; 85 | is_bltu: result = {31'b0, LTU}; 86 | is_bgeu: result = {31'b0, !LTU}; 87 | default: result = 32'b0; 88 | endcase 89 | end 90 | endcase 91 | end 92 | 93 | assign zero = result == 32'b0; 94 | endmodule 95 | -------------------------------------------------------------------------------- /Hardware/KianV-Icestudio/Level-02/bram.v: -------------------------------------------------------------------------------- 1 | /* 2 | * kianv.v - a simple RISC-V rv32i 3 | * 4 | * copyright (c) 2022 hirosh dabui 5 | * 6 | * permission to use, copy, modify, and/or distribute this software for any 7 | * purpose with or without fee is hereby granted, provided that the above 8 | * copyright notice and this permission notice appear in all copies. 9 | * 10 | * the software is provided "as is" and the author disclaims all warranties 11 | * with regard to this software including all implied warranties of 12 | * merchantability and fitness. in no event shall the author be liable for 13 | * any special, direct, indirect, or consequential damages or any damages 14 | * whatsoever resulting from loss of use, data or profits, whether in an 15 | * action of contract, negligence or other tortious action, arising out of 16 | * or in connection with the use or performance of this software. 17 | * 18 | */ 19 | `default_nettype none `timescale 1 ns / 100 ps 20 | module bram #( 21 | parameter integer WIDTH = 8, 22 | parameter INIT_FILE = "", 23 | parameter SHOW_FIRMWARE = 0 24 | ) ( 25 | input wire clk, 26 | input wire [WIDTH -1:0] addr, 27 | input wire [31:0] wdata, 28 | output reg [31:0] rdata, 29 | input wire [3:0] wmask 30 | ); 31 | reg [31:0] mem[0:(1< 5 | * 6 | * permission to use, copy, modify, and/or distribute this software for any 7 | * purpose with or without fee is hereby granted, provided that the above 8 | * copyright notice and this permission notice appear in all copies. 9 | * 10 | * the software is provided "as is" and the author disclaims all warranties 11 | * with regard to this software including all implied warranties of 12 | * merchantability and fitness. in no event shall the author be liable for 13 | * any special, direct, indirect, or consequential damages or any damages 14 | * whatsoever resulting from loss of use, data or profits, whether in an 15 | * action of contract, negligence or other tortious action, arising out of 16 | * or in connection with the use or performance of this software. 17 | * 18 | */ 19 | `default_nettype none `timescale 1 ns / 100 ps 20 | module clint #( 21 | parameter SYSTEM_CLK = 25_000_000, 22 | parameter CLOCK_TICK = 1000 23 | ) ( 24 | input wire clk, 25 | input wire resetn, 26 | input wire valid, 27 | input wire [31:0] addr, 28 | input wire [3:0] wmask, 29 | input wire [31:0] wdata, 30 | output reg [31:0] rdata, 31 | output wire is_valid, 32 | output reg ready, 33 | output wire IRQ3, 34 | output wire IRQ7 35 | ); 36 | 37 | /* verilator lint_off WIDTHTRUNC */ 38 | localparam CLOCK_TICK_BIT_WIDTH = $clog2(CLOCK_TICK); 39 | localparam [CLOCK_TICK_BIT_WIDTH -1:0] CYCLES_TO_TICK = ($rtoi(SYSTEM_CLK / CLOCK_TICK)); 40 | /* verilator lint_on WIDTHTRUNC */ 41 | wire is_msip = (addr == 32'h1100_0000); 42 | wire is_mtimecmpl = (addr == 32'h1100_4000); 43 | wire is_mtimecmph = (addr == 32'h1100_4004); 44 | wire is_mtimeh = (addr == 32'h1100_bffc); 45 | wire is_mtimel = (addr == 32'h1100_bff8); 46 | 47 | assign is_valid = valid && (is_msip || is_mtimecmpl || is_mtimecmph || is_mtimel || is_mtimeh); 48 | always @(posedge clk) ready <= !resetn ? 1'b0 : is_valid; 49 | 50 | reg [63:0] mtime; 51 | always @(posedge clk) mtime <= !resetn ? 0 : (tick) ? mtime + 1 : mtime; 52 | 53 | wire is_we = |wmask; 54 | 55 | reg [63:0] mtimecmp; 56 | reg msip; 57 | 58 | always @(posedge clk) 59 | if (!resetn) begin 60 | mtimecmp <= 0; 61 | msip <= 0; 62 | end else if (is_mtimecmpl && is_valid) begin 63 | if (wmask[0]) mtimecmp[7:0] <= wdata[7:0]; 64 | if (wmask[1]) mtimecmp[15:8] <= wdata[15:8]; 65 | if (wmask[2]) mtimecmp[23:16] <= wdata[23:16]; 66 | if (wmask[3]) mtimecmp[31:24] <= wdata[31:24]; 67 | end else if (is_mtimecmph && is_valid) begin 68 | if (wmask[0]) mtimecmp[39:32] <= wdata[7:0]; 69 | if (wmask[1]) mtimecmp[47:40] <= wdata[15:8]; 70 | if (wmask[2]) mtimecmp[55:48] <= wdata[23:16]; 71 | if (wmask[3]) mtimecmp[63:56] <= wdata[31:24]; 72 | end else if (is_msip && is_valid) begin 73 | if (wmask[0]) msip <= wdata[0]; 74 | end 75 | 76 | always @(*) begin 77 | case (1'b1) 78 | is_mtimecmpl: rdata = mtimecmp[31:0]; 79 | is_mtimecmph: rdata = mtimecmp[63:32]; 80 | is_mtimel: rdata = mtime[31:0]; 81 | is_mtimeh: rdata = mtime[63:32]; 82 | is_msip: rdata = {31'b0, msip}; 83 | default: rdata = 0; 84 | endcase 85 | end 86 | 87 | 88 | reg [CLOCK_TICK_BIT_WIDTH -1:0] tick_cnt; 89 | wire tick = tick_cnt == (CYCLES_TO_TICK - 1); 90 | always @(posedge clk) begin 91 | if (!resetn) begin 92 | tick_cnt <= 0; 93 | end else begin 94 | if (tick) begin 95 | tick_cnt <= 0; 96 | end else begin 97 | tick_cnt <= tick_cnt + 1; 98 | end 99 | end 100 | end 101 | 102 | assign IRQ3 = msip; 103 | assign IRQ7 = (mtime >= mtimecmp); 104 | 105 | endmodule 106 | 107 | -------------------------------------------------------------------------------- /Hardware/KianV-Icestudio/Level-02/csr_utilities.vh: -------------------------------------------------------------------------------- 1 | /* 2 | * kianv.v - RISC-V rv32ima 3 | * 4 | * copyright (c) 2023 hirosh dabui 5 | * 6 | * permission to use, copy, modify, and/or distribute this software for any 7 | * purpose with or without fee is hereby granted, provided that the above 8 | * copyright notice and this permission notice appear in all copies. 9 | * 10 | * the software is provided "as is" and the author disclaims all warranties 11 | * with regard to this software including all implied warranties of 12 | * merchantability and fitness. in no event shall the author be liable for 13 | * any special, direct, indirect, or consequential damages or any damages 14 | * whatsoever resulting from loss of use, data or profits, whether in an 15 | * action of contract, negligence or other tortious action, arising out of 16 | * or in connection with the use or performance of this software. 17 | * 18 | */ 19 | `ifndef CSR_UTILITIES_VH 20 | `define CSR_UTILITIES_VH 21 | 22 | // Unprivileged Counter/Timers 23 | `define CSR_REG_CYCLE 12'h C00 24 | `define CSR_REG_CYCLEH 12'h C80 25 | `define CSR_REG_INSTRET 12'h C02 26 | `define CSR_REG_INSTRETH 12'h C82 27 | `define CSR_REG_TIME 12'h C01 28 | `define CSR_REG_TIMEH 12'h C81 29 | 30 | // Machine Trap Setup 31 | `define CSR_REG_MSTATUS 12'h 300 32 | `define CSR_REG_MISA 12'h 301 33 | `define CSR_REG_MIE 12'h 304 34 | `define CSR_REG_MTVEC 12'h 305 35 | 36 | // Machine Trap Handling 37 | `define CSR_REG_MSCRATCH 12'h 340 38 | `define CSR_REG_MEPC 12'h 341 39 | `define CSR_REG_MCAUSE 12'h 342 40 | `define CSR_REG_MTVAL 12'h 343 41 | `define CSR_REG_MIP 12'h 344 42 | 43 | `define CSR_REG_MCOUNTEREN 12'h 306 44 | 45 | `define CSR_REG_MHARTID 12'h f14 46 | `define CSR_REG_MVENDORID 12'h f11 47 | 48 | // Machine-Level CSRs 49 | // custrom read-only 50 | `define CSR_PRIVILEGE_MODE 12'h fc0 // machine privilege mode 51 | 52 | 53 | // RISC-V CSR instruction opcodes (7-bit) and funct3 (3-bit) 54 | `define CSR_OPCODE `SYSTEM_OPCODE 55 | `define CSR_FUNCT3_RW 3'b001 56 | `define CSR_FUNCT3_RS 3'b010 57 | `define CSR_FUNCT3_RC 3'b011 58 | `define CSR_FUNCT3_RWI 3'b101 59 | `define CSR_FUNCT3_RSI 3'b110 60 | `define CSR_FUNCT3_RCI 3'b111 61 | 62 | `include "riscv_priv_csr_status.vh" 63 | `include "misa.vh" 64 | `endif 65 | -------------------------------------------------------------------------------- /Hardware/KianV-Icestudio/Level-02/design_elements.v: -------------------------------------------------------------------------------- 1 | /* 2 | * kianv harris multicycle RISC-V rv32im 3 | * 4 | * copyright (c) 2022/23 hirosh dabui 5 | * 6 | * permission to use, copy, modify, and/or distribute this software for any 7 | * purpose with or without fee is hereby granted, provided that the above 8 | * copyright notice and this permission notice appear in all copies. 9 | * 10 | * the software is provided "as is" and the author disclaims all warranties 11 | * with regard to this software including all implied warranties of 12 | * merchantability and fitness. in no event shall the author be liable for 13 | * any special, direct, indirect, or consequential damages or any damages 14 | * whatsoever resulting from loss of use, data or profits, whether in an 15 | * action of contract, negligence or other tortious action, arising out of 16 | * or in connection with the use or performance of this software. 17 | * 18 | */ 19 | `default_nettype none `timescale 1 ns / 100 ps 20 | /* verilator lint_off MULTITOP */ 21 | 22 | module mux2 #( 23 | parameter WIDTH = 32 24 | ) ( 25 | input wire [WIDTH -1:0] d0, 26 | d1, 27 | input wire s, 28 | output wire [WIDTH -1:0] y 29 | ); 30 | 31 | assign y = s ? d1 : d0; 32 | endmodule 33 | 34 | module mux3 #( 35 | parameter WIDTH = 32 36 | ) ( 37 | input wire [WIDTH -1:0] d0, 38 | d1, 39 | d2, 40 | input wire [ 1:0] s, 41 | output wire [WIDTH -1:0] y 42 | ); 43 | 44 | assign y = s[1] ? d2 : (s[0] ? d1 : d0); 45 | endmodule 46 | 47 | module mux4 #( 48 | parameter WIDTH = 32 49 | ) ( 50 | input wire [WIDTH -1:0] d0, 51 | d1, 52 | d2, 53 | d3, 54 | input wire [ 1:0] s, 55 | output wire [WIDTH -1:0] y 56 | ); 57 | 58 | wire [WIDTH -1:0] low, high; 59 | 60 | mux2 lowmux ( 61 | d0, 62 | d1, 63 | s[0], 64 | low 65 | ); 66 | mux2 highmux ( 67 | d2, 68 | d3, 69 | s[0], 70 | high 71 | ); 72 | mux2 finalmux ( 73 | low, 74 | high, 75 | s[1], 76 | y 77 | ); 78 | endmodule 79 | 80 | module mux5 #( 81 | parameter WIDTH = 32 82 | ) ( 83 | input wire [WIDTH -1:0] d0, 84 | d1, 85 | d2, 86 | d3, 87 | d4, 88 | input wire [ 2:0] s, 89 | output wire [WIDTH -1:0] y 90 | 91 | ); 92 | 93 | assign y = (s == 0) ? d0 : (s == 1) ? d1 : (s == 2) ? d2 : (s == 3) ? d3 : d4; 94 | 95 | endmodule 96 | 97 | module mux6 #( 98 | parameter WIDTH = 32 99 | ) ( 100 | input wire [WIDTH -1:0] d0, 101 | d1, 102 | d2, 103 | d3, 104 | d4, 105 | d5, 106 | input wire [ 2:0] s, 107 | output wire [WIDTH -1:0] y 108 | 109 | ); 110 | 111 | assign y = (s == 0) ? d0 : (s == 1) ? d1 : (s == 2) ? d2 : (s == 3) ? d3 : (s == 4) ? d4 : d5; 112 | 113 | endmodule 114 | 115 | module dlatch #( 116 | parameter WIDTH = 32 117 | ) ( 118 | input wire clk, 119 | input wire [WIDTH -1:0] d, 120 | output reg [WIDTH -1:0] q 121 | ); 122 | always @(posedge clk) q <= d; 123 | endmodule 124 | 125 | module dff #( 126 | parameter WIDTH = 32, 127 | parameter PRESET = 0 128 | ) ( 129 | input wire resetn, 130 | input wire clk, 131 | input wire en, 132 | input wire [WIDTH -1:0] d, 133 | output reg [WIDTH -1:0] q 134 | ); 135 | always @(posedge clk) 136 | if (!resetn) q <= PRESET; 137 | else if (en) q <= d; 138 | 139 | endmodule 140 | module counter #( 141 | parameter WIDTH = 32 142 | ) ( 143 | input wire resetn, 144 | input wire clk, 145 | input wire inc, 146 | output reg [WIDTH -1:0] q 147 | ); 148 | always @(posedge clk) 149 | if (!resetn) q <= 0; 150 | else if (inc) q <= q + 1; 151 | 152 | endmodule 153 | /* verilator lint_on MULTITOP */ 154 | -------------------------------------------------------------------------------- /Hardware/KianV-Icestudio/Level-02/divider_decoder.v: -------------------------------------------------------------------------------- 1 | /* 2 | * kianv harris multicycle RISC-V rv32im 3 | * 4 | * copyright (c) 2022 hirosh dabui 5 | * 6 | * permission to use, copy, modify, and/or distribute this software for any 7 | * purpose with or without fee is hereby granted, provided that the above 8 | * copyright notice and this permission notice appear in all copies. 9 | * 10 | * the software is provided "as is" and the author disclaims all warranties 11 | * with regard to this software including all implied warranties of 12 | * merchantability and fitness. in no event shall the author be liable for 13 | * any special, direct, indirect, or consequential damages or any damages 14 | * whatsoever resulting from loss of use, data or profits, whether in an 15 | * action of contract, negligence or other tortious action, arising out of 16 | * or in connection with the use or performance of this software. 17 | * 18 | */ 19 | `default_nettype none `timescale 1 ns / 100 ps 20 | `include "riscv_defines.vh" 21 | module divider_decoder ( 22 | input wire [ 2:0] funct3, 23 | output reg [`DIV_OP_WIDTH -1:0] DIVop, 24 | input wire mul_ext_valid, 25 | output wire div_valid 26 | ); 27 | 28 | wire is_div = funct3 == 3'b100; 29 | wire is_divu = funct3 == 3'b101; 30 | wire is_rem = funct3 == 3'b110; 31 | wire is_remu = funct3 == 3'b111; 32 | reg valid; 33 | 34 | assign div_valid = valid & mul_ext_valid; 35 | 36 | always @(*) begin 37 | valid = 1'b1; 38 | case (1'b1) 39 | is_div: DIVop = `DIV_OP_DIV; 40 | is_divu: DIVop = `DIV_OP_DIVU; 41 | is_rem: DIVop = `DIV_OP_REM; 42 | is_remu: DIVop = `DIV_OP_REMU; 43 | default: begin 44 | /* verilator lint_off WIDTH */ 45 | DIVop = 'hxx; 46 | /* verilator lint_on WIDTH */ 47 | valid = 1'b0; 48 | end 49 | endcase 50 | end 51 | 52 | endmodule 53 | -------------------------------------------------------------------------------- /Hardware/KianV-Icestudio/Level-02/extend.v: -------------------------------------------------------------------------------- 1 | /* 2 | * kianv harris multicycle RISC-V rv32im 3 | * 4 | * copyright (c) 2022 hirosh dabui 5 | * 6 | * permission to use, copy, modify, and/or distribute this software for any 7 | * purpose with or without fee is hereby granted, provided that the above 8 | * copyright notice and this permission notice appear in all copies. 9 | * 10 | * the software is provided "as is" and the author disclaims all warranties 11 | * with regard to this software including all implied warranties of 12 | * merchantability and fitness. in no event shall the author be liable for 13 | * any special, direct, indirect, or consequential damages or any damages 14 | * whatsoever resulting from loss of use, data or profits, whether in an 15 | * action of contract, negligence or other tortious action, arising out of 16 | * or in connection with the use or performance of this software. 17 | * 18 | */ 19 | `default_nettype none `timescale 1 ns / 100 ps 20 | `include "riscv_defines.vh" 21 | module extend ( 22 | input wire [31:7] instr, 23 | input wire [ 2:0] immsrc, 24 | output reg [31:0] immext 25 | ); 26 | 27 | always @(*) begin 28 | case (immsrc) 29 | `IMMSRC_ITYPE: immext = {{20{instr[31]}}, instr[31:20]}; 30 | `IMMSRC_STYPE: immext = {{20{instr[31]}}, instr[31:25], instr[11:7]}; 31 | `IMMSRC_BTYPE: immext = {{20{instr[31]}}, instr[7:7], instr[30:25], instr[11:8], 1'b0}; 32 | `IMMSRC_JTYPE: immext = {{12{instr[31]}}, instr[19:12], instr[20], instr[30:21], 1'b0}; 33 | `IMMSRC_UTYPE: immext = {instr[31:12], 12'b0}; 34 | default: immext = 32'b0; 35 | endcase 36 | end 37 | endmodule 38 | -------------------------------------------------------------------------------- /Hardware/KianV-Icestudio/Level-02/fifo.v: -------------------------------------------------------------------------------- 1 | /* 2 | * fifo.v 3 | * 4 | * copyright (c) 2021 hirosh dabui 5 | * 6 | * permission to use, copy, modify, and/or distribute this software for any 7 | * purpose with or without fee is hereby granted, provided that the above 8 | * copyright notice and this permission notice appear in all copies. 9 | * 10 | * the software is provided "as is" and the author disclaims all warranties 11 | * with regard to this software including all implied warranties of 12 | * merchantability and fitness. in no event shall the author be liable for 13 | * any special, direct, indirect, or consequential damages or any damages 14 | * whatsoever resulting from loss of use, data or profits, whether in an 15 | * action of contract, negligence or other tortious action, arising out of 16 | * or in connection with the use or performance of this software. 17 | * 18 | */ 19 | 20 | `default_nettype none `timescale 1 ns / 100 ps 21 | module fifo #( 22 | parameter DATA_WIDTH = 8, 23 | parameter DEPTH = 4 24 | ) ( 25 | input wire clk, 26 | input wire resetn, 27 | input wire [DATA_WIDTH-1:0] din, 28 | output wire [DATA_WIDTH-1:0] dout, 29 | input wire push, 30 | input wire pop, 31 | output wire full, 32 | output wire empty 33 | ); 34 | 35 | reg [DATA_WIDTH-1:0] ram[0:DEPTH-1]; 36 | 37 | reg [$clog2(DEPTH):0] cnt; 38 | reg [$clog2(DEPTH)-1:0] rd_ptr; 39 | reg [$clog2(DEPTH)-1:0] wr_ptr; 40 | 41 | reg [$clog2(DEPTH):0] cnt_next; 42 | reg [$clog2(DEPTH)-1:0] rd_ptr_next; 43 | reg [$clog2(DEPTH)-1:0] wr_ptr_next; 44 | 45 | assign empty = cnt == 0; 46 | assign full = cnt == DEPTH; 47 | 48 | always @(posedge clk) begin 49 | if (~resetn) begin 50 | rd_ptr <= 0; 51 | wr_ptr <= 0; 52 | cnt <= 0; 53 | end else begin 54 | rd_ptr <= rd_ptr_next; 55 | wr_ptr <= wr_ptr_next; 56 | cnt <= cnt_next; 57 | end 58 | end 59 | 60 | always @(*) begin 61 | rd_ptr_next = rd_ptr; 62 | wr_ptr_next = wr_ptr; 63 | cnt_next = cnt; 64 | 65 | if (push) begin 66 | wr_ptr_next = wr_ptr + 1; 67 | cnt_next = (!pop || empty) ? cnt + 1 : cnt_next; 68 | end 69 | 70 | if (pop) begin 71 | rd_ptr_next = rd_ptr + 1; 72 | cnt_next = (!push || full) ? cnt - 1 : cnt_next; 73 | end 74 | 75 | end 76 | 77 | always @(posedge clk) begin 78 | if (push) ram[wr_ptr] <= din; 79 | end 80 | 81 | assign dout = ram[rd_ptr]; 82 | 83 | endmodule 84 | -------------------------------------------------------------------------------- /Hardware/KianV-Icestudio/Level-02/flash.sh: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | 3 | apio raw "fujprog -l 4 -j FLASH ice-build/Linux-soc-KianV-00/hardware.bit" -------------------------------------------------------------------------------- /Hardware/KianV-Icestudio/Level-02/load_alignment.v: -------------------------------------------------------------------------------- 1 | /* 2 | * kianv harris multicycle RISC-V rv32ima 3 | * 4 | * copyright (c) 2023 hirosh dabui 5 | * 6 | * permission to use, copy, modify, and/or distribute this software for any 7 | * purpose with or without fee is hereby granted, provided that the above 8 | * copyright notice and this permission notice appear in all copies. 9 | * 10 | * the software is provided "as is" and the author disclaims all warranties 11 | * with regard to this software including all implied warranties of 12 | * merchantability and fitness. in no event shall the author be liable for 13 | * any special, direct, indirect, or consequential damages or any damages 14 | * whatsoever resulting from loss of use, data or profits, whether in an 15 | * action of contract, negligence or other tortious action, arising out of 16 | * or in connection with the use or performance of this software. 17 | * 18 | */ 19 | `default_nettype none `timescale 1 ns / 100 ps 20 | `include "riscv_defines.vh" 21 | module load_alignment ( 22 | input wire [ 1:0] addr, 23 | input wire [`LOAD_OP_WIDTH -1:0] LOADop, 24 | input wire [ 31:0] data, 25 | output reg [ 31:0] result, 26 | output reg unaligned_access 27 | ); 28 | 29 | wire is_lb = `LOAD_OP_LB == LOADop; 30 | wire is_lbu = `LOAD_OP_LBU == LOADop; 31 | 32 | wire is_lh = `LOAD_OP_LH == LOADop; 33 | wire is_lhu = `LOAD_OP_LHU == LOADop; 34 | 35 | wire is_lw = `LOAD_OP_LW == LOADop; 36 | 37 | always @* begin 38 | result = 'hx; 39 | unaligned_access = 1'b0; 40 | if (is_lb | is_lbu) begin 41 | result[7:0] = 42 | addr[1:0] == 2'b00 ? data[7 :0] : 43 | addr[1:0] == 2'b01 ? data[15 :8] : 44 | addr[1:0] == 2'b10 ? data[23:16] : 45 | addr[1:0] == 2'b11 ? data[31:24] : 8'hx; 46 | result = {is_lbu ? 24'b0 : {24{result[7]}}, result[7:0]}; 47 | unaligned_access = 1'b0; 48 | end 49 | 50 | if (is_lh | is_lhu) begin 51 | result[15:0] = ~addr[1] ? data[15 : 0] : addr[1] ? data[31 : 16] : 16'hx; 52 | result = {is_lhu ? 16'b0 : {16{result[15]}}, result[15:0]}; 53 | unaligned_access = addr[0]; 54 | end 55 | 56 | if (is_lw) begin 57 | result = data; 58 | unaligned_access = addr[1:0] != 2'b00; 59 | end 60 | end 61 | 62 | endmodule 63 | -------------------------------------------------------------------------------- /Hardware/KianV-Icestudio/Level-02/load_decoder.v: -------------------------------------------------------------------------------- 1 | /* 2 | * kianv harris multicycle RISC-V rv32im 3 | * 4 | * copyright (c) 2022 hirosh dabui 5 | * 6 | * permission to use, copy, modify, and/or distribute this software for any 7 | * purpose with or without fee is hereby granted, provided that the above 8 | * copyright notice and this permission notice appear in all copies. 9 | * 10 | * the software is provided "as is" and the author disclaims all warranties 11 | * with regard to this software including all implied warranties of 12 | * merchantability and fitness. in no event shall the author be liable for 13 | * any special, direct, indirect, or consequential damages or any damages 14 | * whatsoever resulting from loss of use, data or profits, whether in an 15 | * action of contract, negligence or other tortious action, arising out of 16 | * or in connection with the use or performance of this software. 17 | * 18 | */ 19 | `default_nettype none 20 | `timescale 1 ns/100 ps 21 | `include "riscv_defines.vh" 22 | module load_decoder 23 | ( 24 | input wire [ 2: 0] funct3, 25 | input wire amo_load, 26 | output reg [`LOAD_OP_WIDTH -1: 0] LOADop 27 | ); 28 | wire is_lb = funct3 == 3'b 000; 29 | wire is_lh = funct3 == 3'b 001; 30 | wire is_lw = funct3 == 3'b 010; 31 | wire is_lbu = funct3 == 3'b 100; 32 | wire is_lhu = funct3 == 3'b 101; 33 | 34 | always @(*) begin 35 | if (!amo_load) begin 36 | case (1'b1) 37 | is_lb : LOADop = `LOAD_OP_LB; 38 | is_lh : LOADop = `LOAD_OP_LH; 39 | is_lw : LOADop = `LOAD_OP_LW; 40 | is_lbu : LOADop = `LOAD_OP_LBU; 41 | is_lhu : LOADop = `LOAD_OP_LHU; 42 | default: 43 | /* verilator lint_off WIDTH */ 44 | LOADop = 'hxx; 45 | /* verilator lint_on WIDTH */ 46 | endcase 47 | end else begin 48 | LOADop = `LOAD_OP_LW; 49 | end 50 | end 51 | 52 | endmodule 53 | -------------------------------------------------------------------------------- /Hardware/KianV-Icestudio/Level-02/mcause.vh: -------------------------------------------------------------------------------- 1 | /* 2 | * kianv.v - RISC-V rv32ima 3 | * 4 | * copyright (c) 2023 hirosh dabui 5 | * 6 | * permission to use, copy, modify, and/or distribute this software for any 7 | * purpose with or without fee is hereby granted, provided that the above 8 | * copyright notice and this permission notice appear in all copies. 9 | * 10 | * the software is provided "as is" and the author disclaims all warranties 11 | * with regard to this software including all implied warranties of 12 | * merchantability and fitness. in no event shall the author be liable for 13 | * any special, direct, indirect, or consequential damages or any damages 14 | * whatsoever resulting from loss of use, data or profits, whether in an 15 | * action of contract, negligence or other tortious action, arising out of 16 | * or in connection with the use or performance of this software. 17 | * 18 | */ 19 | `ifndef MCAUSE_VH 20 | `define MCAUSE_VH 21 | // Exception codes 22 | `define EXC_INSTR_ADDR_MISALIGNED 32'h00000000 23 | `define EXC_INSTR_ACCESS_FAULT 32'h00000001 24 | `define EXC_ILLEGAL_INSTRUCTION 32'h00000002 25 | `define EXC_BREAKPOINT 32'h00000003 26 | `define EXC_LOAD_AMO_ADDR_MISALIGNED 32'h00000004 27 | `define EXC_LOAD_AMO_ACCESS_FAULT 32'h00000005 28 | `define EXC_STORE_AMO_ADDR_MISALIGNED 32'h00000006 29 | `define EXC_STORE_AMO_ACCESS_FAULT 32'h00000007 30 | `define EXC_ECALL_FROM_UMODE 32'h00000008 31 | `define EXC_ECALL_FROM_SMODE 32'h00000009 32 | `define EXC_ECALL_FROM_MMODE 32'h0000000B 33 | `define EXC_INSTR_PAGE_FAULT 32'h0000000C 34 | `define EXC_LOAD_PAGE_FAULT 32'h0000000D 35 | `define EXC_STORE_AMO_PAGE_FAULT 32'h0000000F 36 | 37 | // Interrupt codes 38 | `define INTERRUPT_USER_SOFTWARE 32'h80000000 39 | `define INTERRUPT_SUPERVISOR_SOFTWARE 32'h80000001 40 | `define INTERRUPT_MACHINE_SOFTWARE 32'h80000003 41 | `define INTERRUPT_USER_TIMER 32'h80000004 42 | `define INTERRUPT_SUPERVISOR_TIMER 32'h80000005 43 | `define INTERRUPT_MACHINE_TIMER 32'h80000007 44 | `define INTERRUPT_USER_EXTERNAL 32'h80000008 45 | `define INTERRUPT_SUPERVISOR_EXTERNAL 32'h80000009 46 | `define INTERRUPT_MACHINE_EXTERNAL 32'h8000000B 47 | `endif 48 | -------------------------------------------------------------------------------- /Hardware/KianV-Icestudio/Level-02/misa.vh: -------------------------------------------------------------------------------- 1 | /* 2 | * kianv.v - RISC-V rv32ima 3 | * 4 | * copyright (c) 2023 hirosh dabui 5 | * 6 | * permission to use, copy, modify, and/or distribute this software for any 7 | * purpose with or without fee is hereby granted, provided that the above 8 | * copyright notice and this permission notice appear in all copies. 9 | * 10 | * the software is provided "as is" and the author disclaims all warranties 11 | * with regard to this software including all implied warranties of 12 | * merchantability and fitness. in no event shall the author be liable for 13 | * any special, direct, indirect, or consequential damages or any damages 14 | * whatsoever resulting from loss of use, data or profits, whether in an 15 | * action of contract, negligence or other tortious action, arising out of 16 | * or in connection with the use or performance of this software. 17 | * 18 | */ 19 | `ifndef MISA_VH 20 | `define MISA_VH 21 | 22 | `define MISA_MXL_RV32 2'b01 23 | `define MISA_EXTENSION_A 5'd0 24 | `define MISA_EXTENSION_B 5'd1 25 | `define MISA_EXTENSION_C 5'd2 26 | `define MISA_EXTENSION_D 5'd3 27 | `define MISA_EXTENSION_E 5'd4 28 | `define MISA_EXTENSION_F 5'd5 29 | `define MISA_EXTENSION_G 5'd6 30 | `define MISA_EXTENSION_H 5'd7 31 | `define MISA_EXTENSION_I 5'd8 32 | `define MISA_EXTENSION_J 5'd9 33 | `define MISA_EXTENSION_K 5'd10 34 | `define MISA_EXTENSION_L 5'd11 35 | `define MISA_EXTENSION_M 5'd12 36 | `define MISA_EXTENSION_N 5'd13 37 | `define MISA_EXTENSION_O 5'd14 38 | `define MISA_EXTENSION_P 5'd15 39 | `define MISA_EXTENSION_Q 5'd16 40 | `define MISA_EXTENSION_R 5'd17 41 | `define MISA_EXTENSION_S 5'd18 42 | `define MISA_EXTENSION_T 5'd19 43 | `define MISA_EXTENSION_U 5'd20 44 | `define MISA_EXTENSION_V 5'd21 45 | `define MISA_EXTENSION_W 5'd22 46 | `define MISA_EXTENSION_X 5'd23 47 | `define MISA_EXTENSION_Y 5'd24 48 | `define MISA_EXTENSION_Z 5'd25 49 | 50 | `define IS_EXTENSION_SUPPORTED(MXL, Extensions, Ext_To_Check) \ 51 | ((MXL) == `MISA_MXL_RV32) && (((Extensions) >> (Ext_To_Check)) & 1'b1) 52 | `define SET_MISA_VALUE(MXL) (MXL << 30) 53 | `define MISA_EXTENSION_BIT(extension) (1 << extension) 54 | 55 | `endif 56 | -------------------------------------------------------------------------------- /Hardware/KianV-Icestudio/Level-02/multiplier_decoder.v: -------------------------------------------------------------------------------- 1 | /* 2 | * kianv harris multicycle RISC-V rv32im 3 | * 4 | * copyright (c) 2022 hirosh dabui 5 | * 6 | * permission to use, copy, modify, and/or distribute this software for any 7 | * purpose with or without fee is hereby granted, provided that the above 8 | * copyright notice and this permission notice appear in all copies. 9 | * 10 | * the software is provided "as is" and the author disclaims all warranties 11 | * with regard to this software including all implied warranties of 12 | * merchantability and fitness. in no event shall the author be liable for 13 | * any special, direct, indirect, or consequential damages or any damages 14 | * whatsoever resulting from loss of use, data or profits, whether in an 15 | * action of contract, negligence or other tortious action, arising out of 16 | * or in connection with the use or performance of this software. 17 | * 18 | */ 19 | `default_nettype none `timescale 1 ns / 100 ps 20 | `include "riscv_defines.vh" 21 | module multiplier_decoder ( 22 | input wire [ 2:0] funct3, 23 | output reg [`MUL_OP_WIDTH -1:0] MULop, 24 | input wire mul_ext_valid, 25 | output wire mul_valid 26 | ); 27 | 28 | wire is_mul = funct3 == 3'b000; 29 | wire is_mulh = funct3 == 3'b001; 30 | wire is_mulsu = funct3 == 3'b010; 31 | wire is_mulu = funct3 == 3'b011; 32 | reg valid; 33 | 34 | assign mul_valid = valid & mul_ext_valid; 35 | always @(*) begin 36 | valid = 1'b1; 37 | case (1'b1) 38 | is_mul: MULop = `MUL_OP_MUL; 39 | is_mulh: MULop = `MUL_OP_MULH; 40 | is_mulsu: MULop = `MUL_OP_MULSU; 41 | is_mulu: MULop = `MUL_OP_MULU; 42 | default: begin 43 | /* verilator lint_off WIDTH */ 44 | MULop = 'hxx; 45 | /* verilator lint_on WIDTH */ 46 | valid = 1'b0; 47 | end 48 | endcase 49 | end 50 | 51 | endmodule 52 | -------------------------------------------------------------------------------- /Hardware/KianV-Icestudio/Level-02/multiplier_extension_decoder.v: -------------------------------------------------------------------------------- 1 | /* 2 | * kianv harris multicycle RISC-V rv32im 3 | * 4 | * copyright (c) 2022 hirosh dabui 5 | * 6 | * permission to use, copy, modify, and/or distribute this software for any 7 | * purpose with or without fee is hereby granted, provided that the above 8 | * copyright notice and this permission notice appear in all copies. 9 | * 10 | * the software is provided "as is" and the author disclaims all warranties 11 | * with regard to this software including all implied warranties of 12 | * merchantability and fitness. in no event shall the author be liable for 13 | * any special, direct, indirect, or consequential damages or any damages 14 | * whatsoever resulting from loss of use, data or profits, whether in an 15 | * action of contract, negligence or other tortious action, arising out of 16 | * or in connection with the use or performance of this software. 17 | * 18 | */ 19 | `default_nettype none `timescale 1 ns / 100 ps 20 | `include "riscv_defines.vh" 21 | module multiplier_extension_decoder ( 22 | input wire [ 2:0] funct3, 23 | output wire [`MUL_OP_WIDTH -1:0] MULop, 24 | output wire [`DIV_OP_WIDTH -1:0] DIVop, 25 | input wire mul_ext_valid, 26 | output wire mul_valid, 27 | output wire div_valid 28 | ); 29 | 30 | multiplier_decoder multiplier_I ( 31 | funct3, 32 | MULop, 33 | mul_ext_valid, 34 | mul_valid 35 | ); 36 | divider_decoder divider_decoder_I ( 37 | funct3, 38 | DIVop, 39 | mul_ext_valid, 40 | div_valid 41 | ); 42 | 43 | endmodule 44 | -------------------------------------------------------------------------------- /Hardware/KianV-Icestudio/Level-02/register_file.v: -------------------------------------------------------------------------------- 1 | /* 2 | * kianv harris multicycle RISC-V rv32ima 3 | * 4 | * copyright (c) 2023 hirosh dabui 5 | * 6 | * permission to use, copy, modify, and/or distribute this software for any 7 | * purpose with or without fee is hereby granted, provided that the above 8 | * copyright notice and this permission notice appear in all copies. 9 | * 10 | * the software is provided "as is" and the author disclaims all warranties 11 | * with regard to this software including all implied warranties of 12 | * merchantability and fitness. in no event shall the author be liable for 13 | * any special, direct, indirect, or consequential damages or any damages 14 | * whatsoever resulting from loss of use, data or profits, whether in an 15 | * action of contract, negligence or other tortious action, arising out of 16 | * or in connection with the use or performance of this software. 17 | * 18 | */ 19 | `default_nettype none `timescale 1 ns / 100 ps 20 | 21 | module register_file #( 22 | parameter REGISTER_DEPTH = 32, // rv32e = 16; rv32i = 32 23 | parameter STACKADDR = 32'hffff_ffff 24 | ) ( 25 | input wire clk, 26 | input wire we, 27 | input wire [ 4:0] A1, 28 | input wire [ 4:0] A2, 29 | input wire [ 4:0] A3, 30 | input wire [31:0] wd, 31 | output wire [31:0] rd1, 32 | output wire [31:0] rd2 33 | ); 34 | reg [31:0] bank0[0:REGISTER_DEPTH -1]; 35 | integer i; 36 | 37 | localparam X2 = 2; 38 | initial begin 39 | bank0[10] = 'h00; // hartid 40 | bank0[11] = 32'h80_000_000 + ((1024*1024*32)-2048);// 32'h81fffa00; // dtb 41 | end 42 | 43 | 44 | always @(posedge clk) begin 45 | 46 | if (we && A3 != 0) begin 47 | bank0[A3] <= wd; 48 | end 49 | end 50 | 51 | assign rd1 = A1 != 0 ? bank0[A1] : 32'b0; 52 | assign rd2 = A2 != 0 ? bank0[A2] : 32'b0; 53 | 54 | endmodule 55 | -------------------------------------------------------------------------------- /Hardware/KianV-Icestudio/Level-02/rv32_amo_opcodes.vh: -------------------------------------------------------------------------------- 1 | /* 2 | * kianv harris multicycle RISC-V rv32im 3 | * 4 | * copyright (c) 2023 hirosh dabui 5 | * 6 | * permission to use, copy, modify, and/or distribute this software for any 7 | * purpose with or without fee is hereby granted, provided that the above 8 | * copyright notice and this permission notice appear in all copies. 9 | * 10 | * the software is provided "as is" and the author disclaims all warranties 11 | * with regard to this software including all implied warranties of 12 | * merchantability and fitness. in no event shall the author be liable for 13 | * any special, direct, indirect, or consequential damages or any damages 14 | * whatsoever resulting from loss of use, data or profits, whether in an 15 | * action of contract, negligence or other tortious action, arising out of 16 | * or in connection with the use or performance of this software. 17 | */ 18 | `define RV32_AMO_OPCODE 7'h2F 19 | `define RV32_AMO_FUNCT3 3'h2 20 | `define RV32_AMOADD_W 5'h00 21 | `define RV32_AMOSWAP_W 5'h01 22 | `define RV32_LR_W 5'h02 23 | `define RV32_SC_W 5'h03 24 | `define RV32_AMOXOR_W 5'h04 25 | `define RV32_AMOAND_W 5'h0C 26 | `define RV32_AMOOR_W 5'h08 27 | `define RV32_AMOMIN_W 5'h10 28 | `define RV32_AMOMAX_W 5'h14 29 | `define RV32_AMOMINU_W 5'h18 30 | `define RV32_AMOMAXU_W 5'h1c 31 | `define RV32_FENCE_OPCODE 7'b0001111 32 | 33 | /* verilog_format: off */ 34 | `define RV32_IS_AMO_INSTRUCTION(opcode, funct3) (opcode == `RV32_AMO_OPCODE && funct3 == `RV32_AMO_FUNCT3) 35 | `define RV32_IS_AMOADD_W(funct5) (funct5 == `RV32_AMOADD_W) 36 | `define RV32_IS_AMOSWAP_W(funct5) (funct5 == `RV32_AMOSWAP_W) 37 | `define RV32_IS_LR_W(funct5) (funct5 == `RV32_LR_W) 38 | `define RV32_IS_SC_W(funct5) (funct5 == `RV32_SC_W) 39 | `define RV32_IS_AMOXOR_W(funct5) ( funct5 == `RV32_AMOXOR_W) 40 | `define RV32_IS_AMOAND_W(funct5) ( funct5 == `RV32_AMOAND_W) 41 | `define RV32_IS_AMOOR_W(funct5) ( funct5 == `RV32_AMOOR_W) 42 | `define RV32_IS_AMOMIN_W(funct5) ( funct5 == `RV32_AMOMIN_W) 43 | `define RV32_IS_AMOMAX_W(funct5) ( funct5 == `RV32_AMOMAX_W) 44 | `define RV32_IS_AMOMINU_W(funct5) ( funct5 == `RV32_AMOMINU_W) 45 | `define RV32_IS_AMOMAXU_W(funct5) ( funct5 == `RV32_AMOMAXU_W) 46 | `define RV32_IS_FENCE(opcode) ( opcode == `RV32_FENCE_OPCODE) 47 | /* verilog_format: on */ 48 | -------------------------------------------------------------------------------- /Hardware/KianV-Icestudio/Level-02/store_alignment.v: -------------------------------------------------------------------------------- 1 | /* 2 | * kianv harris multicycle RISC-V rv32im 3 | * 4 | * copyright (c) 2022 hirosh dabui 5 | * 6 | * permission to use, copy, modify, and/or distribute this software for any 7 | * purpose with or without fee is hereby granted, provided that the above 8 | * copyright notice and this permission notice appear in all copies. 9 | * 10 | * the software is provided "as is" and the author disclaims all warranties 11 | * with regard to this software including all implied warranties of 12 | * merchantability and fitness. in no event shall the author be liable for 13 | * any special, direct, indirect, or consequential damages or any damages 14 | * whatsoever resulting from loss of use, data or profits, whether in an 15 | * action of contract, negligence or other tortious action, arising out of 16 | * or in connection with the use or performance of this software. 17 | * 18 | */ 19 | `default_nettype none `timescale 1 ns / 100 ps 20 | 21 | `include "riscv_defines.vh" 22 | 23 | module store_alignment ( 24 | input wire [ 1:0] addr, 25 | input wire [`STORE_OP_WIDTH -1:0] STOREop, 26 | input wire [ 31:0] data, 27 | output reg [ 31:0] result, 28 | output reg [ 3:0] wmask, 29 | output reg unaligned_access 30 | ); 31 | 32 | always @* begin 33 | unaligned_access = 1'b0; 34 | wmask = 0; 35 | result = 'hx; 36 | 37 | case (STOREop) 38 | (`STORE_OP_SB): begin 39 | result[7:0] = addr[1:0] == 2'b00 ? data[7:0] : 8'hx; 40 | result[15:8] = addr[1:0] == 2'b01 ? data[7:0] : 8'hx; 41 | result[23:16] = addr[1:0] == 2'b10 ? data[7:0] : 8'hx; 42 | result[31:24] = addr[1:0] == 2'b11 ? data[7:0] : 8'hx; 43 | wmask = addr[1:0] == 2'b00 ? 4'b 0001 : 44 | addr[1:0] == 2'b01 ? 4'b 0010 : 45 | addr[1:0] == 2'b10 ? 4'b 0100 : 4'b 1000; 46 | unaligned_access = 1'b0; 47 | end 48 | (`STORE_OP_SH): begin 49 | result[15:0] = ~addr[1] ? data[15:0] : 16'hx; 50 | result[31:16] = addr[1] ? data[15:0] : 16'hx; 51 | wmask = addr[1] ? 4'b1100 : 4'b0011; 52 | unaligned_access = addr[0]; 53 | end 54 | (`STORE_OP_SW): begin 55 | result = data; 56 | wmask = 4'b1111; 57 | unaligned_access = addr[1:0] != 2'b00; 58 | end 59 | default: begin 60 | result = 'hx; 61 | wmask = 4'b0000; 62 | unaligned_access = 1'b0; 63 | end 64 | endcase 65 | 66 | end 67 | endmodule 68 | -------------------------------------------------------------------------------- /Hardware/KianV-Icestudio/Level-02/store_decoder.v: -------------------------------------------------------------------------------- 1 | /* 2 | * kianv harris multicycle RISC-V rv32im 3 | * 4 | * copyright (c) 2022 hirosh dabui 5 | * 6 | * permission to use, copy, modify, and/or distribute this software for any 7 | * purpose with or without fee is hereby granted, provided that the above 8 | * copyright notice and this permission notice appear in all copies. 9 | * 10 | * the software is provided "as is" and the author disclaims all warranties 11 | * with regard to this software including all implied warranties of 12 | * merchantability and fitness. in no event shall the author be liable for 13 | * any special, direct, indirect, or consequential damages or any damages 14 | * whatsoever resulting from loss of use, data or profits, whether in an 15 | * action of contract, negligence or other tortious action, arising out of 16 | * or in connection with the use or performance of this software. 17 | * 18 | */ 19 | `default_nettype none 20 | `timescale 1 ns/100 ps 21 | `include "riscv_defines.vh" 22 | module store_decoder 23 | ( 24 | input wire [ 2: 0] funct3, 25 | input wire amo_store_op, 26 | output reg [`STORE_OP_WIDTH -1: 0] STOREop 27 | ); 28 | wire is_sb = funct3[1:0] == 2'b 00; 29 | wire is_sh = funct3[1:0] == 2'b 01; 30 | wire is_sw = funct3[1:0] == 2'b 10; 31 | 32 | always @(*) begin 33 | if (!amo_store_op) begin 34 | case (1'b1) 35 | is_sb : STOREop = `STORE_OP_SB; 36 | is_sh : STOREop = `STORE_OP_SH; 37 | is_sw : STOREop = `STORE_OP_SW; 38 | default: 39 | /* verilator lint_off WIDTH */ 40 | STOREop = 'hxx; 41 | /* verilator lint_on WIDTH */ 42 | endcase 43 | end else begin 44 | STOREop = `STORE_OP_SW; 45 | end 46 | end 47 | 48 | endmodule 49 | -------------------------------------------------------------------------------- /Hardware/KianV-Icestudio/flash.sh: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | 3 | #-- Flash blinky! 4 | #-- 1. Build the circuit with icestudio 5 | #-- 2. Execute this script for storing the circuit in the flash 6 | #-- (Icestudio upload button load it directly on the FPGA (no flash)) 7 | 8 | apio raw "fujprog -l 4 -j FLASH ice-build/Blinky/hardware.bit" -------------------------------------------------------------------------------- /Images/Linux-anim-1.gif: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/FPGAwars/FLIX-V/d8c229dc90be4a3b2e37252a53767d06c394f755/Images/Linux-anim-1.gif -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # FLIX-V 2 | FLIX-V: FPGA, Linux and RISC-V 3 | 4 | Learning about how to run Linux on no-mmu RISC-V processors on Open Source FPGAs 5 | It is amazing how now we can learn what is happening from the bits to the Linux 6 | 7 | It was a dream to run Linux (open source software) on a Open source processor (RISC-V). Everything build with open source tools (the hardware and the software). It also amazing to see it running on open hardware boards, that in turn, have been designed using open source tools 8 | 9 | * **Board**: [Radiona ULX3S-12F](https://radiona.org/ulx3s/) 10 | 11 | ![Radiona ULX3S-12F](Demo/Images/Radiona-ULX3S-12F-2.jpg) 12 | 13 | ![Linux animation](Images/Linux-anim-1.gif) 14 | 15 | ## How to try 16 | 17 | Follow the [instructions given in the Demo folder](Demo/README.md) 18 | 19 | ## Credits 20 | * Based on this work: [KianRiscV](https://github.com/splinedrive/kianRiscV) by @splinedrive 21 | 22 | --------------------------------------------------------------------------------