├── .github └── workflows │ └── build-and-release.yaml ├── .gitignore ├── .vscode ├── settings.json └── tasks.json ├── LICENSE ├── README.md ├── VERSION ├── _boards_full.csv ├── _boards_issues_only.csv ├── _examples_full.csv ├── _examples_issues_only.csv ├── build.sh ├── clean_examples.sh ├── examples ├── alchitry-cu │ └── blinky │ │ ├── apio.ini │ │ ├── blinky.v │ │ ├── blinky_tb.gtkw │ │ ├── blinky_tb.v │ │ ├── info │ │ └── pinout.pcf ├── alhambra-ii │ ├── bcd-counter-sv │ │ ├── apio.ini │ │ ├── bcd │ │ │ ├── bcd_digit.sv │ │ │ ├── bcd_digit_tb.gtkw │ │ │ └── bcd_digit_tb.sv │ │ ├── info │ │ ├── main.sv │ │ ├── main_tb.gtkw │ │ ├── main_tb.sv │ │ ├── pinout.pcf │ │ ├── testing │ │ │ └── apio_testing.vh │ │ └── util │ │ │ ├── reset_gen.sv │ │ │ ├── ticker.sv │ │ │ ├── ticker_tb.gtkw │ │ │ └── ticker_tb.sv │ ├── bcd-counter │ │ ├── apio.ini │ │ ├── bcd │ │ │ ├── bcd_digit.v │ │ │ ├── bcd_digit_tb.gtkw │ │ │ └── bcd_digit_tb.v │ │ ├── info │ │ ├── main.v │ │ ├── main_tb.gtkw │ │ ├── main_tb.v │ │ ├── pinout.pcf │ │ ├── testing │ │ │ └── apio_testing.vh │ │ └── util │ │ │ ├── reset_gen.v │ │ │ ├── ticker.v │ │ │ ├── ticker_tb.gtkw │ │ │ └── ticker_tb.v │ ├── blinky │ │ ├── apio.ini │ │ ├── blinky.v │ │ ├── info │ │ └── pinout.pcf │ ├── getting-started │ │ ├── apio.ini │ │ ├── info │ │ ├── main.v │ │ ├── main_tb.gtkw │ │ ├── main_tb.v │ │ └── pinout.pcf │ ├── ledon │ │ ├── apio.ini │ │ ├── info │ │ ├── ledon.v │ │ ├── ledon_tb.gtkw │ │ ├── ledon_tb.v │ │ └── pinout.pcf │ ├── multienv │ │ ├── apio.ini │ │ ├── apio_testing.vh │ │ ├── info │ │ ├── main.v │ │ ├── main_tb.gtkw │ │ ├── main_tb.v │ │ └── pinout.pcf │ ├── prog-cmd │ │ ├── apio.ini │ │ ├── blinky.v │ │ ├── info │ │ └── pinout.pcf │ └── template │ │ ├── apio.ini │ │ ├── info │ │ ├── pinout.pcf │ │ └── test.v ├── blackice │ ├── blink │ │ ├── Readme.md │ │ ├── apio.ini │ │ ├── blackice-setup.jpg │ │ ├── blink.pcf │ │ ├── blink.v │ │ └── info │ └── blinky │ │ ├── Blinky.v │ │ ├── apio.ini │ │ ├── blackice.pcf │ │ └── info ├── colorlight-5a-75b-v8 │ ├── blinky │ │ ├── apio.ini │ │ ├── blinky.v │ │ ├── info │ │ └── pinout.lpf │ ├── ledon-sv │ │ ├── apio.ini │ │ ├── info │ │ ├── ledon.sv │ │ ├── ledon_tb.gtkw │ │ ├── ledon_tb.sv │ │ └── pinout.lpf │ └── ledon │ │ ├── apio.ini │ │ ├── info │ │ ├── ledon.v │ │ ├── ledon_tb.gtkw │ │ ├── ledon_tb.v │ │ └── pinout.lpf ├── colorlight-5a-75e-v71-ft2232h │ ├── blinky │ │ ├── apio.ini │ │ ├── blinky.v │ │ ├── info │ │ └── pinout.lpf │ └── ledon │ │ ├── apio.ini │ │ ├── info │ │ ├── ledon.v │ │ └── pinout.lpf ├── cynthion-r1-4 │ └── blinky │ │ ├── Cynthion-r1.4.lpf │ │ ├── apio.ini │ │ ├── blinky.v │ │ └── info ├── edu-ciaa-fpga │ ├── and-gate-sv │ │ ├── and_gate.pcf │ │ ├── and_gate.sv │ │ ├── and_gate_tb.gtkw │ │ ├── and_gate_tb.sv │ │ ├── apio.ini │ │ └── info │ ├── blinky │ │ ├── Blinky.v │ │ ├── apio.ini │ │ ├── info │ │ └── pinout.pcf │ ├── led-green │ │ ├── apio.ini │ │ ├── info │ │ ├── led_green.pcf │ │ └── led_green.v │ └── template │ │ ├── apio.ini │ │ ├── info │ │ ├── pinout.pcf │ │ └── test.v ├── fomu │ ├── blink │ │ ├── apio.ini │ │ ├── blink.v │ │ ├── info │ │ └── pinout.pcf │ └── dsp │ │ ├── apio.ini │ │ ├── apio_testing.vh │ │ ├── info │ │ ├── main.v │ │ ├── main_tb.gtkw │ │ ├── main_tb.v │ │ └── pinout.pcf ├── go-board │ ├── blinky │ │ ├── Blinky.v │ │ ├── apio.ini │ │ ├── go-board.pcf │ │ └── info │ ├── leds │ │ ├── apio.ini │ │ ├── info │ │ ├── leds.pcf │ │ ├── leds.v │ │ ├── leds_tb.gtkw │ │ └── leds_tb.v │ └── template │ │ ├── apio.ini │ │ ├── go-board.pcf │ │ ├── info │ │ ├── main.v │ │ ├── main_tb.gtkw │ │ └── main_tb.v ├── ice40-hx1k-evb │ └── leds │ │ ├── apio.ini │ │ ├── info │ │ ├── leds.pcf │ │ ├── leds.v │ │ ├── leds_tb.gtkw │ │ └── leds_tb.v ├── ice40-hx8k-evb │ └── leds │ │ ├── apio.ini │ │ ├── info │ │ ├── leds.pcf │ │ ├── leds.v │ │ ├── leds_tb.gtkw │ │ └── leds_tb.v ├── ice40-hx8k │ └── leds │ │ ├── apio.ini │ │ ├── info │ │ ├── leds.pcf │ │ ├── leds.v │ │ ├── leds_tb.gtkw │ │ └── leds_tb.v ├── ice40-up5k │ ├── blinky │ │ ├── apio.ini │ │ ├── blink.v │ │ ├── info │ │ └── up5k.pcf │ ├── led-green │ │ ├── apio.ini │ │ ├── info │ │ ├── led-green.v │ │ └── up5k.pcf │ └── switches │ │ ├── apio.ini │ │ ├── info │ │ ├── switches.v │ │ └── up5k.pcf ├── icebreaker │ ├── blinky │ │ ├── apio.ini │ │ ├── blinky.v │ │ ├── icebreaker.pcf │ │ └── info │ ├── buttons │ │ ├── apio.ini │ │ ├── buttons.v │ │ ├── icebreaker.pcf │ │ └── info │ └── led-green │ │ ├── apio.ini │ │ ├── icebreaker.pcf │ │ ├── info │ │ └── led-green.v ├── icefun │ ├── blinky │ │ ├── apio.ini │ │ ├── info │ │ ├── main.v │ │ ├── main_tb.gtkw │ │ ├── main_tb.v │ │ └── pinout.pcf │ └── led-matrix │ │ ├── apio.ini │ │ ├── info │ │ ├── led_matrix.v │ │ ├── led_matrix_tb.gtkw │ │ ├── led_matrix_tb.v │ │ ├── main.v │ │ ├── main_tb.gtkw │ │ ├── main_tb.v │ │ ├── pinout.pcf │ │ ├── rand_gen.v │ │ ├── rand_gen_tb.gtkw │ │ └── rand_gen_tb.v ├── icestick │ ├── leds │ │ ├── apio.ini │ │ ├── info │ │ ├── leds.pcf │ │ ├── leds.v │ │ ├── leds_tb.gtkw │ │ └── leds_tb.v │ └── template │ │ ├── apio.ini │ │ ├── icestick.pcf │ │ ├── info │ │ ├── main.v │ │ ├── main_tb.gtkw │ │ └── main_tb.v ├── icesugar-1-5 │ └── blinky │ │ ├── apio.ini │ │ ├── blink.v │ │ ├── icesugar.pcf │ │ └── info ├── icewerx │ ├── blinky │ │ ├── Blinky.v │ │ ├── apio.ini │ │ ├── info │ │ └── pinout.pcf │ └── ledon │ │ ├── apio.ini │ │ ├── info │ │ ├── ledon.v │ │ ├── ledon_tb.gtkw │ │ ├── ledon_tb.v │ │ └── pinout.pcf ├── icezum │ ├── frere-jacques │ │ ├── README.md │ │ ├── apio.ini │ │ ├── divider.v │ │ ├── divider.vh │ │ ├── frerejacques.pcf │ │ ├── frerejacques.v │ │ ├── frerejacques_tb.gtkw │ │ ├── frerejacques_tb.v │ │ └── info │ ├── leds │ │ ├── apio.ini │ │ ├── info │ │ ├── leds.pcf │ │ ├── leds.v │ │ ├── leds_tb.gtkw │ │ └── leds_tb.v │ ├── marcha-imperial │ │ ├── Makefile │ │ ├── apio.ini │ │ ├── divider.vh │ │ ├── dividerp1.v │ │ ├── genrom.v │ │ ├── imperial.list │ │ ├── info │ │ ├── notas_gen.py │ │ ├── notegen.v │ │ ├── notegen.vh │ │ ├── rom1.list │ │ ├── romnotes.pcf │ │ ├── romnotes.v │ │ ├── romnotes_tb.gtkw │ │ └── romnotes_tb.v │ ├── template │ │ ├── apio.ini │ │ ├── icezum.pcf │ │ ├── info │ │ ├── main.v │ │ ├── main_tb.gtkw │ │ └── main_tb.v │ └── wire │ │ ├── apio.ini │ │ ├── info │ │ ├── wire.pcf │ │ ├── wire.v │ │ ├── wire_tb.gtkw │ │ └── wire_tb.v ├── kefir │ ├── leds │ │ ├── apio.ini │ │ ├── info │ │ ├── leds.pcf │ │ ├── leds.v │ │ ├── leds_tb.gtkw │ │ └── leds_tb.v │ └── template │ │ ├── apio.ini │ │ ├── info │ │ ├── kefir.pcf │ │ ├── main.v │ │ ├── main_tb.gtkw │ │ └── main_tb.v ├── sipeed-tang-nano-4k │ └── blinky │ │ ├── apio.ini │ │ ├── apio_testing.vh │ │ ├── blinky.cst │ │ ├── blinky.v │ │ ├── blinky_tb.gtkw │ │ ├── blinky_tb.v │ │ └── info ├── sipeed-tang-nano-9k │ ├── blinky-sv │ │ ├── apio.ini │ │ ├── apio_testing.svh │ │ ├── blinky.cst │ │ ├── blinky.sv │ │ ├── blinky_tb.gtkw │ │ ├── blinky_tb.sv │ │ └── info │ ├── blinky │ │ ├── apio.ini │ │ ├── apio_testing.vh │ │ ├── blinky.cst │ │ ├── blinky.v │ │ ├── blinky_tb.gtkw │ │ ├── blinky_tb.v │ │ └── info │ └── pll │ │ ├── apio.ini │ │ ├── apio_testing.vh │ │ ├── blinker.v │ │ ├── blinker_tb.gtkw │ │ ├── blinker_tb.v │ │ ├── info │ │ ├── main.cst │ │ ├── main.v │ │ └── pll.v ├── tinyfpga-b2 │ ├── blinky │ │ ├── Blink13.v │ │ ├── README.md │ │ ├── TinyFPGA-B2-pins.pcf │ │ ├── TinyFPGA-B2-setup.jpg │ │ ├── apio.ini │ │ └── info │ └── template │ │ ├── apio.ini │ │ ├── info │ │ ├── pins.pcf │ │ └── tinyfpga_b.v ├── tinyfpga-bx │ ├── blink-sos │ │ ├── BlinkSOS.v │ │ ├── README.me │ │ ├── TinyFPGA-BX-pins.pcf │ │ ├── apio.ini │ │ └── info │ ├── blinky │ │ ├── Blinky.v │ │ ├── TinyFPGA-BX-pins.pcf │ │ ├── apio.ini │ │ └── info │ ├── clock-divider │ │ ├── apio.ini │ │ ├── clock_divider.v │ │ ├── clock_divider_tb.gtkw │ │ ├── clock_divider_tb.v │ │ ├── info │ │ ├── pins.pcf │ │ └── top.v │ └── template │ │ ├── TinyFPGA_BX.v │ │ ├── apio.ini │ │ ├── info │ │ └── pins.pcf ├── ulx3s-12f │ ├── blinky │ │ ├── apio.ini │ │ ├── blinky.v │ │ ├── info │ │ └── ulx3s_v20.lpf │ └── ledon │ │ ├── apio.ini │ │ ├── info │ │ ├── ledon.v │ │ ├── ledon_tb.gtkw │ │ ├── ledon_tb.v │ │ └── ulx3s_v20.lpf ├── ulx3s-45f │ └── blinky │ │ ├── apio.ini │ │ ├── blinky.v │ │ ├── info │ │ └── ulx3s_v20.lpf ├── ulx3s-85f │ └── blinky │ │ ├── apio.ini │ │ ├── blinky.v │ │ ├── info │ │ └── ulx3s_v20.lpf └── upduino31 │ ├── blinky │ ├── apio.ini │ ├── info │ ├── leds.v │ ├── main.pcf │ ├── main.v │ └── oscilator.v │ ├── pll │ ├── .gitignore │ ├── apio.ini │ ├── info │ ├── leds.v │ ├── main.pcf │ ├── main.v │ └── pll.v │ └── testbench │ ├── apio.ini │ ├── apio_testing.vh │ ├── bcd_counter.v │ ├── info │ ├── main.pcf │ ├── main.v │ ├── main_tb.gtkw │ └── main_tb.v ├── format_examples.sh ├── scripts ├── __init__ ├── clean_examples.py ├── format_examples.py └── generate_reports.py └── update_reports.sh /.gitignore: -------------------------------------------------------------------------------- 1 | *.dblite 2 | *.asc 3 | *.bin 4 | *.blif 5 | *.vcd 6 | *.out 7 | hardware.json 8 | abc.history 9 | *.v~ 10 | hardware.bit 11 | hardware.config 12 | _build 13 | .run.sh 14 | VERSION_BUILD 15 | _package/ 16 | .DS_Store 17 | __pycache__ 18 | -------------------------------------------------------------------------------- /.vscode/settings.json: -------------------------------------------------------------------------------- 1 | { 2 | "cSpell.words": [ 3 | "apio", 4 | "localparam", 5 | "tinyfpga" 6 | ] 7 | } -------------------------------------------------------------------------------- /.vscode/tasks.json: -------------------------------------------------------------------------------- 1 | { 2 | // See https://go.microsoft.com/fwlink/?LinkId=733558 3 | // for the documentation about the tasks.json format 4 | "version": "2.0.0", 5 | "tasks": [ 6 | { 7 | "label": "Apio Build", 8 | "type": "shell", 9 | "command": "apio build", 10 | "options": { 11 | "cwd": "${workspaceFolder}/${relativeFileDirname}" 12 | }, 13 | "problemMatcher": [], 14 | "group": { 15 | "kind": "build", 16 | "isDefault": true 17 | } 18 | }, 19 | { 20 | "label": "Apio upload", 21 | "type": "shell", 22 | "command": "apio upload", 23 | "options": { 24 | "cwd": "${workspaceFolder}/${relativeFileDirname}" 25 | }, 26 | "problemMatcher": [] 27 | }, 28 | { 29 | "label": "Apio clean", 30 | "type": "shell", 31 | "command": "apio clean", 32 | "options": { 33 | "cwd": "${workspaceFolder}/${relativeFileDirname}" 34 | }, 35 | "problemMatcher": [] 36 | }, 37 | { 38 | "label": "Apio Sim", 39 | "type": "shell", 40 | "command": "apio sim", 41 | "options": { 42 | "cwd": "${workspaceFolder}/${relativeFileDirname}" 43 | }, 44 | "problemMatcher": [] 45 | } 46 | ] 47 | } 48 | -------------------------------------------------------------------------------- /VERSION: -------------------------------------------------------------------------------- 1 | 0.0.36 2 | -------------------------------------------------------------------------------- /_examples_issues_only.csv: -------------------------------------------------------------------------------- 1 | BOARD,EXAMPLE,NO-TESTBENCH 2 | alhambra-ii,blinky,X 3 | alhambra-ii,prog-cmd,X 4 | alhambra-ii,template,X 5 | blackice,blink,X 6 | blackice,blinky,X 7 | colorlight-5a-75b-v8,blinky,X 8 | colorlight-5a-75e-v71-ft2232h,blinky,X 9 | colorlight-5a-75e-v71-ft2232h,ledon,X 10 | cynthion-r1-4,blinky,X 11 | edu-ciaa-fpga,blinky,X 12 | edu-ciaa-fpga,led-green,X 13 | edu-ciaa-fpga,template,X 14 | fomu,blink,X 15 | go-board,blinky,X 16 | ice40-up5k,blinky,X 17 | ice40-up5k,led-green,X 18 | ice40-up5k,switches,X 19 | icebreaker,blinky,X 20 | icebreaker,buttons,X 21 | icebreaker,led-green,X 22 | icesugar-1-5,blinky,X 23 | icewerx,blinky,X 24 | tinyfpga-b2,blinky,X 25 | tinyfpga-b2,template,X 26 | tinyfpga-bx,blink-sos,X 27 | tinyfpga-bx,blinky,X 28 | tinyfpga-bx,template,X 29 | ulx3s-12f,blinky,X 30 | ulx3s-45f,blinky,X 31 | ulx3s-85f,blinky,X 32 | upduino31,blinky,X 33 | upduino31,pll,X 34 | -------------------------------------------------------------------------------- /clean_examples.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | # A shell script to clean the examples projects. 4 | # Requires python and apio. 5 | 6 | #cd scripts 7 | python scripts/clean_examples.py 8 | -------------------------------------------------------------------------------- /examples/alchitry-cu/blinky/apio.ini: -------------------------------------------------------------------------------- 1 | ; Apio project configuration file. 2 | ; Type 'apio info apio.ini' for details. 3 | 4 | [env:default] 5 | board = alchitry-cu 6 | top-module = blinky 7 | -------------------------------------------------------------------------------- /examples/alchitry-cu/blinky/blinky.v: -------------------------------------------------------------------------------- 1 | //blink all 8 leds on Alchitry-Cu Board 2 | 3 | module blinky #( 4 | // Default blink 1Hz. Can override in a testbench. 5 | parameter integer DELAY = 100000000 / 2 6 | ) ( 7 | //inputs 8 | input clk, //100MHz 9 | 10 | //outputs 11 | output reg [7:0] led = 8'b11111111 //start with all on 12 | ); 13 | 14 | // Blink counter. 15 | reg [26:0] count = 0; 16 | 17 | // Blink the leds 18 | always @(posedge clk) begin 19 | if (count >= DELAY[26:0]) begin 20 | if (led == 8'b0) begin //if off 21 | led <= 8'b11111111; //turn all leds on 22 | end else begin 23 | led <= 8'b0; // turn all leds off 24 | end 25 | count = 27'b0; //reset count 26 | end else begin 27 | count = count + 1'b1; 28 | end 29 | end 30 | 31 | endmodule 32 | -------------------------------------------------------------------------------- /examples/alchitry-cu/blinky/blinky_tb.gtkw: -------------------------------------------------------------------------------- 1 | [*] 2 | [*] GTKWave Analyzer v3.4.0 (w)1999-2022 BSI 3 | [*] Sat Dec 7 01:26:58 2024 4 | [*] 5 | [dumpfile] "/Volumes/projects/apio-examples/repo/examples/alchitry-cu/blinky/_build/blinky_tb.vcd" 6 | [dumpfile_mtime] "Sat Dec 7 01:24:07 2024" 7 | [dumpfile_size] 1274 8 | [savefile] "/Volumes/projects/apio-examples/repo/examples/alchitry-cu/blinky/blinky_tb.gtkw" 9 | [timestart] 0 10 | [size] 1328 786 11 | [pos] -1 -1 12 | *-20.002535 430000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 13 | [treeopen] blinky_tb. 14 | [sst_width] 253 15 | [signals_width] 95 16 | [sst_expanded] 1 17 | [sst_vpaned_height] 222 18 | @29 19 | [color] 2 20 | blinky_tb.clk 21 | @200 22 | - 23 | @800028 24 | blinky_tb.led[7:0] 25 | @28 26 | (0)blinky_tb.led[7:0] 27 | (1)blinky_tb.led[7:0] 28 | (2)blinky_tb.led[7:0] 29 | (3)blinky_tb.led[7:0] 30 | (4)blinky_tb.led[7:0] 31 | (5)blinky_tb.led[7:0] 32 | (6)blinky_tb.led[7:0] 33 | (7)blinky_tb.led[7:0] 34 | @1001208 35 | -group_end 36 | [pattern_trace] 1 37 | [pattern_trace] 0 38 | -------------------------------------------------------------------------------- /examples/alchitry-cu/blinky/blinky_tb.v: -------------------------------------------------------------------------------- 1 | 2 | // Testbench template 3 | 4 | `default_nettype none `timescale 10 ns / 1 ns 5 | 6 | 7 | module blinky_tb; 8 | 9 | // Input. 10 | reg clk = 0; 11 | 12 | // Output 13 | wire [7:0] led; 14 | 15 | // Module instance 16 | blinky #( 17 | .DELAY(5) 18 | ) dut ( 19 | .clk(clk), 20 | .led(led) 21 | ); 22 | 23 | initial begin 24 | // Dump vars to the output .vcd file 25 | $dumpvars(0, blinky_tb); 26 | 27 | repeat (50) begin 28 | #10 clk = ~clk; 29 | end 30 | 31 | $display("End of simulation"); 32 | $finish; 33 | end 34 | 35 | endmodule 36 | -------------------------------------------------------------------------------- /examples/alchitry-cu/blinky/info: -------------------------------------------------------------------------------- 1 | Blinking all leds -------------------------------------------------------------------------------- /examples/alchitry-cu/blinky/pinout.pcf: -------------------------------------------------------------------------------- 1 | # ----------------------------------------------------------------------------- 2 | #- Blinky example for the Alchitry-Cu board (cb132) 3 | #- Constraint file (.pcf) 4 | #- By Reid Holderfield 5 | #- April - 2023 6 | #- GPL license 7 | # ----------------------------------------------------------------------------- 8 | # -- Pinout: 9 | # -- Guide: 10 | 11 | 12 | # clk 13 | set_io clk P7 #81_gbin5 14 | 15 | # leds 16 | set_io led[0] J11 #D2 17 | set_io led[1] K11 #.. 18 | set_io led[2] K12 #.. 19 | set_io led[3] K14 #.. 20 | set_io led[4] L12 #.. 21 | set_io led[5] L14 #.. 22 | set_io led[6] M12 #.. 23 | set_io led[7] N14 #D9 24 | -------------------------------------------------------------------------------- /examples/alhambra-ii/bcd-counter-sv/apio.ini: -------------------------------------------------------------------------------- 1 | ; Apio project configuration file. 2 | ; Type 'apio info apio.ini' for details. 3 | 4 | [env:default] 5 | board = alhambra-ii 6 | top-module = main 7 | 8 | ; When running 'apio sim' without specifying the testbench. 9 | default-testbench = main_tb.sv 10 | 11 | -------------------------------------------------------------------------------- /examples/alhambra-ii/bcd-counter-sv/bcd/bcd_digit.sv: -------------------------------------------------------------------------------- 1 | // A single cascadable decimal digit counter, 0-9. 2 | 3 | module bcd_digit ( 4 | input wire sys_clk, // Continious system clock. 5 | input wire sys_reset, // Syncrhonous global reset. 6 | input wire tick_in, // When high, counting one step. 7 | output wire tick_out, // When high, higher order digit should count. 8 | output reg [3:0] count // Count output, 0-9. 9 | ); 10 | 11 | // Cascading tick condition. 12 | assign tick_out = (count == 9) && tick_in; 13 | 14 | // Sequential logic. 15 | always @(posedge sys_clk) begin 16 | if (sys_reset) begin 17 | // Case 1: Reset. 18 | count <= 0; 19 | end else if (tick_in) begin 20 | // Case 2: Count modulue 10 21 | count <= count >= 9 ? 0 : count + 1; 22 | end 23 | end 24 | 25 | endmodule 26 | 27 | 28 | -------------------------------------------------------------------------------- /examples/alhambra-ii/bcd-counter-sv/bcd/bcd_digit_tb.gtkw: -------------------------------------------------------------------------------- 1 | [*] 2 | [*] GTKWave Analyzer v3.4.0 (w)1999-2022 BSI 3 | [*] Sat Dec 28 03:24:05 2024 4 | [*] 5 | [dumpfile] "/Volumes/projects/apio-examples/repo/examples/alhambra-ii/bcd-counter/_build/bcd_digit_tb.vcd" 6 | [dumpfile_mtime] "Sat Dec 28 03:22:45 2024" 7 | [dumpfile_size] 4396 8 | [savefile] "/Volumes/projects/apio-examples/repo/examples/alhambra-ii/bcd-counter/bcd_digit_tb.gtkw" 9 | [timestart] 0 10 | [size] 1384 772 11 | [pos] -1 -1 12 | *-21.796194 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 13 | [treeopen] bcd_digit_tb. 14 | [sst_width] 253 15 | [signals_width] 111 16 | [sst_expanded] 1 17 | [sst_vpaned_height] 218 18 | @24 19 | bcd_digit_tb.clk_num 20 | @28 21 | bcd_digit_tb.clk 22 | bcd_digit_tb.reset 23 | bcd_digit_tb.tick_in 24 | @200 25 | - 26 | @22 27 | [color] 3 28 | bcd_digit_tb.count[3:0] 29 | @29 30 | [color] 3 31 | bcd_digit_tb.tick_out 32 | [pattern_trace] 1 33 | [pattern_trace] 0 34 | -------------------------------------------------------------------------------- /examples/alhambra-ii/bcd-counter-sv/bcd/bcd_digit_tb.sv: -------------------------------------------------------------------------------- 1 | // A testbench for testing the bcd_digit module. 2 | 3 | `include "testing/apio_testing.vh" 4 | 5 | `timescale 10 ns / 1 ns 6 | 7 | module bcd_digit_tb (); 8 | 9 | // This defines a managed signal called 'clk'. 10 | `DEF_CLK 11 | 12 | // Inputs. 13 | reg reset = 1; 14 | reg tick_in = 0; 15 | 16 | // Outputs. 17 | wire tick_out; 18 | wire [3:0] count; 19 | 20 | bcd_digit digit( 21 | .sys_clk(clk), 22 | .sys_reset(reset), 23 | .tick_in(tick_in), 24 | .tick_out(tick_out), 25 | .count(count) 26 | ); 27 | 28 | initial begin 29 | // Start the test. 30 | `TEST_BEGIN(bcd_digit_tb) 31 | 32 | // Reset for 2 clocks. 33 | `CLKS(2) 34 | reset = 0; 35 | 36 | // Count 15 times 37 | repeat(15) begin 38 | `CLKS(2) 39 | tick_in = 1; 40 | `CLK 41 | tick_in =0; 42 | `CLKS(3) 43 | end 44 | 45 | // Assert on ethe xpected digit value. 46 | `EXPECT(count, 15 % 10) 47 | 48 | // End of test. 49 | `TEST_END 50 | end 51 | 52 | endmodule 53 | -------------------------------------------------------------------------------- /examples/alhambra-ii/bcd-counter-sv/info: -------------------------------------------------------------------------------- 1 | System Verilog example with testbenches and subdirectories. 2 | -------------------------------------------------------------------------------- /examples/alhambra-ii/bcd-counter-sv/main.sv: -------------------------------------------------------------------------------- 1 | // A design that controls the 8 leds with a two digit decimal counter. 2 | 3 | module main #( 4 | // The dividing factor to reach 1 hz from 12Mhz clock. By defining 5 | // it as a parameter we can reduce it in testbench simulations. 6 | parameter integer DIV = 12000000 7 | ) ( 8 | input logic CLK, // 12MHz clock 9 | output logic [7:0] LEDS // LED to blink 10 | ); 11 | 12 | // Global reset from the reset generator. 13 | wire sys_reset; 14 | 15 | // Cascading count ticks. 16 | wire tick1; 17 | wire tick2; 18 | wire tick3; 19 | 20 | // Global reset generator. 21 | reset_gen reset_gen ( 22 | .sys_clk (CLK), 23 | .sys_reset(sys_reset) 24 | ); 25 | 26 | // Timing generator. Tick is 27 | ticker #( 28 | .DIV(DIV) 29 | ) ticker ( 30 | .sys_clk(CLK), 31 | .sys_reset(sys_reset), 32 | .tick(tick1) 33 | ); 34 | 35 | // The units digit counter. 36 | bcd_digit digit1 ( 37 | .sys_clk(CLK), 38 | .sys_reset(sys_reset), 39 | .tick_in(tick1), 40 | .tick_out(tick2), 41 | .count(LEDS[3:0]) 42 | ); 43 | 44 | // The tens digit counter. 45 | bcd_digit digit2 ( 46 | .sys_clk(CLK), 47 | .sys_reset(sys_reset), 48 | .tick_in(tick2), 49 | .tick_out(tick3), 50 | .count(LEDS[7:4]) 51 | ); 52 | 53 | 54 | 55 | 56 | endmodule 57 | 58 | 59 | -------------------------------------------------------------------------------- /examples/alhambra-ii/bcd-counter-sv/main_tb.gtkw: -------------------------------------------------------------------------------- 1 | [*] 2 | [*] GTKWave Analyzer v3.4.0 (w)1999-2022 BSI 3 | [*] Sun Dec 29 20:00:53 2024 4 | [*] 5 | [dumpfile] "/Volumes/projects/apio-examples/repo/examples/alhambra-ii/bcd-counter/_build/main_tb.vcd" 6 | [dumpfile_mtime] "Sun Dec 29 19:55:56 2024" 7 | [dumpfile_size] 22930 8 | [savefile] "/Volumes/projects/apio-examples/repo/examples/alhambra-ii/bcd-counter/main_tb.gtkw" 9 | [timestart] 0 10 | [size] 1408 701 11 | [pos] -1 -1 12 | *-23.910471 7480000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 13 | [treeopen] main_tb. 14 | [treeopen] main_tb.main. 15 | [sst_width] 253 16 | [signals_width] 111 17 | [sst_expanded] 1 18 | [sst_vpaned_height] 191 19 | @200 20 | -System 21 | @420 22 | main_tb.clk_num 23 | @28 24 | main_tb.clk 25 | main_tb.main.reset_gen.sys_reset 26 | @200 27 | - 28 | -Digit 1 29 | @28 30 | main_tb.main.tick1 31 | @8022 32 | [color] 3 33 | main_tb.main.digit1.count[3:0] 34 | @28 35 | main_tb.main.tick2 36 | @200 37 | - 38 | -Digit 2 39 | @28 40 | main_tb.main.tick2 41 | @24 42 | [color] 3 43 | main_tb.main.digit2.count[3:0] 44 | @28 45 | main_tb.main.tick3 46 | [pattern_trace] 1 47 | [pattern_trace] 0 48 | -------------------------------------------------------------------------------- /examples/alhambra-ii/bcd-counter-sv/main_tb.sv: -------------------------------------------------------------------------------- 1 | // A testbench of main.v. 2 | 3 | // Import apio friendly testing macros. 4 | `include "testing/apio_testing.vh" 5 | 6 | `timescale 10 ns / 1 ns 7 | 8 | module main_tb (); 9 | 10 | // This defines a managed signal called 'clk'. 11 | `DEF_CLK 12 | 13 | // Module's output. 14 | wire [7:0] leds; 15 | 16 | main #( 17 | .DIV(3) 18 | ) main ( 19 | .CLK (clk), 20 | .LEDS(leds) 21 | ); 22 | 23 | initial begin 24 | `TEST_BEGIN(main_tb) 25 | 26 | // Free run for 400 clocks. 27 | `CLKS(400) 28 | 29 | // Assert on expected bcd value. 30 | `EXPECT(leds, 'h31) 31 | 32 | `TEST_END 33 | end 34 | 35 | endmodule 36 | -------------------------------------------------------------------------------- /examples/alhambra-ii/bcd-counter-sv/util/reset_gen.sv: -------------------------------------------------------------------------------- 1 | // A module that generates a syncrhonous reset on start. 2 | 3 | module reset_gen ( 4 | input sys_clk, 5 | output reg sys_reset 6 | ); 7 | 8 | // Relying on ICE40 behavior of reseting all DFF on power on reset. 9 | reg [2:0] counter = 0; 10 | 11 | always @(posedge sys_clk) begin 12 | if (counter < 3) begin 13 | // Reset active. 14 | sys_reset <= 1; 15 | counter <= counter + 1; 16 | end else begin 17 | // Reset inactive. 18 | sys_reset <= 0; 19 | end 20 | end 21 | 22 | endmodule 23 | -------------------------------------------------------------------------------- /examples/alhambra-ii/bcd-counter-sv/util/ticker.sv: -------------------------------------------------------------------------------- 1 | // A module that provide the counter tick signal. 2 | // The tick output is high for one clock every one second. 3 | 4 | module ticker #( 5 | // The number of clocks per tick. Controls the tick speed. 6 | // Verilog require that we will specify here a value even though we 7 | // override it in main.v. 8 | parameter integer DIV = 12000000 9 | ) ( 10 | input wire sys_clk, // 12MHz clock 11 | input wire sys_reset, // Syncrhonous global reset 12 | output reg tick // High for one clock every DIF clocks. 13 | ); 14 | 15 | // Clock divider counter. 16 | reg [31:0] counter = 0; 17 | 18 | // Sequential logic. 19 | always @(posedge sys_clk) begin 20 | if (sys_reset) begin 21 | // Case 1: Reset. 22 | counter <= 0; 23 | tick <= 0; 24 | end else if (counter >= (DIV - 1)) begin 25 | // Case 2: Cycle end. 26 | counter <= 0; 27 | tick <= 1; 28 | end else begin 29 | // Case 3: Normal increment. 30 | counter <= counter + 1; 31 | tick <= 0; 32 | end 33 | end 34 | 35 | endmodule 36 | 37 | 38 | -------------------------------------------------------------------------------- /examples/alhambra-ii/bcd-counter-sv/util/ticker_tb.gtkw: -------------------------------------------------------------------------------- 1 | [*] 2 | [*] GTKWave Analyzer v3.4.0 (w)1999-2022 BSI 3 | [*] Sat Dec 28 04:52:05 2024 4 | [*] 5 | [dumpfile] "/Volumes/projects/apio-examples/repo/examples/alhambra-ii/bcd-counter/_build/ticker_tb.vcd" 6 | [dumpfile_mtime] "Sat Dec 28 04:51:45 2024" 7 | [dumpfile_size] 1814 8 | [savefile] "/Volumes/projects/apio-examples/repo/examples/alhambra-ii/bcd-counter/ticker_tb.gtkw" 9 | [timestart] 0 10 | [size] 1272 600 11 | [pos] -1 -1 12 | *-20.536083 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 13 | [treeopen] ticker_tb. 14 | [sst_width] 253 15 | [signals_width] 136 16 | [sst_expanded] 1 17 | [sst_vpaned_height] 158 18 | @28 19 | ticker_tb.clk 20 | ticker_tb.reset 21 | @24 22 | ticker_tb.ticker.counter[31:0] 23 | @200 24 | - 25 | @29 26 | [color] 3 27 | ticker_tb.tick 28 | [pattern_trace] 1 29 | [pattern_trace] 0 30 | -------------------------------------------------------------------------------- /examples/alhambra-ii/bcd-counter-sv/util/ticker_tb.sv: -------------------------------------------------------------------------------- 1 | // A testbench for testing the ticker module. 2 | 3 | `include "testing/apio_testing.vh" 4 | 5 | `timescale 10 ns / 1 ns 6 | 7 | module ticker_tb (); 8 | 9 | // This defines a managed signal called 'clk'. 10 | `DEF_CLK 11 | 12 | // Inputs. 13 | reg reset = 1; 14 | 15 | // Outputs. 16 | wire tick; 17 | 18 | // Instantiate a ticker that generates a tick every 5 clocks. 19 | ticker #( 20 | .DIV(5) 21 | ) ticker ( 22 | .sys_clk(clk), 23 | .sys_reset(reset), 24 | .tick(tick) 25 | ); 26 | 27 | initial begin 28 | `TEST_BEGIN(ticker_tb) 29 | 30 | // Reset for 2 clocks. 31 | `CLKS(2) 32 | reset = 0; 33 | 34 | // Free run for 30 clocks. 35 | `CLKS(30) 36 | 37 | `TEST_END 38 | end 39 | 40 | endmodule 41 | -------------------------------------------------------------------------------- /examples/alhambra-ii/bcd-counter/apio.ini: -------------------------------------------------------------------------------- 1 | ; Apio project configuration file. 2 | ; Type 'apio info apio.ini' for details. 3 | 4 | [env:default] 5 | board = alhambra-ii 6 | top-module = main 7 | 8 | ; When running 'apio sim' without specifying the testbench. 9 | default-testbench = main_tb.v 10 | 11 | -------------------------------------------------------------------------------- /examples/alhambra-ii/bcd-counter/bcd/bcd_digit.v: -------------------------------------------------------------------------------- 1 | // A single cascadable decimal digit counter, 0-9. 2 | 3 | module bcd_digit ( 4 | input wire sys_clk, // Continious system clock. 5 | input wire sys_reset, // Syncrhonous global reset. 6 | input wire tick_in, // When high, counting one step. 7 | output wire tick_out, // When high, higher order digit should count. 8 | output reg [3:0] count // Count output, 0-9. 9 | ); 10 | 11 | // Cascading tick condition. 12 | assign tick_out = (count == 9) && tick_in; 13 | 14 | // Sequential logic. 15 | always @(posedge sys_clk) begin 16 | if (sys_reset) begin 17 | // Case 1: Reset. 18 | count <= 0; 19 | end else if (tick_in) begin 20 | // Case 2: Count modulue 10 21 | count <= count >= 9 ? 0 : count + 1; 22 | end 23 | end 24 | 25 | endmodule 26 | 27 | 28 | -------------------------------------------------------------------------------- /examples/alhambra-ii/bcd-counter/bcd/bcd_digit_tb.gtkw: -------------------------------------------------------------------------------- 1 | [*] 2 | [*] GTKWave Analyzer v3.4.0 (w)1999-2022 BSI 3 | [*] Sat Dec 28 03:24:05 2024 4 | [*] 5 | [dumpfile] "/Volumes/projects/apio-examples/repo/examples/alhambra-ii/bcd-counter/_build/bcd_digit_tb.vcd" 6 | [dumpfile_mtime] "Sat Dec 28 03:22:45 2024" 7 | [dumpfile_size] 4396 8 | [savefile] "/Volumes/projects/apio-examples/repo/examples/alhambra-ii/bcd-counter/bcd_digit_tb.gtkw" 9 | [timestart] 0 10 | [size] 1384 772 11 | [pos] -1 -1 12 | *-21.796194 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 13 | [treeopen] bcd_digit_tb. 14 | [sst_width] 253 15 | [signals_width] 111 16 | [sst_expanded] 1 17 | [sst_vpaned_height] 218 18 | @24 19 | bcd_digit_tb.clk_num 20 | @28 21 | bcd_digit_tb.clk 22 | bcd_digit_tb.reset 23 | bcd_digit_tb.tick_in 24 | @200 25 | - 26 | @22 27 | [color] 3 28 | bcd_digit_tb.count[3:0] 29 | @29 30 | [color] 3 31 | bcd_digit_tb.tick_out 32 | [pattern_trace] 1 33 | [pattern_trace] 0 34 | -------------------------------------------------------------------------------- /examples/alhambra-ii/bcd-counter/bcd/bcd_digit_tb.v: -------------------------------------------------------------------------------- 1 | // A testbench for testing the bcd_digit module. 2 | 3 | `include "testing/apio_testing.vh" 4 | 5 | `timescale 10 ns / 1 ns 6 | 7 | module bcd_digit_tb (); 8 | 9 | // This defines a managed signal called 'clk'. 10 | `DEF_CLK 11 | 12 | // Inputs. 13 | reg reset = 1; 14 | reg tick_in = 0; 15 | 16 | // Outputs. 17 | wire tick_out; 18 | wire [3:0] count; 19 | 20 | bcd_digit digit ( 21 | .sys_clk(clk), 22 | .sys_reset(reset), 23 | .tick_in(tick_in), 24 | .tick_out(tick_out), 25 | .count(count) 26 | ); 27 | 28 | initial begin 29 | // Start the test. 30 | `TEST_BEGIN(bcd_digit_tb) 31 | 32 | // Reset for 2 clocks. 33 | `CLKS(2) 34 | reset = 0; 35 | 36 | // Count 15 times 37 | repeat (15) begin 38 | `CLKS(2) 39 | tick_in = 1; 40 | `CLK 41 | tick_in = 0; 42 | `CLKS(3) 43 | end 44 | 45 | // Assert on ethe xpected digit value. 46 | `EXPECT(count, 15 % 10) 47 | 48 | // End of test. 49 | `TEST_END 50 | end 51 | 52 | endmodule 53 | -------------------------------------------------------------------------------- /examples/alhambra-ii/bcd-counter/info: -------------------------------------------------------------------------------- 1 | Verilog example with testbenches and subdirectories. 2 | -------------------------------------------------------------------------------- /examples/alhambra-ii/bcd-counter/main.v: -------------------------------------------------------------------------------- 1 | // A design that controls the 8 leds with a two digit decimal counter. 2 | 3 | module main #( 4 | // The dividing factor to reach 1 hz from 12Mhz clock. By defining 5 | // it as a parameter we can reduce it in testbench simulations. 6 | parameter integer DIV = 12000000 7 | ) ( 8 | input CLK, // 12MHz clock 9 | output [7:0] LEDS // LED to blink 10 | ); 11 | 12 | // Global reset from the reset generator. 13 | wire sys_reset; 14 | 15 | // Cascading count ticks. 16 | wire tick1; 17 | wire tick2; 18 | wire tick3; 19 | 20 | // Global reset generator. 21 | reset_gen reset_gen ( 22 | .sys_clk (CLK), 23 | .sys_reset(sys_reset) 24 | ); 25 | 26 | // Timing generator. Tick is 27 | ticker #( 28 | .DIV(DIV) 29 | ) ticker ( 30 | .sys_clk(CLK), 31 | .sys_reset(sys_reset), 32 | .tick(tick1) 33 | ); 34 | 35 | // The units digit counter. 36 | bcd_digit digit1 ( 37 | .sys_clk(CLK), 38 | .sys_reset(sys_reset), 39 | .tick_in(tick1), 40 | .tick_out(tick2), 41 | .count(LEDS[3:0]) 42 | ); 43 | 44 | // The tens digit counter. 45 | bcd_digit digit2 ( 46 | .sys_clk(CLK), 47 | .sys_reset(sys_reset), 48 | .tick_in(tick2), 49 | .tick_out(tick3), 50 | .count(LEDS[7:4]) 51 | ); 52 | 53 | 54 | 55 | 56 | endmodule 57 | 58 | 59 | -------------------------------------------------------------------------------- /examples/alhambra-ii/bcd-counter/main_tb.gtkw: -------------------------------------------------------------------------------- 1 | [*] 2 | [*] GTKWave Analyzer v3.4.0 (w)1999-2022 BSI 3 | [*] Sun Dec 29 20:00:53 2024 4 | [*] 5 | [dumpfile] "/Volumes/projects/apio-examples/repo/examples/alhambra-ii/bcd-counter/_build/main_tb.vcd" 6 | [dumpfile_mtime] "Sun Dec 29 19:55:56 2024" 7 | [dumpfile_size] 22930 8 | [savefile] "/Volumes/projects/apio-examples/repo/examples/alhambra-ii/bcd-counter/main_tb.gtkw" 9 | [timestart] 0 10 | [size] 1408 701 11 | [pos] -1 -1 12 | *-23.910471 7480000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 13 | [treeopen] main_tb. 14 | [treeopen] main_tb.main. 15 | [sst_width] 253 16 | [signals_width] 111 17 | [sst_expanded] 1 18 | [sst_vpaned_height] 191 19 | @200 20 | -System 21 | @420 22 | main_tb.clk_num 23 | @28 24 | main_tb.clk 25 | main_tb.main.reset_gen.sys_reset 26 | @200 27 | - 28 | -Digit 1 29 | @28 30 | main_tb.main.tick1 31 | @8022 32 | [color] 3 33 | main_tb.main.digit1.count[3:0] 34 | @28 35 | main_tb.main.tick2 36 | @200 37 | - 38 | -Digit 2 39 | @28 40 | main_tb.main.tick2 41 | @24 42 | [color] 3 43 | main_tb.main.digit2.count[3:0] 44 | @28 45 | main_tb.main.tick3 46 | [pattern_trace] 1 47 | [pattern_trace] 0 48 | -------------------------------------------------------------------------------- /examples/alhambra-ii/bcd-counter/main_tb.v: -------------------------------------------------------------------------------- 1 | // A testbench of main.v. 2 | 3 | // Import apio friendly testing macros. 4 | `include "testing/apio_testing.vh" 5 | 6 | `timescale 10 ns / 1 ns 7 | 8 | module main_tb (); 9 | 10 | // This defines a managed signal called 'clk'. 11 | `DEF_CLK 12 | 13 | // Module's output. 14 | wire [7:0] leds; 15 | 16 | main #( 17 | .DIV(3) 18 | ) main ( 19 | .CLK (clk), 20 | .LEDS(leds) 21 | ); 22 | 23 | initial begin 24 | `TEST_BEGIN(main_tb) 25 | 26 | // Free run for 400 clocks. 27 | `CLKS(400) 28 | 29 | // Assert on expected bcd value. 30 | `EXPECT(leds, 'h31) 31 | 32 | `TEST_END 33 | end 34 | 35 | endmodule 36 | -------------------------------------------------------------------------------- /examples/alhambra-ii/bcd-counter/util/reset_gen.v: -------------------------------------------------------------------------------- 1 | // A module that generates a syncrhonous reset on start. 2 | 3 | module reset_gen ( 4 | input sys_clk, 5 | output reg sys_reset 6 | ); 7 | 8 | // Relying on ICE40 behavior of reseting all DFF on power on reset. 9 | reg [2:0] counter = 0; 10 | 11 | always @(posedge sys_clk) begin 12 | if (counter < 3) begin 13 | // Reset active. 14 | sys_reset <= 1; 15 | counter <= counter + 1; 16 | end else begin 17 | // Reset inactive. 18 | sys_reset <= 0; 19 | end 20 | end 21 | 22 | endmodule 23 | -------------------------------------------------------------------------------- /examples/alhambra-ii/bcd-counter/util/ticker.v: -------------------------------------------------------------------------------- 1 | // A module that provide the counter tick signal. 2 | // The tick output is high for one clock every one second. 3 | 4 | module ticker #( 5 | // The number of clocks per tick. Controls the tick speed. 6 | // Verilog require that we will specify here a value even though we 7 | // override it in main.v. 8 | parameter integer DIV = 12000000 9 | ) ( 10 | input wire sys_clk, // 12MHz clock 11 | input wire sys_reset, // Syncrhonous global reset 12 | output reg tick // High for one clock every DIF clocks. 13 | ); 14 | 15 | // Clock divider counter. 16 | reg [31:0] counter = 0; 17 | 18 | // Sequential logic. 19 | always @(posedge sys_clk) begin 20 | if (sys_reset) begin 21 | // Case 1: Reset. 22 | counter <= 0; 23 | tick <= 0; 24 | end else if (counter >= (DIV - 1)) begin 25 | // Case 2: Cycle end. 26 | counter <= 0; 27 | tick <= 1; 28 | end else begin 29 | // Case 3: Normal increment. 30 | counter <= counter + 1; 31 | tick <= 0; 32 | end 33 | end 34 | 35 | endmodule 36 | 37 | 38 | -------------------------------------------------------------------------------- /examples/alhambra-ii/bcd-counter/util/ticker_tb.gtkw: -------------------------------------------------------------------------------- 1 | [*] 2 | [*] GTKWave Analyzer v3.4.0 (w)1999-2022 BSI 3 | [*] Sat Dec 28 04:52:05 2024 4 | [*] 5 | [dumpfile] "/Volumes/projects/apio-examples/repo/examples/alhambra-ii/bcd-counter/_build/ticker_tb.vcd" 6 | [dumpfile_mtime] "Sat Dec 28 04:51:45 2024" 7 | [dumpfile_size] 1814 8 | [savefile] "/Volumes/projects/apio-examples/repo/examples/alhambra-ii/bcd-counter/ticker_tb.gtkw" 9 | [timestart] 0 10 | [size] 1272 600 11 | [pos] -1 -1 12 | *-20.536083 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 13 | [treeopen] ticker_tb. 14 | [sst_width] 253 15 | [signals_width] 136 16 | [sst_expanded] 1 17 | [sst_vpaned_height] 158 18 | @28 19 | ticker_tb.clk 20 | ticker_tb.reset 21 | @24 22 | ticker_tb.ticker.counter[31:0] 23 | @200 24 | - 25 | @29 26 | [color] 3 27 | ticker_tb.tick 28 | [pattern_trace] 1 29 | [pattern_trace] 0 30 | -------------------------------------------------------------------------------- /examples/alhambra-ii/bcd-counter/util/ticker_tb.v: -------------------------------------------------------------------------------- 1 | // A testbench for testing the ticker module. 2 | 3 | `include "testing/apio_testing.vh" 4 | 5 | `timescale 10 ns / 1 ns 6 | 7 | module ticker_tb (); 8 | 9 | // This defines a managed signal called 'clk'. 10 | `DEF_CLK 11 | 12 | // Inputs. 13 | reg reset = 1; 14 | 15 | // Outputs. 16 | wire tick; 17 | 18 | // Instantiate a ticker that generates a tick every 5 clocks. 19 | ticker #( 20 | .DIV(5) 21 | ) ticker ( 22 | .sys_clk(clk), 23 | .sys_reset(reset), 24 | .tick(tick) 25 | ); 26 | 27 | initial begin 28 | `TEST_BEGIN(ticker_tb) 29 | 30 | // Reset for 2 clocks. 31 | `CLKS(2) 32 | reset = 0; 33 | 34 | // Free run for 30 clocks. 35 | `CLKS(30) 36 | 37 | `TEST_END 38 | end 39 | 40 | endmodule 41 | -------------------------------------------------------------------------------- /examples/alhambra-ii/blinky/apio.ini: -------------------------------------------------------------------------------- 1 | ; Apio project configuration file. 2 | ; Type 'apio info apio.ini' for details. 3 | 4 | [env:default] 5 | board = alhambra-ii 6 | top-module = Test 7 | -------------------------------------------------------------------------------- /examples/alhambra-ii/blinky/blinky.v: -------------------------------------------------------------------------------- 1 | //------------------------------------------------------------------ 2 | //-- Blinking LED 3 | //------------------------------------------------------------------ 4 | 5 | module Test ( 6 | input CLK, // 12MHz clock 7 | output LED7, // LED to blink 8 | // The rest of the LEDs are turned off. 9 | output LED6, 10 | output LED5, 11 | output LED4, 12 | output LED3, 13 | output LED2, 14 | output LED1, 15 | output LED0 16 | ); 17 | 18 | reg [23:0] counter = 0; 19 | 20 | always @(posedge CLK) counter <= counter + 1; 21 | 22 | assign LED7 = counter[23]; 23 | 24 | //-- Turn off the other LEDs 25 | assign {LED6, LED5, LED4} = 3'b0; 26 | assign {LED3, LED2, LED1, LED0} = 4'b0; 27 | 28 | endmodule 29 | 30 | 31 | -------------------------------------------------------------------------------- /examples/alhambra-ii/blinky/info: -------------------------------------------------------------------------------- 1 | Blinking led -------------------------------------------------------------------------------- /examples/alhambra-ii/getting-started/apio.ini: -------------------------------------------------------------------------------- 1 | ; Apio project file. 2 | 3 | [env:default] 4 | 5 | ; Board id. 6 | board = alhambra-ii 7 | 8 | ; Top module name (in main.v) 9 | top-module = Main 10 | -------------------------------------------------------------------------------- /examples/alhambra-ii/getting-started/info: -------------------------------------------------------------------------------- 1 | Example for Apio getting-Starting docs. 2 | -------------------------------------------------------------------------------- /examples/alhambra-ii/getting-started/main.v: -------------------------------------------------------------------------------- 1 | 2 | module Main #( 3 | parameter integer N = 3_000_000 4 | ) ( 5 | input CLK, // 12MHz clock 6 | output LED1, 7 | output LED2 8 | ); 9 | 10 | reg [31:0] counter = 0; 11 | 12 | reg led = 0; 13 | 14 | assign LED1 = led; 15 | assign LED2 = !led; 16 | 17 | always @(posedge CLK) begin 18 | if (counter >= N - 1) begin 19 | counter <= 0; 20 | led <= !led; 21 | end else begin 22 | counter <= counter + 1; 23 | end 24 | end 25 | 26 | endmodule 27 | 28 | 29 | -------------------------------------------------------------------------------- /examples/alhambra-ii/getting-started/main_tb.gtkw: -------------------------------------------------------------------------------- 1 | [*] 2 | [*] GTKWave Analyzer v3.4.0 (w)1999-2022 BSI 3 | [*] Wed Jun 4 02:27:36 2025 4 | [*] 5 | [dumpfile] "/Users/user/work2/_build/default/main_tb.vcd" 6 | [dumpfile_mtime] "Wed Jun 4 02:27:20 2025" 7 | [dumpfile_size] 1028 8 | [savefile] "/Users/user/work2/main_tb.gtkw" 9 | [timestart] 0 10 | [size] 1000 600 11 | [pos] -1 -1 12 | *-18.338169 966000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 13 | [treeopen] testbench. 14 | [sst_width] 253 15 | [signals_width] 136 16 | [sst_expanded] 1 17 | [sst_vpaned_height] 158 18 | @28 19 | testbench.CLK 20 | @200 21 | - 22 | @24 23 | testbench.dut.counter[31:0] 24 | @200 25 | - 26 | @28 27 | [color] 3 28 | testbench.expected_led 29 | @200 30 | - 31 | @28 32 | [color] 2 33 | testbench.LED1 34 | @201 35 | - 36 | @28 37 | [color] 2 38 | testbench.LED2 39 | [pattern_trace] 1 40 | [pattern_trace] 0 41 | -------------------------------------------------------------------------------- /examples/alhambra-ii/getting-started/main_tb.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns/1ps 2 | 3 | module testbench; 4 | 5 | // Clock and DUT signals 6 | reg CLK = 0; 7 | wire LED1, LED2; 8 | 9 | // Instantiate DUT with N = 3 for quick testing 10 | Main #(.N(3)) dut ( 11 | .CLK(CLK), 12 | .LED1(LED1), 13 | .LED2(LED2) 14 | ); 15 | 16 | // Generate 12 MHz-like clock (approx. 83 ns period) 17 | always #42 CLK = ~CLK; 18 | 19 | // Expected state tracker 20 | reg expected_led = 0; 21 | 22 | integer i; 23 | 24 | initial begin 25 | $dumpvars(0, testbench); 26 | 27 | // Simulate 12 rising edges of CLK 28 | for (i = 0; i < 12; i = i + 1) begin 29 | @(posedge CLK); 30 | 31 | // Check LED values before updating expected state 32 | if (LED1 !== expected_led || LED2 !== ~expected_led) begin 33 | $display("ERROR at cycle %0d: LED1 = %b, expected = %b", i, LED1, expected_led); 34 | `ifndef INTERACTIVE_SIM 35 | $fatal(1, "LED state mismatch"); 36 | `endif 37 | end 38 | 39 | // Update expected LED every N=3 cycles 40 | if ((i + 1) % 3 == 0) begin 41 | expected_led = ~expected_led; 42 | end 43 | end 44 | 45 | $finish; 46 | end 47 | 48 | endmodule 49 | -------------------------------------------------------------------------------- /examples/alhambra-ii/getting-started/pinout.pcf: -------------------------------------------------------------------------------- 1 | 2 | set_io LED1 37 # output 3 | set_io LED2 38 # output 4 | 5 | set_io CLK 49 # input 6 | 7 | -------------------------------------------------------------------------------- /examples/alhambra-ii/ledon/apio.ini: -------------------------------------------------------------------------------- 1 | ; Apio project configuration file. 2 | ; Type 'apio info apio.ini' for details. 3 | 4 | [env:default] 5 | board = alhambra-ii 6 | top-module = leds 7 | -------------------------------------------------------------------------------- /examples/alhambra-ii/ledon/info: -------------------------------------------------------------------------------- 1 | Turning on a led -------------------------------------------------------------------------------- /examples/alhambra-ii/ledon/ledon.v: -------------------------------------------------------------------------------- 1 | //------------------------------------------------------------------ 2 | //-- Hello world example for the Alhambra-II baord 3 | //-- Turn on the LED 0 4 | //------------------------------------------------------------------ 5 | module leds ( 6 | output wire LED0, 7 | output wire LED1, 8 | output wire LED2, 9 | output wire LED3, 10 | output wire LED4, 11 | output wire LED5, 12 | output wire LED6, 13 | output wire LED7 14 | ); 15 | 16 | //-- LED0 on 17 | assign LED0 = 1'b1; 18 | 19 | //-- The other LEDs are off 20 | assign {LED1, LED2, LED3, LED4, LED5, LED6, LED7} = 7'b0; 21 | 22 | endmodule 23 | 24 | -------------------------------------------------------------------------------- /examples/alhambra-ii/ledon/ledon_tb.gtkw: -------------------------------------------------------------------------------- 1 | [*] 2 | [*] GTKWave Analyzer v3.3.103 (w)1999-2019 BSI 3 | [*] Wed Apr 27 18:37:07 2022 4 | [*] 5 | [dumpfile] "/home/obijuan/Develop/FPGAwars/apio-examples/Alhambra-II/ledon/ledon_tb.vcd" 6 | [dumpfile_mtime] "Wed Apr 27 18:32:17 2022" 7 | [dumpfile_size] 623 8 | [savefile] "/home/obijuan/Develop/FPGAwars/apio-examples/Alhambra-II/ledon/ledon_tb.gtkw" 9 | [timestart] 0 10 | [size] 1000 600 11 | [pos] -1 -1 12 | *-18.262543 146000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 13 | [treeopen] ledon_tb. 14 | [sst_width] 233 15 | [signals_width] 78 16 | [sst_expanded] 1 17 | [sst_vpaned_height] 144 18 | @28 19 | ledon_tb.UUT.LED7 20 | ledon_tb.UUT.LED6 21 | ledon_tb.UUT.LED5 22 | ledon_tb.UUT.LED4 23 | ledon_tb.UUT.LED3 24 | ledon_tb.UUT.LED2 25 | ledon_tb.UUT.LED1 26 | ledon_tb.UUT.LED0 27 | [pattern_trace] 1 28 | [pattern_trace] 0 29 | -------------------------------------------------------------------------------- /examples/alhambra-ii/ledon/ledon_tb.v: -------------------------------------------------------------------------------- 1 | //------------------------------------------------------------------- 2 | //-- ledon_tb.v 3 | //-- Testbench 4 | //------------------------------------------------------------------- 5 | //-- Juan Gonzalez (Obijuan) 6 | //-- GPL license 7 | //------------------------------------------------------------------- 8 | `default_nettype none `timescale 100 ns / 10 ns 9 | 10 | module ledon_tb (); 11 | 12 | //-- Simulation time: 1us (10 * 100ns) 13 | parameter DURATION = 10; 14 | 15 | //-- Leds port 16 | wire led0, led1, led2, led3, led4, led5, led6, led7; 17 | 18 | //-- Instantiate the unit to test 19 | leds UUT ( 20 | .LED0(led0), 21 | .LED1(led1), 22 | .LED2(led2), 23 | .LED3(led3), 24 | .LED4(led4), 25 | .LED5(led5), 26 | .LED6(led6), 27 | .LED7(led7) 28 | ); 29 | 30 | 31 | initial begin 32 | 33 | //-- Dump vars to the .vcd output file 34 | $dumpvars(0, ledon_tb); 35 | 36 | #(DURATION) $display("End of simulation"); 37 | $finish; 38 | end 39 | 40 | endmodule 41 | -------------------------------------------------------------------------------- /examples/alhambra-ii/multienv/apio.ini: -------------------------------------------------------------------------------- 1 | ; Apio project configuration file. 2 | ; Type 'apio info apio.ini' for details. 3 | 4 | ; This apio.ini demonstrates how the design can be parametrized 5 | ; using apio.ini env. The optional command line flag '--env' allows 6 | ; to select the env to use. 7 | ; 8 | ; Example: 9 | ; apio upload --env fast 10 | 11 | ; Select the default env. Without it, the first listed 12 | ; env is the default. 13 | [apio] 14 | default-env = slow 15 | 16 | ; Common for all envs. 17 | [common] 18 | board = alhambra-ii 19 | top-module = main 20 | 21 | ; Env for build with fast blink. 22 | [env:fast] 23 | defines = 24 | CLK_DIV=3_000_000 25 | 26 | ; Env for build with slow blink. 27 | [env:slow] 28 | defines = 29 | CLK_DIV=12_000_000 30 | 31 | 32 | -------------------------------------------------------------------------------- /examples/alhambra-ii/multienv/info: -------------------------------------------------------------------------------- 1 | Multi apio env demo 2 | -------------------------------------------------------------------------------- /examples/alhambra-ii/multienv/main.v: -------------------------------------------------------------------------------- 1 | //------------------------------------------------------------------ 2 | //-- Blinking LED 3 | //------------------------------------------------------------------ 4 | 5 | module main #( 6 | parameter CLK_DIV = `CLK_DIV 7 | ) ( 8 | input CLK, // 12MHz clock 9 | output [7:0] LEDS // LED to blink 10 | ); 11 | 12 | // The counter should count this number of clocks 13 | // between flipping LED state. 14 | localparam limit = ((CLK_DIV) / 2) - 1; 15 | 16 | reg led = 0; 17 | 18 | reg [23:0] counter = 0; 19 | 20 | always @(posedge CLK) begin 21 | if (counter < limit) begin 22 | counter <= counter + 1; 23 | end else begin 24 | counter <= 0; 25 | led <= ~led; 26 | end 27 | end 28 | 29 | assign LEDS = {led, 7'b0}; 30 | 31 | endmodule 32 | 33 | 34 | -------------------------------------------------------------------------------- /examples/alhambra-ii/multienv/main_tb.gtkw: -------------------------------------------------------------------------------- 1 | [*] 2 | [*] GTKWave Analyzer v3.4.0 (w)1999-2022 BSI 3 | [*] Tue May 13 17:28:34 2025 4 | [*] 5 | [dumpfile] "/Users/user/work/_build/slow/main_tb.vcd" 6 | [dumpfile_mtime] "Tue May 13 17:26:11 2025" 7 | [dumpfile_size] 1275 8 | [savefile] "/Users/user/work/main_tb.gtkw" 9 | [timestart] 0 10 | [size] 1304 776 11 | [pos] -1 -1 12 | *-19.576792 637000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 13 | [treeopen] main_tb. 14 | [sst_width] 253 15 | [signals_width] 179 16 | [sst_expanded] 1 17 | [sst_vpaned_height] 220 18 | @28 19 | main_tb.clk 20 | @420 21 | main_tb.clk_num 22 | @22 23 | main_tb.leds[7:0] 24 | @200 25 | - 26 | @420 27 | [color] 3 28 | main_tb.main.CLK_DIV 29 | @421 30 | [color] 3 31 | main_tb.main.limit 32 | [pattern_trace] 1 33 | [pattern_trace] 0 34 | -------------------------------------------------------------------------------- /examples/alhambra-ii/multienv/main_tb.v: -------------------------------------------------------------------------------- 1 | // A testbench of main.v. 2 | 3 | `include "apio_testing.vh" 4 | 5 | `timescale 10 ns / 1 ns 6 | 7 | module main_tb (); 8 | 9 | // This defines a managed signal called 'clk'. 10 | `DEF_CLK 11 | 12 | // Module's output. 13 | wire [7:0] leds; 14 | 15 | main #( 16 | .CLK_DIV(6) 17 | ) main ( 18 | .CLK (clk), 19 | .LEDS(leds) 20 | ); 21 | 22 | initial begin 23 | `TEST_BEGIN(main_tb) 24 | 25 | // Free run for 400 clocks. 26 | `CLKS(16) 27 | 28 | // Assert on expected bcd value. 29 | `EXPECT(leds, 'b1000_0000) 30 | 31 | `TEST_END 32 | end 33 | 34 | endmodule 35 | -------------------------------------------------------------------------------- /examples/alhambra-ii/multienv/pinout.pcf: -------------------------------------------------------------------------------- 1 | # Pinout file for Alhambra-ii example.. 2 | 3 | # -- 12Mhz clk 4 | set_io CLK 49 5 | 6 | # -- LEDS outputs 7 | set_io LEDS[0] 45 8 | set_io LEDS[1] 44 9 | set_io LEDS[2] 43 10 | set_io LEDS[3] 42 11 | set_io LEDS[4] 41 12 | set_io LEDS[5] 39 13 | set_io LEDS[6] 38 14 | set_io LEDS[7] 37 15 | 16 | -------------------------------------------------------------------------------- /examples/alhambra-ii/prog-cmd/apio.ini: -------------------------------------------------------------------------------- 1 | ; Apio project configuration file. 2 | ; Type 'apio info apio.ini' for details. 3 | 4 | [env:default] 5 | board = alhambra-ii 6 | top-module = Test 7 | 8 | ; Overriding the default programmer command of 'apio upload'. 9 | programmer-cmd = iceprog -d d:${BUS}/${DEV} ${BIN_FILE} 10 | -------------------------------------------------------------------------------- /examples/alhambra-ii/prog-cmd/blinky.v: -------------------------------------------------------------------------------- 1 | //------------------------------------------------------------------ 2 | //-- Blinking LED 3 | //------------------------------------------------------------------ 4 | 5 | module Test ( 6 | input CLK, // 12MHz clock 7 | output LED7, // LED to blink 8 | // The rest of the LEDs are turned off. 9 | output LED6, 10 | output LED5, 11 | output LED4, 12 | output LED3, 13 | output LED2, 14 | output LED1, 15 | output LED0 16 | ); 17 | 18 | reg [23:0] counter = 0; 19 | 20 | always @(posedge CLK) counter <= counter + 1; 21 | 22 | assign LED7 = counter[23]; 23 | 24 | //-- Turn off the other LEDs 25 | assign {LED6, LED5, LED4} = 3'b0; 26 | assign {LED3, LED2, LED1, LED0} = 4'b0; 27 | 28 | endmodule 29 | 30 | 31 | -------------------------------------------------------------------------------- /examples/alhambra-ii/prog-cmd/info: -------------------------------------------------------------------------------- 1 | Using the 'programmer-cmd' opion in apio.ini 2 | -------------------------------------------------------------------------------- /examples/alhambra-ii/template/apio.ini: -------------------------------------------------------------------------------- 1 | ; Apio project configuration file. 2 | ; Type 'apio info apio.ini' for details. 3 | 4 | [env:default] 5 | board = alhambra-ii 6 | top-module = Test 7 | -------------------------------------------------------------------------------- /examples/alhambra-ii/template/info: -------------------------------------------------------------------------------- 1 | Project template -------------------------------------------------------------------------------- /examples/alhambra-ii/template/test.v: -------------------------------------------------------------------------------- 1 | //------------------------------------------------------------------ 2 | //-- Top-level Verilog example 3 | //-- Blinking LED 4 | //------------------------------------------------------------------ 5 | 6 | module Test ( 7 | input CLK, // 12MHz clock 8 | output LED7 9 | ); 10 | 11 | reg [23:0] counter = 0; 12 | 13 | always @(posedge CLK) counter <= counter + 1; 14 | 15 | assign LED7 = counter[23]; 16 | 17 | endmodule 18 | -------------------------------------------------------------------------------- /examples/blackice/blink/Readme.md: -------------------------------------------------------------------------------- 1 | Simple example for testing the mystorm Blackice board 2 | It just blinks the red led 4 3 | 4 | ## Hardware setup 5 | 6 | ![](blackice-setup.jpg) 7 | 8 | ## Instructions 9 | 10 | * Connect the board to the computer (USB shown in the above picture) 11 | * Execute the following command: 12 | 13 | ```sh 14 | apio upload 15 | ``` 16 | This is a fragment of what will be written in the **console**: 17 | 18 | ``` 19 | Board: blackice 20 | [Thu Jan 4 17:52:41 2018] Processing blackice 21 | -------------------------------------------------------------------------------- 22 | FPGA_SIZE: 8k 23 | FPGA_TYPE: hx 24 | FPGA_PACK: tq144:4k 25 | PROG: black-iceprog /dev/ttyACM0 26 | yosys -p "synth_ice40 -blif hardware.blif" -q blink.v 27 | arachne-pnr -d 8k -P tq144:4k -p blink.pcf -o hardware.asc hardware.blif 28 | [...] 29 | icepack hardware.asc hardware.bin 30 | black-iceprog /dev/ttyACM0 hardware.bin 31 | Wrote 135100 bytes 32 | ========================= [SUCCESS] Took 3.77 seconds ========================= 33 | ``` 34 | 35 | After 4 seconds or so, the red led will be **blinking** 36 | -------------------------------------------------------------------------------- /examples/blackice/blink/apio.ini: -------------------------------------------------------------------------------- 1 | ; Apio project configuration file. 2 | ; Type 'apio info apio.ini' for details. 3 | 4 | [env:default] 5 | board = blackice 6 | top-module = blink 7 | -------------------------------------------------------------------------------- /examples/blackice/blink/blackice-setup.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/FPGAwars/apio-examples/ec7da6db0ed17c9d22abc36a527b2a501e7cada0/examples/blackice/blink/blackice-setup.jpg -------------------------------------------------------------------------------- /examples/blackice/blink/blink.pcf: -------------------------------------------------------------------------------- 1 | ############################################################################### 2 | # # 3 | # Copyright 2016 myStorm Copyright and related # 4 | # rights are licensed under the Solderpad Hardware License, Version 0.51 # 5 | # (the “License”); you may not use this file except in compliance with # 6 | # the License. You may obtain a copy of the License at # 7 | # http://solderpad.org/licenses/SHL-0.51. Unless required by applicable # 8 | # law or agreed to in writing, software, hardware and materials # 9 | # distributed under this License is distributed on an “AS IS” BASIS, # 10 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or # 11 | # implied. See the License for the specific language governing # 12 | # permissions and limitations under the License. # 13 | # # 14 | ############################################################################### 15 | 16 | #-- Red led (4) 17 | set_io LED 70 18 | 19 | # Onboard 12Mhz oscillator 20 | set_io clk 129 21 | -------------------------------------------------------------------------------- /examples/blackice/blink/blink.v: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * * 3 | * Copyright 2016 myStorm Copyright and related * 4 | * rights are licensed under the Solderpad Hardware License, Version 0.51 * 5 | * (the “License”); you may not use this file except in compliance with * 6 | * the License. You may obtain a copy of the License at * 7 | * http://solderpad.org/licenses/SHL-0.51. Unless required by applicable * 8 | * law or agreed to in writing, software, hardware and materials * 9 | * distributed under this License is distributed on an “AS IS” BASIS, * 10 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or * 11 | * implied. See the License for the specific language governing * 12 | * permissions and limitations under the License. * 13 | * * 14 | ******************************************************************************/ 15 | 16 | module blink ( 17 | input clk, 18 | output LED 19 | ); 20 | 21 | localparam N = 24; 22 | 23 | reg [N:0] count; 24 | 25 | assign LED = count[N]; 26 | 27 | always @(posedge clk) count <= count + 1; 28 | 29 | endmodule 30 | -------------------------------------------------------------------------------- /examples/blackice/blink/info: -------------------------------------------------------------------------------- 1 | Blinking a led -------------------------------------------------------------------------------- /examples/blackice/blinky/Blinky.v: -------------------------------------------------------------------------------- 1 | //------------------------------------------------------------------ 2 | //-- Blinking LED1 (Blue) 3 | //------------------------------------------------------------------ 4 | 5 | module Test ( 6 | input CLK, // 100MHz clock 7 | output LED1, // Led to blink 8 | output LED2, 9 | LED3, 10 | LED4 //-- Other LEDs: turned off 11 | ); 12 | 13 | reg [25:0] counter = 0; 14 | 15 | always @(posedge CLK) counter <= counter + 1; 16 | 17 | assign LED1 = counter[25]; 18 | 19 | //-- Turn off the other LEDs 20 | assign {LED2, LED3, LED4} = 3'b0; 21 | 22 | endmodule 23 | 24 | 25 | -------------------------------------------------------------------------------- /examples/blackice/blinky/apio.ini: -------------------------------------------------------------------------------- 1 | ; Apio project configuration file. 2 | ; Type 'apio info apio.ini' for details. 3 | 4 | [env:default] 5 | board = blackice 6 | top-module = Test 7 | -------------------------------------------------------------------------------- /examples/blackice/blinky/info: -------------------------------------------------------------------------------- 1 | Blinking a led -------------------------------------------------------------------------------- /examples/colorlight-5a-75b-v8/blinky/apio.ini: -------------------------------------------------------------------------------- 1 | ; Apio project configuration file. 2 | ; Type 'apio info apio.ini' for details. 3 | 4 | [env:default] 5 | board = colorlight-5a-75b-v8 6 | top-module = Test 7 | -------------------------------------------------------------------------------- /examples/colorlight-5a-75b-v8/blinky/blinky.v: -------------------------------------------------------------------------------- 1 | //------------------------------------------------------------------ 2 | //-- Blinking LED 3 | //------------------------------------------------------------------ 4 | 5 | module Test ( 6 | input CLK, // 25MHz clock 7 | output led // LED to blink 8 | ); 9 | 10 | reg [23:0] counter = 0; 11 | 12 | always @(posedge CLK) counter <= counter + 1; 13 | 14 | assign led = counter[23]; 15 | 16 | endmodule 17 | -------------------------------------------------------------------------------- /examples/colorlight-5a-75b-v8/blinky/info: -------------------------------------------------------------------------------- 1 | Blinking a led -------------------------------------------------------------------------------- /examples/colorlight-5a-75b-v8/blinky/pinout.lpf: -------------------------------------------------------------------------------- 1 | # -- Board: ColorLight-5A-75E-V71_(FT2232H) 2 | 3 | # -- CLK 4 | LOCATE COMP "CLK" SITE "P6"; 5 | IOBUF PORT "CLK" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; 6 | 7 | # -- LED 8 | LOCATE COMP "led" SITE "T6"; 9 | IOBUF PORT "led" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; 10 | 11 | 12 | 13 | -------------------------------------------------------------------------------- /examples/colorlight-5a-75b-v8/ledon-sv/apio.ini: -------------------------------------------------------------------------------- 1 | ; Apio project configuration file. 2 | ; Type 'apio info apio.ini' for details. 3 | 4 | [env:default] 5 | board = colorlight-5a-75b-v8 6 | top-module = ledon 7 | -------------------------------------------------------------------------------- /examples/colorlight-5a-75b-v8/ledon-sv/info: -------------------------------------------------------------------------------- 1 | Blinking leds (system verilog) 2 | -------------------------------------------------------------------------------- /examples/colorlight-5a-75b-v8/ledon-sv/ledon.sv: -------------------------------------------------------------------------------- 1 | //-------------------------------------- 2 | //-- Turning on the LED 3 | //-------------------------------------- 4 | 5 | module ledon ( 6 | output logic led //-- LED 7 | ); 8 | 9 | // -- The LED on the ColorLight-5A-75E works 10 | // -- with inverse logic: 11 | // -- 0: Turn on the LED 12 | // -- 1: Turn off the LED 13 | 14 | // Turn on the led 15 | // (output the bit 0 to the led) 16 | assign led = 1'b0; 17 | 18 | endmodule 19 | 20 | -------------------------------------------------------------------------------- /examples/colorlight-5a-75b-v8/ledon-sv/ledon_tb.gtkw: -------------------------------------------------------------------------------- 1 | [*] 2 | [*] GTKWave Analyzer v3.4.0 (w)1999-2022 BSI 3 | [*] Wed Dec 18 18:59:41 2024 4 | [*] 5 | [dumpfile] "/Volumes/projects/apio-examples/repo/examples/colorlight-5a-75b-v8/ledon/_build/ledon_tb.vcd" 6 | [dumpfile_mtime] "Wed Dec 18 18:59:05 2024" 7 | [dumpfile_size] 358 8 | [savefile] "/Volumes/projects/apio-examples/repo/examples/colorlight-5a-75b-v8/ledon/ledon_tb.gtkw" 9 | [timestart] 0 10 | [size] 1000 600 11 | [pos] -1 -1 12 | *-8.286901 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 13 | [treeopen] ledon_tb. 14 | [sst_width] 253 15 | [signals_width] 78 16 | [sst_expanded] 1 17 | [sst_vpaned_height] 158 18 | @28 19 | ledon_tb.led 20 | [pattern_trace] 1 21 | [pattern_trace] 0 22 | -------------------------------------------------------------------------------- /examples/colorlight-5a-75b-v8/ledon-sv/ledon_tb.sv: -------------------------------------------------------------------------------- 1 | //------------------------------------------------------------------- 2 | //-- ledon_tb.v 3 | //-- Testbench 4 | //------------------------------------------------------------------- 5 | //-- Juan Gonzalez (Obijuan) 6 | //-- GPL license 7 | //------------------------------------------------------------------- 8 | `default_nettype none `timescale 100 ns / 10 ns 9 | 10 | module ledon_tb (); 11 | 12 | //-- Simulation time: 1us (10 * 100ns) 13 | parameter DURATION = 10; 14 | 15 | //-- Leds port 16 | wire led; 17 | 18 | //-- Instantiate the unit to test 19 | ledon UUT (.led(led)); 20 | 21 | 22 | initial begin 23 | 24 | //-- Dump vars to the .vcd output file 25 | $dumpvars(0, ledon_tb); 26 | 27 | #(DURATION) $display("End of simulation"); 28 | $finish; 29 | end 30 | 31 | endmodule 32 | -------------------------------------------------------------------------------- /examples/colorlight-5a-75b-v8/ledon-sv/pinout.lpf: -------------------------------------------------------------------------------- 1 | # -- Board: ColorLight-5A-75E-V71_(FT2232H) 2 | 3 | # -- LED 4 | LOCATE COMP "led" SITE "T6"; 5 | IOBUF PORT "led" IO_TYPE=LVCMOS33; 6 | 7 | 8 | 9 | -------------------------------------------------------------------------------- /examples/colorlight-5a-75b-v8/ledon/apio.ini: -------------------------------------------------------------------------------- 1 | ; Apio project configuration file. 2 | ; Type 'apio info apio.ini' for details. 3 | 4 | [env:default] 5 | board = colorlight-5a-75b-v8 6 | top-module = ledon 7 | -------------------------------------------------------------------------------- /examples/colorlight-5a-75b-v8/ledon/info: -------------------------------------------------------------------------------- 1 | Blinking leds -------------------------------------------------------------------------------- /examples/colorlight-5a-75b-v8/ledon/ledon.v: -------------------------------------------------------------------------------- 1 | //-------------------------------------- 2 | //-- Turning on the LED 3 | //-------------------------------------- 4 | 5 | module ledon ( 6 | output led //-- LED 7 | ); 8 | 9 | // -- The LED on the ColorLight-5A-75E works 10 | // -- with inverse logic: 11 | // -- 0: Turn on the LED 12 | // -- 1: Turn off the LED 13 | 14 | // Turn on the led 15 | // (output the bit 0 to the led) 16 | assign led = 1'b0; 17 | 18 | endmodule 19 | 20 | -------------------------------------------------------------------------------- /examples/colorlight-5a-75b-v8/ledon/ledon_tb.gtkw: -------------------------------------------------------------------------------- 1 | [*] 2 | [*] GTKWave Analyzer v3.4.0 (w)1999-2022 BSI 3 | [*] Wed Dec 18 18:59:41 2024 4 | [*] 5 | [dumpfile] "/Volumes/projects/apio-examples/repo/examples/colorlight-5a-75b-v8/ledon/_build/ledon_tb.vcd" 6 | [dumpfile_mtime] "Wed Dec 18 18:59:05 2024" 7 | [dumpfile_size] 358 8 | [savefile] "/Volumes/projects/apio-examples/repo/examples/colorlight-5a-75b-v8/ledon/ledon_tb.gtkw" 9 | [timestart] 0 10 | [size] 1000 600 11 | [pos] -1 -1 12 | *-8.286901 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 13 | [treeopen] ledon_tb. 14 | [sst_width] 253 15 | [signals_width] 78 16 | [sst_expanded] 1 17 | [sst_vpaned_height] 158 18 | @28 19 | ledon_tb.led 20 | [pattern_trace] 1 21 | [pattern_trace] 0 22 | -------------------------------------------------------------------------------- /examples/colorlight-5a-75b-v8/ledon/ledon_tb.v: -------------------------------------------------------------------------------- 1 | //------------------------------------------------------------------- 2 | //-- ledon_tb.v 3 | //-- Testbench 4 | //------------------------------------------------------------------- 5 | //-- Juan Gonzalez (Obijuan) 6 | //-- GPL license 7 | //------------------------------------------------------------------- 8 | `default_nettype none `timescale 100 ns / 10 ns 9 | 10 | module ledon_tb (); 11 | 12 | //-- Simulation time: 1us (10 * 100ns) 13 | parameter DURATION = 10; 14 | 15 | //-- Leds port 16 | wire led; 17 | 18 | //-- Instantiate the unit to test 19 | ledon UUT (.led(led)); 20 | 21 | 22 | initial begin 23 | 24 | //-- Dump vars to the .vcd output file 25 | $dumpvars(0, ledon_tb); 26 | 27 | #(DURATION) $display("End of simulation"); 28 | $finish; 29 | end 30 | 31 | endmodule 32 | -------------------------------------------------------------------------------- /examples/colorlight-5a-75b-v8/ledon/pinout.lpf: -------------------------------------------------------------------------------- 1 | # -- Board: ColorLight-5A-75E-V71_(FT2232H) 2 | 3 | # -- LED 4 | LOCATE COMP "led" SITE "T6"; 5 | IOBUF PORT "led" IO_TYPE=LVCMOS33; 6 | 7 | 8 | 9 | -------------------------------------------------------------------------------- /examples/colorlight-5a-75e-v71-ft2232h/blinky/apio.ini: -------------------------------------------------------------------------------- 1 | ; Apio project configuration file. 2 | ; Type 'apio info apio.ini' for details. 3 | 4 | [env:default] 5 | board = colorlight-5a-75e-v71-ft2232h 6 | top-module = Test 7 | -------------------------------------------------------------------------------- /examples/colorlight-5a-75e-v71-ft2232h/blinky/blinky.v: -------------------------------------------------------------------------------- 1 | //------------------------------------------------------------------ 2 | //-- Blinking LED 3 | //------------------------------------------------------------------ 4 | 5 | module Test ( 6 | input CLK, // 25MHz clock 7 | output led // LED to blink 8 | ); 9 | 10 | reg [23:0] counter = 0; 11 | 12 | always @(posedge CLK) counter <= counter + 1; 13 | 14 | assign led = counter[23]; 15 | 16 | endmodule 17 | -------------------------------------------------------------------------------- /examples/colorlight-5a-75e-v71-ft2232h/blinky/info: -------------------------------------------------------------------------------- 1 | Blinking a led -------------------------------------------------------------------------------- /examples/colorlight-5a-75e-v71-ft2232h/blinky/pinout.lpf: -------------------------------------------------------------------------------- 1 | # -- Board: ColorLight-5A-75E-V71_(FT2232H) 2 | 3 | # -- CLK 4 | LOCATE COMP "CLK" SITE "P6"; 5 | IOBUF PORT "CLK" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; 6 | 7 | # -- LED 8 | LOCATE COMP "led" SITE "P11"; 9 | IOBUF PORT "led" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; 10 | 11 | 12 | 13 | -------------------------------------------------------------------------------- /examples/colorlight-5a-75e-v71-ft2232h/ledon/apio.ini: -------------------------------------------------------------------------------- 1 | ; Apio project configuration file. 2 | ; Type 'apio info apio.ini' for details. 3 | 4 | [env:default] 5 | board = colorlight-5a-75e-v71-ft2232h 6 | top-module = top 7 | -------------------------------------------------------------------------------- /examples/colorlight-5a-75e-v71-ft2232h/ledon/info: -------------------------------------------------------------------------------- 1 | Blinking leds -------------------------------------------------------------------------------- /examples/colorlight-5a-75e-v71-ft2232h/ledon/ledon.v: -------------------------------------------------------------------------------- 1 | //-------------------------------------- 2 | //-- Turning on the LED 3 | //-------------------------------------- 4 | 5 | module top ( 6 | output led //-- LED 7 | ); 8 | 9 | // -- The LED on the ColorLight-5A-75E works 10 | // -- with inverse logic: 11 | // -- 0: Turn on the LED 12 | // -- 1: Turn off the LED 13 | 14 | // Turn on the led 15 | // (output the bit 0 to the led) 16 | assign led = 1'b0; 17 | 18 | endmodule 19 | 20 | -------------------------------------------------------------------------------- /examples/colorlight-5a-75e-v71-ft2232h/ledon/pinout.lpf: -------------------------------------------------------------------------------- 1 | # -- Board: ColorLight-5A-75E-V71_(FT2232H) 2 | 3 | # -- LED 4 | LOCATE COMP "led" SITE "P11"; 5 | IOBUF PORT "led" IO_TYPE=LVCMOS33; 6 | 7 | 8 | 9 | -------------------------------------------------------------------------------- /examples/cynthion-r1-4/blinky/apio.ini: -------------------------------------------------------------------------------- 1 | ; Apio project configuration file. 2 | ; Type 'apio info apio.ini' for details. 3 | 4 | [env:default] 5 | board = cynthion-r1-4 6 | top-module = top 7 | -------------------------------------------------------------------------------- /examples/cynthion-r1-4/blinky/blinky.v: -------------------------------------------------------------------------------- 1 | //------------------------------------------------------------------ 2 | //-- Blinking FPGA LED5 (Red) 3 | //------------------------------------------------------------------ 4 | 5 | module top ( 6 | input clk_60mhz, //-- 60Mhz clock 7 | output [5:0] led //-- FPGA LEDs 8 | ); 9 | 10 | //-- Turn off all the LEDs except LED0 11 | //-- (note that Cynthion LED logic is inverted: 0=on, 1=off) 12 | assign led[4:0] = 5'b11111; 13 | 14 | //-- 24 bits counter 15 | reg [23:0] counter = 0; 16 | 17 | always @(posedge clk_60mhz) counter <= counter + 1; 18 | 19 | //-- The most significant bit of the counter 20 | //-- is displayed on LED5 (Red) 21 | assign led[5] = counter[23]; 22 | 23 | endmodule 24 | -------------------------------------------------------------------------------- /examples/cynthion-r1-4/blinky/info: -------------------------------------------------------------------------------- 1 | Blinking a led -------------------------------------------------------------------------------- /examples/edu-ciaa-fpga/and-gate-sv/and_gate.pcf: -------------------------------------------------------------------------------- 1 | set_io --warn-no-port s 1 #-- output 2 | set_io --warn-no-port a 31 # input 3 | set_io --warn-no-port b 32 # input -------------------------------------------------------------------------------- /examples/edu-ciaa-fpga/and-gate-sv/and_gate.sv: -------------------------------------------------------------------------------- 1 | module and_gate ( 2 | input logic a, 3 | input logic b, 4 | output logic s 5 | ); 6 | 7 | assign s = a & b; 8 | 9 | endmodule 10 | -------------------------------------------------------------------------------- /examples/edu-ciaa-fpga/and-gate-sv/and_gate_tb.gtkw: -------------------------------------------------------------------------------- 1 | [*] 2 | [*] GTKWave Analyzer v3.4.0 (w)1999-2022 BSI 3 | [*] Wed Dec 18 04:17:41 2024 4 | [*] 5 | [dumpfile] "/Volumes/projects/apio-dev/repo/test-examples/TB/edu-ciaa-fpga/and-gate/_build/and_gate_tb.vcd" 6 | [dumpfile_mtime] "Wed Dec 18 04:17:00 2024" 7 | [dumpfile_size] 38921 8 | [savefile] "/Volumes/projects/apio-dev/repo/test-examples/TB/edu-ciaa-fpga/and-gate/and_gate_tb.gtkw" 9 | [timestart] 0 10 | [size] 1000 600 11 | [pos] -1 -1 12 | *-20.251245 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 13 | [treeopen] and_gate_testbench. 14 | [sst_width] 253 15 | [signals_width] 78 16 | [sst_expanded] 1 17 | [sst_vpaned_height] 334 18 | @28 19 | and_gate_testbench.a 20 | and_gate_testbench.b 21 | @29 22 | and_gate_testbench.s 23 | [pattern_trace] 1 24 | [pattern_trace] 0 25 | -------------------------------------------------------------------------------- /examples/edu-ciaa-fpga/and-gate-sv/and_gate_tb.sv: -------------------------------------------------------------------------------- 1 | `default_nettype none `timescale 100 ns / 10 ns 2 | 3 | module and_gate_testbench (); 4 | 5 | logic a, b, s; 6 | 7 | // Instantiate device under test 8 | and_gate dut ( 9 | a, 10 | b, 11 | s 12 | ); 13 | 14 | // Apply inputs one at a time 15 | initial begin 16 | $dumpvars(0, and_gate_testbench); 17 | 18 | a = 0; 19 | b = 0; 20 | #10; 21 | a = 0; 22 | b = 1; 23 | #10; 24 | a = 1; 25 | b = 0; 26 | #10; 27 | a = 1; 28 | b = 1; 29 | #10; 30 | 31 | $display("End of simulation"); 32 | $finish; 33 | 34 | end 35 | endmodule 36 | -------------------------------------------------------------------------------- /examples/edu-ciaa-fpga/and-gate-sv/apio.ini: -------------------------------------------------------------------------------- 1 | ; Apio project configuration file. 2 | ; Type 'apio info apio.ini' for details. 3 | 4 | [env:default] 5 | board = edu-ciaa-fpga 6 | top-module = and_gate 7 | 8 | -------------------------------------------------------------------------------- /examples/edu-ciaa-fpga/and-gate-sv/info: -------------------------------------------------------------------------------- 1 | Experimental system-verilog -------------------------------------------------------------------------------- /examples/edu-ciaa-fpga/blinky/Blinky.v: -------------------------------------------------------------------------------- 1 | //------------------------------------------------------------------ 2 | //-- Blinking LED 3 | //------------------------------------------------------------------ 4 | 5 | module Test ( 6 | input CLK, // 12MHz clock 7 | output LED0 // D6 8 | ); 9 | 10 | reg [23:0] counter = 0; 11 | 12 | always @(posedge CLK) counter <= counter + 1; 13 | 14 | assign LED0 = counter[23]; 15 | 16 | endmodule 17 | 18 | 19 | -------------------------------------------------------------------------------- /examples/edu-ciaa-fpga/blinky/apio.ini: -------------------------------------------------------------------------------- 1 | ; Apio project configuration file. 2 | ; Type 'apio info apio.ini' for details. 3 | 4 | [env:default] 5 | board = edu-ciaa-fpga 6 | top-module = Test 7 | -------------------------------------------------------------------------------- /examples/edu-ciaa-fpga/blinky/info: -------------------------------------------------------------------------------- 1 | Blinking a led -------------------------------------------------------------------------------- /examples/edu-ciaa-fpga/led-green/apio.ini: -------------------------------------------------------------------------------- 1 | ; Apio project configuration file. 2 | ; Type 'apio info apio.ini' for details. 3 | 4 | [env:default] 5 | board = edu-ciaa-fpga 6 | top-module = leds 7 | -------------------------------------------------------------------------------- /examples/edu-ciaa-fpga/led-green/info: -------------------------------------------------------------------------------- 1 | Truning on a led -------------------------------------------------------------------------------- /examples/edu-ciaa-fpga/led-green/led_green.pcf: -------------------------------------------------------------------------------- 1 | # ----------------------------------------------------------------------------- 2 | #- EDU-CIAA-FPGA constraint file (.pcf) 3 | #- Sep - 2020 4 | #- GPL license 5 | #- Repo: https://gitlab.com/educiaafpga 6 | # ----------------------------------------------------------------------------- 7 | 8 | #------ User LEDs 9 | #-- Green LED 10 | set_io LEDG 4 #-- output 11 | 12 | 13 | 14 | 15 | -------------------------------------------------------------------------------- /examples/edu-ciaa-fpga/led-green/led_green.v: -------------------------------------------------------------------------------- 1 | //------------------------------------------------------------------ 2 | //-- Hello world example for the EDU-CIAA-FPGA 3 | //-- Turn on the green LED 4 | //------------------------------------------------------------------ 5 | module leds ( 6 | output wire LEDG 7 | ); 8 | 9 | assign LEDG = 1'b1; 10 | 11 | endmodule 12 | 13 | -------------------------------------------------------------------------------- /examples/edu-ciaa-fpga/template/apio.ini: -------------------------------------------------------------------------------- 1 | ; Apio project configuration file. 2 | ; Type 'apio info apio.ini' for details. 3 | 4 | [env:default] 5 | board = edu-ciaa-fpga 6 | top-module = Test 7 | -------------------------------------------------------------------------------- /examples/edu-ciaa-fpga/template/info: -------------------------------------------------------------------------------- 1 | Project template -------------------------------------------------------------------------------- /examples/edu-ciaa-fpga/template/test.v: -------------------------------------------------------------------------------- 1 | //------------------------------------------------------------------ 2 | //-- Top-level Verilog example 3 | //------------------------------------------------------------------ 4 | 5 | module Test ( 6 | input CLK, // 12MHz clock 7 | output LED0 // D6 8 | ); 9 | 10 | reg [23:0] counter = 0; 11 | 12 | always @(posedge CLK) counter <= counter + 1; 13 | 14 | assign LED0 = counter[23]; 15 | 16 | endmodule 17 | -------------------------------------------------------------------------------- /examples/fomu/blink/apio.ini: -------------------------------------------------------------------------------- 1 | ; Apio project configuration file. 2 | ; Type 'apio info apio.ini' for details. 3 | 4 | [env:default] 5 | board = fomu 6 | top-module = top 7 | -------------------------------------------------------------------------------- /examples/fomu/blink/info: -------------------------------------------------------------------------------- 1 | Tri-colour led blink -------------------------------------------------------------------------------- /examples/fomu/blink/pinout.pcf: -------------------------------------------------------------------------------- 1 | set_io -nowarn rgb0 A5 2 | set_io -nowarn rgb1 B5 3 | set_io -nowarn rgb2 C5 4 | set_io -nowarn pmod_1 E4 5 | set_io -nowarn pmod_2 D5 6 | set_io -nowarn pmod_3 E5 7 | set_io -nowarn pmod_4 F5 8 | set_io -nowarn pmoda_1 E4 9 | set_io -nowarn pmoda_2 D5 10 | set_io -nowarn pmoda_3 E5 11 | set_io -nowarn pmoda_4 F5 12 | set_io -nowarn clki F4 13 | set_io -nowarn user_1 E4 14 | set_io -nowarn user_2 D5 15 | set_io -nowarn user_3 E5 16 | set_io -nowarn user_4 F5 17 | set_io -nowarn touch_1 E4 18 | set_io -nowarn touch_2 D5 19 | set_io -nowarn touch_3 E5 20 | set_io -nowarn touch_4 F5 21 | set_io -nowarn spi_mosi F1 22 | set_io -nowarn spi_miso E1 23 | set_io -nowarn spi_clk D1 24 | set_io -nowarn spi_io2 F2 25 | set_io -nowarn spi_io3 B1 26 | set_io -nowarn spi_cs C1 27 | set_io -nowarn usb_dn A2 28 | set_io -nowarn usb_dp A1 29 | set_io -nowarn usb_dp_pu A4 30 | -------------------------------------------------------------------------------- /examples/fomu/dsp/apio.ini: -------------------------------------------------------------------------------- 1 | ; Apio project configuration file. 2 | ; Type 'apio info apio.ini' for details. 3 | 4 | [env:default] 5 | board = fomu 6 | top-module = main 7 | 8 | ; This option enables the use of ICESTORM_DSP cells as viewed 9 | ; using the 'apio report' command. 10 | yosys-synth-extra-options = -dsp 11 | -------------------------------------------------------------------------------- /examples/fomu/dsp/info: -------------------------------------------------------------------------------- 1 | Using -dsp to enable DSP cells. 2 | -------------------------------------------------------------------------------- /examples/fomu/dsp/main.v: -------------------------------------------------------------------------------- 1 | // This example demonstrates the effect the -dsp has on the 2 | // synthesis phase. See apio.ini for the option definition 3 | // and use 'apio report' to see how yosys shifts the implemeation 4 | // from ICESTORM_DSP and ICESTORM_LC cells. 5 | 6 | module main ( 7 | 8 | input clki, 9 | input user_1, // serial data in. 10 | output reg user_2, // serial data out 11 | 12 | // USB Pins (which should be statically driven if not being used). 13 | output usb_dp, 14 | output usb_dn, 15 | output usb_dp_pu 16 | ); 17 | 18 | // Prevent the host from trying to connect to this design. 19 | assign usb_dp = 1'b0; 20 | assign usb_dn = 1'b0; 21 | assign usb_dp_pu = 1'b0; 22 | 23 | // The size of each of the serial registers. 24 | // TODO: Why this fails with N = 40. 25 | localparam N = 32; 26 | 27 | // The two words we multiply. 28 | reg [N-1:0] reg1; 29 | reg [N-1:0] reg2; 30 | 31 | always @(posedge clki) begin 32 | // Shift din into 2 x N words 33 | reg1 <= {reg1[N-2:0], user_1}; 34 | reg2 <= {reg1[N-2:0], reg1[N-1]}; 35 | // Multiply the words, and output the parity of the result. 36 | user_2 <= ~^(reg1 * reg2); 37 | end 38 | 39 | endmodule 40 | -------------------------------------------------------------------------------- /examples/fomu/dsp/main_tb.gtkw: -------------------------------------------------------------------------------- 1 | [*] 2 | [*] GTKWave Analyzer v3.4.0 (w)1999-2022 BSI 3 | [*] Thu Jan 23 06:27:03 2025 4 | [*] 5 | [dumpfile] "/Volumes/projects/apio-examples/repo/examples/fomu/dsp/_build/main_tb.vcd" 6 | [dumpfile_mtime] "Thu Jan 23 06:25:12 2025" 7 | [dumpfile_size] 21907 8 | [savefile] "/Volumes/projects/apio-examples/repo/examples/fomu/dsp/main_tb.gtkw" 9 | [timestart] 0 10 | [size] 1408 825 11 | [pos] -1 -1 12 | *-22.912270 13570000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 13 | [treeopen] main_tb. 14 | [sst_width] 253 15 | [signals_width] 111 16 | [sst_expanded] 1 17 | [sst_vpaned_height] 237 18 | @420 19 | main_tb.clk_num 20 | @28 21 | main_tb.clk 22 | @200 23 | - 24 | @28 25 | main_tb.user_1 26 | @29 27 | [color] 2 28 | main_tb.user_2 29 | @200 30 | - 31 | @22 32 | main_tb.tested.reg1[31:0] 33 | main_tb.tested.reg2[31:0] 34 | [pattern_trace] 1 35 | [pattern_trace] 0 36 | -------------------------------------------------------------------------------- /examples/fomu/dsp/main_tb.v: -------------------------------------------------------------------------------- 1 | 2 | `include "apio_testing.vh" 3 | 4 | `timescale 10 ns / 1 ns 5 | 6 | 7 | module main_tb (); 8 | 9 | `DEF_CLK 10 | 11 | // Inputs 12 | wire user_1 = ^clk_num; 13 | 14 | // Outputs 15 | wire user_2; 16 | 17 | 18 | main tested ( 19 | .clki(clk), 20 | .user_1(user_1), 21 | .user_2(user_2), 22 | .usb_dp(), 23 | .usb_dn(), 24 | .usb_dp_pu() 25 | ); 26 | 27 | 28 | 29 | // The test sequence. 30 | initial begin 31 | `TEST_BEGIN(main_tb) 32 | 33 | `CLKS(200) 34 | 35 | `TEST_END 36 | end 37 | 38 | endmodule 39 | -------------------------------------------------------------------------------- /examples/fomu/dsp/pinout.pcf: -------------------------------------------------------------------------------- 1 | set_io -nowarn rgb0 A5 2 | set_io -nowarn rgb1 B5 3 | set_io -nowarn rgb2 C5 4 | set_io -nowarn pmod_1 E4 5 | set_io -nowarn pmod_2 D5 6 | set_io -nowarn pmod_3 E5 7 | set_io -nowarn pmod_4 F5 8 | set_io -nowarn pmoda_1 E4 9 | set_io -nowarn pmoda_2 D5 10 | set_io -nowarn pmoda_3 E5 11 | set_io -nowarn pmoda_4 F5 12 | set_io -nowarn clki F4 13 | set_io -nowarn user_1 E4 14 | set_io -nowarn user_2 D5 15 | set_io -nowarn user_3 E5 16 | set_io -nowarn user_4 F5 17 | set_io -nowarn touch_1 E4 18 | set_io -nowarn touch_2 D5 19 | set_io -nowarn touch_3 E5 20 | set_io -nowarn touch_4 F5 21 | set_io -nowarn spi_mosi F1 22 | set_io -nowarn spi_miso E1 23 | set_io -nowarn spi_clk D1 24 | set_io -nowarn spi_io2 F2 25 | set_io -nowarn spi_io3 B1 26 | set_io -nowarn spi_cs C1 27 | set_io -nowarn usb_dn A2 28 | set_io -nowarn usb_dp A1 29 | set_io -nowarn usb_dp_pu A4 30 | -------------------------------------------------------------------------------- /examples/go-board/blinky/Blinky.v: -------------------------------------------------------------------------------- 1 | //------------------------------------------------------------------ 2 | //-- Blinking LED 3 | //------------------------------------------------------------------ 4 | 5 | module Test ( 6 | input CLK, // 25MHz clock 7 | output LED1, //-- LED to Blink 8 | //-- The other LEDs 9 | output LED2, 10 | output LED3, 11 | output LED4 12 | ); 13 | 14 | reg [23:0] counter = 0; 15 | 16 | always @(posedge CLK) counter <= counter + 1; 17 | 18 | assign LED1 = counter[23]; 19 | 20 | //-- Turn off the other LEDs 21 | assign {LED2, LED3, LED4} = 3'b0; 22 | 23 | endmodule 24 | 25 | -------------------------------------------------------------------------------- /examples/go-board/blinky/apio.ini: -------------------------------------------------------------------------------- 1 | ; Apio project configuration file. 2 | ; Type 'apio info apio.ini' for details. 3 | 4 | [env:default] 5 | board = go-board 6 | top-module = Test 7 | -------------------------------------------------------------------------------- /examples/go-board/blinky/info: -------------------------------------------------------------------------------- 1 | Blinking a led -------------------------------------------------------------------------------- /examples/go-board/leds/apio.ini: -------------------------------------------------------------------------------- 1 | ; Apio project configuration file. 2 | ; Type 'apio info apio.ini' for details. 3 | 4 | [env:default] 5 | board = go-board 6 | top-module = leds 7 | -------------------------------------------------------------------------------- /examples/go-board/leds/info: -------------------------------------------------------------------------------- 1 | Turning all leds on -------------------------------------------------------------------------------- /examples/go-board/leds/leds.pcf: -------------------------------------------------------------------------------- 1 | # ----------------------------------------------------------------------------- 2 | #- Leds example for the Nanland go-board 3 | #- Constraint file (.pcf) 4 | #- By Juan Gonzalez (Obijuan) 5 | #- April - 2016 6 | #- GPL license 7 | #- Data obtained from the go-board official constraint file: 8 | #- https://www.nandland.com/goboard/Go_Board_Constraints.pcf 9 | #- 10 | # ----------------------------------------------------------------------------- 11 | # -- Board info: https://www.nandland.com/goboard/introduction.html 12 | # -- Pinout: https://www.nandland.com/goboard/images/Go_Board_V1.pdf 13 | 14 | # ------------ User Leds ------------------------------------------------------ 15 | set_io LED1 56 16 | set_io LED2 57 17 | set_io LED3 59 18 | set_io LED4 60 19 | -------------------------------------------------------------------------------- /examples/go-board/leds/leds.v: -------------------------------------------------------------------------------- 1 | //------------------------------------------------------------------ 2 | //-- Hello world example for the nandland go-board 3 | //-- Turn on all the leds 4 | //------------------------------------------------------------------ 5 | 6 | module leds ( 7 | output wire LED1, 8 | output wire LED2, 9 | output wire LED3, 10 | output wire LED4 11 | ); 12 | 13 | assign LED1 = 1'b1; 14 | assign LED2 = 1'b1; 15 | assign LED3 = 1'b1; 16 | assign LED4 = 1'b1; 17 | 18 | endmodule 19 | -------------------------------------------------------------------------------- /examples/go-board/leds/leds_tb.gtkw: -------------------------------------------------------------------------------- 1 | [*] 2 | [*] GTKWave Analyzer v3.3.66 (w)1999-2015 BSI 3 | [*] Mon Aug 29 09:15:38 2016 4 | [*] 5 | [dumpfile] "/home/jesus/code/apio-examples/go-board-leds/leds_tb.vcd" 6 | [dumpfile_mtime] "Mon Aug 29 09:15:35 2016" 7 | [dumpfile_size] 567 8 | [savefile] "/home/jesus/code/apio-examples/go-board-leds/leds_tb.gtkw" 9 | [timestart] 0 10 | [size] 1000 600 11 | [pos] 12 0 12 | *0.000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 13 | [treeopen] leds_tb. 14 | [sst_width] 223 15 | [signals_width] 78 16 | [sst_expanded] 1 17 | [sst_vpaned_height] 160 18 | @28 19 | leds_tb.UUT.LED1 20 | leds_tb.UUT.LED2 21 | leds_tb.UUT.LED3 22 | @29 23 | leds_tb.UUT.LED4 24 | [pattern_trace] 1 25 | [pattern_trace] 0 26 | -------------------------------------------------------------------------------- /examples/go-board/leds/leds_tb.v: -------------------------------------------------------------------------------- 1 | //------------------------------------------------------------------- 2 | //-- leds_tb.v 3 | //-- Testbench 4 | //------------------------------------------------------------------- 5 | //-- Juan Gonzalez (Obijuan) 6 | //-- Jesus Arroyo Torrens 7 | //-- GPL license 8 | //------------------------------------------------------------------- 9 | `default_nettype none `timescale 100 ns / 10 ns 10 | 11 | module leds_tb (); 12 | 13 | //-- Simulation time: 1us (10 * 100ns) 14 | parameter DURATION = 10; 15 | 16 | //-- Clock signal. It is not used in this simulation 17 | reg clk = 0; 18 | always #0.5 clk = ~clk; 19 | 20 | //-- Leds port 21 | wire l1, l2, l3, l4; 22 | 23 | //-- Instantiate the unit to test 24 | leds UUT ( 25 | .LED1(l1), 26 | .LED2(l2), 27 | .LED3(l3), 28 | .LED4(l4) 29 | ); 30 | 31 | 32 | initial begin 33 | 34 | //-- Dump vars to the .vcd output file 35 | $dumpvars(0, leds_tb); 36 | 37 | #(DURATION) $display("End of simulation"); 38 | $finish; 39 | end 40 | 41 | endmodule 42 | -------------------------------------------------------------------------------- /examples/go-board/template/apio.ini: -------------------------------------------------------------------------------- 1 | ; Apio project configuration file. 2 | ; Type 'apio info apio.ini' for details. 3 | 4 | [env:default] 5 | board = go-board 6 | top-module = top 7 | -------------------------------------------------------------------------------- /examples/go-board/template/info: -------------------------------------------------------------------------------- 1 | Project template -------------------------------------------------------------------------------- /examples/go-board/template/main.v: -------------------------------------------------------------------------------- 1 | //------------------------------------------------------------------ 2 | //-- Verilog template 3 | //-- Top entity 4 | //-- Board: Nandland go-board 5 | //------------------------------------------------------------------ 6 | `default_nettype none 7 | 8 | //-- Template for the top entity 9 | module top ( 10 | output wire LED1 11 | ); 12 | 13 | //-- Turn on the D1 (red led) on the icestick 14 | assign LED1 = 1'b1; 15 | 16 | endmodule 17 | -------------------------------------------------------------------------------- /examples/go-board/template/main_tb.gtkw: -------------------------------------------------------------------------------- 1 | [*] 2 | [*] GTKWave Analyzer v3.4.0 (w)1999-2022 BSI 3 | [*] Wed Dec 18 19:00:23 2024 4 | [*] 5 | [dumpfile] "/Volumes/projects/apio-examples/repo/examples/go-board/template/_build/main_tb.vcd" 6 | [dumpfile_mtime] "Wed Dec 18 19:00:11 2024" 7 | [dumpfile_size] 596 8 | [savefile] "/Volumes/projects/apio-examples/repo/examples/go-board/template/main_tb.gtkw" 9 | [timestart] 0 10 | [size] 1000 600 11 | [pos] -1 -1 12 | *-18.251245 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 13 | [treeopen] main_tb. 14 | [sst_width] 253 15 | [signals_width] 78 16 | [sst_expanded] 1 17 | [sst_vpaned_height] 158 18 | @28 19 | main_tb.clk 20 | @29 21 | main_tb.l1 22 | [pattern_trace] 1 23 | [pattern_trace] 0 24 | -------------------------------------------------------------------------------- /examples/go-board/template/main_tb.v: -------------------------------------------------------------------------------- 1 | //------------------------------------------------------------------ 2 | //-- Verilog template 3 | //-- Test-bench entity 4 | //-- Board: Nandland go-board 5 | //------------------------------------------------------------------ 6 | 7 | `default_nettype none `timescale 100 ns / 10 ns 8 | 9 | module main_tb (); 10 | 11 | //-- Simulation time: 1us (10 * 100ns) 12 | parameter DURATION = 10; 13 | 14 | //-- Clock signal. It is not used in this simulation 15 | reg clk = 0; 16 | always #0.5 clk = ~clk; 17 | 18 | //-- Led port 19 | wire l1; 20 | 21 | //-- Instantiation of the unit to test 22 | top UUT (.LED1(l1)); 23 | 24 | 25 | initial begin 26 | 27 | //-- Dump vars to the .vcd output file 28 | $dumpvars(0, main_tb); 29 | 30 | #(DURATION) $display("End of simulation"); 31 | $finish; 32 | end 33 | 34 | endmodule 35 | -------------------------------------------------------------------------------- /examples/ice40-hx1k-evb/leds/apio.ini: -------------------------------------------------------------------------------- 1 | ; Apio project configuration file. 2 | ; Type 'apio info apio.ini' for details. 3 | 4 | [env:default] 5 | board = ice40-hx1k-evb 6 | top-module = leds 7 | -------------------------------------------------------------------------------- /examples/ice40-hx1k-evb/leds/info: -------------------------------------------------------------------------------- 1 | Turning leds on/off -------------------------------------------------------------------------------- /examples/ice40-hx1k-evb/leds/leds.pcf: -------------------------------------------------------------------------------- 1 | # in the pcf (physical constrain file) 2 | # the external pins of the fpga are defined 3 | # compare to the schematic of the board and the datasheet of fpga 4 | 5 | set_io -nowarn clk_in 15 6 | set_io but[0] 41 7 | set_io but[1] 42 8 | set_io led[0] 40 9 | set_io led[1] 51 10 | 11 | -------------------------------------------------------------------------------- /examples/ice40-hx1k-evb/leds/leds.v: -------------------------------------------------------------------------------- 1 | //------------------------------------------------------------------ 2 | //-- Hello world example 3 | //-- Control leds by pushing the buttons 4 | //-- This example has been tested on the following boards: 5 | //-- * iCE40-HX1K-EVB Olimex 6 | //------------------------------------------------------------------ 7 | 8 | module leds ( 9 | output wire [1:0] led, 10 | input wire [1:0] but 11 | ); 12 | 13 | assign led[0] = but[0]; 14 | assign led[1] = but[1]; 15 | 16 | endmodule 17 | -------------------------------------------------------------------------------- /examples/ice40-hx1k-evb/leds/leds_tb.gtkw: -------------------------------------------------------------------------------- 1 | [*] 2 | [*] GTKWave Analyzer v3.3.98 (w)1999-2019 BSI 3 | [*] Thu May 21 10:25:11 2020 4 | [*] 5 | [dumpfile] "/home/micha/git/gitlab/leds/leds_tb.vcd" 6 | [dumpfile_mtime] "Thu May 21 10:24:51 2020" 7 | [dumpfile_size] 1151 8 | [savefile] "/home/micha/git/gitlab/leds/leds_tb.gtkw" 9 | [timestart] 0 10 | [size] 1000 600 11 | [pos] 12 0 12 | *-20.000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 13 | [treeopen] leds_tb. 14 | [sst_width] 238 15 | [signals_width] 94 16 | [sst_expanded] 1 17 | [sst_vpaned_height] 160 18 | @28 19 | leds_tb.UUT.but[1:0] 20 | @29 21 | leds_tb.UUT.led[1:0] 22 | [pattern_trace] 1 23 | [pattern_trace] 0 24 | -------------------------------------------------------------------------------- /examples/ice40-hx1k-evb/leds/leds_tb.v: -------------------------------------------------------------------------------- 1 | //------------------------------------------------------------------- 2 | //-- leds_tb.v 3 | //-- Testbench 4 | //------------------------------------------------------------------- 5 | //-- Michael Schröder 6 | //-- GPL license 7 | //------------------------------------------------------------------- 8 | `default_nettype none `timescale 100 ns / 10 ns 9 | 10 | module leds_tb (); 11 | 12 | //-- Simulation time: 1us (10 * 100ns) 13 | parameter DURATION = 10; 14 | 15 | //-- Clock signal. It is not used in this simulation 16 | reg clk = 0; 17 | always #0.5 clk = ~clk; 18 | 19 | //-- Leds port 20 | wire [1:0] led; 21 | reg [1:0] but; 22 | 23 | //-- Instantiate the unit to test 24 | leds UUT ( 25 | .led(led), 26 | .but(but) 27 | ); 28 | 29 | 30 | initial begin 31 | 32 | //-- Dump vars to the .vcd output file 33 | $dumpvars(0, leds_tb); 34 | #5 but = 0; 35 | #5 but = 1; 36 | #5 but = 2; 37 | #5 but = 3; 38 | 39 | #(DURATION) $display("End of simulation"); 40 | $finish; 41 | end 42 | 43 | endmodule 44 | -------------------------------------------------------------------------------- /examples/ice40-hx8k-evb/leds/apio.ini: -------------------------------------------------------------------------------- 1 | ; Apio project configuration file. 2 | ; Type 'apio info apio.ini' for details. 3 | 4 | [env:default] 5 | board = ice40-hx8k-evb 6 | top-module = leds 7 | -------------------------------------------------------------------------------- /examples/ice40-hx8k-evb/leds/info: -------------------------------------------------------------------------------- 1 | Turning leds on/off -------------------------------------------------------------------------------- /examples/ice40-hx8k-evb/leds/leds.pcf: -------------------------------------------------------------------------------- 1 | # physical constrain file 2 | # assign io-pins to pin numbering of iCE40-HX8K on olimex board iCE40-HX8K-EVB 3 | # compare to the schematic of the board and the datasheet of fpga 4 | 5 | #set_io clk_in J3 6 | set_io but[0] K11 7 | set_io but[1] P13 8 | 9 | set_io led[0] M12 10 | set_io led[1] R16 11 | 12 | #set_io rx L11 # UEXT 13 | #set_io tx T16 # UEXT 14 | 15 | #set_io sram_addr[0] N6 16 | #set_io sram_addr[1] T1 17 | #set_io sram_addr[2] P4 18 | #set_io sram_addr[3] R2 19 | #set_io sram_addr[4] N5 20 | #set_io sram_addr[5] T2 21 | #set_io sram_addr[6] P5 22 | #set_io sram_addr[7] R3 23 | #set_io sram_addr[8] R5 24 | #set_io sram_addr[9] T3 25 | #set_io sram_addr[10] R4 26 | #set_io sram_addr[11] M7 27 | #set_io sram_addr[12] N7 28 | #set_io sram_addr[13] P6 29 | #set_io sram_addr[14] M8 30 | #set_io sram_addr[15] T5 31 | #set_io sram_addr[16] R6 32 | #set_io sram_addr[17] P8 33 | 34 | #set_io sram_cen T6 35 | #set_io sram_oen L9 36 | #set_io sram_wen T7 37 | 38 | #set_io sram_data[0] T8 39 | #set_io sram_data[1] P7 40 | #set_io sram_data[2] N9 41 | #set_io sram_data[3] T9 42 | #set_io sram_data[4] M9 43 | #set_io sram_data[5] R9 44 | #set_io sram_data[6] K9 45 | #set_io sram_data[7] P9 46 | #set_io sram_data[8] R10 47 | #set_io sram_data[9] L10 48 | #set_io sram_data[10] P10 49 | #set_io sram_data[11] N10 50 | #set_io sram_data[12] T10 51 | #set_io sram_data[13] T11 52 | #set_io sram_data[14] T15 53 | #set_io sram_data[15] T14 54 | -------------------------------------------------------------------------------- /examples/ice40-hx8k-evb/leds/leds.v: -------------------------------------------------------------------------------- 1 | //------------------------------------------------------------------ 2 | //-- Hello world example 3 | //-- Control leds by pushing the buttons 4 | //-- This example has been tested on the following boards: 5 | //-- * iCE40-HX1K-EVB Olimex 6 | //------------------------------------------------------------------ 7 | 8 | module leds ( 9 | output wire [1:0] led, 10 | input wire [1:0] but 11 | ); 12 | 13 | assign led[0] = but[0]; 14 | assign led[1] = but[1]; 15 | 16 | endmodule 17 | -------------------------------------------------------------------------------- /examples/ice40-hx8k-evb/leds/leds_tb.gtkw: -------------------------------------------------------------------------------- 1 | [*] 2 | [*] GTKWave Analyzer v3.4.0 (w)1999-2022 BSI 3 | [*] Wed Dec 18 19:01:23 2024 4 | [*] 5 | [dumpfile] "/Volumes/projects/apio-examples/repo/examples/ice40-hx8k-evb/leds/_build/leds_tb.vcd" 6 | [dumpfile_mtime] "Wed Dec 18 19:00:48 2024" 7 | [dumpfile_size] 1250 8 | [savefile] "/Volumes/projects/apio-examples/repo/examples/ice40-hx8k-evb/leds/leds_tb.gtkw" 9 | [timestart] 0 10 | [size] 1000 600 11 | [pos] -1 -1 12 | *-19.836206 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 13 | [treeopen] leds_tb. 14 | [sst_width] 253 15 | [signals_width] 95 16 | [sst_expanded] 1 17 | [sst_vpaned_height] 158 18 | @28 19 | leds_tb.clk 20 | leds_tb.led[1:0] 21 | leds_tb.but[1:0] 22 | [pattern_trace] 1 23 | [pattern_trace] 0 24 | -------------------------------------------------------------------------------- /examples/ice40-hx8k-evb/leds/leds_tb.v: -------------------------------------------------------------------------------- 1 | //------------------------------------------------------------------- 2 | //-- leds_tb.v 3 | //-- Testbench 4 | //------------------------------------------------------------------- 5 | //-- Michael Schröder 6 | //-- GPL license 7 | //------------------------------------------------------------------- 8 | `default_nettype none `timescale 100 ns / 10 ns 9 | 10 | module leds_tb (); 11 | 12 | //-- Simulation time: 1us (10 * 100ns) 13 | parameter DURATION = 10; 14 | 15 | //-- Clock signal. It is not used in this simulation 16 | reg clk = 0; 17 | always #0.5 clk = ~clk; 18 | 19 | //-- Leds port 20 | wire [1:0] led; 21 | reg [1:0] but; 22 | 23 | //-- Instantiate the unit to test 24 | leds UUT ( 25 | .led(led), 26 | .but(but) 27 | ); 28 | 29 | 30 | initial begin 31 | 32 | //-- Dump vars to the .vcd output file 33 | $dumpvars(0, leds_tb); 34 | #5 but = 0; 35 | #5 but = 1; 36 | #5 but = 2; 37 | #5 but = 3; 38 | 39 | #(DURATION) $display("End of simulation"); 40 | $finish; 41 | end 42 | 43 | endmodule 44 | -------------------------------------------------------------------------------- /examples/ice40-hx8k/leds/apio.ini: -------------------------------------------------------------------------------- 1 | ; Apio project configuration file. 2 | ; Type 'apio info apio.ini' for details. 3 | 4 | [env:default] 5 | board = ice40-hx8k 6 | top-module = leds 7 | -------------------------------------------------------------------------------- /examples/ice40-hx8k/leds/info: -------------------------------------------------------------------------------- 1 | Turning all the leds on -------------------------------------------------------------------------------- /examples/ice40-hx8k/leds/leds.pcf: -------------------------------------------------------------------------------- 1 | # ----------------------------------------------------------------------------- 2 | #- Leds example for the iCE40-HX8K board 3 | #- Constraint file (.pcf) 4 | #- By Jesus Arroyo 5 | #- August - 2016 6 | #- GPL license 7 | # ----------------------------------------------------------------------------- 8 | # -- Pinout: 9 | # -- Guide: 10 | 11 | # ------------ User Leds ------------------------------------------------------ 12 | set_io D2 C3 13 | set_io D3 B3 14 | set_io D4 C4 15 | set_io D5 C5 16 | set_io D6 A1 17 | set_io D7 A2 18 | set_io D8 B4 19 | set_io D9 B5 20 | -------------------------------------------------------------------------------- /examples/ice40-hx8k/leds/leds.v: -------------------------------------------------------------------------------- 1 | //------------------------------------------------------------------ 2 | //-- Hello world example for the iCE40-HX8K board 3 | //-- Turn on all the leds 4 | //------------------------------------------------------------------ 5 | 6 | module leds ( 7 | output wire D2, 8 | output wire D3, 9 | output wire D4, 10 | output wire D5, 11 | output wire D6, 12 | output wire D7, 13 | output wire D8, 14 | output wire D9 15 | ); 16 | 17 | assign D2 = 1'b1; 18 | assign D3 = 1'b1; 19 | assign D4 = 1'b1; 20 | assign D5 = 1'b1; 21 | assign D6 = 1'b1; 22 | assign D7 = 1'b1; 23 | assign D8 = 1'b1; 24 | assign D9 = 1'b1; 25 | 26 | endmodule 27 | -------------------------------------------------------------------------------- /examples/ice40-hx8k/leds/leds_tb.gtkw: -------------------------------------------------------------------------------- 1 | [*] 2 | [*] GTKWave Analyzer v3.3.66 (w)1999-2015 BSI 3 | [*] Mon Aug 29 10:04:11 2016 4 | [*] 5 | [dumpfile] "/home/jesus/code/apio-examples/iCE40-HX8K-leds/leds_tb.vcd" 6 | [dumpfile_mtime] "Mon Aug 29 10:03:23 2016" 7 | [dumpfile_size] 747 8 | [savefile] "/home/jesus/code/apio-examples/iCE40-HX8K-leds/leds_tb.gtkw" 9 | [timestart] 0 10 | [size] 1000 600 11 | [pos] 507 137 12 | *0.000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 13 | [treeopen] leds_tb. 14 | [sst_width] 223 15 | [signals_width] 78 16 | [sst_expanded] 1 17 | [sst_vpaned_height] 160 18 | @28 19 | leds_tb.UUT.D2 20 | leds_tb.UUT.D3 21 | leds_tb.UUT.D4 22 | leds_tb.UUT.D5 23 | @29 24 | leds_tb.UUT.D6 25 | leds_tb.UUT.D7 26 | leds_tb.UUT.D8 27 | leds_tb.UUT.D9 28 | [pattern_trace] 1 29 | [pattern_trace] 0 30 | -------------------------------------------------------------------------------- /examples/ice40-hx8k/leds/leds_tb.v: -------------------------------------------------------------------------------- 1 | //------------------------------------------------------------------- 2 | //-- leds_tb.v 3 | //-- Testbench 4 | //------------------------------------------------------------------- 5 | //-- Juan Gonzalez (Obijuan) 6 | //-- Jesus Arroyo Torrens 7 | //-- GPL license 8 | //------------------------------------------------------------------- 9 | `default_nettype none `timescale 100 ns / 10 ns 10 | 11 | module leds_tb (); 12 | 13 | //-- Simulation time: 1us (10 * 100ns) 14 | parameter DURATION = 10; 15 | 16 | //-- Clock signal. It is not used in this simulation 17 | reg clk = 0; 18 | always #0.5 clk = ~clk; 19 | 20 | //-- Leds port 21 | wire d2, d3, d4, d5, d6, d7, d8, d9; 22 | 23 | //-- Instantiate the unit to test 24 | leds UUT ( 25 | .D2(d2), 26 | .D3(d3), 27 | .D4(d4), 28 | .D5(d5), 29 | .D6(d6), 30 | .D7(d7), 31 | .D8(d8), 32 | .D9(d9) 33 | ); 34 | 35 | 36 | initial begin 37 | 38 | //-- Dump vars to the .vcd output file 39 | $dumpvars(0, leds_tb); 40 | 41 | #(DURATION) $display("End of simulation"); 42 | $finish; 43 | end 44 | 45 | endmodule 46 | -------------------------------------------------------------------------------- /examples/ice40-up5k/blinky/apio.ini: -------------------------------------------------------------------------------- 1 | ; Apio project configuration file. 2 | ; Type 'apio info apio.ini' for details. 3 | 4 | [env:default] 5 | board = ice40-up5k 6 | top-module = rgb_test 7 | -------------------------------------------------------------------------------- /examples/ice40-up5k/blinky/blink.v: -------------------------------------------------------------------------------- 1 | 2 | module rgb_test ( 3 | input clk, 4 | output led_blue, 5 | output led_green, 6 | output led_red 7 | ); 8 | 9 | 10 | //-- Modify this value for changing the blink frequency 11 | localparam N = 24; //-- N<=21 Fast, N>=23 Slow 12 | 13 | reg [N:0] counter; 14 | always @(posedge clk) counter <= counter + 1; 15 | 16 | assign led_green = counter[N]; 17 | assign led_blue = counter[N-1]; 18 | assign led_red = counter[N-2]; 19 | 20 | endmodule 21 | -------------------------------------------------------------------------------- /examples/ice40-up5k/blinky/info: -------------------------------------------------------------------------------- 1 | Blink the RGB led -------------------------------------------------------------------------------- /examples/ice40-up5k/blinky/up5k.pcf: -------------------------------------------------------------------------------- 1 | 2 | set_io -nowarn led_blue 39 3 | set_io -nowarn led_green 40 4 | set_io -nowarn led_red 41 5 | set_io -nowarn clk 35 6 | 7 | 8 | 9 | -------------------------------------------------------------------------------- /examples/ice40-up5k/led-green/apio.ini: -------------------------------------------------------------------------------- 1 | ; Apio project configuration file. 2 | ; Type 'apio info apio.ini' for details. 3 | 4 | [env:default] 5 | board = ice40-up5k 6 | top-module = rgb_test 7 | -------------------------------------------------------------------------------- /examples/ice40-up5k/led-green/info: -------------------------------------------------------------------------------- 1 | Turning the RGB led green -------------------------------------------------------------------------------- /examples/ice40-up5k/led-green/led-green.v: -------------------------------------------------------------------------------- 1 | //-- Turning the RGB LED into Green 2 | //-- Board: iCE40-UP5K 3 | module rgb_test ( 4 | output led_blue, 5 | output led_green, 6 | output led_red 7 | ); 8 | 9 | //-- Turn on the green signal (inverse logic) 10 | //-- Turn off the red and blue signals (inverse logic) 11 | 12 | assign led_red = 1; //-- RED off 13 | assign led_green = 0; //-- Green ON 14 | assign led_blue = 1; //-- Blue off 15 | 16 | endmodule 17 | -------------------------------------------------------------------------------- /examples/ice40-up5k/led-green/up5k.pcf: -------------------------------------------------------------------------------- 1 | 2 | set_io -nowarn led_blue 39 3 | set_io -nowarn led_green 40 4 | set_io -nowarn led_red 41 5 | set_io -nowarn clk 35 6 | set_io -nowarn sw3 23 7 | set_io -nowarn sw2 25 8 | set_io -nowarn sw1 34 9 | set_io -nowarn sw0 43 10 | 11 | 12 | 13 | 14 | 15 | -------------------------------------------------------------------------------- /examples/ice40-up5k/switches/apio.ini: -------------------------------------------------------------------------------- 1 | ; Apio project configuration file. 2 | ; Type 'apio info apio.ini' for details. 3 | 4 | [env:default] 5 | board = ice40-up5k 6 | top-module = rgb_test 7 | -------------------------------------------------------------------------------- /examples/ice40-up5k/switches/info: -------------------------------------------------------------------------------- 1 | Switches controlling RGB led -------------------------------------------------------------------------------- /examples/ice40-up5k/switches/switches.v: -------------------------------------------------------------------------------- 1 | // Example of using 3 switches for setting the color of the RGB led 2 | // Board: iCE40-UP5K 3 | module rgb_test ( 4 | input sw2, 5 | input sw1, 6 | input sw0, 7 | output led_blue, 8 | output led_green, 9 | output led_red 10 | ); 11 | 12 | 13 | assign led_red = sw2; 14 | assign led_green = sw1; 15 | assign led_blue = sw0; 16 | 17 | endmodule 18 | -------------------------------------------------------------------------------- /examples/ice40-up5k/switches/up5k.pcf: -------------------------------------------------------------------------------- 1 | 2 | set_io -nowarn led_blue 39 3 | set_io -nowarn led_green 40 4 | set_io -nowarn led_red 41 5 | set_io -nowarn clk 35 6 | set_io -nowarn sw3 23 7 | set_io -nowarn sw2 25 8 | set_io -nowarn sw1 34 9 | set_io -nowarn sw0 43 10 | 11 | 12 | 13 | 14 | 15 | -------------------------------------------------------------------------------- /examples/icebreaker/blinky/apio.ini: -------------------------------------------------------------------------------- 1 | ; Apio project configuration file. 2 | ; Type 'apio info apio.ini' for details. 3 | 4 | [env:default] 5 | board = icebreaker 6 | top-module = blink_test 7 | -------------------------------------------------------------------------------- /examples/icebreaker/blinky/blinky.v: -------------------------------------------------------------------------------- 1 | //------------------------------------------------------------------ 2 | //-- Blinking LED 3 | //-- The Green LED is blinking. The other LEDs are turned off 4 | //------------------------------------------------------------------ 5 | module blink_test ( 6 | input CLK, //-- 12 Mhz 7 | output LEDG_N, //-- Green led to blink 8 | output LEDR_N, 9 | output LED1, 10 | output LED2, 11 | output LED3, 12 | output LED4, 13 | output LED5 14 | ); 15 | 16 | reg [23:0] counter = 0; 17 | 18 | always @(posedge CLK) counter <= counter + 1; 19 | 20 | //-- Toggle the green LED 21 | assign LEDG_N = counter[23]; 22 | 23 | //-- Turn off the other LEDs 24 | assign LEDR_N = 1'b1; 25 | assign {LED5, LED4, LED3, LED2, LED1} = 5'b0; 26 | 27 | endmodule 28 | -------------------------------------------------------------------------------- /examples/icebreaker/blinky/icebreaker.pcf: -------------------------------------------------------------------------------- 1 | # 12 MHz clock 2 | set_io -nowarn CLK 35 3 | 4 | # RS232 5 | set_io -nowarn RX 6 6 | set_io -nowarn TX 9 7 | 8 | # LEDs and Button 9 | set_io -nowarn BTN_N 10 10 | set_io -nowarn LEDR_N 11 11 | set_io -nowarn LEDG_N 37 12 | 13 | # RGB LED Driver 14 | set_io -nowarn LED_RED_N 39 15 | set_io -nowarn LED_GRN_N 40 16 | set_io -nowarn LED_BLU_N 41 17 | 18 | # SPI Flash 19 | set_io -nowarn FLASH_SCK 15 20 | set_io -nowarn FLASH_SSB 16 21 | set_io -nowarn FLASH_IO0 14 22 | set_io -nowarn FLASH_IO1 17 23 | set_io -nowarn FLASH_IO2 12 24 | set_io -nowarn FLASH_IO3 13 25 | 26 | # PMOD 1A 27 | set_io -nowarn P1A1 4 28 | set_io -nowarn P1A2 2 29 | set_io -nowarn P1A3 47 30 | set_io -nowarn P1A4 45 31 | set_io -nowarn P1A7 3 32 | set_io -nowarn P1A8 48 33 | set_io -nowarn P1A9 46 34 | set_io -nowarn P1A10 44 35 | 36 | # PMOD 1B 37 | set_io -nowarn P1B1 43 38 | set_io -nowarn P1B2 38 39 | set_io -nowarn P1B3 34 40 | set_io -nowarn P1B4 31 41 | set_io -nowarn P1B7 42 42 | set_io -nowarn P1B8 36 43 | set_io -nowarn P1B9 32 44 | set_io -nowarn P1B10 28 45 | 46 | # PMOD 2 47 | set_io -nowarn P2_1 27 48 | set_io -nowarn P2_2 25 49 | set_io -nowarn P2_3 21 50 | set_io -nowarn P2_4 19 51 | set_io -nowarn P2_7 26 52 | set_io -nowarn P2_8 23 53 | set_io -nowarn P2_9 20 54 | set_io -nowarn P2_10 18 55 | 56 | # LEDs and Buttons (PMOD 2) 57 | set_io -nowarn LED1 26 58 | set_io -nowarn LED2 27 59 | set_io -nowarn LED3 25 60 | set_io -nowarn LED4 23 61 | set_io -nowarn LED5 21 62 | set_io -nowarn BTN1 20 63 | set_io -nowarn BTN2 19 64 | set_io -nowarn BTN3 18 65 | -------------------------------------------------------------------------------- /examples/icebreaker/blinky/info: -------------------------------------------------------------------------------- 1 | Blinking a led -------------------------------------------------------------------------------- /examples/icebreaker/buttons/apio.ini: -------------------------------------------------------------------------------- 1 | ; Apio project configuration file. 2 | ; Type 'apio info apio.ini' for details. 3 | 4 | [env:default] 5 | board = icebreaker 6 | top-module = rgb_test 7 | -------------------------------------------------------------------------------- /examples/icebreaker/buttons/buttons.v: -------------------------------------------------------------------------------- 1 | // Example of using 3 buttons for toggeling the LED 2 | // Board: iCE40-UP5K 3 | module rgb_test ( 4 | input BTN_N, 5 | input BTN1, 6 | input BTN2, 7 | input BTN3, 8 | output LEDR_N, 9 | output LEDG_N, 10 | output LED4, 11 | output LED1, 12 | output LED5 13 | ); 14 | 15 | assign {LEDR_N, LEDG_N} = {BTN_N, ~BTN_N}; 16 | assign {LED4, LED1, LED5} = {BTN1, BTN2, BTN3}; 17 | 18 | endmodule 19 | -------------------------------------------------------------------------------- /examples/icebreaker/buttons/icebreaker.pcf: -------------------------------------------------------------------------------- 1 | # 12 MHz clock 2 | set_io -nowarn CLK 35 3 | 4 | # RS232 5 | set_io -nowarn RX 6 6 | set_io -nowarn TX 9 7 | 8 | # LEDs and Button 9 | set_io -nowarn BTN_N 10 10 | set_io -nowarn LEDR_N 11 11 | set_io -nowarn LEDG_N 37 12 | 13 | # RGB LED Driver 14 | set_io -nowarn LED_RED_N 39 15 | set_io -nowarn LED_GRN_N 40 16 | set_io -nowarn LED_BLU_N 41 17 | 18 | # SPI Flash 19 | set_io -nowarn FLASH_SCK 15 20 | set_io -nowarn FLASH_SSB 16 21 | set_io -nowarn FLASH_IO0 14 22 | set_io -nowarn FLASH_IO1 17 23 | set_io -nowarn FLASH_IO2 12 24 | set_io -nowarn FLASH_IO3 13 25 | 26 | # PMOD 1A 27 | set_io -nowarn P1A1 4 28 | set_io -nowarn P1A2 2 29 | set_io -nowarn P1A3 47 30 | set_io -nowarn P1A4 45 31 | set_io -nowarn P1A7 3 32 | set_io -nowarn P1A8 48 33 | set_io -nowarn P1A9 46 34 | set_io -nowarn P1A10 44 35 | 36 | # PMOD 1B 37 | set_io -nowarn P1B1 43 38 | set_io -nowarn P1B2 38 39 | set_io -nowarn P1B3 34 40 | set_io -nowarn P1B4 31 41 | set_io -nowarn P1B7 42 42 | set_io -nowarn P1B8 36 43 | set_io -nowarn P1B9 32 44 | set_io -nowarn P1B10 28 45 | 46 | # PMOD 2 47 | set_io -nowarn P2_1 27 48 | set_io -nowarn P2_2 25 49 | set_io -nowarn P2_3 21 50 | set_io -nowarn P2_4 19 51 | set_io -nowarn P2_7 26 52 | set_io -nowarn P2_8 23 53 | set_io -nowarn P2_9 20 54 | set_io -nowarn P2_10 18 55 | 56 | # LEDs and Buttons (PMOD 2) 57 | set_io -nowarn LED1 26 58 | set_io -nowarn LED2 27 59 | set_io -nowarn LED3 25 60 | set_io -nowarn LED4 23 61 | set_io -nowarn LED5 21 62 | set_io -nowarn BTN1 20 63 | set_io -nowarn BTN2 19 64 | set_io -nowarn BTN3 18 65 | -------------------------------------------------------------------------------- /examples/icebreaker/buttons/info: -------------------------------------------------------------------------------- 1 | Controlling a led using the buttons -------------------------------------------------------------------------------- /examples/icebreaker/led-green/apio.ini: -------------------------------------------------------------------------------- 1 | ; Apio project configuration file. 2 | ; Type 'apio info apio.ini' for details. 3 | 4 | [env:default] 5 | board = icebreaker 6 | top-module = led_test 7 | -------------------------------------------------------------------------------- /examples/icebreaker/led-green/info: -------------------------------------------------------------------------------- 1 | Turning the green led on -------------------------------------------------------------------------------- /examples/icebreaker/led-green/led-green.v: -------------------------------------------------------------------------------- 1 | //-- Turn on the Green on board LED 2 | //-- Board: iCE40-UP5K 3 | module led_test ( 4 | output LEDG_N, 5 | output LEDR_N, 6 | output LED1, 7 | output LED2, 8 | output LED3, 9 | output LED4, 10 | output LED5 11 | ); 12 | 13 | //-- Turn on the green signal (inverse logic) 14 | //-- Turn off the red and blue signals (inverse logic) 15 | //-- On board leds are inverse logic, PMOD LEDs are positive logic. 16 | 17 | assign LEDR_N = 1; //-- RED off 18 | assign LEDG_N = 0; //-- GREEN ON 19 | assign LED1 = 0; //-- LED1 off 20 | assign LED2 = 0; //-- LED1 off 21 | assign LED3 = 0; //-- LED1 off 22 | assign LED4 = 0; //-- LED1 off 23 | assign LED5 = 0; //-- LED1 off 24 | 25 | endmodule 26 | -------------------------------------------------------------------------------- /examples/icefun/blinky/apio.ini: -------------------------------------------------------------------------------- 1 | 2 | [env:default] 3 | board = icefun 4 | top-module = Main 5 | -------------------------------------------------------------------------------- /examples/icefun/blinky/info: -------------------------------------------------------------------------------- 1 | Blinking LEDs. AI generated testbench. 2 | -------------------------------------------------------------------------------- /examples/icefun/blinky/main.v: -------------------------------------------------------------------------------- 1 | 2 | module Main #( 3 | parameter integer N = 3_000_000 4 | ) ( 5 | input CLK, // 12MHz clock 6 | output [7:0] ROWS, // LED rows 7 | output [3:0] COLS // LED columns 8 | ); 9 | 10 | reg [31:0] counter = 0; 11 | 12 | reg toggle = 0; 13 | 14 | // Rows and columns are active low. 15 | assign ROWS = {6'b111111, toggle, ~toggle}; 16 | assign COLS = 4'b1110; 17 | 18 | always @(posedge CLK) begin 19 | if (counter >= N - 1) begin 20 | counter <= 0; 21 | toggle <= !toggle; 22 | end else begin 23 | counter <= counter + 1; 24 | end 25 | end 26 | 27 | endmodule 28 | 29 | 30 | -------------------------------------------------------------------------------- /examples/icefun/blinky/main_tb.gtkw: -------------------------------------------------------------------------------- 1 | [*] 2 | [*] GTKWave Analyzer v3.4.0 (w)1999-2022 BSI 3 | [*] Fri Jun 6 00:45:21 2025 4 | [*] 5 | [dumpfile] "/Users/user/work/_build/default/main_tb.vcd" 6 | [dumpfile_mtime] "Fri Jun 6 00:43:27 2025" 7 | [dumpfile_size] 851 8 | [savefile] "/Users/user/work/main_tb.gtkw" 9 | [timestart] 0 10 | [size] 1320 747 11 | [pos] -1 -1 12 | *-4.268218 12 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 13 | [treeopen] test_Main. 14 | [sst_width] 253 15 | [signals_width] 136 16 | [sst_expanded] 1 17 | [sst_vpaned_height] 208 18 | @29 19 | test_Main.CLK 20 | @200 21 | - 22 | @24 23 | test_Main.dut.counter[31:0] 24 | @200 25 | - 26 | @28 27 | [color] 3 28 | test_Main.dut.ROWS[7:0] 29 | @200 30 | - 31 | @28 32 | test_Main.dut.COLS[3:0] 33 | @200 34 | - 35 | @28 36 | test_Main.tb_error 37 | [pattern_trace] 1 38 | [pattern_trace] 0 39 | -------------------------------------------------------------------------------- /examples/icefun/blinky/pinout.pcf: -------------------------------------------------------------------------------- 1 | # Pinout for iceFUN board example 2 | 3 | # LED rows 4 | set_io ROWS[0] C10 5 | set_io ROWS[1] A10 6 | set_io ROWS[2] D7 7 | set_io ROWS[3] D6 8 | set_io ROWS[4] A7 9 | set_io ROWS[5] C7 10 | set_io ROWS[6] A4 11 | set_io ROWS[7] C4 12 | 13 | # LED columns 14 | set_io COLS[0] A12 15 | set_io COLS[1] D10 16 | set_io COLS[2] A6 17 | set_io COLS[3] C5 18 | 19 | set_io CLK P7 20 | 21 | -------------------------------------------------------------------------------- /examples/icefun/led-matrix/apio.ini: -------------------------------------------------------------------------------- 1 | 2 | [env:default] 3 | board = icefun 4 | top-module = main 5 | default-testbench = main_tb.v 6 | -------------------------------------------------------------------------------- /examples/icefun/led-matrix/info: -------------------------------------------------------------------------------- 1 | LED matrix module. 2 | -------------------------------------------------------------------------------- /examples/icefun/led-matrix/led_matrix_tb.gtkw: -------------------------------------------------------------------------------- 1 | [*] 2 | [*] GTKWave Analyzer v3.4.0 (w)1999-2022 BSI 3 | [*] Sat Jun 7 16:24:41 2025 4 | [*] 5 | [dumpfile] "/Users/user/work/_build/default/led_matrix_tb.vcd" 6 | [dumpfile_mtime] "Sat Jun 7 16:22:05 2025" 7 | [dumpfile_size] 2418 8 | [savefile] "/Users/user/work/led_matrix_tb.gtkw" 9 | [timestart] 0 10 | [size] 1240 665 11 | [pos] -1 -1 12 | *-19.549362 383000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 13 | [treeopen] led_matrix_tb. 14 | [sst_width] 253 15 | [signals_width] 177 16 | [sst_expanded] 1 17 | [sst_vpaned_height] 181 18 | @28 19 | led_matrix_tb.clk 20 | @200 21 | - 22 | @24 23 | led_matrix_tb.led_matrix.timer[31:0] 24 | @28 25 | led_matrix_tb.led_matrix.col[1:0] 26 | led_matrix_tb.frame_tick 27 | @200 28 | - 29 | @22 30 | led_matrix_tb.data[31:0] 31 | led_matrix_tb.led_matrix.shifted_data[31:0] 32 | @200 33 | - 34 | @28 35 | [color] 3 36 | led_matrix_tb.cols[3:0] 37 | [color] 3 38 | led_matrix_tb.rows[7:0] 39 | @200 40 | - 41 | - 42 | -Inverted cols/rows 43 | @68 44 | led_matrix_tb.cols[3:0] 45 | @63 46 | led_matrix_tb.rows[7:0] 47 | [pattern_trace] 1 48 | [pattern_trace] 0 49 | -------------------------------------------------------------------------------- /examples/icefun/led-matrix/led_matrix_tb.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module led_matrix_tb; 4 | 5 | reg clk = 0; 6 | reg [31:0] data; 7 | wire [ 7:0] rows; 8 | wire [ 3:0] cols; 9 | wire frame_tick; 10 | 11 | // Instantiate the module under test 12 | led_matrix #( 13 | .N(5) 14 | ) led_matrix ( 15 | .clk(clk), 16 | .data(data), 17 | .intensity(15), 18 | .frame_tick(frame_tick), 19 | .rows(rows), 20 | .cols(cols) 21 | ); 22 | 23 | // Clock generation: 12MHz => 83.33ns period 24 | always #42 clk = ~clk; 25 | 26 | initial begin 27 | // Enable waveform dumping 28 | $dumpvars(0, led_matrix_tb); 29 | 30 | // Initialize input 31 | data = 32'h3F_9A_7C_21; // Example LED pattern 32 | 33 | // Run simulation for some time 34 | #4000; 35 | 36 | $display("End of simulation"); 37 | $finish; 38 | end 39 | 40 | endmodule 41 | -------------------------------------------------------------------------------- /examples/icefun/led-matrix/main.v: -------------------------------------------------------------------------------- 1 | 2 | module main #( 3 | parameter integer N1 = 5_000, // clks per col scan 4 | parameter integer N2 = 6_000_000, // clks per rnd update 5 | parameter integer INTENSITY = 0 // Leds intensity, 0-15 6 | ) ( 7 | input CLK, // 12MHz clock 8 | output [7:0] ROWS, // LED rows 9 | output [3:0] COLS // LED columns 10 | ); 11 | 12 | // Running rand value. 13 | wire [31:0] rnd; 14 | 15 | // Sampled rand to display 16 | reg [31:0] sampled_rnd = 0; 17 | 18 | // wire frame_tick; 19 | 20 | rand_gen rand_gen ( 21 | .clk(CLK), 22 | .rnd(rnd) 23 | ); 24 | 25 | led_matrix #( 26 | .N(N1) 27 | ) led_matrix ( 28 | .clk(CLK), 29 | .data(sampled_rnd), 30 | .intensity(INTENSITY[3:0]), 31 | .frame_tick(), 32 | .rows(ROWS), 33 | .cols(COLS) 34 | ); 35 | 36 | reg [31:0] timer = 0; 37 | 38 | 39 | always @(posedge CLK) begin 40 | // Increment timer mod N2. 41 | timer = (timer >= N2 - 1) ? 0 : timer + 1; 42 | if (timer == 0) begin 43 | // Get a new rand. 44 | sampled_rnd <= rnd; 45 | end 46 | end 47 | 48 | endmodule 49 | 50 | 51 | -------------------------------------------------------------------------------- /examples/icefun/led-matrix/main_tb.gtkw: -------------------------------------------------------------------------------- 1 | [*] 2 | [*] GTKWave Analyzer v3.4.0 (w)1999-2022 BSI 3 | [*] Sat Jun 7 16:47:44 2025 4 | [*] 5 | [dumpfile] "/Users/user/work/_build/default/main_tb.vcd" 6 | [dumpfile_mtime] "Sat Jun 7 16:46:02 2025" 7 | [dumpfile_size] 22370 8 | [savefile] "/Users/user/work/main_tb.gtkw" 9 | [timestart] 4293000 10 | [size] 1320 747 11 | [pos] -1 -1 12 | *-18.474415 5082000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 13 | [treeopen] main_tb. 14 | [treeopen] main_tb.main. 15 | [sst_width] 253 16 | [signals_width] 177 17 | [sst_expanded] 1 18 | [sst_vpaned_height] 208 19 | @28 20 | main_tb.clk 21 | @200 22 | - 23 | @22 24 | main_tb.main.rnd[31:0] 25 | @200 26 | - 27 | @22 28 | main_tb.main.sampled_rnd[31:0] 29 | @200 30 | - 31 | @28 32 | main_tb.main.led_matrix.frame_tick 33 | @200 34 | - 35 | @28 36 | main_tb.cols[3:0] 37 | main_tb.rows[7:0] 38 | @200 39 | - 40 | [pattern_trace] 1 41 | [pattern_trace] 0 42 | -------------------------------------------------------------------------------- /examples/icefun/led-matrix/main_tb.v: -------------------------------------------------------------------------------- 1 | 2 | 3 | `default_nettype none `timescale 1ns / 1ps 4 | 5 | module main_tb; 6 | 7 | reg clk = 0; 8 | wire [7:0] rows; 9 | wire [3:0] cols; 10 | 11 | // Instantiate the DUT (Device Under Test) 12 | main #( 13 | .N1(3), // Small value for fast sim 14 | .N2(40), // Small value for fast sim 15 | .INTENSITY(15) // Max intensity, no pwm 16 | ) main ( 17 | .CLK (clk), 18 | .ROWS(rows), 19 | .COLS(cols) 20 | ); 21 | 22 | // Clock generation: 12MHz → ~83ns period 23 | always #42 clk = ~clk; 24 | 25 | initial begin 26 | // Enable waveform capture 27 | $dumpvars(0, main_tb); 28 | 29 | $display("Starting simulation..."); 30 | 31 | // Run for a limited time 32 | repeat (150) begin 33 | @(posedge clk); 34 | // $display("ROWS = %b, COLS = %b", rows, cols); 35 | end 36 | 37 | $display("End of simulation"); 38 | $finish; 39 | end 40 | 41 | endmodule 42 | 43 | -------------------------------------------------------------------------------- /examples/icefun/led-matrix/pinout.pcf: -------------------------------------------------------------------------------- 1 | # Pinout for iceFUN board example 2 | 3 | # LED rows 4 | set_io ROWS[0] C10 5 | set_io ROWS[1] A10 6 | set_io ROWS[2] D7 7 | set_io ROWS[3] D6 8 | set_io ROWS[4] A7 9 | set_io ROWS[5] C7 10 | set_io ROWS[6] A4 11 | set_io ROWS[7] C4 12 | 13 | # LED columns 14 | set_io COLS[0] A12 15 | set_io COLS[1] D10 16 | set_io COLS[2] A6 17 | set_io COLS[3] C5 18 | 19 | set_io CLK P7 20 | 21 | -------------------------------------------------------------------------------- /examples/icefun/led-matrix/rand_gen.v: -------------------------------------------------------------------------------- 1 | module rand_gen ( 2 | input clk, 3 | output reg [31:0] rnd = ~0 4 | ); 5 | 6 | // The shifting feedback bit. 7 | wire feedback = rnd[31] ^ rnd[21] ^ rnd[1] ^ rnd[0]; 8 | 9 | // On startup rnd may be zero which will cause it 10 | // to stay forever in a zero loop. 11 | wire zero_loop = (rnd == 0); 12 | 13 | always @(posedge clk) begin 14 | if (zero_loop) begin 15 | rnd <= ~rnd; 16 | end else begin 17 | rnd <= {rnd[30:0], feedback}; 18 | end 19 | end 20 | 21 | endmodule 22 | -------------------------------------------------------------------------------- /examples/icefun/led-matrix/rand_gen_tb.gtkw: -------------------------------------------------------------------------------- 1 | [*] 2 | [*] GTKWave Analyzer v3.4.0 (w)1999-2022 BSI 3 | [*] Sat Jun 7 15:37:58 2025 4 | [*] 5 | [dumpfile] "/Users/user/work/_build/default/rand_gen_tb.vcd" 6 | [dumpfile_mtime] "Sat Jun 7 15:37:31 2025" 7 | [dumpfile_size] 10030 8 | [savefile] "/Users/user/work/rand_gen_tb.gtkw" 9 | [timestart] 0 10 | [size] 1376 786 11 | [pos] -1 -1 12 | *-17.793407 615000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 13 | [treeopen] rand_gen_tb. 14 | [sst_width] 253 15 | [signals_width] 219 16 | [sst_expanded] 1 17 | [sst_vpaned_height] 224 18 | @28 19 | rand_gen_tb.clk 20 | @200 21 | - 22 | @28 23 | rand_gen_tb.rang_gen.feedback 24 | @200 25 | - 26 | @29 27 | rand_gen_tb.rang_gen.zero_loop 28 | @200 29 | - 30 | @22 31 | [color] 3 32 | rand_gen_tb.rnd[31:0] 33 | [pattern_trace] 1 34 | [pattern_trace] 0 35 | -------------------------------------------------------------------------------- /examples/icefun/led-matrix/rand_gen_tb.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module rand_gen_tb; 4 | 5 | reg clk = 0; 6 | wire [31:0] rnd; 7 | 8 | // Instantiate the module under test 9 | rand_gen uut ( 10 | .clk(clk), 11 | .rnd(rnd) 12 | ); 13 | 14 | // Generate clock 15 | always #5 clk = ~clk; 16 | 17 | initial begin 18 | // Enable waveform dumping 19 | $dumpvars(0, rand_gen_tb); 20 | 21 | // Run for several cycles to observe randomness 22 | repeat (100) begin 23 | @(posedge clk); 24 | // $display("Random: 0x%08X", rnd); 25 | end 26 | 27 | $display("End of simulation"); 28 | $finish; 29 | end 30 | 31 | endmodule 32 | -------------------------------------------------------------------------------- /examples/icestick/leds/apio.ini: -------------------------------------------------------------------------------- 1 | ; Apio project configuration file. 2 | ; Type 'apio info apio.ini' for details. 3 | 4 | [env:default] 5 | board = icestick 6 | top-module = leds 7 | -------------------------------------------------------------------------------- /examples/icestick/leds/info: -------------------------------------------------------------------------------- 1 | Turning all the lds on -------------------------------------------------------------------------------- /examples/icestick/leds/leds.pcf: -------------------------------------------------------------------------------- 1 | # ----------------------------------------------------------------------------- 2 | #- Leds example for the iCEstick board 3 | #- Constraint file (.pcf) 4 | # ----------------------------------------------------------------------------- 5 | # -- Pinout: https://github.com/Obijuan/open-fpga-verilog-tutorial/blob/master/tutorial/doc/images/icestick_pinout.png 6 | # -- Guide: https://github.com/Obijuan/open-fpga-verilog-tutorial/blob/master/tutorial/doc/icestickusermanual.pdf 7 | 8 | # ------------ User Leds ------------------------------------------------------ 9 | set_io D1 99 10 | set_io D2 98 11 | set_io D3 97 12 | set_io D4 96 13 | set_io D5 95 14 | -------------------------------------------------------------------------------- /examples/icestick/leds/leds.v: -------------------------------------------------------------------------------- 1 | //------------------------------------------------------------------ 2 | //-- Hello world example for the iCEstick board 3 | //-- Turn on all the leds 4 | //------------------------------------------------------------------ 5 | 6 | module leds ( 7 | output wire D1, 8 | output wire D2, 9 | output wire D3, 10 | output wire D4, 11 | output wire D5 12 | ); 13 | 14 | assign D1 = 1'b1; 15 | assign D2 = 1'b1; 16 | assign D3 = 1'b1; 17 | assign D4 = 1'b1; 18 | assign D5 = 1'b1; 19 | 20 | endmodule 21 | -------------------------------------------------------------------------------- /examples/icestick/leds/leds_tb.gtkw: -------------------------------------------------------------------------------- 1 | [*] 2 | [*] GTKWave Analyzer v3.3.66 (w)1999-2015 BSI 3 | [*] Mon Aug 29 09:12:21 2016 4 | [*] 5 | [dumpfile] "/home/jesus/code/apio-examples/icestick-leds/leds_tb.vcd" 6 | [dumpfile_mtime] "Mon Aug 29 09:10:49 2016" 7 | [dumpfile_size] 606 8 | [savefile] "/home/jesus/code/apio-examples/icestick-leds/leds_tb.gtkw" 9 | [timestart] 0 10 | [size] 1000 600 11 | [pos] 507 137 12 | *0.000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 13 | [treeopen] leds_tb. 14 | [sst_width] 223 15 | [signals_width] 78 16 | [sst_expanded] 1 17 | [sst_vpaned_height] 160 18 | @28 19 | leds_tb.UUT.D1 20 | leds_tb.UUT.D2 21 | leds_tb.UUT.D3 22 | leds_tb.UUT.D4 23 | @29 24 | leds_tb.UUT.D5 25 | [pattern_trace] 1 26 | [pattern_trace] 0 27 | -------------------------------------------------------------------------------- /examples/icestick/leds/leds_tb.v: -------------------------------------------------------------------------------- 1 | //------------------------------------------------------------------- 2 | //-- leds_tb.v 3 | //-- Testbench 4 | //------------------------------------------------------------------- 5 | //-- Juan Gonzalez (Obijuan) 6 | //-- Jesus Arroyo Torrens 7 | //-- GPL license 8 | //------------------------------------------------------------------- 9 | `default_nettype none `timescale 100 ns / 10 ns 10 | 11 | module leds_tb (); 12 | 13 | //-- Simulation time: 1us (10 * 100ns) 14 | parameter DURATION = 10; 15 | 16 | //-- Clock signal. It is not used in this simulation 17 | reg clk = 0; 18 | always #0.5 clk = ~clk; 19 | 20 | //-- Leds port 21 | wire d1, d2, d3, d4, d5; 22 | 23 | //-- Instantiate the unit to test 24 | leds UUT ( 25 | .D1(d1), 26 | .D2(d2), 27 | .D3(d3), 28 | .D4(d4), 29 | .D5(d5) 30 | ); 31 | 32 | 33 | initial begin 34 | 35 | //-- Dump vars to the .vcd output file 36 | $dumpvars(0, leds_tb); 37 | 38 | #(DURATION) $display("End of simulation"); 39 | $finish; 40 | end 41 | 42 | endmodule 43 | -------------------------------------------------------------------------------- /examples/icestick/template/apio.ini: -------------------------------------------------------------------------------- 1 | ; Apio project configuration file. 2 | ; Type 'apio info apio.ini' for details. 3 | 4 | [env:default] 5 | board = icestick 6 | top-module = top 7 | -------------------------------------------------------------------------------- /examples/icestick/template/info: -------------------------------------------------------------------------------- 1 | Project template -------------------------------------------------------------------------------- /examples/icestick/template/main.v: -------------------------------------------------------------------------------- 1 | //------------------------------------------------------------------ 2 | //-- Verilog template 3 | //-- Top entity 4 | //-- Board: icestick 5 | //------------------------------------------------------------------ 6 | `default_nettype none 7 | 8 | //-- Template for the top entity 9 | module top ( 10 | output wire D1 11 | ); 12 | 13 | //-- Turn on the D1 (red led) on the icestick 14 | assign D1 = 1'b1; 15 | 16 | endmodule 17 | -------------------------------------------------------------------------------- /examples/icestick/template/main_tb.gtkw: -------------------------------------------------------------------------------- 1 | [*] 2 | [*] GTKWave Analyzer v3.4.0 (w)1999-2022 BSI 3 | [*] Wed Dec 18 19:02:05 2024 4 | [*] 5 | [dumpfile] "/Volumes/projects/apio-examples/repo/examples/icestick/template/_build/main_tb.vcd" 6 | [dumpfile_mtime] "Wed Dec 18 19:01:55 2024" 7 | [dumpfile_size] 594 8 | [savefile] "/Volumes/projects/apio-examples/repo/examples/icestick/template/main_tb.gtkw" 9 | [timestart] 0 10 | [size] 1000 600 11 | [pos] -1 -1 12 | *-18.251245 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 13 | [treeopen] main_tb. 14 | [sst_width] 253 15 | [signals_width] 78 16 | [sst_expanded] 1 17 | [sst_vpaned_height] 158 18 | @28 19 | main_tb.clk 20 | @29 21 | main_tb.l1 22 | [pattern_trace] 1 23 | [pattern_trace] 0 24 | -------------------------------------------------------------------------------- /examples/icestick/template/main_tb.v: -------------------------------------------------------------------------------- 1 | //------------------------------------------------------------------ 2 | //-- Verilog template 3 | //-- Test-bench entity 4 | //-- Board: icestick 5 | //------------------------------------------------------------------ 6 | 7 | `default_nettype none `timescale 100 ns / 10 ns 8 | 9 | module main_tb (); 10 | 11 | //-- Simulation time: 1us (10 * 100ns) 12 | parameter DURATION = 10; 13 | 14 | //-- Clock signal. It is not used in this simulation 15 | reg clk = 0; 16 | always #0.5 clk = ~clk; 17 | 18 | //-- Led port 19 | wire l1; 20 | 21 | //-- Instantiation of the unit to test 22 | top UUT (.D1(l1)); 23 | 24 | 25 | initial begin 26 | 27 | //-- Dump vars to the .vcd output file 28 | $dumpvars(0, main_tb); 29 | 30 | #(DURATION) $display("End of simulation"); 31 | $finish; 32 | end 33 | 34 | endmodule 35 | -------------------------------------------------------------------------------- /examples/icesugar-1-5/blinky/apio.ini: -------------------------------------------------------------------------------- 1 | ; Apio project configuration file. 2 | ; Type 'apio info apio.ini' for details. 3 | 4 | [env:default] 5 | board = icesugar-1-5 6 | top-module = blink_test 7 | -------------------------------------------------------------------------------- /examples/icesugar-1-5/blinky/blink.v: -------------------------------------------------------------------------------- 1 | 2 | module blink_test ( 3 | input CLK, 4 | output LED_G, 5 | output LED_R, 6 | output LED_B 7 | ); 8 | 9 | //-- Modify this value for changing the blink frequency 10 | localparam N = 24; //-- N<=21 Fast, N>=23 Slow 11 | 12 | reg [N:0] counter; 13 | always @(posedge CLK) counter <= counter + 1; 14 | 15 | assign LED_G = counter[N]; 16 | assign LED_R = counter[N-1]; 17 | assign LED_B = counter[N-2]; 18 | 19 | endmodule 20 | -------------------------------------------------------------------------------- /examples/icesugar-1-5/blinky/icesugar.pcf: -------------------------------------------------------------------------------- 1 | # For the iCESugar Board (iCE40UP5K-QFN48) 2 | 3 | set_io -nowarn LED_G 41 4 | set_io -nowarn LED_R 40 5 | set_io -nowarn LED_B 39 6 | 7 | set_io -nowarn SW[0] 18 8 | set_io -nowarn SW[1] 19 9 | set_io -nowarn SW[2] 20 10 | set_io -nowarn SW[3] 21 11 | 12 | set_io -nowarn CLK 35 13 | 14 | set_io -nowarn RX 4 15 | set_io -nowarn TX 6 16 | 17 | set_io -nowarn USB_DP 10 18 | set_io -nowarn USB_DN 9 19 | set_io -nowarn USB_PULLUP 11 20 | 21 | # PMOD 1 22 | set_io -nowarn P1_1 10 23 | set_io -nowarn P1_2 6 24 | set_io -nowarn P1_3 3 25 | set_io -nowarn P1_4 48 26 | set_io -nowarn P1_9 47 27 | set_io -nowarn P1_10 2 28 | set_io -nowarn P1_11 4 29 | set_io -nowarn P1_12 9 30 | 31 | # PMOD 2 32 | set_io -nowarn P2_1 46 33 | set_io -nowarn P2_2 44 34 | set_io -nowarn P2_3 42 35 | set_io -nowarn P2_4 37 36 | set_io -nowarn P2_9 36 37 | set_io -nowarn P2_10 38 38 | set_io -nowarn P2_11 43 39 | set_io -nowarn P2_12 45 40 | 41 | # PMOD 3 42 | set_io -nowarn P3_1 34 43 | set_io -nowarn P3_2 31 44 | set_io -nowarn P3_3 27 45 | set_io -nowarn P3_4 25 46 | set_io -nowarn P3_9 23 47 | set_io -nowarn P3_10 26 48 | set_io -nowarn P3_11 28 49 | set_io -nowarn P3_12 32 50 | 51 | # PMOD 4 52 | set_io -nowarn P4_1 21 53 | set_io -nowarn P4_2 20 54 | set_io -nowarn P4_3 19 55 | set_io -nowarn P4_4 18 56 | 57 | #spi 58 | set_io -nowarn SPI_SS 16 59 | set_io -nowarn SPI_SCK 15 60 | set_io -nowarn SPI_MOSI 17 61 | set_io -nowarn SPI_MISO 14 62 | -------------------------------------------------------------------------------- /examples/icesugar-1-5/blinky/info: -------------------------------------------------------------------------------- 1 | Blinking red/green/blue leds -------------------------------------------------------------------------------- /examples/icewerx/blinky/Blinky.v: -------------------------------------------------------------------------------- 1 | //------------------------------------------------------------------ 2 | //-- Blinking LED 3 | //------------------------------------------------------------------ 4 | 5 | module Test ( 6 | input CLK, // 12MHz clock 7 | output LEDG // LED to blink 8 | ); 9 | 10 | reg [23:0] counter = 0; 11 | 12 | always @(posedge CLK) counter <= counter + 1; 13 | 14 | assign LEDG = counter[23]; 15 | 16 | endmodule 17 | 18 | 19 | -------------------------------------------------------------------------------- /examples/icewerx/blinky/apio.ini: -------------------------------------------------------------------------------- 1 | ; Apio project configuration file. 2 | ; Type 'apio info apio.ini' for details. 3 | 4 | [env:default] 5 | board = icewerx 6 | top-module = Test 7 | -------------------------------------------------------------------------------- /examples/icewerx/blinky/info: -------------------------------------------------------------------------------- 1 | Blinking the Green LED 2 | -------------------------------------------------------------------------------- /examples/icewerx/blinky/pinout.pcf: -------------------------------------------------------------------------------- 1 | # ----------------------------------------------------------------------------- 2 | #- iceWerx constraint file (.pcf) 3 | #- By Juan Gonzalez (Obijuan) 4 | #- April - 2022 5 | #- GPL license 6 | # ----------------------------------------------------------------------------- 7 | 8 | 9 | # ------------ User Leds ------------------------------------------------------ 10 | #-- Red LED 11 | set_io -nowarn LEDR A5 # output 12 | 13 | #-- Green LED 14 | set_io -nowarn LEDG M4 # output 15 | 16 | #-- 12 Mhz clock 17 | set_io -nowarn CLK P7 # input 18 | -------------------------------------------------------------------------------- /examples/icewerx/ledon/apio.ini: -------------------------------------------------------------------------------- 1 | ; Apio project configuration file. 2 | ; Type 'apio info apio.ini' for details. 3 | 4 | [env:default] 5 | board = icewerx 6 | top-module = leds 7 | -------------------------------------------------------------------------------- /examples/icewerx/ledon/info: -------------------------------------------------------------------------------- 1 | Turning on the red led -------------------------------------------------------------------------------- /examples/icewerx/ledon/ledon.v: -------------------------------------------------------------------------------- 1 | //------------------------------------------------------------------ 2 | //-- Hello world example for the iceWerx board 3 | //-- Turn on the Red LED 4 | //------------------------------------------------------------------ 5 | module leds ( 6 | output wire LEDR 7 | ); 8 | 9 | //-- Red LED on 10 | //-- Inverse logic: 0: ON, 1: OFF 11 | assign LEDR = 1'b0; 12 | 13 | endmodule 14 | 15 | -------------------------------------------------------------------------------- /examples/icewerx/ledon/ledon_tb.gtkw: -------------------------------------------------------------------------------- 1 | [*] 2 | [*] GTKWave Analyzer v3.3.103 (w)1999-2019 BSI 3 | [*] Thu Apr 28 17:06:11 2022 4 | [*] 5 | [dumpfile] "/home/obijuan/Develop/FPGAwars/apio-examples/iceWerx/ledon/ledon_tb.vcd" 6 | [dumpfile_mtime] "Thu Apr 28 17:05:43 2022" 7 | [dumpfile_size] 266 8 | [savefile] "/home/obijuan/Develop/FPGAwars/apio-examples/iceWerx/ledon/ledon_tb.gtkw" 9 | [timestart] 0 10 | [size] 1000 600 11 | [pos] -1 -1 12 | *-18.262543 146000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 13 | [treeopen] ledon_tb. 14 | [sst_width] 233 15 | [signals_width] 78 16 | [sst_expanded] 1 17 | [sst_vpaned_height] 144 18 | @28 19 | ledon_tb.ledr 20 | [pattern_trace] 1 21 | [pattern_trace] 0 22 | -------------------------------------------------------------------------------- /examples/icewerx/ledon/ledon_tb.v: -------------------------------------------------------------------------------- 1 | //------------------------------------------------------------------- 2 | //-- ledon_tb.v 3 | //-- Testbench 4 | //------------------------------------------------------------------- 5 | //-- Juan Gonzalez (Obijuan) 6 | //-- GPL license 7 | //------------------------------------------------------------------- 8 | `default_nettype none `timescale 100 ns / 10 ns 9 | 10 | module ledon_tb (); 11 | 12 | //-- Simulation time: 1us (10 * 100ns) 13 | parameter DURATION = 10; 14 | 15 | //-- Red led 16 | wire ledr; 17 | 18 | //-- Instantiate the unit to test 19 | leds UUT (.LEDR(ledr)); 20 | 21 | 22 | initial begin 23 | 24 | //-- Dump vars to the .vcd output file 25 | $dumpvars(0, ledon_tb); 26 | 27 | #(DURATION) $display("End of simulation"); 28 | $finish; 29 | end 30 | 31 | endmodule 32 | -------------------------------------------------------------------------------- /examples/icewerx/ledon/pinout.pcf: -------------------------------------------------------------------------------- 1 | # ----------------------------------------------------------------------------- 2 | #- iceWerx constraint file (.pcf) 3 | #- By Juan Gonzalez (Obijuan) 4 | #- April - 2022 5 | #- GPL license 6 | # ----------------------------------------------------------------------------- 7 | 8 | 9 | # ------------ User Leds ------------------------------------------------------ 10 | #-- Red LED 11 | set_io --warn-no-port LEDR A5 # output 12 | -------------------------------------------------------------------------------- /examples/icezum/frere-jacques/README.md: -------------------------------------------------------------------------------- 1 | #Frère Jacques Two voices melody 2 | 3 | Melody created in Verilog following the tutorial example of Juan Gonzalez Gomez: 4 | 5 | https://github.com/Obijuan/open-fpga-verilog-tutorial/wiki/Cap%C3%ADtulo-19%3A-Secuenciando-notas 6 | 7 | If you have an IceZum Alhambra connect the first Buzzer to Pin 0 (119) and the second buzzer to Pin 1 (118) 8 | 9 | If you are going to use another board, remember to change the PCF file connections. 10 | 11 | ============= 12 | 13 | Licencia Creative Commons
Frère Jacques Two voices melody por Julián Caro Linares licensed by Creative Commons Attribution-ShareAlike 4.0 International License.

14 | 15 | Based on https://github.com/Obijuan/open-fpga-verilog-tutorial/wiki/Cap%C3%ADtulo-19%3A-Secuenciando-notas 16 | -------------------------------------------------------------------------------- /examples/icezum/frere-jacques/apio.ini: -------------------------------------------------------------------------------- 1 | ; Apio project configuration file. 2 | ; Type 'apio info apio.ini' for details. 3 | 4 | [env:default] 5 | board = icezum 6 | top-module = secnotas 7 | -------------------------------------------------------------------------------- /examples/icezum/frere-jacques/divider.v: -------------------------------------------------------------------------------- 1 | //----------------------------------------------------------------------------- 2 | //-- Divisor de frecuencia generico 3 | //-- (c) BQ. August 2015. written by Juan Gonzalez (obijuan) 4 | //----------------------------------------------------------------------------- 5 | //-- GPL license 6 | //----------------------------------------------------------------------------- 7 | 8 | `include "divider.vh" 9 | 10 | //-- Entrada: clk_in. Señal original 11 | //-- Salida: clk_out. Señal de frecuencia 1/M de la original 12 | module divider ( 13 | input wire clk_in, 14 | output wire clk_out 15 | ); 16 | 17 | //-- Valor por defecto del divisor 18 | //-- Lo ponemos a 1 Hz 19 | parameter M = `F_2KHz; 20 | 21 | //-- Numero de bits para almacenar el divisor 22 | //-- Se calculan con la funcion de verilog $clog2, que nos devuelve el 23 | //-- numero de bits necesarios para representar el numero M 24 | //-- Es un parametro local, que no se puede modificar al instanciar 25 | localparam N = $clog2(M); 26 | 27 | //-- Registro para implementar el contador modulo M 28 | reg [N-1:0] divcounter = 0; 29 | 30 | //-- Contador módulo M 31 | always @(posedge clk_in) divcounter <= (divcounter == M - 1) ? 0 : divcounter + 1; 32 | 33 | //-- Sacar el bit mas significativo por clk_out 34 | assign clk_out = divcounter[N-1]; 35 | 36 | endmodule 37 | 38 | //-- Contador módulo M: Otra manera de implementarlo 39 | /* 40 | always @(posedge clk_in) 41 | if (divcounter == M - 1) 42 | divcounter <= 0; 43 | else 44 | divcounter <= divcounter + 1; 45 | */ 46 | 47 | -------------------------------------------------------------------------------- /examples/icezum/frere-jacques/frerejacques.pcf: -------------------------------------------------------------------------------- 1 | set_io ch_out 119 2 | set_io ch_out2 118 3 | set_io clk 21 4 | -------------------------------------------------------------------------------- /examples/icezum/frere-jacques/frerejacques_tb.gtkw: -------------------------------------------------------------------------------- 1 | [*] 2 | [*] GTKWave Analyzer v3.3.66 (w)1999-2015 BSI 3 | [*] Mon Jan 2 17:35:18 2017 4 | [*] 5 | [dumpfile] "/home/jcarolinares/TFM/Arquitectura_robotica_de_control_hibrida_bionspirada_mediante_fpgas_libres/Miscelanea_y_comunidad/frere_jacques_two_voices_melody/frerejacques_tb.vcd" 6 | [dumpfile_mtime] "Mon Jan 2 17:34:11 2017" 7 | [dumpfile_size] 11373 8 | [savefile] "/home/jcarolinares/TFM/Arquitectura_robotica_de_control_hibrida_bionspirada_mediante_fpgas_libres/Miscelanea_y_comunidad/frere_jacques_two_voices_melody/frerejacques_tb.gtkw" 9 | [timestart] 0 10 | [size] 1366 744 11 | [pos] 217 83 12 | *-5.773307 31 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 13 | [treeopen] secnotas_tb. 14 | [sst_width] 225 15 | [signals_width] 117 16 | [sst_expanded] 1 17 | [sst_vpaned_height] 211 18 | @28 19 | secnotas_tb.clk 20 | secnotas_tb.dut.ch0 21 | secnotas_tb.dut.ch1 22 | secnotas_tb.dut.ch2 23 | secnotas_tb.ch_out 24 | secnotas_tb.dut.ch_out2 25 | @24 26 | secnotas_tb.dut.sel[5:0] 27 | secnotas_tb.dut.sel2[5:0] 28 | [pattern_trace] 1 29 | [pattern_trace] 0 30 | -------------------------------------------------------------------------------- /examples/icezum/frere-jacques/frerejacques_tb.v: -------------------------------------------------------------------------------- 1 | //------------------------------------------------------------------- 2 | //-- sectones_tb.v 3 | //-- Banco de pruebas para el secuenciador de 4 notas 4 | //------------------------------------------------------------------- 5 | //-- BQ August 2015. Written by Juan Gonzalez (Obijuan) 6 | //------------------------------------------------------------------- 7 | //-- GPL License 8 | //------------------------------------------------------------------- 9 | 10 | `define DUMP_FILE_NAME(x) `"x.vcd`" 11 | 12 | module secnotas_tb (); 13 | 14 | //-- Registro para generar la señal de reloj 15 | reg clk = 0; 16 | 17 | //-- Salidas de los canales 18 | wire ch_out; 19 | 20 | 21 | //-- Instanciar el componente y establecer el valor del divisor 22 | //-- Se pone un valor bajo para simular (de lo contrario tardaria mucho) 23 | secnotas #( 24 | .N0 (4), 25 | .N1 (3), 26 | .N2 (2), 27 | .DUR(10) 28 | ) dut ( 29 | .clk(clk), 30 | .ch_out(ch_out) 31 | ); 32 | 33 | //-- Generador de reloj. Periodo 2 unidades 34 | always #1 clk <= ~clk; 35 | 36 | 37 | //-- Proceso al inicio 38 | initial begin 39 | 40 | //-- Dump vars to the .vcd output file 41 | $dumpvars(0, secnotas_tb); 42 | 43 | #200 $display("FIN de la simulacion"); 44 | $finish; 45 | end 46 | 47 | endmodule 48 | 49 | -------------------------------------------------------------------------------- /examples/icezum/frere-jacques/info: -------------------------------------------------------------------------------- 1 | Frère Jacques two voices melody (see READMEmd) -------------------------------------------------------------------------------- /examples/icezum/leds/apio.ini: -------------------------------------------------------------------------------- 1 | ; Apio project configuration file. 2 | ; Type 'apio info apio.ini' for details. 3 | 4 | [env:default] 5 | board = icezum 6 | top-module = leds 7 | -------------------------------------------------------------------------------- /examples/icezum/leds/info: -------------------------------------------------------------------------------- 1 | Turning all the leds on -------------------------------------------------------------------------------- /examples/icezum/leds/leds.pcf: -------------------------------------------------------------------------------- 1 | # ----------------------------------------------------------------------------- 2 | #- Leds example for the Icezum board 3 | #- Constraint file (.pcf) 4 | # ----------------------------------------------------------------------------- 5 | # -- Repo: https://github.com/FPGAwars/icezum/wiki 6 | # -- Pinout: https://github.com/FPGAwars/icezum/blob/master/doc/pinout/icezum-pinout.pdf 7 | 8 | # ------------ User Leds ------------------------------------------------------ 9 | set_io LED0 95 10 | set_io LED1 96 11 | set_io LED2 97 12 | set_io LED3 98 13 | set_io LED4 99 14 | set_io LED5 101 15 | set_io LED6 102 16 | set_io LED7 104 17 | -------------------------------------------------------------------------------- /examples/icezum/leds/leds.v: -------------------------------------------------------------------------------- 1 | //------------------------------------------------------------------ 2 | //-- Hello world example for the iCEstick board 3 | //-- Turn on all the leds 4 | //------------------------------------------------------------------ 5 | 6 | module leds ( 7 | output wire LED0, 8 | output wire LED1, 9 | output wire LED2, 10 | output wire LED3, 11 | output wire LED4, 12 | output wire LED5, 13 | output wire LED6, 14 | output wire LED7 15 | ); 16 | 17 | assign LED0 = 1'b1; 18 | assign LED1 = 1'b1; 19 | assign LED2 = 1'b1; 20 | assign LED3 = 1'b1; 21 | assign LED4 = 1'b1; 22 | assign LED5 = 1'b1; 23 | assign LED6 = 1'b1; 24 | assign LED7 = 1'b1; 25 | 26 | endmodule 27 | -------------------------------------------------------------------------------- /examples/icezum/leds/leds_tb.gtkw: -------------------------------------------------------------------------------- 1 | [*] 2 | [*] GTKWave Analyzer v3.3.66 (w)1999-2015 BSI 3 | [*] Mon Aug 29 09:12:21 2016 4 | [*] 5 | [dumpfile] "/home/jesus/code/apio-examples/icestick-leds/leds_tb.vcd" 6 | [dumpfile_mtime] "Mon Aug 29 09:10:49 2016" 7 | [dumpfile_size] 606 8 | [savefile] "/home/jesus/code/apio-examples/icestick-leds/leds_tb.gtkw" 9 | [timestart] 0 10 | [size] 1000 600 11 | [pos] 507 137 12 | *0.000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 13 | [treeopen] leds_tb. 14 | [sst_width] 223 15 | [signals_width] 78 16 | [sst_expanded] 1 17 | [sst_vpaned_height] 160 18 | @28 19 | leds_tb.UUT.LED0 20 | leds_tb.UUT.LED1 21 | leds_tb.UUT.LED2 22 | leds_tb.UUT.LED3 23 | @29 24 | leds_tb.UUT.LED4 25 | leds_tb.UUT.LED5 26 | leds_tb.UUT.LED6 27 | leds_tb.UUT.LED7 28 | [pattern_trace] 1 29 | [pattern_trace] 0 30 | -------------------------------------------------------------------------------- /examples/icezum/leds/leds_tb.v: -------------------------------------------------------------------------------- 1 | //------------------------------------------------------------------- 2 | //-- leds_tb.v 3 | //-- Testbench 4 | //------------------------------------------------------------------- 5 | //-- Juan Gonzalez (Obijuan) 6 | //-- Jesus Arroyo Torrens 7 | //-- GPL license 8 | //------------------------------------------------------------------- 9 | `default_nettype none `timescale 100 ns / 10 ns 10 | 11 | module leds_tb (); 12 | 13 | //-- Simulation time: 1us (10 * 100ns) 14 | parameter DURATION = 10; 15 | 16 | //-- Clock signal. It is not used in this simulation 17 | reg clk = 0; 18 | always #0.5 clk = ~clk; 19 | 20 | //-- Leds port 21 | wire led0, led1, led2, led3, led4, led5, led6, led7; 22 | 23 | //-- Instantiate the unit to test 24 | leds UUT ( 25 | .LED0(led0), 26 | .LED1(led1), 27 | .LED2(led2), 28 | .LED3(led3), 29 | .LED4(led4), 30 | .LED5(led5), 31 | .LED6(led6), 32 | .LED7(led7) 33 | ); 34 | 35 | 36 | initial begin 37 | 38 | //-- Dump vars to the .vcd output file 39 | $dumpvars(0, leds_tb); 40 | 41 | #(DURATION) $display("End of simulation"); 42 | $finish; 43 | end 44 | 45 | endmodule 46 | -------------------------------------------------------------------------------- /examples/icezum/marcha-imperial/apio.ini: -------------------------------------------------------------------------------- 1 | ; Apio project configuration file. 2 | ; Type 'apio info apio.ini' for details. 3 | 4 | [env:default] 5 | board = icezum 6 | top-module = romnotes 7 | -------------------------------------------------------------------------------- /examples/icezum/marcha-imperial/dividerp1.v: -------------------------------------------------------------------------------- 1 | //----------------------------------------------------------------------------- 2 | //-- Divisor de reloj 3 | //-- Señal de periodo igual al indicado 4 | //-- El ancho del pulso positivo es de 1 ciclo de reloj 5 | //-- 6 | //-- (c) BQ. September 2015. written by Juan Gonzalez (obijuan) 7 | //----------------------------------------------------------------------------- 8 | //-- GPL license 9 | //----------------------------------------------------------------------------- 10 | `include "divider.vh" 11 | 12 | //-- ENTRADAS: 13 | //-- -clk: Senal de reloj del sistema (12 MHZ en la iceStick) 14 | // 15 | //-- SALIDAS: 16 | //-- - clk_out. Señal de salida para lograr la velocidad en baudios indicada 17 | //-- Anchura de 1 periodo de clk. SALIDA NO REGISTRADA 18 | module dividerp1 ( 19 | input wire clk, 20 | output wire clk_out 21 | ); 22 | 23 | //-- Valor por defecto de la velocidad en baudios 24 | parameter M = `T_100ms; 25 | 26 | //-- Numero de bits para almacenar el divisor de baudios 27 | localparam N = $clog2(M); 28 | 29 | //-- Registro para implementar el contador modulo M 30 | reg [N-1:0] divcounter = 0; 31 | 32 | //-- Contador módulo M 33 | always @(posedge clk) divcounter <= (divcounter == M - 1) ? 0 : divcounter + 1; 34 | 35 | //-- Sacar un pulso de anchura 1 ciclo de reloj si el generador 36 | assign clk_out = (divcounter == 0) ? 1 : 0; 37 | 38 | 39 | endmodule 40 | 41 | 42 | 43 | 44 | -------------------------------------------------------------------------------- /examples/icezum/marcha-imperial/genrom.v: -------------------------------------------------------------------------------- 1 | //---------------------------------------------------------------------------- 2 | //-- Memoria ROM genérica 3 | //------------------------------------------ 4 | //-- (C) BQ. October 2015. Written by Juan Gonzalez (Obijuan) 5 | //-- GPL license 6 | //---------------------------------------------------------------------------- 7 | //-- Memoria con los siguientes parametros: 8 | //-- * AW: Numero de bits de las direcciones 9 | //-- * DW: Numero de bits de los datos 10 | //-- * ROMFILE: Fichero a usar para cargar la memoria 11 | //-- 12 | //-- Con este componente podemos hacer memorias rom de cualquier tamaño 13 | //---------------------------------------------------------------------------- 14 | 15 | module genrom #( //-- Parametros 16 | //-- Parametro: Nombre del fichero con el contenido de la ROM 17 | parameter ROMFILE = "rom1.list", 18 | parameter AW = 5, //-- Bits de las direcciones (Adress width) 19 | parameter DW = 4 20 | ) //-- Bits de los datos (Data witdh) 21 | 22 | ( //-- Puertos 23 | input clk, //-- Señal de reloj global 24 | input wire [AW-1:0] addr, //-- Direcciones 25 | output reg [DW-1:0] data 26 | ); //-- Dato de salida 27 | 28 | //-- Calcular el numero de posiciones totales de memoria 29 | localparam NPOS = 2 ** AW; 30 | 31 | //-- Memoria 32 | reg [DW-1:0] rom[0:NPOS-1]; 33 | 34 | //-- Lectura de la memoria 35 | always @(posedge clk) begin 36 | data <= rom[addr]; 37 | end 38 | 39 | //-- Cargar en la memoria el fichero ROMFILE 40 | //-- Los valores deben estan dados en hexadecimal 41 | initial begin 42 | $readmemh(ROMFILE, rom); 43 | end 44 | 45 | 46 | endmodule 47 | 48 | 49 | 50 | -------------------------------------------------------------------------------- /examples/icezum/marcha-imperial/info: -------------------------------------------------------------------------------- 1 | Project template for the icezum board 2 | -------------------------------------------------------------------------------- /examples/icezum/marcha-imperial/rom1.list: -------------------------------------------------------------------------------- 1 | //-- Fichero rom1.list 2 | //-- Cada linea se corresponde con una posicion de memoria 3 | //-- Se pueden poner comentarios 4 | //-- ROM1: contiene los numeros del 0 al 31 (en hexadecimal) 5 | 0 //-- Posicion 0 6 | 1 //-- Posicion 1 7 | 2 8 | 3 9 | 4 10 | 5 11 | 6 12 | 7 13 | 8 14 | 9 15 | A 16 | B 17 | C 18 | D 19 | E 20 | F 21 | 10 22 | 11 23 | 12 24 | 13 25 | 14 26 | 15 27 | 16 28 | 17 29 | 18 30 | 19 31 | 1A 32 | 1B 33 | 1C 34 | 1D 35 | 1E 36 | 1F 37 | 38 | -------------------------------------------------------------------------------- /examples/icezum/marcha-imperial/romnotes.pcf: -------------------------------------------------------------------------------- 1 | set_io leds[0] 95 2 | set_io leds[1] 96 3 | set_io leds[2] 97 4 | set_io leds[3] 98 5 | set_io leds[4] 99 6 | set_io leds[5] 101 7 | set_io leds[6] 102 8 | set_io leds[7] 104 9 | set_io ch_out 78 10 | set_io clk 21 11 | 12 | 13 | 14 | 15 | 16 | -------------------------------------------------------------------------------- /examples/icezum/marcha-imperial/romnotes_tb.gtkw: -------------------------------------------------------------------------------- 1 | [*] 2 | [*] GTKWave Analyzer v3.3.64 (w)1999-2014 BSI 3 | [*] Wed Oct 21 07:01:09 2015 4 | [*] 5 | [dumpfile] "/home/obijuan/development/open-fpga-verilog-tutorial/tutorial/T27-rom-param/romnotes_tb.vcd" 6 | [dumpfile_mtime] "Wed Oct 21 07:00:07 2015" 7 | [dumpfile_size] 6508 8 | [savefile] "/home/obijuan/development/open-fpga-verilog-tutorial/tutorial/T27-rom-param/romnotes_tb.gtkw" 9 | [timestart] 28 10 | [size] 1018 316 11 | [pos] -856 -429 12 | *-4.421464 97 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 13 | [treeopen] romnotes_tb. 14 | [sst_width] 223 15 | [signals_width] 102 16 | [sst_expanded] 1 17 | [sst_vpaned_height] 60 18 | @29 19 | romnotes_tb.clk 20 | @28 21 | romnotes_tb.ch_out 22 | @22 23 | romnotes_tb.dut.leds[4:0] 24 | [pattern_trace] 1 25 | [pattern_trace] 0 26 | -------------------------------------------------------------------------------- /examples/icezum/marcha-imperial/romnotes_tb.v: -------------------------------------------------------------------------------- 1 | //------------------------------------------------------------------- 2 | //-- romnotes_tb.v 3 | //-- Banco de pruebas para el reproductor de melodias 4 | //------------------------------------------------------------------- 5 | //-- BQ October 2015. Written by Juan Gonzalez (Obijuan) 6 | //------------------------------------------------------------------- 7 | //-- GPL License 8 | //------------------------------------------------------------------- 9 | 10 | `define DUMP_FILE_NAME(x) `"x.vcd`" 11 | 12 | module romnotes_tb (); 13 | 14 | //-- Registro para generar la señal de reloj 15 | reg clk = 0; 16 | 17 | //-- Salidas de los canales 18 | wire ch_out; 19 | 20 | 21 | //-- Instanciar el componente y establecer el valor del divisor 22 | //-- Se pone un valor bajo para simular (de lo contrario tardaria mucho) 23 | romnotes #( 24 | .DUR(2) 25 | ) dut ( 26 | .clk(clk), 27 | .ch_out(ch_out) 28 | ); 29 | 30 | //-- Generador de reloj. Periodo 2 unidades 31 | always #1 clk <= ~clk; 32 | 33 | 34 | //-- Proceso al inicio 35 | initial begin 36 | 37 | //-- Dump vars to the .vcd output file 38 | $dumpvars(0, romnotes_tb); 39 | 40 | #200 $display("FIN de la simulacion"); 41 | $finish; 42 | end 43 | 44 | endmodule 45 | 46 | -------------------------------------------------------------------------------- /examples/icezum/template/apio.ini: -------------------------------------------------------------------------------- 1 | ; Apio project configuration file. 2 | ; Type 'apio info apio.ini' for details. 3 | 4 | [env:default] 5 | board = icezum 6 | top-module = top 7 | -------------------------------------------------------------------------------- /examples/icezum/template/info: -------------------------------------------------------------------------------- 1 | Project template -------------------------------------------------------------------------------- /examples/icezum/template/main.v: -------------------------------------------------------------------------------- 1 | //------------------------------------------------------------------ 2 | //-- Verilog template 3 | //-- Top entity 4 | //-- Board: icezum 5 | //------------------------------------------------------------------ 6 | `default_nettype none 7 | 8 | //-- Template for the top entity 9 | module top ( 10 | output wire LED0 11 | ); 12 | 13 | //-- Turn on the LED0 on the icezum 14 | assign LED0 = 1'b1; 15 | 16 | endmodule 17 | -------------------------------------------------------------------------------- /examples/icezum/template/main_tb.gtkw: -------------------------------------------------------------------------------- 1 | [*] 2 | [*] GTKWave Analyzer v3.4.0 (w)1999-2022 BSI 3 | [*] Wed Dec 18 19:02:38 2024 4 | [*] 5 | [dumpfile] "/Volumes/projects/apio-examples/repo/examples/icezum/template/_build/main_tb.vcd" 6 | [dumpfile_mtime] "Wed Dec 18 19:02:28 2024" 7 | [dumpfile_size] 596 8 | [savefile] "/Volumes/projects/apio-examples/repo/examples/icezum/template/main_tb.gtkw" 9 | [timestart] 0 10 | [size] 1000 600 11 | [pos] -1 -1 12 | *-18.251245 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 13 | [treeopen] main_tb. 14 | [sst_width] 253 15 | [signals_width] 78 16 | [sst_expanded] 1 17 | [sst_vpaned_height] 158 18 | @28 19 | main_tb.clk 20 | @29 21 | main_tb.l0 22 | [pattern_trace] 1 23 | [pattern_trace] 0 24 | -------------------------------------------------------------------------------- /examples/icezum/template/main_tb.v: -------------------------------------------------------------------------------- 1 | //------------------------------------------------------------------ 2 | //-- Verilog template 3 | //-- Test-bench entity 4 | //-- Board: icezum 5 | //------------------------------------------------------------------ 6 | 7 | `default_nettype none `timescale 100 ns / 10 ns 8 | 9 | module main_tb (); 10 | 11 | //-- Simulation time: 1us (10 * 100ns) 12 | parameter DURATION = 10; 13 | 14 | //-- Clock signal. It is not used in this simulation 15 | reg clk = 0; 16 | always #0.5 clk = ~clk; 17 | 18 | //-- Led port 19 | wire l0; 20 | 21 | //-- Instantiation of the unit to test 22 | top UUT (.LED0(l0)); 23 | 24 | 25 | initial begin 26 | 27 | //-- Dump vars to the .vcd output file 28 | $dumpvars(0, main_tb); 29 | 30 | #(DURATION) $display("End of simulation"); 31 | $finish; 32 | end 33 | 34 | endmodule 35 | -------------------------------------------------------------------------------- /examples/icezum/wire/apio.ini: -------------------------------------------------------------------------------- 1 | ; Apio project configuration file. 2 | ; Type 'apio info apio.ini' for details. 3 | 4 | [env:default] 5 | board = icezum 6 | top-module = simplewire 7 | -------------------------------------------------------------------------------- /examples/icezum/wire/info: -------------------------------------------------------------------------------- 1 | Describing a simple wire -------------------------------------------------------------------------------- /examples/icezum/wire/wire.pcf: -------------------------------------------------------------------------------- 1 | ## -- Constraints for the IceZUM Alhambra or compatible 2 | 3 | set_io in 144 #-- D13 on icezum Alhambra 4 | set_io out 95 #-- Led0 on icezum Alhambra 5 | -------------------------------------------------------------------------------- /examples/icezum/wire/wire.v: -------------------------------------------------------------------------------- 1 | //------------------------------------------------------------------ 2 | //-- A simple wire that connects the input with the output 3 | //-- In the icezum board this wire is for connecting the DIO 13 with 4 | //-- the led0 5 | //-- 6 | //-- This example has been tested on the following boards: 7 | //-- * Icezum alhambra (https://github.com/FPGAwars/icezum) 8 | //------------------------------------------------------------------ 9 | 10 | module simplewire ( 11 | input wire in, 12 | output wire out 13 | ); 14 | 15 | //-- Wire: Connect the input with the output 16 | assign out = in; 17 | 18 | endmodule 19 | -------------------------------------------------------------------------------- /examples/icezum/wire/wire_tb.gtkw: -------------------------------------------------------------------------------- 1 | [*] 2 | [*] GTKWave Analyzer v3.3.66 (w)1999-2015 BSI 3 | [*] Thu Apr 14 10:59:17 2016 4 | [*] 5 | [dumpfile] "/home/obijuan/development/apio/examples/wire/wire_tb.vcd" 6 | [dumpfile_mtime] "Thu Apr 14 10:59:08 2016" 7 | [dumpfile_size] 638 8 | [savefile] "/home/obijuan/development/apio/examples/wire/wire_tb.gtkw" 9 | [timestart] 0 10 | [size] 1022 600 11 | [pos] 0 65 12 | *-9.318040 380 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 13 | [sst_width] 223 14 | [signals_width] 134 15 | [sst_expanded] 1 16 | [sst_vpaned_height] 160 17 | @28 18 | wire_tb.in 19 | @29 20 | wire_tb.out 21 | [pattern_trace] 1 22 | [pattern_trace] 0 23 | -------------------------------------------------------------------------------- /examples/icezum/wire/wire_tb.v: -------------------------------------------------------------------------------- 1 | //------------------------------------------------------------------- 2 | //-- leds_on_tb.v 3 | //-- Testbench 4 | //------------------------------------------------------------------- 5 | //-- Juan Gonzalez (Obijuan). April-2016 6 | //-- Jesus Arroyo Torrens 7 | //-- GPL license 8 | //------------------------------------------------------------------- 9 | `default_nettype none `timescale 100 ns / 10 ns 10 | 11 | module wire_tb (); 12 | 13 | //-- Simulation time: 1us (10 * 100ns) 14 | parameter DURATION = 10; 15 | 16 | //-- Clock signal. It is not used in this simulation 17 | reg clk = 0; 18 | always #0.5 clk = ~clk; 19 | 20 | //-- wures 21 | reg in; 22 | wire out; 23 | 24 | //-- Instantiate the unit to test 25 | simplewire UUT ( 26 | .in (in), 27 | .out(out) 28 | ); 29 | 30 | 31 | initial begin 32 | 33 | //-- Dump vars to the .vcd output file 34 | $dumpvars(0, wire_tb); 35 | 36 | //-- Set the cable to 0 37 | in <= 0; 38 | 39 | //-- Set the cable to 1 40 | #10 in <= 1; 41 | 42 | #(DURATION) $display("End of simulation"); 43 | $finish; 44 | end 45 | 46 | endmodule 47 | -------------------------------------------------------------------------------- /examples/kefir/leds/apio.ini: -------------------------------------------------------------------------------- 1 | ; Apio project configuration file. 2 | ; Type 'apio info apio.ini' for details. 3 | 4 | [env:default] 5 | board = kefir 6 | top-module = leds 7 | -------------------------------------------------------------------------------- /examples/kefir/leds/info: -------------------------------------------------------------------------------- 1 | Turning all the leds on -------------------------------------------------------------------------------- /examples/kefir/leds/leds.pcf: -------------------------------------------------------------------------------- 1 | # ----------------------------------------------------------------------------- 2 | #- Leds example for the Kéfir I board 3 | #- Constraint file (.pcf) 4 | # ----------------------------------------------------------------------------- 5 | 6 | # ------------ User Leds ------------------------------------------------------ 7 | set_io D1 137 8 | set_io D2 135 9 | set_io D3 129 10 | set_io D4 121 11 | 12 | -------------------------------------------------------------------------------- /examples/kefir/leds/leds.v: -------------------------------------------------------------------------------- 1 | //------------------------------------------------------------------ 2 | //-- Hello world example for the Kéfir I board 3 | //-- Turn on all the leds 4 | //------------------------------------------------------------------ 5 | 6 | module leds ( 7 | output wire D1, 8 | output wire D2, 9 | output wire D3, 10 | output wire D4 11 | ); 12 | 13 | assign D1 = 1'b1; 14 | assign D2 = 1'b1; 15 | assign D3 = 1'b1; 16 | assign D4 = 1'b1; 17 | 18 | endmodule 19 | -------------------------------------------------------------------------------- /examples/kefir/leds/leds_tb.gtkw: -------------------------------------------------------------------------------- 1 | [*] 2 | [*] GTKWave Analyzer v3.3.66 (w)1999-2015 BSI 3 | [*] Mon Aug 29 09:12:21 2016 4 | [*] 5 | [dumpfile] "leds_tb.vcd" 6 | [dumpfile_mtime] "Mon Aug 29 09:10:49 2016" 7 | [dumpfile_size] 606 8 | [savefile] "leds_tb.gtkw" 9 | [timestart] 0 10 | [size] 1000 600 11 | [pos] 507 137 12 | *0.000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 13 | [treeopen] leds_tb. 14 | [sst_width] 223 15 | [signals_width] 78 16 | [sst_expanded] 1 17 | [sst_vpaned_height] 160 18 | @28 19 | leds_tb.UUT.D1 20 | leds_tb.UUT.D2 21 | leds_tb.UUT.D3 22 | leds_tb.UUT.D4 23 | [pattern_trace] 1 24 | [pattern_trace] 0 25 | -------------------------------------------------------------------------------- /examples/kefir/leds/leds_tb.v: -------------------------------------------------------------------------------- 1 | //------------------------------------------------------------------- 2 | //-- leds_tb.v 3 | //-- Testbench 4 | //------------------------------------------------------------------- 5 | //-- Juan Gonzalez (Obijuan) 6 | //-- Jesus Arroyo Torrens 7 | //-- GPL license 8 | //------------------------------------------------------------------- 9 | `default_nettype none `timescale 100 ns / 10 ns 10 | 11 | module leds_tb (); 12 | 13 | //-- Simulation time: 1us (10 * 100ns) 14 | parameter DURATION = 10; 15 | 16 | //-- Clock signal. It is not used in this simulation 17 | reg clk = 0; 18 | always #0.5 clk = ~clk; 19 | 20 | //-- Leds port 21 | wire d1, d2, d3, d4; 22 | 23 | //-- Instantiate the unit to test 24 | leds UUT ( 25 | .D1(d1), 26 | .D2(d2), 27 | .D3(d3), 28 | .D4(d4) 29 | ); 30 | 31 | 32 | initial begin 33 | 34 | //-- Dump vars to the .vcd output file 35 | $dumpvars(0, leds_tb); 36 | 37 | #(DURATION) $display("End of simulation"); 38 | $finish; 39 | end 40 | 41 | endmodule 42 | -------------------------------------------------------------------------------- /examples/kefir/template/apio.ini: -------------------------------------------------------------------------------- 1 | ; Apio project configuration file. 2 | ; Type 'apio info apio.ini' for details. 3 | 4 | [env:default] 5 | board = kefir 6 | top-module = top 7 | -------------------------------------------------------------------------------- /examples/kefir/template/info: -------------------------------------------------------------------------------- 1 | Project template -------------------------------------------------------------------------------- /examples/kefir/template/kefir.pcf: -------------------------------------------------------------------------------- 1 | ################################### 2 | # K�fir I HX4K Pin-pout 3 | # Family & Device: iCE40HX4K 4 | # Package: TQ144 5 | ################################### 6 | 7 | # Capacitive-sense buttons 8 | set_io -nowarn BTN1 136 9 | set_io -nowarn BTN2 134 10 | set_io -nowarn BTN3 128 11 | set_io -nowarn BTN4 122 12 | 13 | # LED outputs 14 | set_io -nowarn LED1 137 15 | set_io -nowarn LED2 135 16 | set_io -nowarn LED3 129 17 | set_io -nowarn LED4 121 18 | 19 | # Clock input 20 | set_io -nowarn CLK 49 21 | 22 | # SPI Flash enable control 23 | set_io -nowarn SS_B 71 24 | 25 | # MCP3008 A/D 26 | set_io -nowarn AD_CS 101 27 | set_io -nowarn AD_Din 102 28 | set_io -nowarn AD_Dout 104 29 | set_io -nowarn AD_Clk 105 30 | 31 | # USB 32 | set_io -nowarn USB_Vp_o 112 33 | set_io -nowarn USB_Vm_o 113 34 | set_io -nowarn USB_Vm_i 114 35 | set_io -nowarn USB_Vp_i 115 36 | set_io -nowarn USB_nOE 116 37 | 38 | set_io -nowarn ARDU00 138 39 | set_io -nowarn ARDU01 141 40 | set_io -nowarn ARDU02 143 41 | set_io -nowarn ARDU03 1 42 | 43 | # Arduino Power (P2) 44 | # Active low RESET 45 | #set_io -nowarn RESET_P2 73 -pullup yes 46 | set_io -nowarn RESET_P2 73 47 | 48 | # Milk channel A 49 | set_io -nowarn Milk_TXD 37 50 | set_io -nowarn Milk_RXD 38 51 | 52 | -------------------------------------------------------------------------------- /examples/kefir/template/main.v: -------------------------------------------------------------------------------- 1 | //------------------------------------------------------------------ 2 | //-- Verilog template 3 | //-- Top entity 4 | //-- Board: Kéfir I 5 | //------------------------------------------------------------------ 6 | `default_nettype none 7 | 8 | //-- Template for the top entity 9 | module top ( 10 | output wire LED1 11 | ); 12 | 13 | //-- Turn on the LED1 on the board 14 | assign LED1 = 1'b1; 15 | 16 | endmodule 17 | -------------------------------------------------------------------------------- /examples/kefir/template/main_tb.gtkw: -------------------------------------------------------------------------------- 1 | [*] 2 | [*] GTKWave Analyzer v3.4.0 (w)1999-2022 BSI 3 | [*] Wed Dec 18 19:03:54 2024 4 | [*] 5 | [dumpfile] "/Volumes/projects/apio-examples/repo/examples/kefir/template/_build/main_tb.vcd" 6 | [dumpfile_mtime] "Wed Dec 18 19:03:45 2024" 7 | [dumpfile_size] 596 8 | [savefile] "/Volumes/projects/apio-examples/repo/examples/kefir/template/main_tb.gtkw" 9 | [timestart] 0 10 | [size] 1000 600 11 | [pos] -1 -1 12 | *-18.251245 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 13 | [treeopen] main_tb. 14 | [sst_width] 253 15 | [signals_width] 78 16 | [sst_expanded] 1 17 | [sst_vpaned_height] 158 18 | @28 19 | main_tb.clk 20 | @29 21 | main_tb.l1 22 | [pattern_trace] 1 23 | [pattern_trace] 0 24 | -------------------------------------------------------------------------------- /examples/kefir/template/main_tb.v: -------------------------------------------------------------------------------- 1 | //------------------------------------------------------------------ 2 | //-- Verilog template 3 | //-- Test-bench entity 4 | //-- Board: icestick 5 | //------------------------------------------------------------------ 6 | 7 | `default_nettype none `timescale 100 ns / 10 ns 8 | 9 | module main_tb (); 10 | 11 | //-- Simulation time: 1us (10 * 100ns) 12 | parameter DURATION = 10; 13 | 14 | //-- Clock signal. It is not used in this simulation 15 | reg clk = 0; 16 | always #0.5 clk = ~clk; 17 | 18 | //-- Led port 19 | wire l1; 20 | 21 | //-- Instantiation of the unit to test 22 | top UUT (.LED1(l1)); 23 | 24 | 25 | initial begin 26 | 27 | //-- Dump vars to the .vcd output file 28 | $dumpvars(0, main_tb); 29 | 30 | #(DURATION) $display("End of simulation"); 31 | $finish; 32 | end 33 | 34 | endmodule 35 | -------------------------------------------------------------------------------- /examples/sipeed-tang-nano-4k/blinky/apio.ini: -------------------------------------------------------------------------------- 1 | ; Apio project configuration file. 2 | ; Type 'apio info apio.ini' for details. 3 | 4 | [env:default] 5 | board = sipeed-tang-nano-4k 6 | top-module = blinky 7 | 8 | -------------------------------------------------------------------------------- /examples/sipeed-tang-nano-4k/blinky/blinky.cst: -------------------------------------------------------------------------------- 1 | // Board details at 2 | // https://wiki.sipeed.com/hardware/en/tang/Tang-Nano-4K/examples/led.html 3 | 4 | IO_LOC "sys_clk" 45; 5 | IO_LOC "sys_reset" 15; // Active low 6 | IO_LOC "led" 10; // Active low 7 | -------------------------------------------------------------------------------- /examples/sipeed-tang-nano-4k/blinky/blinky.v: -------------------------------------------------------------------------------- 1 | module blinky #( 2 | // Num of click cycle per led toggle. 3 | parameter integer DIV = 13_499_999 4 | ) ( 5 | input sys_clk, 6 | input sys_reset, // Active low. 7 | output reg led // Active low 8 | ); 9 | 10 | reg [31:0] counter; 11 | 12 | always @(posedge sys_clk) begin 13 | if (!sys_reset) begin 14 | counter <= 0; 15 | led <= 1; 16 | end else if (counter < DIV) begin 17 | counter <= counter + 1; 18 | end else begin 19 | counter <= 0; 20 | led <= ~led; 21 | end 22 | end 23 | 24 | endmodule 25 | -------------------------------------------------------------------------------- /examples/sipeed-tang-nano-4k/blinky/blinky_tb.gtkw: -------------------------------------------------------------------------------- 1 | [*] 2 | [*] GTKWave Analyzer v3.4.0 (w)1999-2022 BSI 3 | [*] Sun Dec 29 03:04:31 2024 4 | [*] 5 | [dumpfile] "/Volumes/projects/apio-dev/repo/test-examples/sipeed-tang-nano-4k/demo/_build/blinky_tb.vcd" 6 | [dumpfile_mtime] "Sun Dec 29 03:03:42 2024" 7 | [dumpfile_size] 1604 8 | [savefile] "/Volumes/projects/apio-dev/repo/test-examples/sipeed-tang-nano-4k/demo/blinky_tb.gtkw" 9 | [timestart] 0 10 | [size] 1000 600 11 | [pos] -1 -1 12 | *-10.986121 620 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 13 | [treeopen] blinky_tb. 14 | [sst_width] 253 15 | [signals_width] 87 16 | [sst_expanded] 1 17 | [sst_vpaned_height] 158 18 | @420 19 | blinky_tb.clk_num 20 | @28 21 | blinky_tb.clk 22 | blinky_tb.reset 23 | @201 24 | - 25 | @28 26 | blinky_tb.led 27 | [pattern_trace] 1 28 | [pattern_trace] 0 29 | -------------------------------------------------------------------------------- /examples/sipeed-tang-nano-4k/blinky/blinky_tb.v: -------------------------------------------------------------------------------- 1 | // A testbench for testing the blinky module. 2 | 3 | `include "apio_testing.vh" 4 | 5 | `timescale 10 ns / 1 ns 6 | 7 | module blinky_tb (); 8 | 9 | // This defines a managed signal called 'clk'. 10 | `DEF_CLK 11 | 12 | // Inputs. 13 | reg reset = 0; 14 | 15 | // Outputs. 16 | wire led; 17 | 18 | // Instantiate a blinky that toggles the led every 5 clocks. 19 | blinky #( 20 | .DIV(5) 21 | ) ticker ( 22 | .sys_clk(clk), 23 | .sys_reset(reset), 24 | .led(led) 25 | ); 26 | 27 | initial begin 28 | `TEST_BEGIN(blinky_tb) 29 | 30 | // Reset for 2 clocks. 31 | `CLKS(2) 32 | reset = 1; 33 | 34 | // Free run for 30 clocks. 35 | `CLKS(30) 36 | 37 | `TEST_END 38 | end 39 | 40 | endmodule 41 | -------------------------------------------------------------------------------- /examples/sipeed-tang-nano-4k/blinky/info: -------------------------------------------------------------------------------- 1 | Blinking led (untested) -------------------------------------------------------------------------------- /examples/sipeed-tang-nano-9k/blinky-sv/apio.ini: -------------------------------------------------------------------------------- 1 | ; Apio project configuration file. 2 | ; Type 'apio info apio.ini' for details. 3 | 4 | [env:default] 5 | board = sipeed-tang-nano-9k 6 | top-module = blinky 7 | 8 | default-testbench = blinky_tb.sv 9 | 10 | -------------------------------------------------------------------------------- /examples/sipeed-tang-nano-9k/blinky-sv/blinky.cst: -------------------------------------------------------------------------------- 1 | // Board details at 2 | // https://wiki.sipeed.com/hardware/en/tang/Tang-Nano-9K/Nano-9K.html 3 | 4 | // See examples here https://github.com/sipeed/TangNano-9K-example/tree/main 5 | 6 | IO_LOC "sys_clk" 52; 7 | IO_PORT "sys_clk" IO_TYPE=LVCMOS33 PULL_MODE=NONE; 8 | 9 | IO_LOC "led" 10; // Active low 10 | 11 | -------------------------------------------------------------------------------- /examples/sipeed-tang-nano-9k/blinky-sv/blinky.sv: -------------------------------------------------------------------------------- 1 | module blinky #( 2 | // Num of click cycle per led toggle. 3 | parameter integer DIV = (27000000 / 2) 4 | ) ( 5 | input sys_clk, 6 | output logic led // Active low 7 | ); 8 | 9 | // ---- Reset generator. 10 | 11 | logic [3:0] reset_counter = 0; 12 | logic sys_reset = 1; 13 | 14 | always_ff @(posedge sys_clk) begin 15 | if (reset_counter < 3) begin 16 | sys_reset <= 1; 17 | reset_counter <= reset_counter + 1; 18 | end else begin 19 | sys_reset <= 0; 20 | end 21 | end 22 | 23 | // ---- Blinker 24 | 25 | reg [31:0] blink_counter; 26 | 27 | always_ff @(posedge sys_clk) begin 28 | if (sys_reset) begin 29 | blink_counter <= 0; 30 | led <= 1; 31 | end else if (blink_counter < (DIV - 1)) begin 32 | blink_counter <= blink_counter + 1; 33 | end else begin 34 | blink_counter <= 0; 35 | led <= ~led; 36 | end 37 | end 38 | 39 | endmodule 40 | -------------------------------------------------------------------------------- /examples/sipeed-tang-nano-9k/blinky-sv/blinky_tb.gtkw: -------------------------------------------------------------------------------- 1 | [*] 2 | [*] GTKWave Analyzer v3.4.0 (w)1999-2022 BSI 3 | [*] Fri Feb 7 22:09:03 2025 4 | [*] 5 | [dumpfile] "/Volumes/projects/apio-examples/repo/examples/sipeed-tang-nano-9k/blinky-sv/_build/blinky_tb.vcd" 6 | [dumpfile_mtime] "Fri Feb 7 22:07:34 2025" 7 | [dumpfile_size] 1897 8 | [savefile] "/Volumes/projects/apio-examples/repo/examples/sipeed-tang-nano-9k/blinky-sv/blinky_tb.gtkw" 9 | [timestart] 0 10 | [size] 1296 600 11 | [pos] -1 -1 12 | *-10.682656 550 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 13 | [treeopen] blinky_tb. 14 | [sst_width] 253 15 | [signals_width] 185 16 | [sst_expanded] 1 17 | [sst_vpaned_height] 158 18 | @420 19 | blinky_tb.clk_num 20 | @28 21 | blinky_tb.clk 22 | @200 23 | - 24 | -Reset Generator 25 | @22 26 | blinky_tb.blinky.reset_counter[3:0] 27 | @28 28 | blinky_tb.blinky.sys_reset 29 | @200 30 | - 31 | - 32 | -LED Blinker 33 | @23 34 | blinky_tb.blinky.blink_counter[31:0] 35 | @28 36 | [color] 3 37 | blinky_tb.led 38 | @200 39 | - 40 | [pattern_trace] 1 41 | [pattern_trace] 0 42 | -------------------------------------------------------------------------------- /examples/sipeed-tang-nano-9k/blinky-sv/blinky_tb.sv: -------------------------------------------------------------------------------- 1 | // A testbench for testing the blinky module. 2 | 3 | `default_nettype none 4 | `timescale 10 ns / 1 ns 5 | 6 | module blinky_tb (); 7 | 8 | // Defines clk, clk_num, and testing utilities. 9 | `include "apio_testing.svh" 10 | 11 | // Outputs. 12 | wire led; 13 | 14 | // Instantiate a blinky that toggles the led every 5 clocks. 15 | blinky #( 16 | .DIV(5) 17 | ) blinky ( 18 | .sys_clk(clk), 19 | .led(led) 20 | ); 21 | 22 | initial begin 23 | // Dump all signals of blinky_tb. 24 | $dumpvars(0, blinky_tb); 25 | 26 | // Go through the reset. 27 | clk1(); 28 | `CHECK_EQ(blinky.sys_reset, 1); 29 | clks(3); 30 | `CHECK_EQ(blinky.sys_reset, 0); 31 | 32 | // Free run for 30 clocks. 33 | clks(30); 34 | 35 | // All done. 36 | `CHECK_EQ(blinky.sys_reset, 0); 37 | $finish; 38 | end 39 | 40 | endmodule 41 | -------------------------------------------------------------------------------- /examples/sipeed-tang-nano-9k/blinky-sv/info: -------------------------------------------------------------------------------- 1 | Blinking led (system verilog) 2 | -------------------------------------------------------------------------------- /examples/sipeed-tang-nano-9k/blinky/apio.ini: -------------------------------------------------------------------------------- 1 | ; Apio project configuration file. 2 | ; Type 'apio info apio.ini' for details. 3 | 4 | [env:default] 5 | board = sipeed-tang-nano-9k 6 | top-module = blinky 7 | 8 | default-testbench = blinky_tb.v 9 | 10 | -------------------------------------------------------------------------------- /examples/sipeed-tang-nano-9k/blinky/blinky.cst: -------------------------------------------------------------------------------- 1 | // Board details at 2 | // https://wiki.sipeed.com/hardware/en/tang/Tang-Nano-9K/Nano-9K.html 3 | 4 | // See examples here https://github.com/sipeed/TangNano-9K-example/tree/main 5 | 6 | IO_LOC "sys_clk" 52; 7 | IO_PORT "sys_clk" IO_TYPE=LVCMOS33 PULL_MODE=NONE; 8 | 9 | IO_LOC "led" 10; // Active low 10 | 11 | -------------------------------------------------------------------------------- /examples/sipeed-tang-nano-9k/blinky/blinky.v: -------------------------------------------------------------------------------- 1 | module blinky #( 2 | // Num of click cycle per led toggle. 3 | parameter integer DIV = (27000000 / 2) 4 | ) ( 5 | input sys_clk, 6 | output reg led // Active low 7 | ); 8 | 9 | // ---- Reset generator. 10 | 11 | reg [3:0] reset_counter = 0; 12 | reg sys_reset = 1; 13 | 14 | always @(posedge sys_clk) begin 15 | if (reset_counter < 3) begin 16 | sys_reset <= 1; 17 | reset_counter <= reset_counter + 1; 18 | end else begin 19 | sys_reset <= 0; 20 | end 21 | end 22 | 23 | // ---- Blinker 24 | 25 | reg [31:0] blink_counter; 26 | 27 | always @(posedge sys_clk) begin 28 | if (sys_reset) begin 29 | blink_counter <= 0; 30 | led <= 1; 31 | end else if (blink_counter < (DIV - 1)) begin 32 | blink_counter <= blink_counter + 1; 33 | end else begin 34 | blink_counter <= 0; 35 | led <= ~led; 36 | end 37 | end 38 | 39 | endmodule 40 | -------------------------------------------------------------------------------- /examples/sipeed-tang-nano-9k/blinky/blinky_tb.gtkw: -------------------------------------------------------------------------------- 1 | [*] 2 | [*] GTKWave Analyzer v3.4.0 (w)1999-2022 BSI 3 | [*] Sun Jan 5 07:47:26 2025 4 | [*] 5 | [dumpfile] "/Volumes/projects/apio-examples/repo/examples/sipeed-tang-nano-9k/blinky/_build/blinky_tb.vcd" 6 | [dumpfile_mtime] "Sun Jan 5 07:45:31 2025" 7 | [dumpfile_size] 1557 8 | [savefile] "/Volumes/projects/apio-examples/repo/examples/sipeed-tang-nano-9k/blinky/blinky_tb.gtkw" 9 | [timestart] 0 10 | [size] 1296 600 11 | [pos] -1 -1 12 | *-10.521719 1900 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 13 | [treeopen] blinky_tb. 14 | [sst_width] 253 15 | [signals_width] 185 16 | [sst_expanded] 1 17 | [sst_vpaned_height] 158 18 | @420 19 | blinky_tb.clk_num 20 | @28 21 | blinky_tb.clk 22 | @200 23 | - 24 | -Reset Generator 25 | @22 26 | blinky_tb.ticker.reset_counter[3:0] 27 | @28 28 | blinky_tb.ticker.sys_reset 29 | @200 30 | - 31 | - 32 | -LED Blinker 33 | @22 34 | blinky_tb.ticker.blink_counter[31:0] 35 | @29 36 | [color] 3 37 | blinky_tb.led 38 | @200 39 | - 40 | [pattern_trace] 1 41 | [pattern_trace] 0 42 | -------------------------------------------------------------------------------- /examples/sipeed-tang-nano-9k/blinky/blinky_tb.v: -------------------------------------------------------------------------------- 1 | // A testbench for testing the blinky module. 2 | 3 | `include "apio_testing.vh" 4 | 5 | `timescale 10 ns / 1 ns 6 | 7 | module blinky_tb (); 8 | 9 | // This defines a managed signal called 'clk'. 10 | `DEF_CLK 11 | 12 | // Outputs. 13 | wire led; 14 | 15 | // Instantiate a blinky that toggles the led every 5 clocks. 16 | blinky #( 17 | .DIV(5) 18 | ) ticker ( 19 | .sys_clk(clk), 20 | .led(led) 21 | ); 22 | 23 | initial begin 24 | `TEST_BEGIN(blinky_tb) 25 | 26 | // Free run for 50 clocks. 27 | `CLKS(30) 28 | 29 | `TEST_END 30 | end 31 | 32 | endmodule 33 | -------------------------------------------------------------------------------- /examples/sipeed-tang-nano-9k/blinky/info: -------------------------------------------------------------------------------- 1 | Blinking led -------------------------------------------------------------------------------- /examples/sipeed-tang-nano-9k/pll/apio.ini: -------------------------------------------------------------------------------- 1 | ; Apio project configuration file. 2 | ; Type 'apio info apio.ini' for details. 3 | 4 | [env:default] 5 | board = sipeed-tang-nano-9k 6 | top-module = main 7 | 8 | default-testbench = blinker_tb.v 9 | 10 | -------------------------------------------------------------------------------- /examples/sipeed-tang-nano-9k/pll/blinker.v: -------------------------------------------------------------------------------- 1 | module blinker #( 2 | parameter integer DIV = (54000000 / 2) 3 | ) ( 4 | input clk, // 27 Mhz 5 | output led // Active low 6 | ); 7 | 8 | reg [31:0] blink_counter; 9 | reg led_reg = 0; 10 | 11 | assign led = led_reg; 12 | 13 | always @(posedge clk) begin 14 | if (blink_counter < (DIV - 1)) begin 15 | blink_counter <= blink_counter + 1; 16 | end else begin 17 | blink_counter <= 0; 18 | led_reg <= ~led_reg; 19 | end 20 | end 21 | 22 | endmodule 23 | -------------------------------------------------------------------------------- /examples/sipeed-tang-nano-9k/pll/blinker_tb.gtkw: -------------------------------------------------------------------------------- 1 | [*] 2 | [*] GTKWave Analyzer v3.4.0 (w)1999-2022 BSI 3 | [*] Fri Jan 10 18:07:58 2025 4 | [*] 5 | [dumpfile] "/Volumes/projects/apio-examples/repo/examples/sipeed-tang-nano-9k/pll/_build/blinker_tb.vcd" 6 | [dumpfile_mtime] "Fri Jan 10 18:07:19 2025" 7 | [dumpfile_size] 1459 8 | [savefile] "/Volumes/projects/apio-examples/repo/examples/sipeed-tang-nano-9k/pll/blinker_tb.gtkw" 9 | [timestart] 0 10 | [size] 1000 600 11 | [pos] -1 -1 12 | *-10.894506 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 13 | [treeopen] blinker_tb. 14 | [sst_width] 253 15 | [signals_width] 185 16 | [sst_expanded] 1 17 | [sst_vpaned_height] 158 18 | @28 19 | blinker_tb.clk 20 | @420 21 | blinker_tb.clk_num 22 | @200 23 | - 24 | @22 25 | blinker_tb.blinker.blink_counter[31:0] 26 | @29 27 | blinker_tb.led 28 | [pattern_trace] 1 29 | [pattern_trace] 0 30 | -------------------------------------------------------------------------------- /examples/sipeed-tang-nano-9k/pll/blinker_tb.v: -------------------------------------------------------------------------------- 1 | // A testbench for testing the blinky module. 2 | 3 | `include "apio_testing.vh" 4 | 5 | `timescale 10 ns / 1 ns 6 | 7 | module blinker_tb (); 8 | 9 | // This defines a managed signal called 'clk'. 10 | `DEF_CLK 11 | 12 | // Outputs. 13 | wire led; 14 | 15 | // Instantiate a blinker that toggles the led every 5 clocks. 16 | blinker #( 17 | .DIV(5) 18 | ) blinker ( 19 | .clk(clk), 20 | .led(led) 21 | ); 22 | 23 | initial begin 24 | `TEST_BEGIN(blinker_tb) 25 | 26 | // Free run for 50 clocks. 27 | `CLKS(30) 28 | 29 | `TEST_END 30 | end 31 | 32 | endmodule 33 | -------------------------------------------------------------------------------- /examples/sipeed-tang-nano-9k/pll/info: -------------------------------------------------------------------------------- 1 | PLL clock multiplier -------------------------------------------------------------------------------- /examples/sipeed-tang-nano-9k/pll/main.cst: -------------------------------------------------------------------------------- 1 | // Board details at 2 | // https://wiki.sipeed.com/hardware/en/tang/Tang-Nano-9K/Nano-9K.html 3 | 4 | // See examples here https://github.com/sipeed/TangNano-9K-example/tree/main 5 | 6 | IO_LOC "sys_clk" 52; 7 | IO_PORT "sys_clk" IO_TYPE=LVCMOS33 PULL_MODE=NONE; 8 | 9 | IO_LOC "led" 10; // Active low 10 | 11 | -------------------------------------------------------------------------------- /examples/sipeed-tang-nano-9k/pll/main.v: -------------------------------------------------------------------------------- 1 | module main ( 2 | input sys_clk, // 27 Mhz 3 | output reg led // Active low 4 | ); 5 | 6 | wire pll_clk; 7 | 8 | // Clock multiplier. 9 | pll pll ( 10 | .clk_in (sys_clk), // 27 Mhz 11 | .clk_out (pll_clk), // 54 Mhz 12 | .clk_lock() 13 | ); 14 | 15 | // The blinker. Runs on pll clock and prints once a second. 16 | localparam DIV = (54000000 / 2); 17 | 18 | reg [31:0] blink_counter; 19 | 20 | always @(posedge pll_clk) begin 21 | if (blink_counter < (DIV - 1)) begin 22 | blink_counter <= blink_counter + 1; 23 | end else begin 24 | blink_counter <= 0; 25 | led <= ~led; 26 | end 27 | end 28 | 29 | endmodule 30 | -------------------------------------------------------------------------------- /examples/sipeed-tang-nano-9k/pll/pll.v: -------------------------------------------------------------------------------- 1 | // PLL example. 2 | 3 | // See the Gowin PLL online calculator at: 4 | // at https://juj.github.io/gowin_fpga_code_generators/pll_calculator.html 5 | 6 | module pll ( 7 | input clk_in, 8 | output clk_out, // 27 MHz 9 | output clk_lock // 54 MHz 10 | ); 11 | 12 | rPLL #( // For GW1NR-9C C6/I5 (Tang Nano 9K proto dev board) 13 | .FCLKIN("27"), 14 | .IDIV_SEL(0), // -> PFD = 27 MHz (range: 3-400 MHz) 15 | .FBDIV_SEL(1), // -> CLKOUT = 54 MHz (range: 3.125-600 MHz) 16 | .ODIV_SEL(16) // -> VCO = 864 MHz (range: 400-1200 MHz) 17 | ) pll ( 18 | .CLKOUTP(), 19 | .CLKOUTD(), 20 | .CLKOUTD3(), 21 | .RESET(1'b0), 22 | .RESET_P(1'b0), 23 | .CLKFB(1'b0), 24 | .FBDSEL(6'b0), 25 | .IDSEL(6'b0), 26 | .ODSEL(6'b0), 27 | .PSDA(4'b0), 28 | .DUTYDA(4'b0), 29 | .FDLY(4'b0), 30 | .CLKIN(clk_in), // 27 MHz 31 | .CLKOUT(clk_out), // 54 MHz 32 | .LOCK(clk_lock) 33 | ); 34 | 35 | endmodule 36 | -------------------------------------------------------------------------------- /examples/tinyfpga-b2/blinky/Blink13.v: -------------------------------------------------------------------------------- 1 | //-- Hello world example for the TinyFPGA_B2 board 2 | //-- It just blinks the led conected to the pin13 3 | module TinyFPGA_B ( 4 | input pin3_clk_16mhz, 5 | output pin13 6 | ); 7 | 8 | //-- Modify this value for changing the blink frequency 9 | localparam N = 21; //-- N<=21 Fast, N>=23 Slow 10 | 11 | reg [N:0] counter; 12 | always @(posedge pin3_clk_16mhz) counter <= counter + 1; 13 | 14 | assign pin13 = counter[N]; 15 | 16 | endmodule 17 | -------------------------------------------------------------------------------- /examples/tinyfpga-b2/blinky/README.md: -------------------------------------------------------------------------------- 1 | Simple example for testing the TinyFPGA-B2 board 2 | It just blinks the led connected to pin 13 3 | 4 | ## Hardware setup 5 | 6 | ![](TinyFPGA-B2-setup.jpg) 7 | 8 | ## Instructions 9 | 10 | * Press the reset **button** on the **TinyFPGA-B2** board 11 | * Execute the following command: 12 | 13 | ```sh 14 | apio upload 15 | ``` 16 | This is a fragment of what will be written in the **console**: 17 | 18 | ``` 19 | Board: TinyFPGA-B2 20 | [Thu Jan 4 12:04:42 2018] Processing TinyFPGA-B2 21 | -------------------------------------------------------------------------------- 22 | FPGA_SIZE: 8k 23 | FPGA_TYPE: lp 24 | FPGA_PACK: cm81 25 | PROG: tinyfpgab -c /dev/ttyACM0 --program 26 | yosys -p "synth_ice40 -blif hardware.blif" -q Blink13.v 27 | arachne-pnr -d 8k -P cm81 -p TinyFPGA-B2-pins.pcf -o hardware.asc hardware.blif 28 | [...] 29 | icepack hardware.asc hardware.bin 30 | tinyfpgab -c /dev/ttyACM0 --program hardware.bin 31 | 32 | TinyFPGA B-series Programmer CLI 33 | -------------------------------- 34 | Using device id 1209:2100 35 | Programming /dev/ttyACM0 with hardware.bin 36 | Bootloader not active 37 | Programming at addr 030000 38 | Waking up SPI flash 39 | 135100 bytes to program 40 | Erasing designated flash pages 41 | Writing bitstream 42 | Verifying bitstream 43 | Success! 44 | ========================= [SUCCESS] Took 7.05 seconds ========================= 45 | ``` 46 | 47 | After 10 seconds or so, the led will **blink** 48 | -------------------------------------------------------------------------------- /examples/tinyfpga-b2/blinky/TinyFPGA-B2-pins.pcf: -------------------------------------------------------------------------------- 1 | ### left side of board 2 | set_io -nowarn pin1_usb_dp A3 3 | set_io -nowarn pin2_usb_dn A4 4 | set_io -nowarn pin3_clk_16mhz B4 5 | set_io -nowarn pin4 B2 6 | set_io -nowarn pin5 A2 7 | set_io -nowarn pin6 A1 8 | set_io -nowarn pin7 B1 9 | set_io -nowarn pin8 C1 10 | set_io -nowarn pin9 D1 11 | set_io -nowarn pin10 E1 12 | set_io -nowarn pin11 G1 13 | set_io -nowarn pin12 H1 14 | set_io -nowarn pin13 J1 15 | 16 | ### right side of board 17 | set_io -nowarn pin14_sdo G6 18 | set_io -nowarn pin15_sdi H7 19 | set_io -nowarn pin16_sck G7 20 | set_io -nowarn pin17_ss F7 21 | set_io -nowarn pin18 D9 22 | set_io -nowarn pin19 C9 23 | set_io -nowarn pin20 E8 24 | set_io -nowarn pin21 A9 25 | set_io -nowarn pin22 A8 26 | set_io -nowarn pin23 A7 27 | set_io -nowarn pin24 A6 28 | -------------------------------------------------------------------------------- /examples/tinyfpga-b2/blinky/TinyFPGA-B2-setup.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/FPGAwars/apio-examples/ec7da6db0ed17c9d22abc36a527b2a501e7cada0/examples/tinyfpga-b2/blinky/TinyFPGA-B2-setup.jpg -------------------------------------------------------------------------------- /examples/tinyfpga-b2/blinky/apio.ini: -------------------------------------------------------------------------------- 1 | ; Apio project configuration file. 2 | ; Type 'apio info apio.ini' for details. 3 | 4 | [env:default] 5 | board = tinyfpga-b2 6 | top-module = TinyFPGA_B 7 | -------------------------------------------------------------------------------- /examples/tinyfpga-b2/blinky/info: -------------------------------------------------------------------------------- 1 | Blinking a led -------------------------------------------------------------------------------- /examples/tinyfpga-b2/template/apio.ini: -------------------------------------------------------------------------------- 1 | ; Apio project configuration file. 2 | ; Type 'apio info apio.ini' for details. 3 | 4 | [env:default] 5 | board = tinyfpga-b2 6 | top-module = TinyFPGA_B 7 | -------------------------------------------------------------------------------- /examples/tinyfpga-b2/template/info: -------------------------------------------------------------------------------- 1 | Project template -------------------------------------------------------------------------------- /examples/tinyfpga-b2/template/pins.pcf: -------------------------------------------------------------------------------- 1 | ### left side of board 2 | set_io -nowarn pin1_usb_dp A3 3 | set_io -nowarn pin2_usb_dn A4 4 | set_io -nowarn pin3_clk_16mhz B4 5 | set_io -nowarn pin4 B2 6 | set_io -nowarn pin5 A2 7 | set_io -nowarn pin6 A1 8 | set_io -nowarn pin7 B1 9 | set_io -nowarn pin8 C1 10 | set_io -nowarn pin9 D1 11 | set_io -nowarn pin10 E1 12 | set_io -nowarn pin11 G1 13 | set_io -nowarn pin12 H1 14 | set_io -nowarn pin13 J1 15 | 16 | ### right side of board 17 | set_io -nowarn pin14_sdo G6 18 | set_io -nowarn pin15_sdi H7 19 | set_io -nowarn pin16_sck G7 20 | set_io -nowarn pin17_ss F7 21 | set_io -nowarn pin18 D9 22 | set_io -nowarn pin19 C9 23 | set_io -nowarn pin20 E8 24 | set_io -nowarn pin21 A9 25 | set_io -nowarn pin22 A8 26 | set_io -nowarn pin23 A7 27 | set_io -nowarn pin24 A6 28 | -------------------------------------------------------------------------------- /examples/tinyfpga-bx/blink-sos/BlinkSOS.v: -------------------------------------------------------------------------------- 1 | // look in pins.pcf for all the pin names on the TinyFPGA BX board 2 | module BlinkSOS ( 3 | input CLK, // 16MHz clock 4 | output LED, // User/boot LED next to power LED 5 | output USBPU // USB pull-up resistor 6 | ); 7 | // drive USB pull-up resistor to '0' to disable USB 8 | assign USBPU = 0; 9 | 10 | //////// 11 | // make a simple blink circuit 12 | //////// 13 | 14 | // keep track of time and location in blink_pattern 15 | reg [25:0] blink_counter; 16 | 17 | // pattern that will be flashed over the LED over time 18 | wire [31:0] blink_pattern = 32'b101010001110111011100010101; 19 | 20 | // increment the blink_counter every clock 21 | always @(posedge CLK) begin 22 | blink_counter <= blink_counter + 1; 23 | end 24 | 25 | // light up the LED according to the pattern 26 | assign LED = blink_pattern[blink_counter[25:21]]; 27 | endmodule 28 | -------------------------------------------------------------------------------- /examples/tinyfpga-bx/blink-sos/README.me: -------------------------------------------------------------------------------- 1 | Simple example for testing the TinyFPGA-BX board 2 | It just blinks the led connected to pin 13 3 | 4 | 5 | ## Instructions 6 | 7 | * Press the reset **button** on the **TinyFPGA-B2** board 8 | * Execute the following command: 9 | 10 | ```sh 11 | apio upload 12 | ``` 13 | This is a fragment of what will be written in the **console**: 14 | 15 | ``` 16 | Board: TinyFPGA-BX 17 | [Thu Jan 4 12:04:42 2018] Processing TinyFPGA-BX 18 | -------------------------------------------------------------------------------- 19 | FPGA_SIZE: 8k 20 | FPGA_TYPE: lp 21 | FPGA_PACK: cm81 22 | PROG: tinyfpgab -c /dev/ttyACM0 --program 23 | yosys -p "synth_ice40 -blif hardware.blif" -q BlinkSOS.v 24 | arachne-pnr -d 8k -P cm81 -p TinyFPGA-BX-pins.pcf -o hardware.asc hardware.blif 25 | [...] 26 | icepack hardware.asc hardware.bin 27 | tinyfpgab -c /dev/ttyACM0 --program hardware.bin 28 | 29 | TinyFPGA B-series Programmer CLI 30 | -------------------------------- 31 | Using device id 1d50:6130 32 | Programming /dev/ttyACM0 with hardware.bin 33 | Bootloader not active 34 | Programming at addr 030000 35 | Waking up SPI flash 36 | 135100 bytes to program 37 | Erasing designated flash pages 38 | Writing bitstream 39 | Verifying bitstream 40 | Success! 41 | ========================= [SUCCESS] Took 7.05 seconds ========================= 42 | ``` 43 | 44 | After 10 seconds or so, the led will **blink** 45 | -------------------------------------------------------------------------------- /examples/tinyfpga-bx/blink-sos/apio.ini: -------------------------------------------------------------------------------- 1 | ; Apio project configuration file. 2 | ; Type 'apio info apio.ini' for details. 3 | 4 | [env:default] 5 | board = tinyfpga-bx 6 | top-module = BlinkSOS 7 | -------------------------------------------------------------------------------- /examples/tinyfpga-bx/blink-sos/info: -------------------------------------------------------------------------------- 1 | Blink SOS pattern -------------------------------------------------------------------------------- /examples/tinyfpga-bx/blinky/Blinky.v: -------------------------------------------------------------------------------- 1 | //------------------------------------------------------------------ 2 | //-- Blinking LED 3 | //------------------------------------------------------------------ 4 | 5 | module Test ( 6 | input CLK, // 16MHz clock 7 | output LED, // User/boot LED next to power LED 8 | output USBPU // USB pull-up resistor 9 | ); 10 | 11 | // drive USB pull-up resistor to '0' to disable USB 12 | assign USBPU = 0; 13 | 14 | reg [24:0] counter = 0; 15 | 16 | always @(posedge CLK) counter <= counter + 1; 17 | 18 | assign LED = counter[24]; 19 | 20 | endmodule 21 | 22 | 23 | -------------------------------------------------------------------------------- /examples/tinyfpga-bx/blinky/apio.ini: -------------------------------------------------------------------------------- 1 | ; Apio project configuration file. 2 | ; Type 'apio info apio.ini' for details. 3 | 4 | [env:default] 5 | board = tinyfpga-bx 6 | top-module = Test 7 | -------------------------------------------------------------------------------- /examples/tinyfpga-bx/blinky/info: -------------------------------------------------------------------------------- 1 | Blinking led -------------------------------------------------------------------------------- /examples/tinyfpga-bx/clock-divider/apio.ini: -------------------------------------------------------------------------------- 1 | ; Apio project configuration file. 2 | ; Type 'apio info apio.ini' for details. 3 | 4 | [env:default] 5 | board = tinyfpga-bx 6 | top-module = top 7 | 8 | -------------------------------------------------------------------------------- /examples/tinyfpga-bx/clock-divider/clock_divider.v: -------------------------------------------------------------------------------- 1 | module clock_divider ( 2 | input clock_in, 3 | output reg clock_div4_0 = 0, 4 | output reg clock_div4_90 = 0 5 | ); 6 | 7 | reg clock_div2 = 0; 8 | 9 | always @(posedge clock_in) begin 10 | clock_div2 <= ~clock_div2; 11 | end 12 | 13 | always @(posedge clock_div2) begin 14 | clock_div4_0 <= ~clock_div4_0; 15 | end 16 | 17 | always @(negedge clock_div2) begin 18 | clock_div4_90 <= ~clock_div4_90; 19 | end 20 | 21 | endmodule 22 | -------------------------------------------------------------------------------- /examples/tinyfpga-bx/clock-divider/clock_divider_tb.gtkw: -------------------------------------------------------------------------------- 1 | [*] 2 | [*] GTKWave Analyzer v3.4.0 (w)1999-2022 BSI 3 | [*] Thu Dec 5 05:13:16 2024 4 | [*] 5 | [dumpfile] "/Volumes/projects/apio-examples/repo/examples/tinyfpga-bx/clock-divider/_build/clock_divider_tb.vcd" 6 | [dumpfile_mtime] "Thu Dec 5 05:11:25 2024" 7 | [dumpfile_size] 45675 8 | [savefile] "/Volumes/projects/apio-examples/repo/examples/tinyfpga-bx/clock-divider/clock_divider_tb.gtkw" 9 | [timestart] 0 10 | [size] 1000 600 11 | [pos] -1 -1 12 | *-15.388074 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 13 | [treeopen] clock_divider_tb. 14 | [sst_width] 253 15 | [signals_width] 136 16 | [sst_expanded] 1 17 | [sst_vpaned_height] 158 18 | @29 19 | [color] 2 20 | clock_divider_tb.cdiv.clock_in 21 | @28 22 | clock_divider_tb.cdiv.clock_div2 23 | clock_divider_tb.cdiv.clock_div4_0 24 | clock_divider_tb.cdiv.clock_div4_90 25 | [pattern_trace] 1 26 | [pattern_trace] 0 27 | -------------------------------------------------------------------------------- /examples/tinyfpga-bx/clock-divider/clock_divider_tb.v: -------------------------------------------------------------------------------- 1 | `timescale 1 ns / 100 ps 2 | `define DUMP_FILE_NAME(x) `"x.vcd`" 3 | 4 | 5 | module clock_divider_tb; 6 | 7 | wire clock_div4_0; 8 | wire clock_div4_90; 9 | 10 | reg clk = 0; 11 | 12 | clock_divider cdiv ( 13 | .clock_in(clk), 14 | .clock_div4_0(clock_div4_0), 15 | .clock_div4_90(clock_div4_90) 16 | ); 17 | 18 | initial begin 19 | //-- Dump vars to the .vcd output file 20 | $dumpvars(0, clock_divider_tb); 21 | #1000 $finish; 22 | end 23 | 24 | always begin 25 | clk = 1'b1; 26 | #2.5; 27 | 28 | clk = 1'b0; 29 | #2.5; 30 | end 31 | 32 | endmodule 33 | -------------------------------------------------------------------------------- /examples/tinyfpga-bx/clock-divider/info: -------------------------------------------------------------------------------- 1 | Clock divider with two phases outputs -------------------------------------------------------------------------------- /examples/tinyfpga-bx/clock-divider/top.v: -------------------------------------------------------------------------------- 1 | // look in pins.pcf for all the pin names on the TinyFPGA BX board 2 | module top ( 3 | input CLK, // 16MHz clock 4 | output LED, // User/boot LED next to power LED 5 | output USBPU 6 | ); 7 | 8 | wire clock_div4_0; 9 | wire clock_div4_90; 10 | 11 | // drive USB pull-up resistor to '0' to disable USB 12 | assign USBPU = 0; 13 | 14 | clock_divider cdiv ( 15 | .clock_in(CLK), 16 | .clock_div4_0(clock_div4_0), 17 | .clock_div4_90(clock_div4_90) 18 | ); 19 | 20 | 21 | // light up the LED according to the pattern 22 | assign LED = clock_div4_0; 23 | 24 | endmodule 25 | -------------------------------------------------------------------------------- /examples/tinyfpga-bx/template/TinyFPGA_BX.v: -------------------------------------------------------------------------------- 1 | /////////////////////////////////////////////////////////////////////////////// 2 | /////////////////////////////////////////////////////////////////////////////// 3 | /// 4 | /// Top-Level Verilog Module 5 | /// 6 | /// Only include pins the design is actually using. Make sure that the pin is 7 | /// given the correct direction: input vs. output vs. inout 8 | /// 9 | /////////////////////////////////////////////////////////////////////////////// 10 | /////////////////////////////////////////////////////////////////////////////// 11 | module TinyFPGA_B ( 12 | input CLK, // 16MHz clock 13 | output LED, // User/boot LED next to power LED 14 | output USBPU // USB pull-up resistor 15 | ); 16 | reg [23:0] counter; 17 | always @(posedge CLK) counter <= counter + 1; 18 | 19 | // drive USB pull-up resistor to '0' to disable USB 20 | assign USBPU = 0; 21 | 22 | assign LED = counter[23]; 23 | 24 | endmodule 25 | -------------------------------------------------------------------------------- /examples/tinyfpga-bx/template/apio.ini: -------------------------------------------------------------------------------- 1 | ; Apio project configuration file. 2 | ; Type 'apio info apio.ini' for details. 3 | 4 | [env:default] 5 | board = tinyfpga-bx 6 | top-module = TinyFPGA_B 7 | -------------------------------------------------------------------------------- /examples/tinyfpga-bx/template/info: -------------------------------------------------------------------------------- 1 | Project template -------------------------------------------------------------------------------- /examples/ulx3s-12f/blinky/apio.ini: -------------------------------------------------------------------------------- 1 | ; Apio project configuration file. 2 | ; Type 'apio info apio.ini' for details. 3 | 4 | [env:default] 5 | board = ulx3s-12f 6 | top-module = top 7 | -------------------------------------------------------------------------------- /examples/ulx3s-12f/blinky/blinky.v: -------------------------------------------------------------------------------- 1 | //------------------------------------------------------------------ 2 | //-- Blinking LED7 (Blue) 3 | //------------------------------------------------------------------ 4 | 5 | module top ( 6 | input clk_25mhz, //-- 25Mhz clock 7 | output [7:0] led, //-- LEDs 8 | output wifi_gpio0 9 | ); 10 | 11 | // Tie GPIO0, keep board from rebooting 12 | assign wifi_gpio0 = 1'b1; 13 | 14 | //-- Turn off all the LEDs except LED7 15 | assign led[6:0] = 7'b0; 16 | 17 | //-- 24 bits counter 18 | reg [23:0] counter = 0; 19 | 20 | always @(posedge clk_25mhz) counter <= counter + 1; 21 | 22 | //-- The most significant bit of the counter 23 | //-- is diplayed on LED7 (blue) 24 | assign led[7] = counter[23]; 25 | 26 | endmodule 27 | -------------------------------------------------------------------------------- /examples/ulx3s-12f/blinky/info: -------------------------------------------------------------------------------- 1 | Blinking a led -------------------------------------------------------------------------------- /examples/ulx3s-12f/ledon/apio.ini: -------------------------------------------------------------------------------- 1 | ; Apio project configuration file. 2 | ; Type 'apio info apio.ini' for details. 3 | 4 | [env:default] 5 | board = ulx3s-12f 6 | top-module = led_on 7 | -------------------------------------------------------------------------------- /examples/ulx3s-12f/ledon/info: -------------------------------------------------------------------------------- 1 | Turning on a led -------------------------------------------------------------------------------- /examples/ulx3s-12f/ledon/ledon.v: -------------------------------------------------------------------------------- 1 | //------------------------------------------------------------------ 2 | //-- Turn on one LED 3 | //------------------------------------------------------------------ 4 | module led_on ( 5 | output [7:0] led //-- LEDs 6 | ); 7 | 8 | //-- LED0 on 9 | assign led[0] = 1'b1; 10 | 11 | //-- The other LEDs are off 12 | assign led[7:1] = 7'b0; 13 | 14 | endmodule 15 | 16 | -------------------------------------------------------------------------------- /examples/ulx3s-12f/ledon/ledon_tb.gtkw: -------------------------------------------------------------------------------- 1 | [*] 2 | [*] GTKWave Analyzer v3.3.103 (w)1999-2019 BSI 3 | [*] Thu Apr 28 07:18:35 2022 4 | [*] 5 | [dumpfile] "/home/obijuan/Develop/FPGAwars/apio-examples/ulx3s-12f/ledon/ledon_tb.vcd" 6 | [dumpfile_mtime] "Thu Apr 28 07:14:34 2022" 7 | [dumpfile_size] 462 8 | [savefile] "/home/obijuan/Develop/FPGAwars/apio-examples/ulx3s-12f/ledon/ledon_tb.gtkw" 9 | [timestart] 0 10 | [size] 1920 1043 11 | [pos] -39 -39 12 | *-7.038382 49 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 13 | [treeopen] ledon_tb. 14 | [sst_width] 233 15 | [signals_width] 111 16 | [sst_expanded] 1 17 | [sst_vpaned_height] 298 18 | @28 19 | ledon_tb.led7 20 | ledon_tb.led6 21 | ledon_tb.led5 22 | ledon_tb.led4 23 | ledon_tb.led3 24 | ledon_tb.led2 25 | ledon_tb.led1 26 | @29 27 | ledon_tb.led0 28 | [pattern_trace] 1 29 | [pattern_trace] 0 30 | -------------------------------------------------------------------------------- /examples/ulx3s-12f/ledon/ledon_tb.v: -------------------------------------------------------------------------------- 1 | //------------------------------------------------------------------- 2 | //-- ledon_tb.v 3 | //-- Testbench 4 | //------------------------------------------------------------------- 5 | //-- Juan Gonzalez (Obijuan) 6 | //-- GPL license 7 | //------------------------------------------------------------------- 8 | `default_nettype none `timescale 100 ns / 10 ns 9 | 10 | module ledon_tb (); 11 | 12 | //-- Simulation time: 1us (10 * 100ns) 13 | parameter DURATION = 10; 14 | 15 | //-- Leds port 16 | wire led0, led1, led2, led3, led4, led5, led6, led7; 17 | 18 | //-- Instantiate the unit to test 19 | led_on UUT (.led({led7, led6, led5, led4, led3, led2, led1, led0})); 20 | 21 | 22 | initial begin 23 | 24 | //-- Dump vars to the .vcd output file 25 | $dumpvars(0, ledon_tb); 26 | 27 | #(DURATION) $display("End of simulation"); 28 | $finish; 29 | end 30 | 31 | endmodule 32 | -------------------------------------------------------------------------------- /examples/ulx3s-45f/blinky/apio.ini: -------------------------------------------------------------------------------- 1 | ; Apio project configuration file. 2 | ; Type 'apio info apio.ini' for details. 3 | 4 | [env:default] 5 | board = ulx3s-45f 6 | top-module = blinky 7 | -------------------------------------------------------------------------------- /examples/ulx3s-45f/blinky/blinky.v: -------------------------------------------------------------------------------- 1 | 2 | module blinky ( 3 | input clk_25mhz, 4 | input [6:0] btn, 5 | output [7:0] led, 6 | output wifi_gpio0 7 | ); 8 | 9 | localparam ctr_width = 32; 10 | 11 | wire i_clk; 12 | 13 | // Tie GPIO0, keep board from rebooting 14 | assign wifi_gpio0 = 1'b1; 15 | assign i_clk = clk_25mhz; 16 | reg [7:0] o_led; 17 | assign led = o_led; 18 | 19 | reg [ctr_width-1:0] ctr = 0; 20 | 21 | always @(posedge i_clk) begin 22 | ctr <= ctr + 1; 23 | o_led[7] <= 1; 24 | o_led[6] <= btn[1]; 25 | o_led[5:0] <= ctr[23:18]; 26 | end 27 | 28 | endmodule 29 | -------------------------------------------------------------------------------- /examples/ulx3s-45f/blinky/info: -------------------------------------------------------------------------------- 1 | Blinking leds -------------------------------------------------------------------------------- /examples/ulx3s-85f/blinky/apio.ini: -------------------------------------------------------------------------------- 1 | ; Apio project configuration file. 2 | ; Type 'apio info apio.ini' for details. 3 | 4 | [env:default] 5 | board = ulx3s-85f 6 | top-module = blinky 7 | -------------------------------------------------------------------------------- /examples/ulx3s-85f/blinky/blinky.v: -------------------------------------------------------------------------------- 1 | 2 | module blinky ( 3 | input clk_25mhz, 4 | input [6:0] btn, 5 | output [7:0] led, 6 | output wifi_gpio0 7 | ); 8 | 9 | localparam ctr_width = 32; 10 | 11 | wire i_clk; 12 | 13 | // Tie GPIO0, keep board from rebooting 14 | assign wifi_gpio0 = 1'b1; 15 | assign i_clk = clk_25mhz; 16 | reg [7:0] o_led; 17 | assign led = o_led; 18 | 19 | reg [ctr_width-1:0] ctr = 0; 20 | 21 | always @(posedge i_clk) begin 22 | ctr <= ctr + 1; 23 | o_led[7] <= 1; 24 | o_led[6] <= btn[1]; 25 | o_led[5:0] <= ctr[23:18]; 26 | end 27 | 28 | endmodule 29 | -------------------------------------------------------------------------------- /examples/ulx3s-85f/blinky/info: -------------------------------------------------------------------------------- 1 | Blinking leds -------------------------------------------------------------------------------- /examples/upduino31/blinky/apio.ini: -------------------------------------------------------------------------------- 1 | ; Apio project configuration file. 2 | ; Type 'apio info apio.ini' for details. 3 | 4 | [env:default] 5 | board = upduino31 6 | top-module = main 7 | -------------------------------------------------------------------------------- /examples/upduino31/blinky/info: -------------------------------------------------------------------------------- 1 | Using the SB_RGBA_DRV primitive led driver -------------------------------------------------------------------------------- /examples/upduino31/blinky/main.pcf: -------------------------------------------------------------------------------- 1 | # Mapping of the design signals to FPGA pins. 2 | 3 | # The full Upduino3 PCF file is availble at: 4 | # https://github.com/tinyvision-ai-inc/UPduino-v3.0/tree/master/RTL/common 5 | 6 | set_io leds_out[0] 41 # Red. 7 | set_io leds_out[1] 39 # Green. 8 | set_io leds_out[2] 40 # Blue. -------------------------------------------------------------------------------- /examples/upduino31/blinky/main.v: -------------------------------------------------------------------------------- 1 | // Generates a RGB blinking pattern. Uses the internal oscilator. 2 | module main ( 3 | // [0]=red, [1]=green, [2]=blue. See pin definitions in main.pcf 4 | output [2:0] leds_out 5 | ); 6 | 7 | wire clk; 8 | 9 | oscilator oscilator (.clk(clk)); 10 | 11 | // Frequency divider to generate the RGB patterns. 12 | reg [25:0] divider; 13 | wire red_en = divider[25] & divider[24]; 14 | wire green_en = divider[25] & ~divider[24]; 15 | wire blue_en = ~divider[25] & divider[24]; 16 | 17 | leds leds ( 18 | .clk(clk), 19 | .red_en(red_en), 20 | .green_en(green_en), 21 | .blue_en(blue_en), 22 | .leds_out(leds_out) 23 | ); 24 | 25 | // Behavior. 26 | always @(posedge clk) begin 27 | divider <= divider + 1'b1; 28 | end 29 | 30 | endmodule 31 | -------------------------------------------------------------------------------- /examples/upduino31/blinky/oscilator.v: -------------------------------------------------------------------------------- 1 | // Instanciates the internal high speed oscilator. This is needed 2 | // only if the external Upduino oscilator is not connected to the FPGA. 3 | 4 | module oscilator ( 5 | output clk 6 | ); 7 | 8 | SB_HFOSC interal_osc ( 9 | .CLKHFPU(1'b1), 10 | .CLKHFEN(1'b1), 11 | .CLKHF (clk), 12 | 13 | // Unused 14 | .TRIM0(), 15 | .TRIM1(), 16 | .TRIM2(), 17 | .TRIM3(), 18 | .TRIM4(), 19 | .TRIM5(), 20 | .TRIM6(), 21 | .TRIM7(), 22 | .TRIM8(), 23 | .TRIM9() 24 | ); 25 | 26 | endmodule 27 | -------------------------------------------------------------------------------- /examples/upduino31/pll/.gitignore: -------------------------------------------------------------------------------- 1 | .sconsign.dblite 2 | *.vcd 3 | *.out 4 | hardware.rpt 5 | hardware.json 6 | hardware.asc 7 | hardware.bin 8 | hardware.out 9 | -------------------------------------------------------------------------------- /examples/upduino31/pll/apio.ini: -------------------------------------------------------------------------------- 1 | ; Apio project configuration file. 2 | ; Type 'apio info apio.ini' for details. 3 | 4 | [env:default] 5 | board = upduino31 6 | top-module = main 7 | -------------------------------------------------------------------------------- /examples/upduino31/pll/info: -------------------------------------------------------------------------------- 1 | Generating 30Mhz clock using a pll -------------------------------------------------------------------------------- /examples/upduino31/pll/main.pcf: -------------------------------------------------------------------------------- 1 | # Mapping of the design signals to FPGA pins. 2 | 3 | # The full Upduino3 PCF file is availble at: 4 | # https://github.com/tinyvision-ai-inc/UPduino-v3.0/tree/master/RTL/common 5 | 6 | set_io leds_out[0] 41 # Red. 7 | set_io leds_out[1] 39 # Green. 8 | set_io leds_out[2] 40 # Blue. 9 | 10 | # External 12Mhz clock. Make sure to short the OSC solder jumper. 11 | set_io ext_clk 20 # 12Mhz in 12 | 13 | set_io pll_clk 26 # 30Mhz out 14 | set_io pll_locked 27 15 | 16 | -------------------------------------------------------------------------------- /examples/upduino31/pll/main.v: -------------------------------------------------------------------------------- 1 | // This exapmple demonstrates the use of the PLL to generate 30Mhz clock 2 | // from the external 12Mhz clock. Make sure to short the OSC jumper 3 | // to connect the external clock to the FPGA. 4 | // 5 | // Expected results: 6 | // * 30Mhz output at pin 26 (pll_clk) 7 | // * Green led blinks at 1Hz. 8 | 9 | // IMPORTANT: This example requires to short the OSC solder jumper 10 | // to feed the external 12Mhz clock to the FPGA. 11 | 12 | module main ( 13 | input ext_clk, // 12Mhz in 14 | output pll_clk, // 30Mhz out 15 | output pll_locked, 16 | output [2:0] leds_out 17 | ); 18 | 19 | reg [24:0] counter; 20 | reg led_on; 21 | 22 | // Generate the 1Hz blink 23 | always @(posedge pll_clk) begin 24 | if (counter >= 30000000 - 1) counter <= 0; 25 | else counter <= counter + 1; 26 | led_on <= counter <= 10000000; 27 | end 28 | 29 | pll pll ( 30 | .clock_in(ext_clk), 31 | .clock_out(pll_clk), 32 | .locked(pll_locked) 33 | ); 34 | 35 | leds leds ( 36 | .clk(pll_clk), 37 | .red_en(1'b0), 38 | .green_en(led_on), 39 | .blue_en(1'b0), 40 | .leds_out(leds_out) 41 | ); 42 | 43 | endmodule 44 | 45 | -------------------------------------------------------------------------------- /examples/upduino31/pll/pll.v: -------------------------------------------------------------------------------- 1 | // MOTE: This file was generated with the command: 2 | // icepll -m -i 12 -o 30 3 | 4 | /** 5 | * PLL configuration 6 | * 7 | * This Verilog module was generated automatically 8 | * using the icepll tool from the IceStorm project. 9 | * Use at your own risk. 10 | * 11 | * Given input frequency: 12.000 MHz 12 | * Requested output frequency: 30.000 MHz 13 | * Achieved output frequency: 30.000 MHz 14 | */ 15 | 16 | module pll ( 17 | input clock_in, 18 | output clock_out, 19 | output locked 20 | ); 21 | 22 | SB_PLL40_CORE #( 23 | .FEEDBACK_PATH("SIMPLE"), 24 | .DIVR(4'b0000), // DIVR = 0 25 | .DIVF(7'b1001111), // DIVF = 79 26 | .DIVQ(3'b101), // DIVQ = 5 27 | .FILTER_RANGE(3'b001) // FILTER_RANGE = 1 28 | ) pll_core ( 29 | .LOCK(locked), 30 | .RESETB(1'b1), 31 | .BYPASS(1'b0), 32 | .REFERENCECLK(clock_in), 33 | .PLLOUTCORE(clock_out), 34 | 35 | // Unused 36 | .PLLOUTGLOBAL(), 37 | .EXTFEEDBACK(), 38 | .LATCHINPUTVALUE(), 39 | .SDO(), 40 | .SDI(), 41 | .SCLK(), 42 | .DYNAMICDELAY() 43 | 44 | ); 45 | 46 | endmodule 47 | 48 | -------------------------------------------------------------------------------- /examples/upduino31/testbench/apio.ini: -------------------------------------------------------------------------------- 1 | ; Apio project configuration file. 2 | ; Type 'apio info apio.ini' for details. 3 | 4 | [env:default] 5 | board = upduino31 6 | top-module = main 7 | -------------------------------------------------------------------------------- /examples/upduino31/testbench/bcd_counter.v: -------------------------------------------------------------------------------- 1 | // A 4 bit BCD counter with synchronous clock and carry out. 2 | // It Counts up on positive edge of clk, when count_en is high. 3 | 4 | module bcd_counter ( 5 | input clk, 6 | input reset, 7 | input count_en, 8 | output reg [3:0] data_out, 9 | output carry 10 | ); 11 | 12 | // Behavior. 13 | always @(posedge clk) begin 14 | if (reset || data_out > 9) begin 15 | // Case 1: Reset or invalid state.; 16 | data_out <= 0; 17 | end else if (count_en) begin 18 | // Case 1: Increment, with optional overflow from 9 to 0. 19 | data_out <= (data_out == 9) ? 0 : data_out + 1; 20 | end 21 | end 22 | 23 | assign carry = !reset && count_en && (data_out == 9); 24 | 25 | endmodule 26 | -------------------------------------------------------------------------------- /examples/upduino31/testbench/info: -------------------------------------------------------------------------------- 1 | A testbench example -------------------------------------------------------------------------------- /examples/upduino31/testbench/main.pcf: -------------------------------------------------------------------------------- 1 | # Mapping of the design signals to FPGA pins. 2 | 3 | # The full Upduino3 PCF file is availble at: 4 | # https://github.com/tinyvision-ai-inc/UPduino-v3.0/tree/master/RTL/common 5 | 6 | set_io clk 10 7 | set_io reset 12 8 | set_io count_en 21 9 | set_io carry 13 10 | 11 | set_io digit_1[0] 19 12 | set_io digit_1[1] 18 13 | set_io digit_1[2] 11 14 | set_io digit_1[3] 9 15 | 16 | set_io digit_10[0] 44 17 | set_io digit_10[1] 4 18 | set_io digit_10[2] 3 19 | set_io digit_10[3] 48 20 | 21 | -------------------------------------------------------------------------------- /examples/upduino31/testbench/main.v: -------------------------------------------------------------------------------- 1 | // Generates a RGB blinking pattern. Uses the internal oscilator. 2 | module main ( 3 | input clk, 4 | input reset, 5 | input count_en, 6 | output [3:0] digit_1, 7 | output [3:0] digit_10, 8 | output carry 9 | ); 10 | 11 | wire carry_1; 12 | 13 | bcd_counter count_1 ( 14 | .clk(clk), 15 | .reset(reset), 16 | .count_en(count_en), 17 | .data_out(digit_1), 18 | .carry(carry_1) 19 | ); 20 | 21 | bcd_counter count_10 ( 22 | .clk(clk), 23 | .reset(reset), 24 | .count_en(carry_1), 25 | .data_out(digit_10), 26 | .carry(carry) 27 | ); 28 | 29 | endmodule 30 | -------------------------------------------------------------------------------- /examples/upduino31/testbench/main_tb.gtkw: -------------------------------------------------------------------------------- 1 | [*] 2 | [*] GTKWave Analyzer v3.4.0 (w)1999-2022 BSI 3 | [*] Sat Mar 2 22:47:15 2024 4 | [*] 5 | [dumpfile] "main_tb.vcd" 6 | [dumpfile_mtime] "Sat Mar 2 22:46:12 2024" 7 | [dumpfile_size] 7168 8 | [savefile] "main_tb.gtkw" 9 | [timestart] 0 10 | [size] 1440 900 11 | [pos] -1 -26 12 | *-22.382421 3100000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 13 | [markername] AA 14 | [markername] BB 15 | [markername] CC 16 | [markername] DD 17 | [markername] EE 18 | [markername] FF 19 | [markername] GG 20 | [markername] HH 21 | [markername] II 22 | [markername] JJ 23 | [markername] KK 24 | [markername] LL 25 | [markername] MM 26 | [markername] NN 27 | [markername] OO 28 | [markername] PP 29 | [markername] QQ 30 | [markername] RR 31 | [markername] SS 32 | [markername] TT 33 | [markername] UU 34 | [markername] VV 35 | [markername] WW 36 | [markername] XX 37 | [markername] YY 38 | [markername] ZZ 39 | [treeopen] main_tb. 40 | [sst_width] 253 41 | [signals_width] 161 42 | [sst_expanded] 1 43 | [sst_vpaned_height] 264 44 | @28 45 | main_tb.clk 46 | main_tb.reset 47 | [color] 3 48 | main_tb.count_en 49 | @24 50 | main_tb.digit_1[3:0] 51 | @25 52 | main_tb.digit_10[3:0] 53 | @28 54 | main_tb.carry 55 | @24 56 | main_tb.carry_count[5:0] 57 | [pattern_trace] 1 58 | [pattern_trace] 0 59 | -------------------------------------------------------------------------------- /format_examples.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | # A shell script to format the source files of all examples. 4 | 5 | python scripts/format_examples.py 6 | 7 | -------------------------------------------------------------------------------- /scripts/__init__: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/FPGAwars/apio-examples/ec7da6db0ed17c9d22abc36a527b2a501e7cada0/scripts/__init__ -------------------------------------------------------------------------------- /scripts/clean_examples.py: -------------------------------------------------------------------------------- 1 | """A python script to clean the examples projects. 2 | 3 | Usage: 4 | python build_examples.py 5 | """ 6 | 7 | from pathlib import Path 8 | import os 9 | from glob import glob 10 | 11 | # -- The examples root directory. 12 | examples_dir = Path("examples").resolve() 13 | assert examples_dir.is_dir(), examples_dir 14 | 15 | for board in glob("*", root_dir=examples_dir): 16 | board_dir = examples_dir / board 17 | for example in glob("*", root_dir=board_dir): 18 | example_dir = board_dir / example 19 | 20 | # -- Change to example directory. 21 | print(f"cd {example_dir}") 22 | os.chdir(example_dir) 23 | 24 | # -- Run 'apio clean'. We don't check the status. 25 | print(f"apio clean") 26 | os.system("apio clean") 27 | -------------------------------------------------------------------------------- /scripts/format_examples.py: -------------------------------------------------------------------------------- 1 | """A python script that scans the entire examples tree and formats the 2 | source files. 3 | 4 | Do not run directly, run format_examples.py from repo's root. 5 | """ 6 | 7 | from pathlib import Path 8 | import os 9 | from pathlib import Path 10 | import os 11 | from glob import glob 12 | 13 | 14 | examples_dir = Path("examples").resolve() 15 | print(examples_dir) 16 | assert examples_dir.is_dir(), examples_dir 17 | 18 | for board_name in glob("*", root_dir=examples_dir): 19 | board_dir = examples_dir / board_name 20 | for example_name in glob("*", root_dir=board_dir): 21 | example_dir = board_dir / example_name 22 | print(f"*** Example {str(examples_dir)}") 23 | os.chdir(example_dir) 24 | status = os.system("apio format") 25 | assert status == 0, "Failed formatting" 26 | -------------------------------------------------------------------------------- /update_reports.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | # A shell script that generate reports. 4 | 5 | rm -f _boards_full.csv _boards_issues_only.csv 6 | rm -f _examples_full.csv _examples_issues_only.csv 7 | 8 | python scripts/generate_reports.py 9 | 10 | --------------------------------------------------------------------------------