├── .cproject ├── .gitignore ├── .project ├── .pydevproject ├── .settings └── language.settings.xml ├── .svproject ├── ChangeLog.txt ├── LICENSE ├── README.md ├── azure-pipelines.yml ├── doc ├── fwrisc_design.md ├── fwrisc_diagram.graphml ├── fwrisc_diagram.png ├── fwrisc_formal_testbench_diagram.graphml ├── fwrisc_formal_testbench_diagram.png ├── fwrisc_quickstart.md ├── fwrisc_setup.md ├── fwrisc_synthesis.md ├── fwrisc_testbench_diagram.graphml ├── fwrisc_testbench_diagram.png ├── fwrisc_tools.md ├── fwrisc_verification.md ├── fwrisc_zephyr.md └── imgs │ ├── Philosophers.gif │ ├── csrrc.json │ ├── csrrc.png │ ├── csrrc_2.json │ ├── csrrs.json │ ├── csrrs.pmg │ ├── csrrs.png │ ├── csrrw.json │ ├── csrrw.png │ ├── exception.json │ ├── fwrisc_state_machine.epgz │ ├── memread.json │ ├── unit_testbench.epgz │ ├── unit_testbench.png │ └── unit_testbench_crop.png ├── etc ├── fwrisc_env.sh ├── ivpm.info └── packages.mf ├── ivpm.yaml ├── requirements.txt ├── requirements_dev.txt ├── rtl ├── defs_rules.mk ├── fwrisc.f ├── fwrisc.sv ├── fwrisc_alu.sv ├── fwrisc_alu_op.svh ├── fwrisc_c_decode.sv ├── fwrisc_csr_addr.svh ├── fwrisc_decode.sv ├── fwrisc_defines.vh ├── fwrisc_exec.sv ├── fwrisc_fetch.sv ├── fwrisc_mem.sv ├── fwrisc_mem_op.svh ├── fwrisc_mul_div_shift.sv ├── fwrisc_mul_div_shift_op.svh ├── fwrisc_op_type.svh ├── fwrisc_regfile.sv ├── fwrisc_rv32i.sv ├── fwrisc_rv32i_wb.sv ├── fwrisc_rv32ic.sv ├── fwrisc_rv32im.sv ├── fwrisc_rv32imc.sv ├── fwrisc_system_op.svh ├── fwrisc_tracer.sv ├── fwrisc_wb.sv ├── regs.hex ├── sav │ ├── fwrisc.sv.orig │ ├── fwrisc.sv.orig.sav │ ├── fwrisc_comparator.sv │ └── fwrisc_dbus_if.sv └── sve.F ├── scripts ├── ivpm.mk └── ivpm.py ├── soc ├── fwrisc_fpga_top.sv └── fwrisc_soc.f ├── sve.F ├── sve_top.F ├── sw ├── defs_rules.mk └── fwrisc │ └── dts │ └── bindings │ ├── fwrisc.yaml │ └── fwrisc.yaml.sav ├── synth ├── intel │ └── fwrisc │ │ ├── fwrisc.qpf │ │ ├── fwrisc.qsf │ │ └── fwrisc.sdc ├── lattice │ └── icestorm │ │ ├── Makefile │ │ └── cmds.do └── microsemi │ ├── .gitignore │ ├── Makefile │ ├── bitstream │ └── fwrisc_fpga_top.stp │ ├── constraints │ ├── fwrisc_fpga_top.pdc │ └── fwrisc_fpga_top.sdc │ ├── fwrisc_decode_regfile │ ├── fwrisc_decode_regfile.prj │ └── fwrisc_decode_regfile.sv │ ├── scripts │ └── fwrisc_synthesis.tcl │ ├── sw │ ├── led_flash │ │ ├── CMakeLists.txt │ │ └── src │ │ │ └── led_flash.c │ └── rom.hex │ └── synplify │ ├── fwrisc │ ├── fwrisc.prd │ ├── fwrisc.prj │ ├── fwrisc_alu_op.svh │ ├── fwrisc_csr_addr.svh │ ├── fwrisc_mem_op.svh │ ├── fwrisc_mul_div_shift_op.svh │ ├── fwrisc_op_type.svh │ └── fwrisc_system_op.svh │ └── fwrisc_area.prj └── ve ├── fwrisc_decode_formal ├── formal │ ├── fwrisc_decode_formal.py │ ├── scripts │ │ ├── Makefile │ │ ├── fwrisc_decode_formal.sby │ │ ├── status.sh │ │ └── vsc.py │ ├── testlists │ │ └── fwrisc_decode_formal_all.f │ └── tests │ │ ├── fwrisc_decode_formal_all_sims.py │ │ ├── fwrisc_decode_formal_i32_btype.f │ │ ├── fwrisc_decode_formal_i32_itype.f │ │ ├── fwrisc_decode_formal_i32_lui.f │ │ ├── fwrisc_decode_formal_i32_rtype.f │ │ └── fwrisc_decode_formal_tests.py ├── tb │ ├── fwrisc_decode_formal_i32_btype_checker.sv │ ├── fwrisc_decode_formal_i32_checker.sv │ ├── fwrisc_decode_formal_i32_itype_checker.sv │ ├── fwrisc_decode_formal_i32_lui_checker.sv │ ├── fwrisc_decode_formal_i32_rtype_checker.sv │ ├── fwrisc_decode_formal_smoke_checker.sv │ └── fwrisc_decode_formal_tb.sv └── tests │ ├── fwrisc_decode_formal_i32_btype_test.sv │ ├── fwrisc_decode_formal_i32_itype_test.sv │ ├── fwrisc_decode_formal_i32_lui_test.sv │ ├── fwrisc_decode_formal_i32_rtype_test.sv │ ├── fwrisc_decode_formal_opcode_defines.svh │ └── fwrisc_decode_formal_smoke_test.sv ├── fwrisc_exec_formal ├── formal │ ├── scripts │ │ ├── Makefile │ │ ├── fwrisc_exec_formal.sby │ │ └── status.sh │ ├── testlists │ │ └── fwrisc_exec_formal_all.f │ └── tests │ │ ├── fwrisc_exec_formal_arith.f │ │ ├── fwrisc_exec_formal_branch.f │ │ ├── fwrisc_exec_formal_call.f │ │ ├── fwrisc_exec_formal_csr.f │ │ ├── fwrisc_exec_formal_jump.f │ │ ├── fwrisc_exec_formal_mds.f │ │ ├── fwrisc_exec_formal_mem.f │ │ └── fwrisc_exec_formal_smoke.f ├── sve.F ├── tb │ ├── fwrisc_exec_formal_arith_checker.sv │ ├── fwrisc_exec_formal_branch_checker.sv │ ├── fwrisc_exec_formal_call_checker.sv │ ├── fwrisc_exec_formal_csr_checker.sv │ ├── fwrisc_exec_formal_defines.svh │ ├── fwrisc_exec_formal_jump_checker.sv │ ├── fwrisc_exec_formal_mds_checker.sv │ ├── fwrisc_exec_formal_mem_checker.sv │ ├── fwrisc_exec_formal_smoke_checker.sv │ └── fwrisc_exec_formal_tb.sv └── tests │ ├── fwrisc_exec_formal_arith_test.sv │ ├── fwrisc_exec_formal_branch_test.sv │ ├── fwrisc_exec_formal_call_test.sv │ ├── fwrisc_exec_formal_csr_test.sv │ ├── fwrisc_exec_formal_jump_test.sv │ ├── fwrisc_exec_formal_mds_test.sv │ ├── fwrisc_exec_formal_mem_test.sv │ └── fwrisc_exec_formal_smoke_test.sv ├── fwrisc_fetch_formal ├── formal │ ├── scripts │ │ ├── Makefile │ │ ├── fwrisc_fetch_formal.sby │ │ └── status.sh │ ├── testlists │ │ └── fwrisc_fetch_formal_all.f │ └── tests │ │ ├── fwrisc_fetch_formal_seq16.f │ │ ├── fwrisc_fetch_formal_seq32.f │ │ ├── fwrisc_fetch_formal_seqmix.f │ │ └── fwrisc_fetch_formal_smoke.f ├── tb │ ├── fwrisc_fetch_formal_defines.svh │ ├── fwrisc_fetch_formal_seqmix_checker.sv │ ├── fwrisc_fetch_formal_smoke_checker.sv │ └── fwrisc_fetch_formal_tb.sv └── tests │ ├── fwrisc_fetch_formal_seq16_test.sv │ ├── fwrisc_fetch_formal_seq32_test.sv │ ├── fwrisc_fetch_formal_seqmix_test.sv │ └── fwrisc_fetch_formal_smoke_test.sv ├── fwrisc_formal ├── sim │ ├── scripts │ │ ├── Makefile │ │ ├── fwrisc_formal.sby │ │ └── status.sh │ ├── testlists │ │ └── fwrisc_formal_all.f │ └── tests │ │ ├── fwrisc_formal_add_i.f │ │ ├── fwrisc_formal_add_r.f │ │ ├── fwrisc_formal_and_r.f │ │ ├── fwrisc_formal_auipc.f │ │ ├── fwrisc_formal_jal.f │ │ ├── fwrisc_formal_jalr.f │ │ ├── fwrisc_formal_ld.f │ │ ├── fwrisc_formal_lui.f │ │ ├── fwrisc_formal_or_i.f │ │ ├── fwrisc_formal_or_r.f │ │ ├── fwrisc_formal_sll_i.f │ │ ├── fwrisc_formal_sll_r.f │ │ ├── fwrisc_formal_slt_i.f │ │ ├── fwrisc_formal_slt_r.f │ │ ├── fwrisc_formal_sltu_i.f │ │ ├── fwrisc_formal_sltu_r.f │ │ ├── fwrisc_formal_srl_r.f │ │ ├── fwrisc_formal_sub_r.f │ │ ├── fwrisc_formal_xor_i.f │ │ └── fwrisc_formal_xor_r.f ├── tb │ ├── fwrisc.sby │ ├── fwrisc_formal_arith_checker.sv │ ├── fwrisc_formal_jump_checker.sv │ ├── fwrisc_formal_ldst_checker.sv │ ├── fwrisc_formal_opcode_defines.svh │ └── fwrisc_formal_tb.sv └── tests │ ├── fwrisc_formal_add_i.svh │ ├── fwrisc_formal_add_r.svh │ ├── fwrisc_formal_and_r.svh │ ├── fwrisc_formal_auipc.svh │ ├── fwrisc_formal_jal.svh │ ├── fwrisc_formal_jalr.svh │ ├── fwrisc_formal_ld.svh │ ├── fwrisc_formal_lui.svh │ ├── fwrisc_formal_or_i.svh │ ├── fwrisc_formal_or_r.svh │ ├── fwrisc_formal_sll_i.svh │ ├── fwrisc_formal_sll_r.svh │ ├── fwrisc_formal_slt_i.svh │ ├── fwrisc_formal_slt_r.svh │ ├── fwrisc_formal_sltu_i.svh │ ├── fwrisc_formal_sltu_r.svh │ ├── fwrisc_formal_sra_r.svh │ ├── fwrisc_formal_srl_r.svh │ ├── fwrisc_formal_sub_r.svh │ ├── fwrisc_formal_xor_i.svh │ └── fwrisc_formal_xor_r.svh ├── fwrisc_mem_formal ├── formal │ ├── scripts │ │ ├── Makefile │ │ ├── fwrisc_mem.sby │ │ └── status.sh │ ├── testlists │ │ └── fwrisc_mem_all.f │ └── tests │ │ └── fwrisc_mem_smoke.f ├── tb │ ├── fwrisc_mem_defines.svh │ ├── fwrisc_mem_smoke_checker.sv │ └── fwrisc_mem_tb.sv └── tests │ └── fwrisc_mem_smoke_test.sv ├── fwrisc_mul_div_shift_formal ├── sim │ ├── scripts │ │ ├── Makefile │ │ ├── fwrisc_mul_div_shift_formal.sby │ │ └── status.sh │ ├── testlists │ │ └── fwrisc_mul_div_shift_formal_all.f │ └── tests │ │ ├── fwrisc_mul_div_shift_formal_mul.f │ │ ├── fwrisc_mul_div_shift_formal_mulh.f │ │ ├── fwrisc_mul_div_shift_formal_muls.f │ │ ├── fwrisc_mul_div_shift_formal_mulsh.f │ │ ├── fwrisc_mul_div_shift_formal_shl.f │ │ ├── fwrisc_mul_div_shift_formal_sra.f │ │ └── fwrisc_mul_div_shift_formal_srl.f ├── tb │ ├── fwrisc_mul_div_shift_formal_mul_checker.sv │ ├── fwrisc_mul_div_shift_formal_shift_checker.sv │ └── fwrisc_mul_div_shift_formal_tb.sv └── tests │ ├── fwrisc_mul_div_shift_formal_mul.sv │ ├── fwrisc_mul_div_shift_formal_mulh.sv │ ├── fwrisc_mul_div_shift_formal_muls.sv │ ├── fwrisc_mul_div_shift_formal_mulsh.sv │ ├── fwrisc_mul_div_shift_formal_shl.sv │ ├── fwrisc_mul_div_shift_formal_sra.sv │ └── fwrisc_mul_div_shift_formal_srl.sv ├── fwrisc_rv32e ├── fwrisc_rv32e.F ├── sim │ ├── .simscripts │ ├── scripts │ │ ├── Makefile │ │ ├── embedded.mk │ │ ├── mk_instr_tests.sh │ │ ├── status.sh │ │ ├── vlog.f │ │ ├── vlog_hdl.f │ │ ├── vlog_hdl_ms.f │ │ ├── vlog_hvl.f │ │ ├── vlog_hvl_ms.f │ │ ├── vlog_ms.f │ │ └── vlog_vl-pyhpi_hdl.f │ ├── testlists │ │ ├── fwrisc_riscv_all_tests.tl │ │ ├── fwrisc_riscv_compliance_tests.tl │ │ ├── fwrisc_riscv_instr_tests.tl │ │ ├── fwrisc_riscv_ripe_tests.tl │ │ └── fwrisc_riscv_unit_tests.f │ └── tests │ │ ├── fwrisc_instr_tests_arith_add.f │ │ ├── fwrisc_instr_tests_arith_addi.f │ │ ├── fwrisc_instr_tests_arith_addi_neg.f │ │ ├── fwrisc_instr_tests_arith_and.f │ │ ├── fwrisc_instr_tests_arith_andi.f │ │ ├── fwrisc_instr_tests_arith_or.f │ │ ├── fwrisc_instr_tests_arith_ori.f │ │ ├── fwrisc_instr_tests_arith_sll.f │ │ ├── fwrisc_instr_tests_arith_slli.f │ │ ├── fwrisc_instr_tests_arith_slt_f.f │ │ ├── fwrisc_instr_tests_arith_slt_t_neg.f │ │ ├── fwrisc_instr_tests_arith_slt_t_pos.f │ │ ├── fwrisc_instr_tests_arith_slti_f.f │ │ ├── fwrisc_instr_tests_arith_slti_t.f │ │ ├── fwrisc_instr_tests_arith_sltu_t.f │ │ ├── fwrisc_instr_tests_arith_sra.f │ │ ├── fwrisc_instr_tests_arith_srai.f │ │ ├── fwrisc_instr_tests_arith_srl.f │ │ ├── fwrisc_instr_tests_arith_srli.f │ │ ├── fwrisc_instr_tests_arith_sub.f │ │ ├── fwrisc_instr_tests_arith_xor.f │ │ ├── fwrisc_instr_tests_arith_xori.f │ │ ├── fwrisc_instr_tests_branch_beq_f_back.f │ │ ├── fwrisc_instr_tests_branch_beq_f_fwd.f │ │ ├── fwrisc_instr_tests_branch_beq_t_back.f │ │ ├── fwrisc_instr_tests_branch_beq_t_fwd.f │ │ ├── fwrisc_instr_tests_branch_bge_eq_t_neg.f │ │ ├── fwrisc_instr_tests_branch_bge_eq_t_pos.f │ │ ├── fwrisc_instr_tests_branch_bge_gt_t_neg.f │ │ ├── fwrisc_instr_tests_branch_bge_gt_t_pos.f │ │ ├── fwrisc_instr_tests_branch_blt_t_neg.f │ │ ├── fwrisc_instr_tests_branch_blt_t_pos.f │ │ ├── fwrisc_instr_tests_branch_bltu_t_neg.f │ │ ├── fwrisc_instr_tests_branch_bltu_t_pos.f │ │ ├── fwrisc_instr_tests_branch_bne_f_back.f │ │ ├── fwrisc_instr_tests_branch_bne_f_fwd.f │ │ ├── fwrisc_instr_tests_branch_bne_t_back.f │ │ ├── fwrisc_instr_tests_branch_bne_t_fwd.f │ │ ├── fwrisc_instr_tests_counters_cycle.f │ │ ├── fwrisc_instr_tests_exception_bne.f │ │ ├── fwrisc_instr_tests_exception_dep_x.f │ │ ├── fwrisc_instr_tests_exception_j.f │ │ ├── fwrisc_instr_tests_exception_jalr.f │ │ ├── fwrisc_instr_tests_exception_lw.f │ │ ├── fwrisc_instr_tests_jump_j.f │ │ ├── fwrisc_instr_tests_jump_jal.f │ │ ├── fwrisc_instr_tests_jump_jalr.f │ │ ├── fwrisc_instr_tests_jump_jalr_off_neg.f │ │ ├── fwrisc_instr_tests_jump_jalr_off_pos.f │ │ ├── fwrisc_instr_tests_ldst_lb.f │ │ ├── fwrisc_instr_tests_ldst_lb_s.f │ │ ├── fwrisc_instr_tests_ldst_lb_u.f │ │ ├── fwrisc_instr_tests_ldst_lbu_s.f │ │ ├── fwrisc_instr_tests_ldst_lh_s.f │ │ ├── fwrisc_instr_tests_ldst_lh_u.f │ │ ├── fwrisc_instr_tests_ldst_lhu_s.f │ │ ├── fwrisc_instr_tests_ldst_lw.f │ │ ├── fwrisc_instr_tests_ldst_sb_lw.f │ │ ├── fwrisc_instr_tests_ldst_sh_lw.f │ │ ├── fwrisc_instr_tests_ldst_sw_lw.f │ │ ├── fwrisc_instr_tests_long_loop.f │ │ ├── fwrisc_instr_tests_lui.f │ │ ├── fwrisc_instr_tests_system_csrc.f │ │ ├── fwrisc_instr_tests_system_csrr.f │ │ ├── fwrisc_instr_tests_system_csrs.f │ │ ├── fwrisc_instr_tests_system_csrsi.f │ │ ├── fwrisc_instr_tests_system_csrw.f │ │ ├── fwrisc_instr_tests_system_csrw_csrr.f │ │ ├── fwrisc_instr_tests_system_ecall.f │ │ ├── fwrisc_instr_tests_system_eret.f │ │ ├── fwrisc_ripe_1.f │ │ ├── fwrisc_ripe_2.f │ │ ├── fwrisc_ripe_3.f │ │ ├── fwrisc_ripe_4.f │ │ ├── fwrisc_ripe_5.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-ADD-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-ADDI-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-AND-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-ANDI-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-AUIPC-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-BEQ-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-BGE-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-BGEU-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-BLT-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-BLTU-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-BNE-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-CSRRC-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-CSRRCI-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-CSRRS-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-CSRRSI-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-CSRRW-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-CSRRWI-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-DELAY_SLOTS-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-EBREAK-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-ECALL-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-ENDIANESS-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-FENCE.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-IO.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-JAL-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-JALR-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-LB-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-LBU-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-LH-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-LHU-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-LUI-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-LW-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-MISALIGN_JMP-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-MISALIGN_LDST-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-NOP-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-OR-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-ORI-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-RF_size-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-RF_width-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-RF_x0-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-SB-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-SH-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-SLL-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-SLLI-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-SLT-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-SLTI-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-SLTIU-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-SLTU-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-SRA-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-SRAI-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-SRL-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-SRLI-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-SUB-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-SW-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-XOR-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-XORI-01.f │ │ ├── fwrisc_zephyr_dhrystone.f │ │ ├── fwrisc_zephyr_hello_world.f │ │ ├── fwrisc_zephyr_philosophers.f │ │ └── fwrisc_zephyr_synchronization.f ├── tb │ ├── fwrisc_rv32e_tb_hdl.sv │ ├── fwrisc_rv32i_tb_hvl.sv │ ├── tb.F │ └── vl │ │ ├── fwrisc_tb_hdl.cpp │ │ ├── fwrisc_tb_hdl.h │ │ └── fwrisc_tb_vl.mk └── tests │ ├── cpp │ ├── ElfDataReader.cpp │ ├── ElfDataReader.h │ ├── ElfFileReader.cpp │ ├── ElfFileReader.h │ ├── ElfSymtabReader.cpp │ ├── ElfSymtabReader.h │ ├── fwrisc_ctest_base.cpp │ ├── fwrisc_ctest_base.h │ ├── fwrisc_instr_tests.cpp │ ├── fwrisc_instr_tests.h │ ├── fwrisc_instr_tests_counters.cpp │ ├── fwrisc_instr_tests_counters.h │ ├── fwrisc_perf_tests.cpp │ ├── fwrisc_perf_tests.h │ ├── fwrisc_ripe_tests.cpp │ ├── fwrisc_ripe_tests.h │ ├── fwrisc_zephyr_tests.cpp │ ├── fwrisc_zephyr_tests.h │ ├── riscv_compliance_tests.cpp │ └── riscv_compliance_tests.h │ ├── dhrystone │ ├── CMakeLists.txt │ ├── dhrystone.mk │ └── src │ │ ├── dhrystone.c │ │ ├── dhrystone.h │ │ ├── dhrystone_main.c │ │ └── util.h │ ├── fwrisc_tests.mk │ ├── pyfv-hpi │ └── fwrisc_tests │ │ ├── __init__.py │ │ ├── base.py │ │ ├── instr.py │ │ ├── riscv_compliance.py │ │ └── zephyr.py │ ├── tests.F │ ├── unit │ ├── arith_add.S │ ├── arith_addi.S │ ├── arith_addi_neg.S │ ├── arith_and.S │ ├── arith_andi.S │ ├── arith_or.S │ ├── arith_ori.S │ ├── arith_sll.S │ ├── arith_slli.S │ ├── arith_slt_f.S │ ├── arith_slt_t_neg.S │ ├── arith_slt_t_pos.S │ ├── arith_slti_f.S │ ├── arith_slti_t.S │ ├── arith_sltu_t.S │ ├── arith_sra.S │ ├── arith_srai.S │ ├── arith_srl.S │ ├── arith_srli.S │ ├── arith_sub.S │ ├── arith_xor.S │ ├── arith_xori.S │ ├── branch_beq_f_back.S │ ├── branch_beq_f_fwd.S │ ├── branch_beq_t_back.S │ ├── branch_beq_t_fwd.S │ ├── branch_bge_eq_t_neg.S │ ├── branch_bge_eq_t_pos.S │ ├── branch_bge_gt_t_neg.S │ ├── branch_bge_gt_t_pos.S │ ├── branch_blt_t_neg.S │ ├── branch_blt_t_pos.S │ ├── branch_bltu_t_neg.S │ ├── branch_bltu_t_pos.S │ ├── branch_bne_f_back.S │ ├── branch_bne_f_fwd.S │ ├── branch_bne_t_back.S │ ├── branch_bne_t_fwd.S │ ├── exception_bne.S │ ├── exception_dep_x.S │ ├── exception_j.S │ ├── exception_jalr.S │ ├── exception_lw.S │ ├── jump_j.S │ ├── jump_jal.S │ ├── jump_jalr.S │ ├── jump_jalr_off_neg.S │ ├── jump_jalr_off_pos.S │ ├── ldst_lb.S │ ├── ldst_lb_s.S │ ├── ldst_lb_u.S │ ├── ldst_lbu_s.S │ ├── ldst_lh_s.S │ ├── ldst_lh_u.S │ ├── ldst_lhu_s.S │ ├── ldst_lw.S │ ├── ldst_sb_lw.S │ ├── ldst_sh_lw.S │ ├── ldst_sw_lw.S │ ├── long_loop.S │ ├── lui.S │ ├── system_csrc.S │ ├── system_csrr.S │ ├── system_csrs.S │ ├── system_csrsi.S │ ├── system_csrw.S │ ├── system_csrw_csrr.S │ ├── system_ecall.S │ ├── system_eret.S │ ├── unit.ld │ └── unit_header.h │ └── uvm │ ├── elf_symtab_reader.svh │ ├── fwrisc_instr_test.svh │ ├── fwrisc_riscv_compliance_tests.svh │ ├── fwrisc_test_base.svh │ └── fwrisc_tests_pkg.sv ├── fwrisc_rv32i ├── fwrisc_rv32i.F ├── sim │ ├── .simscripts │ ├── scripts │ │ ├── Makefile │ │ ├── embedded.mk │ │ ├── mk_instr_tests.sh │ │ ├── status.sh │ │ ├── vlog.f │ │ ├── vlog_hdl.f │ │ ├── vlog_hdl_ms.f │ │ ├── vlog_hvl.f │ │ ├── vlog_hvl_ms.f │ │ ├── vlog_ms.f │ │ └── vlog_vl-pyhpi_hdl.f │ ├── testlists │ │ ├── fwrisc_riscv_all_tests.tl │ │ ├── fwrisc_riscv_azure_tests.tl │ │ ├── fwrisc_riscv_compliance_tests.tl │ │ ├── fwrisc_riscv_instr_tests.tl │ │ ├── fwrisc_riscv_ripe_tests.tl │ │ └── fwrisc_riscv_unit_tests.f │ └── tests │ │ ├── fwrisc_instr_tests_arith_add.f │ │ ├── fwrisc_instr_tests_arith_addi.f │ │ ├── fwrisc_instr_tests_arith_addi_neg.f │ │ ├── fwrisc_instr_tests_arith_and.f │ │ ├── fwrisc_instr_tests_arith_andi.f │ │ ├── fwrisc_instr_tests_arith_or.f │ │ ├── fwrisc_instr_tests_arith_ori.f │ │ ├── fwrisc_instr_tests_arith_sll.f │ │ ├── fwrisc_instr_tests_arith_slli.f │ │ ├── fwrisc_instr_tests_arith_slt_f.f │ │ ├── fwrisc_instr_tests_arith_slt_t_neg.f │ │ ├── fwrisc_instr_tests_arith_slt_t_pos.f │ │ ├── fwrisc_instr_tests_arith_slti_f.f │ │ ├── fwrisc_instr_tests_arith_slti_t.f │ │ ├── fwrisc_instr_tests_arith_sltu_t.f │ │ ├── fwrisc_instr_tests_arith_sra.f │ │ ├── fwrisc_instr_tests_arith_srai.f │ │ ├── fwrisc_instr_tests_arith_srl.f │ │ ├── fwrisc_instr_tests_arith_srli.f │ │ ├── fwrisc_instr_tests_arith_sub.f │ │ ├── fwrisc_instr_tests_arith_xor.f │ │ ├── fwrisc_instr_tests_arith_xori.f │ │ ├── fwrisc_instr_tests_branch_beq_f_back.f │ │ ├── fwrisc_instr_tests_branch_beq_f_fwd.f │ │ ├── fwrisc_instr_tests_branch_beq_t_back.f │ │ ├── fwrisc_instr_tests_branch_beq_t_fwd.f │ │ ├── fwrisc_instr_tests_branch_bge_eq_t_neg.f │ │ ├── fwrisc_instr_tests_branch_bge_eq_t_pos.f │ │ ├── fwrisc_instr_tests_branch_bge_gt_t_neg.f │ │ ├── fwrisc_instr_tests_branch_bge_gt_t_pos.f │ │ ├── fwrisc_instr_tests_branch_blt_t_neg.f │ │ ├── fwrisc_instr_tests_branch_blt_t_pos.f │ │ ├── fwrisc_instr_tests_branch_bltu_t_neg.f │ │ ├── fwrisc_instr_tests_branch_bltu_t_pos.f │ │ ├── fwrisc_instr_tests_branch_bne_f_back.f │ │ ├── fwrisc_instr_tests_branch_bne_f_fwd.f │ │ ├── fwrisc_instr_tests_branch_bne_t_back.f │ │ ├── fwrisc_instr_tests_branch_bne_t_fwd.f │ │ ├── fwrisc_instr_tests_counters_cycle.f │ │ ├── fwrisc_instr_tests_exception_bne.f │ │ ├── fwrisc_instr_tests_exception_dep_x.f │ │ ├── fwrisc_instr_tests_exception_j.f │ │ ├── fwrisc_instr_tests_exception_jalr.f │ │ ├── fwrisc_instr_tests_exception_lw.f │ │ ├── fwrisc_instr_tests_jump_j.f │ │ ├── fwrisc_instr_tests_jump_jal.f │ │ ├── fwrisc_instr_tests_jump_jalr.f │ │ ├── fwrisc_instr_tests_jump_jalr_off_neg.f │ │ ├── fwrisc_instr_tests_jump_jalr_off_pos.f │ │ ├── fwrisc_instr_tests_ldst_lb.f │ │ ├── fwrisc_instr_tests_ldst_lb_s.f │ │ ├── fwrisc_instr_tests_ldst_lb_u.f │ │ ├── fwrisc_instr_tests_ldst_lbu_s.f │ │ ├── fwrisc_instr_tests_ldst_lh_s.f │ │ ├── fwrisc_instr_tests_ldst_lh_u.f │ │ ├── fwrisc_instr_tests_ldst_lhu_s.f │ │ ├── fwrisc_instr_tests_ldst_lw.f │ │ ├── fwrisc_instr_tests_ldst_sb_lw.f │ │ ├── fwrisc_instr_tests_ldst_sh_lw.f │ │ ├── fwrisc_instr_tests_ldst_sw_lw.f │ │ ├── fwrisc_instr_tests_long_loop.f │ │ ├── fwrisc_instr_tests_lui.f │ │ ├── fwrisc_instr_tests_system_csrc.f │ │ ├── fwrisc_instr_tests_system_csrr.f │ │ ├── fwrisc_instr_tests_system_csrs.f │ │ ├── fwrisc_instr_tests_system_csrsi.f │ │ ├── fwrisc_instr_tests_system_csrw.f │ │ ├── fwrisc_instr_tests_system_csrw_csrr.f │ │ ├── fwrisc_instr_tests_system_ecall.f │ │ ├── fwrisc_instr_tests_system_eret.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-ADD-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-ADDI-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-AND-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-ANDI-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-AUIPC-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-BEQ-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-BGE-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-BGEU-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-BLT-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-BLTU-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-BNE-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-DELAY_SLOTS-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-EBREAK-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-ECALL-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-ENDIANESS-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-IO.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-JAL-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-JALR-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-LB-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-LBU-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-LH-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-LHU-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-LUI-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-LW-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-MISALIGN_JMP-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-MISALIGN_LDST-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-NOP-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-OR-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-ORI-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-RF_size-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-RF_width-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-RF_x0-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-SB-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-SH-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-SLL-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-SLLI-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-SLT-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-SLTI-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-SLTIU-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-SLTU-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-SRA-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-SRAI-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-SRL-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-SRLI-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-SUB-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-SW-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-XOR-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-XORI-01.f │ │ ├── fwrisc_zephyr_dhrystone.f │ │ ├── fwrisc_zephyr_hello_world.f │ │ ├── fwrisc_zephyr_philosophers.f │ │ └── fwrisc_zephyr_synchronization.f ├── tb │ ├── fwrisc_rv32i_tb_hdl.sv │ ├── fwrisc_rv32i_tb_hvl.sv │ ├── tb.f │ └── vl │ │ ├── fwrisc_tb_hdl.cpp │ │ ├── fwrisc_tb_hdl.h │ │ └── fwrisc_tb_vl.mk └── tests │ ├── cocotb │ └── fwrisc_rv32i_tests │ │ ├── __init__.py │ │ ├── compliance_tests.py │ │ ├── instr_tests.py │ │ ├── zephyr_hello_world_test.py │ │ ├── zephyr_philosophers_test.py │ │ ├── zephyr_synchronization_test.py │ │ └── zephyr_tests.py │ ├── dhrystone │ ├── CMakeLists.txt │ ├── dhrystone.mk │ └── src │ │ ├── dhrystone.c │ │ ├── dhrystone.h │ │ ├── dhrystone_main.c │ │ └── util.h │ ├── fwrisc_tests.mk │ ├── tests.F │ └── unit │ ├── arith_add.S │ ├── arith_addi.S │ ├── arith_addi_neg.S │ ├── arith_and.S │ ├── arith_andi.S │ ├── arith_or.S │ ├── arith_ori.S │ ├── arith_sll.S │ ├── arith_slli.S │ ├── arith_slt_f.S │ ├── arith_slt_t_neg.S │ ├── arith_slt_t_pos.S │ ├── arith_slti_f.S │ ├── arith_slti_t.S │ ├── arith_sltu_t.S │ ├── arith_sra.S │ ├── arith_srai.S │ ├── arith_srl.S │ ├── arith_srli.S │ ├── arith_sub.S │ ├── arith_xor.S │ ├── arith_xori.S │ ├── branch_beq_f_back.S │ ├── branch_beq_f_fwd.S │ ├── branch_beq_t_back.S │ ├── branch_beq_t_fwd.S │ ├── branch_bge_eq_t_neg.S │ ├── branch_bge_eq_t_pos.S │ ├── branch_bge_gt_t_neg.S │ ├── branch_bge_gt_t_pos.S │ ├── branch_blt_t_neg.S │ ├── branch_blt_t_pos.S │ ├── branch_bltu_t_neg.S │ ├── branch_bltu_t_pos.S │ ├── branch_bne_f_back.S │ ├── branch_bne_f_fwd.S │ ├── branch_bne_t_back.S │ ├── branch_bne_t_fwd.S │ ├── exception_bne.S │ ├── exception_dep_x.S │ ├── exception_j.S │ ├── exception_jalr.S │ ├── exception_lw.S │ ├── jump_j.S │ ├── jump_jal.S │ ├── jump_jalr.S │ ├── jump_jalr_off_neg.S │ ├── jump_jalr_off_pos.S │ ├── ldst_lb.S │ ├── ldst_lb_s.S │ ├── ldst_lb_u.S │ ├── ldst_lbu_s.S │ ├── ldst_lh_s.S │ ├── ldst_lh_u.S │ ├── ldst_lhu_s.S │ ├── ldst_lw.S │ ├── ldst_sb_lw.S │ ├── ldst_sh_lw.S │ ├── ldst_sw_lw.S │ ├── long_loop.S │ ├── lui.S │ ├── system_csrc.S │ ├── system_csrr.S │ ├── system_csrs.S │ ├── system_csrsi.S │ ├── system_csrw.S │ ├── system_csrw_csrr.S │ ├── system_ecall.S │ ├── system_eret.S │ ├── unit.ld │ └── unit_header.h ├── fwrisc_rv32imc ├── fwrisc.F ├── sim │ ├── .simscripts │ ├── scripts │ │ ├── Makefile │ │ ├── embedded.mk │ │ ├── mk_instr_tests.sh │ │ ├── status.sh │ │ ├── vlog.f │ │ ├── vlog_hdl.f │ │ ├── vlog_hdl_ms.f │ │ ├── vlog_hvl.f │ │ ├── vlog_hvl_ms.f │ │ ├── vlog_ms.f │ │ └── vlog_vl-pyhpi_hdl.f │ ├── testlists │ │ ├── fwrisc_riscv_all_tests.tl │ │ ├── fwrisc_riscv_compliance_tests.tl │ │ ├── fwrisc_riscv_instr_tests.tl │ │ ├── fwrisc_riscv_ripe_tests.tl │ │ └── fwrisc_riscv_unit_tests.f │ └── tests │ │ ├── fwrisc_instr_tests_arith_add.f │ │ ├── fwrisc_instr_tests_arith_addi.f │ │ ├── fwrisc_instr_tests_arith_addi_neg.f │ │ ├── fwrisc_instr_tests_arith_and.f │ │ ├── fwrisc_instr_tests_arith_andi.f │ │ ├── fwrisc_instr_tests_arith_or.f │ │ ├── fwrisc_instr_tests_arith_ori.f │ │ ├── fwrisc_instr_tests_arith_sll.f │ │ ├── fwrisc_instr_tests_arith_slli.f │ │ ├── fwrisc_instr_tests_arith_slt_f.f │ │ ├── fwrisc_instr_tests_arith_slt_t_neg.f │ │ ├── fwrisc_instr_tests_arith_slt_t_pos.f │ │ ├── fwrisc_instr_tests_arith_slti_f.f │ │ ├── fwrisc_instr_tests_arith_slti_t.f │ │ ├── fwrisc_instr_tests_arith_sltu_t.f │ │ ├── fwrisc_instr_tests_arith_sra.f │ │ ├── fwrisc_instr_tests_arith_srai.f │ │ ├── fwrisc_instr_tests_arith_srl.f │ │ ├── fwrisc_instr_tests_arith_srli.f │ │ ├── fwrisc_instr_tests_arith_sub.f │ │ ├── fwrisc_instr_tests_arith_xor.f │ │ ├── fwrisc_instr_tests_arith_xori.f │ │ ├── fwrisc_instr_tests_branch_beq_f_back.f │ │ ├── fwrisc_instr_tests_branch_beq_f_fwd.f │ │ ├── fwrisc_instr_tests_branch_beq_t_back.f │ │ ├── fwrisc_instr_tests_branch_beq_t_fwd.f │ │ ├── fwrisc_instr_tests_branch_bge_eq_t_neg.f │ │ ├── fwrisc_instr_tests_branch_bge_eq_t_pos.f │ │ ├── fwrisc_instr_tests_branch_bge_gt_t_neg.f │ │ ├── fwrisc_instr_tests_branch_bge_gt_t_pos.f │ │ ├── fwrisc_instr_tests_branch_blt_t_neg.f │ │ ├── fwrisc_instr_tests_branch_blt_t_pos.f │ │ ├── fwrisc_instr_tests_branch_bltu_t_neg.f │ │ ├── fwrisc_instr_tests_branch_bltu_t_pos.f │ │ ├── fwrisc_instr_tests_branch_bne_f_back.f │ │ ├── fwrisc_instr_tests_branch_bne_f_fwd.f │ │ ├── fwrisc_instr_tests_branch_bne_t_back.f │ │ ├── fwrisc_instr_tests_branch_bne_t_fwd.f │ │ ├── fwrisc_instr_tests_counters_cycle.f │ │ ├── fwrisc_instr_tests_exception_bne.f │ │ ├── fwrisc_instr_tests_exception_dep_x.f │ │ ├── fwrisc_instr_tests_exception_j.f │ │ ├── fwrisc_instr_tests_exception_jalr.f │ │ ├── fwrisc_instr_tests_exception_lw.f │ │ ├── fwrisc_instr_tests_jump_j.f │ │ ├── fwrisc_instr_tests_jump_jal.f │ │ ├── fwrisc_instr_tests_jump_jalr.f │ │ ├── fwrisc_instr_tests_jump_jalr_off_neg.f │ │ ├── fwrisc_instr_tests_jump_jalr_off_pos.f │ │ ├── fwrisc_instr_tests_ldst_lb.f │ │ ├── fwrisc_instr_tests_ldst_lb_s.f │ │ ├── fwrisc_instr_tests_ldst_lb_u.f │ │ ├── fwrisc_instr_tests_ldst_lbu_s.f │ │ ├── fwrisc_instr_tests_ldst_lh_s.f │ │ ├── fwrisc_instr_tests_ldst_lh_u.f │ │ ├── fwrisc_instr_tests_ldst_lhu_s.f │ │ ├── fwrisc_instr_tests_ldst_lw.f │ │ ├── fwrisc_instr_tests_ldst_sb_lw.f │ │ ├── fwrisc_instr_tests_ldst_sh_lw.f │ │ ├── fwrisc_instr_tests_ldst_sw_lw.f │ │ ├── fwrisc_instr_tests_long_loop.f │ │ ├── fwrisc_instr_tests_lui.f │ │ ├── fwrisc_instr_tests_system_csrc.f │ │ ├── fwrisc_instr_tests_system_csrr.f │ │ ├── fwrisc_instr_tests_system_csrs.f │ │ ├── fwrisc_instr_tests_system_csrsi.f │ │ ├── fwrisc_instr_tests_system_csrw.f │ │ ├── fwrisc_instr_tests_system_csrw_csrr.f │ │ ├── fwrisc_instr_tests_system_ecall.f │ │ ├── fwrisc_instr_tests_system_eret.f │ │ ├── fwrisc_ripe_1.f │ │ ├── fwrisc_ripe_2.f │ │ ├── fwrisc_ripe_3.f │ │ ├── fwrisc_ripe_4.f │ │ ├── fwrisc_ripe_5.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-ADD-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-ADDI-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-AND-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-ANDI-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-AUIPC-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-BEQ-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-BGE-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-BGEU-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-BLT-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-BLTU-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-BNE-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-CSRRC-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-CSRRCI-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-CSRRS-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-CSRRSI-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-CSRRW-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-CSRRWI-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-DELAY_SLOTS-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-EBREAK-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-ECALL-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-ENDIANESS-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-FENCE.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-IO.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-JAL-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-JALR-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-LB-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-LBU-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-LH-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-LHU-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-LUI-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-LW-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-MISALIGN_JMP-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-MISALIGN_LDST-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-NOP-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-OR-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-ORI-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-RF_size-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-RF_width-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-RF_x0-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-SB-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-SH-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-SLL-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-SLLI-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-SLT-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-SLTI-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-SLTIU-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-SLTU-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-SRA-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-SRAI-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-SRL-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-SRLI-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-SUB-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-SW-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-XOR-01.f │ │ ├── fwrisc_riscv_compliance_rv32i_I-XORI-01.f │ │ ├── fwrisc_zephyr_dhrystone.f │ │ ├── fwrisc_zephyr_hello_world.f │ │ ├── fwrisc_zephyr_philosophers.f │ │ └── fwrisc_zephyr_synchronization.f ├── tb │ ├── fwrisc_tb_hdl.sv │ ├── fwrisc_tb_hvl.sv │ ├── tb.F │ └── vl │ │ ├── fwrisc_tb_hdl.cpp │ │ ├── fwrisc_tb_hdl.h │ │ └── fwrisc_tb_vl.mk └── tests │ ├── cpp │ ├── ElfDataReader.cpp │ ├── ElfDataReader.h │ ├── ElfFileReader.cpp │ ├── ElfFileReader.h │ ├── ElfSymtabReader.cpp │ ├── ElfSymtabReader.h │ ├── fwrisc_ctest_base.cpp │ ├── fwrisc_ctest_base.h │ ├── fwrisc_instr_tests.cpp │ ├── fwrisc_instr_tests.h │ ├── fwrisc_instr_tests_counters.cpp │ ├── fwrisc_instr_tests_counters.h │ ├── fwrisc_perf_tests.cpp │ ├── fwrisc_perf_tests.h │ ├── fwrisc_ripe_tests.cpp │ ├── fwrisc_ripe_tests.h │ ├── fwrisc_zephyr_tests.cpp │ ├── fwrisc_zephyr_tests.h │ ├── riscv_compliance_tests.cpp │ └── riscv_compliance_tests.h │ ├── dhrystone │ ├── CMakeLists.txt │ ├── dhrystone.mk │ └── src │ │ ├── dhrystone.c │ │ ├── dhrystone.h │ │ ├── dhrystone_main.c │ │ └── util.h │ ├── fwrisc_tests.mk │ ├── pyfv-hpi │ └── fwrisc_tests │ │ ├── __init__.py │ │ ├── base.py │ │ ├── instr.py │ │ ├── riscv_compliance.py │ │ └── zephyr.py │ ├── tests.F │ ├── unit │ ├── arith_add.S │ ├── arith_addi.S │ ├── arith_addi_neg.S │ ├── arith_and.S │ ├── arith_andi.S │ ├── arith_or.S │ ├── arith_ori.S │ ├── arith_sll.S │ ├── arith_slli.S │ ├── arith_slt_f.S │ ├── arith_slt_t_neg.S │ ├── arith_slt_t_pos.S │ ├── arith_slti_f.S │ ├── arith_slti_t.S │ ├── arith_sltu_t.S │ ├── arith_sra.S │ ├── arith_srai.S │ ├── arith_srl.S │ ├── arith_srli.S │ ├── arith_sub.S │ ├── arith_xor.S │ ├── arith_xori.S │ ├── branch_beq_f_back.S │ ├── branch_beq_f_fwd.S │ ├── branch_beq_t_back.S │ ├── branch_beq_t_fwd.S │ ├── branch_bge_eq_t_neg.S │ ├── branch_bge_eq_t_pos.S │ ├── branch_bge_gt_t_neg.S │ ├── branch_bge_gt_t_pos.S │ ├── branch_blt_t_neg.S │ ├── branch_blt_t_pos.S │ ├── branch_bltu_t_neg.S │ ├── branch_bltu_t_pos.S │ ├── branch_bne_f_back.S │ ├── branch_bne_f_fwd.S │ ├── branch_bne_t_back.S │ ├── branch_bne_t_fwd.S │ ├── exception_bne.S │ ├── exception_dep_x.S │ ├── exception_j.S │ ├── exception_jalr.S │ ├── exception_lw.S │ ├── jump_j.S │ ├── jump_jal.S │ ├── jump_jalr.S │ ├── jump_jalr_off_neg.S │ ├── jump_jalr_off_pos.S │ ├── ldst_lb.S │ ├── ldst_lb_s.S │ ├── ldst_lb_u.S │ ├── ldst_lbu_s.S │ ├── ldst_lh_s.S │ ├── ldst_lh_u.S │ ├── ldst_lhu_s.S │ ├── ldst_lw.S │ ├── ldst_sb_lw.S │ ├── ldst_sh_lw.S │ ├── ldst_sw_lw.S │ ├── long_loop.S │ ├── lui.S │ ├── system_csrc.S │ ├── system_csrr.S │ ├── system_csrs.S │ ├── system_csrsi.S │ ├── system_csrw.S │ ├── system_csrw_csrr.S │ ├── system_ecall.S │ ├── system_eret.S │ ├── unit.ld │ └── unit_header.h │ └── uvm │ ├── elf_symtab_reader.svh │ ├── fwrisc_instr_test.svh │ ├── fwrisc_riscv_compliance_tests.svh │ ├── fwrisc_test_base.svh │ └── fwrisc_tests_pkg.sv ├── fwrisc_rv32imc_fpga ├── sim │ ├── .simscripts │ ├── mk_testlist.sh │ ├── scripts │ │ ├── Makefile │ │ ├── embedded.mk │ │ ├── mk_instr_tests.sh │ │ ├── status.sh │ │ ├── vlog_hdl.f │ │ └── vlog_hvl.f │ ├── testlists │ │ ├── fwrisc_riscv_compliance_tests.tl │ │ └── fwrisc_riscv_unit_tests.f │ └── tests │ │ ├── fwrisc_fpga_led_flash.f │ │ ├── fwrisc_fpga_memtest.f │ │ └── fwrisc_fpga_zephyr_hello_world.f ├── stdout.log ├── tb │ ├── fwrisc_fpga_tb_hdl.sv │ ├── tb.F │ └── vl │ │ ├── fwrisc_fpga_tb_hdl.cpp │ │ ├── fwrisc_fpga_tb_hdl.h │ │ └── fwrisc_fpga_tb_vl.mk └── tests │ ├── fwrisc_fpga_tests.cpp │ ├── fwrisc_fpga_tests.h │ ├── fwrisc_fpga_tests.mk │ └── sw │ ├── baremetal.ld │ ├── fwrisc_fpga_tests_sw.mk │ ├── led_flash.S │ └── memtest.S ├── fwrisc_tracer_bfm ├── fwrisc_tracer_bfm.bid ├── fwrisc_tracer_bfm.sv ├── fwrisc_tracer_bfm_api.svh ├── fwrisc_tracer_bfm_api_pkg.sv ├── gvm │ ├── fwrisc_tracer_bfm.cpp │ ├── fwrisc_tracer_bfm.h │ ├── fwrisc_tracer_bfm.mk │ ├── fwrisc_tracer_bfm_if.h │ └── fwrisc_tracer_bfm_rsp_if.h ├── pyfv-hpi │ └── fwrisc_tracer_bfm │ │ ├── __init__.py │ │ ├── __pycache__ │ │ ├── __init__.cpython-36.pyc │ │ └── fwrisc_tracer_bfm.cpython-36.pyc │ │ └── fwrisc_tracer_bfm.py ├── rv32_tracer.f └── src │ └── fwrisc_tracer_bfm │ ├── __init__.py │ ├── fwrisc_tracer_bfm.py │ ├── fwrisc_tracer_bfm_if.py │ ├── fwrisc_tracer_signal_bfm.py │ └── hdl │ └── fwrisc_tracer_bfm.v ├── sve.F ├── testlists └── fwrisc.py └── ve.F /.gitignore: -------------------------------------------------------------------------------- 1 | 2 | packages/ 3 | rundir 4 | 5 | -------------------------------------------------------------------------------- /doc/fwrisc_diagram.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Featherweight-IP/fwrisc/0e21466336c9d611c2b465dcb0de04572b6ebbcf/doc/fwrisc_diagram.png -------------------------------------------------------------------------------- /doc/fwrisc_formal_testbench_diagram.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Featherweight-IP/fwrisc/0e21466336c9d611c2b465dcb0de04572b6ebbcf/doc/fwrisc_formal_testbench_diagram.png -------------------------------------------------------------------------------- /doc/fwrisc_testbench_diagram.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Featherweight-IP/fwrisc/0e21466336c9d611c2b465dcb0de04572b6ebbcf/doc/fwrisc_testbench_diagram.png -------------------------------------------------------------------------------- /doc/imgs/Philosophers.gif: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Featherweight-IP/fwrisc/0e21466336c9d611c2b465dcb0de04572b6ebbcf/doc/imgs/Philosophers.gif -------------------------------------------------------------------------------- /doc/imgs/csrrc.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Featherweight-IP/fwrisc/0e21466336c9d611c2b465dcb0de04572b6ebbcf/doc/imgs/csrrc.png -------------------------------------------------------------------------------- /doc/imgs/csrrs.pmg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Featherweight-IP/fwrisc/0e21466336c9d611c2b465dcb0de04572b6ebbcf/doc/imgs/csrrs.pmg -------------------------------------------------------------------------------- /doc/imgs/csrrs.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Featherweight-IP/fwrisc/0e21466336c9d611c2b465dcb0de04572b6ebbcf/doc/imgs/csrrs.png -------------------------------------------------------------------------------- /doc/imgs/csrrw.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Featherweight-IP/fwrisc/0e21466336c9d611c2b465dcb0de04572b6ebbcf/doc/imgs/csrrw.png -------------------------------------------------------------------------------- /doc/imgs/fwrisc_state_machine.epgz: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Featherweight-IP/fwrisc/0e21466336c9d611c2b465dcb0de04572b6ebbcf/doc/imgs/fwrisc_state_machine.epgz -------------------------------------------------------------------------------- /doc/imgs/unit_testbench.epgz: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Featherweight-IP/fwrisc/0e21466336c9d611c2b465dcb0de04572b6ebbcf/doc/imgs/unit_testbench.epgz -------------------------------------------------------------------------------- /doc/imgs/unit_testbench.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Featherweight-IP/fwrisc/0e21466336c9d611c2b465dcb0de04572b6ebbcf/doc/imgs/unit_testbench.png -------------------------------------------------------------------------------- /doc/imgs/unit_testbench_crop.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Featherweight-IP/fwrisc/0e21466336c9d611c2b465dcb0de04572b6ebbcf/doc/imgs/unit_testbench_crop.png -------------------------------------------------------------------------------- /etc/ivpm.info: -------------------------------------------------------------------------------- 1 | 2 | name=fwrisc 3 | version=1.0.0 4 | rootvar=FWRISC 5 | 6 | -------------------------------------------------------------------------------- /requirements.txt: -------------------------------------------------------------------------------- 1 | 2 | pyelftools 3 | pyyaml 4 | vlsim 5 | cocotb 6 | pybfms 7 | pybfms_rv 8 | pybfms_generic_sram 9 | -e git+https://github.com/pybfms/mem_bfms_core.git#egg=mem_bfms_core 10 | -e git+https://github.com/fvutils/fltools.git#egg=fltools 11 | 12 | 13 | -------------------------------------------------------------------------------- /soc/fwrisc_soc.f: -------------------------------------------------------------------------------- 1 | 2 | ${FWRISC}/soc/fwrisc_fpga_top.sv 3 | -------------------------------------------------------------------------------- /sve.F: -------------------------------------------------------------------------------- 1 | //*************************************************************************** 2 | //* sve.F 3 | //*************************************************************************** 4 | 5 | // List file paths and processing directives here 6 | -F ./rtl/sve.F 7 | -F ./ve/ve.F 8 | 9 | 10 | 11 | -------------------------------------------------------------------------------- /sve_top.F: -------------------------------------------------------------------------------- 1 | //*************************************************************************** 2 | //* sve.F 3 | //*************************************************************************** 4 | 5 | // List file paths and processing directives here 6 | -F ./packages/sve.F 7 | -F ./sve.F 8 | 9 | 10 | 11 | 12 | -------------------------------------------------------------------------------- /sw/defs_rules.mk: -------------------------------------------------------------------------------- 1 | 2 | FWRISC_SWDIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST)))) 3 | 4 | ifneq (1,$(RULES)) 5 | ifeq (,$(findstring $(FWRISC_SWDIR),$(MKDV_INCLUDED_DEFS))) 6 | MKDV_INCLUDED_DEFS += $(FWRISC_SWDIR) 7 | ZEPHYR_MODULES += $(FWRISC_SWDIR)/fwrisc 8 | endif 9 | 10 | else # Rules 11 | 12 | endif 13 | -------------------------------------------------------------------------------- /sw/fwrisc/dts/bindings/fwrisc.yaml: -------------------------------------------------------------------------------- 1 | 2 | description: Featherweight IP RISC-V processor 3 | 4 | compatible: "fwrisc" 5 | 6 | include: [base.yaml] 7 | 8 | properties: 9 | "#address-cells": 10 | const: 1 11 | 12 | "#size-cells": 13 | const: 0 14 | 15 | -------------------------------------------------------------------------------- /synth/microsemi/.gitignore: -------------------------------------------------------------------------------- 1 | libero/ 2 | -------------------------------------------------------------------------------- /synth/microsemi/sw/led_flash/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | 2 | cmake_minimum_required(VERSION 3.8.2) 3 | 4 | include($ENV{ZEPHYR_BASE}/cmake/app/boilerplate.cmake NO_POLICY_SCOPE) 5 | project(dhrystone) 6 | 7 | target_sources(app PRIVATE src/led_flash.c) 8 | 9 | set(CMAKE_C_FLAGS "${CMAKE_C_FLAGS} -Wno-implicit-int") 10 | 11 | -------------------------------------------------------------------------------- /synth/microsemi/sw/led_flash/src/led_flash.c: -------------------------------------------------------------------------------- 1 | 2 | #include 3 | 4 | int main(void) { 5 | volatile uint32_t *led = (volatile uint32_t)0xC0000000; 6 | uint32_t count = 0; 7 | 8 | 9 | while (1) { 10 | *led = (count >> 16); 11 | count++; 12 | } 13 | 14 | return 0; 15 | } 16 | 17 | -------------------------------------------------------------------------------- /synth/microsemi/synplify/fwrisc/fwrisc_system_op.svh: -------------------------------------------------------------------------------- 1 | 2 | parameter [3:0] 3 | OP_TYPE_ECALL = 1'd0, 4 | OP_TYPE_EBREAK = (OP_TYPE_ECALL + 1'd1), 5 | OP_TYPE_ERET = (OP_TYPE_EBREAK + 1'd1) 6 | // TODO: OP_TYPE_WFI 7 | ; 8 | 9 | -------------------------------------------------------------------------------- /ve/fwrisc_decode_formal/formal/testlists/fwrisc_decode_formal_all.f: -------------------------------------------------------------------------------- 1 | 2 | 3 | tests/fwrisc_decode_formal_i32_btype.f 4 | tests/fwrisc_decode_formal_i32_itype.f 5 | tests/fwrisc_decode_formal_i32_lui.f 6 | tests/fwrisc_decode_formal_i32_rtype.f 7 | -------------------------------------------------------------------------------- /ve/fwrisc_decode_formal/formal/tests/fwrisc_decode_formal_all_sims.py: -------------------------------------------------------------------------------- 1 | 2 | import fwrisc_decode_formal_tests 3 | 4 | 5 | def suite(): 6 | print("suite: " + str(fwrisc_decode_formal_tests)) 7 | pass 8 | -------------------------------------------------------------------------------- /ve/fwrisc_decode_formal/formal/tests/fwrisc_decode_formal_i32_btype.f: -------------------------------------------------------------------------------- 1 | 2 | 3 | +MODE=cover +DEPTH=64 4 | +CHECKER=fwrisc_decode_formal_i32_btype_checker 5 | -------------------------------------------------------------------------------- /ve/fwrisc_decode_formal/formal/tests/fwrisc_decode_formal_i32_itype.f: -------------------------------------------------------------------------------- 1 | 2 | 3 | +MODE=cover +DEPTH=64 4 | +CHECKER=fwrisc_decode_formal_i32_itype_checker 5 | -------------------------------------------------------------------------------- /ve/fwrisc_decode_formal/formal/tests/fwrisc_decode_formal_i32_lui.f: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | +CHECKER=fwrisc_decode_formal_i32_lui_checker 5 | -------------------------------------------------------------------------------- /ve/fwrisc_decode_formal/formal/tests/fwrisc_decode_formal_i32_rtype.f: -------------------------------------------------------------------------------- 1 | 2 | 3 | +MODE=cover +DEPTH=64 4 | +CHECKER=fwrisc_decode_formal_i32_rtype_checker 5 | -------------------------------------------------------------------------------- /ve/fwrisc_decode_formal/tb/fwrisc_decode_formal_smoke_checker.sv: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | module fwrisc_decode_formal_checker( 5 | // TODO: fill in port list 6 | ); 7 | 8 | endmodule 9 | -------------------------------------------------------------------------------- /ve/fwrisc_exec_formal/formal/testlists/fwrisc_exec_formal_all.f: -------------------------------------------------------------------------------- 1 | 2 | tests/fwrisc_exec_formal_arith.f 3 | tests/fwrisc_exec_formal_branch.f 4 | tests/fwrisc_exec_formal_jump.f 5 | tests/fwrisc_exec_formal_csr.f 6 | tests/fwrisc_exec_formal_mem.f 7 | tests/fwrisc_exec_formal_mds.f 8 | 9 | -------------------------------------------------------------------------------- /ve/fwrisc_exec_formal/formal/tests/fwrisc_exec_formal_arith.f: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | +CHECKER=fwrisc_exec_formal_arith_checker 5 | +MODE=cover 6 | 7 | -------------------------------------------------------------------------------- /ve/fwrisc_exec_formal/formal/tests/fwrisc_exec_formal_branch.f: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | +CHECKER=fwrisc_exec_formal_branch_checker 5 | +MODE=cover 6 | +DEPTH=32 7 | -------------------------------------------------------------------------------- /ve/fwrisc_exec_formal/formal/tests/fwrisc_exec_formal_call.f: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | +CHECKER=fwrisc_exec_formal_call_checker 5 | +MODE=cover 6 | +DEPTH=64 7 | 8 | -------------------------------------------------------------------------------- /ve/fwrisc_exec_formal/formal/tests/fwrisc_exec_formal_csr.f: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | +CHECKER=fwrisc_exec_formal_csr_checker 5 | +MODE=cover 6 | +DEPTH=32 7 | 8 | -------------------------------------------------------------------------------- /ve/fwrisc_exec_formal/formal/tests/fwrisc_exec_formal_jump.f: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | +CHECKER=fwrisc_exec_formal_jump_checker 5 | +MODE=cover 6 | +DEPTH=32 7 | 8 | -------------------------------------------------------------------------------- /ve/fwrisc_exec_formal/formal/tests/fwrisc_exec_formal_mds.f: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | +CHECKER=fwrisc_exec_formal_mds_checker 5 | +MODE=cover 6 | +DEPTH=64 7 | 8 | -------------------------------------------------------------------------------- /ve/fwrisc_exec_formal/formal/tests/fwrisc_exec_formal_mem.f: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | +CHECKER=fwrisc_exec_formal_mem_checker 5 | +MODE=cover 6 | +DEPTH=32 7 | 8 | -------------------------------------------------------------------------------- /ve/fwrisc_exec_formal/formal/tests/fwrisc_exec_formal_smoke.f: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | +CHECKER=fwrisc_exec_formal_smoke_checker 5 | -------------------------------------------------------------------------------- /ve/fwrisc_exec_formal/sve.F: -------------------------------------------------------------------------------- 1 | 2 | +incdir+./tb 3 | ./tb/fwrisc_exec_formal_tb.sv 4 | ./tests/fwrisc_exec_formal_arith_test.sv 5 | ./tests/fwrisc_exec_formal_branch_test.sv 6 | ./tests/fwrisc_exec_formal_jump_test.sv 7 | ./tests/fwrisc_exec_formal_smoke_test.sv 8 | 9 | -------------------------------------------------------------------------------- /ve/fwrisc_exec_formal/tb/fwrisc_exec_formal_defines.svh: -------------------------------------------------------------------------------- 1 | 2 | `ifdef FORMAL 3 | `define assert(x) assert(x) 4 | `define cover(x) cover(x) 5 | `define anyseq $anyseq 6 | `define anyconst $anyconst 7 | `else 8 | `define assert(x) 9 | `define cover(x) 10 | `define anyseq $urandom 11 | `define anyconst $urandom 12 | `endif -------------------------------------------------------------------------------- /ve/fwrisc_fetch_formal/formal/tests/fwrisc_fetch_formal_seq16.f: -------------------------------------------------------------------------------- 1 | 2 | 3 | +CHECKER=fwrisc_fetch_formal_smoke_checker 4 | +MODE=cover 5 | +DEPTH=64 6 | 7 | -------------------------------------------------------------------------------- /ve/fwrisc_fetch_formal/formal/tests/fwrisc_fetch_formal_seq32.f: -------------------------------------------------------------------------------- 1 | 2 | 3 | +CHECKER=fwrisc_fetch_formal_smoke_checker 4 | +MODE=cover 5 | +DEPTH=64 6 | 7 | -------------------------------------------------------------------------------- /ve/fwrisc_fetch_formal/formal/tests/fwrisc_fetch_formal_seqmix.f: -------------------------------------------------------------------------------- 1 | 2 | 3 | +CHECKER=fwrisc_fetch_formal_seqmix_checker 4 | +MODE=cover 5 | +DEPTH=128 6 | 7 | -------------------------------------------------------------------------------- /ve/fwrisc_fetch_formal/formal/tests/fwrisc_fetch_formal_smoke.f: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | +CHECKER=fwrisc_fetch_formal_smoke_checker 5 | -------------------------------------------------------------------------------- /ve/fwrisc_fetch_formal/tb/fwrisc_fetch_formal_defines.svh: -------------------------------------------------------------------------------- 1 | 2 | `ifdef FORMAL 3 | `define assert(x) assert(x) 4 | `define cover(x) cover(x) 5 | `define anyseq $anyseq 6 | `define anyconst $anyconst 7 | `else 8 | `define assert(x) 9 | `define cover(x) 10 | `define anyseq $urandom 11 | `define anyconst $urandom 12 | `endif -------------------------------------------------------------------------------- /ve/fwrisc_fetch_formal/tests/fwrisc_fetch_formal_smoke_test.sv: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | module fwrisc_fetch_formal_test( 5 | // TODO: specify portlist 6 | ); 7 | 8 | 9 | endmodule -------------------------------------------------------------------------------- /ve/fwrisc_formal/sim/tests/fwrisc_formal_add_i.f: -------------------------------------------------------------------------------- 1 | 2 | +INSTRUCTION_CHECKER=fwrisc_formal_arith_checker 3 | 4 | -------------------------------------------------------------------------------- /ve/fwrisc_formal/sim/tests/fwrisc_formal_add_r.f: -------------------------------------------------------------------------------- 1 | 2 | +INSTRUCTION_CHECKER=fwrisc_formal_arith_checker 3 | 4 | -------------------------------------------------------------------------------- /ve/fwrisc_formal/sim/tests/fwrisc_formal_and_r.f: -------------------------------------------------------------------------------- 1 | 2 | +INSTRUCTION_CHECKER=fwrisc_formal_arith_checker 3 | 4 | -------------------------------------------------------------------------------- /ve/fwrisc_formal/sim/tests/fwrisc_formal_auipc.f: -------------------------------------------------------------------------------- 1 | 2 | +INSTRUCTION_CHECKER=fwrisc_formal_arith_checker 3 | 4 | -------------------------------------------------------------------------------- /ve/fwrisc_formal/sim/tests/fwrisc_formal_jal.f: -------------------------------------------------------------------------------- 1 | 2 | +INSTRUCTION_CHECKER=fwrisc_formal_jump_checker 3 | +DEPTH=20 4 | 5 | -------------------------------------------------------------------------------- /ve/fwrisc_formal/sim/tests/fwrisc_formal_jalr.f: -------------------------------------------------------------------------------- 1 | 2 | +INSTRUCTION_CHECKER=fwrisc_formal_jump_checker 3 | +DEPTH=20 4 | 5 | -------------------------------------------------------------------------------- /ve/fwrisc_formal/sim/tests/fwrisc_formal_ld.f: -------------------------------------------------------------------------------- 1 | 2 | +INSTRUCTION_CHECKER=fwrisc_formal_ldst_checker 3 | 4 | -------------------------------------------------------------------------------- /ve/fwrisc_formal/sim/tests/fwrisc_formal_lui.f: -------------------------------------------------------------------------------- 1 | 2 | +INSTRUCTION_CHECKER=fwrisc_formal_arith_checker 3 | 4 | -------------------------------------------------------------------------------- /ve/fwrisc_formal/sim/tests/fwrisc_formal_or_i.f: -------------------------------------------------------------------------------- 1 | 2 | +INSTRUCTION_CHECKER=fwrisc_formal_arith_checker 3 | 4 | -------------------------------------------------------------------------------- /ve/fwrisc_formal/sim/tests/fwrisc_formal_or_r.f: -------------------------------------------------------------------------------- 1 | 2 | +INSTRUCTION_CHECKER=fwrisc_formal_arith_checker 3 | 4 | -------------------------------------------------------------------------------- /ve/fwrisc_formal/sim/tests/fwrisc_formal_sll_i.f: -------------------------------------------------------------------------------- 1 | 2 | +INSTRUCTION_CHECKER=fwrisc_formal_arith_checker 3 | +STEPS=64 4 | 5 | -------------------------------------------------------------------------------- /ve/fwrisc_formal/sim/tests/fwrisc_formal_sll_r.f: -------------------------------------------------------------------------------- 1 | 2 | +INSTRUCTION_CHECKER=fwrisc_formal_arith_checker 3 | +STEPS=64 4 | 5 | -------------------------------------------------------------------------------- /ve/fwrisc_formal/sim/tests/fwrisc_formal_slt_i.f: -------------------------------------------------------------------------------- 1 | 2 | +INSTRUCTION_CHECKER=fwrisc_formal_arith_checker 3 | 4 | -------------------------------------------------------------------------------- /ve/fwrisc_formal/sim/tests/fwrisc_formal_slt_r.f: -------------------------------------------------------------------------------- 1 | 2 | +INSTRUCTION_CHECKER=fwrisc_formal_arith_checker 3 | 4 | -------------------------------------------------------------------------------- /ve/fwrisc_formal/sim/tests/fwrisc_formal_sltu_i.f: -------------------------------------------------------------------------------- 1 | 2 | +INSTRUCTION_CHECKER=fwrisc_formal_arith_checker 3 | 4 | -------------------------------------------------------------------------------- /ve/fwrisc_formal/sim/tests/fwrisc_formal_sltu_r.f: -------------------------------------------------------------------------------- 1 | 2 | +INSTRUCTION_CHECKER=fwrisc_formal_arith_checker 3 | 4 | -------------------------------------------------------------------------------- /ve/fwrisc_formal/sim/tests/fwrisc_formal_srl_r.f: -------------------------------------------------------------------------------- 1 | 2 | +INSTRUCTION_CHECKER=fwrisc_formal_arith_checker 3 | 4 | -------------------------------------------------------------------------------- /ve/fwrisc_formal/sim/tests/fwrisc_formal_sub_r.f: -------------------------------------------------------------------------------- 1 | 2 | +INSTRUCTION_CHECKER=fwrisc_formal_arith_checker 3 | 4 | -------------------------------------------------------------------------------- /ve/fwrisc_formal/sim/tests/fwrisc_formal_xor_i.f: -------------------------------------------------------------------------------- 1 | 2 | +INSTRUCTION_CHECKER=fwrisc_formal_arith_checker 3 | 4 | -------------------------------------------------------------------------------- /ve/fwrisc_formal/sim/tests/fwrisc_formal_xor_r.f: -------------------------------------------------------------------------------- 1 | 2 | +INSTRUCTION_CHECKER=fwrisc_formal_arith_checker 3 | 4 | -------------------------------------------------------------------------------- /ve/fwrisc_formal/tests/fwrisc_formal_add_i.svh: -------------------------------------------------------------------------------- 1 | 2 | `include "fwrisc_formal_opcode_defines.svh" 3 | 4 | `itype_add(idata, $anyconst, $anyconst, $anyconst); -------------------------------------------------------------------------------- /ve/fwrisc_formal/tests/fwrisc_formal_add_r.svh: -------------------------------------------------------------------------------- 1 | 2 | `include "fwrisc_formal_opcode_defines.svh" 3 | 4 | `rtype_add(idata, $anyconst, $anyconst, $anyconst); -------------------------------------------------------------------------------- /ve/fwrisc_formal/tests/fwrisc_formal_and_r.svh: -------------------------------------------------------------------------------- 1 | 2 | `include "fwrisc_formal_opcode_defines.svh" 3 | 4 | `rtype_and(idata, $anyconst, $anyconst, $anyconst); -------------------------------------------------------------------------------- /ve/fwrisc_formal/tests/fwrisc_formal_auipc.svh: -------------------------------------------------------------------------------- 1 | 2 | `include "fwrisc_formal_opcode_defines.svh" 3 | 4 | `utype_auipc(idata, $anyconst, $anyconst); -------------------------------------------------------------------------------- /ve/fwrisc_formal/tests/fwrisc_formal_jal.svh: -------------------------------------------------------------------------------- 1 | 2 | `include "fwrisc_formal_opcode_defines.svh" 3 | 4 | `jal(idata, $anyconst, $anyconst); 5 | 6 | -------------------------------------------------------------------------------- /ve/fwrisc_formal/tests/fwrisc_formal_jalr.svh: -------------------------------------------------------------------------------- 1 | 2 | `include "fwrisc_formal_opcode_defines.svh" 3 | 4 | `jalr(idata, $anyconst, $anyconst, $anyconst); 5 | // `jal(idata, 4, $anyconst); -------------------------------------------------------------------------------- /ve/fwrisc_formal/tests/fwrisc_formal_ld.svh: -------------------------------------------------------------------------------- 1 | 2 | `include "fwrisc_formal_opcode_defines.svh" 3 | 4 | `utype_lui(idata, $anyconst, $anyconst); -------------------------------------------------------------------------------- /ve/fwrisc_formal/tests/fwrisc_formal_lui.svh: -------------------------------------------------------------------------------- 1 | 2 | `include "fwrisc_formal_opcode_defines.svh" 3 | 4 | `utype_lui(idata, $anyconst, $anyconst); -------------------------------------------------------------------------------- /ve/fwrisc_formal/tests/fwrisc_formal_or_i.svh: -------------------------------------------------------------------------------- 1 | 2 | `include "fwrisc_formal_opcode_defines.svh" 3 | 4 | `itype_or(idata, $anyconst, $anyconst, $anyconst); -------------------------------------------------------------------------------- /ve/fwrisc_formal/tests/fwrisc_formal_or_r.svh: -------------------------------------------------------------------------------- 1 | 2 | `include "fwrisc_formal_opcode_defines.svh" 3 | 4 | `rtype_or(idata, $anyconst, $anyconst, $anyconst); -------------------------------------------------------------------------------- /ve/fwrisc_formal/tests/fwrisc_formal_sll_i.svh: -------------------------------------------------------------------------------- 1 | 2 | `include "fwrisc_formal_opcode_defines.svh" 3 | 4 | `itype_sll(idata, $anyconst, $anyconst, $anyconst); -------------------------------------------------------------------------------- /ve/fwrisc_formal/tests/fwrisc_formal_sll_r.svh: -------------------------------------------------------------------------------- 1 | 2 | `include "fwrisc_formal_opcode_defines.svh" 3 | 4 | `rtype_sll(idata, $anyconst, $anyconst, $anyconst); -------------------------------------------------------------------------------- /ve/fwrisc_formal/tests/fwrisc_formal_slt_i.svh: -------------------------------------------------------------------------------- 1 | 2 | `include "fwrisc_formal_opcode_defines.svh" 3 | 4 | `itype_slt(idata, $anyconst, $anyconst, $anyconst); -------------------------------------------------------------------------------- /ve/fwrisc_formal/tests/fwrisc_formal_slt_r.svh: -------------------------------------------------------------------------------- 1 | 2 | `include "fwrisc_formal_opcode_defines.svh" 3 | 4 | `rtype_slt(idata, $anyconst, $anyconst, $anyconst); -------------------------------------------------------------------------------- /ve/fwrisc_formal/tests/fwrisc_formal_sltu_i.svh: -------------------------------------------------------------------------------- 1 | 2 | `include "fwrisc_formal_opcode_defines.svh" 3 | 4 | `itype_sltu(idata, $anyconst, $anyconst, $anyconst); -------------------------------------------------------------------------------- /ve/fwrisc_formal/tests/fwrisc_formal_sltu_r.svh: -------------------------------------------------------------------------------- 1 | 2 | `include "fwrisc_formal_opcode_defines.svh" 3 | 4 | `rtype_sltu(idata, $anyconst, $anyconst, $anyconst); -------------------------------------------------------------------------------- /ve/fwrisc_formal/tests/fwrisc_formal_sra_r.svh: -------------------------------------------------------------------------------- 1 | 2 | `include "fwrisc_formal_opcode_defines.svh" 3 | 4 | `rtype_sra(idata, $anyconst, $anyconst, $anyconst); -------------------------------------------------------------------------------- /ve/fwrisc_formal/tests/fwrisc_formal_srl_r.svh: -------------------------------------------------------------------------------- 1 | 2 | `include "fwrisc_formal_opcode_defines.svh" 3 | 4 | `rtype_srl(idata, $anyconst, $anyconst, $anyconst); -------------------------------------------------------------------------------- /ve/fwrisc_formal/tests/fwrisc_formal_sub_r.svh: -------------------------------------------------------------------------------- 1 | 2 | `include "fwrisc_formal_opcode_defines.svh" 3 | 4 | `rtype_sub(idata, $anyconst, $anyconst, $anyconst); -------------------------------------------------------------------------------- /ve/fwrisc_formal/tests/fwrisc_formal_xor_i.svh: -------------------------------------------------------------------------------- 1 | 2 | `include "fwrisc_formal_opcode_defines.svh" 3 | 4 | `itype_xor(idata, $anyconst, $anyconst, $anyconst); -------------------------------------------------------------------------------- /ve/fwrisc_formal/tests/fwrisc_formal_xor_r.svh: -------------------------------------------------------------------------------- 1 | 2 | `include "fwrisc_formal_opcode_defines.svh" 3 | 4 | `rtype_xor(idata, $anyconst, $anyconst, $anyconst); -------------------------------------------------------------------------------- /ve/fwrisc_mem_formal/formal/testlists/fwrisc_mem_all.f: -------------------------------------------------------------------------------- 1 | 2 | 3 | tests/fwrisc_mem_smoke.f 4 | 5 | -------------------------------------------------------------------------------- /ve/fwrisc_mem_formal/formal/tests/fwrisc_mem_smoke.f: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | +CHECKER=fwrisc_mem_smoke_checker 5 | +MODE=cover 6 | 7 | -------------------------------------------------------------------------------- /ve/fwrisc_mul_div_shift_formal/sim/tests/fwrisc_mul_div_shift_formal_mul.f: -------------------------------------------------------------------------------- 1 | 2 | +CHECKER=fwrisc_mul_div_shift_formal_mul_checker 3 | 4 | -------------------------------------------------------------------------------- /ve/fwrisc_mul_div_shift_formal/sim/tests/fwrisc_mul_div_shift_formal_mulh.f: -------------------------------------------------------------------------------- 1 | 2 | +CHECKER=fwrisc_mul_div_shift_formal_mul_checker 3 | 4 | -------------------------------------------------------------------------------- /ve/fwrisc_mul_div_shift_formal/sim/tests/fwrisc_mul_div_shift_formal_muls.f: -------------------------------------------------------------------------------- 1 | 2 | +CHECKER=fwrisc_mul_div_shift_formal_mul_checker 3 | 4 | -------------------------------------------------------------------------------- /ve/fwrisc_mul_div_shift_formal/sim/tests/fwrisc_mul_div_shift_formal_mulsh.f: -------------------------------------------------------------------------------- 1 | 2 | +CHECKER=fwrisc_mul_div_shift_formal_mul_checker 3 | 4 | -------------------------------------------------------------------------------- /ve/fwrisc_mul_div_shift_formal/sim/tests/fwrisc_mul_div_shift_formal_shl.f: -------------------------------------------------------------------------------- 1 | 2 | +CHECKER=fwrisc_mul_div_shift_formal_shift_checker 3 | 4 | -------------------------------------------------------------------------------- /ve/fwrisc_mul_div_shift_formal/sim/tests/fwrisc_mul_div_shift_formal_sra.f: -------------------------------------------------------------------------------- 1 | 2 | +CHECKER=fwrisc_mul_div_shift_formal_shift_checker 3 | 4 | -------------------------------------------------------------------------------- /ve/fwrisc_mul_div_shift_formal/sim/tests/fwrisc_mul_div_shift_formal_srl.f: -------------------------------------------------------------------------------- 1 | 2 | +CHECKER=fwrisc_mul_div_shift_formal_shift_checker 3 | 4 | -------------------------------------------------------------------------------- /ve/fwrisc_mul_div_shift_formal/tests/fwrisc_mul_div_shift_formal_shl.sv: -------------------------------------------------------------------------------- 1 | 2 | module fwrisc_mul_div_shift_formal_op( 3 | output[31:0] in_a, 4 | output[31:0] in_b, 5 | output[3:0] op 6 | ); 7 | 8 | assign op = 4'b0000; // shl 9 | assign in_a = $anyconst; 10 | assign in_b = $anyconst; 11 | 12 | endmodule 13 | -------------------------------------------------------------------------------- /ve/fwrisc_mul_div_shift_formal/tests/fwrisc_mul_div_shift_formal_sra.sv: -------------------------------------------------------------------------------- 1 | 2 | module fwrisc_mul_div_shift_formal_op( 3 | output[31:0] in_a, 4 | output[31:0] in_b, 5 | output[3:0] op 6 | ); 7 | 8 | assign op = 4'b0010; // sra 9 | assign in_a = $anyconst; 10 | assign in_b = $anyconst; 11 | 12 | endmodule 13 | -------------------------------------------------------------------------------- /ve/fwrisc_mul_div_shift_formal/tests/fwrisc_mul_div_shift_formal_srl.sv: -------------------------------------------------------------------------------- 1 | 2 | module fwrisc_mul_div_shift_formal_op( 3 | output[31:0] in_a, 4 | output[31:0] in_b, 5 | output[3:0] op 6 | ); 7 | 8 | assign op = 4'b0001; // srl 9 | assign in_a = $anyconst; 10 | assign in_b = $anyconst; 11 | 12 | endmodule -------------------------------------------------------------------------------- /ve/fwrisc_rv32e/fwrisc_rv32e.F: -------------------------------------------------------------------------------- 1 | -F ./tb/tb.F 2 | -F ./tests/tests.F 3 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32e/sim/.simscripts: -------------------------------------------------------------------------------- 1 | sim=vl 2 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32e/sim/scripts/vlog.f: -------------------------------------------------------------------------------- 1 | 2 | -f ${FWRISC}/ve/fwrisc/sim/scripts/vlog_hdl.f 3 | -f ${FWRISC}/ve/fwrisc/sim/scripts/vlog_hvl.f 4 | 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32e/sim/scripts/vlog_hdl.f: -------------------------------------------------------------------------------- 1 | 2 | // +define+MINIMIZE_COMM 3 | 4 | -f ${MEMORY_PRIMITIVES}/rtl/sim/sim.f 5 | 6 | -f ${FWRISC}/rtl/fwrisc.f 7 | +incdir+${FWRISC}/ve/fwrisc_tracer_bfm 8 | ${FWRISC}/ve/fwrisc_tracer_bfm/fwrisc_tracer_bfm.sv 9 | -F ${FWRISC}/ve/fwrisc_rv32imc/tb/tb.F 10 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32e/sim/scripts/vlog_hdl_ms.f: -------------------------------------------------------------------------------- 1 | 2 | -f ${MEMORY_PRIMITIVES}/rtl/sim/sim.f 3 | 4 | -f ${FWRISC}/rtl/fwrisc.f 5 | ${FWRISC}/ve/fwrisc_tracer_bfm/fwrisc_tracer_bfm_api_pkg.sv 6 | ${FWRISC}/ve/fwrisc_tracer_bfm/fwrisc_tracer_bfm.sv 7 | -F ${FWRISC}/ve/fwrisc/tb/tb.F 8 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32e/sim/scripts/vlog_hvl.f: -------------------------------------------------------------------------------- 1 | 2 | ${PACKAGES_DIR}/googletest-hdl/src/sv/googletest_sv_pkg.sv 3 | ${FWRISC}/ve/fwrisc/tb/fwrisc_tb_hvl.sv 4 | 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32e/sim/scripts/vlog_hvl_ms.f: -------------------------------------------------------------------------------- 1 | 2 | ${PACKAGES_DIR}/googletest-hdl/src/sv/googletest_sv_pkg.sv 3 | 4 | +incdir+${FWRISC}/ve/fwrisc/tests/uvm 5 | ${FWRISC}/ve/fwrisc/tests/uvm/fwrisc_tests_pkg.sv 6 | ${FWRISC}/ve/fwrisc/tb/fwrisc_tb_hvl.sv 7 | 8 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32e/sim/scripts/vlog_ms.f: -------------------------------------------------------------------------------- 1 | 2 | -f ${FWRISC}/ve/fwrisc/sim/scripts/vlog_hdl_ms.f 3 | -f ${FWRISC}/ve/fwrisc/sim/scripts/vlog_hvl_ms.f 4 | 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32e/sim/testlists/fwrisc_riscv_ripe_tests.tl: -------------------------------------------------------------------------------- 1 | 2 | tests/fwrisc_ripe_1.f 3 | tests/fwrisc_ripe_2.f 4 | tests/fwrisc_ripe_3.f 5 | tests/fwrisc_ripe_4.f 6 | tests/fwrisc_ripe_5.f 7 | 8 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32e/sim/tests/fwrisc_instr_tests_arith_add.f: -------------------------------------------------------------------------------- 1 | +gtest-filter=fwrisc_instr_tests.runtest 2 | +UVM_TESTNAME=fwrisc_instr_test 3 | +hpi.entry=fwrisc_tests.instr_main 4 | +SW_IMAGE=${BUILD_DIR}/esw/unit/arith_add.elf 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32e/sim/tests/fwrisc_instr_tests_arith_addi.f: -------------------------------------------------------------------------------- 1 | +gtest-filter=fwrisc_instr_tests.runtest 2 | +UVM_TESTNAME=fwrisc_instr_test 3 | +hpi.entry=fwrisc_tests.instr_main 4 | +SW_IMAGE=${BUILD_DIR}/esw/unit/arith_addi.elf 5 | 6 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32e/sim/tests/fwrisc_instr_tests_arith_addi_neg.f: -------------------------------------------------------------------------------- 1 | +gtest-filter=fwrisc_instr_tests.runtest 2 | +UVM_TESTNAME=fwrisc_instr_test 3 | +hpi.entry=fwrisc_tests.instr_main 4 | +SW_IMAGE=${BUILD_DIR}/esw/unit/arith_addi_neg.elf 5 | 6 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32e/sim/tests/fwrisc_instr_tests_arith_and.f: -------------------------------------------------------------------------------- 1 | +gtest-filter=fwrisc_instr_tests.runtest 2 | +UVM_TESTNAME=fwrisc_instr_test 3 | +hpi.entry=fwrisc_tests.instr_main 4 | +SW_IMAGE=${BUILD_DIR}/esw/unit/arith_and.elf 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32e/sim/tests/fwrisc_instr_tests_arith_andi.f: -------------------------------------------------------------------------------- 1 | +gtest-filter=fwrisc_instr_tests.runtest 2 | +UVM_TESTNAME=fwrisc_instr_test 3 | +hpi.entry=fwrisc_tests.instr_main 4 | +SW_IMAGE=${BUILD_DIR}/esw/unit/arith_andi.elf 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32e/sim/tests/fwrisc_instr_tests_arith_or.f: -------------------------------------------------------------------------------- 1 | +gtest-filter=fwrisc_instr_tests.runtest 2 | +UVM_TESTNAME=fwrisc_instr_test 3 | +hpi.entry=fwrisc_tests.instr_main 4 | +SW_IMAGE=${BUILD_DIR}/esw/unit/arith_or.elf 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32e/sim/tests/fwrisc_instr_tests_arith_ori.f: -------------------------------------------------------------------------------- 1 | +gtest-filter=fwrisc_instr_tests.runtest 2 | +UVM_TESTNAME=fwrisc_instr_test 3 | +hpi.entry=fwrisc_tests.instr_main 4 | +SW_IMAGE=${BUILD_DIR}/esw/unit/arith_ori.elf 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32e/sim/tests/fwrisc_instr_tests_arith_sll.f: -------------------------------------------------------------------------------- 1 | +gtest-filter=fwrisc_instr_tests.runtest 2 | +UVM_TESTNAME=fwrisc_instr_test 3 | +hpi.entry=fwrisc_tests.instr_main 4 | +SW_IMAGE=${BUILD_DIR}/esw/unit/arith_sll.elf 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32e/sim/tests/fwrisc_instr_tests_arith_slli.f: -------------------------------------------------------------------------------- 1 | +gtest-filter=fwrisc_instr_tests.runtest 2 | +UVM_TESTNAME=fwrisc_instr_test 3 | +hpi.entry=fwrisc_tests.instr_main 4 | +SW_IMAGE=${BUILD_DIR}/esw/unit/arith_slli.elf 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32e/sim/tests/fwrisc_instr_tests_arith_slt_f.f: -------------------------------------------------------------------------------- 1 | +gtest-filter=fwrisc_instr_tests.runtest 2 | +UVM_TESTNAME=fwrisc_instr_test 3 | +hpi.entry=fwrisc_tests.instr_main 4 | +SW_IMAGE=${BUILD_DIR}/esw/unit/arith_slt_f.elf 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32e/sim/tests/fwrisc_instr_tests_arith_slt_t_neg.f: -------------------------------------------------------------------------------- 1 | +gtest-filter=fwrisc_instr_tests.runtest 2 | +UVM_TESTNAME=fwrisc_instr_test 3 | +hpi.entry=fwrisc_tests.instr_main 4 | +SW_IMAGE=${BUILD_DIR}/esw/unit/arith_slt_t_neg.elf 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32e/sim/tests/fwrisc_instr_tests_arith_slt_t_pos.f: -------------------------------------------------------------------------------- 1 | +gtest-filter=fwrisc_instr_tests.runtest 2 | +UVM_TESTNAME=fwrisc_instr_test 3 | +hpi.entry=fwrisc_tests.instr_main 4 | +SW_IMAGE=${BUILD_DIR}/esw/unit/arith_slt_t_pos.elf 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32e/sim/tests/fwrisc_instr_tests_arith_slti_f.f: -------------------------------------------------------------------------------- 1 | +gtest-filter=fwrisc_instr_tests.runtest 2 | +UVM_TESTNAME=fwrisc_instr_test 3 | +hpi.entry=fwrisc_tests.instr_main 4 | +SW_IMAGE=${BUILD_DIR}/esw/unit/arith_slti_f.elf 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32e/sim/tests/fwrisc_instr_tests_arith_slti_t.f: -------------------------------------------------------------------------------- 1 | +gtest-filter=fwrisc_instr_tests.runtest 2 | +UVM_TESTNAME=fwrisc_instr_test 3 | +hpi.entry=fwrisc_tests.instr_main 4 | +SW_IMAGE=${BUILD_DIR}/esw/unit/arith_slti_t.elf 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32e/sim/tests/fwrisc_instr_tests_arith_sltu_t.f: -------------------------------------------------------------------------------- 1 | +gtest-filter=fwrisc_instr_tests.runtest 2 | +UVM_TESTNAME=fwrisc_instr_test 3 | +hpi.entry=fwrisc_tests.instr_main 4 | +SW_IMAGE=${BUILD_DIR}/esw/unit/arith_sltu_t.elf 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32e/sim/tests/fwrisc_instr_tests_arith_sra.f: -------------------------------------------------------------------------------- 1 | +gtest-filter=fwrisc_instr_tests.runtest 2 | +UVM_TESTNAME=fwrisc_instr_test 3 | +hpi.entry=fwrisc_tests.instr_main 4 | +SW_IMAGE=${BUILD_DIR}/esw/unit/arith_sra.elf 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32e/sim/tests/fwrisc_instr_tests_arith_srai.f: -------------------------------------------------------------------------------- 1 | +gtest-filter=fwrisc_instr_tests.runtest 2 | +UVM_TESTNAME=fwrisc_instr_test 3 | +hpi.entry=fwrisc_tests.instr_main 4 | +SW_IMAGE=${BUILD_DIR}/esw/unit/arith_srai.elf 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32e/sim/tests/fwrisc_instr_tests_arith_srl.f: -------------------------------------------------------------------------------- 1 | +gtest-filter=fwrisc_instr_tests.runtest 2 | +UVM_TESTNAME=fwrisc_instr_test 3 | +hpi.entry=fwrisc_tests.instr_main 4 | +SW_IMAGE=${BUILD_DIR}/esw/unit/arith_srl.elf 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32e/sim/tests/fwrisc_instr_tests_arith_srli.f: -------------------------------------------------------------------------------- 1 | +gtest-filter=fwrisc_instr_tests.runtest 2 | +UVM_TESTNAME=fwrisc_instr_test 3 | +hpi.entry=fwrisc_tests.instr_main 4 | +SW_IMAGE=${BUILD_DIR}/esw/unit/arith_srli.elf 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32e/sim/tests/fwrisc_instr_tests_arith_sub.f: -------------------------------------------------------------------------------- 1 | +gtest-filter=fwrisc_instr_tests.runtest 2 | +UVM_TESTNAME=fwrisc_instr_test 3 | +hpi.entry=fwrisc_tests.instr_main 4 | +SW_IMAGE=${BUILD_DIR}/esw/unit/arith_sub.elf 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32e/sim/tests/fwrisc_instr_tests_arith_xor.f: -------------------------------------------------------------------------------- 1 | +gtest-filter=fwrisc_instr_tests.runtest 2 | +UVM_TESTNAME=fwrisc_instr_test 3 | +hpi.entry=fwrisc_tests.instr_main 4 | +SW_IMAGE=${BUILD_DIR}/esw/unit/arith_xor.elf 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32e/sim/tests/fwrisc_instr_tests_arith_xori.f: -------------------------------------------------------------------------------- 1 | +gtest-filter=fwrisc_instr_tests.runtest 2 | +UVM_TESTNAME=fwrisc_instr_test 3 | +hpi.entry=fwrisc_tests.instr_main 4 | +SW_IMAGE=${BUILD_DIR}/esw/unit/arith_xori.elf 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32e/sim/tests/fwrisc_instr_tests_branch_beq_f_back.f: -------------------------------------------------------------------------------- 1 | +gtest-filter=fwrisc_instr_tests.runtest 2 | +UVM_TESTNAME=fwrisc_instr_test 3 | +hpi.entry=fwrisc_tests.instr_main 4 | +SW_IMAGE=${BUILD_DIR}/esw/unit/branch_beq_f_back.elf 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32e/sim/tests/fwrisc_instr_tests_branch_beq_f_fwd.f: -------------------------------------------------------------------------------- 1 | +gtest-filter=fwrisc_instr_tests.runtest 2 | +UVM_TESTNAME=fwrisc_instr_test 3 | +hpi.entry=fwrisc_tests.instr_main 4 | +SW_IMAGE=${BUILD_DIR}/esw/unit/branch_beq_f_fwd.elf 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32e/sim/tests/fwrisc_instr_tests_branch_beq_t_back.f: -------------------------------------------------------------------------------- 1 | +gtest-filter=fwrisc_instr_tests.runtest 2 | +UVM_TESTNAME=fwrisc_instr_test 3 | +hpi.entry=fwrisc_tests.instr_main 4 | +SW_IMAGE=${BUILD_DIR}/esw/unit/branch_beq_t_back.elf 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32e/sim/tests/fwrisc_instr_tests_branch_beq_t_fwd.f: -------------------------------------------------------------------------------- 1 | +gtest-filter=fwrisc_instr_tests.runtest 2 | +UVM_TESTNAME=fwrisc_instr_test 3 | +hpi.entry=fwrisc_tests.instr_main 4 | +SW_IMAGE=${BUILD_DIR}/esw/unit/branch_beq_t_fwd.elf 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32e/sim/tests/fwrisc_instr_tests_branch_bge_eq_t_neg.f: -------------------------------------------------------------------------------- 1 | +gtest-filter=fwrisc_instr_tests.runtest 2 | +UVM_TESTNAME=fwrisc_instr_test 3 | +hpi.entry=fwrisc_tests.instr_main 4 | +SW_IMAGE=${BUILD_DIR}/esw/unit/branch_bge_eq_t_neg.elf 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32e/sim/tests/fwrisc_instr_tests_branch_bge_eq_t_pos.f: -------------------------------------------------------------------------------- 1 | +gtest-filter=fwrisc_instr_tests.runtest 2 | +UVM_TESTNAME=fwrisc_instr_test 3 | +hpi.entry=fwrisc_tests.instr_main 4 | +SW_IMAGE=${BUILD_DIR}/esw/unit/branch_bge_eq_t_pos.elf 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32e/sim/tests/fwrisc_instr_tests_branch_bge_gt_t_neg.f: -------------------------------------------------------------------------------- 1 | +gtest-filter=fwrisc_instr_tests.runtest 2 | +UVM_TESTNAME=fwrisc_instr_test 3 | +hpi.entry=fwrisc_tests.instr_main 4 | +SW_IMAGE=${BUILD_DIR}/esw/unit/branch_bge_gt_t_neg.elf 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32e/sim/tests/fwrisc_instr_tests_branch_bge_gt_t_pos.f: -------------------------------------------------------------------------------- 1 | +gtest-filter=fwrisc_instr_tests.runtest 2 | +UVM_TESTNAME=fwrisc_instr_test 3 | +hpi.entry=fwrisc_tests.instr_main 4 | +SW_IMAGE=${BUILD_DIR}/esw/unit/branch_bge_gt_t_pos.elf 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32e/sim/tests/fwrisc_instr_tests_branch_blt_t_neg.f: -------------------------------------------------------------------------------- 1 | +gtest-filter=fwrisc_instr_tests.runtest 2 | +UVM_TESTNAME=fwrisc_instr_test 3 | +hpi.entry=fwrisc_tests.instr_main 4 | +SW_IMAGE=${BUILD_DIR}/esw/unit/branch_blt_t_neg.elf 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32e/sim/tests/fwrisc_instr_tests_branch_blt_t_pos.f: -------------------------------------------------------------------------------- 1 | +gtest-filter=fwrisc_instr_tests.runtest 2 | +UVM_TESTNAME=fwrisc_instr_test 3 | +hpi.entry=fwrisc_tests.instr_main 4 | +SW_IMAGE=${BUILD_DIR}/esw/unit/branch_blt_t_pos.elf 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32e/sim/tests/fwrisc_instr_tests_branch_bltu_t_neg.f: -------------------------------------------------------------------------------- 1 | +gtest-filter=fwrisc_instr_tests.runtest 2 | +UVM_TESTNAME=fwrisc_instr_test 3 | +hpi.entry=fwrisc_tests.instr_main 4 | +SW_IMAGE=${BUILD_DIR}/esw/unit/branch_bltu_t_neg.elf 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32e/sim/tests/fwrisc_instr_tests_branch_bltu_t_pos.f: -------------------------------------------------------------------------------- 1 | +gtest-filter=fwrisc_instr_tests.runtest 2 | +UVM_TESTNAME=fwrisc_instr_test 3 | +hpi.entry=fwrisc_tests.instr_main 4 | +SW_IMAGE=${BUILD_DIR}/esw/unit/branch_bltu_t_pos.elf 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32e/sim/tests/fwrisc_instr_tests_branch_bne_f_back.f: -------------------------------------------------------------------------------- 1 | +gtest-filter=fwrisc_instr_tests.runtest 2 | +UVM_TESTNAME=fwrisc_instr_test 3 | +hpi.entry=fwrisc_tests.instr_main 4 | +SW_IMAGE=${BUILD_DIR}/esw/unit/branch_bne_f_back.elf 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32e/sim/tests/fwrisc_instr_tests_branch_bne_f_fwd.f: -------------------------------------------------------------------------------- 1 | +gtest-filter=fwrisc_instr_tests.runtest 2 | +UVM_TESTNAME=fwrisc_instr_test 3 | +hpi.entry=fwrisc_tests.instr_main 4 | +SW_IMAGE=${BUILD_DIR}/esw/unit/branch_bne_f_fwd.elf 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32e/sim/tests/fwrisc_instr_tests_branch_bne_t_back.f: -------------------------------------------------------------------------------- 1 | +gtest-filter=fwrisc_instr_tests.runtest 2 | +UVM_TESTNAME=fwrisc_instr_test 3 | +hpi.entry=fwrisc_tests.instr_main 4 | +SW_IMAGE=${BUILD_DIR}/esw/unit/branch_bne_t_back.elf 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32e/sim/tests/fwrisc_instr_tests_branch_bne_t_fwd.f: -------------------------------------------------------------------------------- 1 | +gtest-filter=fwrisc_instr_tests.runtest 2 | +UVM_TESTNAME=fwrisc_instr_test 3 | +hpi.entry=fwrisc_tests.instr_main 4 | +SW_IMAGE=${BUILD_DIR}/esw/unit/branch_bne_t_fwd.elf 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32e/sim/tests/fwrisc_instr_tests_counters_cycle.f: -------------------------------------------------------------------------------- 1 | +gtest-filter=fwrisc_instr_tests_counters.cycle 2 | +UVM_TESTNAME=fwrisc_instr_test 3 | +hpi.entry=fwrisc_tests.instr_main 4 | 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32e/sim/tests/fwrisc_instr_tests_exception_bne.f: -------------------------------------------------------------------------------- 1 | +gtest-filter=fwrisc_instr_tests.runtest 2 | +UVM_TESTNAME=fwrisc_instr_test 3 | +hpi.entry=fwrisc_tests.instr_main 4 | +SW_IMAGE=${BUILD_DIR}/esw/unit/exception_bne.elf 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32e/sim/tests/fwrisc_instr_tests_exception_dep_x.f: -------------------------------------------------------------------------------- 1 | +gtest-filter=fwrisc_instr_tests.runtest 2 | +UVM_TESTNAME=fwrisc_instr_test 3 | +hpi.entry=fwrisc_tests.instr_main 4 | +SW_IMAGE=${BUILD_DIR}/esw/unit/exception_dep_x.elf 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32e/sim/tests/fwrisc_instr_tests_exception_j.f: -------------------------------------------------------------------------------- 1 | +gtest-filter=fwrisc_instr_tests.runtest 2 | +UVM_TESTNAME=fwrisc_instr_test 3 | +hpi.entry=fwrisc_tests.instr_main 4 | +SW_IMAGE=${BUILD_DIR}/esw/unit/branch_beq_t_back.elf 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32e/sim/tests/fwrisc_instr_tests_exception_jalr.f: -------------------------------------------------------------------------------- 1 | +gtest-filter=fwrisc_instr_tests.runtest 2 | +UVM_TESTNAME=fwrisc_instr_test 3 | +hpi.entry=fwrisc_tests.instr_main 4 | +SW_IMAGE=${BUILD_DIR}/esw/unit/exception_jalr.elf 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32e/sim/tests/fwrisc_instr_tests_exception_lw.f: -------------------------------------------------------------------------------- 1 | +gtest-filter=fwrisc_instr_tests.runtest 2 | +UVM_TESTNAME=fwrisc_instr_test 3 | +hpi.entry=fwrisc_tests.instr_main 4 | +SW_IMAGE=${BUILD_DIR}/esw/unit/exception_lw.elf 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32e/sim/tests/fwrisc_instr_tests_jump_j.f: -------------------------------------------------------------------------------- 1 | +gtest-filter=fwrisc_instr_tests.runtest 2 | +UVM_TESTNAME=fwrisc_instr_test 3 | +hpi.entry=fwrisc_tests.instr_main 4 | +SW_IMAGE=${BUILD_DIR}/esw/unit/jump_j.elf 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32e/sim/tests/fwrisc_instr_tests_jump_jal.f: -------------------------------------------------------------------------------- 1 | +gtest-filter=fwrisc_instr_tests.runtest 2 | +UVM_TESTNAME=fwrisc_instr_test 3 | +hpi.entry=fwrisc_tests.instr_main 4 | +SW_IMAGE=${BUILD_DIR}/esw/unit/jump_jal.elf 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32e/sim/tests/fwrisc_instr_tests_jump_jalr.f: -------------------------------------------------------------------------------- 1 | +gtest-filter=fwrisc_instr_tests.runtest 2 | +UVM_TESTNAME=fwrisc_instr_test 3 | +hpi.entry=fwrisc_tests.instr_main 4 | +SW_IMAGE=${BUILD_DIR}/esw/unit/jump_jalr.elf 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32e/sim/tests/fwrisc_instr_tests_jump_jalr_off_neg.f: -------------------------------------------------------------------------------- 1 | +gtest-filter=fwrisc_instr_tests.runtest 2 | +UVM_TESTNAME=fwrisc_instr_test 3 | +hpi.entry=fwrisc_tests.instr_main 4 | +SW_IMAGE=${BUILD_DIR}/esw/unit/jump_jalr_off_neg.elf 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32e/sim/tests/fwrisc_instr_tests_jump_jalr_off_pos.f: -------------------------------------------------------------------------------- 1 | +gtest-filter=fwrisc_instr_tests.runtest 2 | +UVM_TESTNAME=fwrisc_instr_test 3 | +hpi.entry=fwrisc_tests.instr_main 4 | +SW_IMAGE=${BUILD_DIR}/esw/unit/jump_jalr_off_pos.elf 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32e/sim/tests/fwrisc_instr_tests_ldst_lb.f: -------------------------------------------------------------------------------- 1 | +gtest-filter=fwrisc_instr_tests.runtest 2 | +UVM_TESTNAME=fwrisc_instr_test 3 | +hpi.entry=fwrisc_tests.instr_main 4 | +SW_IMAGE=${BUILD_DIR}/esw/unit/ldst_lb.elf 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32e/sim/tests/fwrisc_instr_tests_ldst_lb_s.f: -------------------------------------------------------------------------------- 1 | +gtest-filter=fwrisc_instr_tests.runtest 2 | +UVM_TESTNAME=fwrisc_instr_test 3 | +hpi.entry=fwrisc_tests.instr_main 4 | +SW_IMAGE=${BUILD_DIR}/esw/unit/ldst_lb_s.elf 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32e/sim/tests/fwrisc_instr_tests_ldst_lb_u.f: -------------------------------------------------------------------------------- 1 | +gtest-filter=fwrisc_instr_tests.runtest 2 | +UVM_TESTNAME=fwrisc_instr_test 3 | +hpi.entry=fwrisc_tests.instr_main 4 | +SW_IMAGE=${BUILD_DIR}/esw/unit/ldst_lb_u.elf 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32e/sim/tests/fwrisc_instr_tests_ldst_lbu_s.f: -------------------------------------------------------------------------------- 1 | +gtest-filter=fwrisc_instr_tests.runtest 2 | +UVM_TESTNAME=fwrisc_instr_test 3 | +hpi.entry=fwrisc_tests.instr_main 4 | +SW_IMAGE=${BUILD_DIR}/esw/unit/ldst_lbu_s.elf 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32e/sim/tests/fwrisc_instr_tests_ldst_lh_s.f: -------------------------------------------------------------------------------- 1 | +gtest-filter=fwrisc_instr_tests.runtest 2 | +UVM_TESTNAME=fwrisc_instr_test 3 | +hpi.entry=fwrisc_tests.instr_main 4 | +SW_IMAGE=${BUILD_DIR}/esw/unit/ldst_lh_s.elf 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32e/sim/tests/fwrisc_instr_tests_ldst_lh_u.f: -------------------------------------------------------------------------------- 1 | +gtest-filter=fwrisc_instr_tests.runtest 2 | +UVM_TESTNAME=fwrisc_instr_test 3 | +hpi.entry=fwrisc_tests.instr_main 4 | +SW_IMAGE=${BUILD_DIR}/esw/unit/ldst_lh_u.elf 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32e/sim/tests/fwrisc_instr_tests_ldst_lhu_s.f: -------------------------------------------------------------------------------- 1 | +gtest-filter=fwrisc_instr_tests.runtest 2 | +UVM_TESTNAME=fwrisc_instr_test 3 | +hpi.entry=fwrisc_tests.instr_main 4 | +SW_IMAGE=${BUILD_DIR}/esw/unit/ldst_lhu_s.elf 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32e/sim/tests/fwrisc_instr_tests_ldst_lw.f: -------------------------------------------------------------------------------- 1 | +gtest-filter=fwrisc_instr_tests.runtest 2 | +UVM_TESTNAME=fwrisc_instr_test 3 | +hpi.entry=fwrisc_tests.instr_main 4 | +SW_IMAGE=${BUILD_DIR}/esw/unit/ldst_lw.elf 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32e/sim/tests/fwrisc_instr_tests_ldst_sb_lw.f: -------------------------------------------------------------------------------- 1 | +gtest-filter=fwrisc_instr_tests.runtest 2 | +UVM_TESTNAME=fwrisc_instr_test 3 | +hpi.entry=fwrisc_tests.instr_main 4 | +SW_IMAGE=${BUILD_DIR}/esw/unit/ldst_sb_lw.elf 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32e/sim/tests/fwrisc_instr_tests_ldst_sh_lw.f: -------------------------------------------------------------------------------- 1 | +gtest-filter=fwrisc_instr_tests.runtest 2 | +UVM_TESTNAME=fwrisc_instr_test 3 | +hpi.entry=fwrisc_tests.instr_main 4 | +SW_IMAGE=${BUILD_DIR}/esw/unit/ldst_sh_lw.elf 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32e/sim/tests/fwrisc_instr_tests_ldst_sw_lw.f: -------------------------------------------------------------------------------- 1 | +gtest-filter=fwrisc_instr_tests.runtest 2 | +UVM_TESTNAME=fwrisc_instr_test 3 | +hpi.entry=fwrisc_tests.instr_main 4 | +SW_IMAGE=${BUILD_DIR}/esw/unit/ldst_sw_lw.elf 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32e/sim/tests/fwrisc_instr_tests_long_loop.f: -------------------------------------------------------------------------------- 1 | +gtest-filter=fwrisc_instr_tests.runtest 2 | +UVM_TESTNAME=fwrisc_instr_test 3 | +hpi.entry=fwrisc_tests.instr_main 4 | +SW_IMAGE=${BUILD_DIR}/esw/unit/long_loop.elf 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32e/sim/tests/fwrisc_instr_tests_lui.f: -------------------------------------------------------------------------------- 1 | +gtest-filter=fwrisc_instr_tests.runtest 2 | +UVM_TESTNAME=fwrisc_instr_test 3 | +hpi.entry=fwrisc_tests.instr_main 4 | +SW_IMAGE=${BUILD_DIR}/esw/unit/lui.elf 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32e/sim/tests/fwrisc_instr_tests_system_csrc.f: -------------------------------------------------------------------------------- 1 | +gtest-filter=fwrisc_instr_tests.runtest 2 | +UVM_TESTNAME=fwrisc_instr_test 3 | +hpi.entry=fwrisc_tests.instr_main 4 | +SW_IMAGE=${BUILD_DIR}/esw/unit/system_csrc.elf 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32e/sim/tests/fwrisc_instr_tests_system_csrr.f: -------------------------------------------------------------------------------- 1 | +gtest-filter=fwrisc_instr_tests.runtest 2 | +UVM_TESTNAME=fwrisc_instr_test 3 | +hpi.entry=fwrisc_tests.instr_main 4 | +SW_IMAGE=${BUILD_DIR}/esw/unit/system_csrr.elf 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32e/sim/tests/fwrisc_instr_tests_system_csrs.f: -------------------------------------------------------------------------------- 1 | +gtest-filter=fwrisc_instr_tests.runtest 2 | +UVM_TESTNAME=fwrisc_instr_test 3 | +hpi.entry=fwrisc_tests.instr_main 4 | +SW_IMAGE=${BUILD_DIR}/esw/unit/system_csrs.elf 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32e/sim/tests/fwrisc_instr_tests_system_csrsi.f: -------------------------------------------------------------------------------- 1 | +gtest-filter=fwrisc_instr_tests.runtest 2 | +UVM_TESTNAME=fwrisc_instr_test 3 | +hpi.entry=fwrisc_tests.instr_main 4 | +SW_IMAGE=${BUILD_DIR}/esw/unit/system_csrsi.elf 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32e/sim/tests/fwrisc_instr_tests_system_csrw.f: -------------------------------------------------------------------------------- 1 | +gtest-filter=fwrisc_instr_tests.runtest 2 | +UVM_TESTNAME=fwrisc_instr_test 3 | +hpi.entry=fwrisc_tests.instr_main 4 | +SW_IMAGE=${BUILD_DIR}/esw/unit/system_csrw.elf 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32e/sim/tests/fwrisc_instr_tests_system_csrw_csrr.f: -------------------------------------------------------------------------------- 1 | +gtest-filter=fwrisc_instr_tests.runtest 2 | +UVM_TESTNAME=fwrisc_instr_test 3 | +hpi.entry=fwrisc_tests.instr_main 4 | +SW_IMAGE=${BUILD_DIR}/esw/unit/system_csrw_csrr.elf 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32e/sim/tests/fwrisc_instr_tests_system_ecall.f: -------------------------------------------------------------------------------- 1 | +gtest-filter=fwrisc_instr_tests.runtest 2 | +UVM_TESTNAME=fwrisc_instr_test 3 | +hpi.entry=fwrisc_tests.instr_main 4 | +SW_IMAGE=${BUILD_DIR}/esw/unit/system_ecall.elf 5 | 6 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32e/sim/tests/fwrisc_instr_tests_system_eret.f: -------------------------------------------------------------------------------- 1 | +gtest-filter=fwrisc_instr_tests.runtest 2 | +UVM_TESTNAME=fwrisc_instr_test 3 | +hpi.entry=fwrisc_tests.instr_main 4 | +SW_IMAGE=${BUILD_DIR}/esw/unit/system_eret.elf 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32e/sim/tests/fwrisc_ripe_1.f: -------------------------------------------------------------------------------- 1 | 2 | +SW_IMAGE=${BUILD_DIR}/esw/ripe_1/zephyr/zephyr.elf 3 | // +TRACE_INSTR 4 | // +TRACE_FUNCS 5 | +gtest-filter=fwrisc_ripe_tests.ripe 6 | 7 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32e/sim/tests/fwrisc_ripe_2.f: -------------------------------------------------------------------------------- 1 | 2 | +SW_IMAGE=${BUILD_DIR}/esw/ripe_2/zephyr/zephyr.elf 3 | +gtest-filter=fwrisc_ripe_tests.ripe 4 | 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32e/sim/tests/fwrisc_ripe_3.f: -------------------------------------------------------------------------------- 1 | 2 | +SW_IMAGE=${BUILD_DIR}/esw/ripe_3/zephyr/zephyr.elf 3 | +gtest-filter=fwrisc_ripe_tests.ripe 4 | 5 | 6 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32e/sim/tests/fwrisc_ripe_4.f: -------------------------------------------------------------------------------- 1 | 2 | +SW_IMAGE=${BUILD_DIR}/esw/ripe_4/zephyr/zephyr.elf 3 | +gtest-filter=fwrisc_ripe_tests.ripe 4 | 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32e/sim/tests/fwrisc_ripe_5.f: -------------------------------------------------------------------------------- 1 | 2 | +SW_IMAGE=${BUILD_DIR}/esw/ripe_5/zephyr/zephyr.elf 3 | +gtest-filter=fwrisc_ripe_tests.ripe 4 | 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32e/sim/tests/fwrisc_riscv_compliance_rv32i_I-ADDI-01.f: -------------------------------------------------------------------------------- 1 | +SW_IMAGE=${BUILD_DIR}/esw/I-ADDI-01.elf 2 | +REF_FILE=${FWRISC}/ve/fwrisc/tests/riscv-compliance/riscv-test-suite/rv32i/references/I-ADDI-01.reference_output 3 | +gtest-filter=riscv_compliance_tests.runtest 4 | +hpi.entry=fwrisc_tests.riscv_compliance_main 5 | 6 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32e/sim/tests/fwrisc_riscv_compliance_rv32i_I-AND-01.f: -------------------------------------------------------------------------------- 1 | +SW_IMAGE=${BUILD_DIR}/esw/I-AND-01.elf 2 | +REF_FILE=${FWRISC}/ve/fwrisc/tests/riscv-compliance/riscv-test-suite/rv32i/references/I-AND-01.reference_output 3 | +gtest-filter=riscv_compliance_tests.runtest 4 | +hpi.entry=fwrisc_tests.riscv_compliance_main 5 | 6 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32e/sim/tests/fwrisc_riscv_compliance_rv32i_I-ANDI-01.f: -------------------------------------------------------------------------------- 1 | +SW_IMAGE=${BUILD_DIR}/esw/I-ANDI-01.elf 2 | +REF_FILE=${FWRISC}/ve/fwrisc/tests/riscv-compliance/riscv-test-suite/rv32i/references/I-ANDI-01.reference_output 3 | +gtest-filter=riscv_compliance_tests.runtest 4 | +hpi.entry=fwrisc_tests.riscv_compliance_main 5 | 6 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32e/sim/tests/fwrisc_riscv_compliance_rv32i_I-AUIPC-01.f: -------------------------------------------------------------------------------- 1 | +SW_IMAGE=${BUILD_DIR}/esw/I-AUIPC-01.elf 2 | +REF_FILE=${FWRISC}/ve/fwrisc/tests/riscv-compliance/riscv-test-suite/rv32i/references/I-AUIPC-01.reference_output 3 | +gtest-filter=riscv_compliance_tests.runtest 4 | +hpi.entry=fwrisc_tests.riscv_compliance_main 5 | 6 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32e/sim/tests/fwrisc_riscv_compliance_rv32i_I-BEQ-01.f: -------------------------------------------------------------------------------- 1 | +SW_IMAGE=${BUILD_DIR}/esw/I-BEQ-01.elf 2 | +REF_FILE=${FWRISC}/ve/fwrisc/tests/riscv-compliance/riscv-test-suite/rv32i/references/I-BEQ-01.reference_output 3 | +gtest-filter=riscv_compliance_tests.runtest 4 | +hpi.entry=fwrisc_tests.riscv_compliance_main 5 | 6 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32e/sim/tests/fwrisc_riscv_compliance_rv32i_I-BGE-01.f: -------------------------------------------------------------------------------- 1 | +SW_IMAGE=${BUILD_DIR}/esw/I-BGE-01.elf 2 | +REF_FILE=${FWRISC}/ve/fwrisc/tests/riscv-compliance/riscv-test-suite/rv32i/references/I-BGE-01.reference_output 3 | +gtest-filter=riscv_compliance_tests.runtest 4 | +hpi.entry=fwrisc_tests.riscv_compliance_main 5 | 6 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32e/sim/tests/fwrisc_riscv_compliance_rv32i_I-BGEU-01.f: -------------------------------------------------------------------------------- 1 | +SW_IMAGE=${BUILD_DIR}/esw/I-BGEU-01.elf 2 | +REF_FILE=${FWRISC}/ve/fwrisc/tests/riscv-compliance/riscv-test-suite/rv32i/references/I-BGEU-01.reference_output 3 | +gtest-filter=riscv_compliance_tests.runtest 4 | +hpi.entry=fwrisc_tests.riscv_compliance_main 5 | 6 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32e/sim/tests/fwrisc_riscv_compliance_rv32i_I-BLT-01.f: -------------------------------------------------------------------------------- 1 | +SW_IMAGE=${BUILD_DIR}/esw/I-BLT-01.elf 2 | +REF_FILE=${FWRISC}/ve/fwrisc/tests/riscv-compliance/riscv-test-suite/rv32i/references/I-BLT-01.reference_output 3 | +gtest-filter=riscv_compliance_tests.runtest 4 | +hpi.entry=fwrisc_tests.riscv_compliance_main 5 | 6 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32e/sim/tests/fwrisc_riscv_compliance_rv32i_I-BLTU-01.f: -------------------------------------------------------------------------------- 1 | +SW_IMAGE=${BUILD_DIR}/esw/I-BLTU-01.elf 2 | +REF_FILE=${FWRISC}/ve/fwrisc/tests/riscv-compliance/riscv-test-suite/rv32i/references/I-BLTU-01.reference_output 3 | +gtest-filter=riscv_compliance_tests.runtest 4 | +hpi.entry=fwrisc_tests.riscv_compliance_main 5 | 6 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32e/sim/tests/fwrisc_riscv_compliance_rv32i_I-BNE-01.f: -------------------------------------------------------------------------------- 1 | +SW_IMAGE=${BUILD_DIR}/esw/I-BNE-01.elf 2 | +REF_FILE=${FWRISC}/ve/fwrisc/tests/riscv-compliance/riscv-test-suite/rv32i/references/I-BNE-01.reference_output 3 | +gtest-filter=riscv_compliance_tests.runtest 4 | +hpi.entry=fwrisc_tests.riscv_compliance_main 5 | 6 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32e/sim/tests/fwrisc_riscv_compliance_rv32i_I-CSRRC-01.f: -------------------------------------------------------------------------------- 1 | +SW_IMAGE=${BUILD_DIR}/esw/I-CSRRC-01.elf 2 | +REF_FILE=${FWRISC}/ve/fwrisc/tests/riscv-compliance/riscv-test-suite/rv32i/references/I-CSRRC-01.reference_output 3 | +gtest-filter=riscv_compliance_tests.runtest 4 | +hpi.entry=fwrisc_tests.riscv_compliance_main 5 | 6 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32e/sim/tests/fwrisc_riscv_compliance_rv32i_I-CSRRS-01.f: -------------------------------------------------------------------------------- 1 | +SW_IMAGE=${BUILD_DIR}/esw/I-CSRRS-01.elf 2 | +REF_FILE=${FWRISC}/ve/fwrisc/tests/riscv-compliance/riscv-test-suite/rv32i/references/I-CSRRS-01.reference_output 3 | +gtest-filter=riscv_compliance_tests.runtest 4 | +hpi.entry=fwrisc_tests.riscv_compliance_main 5 | 6 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32e/sim/tests/fwrisc_riscv_compliance_rv32i_I-CSRRW-01.f: -------------------------------------------------------------------------------- 1 | +SW_IMAGE=${BUILD_DIR}/esw/I-CSRRW-01.elf 2 | +REF_FILE=${FWRISC}/ve/fwrisc/tests/riscv-compliance/riscv-test-suite/rv32i/references/I-CSRRW-01.reference_output 3 | +gtest-filter=riscv_compliance_tests.runtest 4 | +hpi.entry=fwrisc_tests.riscv_compliance_main 5 | 6 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32e/sim/tests/fwrisc_riscv_compliance_rv32i_I-ECALL-01.f: -------------------------------------------------------------------------------- 1 | +SW_IMAGE=${BUILD_DIR}/esw/I-ECALL-01.elf 2 | +REF_FILE=${FWRISC}/ve/fwrisc/tests/riscv-compliance/riscv-test-suite/rv32i/references/I-ECALL-01.reference_output 3 | +gtest-filter=riscv_compliance_tests.runtest 4 | +hpi.entry=fwrisc_tests.riscv_compliance_main 5 | 6 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32e/sim/tests/fwrisc_riscv_compliance_rv32i_I-FENCE.f: -------------------------------------------------------------------------------- 1 | +SW_IMAGE=${BUILD_DIR}/esw/I-FENCE.I-01.elf 2 | +REF_FILE=${FWRISC}/ve/fwrisc/tests/riscv-compliance/riscv-test-suite/rv32i/references/I-FENCE.I-01.reference_output 3 | +gtest-filter=riscv_compliance_tests.runtest 4 | +hpi.entry=fwrisc_tests.riscv_compliance_main 5 | 6 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32e/sim/tests/fwrisc_riscv_compliance_rv32i_I-IO.f: -------------------------------------------------------------------------------- 1 | +SW_IMAGE=${BUILD_DIR}/esw/I-IO.elf 2 | +REF_FILE=${FWRISC}/ve/fwrisc/tests/riscv-compliance/riscv-test-suite/rv32i/references/I-IO.reference_output 3 | +gtest-filter=riscv_compliance_tests.runtest 4 | +hpi.entry=fwrisc_tests.riscv_compliance_main 5 | 6 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32e/sim/tests/fwrisc_riscv_compliance_rv32i_I-JAL-01.f: -------------------------------------------------------------------------------- 1 | +SW_IMAGE=${BUILD_DIR}/esw/I-JAL-01.elf 2 | +REF_FILE=${FWRISC}/ve/fwrisc/tests/riscv-compliance/riscv-test-suite/rv32i/references/I-JAL-01.reference_output 3 | +gtest-filter=riscv_compliance_tests.runtest 4 | +hpi.entry=fwrisc_tests.riscv_compliance_main 5 | 6 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32e/sim/tests/fwrisc_riscv_compliance_rv32i_I-JALR-01.f: -------------------------------------------------------------------------------- 1 | +SW_IMAGE=${BUILD_DIR}/esw/I-JALR-01.elf 2 | +REF_FILE=${FWRISC}/ve/fwrisc/tests/riscv-compliance/riscv-test-suite/rv32i/references/I-JALR-01.reference_output 3 | +gtest-filter=riscv_compliance_tests.runtest 4 | +hpi.entry=fwrisc_tests.riscv_compliance_main 5 | 6 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32e/sim/tests/fwrisc_riscv_compliance_rv32i_I-LB-01.f: -------------------------------------------------------------------------------- 1 | +SW_IMAGE=${BUILD_DIR}/esw/I-LB-01.elf 2 | +REF_FILE=${FWRISC}/ve/fwrisc/tests/riscv-compliance/riscv-test-suite/rv32i/references/I-LB-01.reference_output 3 | +gtest-filter=riscv_compliance_tests.runtest 4 | +hpi.entry=fwrisc_tests.riscv_compliance_main 5 | 6 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32e/sim/tests/fwrisc_riscv_compliance_rv32i_I-LBU-01.f: -------------------------------------------------------------------------------- 1 | +SW_IMAGE=${BUILD_DIR}/esw/I-LBU-01.elf 2 | +REF_FILE=${FWRISC}/ve/fwrisc/tests/riscv-compliance/riscv-test-suite/rv32i/references/I-LBU-01.reference_output 3 | +gtest-filter=riscv_compliance_tests.runtest 4 | +hpi.entry=fwrisc_tests.riscv_compliance_main 5 | 6 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32e/sim/tests/fwrisc_riscv_compliance_rv32i_I-LH-01.f: -------------------------------------------------------------------------------- 1 | +SW_IMAGE=${BUILD_DIR}/esw/I-LH-01.elf 2 | +REF_FILE=${FWRISC}/ve/fwrisc/tests/riscv-compliance/riscv-test-suite/rv32i/references/I-LH-01.reference_output 3 | +gtest-filter=riscv_compliance_tests.runtest 4 | +hpi.entry=fwrisc_tests.riscv_compliance_main 5 | 6 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32e/sim/tests/fwrisc_riscv_compliance_rv32i_I-LHU-01.f: -------------------------------------------------------------------------------- 1 | +SW_IMAGE=${BUILD_DIR}/esw/I-LHU-01.elf 2 | +REF_FILE=${FWRISC}/ve/fwrisc/tests/riscv-compliance/riscv-test-suite/rv32i/references/I-LHU-01.reference_output 3 | +gtest-filter=riscv_compliance_tests.runtest 4 | +hpi.entry=fwrisc_tests.riscv_compliance_main 5 | 6 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32e/sim/tests/fwrisc_riscv_compliance_rv32i_I-LUI-01.f: -------------------------------------------------------------------------------- 1 | +SW_IMAGE=${BUILD_DIR}/esw/I-LUI-01.elf 2 | +REF_FILE=${FWRISC}/ve/fwrisc/tests/riscv-compliance/riscv-test-suite/rv32i/references/I-LUI-01.reference_output 3 | +gtest-filter=riscv_compliance_tests.runtest 4 | +hpi.entry=fwrisc_tests.riscv_compliance_main 5 | 6 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32e/sim/tests/fwrisc_riscv_compliance_rv32i_I-LW-01.f: -------------------------------------------------------------------------------- 1 | +SW_IMAGE=${BUILD_DIR}/esw/I-LW-01.elf 2 | +REF_FILE=${FWRISC}/ve/fwrisc/tests/riscv-compliance/riscv-test-suite/rv32i/references/I-LW-01.reference_output 3 | +gtest-filter=riscv_compliance_tests.runtest 4 | +hpi.entry=fwrisc_tests.riscv_compliance_main 5 | 6 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32e/sim/tests/fwrisc_riscv_compliance_rv32i_I-NOP-01.f: -------------------------------------------------------------------------------- 1 | +SW_IMAGE=${BUILD_DIR}/esw/I-NOP-01.elf 2 | +REF_FILE=${FWRISC}/ve/fwrisc/tests/riscv-compliance/riscv-test-suite/rv32i/references/I-NOP-01.reference_output 3 | +gtest-filter=riscv_compliance_tests.runtest 4 | +hpi.entry=fwrisc_tests.riscv_compliance_main 5 | 6 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32e/sim/tests/fwrisc_riscv_compliance_rv32i_I-OR-01.f: -------------------------------------------------------------------------------- 1 | +SW_IMAGE=${BUILD_DIR}/esw/I-OR-01.elf 2 | +REF_FILE=${FWRISC}/ve/fwrisc/tests/riscv-compliance/riscv-test-suite/rv32i/references/I-OR-01.reference_output 3 | +gtest-filter=riscv_compliance_tests.runtest 4 | +hpi.entry=fwrisc_tests.riscv_compliance_main 5 | 6 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32e/sim/tests/fwrisc_riscv_compliance_rv32i_I-ORI-01.f: -------------------------------------------------------------------------------- 1 | +SW_IMAGE=${BUILD_DIR}/esw/I-ORI-01.elf 2 | +REF_FILE=${FWRISC}/ve/fwrisc/tests/riscv-compliance/riscv-test-suite/rv32i/references/I-ORI-01.reference_output 3 | +gtest-filter=riscv_compliance_tests.runtest 4 | +hpi.entry=fwrisc_tests.riscv_compliance_main 5 | 6 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32e/sim/tests/fwrisc_riscv_compliance_rv32i_I-RF_x0-01.f: -------------------------------------------------------------------------------- 1 | +SW_IMAGE=${BUILD_DIR}/esw/I-RF_x0-01.elf 2 | +REF_FILE=${FWRISC}/ve/fwrisc/tests/riscv-compliance/riscv-test-suite/rv32i/references/I-RF_x0-01.reference_output 3 | +gtest-filter=riscv_compliance_tests.runtest 4 | +hpi.entry=fwrisc_tests.riscv_compliance_main 5 | 6 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32e/sim/tests/fwrisc_riscv_compliance_rv32i_I-SB-01.f: -------------------------------------------------------------------------------- 1 | +SW_IMAGE=${BUILD_DIR}/esw/I-SB-01.elf 2 | +REF_FILE=${FWRISC}/ve/fwrisc/tests/riscv-compliance/riscv-test-suite/rv32i/references/I-SB-01.reference_output 3 | +gtest-filter=riscv_compliance_tests.runtest 4 | +hpi.entry=fwrisc_tests.riscv_compliance_main 5 | 6 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32e/sim/tests/fwrisc_riscv_compliance_rv32i_I-SH-01.f: -------------------------------------------------------------------------------- 1 | +SW_IMAGE=${BUILD_DIR}/esw/I-SH-01.elf 2 | +REF_FILE=${FWRISC}/ve/fwrisc/tests/riscv-compliance/riscv-test-suite/rv32i/references/I-SH-01.reference_output 3 | +gtest-filter=riscv_compliance_tests.runtest 4 | +hpi.entry=fwrisc_tests.riscv_compliance_main 5 | 6 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32e/sim/tests/fwrisc_riscv_compliance_rv32i_I-SLL-01.f: -------------------------------------------------------------------------------- 1 | +SW_IMAGE=${BUILD_DIR}/esw/I-SLL-01.elf 2 | +REF_FILE=${FWRISC}/ve/fwrisc/tests/riscv-compliance/riscv-test-suite/rv32i/references/I-SLL-01.reference_output 3 | +gtest-filter=riscv_compliance_tests.runtest 4 | +hpi.entry=fwrisc_tests.riscv_compliance_main 5 | 6 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32e/sim/tests/fwrisc_riscv_compliance_rv32i_I-SLLI-01.f: -------------------------------------------------------------------------------- 1 | +SW_IMAGE=${BUILD_DIR}/esw/I-SLLI-01.elf 2 | +REF_FILE=${FWRISC}/ve/fwrisc/tests/riscv-compliance/riscv-test-suite/rv32i/references/I-SLLI-01.reference_output 3 | +gtest-filter=riscv_compliance_tests.runtest 4 | +hpi.entry=fwrisc_tests.riscv_compliance_main 5 | 6 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32e/sim/tests/fwrisc_riscv_compliance_rv32i_I-SLT-01.f: -------------------------------------------------------------------------------- 1 | +SW_IMAGE=${BUILD_DIR}/esw/I-SLT-01.elf 2 | +REF_FILE=${FWRISC}/ve/fwrisc/tests/riscv-compliance/riscv-test-suite/rv32i/references/I-SLT-01.reference_output 3 | +gtest-filter=riscv_compliance_tests.runtest 4 | +hpi.entry=fwrisc_tests.riscv_compliance_main 5 | 6 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32e/sim/tests/fwrisc_riscv_compliance_rv32i_I-SLTI-01.f: -------------------------------------------------------------------------------- 1 | +SW_IMAGE=${BUILD_DIR}/esw/I-SLTI-01.elf 2 | +REF_FILE=${FWRISC}/ve/fwrisc/tests/riscv-compliance/riscv-test-suite/rv32i/references/I-SLTI-01.reference_output 3 | +gtest-filter=riscv_compliance_tests.runtest 4 | +hpi.entry=fwrisc_tests.riscv_compliance_main 5 | 6 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32e/sim/tests/fwrisc_riscv_compliance_rv32i_I-SLTIU-01.f: -------------------------------------------------------------------------------- 1 | +SW_IMAGE=${BUILD_DIR}/esw/I-SLTIU-01.elf 2 | +REF_FILE=${FWRISC}/ve/fwrisc/tests/riscv-compliance/riscv-test-suite/rv32i/references/I-SLTIU-01.reference_output 3 | +gtest-filter=riscv_compliance_tests.runtest 4 | +hpi.entry=fwrisc_tests.riscv_compliance_main 5 | 6 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32e/sim/tests/fwrisc_riscv_compliance_rv32i_I-SLTU-01.f: -------------------------------------------------------------------------------- 1 | +SW_IMAGE=${BUILD_DIR}/esw/I-SLTU-01.elf 2 | +REF_FILE=${FWRISC}/ve/fwrisc/tests/riscv-compliance/riscv-test-suite/rv32i/references/I-SLTU-01.reference_output 3 | +gtest-filter=riscv_compliance_tests.runtest 4 | +hpi.entry=fwrisc_tests.riscv_compliance_main 5 | 6 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32e/sim/tests/fwrisc_riscv_compliance_rv32i_I-SRA-01.f: -------------------------------------------------------------------------------- 1 | +SW_IMAGE=${BUILD_DIR}/esw/I-SRA-01.elf 2 | +REF_FILE=${FWRISC}/ve/fwrisc/tests/riscv-compliance/riscv-test-suite/rv32i/references/I-SRA-01.reference_output 3 | +gtest-filter=riscv_compliance_tests.runtest 4 | +hpi.entry=fwrisc_tests.riscv_compliance_main 5 | 6 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32e/sim/tests/fwrisc_riscv_compliance_rv32i_I-SRAI-01.f: -------------------------------------------------------------------------------- 1 | +SW_IMAGE=${BUILD_DIR}/esw/I-SRAI-01.elf 2 | +REF_FILE=${FWRISC}/ve/fwrisc/tests/riscv-compliance/riscv-test-suite/rv32i/references/I-SRAI-01.reference_output 3 | +gtest-filter=riscv_compliance_tests.runtest 4 | +hpi.entry=fwrisc_tests.riscv_compliance_main 5 | 6 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32e/sim/tests/fwrisc_riscv_compliance_rv32i_I-SRL-01.f: -------------------------------------------------------------------------------- 1 | +SW_IMAGE=${BUILD_DIR}/esw/I-SRL-01.elf 2 | +REF_FILE=${FWRISC}/ve/fwrisc/tests/riscv-compliance/riscv-test-suite/rv32i/references/I-SRL-01.reference_output 3 | +gtest-filter=riscv_compliance_tests.runtest 4 | +hpi.entry=fwrisc_tests.riscv_compliance_main 5 | 6 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32e/sim/tests/fwrisc_riscv_compliance_rv32i_I-SRLI-01.f: -------------------------------------------------------------------------------- 1 | +SW_IMAGE=${BUILD_DIR}/esw/I-SRLI-01.elf 2 | +REF_FILE=${FWRISC}/ve/fwrisc/tests/riscv-compliance/riscv-test-suite/rv32i/references/I-SRLI-01.reference_output 3 | +gtest-filter=riscv_compliance_tests.runtest 4 | +hpi.entry=fwrisc_tests.riscv_compliance_main 5 | 6 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32e/sim/tests/fwrisc_riscv_compliance_rv32i_I-SUB-01.f: -------------------------------------------------------------------------------- 1 | +SW_IMAGE=${BUILD_DIR}/esw/I-SUB-01.elf 2 | +REF_FILE=${FWRISC}/ve/fwrisc/tests/riscv-compliance/riscv-test-suite/rv32i/references/I-SUB-01.reference_output 3 | +gtest-filter=riscv_compliance_tests.runtest 4 | +hpi.entry=fwrisc_tests.riscv_compliance_main 5 | 6 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32e/sim/tests/fwrisc_riscv_compliance_rv32i_I-SW-01.f: -------------------------------------------------------------------------------- 1 | +SW_IMAGE=${BUILD_DIR}/esw/I-SW-01.elf 2 | +REF_FILE=${FWRISC}/ve/fwrisc/tests/riscv-compliance/riscv-test-suite/rv32i/references/I-SW-01.reference_output 3 | +gtest-filter=riscv_compliance_tests.runtest 4 | +hpi.entry=fwrisc_tests.riscv_compliance_main 5 | 6 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32e/sim/tests/fwrisc_riscv_compliance_rv32i_I-XOR-01.f: -------------------------------------------------------------------------------- 1 | +SW_IMAGE=${BUILD_DIR}/esw/I-XOR-01.elf 2 | +REF_FILE=${FWRISC}/ve/fwrisc/tests/riscv-compliance/riscv-test-suite/rv32i/references/I-XOR-01.reference_output 3 | +gtest-filter=riscv_compliance_tests.runtest 4 | +hpi.entry=fwrisc_tests.riscv_compliance_main 5 | 6 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32e/sim/tests/fwrisc_riscv_compliance_rv32i_I-XORI-01.f: -------------------------------------------------------------------------------- 1 | +SW_IMAGE=${BUILD_DIR}/esw/I-XORI-01.elf 2 | +REF_FILE=${FWRISC}/ve/fwrisc/tests/riscv-compliance/riscv-test-suite/rv32i/references/I-XORI-01.reference_output 3 | +gtest-filter=riscv_compliance_tests.runtest 4 | +hpi.entry=fwrisc_tests.riscv_compliance_main 5 | 6 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32e/sim/tests/fwrisc_zephyr_dhrystone.f: -------------------------------------------------------------------------------- 1 | 2 | +SW_IMAGE=${BUILD_DIR}/esw/zephyr_tests/dhrystone/zephyr/zephyr.elf 3 | +gtest-filter=fwrisc_zephyr_tests.dhrystone 4 | 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32e/sim/tests/fwrisc_zephyr_hello_world.f: -------------------------------------------------------------------------------- 1 | 2 | +SW_IMAGE=${BUILD_DIR}/esw/zephyr/hello_world/zephyr/zephyr.elf 3 | +gtest-filter=fwrisc_zephyr_tests.hello_world 4 | 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32e/sim/tests/fwrisc_zephyr_philosophers.f: -------------------------------------------------------------------------------- 1 | 2 | +SW_IMAGE=${BUILD_DIR}/esw/zephyr/philosophers/zephyr/zephyr.elf 3 | +gtest-filter=fwrisc_zephyr_tests.philosophers 4 | 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32e/sim/tests/fwrisc_zephyr_synchronization.f: -------------------------------------------------------------------------------- 1 | 2 | +SW_IMAGE=${BUILD_DIR}/esw/zephyr/synchronization/zephyr/zephyr.elf 3 | +gtest-filter=fwrisc_zephyr_tests.synchronization 4 | 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32e/tb/tb.F: -------------------------------------------------------------------------------- 1 | 2 | +incdir+. 3 | ./fwrisc_rv32i_tb_hdl.sv 4 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32e/tests/dhrystone/dhrystone.mk: -------------------------------------------------------------------------------- 1 | 2 | FWRISC_TESTS_DHRYSTONE_DIR := $(dir $(lastword $(MAKEFILE_LIST))) 3 | 4 | ifneq (1,$(RULES)) 5 | 6 | SRC_DIRS += $(FWRISC_TESTS_DHRYSTONE_DIR) 7 | 8 | else # Rules 9 | 10 | endif 11 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32e/tests/pyfv-hpi/fwrisc_tests/__init__.py: -------------------------------------------------------------------------------- 1 | 2 | print("Hello from fwrisc_tests") 3 | 4 | from fwrisc_tests.instr import instr_main 5 | from fwrisc_tests.riscv_compliance import riscv_compliance_main -------------------------------------------------------------------------------- /ve/fwrisc_rv32e/tests/pyfv-hpi/fwrisc_tests/base.py: -------------------------------------------------------------------------------- 1 | ''' 2 | Created on Jun 1, 2019 3 | 4 | @author: ballance 5 | ''' 6 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32e/tests/tests.F: -------------------------------------------------------------------------------- 1 | +incdir+. 2 | ./fwrisc_tests_pkg.sv 3 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32e/tests/unit/arith_add.S: -------------------------------------------------------------------------------- 1 | 2 | #include "unit_header.h" 3 | 4 | entry: 5 | li x1, 5 6 | li x2, 6 7 | add x3, x1, x2 8 | j done 9 | 10 | 11 | start_expected: 12 | .word 1, 5 13 | .word 2, 6 14 | .word 3, 11 15 | end_expected: 16 | 17 | 18 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32e/tests/unit/arith_addi.S: -------------------------------------------------------------------------------- 1 | 2 | #include "unit_header.h" 3 | 4 | entry: 5 | li x1, 5 6 | add x3, x1, 6 7 | j done 8 | 9 | // Expected value for registers 10 | start_expected: 11 | .word 1, 5 12 | .word 3, 11 13 | end_expected: 14 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32e/tests/unit/arith_addi_neg.S: -------------------------------------------------------------------------------- 1 | 2 | #include "unit_header.h" 3 | 4 | entry: 5 | li x1, 5 6 | add x3, x1, -1 7 | j done 8 | 9 | // Expected value for registers 10 | start_expected: 11 | .word 1, 5 12 | .word 3, 4 13 | end_expected: 14 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32e/tests/unit/arith_and.S: -------------------------------------------------------------------------------- 1 | 2 | #include "unit_header.h" 3 | 4 | entry: 5 | li x1, 5 6 | li x2, 6 7 | and x3, x1, x2 8 | j done 9 | 10 | 11 | start_expected: 12 | .word 1, 5 13 | .word 2, 6 14 | .word 3, 4 15 | end_expected: 16 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32e/tests/unit/arith_andi.S: -------------------------------------------------------------------------------- 1 | 2 | #include "unit_header.h" 3 | 4 | entry: 5 | li x1, 5 6 | andi x3, x1, 4 7 | j done 8 | 9 | start_expected: 10 | .word 1, 5 11 | .word 3, 4 // 5&6==4 12 | end_expected: 13 | 14 | 15 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32e/tests/unit/arith_or.S: -------------------------------------------------------------------------------- 1 | 2 | #include "unit_header.h" 3 | 4 | entry: 5 | li x1, 5 6 | li x2, 6 7 | or x3, x1, x2 8 | j done 9 | 10 | start_expected: 11 | .word 1, 5 12 | .word 2, 6 13 | .word 3, 7 // 5|6==7 14 | end_expected: 15 | 16 | 17 | 18 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32e/tests/unit/arith_ori.S: -------------------------------------------------------------------------------- 1 | 2 | #include "unit_header.h" 3 | 4 | entry: 5 | li x1, 5 6 | ori x3, x1, 6 7 | j done 8 | 9 | 10 | start_expected: 11 | .word 1, 5 12 | .word 3, 7 // 5|6==7 13 | end_expected: 14 | 15 | 16 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32e/tests/unit/arith_sll.S: -------------------------------------------------------------------------------- 1 | 2 | #include "unit_header.h" 3 | 4 | entry: 5 | li x1, 5 6 | li x2, 1 7 | sll x3, x2, x1 8 | j done 9 | 10 | start_expected: 11 | .word 1, 5 12 | .word 2, 1 13 | .word 3, (1 << 5) 14 | end_expected: 15 | 16 | 17 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32e/tests/unit/arith_slli.S: -------------------------------------------------------------------------------- 1 | 2 | #include "unit_header.h" 3 | 4 | entry: 5 | li x1, 1 6 | slli x3, x1, 5 7 | j done 8 | 9 | start_expected: 10 | .word 1, 1 11 | .word 3, (1 << 5) 12 | end_expected: 13 | 14 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32e/tests/unit/arith_slt_f.S: -------------------------------------------------------------------------------- 1 | 2 | #include "unit_header.h" 3 | 4 | entry: 5 | li x1, 5 6 | li x2, 5 7 | slt x3, x1, x2 8 | j done 9 | 10 | 11 | start_expected: 12 | .word 1, 5 13 | .word 2, 5 14 | .word 3, 0 // !(5<5) 15 | end_expected: 16 | 17 | 18 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32e/tests/unit/arith_slt_t_neg.S: -------------------------------------------------------------------------------- 1 | 2 | #include "unit_header.h" 3 | 4 | entry: 5 | li x1, -6 6 | li x2, -5 7 | slt x3, x1, x2 8 | j done 9 | 10 | 11 | start_expected: 12 | .word 1, -6 13 | .word 2, -5 14 | .word 3, 1 // -6 < -5 15 | end_expected: 16 | 17 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32e/tests/unit/arith_slt_t_pos.S: -------------------------------------------------------------------------------- 1 | 2 | #include "unit_header.h" 3 | 4 | entry: 5 | li x1, 5 6 | li x2, 6 7 | slt x3, x1, x2 8 | j done 9 | 10 | start_expected: 11 | .word 1, 5 12 | .word 2, 6 13 | .word 3, 1 // 5 < 6 14 | end_expected: 15 | 16 | 17 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32e/tests/unit/arith_slti_f.S: -------------------------------------------------------------------------------- 1 | 2 | #include "unit_header.h" 3 | 4 | entry: 5 | li x1, 5 6 | slti x3, x1, 4 7 | j done 8 | 9 | 10 | start_expected: 11 | .word 1, 5 12 | .word 3, 0 // !(5<4) 13 | end_expected: 14 | 15 | 16 | 17 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32e/tests/unit/arith_slti_t.S: -------------------------------------------------------------------------------- 1 | 2 | #include "unit_header.h" 3 | 4 | 5 | entry: 6 | li x1, 5 7 | slti x3, x1, 6 8 | j done 9 | 10 | 11 | start_expected: 12 | .word 1, 5 13 | .word 3, 1 // (5<6) 14 | end_expected: 15 | 16 | 17 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32e/tests/unit/arith_sltu_t.S: -------------------------------------------------------------------------------- 1 | 2 | #include "unit_header.h" 3 | 4 | entry: 5 | li x1, 0x80000000 6 | li x2, 0x80000001 7 | sltu x3, x1, x2 8 | j done 9 | 10 | 11 | start_expected: 12 | .word 1, 0x80000000 13 | .word 2, 0x80000001 14 | .word 3, 1 15 | end_expected: 16 | 17 | 18 | 19 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32e/tests/unit/arith_sra.S: -------------------------------------------------------------------------------- 1 | 2 | #include "unit_header.h" 3 | 4 | entry: 5 | li x1, 4 6 | li x2, 0x80000000 7 | sra x3, x2, x1 8 | j done 9 | 10 | 11 | start_expected: 12 | .word 1, 4 13 | .word 2, 0x80000000 14 | .word 3, 0xF8000000 15 | end_expected: 16 | 17 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32e/tests/unit/arith_srai.S: -------------------------------------------------------------------------------- 1 | 2 | #include "unit_header.h" 3 | 4 | entry: 5 | li x2, 0x80000000 6 | srai x3, x2, 4 7 | j done 8 | 9 | 10 | start_expected: 11 | .word 2, 0x80000000 12 | .word 3, 0xF8000000 13 | end_expected: 14 | 15 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32e/tests/unit/arith_srl.S: -------------------------------------------------------------------------------- 1 | 2 | #include "unit_header.h" 3 | 4 | entry: 5 | li x1, 5 6 | li x2, 0x80000000 7 | srl x3, x2, x1 8 | j done 9 | 10 | 11 | start_expected: 12 | .word 1, 5 13 | .word 2, 0x80000000 14 | .word 3, (0x80000000 >> 5) 15 | end_expected: 16 | 17 | 18 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32e/tests/unit/arith_srli.S: -------------------------------------------------------------------------------- 1 | 2 | #include "unit_header.h" 3 | 4 | entry: 5 | li x2, 0x80000000 6 | srli x3, x2, 5 7 | j done 8 | 9 | 10 | start_expected: 11 | .word 2, 0x80000000 12 | .word 3, (0x80000000 >> 5) 13 | end_expected: 14 | 15 | 16 | 17 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32e/tests/unit/arith_sub.S: -------------------------------------------------------------------------------- 1 | 2 | #include "unit_header.h" 3 | 4 | entry: 5 | li x1, 5 6 | li x2, 6 7 | sub x3, x2, x1 8 | j done 9 | 10 | 11 | start_expected: 12 | .word 1, 5 13 | .word 2, 6 14 | .word 3, 1 15 | end_expected: 16 | 17 | 18 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32e/tests/unit/arith_xor.S: -------------------------------------------------------------------------------- 1 | 2 | #include "unit_header.h" 3 | 4 | entry: 5 | li x1, 5 6 | li x2, 6 7 | xor x3, x1, x2 8 | j done 9 | 10 | 11 | start_expected: 12 | .word 1, 5 13 | .word 2, 6 14 | .word 3, 3 15 | end_expected: 16 | 17 | 18 | 19 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32e/tests/unit/arith_xori.S: -------------------------------------------------------------------------------- 1 | 2 | #include "unit_header.h" 3 | 4 | entry: 5 | li x1, 5 6 | xori x3, x1, 6 7 | j done 8 | 9 | 10 | start_expected: 11 | .word 1, 5 12 | .word 3, 3 13 | end_expected: 14 | 15 | 16 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32e/tests/unit/long_loop.S: -------------------------------------------------------------------------------- 1 | 2 | #include "unit_header.h" 3 | 4 | entry: 5 | li x1, 0 6 | li x2, 5000000 7 | 1: 8 | addi x1, x1, 1 9 | bne x1, x2, 1b 10 | j done 11 | 12 | 13 | start_expected: 14 | .word 1, 10000000 15 | .word 2, 10000000 16 | end_expected: 17 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32e/tests/unit/lui.S: -------------------------------------------------------------------------------- 1 | 2 | #include "unit_header.h" 3 | 4 | entry: 5 | lui x1, 5 6 | j done 7 | 8 | // Expected value for registers 9 | start_expected: 10 | .word 1, 0x00005000 11 | end_expected: 12 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32e/tests/unit/system_csrc.S: -------------------------------------------------------------------------------- 1 | 2 | #include "unit_header.h" 3 | 4 | entry: 5 | li x1, 0xf 6 | li x2, 0x1 7 | csrw mtvec, x1 8 | csrrc x1, mtvec, x2 9 | 10 | j done 11 | 12 | 13 | start_expected: 14 | .word 1, 0x0f 15 | .word 2, 0x01 16 | .word 0x2D, 0x0e 17 | end_expected: 18 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32e/tests/unit/system_csrr.S: -------------------------------------------------------------------------------- 1 | 2 | #include "unit_header.h" 3 | 4 | entry: 5 | csrr x1, mcause 6 | j done 7 | 8 | 9 | start_expected: 10 | .word 1, 0 11 | .word (0x30+2), 0 12 | end_expected: 13 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32e/tests/unit/system_csrw.S: -------------------------------------------------------------------------------- 1 | 2 | #include "unit_header.h" 3 | 4 | entry: 5 | li x1, 5 6 | csrw mtvec, x1 7 | csrr x2, mtvec 8 | 9 | j done 10 | 11 | 12 | start_expected: 13 | .word 1, 5 14 | .word 2, 5 15 | .word 0x2d, 5 16 | end_expected: 17 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32e/tests/unit/system_csrw_csrr.S: -------------------------------------------------------------------------------- 1 | 2 | #include "unit_header.h" 3 | 4 | entry: 5 | li x1, 5 6 | csrw medeleg, x1 7 | csrr x2, medeleg 8 | 9 | j done 10 | 11 | 12 | start_expected: 13 | .word 0x01, 5 14 | .word 0x02, 5 15 | .word (0x28+2), 5 16 | end_expected: 17 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32e/tests/unit/unit.ld: -------------------------------------------------------------------------------- 1 | 2 | OUTPUT_ARCH("riscv") 3 | ENTRY(_start) 4 | 5 | SECTIONS 6 | { 7 | . = 0x80000000; 8 | .text.init : { *(.text.init) } 9 | . = ALIGN(0x1000); 10 | _end = .; 11 | } 12 | 13 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32i/fwrisc_rv32i.F: -------------------------------------------------------------------------------- 1 | -F ./tb/tb.F 2 | -F ./tests/tests.F 3 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32i/sim/.simscripts: -------------------------------------------------------------------------------- 1 | sim=vlsim 2 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32i/sim/scripts/vlog.f: -------------------------------------------------------------------------------- 1 | 2 | -f ${FWRISC}/ve/fwrisc/sim/scripts/vlog_hdl.f 3 | -f ${FWRISC}/ve/fwrisc/sim/scripts/vlog_hvl.f 4 | 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32i/sim/scripts/vlog_hdl.f: -------------------------------------------------------------------------------- 1 | 2 | // +define+MINIMIZE_COMM 3 | 4 | -f ${MEMORY_PRIMITIVES}/rtl/sim/sim.f 5 | 6 | -f ${FWRISC}/rtl/fwrisc.f 7 | +incdir+${FWRISC}/ve/fwrisc_tracer_bfm 8 | // ${FWRISC}/ve/fwrisc_tracer_bfm/fwrisc_tracer_bfm.sv 9 | -f ${FWRISC}/ve/fwrisc_rv32i/tb/tb.f 10 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32i/sim/scripts/vlog_hdl_ms.f: -------------------------------------------------------------------------------- 1 | 2 | -f ${MEMORY_PRIMITIVES}/rtl/sim/sim.f 3 | 4 | -f ${FWRISC}/rtl/fwrisc.f 5 | ${FWRISC}/ve/fwrisc_tracer_bfm/fwrisc_tracer_bfm_api_pkg.sv 6 | ${FWRISC}/ve/fwrisc_tracer_bfm/fwrisc_tracer_bfm.sv 7 | -F ${FWRISC}/ve/fwrisc/tb/tb.F 8 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32i/sim/scripts/vlog_hvl.f: -------------------------------------------------------------------------------- 1 | 2 | ${PACKAGES_DIR}/googletest-hdl/src/sv/googletest_sv_pkg.sv 3 | ${FWRISC}/ve/fwrisc/tb/fwrisc_tb_hvl.sv 4 | 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32i/sim/scripts/vlog_hvl_ms.f: -------------------------------------------------------------------------------- 1 | 2 | ${PACKAGES_DIR}/googletest-hdl/src/sv/googletest_sv_pkg.sv 3 | 4 | +incdir+${FWRISC}/ve/fwrisc/tests/uvm 5 | ${FWRISC}/ve/fwrisc/tests/uvm/fwrisc_tests_pkg.sv 6 | ${FWRISC}/ve/fwrisc/tb/fwrisc_tb_hvl.sv 7 | 8 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32i/sim/scripts/vlog_ms.f: -------------------------------------------------------------------------------- 1 | 2 | -f ${FWRISC}/ve/fwrisc/sim/scripts/vlog_hdl_ms.f 3 | -f ${FWRISC}/ve/fwrisc/sim/scripts/vlog_hvl_ms.f 4 | 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32i/sim/testlists/fwrisc_riscv_ripe_tests.tl: -------------------------------------------------------------------------------- 1 | 2 | tests/fwrisc_ripe_1.f 3 | tests/fwrisc_ripe_2.f 4 | tests/fwrisc_ripe_3.f 5 | tests/fwrisc_ripe_4.f 6 | tests/fwrisc_ripe_5.f 7 | 8 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32i/sim/tests/fwrisc_instr_tests_arith_add.f: -------------------------------------------------------------------------------- 1 | +cocotb.module=fwrisc_rv32i_tests.instr_tests 2 | +SW_IMAGE=${BUILD_DIR}/esw/unit/arith_add.elf 3 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32i/sim/tests/fwrisc_instr_tests_arith_addi.f: -------------------------------------------------------------------------------- 1 | +cocotb.module=fwrisc_rv32i_tests.instr_tests 2 | +SW_IMAGE=${BUILD_DIR}/esw/unit/arith_addi.elf 3 | 4 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32i/sim/tests/fwrisc_instr_tests_arith_addi_neg.f: -------------------------------------------------------------------------------- 1 | +cocotb.module=fwrisc_rv32i_tests.instr_tests 2 | +SW_IMAGE=${BUILD_DIR}/esw/unit/arith_addi_neg.elf 3 | 4 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32i/sim/tests/fwrisc_instr_tests_arith_and.f: -------------------------------------------------------------------------------- 1 | +cocotb.module=fwrisc_rv32i_tests.instr_tests 2 | +SW_IMAGE=${BUILD_DIR}/esw/unit/arith_and.elf 3 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32i/sim/tests/fwrisc_instr_tests_arith_andi.f: -------------------------------------------------------------------------------- 1 | +cocotb.module=fwrisc_rv32i_tests.instr_tests 2 | +SW_IMAGE=${BUILD_DIR}/esw/unit/arith_andi.elf 3 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32i/sim/tests/fwrisc_instr_tests_arith_or.f: -------------------------------------------------------------------------------- 1 | +cocotb.module=fwrisc_rv32i_tests.instr_tests 2 | +SW_IMAGE=${BUILD_DIR}/esw/unit/arith_or.elf 3 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32i/sim/tests/fwrisc_instr_tests_arith_ori.f: -------------------------------------------------------------------------------- 1 | +cocotb.module=fwrisc_rv32i_tests.instr_tests 2 | +SW_IMAGE=${BUILD_DIR}/esw/unit/arith_ori.elf 3 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32i/sim/tests/fwrisc_instr_tests_arith_sll.f: -------------------------------------------------------------------------------- 1 | +cocotb.module=fwrisc_rv32i_tests.instr_tests 2 | +SW_IMAGE=${BUILD_DIR}/esw/unit/arith_sll.elf 3 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32i/sim/tests/fwrisc_instr_tests_arith_slli.f: -------------------------------------------------------------------------------- 1 | +cocotb.module=fwrisc_rv32i_tests.instr_tests 2 | +SW_IMAGE=${BUILD_DIR}/esw/unit/arith_slli.elf 3 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32i/sim/tests/fwrisc_instr_tests_arith_slt_f.f: -------------------------------------------------------------------------------- 1 | +cocotb.module=fwrisc_rv32i_tests.instr_tests 2 | +SW_IMAGE=${BUILD_DIR}/esw/unit/arith_slt_f.elf 3 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32i/sim/tests/fwrisc_instr_tests_arith_slt_t_neg.f: -------------------------------------------------------------------------------- 1 | +cocotb.module=fwrisc_rv32i_tests.instr_tests 2 | +SW_IMAGE=${BUILD_DIR}/esw/unit/arith_slt_t_neg.elf 3 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32i/sim/tests/fwrisc_instr_tests_arith_slt_t_pos.f: -------------------------------------------------------------------------------- 1 | +cocotb.module=fwrisc_rv32i_tests.instr_tests 2 | +SW_IMAGE=${BUILD_DIR}/esw/unit/arith_slt_t_pos.elf 3 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32i/sim/tests/fwrisc_instr_tests_arith_slti_f.f: -------------------------------------------------------------------------------- 1 | +cocotb.module=fwrisc_rv32i_tests.instr_tests 2 | +SW_IMAGE=${BUILD_DIR}/esw/unit/arith_slti_f.elf 3 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32i/sim/tests/fwrisc_instr_tests_arith_slti_t.f: -------------------------------------------------------------------------------- 1 | +cocotb.module=fwrisc_rv32i_tests.instr_tests 2 | +SW_IMAGE=${BUILD_DIR}/esw/unit/arith_slti_t.elf 3 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32i/sim/tests/fwrisc_instr_tests_arith_sltu_t.f: -------------------------------------------------------------------------------- 1 | +cocotb.module=fwrisc_rv32i_tests.instr_tests 2 | +SW_IMAGE=${BUILD_DIR}/esw/unit/arith_sltu_t.elf 3 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32i/sim/tests/fwrisc_instr_tests_arith_sra.f: -------------------------------------------------------------------------------- 1 | +cocotb.module=fwrisc_rv32i_tests.instr_tests 2 | +SW_IMAGE=${BUILD_DIR}/esw/unit/arith_sra.elf 3 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32i/sim/tests/fwrisc_instr_tests_arith_srai.f: -------------------------------------------------------------------------------- 1 | +cocotb.module=fwrisc_rv32i_tests.instr_tests 2 | +SW_IMAGE=${BUILD_DIR}/esw/unit/arith_srai.elf 3 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32i/sim/tests/fwrisc_instr_tests_arith_srl.f: -------------------------------------------------------------------------------- 1 | +cocotb.module=fwrisc_rv32i_tests.instr_tests 2 | +SW_IMAGE=${BUILD_DIR}/esw/unit/arith_srl.elf 3 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32i/sim/tests/fwrisc_instr_tests_arith_srli.f: -------------------------------------------------------------------------------- 1 | +cocotb.module=fwrisc_rv32i_tests.instr_tests 2 | +SW_IMAGE=${BUILD_DIR}/esw/unit/arith_srli.elf 3 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32i/sim/tests/fwrisc_instr_tests_arith_sub.f: -------------------------------------------------------------------------------- 1 | +cocotb.module=fwrisc_rv32i_tests.instr_tests 2 | +SW_IMAGE=${BUILD_DIR}/esw/unit/arith_sub.elf 3 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32i/sim/tests/fwrisc_instr_tests_arith_xor.f: -------------------------------------------------------------------------------- 1 | +cocotb.module=fwrisc_rv32i_tests.instr_tests 2 | +SW_IMAGE=${BUILD_DIR}/esw/unit/arith_xor.elf 3 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32i/sim/tests/fwrisc_instr_tests_arith_xori.f: -------------------------------------------------------------------------------- 1 | +cocotb.module=fwrisc_rv32i_tests.instr_tests 2 | +SW_IMAGE=${BUILD_DIR}/esw/unit/arith_xori.elf 3 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32i/sim/tests/fwrisc_instr_tests_branch_beq_f_back.f: -------------------------------------------------------------------------------- 1 | +cocotb.module=fwrisc_rv32i_tests.instr_tests 2 | +SW_IMAGE=${BUILD_DIR}/esw/unit/branch_beq_f_back.elf 3 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32i/sim/tests/fwrisc_instr_tests_branch_beq_f_fwd.f: -------------------------------------------------------------------------------- 1 | +cocotb.module=fwrisc_rv32i_tests.instr_tests 2 | +SW_IMAGE=${BUILD_DIR}/esw/unit/branch_beq_f_fwd.elf 3 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32i/sim/tests/fwrisc_instr_tests_branch_beq_t_back.f: -------------------------------------------------------------------------------- 1 | +cocotb.module=fwrisc_rv32i_tests.instr_tests 2 | +SW_IMAGE=${BUILD_DIR}/esw/unit/branch_beq_t_back.elf 3 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32i/sim/tests/fwrisc_instr_tests_branch_beq_t_fwd.f: -------------------------------------------------------------------------------- 1 | +cocotb.module=fwrisc_rv32i_tests.instr_tests 2 | +SW_IMAGE=${BUILD_DIR}/esw/unit/branch_beq_t_fwd.elf 3 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32i/sim/tests/fwrisc_instr_tests_branch_bge_eq_t_neg.f: -------------------------------------------------------------------------------- 1 | +cocotb.module=fwrisc_rv32i_tests.instr_tests 2 | +SW_IMAGE=${BUILD_DIR}/esw/unit/branch_bge_eq_t_neg.elf 3 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32i/sim/tests/fwrisc_instr_tests_branch_bge_eq_t_pos.f: -------------------------------------------------------------------------------- 1 | +cocotb.module=fwrisc_rv32i_tests.instr_tests 2 | +SW_IMAGE=${BUILD_DIR}/esw/unit/branch_bge_eq_t_pos.elf 3 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32i/sim/tests/fwrisc_instr_tests_branch_bge_gt_t_neg.f: -------------------------------------------------------------------------------- 1 | +cocotb.module=fwrisc_rv32i_tests.instr_tests 2 | +SW_IMAGE=${BUILD_DIR}/esw/unit/branch_bge_gt_t_neg.elf 3 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32i/sim/tests/fwrisc_instr_tests_branch_bge_gt_t_pos.f: -------------------------------------------------------------------------------- 1 | +cocotb.module=fwrisc_rv32i_tests.instr_tests 2 | +SW_IMAGE=${BUILD_DIR}/esw/unit/branch_bge_gt_t_pos.elf 3 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32i/sim/tests/fwrisc_instr_tests_branch_blt_t_neg.f: -------------------------------------------------------------------------------- 1 | +cocotb.module=fwrisc_rv32i_tests.instr_tests 2 | +SW_IMAGE=${BUILD_DIR}/esw/unit/branch_blt_t_neg.elf 3 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32i/sim/tests/fwrisc_instr_tests_branch_blt_t_pos.f: -------------------------------------------------------------------------------- 1 | +cocotb.module=fwrisc_rv32i_tests.instr_tests 2 | +SW_IMAGE=${BUILD_DIR}/esw/unit/branch_blt_t_pos.elf 3 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32i/sim/tests/fwrisc_instr_tests_branch_bltu_t_neg.f: -------------------------------------------------------------------------------- 1 | +cocotb.module=fwrisc_rv32i_tests.instr_tests 2 | +SW_IMAGE=${BUILD_DIR}/esw/unit/branch_bltu_t_neg.elf 3 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32i/sim/tests/fwrisc_instr_tests_branch_bltu_t_pos.f: -------------------------------------------------------------------------------- 1 | +cocotb.module=fwrisc_rv32i_tests.instr_tests 2 | +SW_IMAGE=${BUILD_DIR}/esw/unit/branch_bltu_t_pos.elf 3 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32i/sim/tests/fwrisc_instr_tests_branch_bne_f_back.f: -------------------------------------------------------------------------------- 1 | +cocotb.module=fwrisc_rv32i_tests.instr_tests 2 | +SW_IMAGE=${BUILD_DIR}/esw/unit/branch_bne_f_back.elf 3 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32i/sim/tests/fwrisc_instr_tests_branch_bne_f_fwd.f: -------------------------------------------------------------------------------- 1 | +cocotb.module=fwrisc_rv32i_tests.instr_tests 2 | +SW_IMAGE=${BUILD_DIR}/esw/unit/branch_bne_f_fwd.elf 3 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32i/sim/tests/fwrisc_instr_tests_branch_bne_t_back.f: -------------------------------------------------------------------------------- 1 | +cocotb.module=fwrisc_rv32i_tests.instr_tests 2 | +SW_IMAGE=${BUILD_DIR}/esw/unit/branch_bne_t_back.elf 3 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32i/sim/tests/fwrisc_instr_tests_branch_bne_t_fwd.f: -------------------------------------------------------------------------------- 1 | +cocotb.module=fwrisc_rv32i_tests.instr_tests 2 | +SW_IMAGE=${BUILD_DIR}/esw/unit/branch_bne_t_fwd.elf 3 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32i/sim/tests/fwrisc_instr_tests_counters_cycle.f: -------------------------------------------------------------------------------- 1 | +cocotb.module=fwrisc_rv32i_tests.instr_tests 2 | 3 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32i/sim/tests/fwrisc_instr_tests_exception_bne.f: -------------------------------------------------------------------------------- 1 | +cocotb.module=fwrisc_rv32i_tests.instr_tests 2 | +SW_IMAGE=${BUILD_DIR}/esw/unit/exception_bne.elf 3 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32i/sim/tests/fwrisc_instr_tests_exception_dep_x.f: -------------------------------------------------------------------------------- 1 | +cocotb.module=fwrisc_rv32i_tests.instr_tests 2 | +SW_IMAGE=${BUILD_DIR}/esw/unit/exception_dep_x.elf 3 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32i/sim/tests/fwrisc_instr_tests_exception_j.f: -------------------------------------------------------------------------------- 1 | +cocotb.module=fwrisc_rv32i_tests.instr_tests 2 | +SW_IMAGE=${BUILD_DIR}/esw/unit/branch_beq_t_back.elf 3 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32i/sim/tests/fwrisc_instr_tests_exception_jalr.f: -------------------------------------------------------------------------------- 1 | +cocotb.module=fwrisc_rv32i_tests.instr_tests 2 | +SW_IMAGE=${BUILD_DIR}/esw/unit/exception_jalr.elf 3 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32i/sim/tests/fwrisc_instr_tests_exception_lw.f: -------------------------------------------------------------------------------- 1 | +cocotb.module=fwrisc_rv32i_tests.instr_tests 2 | +SW_IMAGE=${BUILD_DIR}/esw/unit/exception_lw.elf 3 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32i/sim/tests/fwrisc_instr_tests_jump_j.f: -------------------------------------------------------------------------------- 1 | +cocotb.module=fwrisc_rv32i_tests.instr_tests 2 | +SW_IMAGE=${BUILD_DIR}/esw/unit/jump_j.elf 3 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32i/sim/tests/fwrisc_instr_tests_jump_jal.f: -------------------------------------------------------------------------------- 1 | +cocotb.module=fwrisc_rv32i_tests.instr_tests 2 | +SW_IMAGE=${BUILD_DIR}/esw/unit/jump_jal.elf 3 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32i/sim/tests/fwrisc_instr_tests_jump_jalr.f: -------------------------------------------------------------------------------- 1 | +cocotb.module=fwrisc_rv32i_tests.instr_tests 2 | +SW_IMAGE=${BUILD_DIR}/esw/unit/jump_jalr.elf 3 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32i/sim/tests/fwrisc_instr_tests_jump_jalr_off_neg.f: -------------------------------------------------------------------------------- 1 | +cocotb.module=fwrisc_rv32i_tests.instr_tests 2 | +SW_IMAGE=${BUILD_DIR}/esw/unit/jump_jalr_off_neg.elf 3 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32i/sim/tests/fwrisc_instr_tests_jump_jalr_off_pos.f: -------------------------------------------------------------------------------- 1 | +cocotb.module=fwrisc_rv32i_tests.instr_tests 2 | +SW_IMAGE=${BUILD_DIR}/esw/unit/jump_jalr_off_pos.elf 3 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32i/sim/tests/fwrisc_instr_tests_ldst_lb.f: -------------------------------------------------------------------------------- 1 | +cocotb.module=fwrisc_rv32i_tests.instr_tests 2 | +SW_IMAGE=${BUILD_DIR}/esw/unit/ldst_lb.elf 3 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32i/sim/tests/fwrisc_instr_tests_ldst_lb_s.f: -------------------------------------------------------------------------------- 1 | +cocotb.module=fwrisc_rv32i_tests.instr_tests 2 | +SW_IMAGE=${BUILD_DIR}/esw/unit/ldst_lb_s.elf 3 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32i/sim/tests/fwrisc_instr_tests_ldst_lb_u.f: -------------------------------------------------------------------------------- 1 | +cocotb.module=fwrisc_rv32i_tests.instr_tests 2 | +SW_IMAGE=${BUILD_DIR}/esw/unit/ldst_lb_u.elf 3 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32i/sim/tests/fwrisc_instr_tests_ldst_lbu_s.f: -------------------------------------------------------------------------------- 1 | +cocotb.module=fwrisc_rv32i_tests.instr_tests 2 | +SW_IMAGE=${BUILD_DIR}/esw/unit/ldst_lbu_s.elf 3 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32i/sim/tests/fwrisc_instr_tests_ldst_lh_s.f: -------------------------------------------------------------------------------- 1 | +cocotb.module=fwrisc_rv32i_tests.instr_tests 2 | +SW_IMAGE=${BUILD_DIR}/esw/unit/ldst_lh_s.elf 3 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32i/sim/tests/fwrisc_instr_tests_ldst_lh_u.f: -------------------------------------------------------------------------------- 1 | +cocotb.module=fwrisc_rv32i_tests.instr_tests 2 | +SW_IMAGE=${BUILD_DIR}/esw/unit/ldst_lh_u.elf 3 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32i/sim/tests/fwrisc_instr_tests_ldst_lhu_s.f: -------------------------------------------------------------------------------- 1 | +cocotb.module=fwrisc_rv32i_tests.instr_tests 2 | +SW_IMAGE=${BUILD_DIR}/esw/unit/ldst_lhu_s.elf 3 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32i/sim/tests/fwrisc_instr_tests_ldst_lw.f: -------------------------------------------------------------------------------- 1 | +cocotb.module=fwrisc_rv32i_tests.instr_tests 2 | +SW_IMAGE=${BUILD_DIR}/esw/unit/ldst_lw.elf 3 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32i/sim/tests/fwrisc_instr_tests_ldst_sb_lw.f: -------------------------------------------------------------------------------- 1 | +cocotb.module=fwrisc_rv32i_tests.instr_tests 2 | +SW_IMAGE=${BUILD_DIR}/esw/unit/ldst_sb_lw.elf 3 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32i/sim/tests/fwrisc_instr_tests_ldst_sh_lw.f: -------------------------------------------------------------------------------- 1 | +cocotb.module=fwrisc_rv32i_tests.instr_tests 2 | +SW_IMAGE=${BUILD_DIR}/esw/unit/ldst_sh_lw.elf 3 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32i/sim/tests/fwrisc_instr_tests_ldst_sw_lw.f: -------------------------------------------------------------------------------- 1 | +cocotb.module=fwrisc_rv32i_tests.instr_tests 2 | +SW_IMAGE=${BUILD_DIR}/esw/unit/ldst_sw_lw.elf 3 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32i/sim/tests/fwrisc_instr_tests_long_loop.f: -------------------------------------------------------------------------------- 1 | +cocotb.module=fwrisc_rv32i_tests.instr_tests 2 | +SW_IMAGE=${BUILD_DIR}/esw/unit/long_loop.elf 3 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32i/sim/tests/fwrisc_instr_tests_lui.f: -------------------------------------------------------------------------------- 1 | +cocotb.module=fwrisc_rv32i_tests.instr_tests 2 | +SW_IMAGE=${BUILD_DIR}/esw/unit/lui.elf 3 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32i/sim/tests/fwrisc_instr_tests_system_csrc.f: -------------------------------------------------------------------------------- 1 | +cocotb.module=fwrisc_rv32i_tests.instr_tests 2 | +SW_IMAGE=${BUILD_DIR}/esw/unit/system_csrc.elf 3 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32i/sim/tests/fwrisc_instr_tests_system_csrr.f: -------------------------------------------------------------------------------- 1 | +cocotb.module=fwrisc_rv32i_tests.instr_tests 2 | +SW_IMAGE=${BUILD_DIR}/esw/unit/system_csrr.elf 3 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32i/sim/tests/fwrisc_instr_tests_system_csrs.f: -------------------------------------------------------------------------------- 1 | +cocotb.module=fwrisc_rv32i_tests.instr_tests 2 | +SW_IMAGE=${BUILD_DIR}/esw/unit/system_csrs.elf 3 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32i/sim/tests/fwrisc_instr_tests_system_csrsi.f: -------------------------------------------------------------------------------- 1 | +cocotb.module=fwrisc_rv32i_tests.instr_tests 2 | +SW_IMAGE=${BUILD_DIR}/esw/unit/system_csrsi.elf 3 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32i/sim/tests/fwrisc_instr_tests_system_csrw.f: -------------------------------------------------------------------------------- 1 | +cocotb.module=fwrisc_rv32i_tests.instr_tests 2 | +SW_IMAGE=${BUILD_DIR}/esw/unit/system_csrw.elf 3 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32i/sim/tests/fwrisc_instr_tests_system_csrw_csrr.f: -------------------------------------------------------------------------------- 1 | +cocotb.module=fwrisc_rv32i_tests.instr_tests 2 | +SW_IMAGE=${BUILD_DIR}/esw/unit/system_csrw_csrr.elf 3 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32i/sim/tests/fwrisc_instr_tests_system_ecall.f: -------------------------------------------------------------------------------- 1 | +cocotb.module=fwrisc_rv32i_tests.instr_tests 2 | +SW_IMAGE=${BUILD_DIR}/esw/unit/system_ecall.elf 3 | 4 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32i/sim/tests/fwrisc_instr_tests_system_eret.f: -------------------------------------------------------------------------------- 1 | +cocotb.module=fwrisc_rv32i_tests.instr_tests 2 | +SW_IMAGE=${BUILD_DIR}/esw/unit/system_eret.elf 3 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32i/sim/tests/fwrisc_riscv_compliance_rv32i_I-ADD-01.f: -------------------------------------------------------------------------------- 1 | +cocotb.module=fwrisc_rv32i_tests.compliance_tests 2 | +SW_IMAGE=${BUILD_DIR}/esw/I-ADD-01.elf 3 | +REF_FILE=${PACKAGES_DIR}/riscv-compliance/riscv-test-suite/rv32i/references/I-ADD-01.reference_output 4 | 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32i/sim/tests/fwrisc_riscv_compliance_rv32i_I-ADDI-01.f: -------------------------------------------------------------------------------- 1 | +cocotb.module=fwrisc_rv32i_tests.compliance_tests 2 | +SW_IMAGE=${BUILD_DIR}/esw/I-ADDI-01.elf 3 | +REF_FILE=${PACKAGES_DIR}/riscv-compliance/riscv-test-suite/rv32i/references/I-ADDI-01.reference_output 4 | 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32i/sim/tests/fwrisc_riscv_compliance_rv32i_I-AND-01.f: -------------------------------------------------------------------------------- 1 | +cocotb.module=fwrisc_rv32i_tests.compliance_tests 2 | +SW_IMAGE=${BUILD_DIR}/esw/I-AND-01.elf 3 | +REF_FILE=${PACKAGES_DIR}/riscv-compliance/riscv-test-suite/rv32i/references/I-AND-01.reference_output 4 | 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32i/sim/tests/fwrisc_riscv_compliance_rv32i_I-ANDI-01.f: -------------------------------------------------------------------------------- 1 | +cocotb.module=fwrisc_rv32i_tests.compliance_tests 2 | +SW_IMAGE=${BUILD_DIR}/esw/I-ANDI-01.elf 3 | +REF_FILE=${PACKAGES_DIR}/riscv-compliance/riscv-test-suite/rv32i/references/I-ANDI-01.reference_output 4 | 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32i/sim/tests/fwrisc_riscv_compliance_rv32i_I-AUIPC-01.f: -------------------------------------------------------------------------------- 1 | +cocotb.module=fwrisc_rv32i_tests.compliance_tests 2 | +SW_IMAGE=${BUILD_DIR}/esw/I-AUIPC-01.elf 3 | +REF_FILE=${PACKAGES_DIR}/riscv-compliance/riscv-test-suite/rv32i/references/I-AUIPC-01.reference_output 4 | 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32i/sim/tests/fwrisc_riscv_compliance_rv32i_I-BEQ-01.f: -------------------------------------------------------------------------------- 1 | +cocotb.module=fwrisc_rv32i_tests.compliance_tests 2 | +SW_IMAGE=${BUILD_DIR}/esw/I-BEQ-01.elf 3 | +REF_FILE=${PACKAGES_DIR}/riscv-compliance/riscv-test-suite/rv32i/references/I-BEQ-01.reference_output 4 | 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32i/sim/tests/fwrisc_riscv_compliance_rv32i_I-BGE-01.f: -------------------------------------------------------------------------------- 1 | +cocotb.module=fwrisc_rv32i_tests.compliance_tests 2 | +SW_IMAGE=${BUILD_DIR}/esw/I-BGE-01.elf 3 | +REF_FILE=${PACKAGES_DIR}/riscv-compliance/riscv-test-suite/rv32i/references/I-BGE-01.reference_output 4 | 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32i/sim/tests/fwrisc_riscv_compliance_rv32i_I-BGEU-01.f: -------------------------------------------------------------------------------- 1 | +cocotb.module=fwrisc_rv32i_tests.compliance_tests 2 | +SW_IMAGE=${BUILD_DIR}/esw/I-BGEU-01.elf 3 | +REF_FILE=${PACKAGES_DIR}/riscv-compliance/riscv-test-suite/rv32i/references/I-BGEU-01.reference_output 4 | 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32i/sim/tests/fwrisc_riscv_compliance_rv32i_I-BLT-01.f: -------------------------------------------------------------------------------- 1 | +cocotb.module=fwrisc_rv32i_tests.compliance_tests 2 | +SW_IMAGE=${BUILD_DIR}/esw/I-BLT-01.elf 3 | +REF_FILE=${PACKAGES_DIR}/riscv-compliance/riscv-test-suite/rv32i/references/I-BLT-01.reference_output 4 | 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32i/sim/tests/fwrisc_riscv_compliance_rv32i_I-BLTU-01.f: -------------------------------------------------------------------------------- 1 | +cocotb.module=fwrisc_rv32i_tests.compliance_tests 2 | +SW_IMAGE=${BUILD_DIR}/esw/I-BLTU-01.elf 3 | +REF_FILE=${PACKAGES_DIR}/riscv-compliance/riscv-test-suite/rv32i/references/I-BLTU-01.reference_output 4 | 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32i/sim/tests/fwrisc_riscv_compliance_rv32i_I-BNE-01.f: -------------------------------------------------------------------------------- 1 | +cocotb.module=fwrisc_rv32i_tests.compliance_tests 2 | +SW_IMAGE=${BUILD_DIR}/esw/I-BNE-01.elf 3 | +REF_FILE=${PACKAGES_DIR}/riscv-compliance/riscv-test-suite/rv32i/references/I-BNE-01.reference_output 4 | 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32i/sim/tests/fwrisc_riscv_compliance_rv32i_I-DELAY_SLOTS-01.f: -------------------------------------------------------------------------------- 1 | +cocotb.module=fwrisc_rv32i_tests.compliance_tests 2 | +SW_IMAGE=${BUILD_DIR}/esw/I-DELAY_SLOTS-01.elf 3 | +REF_FILE=${PACKAGES_DIR}/riscv-compliance/riscv-test-suite/rv32i/references/I-DELAY_SLOTS-01.reference_output 4 | 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32i/sim/tests/fwrisc_riscv_compliance_rv32i_I-EBREAK-01.f: -------------------------------------------------------------------------------- 1 | +cocotb.module=fwrisc_rv32i_tests.compliance_tests 2 | +SW_IMAGE=${BUILD_DIR}/esw/I-EBREAK-01.elf 3 | +REF_FILE=${PACKAGES_DIR}/riscv-compliance/riscv-test-suite/rv32i/references/I-EBREAK-01.reference_output 4 | 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32i/sim/tests/fwrisc_riscv_compliance_rv32i_I-ECALL-01.f: -------------------------------------------------------------------------------- 1 | +cocotb.module=fwrisc_rv32i_tests.compliance_tests 2 | +SW_IMAGE=${BUILD_DIR}/esw/I-ECALL-01.elf 3 | +REF_FILE=${PACKAGES_DIR}/riscv-compliance/riscv-test-suite/rv32i/references/I-ECALL-01.reference_output 4 | 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32i/sim/tests/fwrisc_riscv_compliance_rv32i_I-ENDIANESS-01.f: -------------------------------------------------------------------------------- 1 | +cocotb.module=fwrisc_rv32i_tests.compliance_tests 2 | +SW_IMAGE=${BUILD_DIR}/esw/I-ENDIANESS-01.elf 3 | +REF_FILE=${PACKAGES_DIR}/riscv-compliance/riscv-test-suite/rv32i/references/I-ENDIANESS-01.reference_output 4 | 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32i/sim/tests/fwrisc_riscv_compliance_rv32i_I-IO.f: -------------------------------------------------------------------------------- 1 | +cocotb.module=fwrisc_rv32i_tests.compliance_tests 2 | +SW_IMAGE=${BUILD_DIR}/esw/I-IO.elf 3 | +REF_FILE=${PACKAGES_DIR}/riscv-compliance/riscv-test-suite/rv32i/references/I-IO.reference_output 4 | 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32i/sim/tests/fwrisc_riscv_compliance_rv32i_I-JAL-01.f: -------------------------------------------------------------------------------- 1 | +cocotb.module=fwrisc_rv32i_tests.compliance_tests 2 | +SW_IMAGE=${BUILD_DIR}/esw/I-JAL-01.elf 3 | +REF_FILE=${PACKAGES_DIR}/riscv-compliance/riscv-test-suite/rv32i/references/I-JAL-01.reference_output 4 | 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32i/sim/tests/fwrisc_riscv_compliance_rv32i_I-JALR-01.f: -------------------------------------------------------------------------------- 1 | +cocotb.module=fwrisc_rv32i_tests.compliance_tests 2 | +SW_IMAGE=${BUILD_DIR}/esw/I-JALR-01.elf 3 | +REF_FILE=${PACKAGES_DIR}/riscv-compliance/riscv-test-suite/rv32i/references/I-JALR-01.reference_output 4 | 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32i/sim/tests/fwrisc_riscv_compliance_rv32i_I-LB-01.f: -------------------------------------------------------------------------------- 1 | +cocotb.module=fwrisc_rv32i_tests.compliance_tests 2 | +SW_IMAGE=${BUILD_DIR}/esw/I-LB-01.elf 3 | +REF_FILE=${PACKAGES_DIR}/riscv-compliance/riscv-test-suite/rv32i/references/I-LB-01.reference_output 4 | 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32i/sim/tests/fwrisc_riscv_compliance_rv32i_I-LBU-01.f: -------------------------------------------------------------------------------- 1 | +cocotb.module=fwrisc_rv32i_tests.compliance_tests 2 | +SW_IMAGE=${BUILD_DIR}/esw/I-LBU-01.elf 3 | +REF_FILE=${PACKAGES_DIR}/riscv-compliance/riscv-test-suite/rv32i/references/I-LBU-01.reference_output 4 | 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32i/sim/tests/fwrisc_riscv_compliance_rv32i_I-LH-01.f: -------------------------------------------------------------------------------- 1 | +cocotb.module=fwrisc_rv32i_tests.compliance_tests 2 | +SW_IMAGE=${BUILD_DIR}/esw/I-LH-01.elf 3 | +REF_FILE=${PACKAGES_DIR}/riscv-compliance/riscv-test-suite/rv32i/references/I-LH-01.reference_output 4 | 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32i/sim/tests/fwrisc_riscv_compliance_rv32i_I-LHU-01.f: -------------------------------------------------------------------------------- 1 | +cocotb.module=fwrisc_rv32i_tests.compliance_tests 2 | +SW_IMAGE=${BUILD_DIR}/esw/I-LHU-01.elf 3 | +REF_FILE=${PACKAGES_DIR}/riscv-compliance/riscv-test-suite/rv32i/references/I-LHU-01.reference_output 4 | 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32i/sim/tests/fwrisc_riscv_compliance_rv32i_I-LUI-01.f: -------------------------------------------------------------------------------- 1 | +cocotb.module=fwrisc_rv32i_tests.compliance_tests 2 | +SW_IMAGE=${BUILD_DIR}/esw/I-LUI-01.elf 3 | +REF_FILE=${PACKAGES_DIR}/riscv-compliance/riscv-test-suite/rv32i/references/I-LUI-01.reference_output 4 | 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32i/sim/tests/fwrisc_riscv_compliance_rv32i_I-LW-01.f: -------------------------------------------------------------------------------- 1 | +cocotb.module=fwrisc_rv32i_tests.compliance_tests 2 | +SW_IMAGE=${BUILD_DIR}/esw/I-LW-01.elf 3 | +REF_FILE=${PACKAGES_DIR}/riscv-compliance/riscv-test-suite/rv32i/references/I-LW-01.reference_output 4 | 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32i/sim/tests/fwrisc_riscv_compliance_rv32i_I-MISALIGN_JMP-01.f: -------------------------------------------------------------------------------- 1 | +cocotb.module=fwrisc_rv32i_tests.compliance_tests 2 | +SW_IMAGE=${BUILD_DIR}/esw/I-MISALIGN_JMP-01.elf 3 | +REF_FILE=${PACKAGES_DIR}/riscv-compliance/riscv-test-suite/rv32i/references/I-MISALIGN_JMP-01.reference_output 4 | 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32i/sim/tests/fwrisc_riscv_compliance_rv32i_I-MISALIGN_LDST-01.f: -------------------------------------------------------------------------------- 1 | +cocotb.module=fwrisc_rv32i_tests.compliance_tests 2 | +SW_IMAGE=${BUILD_DIR}/esw/I-MISALIGN_LDST-01.elf 3 | +REF_FILE=${PACKAGES_DIR}/riscv-compliance/riscv-test-suite/rv32i/references/I-MISALIGN_LDST-01.reference_output 4 | 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32i/sim/tests/fwrisc_riscv_compliance_rv32i_I-NOP-01.f: -------------------------------------------------------------------------------- 1 | +cocotb.module=fwrisc_rv32i_tests.compliance_tests 2 | +SW_IMAGE=${BUILD_DIR}/esw/I-NOP-01.elf 3 | +REF_FILE=${PACKAGES_DIR}/riscv-compliance/riscv-test-suite/rv32i/references/I-NOP-01.reference_output 4 | 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32i/sim/tests/fwrisc_riscv_compliance_rv32i_I-OR-01.f: -------------------------------------------------------------------------------- 1 | +cocotb.module=fwrisc_rv32i_tests.compliance_tests 2 | +SW_IMAGE=${BUILD_DIR}/esw/I-OR-01.elf 3 | +REF_FILE=${PACKAGES_DIR}/riscv-compliance/riscv-test-suite/rv32i/references/I-OR-01.reference_output 4 | 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32i/sim/tests/fwrisc_riscv_compliance_rv32i_I-ORI-01.f: -------------------------------------------------------------------------------- 1 | +cocotb.module=fwrisc_rv32i_tests.compliance_tests 2 | +SW_IMAGE=${BUILD_DIR}/esw/I-ORI-01.elf 3 | +REF_FILE=${PACKAGES_DIR}/riscv-compliance/riscv-test-suite/rv32i/references/I-ORI-01.reference_output 4 | 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32i/sim/tests/fwrisc_riscv_compliance_rv32i_I-RF_size-01.f: -------------------------------------------------------------------------------- 1 | +cocotb.module=fwrisc_rv32i_tests.compliance_tests 2 | +SW_IMAGE=${BUILD_DIR}/esw/I-RF_size-01.elf 3 | +REF_FILE=${PACKAGES_DIR}/riscv-compliance/riscv-test-suite/rv32i/references/I-RF_size-01.reference_output 4 | 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32i/sim/tests/fwrisc_riscv_compliance_rv32i_I-RF_width-01.f: -------------------------------------------------------------------------------- 1 | +cocotb.module=fwrisc_rv32i_tests.compliance_tests 2 | +SW_IMAGE=${BUILD_DIR}/esw/I-RF_width-01.elf 3 | +REF_FILE=${PACKAGES_DIR}/riscv-compliance/riscv-test-suite/rv32i/references/I-RF_width-01.reference_output 4 | 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32i/sim/tests/fwrisc_riscv_compliance_rv32i_I-RF_x0-01.f: -------------------------------------------------------------------------------- 1 | +cocotb.module=fwrisc_rv32i_tests.compliance_tests 2 | +SW_IMAGE=${BUILD_DIR}/esw/I-RF_x0-01.elf 3 | +REF_FILE=${PACKAGES_DIR}/riscv-compliance/riscv-test-suite/rv32i/references/I-RF_x0-01.reference_output 4 | 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32i/sim/tests/fwrisc_riscv_compliance_rv32i_I-SB-01.f: -------------------------------------------------------------------------------- 1 | +cocotb.module=fwrisc_rv32i_tests.compliance_tests 2 | +SW_IMAGE=${BUILD_DIR}/esw/I-SB-01.elf 3 | +REF_FILE=${PACKAGES_DIR}/riscv-compliance/riscv-test-suite/rv32i/references/I-SB-01.reference_output 4 | 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32i/sim/tests/fwrisc_riscv_compliance_rv32i_I-SH-01.f: -------------------------------------------------------------------------------- 1 | +cocotb.module=fwrisc_rv32i_tests.compliance_tests 2 | +SW_IMAGE=${BUILD_DIR}/esw/I-SH-01.elf 3 | +REF_FILE=${PACKAGES_DIR}/riscv-compliance/riscv-test-suite/rv32i/references/I-SH-01.reference_output 4 | 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32i/sim/tests/fwrisc_riscv_compliance_rv32i_I-SLL-01.f: -------------------------------------------------------------------------------- 1 | +cocotb.module=fwrisc_rv32i_tests.compliance_tests 2 | +SW_IMAGE=${BUILD_DIR}/esw/I-SLL-01.elf 3 | +REF_FILE=${PACKAGES_DIR}/riscv-compliance/riscv-test-suite/rv32i/references/I-SLL-01.reference_output 4 | 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32i/sim/tests/fwrisc_riscv_compliance_rv32i_I-SLLI-01.f: -------------------------------------------------------------------------------- 1 | +cocotb.module=fwrisc_rv32i_tests.compliance_tests 2 | +SW_IMAGE=${BUILD_DIR}/esw/I-SLLI-01.elf 3 | +REF_FILE=${PACKAGES_DIR}/riscv-compliance/riscv-test-suite/rv32i/references/I-SLLI-01.reference_output 4 | 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32i/sim/tests/fwrisc_riscv_compliance_rv32i_I-SLT-01.f: -------------------------------------------------------------------------------- 1 | +cocotb.module=fwrisc_rv32i_tests.compliance_tests 2 | +SW_IMAGE=${BUILD_DIR}/esw/I-SLT-01.elf 3 | +REF_FILE=${PACKAGES_DIR}/riscv-compliance/riscv-test-suite/rv32i/references/I-SLT-01.reference_output 4 | 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32i/sim/tests/fwrisc_riscv_compliance_rv32i_I-SLTI-01.f: -------------------------------------------------------------------------------- 1 | +cocotb.module=fwrisc_rv32i_tests.compliance_tests 2 | +SW_IMAGE=${BUILD_DIR}/esw/I-SLTI-01.elf 3 | +REF_FILE=${PACKAGES_DIR}/riscv-compliance/riscv-test-suite/rv32i/references/I-SLTI-01.reference_output 4 | 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32i/sim/tests/fwrisc_riscv_compliance_rv32i_I-SLTIU-01.f: -------------------------------------------------------------------------------- 1 | +cocotb.module=fwrisc_rv32i_tests.compliance_tests 2 | +SW_IMAGE=${BUILD_DIR}/esw/I-SLTIU-01.elf 3 | +REF_FILE=${PACKAGES_DIR}/riscv-compliance/riscv-test-suite/rv32i/references/I-SLTIU-01.reference_output 4 | 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32i/sim/tests/fwrisc_riscv_compliance_rv32i_I-SLTU-01.f: -------------------------------------------------------------------------------- 1 | +cocotb.module=fwrisc_rv32i_tests.compliance_tests 2 | +SW_IMAGE=${BUILD_DIR}/esw/I-SLTU-01.elf 3 | +REF_FILE=${PACKAGES_DIR}/riscv-compliance/riscv-test-suite/rv32i/references/I-SLTU-01.reference_output 4 | 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32i/sim/tests/fwrisc_riscv_compliance_rv32i_I-SRA-01.f: -------------------------------------------------------------------------------- 1 | +cocotb.module=fwrisc_rv32i_tests.compliance_tests 2 | +SW_IMAGE=${BUILD_DIR}/esw/I-SRA-01.elf 3 | +REF_FILE=${PACKAGES_DIR}/riscv-compliance/riscv-test-suite/rv32i/references/I-SRA-01.reference_output 4 | 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32i/sim/tests/fwrisc_riscv_compliance_rv32i_I-SRAI-01.f: -------------------------------------------------------------------------------- 1 | +cocotb.module=fwrisc_rv32i_tests.compliance_tests 2 | +SW_IMAGE=${BUILD_DIR}/esw/I-SRAI-01.elf 3 | +REF_FILE=${PACKAGES_DIR}/riscv-compliance/riscv-test-suite/rv32i/references/I-SRAI-01.reference_output 4 | 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32i/sim/tests/fwrisc_riscv_compliance_rv32i_I-SRL-01.f: -------------------------------------------------------------------------------- 1 | +cocotb.module=fwrisc_rv32i_tests.compliance_tests 2 | +SW_IMAGE=${BUILD_DIR}/esw/I-SRL-01.elf 3 | +REF_FILE=${PACKAGES_DIR}/riscv-compliance/riscv-test-suite/rv32i/references/I-SRL-01.reference_output 4 | 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32i/sim/tests/fwrisc_riscv_compliance_rv32i_I-SRLI-01.f: -------------------------------------------------------------------------------- 1 | +cocotb.module=fwrisc_rv32i_tests.compliance_tests 2 | +SW_IMAGE=${BUILD_DIR}/esw/I-SRLI-01.elf 3 | +REF_FILE=${PACKAGES_DIR}/riscv-compliance/riscv-test-suite/rv32i/references/I-SRLI-01.reference_output 4 | 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32i/sim/tests/fwrisc_riscv_compliance_rv32i_I-SUB-01.f: -------------------------------------------------------------------------------- 1 | +cocotb.module=fwrisc_rv32i_tests.compliance_tests 2 | +SW_IMAGE=${BUILD_DIR}/esw/I-SUB-01.elf 3 | +REF_FILE=${PACKAGES_DIR}/riscv-compliance/riscv-test-suite/rv32i/references/I-SUB-01.reference_output 4 | 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32i/sim/tests/fwrisc_riscv_compliance_rv32i_I-SW-01.f: -------------------------------------------------------------------------------- 1 | +cocotb.module=fwrisc_rv32i_tests.compliance_tests 2 | +SW_IMAGE=${BUILD_DIR}/esw/I-SW-01.elf 3 | +REF_FILE=${PACKAGES_DIR}/riscv-compliance/riscv-test-suite/rv32i/references/I-SW-01.reference_output 4 | 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32i/sim/tests/fwrisc_riscv_compliance_rv32i_I-XOR-01.f: -------------------------------------------------------------------------------- 1 | +cocotb.module=fwrisc_rv32i_tests.compliance_tests 2 | +SW_IMAGE=${BUILD_DIR}/esw/I-XOR-01.elf 3 | +REF_FILE=${PACKAGES_DIR}/riscv-compliance/riscv-test-suite/rv32i/references/I-XOR-01.reference_output 4 | 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32i/sim/tests/fwrisc_riscv_compliance_rv32i_I-XORI-01.f: -------------------------------------------------------------------------------- 1 | +cocotb.module=fwrisc_rv32i_tests.compliance_tests 2 | +SW_IMAGE=${BUILD_DIR}/esw/I-XORI-01.elf 3 | +REF_FILE=${PACKAGES_DIR}/riscv-compliance/riscv-test-suite/rv32i/references/I-XORI-01.reference_output 4 | 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32i/sim/tests/fwrisc_zephyr_dhrystone.f: -------------------------------------------------------------------------------- 1 | 2 | +SW_IMAGE=${BUILD_DIR}/esw/zephyr_tests/dhrystone/zephyr/zephyr.elf 3 | +gtest-filter=fwrisc_zephyr_tests.dhrystone 4 | 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32i/sim/tests/fwrisc_zephyr_hello_world.f: -------------------------------------------------------------------------------- 1 | 2 | +cocotb.module=fwrisc_rv32i_tests.zephyr_hello_world_test 3 | +SW_IMAGE=${BUILD_DIR}/esw/zephyr/hello_world/zephyr/zephyr.elf 4 | 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32i/sim/tests/fwrisc_zephyr_philosophers.f: -------------------------------------------------------------------------------- 1 | +cocotb.module=fwrisc_rv32i_tests.zephyr_philosophers_test 2 | +SW_IMAGE=${BUILD_DIR}/esw/zephyr/philosophers/zephyr/zephyr.elf 3 | +TIMEOUT=1000ms 4 | 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32i/sim/tests/fwrisc_zephyr_synchronization.f: -------------------------------------------------------------------------------- 1 | +cocotb.module=fwrisc_rv32i_tests.zephyr_synchronization_test 2 | +SW_IMAGE=${BUILD_DIR}/esw/zephyr/synchronization/zephyr/zephyr.elf 3 | +TIMEOUT=40ms 4 | 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32i/tb/tb.f: -------------------------------------------------------------------------------- 1 | 2 | +incdir+${FWRISC}/ve/fwrisc_rv32i/tb 3 | ${FWRISC}/ve/fwrisc_rv32i/tb/fwrisc_rv32i_tb_hdl.sv 4 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32i/tests/cocotb/fwrisc_rv32i_tests/__init__.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Featherweight-IP/fwrisc/0e21466336c9d611c2b465dcb0de04572b6ebbcf/ve/fwrisc_rv32i/tests/cocotb/fwrisc_rv32i_tests/__init__.py -------------------------------------------------------------------------------- /ve/fwrisc_rv32i/tests/dhrystone/dhrystone.mk: -------------------------------------------------------------------------------- 1 | 2 | FWRISC_TESTS_DHRYSTONE_DIR := $(dir $(lastword $(MAKEFILE_LIST))) 3 | 4 | ifneq (1,$(RULES)) 5 | 6 | SRC_DIRS += $(FWRISC_TESTS_DHRYSTONE_DIR) 7 | 8 | else # Rules 9 | 10 | endif 11 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32i/tests/tests.F: -------------------------------------------------------------------------------- 1 | +incdir+. 2 | ./fwrisc_tests_pkg.sv 3 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32i/tests/unit/arith_add.S: -------------------------------------------------------------------------------- 1 | 2 | #include "unit_header.h" 3 | 4 | entry: 5 | li x1, 5 6 | li x2, 6 7 | add x3, x1, x2 8 | j done 9 | 10 | 11 | start_expected: 12 | .word 1, 5 13 | .word 2, 6 14 | .word 3, 11 15 | end_expected: 16 | 17 | 18 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32i/tests/unit/arith_addi.S: -------------------------------------------------------------------------------- 1 | 2 | #include "unit_header.h" 3 | 4 | entry: 5 | li x1, 5 6 | add x3, x1, 6 7 | j done 8 | 9 | // Expected value for registers 10 | start_expected: 11 | .word 1, 5 12 | .word 3, 11 13 | end_expected: 14 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32i/tests/unit/arith_addi_neg.S: -------------------------------------------------------------------------------- 1 | 2 | #include "unit_header.h" 3 | 4 | entry: 5 | li x1, 5 6 | add x3, x1, -1 7 | j done 8 | 9 | // Expected value for registers 10 | start_expected: 11 | .word 1, 5 12 | .word 3, 4 13 | end_expected: 14 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32i/tests/unit/arith_and.S: -------------------------------------------------------------------------------- 1 | 2 | #include "unit_header.h" 3 | 4 | entry: 5 | li x1, 5 6 | li x2, 6 7 | and x3, x1, x2 8 | j done 9 | 10 | 11 | start_expected: 12 | .word 1, 5 13 | .word 2, 6 14 | .word 3, 4 15 | end_expected: 16 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32i/tests/unit/arith_andi.S: -------------------------------------------------------------------------------- 1 | 2 | #include "unit_header.h" 3 | 4 | entry: 5 | li x1, 5 6 | andi x3, x1, 4 7 | j done 8 | 9 | start_expected: 10 | .word 1, 5 11 | .word 3, 4 // 5&6==4 12 | end_expected: 13 | 14 | 15 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32i/tests/unit/arith_or.S: -------------------------------------------------------------------------------- 1 | 2 | #include "unit_header.h" 3 | 4 | entry: 5 | li x1, 5 6 | li x2, 6 7 | or x3, x1, x2 8 | j done 9 | 10 | start_expected: 11 | .word 1, 5 12 | .word 2, 6 13 | .word 3, 7 // 5|6==7 14 | end_expected: 15 | 16 | 17 | 18 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32i/tests/unit/arith_ori.S: -------------------------------------------------------------------------------- 1 | 2 | #include "unit_header.h" 3 | 4 | entry: 5 | li x1, 5 6 | ori x3, x1, 6 7 | j done 8 | 9 | 10 | start_expected: 11 | .word 1, 5 12 | .word 3, 7 // 5|6==7 13 | end_expected: 14 | 15 | 16 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32i/tests/unit/arith_sll.S: -------------------------------------------------------------------------------- 1 | 2 | #include "unit_header.h" 3 | 4 | entry: 5 | li x1, 5 6 | li x2, 1 7 | sll x3, x2, x1 8 | j done 9 | 10 | start_expected: 11 | .word 1, 5 12 | .word 2, 1 13 | .word 3, (1 << 5) 14 | end_expected: 15 | 16 | 17 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32i/tests/unit/arith_slli.S: -------------------------------------------------------------------------------- 1 | 2 | #include "unit_header.h" 3 | 4 | entry: 5 | li x1, 1 6 | slli x3, x1, 5 7 | j done 8 | 9 | start_expected: 10 | .word 1, 1 11 | .word 3, (1 << 5) 12 | end_expected: 13 | 14 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32i/tests/unit/arith_slt_f.S: -------------------------------------------------------------------------------- 1 | 2 | #include "unit_header.h" 3 | 4 | entry: 5 | li x1, 5 6 | li x2, 5 7 | slt x3, x1, x2 8 | j done 9 | 10 | 11 | start_expected: 12 | .word 1, 5 13 | .word 2, 5 14 | .word 3, 0 // !(5<5) 15 | end_expected: 16 | 17 | 18 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32i/tests/unit/arith_slt_t_neg.S: -------------------------------------------------------------------------------- 1 | 2 | #include "unit_header.h" 3 | 4 | entry: 5 | li x1, -6 6 | li x2, -5 7 | slt x3, x1, x2 8 | j done 9 | 10 | 11 | start_expected: 12 | .word 1, -6 13 | .word 2, -5 14 | .word 3, 1 // -6 < -5 15 | end_expected: 16 | 17 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32i/tests/unit/arith_slt_t_pos.S: -------------------------------------------------------------------------------- 1 | 2 | #include "unit_header.h" 3 | 4 | entry: 5 | li x1, 5 6 | li x2, 6 7 | slt x3, x1, x2 8 | j done 9 | 10 | start_expected: 11 | .word 1, 5 12 | .word 2, 6 13 | .word 3, 1 // 5 < 6 14 | end_expected: 15 | 16 | 17 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32i/tests/unit/arith_slti_f.S: -------------------------------------------------------------------------------- 1 | 2 | #include "unit_header.h" 3 | 4 | entry: 5 | li x1, 5 6 | slti x3, x1, 4 7 | j done 8 | 9 | 10 | start_expected: 11 | .word 1, 5 12 | .word 3, 0 // !(5<4) 13 | end_expected: 14 | 15 | 16 | 17 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32i/tests/unit/arith_slti_t.S: -------------------------------------------------------------------------------- 1 | 2 | #include "unit_header.h" 3 | 4 | 5 | entry: 6 | li x1, 5 7 | slti x3, x1, 6 8 | j done 9 | 10 | 11 | start_expected: 12 | .word 1, 5 13 | .word 3, 1 // (5<6) 14 | end_expected: 15 | 16 | 17 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32i/tests/unit/arith_sltu_t.S: -------------------------------------------------------------------------------- 1 | 2 | #include "unit_header.h" 3 | 4 | entry: 5 | li x1, 0x80000000 6 | li x2, 0x80000001 7 | sltu x3, x1, x2 8 | j done 9 | 10 | 11 | start_expected: 12 | .word 1, 0x80000000 13 | .word 2, 0x80000001 14 | .word 3, 1 15 | end_expected: 16 | 17 | 18 | 19 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32i/tests/unit/arith_sra.S: -------------------------------------------------------------------------------- 1 | 2 | #include "unit_header.h" 3 | 4 | entry: 5 | li x1, 4 6 | li x2, 0x80000000 7 | sra x3, x2, x1 8 | j done 9 | 10 | 11 | start_expected: 12 | .word 1, 4 13 | .word 2, 0x80000000 14 | .word 3, 0xF8000000 15 | end_expected: 16 | 17 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32i/tests/unit/arith_srai.S: -------------------------------------------------------------------------------- 1 | 2 | #include "unit_header.h" 3 | 4 | entry: 5 | li x2, 0x80000000 6 | srai x3, x2, 4 7 | j done 8 | 9 | 10 | start_expected: 11 | .word 2, 0x80000000 12 | .word 3, 0xF8000000 13 | end_expected: 14 | 15 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32i/tests/unit/arith_srl.S: -------------------------------------------------------------------------------- 1 | 2 | #include "unit_header.h" 3 | 4 | entry: 5 | li x1, 5 6 | li x2, 0x80000000 7 | srl x3, x2, x1 8 | j done 9 | 10 | 11 | start_expected: 12 | .word 1, 5 13 | .word 2, 0x80000000 14 | .word 3, (0x80000000 >> 5) 15 | end_expected: 16 | 17 | 18 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32i/tests/unit/arith_srli.S: -------------------------------------------------------------------------------- 1 | 2 | #include "unit_header.h" 3 | 4 | entry: 5 | li x2, 0x80000000 6 | srli x3, x2, 5 7 | j done 8 | 9 | 10 | start_expected: 11 | .word 2, 0x80000000 12 | .word 3, (0x80000000 >> 5) 13 | end_expected: 14 | 15 | 16 | 17 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32i/tests/unit/arith_sub.S: -------------------------------------------------------------------------------- 1 | 2 | #include "unit_header.h" 3 | 4 | entry: 5 | li x1, 5 6 | li x2, 6 7 | sub x3, x2, x1 8 | j done 9 | 10 | 11 | start_expected: 12 | .word 1, 5 13 | .word 2, 6 14 | .word 3, 1 15 | end_expected: 16 | 17 | 18 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32i/tests/unit/arith_xor.S: -------------------------------------------------------------------------------- 1 | 2 | #include "unit_header.h" 3 | 4 | entry: 5 | li x1, 5 6 | li x2, 6 7 | xor x3, x1, x2 8 | j done 9 | 10 | 11 | start_expected: 12 | .word 1, 5 13 | .word 2, 6 14 | .word 3, 3 15 | end_expected: 16 | 17 | 18 | 19 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32i/tests/unit/arith_xori.S: -------------------------------------------------------------------------------- 1 | 2 | #include "unit_header.h" 3 | 4 | entry: 5 | li x1, 5 6 | xori x3, x1, 6 7 | j done 8 | 9 | 10 | start_expected: 11 | .word 1, 5 12 | .word 3, 3 13 | end_expected: 14 | 15 | 16 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32i/tests/unit/long_loop.S: -------------------------------------------------------------------------------- 1 | 2 | #include "unit_header.h" 3 | 4 | entry: 5 | li x1, 0 6 | li x2, 5000000 7 | 1: 8 | addi x1, x1, 1 9 | bne x1, x2, 1b 10 | j done 11 | 12 | 13 | start_expected: 14 | .word 1, 10000000 15 | .word 2, 10000000 16 | end_expected: 17 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32i/tests/unit/lui.S: -------------------------------------------------------------------------------- 1 | 2 | #include "unit_header.h" 3 | 4 | entry: 5 | lui x1, 5 6 | j done 7 | 8 | // Expected value for registers 9 | start_expected: 10 | .word 1, 0x00005000 11 | end_expected: 12 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32i/tests/unit/system_csrc.S: -------------------------------------------------------------------------------- 1 | 2 | #include "unit_header.h" 3 | 4 | entry: 5 | li x1, 0xf 6 | li x2, 0x1 7 | csrw mtvec, x1 8 | csrrc x1, mtvec, x2 9 | 10 | j done 11 | 12 | 13 | start_expected: 14 | .word 1, 0x0f 15 | .word 2, 0x01 16 | .word 0x2D, 0x0e 17 | end_expected: 18 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32i/tests/unit/system_csrr.S: -------------------------------------------------------------------------------- 1 | 2 | #include "unit_header.h" 3 | 4 | entry: 5 | csrr x1, mcause 6 | j done 7 | 8 | 9 | start_expected: 10 | .word 1, 0 11 | .word (0x30+2), 0 12 | end_expected: 13 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32i/tests/unit/system_csrw.S: -------------------------------------------------------------------------------- 1 | 2 | #include "unit_header.h" 3 | 4 | entry: 5 | li x1, 5 6 | csrw mtvec, x1 7 | csrr x2, mtvec 8 | 9 | j done 10 | 11 | 12 | start_expected: 13 | .word 1, 5 14 | .word 2, 5 15 | .word 0x2d, 5 16 | end_expected: 17 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32i/tests/unit/system_csrw_csrr.S: -------------------------------------------------------------------------------- 1 | 2 | #include "unit_header.h" 3 | 4 | entry: 5 | li x1, 5 6 | csrw medeleg, x1 7 | csrr x2, medeleg 8 | 9 | j done 10 | 11 | 12 | start_expected: 13 | .word 0x01, 5 14 | .word 0x02, 5 15 | .word (0x28+2), 5 16 | end_expected: 17 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32i/tests/unit/unit.ld: -------------------------------------------------------------------------------- 1 | 2 | OUTPUT_ARCH("riscv") 3 | ENTRY(_start) 4 | 5 | SECTIONS 6 | { 7 | . = 0x80000000; 8 | .text.init : { *(.text.init) } 9 | . = ALIGN(0x1000); 10 | _end = .; 11 | } 12 | 13 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32imc/fwrisc.F: -------------------------------------------------------------------------------- 1 | -F ./tb/tb.F 2 | -F ./tests/tests.F 3 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32imc/sim/.simscripts: -------------------------------------------------------------------------------- 1 | sim=vlsim 2 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32imc/sim/scripts/vlog.f: -------------------------------------------------------------------------------- 1 | 2 | -f ${FWRISC}/ve/fwrisc/sim/scripts/vlog_hdl.f 3 | -f ${FWRISC}/ve/fwrisc/sim/scripts/vlog_hvl.f 4 | 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32imc/sim/scripts/vlog_hdl.f: -------------------------------------------------------------------------------- 1 | 2 | // +define+MINIMIZE_COMM 3 | 4 | -f ${MEMORY_PRIMITIVES}/rtl/sim/sim.f 5 | 6 | -f ${FWRISC}/rtl/fwrisc.f 7 | +incdir+${FWRISC}/ve/fwrisc_tracer_bfm 8 | ${FWRISC}/ve/fwrisc_tracer_bfm/fwrisc_tracer_bfm.sv 9 | -F ${FWRISC}/ve/fwrisc_rv32imc/tb/tb.F 10 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32imc/sim/scripts/vlog_hdl_ms.f: -------------------------------------------------------------------------------- 1 | 2 | -f ${MEMORY_PRIMITIVES}/rtl/sim/sim.f 3 | 4 | -f ${FWRISC}/rtl/fwrisc.f 5 | ${FWRISC}/ve/fwrisc_tracer_bfm/fwrisc_tracer_bfm_api_pkg.sv 6 | ${FWRISC}/ve/fwrisc_tracer_bfm/fwrisc_tracer_bfm.sv 7 | -F ${FWRISC}/ve/fwrisc/tb/tb.F 8 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32imc/sim/scripts/vlog_hvl.f: -------------------------------------------------------------------------------- 1 | 2 | ${PACKAGES_DIR}/googletest-hdl/src/sv/googletest_sv_pkg.sv 3 | ${FWRISC}/ve/fwrisc/tb/fwrisc_tb_hvl.sv 4 | 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32imc/sim/scripts/vlog_hvl_ms.f: -------------------------------------------------------------------------------- 1 | 2 | ${PACKAGES_DIR}/googletest-hdl/src/sv/googletest_sv_pkg.sv 3 | 4 | +incdir+${FWRISC}/ve/fwrisc/tests/uvm 5 | ${FWRISC}/ve/fwrisc/tests/uvm/fwrisc_tests_pkg.sv 6 | ${FWRISC}/ve/fwrisc/tb/fwrisc_tb_hvl.sv 7 | 8 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32imc/sim/scripts/vlog_ms.f: -------------------------------------------------------------------------------- 1 | 2 | -f ${FWRISC}/ve/fwrisc/sim/scripts/vlog_hdl_ms.f 3 | -f ${FWRISC}/ve/fwrisc/sim/scripts/vlog_hvl_ms.f 4 | 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32imc/sim/testlists/fwrisc_riscv_ripe_tests.tl: -------------------------------------------------------------------------------- 1 | 2 | tests/fwrisc_ripe_1.f 3 | tests/fwrisc_ripe_2.f 4 | tests/fwrisc_ripe_3.f 5 | tests/fwrisc_ripe_4.f 6 | tests/fwrisc_ripe_5.f 7 | 8 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32imc/sim/tests/fwrisc_instr_tests_arith_add.f: -------------------------------------------------------------------------------- 1 | +gtest-filter=fwrisc_instr_tests.runtest 2 | +UVM_TESTNAME=fwrisc_instr_test 3 | +hpi.entry=fwrisc_tests.instr_main 4 | +SW_IMAGE=${BUILD_DIR}/esw/unit/arith_add.elf 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32imc/sim/tests/fwrisc_instr_tests_arith_addi.f: -------------------------------------------------------------------------------- 1 | +gtest-filter=fwrisc_instr_tests.runtest 2 | +UVM_TESTNAME=fwrisc_instr_test 3 | +hpi.entry=fwrisc_tests.instr_main 4 | +SW_IMAGE=${BUILD_DIR}/esw/unit/arith_addi.elf 5 | 6 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32imc/sim/tests/fwrisc_instr_tests_arith_addi_neg.f: -------------------------------------------------------------------------------- 1 | +gtest-filter=fwrisc_instr_tests.runtest 2 | +UVM_TESTNAME=fwrisc_instr_test 3 | +hpi.entry=fwrisc_tests.instr_main 4 | +SW_IMAGE=${BUILD_DIR}/esw/unit/arith_addi_neg.elf 5 | 6 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32imc/sim/tests/fwrisc_instr_tests_arith_and.f: -------------------------------------------------------------------------------- 1 | +gtest-filter=fwrisc_instr_tests.runtest 2 | +UVM_TESTNAME=fwrisc_instr_test 3 | +hpi.entry=fwrisc_tests.instr_main 4 | +SW_IMAGE=${BUILD_DIR}/esw/unit/arith_and.elf 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32imc/sim/tests/fwrisc_instr_tests_arith_andi.f: -------------------------------------------------------------------------------- 1 | +gtest-filter=fwrisc_instr_tests.runtest 2 | +UVM_TESTNAME=fwrisc_instr_test 3 | +hpi.entry=fwrisc_tests.instr_main 4 | +SW_IMAGE=${BUILD_DIR}/esw/unit/arith_andi.elf 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32imc/sim/tests/fwrisc_instr_tests_arith_or.f: -------------------------------------------------------------------------------- 1 | +gtest-filter=fwrisc_instr_tests.runtest 2 | +UVM_TESTNAME=fwrisc_instr_test 3 | +hpi.entry=fwrisc_tests.instr_main 4 | +SW_IMAGE=${BUILD_DIR}/esw/unit/arith_or.elf 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32imc/sim/tests/fwrisc_instr_tests_arith_ori.f: -------------------------------------------------------------------------------- 1 | +gtest-filter=fwrisc_instr_tests.runtest 2 | +UVM_TESTNAME=fwrisc_instr_test 3 | +hpi.entry=fwrisc_tests.instr_main 4 | +SW_IMAGE=${BUILD_DIR}/esw/unit/arith_ori.elf 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32imc/sim/tests/fwrisc_instr_tests_arith_sll.f: -------------------------------------------------------------------------------- 1 | +gtest-filter=fwrisc_instr_tests.runtest 2 | +UVM_TESTNAME=fwrisc_instr_test 3 | +hpi.entry=fwrisc_tests.instr_main 4 | +SW_IMAGE=${BUILD_DIR}/esw/unit/arith_sll.elf 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32imc/sim/tests/fwrisc_instr_tests_arith_slli.f: -------------------------------------------------------------------------------- 1 | +gtest-filter=fwrisc_instr_tests.runtest 2 | +UVM_TESTNAME=fwrisc_instr_test 3 | +hpi.entry=fwrisc_tests.instr_main 4 | +SW_IMAGE=${BUILD_DIR}/esw/unit/arith_slli.elf 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32imc/sim/tests/fwrisc_instr_tests_arith_slt_f.f: -------------------------------------------------------------------------------- 1 | +gtest-filter=fwrisc_instr_tests.runtest 2 | +UVM_TESTNAME=fwrisc_instr_test 3 | +hpi.entry=fwrisc_tests.instr_main 4 | +SW_IMAGE=${BUILD_DIR}/esw/unit/arith_slt_f.elf 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32imc/sim/tests/fwrisc_instr_tests_arith_slt_t_neg.f: -------------------------------------------------------------------------------- 1 | +gtest-filter=fwrisc_instr_tests.runtest 2 | +UVM_TESTNAME=fwrisc_instr_test 3 | +hpi.entry=fwrisc_tests.instr_main 4 | +SW_IMAGE=${BUILD_DIR}/esw/unit/arith_slt_t_neg.elf 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32imc/sim/tests/fwrisc_instr_tests_arith_slt_t_pos.f: -------------------------------------------------------------------------------- 1 | +gtest-filter=fwrisc_instr_tests.runtest 2 | +UVM_TESTNAME=fwrisc_instr_test 3 | +hpi.entry=fwrisc_tests.instr_main 4 | +SW_IMAGE=${BUILD_DIR}/esw/unit/arith_slt_t_pos.elf 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32imc/sim/tests/fwrisc_instr_tests_arith_slti_f.f: -------------------------------------------------------------------------------- 1 | +gtest-filter=fwrisc_instr_tests.runtest 2 | +UVM_TESTNAME=fwrisc_instr_test 3 | +hpi.entry=fwrisc_tests.instr_main 4 | +SW_IMAGE=${BUILD_DIR}/esw/unit/arith_slti_f.elf 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32imc/sim/tests/fwrisc_instr_tests_arith_slti_t.f: -------------------------------------------------------------------------------- 1 | +gtest-filter=fwrisc_instr_tests.runtest 2 | +UVM_TESTNAME=fwrisc_instr_test 3 | +hpi.entry=fwrisc_tests.instr_main 4 | +SW_IMAGE=${BUILD_DIR}/esw/unit/arith_slti_t.elf 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32imc/sim/tests/fwrisc_instr_tests_arith_sltu_t.f: -------------------------------------------------------------------------------- 1 | +gtest-filter=fwrisc_instr_tests.runtest 2 | +UVM_TESTNAME=fwrisc_instr_test 3 | +hpi.entry=fwrisc_tests.instr_main 4 | +SW_IMAGE=${BUILD_DIR}/esw/unit/arith_sltu_t.elf 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32imc/sim/tests/fwrisc_instr_tests_arith_sra.f: -------------------------------------------------------------------------------- 1 | +gtest-filter=fwrisc_instr_tests.runtest 2 | +UVM_TESTNAME=fwrisc_instr_test 3 | +hpi.entry=fwrisc_tests.instr_main 4 | +SW_IMAGE=${BUILD_DIR}/esw/unit/arith_sra.elf 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32imc/sim/tests/fwrisc_instr_tests_arith_srai.f: -------------------------------------------------------------------------------- 1 | +gtest-filter=fwrisc_instr_tests.runtest 2 | +UVM_TESTNAME=fwrisc_instr_test 3 | +hpi.entry=fwrisc_tests.instr_main 4 | +SW_IMAGE=${BUILD_DIR}/esw/unit/arith_srai.elf 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32imc/sim/tests/fwrisc_instr_tests_arith_srl.f: -------------------------------------------------------------------------------- 1 | +gtest-filter=fwrisc_instr_tests.runtest 2 | +UVM_TESTNAME=fwrisc_instr_test 3 | +hpi.entry=fwrisc_tests.instr_main 4 | +SW_IMAGE=${BUILD_DIR}/esw/unit/arith_srl.elf 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32imc/sim/tests/fwrisc_instr_tests_arith_srli.f: -------------------------------------------------------------------------------- 1 | +gtest-filter=fwrisc_instr_tests.runtest 2 | +UVM_TESTNAME=fwrisc_instr_test 3 | +hpi.entry=fwrisc_tests.instr_main 4 | +SW_IMAGE=${BUILD_DIR}/esw/unit/arith_srli.elf 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32imc/sim/tests/fwrisc_instr_tests_arith_sub.f: -------------------------------------------------------------------------------- 1 | +gtest-filter=fwrisc_instr_tests.runtest 2 | +UVM_TESTNAME=fwrisc_instr_test 3 | +hpi.entry=fwrisc_tests.instr_main 4 | +SW_IMAGE=${BUILD_DIR}/esw/unit/arith_sub.elf 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32imc/sim/tests/fwrisc_instr_tests_arith_xor.f: -------------------------------------------------------------------------------- 1 | +gtest-filter=fwrisc_instr_tests.runtest 2 | +UVM_TESTNAME=fwrisc_instr_test 3 | +hpi.entry=fwrisc_tests.instr_main 4 | +SW_IMAGE=${BUILD_DIR}/esw/unit/arith_xor.elf 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32imc/sim/tests/fwrisc_instr_tests_arith_xori.f: -------------------------------------------------------------------------------- 1 | +gtest-filter=fwrisc_instr_tests.runtest 2 | +UVM_TESTNAME=fwrisc_instr_test 3 | +hpi.entry=fwrisc_tests.instr_main 4 | +SW_IMAGE=${BUILD_DIR}/esw/unit/arith_xori.elf 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32imc/sim/tests/fwrisc_instr_tests_branch_beq_f_back.f: -------------------------------------------------------------------------------- 1 | +gtest-filter=fwrisc_instr_tests.runtest 2 | +UVM_TESTNAME=fwrisc_instr_test 3 | +hpi.entry=fwrisc_tests.instr_main 4 | +SW_IMAGE=${BUILD_DIR}/esw/unit/branch_beq_f_back.elf 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32imc/sim/tests/fwrisc_instr_tests_branch_beq_f_fwd.f: -------------------------------------------------------------------------------- 1 | +gtest-filter=fwrisc_instr_tests.runtest 2 | +UVM_TESTNAME=fwrisc_instr_test 3 | +hpi.entry=fwrisc_tests.instr_main 4 | +SW_IMAGE=${BUILD_DIR}/esw/unit/branch_beq_f_fwd.elf 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32imc/sim/tests/fwrisc_instr_tests_branch_beq_t_back.f: -------------------------------------------------------------------------------- 1 | +gtest-filter=fwrisc_instr_tests.runtest 2 | +UVM_TESTNAME=fwrisc_instr_test 3 | +hpi.entry=fwrisc_tests.instr_main 4 | +SW_IMAGE=${BUILD_DIR}/esw/unit/branch_beq_t_back.elf 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32imc/sim/tests/fwrisc_instr_tests_branch_beq_t_fwd.f: -------------------------------------------------------------------------------- 1 | +gtest-filter=fwrisc_instr_tests.runtest 2 | +UVM_TESTNAME=fwrisc_instr_test 3 | +hpi.entry=fwrisc_tests.instr_main 4 | +SW_IMAGE=${BUILD_DIR}/esw/unit/branch_beq_t_fwd.elf 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32imc/sim/tests/fwrisc_instr_tests_branch_bge_eq_t_neg.f: -------------------------------------------------------------------------------- 1 | +gtest-filter=fwrisc_instr_tests.runtest 2 | +UVM_TESTNAME=fwrisc_instr_test 3 | +hpi.entry=fwrisc_tests.instr_main 4 | +SW_IMAGE=${BUILD_DIR}/esw/unit/branch_bge_eq_t_neg.elf 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32imc/sim/tests/fwrisc_instr_tests_branch_bge_eq_t_pos.f: -------------------------------------------------------------------------------- 1 | +gtest-filter=fwrisc_instr_tests.runtest 2 | +UVM_TESTNAME=fwrisc_instr_test 3 | +hpi.entry=fwrisc_tests.instr_main 4 | +SW_IMAGE=${BUILD_DIR}/esw/unit/branch_bge_eq_t_pos.elf 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32imc/sim/tests/fwrisc_instr_tests_branch_bge_gt_t_neg.f: -------------------------------------------------------------------------------- 1 | +gtest-filter=fwrisc_instr_tests.runtest 2 | +UVM_TESTNAME=fwrisc_instr_test 3 | +hpi.entry=fwrisc_tests.instr_main 4 | +SW_IMAGE=${BUILD_DIR}/esw/unit/branch_bge_gt_t_neg.elf 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32imc/sim/tests/fwrisc_instr_tests_branch_bge_gt_t_pos.f: -------------------------------------------------------------------------------- 1 | +gtest-filter=fwrisc_instr_tests.runtest 2 | +UVM_TESTNAME=fwrisc_instr_test 3 | +hpi.entry=fwrisc_tests.instr_main 4 | +SW_IMAGE=${BUILD_DIR}/esw/unit/branch_bge_gt_t_pos.elf 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32imc/sim/tests/fwrisc_instr_tests_branch_blt_t_neg.f: -------------------------------------------------------------------------------- 1 | +gtest-filter=fwrisc_instr_tests.runtest 2 | +UVM_TESTNAME=fwrisc_instr_test 3 | +hpi.entry=fwrisc_tests.instr_main 4 | +SW_IMAGE=${BUILD_DIR}/esw/unit/branch_blt_t_neg.elf 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32imc/sim/tests/fwrisc_instr_tests_branch_blt_t_pos.f: -------------------------------------------------------------------------------- 1 | +gtest-filter=fwrisc_instr_tests.runtest 2 | +UVM_TESTNAME=fwrisc_instr_test 3 | +hpi.entry=fwrisc_tests.instr_main 4 | +SW_IMAGE=${BUILD_DIR}/esw/unit/branch_blt_t_pos.elf 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32imc/sim/tests/fwrisc_instr_tests_branch_bltu_t_neg.f: -------------------------------------------------------------------------------- 1 | +gtest-filter=fwrisc_instr_tests.runtest 2 | +UVM_TESTNAME=fwrisc_instr_test 3 | +hpi.entry=fwrisc_tests.instr_main 4 | +SW_IMAGE=${BUILD_DIR}/esw/unit/branch_bltu_t_neg.elf 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32imc/sim/tests/fwrisc_instr_tests_branch_bltu_t_pos.f: -------------------------------------------------------------------------------- 1 | +gtest-filter=fwrisc_instr_tests.runtest 2 | +UVM_TESTNAME=fwrisc_instr_test 3 | +hpi.entry=fwrisc_tests.instr_main 4 | +SW_IMAGE=${BUILD_DIR}/esw/unit/branch_bltu_t_pos.elf 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32imc/sim/tests/fwrisc_instr_tests_branch_bne_f_back.f: -------------------------------------------------------------------------------- 1 | +gtest-filter=fwrisc_instr_tests.runtest 2 | +UVM_TESTNAME=fwrisc_instr_test 3 | +hpi.entry=fwrisc_tests.instr_main 4 | +SW_IMAGE=${BUILD_DIR}/esw/unit/branch_bne_f_back.elf 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32imc/sim/tests/fwrisc_instr_tests_branch_bne_f_fwd.f: -------------------------------------------------------------------------------- 1 | +gtest-filter=fwrisc_instr_tests.runtest 2 | +UVM_TESTNAME=fwrisc_instr_test 3 | +hpi.entry=fwrisc_tests.instr_main 4 | +SW_IMAGE=${BUILD_DIR}/esw/unit/branch_bne_f_fwd.elf 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32imc/sim/tests/fwrisc_instr_tests_branch_bne_t_back.f: -------------------------------------------------------------------------------- 1 | +gtest-filter=fwrisc_instr_tests.runtest 2 | +UVM_TESTNAME=fwrisc_instr_test 3 | +hpi.entry=fwrisc_tests.instr_main 4 | +SW_IMAGE=${BUILD_DIR}/esw/unit/branch_bne_t_back.elf 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32imc/sim/tests/fwrisc_instr_tests_branch_bne_t_fwd.f: -------------------------------------------------------------------------------- 1 | +gtest-filter=fwrisc_instr_tests.runtest 2 | +UVM_TESTNAME=fwrisc_instr_test 3 | +hpi.entry=fwrisc_tests.instr_main 4 | +SW_IMAGE=${BUILD_DIR}/esw/unit/branch_bne_t_fwd.elf 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32imc/sim/tests/fwrisc_instr_tests_counters_cycle.f: -------------------------------------------------------------------------------- 1 | +gtest-filter=fwrisc_instr_tests_counters.cycle 2 | +UVM_TESTNAME=fwrisc_instr_test 3 | +hpi.entry=fwrisc_tests.instr_main 4 | 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32imc/sim/tests/fwrisc_instr_tests_exception_bne.f: -------------------------------------------------------------------------------- 1 | +gtest-filter=fwrisc_instr_tests.runtest 2 | +UVM_TESTNAME=fwrisc_instr_test 3 | +hpi.entry=fwrisc_tests.instr_main 4 | +SW_IMAGE=${BUILD_DIR}/esw/unit/exception_bne.elf 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32imc/sim/tests/fwrisc_instr_tests_exception_dep_x.f: -------------------------------------------------------------------------------- 1 | +gtest-filter=fwrisc_instr_tests.runtest 2 | +UVM_TESTNAME=fwrisc_instr_test 3 | +hpi.entry=fwrisc_tests.instr_main 4 | +SW_IMAGE=${BUILD_DIR}/esw/unit/exception_dep_x.elf 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32imc/sim/tests/fwrisc_instr_tests_exception_j.f: -------------------------------------------------------------------------------- 1 | +gtest-filter=fwrisc_instr_tests.runtest 2 | +UVM_TESTNAME=fwrisc_instr_test 3 | +hpi.entry=fwrisc_tests.instr_main 4 | +SW_IMAGE=${BUILD_DIR}/esw/unit/branch_beq_t_back.elf 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32imc/sim/tests/fwrisc_instr_tests_exception_jalr.f: -------------------------------------------------------------------------------- 1 | +gtest-filter=fwrisc_instr_tests.runtest 2 | +UVM_TESTNAME=fwrisc_instr_test 3 | +hpi.entry=fwrisc_tests.instr_main 4 | +SW_IMAGE=${BUILD_DIR}/esw/unit/exception_jalr.elf 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32imc/sim/tests/fwrisc_instr_tests_exception_lw.f: -------------------------------------------------------------------------------- 1 | +gtest-filter=fwrisc_instr_tests.runtest 2 | +UVM_TESTNAME=fwrisc_instr_test 3 | +hpi.entry=fwrisc_tests.instr_main 4 | +SW_IMAGE=${BUILD_DIR}/esw/unit/exception_lw.elf 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32imc/sim/tests/fwrisc_instr_tests_jump_j.f: -------------------------------------------------------------------------------- 1 | +gtest-filter=fwrisc_instr_tests.runtest 2 | +UVM_TESTNAME=fwrisc_instr_test 3 | +hpi.entry=fwrisc_tests.instr_main 4 | +SW_IMAGE=${BUILD_DIR}/esw/unit/jump_j.elf 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32imc/sim/tests/fwrisc_instr_tests_jump_jal.f: -------------------------------------------------------------------------------- 1 | +gtest-filter=fwrisc_instr_tests.runtest 2 | +UVM_TESTNAME=fwrisc_instr_test 3 | +hpi.entry=fwrisc_tests.instr_main 4 | +SW_IMAGE=${BUILD_DIR}/esw/unit/jump_jal.elf 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32imc/sim/tests/fwrisc_instr_tests_jump_jalr.f: -------------------------------------------------------------------------------- 1 | +gtest-filter=fwrisc_instr_tests.runtest 2 | +UVM_TESTNAME=fwrisc_instr_test 3 | +hpi.entry=fwrisc_tests.instr_main 4 | +SW_IMAGE=${BUILD_DIR}/esw/unit/jump_jalr.elf 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32imc/sim/tests/fwrisc_instr_tests_jump_jalr_off_neg.f: -------------------------------------------------------------------------------- 1 | +gtest-filter=fwrisc_instr_tests.runtest 2 | +UVM_TESTNAME=fwrisc_instr_test 3 | +hpi.entry=fwrisc_tests.instr_main 4 | +SW_IMAGE=${BUILD_DIR}/esw/unit/jump_jalr_off_neg.elf 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32imc/sim/tests/fwrisc_instr_tests_jump_jalr_off_pos.f: -------------------------------------------------------------------------------- 1 | +gtest-filter=fwrisc_instr_tests.runtest 2 | +UVM_TESTNAME=fwrisc_instr_test 3 | +hpi.entry=fwrisc_tests.instr_main 4 | +SW_IMAGE=${BUILD_DIR}/esw/unit/jump_jalr_off_pos.elf 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32imc/sim/tests/fwrisc_instr_tests_ldst_lb.f: -------------------------------------------------------------------------------- 1 | +gtest-filter=fwrisc_instr_tests.runtest 2 | +UVM_TESTNAME=fwrisc_instr_test 3 | +hpi.entry=fwrisc_tests.instr_main 4 | +SW_IMAGE=${BUILD_DIR}/esw/unit/ldst_lb.elf 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32imc/sim/tests/fwrisc_instr_tests_ldst_lb_s.f: -------------------------------------------------------------------------------- 1 | +gtest-filter=fwrisc_instr_tests.runtest 2 | +UVM_TESTNAME=fwrisc_instr_test 3 | +hpi.entry=fwrisc_tests.instr_main 4 | +SW_IMAGE=${BUILD_DIR}/esw/unit/ldst_lb_s.elf 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32imc/sim/tests/fwrisc_instr_tests_ldst_lb_u.f: -------------------------------------------------------------------------------- 1 | +gtest-filter=fwrisc_instr_tests.runtest 2 | +UVM_TESTNAME=fwrisc_instr_test 3 | +hpi.entry=fwrisc_tests.instr_main 4 | +SW_IMAGE=${BUILD_DIR}/esw/unit/ldst_lb_u.elf 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32imc/sim/tests/fwrisc_instr_tests_ldst_lbu_s.f: -------------------------------------------------------------------------------- 1 | +gtest-filter=fwrisc_instr_tests.runtest 2 | +UVM_TESTNAME=fwrisc_instr_test 3 | +hpi.entry=fwrisc_tests.instr_main 4 | +SW_IMAGE=${BUILD_DIR}/esw/unit/ldst_lbu_s.elf 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32imc/sim/tests/fwrisc_instr_tests_ldst_lh_s.f: -------------------------------------------------------------------------------- 1 | +gtest-filter=fwrisc_instr_tests.runtest 2 | +UVM_TESTNAME=fwrisc_instr_test 3 | +hpi.entry=fwrisc_tests.instr_main 4 | +SW_IMAGE=${BUILD_DIR}/esw/unit/ldst_lh_s.elf 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32imc/sim/tests/fwrisc_instr_tests_ldst_lh_u.f: -------------------------------------------------------------------------------- 1 | +gtest-filter=fwrisc_instr_tests.runtest 2 | +UVM_TESTNAME=fwrisc_instr_test 3 | +hpi.entry=fwrisc_tests.instr_main 4 | +SW_IMAGE=${BUILD_DIR}/esw/unit/ldst_lh_u.elf 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32imc/sim/tests/fwrisc_instr_tests_ldst_lhu_s.f: -------------------------------------------------------------------------------- 1 | +gtest-filter=fwrisc_instr_tests.runtest 2 | +UVM_TESTNAME=fwrisc_instr_test 3 | +hpi.entry=fwrisc_tests.instr_main 4 | +SW_IMAGE=${BUILD_DIR}/esw/unit/ldst_lhu_s.elf 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32imc/sim/tests/fwrisc_instr_tests_ldst_lw.f: -------------------------------------------------------------------------------- 1 | +gtest-filter=fwrisc_instr_tests.runtest 2 | +UVM_TESTNAME=fwrisc_instr_test 3 | +hpi.entry=fwrisc_tests.instr_main 4 | +SW_IMAGE=${BUILD_DIR}/esw/unit/ldst_lw.elf 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32imc/sim/tests/fwrisc_instr_tests_ldst_sb_lw.f: -------------------------------------------------------------------------------- 1 | +gtest-filter=fwrisc_instr_tests.runtest 2 | +UVM_TESTNAME=fwrisc_instr_test 3 | +hpi.entry=fwrisc_tests.instr_main 4 | +SW_IMAGE=${BUILD_DIR}/esw/unit/ldst_sb_lw.elf 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32imc/sim/tests/fwrisc_instr_tests_ldst_sh_lw.f: -------------------------------------------------------------------------------- 1 | +gtest-filter=fwrisc_instr_tests.runtest 2 | +UVM_TESTNAME=fwrisc_instr_test 3 | +hpi.entry=fwrisc_tests.instr_main 4 | +SW_IMAGE=${BUILD_DIR}/esw/unit/ldst_sh_lw.elf 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32imc/sim/tests/fwrisc_instr_tests_ldst_sw_lw.f: -------------------------------------------------------------------------------- 1 | +gtest-filter=fwrisc_instr_tests.runtest 2 | +UVM_TESTNAME=fwrisc_instr_test 3 | +hpi.entry=fwrisc_tests.instr_main 4 | +SW_IMAGE=${BUILD_DIR}/esw/unit/ldst_sw_lw.elf 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32imc/sim/tests/fwrisc_instr_tests_long_loop.f: -------------------------------------------------------------------------------- 1 | +gtest-filter=fwrisc_instr_tests.runtest 2 | +UVM_TESTNAME=fwrisc_instr_test 3 | +hpi.entry=fwrisc_tests.instr_main 4 | +SW_IMAGE=${BUILD_DIR}/esw/unit/long_loop.elf 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32imc/sim/tests/fwrisc_instr_tests_lui.f: -------------------------------------------------------------------------------- 1 | +gtest-filter=fwrisc_instr_tests.runtest 2 | +UVM_TESTNAME=fwrisc_instr_test 3 | +hpi.entry=fwrisc_tests.instr_main 4 | +SW_IMAGE=${BUILD_DIR}/esw/unit/lui.elf 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32imc/sim/tests/fwrisc_instr_tests_system_csrc.f: -------------------------------------------------------------------------------- 1 | +gtest-filter=fwrisc_instr_tests.runtest 2 | +UVM_TESTNAME=fwrisc_instr_test 3 | +hpi.entry=fwrisc_tests.instr_main 4 | +SW_IMAGE=${BUILD_DIR}/esw/unit/system_csrc.elf 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32imc/sim/tests/fwrisc_instr_tests_system_csrr.f: -------------------------------------------------------------------------------- 1 | +gtest-filter=fwrisc_instr_tests.runtest 2 | +UVM_TESTNAME=fwrisc_instr_test 3 | +hpi.entry=fwrisc_tests.instr_main 4 | +SW_IMAGE=${BUILD_DIR}/esw/unit/system_csrr.elf 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32imc/sim/tests/fwrisc_instr_tests_system_csrs.f: -------------------------------------------------------------------------------- 1 | +gtest-filter=fwrisc_instr_tests.runtest 2 | +UVM_TESTNAME=fwrisc_instr_test 3 | +hpi.entry=fwrisc_tests.instr_main 4 | +SW_IMAGE=${BUILD_DIR}/esw/unit/system_csrs.elf 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32imc/sim/tests/fwrisc_instr_tests_system_csrsi.f: -------------------------------------------------------------------------------- 1 | +gtest-filter=fwrisc_instr_tests.runtest 2 | +UVM_TESTNAME=fwrisc_instr_test 3 | +hpi.entry=fwrisc_tests.instr_main 4 | +SW_IMAGE=${BUILD_DIR}/esw/unit/system_csrsi.elf 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32imc/sim/tests/fwrisc_instr_tests_system_csrw.f: -------------------------------------------------------------------------------- 1 | +gtest-filter=fwrisc_instr_tests.runtest 2 | +UVM_TESTNAME=fwrisc_instr_test 3 | +hpi.entry=fwrisc_tests.instr_main 4 | +SW_IMAGE=${BUILD_DIR}/esw/unit/system_csrw.elf 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32imc/sim/tests/fwrisc_instr_tests_system_csrw_csrr.f: -------------------------------------------------------------------------------- 1 | +gtest-filter=fwrisc_instr_tests.runtest 2 | +UVM_TESTNAME=fwrisc_instr_test 3 | +hpi.entry=fwrisc_tests.instr_main 4 | +SW_IMAGE=${BUILD_DIR}/esw/unit/system_csrw_csrr.elf 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32imc/sim/tests/fwrisc_instr_tests_system_ecall.f: -------------------------------------------------------------------------------- 1 | +gtest-filter=fwrisc_instr_tests.runtest 2 | +UVM_TESTNAME=fwrisc_instr_test 3 | +hpi.entry=fwrisc_tests.instr_main 4 | +SW_IMAGE=${BUILD_DIR}/esw/unit/system_ecall.elf 5 | 6 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32imc/sim/tests/fwrisc_instr_tests_system_eret.f: -------------------------------------------------------------------------------- 1 | +gtest-filter=fwrisc_instr_tests.runtest 2 | +UVM_TESTNAME=fwrisc_instr_test 3 | +hpi.entry=fwrisc_tests.instr_main 4 | +SW_IMAGE=${BUILD_DIR}/esw/unit/system_eret.elf 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32imc/sim/tests/fwrisc_ripe_1.f: -------------------------------------------------------------------------------- 1 | 2 | +SW_IMAGE=${BUILD_DIR}/esw/ripe_1/zephyr/zephyr.elf 3 | // +TRACE_INSTR 4 | // +TRACE_FUNCS 5 | +gtest-filter=fwrisc_ripe_tests.ripe 6 | 7 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32imc/sim/tests/fwrisc_ripe_2.f: -------------------------------------------------------------------------------- 1 | 2 | +SW_IMAGE=${BUILD_DIR}/esw/ripe_2/zephyr/zephyr.elf 3 | +gtest-filter=fwrisc_ripe_tests.ripe 4 | 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32imc/sim/tests/fwrisc_ripe_3.f: -------------------------------------------------------------------------------- 1 | 2 | +SW_IMAGE=${BUILD_DIR}/esw/ripe_3/zephyr/zephyr.elf 3 | +gtest-filter=fwrisc_ripe_tests.ripe 4 | 5 | 6 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32imc/sim/tests/fwrisc_ripe_4.f: -------------------------------------------------------------------------------- 1 | 2 | +SW_IMAGE=${BUILD_DIR}/esw/ripe_4/zephyr/zephyr.elf 3 | +gtest-filter=fwrisc_ripe_tests.ripe 4 | 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32imc/sim/tests/fwrisc_ripe_5.f: -------------------------------------------------------------------------------- 1 | 2 | +SW_IMAGE=${BUILD_DIR}/esw/ripe_5/zephyr/zephyr.elf 3 | +gtest-filter=fwrisc_ripe_tests.ripe 4 | 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32imc/sim/tests/fwrisc_riscv_compliance_rv32i_I-ADDI-01.f: -------------------------------------------------------------------------------- 1 | +SW_IMAGE=${BUILD_DIR}/esw/I-ADDI-01.elf 2 | +REF_FILE=${PACKAGES_DIR}/riscv-compliance/riscv-test-suite/rv32i/references/I-ADDI-01.reference_output 3 | +gtest-filter=riscv_compliance_tests.runtest 4 | +hpi.entry=fwrisc_tests.riscv_compliance_main 5 | 6 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32imc/sim/tests/fwrisc_riscv_compliance_rv32i_I-AND-01.f: -------------------------------------------------------------------------------- 1 | +SW_IMAGE=${BUILD_DIR}/esw/I-AND-01.elf 2 | +REF_FILE=${PACKAGES_DIR}/riscv-compliance/riscv-test-suite/rv32i/references/I-AND-01.reference_output 3 | +gtest-filter=riscv_compliance_tests.runtest 4 | +hpi.entry=fwrisc_tests.riscv_compliance_main 5 | 6 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32imc/sim/tests/fwrisc_riscv_compliance_rv32i_I-ANDI-01.f: -------------------------------------------------------------------------------- 1 | +SW_IMAGE=${BUILD_DIR}/esw/I-ANDI-01.elf 2 | +REF_FILE=${PACKAGES_DIR}/riscv-compliance/riscv-test-suite/rv32i/references/I-ANDI-01.reference_output 3 | +gtest-filter=riscv_compliance_tests.runtest 4 | +hpi.entry=fwrisc_tests.riscv_compliance_main 5 | 6 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32imc/sim/tests/fwrisc_riscv_compliance_rv32i_I-AUIPC-01.f: -------------------------------------------------------------------------------- 1 | +SW_IMAGE=${BUILD_DIR}/esw/I-AUIPC-01.elf 2 | +REF_FILE=${PACKAGES_DIR}/riscv-compliance/riscv-test-suite/rv32i/references/I-AUIPC-01.reference_output 3 | +gtest-filter=riscv_compliance_tests.runtest 4 | +hpi.entry=fwrisc_tests.riscv_compliance_main 5 | 6 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32imc/sim/tests/fwrisc_riscv_compliance_rv32i_I-BEQ-01.f: -------------------------------------------------------------------------------- 1 | +SW_IMAGE=${BUILD_DIR}/esw/I-BEQ-01.elf 2 | +REF_FILE=${PACKAGES_DIR}/riscv-compliance/riscv-test-suite/rv32i/references/I-BEQ-01.reference_output 3 | +gtest-filter=riscv_compliance_tests.runtest 4 | +hpi.entry=fwrisc_tests.riscv_compliance_main 5 | 6 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32imc/sim/tests/fwrisc_riscv_compliance_rv32i_I-BGE-01.f: -------------------------------------------------------------------------------- 1 | +SW_IMAGE=${BUILD_DIR}/esw/I-BGE-01.elf 2 | +REF_FILE=${PACKAGES_DIR}/riscv-compliance/riscv-test-suite/rv32i/references/I-BGE-01.reference_output 3 | +gtest-filter=riscv_compliance_tests.runtest 4 | +hpi.entry=fwrisc_tests.riscv_compliance_main 5 | 6 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32imc/sim/tests/fwrisc_riscv_compliance_rv32i_I-BGEU-01.f: -------------------------------------------------------------------------------- 1 | +SW_IMAGE=${BUILD_DIR}/esw/I-BGEU-01.elf 2 | +REF_FILE=${PACKAGES_DIR}/riscv-compliance/riscv-test-suite/rv32i/references/I-BGEU-01.reference_output 3 | +gtest-filter=riscv_compliance_tests.runtest 4 | +hpi.entry=fwrisc_tests.riscv_compliance_main 5 | 6 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32imc/sim/tests/fwrisc_riscv_compliance_rv32i_I-BLT-01.f: -------------------------------------------------------------------------------- 1 | +SW_IMAGE=${BUILD_DIR}/esw/I-BLT-01.elf 2 | +REF_FILE=${PACKAGES_DIR}/riscv-compliance/riscv-test-suite/rv32i/references/I-BLT-01.reference_output 3 | +gtest-filter=riscv_compliance_tests.runtest 4 | +hpi.entry=fwrisc_tests.riscv_compliance_main 5 | 6 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32imc/sim/tests/fwrisc_riscv_compliance_rv32i_I-BLTU-01.f: -------------------------------------------------------------------------------- 1 | +SW_IMAGE=${BUILD_DIR}/esw/I-BLTU-01.elf 2 | +REF_FILE=${PACKAGES_DIR}/riscv-compliance/riscv-test-suite/rv32i/references/I-BLTU-01.reference_output 3 | +gtest-filter=riscv_compliance_tests.runtest 4 | +hpi.entry=fwrisc_tests.riscv_compliance_main 5 | 6 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32imc/sim/tests/fwrisc_riscv_compliance_rv32i_I-BNE-01.f: -------------------------------------------------------------------------------- 1 | +SW_IMAGE=${BUILD_DIR}/esw/I-BNE-01.elf 2 | +REF_FILE=${PACKAGES_DIR}/riscv-compliance/riscv-test-suite/rv32i/references/I-BNE-01.reference_output 3 | +gtest-filter=riscv_compliance_tests.runtest 4 | +hpi.entry=fwrisc_tests.riscv_compliance_main 5 | 6 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32imc/sim/tests/fwrisc_riscv_compliance_rv32i_I-CSRRC-01.f: -------------------------------------------------------------------------------- 1 | +SW_IMAGE=${BUILD_DIR}/esw/I-CSRRC-01.elf 2 | +REF_FILE=${PACKAGES_DIR}/riscv-compliance/riscv-test-suite/rv32i/references/I-CSRRC-01.reference_output 3 | +gtest-filter=riscv_compliance_tests.runtest 4 | +hpi.entry=fwrisc_tests.riscv_compliance_main 5 | 6 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32imc/sim/tests/fwrisc_riscv_compliance_rv32i_I-CSRRCI-01.f: -------------------------------------------------------------------------------- 1 | +SW_IMAGE=${BUILD_DIR}/esw/I-CSRRCI-01.elf 2 | +REF_FILE=${PACKAGES_DIR}/riscv-compliance/riscv-test-suite/rv32i/references/I-CSRRCI-01.reference_output 3 | +gtest-filter=riscv_compliance_tests.runtest 4 | +hpi.entry=fwrisc_tests.riscv_compliance_main 5 | 6 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32imc/sim/tests/fwrisc_riscv_compliance_rv32i_I-CSRRS-01.f: -------------------------------------------------------------------------------- 1 | +SW_IMAGE=${BUILD_DIR}/esw/I-CSRRS-01.elf 2 | +REF_FILE=${PACKAGES_DIR}/riscv-compliance/riscv-test-suite/rv32i/references/I-CSRRS-01.reference_output 3 | +gtest-filter=riscv_compliance_tests.runtest 4 | +hpi.entry=fwrisc_tests.riscv_compliance_main 5 | 6 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32imc/sim/tests/fwrisc_riscv_compliance_rv32i_I-CSRRSI-01.f: -------------------------------------------------------------------------------- 1 | +SW_IMAGE=${BUILD_DIR}/esw/I-CSRRSI-01.elf 2 | +REF_FILE=${PACKAGES_DIR}/riscv-compliance/riscv-test-suite/rv32i/references/I-CSRRSI-01.reference_output 3 | +gtest-filter=riscv_compliance_tests.runtest 4 | +hpi.entry=fwrisc_tests.riscv_compliance_main 5 | 6 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32imc/sim/tests/fwrisc_riscv_compliance_rv32i_I-CSRRW-01.f: -------------------------------------------------------------------------------- 1 | +SW_IMAGE=${BUILD_DIR}/esw/I-CSRRW-01.elf 2 | +REF_FILE=${PACKAGES_DIR}/riscv-compliance/riscv-test-suite/rv32i/references/I-CSRRW-01.reference_output 3 | +gtest-filter=riscv_compliance_tests.runtest 4 | +hpi.entry=fwrisc_tests.riscv_compliance_main 5 | 6 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32imc/sim/tests/fwrisc_riscv_compliance_rv32i_I-CSRRWI-01.f: -------------------------------------------------------------------------------- 1 | +SW_IMAGE=${BUILD_DIR}/esw/I-CSRRWI-01.elf 2 | +REF_FILE=${PACKAGES_DIR}/riscv-compliance/riscv-test-suite/rv32i/references/I-CSRRWI-01.reference_output 3 | +gtest-filter=riscv_compliance_tests.runtest 4 | +hpi.entry=fwrisc_tests.riscv_compliance_main 5 | 6 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32imc/sim/tests/fwrisc_riscv_compliance_rv32i_I-EBREAK-01.f: -------------------------------------------------------------------------------- 1 | +SW_IMAGE=${BUILD_DIR}/esw/I-EBREAK-01.elf 2 | +REF_FILE=${PACKAGES_DIR}/riscv-compliance/riscv-test-suite/rv32i/references/I-EBREAK-01.reference_output 3 | +gtest-filter=riscv_compliance_tests.runtest 4 | +hpi.entry=fwrisc_tests.riscv_compliance_main 5 | 6 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32imc/sim/tests/fwrisc_riscv_compliance_rv32i_I-ECALL-01.f: -------------------------------------------------------------------------------- 1 | +SW_IMAGE=${BUILD_DIR}/esw/I-ECALL-01.elf 2 | +REF_FILE=${PACKAGES_DIR}/riscv-compliance/riscv-test-suite/rv32i/references/I-ECALL-01.reference_output 3 | +gtest-filter=riscv_compliance_tests.runtest 4 | +hpi.entry=fwrisc_tests.riscv_compliance_main 5 | 6 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32imc/sim/tests/fwrisc_riscv_compliance_rv32i_I-FENCE.f: -------------------------------------------------------------------------------- 1 | +SW_IMAGE=${BUILD_DIR}/esw/I-FENCE.I-01.elf 2 | +REF_FILE=${PACKAGES_DIR}/riscv-compliance/riscv-test-suite/rv32i/references/I-FENCE.I-01.reference_output 3 | +gtest-filter=riscv_compliance_tests.runtest 4 | +hpi.entry=fwrisc_tests.riscv_compliance_main 5 | 6 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32imc/sim/tests/fwrisc_riscv_compliance_rv32i_I-IO.f: -------------------------------------------------------------------------------- 1 | +SW_IMAGE=${BUILD_DIR}/esw/I-IO.elf 2 | +REF_FILE=${PACKAGES_DIR}/riscv-compliance/riscv-test-suite/rv32i/references/I-IO.reference_output 3 | +gtest-filter=riscv_compliance_tests.runtest 4 | +hpi.entry=fwrisc_tests.riscv_compliance_main 5 | 6 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32imc/sim/tests/fwrisc_riscv_compliance_rv32i_I-JAL-01.f: -------------------------------------------------------------------------------- 1 | +SW_IMAGE=${BUILD_DIR}/esw/I-JAL-01.elf 2 | +REF_FILE=${PACKAGES_DIR}/riscv-compliance/riscv-test-suite/rv32i/references/I-JAL-01.reference_output 3 | +gtest-filter=riscv_compliance_tests.runtest 4 | +hpi.entry=fwrisc_tests.riscv_compliance_main 5 | 6 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32imc/sim/tests/fwrisc_riscv_compliance_rv32i_I-JALR-01.f: -------------------------------------------------------------------------------- 1 | +SW_IMAGE=${BUILD_DIR}/esw/I-JALR-01.elf 2 | +REF_FILE=${PACKAGES_DIR}/riscv-compliance/riscv-test-suite/rv32i/references/I-JALR-01.reference_output 3 | +gtest-filter=riscv_compliance_tests.runtest 4 | +hpi.entry=fwrisc_tests.riscv_compliance_main 5 | 6 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32imc/sim/tests/fwrisc_riscv_compliance_rv32i_I-LB-01.f: -------------------------------------------------------------------------------- 1 | +SW_IMAGE=${BUILD_DIR}/esw/I-LB-01.elf 2 | +REF_FILE=${PACKAGES_DIR}/riscv-compliance/riscv-test-suite/rv32i/references/I-LB-01.reference_output 3 | +gtest-filter=riscv_compliance_tests.runtest 4 | +hpi.entry=fwrisc_tests.riscv_compliance_main 5 | 6 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32imc/sim/tests/fwrisc_riscv_compliance_rv32i_I-LBU-01.f: -------------------------------------------------------------------------------- 1 | +SW_IMAGE=${BUILD_DIR}/esw/I-LBU-01.elf 2 | +REF_FILE=${PACKAGES_DIR}/riscv-compliance/riscv-test-suite/rv32i/references/I-LBU-01.reference_output 3 | +gtest-filter=riscv_compliance_tests.runtest 4 | +hpi.entry=fwrisc_tests.riscv_compliance_main 5 | 6 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32imc/sim/tests/fwrisc_riscv_compliance_rv32i_I-LH-01.f: -------------------------------------------------------------------------------- 1 | +SW_IMAGE=${BUILD_DIR}/esw/I-LH-01.elf 2 | +REF_FILE=${PACKAGES_DIR}/riscv-compliance/riscv-test-suite/rv32i/references/I-LH-01.reference_output 3 | +gtest-filter=riscv_compliance_tests.runtest 4 | +hpi.entry=fwrisc_tests.riscv_compliance_main 5 | 6 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32imc/sim/tests/fwrisc_riscv_compliance_rv32i_I-LHU-01.f: -------------------------------------------------------------------------------- 1 | +SW_IMAGE=${BUILD_DIR}/esw/I-LHU-01.elf 2 | +REF_FILE=${PACKAGES_DIR}/riscv-compliance/riscv-test-suite/rv32i/references/I-LHU-01.reference_output 3 | +gtest-filter=riscv_compliance_tests.runtest 4 | +hpi.entry=fwrisc_tests.riscv_compliance_main 5 | 6 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32imc/sim/tests/fwrisc_riscv_compliance_rv32i_I-LUI-01.f: -------------------------------------------------------------------------------- 1 | +SW_IMAGE=${BUILD_DIR}/esw/I-LUI-01.elf 2 | +REF_FILE=${PACKAGES_DIR}/riscv-compliance/riscv-test-suite/rv32i/references/I-LUI-01.reference_output 3 | +gtest-filter=riscv_compliance_tests.runtest 4 | +hpi.entry=fwrisc_tests.riscv_compliance_main 5 | 6 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32imc/sim/tests/fwrisc_riscv_compliance_rv32i_I-LW-01.f: -------------------------------------------------------------------------------- 1 | +SW_IMAGE=${BUILD_DIR}/esw/I-LW-01.elf 2 | +REF_FILE=${PACKAGES_DIR}/riscv-compliance/riscv-test-suite/rv32i/references/I-LW-01.reference_output 3 | +gtest-filter=riscv_compliance_tests.runtest 4 | +hpi.entry=fwrisc_tests.riscv_compliance_main 5 | 6 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32imc/sim/tests/fwrisc_riscv_compliance_rv32i_I-NOP-01.f: -------------------------------------------------------------------------------- 1 | +SW_IMAGE=${BUILD_DIR}/esw/I-NOP-01.elf 2 | +REF_FILE=${PACKAGES_DIR}/riscv-compliance/riscv-test-suite/rv32i/references/I-NOP-01.reference_output 3 | +gtest-filter=riscv_compliance_tests.runtest 4 | +hpi.entry=fwrisc_tests.riscv_compliance_main 5 | 6 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32imc/sim/tests/fwrisc_riscv_compliance_rv32i_I-OR-01.f: -------------------------------------------------------------------------------- 1 | +SW_IMAGE=${BUILD_DIR}/esw/I-OR-01.elf 2 | +REF_FILE=${PACKAGES_DIR}/riscv-compliance/riscv-test-suite/rv32i/references/I-OR-01.reference_output 3 | +gtest-filter=riscv_compliance_tests.runtest 4 | +hpi.entry=fwrisc_tests.riscv_compliance_main 5 | 6 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32imc/sim/tests/fwrisc_riscv_compliance_rv32i_I-ORI-01.f: -------------------------------------------------------------------------------- 1 | +SW_IMAGE=${BUILD_DIR}/esw/I-ORI-01.elf 2 | +REF_FILE=${PACKAGES_DIR}/riscv-compliance/riscv-test-suite/rv32i/references/I-ORI-01.reference_output 3 | +gtest-filter=riscv_compliance_tests.runtest 4 | +hpi.entry=fwrisc_tests.riscv_compliance_main 5 | 6 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32imc/sim/tests/fwrisc_riscv_compliance_rv32i_I-RF_x0-01.f: -------------------------------------------------------------------------------- 1 | +SW_IMAGE=${BUILD_DIR}/esw/I-RF_x0-01.elf 2 | +REF_FILE=${PACKAGES_DIR}/riscv-compliance/riscv-test-suite/rv32i/references/I-RF_x0-01.reference_output 3 | +gtest-filter=riscv_compliance_tests.runtest 4 | +hpi.entry=fwrisc_tests.riscv_compliance_main 5 | 6 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32imc/sim/tests/fwrisc_riscv_compliance_rv32i_I-SB-01.f: -------------------------------------------------------------------------------- 1 | +SW_IMAGE=${BUILD_DIR}/esw/I-SB-01.elf 2 | +REF_FILE=${PACKAGES_DIR}/riscv-compliance/riscv-test-suite/rv32i/references/I-SB-01.reference_output 3 | +gtest-filter=riscv_compliance_tests.runtest 4 | +hpi.entry=fwrisc_tests.riscv_compliance_main 5 | 6 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32imc/sim/tests/fwrisc_riscv_compliance_rv32i_I-SH-01.f: -------------------------------------------------------------------------------- 1 | +SW_IMAGE=${BUILD_DIR}/esw/I-SH-01.elf 2 | +REF_FILE=${PACKAGES_DIR}/riscv-compliance/riscv-test-suite/rv32i/references/I-SH-01.reference_output 3 | +gtest-filter=riscv_compliance_tests.runtest 4 | +hpi.entry=fwrisc_tests.riscv_compliance_main 5 | 6 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32imc/sim/tests/fwrisc_riscv_compliance_rv32i_I-SLL-01.f: -------------------------------------------------------------------------------- 1 | +SW_IMAGE=${BUILD_DIR}/esw/I-SLL-01.elf 2 | +REF_FILE=${PACKAGES_DIR}/riscv-compliance/riscv-test-suite/rv32i/references/I-SLL-01.reference_output 3 | +gtest-filter=riscv_compliance_tests.runtest 4 | +hpi.entry=fwrisc_tests.riscv_compliance_main 5 | 6 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32imc/sim/tests/fwrisc_riscv_compliance_rv32i_I-SLLI-01.f: -------------------------------------------------------------------------------- 1 | +SW_IMAGE=${BUILD_DIR}/esw/I-SLLI-01.elf 2 | +REF_FILE=${PACKAGES_DIR}/riscv-compliance/riscv-test-suite/rv32i/references/I-SLLI-01.reference_output 3 | +gtest-filter=riscv_compliance_tests.runtest 4 | +hpi.entry=fwrisc_tests.riscv_compliance_main 5 | 6 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32imc/sim/tests/fwrisc_riscv_compliance_rv32i_I-SLT-01.f: -------------------------------------------------------------------------------- 1 | +SW_IMAGE=${BUILD_DIR}/esw/I-SLT-01.elf 2 | +REF_FILE=${PACKAGES_DIR}/riscv-compliance/riscv-test-suite/rv32i/references/I-SLT-01.reference_output 3 | +gtest-filter=riscv_compliance_tests.runtest 4 | +hpi.entry=fwrisc_tests.riscv_compliance_main 5 | 6 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32imc/sim/tests/fwrisc_riscv_compliance_rv32i_I-SLTI-01.f: -------------------------------------------------------------------------------- 1 | +SW_IMAGE=${BUILD_DIR}/esw/I-SLTI-01.elf 2 | +REF_FILE=${PACKAGES_DIR}/riscv-compliance/riscv-test-suite/rv32i/references/I-SLTI-01.reference_output 3 | +gtest-filter=riscv_compliance_tests.runtest 4 | +hpi.entry=fwrisc_tests.riscv_compliance_main 5 | 6 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32imc/sim/tests/fwrisc_riscv_compliance_rv32i_I-SLTIU-01.f: -------------------------------------------------------------------------------- 1 | +SW_IMAGE=${BUILD_DIR}/esw/I-SLTIU-01.elf 2 | +REF_FILE=${PACKAGES_DIR}/riscv-compliance/riscv-test-suite/rv32i/references/I-SLTIU-01.reference_output 3 | +gtest-filter=riscv_compliance_tests.runtest 4 | +hpi.entry=fwrisc_tests.riscv_compliance_main 5 | 6 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32imc/sim/tests/fwrisc_riscv_compliance_rv32i_I-SLTU-01.f: -------------------------------------------------------------------------------- 1 | +SW_IMAGE=${BUILD_DIR}/esw/I-SLTU-01.elf 2 | +REF_FILE=${PACKAGES_DIR}/riscv-compliance/riscv-test-suite/rv32i/references/I-SLTU-01.reference_output 3 | +gtest-filter=riscv_compliance_tests.runtest 4 | +hpi.entry=fwrisc_tests.riscv_compliance_main 5 | 6 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32imc/sim/tests/fwrisc_riscv_compliance_rv32i_I-SRA-01.f: -------------------------------------------------------------------------------- 1 | +SW_IMAGE=${BUILD_DIR}/esw/I-SRA-01.elf 2 | +REF_FILE=${PACKAGES_DIR}/riscv-compliance/riscv-test-suite/rv32i/references/I-SRA-01.reference_output 3 | +gtest-filter=riscv_compliance_tests.runtest 4 | +hpi.entry=fwrisc_tests.riscv_compliance_main 5 | 6 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32imc/sim/tests/fwrisc_riscv_compliance_rv32i_I-SRAI-01.f: -------------------------------------------------------------------------------- 1 | +SW_IMAGE=${BUILD_DIR}/esw/I-SRAI-01.elf 2 | +REF_FILE=${PACKAGES_DIR}/riscv-compliance/riscv-test-suite/rv32i/references/I-SRAI-01.reference_output 3 | +gtest-filter=riscv_compliance_tests.runtest 4 | +hpi.entry=fwrisc_tests.riscv_compliance_main 5 | 6 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32imc/sim/tests/fwrisc_riscv_compliance_rv32i_I-SRL-01.f: -------------------------------------------------------------------------------- 1 | +SW_IMAGE=${BUILD_DIR}/esw/I-SRL-01.elf 2 | +REF_FILE=${PACKAGES_DIR}/riscv-compliance/riscv-test-suite/rv32i/references/I-SRL-01.reference_output 3 | +gtest-filter=riscv_compliance_tests.runtest 4 | +hpi.entry=fwrisc_tests.riscv_compliance_main 5 | 6 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32imc/sim/tests/fwrisc_riscv_compliance_rv32i_I-SRLI-01.f: -------------------------------------------------------------------------------- 1 | +SW_IMAGE=${BUILD_DIR}/esw/I-SRLI-01.elf 2 | +REF_FILE=${PACKAGES_DIR}/riscv-compliance/riscv-test-suite/rv32i/references/I-SRLI-01.reference_output 3 | +gtest-filter=riscv_compliance_tests.runtest 4 | +hpi.entry=fwrisc_tests.riscv_compliance_main 5 | 6 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32imc/sim/tests/fwrisc_riscv_compliance_rv32i_I-SUB-01.f: -------------------------------------------------------------------------------- 1 | +SW_IMAGE=${BUILD_DIR}/esw/I-SUB-01.elf 2 | +REF_FILE=${PACKAGES_DIR}/riscv-compliance/riscv-test-suite/rv32i/references/I-SUB-01.reference_output 3 | +gtest-filter=riscv_compliance_tests.runtest 4 | +hpi.entry=fwrisc_tests.riscv_compliance_main 5 | 6 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32imc/sim/tests/fwrisc_riscv_compliance_rv32i_I-SW-01.f: -------------------------------------------------------------------------------- 1 | +SW_IMAGE=${BUILD_DIR}/esw/I-SW-01.elf 2 | +REF_FILE=${PACKAGES_DIR}/riscv-compliance/riscv-test-suite/rv32i/references/I-SW-01.reference_output 3 | +gtest-filter=riscv_compliance_tests.runtest 4 | +hpi.entry=fwrisc_tests.riscv_compliance_main 5 | 6 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32imc/sim/tests/fwrisc_riscv_compliance_rv32i_I-XOR-01.f: -------------------------------------------------------------------------------- 1 | +SW_IMAGE=${BUILD_DIR}/esw/I-XOR-01.elf 2 | +REF_FILE=${PACKAGES_DIR}/riscv-compliance/riscv-test-suite/rv32i/references/I-XOR-01.reference_output 3 | +gtest-filter=riscv_compliance_tests.runtest 4 | +hpi.entry=fwrisc_tests.riscv_compliance_main 5 | 6 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32imc/sim/tests/fwrisc_riscv_compliance_rv32i_I-XORI-01.f: -------------------------------------------------------------------------------- 1 | +SW_IMAGE=${BUILD_DIR}/esw/I-XORI-01.elf 2 | +REF_FILE=${PACKAGES_DIR}/riscv-compliance/riscv-test-suite/rv32i/references/I-XORI-01.reference_output 3 | +gtest-filter=riscv_compliance_tests.runtest 4 | +hpi.entry=fwrisc_tests.riscv_compliance_main 5 | 6 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32imc/sim/tests/fwrisc_zephyr_dhrystone.f: -------------------------------------------------------------------------------- 1 | 2 | +SW_IMAGE=${BUILD_DIR}/esw/zephyr_tests/dhrystone/zephyr/zephyr.elf 3 | +gtest-filter=fwrisc_zephyr_tests.dhrystone 4 | 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32imc/sim/tests/fwrisc_zephyr_hello_world.f: -------------------------------------------------------------------------------- 1 | 2 | +SW_IMAGE=${BUILD_DIR}/esw/zephyr/hello_world/zephyr/zephyr.elf 3 | +gtest-filter=fwrisc_zephyr_tests.hello_world 4 | 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32imc/sim/tests/fwrisc_zephyr_philosophers.f: -------------------------------------------------------------------------------- 1 | 2 | +SW_IMAGE=${BUILD_DIR}/esw/zephyr/philosophers/zephyr/zephyr.elf 3 | +gtest-filter=fwrisc_zephyr_tests.philosophers 4 | 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32imc/sim/tests/fwrisc_zephyr_synchronization.f: -------------------------------------------------------------------------------- 1 | 2 | +SW_IMAGE=${BUILD_DIR}/esw/zephyr/synchronization/zephyr/zephyr.elf 3 | +gtest-filter=fwrisc_zephyr_tests.synchronization 4 | 5 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32imc/tb/tb.F: -------------------------------------------------------------------------------- 1 | 2 | +incdir+. 3 | ./fwrisc_tb_hdl.sv 4 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32imc/tests/dhrystone/dhrystone.mk: -------------------------------------------------------------------------------- 1 | 2 | FWRISC_TESTS_DHRYSTONE_DIR := $(dir $(lastword $(MAKEFILE_LIST))) 3 | 4 | ifneq (1,$(RULES)) 5 | 6 | SRC_DIRS += $(FWRISC_TESTS_DHRYSTONE_DIR) 7 | 8 | else # Rules 9 | 10 | endif 11 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32imc/tests/pyfv-hpi/fwrisc_tests/__init__.py: -------------------------------------------------------------------------------- 1 | 2 | print("Hello from fwrisc_tests") 3 | 4 | from fwrisc_tests.instr import instr_main 5 | from fwrisc_tests.riscv_compliance import riscv_compliance_main -------------------------------------------------------------------------------- /ve/fwrisc_rv32imc/tests/pyfv-hpi/fwrisc_tests/base.py: -------------------------------------------------------------------------------- 1 | ''' 2 | Created on Jun 1, 2019 3 | 4 | @author: ballance 5 | ''' 6 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32imc/tests/tests.F: -------------------------------------------------------------------------------- 1 | +incdir+. 2 | ./fwrisc_tests_pkg.sv 3 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32imc/tests/unit/arith_add.S: -------------------------------------------------------------------------------- 1 | 2 | #include "unit_header.h" 3 | 4 | entry: 5 | li x1, 5 6 | li x2, 6 7 | add x3, x1, x2 8 | j done 9 | 10 | 11 | start_expected: 12 | .word 1, 5 13 | .word 2, 6 14 | .word 3, 11 15 | end_expected: 16 | 17 | 18 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32imc/tests/unit/arith_addi.S: -------------------------------------------------------------------------------- 1 | 2 | #include "unit_header.h" 3 | 4 | entry: 5 | li x1, 5 6 | add x3, x1, 6 7 | j done 8 | 9 | // Expected value for registers 10 | start_expected: 11 | .word 1, 5 12 | .word 3, 11 13 | end_expected: 14 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32imc/tests/unit/arith_addi_neg.S: -------------------------------------------------------------------------------- 1 | 2 | #include "unit_header.h" 3 | 4 | entry: 5 | li x1, 5 6 | add x3, x1, -1 7 | j done 8 | 9 | // Expected value for registers 10 | start_expected: 11 | .word 1, 5 12 | .word 3, 4 13 | end_expected: 14 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32imc/tests/unit/arith_and.S: -------------------------------------------------------------------------------- 1 | 2 | #include "unit_header.h" 3 | 4 | entry: 5 | li x1, 5 6 | li x2, 6 7 | and x3, x1, x2 8 | j done 9 | 10 | 11 | start_expected: 12 | .word 1, 5 13 | .word 2, 6 14 | .word 3, 4 15 | end_expected: 16 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32imc/tests/unit/arith_andi.S: -------------------------------------------------------------------------------- 1 | 2 | #include "unit_header.h" 3 | 4 | entry: 5 | li x1, 5 6 | andi x3, x1, 4 7 | j done 8 | 9 | start_expected: 10 | .word 1, 5 11 | .word 3, 4 // 5&6==4 12 | end_expected: 13 | 14 | 15 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32imc/tests/unit/arith_or.S: -------------------------------------------------------------------------------- 1 | 2 | #include "unit_header.h" 3 | 4 | entry: 5 | li x1, 5 6 | li x2, 6 7 | or x3, x1, x2 8 | j done 9 | 10 | start_expected: 11 | .word 1, 5 12 | .word 2, 6 13 | .word 3, 7 // 5|6==7 14 | end_expected: 15 | 16 | 17 | 18 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32imc/tests/unit/arith_ori.S: -------------------------------------------------------------------------------- 1 | 2 | #include "unit_header.h" 3 | 4 | entry: 5 | li x1, 5 6 | ori x3, x1, 6 7 | j done 8 | 9 | 10 | start_expected: 11 | .word 1, 5 12 | .word 3, 7 // 5|6==7 13 | end_expected: 14 | 15 | 16 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32imc/tests/unit/arith_sll.S: -------------------------------------------------------------------------------- 1 | 2 | #include "unit_header.h" 3 | 4 | entry: 5 | li x1, 5 6 | li x2, 1 7 | sll x3, x2, x1 8 | j done 9 | 10 | start_expected: 11 | .word 1, 5 12 | .word 2, 1 13 | .word 3, (1 << 5) 14 | end_expected: 15 | 16 | 17 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32imc/tests/unit/arith_slli.S: -------------------------------------------------------------------------------- 1 | 2 | #include "unit_header.h" 3 | 4 | entry: 5 | li x1, 1 6 | slli x3, x1, 5 7 | j done 8 | 9 | start_expected: 10 | .word 1, 1 11 | .word 3, (1 << 5) 12 | end_expected: 13 | 14 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32imc/tests/unit/arith_slt_f.S: -------------------------------------------------------------------------------- 1 | 2 | #include "unit_header.h" 3 | 4 | entry: 5 | li x1, 5 6 | li x2, 5 7 | slt x3, x1, x2 8 | j done 9 | 10 | 11 | start_expected: 12 | .word 1, 5 13 | .word 2, 5 14 | .word 3, 0 // !(5<5) 15 | end_expected: 16 | 17 | 18 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32imc/tests/unit/arith_slt_t_neg.S: -------------------------------------------------------------------------------- 1 | 2 | #include "unit_header.h" 3 | 4 | entry: 5 | li x1, -6 6 | li x2, -5 7 | slt x3, x1, x2 8 | j done 9 | 10 | 11 | start_expected: 12 | .word 1, -6 13 | .word 2, -5 14 | .word 3, 1 // -6 < -5 15 | end_expected: 16 | 17 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32imc/tests/unit/arith_slt_t_pos.S: -------------------------------------------------------------------------------- 1 | 2 | #include "unit_header.h" 3 | 4 | entry: 5 | li x1, 5 6 | li x2, 6 7 | slt x3, x1, x2 8 | j done 9 | 10 | start_expected: 11 | .word 1, 5 12 | .word 2, 6 13 | .word 3, 1 // 5 < 6 14 | end_expected: 15 | 16 | 17 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32imc/tests/unit/arith_slti_f.S: -------------------------------------------------------------------------------- 1 | 2 | #include "unit_header.h" 3 | 4 | entry: 5 | li x1, 5 6 | slti x3, x1, 4 7 | j done 8 | 9 | 10 | start_expected: 11 | .word 1, 5 12 | .word 3, 0 // !(5<4) 13 | end_expected: 14 | 15 | 16 | 17 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32imc/tests/unit/arith_slti_t.S: -------------------------------------------------------------------------------- 1 | 2 | #include "unit_header.h" 3 | 4 | 5 | entry: 6 | li x1, 5 7 | slti x3, x1, 6 8 | j done 9 | 10 | 11 | start_expected: 12 | .word 1, 5 13 | .word 3, 1 // (5<6) 14 | end_expected: 15 | 16 | 17 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32imc/tests/unit/arith_sltu_t.S: -------------------------------------------------------------------------------- 1 | 2 | #include "unit_header.h" 3 | 4 | entry: 5 | li x1, 0x80000000 6 | li x2, 0x80000001 7 | sltu x3, x1, x2 8 | j done 9 | 10 | 11 | start_expected: 12 | .word 1, 0x80000000 13 | .word 2, 0x80000001 14 | .word 3, 1 15 | end_expected: 16 | 17 | 18 | 19 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32imc/tests/unit/arith_sra.S: -------------------------------------------------------------------------------- 1 | 2 | #include "unit_header.h" 3 | 4 | entry: 5 | li x1, 4 6 | li x2, 0x80000000 7 | sra x3, x2, x1 8 | j done 9 | 10 | 11 | start_expected: 12 | .word 1, 4 13 | .word 2, 0x80000000 14 | .word 3, 0xF8000000 15 | end_expected: 16 | 17 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32imc/tests/unit/arith_srai.S: -------------------------------------------------------------------------------- 1 | 2 | #include "unit_header.h" 3 | 4 | entry: 5 | li x2, 0x80000000 6 | srai x3, x2, 4 7 | j done 8 | 9 | 10 | start_expected: 11 | .word 2, 0x80000000 12 | .word 3, 0xF8000000 13 | end_expected: 14 | 15 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32imc/tests/unit/arith_srl.S: -------------------------------------------------------------------------------- 1 | 2 | #include "unit_header.h" 3 | 4 | entry: 5 | li x1, 5 6 | li x2, 0x80000000 7 | srl x3, x2, x1 8 | j done 9 | 10 | 11 | start_expected: 12 | .word 1, 5 13 | .word 2, 0x80000000 14 | .word 3, (0x80000000 >> 5) 15 | end_expected: 16 | 17 | 18 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32imc/tests/unit/arith_srli.S: -------------------------------------------------------------------------------- 1 | 2 | #include "unit_header.h" 3 | 4 | entry: 5 | li x2, 0x80000000 6 | srli x3, x2, 5 7 | j done 8 | 9 | 10 | start_expected: 11 | .word 2, 0x80000000 12 | .word 3, (0x80000000 >> 5) 13 | end_expected: 14 | 15 | 16 | 17 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32imc/tests/unit/arith_sub.S: -------------------------------------------------------------------------------- 1 | 2 | #include "unit_header.h" 3 | 4 | entry: 5 | li x1, 5 6 | li x2, 6 7 | sub x3, x2, x1 8 | j done 9 | 10 | 11 | start_expected: 12 | .word 1, 5 13 | .word 2, 6 14 | .word 3, 1 15 | end_expected: 16 | 17 | 18 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32imc/tests/unit/arith_xor.S: -------------------------------------------------------------------------------- 1 | 2 | #include "unit_header.h" 3 | 4 | entry: 5 | li x1, 5 6 | li x2, 6 7 | xor x3, x1, x2 8 | j done 9 | 10 | 11 | start_expected: 12 | .word 1, 5 13 | .word 2, 6 14 | .word 3, 3 15 | end_expected: 16 | 17 | 18 | 19 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32imc/tests/unit/arith_xori.S: -------------------------------------------------------------------------------- 1 | 2 | #include "unit_header.h" 3 | 4 | entry: 5 | li x1, 5 6 | xori x3, x1, 6 7 | j done 8 | 9 | 10 | start_expected: 11 | .word 1, 5 12 | .word 3, 3 13 | end_expected: 14 | 15 | 16 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32imc/tests/unit/long_loop.S: -------------------------------------------------------------------------------- 1 | 2 | #include "unit_header.h" 3 | 4 | entry: 5 | li x1, 0 6 | li x2, 5000000 7 | 1: 8 | addi x1, x1, 1 9 | bne x1, x2, 1b 10 | j done 11 | 12 | 13 | start_expected: 14 | .word 1, 10000000 15 | .word 2, 10000000 16 | end_expected: 17 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32imc/tests/unit/lui.S: -------------------------------------------------------------------------------- 1 | 2 | #include "unit_header.h" 3 | 4 | entry: 5 | lui x1, 5 6 | j done 7 | 8 | // Expected value for registers 9 | start_expected: 10 | .word 1, 0x00005000 11 | end_expected: 12 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32imc/tests/unit/system_csrc.S: -------------------------------------------------------------------------------- 1 | 2 | #include "unit_header.h" 3 | 4 | entry: 5 | li x1, 0xf 6 | li x2, 0x1 7 | csrw mtvec, x1 8 | csrrc x1, mtvec, x2 9 | 10 | j done 11 | 12 | 13 | start_expected: 14 | .word 1, 0x0f 15 | .word 2, 0x01 16 | .word 0x2D, 0x0e 17 | end_expected: 18 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32imc/tests/unit/system_csrr.S: -------------------------------------------------------------------------------- 1 | 2 | #include "unit_header.h" 3 | 4 | entry: 5 | csrr x1, mcause 6 | j done 7 | 8 | 9 | start_expected: 10 | .word 1, 0 11 | .word (0x30+2), 0 12 | end_expected: 13 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32imc/tests/unit/system_csrw.S: -------------------------------------------------------------------------------- 1 | 2 | #include "unit_header.h" 3 | 4 | entry: 5 | li x1, 5 6 | csrw mtvec, x1 7 | csrr x2, mtvec 8 | 9 | j done 10 | 11 | 12 | start_expected: 13 | .word 1, 5 14 | .word 2, 5 15 | .word 0x2d, 5 16 | end_expected: 17 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32imc/tests/unit/system_csrw_csrr.S: -------------------------------------------------------------------------------- 1 | 2 | #include "unit_header.h" 3 | 4 | entry: 5 | li x1, 5 6 | csrw medeleg, x1 7 | csrr x2, medeleg 8 | 9 | j done 10 | 11 | 12 | start_expected: 13 | .word 0x01, 5 14 | .word 0x02, 5 15 | .word (0x28+2), 5 16 | end_expected: 17 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32imc/tests/unit/unit.ld: -------------------------------------------------------------------------------- 1 | 2 | OUTPUT_ARCH("riscv") 3 | ENTRY(_start) 4 | 5 | SECTIONS 6 | { 7 | . = 0x80000000; 8 | .text.init : { *(.text.init) } 9 | . = ALIGN(0x1000); 10 | _end = .; 11 | } 12 | 13 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32imc_fpga/sim/.simscripts: -------------------------------------------------------------------------------- 1 | sim=vl 2 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32imc_fpga/sim/mk_testlist.sh: -------------------------------------------------------------------------------- 1 | 2 | test="" 3 | 4 | while read line; do 5 | is_category=`echo $line | sed -e 's/^.*\.$/true/g'` 6 | if test "x$is_category" = "xtrue"; then 7 | test=$line 8 | else 9 | echo "${test}${line}" 10 | fi 11 | done 12 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32imc_fpga/sim/scripts/vlog_hdl.f: -------------------------------------------------------------------------------- 1 | 2 | -f ${MEMORY_PRIMITIVES}/rtl/sim/sim.f 3 | 4 | -f ${FWRISC}/rtl/fwrisc.f 5 | -f ${FWRISC}/soc/fwrisc_soc.f 6 | +incdir+${FWRISC}/ve/fwrisc_tracer_bfm 7 | ${FWRISC}/ve/fwrisc_tracer_bfm/fwrisc_tracer_bfm.sv 8 | -F ${FWRISC}/ve/fwrisc_rv32imc_fpga/tb/tb.F 9 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32imc_fpga/sim/scripts/vlog_hvl.f: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Featherweight-IP/fwrisc/0e21466336c9d611c2b465dcb0de04572b6ebbcf/ve/fwrisc_rv32imc_fpga/sim/scripts/vlog_hvl.f -------------------------------------------------------------------------------- /ve/fwrisc_rv32imc_fpga/sim/tests/fwrisc_fpga_led_flash.f: -------------------------------------------------------------------------------- 1 | 2 | +SW_IMAGE=${BUILD_DIR}/esw/led_flash.elf 3 | --gtest_filter=fwrisc_fpga_tests.led_flash 4 | 5 | 6 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32imc_fpga/sim/tests/fwrisc_fpga_memtest.f: -------------------------------------------------------------------------------- 1 | 2 | +SW_IMAGE=${BUILD_DIR}/esw/memtest.elf 3 | --gtest_filter=fwrisc_fpga_tests.memtest 4 | 5 | 6 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32imc_fpga/sim/tests/fwrisc_fpga_zephyr_hello_world.f: -------------------------------------------------------------------------------- 1 | 2 | +SW_IMAGE=${BUILD_DIR}/esw/zephyr/hello_world/zephyr/zephyr.elf 3 | --gtest_filter=fwrisc_fpga_tests.zephyr_hello_world 4 | 5 | 6 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32imc_fpga/tb/tb.F: -------------------------------------------------------------------------------- 1 | +incdir+. 2 | ./fwrisc_fpga_tb_hdl.sv 3 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32imc_fpga/tests/sw/baremetal.ld: -------------------------------------------------------------------------------- 1 | 2 | OUTPUT_ARCH("riscv") 3 | ENTRY(_start) 4 | 5 | SECTIONS 6 | { 7 | . = 0x80000000; 8 | .text.init : { *(.text.init) } 9 | . = ALIGN(0x1000); 10 | _end = .; 11 | 12 | } 13 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32imc_fpga/tests/sw/fwrisc_fpga_tests_sw.mk: -------------------------------------------------------------------------------- 1 | 2 | FWRISC_FPGA_TESTS_SW_DIR := $(dir $(lastword $(MAKEFILE_LIST))) 3 | 4 | ifneq (1,$(RULES)) 5 | 6 | SRC_DIRS += $(FWRISC_FPGA_TESTS_SW_DIR) 7 | 8 | else # Rules 9 | 10 | endif 11 | -------------------------------------------------------------------------------- /ve/fwrisc_rv32imc_fpga/tests/sw/led_flash.S: -------------------------------------------------------------------------------- 1 | 2 | .section .text.init; 3 | 4 | .globl _start 5 | _start: 6 | li x1, 0xc0000000; 7 | li x2, 0x0 8 | li x4, 0x80002000; 9 | sb x2, 0(x4) 10 | 1: 11 | lb x3, 0(x4) 12 | sw x3, 0(x1) 13 | addi x3, x3, 1 14 | sb x3, 0(x4) 15 | j 1b 16 | nop 17 | 18 | -------------------------------------------------------------------------------- /ve/fwrisc_tracer_bfm/pyfv-hpi/fwrisc_tracer_bfm/__init__.py: -------------------------------------------------------------------------------- 1 | 2 | print("loading fwrisc_tracer_bfm") 3 | from fwrisc_tracer_bfm import fwrisc_tracer_bfm -------------------------------------------------------------------------------- /ve/fwrisc_tracer_bfm/pyfv-hpi/fwrisc_tracer_bfm/__pycache__/__init__.cpython-36.pyc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Featherweight-IP/fwrisc/0e21466336c9d611c2b465dcb0de04572b6ebbcf/ve/fwrisc_tracer_bfm/pyfv-hpi/fwrisc_tracer_bfm/__pycache__/__init__.cpython-36.pyc -------------------------------------------------------------------------------- /ve/fwrisc_tracer_bfm/pyfv-hpi/fwrisc_tracer_bfm/__pycache__/fwrisc_tracer_bfm.cpython-36.pyc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Featherweight-IP/fwrisc/0e21466336c9d611c2b465dcb0de04572b6ebbcf/ve/fwrisc_tracer_bfm/pyfv-hpi/fwrisc_tracer_bfm/__pycache__/fwrisc_tracer_bfm.cpython-36.pyc -------------------------------------------------------------------------------- /ve/fwrisc_tracer_bfm/rv32_tracer.f: -------------------------------------------------------------------------------- 1 | 2 | +incdir+${FWRISC}/ve/rv32_tracer 3 | ${FWRISC}/ve/rv32_tracer/rv32_tracer_bfm.sv 4 | -------------------------------------------------------------------------------- /ve/fwrisc_tracer_bfm/src/fwrisc_tracer_bfm/__init__.py: -------------------------------------------------------------------------------- 1 | 2 | from fwrisc_tracer_bfm.fwrisc_tracer_bfm import * 3 | from fwrisc_tracer_bfm.fwrisc_tracer_bfm_if import * -------------------------------------------------------------------------------- /ve/sve.F: -------------------------------------------------------------------------------- 1 | 2 | -F ./fwrisc_exec_formal/sve.F -------------------------------------------------------------------------------- /ve/ve.F: -------------------------------------------------------------------------------- 1 | 2 | -f ./rv32_tracer/rv32_tracer.f 3 | -F ./fwrisc/fwrisc.F 4 | -F ./fwrisc_exec_formal/sve.F 5 | 6 | 7 | --------------------------------------------------------------------------------