├── .gitignore ├── LICENSE ├── README.md ├── apu.vhd ├── audio_pll.bsf ├── audio_pll.cmp ├── audio_pll.ppf ├── audio_pll.qip ├── audio_pll.sip ├── audio_pll.spd ├── audio_pll.vhd ├── audio_pll ├── audio_pll_0002.qip └── audio_pll_0002.v ├── audio_pll_sim.f ├── audio_pll_sim ├── aldec │ └── rivierapro_setup.tcl ├── audio_pll.vho ├── cadence │ ├── cds.lib │ ├── hdl.var │ └── ncsim_setup.sh ├── mentor │ └── msim_setup.tcl └── synopsys │ └── vcsmx │ ├── synopsys_sim.setup │ └── vcsmx_setup.sh ├── biquad.vhd ├── common.vhd ├── cpu.vhd ├── data_path.vhd ├── datamem.cmp ├── datamem.qip ├── datamem.vhd ├── debounce.vhd ├── doc ├── IMG_0918.jpeg ├── IMG_0919.jpeg ├── IMG_0920.jpeg ├── IMG_1074.jpeg ├── IMG_1418.jpeg ├── IMG_1419.jpeg └── nes-signal-timings │ ├── 2006 write to PPU A13 output │ ├── 0clk.JPG │ ├── 1clk.JPG │ ├── 2clk.JPG │ └── 3clk.JPG │ ├── CPU cycle timing.txt │ ├── PPU address change vs vbl │ ├── 3dot-2clk.JPG │ ├── 3dot-3clk.JPG │ ├── 4dot-0clk.JPG │ ├── 4dot-1clk.JPG │ ├── 4dot-2clk.JPG │ └── 4dot-3clk.JPG │ ├── enable nmi around vbl end │ ├── 6818dot 2clk nmi.JPG │ ├── 6818dot 3clk nmi.JPG │ ├── 6819dot 0clk.JPG │ └── 6819dot 1clk.JPG │ ├── misc │ ├── 2002 D7 read.JPG │ ├── CPU data out.JPG │ ├── PHI2.JPG │ ├── PPU CE.JPG │ └── PRG CE.JPG │ ├── nmi after 2002 read before vbl │ ├── -2dot 0clk nmi.JPG │ ├── -2dot 1clk nmi.JPG │ ├── -2dot 2clk no nmi.JPG │ ├── -3dot 2clk nmi.JPG │ └── -3dot 3clk nmi.JPG │ ├── nmi detection time │ ├── 1dot 2clk no nmi.JPG │ └── 1dot 3clk nmi.JPG │ ├── read 2002 around vbl begin │ ├── +0dot+0clk 80.JPG │ ├── +0dot+1clk 80.JPG │ ├── +0dot+2clk 80.JPG │ ├── +0dot+3clk 80.JPG │ ├── -1dot+2clk 00.JPG │ └── -1dot+3clk 00.JPG │ ├── read 2002 around vbl end │ ├── 6819dot 1clk 80.JPG │ ├── 6819dot 2clk 80.JPG │ ├── 6819dot 3clk 80.JPG │ ├── 6820dot 0clk 00.JPG │ └── 6820dot 1clk 00.JPG │ ├── read latch time │ ├── 2clk 80.JPG │ ├── 3clk 00.JPG │ ├── 4clk 00.JPG │ └── 5clk 00.JPG │ ├── terms.txt │ └── timing pictures.txt ├── frmmem.cmp ├── frmmem.qip ├── frmmem.vhd ├── hex_digit.vhd ├── i2c.vhd ├── i2c_master.vhd ├── i2s.vhd ├── master_ctrl.vhd ├── master_pll.bsf ├── master_pll.cmp ├── master_pll.ppf ├── master_pll.qip ├── master_pll.sip ├── master_pll.spd ├── master_pll.vhd ├── master_pll ├── master_pll_0002.qip └── master_pll_0002.v ├── master_pll_sim.f ├── master_pll_sim ├── aldec │ └── rivierapro_setup.tcl ├── cadence │ ├── cds.lib │ ├── hdl.var │ └── ncsim_setup.sh ├── master_pll.vho ├── mentor │ └── msim_setup.tcl └── synopsys │ └── vcsmx │ ├── synopsys_sim.setup │ └── vcsmx_setup.sh ├── master_reconfig.bsf ├── master_reconfig.cmp ├── master_reconfig.ppf ├── master_reconfig.qip ├── master_reconfig.sip ├── master_reconfig.spd ├── master_reconfig.vhd ├── master_reconfig ├── altera_pll_reconfig_core.v ├── altera_pll_reconfig_top.v └── altera_std_synchronizer.v ├── master_reconfig_sim.f ├── master_reconfig_sim ├── aldec │ └── rivierapro_setup.tcl ├── altera_pll_reconfig │ ├── altera_pll_reconfig_core.v │ ├── altera_pll_reconfig_top.v │ └── altera_std_synchronizer.v ├── cadence │ ├── cds.lib │ ├── cds_libs │ │ └── master_reconfig.cds.lib │ ├── hdl.var │ └── ncsim_setup.sh ├── master_reconfig.vhd ├── mentor │ └── msim_setup.tcl └── synopsys │ └── vcsmx │ ├── synopsys_sim.setup │ └── vcsmx_setup.sh ├── nes.cdf ├── nes.cof ├── nes.qpf ├── nes.qsf ├── nes.sdc ├── nes.vhd ├── nes_assignment_defaults.qdf ├── periphery_ctrl.vhd ├── pixel_pll ├── pixel_pll_0002.qip └── pixel_pll_0002.v ├── pixel_pll_sim ├── aldec │ └── rivierapro_setup.tcl ├── cadence │ ├── cds.lib │ ├── hdl.var │ └── ncsim_setup.sh ├── mentor │ └── msim_setup.tcl ├── pixel_pll.vho └── synopsys │ └── vcsmx │ ├── synopsys_sim.setup │ └── vcsmx_setup.sh ├── ppu.vhd ├── progmem.cmp ├── progmem.qip ├── progmem.vhd ├── sequencer.vhd ├── soamem.cmp ├── soamem.qip ├── soamem.vhd ├── spritemem.cmp ├── spritemem.qip ├── spritemem.vhd ├── stp.stp ├── vga.vhd ├── vga_pll.bsf ├── vga_pll.cmp ├── vga_pll.ppf ├── vga_pll.qip ├── vga_pll.sip ├── vga_pll.spd ├── vga_pll.vhd ├── vga_pll ├── vga_pll_0002.qip └── vga_pll_0002.v ├── vga_pll_sim.f ├── vga_pll_sim ├── aldec │ └── rivierapro_setup.tcl ├── cadence │ ├── cds.lib │ ├── hdl.var │ └── ncsim_setup.sh ├── mentor │ └── msim_setup.tcl ├── synopsys │ └── vcsmx │ │ ├── synopsys_sim.setup │ │ └── vcsmx_setup.sh └── vga_pll.vho ├── videomem.cmp ├── videomem.qip ├── videomem.vhd ├── videorom.cmp ├── videorom.qip └── videorom.vhd /.gitignore: -------------------------------------------------------------------------------- 1 | simulation/ 2 | incremental_db/ 3 | db/ 4 | .qsys_edit/ 5 | output_files/ 6 | greybox_tmp/ 7 | *.rpt 8 | *.bak 9 | PLLJ_PLLSPE_INFO.txt 10 | c5_pin_model_dump.txt 11 | *.pof 12 | test_modules/ 13 | nes.map 14 | *.hex 15 | nes_description.txt 16 | output_file.map 17 | nes.qws 18 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # fpgaNES 2 | 3 | This is an implementation of the Nintendo Entertainment System in an FPGA. 4 | 5 | It is based on the development board Cyclone V GX Starter Kit by Terasic with an 6 | Altera Cyclone V on board. It features plenty of memory, an HDMI out and an analog 7 | Audio Codec. For some reason they decided to not connect the HDMI audio pins of the 8 | ADV7513 HDMI chip to the FPGA. But kindly they added solder points for the audio pins 9 | so i was able to access them trough some GPIO pins of the FPGA getting 44.1 kHz Audio 10 | directly through the HDMI connection. The hdmi video resolution is 640x480 at a 11 | framerate of 50 Hz having 2x2 display pixels per NES pixel. Beside the HDMI audio pins i 12 | soldered a NES Four Score to the GPIO-Port to simply plug/unplug the controllers to the 13 | FPGA. 14 | 15 | The following tests are from http://wiki.nesdev.com/w/index.php/Emulator_tests. 16 | 17 | Test Results: 18 | 19 | CPU) 20 | - cpu_interrupts_v2 (5/5) 21 | - instr_misc (2/4) : 03-dummy_reads, 04_dummy_reads_apu 22 | - instr_timing (1/2) : 1-instr_timing (because illegal opcodes not supported yet) 23 | - instr_test-v5 (16/16) : OFFICIAL Opcodes only 24 | - cpu_dummy_reads (1/1) 25 | 26 | PPU) 27 | - oam_read (1/1) 28 | - oam_stress (1/1) 29 | - ppu_sprite_hit (10/10) 30 | - ppu_open_bus (1/1) 31 | - ppu_vbl_nmi (10/10) 32 | - ppu_sprite_overflow (4/5) : 05-emulator 33 | 34 | APU) 35 | - blargg_apu_2005.07.30 (10/11) : 09.reset_timing 36 | - apu_test (8/8) 37 | - apu_mixer (2/4) : noise, triangle 38 | - dmc_dma_during_read4 (1/5) : dma_2007_read, dma_2007_write, dma_4016_read, read_write_2007 39 | - square_timer_div2 (1/1) 40 | - test_apu_env (1/1) 41 | - test_apu_sweep (2/2) 42 | - test_apu_timers (4/4) 43 | - test_tri_lin_ctr (?/1) UNSURE 44 | 45 | 46 | What works: 47 | 48 | - https://github.com/Klaus2m5/6502_65C02_functional_tests 49 | - Super Mario Brothers 1 50 | - Super Mario Brothers 2 51 | - Super Mario Brothers 3 52 | - Mario Bros. Classic 53 | - Mario & Yoshi 54 | - Donkey Kong 55 | - The Smurfs 56 | - Metroid 57 | - Megaman 1-6 58 | 59 | 60 | What works a little bit 61 | 62 | - Micro Machines (various glitches) 63 | - Battletoads (various glitches) 64 | 65 | 66 | What is currently not implemented: 67 | 68 | - low / high pass filter (i added both with the equations blargg published but for some reason they don’t work) 69 | 70 | 71 | # How to load games with this solution 72 | 73 | To start a game (or test rom) there are two solutions to achieve this. Either by simulating the gamepak logic within the fpga which is very simple especially for the early (and more simple) gamepaks e.g. Super Mario Brothers 1 / Donkey Kong and so on. The other way is to build some kind of hardware adapter to connect the gamepak (based on 5V logic) to the fpga, which is in my case 3.3V logic. Since i always wanted to play with the original gamepaks i decided to go with the apdapter solution. 74 | 75 | ### First adapter board 76 | My first solution was based on 8x SN74LVC8T245DWR logic level shifters on a piece of perfboard, but since my knowledge about electronics is very limited i missed things like serial. 77 | termination of the bus lines and short traces of the decoupling caps. 78 | 79 | 80 | A picture of the adapter board connected to the devkit board. It also utilizes the GPIO-HSTC daughter board from Terrasic to get more gpio pins on this standard 40 pin header. 81 | 82 | ![First adapter board connected to dekit](doc/IMG_0918.jpeg) 83 | 84 | 85 | Top of the board: 86 | 87 | ![First adapter top](doc/IMG_0919.jpeg) 88 | 89 | 90 | Bottom of the board: 91 | 92 | ![First adapter bottom](doc/IMG_0920.jpeg) 93 | 94 | 95 | This solution worked well for simple gamepaks like Super Mario Brothers 1 which don't write back the gamepak to switch rom banks for example. Dr. Mario worked, but with various glitches and more complex gamepaks like Super Mario Brothers 3 simply didn't start. 96 | 97 | ### Second adapter board 98 | But since i wanted to also run the more complex gamepaks **and** use an universal gamepak with a sdcard slot to bring the fantastic tests roms from http://www.nesdev.com to my fpgaNES to find all the small inaccuracies and bugs in my solution i needed a better adapter board, which means i had to improve my electronics and soldering skills. 99 | 100 | 101 | This is a picture of my second adapter board which uses much shorter cables and the pcb was made by a manufacturer. This solution worked quite well, more advanced gamepaks like Dr. Mario and Mario Brothers 3 works flawlessly (except for the bugs in my vhdl code) and i could run test roms from the EverDrive N8 game pak. 102 | 103 | ![Second adapter board connect to dekit](doc/IMG_1074.jpeg) 104 | 105 | 106 | ### Third adapter board 107 | Here you can see my third adapter board. This board have a Samtex QSH-090-01-L-D-A connector so i don't need the GPIO-HSTC daughter board and directly connect to the devkit board and added ports for the original game controllers. 108 | 109 | #### Side view 110 | 111 | ![Adapter PCB with inserted EverDrive N8 Cardridge](doc/IMG_1418.jpeg) 112 | 113 | #### Top view 114 | 115 | ![Adapter PCB attached to Cyclone V devkit board](doc/IMG_1419.jpeg) 116 | 117 | 118 | ### Current status 119 | It seems i made some mistakes with my third adapter board i didn't find so far. Original gamepaks works great, no problems so far but the EverDrive N8 don't want to work any more. When i compare the signals of an original gamepak with the signals of the EverDrive N8 on my scope, i can see that orignal gamepaks produce since and clean 5V signals whereas the EverDrive N8 sometimes produce more unclean signals near 3.3V. I have to investigate further to find a solution. 120 | 121 | At the moment the layout of the board is done in eagle. After i found by bugs i will switch to kicad to release it here for interested ones. 122 | -------------------------------------------------------------------------------- /audio_pll.bsf: -------------------------------------------------------------------------------- 1 | /* 2 | WARNING: Do NOT edit the input and output ports in this file in a text 3 | editor if you plan to continue editing the block that represents it in 4 | the Block Editor! File corruption is VERY likely to occur. 5 | */ 6 | /* 7 | Copyright (C) 2018 Intel Corporation. All rights reserved. 8 | Your use of Intel Corporation's design tools, logic functions 9 | and other software and tools, and its AMPP partner logic 10 | functions, and any output files from any of the foregoing 11 | (including device programming or simulation files), and any 12 | associated documentation or information are expressly subject 13 | to the terms and conditions of the Intel Program License 14 | Subscription Agreement, the Intel Quartus Prime License Agreement, 15 | the Intel FPGA IP License Agreement, or other applicable license 16 | agreement, including, without limitation, that your use is for 17 | the sole purpose of programming logic devices manufactured by 18 | Intel and sold by Intel or its authorized distributors. Please 19 | refer to the applicable agreement for further details. 20 | */ 21 | (header "symbol" (version "1.1")) 22 | (symbol 23 | (rect 0 0 160 144) 24 | (text "audio_pll" (rect 55 -1 88 11)(font "Arial" (font_size 10))) 25 | (text "inst" (rect 8 128 20 140)(font "Arial" )) 26 | (port 27 | (pt 0 72) 28 | (input) 29 | (text "refclk" (rect 0 0 22 12)(font "Arial" (font_size 8))) 30 | (text "refclk" (rect 4 61 40 72)(font "Arial" (font_size 8))) 31 | (line (pt 0 72)(pt 48 72)(line_width 1)) 32 | ) 33 | (port 34 | (pt 0 112) 35 | (input) 36 | (text "rst" (rect 0 0 10 12)(font "Arial" (font_size 8))) 37 | (text "rst" (rect 4 101 22 112)(font "Arial" (font_size 8))) 38 | (line (pt 0 112)(pt 48 112)(line_width 1)) 39 | ) 40 | (port 41 | (pt 160 72) 42 | (output) 43 | (text "outclk_0" (rect 0 0 33 12)(font "Arial" (font_size 8))) 44 | (text "outclk_0" (rect 117 61 165 72)(font "Arial" (font_size 8))) 45 | (line (pt 160 72)(pt 112 72)(line_width 1)) 46 | ) 47 | (port 48 | (pt 160 112) 49 | (output) 50 | (text "locked" (rect 0 0 24 12)(font "Arial" (font_size 8))) 51 | (text "locked" (rect 127 101 163 112)(font "Arial" (font_size 8))) 52 | (line (pt 160 112)(pt 112 112)(line_width 1)) 53 | ) 54 | (drawing 55 | (text "refclk" (rect 16 43 68 99)(font "Arial" (color 128 0 0)(font_size 9))) 56 | (text "clk" (rect 53 67 124 144)(font "Arial" (color 0 0 0))) 57 | (text "reset" (rect 19 83 68 179)(font "Arial" (color 128 0 0)(font_size 9))) 58 | (text "reset" (rect 53 107 136 224)(font "Arial" (color 0 0 0))) 59 | (text "outclk0" (rect 113 43 268 99)(font "Arial" (color 128 0 0)(font_size 9))) 60 | (text "clk" (rect 97 67 212 144)(font "Arial" (color 0 0 0))) 61 | (text "locked" (rect 113 83 262 179)(font "Arial" (color 128 0 0)(font_size 9))) 62 | (text "export" (rect 82 107 200 224)(font "Arial" (color 0 0 0))) 63 | (text " altera_pll " (rect 118 128 308 266)(font "Arial" )) 64 | (line (pt 48 32)(pt 112 32)(line_width 1)) 65 | (line (pt 112 32)(pt 112 128)(line_width 1)) 66 | (line (pt 48 128)(pt 112 128)(line_width 1)) 67 | (line (pt 48 32)(pt 48 128)(line_width 1)) 68 | (line (pt 49 52)(pt 49 76)(line_width 1)) 69 | (line (pt 50 52)(pt 50 76)(line_width 1)) 70 | (line (pt 49 92)(pt 49 116)(line_width 1)) 71 | (line (pt 50 92)(pt 50 116)(line_width 1)) 72 | (line (pt 111 52)(pt 111 76)(line_width 1)) 73 | (line (pt 110 52)(pt 110 76)(line_width 1)) 74 | (line (pt 111 92)(pt 111 116)(line_width 1)) 75 | (line (pt 110 92)(pt 110 116)(line_width 1)) 76 | (line (pt 0 0)(pt 160 0)(line_width 1)) 77 | (line (pt 160 0)(pt 160 144)(line_width 1)) 78 | (line (pt 0 144)(pt 160 144)(line_width 1)) 79 | (line (pt 0 0)(pt 0 144)(line_width 1)) 80 | ) 81 | ) 82 | -------------------------------------------------------------------------------- /audio_pll.cmp: -------------------------------------------------------------------------------- 1 | component audio_pll is 2 | port ( 3 | refclk : in std_logic := 'X'; -- clk 4 | rst : in std_logic := 'X'; -- reset 5 | outclk_0 : out std_logic; -- clk 6 | locked : out std_logic -- export 7 | ); 8 | end component audio_pll; 9 | 10 | -------------------------------------------------------------------------------- /audio_pll.ppf: -------------------------------------------------------------------------------- 1 | 2 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | -------------------------------------------------------------------------------- /audio_pll.sip: -------------------------------------------------------------------------------- 1 | set_global_assignment -entity "audio_pll" -library "lib_audio_pll" -name IP_TOOL_NAME "altera_pll" 2 | set_global_assignment -entity "audio_pll" -library "lib_audio_pll" -name IP_TOOL_VERSION "18.0" 3 | set_global_assignment -entity "audio_pll" -library "lib_audio_pll" -name IP_TOOL_ENV "mwpim" 4 | set_global_assignment -library "lib_audio_pll" -name SPD_FILE [file join $::quartus(sip_path) "audio_pll.spd"] 5 | 6 | set_global_assignment -library "lib_audio_pll" -name MISC_FILE [file join $::quartus(sip_path) "audio_pll_sim/audio_pll.vho"] 7 | -------------------------------------------------------------------------------- /audio_pll.spd: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | -------------------------------------------------------------------------------- /audio_pll/audio_pll_0002.qip: -------------------------------------------------------------------------------- 1 | set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to "*audio_pll_0002*|altera_pll:altera_pll_i*|*" 2 | 3 | set_instance_assignment -name PLL_AUTO_RESET OFF -to "*audio_pll_0002*|altera_pll:altera_pll_i*|*" 4 | set_instance_assignment -name PLL_BANDWIDTH_PRESET AUTO -to "*audio_pll_0002*|altera_pll:altera_pll_i*|*" 5 | -------------------------------------------------------------------------------- /audio_pll/audio_pll_0002.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns/10ps 2 | module audio_pll_0002( 3 | 4 | // interface 'refclk' 5 | input wire refclk, 6 | 7 | // interface 'reset' 8 | input wire rst, 9 | 10 | // interface 'outclk0' 11 | output wire outclk_0, 12 | 13 | // interface 'locked' 14 | output wire locked 15 | ); 16 | 17 | altera_pll #( 18 | .fractional_vco_multiplier("false"), 19 | .reference_clock_frequency("50.0 MHz"), 20 | .operation_mode("direct"), 21 | .number_of_clocks(1), 22 | .output_clock_frequency0("11.288888 MHz"), 23 | .phase_shift0("0 ps"), 24 | .duty_cycle0(50), 25 | .output_clock_frequency1("0 MHz"), 26 | .phase_shift1("0 ps"), 27 | .duty_cycle1(50), 28 | .output_clock_frequency2("0 MHz"), 29 | .phase_shift2("0 ps"), 30 | .duty_cycle2(50), 31 | .output_clock_frequency3("0 MHz"), 32 | .phase_shift3("0 ps"), 33 | .duty_cycle3(50), 34 | .output_clock_frequency4("0 MHz"), 35 | .phase_shift4("0 ps"), 36 | .duty_cycle4(50), 37 | .output_clock_frequency5("0 MHz"), 38 | .phase_shift5("0 ps"), 39 | .duty_cycle5(50), 40 | .output_clock_frequency6("0 MHz"), 41 | .phase_shift6("0 ps"), 42 | .duty_cycle6(50), 43 | .output_clock_frequency7("0 MHz"), 44 | .phase_shift7("0 ps"), 45 | .duty_cycle7(50), 46 | .output_clock_frequency8("0 MHz"), 47 | .phase_shift8("0 ps"), 48 | .duty_cycle8(50), 49 | .output_clock_frequency9("0 MHz"), 50 | .phase_shift9("0 ps"), 51 | .duty_cycle9(50), 52 | .output_clock_frequency10("0 MHz"), 53 | .phase_shift10("0 ps"), 54 | .duty_cycle10(50), 55 | .output_clock_frequency11("0 MHz"), 56 | .phase_shift11("0 ps"), 57 | .duty_cycle11(50), 58 | .output_clock_frequency12("0 MHz"), 59 | .phase_shift12("0 ps"), 60 | .duty_cycle12(50), 61 | .output_clock_frequency13("0 MHz"), 62 | .phase_shift13("0 ps"), 63 | .duty_cycle13(50), 64 | .output_clock_frequency14("0 MHz"), 65 | .phase_shift14("0 ps"), 66 | .duty_cycle14(50), 67 | .output_clock_frequency15("0 MHz"), 68 | .phase_shift15("0 ps"), 69 | .duty_cycle15(50), 70 | .output_clock_frequency16("0 MHz"), 71 | .phase_shift16("0 ps"), 72 | .duty_cycle16(50), 73 | .output_clock_frequency17("0 MHz"), 74 | .phase_shift17("0 ps"), 75 | .duty_cycle17(50), 76 | .pll_type("General"), 77 | .pll_subtype("General") 78 | ) altera_pll_i ( 79 | .rst (rst), 80 | .outclk ({outclk_0}), 81 | .locked (locked), 82 | .fboutclk ( ), 83 | .fbclk (1'b0), 84 | .refclk (refclk) 85 | ); 86 | endmodule 87 | 88 | -------------------------------------------------------------------------------- /audio_pll_sim.f: -------------------------------------------------------------------------------- 1 | audio_pll_sim/audio_pll.vho 2 | -------------------------------------------------------------------------------- /audio_pll_sim/cadence/cds.lib: -------------------------------------------------------------------------------- 1 | 2 | DEFINE std $CDS_ROOT/tools/inca/files/STD/ 3 | DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/ 4 | DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/ 5 | DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/ 6 | DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/ 7 | DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/ 8 | DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/ 9 | DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/ 10 | DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/ 11 | DEFINE work ./libraries/work/ 12 | DEFINE altera ./libraries/altera/ 13 | DEFINE lpm ./libraries/lpm/ 14 | DEFINE sgate ./libraries/sgate/ 15 | DEFINE altera_mf ./libraries/altera_mf/ 16 | DEFINE altera_lnsim ./libraries/altera_lnsim/ 17 | DEFINE cyclonev ./libraries/cyclonev/ 18 | -------------------------------------------------------------------------------- /audio_pll_sim/cadence/hdl.var: -------------------------------------------------------------------------------- 1 | 2 | DEFINE WORK work 3 | -------------------------------------------------------------------------------- /audio_pll_sim/synopsys/vcsmx/synopsys_sim.setup: -------------------------------------------------------------------------------- 1 | 2 | WORK > DEFAULT 3 | DEFAULT: ./libraries/work/ 4 | work: ./libraries/work/ 5 | altera: ./libraries/altera/ 6 | lpm: ./libraries/lpm/ 7 | sgate: ./libraries/sgate/ 8 | altera_mf: ./libraries/altera_mf/ 9 | altera_lnsim: ./libraries/altera_lnsim/ 10 | cyclonev: ./libraries/cyclonev/ 11 | LIBRARY_SCAN = TRUE 12 | -------------------------------------------------------------------------------- /common.vhd: -------------------------------------------------------------------------------- 1 | /* 2 | This file is part of fpgaNES. 3 | 4 | fpgaNES is free software: you can redistribute it and/or modify 5 | it under the terms of the GNU General Public License as published by 6 | the Free Software Foundation, either version 3 of the License, or 7 | (at your option) any later version. 8 | 9 | fpgaNES is distributed in the hope that it will be useful, 10 | but WITHOUT ANY WARRANTY; without even the implied warranty of 11 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 | GNU General Public License for more details. 13 | 14 | You should have received a copy of the GNU General Public License 15 | along with fpgaNES. If not, see . 16 | */ 17 | 18 | library ieee; 19 | use ieee.std_logic_1164.all; 20 | use ieee.std_logic_unsigned.all; 21 | use ieee.numeric_std.all; 22 | 23 | package common is 24 | 25 | type flags_t is record 26 | n : std_logic; 27 | v : std_logic; 28 | d : std_logic; 29 | i : std_logic; 30 | z : std_logic; 31 | c : std_logic; 32 | end record; 33 | 34 | type mode_t is (imp, imm, acc, zpn, zpx, zpy, abn, abx, aby, inx, iny, ind, rel); 35 | type instruction_t is (unk, nop, lda, ldx, ldy, tax, tay, txa, tya, tsx, txs, clc, cli, clv, cld, secr, sed, sei, adc, sbc, inc, inx, iny, dec, dex, dey, cpx, cpy, bcc, bcs, beq, bne, bmi, bpl, bvc, bvs, jsr, rts, rti, ora, and_i, eor, cmp, sta, stx, sty, pha, php, pla, plp, rol_i, ror_i, lsr, asl, jmp, bit_i, brk); 36 | 37 | type pc_op_t is (nop, inc, split, pla, pha, daq, enb); 38 | type in_op_t is (nop, ena, alq, ald, fff); 39 | type out_op_t is (nop, ena, din, pch, pcl, arg, xrg, yrg, flg); 40 | type reg_op_t is (nop, arg, xrg, yrg, srg); 41 | type alu_op_t is (psa, add, adc, sub, sbc, ada, ora, eor, rla, rra, lsr, asl); 42 | type addr_op_t is (nop, zaq, daq, aqd, div, oaq, oad, zvl, adv, vaq); 43 | type ctrl_op_t is (nop, alc, bcc, bcs, beq, bne, bmi, bpl, bvc, bvs, don); 44 | type flags_op_t is (nop, din, nz, nzc, nzv, nvzc, clc, cli, clv, cld, stc, sed, sei); 45 | type alu_inp_t is (din, val, arg, xrg, yrg, srg, one, pcl, pch, aci, alq, auc, brk); 46 | 47 | type video_mode_t is (ntsc, pal); 48 | 49 | -- Constants 50 | constant N_FLAG : integer := 7; 51 | constant V_FLAG : integer := 6; 52 | constant D_FLAG : integer := 3; 53 | constant I_FLAG : integer := 2; 54 | constant Z_FLAG : integer := 1; 55 | constant C_FLAG : integer := 0; 56 | 57 | -- Functions 58 | function to_std_logic_vector(a: flags_t; b: std_logic) return std_logic_vector; 59 | function reverse_vector(a: in std_logic_vector) return std_logic_vector; 60 | 61 | end common; 62 | 63 | package body common is 64 | 65 | function to_std_logic_vector(a: flags_t; b: std_logic) return std_logic_vector is 66 | begin 67 | return a.n & a.v & '1' & b & a.d & a.i & a.z & a.c; 68 | end; 69 | 70 | function reverse_vector(a: in std_logic_vector) return std_logic_vector is 71 | variable result: std_logic_vector(a'range); 72 | alias aa: std_logic_vector(a'reverse_range) is a; 73 | begin 74 | for i in aa'range loop 75 | result(i) := aa(i); 76 | end loop; 77 | 78 | return result; 79 | end; 80 | 81 | end package body; 82 | -------------------------------------------------------------------------------- /data_path.vhd: -------------------------------------------------------------------------------- 1 | /* 2 | This file is part of fpgaNES. 3 | 4 | fpgaNES is free software: you can redistribute it and/or modify 5 | it under the terms of the GNU General Public License as published by 6 | the Free Software Foundation, either version 3 of the License, or 7 | (at your option) any later version. 8 | 9 | fpgaNES is distributed in the hope that it will be useful, 10 | but WITHOUT ANY WARRANTY; without even the implied warranty of 11 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 | GNU General Public License for more details. 13 | 14 | You should have received a copy of the GNU General Public License 15 | along with fpgaNES. If not, see . 16 | */ 17 | 18 | -- this component get accessed by the cpu if a value should be read from 19 | -- memory or be written to. it covers the complete cpu address space 20 | -- and redirects the requests to the specific sub modules like 21 | -- the program ROM, the RAM, the PPU- or APU-ports 22 | 23 | library ieee; 24 | use ieee.std_logic_1164.all; 25 | use ieee.std_logic_unsigned.all; 26 | use ieee.numeric_std.all; 27 | 28 | entity data_path is 29 | port 30 | ( 31 | i_clk : in std_logic; 32 | i_clk_enable : in std_logic := '1'; 33 | i_reset_n : in std_logic; 34 | i_sync : in std_logic; 35 | i_addr : in std_logic_vector(15 downto 0); 36 | i_data : in std_logic_vector(7 downto 0); 37 | i_write_enable : in std_logic; 38 | i_ppu_q : in std_logic_vector(7 downto 0); 39 | i_apu_q : in std_logic_vector(7 downto 0); 40 | i_prg_q : in std_logic_vector(7 downto 0); 41 | i_pio_q : in std_logic_vector(7 downto 0); 42 | o_prg_addr : out std_logic_vector(14 downto 0); 43 | o_prg_cs_n : out std_logic; 44 | o_ppu_addr : out std_logic_vector(2 downto 0); 45 | o_ppu_cs_n : out std_logic; 46 | o_apu_addr : out std_logic_vector(4 downto 0); 47 | o_apu_cs_n : out std_logic; 48 | o_pio_addr : out std_logic_vector(2 downto 0); 49 | o_pio_cs_n : out std_logic; 50 | o_q : out std_logic_vector(7 downto 0) 51 | ); 52 | end data_path; 53 | 54 | architecture behavioral of data_path is 55 | component datamem is 56 | port 57 | ( 58 | address : in std_logic_vector(10 downto 0); 59 | clken : in std_logic := '1'; 60 | clock : in std_logic := '1'; 61 | data : in std_logic_vector(7 downto 0); 62 | wren : in std_logic; 63 | q : out std_logic_vector(7 downto 0) 64 | ); 65 | end component; 66 | 67 | type addr_type_t is (nop, ram, rom, ppu, apu, pio); 68 | 69 | signal s_prgram_addr : std_logic_vector(10 downto 0); 70 | signal s_prgram_q : std_logic_vector(7 downto 0); 71 | signal s_prgram_write_enable : std_logic; 72 | signal s_curr_addr : std_logic_vector(15 downto 0); 73 | signal s_ppu_addr : std_logic_vector(14 downto 0); 74 | signal s_addr_type : addr_type_t; 75 | signal s_addr_type_d : addr_type_t := nop; 76 | 77 | begin 78 | prgram : datamem port map 79 | ( 80 | address => s_prgram_addr, 81 | clken => i_clk_enable, 82 | clock => i_clk, 83 | data => i_data, 84 | wren => s_prgram_write_enable, 85 | q => s_prgram_q 86 | ); 87 | 88 | process (i_clk) 89 | begin 90 | if rising_edge(i_clk) then 91 | if i_clk_enable = '1' then 92 | s_addr_type_d <= s_addr_type; 93 | end if; 94 | end if; 95 | end process; 96 | 97 | s_addr_type <= ppu when i_addr(15 downto 13) = "001" 98 | else ram when i_addr(15 downto 13) = "000" 99 | else pio when i_addr(15 downto 3) = "0100000000011" 100 | else apu when i_addr(15 downto 5) = "01000000000" 101 | else rom; 102 | 103 | with s_addr_type_d select o_q <= 104 | s_prgram_q when ram, 105 | i_ppu_q when ppu, 106 | i_apu_q when apu, 107 | i_pio_q when pio, 108 | i_prg_q when others; 109 | 110 | s_prgram_addr <= i_addr(10 downto 0); 111 | s_prgram_write_enable <= i_write_enable when s_addr_type = ram else '0'; 112 | 113 | o_ppu_addr <= i_addr(2 downto 0); 114 | o_apu_addr <= i_addr(4 downto 0); 115 | o_prg_addr <= i_addr(14 downto 0); 116 | o_pio_addr <= i_addr(2 downto 0); 117 | 118 | o_pio_cs_n <= not i_clk_enable when s_addr_type = pio else '1'; 119 | o_ppu_cs_n <= not i_sync when s_addr_type = ppu else '1'; 120 | o_apu_cs_n <= not i_clk_enable when s_addr_type = apu else '1'; 121 | o_prg_cs_n <= i_sync nand i_addr(15); 122 | 123 | end; 124 | -------------------------------------------------------------------------------- /datamem.cmp: -------------------------------------------------------------------------------- 1 | --Copyright (C) 2018 Intel Corporation. All rights reserved. 2 | --Your use of Intel Corporation's design tools, logic functions 3 | --and other software and tools, and its AMPP partner logic 4 | --functions, and any output files from any of the foregoing 5 | --(including device programming or simulation files), and any 6 | --associated documentation or information are expressly subject 7 | --to the terms and conditions of the Intel Program License 8 | --Subscription Agreement, the Intel Quartus Prime License Agreement, 9 | --the Intel FPGA IP License Agreement, or other applicable license 10 | --agreement, including, without limitation, that your use is for 11 | --the sole purpose of programming logic devices manufactured by 12 | --Intel and sold by Intel or its authorized distributors. Please 13 | --refer to the applicable agreement for further details. 14 | 15 | 16 | component datamem 17 | PORT 18 | ( 19 | address : IN STD_LOGIC_VECTOR (10 DOWNTO 0); 20 | clken : IN STD_LOGIC := '1'; 21 | clock : IN STD_LOGIC := '1'; 22 | data : IN STD_LOGIC_VECTOR (7 DOWNTO 0); 23 | wren : IN STD_LOGIC ; 24 | q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) 25 | ); 26 | end component; 27 | -------------------------------------------------------------------------------- /datamem.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "RAM: 1-PORT" 2 | set_global_assignment -name IP_TOOL_VERSION "18.0" 3 | set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone V}" 4 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "datamem.vhd"] 5 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "datamem.cmp"] 6 | -------------------------------------------------------------------------------- /datamem.vhd: -------------------------------------------------------------------------------- 1 | -- megafunction wizard: %RAM: 1-PORT% 2 | -- GENERATION: STANDARD 3 | -- VERSION: WM1.0 4 | -- MODULE: altsyncram 5 | 6 | -- ============================================================ 7 | -- File Name: datamem.vhd 8 | -- Megafunction Name(s): 9 | -- altsyncram 10 | -- 11 | -- Simulation Library Files(s): 12 | -- altera_mf 13 | -- ============================================================ 14 | -- ************************************************************ 15 | -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! 16 | -- 17 | -- 18.0.0 Build 614 04/24/2018 SJ Lite Edition 18 | -- ************************************************************ 19 | 20 | 21 | --Copyright (C) 2018 Intel Corporation. All rights reserved. 22 | --Your use of Intel Corporation's design tools, logic functions 23 | --and other software and tools, and its AMPP partner logic 24 | --functions, and any output files from any of the foregoing 25 | --(including device programming or simulation files), and any 26 | --associated documentation or information are expressly subject 27 | --to the terms and conditions of the Intel Program License 28 | --Subscription Agreement, the Intel Quartus Prime License Agreement, 29 | --the Intel FPGA IP License Agreement, or other applicable license 30 | --agreement, including, without limitation, that your use is for 31 | --the sole purpose of programming logic devices manufactured by 32 | --Intel and sold by Intel or its authorized distributors. Please 33 | --refer to the applicable agreement for further details. 34 | 35 | 36 | LIBRARY ieee; 37 | USE ieee.std_logic_1164.all; 38 | 39 | LIBRARY altera_mf; 40 | USE altera_mf.altera_mf_components.all; 41 | 42 | ENTITY datamem IS 43 | PORT 44 | ( 45 | address : IN STD_LOGIC_VECTOR (10 DOWNTO 0); 46 | clken : IN STD_LOGIC := '1'; 47 | clock : IN STD_LOGIC := '1'; 48 | data : IN STD_LOGIC_VECTOR (7 DOWNTO 0); 49 | wren : IN STD_LOGIC ; 50 | q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) 51 | ); 52 | END datamem; 53 | 54 | 55 | ARCHITECTURE SYN OF datamem IS 56 | 57 | SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0); 58 | 59 | BEGIN 60 | q <= sub_wire0(7 DOWNTO 0); 61 | 62 | altsyncram_component : altsyncram 63 | GENERIC MAP ( 64 | clock_enable_input_a => "NORMAL", 65 | clock_enable_output_a => "BYPASS", 66 | intended_device_family => "Cyclone V", 67 | lpm_hint => "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=DATA", 68 | lpm_type => "altsyncram", 69 | numwords_a => 2048, 70 | operation_mode => "SINGLE_PORT", 71 | outdata_aclr_a => "NONE", 72 | outdata_reg_a => "UNREGISTERED", 73 | power_up_uninitialized => "FALSE", 74 | read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ", 75 | widthad_a => 11, 76 | width_a => 8, 77 | width_byteena_a => 1 78 | ) 79 | PORT MAP ( 80 | address_a => address, 81 | clock0 => clock, 82 | clocken0 => clken, 83 | data_a => data, 84 | wren_a => wren, 85 | q_a => sub_wire0 86 | ); 87 | 88 | 89 | 90 | END SYN; 91 | 92 | -- ============================================================ 93 | -- CNX file retrieval info 94 | -- ============================================================ 95 | -- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" 96 | -- Retrieval info: PRIVATE: AclrAddr NUMERIC "0" 97 | -- Retrieval info: PRIVATE: AclrByte NUMERIC "0" 98 | -- Retrieval info: PRIVATE: AclrData NUMERIC "0" 99 | -- Retrieval info: PRIVATE: AclrOutput NUMERIC "0" 100 | -- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0" 101 | -- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" 102 | -- Retrieval info: PRIVATE: BlankMemory NUMERIC "1" 103 | -- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "1" 104 | -- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" 105 | -- Retrieval info: PRIVATE: Clken NUMERIC "1" 106 | -- Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1" 107 | -- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" 108 | -- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" 109 | -- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" 110 | -- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V" 111 | -- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "1" 112 | -- Retrieval info: PRIVATE: JTAG_ID STRING "DATA" 113 | -- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" 114 | -- Retrieval info: PRIVATE: MIFfilename STRING "datamem.mif" 115 | -- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "2048" 116 | -- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" 117 | -- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3" 118 | -- Retrieval info: PRIVATE: RegAddr NUMERIC "1" 119 | -- Retrieval info: PRIVATE: RegData NUMERIC "1" 120 | -- Retrieval info: PRIVATE: RegOutput NUMERIC "0" 121 | -- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" 122 | -- Retrieval info: PRIVATE: SingleClock NUMERIC "1" 123 | -- Retrieval info: PRIVATE: UseDQRAM NUMERIC "1" 124 | -- Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0" 125 | -- Retrieval info: PRIVATE: WidthAddr NUMERIC "11" 126 | -- Retrieval info: PRIVATE: WidthData NUMERIC "8" 127 | -- Retrieval info: PRIVATE: rden NUMERIC "0" 128 | -- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all 129 | -- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "NORMAL" 130 | -- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" 131 | -- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V" 132 | -- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=DATA" 133 | -- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" 134 | -- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "2048" 135 | -- Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT" 136 | -- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" 137 | -- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED" 138 | -- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE" 139 | -- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ" 140 | -- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "11" 141 | -- Retrieval info: CONSTANT: WIDTH_A NUMERIC "8" 142 | -- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" 143 | -- Retrieval info: USED_PORT: address 0 0 11 0 INPUT NODEFVAL "address[10..0]" 144 | -- Retrieval info: USED_PORT: clken 0 0 0 0 INPUT VCC "clken" 145 | -- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" 146 | -- Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]" 147 | -- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]" 148 | -- Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren" 149 | -- Retrieval info: CONNECT: @address_a 0 0 11 0 address 0 0 11 0 150 | -- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 151 | -- Retrieval info: CONNECT: @clocken0 0 0 0 0 clken 0 0 0 0 152 | -- Retrieval info: CONNECT: @data_a 0 0 8 0 data 0 0 8 0 153 | -- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0 154 | -- Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0 155 | -- Retrieval info: GEN_FILE: TYPE_NORMAL datamem.vhd TRUE 156 | -- Retrieval info: GEN_FILE: TYPE_NORMAL datamem.inc FALSE 157 | -- Retrieval info: GEN_FILE: TYPE_NORMAL datamem.cmp TRUE 158 | -- Retrieval info: GEN_FILE: TYPE_NORMAL datamem.bsf FALSE 159 | -- Retrieval info: GEN_FILE: TYPE_NORMAL datamem_inst.vhd FALSE 160 | -- Retrieval info: LIB_FILE: altera_mf 161 | -------------------------------------------------------------------------------- /debounce.vhd: -------------------------------------------------------------------------------- 1 | /* 2 | This file is part of fpgaNES. 3 | 4 | fpgaNES is free software: you can redistribute it and/or modify 5 | it under the terms of the GNU General Public License as published by 6 | the Free Software Foundation, either version 3 of the License, or 7 | (at your option) any later version. 8 | 9 | fpgaNES is distributed in the hope that it will be useful, 10 | but WITHOUT ANY WARRANTY; without even the implied warranty of 11 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 | GNU General Public License for more details. 13 | 14 | You should have received a copy of the GNU General Public License 15 | along with fpgaNES. If not, see . 16 | 17 | from http://www.lothar-miller.de/s9y/categories/5-Entprellung 18 | */ 19 | 20 | library ieee; 21 | use ieee.std_logic_1164.all; 22 | use ieee.numeric_std.all; 23 | 24 | entity debounce is 25 | port 26 | ( 27 | i_clk : in std_logic; 28 | i_in : in std_logic; 29 | o_q : out std_logic; 30 | o_riseedge : out std_logic; 31 | o_falledge : out std_logic 32 | ); 33 | end debounce; 34 | 35 | architecture behavioral of debounce is 36 | signal s_prescaler : integer range 0 to 10239; 37 | signal s_shift_register : std_logic_vector(3 downto 0) := (others => '0'); 38 | begin 39 | process (i_clk) 40 | begin 41 | if rising_edge(i_clk) then 42 | o_riseedge <= '0'; 43 | o_falledge <= '0'; 44 | 45 | if s_prescaler = 0 then 46 | s_prescaler <= 10239; 47 | 48 | -- Pegel zuweisen 49 | if s_shift_register = "0000" then 50 | o_q <= '0'; 51 | end if; 52 | 53 | if s_shift_register = "1111" then 54 | o_q <= '1'; 55 | end if; 56 | 57 | -- steigende Flanke 58 | if s_shift_register = "0111" then 59 | o_riseedge <= '1'; 60 | end if; 61 | 62 | -- fallende Flanke 63 | if s_shift_register = "1000" then 64 | o_falledge <= '1'; 65 | end if; 66 | 67 | -- von rechts Eintakten 68 | s_shift_register <= s_shift_register(2 downto 0) & i_in; 69 | else 70 | s_prescaler <= s_prescaler - 1; 71 | end if; 72 | end if; 73 | end process; 74 | end behavioral; 75 | -------------------------------------------------------------------------------- /doc/IMG_0918.jpeg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Feuerwerk/fpgaNES/fe1c8c5c212566582f1dad7096db0ce1ca793e47/doc/IMG_0918.jpeg -------------------------------------------------------------------------------- /doc/IMG_0919.jpeg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Feuerwerk/fpgaNES/fe1c8c5c212566582f1dad7096db0ce1ca793e47/doc/IMG_0919.jpeg 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11111111112222222222333333333344444444445555555555 2 | 7654321012345678901234567890123456789012345678901234567890123456789 3 | _______ ___ 4 | A0-A15_______\_______________________________________________________/___ 5 | 0 559 6 | ____________________________________________ 7 | Latest /NMI \________________ 8 | 434 9 | _____________ 10 | D0-D7 in Valid _______/_____________ 11 | 460 12 | _ _________________________________ 13 | PHI2 \___________________/ \___________ 14 | -60 135 487 15 | ___________________ ________ 16 | PRG /CE \___________________________________/ 17 | 150 510 18 | ___________________ _______ 19 | PPU /CE \___________________________________/ 20 | 163 517 21 | _______________________ 22 | PPU D7 out _______________________\______________________________________ 23 | 210 24 | ______________________________________ 25 | /VBL clear _______________________/ 26 | 210 27 | ____________________________ 28 | D0-D7 out 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(2C02). The PPU 4 | divides this by 4, and the CPU this by 12. Separate terms are used for a 5 | complete cycle of each clock, for brevity. 6 | 7 | Rate Period Term Name 8 | 21.477272 MHz ( 46.56 ns) "clocks" master clock 9 | 5.369318 MHz (186.24 ns) "dots" PPU clock 10 | 1.789772 MHz (558.73 ns) "cycles" CPU clock 11 | 12 | Note that there are exactly 3 dots per cycle (12/4=3). 13 | 14 | There are four possible relative alignments of dots to cycles: 15 | 16 | clocks ************************ 17 | dots [**][**][**][**][**][**] 18 | dots **][**][**][**][**][**][ 19 | dots *][**][**][**][**][**][* 20 | dots ][**][**][**][**][**][** 21 | cycles [**********][**********] 22 | 23 | The CPU and PPU dividers have some internal state to remember how many 24 | master clocks have occurred since the most recent output clock. When the 25 | NES is powered up or reset, this internal state takes on random values, 26 | such that the alignment that gets established can't be known in advance. 27 | Once established, though, it does not change until the NES is reset or 28 | powered off. 29 | 30 | 31 | Alignment effects 32 | ----------------- 33 | The CPU interacts with the PPU via reads, writes, interrupts, and 34 | indirectly via the cartridge mapper. If all these interactions were at the 35 | exact same point in a cycle, behavior would be the same regardless of 36 | alignment: 37 | 38 | dots [X*][X*][X*] 39 | dots X*][X*][X*][ 40 | dots *][X*][X*][X 41 | dots ][X*][X*][X* 42 | cycles [****W*****] 43 | 44 | Above, the CPU writes to the PPU. It takes effect on the next X within a 45 | dot. So in the first alignment, it takes effect immediately. In the other 46 | algnments, it's too late, so it takes effect in the next dot, being delayed 47 | by 3, 2, and 1 clocks respectively. 48 | 49 | It might seem that this varying delay is different behavior, but since the 50 | CPU can only write (or read) once per cycle, it makes no difference beyond 51 | this tiny delay; the CPU can't detect it, and nothing can "amplify" it to 52 | anything more than this. 53 | 54 | But, the above is not the case. Some events are processed at different 55 | times during a dot: 56 | 57 | dots [XY][XY][XY] 58 | dots XY][XY][XY][ 59 | cycles [****W*****] 60 | 61 | In the first alignment, a write to X in the PPU is processed immediately, 62 | and Y in 1 clock, both in the second dot. In the second alignment, a write 63 | to X takes 3 clocks, occuring in the next dot, but Y occurs immediately. in 64 | the current dot. So depending on alignment, the dot the write goes to 65 | varies. This is the "amplification" effect. From here, one could write code 66 | that caused this difference to be a black screen and a white screen. 67 | 68 | There are many aspects of events vary within a cycle and dot. CPU read, 69 | write, interrupt check. Mapper write. PPU write, read. Particular PPU 70 | registers taking more or less time to process. So when the alignment varies 71 | even by a single clock, some of these fall on the next cycle/dot, while 72 | others stay on the same one. Thus, the timing must be documented for each 73 | of the four alignments. 74 | 75 | 76 | Frame synchronization 77 | --------------------- 78 | To test the effects, code must synchronize the CPU to a PPU video frame. 79 | This could be based on any event that occurs at a specific time in the PPU 80 | frame. The simplest is when the VBL flag in $2002 bit 7 is set. 81 | 82 | Since the VBL flag will read back as 1 anytime after it's set, we want to 83 | synchronize so that we read it the earliest possible in the frame where 84 | it's set. We can do this by having a loop that reads $2002 once per frame, 85 | with a delay of one frame + 1 dot. This way in each frame it will 86 | effectively check one dot later, until it finds the VBL flag set (the loop 87 | is started so that the $2002 read is slightly before the flag is set). 88 | 89 | vbl ---****--------------****--------------****--------------****---- 90 | read *------------------*------------------*------------------* 91 | 92 | There are 341 dots per line, 262 lines per frame, thus 89342 dots per 93 | frame. When rendering is enabled, every other frame has one fewer dot. 94 | We'll synchronize with rendering disabled, for simplicity. Since there are 95 | 3 dots per cycle, there are 89342/3=29780.67 cycles per frame, that is, 96 | 29780 cycles and 2 dots. This isn't a whole number, so the frame's 97 | beginning will shift forward relative to a cycle each frame. If we delay 98 | 29781 cycles, we'll effectively delay 1 frame+1 dot. 99 | 100 | dots *****F*** first frame 101 | dots ****F**** second frame (29781 cycles later) 102 | dots ***F***** third frame 103 | dots **F****** fourth frame 104 | cycles [*][*][*] 105 | 106 | sync: delay 29781-7 107 | bit $2002 108 | bpl sync 109 | 110 | We first need to roughly synchronize so that VBL will occur before the 111 | $2002 read in the final synchronization loop. 112 | 113 | bit $2002 ; clear first 114 | coarse: bit $2002 115 | bpl coarse 116 | 117 | delay 29760 ; almost a frame 118 | 119 | sync: delay 29781-7 120 | bit $2002 121 | bpl sync 122 | 123 | After this, we are synchronized with the PPU to dot precision. At this 124 | point we are 3 cycles after the beginning of the cycle that read $2002 just 125 | as VBL was set. If we do a read 29781-3 cycles after this, we'll be reading 126 | $2002 one dot after VBL was set (the second -3 delay adjustment is for the 127 | three cycles before the read in LDA $2002): 128 | 129 | delay 29781 - 3 - 3 130 | lda $2002 131 | 132 | If we wanted to read $2002 just as VBL is being set, we'd wait three frames 133 | (so we'd be 3 dots later in frame), minus one cycle (-3 dots), giving us 134 | effectively 0 dots delay: 135 | 136 | delay 29781*3 - 1 - 3 - 3 137 | lda $2002 138 | 139 | If we wanted to read $2002 one dot *before* VBL is set, we'd wait two 140 | frames (2 dots later in frame) minus one cycle (-3 dots), giving us 141 | effectively -1 dots: 142 | 143 | delay 29781*2-1 - 3 - 3 144 | lda $2002 145 | 146 | (the above code has been tested to be sure it really does read at the 147 | claimed times in the frame) 148 | 149 | Timings of events will be referred to relative to the earliest read cycle 150 | in a frame that finds the VBL flag set. So this read cycle is +0 dots. One 151 | dot before is -1 dots. 152 | 153 | 154 | Alignments 155 | ---------- 156 | The NES powers up/resets into one of four CPU-PPU alignments. Each is one 157 | master clock apart from the adjacent one. An alignment of 0 clocks is the 158 | one which causes the VBL sync loop above to read the VBL flag the absolute 159 | earliest in the frame. 1 clock reads the VBL flag one master clock after 160 | this, etc. up to an alignment of 3 clocks. 161 | 162 | clocks **************** 163 | dots [**][**][**][**] 164 | vbl ----************ 165 | 0clk [***R******] 166 | 1clk [***R******] 167 | 2clk [***R******] 168 | 3clk [***R******] 169 | 170 | -------------------------------------------------------------------------------- /doc/nes-signal-timings/timing pictures.txt: -------------------------------------------------------------------------------- 1 | Terms 2 | ----- 3 | clock = master clock (21.477272 MHz) 4 | dot = 4 clocks = PPU pixel time 5 | cycle = 12 clocks = CPU instruction cycle 6 | 7 | Times relative to earliest in frame that $2002 reads VBL flag as set ($80), where that time is 0 dots + 0 clocks. 8 | 9 | 10 | Scope 11 | ----- 12 | The scope settings are in the photos. Note that the voltage range is 2V/div since 10x probes are being used. Most pictures use 0.1uS/div (i.e. 100ns/div). 13 | 14 | Many of the B channel traces have the clock slightly visible. 15 | 16 | 17 | Timing pictures 18 | =============== 19 | 20 | Misc 21 | ---- 22 | CHA: CPU A8, low for cycle that does indicated access. 23 | CHB: indicated line 24 | 25 | 2002 D7 read 26 | CPU data out 27 | PHI2 28 | PPU *CE 29 | PRG *CE 30 | 31 | 32 | enable nmi around vbl end 33 | ------------------------- 34 | Enables NMI around when VBL is ending 35 | 36 | CHA: CPU A8, low for cycle that writes $80 to $2000 37 | CHB: /VBL 38 | 39 | 6818 dots + 3 clocks is the latest in the frame that NMI can be enabled and still occur. 6819+0 doesn't cause NMI, even though VBL spikes low for a moment. 40 | 41 | 42 | read 2002 around vbl end 43 | ------------------------ 44 | Reads $2002 around when VBL is ending 45 | 46 | CHA: CPU A8, low for cycle that reads $2002 47 | CHB: /VBL 48 | 49 | Two versions of CHB are superimposed: one with the $2002 read, and one without it, so that the time of normal clearing of /VBL can be seen for reference. 50 | 51 | 6819 dots + 3 clocks is the latest in the frame that $2002 can be read back as $80. 52 | 5820 dots + 0 clocks reads back as $00. 53 | 54 | 55 | read 2002 around vbl begin 56 | -------------------------- 57 | Reads $2002 around time VBL begins. 58 | 59 | CHA: CPU A8, low for cycle that reads $2002 60 | CHB: /VBL 61 | 62 | Two versions of CHB are superimposed: one with the $2002 read, and one without it, so that the time of normal assertion time /VBL can be seen for reference. 63 | 64 | As expected, the earliest read that finds the VBL flag set is at 0 dots + 0 clocks, since this is the definition of our relative times. 65 | 66 | 67 | nmi after 2002 read before vbl 68 | ------------------------------ 69 | Reads $2002 somewhat before VBL begins, and notes whether this suppresses NMI. 70 | 71 | CHA: CPU A8, low for cycle that reads $2002 72 | CHB: /VBL 73 | 74 | Two versions of CHB are superimposed: one with the $2002 read, and one without it, so that the time of normal assertion time /VBL can be seen for reference. 75 | 76 | The latest $2002 can be read without suppressing assertion of /VBL (and thus the NMI) is -2 dots + 1 clock (that is, -7 clocks). It's interesting that for two clock offsets, the $2002 read very slightly delays when /VBL goes low but doesn't suppress it. 77 | 78 | 79 | nmi detection time 80 | ------------------ 81 | Reads $2002 slightly after VBL begins, to find latest time in previous instruction cycle that it can trigger NMI. 82 | 83 | CHA: CPU A8, low for cycle that reads $2002 84 | CHB: /VBL 85 | 86 | 87 | 2006 write to PPU A13 output 88 | ---------------------------- 89 | Writes $2006 at the four CPU-PPU alignments. 90 | 91 | CHA: CPU A8, low for cycle that writes $2006 92 | CHB: PPU A13 93 | 94 | This shows how the PPU quantizes $2006 address changes to a dot. All four result in PPU A13 changing at the same time. 95 | 96 | 97 | PPU address change vs vbl 98 | ------------------------- 99 | Writes to $2006 to change PPU address at various times relative to VBL begin. 100 | 101 | CHA: PPU A13 102 | CHB: /VBL 103 | 104 | This shows how the PPU quantizes $2006 address changes to a dot, and how the change time is almost synchronized with the /VBL time (about 38 ns earlier than /VBL). This might be useful for other measurements. 105 | 106 | 107 | Read latch time 108 | --------------- 109 | Has CPU D7 change at various times in read cycle. 110 | 111 | CHA: CPU A8, low for cycle that reads 112 | CHB: CPU D7 input 113 | 114 | CPU apparently latches about 460ns after A8 goes low. 115 | 116 | -------------------------------------------------------------------------------- /frmmem.cmp: -------------------------------------------------------------------------------- 1 | --Copyright (C) 2018 Intel Corporation. All rights reserved. 2 | --Your use of Intel Corporation's design tools, logic functions 3 | --and other software and tools, and its AMPP partner logic 4 | --functions, and any output files from any of the foregoing 5 | --(including device programming or simulation files), and any 6 | --associated documentation or information are expressly subject 7 | --to the terms and conditions of the Intel Program License 8 | --Subscription Agreement, the Intel Quartus Prime License Agreement, 9 | --the Intel FPGA IP License Agreement, or other applicable license 10 | --agreement, including, without limitation, that your use is for 11 | --the sole purpose of programming logic devices manufactured by 12 | --Intel and sold by Intel or its authorized distributors. Please 13 | --refer to the applicable agreement for further details. 14 | 15 | 16 | component frmmem 17 | PORT 18 | ( 19 | data : IN STD_LOGIC_VECTOR (8 DOWNTO 0); 20 | rdaddress : IN STD_LOGIC_VECTOR (15 DOWNTO 0); 21 | rdclock : IN STD_LOGIC ; 22 | rdclocken : IN STD_LOGIC := '1'; 23 | wraddress : IN STD_LOGIC_VECTOR (15 DOWNTO 0); 24 | wrclock : IN STD_LOGIC := '1'; 25 | wrclocken : IN STD_LOGIC := '1'; 26 | wren : IN STD_LOGIC := '0'; 27 | q : OUT STD_LOGIC_VECTOR (8 DOWNTO 0) 28 | ); 29 | end component; 30 | -------------------------------------------------------------------------------- /frmmem.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "RAM: 2-PORT" 2 | set_global_assignment -name IP_TOOL_VERSION "18.0" 3 | set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone V}" 4 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "frmmem.vhd"] 5 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "frmmem.cmp"] 6 | -------------------------------------------------------------------------------- /hex_digit.vhd: -------------------------------------------------------------------------------- 1 | /* 2 | This file is part of fpgaNES. 3 | 4 | fpgaNES is free software: you can redistribute it and/or modify 5 | it under the terms of the GNU General Public License as published by 6 | the Free Software Foundation, either version 3 of the License, or 7 | (at your option) any later version. 8 | 9 | fpgaNES is distributed in the hope that it will be useful, 10 | but WITHOUT ANY WARRANTY; without even the implied warranty of 11 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 | GNU General Public License for more details. 13 | 14 | You should have received a copy of the GNU General Public License 15 | along with fpgaNES. If not, see . 16 | */ 17 | 18 | library ieee; 19 | use ieee.std_logic_1164.all; 20 | use ieee.std_logic_unsigned.all; 21 | 22 | entity hex_digit is 23 | port 24 | ( 25 | i_d : in std_logic_vector(3 downto 0); 26 | o_q : out std_logic_vector(6 downto 0) 27 | ); 28 | end hex_digit; 29 | 30 | architecture behavioral of hex_digit is 31 | signal s_q: std_logic_vector(6 downto 0); 32 | begin 33 | 34 | process (i_d) 35 | begin 36 | case i_d is 37 | when "0000" => -- 0 38 | s_q <= "0111111"; 39 | 40 | when "0001" => -- 1 41 | s_q <= "0000110"; 42 | 43 | when "0010" => -- 2 44 | s_q <= "1011011"; 45 | 46 | when "0011" => -- 3 47 | s_q <= "1001111"; 48 | 49 | when "0100" => -- 4 50 | s_q <= "1100110"; 51 | 52 | when "0101" => -- 5 53 | s_q <= "1101101"; 54 | 55 | when "0110" => -- 6 56 | s_q <= "1111101"; 57 | 58 | when "0111" => -- 7 59 | s_q <= "0000111"; 60 | 61 | when "1000" => -- 8 62 | s_q <= "1111111"; 63 | 64 | when "1001" => -- 9 65 | s_q <= "1101111"; 66 | 67 | when "1010" => -- A 68 | s_q <= "1110111"; 69 | 70 | when "1011" => -- B 71 | s_q <= "1111100"; 72 | 73 | when "1100" => -- C 74 | s_q <= "0111001"; 75 | 76 | when "1101" => -- D 77 | s_q <= "1011110"; 78 | 79 | when "1110" => -- E 80 | s_q <= "1111001"; 81 | 82 | when "1111" => -- F 83 | s_q <= "1110001"; 84 | 85 | when others => 86 | s_q <= "0000000"; 87 | 88 | end case; 89 | end process; 90 | 91 | o_q <= not s_q; 92 | 93 | end architecture; -------------------------------------------------------------------------------- /i2c_master.vhd: -------------------------------------------------------------------------------- 1 | /* 2 | This file is part of fpgaNES. 3 | 4 | fpgaNES is free software: you can redistribute it and/or modify 5 | it under the terms of the GNU General Public License as published by 6 | the Free Software Foundation, either version 3 of the License, or 7 | (at your option) any later version. 8 | 9 | fpgaNES is distributed in the hope that it will be useful, 10 | but WITHOUT ANY WARRANTY; without even the implied warranty of 11 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 | GNU General Public License for more details. 13 | 14 | You should have received a copy of the GNU General Public License 15 | along with fpgaNES. If not, see . 16 | */ 17 | 18 | library ieee; 19 | use ieee.std_logic_1164.all; 20 | use ieee.std_logic_unsigned.all; 21 | use ieee.numeric_std.all; 22 | use work.common.all; 23 | 24 | entity i2c_master is 25 | generic 26 | ( 27 | CLK_SPEED : integer := 50_000_000; 28 | WAIT_TIMEOUT : integer := 100 29 | ); 30 | port 31 | ( 32 | i_clk : in std_logic; 33 | i_reset_n : in std_logic := '1'; 34 | i_enable : in std_logic := '0'; 35 | i_active : in std_logic := '0'; 36 | i_addr : in std_logic_vector(7 downto 0) := x"00"; 37 | i_cmd : in std_logic_vector(7 downto 0) := x"00"; 38 | i_data : in std_logic_vector(7 downto 0) := x"00"; 39 | i_read_not_write : std_logic := '1'; 40 | io_sda : inout std_logic; 41 | io_scl : inout std_logic; 42 | o_q : out std_logic_vector(7 downto 0); 43 | o_busy : out std_logic; 44 | o_ack_error : out std_logic 45 | ); 46 | end i2c_master; 47 | 48 | architecture behavioral of i2c_master is 49 | component i2c is 50 | generic 51 | ( 52 | input_clk : integer := 50_000_000; 53 | bus_clk : integer := 400_000 54 | ); 55 | port 56 | ( 57 | i_clk : in std_logic; 58 | i_reset_n : in std_logic; 59 | i_enable : in std_logic; 60 | i_flag : in std_logic; 61 | i_start_condition : in std_logic; 62 | i_stop_condition : in std_logic; 63 | i_enable_ack : in std_logic; 64 | i_data : in std_logic_vector(7 downto 0); 65 | io_sda : inout std_logic; 66 | io_scl : inout std_logic; 67 | o_q : out std_logic_vector(7 downto 0); 68 | o_status : out std_logic_vector(4 downto 0); 69 | o_busy : out std_logic; 70 | o_ack_error : out std_logic 71 | ); 72 | end component; 73 | 74 | type state_t is (idle, start_read, addr_for_read1, cmd_for_read, restart, addr_for_read2, read_data, start_write, addr_for_write, cmd_for_write, write_data, wait_after_write, ready, stopping); 75 | 76 | signal s_state : state_t := idle; 77 | signal s_start : std_logic := '0'; 78 | signal s_stop : std_logic := '0'; 79 | signal s_busy : std_logic; 80 | signal s_addr : std_logic_vector(6 downto 0) := 7x"00"; 81 | signal s_cmd : std_logic_vector(7 downto 0) := x"00"; 82 | signal s_data : std_logic_vector(7 downto 0) := x"00"; 83 | signal s_buffer : std_logic_vector(7 downto 0) := x"00"; 84 | signal s_transition : boolean; 85 | signal s_wait_counter : integer range 0 to WAIT_TIMEOUT := 0; 86 | signal s_cmd_enable : std_logic; 87 | signal s_enable : std_logic := '0'; 88 | begin 89 | i2c_cmp : i2c generic map ( input_clk => CLK_SPEED ) port map 90 | ( 91 | i_clk => i_clk, 92 | i_reset_n => i_reset_n, 93 | i_enable => '1', 94 | i_flag => s_cmd_enable, 95 | i_start_condition => s_start, 96 | i_stop_condition => s_stop, 97 | i_enable_ack => '0', 98 | i_data => s_buffer, 99 | io_sda => io_sda, 100 | io_scl => io_scl, 101 | o_q => o_q, 102 | o_busy => s_busy, 103 | o_ack_error => o_ack_error 104 | ); 105 | 106 | process (i_clk) 107 | begin 108 | if rising_edge(i_clk) then 109 | s_enable <= '0'; 110 | 111 | if i_reset_n = '0' then 112 | s_state <= idle; 113 | s_wait_counter <= 0; 114 | s_addr <= 7x"00"; 115 | s_cmd <= x"00"; 116 | s_data <= x"00"; 117 | s_buffer <= x"00"; 118 | s_start <= '0'; 119 | else 120 | if (s_wait_counter /= 0) then 121 | s_wait_counter <= s_wait_counter - 1; 122 | end if; 123 | 124 | if s_transition then 125 | case s_state is 126 | 127 | when idle => 128 | if i_enable = '1' then 129 | if i_active = '1' then 130 | if i_read_not_write = '1' then 131 | s_state <= start_read; 132 | else 133 | s_state <= start_write; 134 | end if; 135 | 136 | s_addr <= i_addr(7 downto 1); 137 | s_cmd <= i_cmd; 138 | s_data <= i_data; 139 | s_start <= '1'; 140 | s_enable <= '1'; 141 | end if; 142 | end if; 143 | 144 | when ready => 145 | if i_enable = '1' then 146 | if i_active = '1' then 147 | if i_read_not_write = '1' then 148 | s_state <= start_read; 149 | else 150 | s_state <= start_write; 151 | end if; 152 | 153 | s_addr <= i_addr(7 downto 1); 154 | s_cmd <= i_cmd; 155 | s_data <= i_data; 156 | s_start <= '1'; 157 | s_enable <= '1'; 158 | else 159 | s_stop <= '1'; 160 | s_enable <= '1'; 161 | s_state <= stopping; 162 | end if; 163 | end if; 164 | 165 | when stopping => 166 | s_stop <= '0'; 167 | s_state <= idle; 168 | 169 | when start_read => 170 | s_start <= '0'; 171 | s_buffer <= s_addr & '0'; 172 | s_state <= addr_for_read1; 173 | s_enable <= '1'; 174 | 175 | when addr_for_read1 => 176 | s_buffer <= s_cmd; 177 | s_state <= cmd_for_read; 178 | s_enable <= '1'; 179 | 180 | when cmd_for_read => 181 | s_start <= '1'; 182 | s_state <= restart; 183 | s_enable <= '1'; 184 | 185 | when restart => 186 | s_start <= '0'; 187 | s_buffer <= s_addr & '1'; 188 | s_state <= addr_for_read2; 189 | s_enable <= '1'; 190 | 191 | when addr_for_read2 => 192 | s_state <= read_data; 193 | s_enable <= '1'; 194 | 195 | when read_data => 196 | s_state <= ready; 197 | 198 | when start_write => 199 | s_start <= '0'; 200 | s_buffer <= s_addr & '0'; 201 | s_state <= addr_for_write; 202 | s_enable <= '1'; 203 | 204 | when addr_for_write => 205 | s_buffer <= s_cmd; 206 | s_state <= cmd_for_write; 207 | s_enable <= '1'; 208 | 209 | when cmd_for_write => 210 | s_buffer <= s_data; 211 | s_state <= write_data; 212 | s_enable <= '1'; 213 | 214 | when write_data => 215 | s_wait_counter <= WAIT_TIMEOUT; -- Nach einem Schreibkommando je 7 ms auf EE2 warten 216 | s_state <= wait_after_write; 217 | 218 | when wait_after_write => 219 | if s_wait_counter = 0 then 220 | s_state <= ready; 221 | end if; 222 | 223 | end case; 224 | end if; 225 | end if; 226 | end if; 227 | end process; 228 | 229 | s_cmd_enable <= '0' when s_state = wait_after_write else s_enable; 230 | s_transition <= (s_wait_counter = 0) when s_state = wait_after_write else (s_busy = '0') and (s_enable = '0'); 231 | o_busy <= '0' when (s_state = idle) or (s_state = ready) else '1'; 232 | 233 | end behavioral; 234 | -------------------------------------------------------------------------------- /i2s.vhd: -------------------------------------------------------------------------------- 1 | /* 2 | This file is part of fpgaNES. 3 | 4 | fpgaNES is free software: you can redistribute it and/or modify 5 | it under the terms of the GNU General Public License as published by 6 | the Free Software Foundation, either version 3 of the License, or 7 | (at your option) any later version. 8 | 9 | fpgaNES is distributed in the hope that it will be useful, 10 | but WITHOUT ANY WARRANTY; without even the implied warranty of 11 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 | GNU General Public License for more details. 13 | 14 | You should have received a copy of the GNU General Public License 15 | along with fpgaNES. If not, see . 16 | */ 17 | 18 | -- this component will output a left aligned 16 bit audio sample with 44.1 kHz over an I2S connection 19 | -- while SCLK and MCLK is driven by its own clock the audio sample itself comes from the master clock domain 20 | -- and has to be synched with the audio clock 21 | 22 | library ieee; 23 | use ieee.std_logic_1164.all; 24 | use ieee.numeric_std.all; 25 | 26 | entity i2s is 27 | generic 28 | ( 29 | DIVIDER : natural := 4; 30 | WORD_WIDTH : natural := 16; 31 | CHANNEL_WIDTH : natural := 32 32 | ); 33 | port 34 | ( 35 | i_audio_clk : in std_logic; 36 | i_master_clk : in std_logic; 37 | i_clk_enable : in std_logic; 38 | i_audio_reset_n : in std_logic := '1'; 39 | i_master_reset_n : in std_logic := '1'; 40 | i_data : in std_logic_vector(WORD_WIDTH - 1 downto 0); 41 | o_lrclk : out std_logic; 42 | o_sclk : out std_logic; 43 | o_sdata : out std_logic 44 | ); 45 | end i2s; 46 | 47 | architecture behavioral of i2s is 48 | component biquad is 49 | generic 50 | ( 51 | B0 : std_logic_vector(31 downto 0); 52 | B1 : std_logic_vector(31 downto 0); 53 | B2 : std_logic_vector(31 downto 0); 54 | A1 : std_logic_vector(31 downto 0); 55 | A2 : std_logic_vector(31 downto 0) 56 | ); 57 | port 58 | ( 59 | i_clk : in std_logic; 60 | i_reset_n : in std_logic := '1'; 61 | i_sample_trig : in std_logic; 62 | i_x : in std_logic_vector(17 downto 0); 63 | o_filter_done : out std_logic; 64 | o_q : out std_logic_vector(17 downto 0) 65 | ); 66 | end component; 67 | 68 | constant HALF_DIVIDER : natural := DIVIDER / 2; 69 | 70 | signal s_clk_divider : natural range 0 to DIVIDER - 1 := 0; 71 | signal s_sdata : std_logic; 72 | signal s_sclk : std_logic := '0'; 73 | signal s_buffer : std_logic_vector(WORD_WIDTH - 1 downto 0) := (others => '0'); 74 | signal s_data : std_logic_vector(WORD_WIDTH - 1 downto 0) := (others => '0'); 75 | signal s_bit_index : natural range 0 to CHANNEL_WIDTH - 1 := 0; 76 | signal s_lrclk : std_logic := '1'; 77 | signal s_sclk_sync : std_logic_vector(1 downto 0) := "00"; 78 | signal s_falling_sclk : std_logic; 79 | signal s_sample_last : std_logic; 80 | signal s_bq_low_done : std_logic; 81 | signal s_bq_high90_done : std_logic; 82 | signal s_bq_high440_done : std_logic; 83 | signal s_bq_high90_q : std_logic_vector(17 downto 0); 84 | signal s_bq_high440_q : std_logic_vector(17 downto 0); 85 | signal s_bq_low_q : std_logic_vector(17 downto 0); 86 | 87 | begin 88 | 89 | -- Low-Pass 1st Order: fs= 44.1kHz, fc = 14.0 kHz 90 | bq_low : biquad generic map 91 | ( 92 | B0 => B"00_10_0110_1110_0010_1001_1111_0111_0101", -- 0.607581963 93 | B1 => B"00_10_0110_1110_0010_1001_1111_0111_0101", -- 0.607581963 94 | B2 => B"00_00_0000_0000_0000_0000_0000_0000_0000", -- 0.0 95 | A1 => B"00_00_1101_1100_0101_0011_1110_1110_1010", -- 0.215163926 96 | A2 => B"00_00_0000_0000_0000_0000_0000_0000_0000" -- 0.0 97 | ) 98 | port map 99 | ( 100 | i_clk => i_master_clk, 101 | i_sample_trig => s_falling_sclk and s_sample_last, 102 | i_reset_n => i_master_reset_n, 103 | i_x => "00" & i_data, 104 | o_filter_done => s_bq_low_done, 105 | o_q => s_bq_low_q 106 | ); 107 | 108 | -- High-Pass 1st Order: fs= 44.1kHz, fc = 440 Hz 109 | bq_high440 : biquad generic map 110 | ( 111 | B0 => B"00_11_1110_0000_1101_1110_0101_1111_1001", -- 0.969598287 112 | B1 => B"11_00_0001_1111_0010_0001_1010_0000_0111", -- -0.969598287 113 | B2 => B"00_00_0000_0000_0000_0000_0000_0000_0000", -- 0.0 114 | A1 => B"11_00_0011_1110_0100_0011_0100_0000_1111", -- -0,939196573 115 | A2 => B"00_00_0000_0000_0000_0000_0000_0000_0000" -- 0.0 116 | ) 117 | port map 118 | ( 119 | i_clk => i_master_clk, 120 | i_sample_trig => s_bq_low_done, 121 | i_reset_n => i_master_reset_n, 122 | i_x => s_bq_low_q, 123 | o_filter_done => s_bq_high440_done, 124 | o_q => s_bq_high440_q 125 | ); 126 | 127 | -- High-Pass 1st Order: fs= 44.1kHz, fc = 90 Hz 128 | bq_high90 : biquad generic map 129 | ( 130 | B0 => B"00_11_1111_1001_0111_1001_1111_1000_1000", -- 0.993629344 131 | B1 => B"11_00_0000_0110_1000_0110_0000_0111_1000", -- -0.993629344 132 | B2 => B"00_00_0000_0000_0000_0000_0000_0000_0000", -- 0.0 133 | A1 => B"11_00_0000_1101_0000_1100_0000_1111_0000", -- -0.987258688 134 | A2 => B"00_00_0000_0000_0000_0000_0000_0000_0000" -- 0.0 135 | ) 136 | port map 137 | ( 138 | i_clk => i_master_clk, 139 | i_sample_trig => s_bq_high440_done, 140 | i_reset_n => i_master_reset_n, 141 | i_x => s_bq_high440_q, 142 | o_filter_done => s_bq_high90_done, 143 | o_q => s_bq_high90_q 144 | ); 145 | 146 | -- Clock Divider 147 | 148 | process (i_audio_clk) 149 | begin 150 | if rising_edge(i_audio_clk) then 151 | if i_audio_reset_n = '0' then 152 | s_clk_divider <= 0; 153 | s_sclk <= '0'; 154 | else 155 | if s_clk_divider = DIVIDER - 1 then 156 | s_clk_divider <= 0; 157 | else 158 | s_clk_divider <= s_clk_divider + 1; 159 | end if; 160 | 161 | if s_clk_divider = DIVIDER - 1 then 162 | s_sclk <= '1'; 163 | elsif s_clk_divider = HALF_DIVIDER - 1 then 164 | s_sclk <= '0'; 165 | end if; 166 | 167 | end if; 168 | end if; 169 | end process; 170 | 171 | -- Bit-Stream 172 | 173 | process (i_master_clk) 174 | begin 175 | if rising_edge(i_master_clk) then 176 | if s_bq_low_done = '1' then 177 | s_data <= s_bq_low_q(15 downto 0); 178 | end if; 179 | 180 | if s_falling_sclk = '1' then 181 | if s_sample_last = '1' then 182 | s_bit_index <= 0; 183 | s_lrclk <= not s_lrclk; 184 | s_buffer <= s_data; 185 | else 186 | s_bit_index <= s_bit_index + 1; 187 | s_buffer <= s_buffer(WORD_WIDTH - 2 downto 0) & '0'; 188 | end if; 189 | end if; 190 | 191 | s_sclk_sync <= s_sclk_sync(0) & s_sclk; -- SCLK Synchronization Chain 192 | end if; 193 | end process; 194 | 195 | s_falling_sclk <= s_sclk_sync(1) and not s_sclk_sync(0); -- SCLK falling edge 196 | s_sample_last <= '1' when s_bit_index = CHANNEL_WIDTH - 1 else '0'; 197 | 198 | o_lrclk <= s_lrclk; 199 | o_sclk <= s_sclk; 200 | o_sdata <= s_buffer(WORD_WIDTH - 1); 201 | 202 | end behavioral; 203 | -------------------------------------------------------------------------------- /master_ctrl.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | use ieee.std_logic_unsigned.all; 4 | use ieee.numeric_std.all; 5 | use work.common.all; 6 | 7 | entity master_ctrl is 8 | port 9 | ( 10 | i_clk : in std_logic; 11 | i_reset_n : in std_logic := '1'; 12 | i_video_mode : in video_mode_t; 13 | i_waitrequest : in std_logic := '0'; 14 | i_reconfig_data : in std_logic_vector(31 downto 0) := (others => '0'); 15 | o_video_mode : out video_mode_t; 16 | o_status : out std_logic_vector(7 downto 0); 17 | o_reconfig_read : out std_logic; 18 | o_reconfig_write : out std_logic; 19 | o_reconfig_addr : out std_logic_vector(5 downto 0); 20 | o_reconfig_new_data : out std_logic_vector(31 downto 0) 21 | ); 22 | end master_ctrl; 23 | 24 | architecture behavioral of master_ctrl is 25 | signal s_reconfig_read : std_logic := '0'; 26 | signal s_reconfig_write : std_logic := '0'; 27 | signal s_reconfig_addr : std_logic_vector(5 downto 0) := (others => '0'); 28 | signal s_reconfig_new_data : std_logic_vector(31 downto 0) := (others => '0'); 29 | signal s_m_counter : std_logic_vector(17 downto 0); 30 | signal s_n_counter : std_logic_vector(17 downto 0); 31 | signal s_c_counter : std_logic_vector(17 downto 0); 32 | signal s_loop_filter_res : std_logic_vector(7 downto 0); 33 | signal s_write_count : natural range 0 to 3 := 0; 34 | signal s_state : natural range 0 to 9 := 9; 35 | signal s_video_mode_active : video_mode_t := pal; 36 | signal s_video_mode_new : video_mode_t := pal; 37 | signal s_counter : natural range 0 to 1023 := 1023; 38 | 39 | begin 40 | 41 | process (i_clk) 42 | begin 43 | 44 | if rising_edge(i_clk) then 45 | if i_reset_n = '0' then 46 | s_state <= 0; 47 | s_counter <= 1023; 48 | s_write_count <= 0; 49 | s_reconfig_read <= '0'; 50 | s_reconfig_write <= '0'; 51 | s_reconfig_addr <= (others => '0'); 52 | s_reconfig_new_data <= (others => '0'); 53 | else 54 | case s_state is 55 | 56 | when 0 => /* idle */ 57 | if s_video_mode_active /= i_video_mode then 58 | s_video_mode_new <= i_video_mode; 59 | s_state <= 1; 60 | s_write_count <= 0; 61 | s_reconfig_addr <= 6x"0"; /* waitrequest */ 62 | s_reconfig_new_data <= 32x"0"; 63 | end if; 64 | 65 | when 1 => /* polling mode */ 66 | case s_write_count is 67 | 68 | when 0 => 69 | s_reconfig_write <= '1'; 70 | 71 | when 1 => 72 | s_reconfig_write <= '0'; 73 | 74 | when 2 => 75 | s_write_count <= 0; 76 | s_state <= 2; 77 | s_reconfig_addr <= 6x"4"; /* M counter */ 78 | s_reconfig_new_data <= 14x"0" & s_m_counter; 79 | 80 | when others => 81 | null; 82 | 83 | end case; 84 | 85 | s_write_count <= s_write_count + 1; 86 | 87 | when 2 => /* writing M counter */ 88 | case s_write_count is 89 | 90 | when 0 => 91 | s_reconfig_write <= '1'; 92 | 93 | when 1 => 94 | s_reconfig_write <= '0'; 95 | 96 | when 2 => 97 | s_write_count <= 0; 98 | s_state <= 3; 99 | s_reconfig_addr <= 6x"3"; /* N counter */ 100 | s_reconfig_new_data <= 14x"0" & s_n_counter; 101 | 102 | when others => 103 | null; 104 | 105 | end case; 106 | 107 | s_write_count <= s_write_count + 1; 108 | 109 | when 3 => /* writing N counter */ 110 | case s_write_count is 111 | 112 | when 0 => 113 | s_reconfig_write <= '1'; 114 | 115 | when 1 => 116 | s_reconfig_write <= '0'; 117 | 118 | when 2 => 119 | s_write_count <= 0; 120 | s_state <= 4; 121 | s_reconfig_addr <= 6x"5"; /* C counter */ 122 | s_reconfig_new_data <= 14x"0" & s_c_counter; 123 | 124 | when others => 125 | null; 126 | 127 | end case; 128 | 129 | s_write_count <= s_write_count + 1; 130 | 131 | when 4 => /* writing C counter */ 132 | case s_write_count is 133 | 134 | when 0 => 135 | s_reconfig_write <= '1'; 136 | 137 | when 1 => 138 | s_reconfig_write <= '0'; 139 | 140 | when 2 => 141 | s_write_count <= 0; 142 | s_state <= 5; 143 | s_reconfig_addr <= 6x"8"; /* Loop Filter Resistance */ 144 | s_reconfig_new_data <= 24x"0" & s_loop_filter_res; 145 | 146 | when others => 147 | null; 148 | 149 | end case; 150 | 151 | s_write_count <= s_write_count + 1; 152 | 153 | when 5 => /* writing Loop Filter Resistance */ 154 | case s_write_count is 155 | 156 | when 0 => 157 | s_reconfig_write <= '1'; 158 | 159 | when 1 => 160 | s_reconfig_write <= '0'; 161 | 162 | when 2 => 163 | s_write_count <= 0; 164 | s_state <= 6; 165 | s_reconfig_addr <= 6x"9"; /* Charge Pump */ 166 | s_reconfig_new_data <= 32x"2"; 167 | 168 | when others => 169 | null; 170 | 171 | end case; 172 | 173 | s_write_count <= s_write_count + 1; 174 | 175 | when 6 => /* writing Charge Pump */ 176 | case s_write_count is 177 | 178 | when 0 => 179 | s_reconfig_write <= '1'; 180 | 181 | when 1 => 182 | s_reconfig_write <= '0'; 183 | 184 | when 2 => 185 | s_write_count <= 0; 186 | s_state <= 7; 187 | s_reconfig_addr <= 6x"2"; /* Start reconfiguration */ 188 | s_reconfig_new_data <= 32x"1"; 189 | 190 | when others => 191 | null; 192 | 193 | end case; 194 | 195 | s_write_count <= s_write_count + 1; 196 | 197 | when 7 => /* starting reconfiguration */ 198 | case s_write_count is 199 | 200 | when 0 => 201 | s_reconfig_write <= '1'; 202 | 203 | when 1 => 204 | s_reconfig_write <= '0'; 205 | 206 | when 2 => 207 | s_state <= 8; 208 | 209 | when others => 210 | null; 211 | 212 | end case; 213 | 214 | s_write_count <= s_write_count + 1; 215 | 216 | when 8 => /* checking status */ 217 | if i_waitrequest = '0' then 218 | s_state <= 0; 219 | s_video_mode_active <= s_video_mode_new; 220 | end if; 221 | 222 | when 9 => 223 | if s_counter = 0 then 224 | s_state <= 0; 225 | else 226 | s_counter <= s_counter - 1; 227 | end if; 228 | 229 | end case; 230 | 231 | end if; 232 | end if; 233 | 234 | end process; 235 | 236 | process (s_video_mode_new) 237 | begin 238 | case s_video_mode_new is 239 | 240 | when ntsc => 241 | s_m_counter <= 18x"25F5E"; 242 | s_n_counter <= 18x"0505"; 243 | s_c_counter <= 18x"1616"; 244 | s_loop_filter_res <= 8x"3"; 245 | 246 | when pal => 247 | s_m_counter <= 18x"3636"; 248 | s_n_counter <= 18x"20403"; 249 | s_c_counter <= 18x"20F0E"; 250 | s_loop_filter_res <= 8x"4"; 251 | 252 | end case; 253 | end process; 254 | 255 | o_reconfig_read <= s_reconfig_read; 256 | o_reconfig_write <= s_reconfig_write; 257 | o_reconfig_addr <= s_reconfig_addr; 258 | o_reconfig_new_data <= s_reconfig_new_data; 259 | o_video_mode <= s_video_mode_active; 260 | o_status <= std_logic_vector(to_unsigned(s_state, 8)); 261 | 262 | end; 263 | -------------------------------------------------------------------------------- /master_pll.bsf: -------------------------------------------------------------------------------- 1 | /* 2 | WARNING: Do NOT edit the input and output ports in this file in a text 3 | editor if you plan to continue editing the block that represents it in 4 | the Block Editor! File corruption is VERY likely to occur. 5 | */ 6 | /* 7 | Copyright (C) 2018 Intel Corporation. All rights reserved. 8 | Your use of Intel Corporation's design tools, logic functions 9 | and other software and tools, and its AMPP partner logic 10 | functions, and any output files from any of the foregoing 11 | (including device programming or simulation files), and any 12 | associated documentation or information are expressly subject 13 | to the terms and conditions of the Intel Program License 14 | Subscription Agreement, the Intel Quartus Prime License Agreement, 15 | the Intel FPGA IP License Agreement, or other applicable license 16 | agreement, including, without limitation, that your use is for 17 | the sole purpose of programming logic devices manufactured by 18 | Intel and sold by Intel or its authorized distributors. Please 19 | refer to the applicable agreement for further details. 20 | */ 21 | (header "symbol" (version "1.1")) 22 | (symbol 23 | (rect 0 0 400 184) 24 | (text "master_pll" (rect 170 -1 211 11)(font "Arial" (font_size 10))) 25 | (text "inst" (rect 8 168 20 180)(font "Arial" )) 26 | (port 27 | (pt 0 72) 28 | (input) 29 | (text "refclk" (rect 0 0 22 12)(font "Arial" (font_size 8))) 30 | (text "refclk" (rect 4 61 40 72)(font "Arial" (font_size 8))) 31 | (line (pt 0 72)(pt 112 72)(line_width 1)) 32 | ) 33 | (port 34 | (pt 0 112) 35 | (input) 36 | (text "rst" (rect 0 0 10 12)(font "Arial" (font_size 8))) 37 | (text "rst" (rect 4 101 22 112)(font "Arial" (font_size 8))) 38 | (line (pt 0 112)(pt 112 112)(line_width 1)) 39 | ) 40 | (port 41 | (pt 0 152) 42 | (input) 43 | (text "reconfig_to_pll[63..0]" (rect 0 0 82 12)(font "Arial" (font_size 8))) 44 | (text "reconfig_to_pll[63..0]" (rect 4 141 136 152)(font "Arial" (font_size 8))) 45 | (line (pt 0 152)(pt 112 152)(line_width 3)) 46 | ) 47 | (port 48 | (pt 400 72) 49 | (output) 50 | (text "outclk_0" (rect 0 0 33 12)(font "Arial" (font_size 8))) 51 | (text "outclk_0" (rect 357 61 405 72)(font "Arial" (font_size 8))) 52 | (line (pt 400 72)(pt 272 72)(line_width 1)) 53 | ) 54 | (port 55 | (pt 400 112) 56 | (output) 57 | (text "locked" (rect 0 0 24 12)(font "Arial" (font_size 8))) 58 | (text "locked" (rect 367 101 403 112)(font "Arial" (font_size 8))) 59 | (line (pt 400 112)(pt 272 112)(line_width 1)) 60 | ) 61 | (port 62 | (pt 400 152) 63 | (output) 64 | (text "reconfig_from_pll[63..0]" (rect 0 0 95 12)(font "Arial" (font_size 8))) 65 | (text "reconfig_from_pll[63..0]" (rect 280 141 424 152)(font "Arial" (font_size 8))) 66 | (line (pt 400 152)(pt 272 152)(line_width 3)) 67 | ) 68 | (drawing 69 | (text "refclk" (rect 80 43 196 99)(font "Arial" (color 128 0 0)(font_size 9))) 70 | (text "clk" (rect 117 67 252 144)(font "Arial" (color 0 0 0))) 71 | (text "reset" (rect 83 83 196 179)(font "Arial" (color 128 0 0)(font_size 9))) 72 | (text "reset" (rect 117 107 264 224)(font "Arial" (color 0 0 0))) 73 | (text "outclk0" (rect 273 43 588 99)(font "Arial" (color 128 0 0)(font_size 9))) 74 | (text "clk" (rect 257 67 532 144)(font "Arial" (color 0 0 0))) 75 | (text "locked" (rect 273 83 582 179)(font "Arial" (color 128 0 0)(font_size 9))) 76 | (text "export" (rect 242 107 520 224)(font "Arial" (color 0 0 0))) 77 | (text "reconfig_to_pll" (rect 26 123 142 259)(font "Arial" (color 128 0 0)(font_size 9))) 78 | (text "reconfig_to_pll" (rect 117 147 324 304)(font "Arial" (color 0 0 0))) 79 | (text "reconfig_from_pll" (rect 273 123 648 259)(font "Arial" (color 128 0 0)(font_size 9))) 80 | (text "reconfig_from_pll" (rect 192 147 486 304)(font "Arial" (color 0 0 0))) 81 | (text " altera_pll " (rect 358 168 788 346)(font "Arial" )) 82 | (line (pt 112 32)(pt 272 32)(line_width 1)) 83 | (line (pt 272 32)(pt 272 168)(line_width 1)) 84 | (line (pt 112 168)(pt 272 168)(line_width 1)) 85 | (line (pt 112 32)(pt 112 168)(line_width 1)) 86 | (line (pt 113 52)(pt 113 76)(line_width 1)) 87 | (line (pt 114 52)(pt 114 76)(line_width 1)) 88 | (line (pt 113 92)(pt 113 116)(line_width 1)) 89 | (line (pt 114 92)(pt 114 116)(line_width 1)) 90 | (line (pt 271 52)(pt 271 76)(line_width 1)) 91 | (line (pt 270 52)(pt 270 76)(line_width 1)) 92 | (line (pt 271 92)(pt 271 116)(line_width 1)) 93 | (line (pt 270 92)(pt 270 116)(line_width 1)) 94 | (line (pt 113 132)(pt 113 156)(line_width 1)) 95 | (line (pt 114 132)(pt 114 156)(line_width 1)) 96 | (line (pt 271 132)(pt 271 156)(line_width 1)) 97 | (line (pt 270 132)(pt 270 156)(line_width 1)) 98 | (line (pt 0 0)(pt 400 0)(line_width 1)) 99 | (line (pt 400 0)(pt 400 184)(line_width 1)) 100 | (line (pt 0 184)(pt 400 184)(line_width 1)) 101 | (line (pt 0 0)(pt 0 184)(line_width 1)) 102 | ) 103 | ) 104 | -------------------------------------------------------------------------------- /master_pll.cmp: -------------------------------------------------------------------------------- 1 | component master_pll is 2 | port ( 3 | refclk : in std_logic := 'X'; -- clk 4 | rst : in std_logic := 'X'; -- reset 5 | outclk_0 : out std_logic; -- clk 6 | locked : out std_logic; -- export 7 | reconfig_to_pll : in std_logic_vector(63 downto 0) := (others => 'X'); -- reconfig_to_pll 8 | reconfig_from_pll : out std_logic_vector(63 downto 0) -- reconfig_from_pll 9 | ); 10 | end component master_pll; 11 | 12 | -------------------------------------------------------------------------------- /master_pll.ppf: -------------------------------------------------------------------------------- 1 | 2 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | -------------------------------------------------------------------------------- /master_pll.sip: -------------------------------------------------------------------------------- 1 | set_global_assignment -entity "master_pll" -library "lib_master_pll" -name IP_TOOL_NAME "altera_pll" 2 | set_global_assignment -entity "master_pll" -library "lib_master_pll" -name IP_TOOL_VERSION "18.0" 3 | set_global_assignment -entity "master_pll" -library "lib_master_pll" -name IP_TOOL_ENV "mwpim" 4 | set_global_assignment -library "lib_master_pll" -name SPD_FILE [file join $::quartus(sip_path) "master_pll.spd"] 5 | 6 | set_global_assignment -library "lib_master_pll" -name MISC_FILE [file join $::quartus(sip_path) "master_pll_sim/master_pll.vho"] 7 | -------------------------------------------------------------------------------- /master_pll.spd: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | -------------------------------------------------------------------------------- /master_pll/master_pll_0002.qip: -------------------------------------------------------------------------------- 1 | set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to "*master_pll_0002*|altera_pll:altera_pll_i*|*" 2 | set_instance_assignment -name UNFORCE_MERGE_PLL_OUTPUT_COUNTER ON -to "*master_pll_0002*|altera_pll:altera_pll_i*|*" 3 | -------------------------------------------------------------------------------- /master_pll/master_pll_0002.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns/10ps 2 | module master_pll_0002( 3 | 4 | // interface 'refclk' 5 | input wire refclk, 6 | 7 | // interface 'reset' 8 | input wire rst, 9 | 10 | // interface 'outclk0' 11 | output wire outclk_0, 12 | 13 | // interface 'locked' 14 | output wire locked, 15 | 16 | // interface 'reconfig_to_pll' 17 | input wire [63:0] reconfig_to_pll, 18 | 19 | // interface 'reconfig_from_pll' 20 | output wire [63:0] reconfig_from_pll 21 | ); 22 | 23 | altera_pll #( 24 | .fractional_vco_multiplier("false"), 25 | .reference_clock_frequency("50.0 MHz"), 26 | .pll_fractional_cout(32), 27 | .pll_dsm_out_sel("1st_order"), 28 | .operation_mode("direct"), 29 | .number_of_clocks(1), 30 | .output_clock_frequency0("26.600985 MHz"), 31 | .phase_shift0("0 ps"), 32 | .duty_cycle0(50), 33 | .output_clock_frequency1("0 MHz"), 34 | .phase_shift1("0 ps"), 35 | .duty_cycle1(50), 36 | .output_clock_frequency2("0 MHz"), 37 | .phase_shift2("0 ps"), 38 | .duty_cycle2(50), 39 | .output_clock_frequency3("0 MHz"), 40 | .phase_shift3("0 ps"), 41 | .duty_cycle3(50), 42 | .output_clock_frequency4("0 MHz"), 43 | .phase_shift4("0 ps"), 44 | .duty_cycle4(50), 45 | .output_clock_frequency5("0 MHz"), 46 | .phase_shift5("0 ps"), 47 | .duty_cycle5(50), 48 | .output_clock_frequency6("0 MHz"), 49 | .phase_shift6("0 ps"), 50 | .duty_cycle6(50), 51 | .output_clock_frequency7("0 MHz"), 52 | .phase_shift7("0 ps"), 53 | .duty_cycle7(50), 54 | .output_clock_frequency8("0 MHz"), 55 | .phase_shift8("0 ps"), 56 | .duty_cycle8(50), 57 | .output_clock_frequency9("0 MHz"), 58 | .phase_shift9("0 ps"), 59 | .duty_cycle9(50), 60 | .output_clock_frequency10("0 MHz"), 61 | .phase_shift10("0 ps"), 62 | .duty_cycle10(50), 63 | .output_clock_frequency11("0 MHz"), 64 | .phase_shift11("0 ps"), 65 | .duty_cycle11(50), 66 | .output_clock_frequency12("0 MHz"), 67 | .phase_shift12("0 ps"), 68 | .duty_cycle12(50), 69 | .output_clock_frequency13("0 MHz"), 70 | .phase_shift13("0 ps"), 71 | .duty_cycle13(50), 72 | .output_clock_frequency14("0 MHz"), 73 | .phase_shift14("0 ps"), 74 | .duty_cycle14(50), 75 | .output_clock_frequency15("0 MHz"), 76 | .phase_shift15("0 ps"), 77 | .duty_cycle15(50), 78 | .output_clock_frequency16("0 MHz"), 79 | .phase_shift16("0 ps"), 80 | .duty_cycle16(50), 81 | .output_clock_frequency17("0 MHz"), 82 | .phase_shift17("0 ps"), 83 | .duty_cycle17(50), 84 | .pll_type("Cyclone V"), 85 | .pll_subtype("Reconfigurable"), 86 | .m_cnt_hi_div(54), 87 | .m_cnt_lo_div(54), 88 | .n_cnt_hi_div(4), 89 | .n_cnt_lo_div(3), 90 | .m_cnt_bypass_en("false"), 91 | .n_cnt_bypass_en("false"), 92 | .m_cnt_odd_div_duty_en("false"), 93 | .n_cnt_odd_div_duty_en("true"), 94 | .c_cnt_hi_div0(15), 95 | .c_cnt_lo_div0(14), 96 | .c_cnt_prst0(1), 97 | .c_cnt_ph_mux_prst0(0), 98 | .c_cnt_in_src0("ph_mux_clk"), 99 | .c_cnt_bypass_en0("false"), 100 | .c_cnt_odd_div_duty_en0("true"), 101 | .c_cnt_hi_div1(1), 102 | .c_cnt_lo_div1(1), 103 | .c_cnt_prst1(1), 104 | .c_cnt_ph_mux_prst1(0), 105 | .c_cnt_in_src1("ph_mux_clk"), 106 | .c_cnt_bypass_en1("true"), 107 | .c_cnt_odd_div_duty_en1("false"), 108 | .c_cnt_hi_div2(1), 109 | .c_cnt_lo_div2(1), 110 | .c_cnt_prst2(1), 111 | .c_cnt_ph_mux_prst2(0), 112 | .c_cnt_in_src2("ph_mux_clk"), 113 | .c_cnt_bypass_en2("true"), 114 | .c_cnt_odd_div_duty_en2("false"), 115 | .c_cnt_hi_div3(1), 116 | .c_cnt_lo_div3(1), 117 | .c_cnt_prst3(1), 118 | .c_cnt_ph_mux_prst3(0), 119 | .c_cnt_in_src3("ph_mux_clk"), 120 | .c_cnt_bypass_en3("true"), 121 | .c_cnt_odd_div_duty_en3("false"), 122 | .c_cnt_hi_div4(1), 123 | .c_cnt_lo_div4(1), 124 | .c_cnt_prst4(1), 125 | .c_cnt_ph_mux_prst4(0), 126 | .c_cnt_in_src4("ph_mux_clk"), 127 | .c_cnt_bypass_en4("true"), 128 | .c_cnt_odd_div_duty_en4("false"), 129 | .c_cnt_hi_div5(1), 130 | .c_cnt_lo_div5(1), 131 | .c_cnt_prst5(1), 132 | .c_cnt_ph_mux_prst5(0), 133 | .c_cnt_in_src5("ph_mux_clk"), 134 | .c_cnt_bypass_en5("true"), 135 | .c_cnt_odd_div_duty_en5("false"), 136 | .c_cnt_hi_div6(1), 137 | .c_cnt_lo_div6(1), 138 | .c_cnt_prst6(1), 139 | .c_cnt_ph_mux_prst6(0), 140 | .c_cnt_in_src6("ph_mux_clk"), 141 | .c_cnt_bypass_en6("true"), 142 | .c_cnt_odd_div_duty_en6("false"), 143 | .c_cnt_hi_div7(1), 144 | .c_cnt_lo_div7(1), 145 | .c_cnt_prst7(1), 146 | .c_cnt_ph_mux_prst7(0), 147 | .c_cnt_in_src7("ph_mux_clk"), 148 | .c_cnt_bypass_en7("true"), 149 | .c_cnt_odd_div_duty_en7("false"), 150 | .c_cnt_hi_div8(1), 151 | .c_cnt_lo_div8(1), 152 | .c_cnt_prst8(1), 153 | .c_cnt_ph_mux_prst8(0), 154 | .c_cnt_in_src8("ph_mux_clk"), 155 | .c_cnt_bypass_en8("true"), 156 | .c_cnt_odd_div_duty_en8("false"), 157 | .c_cnt_hi_div9(1), 158 | .c_cnt_lo_div9(1), 159 | .c_cnt_prst9(1), 160 | .c_cnt_ph_mux_prst9(0), 161 | .c_cnt_in_src9("ph_mux_clk"), 162 | .c_cnt_bypass_en9("true"), 163 | .c_cnt_odd_div_duty_en9("false"), 164 | .c_cnt_hi_div10(1), 165 | .c_cnt_lo_div10(1), 166 | .c_cnt_prst10(1), 167 | .c_cnt_ph_mux_prst10(0), 168 | .c_cnt_in_src10("ph_mux_clk"), 169 | .c_cnt_bypass_en10("true"), 170 | .c_cnt_odd_div_duty_en10("false"), 171 | .c_cnt_hi_div11(1), 172 | .c_cnt_lo_div11(1), 173 | .c_cnt_prst11(1), 174 | .c_cnt_ph_mux_prst11(0), 175 | .c_cnt_in_src11("ph_mux_clk"), 176 | .c_cnt_bypass_en11("true"), 177 | .c_cnt_odd_div_duty_en11("false"), 178 | .c_cnt_hi_div12(1), 179 | .c_cnt_lo_div12(1), 180 | .c_cnt_prst12(1), 181 | .c_cnt_ph_mux_prst12(0), 182 | .c_cnt_in_src12("ph_mux_clk"), 183 | .c_cnt_bypass_en12("true"), 184 | .c_cnt_odd_div_duty_en12("false"), 185 | .c_cnt_hi_div13(1), 186 | .c_cnt_lo_div13(1), 187 | .c_cnt_prst13(1), 188 | .c_cnt_ph_mux_prst13(0), 189 | .c_cnt_in_src13("ph_mux_clk"), 190 | .c_cnt_bypass_en13("true"), 191 | .c_cnt_odd_div_duty_en13("false"), 192 | .c_cnt_hi_div14(1), 193 | .c_cnt_lo_div14(1), 194 | .c_cnt_prst14(1), 195 | .c_cnt_ph_mux_prst14(0), 196 | .c_cnt_in_src14("ph_mux_clk"), 197 | .c_cnt_bypass_en14("true"), 198 | .c_cnt_odd_div_duty_en14("false"), 199 | .c_cnt_hi_div15(1), 200 | .c_cnt_lo_div15(1), 201 | .c_cnt_prst15(1), 202 | .c_cnt_ph_mux_prst15(0), 203 | .c_cnt_in_src15("ph_mux_clk"), 204 | .c_cnt_bypass_en15("true"), 205 | .c_cnt_odd_div_duty_en15("false"), 206 | .c_cnt_hi_div16(1), 207 | .c_cnt_lo_div16(1), 208 | .c_cnt_prst16(1), 209 | .c_cnt_ph_mux_prst16(0), 210 | .c_cnt_in_src16("ph_mux_clk"), 211 | .c_cnt_bypass_en16("true"), 212 | .c_cnt_odd_div_duty_en16("false"), 213 | .c_cnt_hi_div17(1), 214 | .c_cnt_lo_div17(1), 215 | .c_cnt_prst17(1), 216 | .c_cnt_ph_mux_prst17(0), 217 | .c_cnt_in_src17("ph_mux_clk"), 218 | .c_cnt_bypass_en17("true"), 219 | .c_cnt_odd_div_duty_en17("false"), 220 | .pll_vco_div(1), 221 | .pll_cp_current(20), 222 | .pll_bwctrl(10000), 223 | .pll_output_clk_frequency("771.428571 MHz"), 224 | .pll_fractional_division("1"), 225 | .mimic_fbclk_type("none"), 226 | .pll_fbclk_mux_1("glb"), 227 | .pll_fbclk_mux_2("m_cnt"), 228 | .pll_m_cnt_in_src("ph_mux_clk"), 229 | .pll_slf_rst("false") 230 | ) altera_pll_i ( 231 | .rst (rst), 232 | .outclk ({outclk_0}), 233 | .locked (locked), 234 | .reconfig_to_pll (reconfig_to_pll), 235 | .fboutclk ( ), 236 | .fbclk (1'b0), 237 | .refclk (refclk), 238 | .reconfig_from_pll (reconfig_from_pll) 239 | ); 240 | endmodule 241 | 242 | -------------------------------------------------------------------------------- /master_pll_sim.f: -------------------------------------------------------------------------------- 1 | master_pll_sim/master_pll.vho 2 | -------------------------------------------------------------------------------- /master_pll_sim/cadence/cds.lib: -------------------------------------------------------------------------------- 1 | 2 | DEFINE std $CDS_ROOT/tools/inca/files/STD/ 3 | DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/ 4 | DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/ 5 | DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/ 6 | DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/ 7 | DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/ 8 | DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/ 9 | DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/ 10 | DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/ 11 | DEFINE work ./libraries/work/ 12 | DEFINE altera ./libraries/altera/ 13 | DEFINE lpm ./libraries/lpm/ 14 | DEFINE sgate ./libraries/sgate/ 15 | DEFINE altera_mf ./libraries/altera_mf/ 16 | DEFINE altera_lnsim ./libraries/altera_lnsim/ 17 | DEFINE cyclonev ./libraries/cyclonev/ 18 | -------------------------------------------------------------------------------- /master_pll_sim/cadence/hdl.var: -------------------------------------------------------------------------------- 1 | 2 | DEFINE WORK work 3 | -------------------------------------------------------------------------------- /master_pll_sim/synopsys/vcsmx/synopsys_sim.setup: -------------------------------------------------------------------------------- 1 | 2 | WORK > DEFAULT 3 | DEFAULT: ./libraries/work/ 4 | work: ./libraries/work/ 5 | altera: ./libraries/altera/ 6 | lpm: ./libraries/lpm/ 7 | sgate: ./libraries/sgate/ 8 | altera_mf: ./libraries/altera_mf/ 9 | altera_lnsim: ./libraries/altera_lnsim/ 10 | cyclonev: ./libraries/cyclonev/ 11 | LIBRARY_SCAN = TRUE 12 | -------------------------------------------------------------------------------- /master_reconfig.bsf: -------------------------------------------------------------------------------- 1 | /* 2 | WARNING: Do NOT edit the input and output ports in this file in a text 3 | editor if you plan to continue editing the block that represents it in 4 | the Block Editor! File corruption is VERY likely to occur. 5 | */ 6 | /* 7 | Copyright (C) 2018 Intel Corporation. All rights reserved. 8 | Your use of Intel Corporation's design tools, logic functions 9 | and other software and tools, and its AMPP partner logic 10 | functions, and any output files from any of the foregoing 11 | (including device programming or simulation files), and any 12 | associated documentation or information are expressly subject 13 | to the terms and conditions of the Intel Program License 14 | Subscription Agreement, the Intel Quartus Prime License Agreement, 15 | the Intel FPGA IP License Agreement, or other applicable license 16 | agreement, including, without limitation, that your use is for 17 | the sole purpose of programming logic devices manufactured by 18 | Intel and sold by Intel or its authorized distributors. Please 19 | refer to the applicable agreement for further details. 20 | */ 21 | (header "symbol" (version "1.1")) 22 | (symbol 23 | (rect 0 0 416 304) 24 | (text "master_reconfig" (rect 160 -1 226 11)(font "Arial" (font_size 10))) 25 | (text "inst" (rect 8 288 20 300)(font "Arial" )) 26 | (port 27 | (pt 0 72) 28 | (input) 29 | (text "mgmt_clk" (rect 0 0 40 12)(font "Arial" (font_size 8))) 30 | (text "mgmt_clk" (rect 4 61 52 72)(font "Arial" (font_size 8))) 31 | (line (pt 0 72)(pt 128 72)(line_width 1)) 32 | ) 33 | (port 34 | (pt 0 112) 35 | (input) 36 | (text "mgmt_reset" (rect 0 0 49 12)(font "Arial" (font_size 8))) 37 | (text "mgmt_reset" (rect 4 101 64 112)(font "Arial" (font_size 8))) 38 | (line (pt 0 112)(pt 128 112)(line_width 1)) 39 | ) 40 | (port 41 | (pt 0 168) 42 | (input) 43 | (text "mgmt_read" (rect 0 0 47 12)(font "Arial" (font_size 8))) 44 | (text "mgmt_read" (rect 4 157 58 168)(font "Arial" (font_size 8))) 45 | (line (pt 0 168)(pt 128 168)(line_width 1)) 46 | ) 47 | (port 48 | (pt 0 184) 49 | (input) 50 | (text "mgmt_write" (rect 0 0 47 12)(font "Arial" (font_size 8))) 51 | (text "mgmt_write" (rect 4 173 64 184)(font "Arial" (font_size 8))) 52 | (line (pt 0 184)(pt 128 184)(line_width 1)) 53 | ) 54 | (port 55 | (pt 0 216) 56 | (input) 57 | (text "mgmt_address[5..0]" (rect 0 0 81 12)(font "Arial" (font_size 8))) 58 | (text "mgmt_address[5..0]" (rect 4 205 112 216)(font "Arial" (font_size 8))) 59 | (line (pt 0 216)(pt 128 216)(line_width 3)) 60 | ) 61 | (port 62 | (pt 0 232) 63 | (input) 64 | (text "mgmt_writedata[31..0]" (rect 0 0 87 12)(font "Arial" (font_size 8))) 65 | (text "mgmt_writedata[31..0]" (rect 4 221 130 232)(font "Arial" (font_size 8))) 66 | (line (pt 0 232)(pt 128 232)(line_width 3)) 67 | ) 68 | (port 69 | (pt 0 272) 70 | (input) 71 | (text "reconfig_from_pll[63..0]" (rect 0 0 95 12)(font "Arial" (font_size 8))) 72 | (text "reconfig_from_pll[63..0]" (rect 4 261 148 272)(font "Arial" (font_size 8))) 73 | (line (pt 0 272)(pt 128 272)(line_width 3)) 74 | ) 75 | (port 76 | (pt 0 152) 77 | (output) 78 | (text "mgmt_waitrequest" (rect 0 0 73 12)(font "Arial" (font_size 8))) 79 | (text "mgmt_waitrequest" (rect 4 141 100 152)(font "Arial" (font_size 8))) 80 | (line (pt 0 152)(pt 128 152)(line_width 1)) 81 | ) 82 | (port 83 | (pt 0 200) 84 | (output) 85 | (text "mgmt_readdata[31..0]" (rect 0 0 87 12)(font "Arial" (font_size 8))) 86 | (text "mgmt_readdata[31..0]" (rect 4 189 124 200)(font "Arial" (font_size 8))) 87 | (line (pt 0 200)(pt 128 200)(line_width 3)) 88 | ) 89 | (port 90 | (pt 416 72) 91 | (output) 92 | (text "reconfig_to_pll[63..0]" (rect 0 0 82 12)(font "Arial" (font_size 8))) 93 | (text "reconfig_to_pll[63..0]" (rect 310 61 442 72)(font "Arial" (font_size 8))) 94 | (line (pt 416 72)(pt 288 72)(line_width 3)) 95 | ) 96 | (drawing 97 | (text "mgmt_clk" (rect 72 43 192 99)(font "Arial" (color 128 0 0)(font_size 9))) 98 | (text "clk" (rect 133 67 284 144)(font "Arial" (color 0 0 0))) 99 | (text "mgmt_reset" (rect 58 83 176 179)(font "Arial" (color 128 0 0)(font_size 9))) 100 | (text "reset" (rect 133 107 296 224)(font "Arial" (color 0 0 0))) 101 | (text "mgmt_avalon_slave" (rect 13 123 128 259)(font "Arial" (color 128 0 0)(font_size 9))) 102 | (text "waitrequest" (rect 133 147 332 304)(font "Arial" (color 0 0 0))) 103 | (text "read" (rect 133 163 290 336)(font "Arial" (color 0 0 0))) 104 | (text "write" (rect 133 179 296 368)(font "Arial" (color 0 0 0))) 105 | (text "readdata" (rect 133 195 314 400)(font "Arial" (color 0 0 0))) 106 | (text "address" (rect 133 211 308 432)(font "Arial" (color 0 0 0))) 107 | (text "writedata" (rect 133 227 320 464)(font "Arial" (color 0 0 0))) 108 | (text "reconfig_to_pll" (rect 289 43 668 99)(font "Arial" (color 128 0 0)(font_size 9))) 109 | (text "reconfig_to_pll" (rect 221 67 532 144)(font "Arial" (color 0 0 0))) 110 | (text "reconfig_from_pll" (rect 25 243 152 499)(font "Arial" (color 128 0 0)(font_size 9))) 111 | (text "reconfig_from_pll" (rect 133 267 368 544)(font "Arial" (color 0 0 0))) 112 | (text " altera_pll_reconfig " (rect 333 288 792 586)(font "Arial" )) 113 | (line (pt 128 32)(pt 288 32)(line_width 1)) 114 | (line (pt 288 32)(pt 288 288)(line_width 1)) 115 | (line (pt 128 288)(pt 288 288)(line_width 1)) 116 | (line (pt 128 32)(pt 128 288)(line_width 1)) 117 | (line (pt 129 52)(pt 129 76)(line_width 1)) 118 | (line (pt 130 52)(pt 130 76)(line_width 1)) 119 | (line (pt 129 92)(pt 129 116)(line_width 1)) 120 | (line (pt 130 92)(pt 130 116)(line_width 1)) 121 | (line (pt 129 132)(pt 129 236)(line_width 1)) 122 | (line (pt 130 132)(pt 130 236)(line_width 1)) 123 | (line (pt 287 52)(pt 287 76)(line_width 1)) 124 | (line (pt 286 52)(pt 286 76)(line_width 1)) 125 | (line (pt 129 252)(pt 129 276)(line_width 1)) 126 | (line (pt 130 252)(pt 130 276)(line_width 1)) 127 | (line (pt 0 0)(pt 416 0)(line_width 1)) 128 | (line (pt 416 0)(pt 416 304)(line_width 1)) 129 | (line (pt 0 304)(pt 416 304)(line_width 1)) 130 | (line (pt 0 0)(pt 0 304)(line_width 1)) 131 | ) 132 | ) 133 | -------------------------------------------------------------------------------- /master_reconfig.cmp: -------------------------------------------------------------------------------- 1 | component master_reconfig is 2 | generic ( 3 | ENABLE_BYTEENABLE : boolean := false; 4 | BYTEENABLE_WIDTH : integer := 4; 5 | RECONFIG_ADDR_WIDTH : integer := 6; 6 | RECONFIG_DATA_WIDTH : integer := 32; 7 | reconf_width : integer := 64; 8 | WAIT_FOR_LOCK : boolean := true 9 | ); 10 | port ( 11 | mgmt_clk : in std_logic := 'X'; -- clk 12 | mgmt_reset : in std_logic := 'X'; -- reset 13 | mgmt_waitrequest : out std_logic; -- waitrequest 14 | mgmt_read : in std_logic := 'X'; -- read 15 | mgmt_write : in std_logic := 'X'; -- write 16 | mgmt_readdata : out std_logic_vector(31 downto 0); -- readdata 17 | mgmt_address : in std_logic_vector(5 downto 0) := (others => 'X'); -- address 18 | mgmt_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata 19 | reconfig_to_pll : out std_logic_vector(63 downto 0); -- reconfig_to_pll 20 | reconfig_from_pll : in std_logic_vector(63 downto 0) := (others => 'X') -- reconfig_from_pll 21 | ); 22 | end component master_reconfig; 23 | 24 | -------------------------------------------------------------------------------- /master_reconfig.ppf: -------------------------------------------------------------------------------- 1 | 2 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | -------------------------------------------------------------------------------- /master_reconfig.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -entity "master_reconfig" -library "master_reconfig" -name IP_TOOL_NAME "altera_pll_reconfig" 2 | set_global_assignment -entity "master_reconfig" -library "master_reconfig" -name IP_TOOL_VERSION "18.0" 3 | set_global_assignment -entity "master_reconfig" -library "master_reconfig" -name IP_TOOL_ENV "mwpim" 4 | set_global_assignment -library "master_reconfig" -name MISC_FILE [file join $::quartus(qip_path) "master_reconfig.cmp"] 5 | set_global_assignment -entity "master_reconfig" -library "master_reconfig" -name IP_TARGETED_DEVICE_FAMILY "Cyclone V" 6 | set_global_assignment -entity "master_reconfig" -library "master_reconfig" -name IP_GENERATED_DEVICE_FAMILY "{Cyclone V}" 7 | set_global_assignment -entity "master_reconfig" -library "master_reconfig" -name IP_QSYS_MODE "UNKNOWN" 8 | set_global_assignment -name SYNTHESIS_ONLY_QIP ON 9 | set_global_assignment -entity "master_reconfig" -library "master_reconfig" -name IP_COMPONENT_NAME "bWFzdGVyX3JlY29uZmln" 10 | set_global_assignment -entity "master_reconfig" -library "master_reconfig" -name IP_COMPONENT_DISPLAY_NAME "UExMIFJlY29uZmlnIEludGVsIEZQR0EgSVA=" 11 | set_global_assignment -entity "master_reconfig" -library "master_reconfig" -name IP_COMPONENT_REPORT_HIERARCHY "Off" 12 | set_global_assignment -entity "master_reconfig" -library "master_reconfig" -name IP_COMPONENT_INTERNAL "Off" 13 | set_global_assignment -entity "master_reconfig" -library "master_reconfig" -name IP_COMPONENT_AUTHOR "SW50ZWwgQ29ycG9yYXRpb24=" 14 | set_global_assignment -entity "master_reconfig" -library "master_reconfig" -name IP_COMPONENT_VERSION "MTguMA==" 15 | set_global_assignment -entity "master_reconfig" -library "master_reconfig" -name IP_COMPONENT_DESCRIPTION "SW50ZWwgUGhhc2UtTG9ja2VkIExvb3AgUmVjb25maWd1cmF0aW9uIEJsb2Nr" 16 | set_global_assignment -entity "master_reconfig" -library "master_reconfig" -name IP_COMPONENT_PARAMETER "RU5BQkxFX0JZVEVFTkFCTEU=::ZmFsc2U=::QWRkIGJ5dGVlbmFibGUgcG9ydA==" 17 | set_global_assignment -entity "master_reconfig" -library "master_reconfig" -name IP_COMPONENT_PARAMETER "QllURUVOQUJMRV9XSURUSA==::NA==::QllURUVOQUJMRV9XSURUSA==" 18 | set_global_assignment -entity "master_reconfig" -library "master_reconfig" -name IP_COMPONENT_PARAMETER "UkVDT05GSUdfQUREUl9XSURUSA==::Ng==::UkVDT05GSUdfQUREUl9XSURUSA==" 19 | set_global_assignment -entity "master_reconfig" -library "master_reconfig" -name IP_COMPONENT_PARAMETER "UkVDT05GSUdfREFUQV9XSURUSA==::MzI=::UkVDT05GSUdfREFUQV9XSURUSA==" 20 | set_global_assignment -entity "master_reconfig" -library "master_reconfig" -name IP_COMPONENT_PARAMETER "cmVjb25mX3dpZHRo::NjQ=::cmVjb25mX3dpZHRo" 21 | set_global_assignment -entity "master_reconfig" -library "master_reconfig" -name IP_COMPONENT_PARAMETER "V0FJVF9GT1JfTE9DSw==::dHJ1ZQ==::V0FJVF9GT1JfTE9DSw==" 22 | set_global_assignment -entity "altera_pll_reconfig_top" -library "master_reconfig" -name IP_COMPONENT_NAME "YWx0ZXJhX3BsbF9yZWNvbmZpZ190b3A=" 23 | set_global_assignment -entity "altera_pll_reconfig_top" -library "master_reconfig" -name IP_COMPONENT_DISPLAY_NAME "UExMIFJlY29uZmlnIEludGVsIEZQR0EgSVA=" 24 | set_global_assignment -entity "altera_pll_reconfig_top" -library "master_reconfig" -name IP_COMPONENT_REPORT_HIERARCHY "Off" 25 | set_global_assignment -entity "altera_pll_reconfig_top" -library "master_reconfig" -name IP_COMPONENT_INTERNAL "Off" 26 | set_global_assignment -entity "altera_pll_reconfig_top" -library "master_reconfig" -name IP_COMPONENT_AUTHOR "SW50ZWwgQ29ycG9yYXRpb24=" 27 | set_global_assignment -entity "altera_pll_reconfig_top" -library "master_reconfig" -name IP_COMPONENT_VERSION "MTguMA==" 28 | set_global_assignment -entity "altera_pll_reconfig_top" -library "master_reconfig" -name IP_COMPONENT_DESCRIPTION "SW50ZWwgUGhhc2UtTG9ja2VkIExvb3AgUmVjb25maWd1cmF0aW9uIEJsb2Nr" 29 | set_global_assignment -entity "altera_pll_reconfig_top" -library "master_reconfig" -name IP_COMPONENT_PARAMETER "ZGV2aWNlX2ZhbWlseQ==::Q3ljbG9uZSBW::ZGV2aWNlX2ZhbWlseQ==" 30 | set_global_assignment -entity "altera_pll_reconfig_top" -library "master_reconfig" -name IP_COMPONENT_PARAMETER "RU5BQkxFX01JRg==::ZmFsc2U=::RW5hYmxlIE1JRiBTdHJlYW1pbmc=" 31 | set_global_assignment -entity "altera_pll_reconfig_top" -library "master_reconfig" -name IP_COMPONENT_PARAMETER "RU5BQkxFX0JZVEVFTkFCTEU=::ZmFsc2U=::QWRkIGJ5dGVlbmFibGUgcG9ydA==" 32 | set_global_assignment -entity "altera_pll_reconfig_top" -library "master_reconfig" -name IP_COMPONENT_PARAMETER "QllURUVOQUJMRV9XSURUSA==::NA==::QllURUVOQUJMRV9XSURUSA==" 33 | set_global_assignment -entity "altera_pll_reconfig_top" -library "master_reconfig" -name IP_COMPONENT_PARAMETER "UkVDT05GSUdfQUREUl9XSURUSA==::Ng==::UkVDT05GSUdfQUREUl9XSURUSA==" 34 | set_global_assignment -entity "altera_pll_reconfig_top" -library "master_reconfig" -name IP_COMPONENT_PARAMETER "UkVDT05GSUdfREFUQV9XSURUSA==::MzI=::UkVDT05GSUdfREFUQV9XSURUSA==" 35 | set_global_assignment -entity "altera_pll_reconfig_top" -library "master_reconfig" -name IP_COMPONENT_PARAMETER "cmVjb25mX3dpZHRo::NjQ=::cmVjb25mX3dpZHRo" 36 | set_global_assignment -entity "altera_pll_reconfig_top" -library "master_reconfig" -name IP_COMPONENT_PARAMETER "V0FJVF9GT1JfTE9DSw==::dHJ1ZQ==::V0FJVF9GT1JfTE9DSw==" 37 | 38 | set_global_assignment -library "master_reconfig" -name VHDL_FILE [file join $::quartus(qip_path) "master_reconfig.vhd"] 39 | set_global_assignment -library "master_reconfig" -name VERILOG_FILE [file join $::quartus(qip_path) "master_reconfig/altera_pll_reconfig_top.v"] 40 | set_global_assignment -library "master_reconfig" -name VERILOG_FILE [file join $::quartus(qip_path) "master_reconfig/altera_pll_reconfig_core.v"] 41 | set_global_assignment -library "master_reconfig" -name VERILOG_FILE [file join $::quartus(qip_path) "master_reconfig/altera_std_synchronizer.v"] 42 | 43 | set_global_assignment -entity "altera_pll_reconfig_top" -library "master_reconfig" -name IP_TOOL_NAME "altera_pll_reconfig" 44 | set_global_assignment -entity "altera_pll_reconfig_top" -library "master_reconfig" -name IP_TOOL_VERSION "18.0" 45 | set_global_assignment -entity "altera_pll_reconfig_top" -library "master_reconfig" -name IP_TOOL_ENV "mwpim" 46 | -------------------------------------------------------------------------------- /master_reconfig.sip: -------------------------------------------------------------------------------- 1 | set_global_assignment -entity "master_reconfig" -library "lib_master_reconfig" -name IP_TOOL_NAME "altera_pll_reconfig" 2 | set_global_assignment -entity "master_reconfig" -library "lib_master_reconfig" -name IP_TOOL_VERSION "18.0" 3 | set_global_assignment -entity "master_reconfig" -library "lib_master_reconfig" -name IP_TOOL_ENV "mwpim" 4 | set_global_assignment -library "lib_master_reconfig" -name SPD_FILE [file join $::quartus(sip_path) "master_reconfig.spd"] 5 | 6 | set_global_assignment -library "lib_master_reconfig" -name MISC_FILE [file join $::quartus(sip_path) "master_reconfig_sim/master_reconfig.vhd"] 7 | set_global_assignment -library "lib_master_reconfig" -name MISC_FILE [file join $::quartus(sip_path) "master_reconfig_sim/altera_pll_reconfig/altera_pll_reconfig_top.v"] 8 | set_global_assignment -library "lib_master_reconfig" -name MISC_FILE [file join $::quartus(sip_path) "master_reconfig_sim/altera_pll_reconfig/altera_pll_reconfig_core.v"] 9 | set_global_assignment -library "lib_master_reconfig" -name MISC_FILE [file join $::quartus(sip_path) "master_reconfig_sim/altera_pll_reconfig/altera_std_synchronizer.v"] 10 | -------------------------------------------------------------------------------- /master_reconfig.spd: -------------------------------------------------------------------------------- 1 | 2 | 3 | 7 | 11 | 15 | 16 | 17 | 18 | 19 | -------------------------------------------------------------------------------- /master_reconfig.vhd: -------------------------------------------------------------------------------- 1 | -- megafunction wizard: %PLL Reconfig Intel FPGA IP v18.0% 2 | -- GENERATION: XML 3 | -- master_reconfig.vhd 4 | 5 | -- Generated using ACDS version 18.0 614 6 | 7 | library IEEE; 8 | use IEEE.std_logic_1164.all; 9 | use IEEE.numeric_std.all; 10 | 11 | entity master_reconfig is 12 | generic ( 13 | ENABLE_BYTEENABLE : boolean := false; 14 | BYTEENABLE_WIDTH : integer := 4; 15 | RECONFIG_ADDR_WIDTH : integer := 6; 16 | RECONFIG_DATA_WIDTH : integer := 32; 17 | reconf_width : integer := 64; 18 | WAIT_FOR_LOCK : boolean := true 19 | ); 20 | port ( 21 | mgmt_clk : in std_logic := '0'; -- mgmt_clk.clk 22 | mgmt_reset : in std_logic := '0'; -- mgmt_reset.reset 23 | mgmt_waitrequest : out std_logic; -- mgmt_avalon_slave.waitrequest 24 | mgmt_read : in std_logic := '0'; -- .read 25 | mgmt_write : in std_logic := '0'; -- .write 26 | mgmt_readdata : out std_logic_vector(31 downto 0); -- .readdata 27 | mgmt_address : in std_logic_vector(5 downto 0) := (others => '0'); -- .address 28 | mgmt_writedata : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata 29 | reconfig_to_pll : out std_logic_vector(63 downto 0); -- reconfig_to_pll.reconfig_to_pll 30 | reconfig_from_pll : in std_logic_vector(63 downto 0) := (others => '0') -- reconfig_from_pll.reconfig_from_pll 31 | ); 32 | end entity master_reconfig; 33 | 34 | architecture rtl of master_reconfig is 35 | component altera_pll_reconfig_top is 36 | generic ( 37 | device_family : string := ""; 38 | ENABLE_MIF : boolean := false; 39 | MIF_FILE_NAME : string := ""; 40 | ENABLE_BYTEENABLE : boolean := false; 41 | BYTEENABLE_WIDTH : integer := 4; 42 | RECONFIG_ADDR_WIDTH : integer := 6; 43 | RECONFIG_DATA_WIDTH : integer := 32; 44 | reconf_width : integer := 64; 45 | WAIT_FOR_LOCK : boolean := true 46 | ); 47 | port ( 48 | mgmt_clk : in std_logic := 'X'; -- clk 49 | mgmt_reset : in std_logic := 'X'; -- reset 50 | mgmt_waitrequest : out std_logic; -- waitrequest 51 | mgmt_read : in std_logic := 'X'; -- read 52 | mgmt_write : in std_logic := 'X'; -- write 53 | mgmt_readdata : out std_logic_vector(31 downto 0); -- readdata 54 | mgmt_address : in std_logic_vector(5 downto 0) := (others => 'X'); -- address 55 | mgmt_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata 56 | reconfig_to_pll : out std_logic_vector(63 downto 0); -- reconfig_to_pll 57 | reconfig_from_pll : in std_logic_vector(63 downto 0) := (others => 'X'); -- reconfig_from_pll 58 | mgmt_byteenable : in std_logic_vector(3 downto 0) := (others => 'X') -- byteenable 59 | ); 60 | end component altera_pll_reconfig_top; 61 | 62 | begin 63 | 64 | master_reconfig_inst : component altera_pll_reconfig_top 65 | generic map ( 66 | device_family => "Cyclone V", 67 | ENABLE_MIF => false, 68 | MIF_FILE_NAME => "", 69 | ENABLE_BYTEENABLE => ENABLE_BYTEENABLE, 70 | BYTEENABLE_WIDTH => BYTEENABLE_WIDTH, 71 | RECONFIG_ADDR_WIDTH => RECONFIG_ADDR_WIDTH, 72 | RECONFIG_DATA_WIDTH => RECONFIG_DATA_WIDTH, 73 | reconf_width => reconf_width, 74 | WAIT_FOR_LOCK => WAIT_FOR_LOCK 75 | ) 76 | port map ( 77 | mgmt_clk => mgmt_clk, -- mgmt_clk.clk 78 | mgmt_reset => mgmt_reset, -- mgmt_reset.reset 79 | mgmt_waitrequest => mgmt_waitrequest, -- mgmt_avalon_slave.waitrequest 80 | mgmt_read => mgmt_read, -- .read 81 | mgmt_write => mgmt_write, -- .write 82 | mgmt_readdata => mgmt_readdata, -- .readdata 83 | mgmt_address => mgmt_address, -- .address 84 | mgmt_writedata => mgmt_writedata, -- .writedata 85 | reconfig_to_pll => reconfig_to_pll, -- reconfig_to_pll.reconfig_to_pll 86 | reconfig_from_pll => reconfig_from_pll, -- reconfig_from_pll.reconfig_from_pll 87 | mgmt_byteenable => "0000" -- (terminated) 88 | ); 89 | 90 | end architecture rtl; -- of master_reconfig 91 | -- Retrieval info: 92 | -- 117 | -- Retrieval info: 118 | -- Retrieval info: 119 | -- Retrieval info: 120 | -- Retrieval info: 121 | -- Retrieval info: 122 | -- Retrieval info: 123 | -- IPFS_FILES : master_reconfig.vho 124 | -- RELATED_FILES: master_reconfig.vhd, altera_pll_reconfig_top.v, altera_pll_reconfig_core.v, altera_std_synchronizer.v 125 | -------------------------------------------------------------------------------- /master_reconfig/altera_std_synchronizer.v: -------------------------------------------------------------------------------- 1 | // (C) 2001-2018 Intel Corporation. All rights reserved. 2 | // Your use of Intel Corporation's design tools, logic functions and other 3 | // software and tools, and its AMPP partner logic functions, and any output 4 | // files from any of the foregoing (including device programming or simulation 5 | // files), and any associated documentation or information are expressly subject 6 | // to the terms and conditions of the Intel Program License Subscription 7 | // Agreement, Intel FPGA IP License Agreement, or other applicable 8 | // license agreement, including, without limitation, that your use is for the 9 | // sole purpose of programming logic devices manufactured by Intel and sold by 10 | // Intel or its authorized distributors. Please refer to the applicable 11 | // agreement for further details. 12 | 13 | 14 | // $Id: //acds/rel/18.0std/ip/sopc/components/primitives/altera_std_synchronizer/altera_std_synchronizer.v#1 $ 15 | // $Revision: #1 $ 16 | // $Date: 2018/01/31 $ 17 | // $Author: psgswbuild $ 18 | //----------------------------------------------------------------------------- 19 | // 20 | // File: altera_std_synchronizer.v 21 | // 22 | // Abstract: Single bit clock domain crossing synchronizer. 23 | // Composed of two or more flip flops connected in series. 24 | // Random metastable condition is simulated when the 25 | // __ALTERA_STD__METASTABLE_SIM macro is defined. 26 | // Use +define+__ALTERA_STD__METASTABLE_SIM argument 27 | // on the Verilog simulator compiler command line to 28 | // enable this mode. In addition, dfine the macro 29 | // __ALTERA_STD__METASTABLE_SIM_VERBOSE to get console output 30 | // with every metastable event generated in the synchronizer. 31 | // 32 | // Copyright (C) Altera Corporation 2009, All Rights Reserved 33 | //----------------------------------------------------------------------------- 34 | 35 | `timescale 1ns / 1ns 36 | 37 | module altera_std_synchronizer ( 38 | clk, 39 | reset_n, 40 | din, 41 | dout 42 | ); 43 | 44 | parameter depth = 3; // This value must be >= 2 ! 45 | 46 | input clk; 47 | input reset_n; 48 | input din; 49 | output dout; 50 | 51 | // QuartusII synthesis directives: 52 | // 1. Preserve all registers ie. do not touch them. 53 | // 2. Do not merge other flip-flops with synchronizer flip-flops. 54 | // QuartusII TimeQuest directives: 55 | // 1. Identify all flip-flops in this module as members of the synchronizer 56 | // to enable automatic metastability MTBF analysis. 57 | // 2. Cut all timing paths terminating on data input pin of the first flop din_s1. 58 | 59 | (* altera_attribute = {"-name ADV_NETLIST_OPT_ALLOWED NEVER_ALLOW; -name SYNCHRONIZER_IDENTIFICATION FORCED_IF_ASYNCHRONOUS; -name DONT_MERGE_REGISTER ON; -name PRESERVE_REGISTER ON; -name SDC_STATEMENT \"set_false_path -to [get_keepers {*altera_std_synchronizer:*|din_s1}]\" "} *) reg din_s1; 60 | 61 | (* altera_attribute = {"-name ADV_NETLIST_OPT_ALLOWED NEVER_ALLOW; -name SYNCHRONIZER_IDENTIFICATION FORCED_IF_ASYNCHRONOUS; -name DONT_MERGE_REGISTER ON; -name PRESERVE_REGISTER ON"} *) reg [depth-2:0] dreg; 62 | 63 | //synthesis translate_off 64 | initial begin 65 | if (depth <2) begin 66 | $display("%m: Error: synchronizer length: %0d less than 2.", depth); 67 | end 68 | end 69 | 70 | // the first synchronizer register is either a simple D flop for synthesis 71 | // and non-metastable simulation or a D flop with a method to inject random 72 | // metastable events resulting in random delay of [0,1] cycles 73 | 74 | `ifdef __ALTERA_STD__METASTABLE_SIM 75 | 76 | reg[31:0] RANDOM_SEED = 123456; 77 | wire next_din_s1; 78 | wire dout; 79 | reg din_last; 80 | reg random; 81 | event metastable_event; // hook for debug monitoring 82 | 83 | initial begin 84 | $display("%m: Info: Metastable event injection simulation mode enabled"); 85 | end 86 | 87 | always @(posedge clk) begin 88 | if (reset_n == 0) 89 | random <= $random(RANDOM_SEED); 90 | else 91 | random <= $random; 92 | end 93 | 94 | assign next_din_s1 = (din_last ^ din) ? random : din; 95 | 96 | always @(posedge clk or negedge reset_n) begin 97 | if (reset_n == 0) 98 | din_last <= 1'b0; 99 | else 100 | din_last <= din; 101 | end 102 | 103 | always @(posedge clk or negedge reset_n) begin 104 | if (reset_n == 0) 105 | din_s1 <= 1'b0; 106 | else 107 | din_s1 <= next_din_s1; 108 | end 109 | 110 | `else 111 | 112 | //synthesis translate_on 113 | always @(posedge clk or negedge reset_n) begin 114 | if (reset_n == 0) 115 | din_s1 <= 1'b0; 116 | else 117 | din_s1 <= din; 118 | end 119 | //synthesis translate_off 120 | 121 | `endif 122 | 123 | `ifdef __ALTERA_STD__METASTABLE_SIM_VERBOSE 124 | always @(*) begin 125 | if (reset_n && (din_last != din) && (random != din)) begin 126 | $display("%m: Verbose Info: metastable event @ time %t", $time); 127 | ->metastable_event; 128 | end 129 | end 130 | `endif 131 | 132 | //synthesis translate_on 133 | 134 | // the remaining synchronizer registers form a simple shift register 135 | // of length depth-1 136 | generate 137 | if (depth < 3) begin 138 | always @(posedge clk or negedge reset_n) begin 139 | if (reset_n == 0) 140 | dreg <= {depth-1{1'b0}}; 141 | else 142 | dreg <= din_s1; 143 | end 144 | end else begin 145 | always @(posedge clk or negedge reset_n) begin 146 | if (reset_n == 0) 147 | dreg <= {depth-1{1'b0}}; 148 | else 149 | dreg <= {dreg[depth-3:0], din_s1}; 150 | end 151 | end 152 | endgenerate 153 | 154 | assign dout = dreg[depth-2]; 155 | 156 | endmodule 157 | 158 | 159 | 160 | -------------------------------------------------------------------------------- /master_reconfig_sim.f: -------------------------------------------------------------------------------- 1 | master_reconfig_sim/master_reconfig.vhd 2 | master_reconfig_sim/altera_pll_reconfig/altera_pll_reconfig_top.v 3 | master_reconfig_sim/altera_pll_reconfig/altera_pll_reconfig_core.v 4 | master_reconfig_sim/altera_pll_reconfig/altera_std_synchronizer.v 5 | -------------------------------------------------------------------------------- /master_reconfig_sim/altera_pll_reconfig/altera_std_synchronizer.v: -------------------------------------------------------------------------------- 1 | // (C) 2001-2018 Intel Corporation. All rights reserved. 2 | // Your use of Intel Corporation's design tools, logic functions and other 3 | // software and tools, and its AMPP partner logic functions, and any output 4 | // files from any of the foregoing (including device programming or simulation 5 | // files), and any associated documentation or information are expressly subject 6 | // to the terms and conditions of the Intel Program License Subscription 7 | // Agreement, Intel FPGA IP License Agreement, or other applicable 8 | // license agreement, including, without limitation, that your use is for the 9 | // sole purpose of programming logic devices manufactured by Intel and sold by 10 | // Intel or its authorized distributors. Please refer to the applicable 11 | // agreement for further details. 12 | 13 | 14 | // $Id: //acds/rel/18.0std/ip/sopc/components/primitives/altera_std_synchronizer/altera_std_synchronizer.v#1 $ 15 | // $Revision: #1 $ 16 | // $Date: 2018/01/31 $ 17 | // $Author: psgswbuild $ 18 | //----------------------------------------------------------------------------- 19 | // 20 | // File: altera_std_synchronizer.v 21 | // 22 | // Abstract: Single bit clock domain crossing synchronizer. 23 | // Composed of two or more flip flops connected in series. 24 | // Random metastable condition is simulated when the 25 | // __ALTERA_STD__METASTABLE_SIM macro is defined. 26 | // Use +define+__ALTERA_STD__METASTABLE_SIM argument 27 | // on the Verilog simulator compiler command line to 28 | // enable this mode. In addition, dfine the macro 29 | // __ALTERA_STD__METASTABLE_SIM_VERBOSE to get console output 30 | // with every metastable event generated in the synchronizer. 31 | // 32 | // Copyright (C) Altera Corporation 2009, All Rights Reserved 33 | //----------------------------------------------------------------------------- 34 | 35 | `timescale 1ns / 1ns 36 | 37 | module altera_std_synchronizer ( 38 | clk, 39 | reset_n, 40 | din, 41 | dout 42 | ); 43 | 44 | parameter depth = 3; // This value must be >= 2 ! 45 | 46 | input clk; 47 | input reset_n; 48 | input din; 49 | output dout; 50 | 51 | // QuartusII synthesis directives: 52 | // 1. Preserve all registers ie. do not touch them. 53 | // 2. Do not merge other flip-flops with synchronizer flip-flops. 54 | // QuartusII TimeQuest directives: 55 | // 1. Identify all flip-flops in this module as members of the synchronizer 56 | // to enable automatic metastability MTBF analysis. 57 | // 2. Cut all timing paths terminating on data input pin of the first flop din_s1. 58 | 59 | (* altera_attribute = {"-name ADV_NETLIST_OPT_ALLOWED NEVER_ALLOW; -name SYNCHRONIZER_IDENTIFICATION FORCED_IF_ASYNCHRONOUS; -name DONT_MERGE_REGISTER ON; -name PRESERVE_REGISTER ON; -name SDC_STATEMENT \"set_false_path -to [get_keepers {*altera_std_synchronizer:*|din_s1}]\" "} *) reg din_s1; 60 | 61 | (* altera_attribute = {"-name ADV_NETLIST_OPT_ALLOWED NEVER_ALLOW; -name SYNCHRONIZER_IDENTIFICATION FORCED_IF_ASYNCHRONOUS; -name DONT_MERGE_REGISTER ON; -name PRESERVE_REGISTER ON"} *) reg [depth-2:0] dreg; 62 | 63 | //synthesis translate_off 64 | initial begin 65 | if (depth <2) begin 66 | $display("%m: Error: synchronizer length: %0d less than 2.", depth); 67 | end 68 | end 69 | 70 | // the first synchronizer register is either a simple D flop for synthesis 71 | // and non-metastable simulation or a D flop with a method to inject random 72 | // metastable events resulting in random delay of [0,1] cycles 73 | 74 | `ifdef __ALTERA_STD__METASTABLE_SIM 75 | 76 | reg[31:0] RANDOM_SEED = 123456; 77 | wire next_din_s1; 78 | wire dout; 79 | reg din_last; 80 | reg random; 81 | event metastable_event; // hook for debug monitoring 82 | 83 | initial begin 84 | $display("%m: Info: Metastable event injection simulation mode enabled"); 85 | end 86 | 87 | always @(posedge clk) begin 88 | if (reset_n == 0) 89 | random <= $random(RANDOM_SEED); 90 | else 91 | random <= $random; 92 | end 93 | 94 | assign next_din_s1 = (din_last ^ din) ? random : din; 95 | 96 | always @(posedge clk or negedge reset_n) begin 97 | if (reset_n == 0) 98 | din_last <= 1'b0; 99 | else 100 | din_last <= din; 101 | end 102 | 103 | always @(posedge clk or negedge reset_n) begin 104 | if (reset_n == 0) 105 | din_s1 <= 1'b0; 106 | else 107 | din_s1 <= next_din_s1; 108 | end 109 | 110 | `else 111 | 112 | //synthesis translate_on 113 | always @(posedge clk or negedge reset_n) begin 114 | if (reset_n == 0) 115 | din_s1 <= 1'b0; 116 | else 117 | din_s1 <= din; 118 | end 119 | //synthesis translate_off 120 | 121 | `endif 122 | 123 | `ifdef __ALTERA_STD__METASTABLE_SIM_VERBOSE 124 | always @(*) begin 125 | if (reset_n && (din_last != din) && (random != din)) begin 126 | $display("%m: Verbose Info: metastable event @ time %t", $time); 127 | ->metastable_event; 128 | end 129 | end 130 | `endif 131 | 132 | //synthesis translate_on 133 | 134 | // the remaining synchronizer registers form a simple shift register 135 | // of length depth-1 136 | generate 137 | if (depth < 3) begin 138 | always @(posedge clk or negedge reset_n) begin 139 | if (reset_n == 0) 140 | dreg <= {depth-1{1'b0}}; 141 | else 142 | dreg <= din_s1; 143 | end 144 | end else begin 145 | always @(posedge clk or negedge reset_n) begin 146 | if (reset_n == 0) 147 | dreg <= {depth-1{1'b0}}; 148 | else 149 | dreg <= {dreg[depth-3:0], din_s1}; 150 | end 151 | end 152 | endgenerate 153 | 154 | assign dout = dreg[depth-2]; 155 | 156 | endmodule 157 | 158 | 159 | 160 | -------------------------------------------------------------------------------- /master_reconfig_sim/cadence/cds.lib: -------------------------------------------------------------------------------- 1 | 2 | DEFINE std $CDS_ROOT/tools/inca/files/STD/ 3 | DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/ 4 | DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/ 5 | DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/ 6 | DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/ 7 | DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/ 8 | DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/ 9 | DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/ 10 | DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/ 11 | DEFINE work ./libraries/work/ 12 | DEFINE master_reconfig ./libraries/master_reconfig/ 13 | DEFINE altera_ver ./libraries/altera_ver/ 14 | DEFINE lpm_ver ./libraries/lpm_ver/ 15 | DEFINE sgate_ver ./libraries/sgate_ver/ 16 | DEFINE altera_mf_ver ./libraries/altera_mf_ver/ 17 | DEFINE cyclonev_ver ./libraries/cyclonev_ver/ 18 | DEFINE cyclonev_hssi_ver ./libraries/cyclonev_hssi_ver/ 19 | DEFINE cyclonev_pcie_hip_ver ./libraries/cyclonev_pcie_hip_ver/ 20 | DEFINE altera ./libraries/altera/ 21 | DEFINE lpm ./libraries/lpm/ 22 | DEFINE sgate ./libraries/sgate/ 23 | DEFINE altera_mf ./libraries/altera_mf/ 24 | DEFINE altera_lnsim ./libraries/altera_lnsim/ 25 | DEFINE cyclonev ./libraries/cyclonev/ 26 | -------------------------------------------------------------------------------- /master_reconfig_sim/cadence/cds_libs/master_reconfig.cds.lib: -------------------------------------------------------------------------------- 1 | 2 | DEFINE std $CDS_ROOT/tools/inca/files/STD/ 3 | DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/ 4 | DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/ 5 | DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/ 6 | DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/ 7 | DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/ 8 | DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/ 9 | DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/ 10 | DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/ 11 | DEFINE work ./../libraries/work/ 12 | DEFINE altera_ver ./../libraries/altera_ver/ 13 | DEFINE lpm_ver ./../libraries/lpm_ver/ 14 | DEFINE sgate_ver ./../libraries/sgate_ver/ 15 | DEFINE altera_mf_ver ./../libraries/altera_mf_ver/ 16 | DEFINE cyclonev_ver ./../libraries/cyclonev_ver/ 17 | DEFINE cyclonev_hssi_ver ./../libraries/cyclonev_hssi_ver/ 18 | DEFINE cyclonev_pcie_hip_ver ./../libraries/cyclonev_pcie_hip_ver/ 19 | DEFINE altera ./../libraries/altera/ 20 | DEFINE lpm ./../libraries/lpm/ 21 | DEFINE sgate ./../libraries/sgate/ 22 | DEFINE altera_mf ./../libraries/altera_mf/ 23 | DEFINE altera_lnsim ./../libraries/altera_lnsim/ 24 | DEFINE cyclonev ./../libraries/cyclonev/ 25 | DEFINE master_reconfig ./../libraries/master_reconfig/ 26 | -------------------------------------------------------------------------------- /master_reconfig_sim/cadence/hdl.var: -------------------------------------------------------------------------------- 1 | 2 | DEFINE WORK work 3 | -------------------------------------------------------------------------------- /master_reconfig_sim/master_reconfig.vhd: -------------------------------------------------------------------------------- 1 | -- master_reconfig.vhd 2 | 3 | -- Generated using ACDS version 18.0 614 4 | 5 | library IEEE; 6 | use IEEE.std_logic_1164.all; 7 | use IEEE.numeric_std.all; 8 | 9 | entity master_reconfig is 10 | port ( 11 | mgmt_clk : in std_logic := '0'; -- mgmt_clk.clk 12 | mgmt_reset : in std_logic := '0'; -- mgmt_reset.reset 13 | mgmt_waitrequest : out std_logic; -- mgmt_avalon_slave.waitrequest 14 | mgmt_read : in std_logic := '0'; -- .read 15 | mgmt_write : in std_logic := '0'; -- .write 16 | mgmt_readdata : out std_logic_vector(31 downto 0); -- .readdata 17 | mgmt_address : in std_logic_vector(5 downto 0) := (others => '0'); -- .address 18 | mgmt_writedata : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata 19 | reconfig_to_pll : out std_logic_vector(63 downto 0); -- reconfig_to_pll.reconfig_to_pll 20 | reconfig_from_pll : in std_logic_vector(63 downto 0) := (others => '0') -- reconfig_from_pll.reconfig_from_pll 21 | ); 22 | end entity master_reconfig; 23 | 24 | architecture rtl of master_reconfig is 25 | component altera_pll_reconfig_top is 26 | generic ( 27 | device_family : string := ""; 28 | ENABLE_MIF : boolean := false; 29 | MIF_FILE_NAME : string := ""; 30 | ENABLE_BYTEENABLE : boolean := false; 31 | BYTEENABLE_WIDTH : integer := 4; 32 | RECONFIG_ADDR_WIDTH : integer := 6; 33 | RECONFIG_DATA_WIDTH : integer := 32; 34 | reconf_width : integer := 64; 35 | WAIT_FOR_LOCK : boolean := true 36 | ); 37 | port ( 38 | mgmt_clk : in std_logic := 'X'; -- clk 39 | mgmt_reset : in std_logic := 'X'; -- reset 40 | mgmt_waitrequest : out std_logic; -- waitrequest 41 | mgmt_read : in std_logic := 'X'; -- read 42 | mgmt_write : in std_logic := 'X'; -- write 43 | mgmt_readdata : out std_logic_vector(31 downto 0); -- readdata 44 | mgmt_address : in std_logic_vector(5 downto 0) := (others => 'X'); -- address 45 | mgmt_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata 46 | reconfig_to_pll : out std_logic_vector(63 downto 0); -- reconfig_to_pll 47 | reconfig_from_pll : in std_logic_vector(63 downto 0) := (others => 'X'); -- reconfig_from_pll 48 | mgmt_byteenable : in std_logic_vector(3 downto 0) := (others => 'X') -- byteenable 49 | ); 50 | end component altera_pll_reconfig_top; 51 | 52 | begin 53 | 54 | master_reconfig_inst : component altera_pll_reconfig_top 55 | generic map ( 56 | device_family => "Cyclone V", 57 | ENABLE_MIF => false, 58 | MIF_FILE_NAME => "", 59 | ENABLE_BYTEENABLE => false, 60 | BYTEENABLE_WIDTH => 4, 61 | RECONFIG_ADDR_WIDTH => 6, 62 | RECONFIG_DATA_WIDTH => 32, 63 | reconf_width => 64, 64 | WAIT_FOR_LOCK => true 65 | ) 66 | port map ( 67 | mgmt_clk => mgmt_clk, -- mgmt_clk.clk 68 | mgmt_reset => mgmt_reset, -- mgmt_reset.reset 69 | mgmt_waitrequest => mgmt_waitrequest, -- mgmt_avalon_slave.waitrequest 70 | mgmt_read => mgmt_read, -- .read 71 | mgmt_write => mgmt_write, -- .write 72 | mgmt_readdata => mgmt_readdata, -- .readdata 73 | mgmt_address => mgmt_address, -- .address 74 | mgmt_writedata => mgmt_writedata, -- .writedata 75 | reconfig_to_pll => reconfig_to_pll, -- reconfig_to_pll.reconfig_to_pll 76 | reconfig_from_pll => reconfig_from_pll, -- reconfig_from_pll.reconfig_from_pll 77 | mgmt_byteenable => "0000" -- (terminated) 78 | ); 79 | 80 | end architecture rtl; -- of master_reconfig 81 | -------------------------------------------------------------------------------- /master_reconfig_sim/synopsys/vcsmx/synopsys_sim.setup: -------------------------------------------------------------------------------- 1 | 2 | WORK > DEFAULT 3 | DEFAULT: ./libraries/work/ 4 | work: ./libraries/work/ 5 | master_reconfig: ./libraries/master_reconfig/ 6 | altera_ver: ./libraries/altera_ver/ 7 | lpm_ver: ./libraries/lpm_ver/ 8 | sgate_ver: ./libraries/sgate_ver/ 9 | altera_mf_ver: ./libraries/altera_mf_ver/ 10 | altera_lnsim_ver: ./libraries/altera_lnsim_ver/ 11 | cyclonev_ver: ./libraries/cyclonev_ver/ 12 | cyclonev_hssi_ver: ./libraries/cyclonev_hssi_ver/ 13 | cyclonev_pcie_hip_ver: ./libraries/cyclonev_pcie_hip_ver/ 14 | altera: ./libraries/altera/ 15 | lpm: ./libraries/lpm/ 16 | sgate: ./libraries/sgate/ 17 | altera_mf: ./libraries/altera_mf/ 18 | altera_lnsim: ./libraries/altera_lnsim/ 19 | cyclonev: ./libraries/cyclonev/ 20 | LIBRARY_SCAN = TRUE 21 | -------------------------------------------------------------------------------- /nes.cdf: -------------------------------------------------------------------------------- 1 | /* Quartus Prime Version 17.0.0 Build 595 04/25/2017 SJ Lite Edition */ 2 | JedecChain; 3 | FileRevision(JESD32A); 4 | DefaultMfr(6E); 5 | 6 | P ActionCode(Cfg) 7 | Device PartName(5CGXFC5C6F27) Path("C:/intelFPGA/projects/fpgaNES/output_files/") File("nes.sof") MfrSpec(OpMask(1)); 8 | 9 | ChainEnd; 10 | 11 | AlteraBegin; 12 | ChainType(JTAG); 13 | AlteraEnd; 14 | -------------------------------------------------------------------------------- /nes.cof: -------------------------------------------------------------------------------- 1 | 2 | 3 | EPCQ256 4 | output_files/nes.pof 5 | 1 6 | 1 7 | 7 8 | 9 | Page_0 10 | 1 11 | 12 | C:/intelFPGA/projects/fpgaNES/output_files/nes.sof 13 | 14 | 15 | 10 16 | 0 17 | 0 18 | 0 19 | 1 20 | 21 | 1 22 | 23 | 24 | 2 25 | 2 26 | 0 27 | -1 28 | -1 29 | 1 30 | 31 | -------------------------------------------------------------------------------- /nes.qpf: -------------------------------------------------------------------------------- 1 | # -------------------------------------------------------------------------- # 2 | # 3 | # Copyright (C) 1991-2015 Altera Corporation. All rights reserved. 4 | # Your use of Altera Corporation's design tools, logic functions 5 | # and other software and tools, and its AMPP partner logic 6 | # functions, and any output files from any of the foregoing 7 | # (including device programming or simulation files), and any 8 | # associated documentation or information are expressly subject 9 | # to the terms and conditions of the Altera Program License 10 | # Subscription Agreement, the Altera Quartus Prime License Agreement, 11 | # the Altera MegaCore Function License Agreement, or other 12 | # applicable license agreement, including, without limitation, 13 | # that your use is for the sole purpose of programming logic 14 | # devices manufactured by Altera and sold by Altera or its 15 | # authorized distributors. Please refer to the applicable 16 | # agreement for further details. 17 | # 18 | # -------------------------------------------------------------------------- # 19 | # 20 | # Quartus Prime 21 | # Version 15.1.1 Build 189 12/02/2015 SJ Lite Edition 22 | # Date created = 18:38:44 February 12, 2016 23 | # 24 | # -------------------------------------------------------------------------- # 25 | 26 | QUARTUS_VERSION = "15.1" 27 | DATE = "18:38:44 February 12, 2016" 28 | 29 | # Revisions 30 | 31 | PROJECT_REVISION = "nes" 32 | -------------------------------------------------------------------------------- /nes.sdc: -------------------------------------------------------------------------------- 1 | #************************************************************** 2 | # This .sdc file is created by Terasic Tool. 3 | # Users are recommended to modify this file to match users logic. 4 | #************************************************************** 5 | 6 | #************************************************************** 7 | # Create Clock 8 | #************************************************************** 9 | create_clock -period 8.000ns [get_ports CLOCK_125_p] 10 | create_clock -period 20.000ns [get_ports CLOCK_50_B5B] 11 | create_clock -period 20.000ns [get_ports CLOCK_50_B6A] 12 | create_clock -period 20.000ns [get_ports CLOCK_50_B7A] 13 | create_clock -period 20.000ns [get_ports CLOCK_50_B8A] 14 | #derive_clocks -period 1MHz 15 | 16 | #************************************************************** 17 | # Create Generated Clock 18 | #************************************************************** 19 | derive_pll_clocks 20 | 21 | 22 | 23 | #************************************************************** 24 | # Set Clock Latency 25 | #************************************************************** 26 | 27 | 28 | 29 | #************************************************************** 30 | # Set Clock Uncertainty 31 | #************************************************************** 32 | derive_clock_uncertainty 33 | 34 | 35 | 36 | #************************************************************** 37 | # Set Input Delay 38 | #************************************************************** 39 | 40 | 41 | 42 | #************************************************************** 43 | # Set Output Delay 44 | #************************************************************** 45 | 46 | 47 | 48 | #************************************************************** 49 | # Set Clock Groups 50 | #************************************************************** 51 | 52 | 53 | 54 | #************************************************************** 55 | # Set False Path 56 | #************************************************************** 57 | set_false_path -from {audio|audio_pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk} -to {master|master_pll_inst|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk} 58 | 59 | 60 | 61 | #************************************************************** 62 | # Set Multicycle Path 63 | #************************************************************** 64 | 65 | 66 | 67 | #************************************************************** 68 | # Set Maximum Delay 69 | #************************************************************** 70 | 71 | 72 | 73 | #************************************************************** 74 | # Set Minimum Delay 75 | #************************************************************** 76 | 77 | 78 | 79 | #************************************************************** 80 | # Set Input Transition 81 | #************************************************************** 82 | 83 | 84 | 85 | #************************************************************** 86 | # Set Load 87 | #************************************************************** 88 | 89 | 90 | 91 | -------------------------------------------------------------------------------- /pixel_pll/pixel_pll_0002.qip: -------------------------------------------------------------------------------- 1 | set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to "*pixel_pll_0002*|altera_pll:altera_pll_i*|*" 2 | 3 | set_instance_assignment -name PLL_AUTO_RESET OFF -to "*pixel_pll_0002*|altera_pll:altera_pll_i*|*" 4 | set_instance_assignment -name PLL_BANDWIDTH_PRESET AUTO -to "*pixel_pll_0002*|altera_pll:altera_pll_i*|*" 5 | -------------------------------------------------------------------------------- /pixel_pll/pixel_pll_0002.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns/10ps 2 | module pixel_pll_0002( 3 | 4 | // interface 'refclk' 5 | input wire refclk, 6 | 7 | // interface 'reset' 8 | input wire rst, 9 | 10 | // interface 'outclk0' 11 | output wire outclk_0, 12 | 13 | // interface 'locked' 14 | output wire locked 15 | ); 16 | 17 | altera_pll #( 18 | .fractional_vco_multiplier("false"), 19 | .reference_clock_frequency("50.0 MHz"), 20 | .operation_mode("direct"), 21 | .number_of_clocks(1), 22 | .output_clock_frequency0("25.000000 MHz"), 23 | .phase_shift0("0 ps"), 24 | .duty_cycle0(50), 25 | .output_clock_frequency1("0 MHz"), 26 | .phase_shift1("0 ps"), 27 | .duty_cycle1(50), 28 | .output_clock_frequency2("0 MHz"), 29 | .phase_shift2("0 ps"), 30 | .duty_cycle2(50), 31 | .output_clock_frequency3("0 MHz"), 32 | .phase_shift3("0 ps"), 33 | .duty_cycle3(50), 34 | .output_clock_frequency4("0 MHz"), 35 | .phase_shift4("0 ps"), 36 | .duty_cycle4(50), 37 | .output_clock_frequency5("0 MHz"), 38 | .phase_shift5("0 ps"), 39 | .duty_cycle5(50), 40 | .output_clock_frequency6("0 MHz"), 41 | .phase_shift6("0 ps"), 42 | .duty_cycle6(50), 43 | .output_clock_frequency7("0 MHz"), 44 | .phase_shift7("0 ps"), 45 | .duty_cycle7(50), 46 | .output_clock_frequency8("0 MHz"), 47 | .phase_shift8("0 ps"), 48 | .duty_cycle8(50), 49 | .output_clock_frequency9("0 MHz"), 50 | .phase_shift9("0 ps"), 51 | .duty_cycle9(50), 52 | .output_clock_frequency10("0 MHz"), 53 | .phase_shift10("0 ps"), 54 | .duty_cycle10(50), 55 | .output_clock_frequency11("0 MHz"), 56 | .phase_shift11("0 ps"), 57 | .duty_cycle11(50), 58 | .output_clock_frequency12("0 MHz"), 59 | .phase_shift12("0 ps"), 60 | .duty_cycle12(50), 61 | .output_clock_frequency13("0 MHz"), 62 | .phase_shift13("0 ps"), 63 | .duty_cycle13(50), 64 | .output_clock_frequency14("0 MHz"), 65 | .phase_shift14("0 ps"), 66 | .duty_cycle14(50), 67 | .output_clock_frequency15("0 MHz"), 68 | .phase_shift15("0 ps"), 69 | .duty_cycle15(50), 70 | .output_clock_frequency16("0 MHz"), 71 | .phase_shift16("0 ps"), 72 | .duty_cycle16(50), 73 | .output_clock_frequency17("0 MHz"), 74 | .phase_shift17("0 ps"), 75 | .duty_cycle17(50), 76 | .pll_type("General"), 77 | .pll_subtype("General") 78 | ) altera_pll_i ( 79 | .rst (rst), 80 | .outclk ({outclk_0}), 81 | .locked (locked), 82 | .fboutclk ( ), 83 | .fbclk (1'b0), 84 | .refclk (refclk) 85 | ); 86 | endmodule 87 | 88 | -------------------------------------------------------------------------------- /pixel_pll_sim/cadence/cds.lib: -------------------------------------------------------------------------------- 1 | 2 | DEFINE std $CDS_ROOT/tools/inca/files/STD/ 3 | DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/ 4 | DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/ 5 | DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/ 6 | DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/ 7 | DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/ 8 | DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/ 9 | DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/ 10 | DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/ 11 | DEFINE work ./libraries/work/ 12 | DEFINE altera ./libraries/altera/ 13 | DEFINE lpm ./libraries/lpm/ 14 | DEFINE sgate ./libraries/sgate/ 15 | DEFINE altera_mf ./libraries/altera_mf/ 16 | DEFINE altera_lnsim ./libraries/altera_lnsim/ 17 | DEFINE cyclonev ./libraries/cyclonev/ 18 | -------------------------------------------------------------------------------- /pixel_pll_sim/cadence/hdl.var: -------------------------------------------------------------------------------- 1 | 2 | DEFINE WORK work 3 | -------------------------------------------------------------------------------- /pixel_pll_sim/cadence/ncsim_setup.sh: -------------------------------------------------------------------------------- 1 | 2 | # (C) 2001-2016 Altera Corporation. All rights reserved. 3 | # Your use of Altera Corporation's design tools, logic functions and 4 | # other software and tools, and its AMPP partner logic functions, and 5 | # any output files any of the foregoing (including device programming 6 | # or simulation files), and any associated documentation or information 7 | # are expressly subject to the terms and conditions of the Altera 8 | # Program License Subscription Agreement, Altera MegaCore Function 9 | # License Agreement, or other applicable license agreement, including, 10 | # without limitation, that your use is for the sole purpose of 11 | # programming logic devices manufactured by Altera and sold by Altera 12 | # or its authorized distributors. Please refer to the applicable 13 | # agreement for further details. 14 | 15 | # ACDS 15.1 189 win32 2016.02.12.19:38:24 16 | 17 | # ---------------------------------------- 18 | # ncsim - auto-generated simulation script 19 | 20 | # ---------------------------------------- 21 | # This script can be used to simulate the following IP: 22 | # pixel_pll 23 | # To create a top-level simulation script which compiles other 24 | # IP, and manages other system issues, copy the following template 25 | # and adapt it to your needs: 26 | # 27 | # # Start of template 28 | # # If the copied and modified template file is "ncsim.sh", run it as: 29 | # # ./ncsim.sh 30 | # # 31 | # # Do the file copy, dev_com and com steps 32 | # source ncsim_setup.sh \ 33 | # SKIP_ELAB=1 \ 34 | # SKIP_SIM=1 35 | # 36 | # # Compile the top level module 37 | # ncvlog -sv "$QSYS_SIMDIR/../top.sv" 38 | # 39 | # # Do the elaboration and sim steps 40 | # # Override the top-level name 41 | # # Override the user-defined sim options, so the simulation 42 | # # runs forever (until $finish()). 43 | # source ncsim_setup.sh \ 44 | # SKIP_FILE_COPY=1 \ 45 | # SKIP_DEV_COM=1 \ 46 | # SKIP_COM=1 \ 47 | # TOP_LEVEL_NAME=top \ 48 | # USER_DEFINED_SIM_OPTIONS="" 49 | # # End of template 50 | # ---------------------------------------- 51 | # If pixel_pll is one of several IP cores in your 52 | # Quartus project, you can generate a simulation script 53 | # suitable for inclusion in your top-level simulation 54 | # script by running the following command line: 55 | # 56 | # ip-setup-simulation --quartus-project= 57 | # 58 | # ip-setup-simulation will discover the Altera IP 59 | # within the Quartus project, and generate a unified 60 | # script which supports all the Altera IP within the design. 61 | # ---------------------------------------- 62 | # ACDS 15.1 189 win32 2016.02.12.19:38:24 63 | # ---------------------------------------- 64 | # initialize variables 65 | TOP_LEVEL_NAME="pixel_pll" 66 | QSYS_SIMDIR="./../" 67 | QUARTUS_INSTALL_DIR="C:/altera/15.1/quartus/" 68 | SKIP_FILE_COPY=0 69 | SKIP_DEV_COM=0 70 | SKIP_COM=0 71 | SKIP_ELAB=0 72 | SKIP_SIM=0 73 | USER_DEFINED_ELAB_OPTIONS="" 74 | USER_DEFINED_SIM_OPTIONS="-input \"@run 100; exit\"" 75 | 76 | # ---------------------------------------- 77 | # overwrite variables - DO NOT MODIFY! 78 | # This block evaluates each command line argument, typically used for 79 | # overwriting variables. An example usage: 80 | # sh _setup.sh SKIP_ELAB=1 SKIP_SIM=1 81 | for expression in "$@"; do 82 | eval $expression 83 | if [ $? -ne 0 ]; then 84 | echo "Error: This command line argument, \"$expression\", is/has an invalid expression." >&2 85 | exit $? 86 | fi 87 | done 88 | 89 | # ---------------------------------------- 90 | # initialize simulation properties - DO NOT MODIFY! 91 | ELAB_OPTIONS="" 92 | SIM_OPTIONS="" 93 | if [[ `ncsim -version` != *"ncsim(64)"* ]]; then 94 | : 95 | else 96 | : 97 | fi 98 | 99 | # ---------------------------------------- 100 | # create compilation libraries 101 | mkdir -p ./libraries/work/ 102 | mkdir -p ./libraries/altera/ 103 | mkdir -p ./libraries/lpm/ 104 | mkdir -p ./libraries/sgate/ 105 | mkdir -p ./libraries/altera_mf/ 106 | mkdir -p ./libraries/altera_lnsim/ 107 | mkdir -p ./libraries/cyclonev/ 108 | 109 | # ---------------------------------------- 110 | # copy RAM/ROM files to simulation directory 111 | 112 | # ---------------------------------------- 113 | # compile device library files 114 | if [ $SKIP_DEV_COM -eq 0 ]; then 115 | ncvhdl -v93 $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_syn_attributes.vhd" -work altera 116 | ncvhdl -v93 $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_standard_functions.vhd" -work altera 117 | ncvhdl -v93 $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/alt_dspbuilder_package.vhd" -work altera 118 | ncvhdl -v93 $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_europa_support_lib.vhd" -work altera 119 | ncvhdl -v93 $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives_components.vhd" -work altera 120 | ncvhdl -v93 $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives.vhd" -work altera 121 | ncvhdl -v93 $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/220pack.vhd" -work lpm 122 | ncvhdl -v93 $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/220model.vhd" -work lpm 123 | ncvhdl -v93 $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate_pack.vhd" -work sgate 124 | ncvhdl -v93 $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate.vhd" -work sgate 125 | ncvhdl -v93 $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf_components.vhd" -work altera_mf 126 | ncvhdl -v93 $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf.vhd" -work altera_mf 127 | ncvlog -sv $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim.sv" -work altera_lnsim 128 | ncvhdl -v93 $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim_components.vhd" -work altera_lnsim 129 | ncvlog $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/cadence/cyclonev_atoms_ncrypt.v" -work cyclonev 130 | ncvhdl -v93 $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_atoms.vhd" -work cyclonev 131 | ncvhdl -v93 $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_components.vhd" -work cyclonev 132 | fi 133 | 134 | # ---------------------------------------- 135 | # compile design files in correct order 136 | if [ $SKIP_COM -eq 0 ]; then 137 | ncvhdl -v93 $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/pixel_pll.vho" 138 | fi 139 | 140 | # ---------------------------------------- 141 | # elaborate top level design 142 | if [ $SKIP_ELAB -eq 0 ]; then 143 | ncelab -access +w+r+c -namemap_mixgen -relax $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS $TOP_LEVEL_NAME 144 | fi 145 | 146 | # ---------------------------------------- 147 | # simulate 148 | if [ $SKIP_SIM -eq 0 ]; then 149 | eval ncsim -licqueue $SIM_OPTIONS $USER_DEFINED_SIM_OPTIONS $TOP_LEVEL_NAME 150 | fi 151 | -------------------------------------------------------------------------------- /pixel_pll_sim/synopsys/vcsmx/synopsys_sim.setup: -------------------------------------------------------------------------------- 1 | 2 | WORK > DEFAULT 3 | DEFAULT: ./libraries/work/ 4 | work: ./libraries/work/ 5 | altera: ./libraries/altera/ 6 | lpm: ./libraries/lpm/ 7 | sgate: ./libraries/sgate/ 8 | altera_mf: ./libraries/altera_mf/ 9 | altera_lnsim: ./libraries/altera_lnsim/ 10 | cyclonev: ./libraries/cyclonev/ 11 | LIBRARY_SCAN = TRUE 12 | -------------------------------------------------------------------------------- /pixel_pll_sim/synopsys/vcsmx/vcsmx_setup.sh: -------------------------------------------------------------------------------- 1 | 2 | # (C) 2001-2016 Altera Corporation. All rights reserved. 3 | # Your use of Altera Corporation's design tools, logic functions and 4 | # other software and tools, and its AMPP partner logic functions, and 5 | # any output files any of the foregoing (including device programming 6 | # or simulation files), and any associated documentation or information 7 | # are expressly subject to the terms and conditions of the Altera 8 | # Program License Subscription Agreement, Altera MegaCore Function 9 | # License Agreement, or other applicable license agreement, including, 10 | # without limitation, that your use is for the sole purpose of 11 | # programming logic devices manufactured by Altera and sold by Altera 12 | # or its authorized distributors. Please refer to the applicable 13 | # agreement for further details. 14 | 15 | # ACDS 15.1 189 win32 2016.02.12.19:38:24 16 | 17 | # ---------------------------------------- 18 | # vcsmx - auto-generated simulation script 19 | 20 | # ---------------------------------------- 21 | # This script can be used to simulate the following IP: 22 | # pixel_pll 23 | # To create a top-level simulation script which compiles other 24 | # IP, and manages other system issues, copy the following template 25 | # and adapt it to your needs: 26 | # 27 | # # Start of template 28 | # # If the copied and modified template file is "vcsmx_sim.sh", run it as: 29 | # # ./vcsmx_sim.sh 30 | # # 31 | # # Do the file copy, dev_com and com steps 32 | # source vcsmx_setup.sh \ 33 | # SKIP_ELAB=1 \ 34 | # SKIP_SIM=1 35 | # 36 | # # Compile the top level module 37 | # vlogan +v2k +systemverilogext+.sv "$QSYS_SIMDIR/../top.sv" 38 | # 39 | # # Do the elaboration and sim steps 40 | # # Override the top-level name 41 | # # Override the user-defined sim options, so the simulation runs 42 | # # forever (until $finish()). 43 | # source vcsmx_setup.sh \ 44 | # SKIP_FILE_COPY=1 \ 45 | # SKIP_DEV_COM=1 \ 46 | # SKIP_COM=1 \ 47 | # TOP_LEVEL_NAME="'-top top'" \ 48 | # USER_DEFINED_SIM_OPTIONS="" 49 | # # End of template 50 | # ---------------------------------------- 51 | # If pixel_pll is one of several IP cores in your 52 | # Quartus project, you can generate a simulation script 53 | # suitable for inclusion in your top-level simulation 54 | # script by running the following command line: 55 | # 56 | # ip-setup-simulation --quartus-project= 57 | # 58 | # ip-setup-simulation will discover the Altera IP 59 | # within the Quartus project, and generate a unified 60 | # script which supports all the Altera IP within the design. 61 | # ---------------------------------------- 62 | # ACDS 15.1 189 win32 2016.02.12.19:38:24 63 | # ---------------------------------------- 64 | # initialize variables 65 | TOP_LEVEL_NAME="pixel_pll" 66 | QSYS_SIMDIR="./../../" 67 | QUARTUS_INSTALL_DIR="C:/altera/15.1/quartus/" 68 | SKIP_FILE_COPY=0 69 | SKIP_DEV_COM=0 70 | SKIP_COM=0 71 | SKIP_ELAB=0 72 | SKIP_SIM=0 73 | USER_DEFINED_ELAB_OPTIONS="" 74 | USER_DEFINED_SIM_OPTIONS="+vcs+finish+100" 75 | 76 | # ---------------------------------------- 77 | # overwrite variables - DO NOT MODIFY! 78 | # This block evaluates each command line argument, typically used for 79 | # overwriting variables. An example usage: 80 | # sh _setup.sh SKIP_ELAB=1 SKIP_SIM=1 81 | for expression in "$@"; do 82 | eval $expression 83 | if [ $? -ne 0 ]; then 84 | echo "Error: This command line argument, \"$expression\", is/has an invalid expression." >&2 85 | exit $? 86 | fi 87 | done 88 | 89 | # ---------------------------------------- 90 | # initialize simulation properties - DO NOT MODIFY! 91 | ELAB_OPTIONS="" 92 | SIM_OPTIONS="" 93 | if [[ `vcs -platform` != *"amd64"* ]]; then 94 | : 95 | else 96 | : 97 | fi 98 | 99 | # ---------------------------------------- 100 | # create compilation libraries 101 | mkdir -p ./libraries/work/ 102 | mkdir -p ./libraries/altera/ 103 | mkdir -p ./libraries/lpm/ 104 | mkdir -p ./libraries/sgate/ 105 | mkdir -p ./libraries/altera_mf/ 106 | mkdir -p ./libraries/altera_lnsim/ 107 | mkdir -p ./libraries/cyclonev/ 108 | 109 | # ---------------------------------------- 110 | # copy RAM/ROM files to simulation directory 111 | 112 | # ---------------------------------------- 113 | # compile device library files 114 | if [ $SKIP_DEV_COM -eq 0 ]; then 115 | vhdlan $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_syn_attributes.vhd" -work altera 116 | vhdlan $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_standard_functions.vhd" -work altera 117 | vhdlan $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/alt_dspbuilder_package.vhd" -work altera 118 | vhdlan $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_europa_support_lib.vhd" -work altera 119 | vhdlan $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives_components.vhd" -work altera 120 | vhdlan $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives.vhd" -work altera 121 | vhdlan $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/220pack.vhd" -work lpm 122 | vhdlan $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/220model.vhd" -work lpm 123 | vhdlan $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate_pack.vhd" -work sgate 124 | vhdlan $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate.vhd" -work sgate 125 | vhdlan $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf_components.vhd" -work altera_mf 126 | vhdlan $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf.vhd" -work altera_mf 127 | vlogan +v2k -sverilog $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim.sv" -work altera_lnsim 128 | vhdlan $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim_components.vhd" -work altera_lnsim 129 | vlogan +v2k $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/synopsys/cyclonev_atoms_ncrypt.v" -work cyclonev 130 | vhdlan $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_atoms.vhd" -work cyclonev 131 | vhdlan $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_components.vhd" -work cyclonev 132 | fi 133 | 134 | # ---------------------------------------- 135 | # compile design files in correct order 136 | if [ $SKIP_COM -eq 0 ]; then 137 | vhdlan -xlrm $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/pixel_pll.vho" 138 | fi 139 | 140 | # ---------------------------------------- 141 | # elaborate top level design 142 | if [ $SKIP_ELAB -eq 0 ]; then 143 | vcs -lca -t ps $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS $TOP_LEVEL_NAME 144 | fi 145 | 146 | # ---------------------------------------- 147 | # simulate 148 | if [ $SKIP_SIM -eq 0 ]; then 149 | ./simv $SIM_OPTIONS $USER_DEFINED_SIM_OPTIONS 150 | fi 151 | -------------------------------------------------------------------------------- /progmem.cmp: -------------------------------------------------------------------------------- 1 | --Copyright (C) 2018 Intel Corporation. All rights reserved. 2 | --Your use of Intel Corporation's design tools, logic functions 3 | --and other software and tools, and its AMPP partner logic 4 | --functions, and any output files from any of the foregoing 5 | --(including device programming or simulation files), and any 6 | --associated documentation or information are expressly subject 7 | --to the terms and conditions of the Intel Program License 8 | --Subscription Agreement, the Intel Quartus Prime License Agreement, 9 | --the Intel FPGA IP License Agreement, or other applicable license 10 | --agreement, including, without limitation, that your use is for 11 | --the sole purpose of programming logic devices manufactured by 12 | --Intel and sold by Intel or its authorized distributors. Please 13 | --refer to the applicable agreement for further details. 14 | 15 | 16 | component progmem 17 | PORT 18 | ( 19 | address : IN STD_LOGIC_VECTOR (14 DOWNTO 0); 20 | clken : IN STD_LOGIC := '1'; 21 | clock : IN STD_LOGIC := '1'; 22 | data : IN STD_LOGIC_VECTOR (7 DOWNTO 0); 23 | wren : IN STD_LOGIC ; 24 | q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) 25 | ); 26 | end component; 27 | -------------------------------------------------------------------------------- /progmem.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "RAM: 1-PORT" 2 | set_global_assignment -name IP_TOOL_VERSION "18.0" 3 | set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone V}" 4 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "progmem.vhd"] 5 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "progmem.cmp"] 6 | -------------------------------------------------------------------------------- /progmem.vhd: -------------------------------------------------------------------------------- 1 | -- megafunction wizard: %RAM: 1-PORT% 2 | -- GENERATION: STANDARD 3 | -- VERSION: WM1.0 4 | -- MODULE: altsyncram 5 | 6 | -- ============================================================ 7 | -- File Name: progmem.vhd 8 | -- Megafunction Name(s): 9 | -- altsyncram 10 | -- 11 | -- Simulation Library Files(s): 12 | -- altera_mf 13 | -- ============================================================ 14 | -- ************************************************************ 15 | -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! 16 | -- 17 | -- 18.0.0 Build 614 04/24/2018 SJ Lite Edition 18 | -- ************************************************************ 19 | 20 | 21 | --Copyright (C) 2018 Intel Corporation. All rights reserved. 22 | --Your use of Intel Corporation's design tools, logic functions 23 | --and other software and tools, and its AMPP partner logic 24 | --functions, and any output files from any of the foregoing 25 | --(including device programming or simulation files), and any 26 | --associated documentation or information are expressly subject 27 | --to the terms and conditions of the Intel Program License 28 | --Subscription Agreement, the Intel Quartus Prime License Agreement, 29 | --the Intel FPGA IP License Agreement, or other applicable license 30 | --agreement, including, without limitation, that your use is for 31 | --the sole purpose of programming logic devices manufactured by 32 | --Intel and sold by Intel or its authorized distributors. Please 33 | --refer to the applicable agreement for further details. 34 | 35 | 36 | LIBRARY ieee; 37 | USE ieee.std_logic_1164.all; 38 | 39 | LIBRARY altera_mf; 40 | USE altera_mf.altera_mf_components.all; 41 | 42 | ENTITY progmem IS 43 | PORT 44 | ( 45 | address : IN STD_LOGIC_VECTOR (14 DOWNTO 0); 46 | clken : IN STD_LOGIC := '1'; 47 | clock : IN STD_LOGIC := '1'; 48 | data : IN STD_LOGIC_VECTOR (7 DOWNTO 0); 49 | wren : IN STD_LOGIC ; 50 | q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) 51 | ); 52 | END progmem; 53 | 54 | 55 | ARCHITECTURE SYN OF progmem IS 56 | 57 | SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0); 58 | 59 | BEGIN 60 | q <= sub_wire0(7 DOWNTO 0); 61 | 62 | altsyncram_component : altsyncram 63 | GENERIC MAP ( 64 | clock_enable_input_a => "NORMAL", 65 | clock_enable_output_a => "BYPASS", 66 | init_file => "test_progmem.hex", 67 | intended_device_family => "Cyclone V", 68 | lpm_hint => "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=PROG", 69 | lpm_type => "altsyncram", 70 | numwords_a => 32768, 71 | operation_mode => "SINGLE_PORT", 72 | outdata_aclr_a => "NONE", 73 | outdata_reg_a => "UNREGISTERED", 74 | power_up_uninitialized => "FALSE", 75 | read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ", 76 | widthad_a => 15, 77 | width_a => 8, 78 | width_byteena_a => 1 79 | ) 80 | PORT MAP ( 81 | address_a => address, 82 | clock0 => clock, 83 | clocken0 => clken, 84 | data_a => data, 85 | wren_a => wren, 86 | q_a => sub_wire0 87 | ); 88 | 89 | 90 | 91 | END SYN; 92 | 93 | -- ============================================================ 94 | -- CNX file retrieval info 95 | -- ============================================================ 96 | -- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" 97 | -- Retrieval info: PRIVATE: AclrAddr NUMERIC "0" 98 | -- Retrieval info: PRIVATE: AclrByte NUMERIC "0" 99 | -- Retrieval info: PRIVATE: AclrData NUMERIC "0" 100 | -- Retrieval info: PRIVATE: AclrOutput NUMERIC "0" 101 | -- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0" 102 | -- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" 103 | -- Retrieval info: PRIVATE: BlankMemory NUMERIC "0" 104 | -- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "1" 105 | -- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" 106 | -- Retrieval info: PRIVATE: Clken NUMERIC "1" 107 | -- Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1" 108 | -- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" 109 | -- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" 110 | -- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" 111 | -- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V" 112 | -- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "1" 113 | -- Retrieval info: PRIVATE: JTAG_ID STRING "PROG" 114 | -- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" 115 | -- Retrieval info: PRIVATE: MIFfilename STRING "test_progmem.hex" 116 | -- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "32768" 117 | -- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" 118 | -- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3" 119 | -- Retrieval info: PRIVATE: RegAddr NUMERIC "1" 120 | -- Retrieval info: PRIVATE: RegData NUMERIC "1" 121 | -- Retrieval info: PRIVATE: RegOutput NUMERIC "0" 122 | -- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" 123 | -- Retrieval info: PRIVATE: SingleClock NUMERIC "1" 124 | -- Retrieval info: PRIVATE: UseDQRAM NUMERIC "1" 125 | -- Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0" 126 | -- Retrieval info: PRIVATE: WidthAddr NUMERIC "15" 127 | -- Retrieval info: PRIVATE: WidthData NUMERIC "8" 128 | -- Retrieval info: PRIVATE: rden NUMERIC "0" 129 | -- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all 130 | -- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "NORMAL" 131 | -- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" 132 | -- Retrieval info: CONSTANT: INIT_FILE STRING "test_progmem.hex" 133 | -- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V" 134 | -- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=PROG" 135 | -- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" 136 | -- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "32768" 137 | -- Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT" 138 | -- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" 139 | -- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED" 140 | -- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE" 141 | -- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ" 142 | -- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "15" 143 | -- Retrieval info: CONSTANT: WIDTH_A NUMERIC "8" 144 | -- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" 145 | -- Retrieval info: USED_PORT: address 0 0 15 0 INPUT NODEFVAL "address[14..0]" 146 | -- Retrieval info: USED_PORT: clken 0 0 0 0 INPUT VCC "clken" 147 | -- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" 148 | -- Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]" 149 | -- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]" 150 | -- Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren" 151 | -- Retrieval info: CONNECT: @address_a 0 0 15 0 address 0 0 15 0 152 | -- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 153 | -- Retrieval info: CONNECT: @clocken0 0 0 0 0 clken 0 0 0 0 154 | -- Retrieval info: CONNECT: @data_a 0 0 8 0 data 0 0 8 0 155 | -- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0 156 | -- Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0 157 | -- Retrieval info: GEN_FILE: TYPE_NORMAL progmem.vhd TRUE 158 | -- Retrieval info: GEN_FILE: TYPE_NORMAL progmem.inc FALSE 159 | -- Retrieval info: GEN_FILE: TYPE_NORMAL progmem.cmp TRUE 160 | -- Retrieval info: GEN_FILE: TYPE_NORMAL progmem.bsf FALSE 161 | -- Retrieval info: GEN_FILE: TYPE_NORMAL progmem_inst.vhd FALSE 162 | -- Retrieval info: LIB_FILE: altera_mf 163 | -------------------------------------------------------------------------------- /soamem.cmp: -------------------------------------------------------------------------------- 1 | --Copyright (C) 2018 Intel Corporation. All rights reserved. 2 | --Your use of Intel Corporation's design tools, logic functions 3 | --and other software and tools, and its AMPP partner logic 4 | --functions, and any output files from any of the foregoing 5 | --(including device programming or simulation files), and any 6 | --associated documentation or information are expressly subject 7 | --to the terms and conditions of the Intel Program License 8 | --Subscription Agreement, the Intel Quartus Prime License Agreement, 9 | --the Intel FPGA IP License Agreement, or other applicable license 10 | --agreement, including, without limitation, that your use is for 11 | --the sole purpose of programming logic devices manufactured by 12 | --Intel and sold by Intel or its authorized distributors. Please 13 | --refer to the applicable agreement for further details. 14 | 15 | 16 | component soamem 17 | PORT 18 | ( 19 | address : IN STD_LOGIC_VECTOR (4 DOWNTO 0); 20 | clken : IN STD_LOGIC := '1'; 21 | clock : IN STD_LOGIC := '1'; 22 | data : IN STD_LOGIC_VECTOR (7 DOWNTO 0); 23 | wren : IN STD_LOGIC ; 24 | q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) 25 | ); 26 | end component; 27 | -------------------------------------------------------------------------------- /soamem.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "RAM: 1-PORT" 2 | set_global_assignment -name IP_TOOL_VERSION "18.0" 3 | set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone V}" 4 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "soamem.vhd"] 5 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "soamem.cmp"] 6 | -------------------------------------------------------------------------------- /soamem.vhd: -------------------------------------------------------------------------------- 1 | -- megafunction wizard: %RAM: 1-PORT% 2 | -- GENERATION: STANDARD 3 | -- VERSION: WM1.0 4 | -- MODULE: altsyncram 5 | 6 | -- ============================================================ 7 | -- File Name: soamem.vhd 8 | -- Megafunction Name(s): 9 | -- altsyncram 10 | -- 11 | -- Simulation Library Files(s): 12 | -- altera_mf 13 | -- ============================================================ 14 | -- ************************************************************ 15 | -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! 16 | -- 17 | -- 18.0.0 Build 614 04/24/2018 SJ Lite Edition 18 | -- ************************************************************ 19 | 20 | 21 | --Copyright (C) 2018 Intel Corporation. All rights reserved. 22 | --Your use of Intel Corporation's design tools, logic functions 23 | --and other software and tools, and its AMPP partner logic 24 | --functions, and any output files from any of the foregoing 25 | --(including device programming or simulation files), and any 26 | --associated documentation or information are expressly subject 27 | --to the terms and conditions of the Intel Program License 28 | --Subscription Agreement, the Intel Quartus Prime License Agreement, 29 | --the Intel FPGA IP License Agreement, or other applicable license 30 | --agreement, including, without limitation, that your use is for 31 | --the sole purpose of programming logic devices manufactured by 32 | --Intel and sold by Intel or its authorized distributors. Please 33 | --refer to the applicable agreement for further details. 34 | 35 | 36 | LIBRARY ieee; 37 | USE ieee.std_logic_1164.all; 38 | 39 | LIBRARY altera_mf; 40 | USE altera_mf.altera_mf_components.all; 41 | 42 | ENTITY soamem IS 43 | PORT 44 | ( 45 | address : IN STD_LOGIC_VECTOR (4 DOWNTO 0); 46 | clken : IN STD_LOGIC := '1'; 47 | clock : IN STD_LOGIC := '1'; 48 | data : IN STD_LOGIC_VECTOR (7 DOWNTO 0); 49 | wren : IN STD_LOGIC ; 50 | q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) 51 | ); 52 | END soamem; 53 | 54 | 55 | ARCHITECTURE SYN OF soamem IS 56 | 57 | SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0); 58 | 59 | BEGIN 60 | q <= sub_wire0(7 DOWNTO 0); 61 | 62 | altsyncram_component : altsyncram 63 | GENERIC MAP ( 64 | clock_enable_input_a => "NORMAL", 65 | clock_enable_output_a => "BYPASS", 66 | intended_device_family => "Cyclone V", 67 | lpm_hint => "ENABLE_RUNTIME_MOD=NO", 68 | lpm_type => "altsyncram", 69 | numwords_a => 32, 70 | operation_mode => "SINGLE_PORT", 71 | outdata_aclr_a => "NONE", 72 | outdata_reg_a => "UNREGISTERED", 73 | power_up_uninitialized => "FALSE", 74 | read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ", 75 | widthad_a => 5, 76 | width_a => 8, 77 | width_byteena_a => 1 78 | ) 79 | PORT MAP ( 80 | address_a => address, 81 | clock0 => clock, 82 | clocken0 => clken, 83 | data_a => data, 84 | wren_a => wren, 85 | q_a => sub_wire0 86 | ); 87 | 88 | 89 | 90 | END SYN; 91 | 92 | -- ============================================================ 93 | -- CNX file retrieval info 94 | -- ============================================================ 95 | -- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" 96 | -- Retrieval info: PRIVATE: AclrAddr NUMERIC "0" 97 | -- Retrieval info: PRIVATE: AclrByte NUMERIC "0" 98 | -- Retrieval info: PRIVATE: AclrData NUMERIC "0" 99 | -- Retrieval info: PRIVATE: AclrOutput NUMERIC "0" 100 | -- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0" 101 | -- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" 102 | -- Retrieval info: PRIVATE: BlankMemory NUMERIC "1" 103 | -- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "1" 104 | -- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" 105 | -- Retrieval info: PRIVATE: Clken NUMERIC "1" 106 | -- Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1" 107 | -- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" 108 | -- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" 109 | -- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" 110 | -- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V" 111 | -- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" 112 | -- Retrieval info: PRIVATE: JTAG_ID STRING "NONE" 113 | -- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" 114 | -- Retrieval info: PRIVATE: MIFfilename STRING "" 115 | -- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "32" 116 | -- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" 117 | -- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3" 118 | -- Retrieval info: PRIVATE: RegAddr NUMERIC "1" 119 | -- Retrieval info: PRIVATE: RegData NUMERIC "1" 120 | -- Retrieval info: PRIVATE: RegOutput NUMERIC "0" 121 | -- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" 122 | -- Retrieval info: PRIVATE: SingleClock NUMERIC "1" 123 | -- Retrieval info: PRIVATE: UseDQRAM NUMERIC "1" 124 | -- Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0" 125 | -- Retrieval info: PRIVATE: WidthAddr NUMERIC "5" 126 | -- Retrieval info: PRIVATE: WidthData NUMERIC "8" 127 | -- Retrieval info: PRIVATE: rden NUMERIC "0" 128 | -- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all 129 | -- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "NORMAL" 130 | -- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" 131 | -- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V" 132 | -- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO" 133 | -- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" 134 | -- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "32" 135 | -- Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT" 136 | -- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" 137 | -- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED" 138 | -- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE" 139 | -- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ" 140 | -- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "5" 141 | -- Retrieval info: CONSTANT: WIDTH_A NUMERIC "8" 142 | -- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" 143 | -- Retrieval info: USED_PORT: address 0 0 5 0 INPUT NODEFVAL "address[4..0]" 144 | -- Retrieval info: USED_PORT: clken 0 0 0 0 INPUT VCC "clken" 145 | -- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" 146 | -- Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]" 147 | -- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]" 148 | -- Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren" 149 | -- Retrieval info: CONNECT: @address_a 0 0 5 0 address 0 0 5 0 150 | -- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 151 | -- Retrieval info: CONNECT: @clocken0 0 0 0 0 clken 0 0 0 0 152 | -- Retrieval info: CONNECT: @data_a 0 0 8 0 data 0 0 8 0 153 | -- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0 154 | -- Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0 155 | -- Retrieval info: GEN_FILE: TYPE_NORMAL soamem.vhd TRUE 156 | -- Retrieval info: GEN_FILE: TYPE_NORMAL soamem.inc FALSE 157 | -- Retrieval info: GEN_FILE: TYPE_NORMAL soamem.cmp TRUE 158 | -- Retrieval info: GEN_FILE: TYPE_NORMAL soamem.bsf FALSE 159 | -- Retrieval info: GEN_FILE: TYPE_NORMAL soamem_inst.vhd FALSE 160 | -- Retrieval info: LIB_FILE: altera_mf 161 | -------------------------------------------------------------------------------- /spritemem.cmp: -------------------------------------------------------------------------------- 1 | --Copyright (C) 2018 Intel Corporation. All rights reserved. 2 | --Your use of Intel Corporation's design tools, logic functions 3 | --and other software and tools, and its AMPP partner logic 4 | --functions, and any output files from any of the foregoing 5 | --(including device programming or simulation files), and any 6 | --associated documentation or information are expressly subject 7 | --to the terms and conditions of the Intel Program License 8 | --Subscription Agreement, the Intel Quartus Prime License Agreement, 9 | --the Intel FPGA IP License Agreement, or other applicable license 10 | --agreement, including, without limitation, that your use is for 11 | --the sole purpose of programming logic devices manufactured by 12 | --Intel and sold by Intel or its authorized distributors. Please 13 | --refer to the applicable agreement for further details. 14 | 15 | 16 | component spritemem 17 | PORT 18 | ( 19 | address : IN STD_LOGIC_VECTOR (7 DOWNTO 0); 20 | clken : IN STD_LOGIC := '1'; 21 | clock : IN STD_LOGIC := '1'; 22 | data : IN STD_LOGIC_VECTOR (7 DOWNTO 0); 23 | wren : IN STD_LOGIC ; 24 | q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) 25 | ); 26 | end component; 27 | -------------------------------------------------------------------------------- /spritemem.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "RAM: 1-PORT" 2 | set_global_assignment -name IP_TOOL_VERSION "18.0" 3 | set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone V}" 4 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "spritemem.vhd"] 5 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "spritemem.cmp"] 6 | -------------------------------------------------------------------------------- /spritemem.vhd: -------------------------------------------------------------------------------- 1 | -- megafunction wizard: %RAM: 1-PORT% 2 | -- GENERATION: STANDARD 3 | -- VERSION: WM1.0 4 | -- MODULE: altsyncram 5 | 6 | -- ============================================================ 7 | -- File Name: spritemem.vhd 8 | -- Megafunction Name(s): 9 | -- altsyncram 10 | -- 11 | -- Simulation Library Files(s): 12 | -- altera_mf 13 | -- ============================================================ 14 | -- ************************************************************ 15 | -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! 16 | -- 17 | -- 18.0.0 Build 614 04/24/2018 SJ Lite Edition 18 | -- ************************************************************ 19 | 20 | 21 | --Copyright (C) 2018 Intel Corporation. All rights reserved. 22 | --Your use of Intel Corporation's design tools, logic functions 23 | --and other software and tools, and its AMPP partner logic 24 | --functions, and any output files from any of the foregoing 25 | --(including device programming or simulation files), and any 26 | --associated documentation or information are expressly subject 27 | --to the terms and conditions of the Intel Program License 28 | --Subscription Agreement, the Intel Quartus Prime License Agreement, 29 | --the Intel FPGA IP License Agreement, or other applicable license 30 | --agreement, including, without limitation, that your use is for 31 | --the sole purpose of programming logic devices manufactured by 32 | --Intel and sold by Intel or its authorized distributors. Please 33 | --refer to the applicable agreement for further details. 34 | 35 | 36 | LIBRARY ieee; 37 | USE ieee.std_logic_1164.all; 38 | 39 | LIBRARY altera_mf; 40 | USE altera_mf.altera_mf_components.all; 41 | 42 | ENTITY spritemem IS 43 | PORT 44 | ( 45 | address : IN STD_LOGIC_VECTOR (7 DOWNTO 0); 46 | clken : IN STD_LOGIC := '1'; 47 | clock : IN STD_LOGIC := '1'; 48 | data : IN STD_LOGIC_VECTOR (7 DOWNTO 0); 49 | wren : IN STD_LOGIC ; 50 | q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) 51 | ); 52 | END spritemem; 53 | 54 | 55 | ARCHITECTURE SYN OF spritemem IS 56 | 57 | SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0); 58 | 59 | BEGIN 60 | q <= sub_wire0(7 DOWNTO 0); 61 | 62 | altsyncram_component : altsyncram 63 | GENERIC MAP ( 64 | clock_enable_input_a => "NORMAL", 65 | clock_enable_output_a => "BYPASS", 66 | intended_device_family => "Cyclone V", 67 | lpm_hint => "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=OAM", 68 | lpm_type => "altsyncram", 69 | numwords_a => 256, 70 | operation_mode => "SINGLE_PORT", 71 | outdata_aclr_a => "NONE", 72 | outdata_reg_a => "UNREGISTERED", 73 | power_up_uninitialized => "FALSE", 74 | read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ", 75 | widthad_a => 8, 76 | width_a => 8, 77 | width_byteena_a => 1 78 | ) 79 | PORT MAP ( 80 | address_a => address, 81 | clock0 => clock, 82 | clocken0 => clken, 83 | data_a => data, 84 | wren_a => wren, 85 | q_a => sub_wire0 86 | ); 87 | 88 | 89 | 90 | END SYN; 91 | 92 | -- ============================================================ 93 | -- CNX file retrieval info 94 | -- ============================================================ 95 | -- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" 96 | -- Retrieval info: PRIVATE: AclrAddr NUMERIC "0" 97 | -- Retrieval info: PRIVATE: AclrByte NUMERIC "0" 98 | -- Retrieval info: PRIVATE: AclrData NUMERIC "0" 99 | -- Retrieval info: PRIVATE: AclrOutput NUMERIC "0" 100 | -- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0" 101 | -- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" 102 | -- Retrieval info: PRIVATE: BlankMemory NUMERIC "1" 103 | -- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "1" 104 | -- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" 105 | -- Retrieval info: PRIVATE: Clken NUMERIC "1" 106 | -- Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1" 107 | -- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" 108 | -- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" 109 | -- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" 110 | -- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V" 111 | -- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "1" 112 | -- Retrieval info: PRIVATE: JTAG_ID STRING "OAM" 113 | -- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" 114 | -- Retrieval info: PRIVATE: MIFfilename STRING "" 115 | -- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "256" 116 | -- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" 117 | -- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3" 118 | -- Retrieval info: PRIVATE: RegAddr NUMERIC "1" 119 | -- Retrieval info: PRIVATE: RegData NUMERIC "1" 120 | -- Retrieval info: PRIVATE: RegOutput NUMERIC "0" 121 | -- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" 122 | -- Retrieval info: PRIVATE: SingleClock NUMERIC "1" 123 | -- Retrieval info: PRIVATE: UseDQRAM NUMERIC "1" 124 | -- Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0" 125 | -- Retrieval info: PRIVATE: WidthAddr NUMERIC "8" 126 | -- Retrieval info: PRIVATE: WidthData NUMERIC "8" 127 | -- Retrieval info: PRIVATE: rden NUMERIC "0" 128 | -- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all 129 | -- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "NORMAL" 130 | -- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" 131 | -- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V" 132 | -- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=OAM" 133 | -- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" 134 | -- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256" 135 | -- Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT" 136 | -- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" 137 | -- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED" 138 | -- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE" 139 | -- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ" 140 | -- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8" 141 | -- Retrieval info: CONSTANT: WIDTH_A NUMERIC "8" 142 | -- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" 143 | -- Retrieval info: USED_PORT: address 0 0 8 0 INPUT NODEFVAL "address[7..0]" 144 | -- Retrieval info: USED_PORT: clken 0 0 0 0 INPUT VCC "clken" 145 | -- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" 146 | -- Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]" 147 | -- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]" 148 | -- Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren" 149 | -- Retrieval info: CONNECT: @address_a 0 0 8 0 address 0 0 8 0 150 | -- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 151 | -- Retrieval info: CONNECT: @clocken0 0 0 0 0 clken 0 0 0 0 152 | -- Retrieval info: CONNECT: @data_a 0 0 8 0 data 0 0 8 0 153 | -- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0 154 | -- Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0 155 | -- Retrieval info: GEN_FILE: TYPE_NORMAL spritemem.vhd TRUE 156 | -- Retrieval info: GEN_FILE: TYPE_NORMAL spritemem.inc FALSE 157 | -- Retrieval info: GEN_FILE: TYPE_NORMAL spritemem.cmp TRUE 158 | -- Retrieval info: GEN_FILE: TYPE_NORMAL spritemem.bsf FALSE 159 | -- Retrieval info: GEN_FILE: TYPE_NORMAL spritemem_inst.vhd FALSE 160 | -- Retrieval info: LIB_FILE: altera_mf 161 | -------------------------------------------------------------------------------- /vga_pll.bsf: -------------------------------------------------------------------------------- 1 | /* 2 | WARNING: Do NOT edit the input and output ports in this file in a text 3 | editor if you plan to continue editing the block that represents it in 4 | the Block Editor! File corruption is VERY likely to occur. 5 | */ 6 | /* 7 | Copyright (C) 2018 Intel Corporation. All rights reserved. 8 | Your use of Intel Corporation's design tools, logic functions 9 | and other software and tools, and its AMPP partner logic 10 | functions, and any output files from any of the foregoing 11 | (including device programming or simulation files), and any 12 | associated documentation or information are expressly subject 13 | to the terms and conditions of the Intel Program License 14 | Subscription Agreement, the Intel Quartus Prime License Agreement, 15 | the Intel FPGA IP License Agreement, or other applicable license 16 | agreement, including, without limitation, that your use is for 17 | the sole purpose of programming logic devices manufactured by 18 | Intel and sold by Intel or its authorized distributors. Please 19 | refer to the applicable agreement for further details. 20 | */ 21 | (header "symbol" (version "1.1")) 22 | (symbol 23 | (rect 0 0 160 144) 24 | (text "vga_pll" (rect 60 -1 88 11)(font "Arial" (font_size 10))) 25 | (text "inst" (rect 8 128 20 140)(font "Arial" )) 26 | (port 27 | (pt 0 72) 28 | (input) 29 | (text "refclk" (rect 0 0 22 12)(font "Arial" (font_size 8))) 30 | (text "refclk" (rect 4 61 40 72)(font "Arial" (font_size 8))) 31 | (line (pt 0 72)(pt 48 72)(line_width 1)) 32 | ) 33 | (port 34 | (pt 0 112) 35 | (input) 36 | (text "rst" (rect 0 0 10 12)(font "Arial" (font_size 8))) 37 | (text "rst" (rect 4 101 22 112)(font "Arial" (font_size 8))) 38 | (line (pt 0 112)(pt 48 112)(line_width 1)) 39 | ) 40 | (port 41 | (pt 160 72) 42 | (output) 43 | (text "outclk_0" (rect 0 0 33 12)(font "Arial" (font_size 8))) 44 | (text "outclk_0" (rect 117 61 165 72)(font "Arial" (font_size 8))) 45 | (line (pt 160 72)(pt 112 72)(line_width 1)) 46 | ) 47 | (port 48 | (pt 160 112) 49 | (output) 50 | (text "locked" (rect 0 0 24 12)(font "Arial" (font_size 8))) 51 | (text "locked" (rect 127 101 163 112)(font "Arial" (font_size 8))) 52 | (line (pt 160 112)(pt 112 112)(line_width 1)) 53 | ) 54 | (drawing 55 | (text "refclk" (rect 16 43 68 99)(font "Arial" (color 128 0 0)(font_size 9))) 56 | (text "clk" (rect 53 67 124 144)(font "Arial" (color 0 0 0))) 57 | (text "reset" (rect 19 83 68 179)(font "Arial" (color 128 0 0)(font_size 9))) 58 | (text "reset" (rect 53 107 136 224)(font "Arial" (color 0 0 0))) 59 | (text "outclk0" (rect 113 43 268 99)(font "Arial" (color 128 0 0)(font_size 9))) 60 | (text "clk" (rect 97 67 212 144)(font "Arial" (color 0 0 0))) 61 | (text "locked" (rect 113 83 262 179)(font "Arial" (color 128 0 0)(font_size 9))) 62 | (text "export" (rect 82 107 200 224)(font "Arial" (color 0 0 0))) 63 | (text " altera_pll " (rect 118 128 308 266)(font "Arial" )) 64 | (line (pt 48 32)(pt 112 32)(line_width 1)) 65 | (line (pt 112 32)(pt 112 128)(line_width 1)) 66 | (line (pt 48 128)(pt 112 128)(line_width 1)) 67 | (line (pt 48 32)(pt 48 128)(line_width 1)) 68 | (line (pt 49 52)(pt 49 76)(line_width 1)) 69 | (line (pt 50 52)(pt 50 76)(line_width 1)) 70 | (line (pt 49 92)(pt 49 116)(line_width 1)) 71 | (line (pt 50 92)(pt 50 116)(line_width 1)) 72 | (line (pt 111 52)(pt 111 76)(line_width 1)) 73 | (line (pt 110 52)(pt 110 76)(line_width 1)) 74 | (line (pt 111 92)(pt 111 116)(line_width 1)) 75 | (line (pt 110 92)(pt 110 116)(line_width 1)) 76 | (line (pt 0 0)(pt 160 0)(line_width 1)) 77 | (line (pt 160 0)(pt 160 144)(line_width 1)) 78 | (line (pt 0 144)(pt 160 144)(line_width 1)) 79 | (line (pt 0 0)(pt 0 144)(line_width 1)) 80 | ) 81 | ) 82 | -------------------------------------------------------------------------------- /vga_pll.cmp: -------------------------------------------------------------------------------- 1 | component vga_pll is 2 | port ( 3 | refclk : in std_logic := 'X'; -- clk 4 | rst : in std_logic := 'X'; -- reset 5 | outclk_0 : out std_logic; -- clk 6 | locked : out std_logic -- export 7 | ); 8 | end component vga_pll; 9 | 10 | -------------------------------------------------------------------------------- /vga_pll.ppf: -------------------------------------------------------------------------------- 1 | 2 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | -------------------------------------------------------------------------------- /vga_pll.sip: -------------------------------------------------------------------------------- 1 | set_global_assignment -entity "vga_pll" -library "lib_vga_pll" -name IP_TOOL_NAME "altera_pll" 2 | set_global_assignment -entity "vga_pll" -library "lib_vga_pll" -name IP_TOOL_VERSION "18.0" 3 | set_global_assignment -entity "vga_pll" -library "lib_vga_pll" -name IP_TOOL_ENV "mwpim" 4 | set_global_assignment -library "lib_vga_pll" -name SPD_FILE [file join $::quartus(sip_path) "vga_pll.spd"] 5 | 6 | set_global_assignment -library "lib_vga_pll" -name MISC_FILE [file join $::quartus(sip_path) "vga_pll_sim/vga_pll.vho"] 7 | -------------------------------------------------------------------------------- /vga_pll.spd: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | -------------------------------------------------------------------------------- /vga_pll/vga_pll_0002.qip: -------------------------------------------------------------------------------- 1 | set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to "*vga_pll_0002*|altera_pll:altera_pll_i*|*" 2 | set_instance_assignment -name PLL_CHANNEL_SPACING "0.0 KHz" -to "*vga_pll_0002*|altera_pll:altera_pll_i*|*" 3 | set_instance_assignment -name PLL_AUTO_RESET OFF -to "*vga_pll_0002*|altera_pll:altera_pll_i*|*" 4 | set_instance_assignment -name PLL_BANDWIDTH_PRESET AUTO -to "*vga_pll_0002*|altera_pll:altera_pll_i*|*" 5 | -------------------------------------------------------------------------------- /vga_pll/vga_pll_0002.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns/10ps 2 | module vga_pll_0002( 3 | 4 | // interface 'refclk' 5 | input wire refclk, 6 | 7 | // interface 'reset' 8 | input wire rst, 9 | 10 | // interface 'outclk0' 11 | output wire outclk_0, 12 | 13 | // interface 'locked' 14 | output wire locked 15 | ); 16 | 17 | altera_pll #( 18 | .fractional_vco_multiplier("true"), 19 | .reference_clock_frequency("50.0 MHz"), 20 | .operation_mode("direct"), 21 | .number_of_clocks(1), 22 | .output_clock_frequency0("25.175000 MHz"), 23 | .phase_shift0("0 ps"), 24 | .duty_cycle0(50), 25 | .output_clock_frequency1("0 MHz"), 26 | .phase_shift1("0 ps"), 27 | .duty_cycle1(50), 28 | .output_clock_frequency2("0 MHz"), 29 | .phase_shift2("0 ps"), 30 | .duty_cycle2(50), 31 | .output_clock_frequency3("0 MHz"), 32 | .phase_shift3("0 ps"), 33 | .duty_cycle3(50), 34 | .output_clock_frequency4("0 MHz"), 35 | .phase_shift4("0 ps"), 36 | .duty_cycle4(50), 37 | .output_clock_frequency5("0 MHz"), 38 | .phase_shift5("0 ps"), 39 | .duty_cycle5(50), 40 | .output_clock_frequency6("0 MHz"), 41 | .phase_shift6("0 ps"), 42 | .duty_cycle6(50), 43 | .output_clock_frequency7("0 MHz"), 44 | .phase_shift7("0 ps"), 45 | .duty_cycle7(50), 46 | .output_clock_frequency8("0 MHz"), 47 | .phase_shift8("0 ps"), 48 | .duty_cycle8(50), 49 | .output_clock_frequency9("0 MHz"), 50 | .phase_shift9("0 ps"), 51 | .duty_cycle9(50), 52 | .output_clock_frequency10("0 MHz"), 53 | .phase_shift10("0 ps"), 54 | .duty_cycle10(50), 55 | .output_clock_frequency11("0 MHz"), 56 | .phase_shift11("0 ps"), 57 | .duty_cycle11(50), 58 | .output_clock_frequency12("0 MHz"), 59 | .phase_shift12("0 ps"), 60 | .duty_cycle12(50), 61 | .output_clock_frequency13("0 MHz"), 62 | .phase_shift13("0 ps"), 63 | .duty_cycle13(50), 64 | .output_clock_frequency14("0 MHz"), 65 | .phase_shift14("0 ps"), 66 | .duty_cycle14(50), 67 | .output_clock_frequency15("0 MHz"), 68 | .phase_shift15("0 ps"), 69 | .duty_cycle15(50), 70 | .output_clock_frequency16("0 MHz"), 71 | .phase_shift16("0 ps"), 72 | .duty_cycle16(50), 73 | .output_clock_frequency17("0 MHz"), 74 | .phase_shift17("0 ps"), 75 | .duty_cycle17(50), 76 | .pll_type("General"), 77 | .pll_subtype("General") 78 | ) altera_pll_i ( 79 | .rst (rst), 80 | .outclk ({outclk_0}), 81 | .locked (locked), 82 | .fboutclk ( ), 83 | .fbclk (1'b0), 84 | .refclk (refclk) 85 | ); 86 | endmodule 87 | 88 | -------------------------------------------------------------------------------- /vga_pll_sim.f: -------------------------------------------------------------------------------- 1 | vga_pll_sim/vga_pll.vho 2 | -------------------------------------------------------------------------------- /vga_pll_sim/cadence/cds.lib: -------------------------------------------------------------------------------- 1 | 2 | DEFINE std $CDS_ROOT/tools/inca/files/STD/ 3 | DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/ 4 | DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/ 5 | DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/ 6 | DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/ 7 | DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/ 8 | DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/ 9 | DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/ 10 | DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/ 11 | DEFINE work ./libraries/work/ 12 | DEFINE altera ./libraries/altera/ 13 | DEFINE lpm ./libraries/lpm/ 14 | DEFINE sgate ./libraries/sgate/ 15 | DEFINE altera_mf ./libraries/altera_mf/ 16 | DEFINE altera_lnsim ./libraries/altera_lnsim/ 17 | DEFINE cyclonev ./libraries/cyclonev/ 18 | -------------------------------------------------------------------------------- /vga_pll_sim/cadence/hdl.var: -------------------------------------------------------------------------------- 1 | 2 | DEFINE WORK work 3 | -------------------------------------------------------------------------------- /vga_pll_sim/synopsys/vcsmx/synopsys_sim.setup: -------------------------------------------------------------------------------- 1 | 2 | WORK > DEFAULT 3 | DEFAULT: ./libraries/work/ 4 | work: ./libraries/work/ 5 | altera: ./libraries/altera/ 6 | lpm: ./libraries/lpm/ 7 | sgate: ./libraries/sgate/ 8 | altera_mf: ./libraries/altera_mf/ 9 | altera_lnsim: ./libraries/altera_lnsim/ 10 | cyclonev: ./libraries/cyclonev/ 11 | LIBRARY_SCAN = TRUE 12 | -------------------------------------------------------------------------------- /videomem.cmp: -------------------------------------------------------------------------------- 1 | --Copyright (C) 2018 Intel Corporation. All rights reserved. 2 | --Your use of Intel Corporation's design tools, logic functions 3 | --and other software and tools, and its AMPP partner logic 4 | --functions, and any output files from any of the foregoing 5 | --(including device programming or simulation files), and any 6 | --associated documentation or information are expressly subject 7 | --to the terms and conditions of the Intel Program License 8 | --Subscription Agreement, the Intel Quartus Prime License Agreement, 9 | --the Intel FPGA IP License Agreement, or other applicable license 10 | --agreement, including, without limitation, that your use is for 11 | --the sole purpose of programming logic devices manufactured by 12 | --Intel and sold by Intel or its authorized distributors. Please 13 | --refer to the applicable agreement for further details. 14 | 15 | 16 | component videomem 17 | PORT 18 | ( 19 | address : IN STD_LOGIC_VECTOR (10 DOWNTO 0); 20 | clken : IN STD_LOGIC := '1'; 21 | clock : IN STD_LOGIC := '1'; 22 | data : IN STD_LOGIC_VECTOR (7 DOWNTO 0); 23 | rden : IN STD_LOGIC := '1'; 24 | wren : IN STD_LOGIC ; 25 | q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) 26 | ); 27 | end component; 28 | -------------------------------------------------------------------------------- /videomem.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "RAM: 1-PORT" 2 | set_global_assignment -name IP_TOOL_VERSION "18.0" 3 | set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone V}" 4 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "videomem.vhd"] 5 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "videomem.cmp"] 6 | -------------------------------------------------------------------------------- /videomem.vhd: -------------------------------------------------------------------------------- 1 | -- megafunction wizard: %RAM: 1-PORT% 2 | -- GENERATION: STANDARD 3 | -- VERSION: WM1.0 4 | -- MODULE: altsyncram 5 | 6 | -- ============================================================ 7 | -- File Name: videomem.vhd 8 | -- Megafunction Name(s): 9 | -- altsyncram 10 | -- 11 | -- Simulation Library Files(s): 12 | -- altera_mf 13 | -- ============================================================ 14 | -- ************************************************************ 15 | -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! 16 | -- 17 | -- 18.0.0 Build 614 04/24/2018 SJ Lite Edition 18 | -- ************************************************************ 19 | 20 | 21 | --Copyright (C) 2018 Intel Corporation. All rights reserved. 22 | --Your use of Intel Corporation's design tools, logic functions 23 | --and other software and tools, and its AMPP partner logic 24 | --functions, and any output files from any of the foregoing 25 | --(including device programming or simulation files), and any 26 | --associated documentation or information are expressly subject 27 | --to the terms and conditions of the Intel Program License 28 | --Subscription Agreement, the Intel Quartus Prime License Agreement, 29 | --the Intel FPGA IP License Agreement, or other applicable license 30 | --agreement, including, without limitation, that your use is for 31 | --the sole purpose of programming logic devices manufactured by 32 | --Intel and sold by Intel or its authorized distributors. Please 33 | --refer to the applicable agreement for further details. 34 | 35 | 36 | LIBRARY ieee; 37 | USE ieee.std_logic_1164.all; 38 | 39 | LIBRARY altera_mf; 40 | USE altera_mf.altera_mf_components.all; 41 | 42 | ENTITY videomem IS 43 | PORT 44 | ( 45 | address : IN STD_LOGIC_VECTOR (10 DOWNTO 0); 46 | clken : IN STD_LOGIC := '1'; 47 | clock : IN STD_LOGIC := '1'; 48 | data : IN STD_LOGIC_VECTOR (7 DOWNTO 0); 49 | rden : IN STD_LOGIC := '1'; 50 | wren : IN STD_LOGIC ; 51 | q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) 52 | ); 53 | END videomem; 54 | 55 | 56 | ARCHITECTURE SYN OF videomem IS 57 | 58 | SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0); 59 | 60 | BEGIN 61 | q <= sub_wire0(7 DOWNTO 0); 62 | 63 | altsyncram_component : altsyncram 64 | GENERIC MAP ( 65 | clock_enable_input_a => "NORMAL", 66 | clock_enable_output_a => "BYPASS", 67 | intended_device_family => "Cyclone V", 68 | lpm_hint => "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=VRAM", 69 | lpm_type => "altsyncram", 70 | numwords_a => 2048, 71 | operation_mode => "SINGLE_PORT", 72 | outdata_aclr_a => "NONE", 73 | outdata_reg_a => "UNREGISTERED", 74 | power_up_uninitialized => "FALSE", 75 | read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ", 76 | widthad_a => 11, 77 | width_a => 8, 78 | width_byteena_a => 1 79 | ) 80 | PORT MAP ( 81 | address_a => address, 82 | clock0 => clock, 83 | clocken0 => clken, 84 | data_a => data, 85 | rden_a => rden, 86 | wren_a => wren, 87 | q_a => sub_wire0 88 | ); 89 | 90 | 91 | 92 | END SYN; 93 | 94 | -- ============================================================ 95 | -- CNX file retrieval info 96 | -- ============================================================ 97 | -- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" 98 | -- Retrieval info: PRIVATE: AclrAddr NUMERIC "0" 99 | -- Retrieval info: PRIVATE: AclrByte NUMERIC "0" 100 | -- Retrieval info: PRIVATE: AclrData NUMERIC "0" 101 | -- Retrieval info: PRIVATE: AclrOutput NUMERIC "0" 102 | -- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0" 103 | -- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" 104 | -- Retrieval info: PRIVATE: BlankMemory NUMERIC "1" 105 | -- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "1" 106 | -- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "1" 107 | -- Retrieval info: PRIVATE: Clken NUMERIC "1" 108 | -- Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1" 109 | -- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" 110 | -- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" 111 | -- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" 112 | -- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V" 113 | -- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "1" 114 | -- Retrieval info: PRIVATE: JTAG_ID STRING "VRAM" 115 | -- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" 116 | -- Retrieval info: PRIVATE: MIFfilename STRING "videomem.hex" 117 | -- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "2048" 118 | -- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" 119 | -- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3" 120 | -- Retrieval info: PRIVATE: RegAddr NUMERIC "1" 121 | -- Retrieval info: PRIVATE: RegData NUMERIC "1" 122 | -- Retrieval info: PRIVATE: RegOutput NUMERIC "0" 123 | -- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" 124 | -- Retrieval info: PRIVATE: SingleClock NUMERIC "1" 125 | -- Retrieval info: PRIVATE: UseDQRAM NUMERIC "1" 126 | -- Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0" 127 | -- Retrieval info: PRIVATE: WidthAddr NUMERIC "11" 128 | -- Retrieval info: PRIVATE: WidthData NUMERIC "8" 129 | -- Retrieval info: PRIVATE: rden NUMERIC "1" 130 | -- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all 131 | -- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "NORMAL" 132 | -- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" 133 | -- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V" 134 | -- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=VRAM" 135 | -- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" 136 | -- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "2048" 137 | -- Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT" 138 | -- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" 139 | -- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED" 140 | -- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE" 141 | -- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ" 142 | -- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "11" 143 | -- Retrieval info: CONSTANT: WIDTH_A NUMERIC "8" 144 | -- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" 145 | -- Retrieval info: USED_PORT: address 0 0 11 0 INPUT NODEFVAL "address[10..0]" 146 | -- Retrieval info: USED_PORT: clken 0 0 0 0 INPUT VCC "clken" 147 | -- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" 148 | -- Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]" 149 | -- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]" 150 | -- Retrieval info: USED_PORT: rden 0 0 0 0 INPUT VCC "rden" 151 | -- Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren" 152 | -- Retrieval info: CONNECT: @address_a 0 0 11 0 address 0 0 11 0 153 | -- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 154 | -- Retrieval info: CONNECT: @clocken0 0 0 0 0 clken 0 0 0 0 155 | -- Retrieval info: CONNECT: @data_a 0 0 8 0 data 0 0 8 0 156 | -- Retrieval info: CONNECT: @rden_a 0 0 0 0 rden 0 0 0 0 157 | -- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0 158 | -- Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0 159 | -- Retrieval info: GEN_FILE: TYPE_NORMAL videomem.vhd TRUE 160 | -- Retrieval info: GEN_FILE: TYPE_NORMAL videomem.inc FALSE 161 | -- Retrieval info: GEN_FILE: TYPE_NORMAL videomem.cmp TRUE 162 | -- Retrieval info: GEN_FILE: TYPE_NORMAL videomem.bsf FALSE 163 | -- Retrieval info: GEN_FILE: TYPE_NORMAL videomem_inst.vhd FALSE 164 | -- Retrieval info: LIB_FILE: altera_mf 165 | -------------------------------------------------------------------------------- /videorom.cmp: -------------------------------------------------------------------------------- 1 | --Copyright (C) 2018 Intel Corporation. All rights reserved. 2 | --Your use of Intel Corporation's design tools, logic functions 3 | --and other software and tools, and its AMPP partner logic 4 | --functions, and any output files from any of the foregoing 5 | --(including device programming or simulation files), and any 6 | --associated documentation or information are expressly subject 7 | --to the terms and conditions of the Intel Program License 8 | --Subscription Agreement, the Intel Quartus Prime License Agreement, 9 | --the Intel FPGA IP License Agreement, or other applicable license 10 | --agreement, including, without limitation, that your use is for 11 | --the sole purpose of programming logic devices manufactured by 12 | --Intel and sold by Intel or its authorized distributors. Please 13 | --refer to the applicable agreement for further details. 14 | 15 | 16 | component videorom 17 | PORT 18 | ( 19 | address : IN STD_LOGIC_VECTOR (12 DOWNTO 0); 20 | clken : IN STD_LOGIC := '1'; 21 | clock : IN STD_LOGIC := '1'; 22 | data : IN STD_LOGIC_VECTOR (7 DOWNTO 0); 23 | rden : IN STD_LOGIC := '1'; 24 | wren : IN STD_LOGIC ; 25 | q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) 26 | ); 27 | end component; 28 | -------------------------------------------------------------------------------- /videorom.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "RAM: 1-PORT" 2 | set_global_assignment -name IP_TOOL_VERSION "18.0" 3 | set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone V}" 4 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "videorom.vhd"] 5 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "videorom.cmp"] 6 | --------------------------------------------------------------------------------