├── README.md ├── cores └── cortexm0_designstart_r1p0 │ └── logical │ ├── cortexm0_dap │ └── verilog │ │ └── CORTEXM0DAP.v │ ├── cortexm0_integration │ └── verilog │ │ ├── CORTEXM0INTEGRATION.v │ │ ├── cortexm0_rst_ctl.v │ │ └── cortexm0_wic.v │ ├── cortexm0ds │ └── verilog │ │ ├── CORTEXM0DS.v │ │ └── cortexm0ds_logic.v │ └── models │ └── cells │ └── cm0_dbg_reset_sync.v ├── documentation └── DUI0926A_cortex_m0_designstart_rtl_testbench_r1p0_user_guide.pdf ├── implementation_tsmc_ce018fg └── cortex_m0_mcu_system_synopsys │ ├── Makefile │ └── scripts │ ├── cmsdk_mcu_system_clocks.tcl │ ├── cmsdk_mcu_system_constraints.tcl │ ├── cmsdk_mcu_system_dft.tcl │ ├── cmsdk_mcu_system_fm.tcl │ ├── cmsdk_mcu_system_reports.tcl │ ├── cmsdk_mcu_system_syn.tcl │ ├── cmsdk_mcu_system_tech.tcl │ ├── cmsdk_mcu_system_verilog-rtl.tcl │ ├── cmsdk_mcu_system_verilog.tcl │ └── design_config.tcl ├── logical ├── cmsdk_ahb_default_slave │ └── verilog │ │ └── cmsdk_ahb_default_slave.v ├── cmsdk_ahb_gpio │ └── verilog │ │ ├── cmsdk_ahb_gpio.v │ │ └── cmsdk_ahb_to_iop.v ├── cmsdk_ahb_slave_mux │ └── verilog │ │ └── cmsdk_ahb_slave_mux.v ├── cmsdk_ahb_to_apb │ └── verilog │ │ └── cmsdk_ahb_to_apb.v ├── cmsdk_apb4_eg_slave │ └── verilog │ │ ├── cmsdk_apb4_eg_slave.v │ │ ├── cmsdk_apb4_eg_slave_interface.v │ │ └── cmsdk_apb4_eg_slave_reg.v ├── cmsdk_apb_dualtimers │ └── verilog │ │ ├── cmsdk_apb_dualtimers.v │ │ ├── cmsdk_apb_dualtimers_defs.v │ │ └── cmsdk_apb_dualtimers_frc.v ├── cmsdk_apb_slave_mux │ └── verilog │ │ └── cmsdk_apb_slave_mux.v ├── cmsdk_apb_subsystem │ └── verilog │ │ ├── cmsdk_apb_subsystem.v │ │ ├── cmsdk_apb_test_slave.v │ │ └── cmsdk_irq_sync.v ├── cmsdk_apb_timer │ └── verilog │ │ └── cmsdk_apb_timer.v ├── cmsdk_apb_uart │ └── verilog │ │ └── cmsdk_apb_uart.v ├── cmsdk_apb_watchdog │ └── verilog │ │ ├── cmsdk_apb_watchdog.v │ │ ├── cmsdk_apb_watchdog_defs.v │ │ └── cmsdk_apb_watchdog_frc.v ├── cmsdk_iop_gpio │ └── verilog │ │ └── cmsdk_iop_gpio.v └── models │ ├── clkgate │ └── cmsdk_clock_gate.v │ └── memories │ ├── cmsdk_ahb_memory_models_defs.v │ ├── cmsdk_ahb_ram.v │ ├── cmsdk_ahb_ram_beh.v │ └── cmsdk_ahb_rom.v ├── software ├── cmsis │ ├── CMSIS │ │ └── Include │ │ │ ├── core_cm0.h │ │ │ ├── core_cm0plus.h │ │ │ ├── core_cmFunc.h │ │ │ └── core_cmInstr.h │ └── Device │ │ └── ARM │ │ └── CMSDK_CM0 │ │ ├── Include │ │ ├── CMSDK_CM0.h │ │ ├── CMSDK_driver.h │ │ └── system_CMSDK_CM0.h │ │ └── Source │ │ ├── ARM │ │ └── startup_CMSDK_CM0.s │ │ ├── CMSDK_driver.c │ │ ├── GCC │ │ └── startup_CMSDK_CM0.s │ │ └── system_CMSDK_CM0.c └── common │ ├── bootloader │ └── bootloader.c │ ├── demos │ ├── dualtimer_demo.c │ ├── interrupt_demo.c │ ├── self_reset_demo.c │ ├── sleep_demo.c │ └── watchdog_demo.c │ ├── dhry │ ├── dhry.h │ ├── dhry_1.c │ └── dhry_2.c │ ├── retarget │ ├── retarget.c │ ├── uart_stdout.c │ └── uart_stdout.h │ ├── scripts │ ├── cmsdk_bootloader.ld │ ├── cmsdk_cm0.ld │ ├── lib-nosys.ld │ ├── lib-rdimon.ld │ ├── sections-nokeep.ld │ └── sections.ld │ └── validation │ ├── apb_mux_tests.c │ ├── default_slaves_tests.c │ ├── gpio_driver_tests.c │ ├── gpio_tests.c │ ├── memory_tests.c │ ├── timer_driver_tests.c │ ├── timer_tests.c │ ├── uart_driver_tests.c │ └── uart_tests.c └── systems └── cortex_m0_mcu ├── rtl_sim ├── makefile └── scripts │ └── check_tests.pl ├── testcodes ├── apb_mux_tests │ ├── apb_mux_tests_cm0.uvopt │ ├── apb_mux_tests_cm0.uvproj │ └── makefile ├── bootloader │ ├── bootloader_cm0.uvopt │ ├── bootloader_cm0.uvproj │ └── makefile ├── default_slaves_tests │ ├── default_slaves_tests_cm0.uvopt │ ├── default_slaves_tests_cm0.uvproj │ └── makefile ├── dhry │ ├── dhry_cm0.uvopt │ ├── dhry_cm0.uvproj │ └── makefile ├── dualtimer_demo │ ├── dualtimer_demo_cm0.uvopt │ ├── dualtimer_demo_cm0.uvproj │ └── makefile ├── generic │ ├── config_id.h │ ├── mcu_debugtester_interface.c │ └── mcu_debugtester_interface.h ├── gpio_driver_tests │ ├── gpio_driver_tests_cm0.uvopt │ ├── gpio_driver_tests_cm0.uvproj │ └── makefile ├── gpio_tests │ ├── gpio_tests_cm0.uvopt │ ├── gpio_tests_cm0.uvproj │ └── makefile ├── hello │ ├── hello.c │ ├── hello_cm0.uvopt │ ├── hello_cm0.uvproj │ └── makefile ├── interrupt_demo │ ├── interrupt_demo_cm0.uvopt │ ├── interrupt_demo_cm0.uvproj │ └── makefile ├── memory_tests │ ├── makefile │ ├── memory_tests_cm0.uvopt │ └── memory_tests_cm0.uvproj ├── rtx_demo │ ├── RTX_Config.c │ ├── makefile │ ├── rtx_demo.c │ ├── rtx_demo_cm0.hex │ ├── rtx_demo_cm0.uvopt │ └── rtx_demo_cm0.uvproj ├── self_reset_demo │ ├── makefile │ ├── self_reset_demo_cm0.uvopt │ └── self_reset_demo_cm0.uvproj ├── sleep_demo │ ├── makefile │ ├── sleep_demo_cm0.uvopt │ └── sleep_demo_cm0.uvproj ├── timer_driver_tests │ ├── makefile │ ├── timer_driver_tests_cm0.uvopt │ └── timer_driver_tests_cm0.uvproj ├── timer_tests │ ├── makefile │ ├── timer_tests_cm0.uvopt │ └── timer_tests_cm0.uvproj ├── uart_driver_tests │ ├── makefile │ ├── uart_driver_tests_cm0.uvopt │ └── uart_driver_tests_cm0.uvproj ├── uart_tests │ ├── makefile │ ├── uart_tests_cm0.uvopt │ └── uart_tests_cm0.uvproj └── watchdog_demo │ ├── makefile │ ├── watchdog_demo_cm0.uvopt │ └── watchdog_demo_cm0.uvproj └── verilog ├── cmsdk_ahb_cs_rom_table.v ├── cmsdk_clkreset.v ├── cmsdk_mcu.v ├── cmsdk_mcu_addr_decode.v ├── cmsdk_mcu_clkctrl.v ├── cmsdk_mcu_defs.v ├── cmsdk_mcu_pin_mux.v ├── cmsdk_mcu_stclkctrl.v ├── cmsdk_mcu_sysctrl.v ├── cmsdk_mcu_system.v ├── cmsdk_uart_capture.v ├── tb_cmsdk_mcu.v └── tbench_M0_DS.vc /README.md: -------------------------------------------------------------------------------- 1 | # cortexm0ds 2 | -------------------------------------------------------------------------------- /cores/cortexm0_designstart_r1p0/logical/cortexm0_dap/verilog/CORTEXM0DAP.v: -------------------------------------------------------------------------------- 1 | //----------------------------------------------------------------------------- 2 | // The confidential and proprietary information contained in this file may 3 | // only be used by a person authorised under and to the extent permitted 4 | // by a subsisting licensing agreement from ARM Limited. 5 | // 6 | // (C) COPYRIGHT 2015 ARM Limited or its affiliates. 7 | // ALL RIGHTS RESERVED 8 | // 9 | // This entire notice must be reproduced on all copies of this file 10 | // and copies of this file may only be made by a person if such person is 11 | // permitted to do so under the terms of a subsisting license agreement 12 | // from ARM Limited. 13 | // 14 | // SVN Information 15 | // 16 | // Checked In : $Date: 2009-03-19 14:11:42 +0000 (Thu, 19 Mar 2009) $ 17 | // 18 | // Revision : $Revision: 104573 $ 19 | // 20 | // Release Information : Cortex-M0 DesignStart-r1p0-00rel0 21 | //----------------------------------------------------------------------------- 22 | 23 | module CORTEXM0DAP 24 | ( //DP Signals 25 | SWCLKTCK, DPRESETn, nTRST, 26 | TDI, TDO, nTDOEN, SWDITMS, SWDO, SWDOEN, 27 | CDBGPWRUPREQ, CDBGPWRUPACK, 28 | //AP Signals 29 | DCLK, APRESETn, DEVICEEN, 30 | SLVADDR, SLVWDATA, SLVTRANS, SLVWRITE, SLVRDATA, SLVREADY, SLVRESP, 31 | SLVSIZE, BASEADDR, 32 | //Configuration Pins 33 | ECOREVNUM, 34 | // DFT 35 | SE 36 | ); 37 | 38 | // ---------------------------------------------------------------------------- 39 | // Port Definitions 40 | // ---------------------------------------------------------------------------- 41 | //DP I/O 42 | input SWCLKTCK; // SW/JTAG clock 43 | input DPRESETn; // Negative sense power-on reset for DP 44 | input nTRST; // JTAG test logic reset signal 45 | input TDI; // JTAG data in 46 | output TDO; // JTAG data out 47 | output nTDOEN; // JTAG TDO Output Enable 48 | input SWDITMS; // SW data in/JTAG TMS 49 | output SWDO; // SW data out 50 | output SWDOEN; // SW data out enable 51 | output CDBGPWRUPREQ; // System Power Up & Reset Request/Acknowledge 52 | input CDBGPWRUPACK; // " " 53 | 54 | //AP I/O 55 | input DCLK; // AP clock 56 | input APRESETn; // Negative sense power-on reset for AP 57 | input DEVICEEN; // Debug enabled by system 58 | output [31:0] SLVADDR; // Bus address 59 | output [31:0] SLVWDATA; // Bus write data 60 | output [1:0] SLVTRANS; // Bus transfer valid 61 | output SLVWRITE; // Bus write/not read 62 | output [1:0] SLVSIZE; // Bus Access Size 63 | input [31:0] SLVRDATA; // Bus read data 64 | input SLVREADY; // Bus Ready from bus 65 | input SLVRESP; // Bus Response from bus 66 | input [31:0] BASEADDR; // AP ROM Table Base Value (to be tied externally) 67 | 68 | //Configuration IO 69 | input [7:0] ECOREVNUM; // Top 4 bits = DP Revision, Bottom 4 = AP Revision 70 | 71 | // DFT 72 | input SE; // Scan enable for DFT 73 | 74 | 75 | assign TDO = 1'b0; 76 | assign nTDOEN = 1'b1; 77 | assign SWDO = 1'b0; 78 | assign SWDOEN = 1'b0; 79 | assign CDBGPWRUPREQ = 1'b0; 80 | assign SLVADDR = 32'h0; 81 | assign SLVWDATA = 32'h0; 82 | assign SLVTRANS = 2'b00; 83 | assign SLVWRITE = 1'b0; 84 | assign SLVSIZE = 2'b00; 85 | 86 | 87 | endmodule 88 | -------------------------------------------------------------------------------- /cores/cortexm0_designstart_r1p0/logical/cortexm0_integration/verilog/cortexm0_rst_ctl.v: -------------------------------------------------------------------------------- 1 | //----------------------------------------------------------------------------- 2 | // The confidential and proprietary information contained in this file may 3 | // only be used by a person authorised under and to the extent permitted 4 | // by a subsisting licensing agreement from ARM Limited. 5 | // 6 | // (C) COPYRIGHT 2009-2015 ARM Limited or its affiliates. 7 | // ALL RIGHTS RESERVED 8 | // 9 | // This entire notice must be reproduced on all copies of this file 10 | // and copies of this file may only be made by a person if such person is 11 | // permitted to do so under the terms of a subsisting license agreement 12 | // from ARM Limited. 13 | // 14 | // SVN Information 15 | // 16 | // Checked In : $Date: 2009-03-21 16:43:18 +0000 (Sat, 21 Mar 2009) $ 17 | // 18 | // Revision : $Revision: 104871 $ 19 | // 20 | // Release Information : Cortex-M0 DesignStart-r1p0-00rel0 21 | //----------------------------------------------------------------------------- 22 | 23 | //----------------------------------------------------------------------------- 24 | // CORTEX-M0 EXAMPLE RESET CONTROLLER 25 | // This module is designed as an example reset controller for the Cortex-M0 26 | // // processor It takes a global reset that can be asynchronously asserted 27 | // and generates from it synchronously asserted and deasserted resets based 28 | // on synchronous reset requests 29 | // This module is intended to interface to the example PMU provided (cortexm0_pmu.v) 30 | // You can modify this module to suit your requirements 31 | //----------------------------------------------------------------------------- 32 | 33 | module cortexm0_rst_ctl 34 | (/*AUTOARG*/ 35 | // Outputs 36 | PORESETn, HRESETn, DBGRESETn, HRESETREQ, 37 | // Inputs 38 | GLOBALRESETn, FCLK, HCLK, DCLK, SYSRESETREQ, PMUHRESETREQ, 39 | PMUDBGRESETREQ, RSTBYPASS, SE 40 | ); 41 | 42 | input GLOBALRESETn; // Global asynchronous reset 43 | input FCLK; // Free running clock (connect to FCLK of CORTEXM0INTEGRATION) 44 | input HCLK; // AHB clock (connect to HCLK of CORTEXM0INTEGRATION) 45 | input DCLK; // Debug clock (connect to DCLK of CORTEXM0INTEGRATION) 46 | input SYSRESETREQ; // Synchronous (to HCLK) request for HRESETn from system 47 | input PMUHRESETREQ; // Synchronous (to HCLK) request for HRESETn from PMU 48 | input PMUDBGRESETREQ; // Synchronous (to DCLK) request for DBGRESETn from PMU 49 | input RSTBYPASS; // Reset synchroniser bypass (for DFT) 50 | input SE; // Scan Enable (for DFT) 51 | 52 | output PORESETn; // Connect to PORESETn of CORTEXM0INTEGRATION 53 | output HRESETn; // Connect to HRESETn of CORTEXM0INTEGRATION 54 | output DBGRESETn; // Connect to DBGRESETn of CORTEXM0INTEGRATION 55 | output HRESETREQ; // Synchronous (to FCLK) indication of HRESET request 56 | 57 | // Sample synchronous requests to assert HRESETn 58 | // Sources: 59 | // 1 - System (SYSRESETREQ) 60 | // 2 - PMU (PMUHRESETREQ) 61 | wire h_reset_req_in = SYSRESETREQ | PMUHRESETREQ; 62 | 63 | cm0_rst_send_set u_hreset_req 64 | (.RSTn (PORESETn), 65 | .CLK (FCLK), 66 | .RSTREQIN (h_reset_req_in), 67 | .RSTREQOUT (HRESETREQ) 68 | ); 69 | 70 | // Sample synchronous requests to assert DBGRESETn 71 | wire dbg_reset_req_sync; 72 | 73 | cm0_rst_send_set u_dbgreset_req 74 | (.RSTn (PORESETn), 75 | .CLK (FCLK), 76 | .RSTREQIN (PMUDBGRESETREQ), 77 | .RSTREQOUT (dbg_reset_req_sync) 78 | ); 79 | 80 | // -------------------- 81 | // Reset synchronisers 82 | // -------------------- 83 | 84 | cm0_rst_sync u_poresetn_sync 85 | (.RSTINn (GLOBALRESETn), 86 | .RSTREQ (1'b0), 87 | .CLK (FCLK), 88 | .SE (SE), 89 | .RSTBYPASS (RSTBYPASS), 90 | .RSTOUTn (PORESETn) 91 | ); 92 | 93 | cm0_rst_sync u_hresetn_sync 94 | (.RSTINn (GLOBALRESETn), 95 | .RSTREQ (HRESETREQ), 96 | .CLK (HCLK), 97 | .SE (SE), 98 | .RSTBYPASS (RSTBYPASS), 99 | .RSTOUTn (HRESETn) 100 | ); 101 | 102 | cm0_rst_sync u_dbgresetn_sync 103 | (.RSTINn (GLOBALRESETn), 104 | .RSTREQ (dbg_reset_req_sync), 105 | .CLK (DCLK), 106 | .SE (SE), 107 | .RSTBYPASS (RSTBYPASS), 108 | .RSTOUTn (DBGRESETn) 109 | ); 110 | 111 | endmodule // cortexm0_rst_ctl 112 | 113 | 114 | 115 | -------------------------------------------------------------------------------- /cores/cortexm0_designstart_r1p0/logical/cortexm0_integration/verilog/cortexm0_wic.v: -------------------------------------------------------------------------------- 1 | //----------------------------------------------------------------------------- 2 | // The confidential and proprietary information contained in this file may 3 | // only be used by a person authorised under and to the extent permitted 4 | // by a subsisting licensing agreement from ARM Limited. 5 | // 6 | // (C) COPYRIGHT 2015 ARM Limited or its affiliates. 7 | // ALL RIGHTS RESERVED 8 | // 9 | // This entire notice must be reproduced on all copies of this file 10 | // and copies of this file may only be made by a person if such person is 11 | // permitted to do so under the terms of a subsisting license agreement 12 | // from ARM Limited. 13 | // 14 | // SVN Information 15 | // 16 | // Checked In : $Date: 2009-03-16 19:48:51 +0000 (Mon, 16 Mar 2009) $ 17 | // 18 | // Revision : $Revision: 104227 $ 19 | // 20 | // Release Information : Cortex-M0 DesignStart-r1p0-00rel0 21 | //----------------------------------------------------------------------------- 22 | 23 | // Purpose : Dummy Cortex-M0 Wake-Up Interrupt Controller 24 | // ----------------------------------------------------------------------------- 25 | 26 | module cortexm0_wic 27 | (input FCLK, 28 | input nRESET, 29 | input WICLOAD, // WIC mask load from core 30 | input WICCLEAR, // WIC mask clear from core 31 | input [33:0] WICINT, // Interrupt request from system 32 | input [33:0] WICMASK, // Mask from core 33 | input WICENREQ, // WIC enable request from PMU 34 | input WICDSACKn, // WIC enable ack from core 35 | output WAKEUP, // Wake up request to PMU 36 | output [33:0] WICSENSE, // 37 | output [33:0] WICPEND, // Pended interrupt request 38 | output WICDSREQn, // WIC enable request to core 39 | output WICENACK); // WIC enable ack to PMU 40 | 41 | assign WAKEUP = 1'b0; 42 | assign WICSENSE = 34'h0; 43 | assign WICPEND = 34'h0; 44 | assign WICDSREQn = 1'b1; 45 | assign WICENACK = 1'b0; 46 | 47 | endmodule 48 | -------------------------------------------------------------------------------- /cores/cortexm0_designstart_r1p0/logical/cortexm0ds/verilog/CORTEXM0DS.v: -------------------------------------------------------------------------------- 1 | //------------------------------------------------------------------------------ 2 | // The confidential and proprietary information contained in this file may 3 | // only be used by a person authorised under and to the extent permitted 4 | // by a subsisting licensing agreement from ARM Limited. 5 | // 6 | // (C) COPYRIGHT 2010-2015 ARM Limited or its affiliates. 7 | // ALL RIGHTS RESERVED 8 | // 9 | // This entire notice must be reproduced on all copies of this file 10 | // and copies of this file may only be made by a person if such person is 11 | // permitted to do so under the terms of a subsisting license agreement 12 | // from ARM Limited. 13 | // 14 | // Version and Release Control Information: 15 | // 16 | // File Revision : $Revision: 275084 $ 17 | // File Date : $Date: 2014-03-27 15:09:11 +0000 (Thu, 27 Mar 2014) $ 18 | // 19 | // Release Information : Cortex-M0 DesignStart-r1p0-00rel0 20 | //------------------------------------------------------------------------------ 21 | // Verilog-2001 (IEEE Std 1364-2001) 22 | //------------------------------------------------------------------------------ 23 | // 24 | //------------------------------------------------------------------------------ 25 | // Cortex-M0 DesignStart processor macro cell level 26 | //------------------------------------------------------------------------------ 27 | 28 | module CORTEXM0DS ( 29 | // CLOCK AND RESETS ------------------ 30 | input wire HCLK, // Clock 31 | input wire HRESETn, // Asynchronous reset 32 | 33 | // AHB-LITE MASTER PORT -------------- 34 | output wire [31:0] HADDR, // AHB transaction address 35 | output wire [ 2:0] HBURST, // AHB burst: tied to single 36 | output wire HMASTLOCK, // AHB locked transfer (always zero) 37 | output wire [ 3:0] HPROT, // AHB protection: priv; data or inst 38 | output wire [ 2:0] HSIZE, // AHB size: byte, half-word or word 39 | output wire [ 1:0] HTRANS, // AHB transfer: non-sequential only 40 | output wire [31:0] HWDATA, // AHB write-data 41 | output wire HWRITE, // AHB write control 42 | input wire [31:0] HRDATA, // AHB read-data 43 | input wire HREADY, // AHB stall signal 44 | input wire HRESP, // AHB error response 45 | 46 | // MISCELLANEOUS --------------------- 47 | input wire NMI, // Non-maskable interrupt input 48 | input wire [31:0] IRQ, // Interrupt request inputs 49 | output wire TXEV, // Event output (SEV executed) 50 | input wire RXEV, // Event input 51 | output wire LOCKUP, // Core is locked-up 52 | output wire SYSRESETREQ, // System reset request 53 | input wire STCLKEN, // SysTick SCLK clock enable 54 | input wire [25:0] STCALIB, // SysTick calibration register value 55 | 56 | // POWER MANAGEMENT ------------------ 57 | output wire SLEEPING // Core and NVIC sleeping 58 | ); 59 | 60 | //------------------------------------------------------------------------------ 61 | // Declare visibility signals and some intermediate signals 62 | //------------------------------------------------------------------------------ 63 | wire [31: 0] cm0_r00; 64 | wire [31: 0] cm0_r01; 65 | wire [31: 0] cm0_r02; 66 | wire [31: 0] cm0_r03; 67 | wire [31: 0] cm0_r04; 68 | wire [31: 0] cm0_r05; 69 | wire [31: 0] cm0_r06; 70 | wire [31: 0] cm0_r07; 71 | wire [31: 0] cm0_r08; 72 | wire [31: 0] cm0_r09; 73 | wire [31: 0] cm0_r10; 74 | wire [31: 0] cm0_r11; 75 | wire [31: 0] cm0_r12; 76 | wire [31: 0] cm0_msp; 77 | wire [31: 0] cm0_psp; 78 | wire [31: 0] cm0_r14; 79 | wire [31: 0] cm0_pc; 80 | wire [31: 0] cm0_xpsr; 81 | wire [31: 0] cm0_control; 82 | wire [31: 0] cm0_primask; 83 | 84 | wire [29: 0] vis_msp; 85 | wire [29: 0] vis_psp; 86 | wire [30: 0] vis_pc; 87 | wire [ 3: 0] vis_apsr; 88 | wire vis_tbit; 89 | wire [ 5: 0] vis_ipsr; 90 | wire vis_control; 91 | wire vis_primask; 92 | 93 | //------------------------------------------------------------------------------ 94 | // Instantiate Cortex-M0 processor logic level 95 | //------------------------------------------------------------------------------ 96 | 97 | cortexm0ds_logic u_logic ( 98 | .hclk (HCLK), 99 | .hreset_n (HRESETn), 100 | 101 | .haddr_o (HADDR[31:0]), 102 | .hburst_o (HBURST[2:0]), 103 | .hmastlock_o (HMASTLOCK), 104 | .hprot_o (HPROT[3:0]), 105 | .hsize_o (HSIZE[2:0]), 106 | .htrans_o (HTRANS[1:0]), 107 | .hwdata_o (HWDATA[31:0]), 108 | .hwrite_o (HWRITE), 109 | .hrdata_i (HRDATA[31:0]), 110 | .hready_i (HREADY), 111 | .hresp_i (HRESP), 112 | 113 | .nmi_i (NMI), 114 | .irq_i (IRQ), 115 | .txev_o (TXEV), 116 | .rxev_i (RXEV), 117 | .lockup_o (LOCKUP), 118 | .sys_reset_req_o (SYSRESETREQ), 119 | .st_clk_en_i (STCLKEN), 120 | .st_calib_i (STCALIB), 121 | 122 | .sleeping_o (SLEEPING), 123 | 124 | .vis_r0_o (cm0_r00[31:0]), 125 | .vis_r1_o (cm0_r01[31:0]), 126 | .vis_r2_o (cm0_r02[31:0]), 127 | .vis_r3_o (cm0_r03[31:0]), 128 | .vis_r4_o (cm0_r04[31:0]), 129 | .vis_r5_o (cm0_r05[31:0]), 130 | .vis_r6_o (cm0_r06[31:0]), 131 | .vis_r7_o (cm0_r07[31:0]), 132 | .vis_r8_o (cm0_r08[31:0]), 133 | .vis_r9_o (cm0_r09[31:0]), 134 | .vis_r10_o (cm0_r10[31:0]), 135 | .vis_r11_o (cm0_r11[31:0]), 136 | .vis_r12_o (cm0_r12[31:0]), 137 | .vis_msp_o (vis_msp[29:0]), 138 | .vis_psp_o (vis_psp[29:0]), 139 | .vis_r14_o (cm0_r14[31:0]), 140 | .vis_pc_o (vis_pc[30:0]), 141 | .vis_apsr_o (vis_apsr[3:0]), 142 | .vis_tbit_o (vis_tbit), 143 | .vis_ipsr_o (vis_ipsr[5:0]), 144 | .vis_control_o (vis_control), 145 | .vis_primask_o (vis_primask) 146 | ); 147 | 148 | //------------------------------------------------------------------------------ 149 | // Construct some visibility signals out of intermediate signals 150 | //------------------------------------------------------------------------------ 151 | 152 | assign cm0_msp = {vis_msp[29:0],2'd0}; 153 | assign cm0_psp = {vis_psp[29:0],2'd0}; 154 | assign cm0_pc = {vis_pc[30:0],1'b0}; 155 | assign cm0_xpsr = {vis_apsr[3:0],3'd0,vis_tbit,18'd0,vis_ipsr[5:0]}; 156 | assign cm0_control = {30'd0,vis_control,1'b0}; 157 | assign cm0_primask = {31'd0,vis_primask}; 158 | 159 | endmodule 160 | -------------------------------------------------------------------------------- /cores/cortexm0_designstart_r1p0/logical/models/cells/cm0_dbg_reset_sync.v: -------------------------------------------------------------------------------- 1 | //----------------------------------------------------------------------------- 2 | // The confidential and proprietary information contained in this file may 3 | // only be used by a person authorised under and to the extent permitted 4 | // by a subsisting licensing agreement from ARM Limited. 5 | // 6 | // (C) COPYRIGHT 2008-2015 ARM Limited or its affiliates. 7 | // ALL RIGHTS RESERVED 8 | // 9 | // This entire notice must be reproduced on all copies of this file 10 | // and copies of this file may only be made by a person if such person is 11 | // permitted to do so under the terms of a subsisting license agreement 12 | // from ARM Limited. 13 | // 14 | // SVN Information 15 | // 16 | // Checked In : $Date: 2009-02-18 14:27:55 +0000 (Wed, 18 Feb 2009) $ 17 | // 18 | // Revision : $Revision: 101336 $ 19 | // 20 | // Release Information : Cortex-M0 DesignStart-r1p0-00rel0 21 | //----------------------------------------------------------------------------- 22 | 23 | module cm0_dbg_reset_sync #(parameter PRESENT = 1) 24 | (input wire RSTIN, 25 | input wire CLK, 26 | input wire SE, 27 | input wire RSTBYPASS, 28 | output wire RSTOUT); 29 | 30 | // This module is instantiated where a reset synchroniser is required. 31 | // The purpose of this module is to produce a reset which is asynchronously 32 | // asserted and synchronously deasserted from a reset that is both asserted 33 | // and deasserted asynchronously. Note that it is assumed here that 34 | // the resets in question are active LOW 35 | 36 | // ------------------------------------------------------------ 37 | // NOTE: THIS MODULE IS NOT INTENDED FOR USE IN SYNTHESIS 38 | // IT IS STRONGLY RECOMMENDED THAT AN EQUIVALENT MODULE 39 | // DIRECTLY INSTANTIATING CELLS FROM YOUR LIBRARY THAT MEET 40 | // THE REQUIREMENTS DETAILED BELOW IS USED INSTEAD 41 | // ------------------------------------------------------------ 42 | 43 | // Requirements 44 | // ------------- 45 | 46 | // 1 - The final D-type in the synchroniser must be guaranteed to 47 | // change cleanly (i.e. never glitch) whilst reset is held 48 | // inactive 49 | 50 | // ------------------------------------------------------------ 51 | // Reference model for reset synchroniser 52 | // ------------------------------------------------------------ 53 | 54 | reg rst_sync0, rst_sync1, rst_sync2; 55 | 56 | wire cfg_present = (PRESENT != 0); 57 | 58 | always @(posedge CLK or negedge RSTIN) 59 | if (~RSTIN) begin 60 | rst_sync0 <= 1'b0; 61 | rst_sync1 <= 1'b0; 62 | rst_sync2 <= 1'b0; 63 | end else if (cfg_present) begin 64 | rst_sync0 <= 1'b1; 65 | rst_sync1 <= rst_sync0; 66 | rst_sync2 <= rst_sync1; 67 | end 68 | 69 | assign RSTOUT = (RSTBYPASS | ~cfg_present) ? RSTIN : rst_sync2; 70 | 71 | endmodule 72 | 73 | // --------------------------------------------------------------- 74 | // EOF 75 | // --------------------------------------------------------------- 76 | -------------------------------------------------------------------------------- /documentation/DUI0926A_cortex_m0_designstart_rtl_testbench_r1p0_user_guide.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ForrestBlue/cortexm0ds/3108090d4a9af226b4e9f87fef89f7ff6f37795a/documentation/DUI0926A_cortex_m0_designstart_rtl_testbench_r1p0_user_guide.pdf -------------------------------------------------------------------------------- /implementation_tsmc_ce018fg/cortex_m0_mcu_system_synopsys/Makefile: -------------------------------------------------------------------------------- 1 | # ----------------------------------------------------------------------------- 2 | # The confidential and proprietary information contained in this file may 3 | # only be used by a person authorised under and to the extent permitted 4 | # by a subsisting licensing agreement from ARM Limited. 5 | # 6 | # (C) COPYRIGHT 2012-2015 ARM Limited or its affiliates. 7 | # ALL RIGHTS RESERVED 8 | # 9 | # This entire notice must be reproduced on all copies of this file 10 | # and copies of this file may only be made by a person if such person is 11 | # permitted to do so under the terms of a subsisting license agreement 12 | # from ARM Limited. 13 | # 14 | # SVN Information 15 | # 16 | # Checked In : $Date: 2013-04-10 14:47:58 +0100 (Wed, 10 Apr 2013) $ 17 | # 18 | # Revision : $Revision: 243487 $ 19 | # 20 | # Release Information : Cortex-M0 DesignStart-r1p0-00rel0 21 | # 22 | # ----------------------------------------------------------------------------- 23 | 24 | # ----------------------------------------------------------------------------- 25 | # Abstract: GNU Makefile for reference implementation scripts 26 | # ----------------------------------------------------------------------------- 27 | # 28 | # Notes: 29 | # Ensure appropriate EDA tools are on search path before using make targets 30 | # Refer to supplied documentation for required EDA tools and versions 31 | # 32 | # ----------------------------------------------------------------------------- 33 | 34 | # Dummy target to prevent 'make' without options running other targets: 35 | intro: 36 | @echo "Refer to supplied documentation for reference implementation" 37 | @echo 38 | @echo "Make targets are available for:" 39 | @echo "synthesis, dft" 40 | @echo 41 | @echo "Make targets included combining the above: front" 42 | @echo 43 | 44 | 45 | .PHONY: clean clean_all dist_clean 46 | 47 | ##################################### 48 | # CLEAN # 49 | ##################################### 50 | 51 | clean clean_all dist_clean: 52 | @echo "Cleaning implementation build directory ....." 53 | @/bin/rm -rf work/* 54 | @/bin/rm -rf logs/* 55 | @/bin/rm -rf data/* 56 | @/bin/rm -rf lec/* 57 | @/bin/rm -rf reports/synthesis/* 58 | @/bin/rm -rf reports/dft/* 59 | @/bin/rm -rf reports/lec/* 60 | @/bin/rm -rf reports/*/* # Catch any remaining reports 61 | 62 | ##################################### 63 | # FRONT # 64 | ##################################### 65 | 66 | synthesis: 67 | @mkdir -p work 68 | @mkdir -p logs 69 | @mkdir -p reports 70 | @mkdir -p reports/dft 71 | @mkdir -p reports/lec 72 | @mkdir -p reports/synthesis 73 | @mkdir -p data 74 | cd work; (time dc_shell-xg-t -64bit -topo -f ../scripts/cmsdk_mcu_system_syn.tcl ) 2>&1 | tee ../logs/$@.log 75 | 76 | dft: #dependency is: synthesis 77 | cd work; (time dc_shell-xg-t -64bit -topo -f ../scripts/cmsdk_mcu_system_dft.tcl ) 2>&1 | tee ../logs/$@.log 78 | 79 | ##################################### 80 | # LOGICAL EQUIVALENCE # 81 | ##################################### 82 | 83 | lec_synthesis: #dependency is: synthesis 84 | cd work; (time fm_shell -64bit -x "set netlist cmsdk_mcu_system.synthesis" -overwrite -name_suffix "cmsdk_mcu_system.synthesis" -f ../scripts/cmsdk_mcu_system_fm.tcl ) 2>&1 | tee ../logs/$@.log 85 | cd work; mv formality_cmsdk_mcu_system.synthesis.log ../reports/lec/cmsdk_mcu_system.synthesis.log 86 | 87 | lec_dft: #dependency is: dft 88 | cd work; (time fm_shell -64bit -x "set netlist cmsdk_mcu_system.dft" -overwrite -name_suffix "cmsdk_mcu_system.dft" -f ../scripts/cmsdk_mcu_system_fm.tcl ) 2>&1 | tee ../logs/$@.log 89 | cd work; mv formality_cmsdk_mcu_system.dft.log ../reports/lec/cmsdk_mcu_system.dft.log 90 | 91 | ##################################### 92 | # COMBINED TARGETS # 93 | ##################################### 94 | 95 | front: synthesis dft 96 | analysis: lec_synthesis lec_dft 97 | 98 | all: front analysis 99 | -------------------------------------------------------------------------------- /implementation_tsmc_ce018fg/cortex_m0_mcu_system_synopsys/scripts/cmsdk_mcu_system_clocks.tcl: -------------------------------------------------------------------------------- 1 | #------------------------------------------------------------------------------ 2 | # The confidential and proprietary information contained in this file may 3 | # only be used by a person authorised under and to the extent permitted 4 | # by a subsisting licensing agreement from ARM Limited. 5 | # 6 | # (C) COPYRIGHT 2010-2015 ARM Limited or its affiliates. 7 | # ALL RIGHTS RESERVED 8 | # 9 | # This entire notice must be reproduced on all copies of this file 10 | # and copies of this file may only be made by a person if such person is 11 | # permitted to do so under the terms of a subsisting license agreement 12 | # from ARM Limited. 13 | # 14 | # Version and Release Control Information: 15 | # 16 | # File Revision : $Revision: 275084 $ 17 | # File Date : $Date: 2014-03-27 15:09:11 +0000 (Thu, 27 Mar 2014) $ 18 | # 19 | # Release Information : Cortex-M0 DesignStart-r1p0-00rel0 20 | #------------------------------------------------------------------------------ 21 | # Purpose : Synthesis Script - Clocks 22 | # 23 | # ------------------------------------------------------------------------------ 24 | 25 | # ------------------------------------------------------------------------------ 26 | # Define the clocks in the $rm_project_top 27 | # ------------------------------------------------------------------------------ 28 | 29 | # Declares the clocks present in the design with period, uncertainty and 30 | # latency information for synthesis: 31 | # 32 | # Period - Describes the frequency to be acheieved by synthesis. 33 | # 34 | # Uncertainty - Describes all parameters that could influence the difference 35 | # in clock timing between two related flops. Since jitter is 36 | # explicitly mentioned this will include OCV, skew and margin. 37 | # 38 | # Latency - Describes the delay in the clock tree from the core clock pin 39 | # to the flop clock pin; at this point it is an estimate. 40 | # 41 | foreach clock_name ${common_clock_ports} { 42 | create_clock -name ${clock_name} -period [expr ${clock_period} - ${clock_period_jitter}] [get_ports ${clock_name} ] 43 | set_clock_uncertainty -setup [expr ${setup_margin} + $pre_cts_clock_skew_estimate] [get_clocks ${clock_name} ] 44 | set_clock_uncertainty -hold [expr ${hold_margin} + $pre_cts_clock_skew_estimate] [get_clocks ${clock_name} ] 45 | set_clock_latency -source -fall -early [expr 0.0 - $clock_dutycycle_jitter] [get_clocks ${clock_name} ] 46 | set_clock_latency -source -fall -late [expr 0.0 + $clock_dutycycle_jitter] [get_clocks ${clock_name} ] 47 | set_clock_latency $pre_cts_clock_latency_estimate [get_clocks ${clock_name} ] 48 | 49 | echo "Defined clock $clock_name" 50 | } 51 | 52 | # ------------------------------------------------------------------------------ 53 | # Virtual clocks 54 | # ------------------------------------------------------------------------------ 55 | 56 | create_clock -name VCLK -period [expr ${clock_period} - ${clock_period_jitter}] 57 | set_clock_uncertainty -setup [expr ${setup_margin} + $pre_cts_clock_skew_estimate] [get_clocks {VCLK} ] 58 | set_clock_uncertainty -hold [expr ${hold_margin} + $pre_cts_clock_skew_estimate] [get_clocks {VCLK} ] 59 | set_clock_latency -source -fall -early [expr 0.0 - $clock_dutycycle_jitter] [get_clocks {VCLK} ] 60 | set_clock_latency -source -fall -late [expr 0.0 + $clock_dutycycle_jitter] [get_clocks {VCLK} ] 61 | set_clock_latency $pre_cts_clock_latency_estimate [get_clocks {VCLK} ] 62 | 63 | echo "Defined clock VCLK" 64 | 65 | # ------------------------------------------------------------------------------ 66 | # Debug logic related clock 67 | # ------------------------------------------------------------------------------ 68 | if {${rm_include_dbg} } { 69 | 70 | # Create debug clock 71 | create_clock -name DCLK -period [expr ${clock_period} - ${clock_period_jitter}] [get_ports {DCLK} ] 72 | set_clock_uncertainty -setup [expr ${setup_margin} + $pre_cts_clock_skew_estimate] [get_clocks {DCLK} ] 73 | set_clock_uncertainty -hold [expr ${hold_margin} + $pre_cts_clock_skew_estimate] [get_clocks {DCLK} ] 74 | set_clock_latency -source -fall -early [expr 0.0 - $clock_dutycycle_jitter] [get_clocks {DCLK} ] 75 | set_clock_latency -source -fall -late [expr 0.0 + $clock_dutycycle_jitter] [get_clocks {DCLK} ] 76 | set_clock_latency $pre_cts_clock_latency_estimate [get_clocks {DCLK} ] 77 | echo "Defined clock DCLK" 78 | 79 | # Create JTAG/Serial clock 80 | create_clock -name SWCLKTCK -period [expr (${swclock_period} - ${clock_period_jitter})] [get_ports {SWCLKTCK} ] 81 | set_clock_uncertainty -setup [expr ${setup_margin} + $pre_cts_clock_skew_estimate] [get_clocks {SWCLKTCK} ] 82 | set_clock_uncertainty -hold [expr ${hold_margin} + $pre_cts_clock_skew_estimate] [get_clocks {SWCLKTCK} ] 83 | set_clock_latency -source -fall -early [expr 0.0 - $clock_dutycycle_jitter] [get_clocks {SWCLKTCK} ] 84 | set_clock_latency -source -fall -late [expr 0.0 + $clock_dutycycle_jitter] [get_clocks {SWCLKTCK} ] 85 | set_clock_latency $pre_cts_clock_latency_estimate [get_clocks {SWCLKTCK} ] 86 | echo "Defined clock SWCLKTCK" 87 | 88 | # Create virtual clock for debug interface 89 | create_clock -name SVCLK -period [expr (${swclock_period} - ${clock_period_jitter})] 90 | set_clock_uncertainty -setup [expr ${setup_margin} + $pre_cts_clock_skew_estimate] [get_clocks {SVCLK} ] 91 | set_clock_uncertainty -hold [expr ${hold_margin} + $pre_cts_clock_skew_estimate] [get_clocks {SVCLK} ] 92 | set_clock_latency -source -fall -early [expr 0.0 - $swclock_dutycycle_jitter] [get_clocks {SVCLK} ] 93 | set_clock_latency -source -fall -late [expr 0.0 + $swclock_dutycycle_jitter] [get_clocks {SVCLK} ] 94 | set_clock_latency $pre_cts_clock_latency_estimate [get_clocks {SVCLK} ] 95 | echo "Defined clock SVCLK" 96 | 97 | } 98 | 99 | 100 | # ------------------------------------------------------------------------------ 101 | # End of File 102 | # ------------------------------------------------------------------------------ 103 | -------------------------------------------------------------------------------- /implementation_tsmc_ce018fg/cortex_m0_mcu_system_synopsys/scripts/cmsdk_mcu_system_reports.tcl: -------------------------------------------------------------------------------- 1 | #------------------------------------------------------------------------------ 2 | # The confidential and proprietary information contained in this file may 3 | # only be used by a person authorised under and to the extent permitted 4 | # by a subsisting licensing agreement from ARM Limited. 5 | # 6 | # (C) COPYRIGHT 2010-2015 ARM Limited or its affiliates. 7 | # ALL RIGHTS RESERVED 8 | # 9 | # This entire notice must be reproduced on all copies of this file 10 | # and copies of this file may only be made by a person if such person is 11 | # permitted to do so under the terms of a subsisting license agreement 12 | # from ARM Limited. 13 | # 14 | # Version and Release Control Information: 15 | # 16 | # File Revision : $Revision: 275084 $ 17 | # File Date : $Date: 2014-03-27 15:09:11 +0000 (Thu, 27 Mar 2014) $ 18 | # 19 | # Release Information : Cortex-M0 DesignStart-r1p0-00rel0 20 | #------------------------------------------------------------------------------ 21 | # Purpose : Synthesis Script - Reports 22 | # 23 | # ------------------------------------------------------------------------------ 24 | 25 | # ------------------------------------------------------------------------------ 26 | # Write final reports 27 | # ------------------------------------------------------------------------------ 28 | 29 | printvar > ../reports/synthesis/${rm_project_top}.vars 30 | 31 | check_design -multiple_designs > \ 32 | ../reports/synthesis/${rm_project_top}.check_design 33 | 34 | check_timing > \ 35 | ../reports/synthesis/${rm_project_top}.check_timing 36 | 37 | report_qor > \ 38 | ../reports/synthesis/${rm_project_top}.qor 39 | 40 | report_timing -delay max \ 41 | -max_paths 50 \ 42 | -nosplit \ 43 | -cap \ 44 | -path full_clock_expanded \ 45 | -nets \ 46 | -transition_time \ 47 | -input_pins > \ 48 | ../reports/synthesis/${rm_project_top}.timing-max 49 | 50 | # Create compacted version of the timing report showing only nets 51 | set fr [open ../reports/synthesis/${rm_project_top}.timing-max r] 52 | set fw [open ../reports/synthesis/${rm_project_top}.timing-max-nets w] 53 | 54 | while {[gets $fr line] >= 0} { 55 | if {[regexp {delay} $line] || 56 | [regexp { data } $line] || 57 | [regexp {slack} $line] || 58 | [regexp {\-\-\-\-} $line] || 59 | [regexp {Group} $line] || 60 | [regexp {Startpoint} $line] || 61 | [regexp {Endpoint} $line] || 62 | [regexp {Point} $line] || 63 | [regexp { clock } $line] || 64 | [regexp {(net)} $line] || 65 | [regexp {^ *$} $line] 66 | } { 67 | if {![regexp {/n[0-9]+ } $line]} { 68 | puts $fw $line 69 | } 70 | } 71 | } 72 | 73 | close $fr 74 | close $fw 75 | 76 | report_timing -loops > \ 77 | ../reports/synthesis/${rm_project_top}.loops 78 | 79 | report_area -nosplit \ 80 | -hierarchy \ 81 | -physical > \ 82 | ../reports/synthesis/${rm_project_top}.area 83 | 84 | report_power -nosplit > \ 85 | ../reports/synthesis/${rm_project_top}.power 86 | 87 | report_constraint -all_violators \ 88 | -nosplit > \ 89 | ../reports/synthesis/${rm_project_top}.constraint_violators 90 | 91 | report_design > \ 92 | ../reports/synthesis/${rm_project_top}.design_attributes 93 | 94 | report_clocks -attributes \ 95 | -skew > \ 96 | ../reports/synthesis/${rm_project_top}.clocks 97 | 98 | report_clock_gating -multi_stage \ 99 | -verbose \ 100 | -gated \ 101 | -ungated \ 102 | > ../reports/synthesis/${rm_project_top}.clock_gating 103 | 104 | report_clock_tree -summary \ 105 | -settings \ 106 | -structure > \ 107 | ../reports/synthesis/${rm_project_top}.clock_tree 108 | 109 | query_objects -truncate 0 [all_registers -level_sensitive ] \ 110 | > ../reports/synthesis/${rm_project_top}.latches 111 | 112 | report_isolate_ports -nosplit > \ 113 | ../reports/synthesis/${rm_project_top}.isolate_ports 114 | 115 | report_net_fanout -threshold 32 -nosplit > \ 116 | ../reports/synthesis/${rm_project_top}.high_fanout_nets 117 | 118 | report_port -verbose \ 119 | -nosplit > \ 120 | ../reports/synthesis/${rm_project_top}.port 121 | 122 | report_hierarchy > \ 123 | ../reports/synthesis/${rm_project_top}.hierarchy 124 | 125 | report_resources -hierarchy > \ 126 | ../reports/synthesis/${rm_project_top}.resources 127 | 128 | report_compile_options > \ 129 | ../reports/synthesis/${rm_project_top}.compile_options 130 | 131 | report_congestion > \ 132 | ../reports/synthesis/${rm_project_top}.congestion 133 | 134 | # Zero interconnect delay mode to investigate potential design/floorplan problems 135 | set_zero_interconnect_delay_mode true 136 | report_timing -delay max \ 137 | -max_paths 50 \ 138 | -nosplit \ 139 | -path full_clock_expanded \ 140 | -nets \ 141 | -transition_time \ 142 | -input_pins > \ 143 | ../reports/synthesis/${rm_project_top}_zero-interconnect.timing 144 | 145 | report_qor > \ 146 | ../reports/synthesis/${rm_project_top}_zero-interconnect.qor 147 | set_zero_interconnect_delay_mode false 148 | 149 | 150 | # ------------------------------------------------------------------------------ 151 | # End of File 152 | # ------------------------------------------------------------------------------ 153 | -------------------------------------------------------------------------------- /implementation_tsmc_ce018fg/cortex_m0_mcu_system_synopsys/scripts/design_config.tcl: -------------------------------------------------------------------------------- 1 | #------------------------------------------------------------------------------ 2 | # The confidential and proprietary information contained in this file may 3 | # only be used by a person authorised under and to the extent permitted 4 | # by a subsisting licensing agreement from ARM Limited. 5 | # 6 | # (C) COPYRIGHT 2010-2015 ARM Limited or its affiliates. 7 | # ALL RIGHTS RESERVED 8 | # 9 | # This entire notice must be reproduced on all copies of this file 10 | # and copies of this file may only be made by a person if such person is 11 | # permitted to do so under the terms of a subsisting license agreement 12 | # from ARM Limited. 13 | # 14 | # Version and Release Control Information: 15 | # 16 | # File Revision : $Revision: 275084 $ 17 | # File Date : $Date: 2014-03-27 15:09:11 +0000 (Thu, 27 Mar 2014) $ 18 | # 19 | # Release Information : Cortex-M0 DesignStart-r1p0-00rel0 20 | #------------------------------------------------------------------------------ 21 | # Purpose : Synthesis Script - Configuration 22 | # 23 | # ------------------------------------------------------------------------------ 24 | 25 | # ------------------------------------------------------------------------------ 26 | # THIS FILE DEFINES CONFIGURATION-SPECIFIC DATA 27 | # ------------------------------------------------------------------------------ 28 | 29 | 30 | # Ultimate top-level of design 31 | set rm_project_top cmsdk_mcu_system 32 | 33 | # ------------------------------------------------------------------------------ 34 | # configuration related 35 | # ------------------------------------------------------------------------------ 36 | set rm_include_dbg 0 ;# Set to 0 if Debug Logic is not included in the RTL (parameter DBG = 0) 37 | set rm_include_dma 0 ;# Set to 0 if DMA-230 module is not included in the RTL 38 | set rm_include_f16 0 ;# Set to 1 for 16-bit Flash support (Cortex-M0+ only) 39 | set rm_core_sel CORTEX_M0 ;# Set to CORTEX_M0 or CORTEX_M0PLUS (default support Cortex-M0+) 40 | set rm_design_start 1 ;# Set to 1 if Coretex-M0 DesignStart core is used 41 | 42 | 43 | set rm_include_mtb 0 ;# set 1 to include CoreSight MTB M0+ (Cortex-M0+ only) 44 | set rm_include_iop 0 ;# set 1 to include IO Port GPIO in place of AHB GPIO (Cortex-M0+ only) 45 | 46 | 47 | # ------------------------------------------------------------------------------ 48 | # configuration checking 49 | # ------------------------------------------------------------------------------ 50 | 51 | # Some checks to make sure invalid selections are caught before running the 52 | # synthesis. Do not modify this subsection. 53 | 54 | if {${rm_core_sel} == "CORTEX_M0PLUS"} { 55 | set rm_design_start 0 ;# Set to 0 if using Cortex-M0+ core 56 | } 57 | 58 | if {${rm_core_sel} == "CORTEX_M0"} { 59 | set rm_include_f16 0 ;# Set to 0 if using Cortex-M0 core 60 | set rm_include_mtb 0 ;# Set to 0 if using Cortex-M0 core 61 | set rm_include_iop 0 ;# Set to 0 if using Cortex-M0 core 62 | } 63 | 64 | if {${rm_design_start} } { 65 | set rm_include_dbg 0 ;# Set to 0 if using Cortex-M0 DesignStart core 66 | } 67 | 68 | 69 | # ------------------------------------------------------------------------------ 70 | # Clock and Reset Definitions 71 | # ------------------------------------------------------------------------------ 72 | 73 | set common_clock_ports [list FCLK HCLK SCLK PCLKG PCLK] 74 | set clock_ports ${common_clock_ports} 75 | 76 | set reset_ports [list PORESETn HRESETn PRESETn] 77 | 78 | 79 | if {${rm_include_dbg} } { 80 | set clock_ports [concat ${clock_ports} DCLK] 81 | set clock_ports [concat ${clock_ports} SWCLKTCK ] 82 | set reset_ports [concat ${reset_ports} DBGRESETn] 83 | set reset_ports [concat ${reset_ports} nTRST] 84 | } 85 | 86 | puts $clock_ports 87 | puts $reset_ports 88 | 89 | #------------------------------------------------------------------------------- 90 | # Technology Variables 91 | #------------------------------------------------------------------------------- 92 | # ------------------------------------------------------------------------------ 93 | # DFT Flow Configuration Parameters 94 | # ------------------------------------------------------------------------------ 95 | 96 | set num_scan_chains 3 ;# Number of scan chains to be inserted 97 | 98 | # ------------------------------------------------------------------------------ 99 | # Define DFT Port Names 100 | # ------------------------------------------------------------------------------ 101 | 102 | set scan_data_in DFTSI ;# Name of internal scan data in ports 103 | set scan_data_out DFTSO ;# Name of internal scan data out ports 104 | set scan_enable DFTSE ;# Name of scan shift enable port 105 | if {${rm_core_sel} == "CORTEX_M0PLUS"} { 106 | set dft_const [list DFTRSTDISABLE] ;# Name of test control port 107 | } else { 108 | set dft_const [list RSTBYPASS] ;# Name of test control port 109 | } 110 | 111 | # ------------------------------------------------------------------------------ 112 | # End of File 113 | # ------------------------------------------------------------------------------ 114 | -------------------------------------------------------------------------------- /logical/cmsdk_ahb_default_slave/verilog/cmsdk_ahb_default_slave.v: -------------------------------------------------------------------------------- 1 | //------------------------------------------------------------------------------ 2 | // The confidential and proprietary information contained in this file may 3 | // only be used by a person authorised under and to the extent permitted 4 | // by a subsisting licensing agreement from ARM Limited. 5 | // 6 | // (C) COPYRIGHT 2010-2015 ARM Limited or its affiliates. 7 | // ALL RIGHTS RESERVED 8 | // 9 | // This entire notice must be reproduced on all copies of this file 10 | // and copies of this file may only be made by a person if such person is 11 | // permitted to do so under the terms of a subsisting license agreement 12 | // from ARM Limited. 13 | // 14 | // Version and Release Control Information: 15 | // 16 | // File Revision : $Revision: 275084 $ 17 | // File Date : $Date: 2014-03-27 15:09:11 +0000 (Thu, 27 Mar 2014) $ 18 | // 19 | // Release Information : Cortex-M0 DesignStart-r1p0-00rel0 20 | //------------------------------------------------------------------------------ 21 | // Verilog-2001 (IEEE Std 1364-2001) 22 | //------------------------------------------------------------------------------ 23 | // 24 | //----------------------------------------------------------------------------- 25 | // Abstract : AHB-Lite Default Slave 26 | //----------------------------------------------------------------------------- 27 | // 28 | // Returns an error response when selected for a transfer 29 | // 30 | 31 | module cmsdk_ahb_default_slave ( 32 | // Inputs 33 | input wire HCLK, // Clock 34 | input wire HRESETn, // Reset 35 | input wire HSEL, // Slave select 36 | input wire [1:0] HTRANS, // Transfer type 37 | input wire HREADY, // System ready 38 | 39 | // Outputs 40 | output wire HREADYOUT, // Slave ready 41 | output wire HRESP); // Slave response 42 | 43 | // 44 | // Start of main code 45 | // 46 | 47 | // Internal signals 48 | wire trans_req; // Transfer Request 49 | reg [1:0] resp_state; // Current FSM state for two-cycle error response 50 | wire [1:0] next_state; // Next FSM state 51 | 52 | // Transfer address phase completes 53 | assign trans_req = HSEL & HTRANS[1] & HREADY; 54 | 55 | // Generate next state for the FSM. 56 | // Bit 0 is connected to HREADYOUT and bit 1 is connected to HRESP, 57 | // so the state encodings are: 58 | // 01 - Idle 59 | // 10 - 1st cycle of error response 60 | // 11 - 2nd cycle of error response 61 | assign next_state = { trans_req | (~resp_state[0]), 62 | ~trans_req }; 63 | 64 | // Registering FSM state 65 | always @(posedge HCLK or negedge HRESETn) 66 | if (~HRESETn) 67 | resp_state <= 2'b01; // ensure HREADYOUT is HIGH at reset 68 | else 69 | resp_state <= next_state; 70 | 71 | // Connect to output 72 | assign HREADYOUT = resp_state[0]; 73 | assign HRESP = resp_state[1]; 74 | 75 | `ifdef ARM_AHB_ASSERT_ON 76 | 77 | // ------------------------------------------------------------ 78 | // Assertions 79 | // ------------------------------------------------------------ 80 | `include "std_ovl_defines.h" 81 | reg ovl_last_hreadyout; 82 | reg ovl_last_hsel; 83 | reg [1:0] ovl_last_htrans; 84 | reg ovl_last_hready; 85 | 86 | always @(posedge HCLK or negedge HRESETn) 87 | begin 88 | if (~HRESETn) 89 | begin 90 | ovl_last_hreadyout <= 1'b1; 91 | ovl_last_hsel <= 1'b0; 92 | ovl_last_htrans <= 2'b00; 93 | ovl_last_hready <= 1'b1; 94 | end 95 | else 96 | begin 97 | ovl_last_hreadyout <= HREADYOUT; 98 | ovl_last_hsel <= HSEL; 99 | ovl_last_htrans <= HTRANS; 100 | ovl_last_hready <= HREADY; 101 | end 102 | end 103 | 104 | assert_implication 105 | #(`OVL_ERROR,`OVL_ASSERT, 106 | "If HREADYOUT is 0, HRESP must be high") 107 | u_ovl_error_response_check_1 108 | (.clk(HCLK), .reset_n(HRESETn), 109 | .antecedent_expr(~HREADYOUT), 110 | .consequent_expr(HRESP) 111 | ); 112 | 113 | assert_implication 114 | #(`OVL_ERROR,`OVL_ASSERT, 115 | "If in last cycle HREADYOUT is 0, this cycle both HRESP and HREADYOUT") 116 | u_ovl_error_response_check_2 117 | (.clk(HCLK), .reset_n(HRESETn), 118 | .antecedent_expr(~ovl_last_hreadyout), 119 | .consequent_expr(HRESP & HREADYOUT) 120 | ); 121 | 122 | assert_implication 123 | #(`OVL_ERROR,`OVL_ASSERT, 124 | "If device is not selected, or if transfer is idle/busy, response must be OKAY") 125 | u_ovl_error_fault_check_1 126 | (.clk(HCLK), .reset_n(HRESETn), 127 | .antecedent_expr(~(ovl_last_hsel & ovl_last_htrans[1]) & ovl_last_hready), 128 | .consequent_expr((~HRESP) & HREADYOUT) 129 | ); 130 | 131 | assert_implication 132 | #(`OVL_ERROR,`OVL_ASSERT, 133 | "If device is selected, and if transfer is nseq/seq, response must be ERROR") 134 | u_ovl_error_fault_check_2 135 | (.clk(HCLK), .reset_n(HRESETn), 136 | .antecedent_expr(ovl_last_hsel & ovl_last_htrans[1] & ovl_last_hready), 137 | .consequent_expr(HRESP & (~HREADYOUT)) 138 | ); 139 | 140 | `endif 141 | 142 | endmodule 143 | -------------------------------------------------------------------------------- /logical/cmsdk_ahb_gpio/verilog/cmsdk_ahb_gpio.v: -------------------------------------------------------------------------------- 1 | //------------------------------------------------------------------------------ 2 | // The confidential and proprietary information contained in this file may 3 | // only be used by a person authorised under and to the extent permitted 4 | // by a subsisting licensing agreement from ARM Limited. 5 | // 6 | // (C) COPYRIGHT 2010-2015 ARM Limited or its affiliates. 7 | // ALL RIGHTS RESERVED 8 | // 9 | // This entire notice must be reproduced on all copies of this file 10 | // and copies of this file may only be made by a person if such person is 11 | // permitted to do so under the terms of a subsisting license agreement 12 | // from ARM Limited. 13 | // 14 | // Version and Release Control Information: 15 | // 16 | // File Revision : $Revision: 275084 $ 17 | // File Date : $Date: 2014-03-27 15:09:11 +0000 (Thu, 27 Mar 2014) $ 18 | // 19 | // Release Information : Cortex-M0 DesignStart-r1p0-00rel0 20 | //------------------------------------------------------------------------------ 21 | // Verilog-2001 (IEEE Std 1364-2001) 22 | //------------------------------------------------------------------------------ 23 | 24 | module cmsdk_ahb_gpio 25 | #(// Parameter to define valid bit pattern for Alternate functions 26 | // If an I/O pin does not have alternate function its function mask 27 | // can be set to 0 to reduce gate count. 28 | // 29 | // By default every bit can have alternate function 30 | parameter ALTERNATE_FUNC_MASK = 16'hFFFF, 31 | 32 | // Default alternate function settings 33 | parameter ALTERNATE_FUNC_DEFAULT = 16'h0000, 34 | 35 | // By default use little endian 36 | parameter BE = 0 37 | ) 38 | 39 | // ---------------------------------------------------------------------------- 40 | // Port Definitions 41 | // ---------------------------------------------------------------------------- 42 | (// AHB Inputs 43 | input wire HCLK, // system bus clock 44 | input wire HRESETn, // system bus reset 45 | input wire FCLK, // system bus clock 46 | input wire HSEL, // AHB peripheral select 47 | input wire HREADY, // AHB ready input 48 | input wire [1:0] HTRANS, // AHB transfer type 49 | input wire [2:0] HSIZE, // AHB hsize 50 | input wire HWRITE, // AHB hwrite 51 | input wire [11:0] HADDR, // AHB address bus 52 | input wire [31:0] HWDATA, // AHB write data bus 53 | 54 | input wire [3:0] ECOREVNUM, // Engineering-change-order revision bits 55 | 56 | input wire [15:0] PORTIN, // GPIO Interface input 57 | 58 | // AHB Outputs 59 | output wire HREADYOUT, // AHB ready output to S->M mux 60 | output wire HRESP, // AHB response 61 | output wire [31:0] HRDATA, 62 | 63 | output wire [15:0] PORTOUT, // GPIO output 64 | output wire [15:0] PORTEN, // GPIO output enable 65 | output wire [15:0] PORTFUNC, // Alternate function control 66 | 67 | output wire [15:0] GPIOINT, // Interrupt output for each pin 68 | output wire COMBINT); // Combined interrupt 69 | 70 | // ---------------------------------------------------------------------------- 71 | // Internal wires 72 | // ---------------------------------------------------------------------------- 73 | 74 | wire [31:0] IORDATA; // I/0 read data bus 75 | wire IOSEL; // Decode for peripheral 76 | wire [11:0] IOADDR; // I/O transfer address 77 | wire IOWRITE; // I/O transfer direction 78 | wire [1:0] IOSIZE; // I/O transfer size 79 | wire IOTRANS; // I/O transaction 80 | wire [31:0] IOWDATA; // I/O write data bus 81 | 82 | // ---------------------------------------------------------------------------- 83 | // Block Instantiations 84 | // ---------------------------------------------------------------------------- 85 | // Convert AHB Lite protocol to simple I/O port interface 86 | cmsdk_ahb_to_iop 87 | u_ahb_to_gpio ( 88 | // Inputs 89 | .HCLK (HCLK), 90 | .HRESETn (HRESETn), 91 | .HSEL (HSEL), 92 | .HREADY (HREADY), 93 | .HTRANS (HTRANS), 94 | .HSIZE (HSIZE), 95 | .HWRITE (HWRITE), 96 | .HADDR (HADDR), 97 | .HWDATA (HWDATA), 98 | 99 | .IORDATA (IORDATA), 100 | 101 | // Outputs 102 | .HREADYOUT (HREADYOUT), 103 | .HRESP (HRESP), 104 | .HRDATA (HRDATA), 105 | 106 | .IOSEL (IOSEL), 107 | .IOADDR (IOADDR[11:0]), 108 | .IOWRITE (IOWRITE), 109 | .IOSIZE (IOSIZE), 110 | .IOTRANS (IOTRANS), 111 | .IOWDATA (IOWDATA)); 112 | 113 | // GPIO module with I/O port interface 114 | cmsdk_iop_gpio #( 115 | .ALTERNATE_FUNC_MASK (ALTERNATE_FUNC_MASK), 116 | .ALTERNATE_FUNC_DEFAULT (ALTERNATE_FUNC_DEFAULT), // All pins default to GPIO 117 | .BE (BE)) 118 | u_iop_gpio ( 119 | // Inputs 120 | .HCLK (HCLK), 121 | .HRESETn (HRESETn), 122 | .FCLK (FCLK), 123 | .IOADDR (IOADDR[11:0]), 124 | .IOSEL (IOSEL), 125 | .IOTRANS (IOTRANS), 126 | .IOSIZE (IOSIZE), 127 | .IOWRITE (IOWRITE), 128 | .IOWDATA (IOWDATA), 129 | 130 | // Outputs 131 | .IORDATA (IORDATA), 132 | 133 | .ECOREVNUM (ECOREVNUM),// Engineering-change-order revision bits 134 | 135 | .PORTIN (PORTIN), // GPIO Interface inputs 136 | .PORTOUT (PORTOUT), // GPIO Interface outputs 137 | .PORTEN (PORTEN), 138 | .PORTFUNC (PORTFUNC), // Alternate function control 139 | 140 | .GPIOINT (GPIOINT), // Interrupt outputs 141 | .COMBINT (COMBINT) 142 | ); 143 | 144 | endmodule 145 | -------------------------------------------------------------------------------- /logical/cmsdk_ahb_gpio/verilog/cmsdk_ahb_to_iop.v: -------------------------------------------------------------------------------- 1 | //------------------------------------------------------------------------------ 2 | // The confidential and proprietary information contained in this file may 3 | // only be used by a person authorised under and to the extent permitted 4 | // by a subsisting licensing agreement from ARM Limited. 5 | // 6 | // (C) COPYRIGHT 2010-2015 ARM Limited or its affiliates. 7 | // ALL RIGHTS RESERVED 8 | // 9 | // This entire notice must be reproduced on all copies of this file 10 | // and copies of this file may only be made by a person if such person is 11 | // permitted to do so under the terms of a subsisting license agreement 12 | // from ARM Limited. 13 | // 14 | // Version and Release Control Information: 15 | // 16 | // File Revision : $Revision: 275084 $ 17 | // File Date : $Date: 2014-03-27 15:09:11 +0000 (Thu, 27 Mar 2014) $ 18 | // 19 | // Release Information : Cortex-M0 DesignStart-r1p0-00rel0 20 | //------------------------------------------------------------------------------ 21 | // Verilog-2001 (IEEE Std 1364-2001) 22 | //------------------------------------------------------------------------------ 23 | // 24 | // Simple AHB to IOP Bridge (for use with the IOP GPIO to make an AHB GPIO). 25 | // 26 | //----------------------------------------------------------------------------- 27 | 28 | module cmsdk_ahb_to_iop 29 | // ---------------------------------------------------------------------------- 30 | // Port Definitions 31 | // ---------------------------------------------------------------------------- 32 | (// AHB Inputs 33 | input wire HCLK, // system bus clock 34 | input wire HRESETn, // system bus reset 35 | input wire HSEL, // AHB peripheral select 36 | input wire HREADY, // AHB ready input 37 | input wire [1:0] HTRANS, // AHB transfer type 38 | input wire [2:0] HSIZE, // AHB hsize 39 | input wire HWRITE, // AHB hwrite 40 | input wire [11:0] HADDR, // AHB address bus 41 | input wire [31:0] HWDATA, // AHB write data bus 42 | 43 | // IOP Inputs 44 | input wire [31:0] IORDATA, // I/0 read data bus 45 | 46 | // AHB Outputs 47 | output wire HREADYOUT, // AHB ready output to S->M mux 48 | output wire HRESP, // AHB response 49 | output wire [31:0] HRDATA, 50 | 51 | // IOP Outputs 52 | output reg IOSEL, // Decode for peripheral 53 | output reg [11:0] IOADDR, // I/O transfer address 54 | output reg IOWRITE, // I/O transfer direction 55 | output reg [1:0] IOSIZE, // I/O transfer size 56 | output reg IOTRANS, // I/O transaction 57 | output wire [31:0] IOWDATA); // I/O write data bus 58 | 59 | // ---------------------------------------------------------- 60 | // Read/write control logic 61 | // ---------------------------------------------------------- 62 | 63 | // registered HSEL, update only if selected to reduce toggling 64 | always @(posedge HCLK or negedge HRESETn) 65 | begin 66 | if (~HRESETn) 67 | IOSEL <= 1'b0; 68 | else 69 | IOSEL <= HSEL & HREADY; 70 | end 71 | 72 | // registered address, update only if selected to reduce toggling 73 | always @(posedge HCLK or negedge HRESETn) 74 | begin 75 | if (~HRESETn) 76 | IOADDR <= {12{1'b0}}; 77 | else 78 | IOADDR <= HADDR[11:0]; 79 | end 80 | 81 | // Data phase write control 82 | always @(posedge HCLK or negedge HRESETn) 83 | begin 84 | if (~HRESETn) 85 | IOWRITE <= 1'b0; 86 | else 87 | IOWRITE <= HWRITE; 88 | end 89 | 90 | // registered hsize, update only if selected to reduce toggling 91 | always @(posedge HCLK or negedge HRESETn) 92 | begin 93 | if (~HRESETn) 94 | IOSIZE <= {2{1'b0}}; 95 | else 96 | IOSIZE <= HSIZE[1:0]; 97 | end 98 | 99 | // registered HTRANS, update only if selected to reduce toggling 100 | always @(posedge HCLK or negedge HRESETn) 101 | begin 102 | if (~HRESETn) 103 | IOTRANS <= 1'b0; 104 | else 105 | IOTRANS <= HTRANS[1]; 106 | end 107 | 108 | assign IOWDATA = HWDATA; 109 | assign HRDATA = IORDATA; 110 | assign HREADYOUT = 1'b1; 111 | assign HRESP = 1'b0; 112 | 113 | endmodule 114 | -------------------------------------------------------------------------------- /logical/cmsdk_apb4_eg_slave/verilog/cmsdk_apb4_eg_slave.v: -------------------------------------------------------------------------------- 1 | //------------------------------------------------------------------------------ 2 | // The confidential and proprietary information contained in this file may 3 | // only be used by a person authorised under and to the extent permitted 4 | // by a subsisting licensing agreement from ARM Limited. 5 | // 6 | // (C) COPYRIGHT 2010-2015 ARM Limited or its affiliates. 7 | // ALL RIGHTS RESERVED 8 | // 9 | // This entire notice must be reproduced on all copies of this file 10 | // and copies of this file may only be made by a person if such person is 11 | // permitted to do so under the terms of a subsisting license agreement 12 | // from ARM Limited. 13 | // 14 | // Version and Release Control Information: 15 | // 16 | // File Revision : $Revision: 275084 $ 17 | // File Date : $Date: 2014-03-27 15:09:11 +0000 (Thu, 27 Mar 2014) $ 18 | // 19 | // Release Information : Cortex-M0 DesignStart-r1p0-00rel0 20 | //------------------------------------------------------------------------------ 21 | // Verilog-2001 (IEEE Std 1364-2001) 22 | //------------------------------------------------------------------------------ 23 | // 24 | //----------------------------------------------------------------------------- 25 | // Abstract : APB example slave, support AMBA APB4. 26 | // slave is always ready and response is always OKAY. 27 | //----------------------------------------------------------------------------- 28 | 29 | module cmsdk_apb4_eg_slave #( 30 | // parameter for address width 31 | parameter ADDRWIDTH = 12) 32 | ( 33 | // IO declaration 34 | input wire PCLK, // pclk 35 | input wire PRESETn, // reset 36 | 37 | // apb interface inputs 38 | input wire PSEL, 39 | input wire [ADDRWIDTH-1:0] PADDR, 40 | input wire PENABLE, 41 | input wire PWRITE, 42 | input wire [31:0] PWDATA, 43 | input wire [3:0] PSTRB, 44 | 45 | input wire [3:0] ECOREVNUM, // Engineering-change-order revision bits 46 | 47 | // apb interface outputs 48 | output wire [31:0] PRDATA, 49 | output wire PREADY, 50 | output wire PSLVERR); 51 | 52 | //------------------------------------------------------------------------------ 53 | // internal wires 54 | //------------------------------------------------------------------------------ 55 | // Register module interface signals 56 | wire [ADDRWIDTH-1:0] reg_addr; 57 | wire reg_read_en; 58 | wire reg_write_en; 59 | wire [3:0] reg_byte_strobe; 60 | wire [31:0] reg_wdata; 61 | wire [31:0] reg_rdata; 62 | 63 | 64 | //------------------------------------------------------------------------------ 65 | // module logic start 66 | //------------------------------------------------------------------------------ 67 | // Interface to convert APB signals to simple read and write controls 68 | cmsdk_apb4_eg_slave_interface 69 | #(.ADDRWIDTH (ADDRWIDTH)) 70 | u_apb_eg_slave_interface( 71 | 72 | .pclk (PCLK), // pclk 73 | .presetn (PRESETn), // reset 74 | 75 | .psel (PSEL), // apb interface inputs 76 | .paddr (PADDR), 77 | .penable (PENABLE), 78 | .pwrite (PWRITE), 79 | .pwdata (PWDATA), 80 | .pstrb (PSTRB), 81 | 82 | .prdata (PRDATA), // apb interface outputs 83 | .pready (PREADY), 84 | .pslverr (PSLVERR), 85 | 86 | // Register interface 87 | .addr (reg_addr), 88 | .read_en (reg_read_en), 89 | .write_en (reg_write_en), 90 | .byte_strobe (reg_byte_strobe), 91 | .wdata (reg_wdata), 92 | .rdata (reg_rdata) 93 | 94 | ); 95 | 96 | // Example hardware register block 97 | cmsdk_apb4_eg_slave_reg 98 | #(.ADDRWIDTH (ADDRWIDTH)) 99 | u_apb_eg_slave_reg ( 100 | .pclk (PCLK), 101 | .presetn (PRESETn), 102 | 103 | // Register interface 104 | .addr (reg_addr), 105 | .read_en (reg_read_en), 106 | .write_en (reg_write_en), 107 | .byte_strobe (reg_byte_strobe), 108 | .wdata (reg_wdata), 109 | .ecorevnum (ECOREVNUM), 110 | .rdata (reg_rdata) 111 | ); 112 | 113 | //------------------------------------------------------------------------------ 114 | // module logic end 115 | //------------------------------------------------------------------------------ 116 | 117 | `ifdef ARM_APB_ASSERT_ON 118 | 119 | `include "std_ovl_defines.h" 120 | // ------------------------------------------------------------ 121 | // Assertions 122 | // ------------------------------------------------------------ 123 | 124 | // Check the reg_write_en signal generated 125 | assert_implication 126 | #(`OVL_ERROR, 127 | `OVL_ASSERT, 128 | "Error! register write signal was not generated! " 129 | ) 130 | u_ovl_apb4_eg_slave_reg_write 131 | (.clk (PCLK), 132 | .reset_n (PRESETn), 133 | .antecedent_expr ( (PSEL & (~PENABLE) & PWRITE) ), 134 | .consequent_expr ( reg_write_en == 1'b1) 135 | ); 136 | 137 | 138 | 139 | // Check the reg_read_en signal generated 140 | assert_implication 141 | #(`OVL_ERROR, 142 | `OVL_ASSERT, 143 | "Error! register read signal was not generated! " 144 | ) 145 | u_ovl_apb4_eg_slave_reg_read 146 | (.clk (PCLK), 147 | .reset_n (PRESETn), 148 | .antecedent_expr ( (PSEL & (~PENABLE) & (~PWRITE)) ), 149 | .consequent_expr ( reg_read_en == 1'b1) 150 | ); 151 | 152 | 153 | // Check register read and write operation won't assert at the same cycle 154 | assert_never 155 | #(`OVL_ERROR, 156 | `OVL_ASSERT, 157 | "Error! register read and write active at the same cycle!") 158 | u_ovl_apb4_eg_slave_rd_wr_illegal 159 | (.clk (PCLK), 160 | .reset_n (PRESETn), 161 | .test_expr ((reg_write_en & reg_read_en)) 162 | ); 163 | 164 | 165 | `endif 166 | 167 | 168 | endmodule 169 | -------------------------------------------------------------------------------- /logical/cmsdk_apb4_eg_slave/verilog/cmsdk_apb4_eg_slave_interface.v: -------------------------------------------------------------------------------- 1 | //------------------------------------------------------------------------------ 2 | // The confidential and proprietary information contained in this file may 3 | // only be used by a person authorised under and to the extent permitted 4 | // by a subsisting licensing agreement from ARM Limited. 5 | // 6 | // (C) COPYRIGHT 2010-2015 ARM Limited or its affiliates. 7 | // ALL RIGHTS RESERVED 8 | // 9 | // This entire notice must be reproduced on all copies of this file 10 | // and copies of this file may only be made by a person if such person is 11 | // permitted to do so under the terms of a subsisting license agreement 12 | // from ARM Limited. 13 | // 14 | // Version and Release Control Information: 15 | // 16 | // File Revision : $Revision: 275084 $ 17 | // File Date : $Date: 2014-03-27 15:09:11 +0000 (Thu, 27 Mar 2014) $ 18 | // 19 | // Release Information : Cortex-M0 DesignStart-r1p0-00rel0 20 | //------------------------------------------------------------------------------ 21 | // Verilog-2001 (IEEE Std 1364-2001) 22 | //------------------------------------------------------------------------------ 23 | // 24 | //----------------------------------------------------------------------------- 25 | // Abstract : AMBA APB4 example slave interface module. Transfer APB BUS protocol to 26 | // simple register read write protocol 27 | //----------------------------------------------------------------------------- 28 | module cmsdk_apb4_eg_slave_interface #( 29 | // parameter for address width 30 | parameter ADDRWIDTH = 12) 31 | ( 32 | // IO declaration 33 | 34 | input wire pclk, // pclk 35 | input wire presetn, // reset 36 | 37 | // apb interface inputs 38 | input wire psel, 39 | input wire [ADDRWIDTH-1:0] paddr, 40 | input wire penable, 41 | input wire pwrite, 42 | input wire [31:0] pwdata, 43 | input wire [3:0] pstrb, 44 | 45 | // apb interface outputs 46 | output wire [31:0] prdata, 47 | output wire pready, 48 | output wire pslverr, 49 | 50 | //Register interface 51 | output wire [ADDRWIDTH-1:0] addr, 52 | output wire read_en, 53 | output wire write_en, 54 | output wire [3:0] byte_strobe, 55 | output wire [31:0] wdata, 56 | input wire [31:0] rdata); 57 | 58 | 59 | //------------------------------------------------------------------------------ 60 | // module logic start 61 | //------------------------------------------------------------------------------ 62 | 63 | // APB interface 64 | assign pready = 1'b1; //always ready. Can be customized to support waitstate if required. 65 | assign pslverr = 1'b0; //always OKAY. Can be customized to support error response if required. 66 | 67 | 68 | // register read and write signal 69 | assign addr = paddr; 70 | assign read_en = psel & (~pwrite); // assert for whole apb read transfer 71 | assign write_en = psel & (~penable) & pwrite; // assert for 1st cycle of write transfer 72 | // It is also possible to change the design to perform the write in the 2nd 73 | // APB cycle. E.g. 74 | // assign write_en = psel & penable & pwrite; 75 | // However, if the design generate waitstate, this expression will result 76 | // in write_en being asserted for multiple cycles. 77 | assign byte_strobe = pstrb; 78 | assign wdata = pwdata; 79 | assign prdata = rdata; 80 | 81 | `ifdef ARM_APB_ASSERT_ON 82 | 83 | `include "std_ovl_defines.h" 84 | // ------------------------------------------------------------ 85 | // Assertions 86 | // ------------------------------------------------------------ 87 | 88 | // Check error response should not be generated if not selected 89 | assert_never 90 | #(`OVL_ERROR, 91 | `OVL_ASSERT, 92 | "Error! Should not generate error response if not selected") 93 | u_ovl_apb4_eg_slave_response_illegal 94 | (.clk (pclk), 95 | .reset_n (presetn), 96 | .test_expr (pslverr & pready & (~psel)) 97 | ); 98 | 99 | `endif 100 | //------------------------------------------------------------------------------ 101 | // module logic end 102 | //------------------------------------------------------------------------------ 103 | 104 | endmodule 105 | 106 | 107 | -------------------------------------------------------------------------------- /logical/cmsdk_apb_dualtimers/verilog/cmsdk_apb_dualtimers_defs.v: -------------------------------------------------------------------------------- 1 | //------------------------------------------------------------------------------ 2 | // The confidential and proprietary information contained in this file may 3 | // only be used by a person authorised under and to the extent permitted 4 | // by a subsisting licensing agreement from ARM Limited. 5 | // 6 | // (C) COPYRIGHT 2010-2015 ARM Limited or its affiliates. 7 | // ALL RIGHTS RESERVED 8 | // 9 | // This entire notice must be reproduced on all copies of this file 10 | // and copies of this file may only be made by a person if such person is 11 | // permitted to do so under the terms of a subsisting license agreement 12 | // from ARM Limited. 13 | // 14 | // Version and Release Control Information: 15 | // 16 | // File Revision : $Revision: 275084 $ 17 | // File Date : $Date: 2014-03-27 15:09:11 +0000 (Thu, 27 Mar 2014) $ 18 | // 19 | // Release Information : Cortex-M0 DesignStart-r1p0-00rel0 20 | //------------------------------------------------------------------------------ 21 | // Verilog-2001 (IEEE Std 1364-2001) 22 | //------------------------------------------------------------------------------ 23 | // 24 | //------------------------------------------------------------------------------ 25 | // Abstract : The constants used in the Timers system are defined in this file 26 | //------------------------------------------------------------------------------ 27 | 28 | //------------------------------------------------------------------------------ 29 | // Timer register addresses 30 | //------------------------------------------------------------------------------ 31 | 32 | // Timer base address prefixes 33 | `define ARM_TIMER1A 7'b0000000 34 | `define ARM_TIMER2A 7'b0000001 35 | `define ARM_TIMER3A 7'b0000010 36 | `define ARM_TIMER4A 7'b0000011 37 | 38 | // Integration Test register base address 39 | `define ARM_TIMERIA 7'b1111000 40 | // Peripheral and PrimeCell register base address 41 | `define ARM_TIMERP0A 7'b1111110 42 | `define ARM_TIMERP1A 7'b1111111 43 | 44 | // Integration Test register and ID registers base address 45 | //`define ARM_TIMERIA 4'b1111 46 | 47 | // Register addresses for use by Frcs 48 | `define ARM_TIMERLOADA 3'b000 49 | `define ARM_TIMERVALUEA 3'b001 50 | `define ARM_TIMERCONTROLA 3'b010 51 | `define ARM_TIMERCLEARA 3'b011 52 | `define ARM_TIMERINTRAWA 3'b100 53 | `define ARM_TIMERINTA 3'b101 54 | `define ARM_TIMERLOADBGA 3'b110 55 | 56 | // Peripheral and PrimeCell ID registers addresses 57 | `define ARM_TIMERITCRA 6'b000000 58 | `define ARM_TIMERITOPA 6'b000001 59 | `define ARM_TPERIPHID4A 4'b0100 60 | `define ARM_TPERIPHID5A 4'b0101 61 | `define ARM_TPERIPHID6A 4'b0110 62 | `define ARM_TPERIPHID7A 4'b0111 63 | `define ARM_TPERIPHID0A 4'b1000 64 | `define ARM_TPERIPHID1A 4'b1001 65 | `define ARM_TPERIPHID2A 4'b1010 66 | `define ARM_TPERIPHID3A 4'b1011 67 | `define ARM_TPCELLID0A 4'b1100 68 | `define ARM_TPCELLID1A 4'b1101 69 | `define ARM_TPCELLID2A 4'b1110 70 | `define ARM_TPCELLID3A 4'b1111 71 | 72 | // --========================= End ===========================================-- 73 | -------------------------------------------------------------------------------- /logical/cmsdk_apb_subsystem/verilog/cmsdk_apb_test_slave.v: -------------------------------------------------------------------------------- 1 | //------------------------------------------------------------------------------ 2 | // The confidential and proprietary information contained in this file may 3 | // only be used by a person authorised under and to the extent permitted 4 | // by a subsisting licensing agreement from ARM Limited. 5 | // 6 | // (C) COPYRIGHT 2010-2015 ARM Limited or its affiliates. 7 | // ALL RIGHTS RESERVED 8 | // 9 | // This entire notice must be reproduced on all copies of this file 10 | // and copies of this file may only be made by a person if such person is 11 | // permitted to do so under the terms of a subsisting license agreement 12 | // from ARM Limited. 13 | // 14 | // Version and Release Control Information: 15 | // 16 | // File Revision : $Revision: 275084 $ 17 | // File Date : $Date: 2014-03-27 15:09:11 +0000 (Thu, 27 Mar 2014) $ 18 | // 19 | // Release Information : Cortex-M0 DesignStart-r1p0-00rel0 20 | //------------------------------------------------------------------------------ 21 | // Verilog-2001 (IEEE Std 1364-2001) 22 | //------------------------------------------------------------------------------ 23 | // 24 | //------------------------------------------------------------------------------ 25 | // Abstract : APB test slave for testing of wait state and error response in 26 | // the APB subsystem. For validation purpose only. 27 | //------------------------------------------------------------------------------ 28 | // Programmer's model 29 | // 0x000 R/W Data0[31:0], 0 wait state (2 cycles transfer) 30 | // 0x004 R/W Data0[31:0], 1 wait state (3 cycles transfer) 31 | // 0x008 R/W Data0[31:0], 2 wait states (4 cycles transfer) 32 | // 0x00C R/W Data0[31:0], 3 wait states (5 cycles transfer) 33 | // 34 | // 0x0F0 R/W Data0[31:0], 0 wait state, error response 35 | // 0x0F4 R/W Data0[31:0], 1 wait state, error response 36 | // 0x0F8 R/W Data0[31:0], 2 wait states, error response 37 | // 0x0FC R/W Data0[31:0], 3 wait states, error response 38 | // 39 | // other addresses : read zero, write ignored 40 | // 41 | 42 | module cmsdk_apb_test_slave( 43 | // IO declaration 44 | input wire PCLK, // clock 45 | input wire PRESETn, // reset 46 | 47 | // APB interface inputs 48 | input wire PSEL, 49 | input wire [11:2] PADDR, 50 | input wire PENABLE, 51 | input wire PWRITE, 52 | input wire [31:0] PWDATA, 53 | input wire [3:0] PSTRB, 54 | 55 | // APB interface outputs 56 | output wire [31:0] PRDATA, 57 | output wire PREADY, 58 | output wire PSLVERR); 59 | 60 | //------------------------------------------------------------------------------ 61 | // internal wires 62 | //------------------------------------------------------------------------------ 63 | reg [31:0] reg_data0; // data register 64 | reg [31:0] nxt_data0; 65 | reg [ 1:0] reg_wait_counter; // wait state counter 66 | reg [ 1:0] nxt_wait_counter; 67 | wire [31:0] read_data_mux; 68 | 69 | //------------------------------------------------------------------------------ 70 | // Main code 71 | //------------------------------------------------------------------------------ 72 | // Data register 73 | always @(PSEL or PENABLE or PWRITE or PWDATA or PSTRB or PADDR or 74 | reg_data0) 75 | begin 76 | case (PSEL & PENABLE & PWRITE & ((PADDR[11:4]==8'h00)|(PADDR[11:4]==8'h0F))) 77 | 1'b1: 78 | begin 79 | nxt_data0[ 7: 0] = (PSTRB[0]) ? PWDATA[ 7: 0] : reg_data0[ 7: 0]; 80 | nxt_data0[15: 8] = (PSTRB[1]) ? PWDATA[15: 8] : reg_data0[15: 8]; 81 | nxt_data0[23:16] = (PSTRB[2]) ? PWDATA[23:16] : reg_data0[23:16]; 82 | nxt_data0[31:24] = (PSTRB[3]) ? PWDATA[31:24] : reg_data0[31:24]; 83 | end 84 | 1'b0: 85 | nxt_data0 = reg_data0; 86 | default: 87 | nxt_data0 = {32{1'bx}}; 88 | endcase 89 | end 90 | 91 | // register data register 92 | always @(posedge PCLK or negedge PRESETn) 93 | begin 94 | if (~PRESETn) 95 | reg_data0 <= {32{1'b0}}; 96 | else 97 | reg_data0 <= nxt_data0; 98 | end 99 | 100 | // Read data multiplexer 101 | assign read_data_mux = ((PADDR[11:2] == 10'b0000_0000_00) | 102 | (PADDR[11:2] == 10'b0000_0000_01) | 103 | (PADDR[11:2] == 10'b0000_0000_10) | 104 | (PADDR[11:2] == 10'b0000_0000_11) | 105 | (PADDR[11:2] == 10'b0000_1111_00) | 106 | (PADDR[11:2] == 10'b0000_1111_01) | 107 | (PADDR[11:2] == 10'b0000_1111_10) | 108 | (PADDR[11:2] == 10'b0000_1111_11) ) ? reg_data0 : {32{1'b0}}; 109 | 110 | // Wait counter 111 | always @(PSEL or PENABLE or PADDR or reg_wait_counter) 112 | begin 113 | if (PSEL & (~PENABLE)) // Set counter at first cycle of APB transfer 114 | nxt_wait_counter = PADDR[3:2]; 115 | else if (|reg_wait_counter) // Decrement after 1st cycle 116 | nxt_wait_counter = reg_wait_counter - 2'b01; 117 | else // Idle 118 | nxt_wait_counter = 2'b00; 119 | end 120 | 121 | // register wait counter 122 | always @(posedge PCLK or negedge PRESETn) 123 | begin 124 | if (~PRESETn) 125 | reg_wait_counter <= 2'b00; 126 | else 127 | reg_wait_counter <= nxt_wait_counter; 128 | end 129 | 130 | assign PREADY = (reg_wait_counter==2'b00) ? 1'b1 : 1'b0; 131 | 132 | // Error response 133 | assign PSLVERR = (PSEL & PENABLE & PREADY & (PADDR[11:4]==8'h0F)) ? 1'b1 : 1'b0; 134 | 135 | assign PRDATA = (PSEL & PENABLE & (~PWRITE)) ? read_data_mux : {32{1'b0}}; 136 | 137 | endmodule 138 | -------------------------------------------------------------------------------- /logical/cmsdk_apb_subsystem/verilog/cmsdk_irq_sync.v: -------------------------------------------------------------------------------- 1 | //------------------------------------------------------------------------------ 2 | // The confidential and proprietary information contained in this file may 3 | // only be used by a person authorised under and to the extent permitted 4 | // by a subsisting licensing agreement from ARM Limited. 5 | // 6 | // (C) COPYRIGHT 2010-2015 ARM Limited or its affiliates. 7 | // ALL RIGHTS RESERVED 8 | // 9 | // This entire notice must be reproduced on all copies of this file 10 | // and copies of this file may only be made by a person if such person is 11 | // permitted to do so under the terms of a subsisting license agreement 12 | // from ARM Limited. 13 | // 14 | // Version and Release Control Information: 15 | // 16 | // File Revision : $Revision: 275084 $ 17 | // File Date : $Date: 2014-03-27 15:09:11 +0000 (Thu, 27 Mar 2014) $ 18 | // 19 | // Release Information : Cortex-M0 DesignStart-r1p0-00rel0 20 | //------------------------------------------------------------------------------ 21 | // Verilog-2001 (IEEE Std 1364-2001) 22 | //------------------------------------------------------------------------------ 23 | // 24 | //------------------------------------------------------------------------------ 25 | // Abstract : IRQ synchronizer 26 | //------------------------------------------------------------------------------ 27 | module cmsdk_irq_sync ( 28 | input wire RSTn, 29 | input wire CLK, 30 | input wire IRQIN, 31 | output wire IRQOUT); 32 | 33 | reg [2:0] sync_reg; 34 | wire [2:0] nxt_sync_reg; 35 | 36 | assign nxt_sync_reg = {sync_reg[1:0],IRQIN}; 37 | 38 | always @(posedge CLK or negedge RSTn) 39 | begin 40 | if (~RSTn) 41 | sync_reg <= 3'b000; 42 | else 43 | sync_reg <= nxt_sync_reg; 44 | end 45 | 46 | // Only consider valid if it is high for two cycles 47 | assign IRQOUT = sync_reg[2] & sync_reg[1]; 48 | 49 | 50 | endmodule 51 | -------------------------------------------------------------------------------- /logical/cmsdk_apb_watchdog/verilog/cmsdk_apb_watchdog_defs.v: -------------------------------------------------------------------------------- 1 | //------------------------------------------------------------------------------ 2 | // The confidential and proprietary information contained in this file may 3 | // only be used by a person authorised under and to the extent permitted 4 | // by a subsisting licensing agreement from ARM Limited. 5 | // 6 | // (C) COPYRIGHT 2010-2015 ARM Limited or its affiliates. 7 | // ALL RIGHTS RESERVED 8 | // 9 | // This entire notice must be reproduced on all copies of this file 10 | // and copies of this file may only be made by a person if such person is 11 | // permitted to do so under the terms of a subsisting license agreement 12 | // from ARM Limited. 13 | // 14 | // Version and Release Control Information: 15 | // 16 | // File Revision : $Revision: 275084 $ 17 | // File Date : $Date: 2014-03-27 15:09:11 +0000 (Thu, 27 Mar 2014) $ 18 | // 19 | // Release Information : Cortex-M0 DesignStart-r1p0-00rel0 20 | //------------------------------------------------------------------------------ 21 | // Verilog-2001 (IEEE Std 1364-2001) 22 | //------------------------------------------------------------------------------ 23 | // 24 | //------------------------------------------------------------------------------ 25 | // Abstract : Constants Definitions for APB watchdog timer 26 | //------------------------------------------------------------------------------ 27 | 28 | //------------------------------------------------------------------------------ 29 | // Watchdog register addresses 30 | //------------------------------------------------------------------------------ 31 | 32 | // Watchdog base address prefixes 33 | `define ARM_WDOG1A 7'b0000000 34 | `define ARM_WDOG2A 7'b0000001 35 | 36 | // Lock register base address 37 | `define ARM_WDOGLA 7'b1100000 38 | // Integration Test register base address 39 | `define ARM_WDOGIA 7'b1111000 40 | // Peripheral and PrimeCell register base address 41 | `define ARM_WDOGPA1 7'b1111111 42 | `define ARM_WDOGPA2 7'b1111110 43 | 44 | // Register addresses for use by Frcs 45 | `define ARM_WDOGLOADA 3'b000 46 | `define ARM_WDOGVALUEA 3'b001 47 | `define ARM_WDOGCONTROLA 3'b010 48 | `define ARM_WDOGCLEARA 3'b011 49 | `define ARM_WDOGINTRAWA 3'b100 50 | `define ARM_WDOGINTA 3'b101 51 | 52 | // Watchdog Lock register 53 | `define ARM_WDOGLOCKA 3'b000 54 | 55 | // Integration Test registers 56 | `define ARM_WDOGTCRA 3'b000 57 | `define ARM_WDOGTOPA 3'b001 58 | 59 | // Peripheral and PrimeCell ID registers 60 | `define ARM_WPERIPHID4A 4'b0100 61 | `define ARM_WPERIPHID5A 4'b0101 62 | `define ARM_WPERIPHID6A 4'b0110 63 | `define ARM_WPERIPHID7A 4'b0111 64 | `define ARM_WPERIPHID0A 4'b1000 65 | `define ARM_WPERIPHID1A 4'b1001 66 | `define ARM_WPERIPHID2A 4'b1010 67 | `define ARM_WPERIPHID3A 4'b1011 68 | `define ARM_WPCELLID0A 4'b1100 69 | `define ARM_WPCELLID1A 4'b1101 70 | `define ARM_WPCELLID2A 4'b1110 71 | `define ARM_WPCELLID3A 4'b1111 72 | 73 | // --============================== End ======================================-- 74 | -------------------------------------------------------------------------------- /logical/models/clkgate/cmsdk_clock_gate.v: -------------------------------------------------------------------------------- 1 | //------------------------------------------------------------------------------ 2 | // The confidential and proprietary information contained in this file may 3 | // only be used by a person authorised under and to the extent permitted 4 | // by a subsisting licensing agreement from ARM Limited. 5 | // 6 | // (C) COPYRIGHT 2010-2015 ARM Limited or its affiliates. 7 | // ALL RIGHTS RESERVED 8 | // 9 | // This entire notice must be reproduced on all copies of this file 10 | // and copies of this file may only be made by a person if such person is 11 | // permitted to do so under the terms of a subsisting license agreement 12 | // from ARM Limited. 13 | // 14 | // Version and Release Control Information: 15 | // 16 | // File Revision : $Revision: $ 17 | // File Date : $Date: $ 18 | // 19 | // Release Information : Cortex-M0 DesignStart-r1p0-00rel0 20 | //------------------------------------------------------------------------------ 21 | // Verilog-2001 (IEEE Std 1364-2001) 22 | //------------------------------------------------------------------------------ 23 | // 24 | //----------------------------------------------------------------------------- 25 | // Abstract : Behavioral model of clock gating cell 26 | //----------------------------------------------------------------------------- 27 | 28 | module cmsdk_clock_gate #( 29 | // --------------------------------------------------------------------------- 30 | // Parameters 31 | // --------------------------------------------------------------------------- 32 | parameter CLKGATE_PRESENT = 0) 33 | ( 34 | // --------------------------------------------------------------------------- 35 | // Port Definitions 36 | // --------------------------------------------------------------------------- 37 | 38 | input wire CLK, 39 | input wire CLKENABLE, 40 | input wire DISABLEG, 41 | 42 | output wire GATEDCLK); 43 | 44 | //---------------------------------------------------------------------------- 45 | // Overview 46 | //---------------------------------------------------------------------------- 47 | // 48 | // The mcu_clock_gate block is used to abstract the high level clock gating 49 | // function used for the primary clocks in the macrocell. 50 | // 51 | // A functional clock enable is combined with 52 | // a scanenable/global disable signal to provide the gating term. This is 53 | // then latched prior to gating with the main clock CLK. 54 | // 55 | // A clock gating cell can be instantiated manually by removing the RTL 56 | // equivalent section and instantiating the appropriate cell. 57 | 58 | // --------------------------------------------------------------------------- 59 | // Signal Declarations 60 | // --------------------------------------------------------------------------- 61 | wire i_clk; 62 | wire clk_en; 63 | reg clk_en_t2; 64 | wire i_gated_clk; 65 | wire mst_clk_en; 66 | wire mst_disable; 67 | 68 | //---------------------------------------------------------------------------- 69 | // Clock gate removal - do not alter this section 70 | //---------------------------------------------------------------------------- 71 | assign GATEDCLK = (CLKGATE_PRESENT != 0) ? i_gated_clk : 1'b0; 72 | assign mst_clk_en = (CLKGATE_PRESENT != 0) ? CLKENABLE : 1'b0; 73 | assign mst_disable = (CLKGATE_PRESENT != 0) ? DISABLEG : 1'b0; 74 | assign i_clk = (CLKGATE_PRESENT != 0) ? CLK : 1'b0; 75 | 76 | //---------------------------------------------------------------------------- 77 | // Beginning of main code 78 | //---------------------------------------------------------------------------- 79 | 80 | //---------------------------------------------------------------------------- 81 | // RTL equivalent - remove this section if you wish to use a real cell 82 | //---------------------------------------------------------------------------- 83 | assign clk_en = mst_clk_en | mst_disable; 84 | 85 | always @(i_clk or clk_en) 86 | if (i_clk == 1'b0) 87 | clk_en_t2 <= clk_en; 88 | 89 | assign i_gated_clk = i_clk & clk_en_t2; 90 | 91 | //---------------------------------------------------------------------------- 92 | // Instantiated clock gating cell - instantiate appropriate cell here if 93 | // replacing RTL equivalent section 94 | //---------------------------------------------------------------------------- 95 | // For example: 96 | // TLATNTSCAX12 ICGCell (.ECK (i_gated_clk), .E (mst_clk_en), .SE (mst_disable), .CK (iCLK)); 97 | 98 | endmodule 99 | -------------------------------------------------------------------------------- /logical/models/memories/cmsdk_ahb_memory_models_defs.v: -------------------------------------------------------------------------------- 1 | //------------------------------------------------------------------------------ 2 | // The confidential and proprietary information contained in this file may 3 | // only be used by a person authorised under and to the extent permitted 4 | // by a subsisting licensing agreement from ARM Limited. 5 | // 6 | // (C) COPYRIGHT 2010-2015 ARM Limited or its affiliates. 7 | // ALL RIGHTS RESERVED 8 | // 9 | // This entire notice must be reproduced on all copies of this file 10 | // and copies of this file may only be made by a person if such person is 11 | // permitted to do so under the terms of a subsisting license agreement 12 | // from ARM Limited. 13 | // 14 | // Version and Release Control Information: 15 | // 16 | // File Revision : $Revision: $ 17 | // File Date : $Date: $ 18 | // 19 | // Release Information : Cortex-M0 DesignStart-r1p0-00rel0 20 | //------------------------------------------------------------------------------ 21 | // Verilog-2001 (IEEE Std 1364-2001) 22 | //------------------------------------------------------------------------------ 23 | // 24 | //----------------------------------------------------------------------------- 25 | // Abstract : Memory model definitions 26 | //----------------------------------------------------------------------------- 27 | 28 | //------------------------------------------------------------------------------ 29 | // Memory types 30 | //------------------------------------------------------------------------------ 31 | // Constants for ROM types - Match to cmsdk_ahb_rom.v 32 | // 0) AHB_ROM_NONE - memory not present 33 | // 1) AHB_ROM_BEH_MODEL - behavioral ROM memory 34 | // 2) AHB_ROM_FPGA_SRAM_MODEL - behavioral FPGA SRAM model with SRAM wrapper 35 | // 3) AHB_ROM_FLASH32_MODEL - behavioral 32-bit flash memory 36 | // 4) AHB_ROM_FLASH16_MODEL - behavioral 16-bit flash memory 37 | 38 | `define AHB_ROM_NONE 0 39 | `define AHB_ROM_BEH_MODEL 1 40 | `define AHB_ROM_FPGA_SRAM_MODEL 2 41 | `define AHB_ROM_FLASH32_MODEL 3 42 | `define AHB_ROM_FLASH16_MODEL 4 43 | 44 | 45 | // Constants for RAM types - Match to cmsdk_ahb_ram.v 46 | // 0) AHB_RAM_NONE - memory not present 47 | // 1) AHB_RAM_BEH_MODEL - behavioral RAM memory 48 | // 2) AHB_RAM_FPGA_SRAM_MODEL - behavioral SRAM model with SRAM wrapper 49 | // 3) AHB_RAM_EXT_SRAM16_MODEL - for benchmarking using 16-bit external asynchronous SRAM 50 | // 4) AHB_RAM_EXT_SRAM8_MODEL - for benchmarking using 8-bit external asynchronous SRAM 51 | 52 | `define AHB_RAM_NONE 0 53 | `define AHB_RAM_BEH_MODEL 1 54 | `define AHB_RAM_FPGA_SRAM_MODEL 2 55 | `define AHB_RAM_EXT_SRAM16_MODEL 3 56 | `define AHB_RAM_EXT_SRAM8_MODEL 4 57 | -------------------------------------------------------------------------------- /software/cmsis/Device/ARM/CMSDK_CM0/Include/system_CMSDK_CM0.h: -------------------------------------------------------------------------------- 1 | /**************************************************************************//** 2 | * @file system_CMSDK_CM0.h 3 | * @brief CMSIS Cortex-M0 Device Peripheral Access Layer Header File for 4 | * Device 5 | * @version V3.01 6 | * @date 06. March 2012 7 | * 8 | * @note 9 | * Copyright (C) 2010-2012 ARM Limited. All rights reserved. 10 | * 11 | * @par 12 | * ARM Limited (ARM) is supplying this software for use with Cortex-M 13 | * processor based microcontrollers. This file can be freely distributed 14 | * within development tools that are supporting such ARM based processors. 15 | * 16 | * @par 17 | * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED 18 | * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF 19 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. 20 | * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR 21 | * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. 22 | * 23 | ******************************************************************************/ 24 | 25 | 26 | #ifndef SYSTEM_CMSDK_CM0_H 27 | #define SYSTEM_CMSDK_CM0_H 28 | 29 | #ifdef __cplusplus 30 | extern "C" { 31 | #endif 32 | 33 | #include 34 | 35 | extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ 36 | 37 | 38 | /** 39 | * Initialize the system 40 | * 41 | * @param none 42 | * @return none 43 | * 44 | * @brief Setup the microcontroller system. 45 | * Initialize the System and update the SystemCoreClock variable. 46 | */ 47 | extern void SystemInit (void); 48 | 49 | /** 50 | * Update SystemCoreClock variable 51 | * 52 | * @param none 53 | * @return none 54 | * 55 | * @brief Updates the SystemCoreClock with current core Clock 56 | * retrieved from cpu registers. 57 | */ 58 | extern void SystemCoreClockUpdate (void); 59 | 60 | #ifdef __cplusplus 61 | } 62 | #endif 63 | 64 | #endif /* SYSTEM_CMSDK_CM0_H */ 65 | -------------------------------------------------------------------------------- /software/cmsis/Device/ARM/CMSDK_CM0/Source/system_CMSDK_CM0.c: -------------------------------------------------------------------------------- 1 | /**************************************************************************//** 2 | * @file system_CMSDK_CM0.c 3 | * @brief CMSIS Cortex-M0 Device Peripheral Access Layer Source File for 4 | * Device CMSDK 5 | * @version V3.01 6 | * @date 06. March 2012 7 | * 8 | * @note 9 | * Copyright (C) 2010-2012 ARM Limited or its affiliates. All rights reserved. 10 | * 11 | * @par 12 | * ARM Limited (ARM) is supplying this software for use with Cortex-M 13 | * processor based microcontrollers. This file can be freely distributed 14 | * within development tools that are supporting such ARM based processors. 15 | * 16 | * @par 17 | * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED 18 | * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF 19 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. 20 | * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR 21 | * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. 22 | * 23 | ******************************************************************************/ 24 | 25 | 26 | #include 27 | #include "CMSDK_CM0.h" 28 | 29 | 30 | /*---------------------------------------------------------------------------- 31 | DEFINES 32 | *----------------------------------------------------------------------------*/ 33 | 34 | /*---------------------------------------------------------------------------- 35 | Define clocks 36 | *----------------------------------------------------------------------------*/ 37 | 38 | #define XTAL (100000000UL) /* Oscillator frequency */ 39 | 40 | 41 | /*---------------------------------------------------------------------------- 42 | Clock Variable definitions 43 | *----------------------------------------------------------------------------*/ 44 | uint32_t SystemFrequency = XTAL; /*!< System Clock Frequency (Core Clock) */ 45 | uint32_t SystemCoreClock = XTAL; /*!< Processor Clock Frequency */ 46 | 47 | 48 | /*---------------------------------------------------------------------------- 49 | Clock functions 50 | *----------------------------------------------------------------------------*/ 51 | void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */ 52 | { 53 | SystemCoreClock = XTAL; 54 | } 55 | 56 | /** 57 | * Initialize the system 58 | * 59 | * @param none 60 | * @return none 61 | * 62 | * @brief Setup the microcontroller system. 63 | * Initialize the System. 64 | */ 65 | void SystemInit (void) 66 | { 67 | SystemCoreClock = XTAL; 68 | } 69 | -------------------------------------------------------------------------------- /software/common/bootloader/bootloader.c: -------------------------------------------------------------------------------- 1 | /* 2 | *----------------------------------------------------------------------------- 3 | * The confidential and proprietary information contained in this file may 4 | * only be used by a person authorised under and to the extent permitted 5 | * by a subsisting licensing agreement from ARM Limited. 6 | * 7 | * (C) COPYRIGHT 2010-2015 ARM Limited or its affiliates. 8 | * ALL RIGHTS RESERVED 9 | * 10 | * This entire notice must be reproduced on all copies of this file 11 | * and copies of this file may only be made by a person if such person is 12 | * permitted to do so under the terms of a subsisting license agreement 13 | * from ARM Limited. 14 | * 15 | * SVN Information 16 | * 17 | * Checked In : $Date: 2013-04-08 17:48:08 +0100 (Mon, 08 Apr 2013) $ 18 | * 19 | * Revision : $Revision: 243249 $ 20 | * 21 | * Release Information : Cortex-M0 DesignStart-r1p0-00rel0 22 | *----------------------------------------------------------------------------- 23 | */ 24 | 25 | // 26 | // Simple boot loader 27 | // - display a message that the boot loader is running 28 | // - clear remap control (user flash accessible from address 0x0) 29 | // - execute program from user flash 30 | // 31 | 32 | #include "CMSDK_CM0.h" 33 | 34 | void UartStdOutInit(void) 35 | { 36 | CMSDK_UART2->BAUDDIV = 16; 37 | CMSDK_UART2->CTRL = 0x41; // High speed test mode, TX only 38 | CMSDK_GPIO1->ALTFUNCSET = (1<<5); 39 | return; 40 | } 41 | // Output a character 42 | unsigned char UartPutc(unsigned char my_ch) 43 | { 44 | while ((CMSDK_UART2->STATE & 1)); // Wait if Transmit Holding register is full 45 | CMSDK_UART2->DATA = my_ch; // write to transmit holding register 46 | return (my_ch); 47 | } 48 | // Uart string output 49 | void UartPuts(unsigned char * mytext) 50 | { 51 | unsigned char CurrChar; 52 | do { 53 | CurrChar = *mytext; 54 | if (CurrChar != (char) 0x0) { 55 | UartPutc(CurrChar); // Normal data 56 | } 57 | *mytext++; 58 | } while (CurrChar != 0); 59 | return; 60 | } 61 | #if defined ( __CC_ARM ) 62 | /* ARM RVDS or Keil MDK */ 63 | __asm void FlashLoader_ASM(void) 64 | { 65 | MOVS R0,#0 66 | LDR R1,[R0] ; Get initial MSP value 67 | MOV SP, R1 68 | LDR R1,[R0, #4] ; Get initial PC value 69 | BX R1 70 | } 71 | 72 | #else 73 | /* ARM GCC */ 74 | void FlashLoader_ASM(void) __attribute__((naked)); 75 | void FlashLoader_ASM(void) 76 | { 77 | __asm(" movs r0,#0\n" 78 | " ldr r1,[r0]\n" /* Get initial MSP value */ 79 | " mov sp, r1\n" 80 | " ldr r1,[r0, #4]\n" /* Get initial PC value */ 81 | " bx r1\n"); 82 | } 83 | 84 | #endif 85 | 86 | void FlashLoader(void) 87 | { 88 | if (CMSDK_SYSCON->REMAP==0) { 89 | /* Remap is already cleared. Something has gone wrong. 90 | Likely that the user is trying to run bootloader as a test, 91 | which is not what this program is for. 92 | */ 93 | UartPuts("- Error: REMAP is already clear\n"); 94 | UartPutc(0x4); // Terminate simulation 95 | while (1); 96 | } 97 | CMSDK_SYSCON->REMAP = 0; // Clear remap 98 | __DSB(); 99 | __ISB(); 100 | 101 | FlashLoader_ASM(); 102 | }; 103 | 104 | int main (void) 105 | { 106 | // UART init 107 | UartStdOutInit(); 108 | 109 | UartPuts("\nCMSDK Boot Loader\n"); 110 | UartPuts("- load flash\n"); 111 | FlashLoader(); 112 | return 0; 113 | } 114 | 115 | -------------------------------------------------------------------------------- /software/common/dhry/dhry_2.c: -------------------------------------------------------------------------------- 1 | /* 2 | This is a MODIFIED version of the Dhrystone 2.1 Benchmark program. 3 | 4 | The only changes which have been made are: 5 | 1) the 'old-style' K&R function declarations have been replaced with 6 | 'ANSI-C-style' function declarations (in dhry_1.c and dhry_2,c), and 7 | 2) function prototypes have been added (in dhry.h) 8 | 3) dhry.h uses CLOCKS_PER_SEC instead of CLK_TCK (to build with -strict) 9 | 10 | These changes allow an ANSI-C compiler to produce more efficient code, with 11 | no warnings. 12 | */ 13 | 14 | /* 15 | **************************************************************************** 16 | * 17 | * "DHRYSTONE" Benchmark Program 18 | * ----------------------------- 19 | * 20 | * Version: C, Version 2.1 21 | * 22 | * File: dhry_2.c (part 3 of 3) 23 | * 24 | * Date: May 25, 1988 25 | * 26 | * Author: Reinhold P. Weicker 27 | * 28 | **************************************************************************** 29 | */ 30 | 31 | #ifndef COMBINED 32 | #include "dhry.h" 33 | #endif 34 | 35 | #ifndef REG 36 | #define REG 37 | /* REG becomes defined as empty */ 38 | /* i.e. no register variables */ 39 | #endif 40 | 41 | extern int Int_Glob; 42 | extern char Ch_1_Glob; 43 | 44 | 45 | void Proc_6 (Enumeration Enum_Val_Par, Enumeration *Enum_Ref_Par) 46 | /*********************************/ 47 | /* executed once */ 48 | /* Enum_Val_Par == Ident_3, Enum_Ref_Par becomes Ident_2 */ 49 | { 50 | *Enum_Ref_Par = Enum_Val_Par; 51 | if (! Func_3 (Enum_Val_Par)) 52 | /* then, not executed */ 53 | *Enum_Ref_Par = Ident_4; 54 | switch (Enum_Val_Par) 55 | { 56 | case Ident_1: 57 | *Enum_Ref_Par = Ident_1; 58 | break; 59 | case Ident_2: 60 | if (Int_Glob > 100) 61 | /* then */ 62 | *Enum_Ref_Par = Ident_1; 63 | else *Enum_Ref_Par = Ident_4; 64 | break; 65 | case Ident_3: /* executed */ 66 | *Enum_Ref_Par = Ident_2; 67 | break; 68 | case Ident_4: break; 69 | case Ident_5: 70 | *Enum_Ref_Par = Ident_3; 71 | break; 72 | } /* switch */ 73 | } /* Proc_6 */ 74 | 75 | 76 | void Proc_7 (One_Fifty Int_1_Par_Val, One_Fifty Int_2_Par_Val, One_Fifty *Int_Par_Ref) 77 | /**********************************************/ 78 | /* executed three times */ 79 | /* first call: Int_1_Par_Val == 2, Int_2_Par_Val == 3, */ 80 | /* Int_Par_Ref becomes 7 */ 81 | /* second call: Int_1_Par_Val == 10, Int_2_Par_Val == 5, */ 82 | /* Int_Par_Ref becomes 17 */ 83 | /* third call: Int_1_Par_Val == 6, Int_2_Par_Val == 10, */ 84 | /* Int_Par_Ref becomes 18 */ 85 | { 86 | One_Fifty Int_Loc; 87 | 88 | Int_Loc = Int_1_Par_Val + 2; 89 | *Int_Par_Ref = Int_2_Par_Val + Int_Loc; 90 | } /* Proc_7 */ 91 | 92 | 93 | void Proc_8 (Arr_1_Dim Arr_1_Par_Ref, Arr_2_Dim Arr_2_Par_Ref, int Int_1_Par_Val, int Int_2_Par_Val) 94 | /*********************************************************************/ 95 | /* executed once */ 96 | /* Int_Par_Val_1 == 3 */ 97 | /* Int_Par_Val_2 == 7 */ 98 | { 99 | REG One_Fifty Int_Index; 100 | REG One_Fifty Int_Loc; 101 | 102 | Int_Loc = Int_1_Par_Val + 5; 103 | Arr_1_Par_Ref [Int_Loc] = Int_2_Par_Val; 104 | Arr_1_Par_Ref [Int_Loc+1] = Arr_1_Par_Ref [Int_Loc]; 105 | Arr_1_Par_Ref [Int_Loc+30] = Int_Loc; 106 | for (Int_Index = Int_Loc; Int_Index <= Int_Loc+1; ++Int_Index) 107 | Arr_2_Par_Ref [Int_Loc] [Int_Index] = Int_Loc; 108 | Arr_2_Par_Ref [Int_Loc] [Int_Loc-1] += 1; 109 | Arr_2_Par_Ref [Int_Loc+20] [Int_Loc] = Arr_1_Par_Ref [Int_Loc]; 110 | Int_Glob = 5; 111 | } /* Proc_8 */ 112 | 113 | 114 | Enumeration Func_1 (Capital_Letter Ch_1_Par_Val, Capital_Letter Ch_2_Par_Val) 115 | /*************************************************/ 116 | /* executed three times */ 117 | /* first call: Ch_1_Par_Val == 'H', Ch_2_Par_Val == 'R' */ 118 | /* second call: Ch_1_Par_Val == 'A', Ch_2_Par_Val == 'C' */ 119 | /* third call: Ch_1_Par_Val == 'B', Ch_2_Par_Val == 'C' */ 120 | { 121 | Capital_Letter Ch_1_Loc; 122 | Capital_Letter Ch_2_Loc; 123 | 124 | Ch_1_Loc = Ch_1_Par_Val; 125 | Ch_2_Loc = Ch_1_Loc; 126 | if (Ch_2_Loc != Ch_2_Par_Val) 127 | /* then, executed */ 128 | return (Ident_1); 129 | else /* not executed */ 130 | { 131 | Ch_1_Glob = Ch_1_Loc; 132 | return (Ident_2); 133 | } 134 | } /* Func_1 */ 135 | 136 | 137 | Boolean Func_2 (Str_30 Str_1_Par_Ref, Str_30 Str_2_Par_Ref) 138 | /*************************************************/ 139 | /* executed once */ 140 | /* Str_1_Par_Ref == "DHRYSTONE PROGRAM, 1'ST STRING" */ 141 | /* Str_2_Par_Ref == "DHRYSTONE PROGRAM, 2'ND STRING" */ 142 | { 143 | REG One_Thirty Int_Loc; 144 | Capital_Letter Ch_Loc; 145 | 146 | Int_Loc = 2; 147 | while (Int_Loc <= 2) /* loop body executed once */ 148 | if (Func_1 (Str_1_Par_Ref[Int_Loc], 149 | Str_2_Par_Ref[Int_Loc+1]) == Ident_1) 150 | /* then, executed */ 151 | { 152 | Ch_Loc = 'A'; 153 | Int_Loc += 1; 154 | } /* if, while */ 155 | if (Ch_Loc >= 'W' && Ch_Loc < 'Z') 156 | /* then, not executed */ 157 | Int_Loc = 7; 158 | if (Ch_Loc == 'R') 159 | /* then, not executed */ 160 | return (true); 161 | else /* executed */ 162 | { 163 | if (strcmp (Str_1_Par_Ref, Str_2_Par_Ref) > 0) 164 | /* then, not executed */ 165 | { 166 | Int_Loc += 7; 167 | Int_Glob = Int_Loc; 168 | return (true); 169 | } 170 | else /* executed */ 171 | return (false); 172 | } /* if Ch_Loc */ 173 | } /* Func_2 */ 174 | 175 | 176 | Boolean Func_3 (Enumeration Enum_Par_Val) 177 | /***************************/ 178 | /* executed once */ 179 | /* Enum_Par_Val == Ident_3 */ 180 | { 181 | Enumeration Enum_Loc; 182 | 183 | Enum_Loc = Enum_Par_Val; 184 | if (Enum_Loc == Ident_3) 185 | /* then, executed */ 186 | return (true); 187 | else /* not executed */ 188 | return (false); 189 | } /* Func_3 */ 190 | 191 | -------------------------------------------------------------------------------- /software/common/retarget/retarget.c: -------------------------------------------------------------------------------- 1 | /* 2 | *----------------------------------------------------------------------------- 3 | * The confidential and proprietary information contained in this file may 4 | * only be used by a person authorised under and to the extent permitted 5 | * by a subsisting licensing agreement from ARM Limited. 6 | * 7 | * (C) COPYRIGHT 2010-2015 ARM Limited or its affiliates. 8 | * ALL RIGHTS RESERVED 9 | * 10 | * This entire notice must be reproduced on all copies of this file 11 | * and copies of this file may only be made by a person if such person is 12 | * permitted to do so under the terms of a subsisting license agreement 13 | * from ARM Limited. 14 | * 15 | * SVN Information 16 | * 17 | * Checked In : $Date: 2013-04-10 15:14:20 +0100 (Wed, 10 Apr 2013) $ 18 | * 19 | * Revision : $Revision: 243501 $ 20 | * 21 | * Release Information : Cortex-M0 DesignStart-r1p0-00rel0 22 | *----------------------------------------------------------------------------- 23 | */ 24 | 25 | 26 | #if defined ( __CC_ARM ) 27 | /******************************************************************************/ 28 | /* Retarget functions for ARM DS-5 Professional / Keil MDK */ 29 | /******************************************************************************/ 30 | 31 | #include 32 | #include 33 | #include 34 | #pragma import(__use_no_semihosting_swi) 35 | 36 | extern unsigned char UartGetc(void); 37 | extern unsigned char UartPutc(unsigned char my_ch); 38 | struct __FILE { int handle; /* Add whatever you need here */ }; 39 | FILE __stdout; 40 | FILE __stdin; 41 | 42 | 43 | int fputc(int ch, FILE *f) { 44 | return (UartPutc(ch)); 45 | } 46 | 47 | int fgetc(FILE *f) { 48 | return (UartPutc(UartGetc())); 49 | } 50 | 51 | int ferror(FILE *f) { 52 | /* Your implementation of ferror */ 53 | return EOF; 54 | } 55 | 56 | 57 | void _ttywrch(int ch) { 58 | UartPutc (ch); 59 | } 60 | 61 | 62 | void _sys_exit(int return_code) { 63 | label: goto label; /* endless loop */ 64 | } 65 | 66 | #else 67 | 68 | /******************************************************************************/ 69 | /* Retarget functions for GNU Tools for ARM Embedded Processors */ 70 | /******************************************************************************/ 71 | #include 72 | #include 73 | 74 | extern unsigned char UartPutc(unsigned char my_ch); 75 | 76 | __attribute__ ((used)) int _write (int fd, char *ptr, int len) 77 | { 78 | size_t i; 79 | for (i=0; iBAUDDIV = 16; 35 | CMSDK_UART2->CTRL = 0x41; // High speed test mode, TX only 36 | CMSDK_GPIO1->ALTFUNCSET = (1<<5); 37 | return; 38 | } 39 | // Output a character 40 | unsigned char UartPutc(unsigned char my_ch) 41 | { 42 | while ((CMSDK_UART2->STATE & 1)); // Wait if Transmit Holding register is full 43 | CMSDK_UART2->DATA = my_ch; // write to transmit holding register 44 | return (my_ch); 45 | } 46 | // Get a character 47 | unsigned char UartGetc(void) 48 | { 49 | while ((CMSDK_UART2->STATE & 2)==0); // Wait if Receive Holding register is empty 50 | return (CMSDK_UART2->DATA); 51 | } 52 | 53 | void UartEndSimulation(void) 54 | { 55 | UartPutc((char) 0x4); // End of simulation 56 | while(1); 57 | } 58 | 59 | -------------------------------------------------------------------------------- /software/common/retarget/uart_stdout.h: -------------------------------------------------------------------------------- 1 | /* 2 | *----------------------------------------------------------------------------- 3 | * The confidential and proprietary information contained in this file may 4 | * only be used by a person authorised under and to the extent permitted 5 | * by a subsisting licensing agreement from ARM Limited. 6 | * 7 | * (C) COPYRIGHT 2010-2015 ARM Limited or its affiliates. 8 | * ALL RIGHTS RESERVED 9 | * 10 | * This entire notice must be reproduced on all copies of this file 11 | * and copies of this file may only be made by a person if such person is 12 | * permitted to do so under the terms of a subsisting license agreement 13 | * from ARM Limited. 14 | * 15 | * SVN Information 16 | * 17 | * Checked In : $Date: 2013-04-10 15:14:20 +0100 (Wed, 10 Apr 2013) $ 18 | * 19 | * Revision : $Revision: 243501 $ 20 | * 21 | * Release Information : Cortex-M0 DesignStart-r1p0-00rel0 22 | *----------------------------------------------------------------------------- 23 | */ 24 | /* Functions for stdout during simulation */ 25 | /* The functions are implemented in shared/software/common/uart_stdout.c */ 26 | 27 | extern void UartStdOutInit(void); 28 | extern unsigned char UartPutc(unsigned char my_ch); 29 | extern unsigned char UartGetc(void); 30 | extern unsigned char UartEndSimulation(void); 31 | -------------------------------------------------------------------------------- /software/common/scripts/cmsdk_bootloader.ld: -------------------------------------------------------------------------------- 1 | /* 2 | *----------------------------------------------------------------------------- 3 | * The confidential and proprietary information contained in this file may 4 | * only be used by a person authorised under and to the extent permitted 5 | * by a subsisting licensing agreement from ARM Limited. 6 | * 7 | * (C) COPYRIGHT 2010-2015 ARM Limited or its affiliates. 8 | * ALL RIGHTS RESERVED 9 | * 10 | * This entire notice must be reproduced on all copies of this file 11 | * and copies of this file may only be made by a person if such person is 12 | * permitted to do so under the terms of a subsisting license agreement 13 | * from ARM Limited. 14 | * 15 | * SVN Information 16 | * 17 | * Checked In : $Date: $ 18 | * 19 | * Revision : $Revision: $ 20 | * 21 | * Release Information : Cortex-M0 DesignStart-r1p0-00rel0 22 | *----------------------------------------------------------------------------- 23 | */ 24 | /* Linker script to configure memory regions. 25 | * Need modifying for a specific board. 26 | * FLASH.ORIGIN: starting address of boot loader 27 | * FLASH.LENGTH: length of flash 28 | * RAM.ORIGIN: starting address of RAM bank 0 29 | * RAM.LENGTH: length of RAM bank 0 30 | */ 31 | 32 | INCLUDE "lib-nosys.ld" 33 | 34 | MEMORY 35 | { 36 | FLASH (rx) : ORIGIN = 0x01000000, LENGTH = 0x1000 /* 4K */ 37 | RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x10000 /* 64K */ 38 | } 39 | 40 | INCLUDE "sections.ld" 41 | -------------------------------------------------------------------------------- /software/common/scripts/cmsdk_cm0.ld: -------------------------------------------------------------------------------- 1 | /* 2 | *----------------------------------------------------------------------------- 3 | * The confidential and proprietary information contained in this file may 4 | * only be used by a person authorised under and to the extent permitted 5 | * by a subsisting licensing agreement from ARM Limited. 6 | * 7 | * (C) COPYRIGHT 2010-2015 ARM Limited or its affiliates. 8 | * ALL RIGHTS RESERVED 9 | * 10 | * This entire notice must be reproduced on all copies of this file 11 | * and copies of this file may only be made by a person if such person is 12 | * permitted to do so under the terms of a subsisting license agreement 13 | * from ARM Limited. 14 | * 15 | * SVN Information 16 | * 17 | * Checked In : $Date: $ 18 | * 19 | * Revision : $Revision: $ 20 | * 21 | * Release Information : Cortex-M0 DesignStart-r1p0-00rel0 22 | *----------------------------------------------------------------------------- 23 | */ 24 | /* Linker script to configure memory regions. 25 | * Need modifying for a specific board. 26 | * FLASH.ORIGIN: starting address of flash 27 | * FLASH.LENGTH: length of flash 28 | * RAM.ORIGIN: starting address of RAM bank 0 29 | * RAM.LENGTH: length of RAM bank 0 30 | */ 31 | 32 | INCLUDE "lib-nosys.ld" 33 | 34 | MEMORY 35 | { 36 | FLASH (rx) : ORIGIN = 0x0, LENGTH = 0x10000 /* 64K */ 37 | RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0xFC00 /* 63K */ 38 | /* 64K is available, but reserve some space for */ 39 | /* 1) debug tester communication for debug tests */ 40 | /* 2) DMA data structure for DMA tests */ 41 | } 42 | 43 | INCLUDE "sections.ld" 44 | -------------------------------------------------------------------------------- /software/common/scripts/lib-nosys.ld: -------------------------------------------------------------------------------- 1 | /* 2 | *----------------------------------------------------------------------------- 3 | * The confidential and proprietary information contained in this file may 4 | * only be used by a person authorised under and to the extent permitted 5 | * by a subsisting licensing agreement from ARM Limited. 6 | * 7 | * (C) COPYRIGHT 2010-2015 ARM Limited or its affiliates. 8 | * ALL RIGHTS RESERVED 9 | * 10 | * This entire notice must be reproduced on all copies of this file 11 | * and copies of this file may only be made by a person if such person is 12 | * permitted to do so under the terms of a subsisting license agreement 13 | * from ARM Limited. 14 | * 15 | * SVN Information 16 | * 17 | * Checked In : $Date: $ 18 | * 19 | * Revision : $Revision: $ 20 | * 21 | * Release Information : Cortex-M0 DesignStart-r1p0-00rel0 22 | *----------------------------------------------------------------------------- 23 | */ 24 | 25 | /* Library configurations */ 26 | GROUP(libgcc.a libc.a libm.a libnosys.a) 27 | -------------------------------------------------------------------------------- /software/common/scripts/lib-rdimon.ld: -------------------------------------------------------------------------------- 1 | /* 2 | *----------------------------------------------------------------------------- 3 | * The confidential and proprietary information contained in this file may 4 | * only be used by a person authorised under and to the extent permitted 5 | * by a subsisting licensing agreement from ARM Limited. 6 | * 7 | * (C) COPYRIGHT 2010-2015 ARM Limited or its affiliates. 8 | * ALL RIGHTS RESERVED 9 | * 10 | * This entire notice must be reproduced on all copies of this file 11 | * and copies of this file may only be made by a person if such person is 12 | * permitted to do so under the terms of a subsisting license agreement 13 | * from ARM Limited. 14 | * 15 | * SVN Information 16 | * 17 | * Checked In : $Date: $ 18 | * 19 | * Revision : $Revision: $ 20 | * 21 | * Release Information : Cortex-M0 DesignStart-r1p0-00rel0 22 | *----------------------------------------------------------------------------- 23 | */ 24 | 25 | /* Library configurations */ 26 | GROUP(libgcc.a libc.a libm.a librdimon.a) 27 | -------------------------------------------------------------------------------- /software/common/scripts/sections-nokeep.ld: -------------------------------------------------------------------------------- 1 | /* 2 | *----------------------------------------------------------------------------- 3 | * The confidential and proprietary information contained in this file may 4 | * only be used by a person authorised under and to the extent permitted 5 | * by a subsisting licensing agreement from ARM Limited. 6 | * 7 | * (C) COPYRIGHT 2010-2015 ARM Limited or its affiliates. 8 | * ALL RIGHTS RESERVED 9 | * 10 | * This entire notice must be reproduced on all copies of this file 11 | * and copies of this file may only be made by a person if such person is 12 | * permitted to do so under the terms of a subsisting license agreement 13 | * from ARM Limited. 14 | * 15 | * SVN Information 16 | * 17 | * Checked In : $Date: $ 18 | * 19 | * Revision : $Revision: $ 20 | * 21 | * Release Information : Cortex-M0 DesignStart-r1p0-00rel0 22 | *----------------------------------------------------------------------------- 23 | */ 24 | /* Linker script to place sections and symbol values. Should be used together 25 | * with other linker script that defines memory regions FLASH and RAM. 26 | * It references following symbols, which must be defined in code: 27 | * Reset_Handler : Entry of reset handler 28 | * 29 | * It defines following symbols, which code can use without definition: 30 | * __exidx_start 31 | * __exidx_end 32 | * __etext 33 | * __data_start__ 34 | * __preinit_array_start 35 | * __preinit_array_end 36 | * __init_array_start 37 | * __init_array_end 38 | * __fini_array_start 39 | * __fini_array_end 40 | * __data_end__ 41 | * __bss_start__ 42 | * __bss_end__ 43 | * __end__ 44 | * end 45 | * __HeapLimit 46 | * __StackLimit 47 | * __StackTop 48 | * __stack 49 | */ 50 | ENTRY(Reset_Handler) 51 | 52 | SECTIONS 53 | { 54 | .text : 55 | { 56 | KEEP(*(.isr_vector)) 57 | *(.text*) 58 | 59 | *(.init) 60 | *(.fini) 61 | 62 | /* .ctors */ 63 | *crtbegin.o(.ctors) 64 | *crtbegin?.o(.ctors) 65 | *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) 66 | *(SORT(.ctors.*)) 67 | *(.ctors) 68 | 69 | /* .dtors */ 70 | *crtbegin.o(.dtors) 71 | *crtbegin?.o(.dtors) 72 | *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) 73 | *(SORT(.dtors.*)) 74 | *(.dtors) 75 | 76 | *(.rodata*) 77 | 78 | *(.eh_frame*) 79 | } > FLASH 80 | 81 | .ARM.extab : 82 | { 83 | *(.ARM.extab* .gnu.linkonce.armextab.*) 84 | } > FLASH 85 | 86 | __exidx_start = .; 87 | .ARM.exidx : 88 | { 89 | *(.ARM.exidx* .gnu.linkonce.armexidx.*) 90 | } > FLASH 91 | __exidx_end = .; 92 | 93 | __etext = .; 94 | 95 | .data : AT (__etext) 96 | { 97 | __data_start__ = .; 98 | *(vtable) 99 | *(.data*) 100 | 101 | . = ALIGN(4); 102 | /* preinit data */ 103 | PROVIDE_HIDDEN (__preinit_array_start = .); 104 | *(.preinit_array) 105 | PROVIDE_HIDDEN (__preinit_array_end = .); 106 | 107 | . = ALIGN(4); 108 | /* init data */ 109 | PROVIDE_HIDDEN (__init_array_start = .); 110 | *(SORT(.init_array.*)) 111 | *(.init_array) 112 | PROVIDE_HIDDEN (__init_array_end = .); 113 | 114 | 115 | . = ALIGN(4); 116 | /* finit data */ 117 | PROVIDE_HIDDEN (__fini_array_start = .); 118 | *(SORT(.fini_array.*)) 119 | *(.fini_array) 120 | PROVIDE_HIDDEN (__fini_array_end = .); 121 | 122 | . = ALIGN(4); 123 | /* All data end */ 124 | __data_end__ = .; 125 | 126 | } > RAM 127 | 128 | .bss : 129 | { 130 | . = ALIGN(4); 131 | __bss_start__ = .; 132 | *(.bss*) 133 | *(COMMON) 134 | . = ALIGN(4); 135 | __bss_end__ = .; 136 | } > RAM 137 | 138 | .heap (COPY): 139 | { 140 | __end__ = .; 141 | end = __end__; 142 | *(.heap*) 143 | __HeapLimit = .; 144 | } > RAM 145 | 146 | /* .stack_dummy section doesn't contains any symbols. It is only 147 | * used for linker to calculate size of stack sections, and assign 148 | * values to stack symbols later */ 149 | .stack_dummy (COPY): 150 | { 151 | *(.stack*) 152 | } > RAM 153 | 154 | /* Set stack top to end of RAM, and stack limit move down by 155 | * size of stack_dummy section */ 156 | __StackTop = ORIGIN(RAM) + LENGTH(RAM); 157 | __StackLimit = __StackTop - SIZEOF(.stack_dummy); 158 | PROVIDE(__stack = __StackTop); 159 | 160 | /* Check if data + heap + stack exceeds RAM limit */ 161 | ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") 162 | } 163 | -------------------------------------------------------------------------------- /software/common/scripts/sections.ld: -------------------------------------------------------------------------------- 1 | /* 2 | *----------------------------------------------------------------------------- 3 | * The confidential and proprietary information contained in this file may 4 | * only be used by a person authorised under and to the extent permitted 5 | * by a subsisting licensing agreement from ARM Limited. 6 | * 7 | * (C) COPYRIGHT 2010-2015 ARM Limited or its affiliates. 8 | * ALL RIGHTS RESERVED 9 | * 10 | * This entire notice must be reproduced on all copies of this file 11 | * and copies of this file may only be made by a person if such person is 12 | * permitted to do so under the terms of a subsisting license agreement 13 | * from ARM Limited. 14 | * 15 | * SVN Information 16 | * 17 | * Checked In : $Date: $ 18 | * 19 | * Revision : $Revision: $ 20 | * 21 | * Release Information : Cortex-M0 DesignStart-r1p0-00rel0 22 | *----------------------------------------------------------------------------- 23 | */ 24 | /* Linker script to place sections and symbol values. Should be used together 25 | * with other linker script that defines memory regions FLASH and RAM. 26 | * It references following symbols, which must be defined in code: 27 | * Reset_Handler : Entry of reset handler 28 | * 29 | * It defines following symbols, which code can use without definition: 30 | * __exidx_start 31 | * __exidx_end 32 | * __etext 33 | * __data_start__ 34 | * __preinit_array_start 35 | * __preinit_array_end 36 | * __init_array_start 37 | * __init_array_end 38 | * __fini_array_start 39 | * __fini_array_end 40 | * __data_end__ 41 | * __bss_start__ 42 | * __bss_end__ 43 | * __end__ 44 | * end 45 | * __HeapLimit 46 | * __StackLimit 47 | * __StackTop 48 | * __stack 49 | */ 50 | ENTRY(Reset_Handler) 51 | 52 | SECTIONS 53 | { 54 | .text : 55 | { 56 | KEEP(*(.isr_vector)) 57 | *(.text*) 58 | 59 | KEEP(*(.init)) 60 | KEEP(*(.fini)) 61 | 62 | /* .ctors */ 63 | *crtbegin.o(.ctors) 64 | *crtbegin?.o(.ctors) 65 | *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) 66 | *(SORT(.ctors.*)) 67 | *(.ctors) 68 | 69 | /* .dtors */ 70 | *crtbegin.o(.dtors) 71 | *crtbegin?.o(.dtors) 72 | *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) 73 | *(SORT(.dtors.*)) 74 | *(.dtors) 75 | 76 | *(.rodata*) 77 | 78 | KEEP(*(.eh_frame*)) 79 | } > FLASH 80 | 81 | .ARM.extab : 82 | { 83 | *(.ARM.extab* .gnu.linkonce.armextab.*) 84 | } > FLASH 85 | 86 | __exidx_start = .; 87 | .ARM.exidx : 88 | { 89 | *(.ARM.exidx* .gnu.linkonce.armexidx.*) 90 | } > FLASH 91 | __exidx_end = .; 92 | 93 | __etext = .; 94 | 95 | .data : AT (__etext) 96 | { 97 | __data_start__ = .; 98 | *(vtable) 99 | *(.data*) 100 | 101 | . = ALIGN(4); 102 | /* preinit data */ 103 | PROVIDE_HIDDEN (__preinit_array_start = .); 104 | KEEP(*(.preinit_array)) 105 | PROVIDE_HIDDEN (__preinit_array_end = .); 106 | 107 | . = ALIGN(4); 108 | /* init data */ 109 | PROVIDE_HIDDEN (__init_array_start = .); 110 | KEEP(*(SORT(.init_array.*))) 111 | KEEP(*(.init_array)) 112 | PROVIDE_HIDDEN (__init_array_end = .); 113 | 114 | 115 | . = ALIGN(4); 116 | /* finit data */ 117 | PROVIDE_HIDDEN (__fini_array_start = .); 118 | KEEP(*(SORT(.fini_array.*))) 119 | KEEP(*(.fini_array)) 120 | PROVIDE_HIDDEN (__fini_array_end = .); 121 | 122 | KEEP(*(.jcr*)) 123 | . = ALIGN(4); 124 | /* All data end */ 125 | __data_end__ = .; 126 | 127 | } > RAM 128 | 129 | .bss : 130 | { 131 | . = ALIGN(4); 132 | __bss_start__ = .; 133 | *(.bss*) 134 | *(COMMON) 135 | . = ALIGN(4); 136 | __bss_end__ = .; 137 | } > RAM 138 | 139 | .heap (COPY): 140 | { 141 | __end__ = .; 142 | end = __end__; 143 | *(.heap*) 144 | __HeapLimit = .; 145 | } > RAM 146 | 147 | /* .stack_dummy section doesn't contains any symbols. It is only 148 | * used for linker to calculate size of stack sections, and assign 149 | * values to stack symbols later */ 150 | .stack_dummy (COPY): 151 | { 152 | *(.stack*) 153 | } > RAM 154 | 155 | /* Set stack top to end of RAM, and stack limit move down by 156 | * size of stack_dummy section */ 157 | __StackTop = ORIGIN(RAM) + LENGTH(RAM); 158 | __StackLimit = __StackTop - SIZEOF(.stack_dummy); 159 | PROVIDE(__stack = __StackTop); 160 | 161 | /* Check if data + heap + stack exceeds RAM limit */ 162 | ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") 163 | } 164 | -------------------------------------------------------------------------------- /software/common/validation/default_slaves_tests.c: -------------------------------------------------------------------------------- 1 | /* 2 | *----------------------------------------------------------------------------- 3 | * The confidential and proprietary information contained in this file may 4 | * only be used by a person authorised under and to the extent permitted 5 | * by a subsisting licensing agreement from ARM Limited. 6 | * 7 | * (C) COPYRIGHT 2010-2015 ARM Limited or its affiliates. 8 | * ALL RIGHTS RESERVED 9 | * 10 | * This entire notice must be reproduced on all copies of this file 11 | * and copies of this file may only be made by a person if such person is 12 | * permitted to do so under the terms of a subsisting license agreement 13 | * from ARM Limited. 14 | * 15 | * SVN Information 16 | * 17 | * Checked In : $Date: 2013-04-08 14:40:10 +0100 (Mon, 08 Apr 2013) $ 18 | * 19 | * Revision : $Revision: 243193 $ 20 | * 21 | * Release Information : Cortex-M0 DesignStart-r1p0-00rel0 22 | *----------------------------------------------------------------------------- 23 | */ 24 | 25 | /* 26 | A simple test to check the operation of default slave and the handling of 27 | error response in the AHB interconnection. 28 | */ 29 | #include "CMSDK_CM0.h" 30 | #include 31 | #include "uart_stdout.h" 32 | 33 | #if defined ( __CC_ARM ) 34 | __asm void address_test_write(unsigned int addr, unsigned int wdata); 35 | __asm unsigned int address_test_read(unsigned int addr); 36 | #else 37 | void address_test_write(unsigned int addr, unsigned int wdata); 38 | unsigned int address_test_read(unsigned int addr); 39 | #endif 40 | void HardFault_Handler_c(unsigned int * hardfault_args, unsigned lr_value); 41 | 42 | /* Global variables */ 43 | volatile int hardfault_occurred; 44 | volatile int hardfault_expected; 45 | volatile int temp_data; 46 | 47 | int main (void) 48 | { 49 | int err_code = 0; 50 | int rdata; /* dummy variable for read data in bus fault testing */ 51 | 52 | // UART init 53 | UartStdOutInit(); 54 | 55 | // Test banner message and revision number 56 | puts("\nCortex Microcontroller System Design Kit - Default Slave Test - revision $Revision: 243193 $\n"); 57 | 58 | 59 | puts("Default slave tests - hard faults expected\n"); 60 | temp_data=0; 61 | hardfault_occurred = 0; 62 | hardfault_expected = 1; 63 | address_test_write(0x18000000, 0x3456789A); 64 | if (hardfault_occurred==0) {err_code |= (1<<0);} 65 | hardfault_occurred = 0; 66 | 67 | rdata = address_test_read(0x18000000); 68 | if (hardfault_occurred==0) {err_code |= (1<<1);} 69 | hardfault_occurred = 0; 70 | 71 | address_test_write(0x58000000, 0x3456789A); 72 | if (hardfault_occurred==0) {err_code |= (1<<2);} 73 | hardfault_occurred = 0; 74 | 75 | rdata = address_test_read(0x58000000); 76 | if (hardfault_occurred==0) {err_code |= (1<<3);} 77 | hardfault_occurred = 0; 78 | 79 | puts("\nAPB test slave - hard faults expected\n"); 80 | rdata = address_test_read(0x4000B0F0); 81 | if (hardfault_occurred==0) {err_code |= (1<<4);} 82 | hardfault_occurred = 0; 83 | 84 | rdata = address_test_read(0x4000B0F4); 85 | if (hardfault_occurred==0) {err_code |= (1<<5);} 86 | hardfault_occurred = 0; 87 | 88 | rdata = address_test_read(0x4000B0F8); 89 | if (hardfault_occurred==0) {err_code |= (1<<6);} 90 | hardfault_occurred = 0; 91 | 92 | rdata = address_test_read(0x4000B0FC); 93 | if (hardfault_occurred==0) {err_code |= (1<<7);} 94 | hardfault_occurred = 0; 95 | 96 | /* clean up */ 97 | hardfault_expected = 0; 98 | 99 | /* Generate test pass/fail and return value */ 100 | if (err_code==0) { 101 | printf ("\n** TEST PASSED **\n"); 102 | } else { 103 | printf ("\n** TEST FAILED **, Error code = (0x%x)\n", err_code); 104 | } 105 | UartEndSimulation(); 106 | return 0; 107 | } 108 | 109 | #if defined ( __CC_ARM ) 110 | /* Test function for write - for ARM / Keil */ 111 | __asm void address_test_write(unsigned int addr, unsigned int wdata) 112 | { 113 | STR R1,[R0] 114 | DSB ; Ensure bus fault occurred before leaving this subroutine 115 | BX LR 116 | } 117 | 118 | #else 119 | /* Test function for write - for gcc */ 120 | void address_test_write(unsigned int addr, unsigned int wdata) __attribute__((naked)); 121 | void address_test_write(unsigned int addr, unsigned int wdata) 122 | { 123 | __asm(" str r1,[r0]\n" 124 | " dsb \n" 125 | " bx lr \n" 126 | ); 127 | } 128 | #endif 129 | 130 | /* Test function for read */ 131 | #if defined ( __CC_ARM ) 132 | /* Test function for read - for ARM / Keil */ 133 | __asm unsigned int address_test_read(unsigned int addr) 134 | { 135 | LDR R1,[R0] 136 | DSB ; Ensure bus fault occurred before leaving this subroutine 137 | MOVS R0, R1 138 | BX LR 139 | } 140 | #else 141 | /* Test function for read - for gcc */ 142 | unsigned int address_test_read(unsigned int addr) __attribute__((naked)); 143 | unsigned int address_test_read(unsigned int addr) 144 | { 145 | __asm(" ldr r1,[r0]\n" 146 | " dsb \n" 147 | " movs r0, r1 \n" 148 | " bx lr \n" 149 | ); 150 | } 151 | #endif 152 | 153 | 154 | #if defined ( __CC_ARM ) 155 | /* ARM or Keil toolchain */ 156 | __asm void HardFault_Handler(void) 157 | { 158 | MOVS r0, #4 159 | MOV r1, LR 160 | TST r0, r1 161 | BEQ stacking_used_MSP 162 | MRS R0, PSP ; // first parameter - stacking was using PSP 163 | B get_LR_and_branch 164 | stacking_used_MSP 165 | MRS R0, MSP ; // first parameter - stacking was using MSP 166 | get_LR_and_branch 167 | MOV R1, LR ; // second parameter is LR current value 168 | LDR R2,=__cpp(HardFault_Handler_c) 169 | BX R2 170 | ALIGN 171 | } 172 | #else 173 | /* gcc toolchain */ 174 | void HardFault_Handler(void) __attribute__((naked)); 175 | void HardFault_Handler(void) 176 | { 177 | __asm(" movs r0,#4\n" 178 | " mov r1,lr\n" 179 | " tst r0,r1\n" 180 | " beq stacking_used_MSP\n" 181 | " mrs r0,psp\n" /* first parameter - stacking was using PSP */ 182 | " ldr r1,=HardFault_Handler_c \n" 183 | " bx r1\n" 184 | "stacking_used_MSP:\n" 185 | " mrs r0,msp\n" /* first parameter - stacking was using PSP */ 186 | " ldr r1,=HardFault_Handler_c \n" 187 | " bx r1\n" 188 | ".pool\n" ); 189 | } 190 | 191 | #endif 192 | /* C part of the fault handler - common between ARM / Keil /gcc */ 193 | void HardFault_Handler_c(unsigned int * hardfault_args, unsigned lr_value) 194 | { 195 | unsigned int stacked_pc; 196 | unsigned int stacked_r0; 197 | hardfault_occurred++; 198 | puts ("[Hard Fault Handler]"); 199 | if (hardfault_expected==0) { 200 | puts ("ERROR : Unexpected HardFault interrupt occurred.\n"); 201 | UartEndSimulation(); 202 | while (1); 203 | } 204 | stacked_r0 = ((unsigned long) hardfault_args[0]); 205 | stacked_pc = ((unsigned long) hardfault_args[6]); 206 | printf(" - Stacked R0 : 0x%x\n", stacked_r0); 207 | printf(" - Stacked PC : 0x%x\n", stacked_pc); 208 | /* Modify R0 to a valid address */ 209 | hardfault_args[0] = (unsigned long) &temp_data; 210 | 211 | return; 212 | } 213 | 214 | -------------------------------------------------------------------------------- /systems/cortex_m0_mcu/rtl_sim/scripts/check_tests.pl: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | #!perl -w 3 | # call perl from PATH 4 | eval 'exec perl -x -S $0 ${1+"$@"}' 5 | if 0; 6 | 7 | ################################################################################# 8 | # 9 | # The confidential and proprietary information contained in this file may 10 | # only be used by a person authorised under and to the extent permitted 11 | # by a subsisting licensing agreement from ARM Limited. 12 | # 13 | # (C) COPYRIGHT 2011-2014 ARM Limited or its affiliates. 14 | # ALL RIGHTS RESERVED 15 | # 16 | # This entire notice must be reproduced on all copies of this file 17 | # and copies of this file may only be made by a person if such person is 18 | # permitted to do so under the terms of a subsisting license agreement 19 | # from ARM Limited. 20 | # 21 | # M0 Design Start Check tests Script 22 | # ================================== 23 | # 24 | # SVN Information 25 | # 26 | # Checked In : $Date: 2012-08-31 12:34:14 +0100 (Fri, 31 Aug 2012) $ 27 | # 28 | # Revision : $Revision: 220755 $ 29 | # 30 | # Release Information : Cortex-M7 AT590-r0p0-00rel0 31 | # 32 | ################################################################################ 33 | # Script Usage: check_tests.pl 34 | ################################################################################ 35 | 36 | use strict; 37 | use warnings; 38 | use Getopt::Long; 39 | 40 | my $dir = 'logs'; 41 | my $testlog = ""; 42 | my $testname = ""; 43 | my %teststatus; 44 | my $test_pass_fail_skip = ""; 45 | my $test_count = 0; 46 | my $pass_count = 0; 47 | my $fail_count = 0; 48 | my $kill_count = 0; 49 | my $skip_count = 0; 50 | my $time = 0; 51 | my $exec_time = 0; 52 | 53 | # Prototype subroutines 54 | sub count_logs(); 55 | 56 | $dir = "logs"; 57 | if ( -d $dir ) { 58 | count_logs(); 59 | } 60 | 61 | sub count_logs() 62 | { 63 | opendir(DIR, $dir) or die $!; 64 | while (my $file = readdir(DIR)) { 65 | # Use a regular expression to ignore files beginning with a period 66 | next if ($file =~ m/^\./); 67 | if (($file =~ /.log/) & ($file !~ /compile.log/) & ($file !~ /tarmac/)) { 68 | $testlog = $dir . "/" . $file; 69 | open LOGFILE, $testlog or die "Error opening log file"; 70 | $test_count++; 71 | 72 | $testname = $file; 73 | $testname =~ s/.log//; 74 | $testname =~ s/run_//; 75 | $time = 0; 76 | $test_pass_fail_skip = "KILL"; 77 | 78 | while (my $log_row = ) { 79 | if ($log_row =~ /# Time:/) { 80 | # Record execution time 81 | ($time) = $log_row =~ /(\d+)/; 82 | } 83 | 84 | if ($log_row =~ /UART: \*\* TEST FAILED \*\*/) { 85 | $test_pass_fail_skip = "FAIL"; 86 | $fail_count++; 87 | } 88 | if ($log_row =~ /UART: \*\* TEST PASSED \*\*/) { 89 | $test_pass_fail_skip = "PASS"; 90 | $pass_count++; 91 | } 92 | if ($log_row =~ /UART: \*\* TEST SKIPPED \*\*/) { 93 | $test_pass_fail_skip = "SKIP"; 94 | $skip_count++; 95 | } 96 | 97 | } #while loop through log file lines 98 | 99 | $exec_time = $exec_time + $time; 100 | print "$test_pass_fail_skip $testname\n"; 101 | 102 | close LOGFILE; 103 | } 104 | } #while loop through log files 105 | $kill_count = $test_count - $pass_count - $fail_count - $skip_count; 106 | print "\n"; 107 | print "Count: $test_count\n"; 108 | print "Passes: $pass_count, Fails: $fail_count, Kills: $kill_count, Skips: $skip_count\n"; 109 | print "Time: $exec_time\n"; 110 | closedir(DIR); 111 | } #end sub count_logs 112 | 113 | -------------------------------------------------------------------------------- /systems/cortex_m0_mcu/testcodes/bootloader/bootloader_cm0.uvopt: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 1.0 5 | 6 |
### uVision Project, (C) Keil Software
7 | 8 | 9 | *.c 10 | *.s*; *.src; *.a* 11 | *.obj 12 | *.lib 13 | *.txt; *.h; *.inc 14 | *.plm 15 | *.cpp 16 | 17 | 18 | 19 | 0 20 | 0 21 | 22 | 23 | 24 | Debug 25 | 0x4 26 | ARM-ADS 27 | 28 | 50000000 29 | 30 | 1 31 | 1 32 | 1 33 | 0 34 | 35 | 36 | 1 37 | 65535 38 | 0 39 | 0 40 | 0 41 | 42 | 43 | 79 44 | 66 45 | 8 46 | .\ 47 | 48 | 49 | 1 50 | 1 51 | 1 52 | 0 53 | 1 54 | 1 55 | 0 56 | 1 57 | 0 58 | 0 59 | 0 60 | 0 61 | 62 | 63 | 1 64 | 1 65 | 1 66 | 1 67 | 1 68 | 1 69 | 1 70 | 0 71 | 0 72 | 73 | 74 | 1 75 | 0 76 | 1 77 | 78 | 255 79 | 80 | SARMCM3.DLL 81 | 82 | DARMCM1.DLL 83 | 84 | SARMCM3.DLL 85 | 86 | TARMCM1.DLL 87 | 88 | 89 | 90 | 1 91 | 0 92 | 1 93 | 1 94 | 1 95 | 1 96 | 1 97 | 1 98 | 1 99 | 1 100 | 0 101 | 1 102 | 1 103 | 1 104 | 0 105 | 1 106 | 0 107 | 0 108 | 0 109 | -1 110 | 111 | 112 | 113 | 114 | 115 | 116 | 117 | 118 | 119 | 120 | 121 | 122 | 123 | 124 | 0 125 | 1 126 | 0 127 | 0 128 | 0 129 | 0 130 | 0 131 | 0 132 | 0 133 | 0 134 | 0 135 | 0 136 | 0 137 | 0 138 | 0 139 | 0 140 | 0 141 | 0 142 | 0 143 | 0 144 | 0 145 | 0 146 | 0 147 | 0 148 | 149 | 150 | 0 151 | 152 | 153 | 154 | 155 | 156 | 157 | 158 | Startup 159 | 1 160 | 0 161 | 0 162 | 0 163 | 164 | 1 165 | 1 166 | 2 167 | 0 168 | 0 169 | 0 170 | 0 171 | 0 172 | 0 173 | 0 174 | ..\..\..\..\software\cmsis\Device\ARM\CMSDK_CM0\Source\ARM\startup_CMSDK_CM0.s 175 | startup_CMSDK_CM0.s 176 | 0 177 | 0 178 | 179 | 180 | 181 | 182 | Application 183 | 1 184 | 0 185 | 0 186 | 0 187 | 188 | 2 189 | 2 190 | 1 191 | 0 192 | 0 193 | 0 194 | 0 195 | 0 196 | 0 197 | 0 198 | ..\..\..\..\software\common\bootloader\bootloader.c 199 | bootloader.c 200 | 0 201 | 0 202 | 203 | 204 | 205 | 206 | System 207 | 1 208 | 0 209 | 0 210 | 0 211 | 212 | 3 213 | 3 214 | 1 215 | 0 216 | 0 217 | 0 218 | 0 219 | 0 220 | 0 221 | 0 222 | ..\..\..\..\software\cmsis\Device\ARM\CMSDK_CM0\Source\system_CMSDK_CM0.c 223 | system_CMSDK_CM0.c 224 | 0 225 | 0 226 | 227 | 228 | 229 | 230 | -------------------------------------------------------------------------------- /systems/cortex_m0_mcu/testcodes/bootloader/makefile: -------------------------------------------------------------------------------- 1 | #----------------------------------------------------------------------------- 2 | # The confidential and proprietary information contained in this file may 3 | # only be used by a person authorised under and to the extent permitted 4 | # by a subsisting licensing agreement from ARM Limited. 5 | # 6 | # (C) COPYRIGHT 2010-2015 ARM Limited or its affiliates. 7 | # ALL RIGHTS RESERVED 8 | # 9 | # This entire notice must be reproduced on all copies of this file 10 | # and copies of this file may only be made by a person if such person is 11 | # permitted to do so under the terms of a subsisting license agreement 12 | # from ARM Limited. 13 | # 14 | # SVN Information 15 | # 16 | # Checked In : $Date: 2013-04-03 15:03:02 +0100 (Wed, 03 Apr 2013) $ 17 | # 18 | # Revision : $Revision: 242778 $ 19 | # 20 | # Release Information : Cortex-M0 DesignStart-r1p0-00rel0 21 | #----------------------------------------------------------------------------- 22 | # 23 | # Cortex-M System Design Kit software compilation make file 24 | # 25 | #----------------------------------------------------------------------------- 26 | # 27 | # Configurations 28 | # 29 | CPU_PRODUCT = CORTEX_M0 30 | 31 | # Shared software directory 32 | SOFTWARE_DIR = ../../../../software 33 | CMSIS_DIR = $(SOFTWARE_DIR)/cmsis 34 | CORE_DIR = $(CMSIS_DIR)/CMSIS/Include 35 | 36 | DEVICE_DIR = $(CMSIS_DIR)/Device/ARM/CMSDK_CM0 37 | 38 | # Program file 39 | BOOTLOADER = bootloader 40 | 41 | # Endian Option 42 | COMPILE_BIGEND = 0 43 | 44 | # Configuration 45 | USER_DEFINE = -DCORTEX_M0 46 | 47 | DEPS_LIST = makefile 48 | 49 | # Tool chain : ds5 / gcc / keil 50 | TOOL_CHAIN = ds5 51 | 52 | ifeq ($(TOOL_CHAIN),ds5) 53 | CPU_TYPE = --cpu Cortex-M0 54 | endif 55 | 56 | ifeq ($(TOOL_CHAIN),gcc) 57 | CPU_TYPE = -mcpu=cortex-m0 58 | endif 59 | 60 | 61 | # Startup code directory for DS-5 62 | ifeq ($(TOOL_CHAIN),ds5) 63 | STARTUP_DIR = $(DEVICE_DIR)/Source/ARM 64 | endif 65 | 66 | # Startup code directory for gcc 67 | ifeq ($(TOOL_CHAIN),gcc) 68 | STARTUP_DIR = $(DEVICE_DIR)/Source/GCC 69 | endif 70 | 71 | STARTUP_FILE = startup_CMSDK_CM0 72 | SYSTEM_FILE = system_CMSDK_CM0 73 | 74 | # --------------------------------------------------------------------------------------- 75 | # DS-5 options 76 | 77 | # MicroLIB option 78 | COMPILE_MICROLIB = 0 79 | 80 | # Small Multiply (Cortex-M0/M0+ has small multiplier option) 81 | COMPILE_SMALLMUL = 0 82 | 83 | ARM_CC_OPTIONS = -c -O3 -g -Otime -I $(DEVICE_DIR)/Include -I $(CORE_DIR) $(USER_DEFINE) 84 | ARM_ASM_OPTIONS = -g 85 | ARM_LINK_OPTIONS = "--keep=$(STARTUP_FILE).o(RESET)" "--first=$(STARTUP_FILE).o(RESET)" \ 86 | --rw_base 0x20000000 --ro_base 0x01000000 --map 87 | 88 | ifeq ($(COMPILE_BIGEND),1) 89 | # Big Endian 90 | ARM_CC_OPTIONS += --bigend 91 | ARM_ASM_OPTIONS += --bigend 92 | ARM_LINK_OPTIONS += --be8 93 | endif 94 | 95 | ifeq ($(COMPILE_MICROLIB),1) 96 | # MicroLIB 97 | ARM_CC_OPTIONS += --library_type=microlib 98 | ARM_ASM_OPTIONS += --library_type=microlib --pd "__MICROLIB SETA 1" 99 | ARM_LINK_OPTIONS += --library_type=microlib 100 | endif 101 | 102 | ifeq ($(COMPILE_SMALLMUL),1) 103 | # In Cortex-M0, small multiply takes 32 cycles 104 | ARM_CC_OPTIONS += --multiply_latency=32 105 | endif 106 | 107 | # --------------------------------------------------------------------------------------- 108 | # gcc options 109 | 110 | GNG_CC = arm-none-eabi-gcc 111 | GNU_OBJDUMP = arm-none-eabi-objdump 112 | GNU_OBJCOPY = arm-none-eabi-objcopy 113 | 114 | LINKER_SCRIPT_PATH = $(SOFTWARE_DIR)/common/scripts 115 | LINKER_SCRIPT = $(LINKER_SCRIPT_PATH)/cmsdk_bootloader.ld 116 | 117 | GNU_CC_FLAGS = -g -O3 -mthumb $(CPU_TYPE) 118 | 119 | ifeq ($(COMPILE_BIGEND),1) 120 | # Big Endian 121 | GNU_CC_FLAGS += -mbig-endian 122 | endif 123 | # --------------------------------------------------------------------------------------- 124 | all: all_$(TOOL_CHAIN) 125 | 126 | # --------------------------------------------------------------------------------------- 127 | # DS-5 128 | all_ds5 : $(BOOTLOADER).hex $(BOOTLOADER).lst 129 | 130 | $(BOOTLOADER).o : $(SOFTWARE_DIR)/common/bootloader/$(BOOTLOADER).c $(DEPS_LIST) 131 | armcc $(ARM_CC_OPTIONS) $(CPU_TYPE) $< -o $@ 132 | 133 | $(SYSTEM_FILE).o : $(DEVICE_DIR)/Source/$(SYSTEM_FILE).c $(DEPS_LIST) 134 | armcc $(ARM_CC_OPTIONS) $(CPU_TYPE) $< -o $@ 135 | 136 | $(STARTUP_FILE).o : $(STARTUP_DIR)/$(STARTUP_FILE).s $(DEPS_LIST) 137 | armasm $(ARM_ASM_OPTIONS) $(CPU_TYPE) $< -o $@ 138 | 139 | $(BOOTLOADER).ELF : $(BOOTLOADER).o $(SYSTEM_FILE).o $(STARTUP_FILE).o $(DEPS_LIST) 140 | armlink $(ARM_LINK_OPTIONS) $(BOOTLOADER).o $(SYSTEM_FILE).o $(STARTUP_FILE).o -o $@ 141 | 142 | $(BOOTLOADER).hex : $(BOOTLOADER).ELF $(DEPS_LIST) 143 | fromelf --vhx --8x1 $< --output $@ 144 | 145 | $(BOOTLOADER).lst : $(BOOTLOADER).ELF $(DEPS_LIST) 146 | fromelf -c -d -e -s $< --output $@ 147 | 148 | # --------------------------------------------------------------------------------------- 149 | # gcc 150 | 151 | all_gcc: 152 | $(GNG_CC) $(GNU_CC_FLAGS) $(STARTUP_DIR)/$(STARTUP_FILE).s \ 153 | $(SOFTWARE_DIR)/common/bootloader/$(BOOTLOADER).c \ 154 | $(DEVICE_DIR)/Source/$(SYSTEM_FILE).c \ 155 | -I $(DEVICE_DIR)/Include -I $(CORE_DIR) \ 156 | -L $(LINKER_SCRIPT_PATH) \ 157 | -D__STACK_SIZE=0x200 \ 158 | -D__HEAP_SIZE=0x1000 \ 159 | $(USER_DEFINE) -T $(LINKER_SCRIPT) -o $(BOOTLOADER).o 160 | # Generate disassembly code 161 | $(GNU_OBJDUMP) -S $(BOOTLOADER).o > $(BOOTLOADER).lst 162 | # Generate binary file 163 | $(GNU_OBJCOPY) -S $(BOOTLOADER).o -O binary $(BOOTLOADER).bin 164 | # Generate hex file 165 | $(GNU_OBJCOPY) -S $(BOOTLOADER).o --adjust-vma -0x01000000 -O verilog $(BOOTLOADER).hex 166 | 167 | # Note: 168 | # Objcopy use --adjust-vma so that the Verilog hex address start at address 0 instead of actual address 0x01000000 169 | # 170 | # If the version of object copy you are using does not support verilog hex file output, 171 | # you can generate the hex file from binary file using the following command 172 | # od -v -A n -t x1 --width=1 $(TESTNAME).bin > $(TESTNAME).hex 173 | 174 | 175 | # --------------------------------------------------------------------------------------- 176 | # Keil MDK 177 | 178 | all_keil: 179 | @echo "Please compile your project code and press ENTER when ready" 180 | @read dummy 181 | 182 | # --------------------------------------------------------------------------------------- 183 | # Binary 184 | 185 | all_bin: $(BOOTLOADER).bin 186 | # Generate hex file from binary 187 | od -v -A n -t x1 --width=1 $(BOOTLOADER).bin > $(BOOTLOADER).hex 188 | 189 | # --------------------------------------------------------------------------------------- 190 | # Clean 191 | clean : 192 | @rm -rf *.o 193 | @if [ -e $(BOOTLOADER).hex ] ; then \ 194 | rm -rf $(BOOTLOADER).hex ; \ 195 | fi 196 | @if [ -e $(BOOTLOADER).lst ] ; then \ 197 | rm -rf $(BOOTLOADER).lst ; \ 198 | fi 199 | @if [ -e $(BOOTLOADER).ELF ] ; then \ 200 | rm -rf $(BOOTLOADER).ELF ; \ 201 | fi 202 | @if [ -e $(BOOTLOADER).bin ] ; then \ 203 | rm -rf $(BOOTLOADER).bin ; \ 204 | fi 205 | @rm -rf *.crf 206 | @rm -rf *.plg 207 | @rm -rf *.tra 208 | @rm -rf *.htm 209 | @rm -rf *.map 210 | @rm -rf *.dep 211 | @rm -rf *.d 212 | @rm -rf *.lnp 213 | @rm -rf *.bak 214 | @rm -rf *.lst 215 | @rm -rf *.axf 216 | @rm -rf *.sct 217 | @rm -rf *.__i 218 | @rm -rf *._ia 219 | 220 | -------------------------------------------------------------------------------- /systems/cortex_m0_mcu/testcodes/generic/mcu_debugtester_interface.c: -------------------------------------------------------------------------------- 1 | /* 2 | *----------------------------------------------------------------------------- 3 | * The confidential and proprietary information contained in this file may 4 | * only be used by a person authorised under and to the extent permitted 5 | * by a subsisting licensing agreement from ARM Limited. 6 | * 7 | * (C) COPYRIGHT 2010-2015 ARM Limited or its affiliates. 8 | * ALL RIGHTS RESERVED 9 | * 10 | * This entire notice must be reproduced on all copies of this file 11 | * and copies of this file may only be made by a person if such person is 12 | * permitted to do so under the terms of a subsisting license agreement 13 | * from ARM Limited. 14 | * 15 | * SVN Information 16 | * 17 | * Checked In : $Date: $ 18 | * 19 | * Revision : $Revision: $ 20 | * 21 | * Release Information : Cortex-M0 DesignStart-r1p0-00rel0 22 | *----------------------------------------------------------------------------- 23 | */ 24 | 25 | #include "mcu_debugtester_interface.h" // For definition of interface to the debug tester 26 | 27 | void EnableDebugTester(void) 28 | { 29 | uint32_t i; 30 | 31 | 32 | // 33 | // Initialise GPIO from MCU to Debug Tester 34 | // 35 | 36 | //Initialize the GPIO0 higher 8 bits output value, set to 0 37 | CMSDK_GPIO0->DATAOUT = (0x00000000); //set GPIO output to 0 for default value, disable the function strobe 38 | CMSDK_gpio_SetOutEnable (CMSDK_GPIO0, DEBUG_CMD); // set specified bit in out enable register 39 | 40 | 41 | // 42 | // Enable the Debug Tester in the testbench 43 | // 44 | 45 | // send command to enable the connection to debug tester 46 | UartPutc((char) DBG_ESCAPE); //send ESCAPE code 47 | UartPutc((char) DBG_CONNECT_ENABLE); //send debug test enable command 48 | puts("\nEnabling debug tester...\n"); 49 | // If debug tester is not present, 50 | if((CMSDK_GPIO0->DATA & DEBUG_ERROR) != 0) 51 | { 52 | puts("DBGERROR bit (debug error) asserted.\n"); 53 | puts("Debug tester not available:\n"); 54 | puts("1: The ARM_CMSDK_INCLUDE_DEBUG_TESTER macro is not defined, or\n"); 55 | puts("2: Cortex-M0 DesignStart is used\n"); 56 | puts("** TEST SKIPPED **\n"); 57 | // End simulation 58 | UartEndSimulation(); 59 | } 60 | 61 | 62 | // 63 | // Initialise the Communication Region 64 | // (Zero the 4 words above Stack Top) 65 | // 66 | 67 | for(i=0; i<4 ; i++) 68 | { 69 | DEBUGTESTERDATA[i] = 0; 70 | } 71 | } 72 | 73 | 74 | void DisableDebugTester(void) 75 | { 76 | //send command to disable the connection to debug tester 77 | UartPutc((char) DBG_ESCAPE); //send debug test disable command, 78 | UartPutc((char) DBG_CONNECT_DISABLE); //send debug test disable command, 79 | UartEndSimulation(); //stop simulation 80 | } 81 | 82 | 83 | //=========================================================================== 84 | // Start a function running on the debug tester 85 | //=========================================================================== 86 | void StartDebugTester(uint32_t Function) 87 | { 88 | // Write function onto function select pins 89 | CMSDK_gpio_SetOutEnable (CMSDK_GPIO0, DEBUG_CMD); // set specified bit in out enable register 90 | 91 | //setup function select and function strobe 92 | CMSDK_gpio_MaskedWrite(CMSDK_GPIO0, Function<DATA & DEBUG_RUNNING) == 0); 96 | 97 | // Clear strobe 98 | CMSDK_gpio_MaskedWrite(CMSDK_GPIO0, 0x0, DEBUG_STROBE); 99 | } 100 | 101 | 102 | //=========================================================================== 103 | // Check that a debug tester function completed 104 | // Return pass/fail accordingly 105 | //=========================================================================== 106 | uint32_t CheckDebugTester(void) 107 | { 108 | // Wait to see Running deasserted 109 | while((CMSDK_GPIO0->DATA & DEBUG_RUNNING)!= 0); 110 | 111 | // Return status, check ERROR bit 112 | if((CMSDK_GPIO0->DATA & DEBUG_ERROR) == 0) 113 | { 114 | return TEST_PASS; 115 | } 116 | else 117 | { 118 | return TEST_FAIL; 119 | } 120 | } 121 | 122 | 123 | //=========================================================================== 124 | // Execute a debug tester function 125 | //=========================================================================== 126 | uint32_t CallDebugTester(uint32_t Function) 127 | { 128 | StartDebugTester(Function); 129 | return CheckDebugTester(); 130 | } 131 | 132 | -------------------------------------------------------------------------------- /systems/cortex_m0_mcu/testcodes/generic/mcu_debugtester_interface.h: -------------------------------------------------------------------------------- 1 | /* 2 | *----------------------------------------------------------------------------- 3 | * The confidential and proprietary information contained in this file may 4 | * only be used by a person authorised under and to the extent permitted 5 | * by a subsisting licensing agreement from ARM Limited. 6 | * 7 | * (C) COPYRIGHT 2010-2015 ARM Limited or its affiliates. 8 | * ALL RIGHTS RESERVED 9 | * 10 | * This entire notice must be reproduced on all copies of this file 11 | * and copies of this file may only be made by a person if such person is 12 | * permitted to do so under the terms of a subsisting license agreement 13 | * from ARM Limited. 14 | * 15 | * SVN Information 16 | * 17 | * Checked In : $Date: 2013-03-27 23:58:01 +0000 (Wed, 27 Mar 2013) $ 18 | * 19 | * Revision : $Revision: 242484 $ 20 | * 21 | * Release Information : Cortex-M0 DesignStart-r1p0-00rel0 22 | *----------------------------------------------------------------------------- 23 | */ 24 | 25 | // 26 | // Definition of CMSDK example MCU to the Debug Tester 27 | // 28 | #include "CMSDK_CM0.h" 29 | #include 30 | #include "uart_stdout.h" // for stdout 31 | #include "CMSDK_driver.h" 32 | #include "config_id.h" // general defines such as test_pass 33 | 34 | 35 | // Functions used by tests that communicate with the Debug Tester 36 | extern void EnableDebugTester(void); 37 | extern void DisableDebugTester(void); 38 | extern uint32_t CallDebugTester(uint32_t); 39 | extern void StartDebugTester(uint32_t); 40 | extern uint32_t CheckDebugTester(void); 41 | 42 | 43 | //Test command sequence definition 44 | #define DBG_ESCAPE 0x1B 45 | #define DBG_CONNECT_ENABLE 0x11 46 | #define DBG_CONNECT_DISABLE 0x12 47 | #define DBG_SIM_STOP 0x4 48 | 49 | 50 | // GPIO0 bit allocation 51 | // 52 | // CM0_MCU GPIO0 -------------------------------------- Debug Tester 53 | // 54 | // GPIO[15] 7 <----------------------------------------< Running 55 | // GPIO[14] 6 <----------------------------------------< Error 56 | // GPIO[13] 5 >----------------------------------------> Function Strobe 57 | // GPIO[12] 4 >----------------------------------------> Function Select bit 4 58 | // GPIO[11] 3 >----------------------------------------> Function Select bit 3 59 | // GPIO[10] 2 >----------------------------------------> Function Select bit 2 60 | // GPIO[9] 1 >----------------------------------------> Function Select bit 1 61 | // GPIO[8] 0 >----------------------------------------> Function Select bit 0 62 | // 63 | #define DEBUG_BIT_LOC 8 //GPIO[8] is the least bit of Function Select 64 | #define DEBUG_CMD 0x3f<<8 //GPIO [13:8] 65 | #define DEBUG_STROBE 0x00002000 //GPIO [13] 66 | #define DEBUG_ERROR 0x00004000 //GPIO [14] 67 | #define DEBUG_RUNNING 0x00008000 //GPIO [15] 68 | 69 | // GPIO1[7] 7 70 | // GPIO1[6] 6 71 | // GPIO1[5] 5 72 | // GPIO1[4] 4 73 | // GPIO1[3] 3 74 | // GPIO1[2] 2 75 | // GPIO1[1] 1 76 | // GPIO1[0] 0 77 | 78 | 79 | // CMSDK example MCU's view of the memory shared with the debugtester 80 | // (4 words above stack top) 81 | // This macro uses the SP value from the vector table as stacktop 82 | // The stacktop cannot be set to the top of the memory. 83 | #define DEBUGTESTERDATA ((volatile uint32_t *) *((uint32_t *) 0x0)) 84 | 85 | -------------------------------------------------------------------------------- /systems/cortex_m0_mcu/testcodes/hello/hello.c: -------------------------------------------------------------------------------- 1 | /* 2 | *----------------------------------------------------------------------------- 3 | * The confidential and proprietary information contained in this file may 4 | * only be used by a person authorised under and to the extent permitted 5 | * by a subsisting licensing agreement from ARM Limited. 6 | * 7 | * (C) COPYRIGHT 2010-2015 ARM Limited or its affiliates. 8 | * ALL RIGHTS RESERVED 9 | * 10 | * This entire notice must be reproduced on all copies of this file 11 | * and copies of this file may only be made by a person if such person is 12 | * permitted to do so under the terms of a subsisting license agreement 13 | * from ARM Limited. 14 | * 15 | * SVN Information 16 | * 17 | * Checked In : $Date: 2013-03-27 23:58:01 +0000 (Wed, 27 Mar 2013) $ 18 | * 19 | * Revision : $Revision: 242484 $ 20 | * 21 | * Release Information : Cortex-M0 DesignStart-r1p0-00rel0 22 | *----------------------------------------------------------------------------- 23 | */ 24 | 25 | #ifdef CORTEX_M0 26 | #include "CMSDK_CM0.h" 27 | #include "core_cm0.h" 28 | #endif 29 | 30 | #ifdef CORTEX_M0PLUS 31 | #include "CMSDK_CM0plus.h" 32 | #include "core_cm0plus.h" 33 | #endif 34 | 35 | #include 36 | #include "uart_stdout.h" 37 | 38 | int main (void) 39 | { 40 | // UART init 41 | UartStdOutInit(); 42 | 43 | printf("Hello world\n"); 44 | 45 | printf("** TEST PASSED **\n"); 46 | 47 | // End simulation 48 | UartEndSimulation(); 49 | 50 | return 0; 51 | } 52 | 53 | -------------------------------------------------------------------------------- /systems/cortex_m0_mcu/testcodes/hello/makefile: -------------------------------------------------------------------------------- 1 | #----------------------------------------------------------------------------- 2 | # The confidential and proprietary information contained in this file may 3 | # only be used by a person authorised under and to the extent permitted 4 | # by a subsisting licensing agreement from ARM Limited. 5 | # 6 | # (C) COPYRIGHT 2010-2015 ARM Limited or its affiliates. 7 | # ALL RIGHTS RESERVED 8 | # 9 | # This entire notice must be reproduced on all copies of this file 10 | # and copies of this file may only be made by a person if such person is 11 | # permitted to do so under the terms of a subsisting license agreement 12 | # from ARM Limited. 13 | # 14 | # SVN Information 15 | # 16 | # Checked In : $Date: 2013-04-03 15:01:25 +0100 (Wed, 03 Apr 2013) $ 17 | # 18 | # Revision : $Revision: 242777 $ 19 | # 20 | # Release Information : Cortex-M0 DesignStart-r1p0-00rel0 21 | #----------------------------------------------------------------------------- 22 | # 23 | # Cortex-M System Design Kit software compilation make file 24 | # 25 | #----------------------------------------------------------------------------- 26 | # 27 | # Configurations 28 | # 29 | CPU_PRODUCT = CORTEX_M0 30 | 31 | # Shared software directory 32 | SOFTWARE_DIR = ../../../../software 33 | CMSIS_DIR = $(SOFTWARE_DIR)/cmsis 34 | CORE_DIR = $(CMSIS_DIR)/CMSIS/Include 35 | 36 | DEVICE_DIR = $(CMSIS_DIR)/Device/ARM/CMSDK_CM0 37 | 38 | # Program file 39 | TESTNAME = hello 40 | 41 | # Endian Option 42 | COMPILE_BIGEND = 0 43 | 44 | # Configuration 45 | USER_DEFINE = -DCORTEX_M0 46 | 47 | DEPS_LIST = makefile 48 | 49 | # Tool chain : ds5 / gcc / keil 50 | TOOL_CHAIN = ds5 51 | 52 | ifeq ($(TOOL_CHAIN),ds5) 53 | CPU_TYPE = --cpu Cortex-M0 54 | endif 55 | 56 | ifeq ($(TOOL_CHAIN),gcc) 57 | CPU_TYPE = -mcpu=cortex-m0 58 | endif 59 | 60 | # Startup code directory for DS-5 61 | ifeq ($(TOOL_CHAIN),ds5) 62 | STARTUP_DIR = $(DEVICE_DIR)/Source/ARM 63 | endif 64 | 65 | # Startup code directory for gcc 66 | ifeq ($(TOOL_CHAIN),gcc) 67 | STARTUP_DIR = $(DEVICE_DIR)/Source/GCC 68 | endif 69 | 70 | STARTUP_FILE = startup_CMSDK_CM0 71 | SYSTEM_FILE = system_CMSDK_CM0 72 | 73 | # --------------------------------------------------------------------------------------- 74 | # DS-5 options 75 | 76 | # MicroLIB option 77 | COMPILE_MICROLIB = 0 78 | 79 | # Small Multiply (Cortex-M0/M0+ has small multiplier option) 80 | COMPILE_SMALLMUL = 0 81 | 82 | ARM_CC_OPTIONS = -c -O3 -g -Otime -I $(DEVICE_DIR)/Include -I $(CORE_DIR) \ 83 | -I $(SOFTWARE_DIR)/common/retarget $(USER_DEFINE) 84 | ARM_ASM_OPTIONS = -g 85 | ARM_LINK_OPTIONS = "--keep=$(STARTUP_FILE).o(RESET)" "--first=$(STARTUP_FILE).o(RESET)" \ 86 | --rw_base 0x20000000 --ro_base 0x00000000 --map 87 | 88 | ifeq ($(COMPILE_BIGEND),1) 89 | # Big Endian 90 | ARM_CC_OPTIONS += --bigend 91 | ARM_ASM_OPTIONS += --bigend 92 | ARM_LINK_OPTIONS += --be8 93 | endif 94 | 95 | ifeq ($(COMPILE_MICROLIB),1) 96 | # MicroLIB 97 | ARM_CC_OPTIONS += --library_type=microlib 98 | ARM_ASM_OPTIONS += --library_type=microlib --pd "__MICROLIB SETA 1" 99 | ARM_LINK_OPTIONS += --library_type=microlib 100 | endif 101 | 102 | ifeq ($(COMPILE_SMALLMUL),1) 103 | # In Cortex-M0, small multiply takes 32 cycles 104 | ARM_CC_OPTIONS += --multiply_latency=32 105 | endif 106 | 107 | # --------------------------------------------------------------------------------------- 108 | # gcc options 109 | 110 | GNG_CC = arm-none-eabi-gcc 111 | GNU_OBJDUMP = arm-none-eabi-objdump 112 | GNU_OBJCOPY = arm-none-eabi-objcopy 113 | 114 | LINKER_SCRIPT_PATH = $(SOFTWARE_DIR)/common/scripts 115 | LINKER_SCRIPT = $(LINKER_SCRIPT_PATH)/cmsdk_cm0.ld 116 | 117 | GNU_CC_FLAGS = -g -O3 -mthumb $(CPU_TYPE) 118 | 119 | ifeq ($(COMPILE_BIGEND),1) 120 | # Big Endian 121 | GNU_CC_FLAGS += -mbig-endian 122 | endif 123 | 124 | # --------------------------------------------------------------------------------------- 125 | all: all_$(TOOL_CHAIN) 126 | 127 | # --------------------------------------------------------------------------------------- 128 | # DS-5 129 | all_ds5 : $(TESTNAME).hex $(TESTNAME).lst 130 | 131 | $(TESTNAME).o : $(TESTNAME).c $(DEPS_LIST) 132 | armcc $(ARM_CC_OPTIONS) $(CPU_TYPE) $< -o $@ 133 | 134 | $(SYSTEM_FILE).o : $(DEVICE_DIR)/Source/$(SYSTEM_FILE).c $(DEPS_LIST) 135 | armcc $(ARM_CC_OPTIONS) $(CPU_TYPE) $< -o $@ 136 | 137 | retarget.o : $(SOFTWARE_DIR)/common/retarget/retarget.c $(DEPS_LIST) 138 | armcc $(ARM_CC_OPTIONS) $(CPU_TYPE) $< -o $@ 139 | 140 | uart_stdout.o : $(SOFTWARE_DIR)/common/retarget/uart_stdout.c $(DEPS_LIST) 141 | armcc $(ARM_CC_OPTIONS) $(CPU_TYPE) $< -o $@ 142 | 143 | $(STARTUP_FILE).o : $(STARTUP_DIR)/$(STARTUP_FILE).s $(DEPS_LIST) 144 | armasm $(ARM_ASM_OPTIONS) $(CPU_TYPE) $< -o $@ 145 | 146 | $(TESTNAME).ELF : $(TESTNAME).o $(SYSTEM_FILE).o $(STARTUP_FILE).o retarget.o uart_stdout.o 147 | armlink $(ARM_LINK_OPTIONS) $(TESTNAME).o $(SYSTEM_FILE).o $(STARTUP_FILE).o retarget.o uart_stdout.o -o $@ 148 | 149 | $(TESTNAME).hex : $(TESTNAME).ELF 150 | fromelf --vhx --8x1 $< --output $@ 151 | 152 | 153 | $(TESTNAME).lst : $(TESTNAME).ELF 154 | fromelf -c -d -e -s $< --output $@ 155 | 156 | # --------------------------------------------------------------------------------------- 157 | # gcc 158 | all_gcc: 159 | $(GNG_CC) $(GNU_CC_FLAGS) $(STARTUP_DIR)/$(STARTUP_FILE).s \ 160 | $(TESTNAME).c \ 161 | $(SOFTWARE_DIR)/common/retarget/retarget.c \ 162 | $(SOFTWARE_DIR)/common/retarget/uart_stdout.c \ 163 | $(DEVICE_DIR)/Source/$(SYSTEM_FILE).c \ 164 | -I $(DEVICE_DIR)/Include -I $(CORE_DIR) \ 165 | -I $(SOFTWARE_DIR)/common/retarget \ 166 | -L $(LINKER_SCRIPT_PATH) \ 167 | -D__STACK_SIZE=0x200 \ 168 | -D__HEAP_SIZE=0x1000 \ 169 | $(USER_DEFINE) -T $(LINKER_SCRIPT) -o $(TESTNAME).o 170 | # Generate disassembly code 171 | $(GNU_OBJDUMP) -S $(TESTNAME).o > $(TESTNAME).lst 172 | # Generate binary file 173 | $(GNU_OBJCOPY) -S $(TESTNAME).o -O binary $(TESTNAME).bin 174 | # Generate hex file 175 | $(GNU_OBJCOPY) -S $(TESTNAME).o -O verilog $(TESTNAME).hex 176 | 177 | # Note: 178 | # If the version of object copy you are using does not support verilog hex file output, 179 | # you can generate the hex file from binary file using the following command 180 | # od -v -A n -t x1 --width=1 $(TESTNAME).bin > $(TESTNAME).hex 181 | 182 | 183 | # --------------------------------------------------------------------------------------- 184 | # Keil MDK 185 | 186 | all_keil: 187 | @echo "Please compile your project code and press ENTER when ready" 188 | @read dummy 189 | 190 | # --------------------------------------------------------------------------------------- 191 | # Binary 192 | 193 | all_bin: $(TESTNAME).bin 194 | # Generate hex file from binary 195 | od -v -A n -t x1 --width=1 $(TESTNAME).bin > $(TESTNAME).hex 196 | 197 | # --------------------------------------------------------------------------------------- 198 | # Clean 199 | clean : 200 | @rm -rf *.o 201 | @if [ -e $(TESTNAME).hex ] ; then \ 202 | rm -rf $(TESTNAME).hex ; \ 203 | fi 204 | @if [ -e $(TESTNAME).lst ] ; then \ 205 | rm -rf $(TESTNAME).lst ; \ 206 | fi 207 | @if [ -e $(TESTNAME).ELF ] ; then \ 208 | rm -rf $(TESTNAME).ELF ; \ 209 | fi 210 | @if [ -e $(TESTNAME).bin ] ; then \ 211 | rm -rf $(TESTNAME).bin ; \ 212 | fi 213 | @rm -rf *.crf 214 | @rm -rf *.plg 215 | @rm -rf *.tra 216 | @rm -rf *.htm 217 | @rm -rf *.map 218 | @rm -rf *.dep 219 | @rm -rf *.d 220 | @rm -rf *.lnp 221 | @rm -rf *.bak 222 | @rm -rf *.lst 223 | @rm -rf *.axf 224 | @rm -rf *.sct 225 | @rm -rf *.__i 226 | @rm -rf *._ia 227 | -------------------------------------------------------------------------------- /systems/cortex_m0_mcu/testcodes/rtx_demo/RTX_Config.c: -------------------------------------------------------------------------------- 1 | /* 2 | *----------------------------------------------------------------------------- 3 | * The confidential and proprietary information contained in this file may 4 | * only be used by a person authorised under and to the extent permitted 5 | * by a subsisting licensing agreement from ARM Limited. 6 | * 7 | * (C) COPYRIGHT 2010-2015 ARM Limited or its affiliates. 8 | * ALL RIGHTS RESERVED 9 | * 10 | * This entire notice must be reproduced on all copies of this file 11 | * and copies of this file may only be made by a person if such person is 12 | * permitted to do so under the terms of a subsisting license agreement 13 | * from ARM Limited. 14 | * 15 | * SVN Information 16 | * 17 | * Checked In : $Date: 2011-03-17 11:32:33 +0000 (Thu, 17 Mar 2011) $ 18 | * 19 | * Revision : $Revision: 164921 $ 20 | * 21 | * Release Information : Cortex-M0 DesignStart-r1p0-00rel0 22 | *----------------------------------------------------------------------------- 23 | */ 24 | 25 | /*---------------------------------------------------------------------------- 26 | * R T L - K e r n e l 27 | *---------------------------------------------------------------------------- 28 | * Name: RTX_CONFIG.C 29 | * Purpose: Configuration of RTX Kernel for Cortex-M 30 | * Rev.: V3.40 31 | *---------------------------------------------------------------------------- 32 | */ 33 | 34 | #include 35 | 36 | /*---------------------------------------------------------------------------- 37 | * RTX User configuration part BEGIN 38 | *---------------------------------------------------------------------------*/ 39 | 40 | //-------- <<< Use Configuration Wizard in Context Menu >>> ----------------- 41 | // 42 | // Task Definitions 43 | // =================== 44 | // 45 | // Number of concurrent running tasks <0-250> 46 | // Define max. number of tasks that will run at the same time. 47 | // Default: 6 48 | #ifndef OS_TASKCNT 49 | #define OS_TASKCNT 6 50 | #endif 51 | 52 | // Number of tasks with user-provided stack <0-250> 53 | // Define the number of tasks that will use a bigger stack. 54 | // The memory space for the stack is provided by the user. 55 | // Default: 0 56 | #ifndef OS_PRIVCNT 57 | #define OS_PRIVCNT 0 58 | #endif 59 | 60 | // Task stack size [bytes] <20-4096:8><#/4> 61 | // Set the stack size for tasks which is assigned by the system. 62 | // Default: 200 63 | #ifndef OS_STKSIZE 64 | #define OS_STKSIZE 200 65 | #endif 66 | 67 | // Check for the stack overflow 68 | // =============================== 69 | // Include the stack checking code for a stack overflow. 70 | // Note that additional code reduces the Kernel performance. 71 | #ifndef OS_STKCHECK 72 | #define OS_STKCHECK 1 73 | #endif 74 | 75 | // Run in privileged mode 76 | // ========================= 77 | // Run all Tasks in privileged mode. 78 | // Default: Unprivileged 79 | #ifndef OS_RUNPRIV 80 | #define OS_RUNPRIV 0 81 | #endif 82 | 83 | // Number of user timers <0-250> 84 | // Define max. number of user timers that will run at the same time. 85 | // Default: 0 (User timers disabled) 86 | #ifndef OS_TIMERCNT 87 | #define OS_TIMERCNT 0 88 | #endif 89 | 90 | // 91 | // SysTick Timer Configuration 92 | // ============================= 93 | // Timer clock value [Hz] <1-1000000000> 94 | // Set the timer clock value for selected timer. 95 | // Default: 6000000 (6MHz) 96 | #ifndef OS_CLOCK 97 | #define OS_CLOCK 50000000 98 | #endif 99 | 100 | // Timer tick value [us] <1-1000000> 101 | // Set the timer tick value for selected timer. 102 | // Default: 10000 (10ms) 103 | #ifndef OS_TICK 104 | #define OS_TICK 200 105 | #endif 106 | 107 | // 108 | // Round-Robin Task switching 109 | // ============================= 110 | // Enable Round-Robin Task switching. 111 | #ifndef OS_ROBIN 112 | #define OS_ROBIN 1 113 | #endif 114 | 115 | // Round-Robin Timeout [ticks] <1-1000> 116 | // Define how long a task will execute before a task switch. 117 | // Default: 5 118 | #ifndef OS_ROBINTOUT 119 | #define OS_ROBINTOUT 5 120 | #endif 121 | 122 | // 123 | 124 | //------------- <<< end of configuration section >>> ----------------------- 125 | 126 | // Standard library system mutexes 127 | // =============================== 128 | // Define max. number system mutexes that are used to protect 129 | // the arm standard runtime library. For microlib they are not used. 130 | #ifndef OS_MUTEXCNT 131 | #define OS_MUTEXCNT 8 132 | #endif 133 | 134 | /*---------------------------------------------------------------------------- 135 | * RTX User configuration part END 136 | *---------------------------------------------------------------------------*/ 137 | 138 | #define OS_TRV ((U32)(((double)OS_CLOCK*(double)OS_TICK)/1E6)-1) 139 | 140 | /*---------------------------------------------------------------------------- 141 | * Global Functions 142 | *---------------------------------------------------------------------------*/ 143 | 144 | /*--------------------------- os_idle_demon ---------------------------------*/ 145 | 146 | __task void os_idle_demon (void) { 147 | /* The idle demon is a system task, running when no other task is ready */ 148 | /* to run. The 'os_xxx' function calls are not allowed from this task. */ 149 | 150 | for (;;) { 151 | /* HERE: include optional user code to be executed when no task runs.*/ 152 | } 153 | } 154 | 155 | 156 | /*--------------------------- os_tmr_call -----------------------------------*/ 157 | 158 | void os_tmr_call (U16 info) { 159 | /* This function is called when the user timer has expired. Parameter */ 160 | /* 'info' holds the value, defined when the timer was created. */ 161 | 162 | /* HERE: include optional user code to be executed on timeout. */ 163 | } 164 | 165 | 166 | /*--------------------------- os_stk_overflow -------------------------------*/ 167 | 168 | void os_stk_overflow (OS_TID task_id) { 169 | /* This function is called when a stack overflow is detected. Parameter */ 170 | /* 'task_id' holds the id of this task. You can use 'RTX Kernel' dialog,*/ 171 | /* page 'Active Tasks' to check, which task needs a bigger stack. */ 172 | 173 | /* HERE: include optional code to be executed on stack overflow. */ 174 | for (;;); 175 | } 176 | 177 | 178 | /*---------------------------------------------------------------------------- 179 | * RTX Configuration Functions 180 | *---------------------------------------------------------------------------*/ 181 | 182 | #include 183 | 184 | /*---------------------------------------------------------------------------- 185 | * end of file 186 | *---------------------------------------------------------------------------*/ 187 | 188 | -------------------------------------------------------------------------------- /systems/cortex_m0_mcu/testcodes/rtx_demo/makefile: -------------------------------------------------------------------------------- 1 | #----------------------------------------------------------------------------- 2 | # The confidential and proprietary information contained in this file may 3 | # only be used by a person authorised under and to the extent permitted 4 | # by a subsisting licensing agreement from ARM Limited. 5 | # 6 | # (C) COPYRIGHT 2010-2015 ARM Limited or its affiliates. 7 | # ALL RIGHTS RESERVED 8 | # 9 | # This entire notice must be reproduced on all copies of this file 10 | # and copies of this file may only be made by a person if such person is 11 | # permitted to do so under the terms of a subsisting license agreement 12 | # from ARM Limited. 13 | # 14 | # SVN Information 15 | # 16 | # Checked In : $Date: 2013-03-05 15:59:45 +0000 (Tue, 05 Mar 2013) $ 17 | # 18 | # Revision : $Revision: 240230 $ 19 | # 20 | # Release Information : Cortex-M0 DesignStart-r1p0-00rel0 21 | #----------------------------------------------------------------------------- 22 | # 23 | # Cortex-M System Design Kit software compilation make file 24 | # 25 | #----------------------------------------------------------------------------- 26 | # 27 | # Configurations 28 | # 29 | 30 | # Tool chain : ds5 / gcc / keil 31 | TOOL_CHAIN = ds5 32 | TESTNAME = rtx_demo 33 | 34 | CPU_PRODUCT = CORTEX_M0 35 | HEXFILE = rtx_demo_cm0.hex 36 | 37 | ifeq ($(CPU_PRODUCT),CORTEX_M0) 38 | HEXFILE = rtx_demo_cm0.hex 39 | endif 40 | 41 | # --------------------------------------------------------------------------------------- 42 | all: all_$(TOOL_CHAIN) 43 | 44 | # --------------------------------------------------------------------------------------- 45 | hexfile_select: 46 | @if [ -e $(HEXFILE) ] ; then \ 47 | cp $(HEXFILE) rtx_demo.hex ; \ 48 | fi 49 | 50 | # --------------------------------------------------------------------------------------- 51 | # DS-5 52 | all_ds5 : hexfile_select 53 | @if [ -e $(TESTNAME).hex ] ; then \ 54 | echo "Found rtx_demo.hex ... use existing hex file. Continue ..." ; \ 55 | else \ 56 | echo "RTX demo compilation not available for DS-5." ; \ 57 | echo "Please compile RTX demo in Keil MDK and press ENTER when ready" ; \ 58 | read dummy ; \ 59 | fi 60 | 61 | # --------------------------------------------------------------------------------------- 62 | # gcc 63 | # 64 | all_gcc: hexfile_select 65 | @if [ -e $(TESTNAME).hex ] ; then \ 66 | echo "Found rtx_demo.hex ... use existing hex file. Continue ..." ; \ 67 | else \ 68 | echo "RTX demo compilation not available for gcc." ;\ 69 | echo "Please compile RTX demo in Keil MDK and press ENTER when ready" ; \ 70 | read dummy ; \ 71 | fi 72 | 73 | # --------------------------------------------------------------------------------------- 74 | # Keil MDK 75 | 76 | all_keil: 77 | @echo "Please compile your project code and press ENTER when ready" 78 | @read dummy 79 | cp $(HEXFILE) rtx_demo.hex 80 | 81 | # --------------------------------------------------------------------------------------- 82 | # Clean 83 | clean : 84 | @rm -rf *.o 85 | @rm -rf *.crf 86 | @rm -rf *.plg 87 | @rm -rf *.tra 88 | @rm -rf *.htm 89 | @rm -rf *.map 90 | @rm -rf *.dep 91 | @rm -rf *.d 92 | @rm -rf *.lnp 93 | @rm -rf *.bak 94 | @rm -rf *.lst 95 | @rm -rf *.axf 96 | @rm -rf *.sct 97 | @rm -rf *.uvgui.* 98 | -------------------------------------------------------------------------------- /systems/cortex_m0_mcu/testcodes/rtx_demo/rtx_demo.c: -------------------------------------------------------------------------------- 1 | /* 2 | *----------------------------------------------------------------------------- 3 | * The confidential and proprietary information contained in this file may 4 | * only be used by a person authorised under and to the extent permitted 5 | * by a subsisting licensing agreement from ARM Limited. 6 | * 7 | * (C) COPYRIGHT 2010-2015 ARM Limited or its affiliates. 8 | * ALL RIGHTS RESERVED 9 | * 10 | * This entire notice must be reproduced on all copies of this file 11 | * and copies of this file may only be made by a person if such person is 12 | * permitted to do so under the terms of a subsisting license agreement 13 | * from ARM Limited. 14 | * 15 | * SVN Information 16 | * 17 | * Checked In : $Date: 2013-03-27 23:58:01 +0000 (Wed, 27 Mar 2013) $ 18 | * 19 | * Revision : $Revision: 242484 $ 20 | * 21 | * Release Information : Cortex-M0 DesignStart-r1p0-00rel0 22 | *----------------------------------------------------------------------------- 23 | */ 24 | 25 | /* Simple demonstration of booting up an RTOS : Keil RTX */ 26 | 27 | #include 28 | #ifdef CORTEX_M0 29 | #include "CMSDK_CM0.h" 30 | #endif 31 | #ifdef CORTEX_M0PLUS 32 | #include "CMSDK_CM0plus.h" 33 | #endif 34 | #include 35 | #include "uart_stdout.h" 36 | 37 | OS_TID t_task1; // Declare a task ID for task1 : Event generator 38 | OS_TID t_task2; // Declare a task ID for task2 : Event receiver 39 | int num = 0; // Counter 40 | 41 | __task void task1(void) { // Task 1 - Event generator 42 | while (1) { 43 | os_dly_wait(1); 44 | puts("task 1 ->"); 45 | os_evt_set (0x0001, t_task2); // Send a event 0x0001 to task 2 46 | } 47 | } 48 | 49 | __task void task2(void) { // Task 2 - Event receiver 50 | while(1) { 51 | os_evt_wait_and (0x0001, 0xffff); // wait for an event flag 0x0001 52 | num ++; 53 | printf (" task 2, %d\n", num); 54 | if (num>=3) { /* Execute 3 times and stop simulation */ 55 | puts("Tasks ran 3 times."); 56 | puts("** TEST PASSED ** \n"); 57 | UartEndSimulation(); 58 | } 59 | } 60 | } 61 | 62 | /* Initialize tasks */ 63 | __task void init (void) { 64 | t_task1 = os_tsk_create (task1, 1); // Create a task "task1" with priority 1 65 | t_task2 = os_tsk_create (task2, 1); // Create a task "task2" with priority 1 66 | os_tsk_delete_self (); 67 | } 68 | 69 | 70 | int main(void) 71 | { 72 | // Starting from CMSIS 1.3, 73 | // CMSIS System Initialization function SystemInit() is called from startup code. 74 | // So there is no need to call it in here. (This test is based on CMSIS 2.0). 75 | 76 | SysTick->VAL=0; /* Initialize SysTick timer value */ 77 | 78 | // UART init 79 | UartStdOutInit(); 80 | 81 | // Test banner message and revision number 82 | puts("\nCortex Microcontroller System Design Kit - RTX Demo - revision $Revision: 242484 $\n"); 83 | puts("- Execute task 1 -> task 2 sequence three times\n"); 84 | 85 | os_sys_init(init); // Initialize OS 86 | } // end main 87 | -------------------------------------------------------------------------------- /systems/cortex_m0_mcu/testcodes/self_reset_demo/makefile: -------------------------------------------------------------------------------- 1 | #----------------------------------------------------------------------------- 2 | # The confidential and proprietary information contained in this file may 3 | # only be used by a person authorised under and to the extent permitted 4 | # by a subsisting licensing agreement from ARM Limited. 5 | # 6 | # (C) COPYRIGHT 2010-2015 ARM Limited or its affiliates. 7 | # ALL RIGHTS RESERVED 8 | # 9 | # This entire notice must be reproduced on all copies of this file 10 | # and copies of this file may only be made by a person if such person is 11 | # permitted to do so under the terms of a subsisting license agreement 12 | # from ARM Limited. 13 | # 14 | # SVN Information 15 | # 16 | # Checked In : $Date: 2013-04-03 15:28:59 +0100 (Wed, 03 Apr 2013) $ 17 | # 18 | # Revision : $Revision: 242786 $ 19 | # 20 | # Release Information : Cortex-M0 DesignStart-r1p0-00rel0 21 | #----------------------------------------------------------------------------- 22 | # 23 | # Cortex-M System Design Kit software compilation make file 24 | # 25 | #----------------------------------------------------------------------------- 26 | # 27 | # Configurations 28 | # 29 | CPU_PRODUCT = CORTEX_M0 30 | 31 | # Shared software directory 32 | SOFTWARE_DIR = ../../../../software 33 | CMSIS_DIR = $(SOFTWARE_DIR)/cmsis 34 | CORE_DIR = $(CMSIS_DIR)/CMSIS/Include 35 | 36 | DEVICE_DIR = $(CMSIS_DIR)/Device/ARM/CMSDK_CM0 37 | 38 | # Program file 39 | TESTNAME = self_reset_demo 40 | 41 | # Endian Option 42 | COMPILE_BIGEND = 0 43 | 44 | # Configuration 45 | USER_DEFINE = -DCORTEX_M0 46 | 47 | DEPS_LIST = makefile 48 | 49 | # Tool chain : ds5 / gcc / keil 50 | TOOL_CHAIN = ds5 51 | 52 | ifeq ($(TOOL_CHAIN),ds5) 53 | CPU_TYPE = --cpu Cortex-M0 54 | endif 55 | 56 | ifeq ($(TOOL_CHAIN),gcc) 57 | CPU_TYPE = -mcpu=cortex-m0 58 | endif 59 | 60 | # Startup code directory for DS-5 61 | ifeq ($(TOOL_CHAIN),ds5) 62 | STARTUP_DIR = $(DEVICE_DIR)/Source/ARM 63 | endif 64 | 65 | # Startup code directory for gcc 66 | ifeq ($(TOOL_CHAIN),gcc) 67 | STARTUP_DIR = $(DEVICE_DIR)/Source/GCC 68 | endif 69 | 70 | STARTUP_FILE = startup_CMSDK_CM0 71 | SYSTEM_FILE = system_CMSDK_CM0 72 | 73 | # --------------------------------------------------------------------------------------- 74 | # DS-5 options 75 | 76 | # MicroLIB option (DS-5) 77 | COMPILE_MICROLIB = 0 78 | 79 | # Small Multiply (Cortex-M0/M0+ has small multiplier option) 80 | COMPILE_SMALLMUL = 0 81 | 82 | ARM_CC_OPTIONS = -c -O3 -g -Otime -I $(CORE_DIR) -I $(DEVICE_DIR)/Include \ 83 | -I $(SOFTWARE_DIR)/common/retarget $(USER_DEFINE) 84 | ARM_ASM_OPTIONS = -g 85 | ARM_LINK_OPTIONS = "--keep=$(STARTUP_FILE).o(RESET)" "--first=$(STARTUP_FILE).o(RESET)" \ 86 | --rw_base 0x20000000 --ro_base 0x00000000 --map 87 | 88 | ifeq ($(COMPILE_BIGEND),1) 89 | # Big Endian 90 | ARM_CC_OPTIONS += --bigend 91 | ARM_ASM_OPTIONS += --bigend 92 | ARM_LINK_OPTIONS += --be8 93 | endif 94 | 95 | ifeq ($(COMPILE_MICROLIB),1) 96 | # MicroLIB 97 | ARM_CC_OPTIONS += --library_type=microlib 98 | ARM_ASM_OPTIONS += --library_type=microlib --pd "__MICROLIB SETA 1" 99 | ARM_LINK_OPTIONS += --library_type=microlib 100 | endif 101 | 102 | ifeq ($(COMPILE_SMALLMUL),1) 103 | # In Cortex-M0, small multiply takes 32 cycles 104 | ARM_CC_OPTIONS += --multiply_latency=32 105 | endif 106 | 107 | 108 | # --------------------------------------------------------------------------------------- 109 | # gcc options 110 | 111 | GNG_CC = arm-none-eabi-gcc 112 | GNU_OBJDUMP = arm-none-eabi-objdump 113 | GNU_OBJCOPY = arm-none-eabi-objcopy 114 | 115 | LINKER_SCRIPT_PATH = $(SOFTWARE_DIR)/common/scripts 116 | LINKER_SCRIPT = $(LINKER_SCRIPT_PATH)/cmsdk_cm0.ld 117 | 118 | GNU_CC_FLAGS = -g -O3 -mthumb $(CPU_TYPE) 119 | 120 | ifeq ($(COMPILE_BIGEND),1) 121 | # Big Endian 122 | GNU_CC_FLAGS += -mbig-endian 123 | endif 124 | 125 | # --------------------------------------------------------------------------------------- 126 | all: all_$(TOOL_CHAIN) 127 | 128 | # --------------------------------------------------------------------------------------- 129 | # DS-5 130 | all_ds5 : $(TESTNAME).hex $(TESTNAME).lst 131 | 132 | $(TESTNAME).o : $(SOFTWARE_DIR)/common/demos/$(TESTNAME).c $(DEPS_LIST) 133 | armcc $(ARM_CC_OPTIONS) $(CPU_TYPE) $< -o $@ 134 | 135 | $(SYSTEM_FILE).o : $(DEVICE_DIR)/Source/$(SYSTEM_FILE).c $(DEPS_LIST) 136 | armcc $(ARM_CC_OPTIONS) $(CPU_TYPE) $< -o $@ 137 | 138 | retarget.o : $(SOFTWARE_DIR)/common/retarget/retarget.c $(DEPS_LIST) 139 | armcc $(ARM_CC_OPTIONS) $(CPU_TYPE) $< -o $@ 140 | 141 | uart_stdout.o : $(SOFTWARE_DIR)/common/retarget/uart_stdout.c $(DEPS_LIST) 142 | armcc $(ARM_CC_OPTIONS) $(CPU_TYPE) $< -o $@ 143 | 144 | $(STARTUP_FILE).o : $(STARTUP_DIR)/$(STARTUP_FILE).s $(DEPS_LIST) 145 | armasm $(ARM_ASM_OPTIONS) $(CPU_TYPE) $< -o $@ 146 | 147 | $(TESTNAME).ELF : $(TESTNAME).o $(SYSTEM_FILE).o $(STARTUP_FILE).o retarget.o uart_stdout.o 148 | armlink $(ARM_LINK_OPTIONS) $(TESTNAME).o $(SYSTEM_FILE).o $(STARTUP_FILE).o retarget.o uart_stdout.o -o $@ 149 | 150 | $(TESTNAME).hex : $(TESTNAME).ELF 151 | fromelf --vhx --8x1 $< --output $@ 152 | 153 | 154 | $(TESTNAME).lst : $(TESTNAME).ELF 155 | fromelf -c -d -e -s $< --output $@ 156 | 157 | # --------------------------------------------------------------------------------------- 158 | # gcc 159 | all_gcc: 160 | $(GNG_CC) $(GNU_CC_FLAGS) $(STARTUP_DIR)/$(STARTUP_FILE).s \ 161 | $(SOFTWARE_DIR)/common/demos/$(TESTNAME).c \ 162 | $(SOFTWARE_DIR)/common/retarget/retarget.c \ 163 | $(SOFTWARE_DIR)/common/retarget/uart_stdout.c \ 164 | $(DEVICE_DIR)/Source/$(SYSTEM_FILE).c \ 165 | -I $(DEVICE_DIR)/Include -I $(CORE_DIR) \ 166 | -I $(SOFTWARE_DIR)/common/retarget \ 167 | -L $(LINKER_SCRIPT_PATH) \ 168 | -D__STACK_SIZE=0x200 \ 169 | -D__HEAP_SIZE=0x1000 \ 170 | $(USER_DEFINE) -T $(LINKER_SCRIPT) -o $(TESTNAME).o 171 | # Generate disassembly code 172 | $(GNU_OBJDUMP) -S $(TESTNAME).o > $(TESTNAME).lst 173 | # Generate binary file 174 | $(GNU_OBJCOPY) -S $(TESTNAME).o -O binary $(TESTNAME).bin 175 | # Generate hex file 176 | $(GNU_OBJCOPY) -S $(TESTNAME).o -O verilog $(TESTNAME).hex 177 | 178 | # Note: 179 | # If the version of object copy you are using does not support verilog hex file output, 180 | # you can generate the hex file from binary file using the following command 181 | # od -v -A n -t x1 --width=1 $(TESTNAME).bin > $(TESTNAME).hex 182 | 183 | # --------------------------------------------------------------------------------------- 184 | # Keil MDK 185 | 186 | all_keil: 187 | @echo "Please compile your project code and press ENTER when ready" 188 | @read dummy 189 | 190 | # --------------------------------------------------------------------------------------- 191 | # Binary 192 | 193 | all_bin: $(TESTNAME).bin 194 | # Generate hex file from binary 195 | od -v -A n -t x1 --width=1 $(TESTNAME).bin > $(TESTNAME).hex 196 | 197 | # --------------------------------------------------------------------------------------- 198 | # Clean 199 | clean : 200 | @rm -rf *.o 201 | @if [ -e $(TESTNAME).hex ] ; then \ 202 | rm -rf $(TESTNAME).hex ; \ 203 | fi 204 | @if [ -e $(TESTNAME).lst ] ; then \ 205 | rm -rf $(TESTNAME).lst ; \ 206 | fi 207 | @if [ -e $(TESTNAME).ELF ] ; then \ 208 | rm -rf $(TESTNAME).ELF ; \ 209 | fi 210 | @if [ -e $(TESTNAME).bin ] ; then \ 211 | rm -rf $(TESTNAME).bin ; \ 212 | fi 213 | @rm -rf *.crf 214 | @rm -rf *.plg 215 | @rm -rf *.tra 216 | @rm -rf *.htm 217 | @rm -rf *.map 218 | @rm -rf *.dep 219 | @rm -rf *.d 220 | @rm -rf *.lnp 221 | @rm -rf *.bak 222 | @rm -rf *.lst 223 | @rm -rf *.axf 224 | @rm -rf *.sct 225 | @rm -rf *.__i 226 | @rm -rf *._ia 227 | -------------------------------------------------------------------------------- /systems/cortex_m0_mcu/testcodes/watchdog_demo/makefile: -------------------------------------------------------------------------------- 1 | #----------------------------------------------------------------------------- 2 | # The confidential and proprietary information contained in this file may 3 | # only be used by a person authorised under and to the extent permitted 4 | # by a subsisting licensing agreement from ARM Limited. 5 | # 6 | # (C) COPYRIGHT 2010-2015 ARM Limited or its affiliates. 7 | # ALL RIGHTS RESERVED 8 | # 9 | # This entire notice must be reproduced on all copies of this file 10 | # and copies of this file may only be made by a person if such person is 11 | # permitted to do so under the terms of a subsisting license agreement 12 | # from ARM Limited. 13 | # 14 | # SVN Information 15 | # 16 | # Checked In : $Date: 2013-04-03 15:28:59 +0100 (Wed, 03 Apr 2013) $ 17 | # 18 | # Revision : $Revision: 242786 $ 19 | # 20 | # Release Information : Cortex-M0 DesignStart-r1p0-00rel0 21 | #----------------------------------------------------------------------------- 22 | # 23 | # Cortex-M System Design Kit software compilation make file 24 | # 25 | #----------------------------------------------------------------------------- 26 | # 27 | # Configurations 28 | # 29 | CPU_PRODUCT = CORTEX_M0 30 | 31 | # Shared software directory 32 | SOFTWARE_DIR = ../../../../software 33 | CMSIS_DIR = $(SOFTWARE_DIR)/cmsis 34 | CORE_DIR = $(CMSIS_DIR)/CMSIS/Include 35 | 36 | DEVICE_DIR = $(CMSIS_DIR)/Device/ARM/CMSDK_CM0 37 | 38 | # Program file 39 | TESTNAME = watchdog_demo 40 | 41 | # Endian Option 42 | COMPILE_BIGEND = 0 43 | 44 | # Configuration 45 | USER_DEFINE = -DCORTEX_M0 46 | 47 | DEPS_LIST = makefile 48 | 49 | # Tool chain : ds5 / gcc / keil 50 | TOOL_CHAIN = ds5 51 | 52 | ifeq ($(TOOL_CHAIN),ds5) 53 | CPU_TYPE = --cpu Cortex-M0 54 | endif 55 | 56 | ifeq ($(TOOL_CHAIN),gcc) 57 | CPU_TYPE = -mcpu=cortex-m0 58 | endif 59 | 60 | # Startup code directory for DS-5 61 | ifeq ($(TOOL_CHAIN),ds5) 62 | STARTUP_DIR = $(DEVICE_DIR)/Source/ARM 63 | endif 64 | 65 | # Startup code directory for gcc 66 | ifeq ($(TOOL_CHAIN),gcc) 67 | STARTUP_DIR = $(DEVICE_DIR)/Source/GCC 68 | endif 69 | 70 | STARTUP_FILE = startup_CMSDK_CM0 71 | SYSTEM_FILE = system_CMSDK_CM0 72 | 73 | # --------------------------------------------------------------------------------------- 74 | # DS-5 options 75 | 76 | # MicroLIB option (DS-5) 77 | COMPILE_MICROLIB = 0 78 | 79 | # Small Multiply (Cortex-M0/M0+ has small multiplier option) 80 | COMPILE_SMALLMUL = 0 81 | 82 | ARM_CC_OPTIONS = -c -O3 -g -Otime -I $(DEVICE_DIR)/Include -I $(CORE_DIR) \ 83 | -I $(SOFTWARE_DIR)/common/retarget $(USER_DEFINE) 84 | ARM_ASM_OPTIONS = -g 85 | ARM_LINK_OPTIONS = "--keep=$(STARTUP_FILE).o(RESET)" "--first=$(STARTUP_FILE).o(RESET)" \ 86 | --rw_base 0x20000000 --ro_base 0x00000000 --map 87 | 88 | ifeq ($(COMPILE_BIGEND),1) 89 | # Big Endian 90 | ARM_CC_OPTIONS += --bigend 91 | ARM_ASM_OPTIONS += --bigend 92 | ARM_LINK_OPTIONS += --be8 93 | endif 94 | 95 | ifeq ($(COMPILE_MICROLIB),1) 96 | # MicroLIB 97 | ARM_CC_OPTIONS += --library_type=microlib 98 | ARM_ASM_OPTIONS += --library_type=microlib --pd "__MICROLIB SETA 1" 99 | ARM_LINK_OPTIONS += --library_type=microlib 100 | endif 101 | 102 | ifeq ($(COMPILE_SMALLMUL),1) 103 | # In Cortex-M0, small multiply takes 32 cycles 104 | ARM_CC_OPTIONS += --multiply_latency=32 105 | endif 106 | 107 | # --------------------------------------------------------------------------------------- 108 | # gcc options 109 | 110 | GNG_CC = arm-none-eabi-gcc 111 | GNU_OBJDUMP = arm-none-eabi-objdump 112 | GNU_OBJCOPY = arm-none-eabi-objcopy 113 | 114 | LINKER_SCRIPT_PATH = $(SOFTWARE_DIR)/common/scripts 115 | LINKER_SCRIPT = $(LINKER_SCRIPT_PATH)/cmsdk_cm0.ld 116 | 117 | GNU_CC_FLAGS = -g -O3 -mthumb $(CPU_TYPE) 118 | 119 | ifeq ($(COMPILE_BIGEND),1) 120 | # Big Endian 121 | GNU_CC_FLAGS += -mbig-endian 122 | endif 123 | 124 | # --------------------------------------------------------------------------------------- 125 | all: all_$(TOOL_CHAIN) 126 | 127 | # --------------------------------------------------------------------------------------- 128 | # DS-5 129 | all_ds5 : $(TESTNAME).hex $(TESTNAME).lst 130 | 131 | $(TESTNAME).o : $(SOFTWARE_DIR)/common/demos/$(TESTNAME).c $(DEPS_LIST) 132 | armcc $(ARM_CC_OPTIONS) $(CPU_TYPE) $< -o $@ 133 | 134 | $(SYSTEM_FILE).o : $(DEVICE_DIR)/Source/$(SYSTEM_FILE).c $(DEPS_LIST) 135 | armcc $(ARM_CC_OPTIONS) $(CPU_TYPE) $< -o $@ 136 | 137 | retarget.o : $(SOFTWARE_DIR)/common/retarget/retarget.c $(DEPS_LIST) 138 | armcc $(ARM_CC_OPTIONS) $(CPU_TYPE) $< -o $@ 139 | 140 | uart_stdout.o : $(SOFTWARE_DIR)/common/retarget/uart_stdout.c $(DEPS_LIST) 141 | armcc $(ARM_CC_OPTIONS) $(CPU_TYPE) $< -o $@ 142 | 143 | $(STARTUP_FILE).o : $(STARTUP_DIR)/$(STARTUP_FILE).s $(DEPS_LIST) 144 | armasm $(ARM_ASM_OPTIONS) $(CPU_TYPE) $< -o $@ 145 | 146 | $(TESTNAME).ELF : $(TESTNAME).o $(SYSTEM_FILE).o $(STARTUP_FILE).o retarget.o uart_stdout.o 147 | armlink $(ARM_LINK_OPTIONS) $(TESTNAME).o $(SYSTEM_FILE).o $(STARTUP_FILE).o retarget.o uart_stdout.o -o $@ 148 | 149 | $(TESTNAME).hex : $(TESTNAME).ELF 150 | fromelf --vhx --8x1 $< --output $@ 151 | 152 | 153 | $(TESTNAME).lst : $(TESTNAME).ELF 154 | fromelf -c -d -e -s $< --output $@ 155 | 156 | # --------------------------------------------------------------------------------------- 157 | # gcc 158 | all_gcc: 159 | $(GNG_CC) $(GNU_CC_FLAGS) $(STARTUP_DIR)/$(STARTUP_FILE).s \ 160 | $(SOFTWARE_DIR)/common/demos/$(TESTNAME).c \ 161 | $(SOFTWARE_DIR)/common/retarget/retarget.c \ 162 | $(SOFTWARE_DIR)/common/retarget/uart_stdout.c \ 163 | $(DEVICE_DIR)/Source/$(SYSTEM_FILE).c \ 164 | -I $(DEVICE_DIR)/Include -I $(CORE_DIR) \ 165 | -I $(SOFTWARE_DIR)/common/retarget \ 166 | -L $(LINKER_SCRIPT_PATH) \ 167 | -D__STACK_SIZE=0x200 \ 168 | -D__HEAP_SIZE=0x1000 \ 169 | $(USER_DEFINE) -T $(LINKER_SCRIPT) -o $(TESTNAME).o 170 | # Generate disassembly code 171 | $(GNU_OBJDUMP) -S $(TESTNAME).o > $(TESTNAME).lst 172 | # Generate binary file 173 | $(GNU_OBJCOPY) -S $(TESTNAME).o -O binary $(TESTNAME).bin 174 | # Generate hex file 175 | $(GNU_OBJCOPY) -S $(TESTNAME).o -O verilog $(TESTNAME).hex 176 | 177 | # Note: 178 | # If the version of object copy you are using does not support verilog hex file output, 179 | # you can generate the hex file from binary file using the following command 180 | # od -v -A n -t x1 --width=1 $(TESTNAME).bin > $(TESTNAME).hex 181 | 182 | 183 | # --------------------------------------------------------------------------------------- 184 | # Keil MDK 185 | 186 | all_keil: 187 | @echo "Please compile your project code and press ENTER when ready" 188 | @read dummy 189 | 190 | # --------------------------------------------------------------------------------------- 191 | # Binary 192 | 193 | all_bin: $(TESTNAME).bin 194 | # Generate hex file from binary 195 | od -v -A n -t x1 --width=1 $(TESTNAME).bin > $(TESTNAME).hex 196 | 197 | # --------------------------------------------------------------------------------------- 198 | # Clean 199 | clean : 200 | @rm -rf *.o 201 | @if [ -e $(TESTNAME).hex ] ; then \ 202 | rm -rf $(TESTNAME).hex ; \ 203 | fi 204 | @if [ -e $(TESTNAME).lst ] ; then \ 205 | rm -rf $(TESTNAME).lst ; \ 206 | fi 207 | @if [ -e $(TESTNAME).ELF ] ; then \ 208 | rm -rf $(TESTNAME).ELF ; \ 209 | fi 210 | @if [ -e $(TESTNAME).bin ] ; then \ 211 | rm -rf $(TESTNAME).bin ; \ 212 | fi 213 | @rm -rf *.crf 214 | @rm -rf *.plg 215 | @rm -rf *.tra 216 | @rm -rf *.htm 217 | @rm -rf *.map 218 | @rm -rf *.dep 219 | @rm -rf *.d 220 | @rm -rf *.lnp 221 | @rm -rf *.bak 222 | @rm -rf *.lst 223 | @rm -rf *.axf 224 | @rm -rf *.sct 225 | @rm -rf *.__i 226 | @rm -rf *._ia 227 | -------------------------------------------------------------------------------- /systems/cortex_m0_mcu/verilog/cmsdk_clkreset.v: -------------------------------------------------------------------------------- 1 | //------------------------------------------------------------------------------ 2 | // The confidential and proprietary information contained in this file may 3 | // only be used by a person authorised under and to the extent permitted 4 | // by a subsisting licensing agreement from ARM Limited. 5 | // 6 | // (C) COPYRIGHT 2010-2015 ARM Limited or its affiliates. 7 | // ALL RIGHTS RESERVED 8 | // 9 | // This entire notice must be reproduced on all copies of this file 10 | // and copies of this file may only be made by a person if such person is 11 | // permitted to do so under the terms of a subsisting license agreement 12 | // from ARM Limited. 13 | // 14 | // Version and Release Control Information: 15 | // 16 | // File Revision : $Revision: 275084 $ 17 | // File Date : $Date: 2014-03-27 15:09:11 +0000 (Thu, 27 Mar 2014) $ 18 | // 19 | // Release Information : Cortex-M0 DesignStart-r1p0-00rel0 20 | //------------------------------------------------------------------------------ 21 | // Verilog-2001 (IEEE Std 1364-2001) 22 | //------------------------------------------------------------------------------ 23 | // 24 | //----------------------------------------------------------------------------- 25 | // Abstract : Simple clock and power on reset generator 26 | //----------------------------------------------------------------------------- 27 | `timescale 1ns/1ps 28 | 29 | module cmsdk_clkreset( 30 | output wire CLK, 31 | output wire NRST); 32 | 33 | reg clock_q = 1'b0; 34 | reg reset_n_q = 1'b0; 35 | 36 | initial 37 | begin 38 | #10 clock_q <= 1'b1; 39 | #100 reset_n_q <= 1'b1; 40 | end 41 | 42 | always @(clock_q) 43 | #10 clock_q <= ~clock_q; 44 | 45 | assign CLK = clock_q; 46 | assign NRST = reset_n_q; 47 | 48 | endmodule 49 | 50 | 51 | 52 | -------------------------------------------------------------------------------- /systems/cortex_m0_mcu/verilog/cmsdk_mcu_addr_decode.v: -------------------------------------------------------------------------------- 1 | //------------------------------------------------------------------------------ 2 | // The confidential and proprietary information contained in this file may 3 | // only be used by a person authorised under and to the extent permitted 4 | // by a subsisting licensing agreement from ARM Limited. 5 | // 6 | // (C) COPYRIGHT 2010-2015 ARM Limited or its affiliates. 7 | // ALL RIGHTS RESERVED 8 | // 9 | // This entire notice must be reproduced on all copies of this file 10 | // and copies of this file may only be made by a person if such person is 11 | // permitted to do so under the terms of a subsisting license agreement 12 | // from ARM Limited. 13 | // 14 | // Version and Release Control Information: 15 | // 16 | // File Revision : $Revision: 275084 $ 17 | // File Date : $Date: 2014-03-27 15:09:11 +0000 (Thu, 27 Mar 2014) $ 18 | // 19 | // Release Information : Cortex-M0 DesignStart-r1p0-00rel0 20 | //------------------------------------------------------------------------------ 21 | // Verilog-2001 (IEEE Std 1364-2001) 22 | //------------------------------------------------------------------------------ 23 | // 24 | //----------------------------------------------------------------------------- 25 | // Abstract : This module performs the address decode of the HADDR from the 26 | // CPU and generates the HSELs for each of the target peripherals. 27 | // Also performs address decode for MTB 28 | //----------------------------------------------------------------------------- 29 | // 30 | `include "cmsdk_mcu_defs.v" 31 | 32 | module cmsdk_mcu_addr_decode #( 33 | // GPIO0 peripheral base address 34 | parameter BASEADDR_GPIO0 = 32'h4001_0000, 35 | // GPIO1 peripheral base address 36 | parameter BASEADDR_GPIO1 = 32'h4001_1000, 37 | 38 | // Generate BOOT_LOADER_PRESENT based on BOOT_MEM_TYPE 39 | // This is a derived parameter - do not override using instantiation 40 | parameter BOOT_LOADER_PRESENT = 0, 41 | 42 | // Location of the System ROM Table. 43 | parameter BASEADDR_SYSROMTABLE = 32'hF000_0000 44 | ) 45 | ( 46 | // System Address 47 | input wire [31:0] haddr, 48 | 49 | input wire remap_ctrl, 50 | 51 | // Memory Selection 52 | output wire boot_hsel, 53 | output wire flash_hsel, 54 | output wire sram_hsel, 55 | 56 | // Peripheral Selection 57 | output wire apbsys_hsel, 58 | output wire gpio0_hsel, 59 | output wire gpio1_hsel, 60 | output wire sysctrl_hsel, 61 | output wire sysrom_hsel, 62 | 63 | // Default slave 64 | output wire defslv_hsel, 65 | 66 | // MTB Selection 67 | output wire hselmtb, // Select MTB 68 | output wire hselram, // Select MTB RAM 69 | output wire hselsfr); // Select MTB Special Function Registers 70 | 71 | 72 | // AHB address decode 73 | // 0x00000000 - 0x0000FFFF : 64K flash / boot firmware 74 | // 0x01000000 - 0x0100FFFF : boot firmware : only 4k is used 75 | // 0x20000000 - 0x2000FFFF : SRAM 76 | // 0x40000000 - 0x4000FFFF : APB subsystem 77 | // 0x40010000 - 0x4001FFFF : AHB peripherals (GPIOs) 78 | // 0xF0000000 - 0xF0000FFF : System ROM Table 79 | 80 | // ---------------------------------------------------------- 81 | // Memory decode logic 82 | // ---------------------------------------------------------- 83 | 84 | // If Boot loader is not present (BOOT_LOADER_PRESENT==0), 85 | // boot_hsel always 0. 86 | // Otherwise select if address = 0x0100xxxx or when remap_ctrl 87 | // is 1, and address = 0x0000xxxx 88 | assign boot_hsel = (BOOT_LOADER_PRESENT==0) ? 1'b0 : 89 | ((haddr[31:16]==16'h0000) & (remap_ctrl==1'b1)) | 90 | (haddr[31:16]==16'h0100); 91 | 92 | assign flash_hsel = (BOOT_LOADER_PRESENT==0) ? // 0x00000000 93 | // Boot loader not present. Select if first 64KB is selected 94 | (haddr[31:16]==16'h0000) : 95 | // Boot loader present. If boot loader is selected then flash is 96 | // not selected 97 | (haddr[31:16]==16'h0000) & (boot_hsel==1'b0); 98 | 99 | assign sram_hsel = (haddr[31:16]==16'h2000); // 0x20000000 100 | 101 | // ---------------------------------------------------------- 102 | // Peripheral Selection decode logic 103 | // ---------------------------------------------------------- 104 | 105 | assign apbsys_hsel = (haddr[31:16]==16'h4000); // 0x40000000 106 | assign gpio0_hsel = (haddr[31:12]== 107 | BASEADDR_GPIO0[31:12]); // 0x40010000 108 | assign gpio1_hsel = (haddr[31:12]== 109 | BASEADDR_GPIO1[31:12]); // 0x40011000 110 | assign sysctrl_hsel = (haddr[31:12]==20'h4001F); // 0x4001F000 111 | assign sysrom_hsel = (haddr[31:12]== 112 | BASEADDR_SYSROMTABLE[31:12]); // 0xF0000000 113 | 114 | // ---------------------------------------------------------- 115 | // Default slave decode logic 116 | // ---------------------------------------------------------- 117 | 118 | assign defslv_hsel = ~(flash_hsel | sram_hsel | 119 | boot_hsel | apbsys_hsel | 120 | gpio0_hsel | gpio1_hsel | 121 | sysctrl_hsel | sysrom_hsel | 122 | hselmtb); 123 | 124 | // ---------------------------------------------------------- 125 | // MTB Selection decode logic 126 | // ---------------------------------------------------------- 127 | 128 | assign hselmtb = 1'b0; 129 | assign hselram = 1'b0; 130 | assign hselsfr = 1'b0; 131 | 132 | endmodule 133 | -------------------------------------------------------------------------------- /systems/cortex_m0_mcu/verilog/cmsdk_mcu_clkctrl.v: -------------------------------------------------------------------------------- 1 | //------------------------------------------------------------------------------ 2 | // The confidential and proprietary information contained in this file may 3 | // only be used by a person authorised under and to the extent permitted 4 | // by a subsisting licensing agreement from ARM Limited. 5 | // 6 | // (C) COPYRIGHT 2010-2015 ARM Limited or its affiliates. 7 | // ALL RIGHTS RESERVED 8 | // 9 | // This entire notice must be reproduced on all copies of this file 10 | // and copies of this file may only be made by a person if such person is 11 | // permitted to do so under the terms of a subsisting license agreement 12 | // from ARM Limited. 13 | // 14 | // Version and Release Control Information: 15 | // 16 | // File Revision : $Revision: 275084 $ 17 | // File Date : $Date: 2014-03-27 15:09:11 +0000 (Thu, 27 Mar 2014) $ 18 | // 19 | // Release Information : Cortex-M0 DesignStart-r1p0-00rel0 20 | //------------------------------------------------------------------------------ 21 | // Verilog-2001 (IEEE Std 1364-2001) 22 | //------------------------------------------------------------------------------ 23 | // 24 | //----------------------------------------------------------------------------- 25 | // Abstract : Simple clock controller for Cortex-M0 example system 26 | //----------------------------------------------------------------------------- 27 | // Note : Most of the clock gating are handled by the example PMU provided 28 | // in the Cortex-M0/Cortex-M0+ deliverable. 29 | 30 | `include "cmsdk_mcu_defs.v" 31 | 32 | module cmsdk_mcu_clkctrl #( 33 | parameter CLKGATE_PRESENT = 0) 34 | ( 35 | input wire XTAL1, // Clock source 36 | input wire NRST, // active low external reset 37 | 38 | input wire APBACTIVE, // APB active status 39 | input wire SLEEPING, // Sleep status 40 | input wire SLEEPDEEP, // Deep Sleep status 41 | input wire SYSRESETREQ, // System reset request 42 | input wire DBGRESETREQ, // Debug reset request 43 | input wire LOCKUP, // LOCKUP status 44 | input wire LOCKUPRESET, // Config - generation reset if locked up 45 | 46 | input wire CGBYPASS, // Clock gating bypass 47 | input wire RSTBYPASS, // Reset by pass 48 | 49 | output wire XTAL2, // Feedback for Crystal oscillator 50 | output wire FCLK, // Free running clock 51 | output wire PCLK, // Peripheral clock 52 | output wire PCLKG, // Gated PCLK for APB transfers 53 | output wire PCLKEN, // Clock divide control for AHB to APB bridge 54 | output wire PORESETn, // Power on reset 55 | output wire HRESETn, // System and AHB reset 56 | output wire PRESETn); // Peripheral reset 57 | 58 | wire clk; 59 | wire reset_n; 60 | reg [2:0] reset_sync_reg; 61 | wire [2:0] nxt_reset_sync; 62 | reg hrst_reg; 63 | wire nxt_hrst; 64 | reg dbgrst_reg; 65 | reg prst_reg; 66 | wire nxt_prst; 67 | wire i_pclken; 68 | wire i_pclkgen; 69 | 70 | // Crystal oscillator inverter 71 | assign XTAL2 = (~(XTAL1 | SLEEPDEEP)); 72 | 73 | // Clock source 74 | assign clk = XTAL1; 75 | 76 | // Reset synchronizer 77 | assign nxt_reset_sync = {reset_sync_reg[1:0], 1'b1}; 78 | 79 | always @(posedge clk or negedge NRST) 80 | begin 81 | if (~NRST) 82 | reset_sync_reg <= 3'b000; 83 | else 84 | reset_sync_reg <= nxt_reset_sync; 85 | end 86 | 87 | assign reset_n = reset_sync_reg[2]; 88 | 89 | // AHB HRESETn 90 | assign nxt_hrst = ~(SYSRESETREQ | (LOCKUP & LOCKUPRESET)); 91 | 92 | always @(posedge clk or negedge reset_n) 93 | begin 94 | if (~reset_n) 95 | hrst_reg <= 1'b0; 96 | else 97 | hrst_reg <= nxt_hrst; 98 | end 99 | 100 | // Debug Reset 101 | always @(posedge clk or negedge reset_n) 102 | begin 103 | if (~reset_n) 104 | dbgrst_reg <= 1'b0; 105 | else 106 | dbgrst_reg <= ~DBGRESETREQ; 107 | end 108 | 109 | // APB PRESETn 110 | assign nxt_prst = ~(SYSRESETREQ | (LOCKUP & LOCKUPRESET)); 111 | 112 | always @(posedge clk or negedge reset_n) 113 | begin 114 | if (~reset_n) 115 | prst_reg <= 1'b0; 116 | else 117 | prst_reg <= nxt_prst; 118 | end 119 | 120 | generate if (CLKGATE_PRESENT == 0) begin : gen_no_clock_gating 121 | 122 | // No clock gating for PCLK 123 | assign i_pclken = 1'b1; // Currently PCLK = HCLK (for AHB to APB bridge) 124 | assign i_pclkgen = 1'b1; // Not used 125 | assign PCLK = clk; // Peripheral clock 126 | assign PCLKG = clk; // Peripheral clock for APB interface 127 | 128 | end else 129 | begin : gen_clock_gating 130 | // Clock gate is present. 131 | // Testing of divided PCLK is only possible when clock gating is available 132 | assign i_pclken = 1'b1; // PCLK = HCLK 133 | assign i_pclkgen = i_pclken & APBACTIVE; 134 | 135 | // PCLK generation 136 | cmsdk_clock_gate 137 | #(.CLKGATE_PRESENT(CLKGATE_PRESENT)) 138 | u_cmsdk_clock_gate_pclk( 139 | .CLK (clk), 140 | .CLKENABLE (i_pclken), 141 | .DISABLEG (CGBYPASS), 142 | .GATEDCLK (PCLK)); 143 | 144 | // Gated PCLK (PCLKG) generation 145 | cmsdk_clock_gate 146 | #(.CLKGATE_PRESENT(CLKGATE_PRESENT)) 147 | u_cmsdk_clock_gate_pclkg( 148 | .CLK (clk), 149 | .CLKENABLE (i_pclkgen), 150 | .DISABLEG (CGBYPASS), 151 | .GATEDCLK (PCLKG)); 152 | 153 | end endgenerate 154 | 155 | // Connect to top level 156 | assign PORESETn = (RSTBYPASS) ? NRST : reset_n; 157 | assign HRESETn = (RSTBYPASS) ? NRST : hrst_reg; 158 | assign PRESETn = (RSTBYPASS) ? NRST : prst_reg; 159 | assign FCLK = clk; // Free running clock 160 | assign PCLKEN = i_pclken; 161 | 162 | endmodule 163 | -------------------------------------------------------------------------------- /systems/cortex_m0_mcu/verilog/cmsdk_mcu_defs.v: -------------------------------------------------------------------------------- 1 | //------------------------------------------------------------------------------ 2 | // The confidential and proprietary information contained in this file may 3 | // only be used by a person authorised under and to the extent permitted 4 | // by a subsisting licensing agreement from ARM Limited. 5 | // 6 | // (C) COPYRIGHT 2010-2015 ARM Limited or its affiliates. 7 | // ALL RIGHTS RESERVED 8 | // 9 | // This entire notice must be reproduced on all copies of this file 10 | // and copies of this file may only be made by a person if such person is 11 | // permitted to do so under the terms of a subsisting license agreement 12 | // from ARM Limited. 13 | // 14 | // Version and Release Control Information: 15 | // 16 | // File Revision : $Revision: 275084 $ 17 | // File Date : $Date: 2014-03-27 15:09:11 +0000 (Thu, 27 Mar 2014) $ 18 | // 19 | // Release Information : Cortex-M0 DesignStart-r1p0-00rel0 20 | //------------------------------------------------------------------------------ 21 | // Verilog-2001 (IEEE Std 1364-2001) 22 | //------------------------------------------------------------------------------ 23 | // 24 | //----------------------------------------------------------------------------- 25 | // Abstract : System configurations for Cortex-M0 example system 26 | //----------------------------------------------------------------------------- 27 | 28 | 29 | // ============= MCU System options =========== 30 | 31 | //------------------------------------------------------------------------------ 32 | // Option for debug protocol 33 | // It can either be SWD (Serial Wire Debug protocol) or JTAG 34 | // These options specified here cannot be controlled purely by parameters 35 | // due to impact on I/O ports 36 | // 37 | //`define ARM_CMSDK_INCLUDE_JTAG 38 | 39 | //------------------------------------------------------------------------------ 40 | // Memory types 41 | //------------------------------------------------------------------------------ 42 | 43 | `include "cmsdk_ahb_memory_models_defs.v" 44 | 45 | // Memory types used in the Example system 46 | 47 | // Memory wait state parameters - used by behaviorial model if applicable*/ 48 | // Boot ROM non-sequential and sequential waitstate 49 | `define ARM_CMSDK_BOOT_MEM_WS_N 0 50 | `define ARM_CMSDK_BOOT_MEM_WS_S 0 51 | 52 | // ROM non-sequential and sequential waitstate 53 | `define ARM_CMSDK_ROM_MEM_WS_N 0 54 | `define ARM_CMSDK_ROM_MEM_WS_S 0 55 | 56 | // RAM non-sequential and sequential waitstate 57 | `define ARM_CMSDK_RAM_MEM_WS_N 0 58 | `define ARM_CMSDK_RAM_MEM_WS_S 0 59 | 60 | 61 | -------------------------------------------------------------------------------- /systems/cortex_m0_mcu/verilog/cmsdk_mcu_stclkctrl.v: -------------------------------------------------------------------------------- 1 | //------------------------------------------------------------------------------ 2 | // The confidential and proprietary information contained in this file may 3 | // only be used by a person authorised under and to the extent permitted 4 | // by a subsisting licensing agreement from ARM Limited. 5 | // 6 | // (C) COPYRIGHT 2010-2015 ARM Limited or its affiliates. 7 | // ALL RIGHTS RESERVED 8 | // 9 | // This entire notice must be reproduced on all copies of this file 10 | // and copies of this file may only be made by a person if such person is 11 | // permitted to do so under the terms of a subsisting license agreement 12 | // from ARM Limited. 13 | // 14 | // Version and Release Control Information: 15 | // 16 | // File Revision : $Revision: 275084 $ 17 | // File Date : $Date: 2014-03-27 15:09:11 +0000 (Thu, 27 Mar 2014) $ 18 | // 19 | // Release Information : Cortex-M0 DesignStart-r1p0-00rel0 20 | //------------------------------------------------------------------------------ 21 | // Verilog-2001 (IEEE Std 1364-2001) 22 | //------------------------------------------------------------------------------ 23 | // 24 | //----------------------------------------------------------------------------- 25 | // Abstract : Simple control for SysTick signals for Cortex-M processor 26 | //----------------------------------------------------------------------------- 27 | 28 | module cmsdk_mcu_stclkctrl #( 29 | // Ratio between FCLK and SysTick reference clock 30 | parameter DIV_RATIO = 18'd01000, 31 | 32 | // Divide by half for each phase 33 | parameter DIVIDER_RELOAD = (DIV_RATIO>>1)-1 34 | ) 35 | ( 36 | input wire FCLK, // Free running clock 37 | input wire SYSRESETn, // System reset 38 | 39 | output wire STCLKEN, // SysTick clock 40 | output wire [25:0] STCALIB // SysTick calibration 41 | ); 42 | 43 | reg [17:0] reg_clk_divider; 44 | reg reg_stclken; 45 | 46 | assign STCALIB[25] = 1'b0; // NoRef - reference clock provided 47 | assign STCALIB[24] = 1'b1; // Skew - reference info not available 48 | assign STCALIB[23:0] = {24{1'b0}}; // 10 ms value set to 0, indicate this value is not used 49 | 50 | // Divider 51 | wire [17:0] reg_clk_div_min1 = reg_clk_divider -1; 52 | always @(posedge FCLK or negedge SYSRESETn) 53 | begin 54 | if (~SYSRESETn) 55 | reg_clk_divider <= {18{1'b0}}; 56 | else 57 | begin 58 | if (|reg_clk_divider) 59 | reg_clk_divider <= reg_clk_div_min1[17:0]; 60 | else 61 | reg_clk_divider <= DIVIDER_RELOAD[17:0]; 62 | end 63 | end 64 | 65 | // Toggle register 66 | always @(posedge FCLK or negedge SYSRESETn) 67 | begin 68 | if (~SYSRESETn) 69 | reg_stclken <= 1'b0; 70 | else 71 | begin 72 | if (reg_clk_divider==18'h00000) 73 | reg_stclken <= ~reg_stclken; 74 | end 75 | end 76 | 77 | // Connect to top level 78 | assign STCLKEN = reg_stclken; 79 | 80 | endmodule 81 | 82 | -------------------------------------------------------------------------------- /systems/cortex_m0_mcu/verilog/tb_cmsdk_mcu.v: -------------------------------------------------------------------------------- 1 | //------------------------------------------------------------------------------ 2 | // The confidential and proprietary information contained in this file may 3 | // only be used by a person authorised under and to the extent permitted 4 | // by a subsisting licensing agreement from ARM Limited. 5 | // 6 | // (C) COPYRIGHT 2010-2015 ARM Limited or its affiliates. 7 | // ALL RIGHTS RESERVED 8 | // 9 | // This entire notice must be reproduced on all copies of this file 10 | // and copies of this file may only be made by a person if such person is 11 | // permitted to do so under the terms of a subsisting license agreement 12 | // from ARM Limited. 13 | // 14 | // Version and Release Control Information: 15 | // 16 | // File Revision : $Revision: 275084 $ 17 | // File Date : $Date: 2014-03-27 15:09:11 +0000 (Thu, 27 Mar 2014) $ 18 | // 19 | // Release Information : Cortex-M0 DesignStart-r1p0-00rel0 20 | //------------------------------------------------------------------------------ 21 | // Verilog-2001 (IEEE Std 1364-2001) 22 | //------------------------------------------------------------------------------ 23 | // 24 | //----------------------------------------------------------------------------- 25 | // Abstract : Testbench for the Cortex-M0 example system 26 | //----------------------------------------------------------------------------- 27 | // 28 | `timescale 1ns/1ps 29 | `include "cmsdk_mcu_defs.v" 30 | 31 | module tb_cmsdk_mcu; 32 | 33 | wire XTAL1; // crystal pin 1 34 | wire XTAL2; // crystal pin 2 35 | wire NRST; // active low reset 36 | 37 | wire [15:0] P0; // Port 0 38 | wire [15:0] P1; // Port 1 39 | 40 | 41 | //Debug tester signals 42 | wire nTRST; 43 | wire TDI; 44 | wire SWDIOTMS; 45 | wire SWCLKTCK; 46 | wire TDO; 47 | 48 | wire PCLK; // Clock for UART capture device 49 | wire [5:0] debug_command; // used to drive debug tester 50 | wire debug_running; // indicate debug test is running 51 | wire debug_err; // indicate debug test has error 52 | 53 | wire debug_test_en; // To enable the debug tester connection to MCU GPIO P0 54 | // This signal is controlled by software, 55 | // Use "UartPutc((char) 0x1B)" to send ESCAPE code to start 56 | // the command, use "UartPutc((char) 0x11)" to send debug test 57 | // enable command, use "UartPutc((char) 0x12)" to send debug test 58 | // disable command. Refer to tb_uart_capture.v file for detail 59 | 60 | parameter BE = 0; // Big or little endian 61 | 62 | parameter BKPT = 4; // Number of breakpoint comparators 63 | parameter DBG = 1; // Debug configuration 64 | parameter NUMIRQ = 32; // NUM of IRQ 65 | parameter SMUL = 0; // Multiplier configuration 66 | parameter SYST = 1; // SysTick 67 | parameter WIC = 1; // Wake-up interrupt controller support 68 | parameter WICLINES = 34; // Supported WIC lines 69 | parameter WPT = 2; // Number of DWT comparators 70 | 71 | // -------------------------------------------------------------------------------- 72 | // Cortex-M0/Cortex-M0+ Microcontroller 73 | // -------------------------------------------------------------------------------- 74 | 75 | cmsdk_mcu 76 | #(.BE (BE), 77 | .BKPT (BKPT), // Number of breakpoint comparators 78 | .DBG (DBG), // Debug configuration 79 | .NUMIRQ (NUMIRQ), // NUMIRQ 80 | .SMUL (SMUL), // Multiplier configuration 81 | .SYST (SYST), // SysTick 82 | .WIC (WIC), // Wake-up interrupt controller support 83 | .WICLINES (WICLINES), // Supported WIC lines 84 | .WPT (WPT) // Number of DWT comparators 85 | ) 86 | u_cmsdk_mcu ( 87 | .XTAL1 (XTAL1), // input 88 | .XTAL2 (XTAL2), // output 89 | .NRST (NRST), // active low reset 90 | .P0 (P0), 91 | .P1 (P1), 92 | .nTRST (nTRST), // Not needed if serial-wire debug is used 93 | .TDI (TDI), // Not needed if serial-wire debug is used 94 | .TDO (TDO), // Not needed if serial-wire debug is used 95 | .SWDIOTMS (SWDIOTMS), 96 | .SWCLKTCK (SWCLKTCK) 97 | ); 98 | 99 | // -------------------------------------------------------------------------------- 100 | // Source for clock and reset 101 | // -------------------------------------------------------------------------------- 102 | cmsdk_clkreset u_cmsdk_clkreset( 103 | .CLK (XTAL1), 104 | .NRST (NRST) 105 | ); 106 | 107 | // -------------------------------------------------------------------------------- 108 | // UART output capture 109 | // -------------------------------------------------------------------------------- 110 | assign PCLK = XTAL1; 111 | 112 | cmsdk_uart_capture u_cmsdk_uart_capture( 113 | .RESETn (NRST), 114 | .CLK (PCLK), 115 | .RXD (P1[5]), // UART 2 use for StdOut 116 | .DEBUG_TESTER_ENABLE (debug_test_en), 117 | .SIMULATIONEND (), // This signal set to 1 at the end of simulation. 118 | .AUXCTRL () 119 | ); 120 | 121 | // UART connection cross over for UART test 122 | assign P1[0] = P1[3]; // UART 0 RXD = UART 1 TXD 123 | assign P1[2] = P1[1]; // UART 1 RXD = UART 0 TXD 124 | 125 | // -------------------------------------------------------------------------------- 126 | // Debug tester connection - 127 | // -------------------------------------------------------------------------------- 128 | 129 | // No debug connection for Cortex-M0 DesignStart 130 | assign nTRST = NRST; 131 | assign TDI = 1'b1; 132 | assign SWDIOTMS = 1'b1; 133 | assign SWCLKTCK = 1'b1; 134 | 135 | bufif1 (P0[31-16], debug_running, debug_test_en); 136 | bufif1 (P0[30-16], debug_err, debug_test_en); 137 | 138 | pullup (debug_running); 139 | pullup (debug_err); 140 | 141 | // -------------------------------------------------------------------------------- 142 | // Misc 143 | // -------------------------------------------------------------------------------- 144 | 145 | // Format for time reporting 146 | initial $timeformat(-9, 0, " ns", 0); 147 | 148 | endmodule 149 | -------------------------------------------------------------------------------- /systems/cortex_m0_mcu/verilog/tbench_M0_DS.vc: -------------------------------------------------------------------------------- 1 | //------------------------------------------------------------------------------ 2 | // The confidential and proprietary information contained in this file may 3 | // only be used by a person authorised under and to the extent permitted 4 | // by a subsisting licensing agreement from ARM Limited. 5 | // 6 | // (C) COPYRIGHT 2010-2015 ARM Limited or its affiliates. 7 | // ALL RIGHTS RESERVED 8 | // 9 | // This entire notice must be reproduced on all copies of this file 10 | // and copies of this file may only be made by a person if such person is 11 | // permitted to do so under the terms of a subsisting license agreement 12 | // from ARM Limited. 13 | // 14 | // Version and Release Control Information: 15 | // 16 | // File Revision : $Revision: 275084 $ 17 | // File Date : $Date: 2014-03-27 15:09:11 +0000 (Thu, 27 Mar 2014) $ 18 | // 19 | // Release Information : Cortex-M0 DesignStart-r1p0-00rel0 20 | //------------------------------------------------------------------------------ 21 | // Verilog-2001 (IEEE Std 1364-2001) 22 | //------------------------------------------------------------------------------ 23 | // 24 | //----------------------------------------------------------------------------- 25 | // Abstract : Verilog Command File for Cortex-M0 example system 26 | //----------------------------------------------------------------------------- 27 | // 28 | // ============= Verilog library extensions =========== 29 | +libext+.v+.vlib 30 | 31 | // ============= Top level file =============== 32 | ../verilog/tb_cmsdk_mcu.v 33 | +incdir+../verilog/ 34 | 35 | 36 | // ============= MCU Module search path ============= 37 | -y ../verilog 38 | -y ../../../logical/cmsdk_apb_timer/verilog 39 | -y ../../../logical/cmsdk_apb_dualtimers/verilog 40 | -y ../../../logical/cmsdk_apb_uart/verilog 41 | -y ../../../logical/cmsdk_apb_watchdog/verilog 42 | -y ../../../logical/cmsdk_apb_slave_mux/verilog 43 | -y ../../../logical/cmsdk_apb_subsystem/verilog 44 | -y ../../../logical/cmsdk_ahb_slave_mux/verilog 45 | -y ../../../logical/cmsdk_ahb_default_slave/verilog 46 | -y ../../../logical/cmsdk_ahb_gpio/verilog 47 | -y ../../../logical/cmsdk_ahb_to_apb/verilog 48 | -y ../../../logical/models/clkgate 49 | -y ../../../logical/models/memories/ 50 | -y ../../../logical/cmsdk_iop_gpio/verilog 51 | +incdir+../../../logical/cmsdk_apb_dualtimers/verilog 52 | +incdir+../../../logical/cmsdk_apb_watchdog/verilog 53 | +incdir+../../../logical/models/memories/ 54 | 55 | // ============= Cortex-M0 Module search path ============= 56 | 57 | //Cortex M0 design start 58 | -y ../../../cores/cortexm0_designstart_r1p0/logical/cortexm0ds/verilog 59 | -y ../../../cores/cortexm0_designstart_r1p0/logical/cortexm0_integration/verilog 60 | -y ../../../cores/cortexm0_designstart_r1p0/logical/cortexm0_dap/verilog 61 | -y ../../../cores/cortexm0_designstart_r1p0/logical/models/cells 62 | +incdir+../../../cores/cortexm0_designstart_r1p0/logical/cortexm0_integration/verilog 63 | +incdir+../../../cores/cortexm0_designstart_r1p0/logical/cortexm0_dap/verilog 64 | +incdir+../../../cores/cortexm0_designstart_r1p0/logical/models/cells 65 | 66 | // ============= Cortex-M0 Include file search path ============= 67 | 68 | +incdir+../../../cores/cortexm0_designstart_r1p0/logical/cortexm0ds/verilog 69 | --------------------------------------------------------------------------------