3 | * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
4 | *
5 | * SPDX-License-Identifier: MIT
6 | *
7 | * Permission is hereby granted, free of charge, to any person obtaining a copy of
8 | * this software and associated documentation files (the "Software"), to deal in
9 | * the Software without restriction, including without limitation the rights to
10 | * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
11 | * the Software, and to permit persons to whom the Software is furnished to do so,
12 | * subject to the following conditions:
13 | *
14 | * The above copyright notice and this permission notice shall be included in all
15 | * copies or substantial portions of the Software.
16 | *
17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
19 | * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
20 | * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
21 | * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
22 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
23 | *
24 | * https://www.FreeRTOS.org
25 | * https://github.com/FreeRTOS
26 | *
27 | */
28 |
29 | #ifndef __PORT_ASM_H__
30 | #define __PORT_ASM_H__
31 |
32 | /* Scheduler includes. */
33 | #include "FreeRTOS.h"
34 |
35 | /* MPU wrappers includes. */
36 | #include "mpu_wrappers.h"
37 |
38 | /**
39 | * @brief Restore the context of the first task so that the first task starts
40 | * executing.
41 | */
42 | void vRestoreContextOfFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
43 |
44 | /**
45 | * @brief Checks whether or not the processor is privileged.
46 | *
47 | * @return 1 if the processor is already privileged, 0 otherwise.
48 | */
49 | BaseType_t xIsPrivileged( void ) __attribute__( ( naked ) );
50 |
51 | /**
52 | * @brief Raises the privilege level by clearing the bit 0 of the CONTROL
53 | * register.
54 | *
55 | * @note This is a privileged function and should only be called from the kenrel
56 | * code.
57 | *
58 | * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
59 | * Bit[0] = 0 --> The processor is running privileged
60 | * Bit[0] = 1 --> The processor is running unprivileged.
61 | */
62 | void vRaisePrivilege( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
63 |
64 | /**
65 | * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
66 | * register.
67 | *
68 | * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
69 | * Bit[0] = 0 --> The processor is running privileged
70 | * Bit[0] = 1 --> The processor is running unprivileged.
71 | */
72 | void vResetPrivilege( void ) __attribute__( ( naked ) );
73 |
74 | /**
75 | * @brief Starts the first task.
76 | */
77 | void vStartFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
78 |
79 | /**
80 | * @brief Disables interrupts.
81 | */
82 | uint32_t ulSetInterruptMask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
83 |
84 | /**
85 | * @brief Enables interrupts.
86 | */
87 | void vClearInterruptMask( uint32_t ulMask ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
88 |
89 | /**
90 | * @brief PendSV Exception handler.
91 | */
92 | void PendSV_Handler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
93 |
94 | /**
95 | * @brief SVC Handler.
96 | */
97 | void SVC_Handler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
98 |
99 | /**
100 | * @brief Allocate a Secure context for the calling task.
101 | *
102 | * @param[in] ulSecureStackSize The size of the stack to be allocated on the
103 | * secure side for the calling task.
104 | */
105 | void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) __attribute__( ( naked ) );
106 |
107 | /**
108 | * @brief Free the task's secure context.
109 | *
110 | * @param[in] pulTCB Pointer to the Task Control Block (TCB) of the task.
111 | */
112 | void vPortFreeSecureContext( uint32_t * pulTCB ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
113 |
114 | #endif /* __PORT_ASM_H__ */
115 |
--------------------------------------------------------------------------------
/GCC/CORTEX_A53_64-bit_UltraScale_MPSoC/bsp_patches/xil-crt0.S:
--------------------------------------------------------------------------------
1 | /******************************************************************************
2 | * Copyright (C) 2014 - 2020 Xilinx, Inc. All rights reserved.
3 | * SPDX-License-Identifier: MIT
4 | ******************************************************************************/
5 | /*****************************************************************************/
6 | /**
7 | * @file xil-crt0.S
8 | *
9 | *
10 | * MODIFICATION HISTORY:
11 | *
12 | * Ver Who Date Changes
13 | * ----- ---- -------- ---------------------------------------------------
14 | * 5.00 pkp 05/21/14 Initial version
15 | * 5.04 pkp 12/18/15 Initialized global constructor for C++ applications
16 | * 5.04 pkp 01/05/16 Set the reset vector register RVBAR equivalent to
17 | * vector table base address
18 | * 6.02 pkp 01/22/17 Added support for EL1 non-secure
19 | * 6.6 srm 10/18/17 Added timer configuration using XTime_StartTTCTimer API.
20 | * Now the TTC instance as specified by the user will be
21 | * started.
22 | * 6.6 mus 01/29/18 Initialized the xen PV console for Cortexa53 64 bit
23 | * EL1 NS BSP.
24 | * 7.2 sd 02/23/20 Clock Init is called
25 | * 7.2 sd 02/23/20 Clock code added under XCLOCKING flag
26 | *
27 | *
28 | * @note
29 | *
30 | * None.
31 | *
32 | ******************************************************************************/
33 | #include "xparameters.h"
34 | #include "bspconfig.h"
35 | .file "xil-crt0.S"
36 | .section ".got2","aw"
37 | .align 2
38 | .globl _vector_table
39 |
40 | #define FREERTOS_SMP
41 |
42 | #ifdef FREERTOS_SMP
43 | .set secondary_cpu_reset_vector, _vector_table
44 | #endif
45 |
46 | .text
47 | .Lsbss_start:
48 | .quad __sbss_start
49 |
50 | .Lsbss_end:
51 | .quad __sbss_end
52 |
53 | .Lbss_start:
54 | .quad __bss_start__
55 |
56 | .Lbss_end:
57 | .quad __bss_end__
58 |
59 | .extern StartAndWaitSecondaryCpuUp
60 |
61 | .set APU_PWRCTL, 0xFD5C0090
62 |
63 | .globl _startup
64 | _startup:
65 |
66 | #ifdef FREERTOS_SMP
67 | /* Get CPU Id */
68 | mrs x0, MPIDR_EL1
69 | and x0, x0, #0xFF
70 | cmp x0, #0
71 | bne c_init_end
72 | #endif
73 |
74 | mov x0, #0
75 | .if (EL3 == 1)
76 | /* Check whether the clearing of bss sections shall be skipped */
77 | ldr x10, =APU_PWRCTL /* Load PWRCTRL address */
78 | ldr w11, [x10] /* Read PWRCTRL register */
79 | mrs x2, MPIDR_EL1 /* Read MPIDR_EL1 */
80 | ubfx x2, x2, #0, #8 /* Extract CPU ID (affinity level 0) */
81 | mov w1, #1
82 | lsl w2, w1, w2 /* Shift CPU ID to get one-hot ID */
83 | ands w11, w11, w2 /* Get PWRCTRL bit for this core */
84 | bne .Lenclbss /* Skip BSS and SBSS clearing */
85 | .endif
86 | /* clear sbss */
87 | ldr x1,.Lsbss_start /* calculate beginning of the SBSS */
88 | ldr x2,.Lsbss_end /* calculate end of the SBSS */
89 |
90 | .Lloop_sbss:
91 | cmp x1,x2
92 | bge .Lenclsbss /* If no SBSS, no clearing required */
93 | str x0, [x1], #8
94 | b .Lloop_sbss
95 |
96 | .Lenclsbss:
97 | /* clear bss */
98 | ldr x1,.Lbss_start /* calculate beginning of the BSS */
99 | ldr x2,.Lbss_end /* calculate end of the BSS */
100 |
101 | .Lloop_bss:
102 | cmp x1,x2
103 | bge .Lenclbss /* If no BSS, no clearing required */
104 | str x0, [x1], #8
105 | b .Lloop_bss
106 |
107 | .Lenclbss:
108 | /* run global constructors */
109 | bl __libc_init_array
110 |
111 | c_init_end:
112 | /* Reset and start Triple Timer Counter */
113 | #if defined (SLEEP_TIMER_BASEADDR)
114 | bl XTime_StartTTCTimer
115 | #endif
116 |
117 | .if (EL1_NONSECURE == 1 && HYP_GUEST == 1 && \
118 | XEN_USE_PV_CONSOLE == 1)
119 | bl XPVXenConsole_Init
120 | .endif
121 |
122 | #ifdef FREERTOS_SMP
123 | /* Get CPU Id */
124 | mrs x0, MPIDR_EL1
125 | and x0, x0, #0xFF
126 | ldr x1, =secondary_cpu_reset_vector
127 | /* void StartAndWaitSecondaryCpuUp(uint64_t CpuID, uint64_t ResetAddr) */
128 | bl StartAndWaitSecondaryCpuUp
129 | #endif
130 | /* make sure argc and argv are valid */
131 | mov x0, #0
132 | mov x1, #0
133 |
134 | #ifdef XCLOCKING
135 | bl Xil_ClockInit
136 | #endif
137 |
138 | bl main /* Jump to main C code */
139 |
140 | /* Cleanup global constructors */
141 | bl __libc_fini_array
142 |
143 | bl exit
144 |
145 | .Lexit: /* should never get here */
146 | b .Lexit
147 |
148 | .Lstart:
149 | .size _startup,.Lstart-_startup
150 |
--------------------------------------------------------------------------------
/GCC/CORTEX_A9_Zynq7000/utility/gtimer.h:
--------------------------------------------------------------------------------
1 | #ifndef GTIMER_H
2 | #define GTIMER_H
3 |
4 | /*
5 | * The gtimer driver supports basic operations on the
6 | * Cortex-A9 global timer.
7 | *
8 | * It does NOT support interrupts.
9 | *
10 | * To extend the driver functionalities refer to the global
11 | * timer registers section on the Cortex-A9 MPCore TMR.
12 | *
13 | */
14 | #include
15 | #include "xparameters_ps.h"
16 |
17 | #ifdef __cplusplus
18 | extern "C" {
19 | #endif
20 |
21 | /* Global timer registers offsets */
22 | #define GT_COUNTER_REGISTER_LOW32_OFFSET 0x0
23 | #define GT_COUNTER_REGISTER_HIGH32_OFFSET 0x4
24 | #define GT_CONTROL_REGISTER_OFFSET 0x8
25 |
26 | /*
27 | #define GT_INTERRUPT_STATUS_REGISTER_OFFSET 0xC
28 | #define GT_COMPARATOR_VALUE_REGISTER_LOW32_OFFSET 0x10
29 | #define GT_COMPARATOR_VALUE_REGISTER_HIGH32_OFFSET 0x14
30 | #define GT_AUTO_INCREMENT_REGISTER_OFFSET 0x18
31 | */
32 |
33 | /* Global timer registers addresses */
34 | #define GT_BASE_ADDRESS XPAR_GLOBAL_TMR_BASEADDR
35 | #define GT_COUNTER_REGISTER_LOW32_ADDRESS (GT_BASE_ADDRESS + GT_COUNTER_REGISTER_LOW32_OFFSET)
36 | #define GT_COUNTER_REGISTER_HIGH32_ADDRESS (GT_BASE_ADDRESS + GT_COUNTER_REGISTER_HIGH32_OFFSET)
37 | #define GT_CONTROL_REGISTER_ADDRESS (GT_BASE_ADDRESS + GT_CONTROL_REGISTER_OFFSET)
38 |
39 | /* Global timer registers */
40 | #define GT_COUNTER_REGISTER_LOW32 (*((volatile uint32_t *) GT_COUNTER_REGISTER_LOW32_ADDRESS))
41 | #define GT_COUNTER_REGISTER_HIGH32 (*((volatile uint32_t *) GT_COUNTER_REGISTER_HIGH32_ADDRESS))
42 | #define GT_CONTROL_REGISTER (*((volatile uint32_t *) GT_CONTROL_REGISTER_ADDRESS))
43 |
44 | /* Utility */
45 | #define GT_CONTROL_REGISTER_PRESCALER_MASK 0xFF00
46 | #define GT_CONTROL_REGISTER_PRESCALER_OFFSET 8U
47 | #define GT_CONTROL_REGISTER_CTRL_BITS_MASK 0xE
48 |
49 | /* Functions declaration */
50 | static inline uint32_t GlobalTimer_isEnabled( void );
51 | static inline void GlobalTimer_Start( void );
52 | static inline void GlobalTimer_Stop( void );
53 | static inline uint32_t GlobalTimer_GetCounter_Low32( void );
54 | static inline void GlobalTimer_SetCounter( uint64_t counterValue );
55 | static inline void GlobalTimer_SetPrescaler( uint8_t prescalerValue );
56 | static inline uint8_t GlobalTimer_GetPrescaler( void );
57 |
58 |
59 | /**
60 | * @brief Check if the global timer is enabled
61 | *
62 | * @return FALSE (0) if the timer is not enabled, TRUE (1) otherwise
63 | */
64 | static inline uint32_t GlobalTimer_isEnabled( void ){
65 | return (GT_CONTROL_REGISTER & 1);
66 | }
67 |
68 | /**
69 | * @brief Enable the global timer
70 | *
71 | */
72 | static inline void GlobalTimer_Start( void ){
73 | GT_CONTROL_REGISTER |= 0x1;
74 | }
75 |
76 | /**
77 | * @brief Stop the global timer
78 | */
79 | static inline void GlobalTimer_Stop( void ){
80 | GT_CONTROL_REGISTER &= ~0x1;
81 | }
82 |
83 | /**
84 | * @brief Read the lower 32 bits of the counter register
85 | *
86 | * @return The read 32-bit value
87 | */
88 | static inline uint32_t GlobalTimer_GetCounter_Low32( void ){
89 | return GT_COUNTER_REGISTER_LOW32;
90 | }
91 |
92 | /**
93 | * @brief Write the 64-bit counter register
94 | *
95 | * @param counterValue The 64-bit value written into the counter register
96 | *
97 | * @note The timer should be stopped before writing
98 | */
99 | static inline void GlobalTimer_SetCounter( uint64_t counterValue ){
100 | GT_COUNTER_REGISTER_HIGH32 = (uint32_t) (counterValue >> 32);
101 | GT_COUNTER_REGISTER_LOW32 = (uint32_t) counterValue;
102 | }
103 |
104 | /**
105 | * @brief Set the prescaler of the global timer
106 | *
107 | * @param prescalerValue The 8-bit prescaler value
108 | */
109 | static inline void GlobalTimer_SetPrescaler( uint8_t prescalerValue ){
110 | GT_CONTROL_REGISTER = ((((uint32_t) (prescalerValue)) << GT_CONTROL_REGISTER_PRESCALER_OFFSET) |
111 | (GT_CONTROL_REGISTER & (~GT_CONTROL_REGISTER_PRESCALER_MASK)));
112 | }
113 |
114 | /**
115 | * @brief Get the prescaler value of the global timer
116 | *
117 | * @return The 8-bit value of the prescaler field
118 | */
119 | static inline uint8_t GlobalTimer_GetPrescaler( void ){
120 | return ((GT_CONTROL_REGISTER & GT_CONTROL_REGISTER_PRESCALER_MASK) >> GT_CONTROL_REGISTER_PRESCALER_OFFSET);
121 | }
122 |
123 | /**
124 | * @brief Clear the Auto-Increment, IRQ enable and Comp Enable
125 | * bits in the control register
126 | */
127 | static inline void GlobalTimer_ClearControlBits( void ){
128 | GT_CONTROL_REGISTER &= (~GT_CONTROL_REGISTER_CTRL_BITS_MASK);
129 | }
130 |
131 | #ifdef __cplusplus
132 | }
133 | #endif
134 |
135 | #endif
--------------------------------------------------------------------------------
/.github/CONTRIBUTING.md:
--------------------------------------------------------------------------------
1 | # Contribution guidelines
2 |
3 | Thank you for your interest in contributing to our project. Whether it's a bug report, new feature, code, or
4 | documentation, we welcome our community to be involved in this project.
5 |
6 | Please read through this document before submitting any issues or pull requests to ensure we are able to help you and all members of the community as effectively as possible.
7 |
8 | ## Code of conduct
9 | This project has adopted the [Amazon Open Source Code of Conduct](https://aws.github.io/code-of-conduct).
10 | For more information see the [Code of Conduct FAQ](https://aws.github.io/code-of-conduct-faq) or contact
11 | opensource-codeofconduct@amazon.com with any additional questions or comments.
12 |
13 |
14 | ## Security issue notifications
15 | If you discover a potential security issue in this project we ask that you notify AWS/Amazon Security via our [vulnerability reporting page](http://aws.amazon.com/security/vulnerability-reporting/). Please do **not** create a public github issue.
16 |
17 |
18 | ## Submitting a bugs/feature request
19 | Have a bug to report or feature to request? Follow these steps:
20 | 1. Search on the [FreeRTOS Community Support Forums](https://forums.freertos.org/) and [GitHub issue tracker](https://github.com/FreeRTOS/FreeRTOS/issues?utf8=%E2%9C%93&q=is%3Aissue) to be sure this hasn't been already reported or discussed.
21 | 2. If your search turns up empty, create a new topic in the [forums](https://forums.freertos.org/) and work with the community to help clarify issues or refine the idea. Include as many of the details listed below.
22 | 3. Once the community has had time to discuss and digest, we welcome you to create an [issue](https://github.com/FreeRTOS/FreeRTOS/issues) to report bugs or suggest features.
23 |
24 | When creating a new topic on the forums or filing an issue, please include as many relevant details as possible. Examples include:
25 |
26 | * A clear description of the situation — what you observe, what you expect, and your view on how the two differ.
27 | * A reproducible test case or sequence of steps.
28 | * The version of our code being used.
29 | * Any modifications you've made relevant to the bug.
30 | * Details of your environment or deployment. Highlight anything unusual.
31 |
32 |
33 | ## Contributing via pull request
34 | Contributions via pull requests are much appreciated. Before sending us a pull request, please ensure that:
35 |
36 | 1. You are working against the latest source on the *master* branch.
37 | 2. You check existing open, and recently merged, pull requests to make sure someone else hasn't addressed the problem already.
38 | 3. You open an issue to discuss any significant work - we would hate for your time to be wasted.
39 |
40 | To send us a pull request, please:
41 |
42 | 1. Fork the repository.
43 | 2. Modify the source; focus on the specific change you are contributing. If you also reformat all the code, it will be hard for us to focus on your change.
44 | 3. Follow the [coding style guide](https://www.freertos.org/FreeRTOS-Coding-Standard-and-Style-Guide.html).
45 | 4. Commit to your fork using clear commit messages.
46 | 5. Send us a pull request, answering any default questions in the pull request interface.
47 | NOTE: Please make sure the default option (Allow edits from maintainers) is left checked.
48 | 6. Pay attention to any automated CI failures reported in the pull request, and stay involved in the conversation.
49 |
50 | GitHub provides additional document on [forking a repository](https://help.github.com/articles/fork-a-repo/) and
51 | [creating a pull request](https://help.github.com/articles/creating-a-pull-request/).
52 |
53 | ## Coding style
54 | * Please ensure that your code complies to the [FreeRTOS coding style guidelines](https://www.freertos.org/FreeRTOS-Coding-Standard-and-Style-Guide.html).
55 |
56 |
57 | ## Getting your pull request merged
58 | All pull requests must be approved by our review team before it can be merged in. We appreciate your patience while pull requests are reviewed. The time it takes to review will depend on complexity and consideration of wider implications.
59 |
60 |
61 | ## Finding contributions to work on
62 | Looking at the existing issues is a great way to find something to contribute on. As our projects, by default, use the default GitHub issue labels (enhancement/bug/duplicate/help wanted/invalid/question/wontfix), tackling open 'help wanted' issues is a great place to start.
63 |
64 |
65 | ## Licensing
66 | The FreeRTOS kernel is released under the MIT open source license, the text of which can be found [here](https://github.com/FreeRTOS/FreeRTOS/blob/master/FreeRTOS/License/license.txt)
67 |
68 | Additional license files can be found in the folders containing any supplementary libraries licensed by their respective copyright owners where applicable.
69 |
70 | We may ask you to sign a [Contributor License Agreement (CLA)](http://en.wikipedia.org/wiki/Contributor_License_Agreement) for larger changes.
71 |
--------------------------------------------------------------------------------
/GCC/RP2350_RISC-V/FreeRTOS_Kernel_import.cmake:
--------------------------------------------------------------------------------
1 | # This is a copy of /portable/ThirdParty/GCC/RP2040/FREERTOS_KERNEL_import.cmake
2 |
3 | # This can be dropped into an external project to help locate the FreeRTOS kernel
4 | # It should be include()ed prior to project(). Alternatively this file may
5 | # or the CMakeLists.txt in this directory may be included or added via add_subdirectory
6 | # respectively.
7 |
8 | if (DEFINED ENV{FREERTOS_KERNEL_PATH} AND (NOT FREERTOS_KERNEL_PATH))
9 | set(FREERTOS_KERNEL_PATH $ENV{FREERTOS_KERNEL_PATH})
10 | message("Using FREERTOS_KERNEL_PATH from environment ('${FREERTOS_KERNEL_PATH}')")
11 | endif ()
12 |
13 | # first pass we look in old tree; second pass we look in new tree
14 | foreach(SEARCH_PASS RANGE 0 1)
15 | if (SEARCH_PASS)
16 | # ports may be moving to submodule in the future
17 | set(FREERTOS_KERNEL_RP2040_RELATIVE_PATH "portable/ThirdParty/Community-Supported-Ports/GCC")
18 | set(FREERTOS_KERNEL_RP2040_BACK_PATH "../../../../..")
19 | else()
20 | set(FREERTOS_KERNEL_RP2040_RELATIVE_PATH "portable/ThirdParty/GCC")
21 | set(FREERTOS_KERNEL_RP2040_BACK_PATH "../../../..")
22 | endif()
23 |
24 | if(PICO_PLATFORM STREQUAL "rp2040")
25 | set(FREERTOS_KERNEL_RP2040_RELATIVE_PATH "${FREERTOS_KERNEL_RP2040_RELATIVE_PATH}/RP2040")
26 | else()
27 | if (PICO_PLATFORM STREQUAL "rp2350-riscv")
28 | set(FREERTOS_KERNEL_RP2040_RELATIVE_PATH "${FREERTOS_KERNEL_RP2040_RELATIVE_PATH}/RP2350_RISC-V")
29 | else()
30 | set(FREERTOS_KERNEL_RP2040_RELATIVE_PATH "${FREERTOS_KERNEL_RP2040_RELATIVE_PATH}/RP2350_ARM_NTZ")
31 | endif()
32 | endif()
33 |
34 | if (NOT FREERTOS_KERNEL_PATH)
35 | # check if we are inside the FreeRTOS kernel tree (i.e. this file has been included directly)
36 | get_filename_component(_ACTUAL_PATH ${CMAKE_CURRENT_LIST_DIR} REALPATH)
37 | get_filename_component(_POSSIBLE_PATH ${CMAKE_CURRENT_LIST_DIR}/${FREERTOS_KERNEL_RP2040_BACK_PATH}/${FREERTOS_KERNEL_RP2040_RELATIVE_PATH} REALPATH)
38 | if (_ACTUAL_PATH STREQUAL _POSSIBLE_PATH)
39 | get_filename_component(FREERTOS_KERNEL_PATH ${CMAKE_CURRENT_LIST_DIR}/${FREERTOS_KERNEL_RP2040_BACK_PATH} REALPATH)
40 | endif()
41 | if (_ACTUAL_PATH STREQUAL _POSSIBLE_PATH)
42 | get_filename_component(FREERTOS_KERNEL_PATH ${CMAKE_CURRENT_LIST_DIR}/${FREERTOS_KERNEL_RP2040_BACK_PATH} REALPATH)
43 | message("Setting FREERTOS_KERNEL_PATH to ${FREERTOS_KERNEL_PATH} based on location of FreeRTOS-Kernel-import.cmake")
44 | break()
45 | elseif (PICO_SDK_PATH AND EXISTS "${PICO_SDK_PATH}/../FreeRTOS-Kernel")
46 | set(FREERTOS_KERNEL_PATH ${PICO_SDK_PATH}/../FreeRTOS-Kernel)
47 | message("Defaulting FREERTOS_KERNEL_PATH as sibling of PICO_SDK_PATH: ${FREERTOS_KERNEL_PATH}")
48 | break()
49 | endif()
50 | endif ()
51 |
52 | if (NOT FREERTOS_KERNEL_PATH)
53 | foreach(POSSIBLE_SUFFIX Source FreeRTOS-Kernel FreeRTOS/Source)
54 | # check if FreeRTOS-Kernel exists under directory that included us
55 | set(SEARCH_ROOT ${CMAKE_CURRENT_SOURCE_DIR})
56 | get_filename_component(_POSSIBLE_PATH ${SEARCH_ROOT}/${POSSIBLE_SUFFIX} REALPATH)
57 | if (EXISTS ${_POSSIBLE_PATH}/${FREERTOS_KERNEL_RP2040_RELATIVE_PATH}/CMakeLists.txt)
58 | get_filename_component(FREERTOS_KERNEL_PATH ${_POSSIBLE_PATH} REALPATH)
59 | message("Setting FREERTOS_KERNEL_PATH to '${FREERTOS_KERNEL_PATH}' found relative to enclosing project")
60 | break()
61 | endif()
62 | endforeach()
63 | if (FREERTOS_KERNEL_PATH)
64 | break()
65 | endif()
66 | endif()
67 |
68 | # user must have specified
69 | if (FREERTOS_KERNEL_PATH)
70 | if (EXISTS "${FREERTOS_KERNEL_PATH}/${FREERTOS_KERNEL_RP2040_RELATIVE_PATH}")
71 | break()
72 | endif()
73 | endif()
74 | endforeach ()
75 |
76 | if (NOT FREERTOS_KERNEL_PATH)
77 | message(FATAL_ERROR "FreeRTOS location was not specified. Please set FREERTOS_KERNEL_PATH.")
78 | endif()
79 |
80 | set(FREERTOS_KERNEL_PATH "${FREERTOS_KERNEL_PATH}" CACHE PATH "Path to the FreeRTOS Kernel")
81 |
82 | get_filename_component(FREERTOS_KERNEL_PATH "${FREERTOS_KERNEL_PATH}" REALPATH BASE_DIR "${CMAKE_BINARY_DIR}")
83 | if (NOT EXISTS ${FREERTOS_KERNEL_PATH})
84 | message(FATAL_ERROR "Directory '${FREERTOS_KERNEL_PATH}' not found")
85 | endif()
86 | if (NOT EXISTS ${FREERTOS_KERNEL_PATH}/${FREERTOS_KERNEL_RP2040_RELATIVE_PATH}/CMakeLists.txt)
87 | message(FATAL_ERROR "Directory '${FREERTOS_KERNEL_PATH}' does not contain a '${PICO_PLATFORM}' port here: ${FREERTOS_KERNEL_RP2040_RELATIVE_PATH}")
88 | endif()
89 | set(FREERTOS_KERNEL_PATH ${FREERTOS_KERNEL_PATH} CACHE PATH "Path to the FreeRTOS_KERNEL" FORCE)
90 |
91 | add_subdirectory(${FREERTOS_KERNEL_PATH}/${FREERTOS_KERNEL_RP2040_RELATIVE_PATH} FREERTOS_KERNEL)
92 |
--------------------------------------------------------------------------------
/GCC/RP2350_ARM_NTZ/FreeRTOS_Kernel_import.cmake:
--------------------------------------------------------------------------------
1 | # This is a copy of /portable/ThirdParty/GCC/RP2040/FREERTOS_KERNEL_import.cmake
2 |
3 | # This can be dropped into an external project to help locate the FreeRTOS kernel
4 | # It should be include()ed prior to project(). Alternatively this file may
5 | # or the CMakeLists.txt in this directory may be included or added via add_subdirectory
6 | # respectively.
7 |
8 | if (DEFINED ENV{FREERTOS_KERNEL_PATH} AND (NOT FREERTOS_KERNEL_PATH))
9 | set(FREERTOS_KERNEL_PATH $ENV{FREERTOS_KERNEL_PATH})
10 | message("Using FREERTOS_KERNEL_PATH from environment ('${FREERTOS_KERNEL_PATH}')")
11 | endif ()
12 |
13 | # first pass we look in old tree; second pass we look in new tree
14 | foreach(SEARCH_PASS RANGE 0 1)
15 | if (SEARCH_PASS)
16 | # ports may be moving to submodule in the future
17 | set(FREERTOS_KERNEL_RP2040_RELATIVE_PATH "portable/ThirdParty/Community-Supported-Ports/GCC")
18 | set(FREERTOS_KERNEL_RP2040_BACK_PATH "../../../../..")
19 | else()
20 | set(FREERTOS_KERNEL_RP2040_RELATIVE_PATH "portable/ThirdParty/GCC")
21 | set(FREERTOS_KERNEL_RP2040_BACK_PATH "../../../..")
22 | endif()
23 |
24 | if(PICO_PLATFORM STREQUAL "rp2040")
25 | set(FREERTOS_KERNEL_RP2040_RELATIVE_PATH "${FREERTOS_KERNEL_RP2040_RELATIVE_PATH}/RP2040")
26 | else()
27 | if (PICO_PLATFORM STREQUAL "rp2350-riscv")
28 | set(FREERTOS_KERNEL_RP2040_RELATIVE_PATH "${FREERTOS_KERNEL_RP2040_RELATIVE_PATH}/RP2350_RISC-V")
29 | else()
30 | set(FREERTOS_KERNEL_RP2040_RELATIVE_PATH "${FREERTOS_KERNEL_RP2040_RELATIVE_PATH}/RP2350_ARM_NTZ")
31 | endif()
32 | endif()
33 |
34 | if (NOT FREERTOS_KERNEL_PATH)
35 | # check if we are inside the FreeRTOS kernel tree (i.e. this file has been included directly)
36 | get_filename_component(_ACTUAL_PATH ${CMAKE_CURRENT_LIST_DIR} REALPATH)
37 | get_filename_component(_POSSIBLE_PATH ${CMAKE_CURRENT_LIST_DIR}/${FREERTOS_KERNEL_RP2040_BACK_PATH}/${FREERTOS_KERNEL_RP2040_RELATIVE_PATH} REALPATH)
38 | if (_ACTUAL_PATH STREQUAL _POSSIBLE_PATH)
39 | get_filename_component(FREERTOS_KERNEL_PATH ${CMAKE_CURRENT_LIST_DIR}/${FREERTOS_KERNEL_RP2040_BACK_PATH} REALPATH)
40 | endif()
41 | if (_ACTUAL_PATH STREQUAL _POSSIBLE_PATH)
42 | get_filename_component(FREERTOS_KERNEL_PATH ${CMAKE_CURRENT_LIST_DIR}/${FREERTOS_KERNEL_RP2040_BACK_PATH} REALPATH)
43 | message("Setting FREERTOS_KERNEL_PATH to ${FREERTOS_KERNEL_PATH} based on location of FreeRTOS-Kernel-import.cmake")
44 | break()
45 | elseif (PICO_SDK_PATH AND EXISTS "${PICO_SDK_PATH}/../FreeRTOS-Kernel")
46 | set(FREERTOS_KERNEL_PATH ${PICO_SDK_PATH}/../FreeRTOS-Kernel)
47 | message("Defaulting FREERTOS_KERNEL_PATH as sibling of PICO_SDK_PATH: ${FREERTOS_KERNEL_PATH}")
48 | break()
49 | endif()
50 | endif ()
51 |
52 | if (NOT FREERTOS_KERNEL_PATH)
53 | foreach(POSSIBLE_SUFFIX Source FreeRTOS-Kernel FreeRTOS/Source)
54 | # check if FreeRTOS-Kernel exists under directory that included us
55 | set(SEARCH_ROOT ${CMAKE_CURRENT_SOURCE_DIR})
56 | get_filename_component(_POSSIBLE_PATH ${SEARCH_ROOT}/${POSSIBLE_SUFFIX} REALPATH)
57 | if (EXISTS ${_POSSIBLE_PATH}/${FREERTOS_KERNEL_RP2040_RELATIVE_PATH}/CMakeLists.txt)
58 | get_filename_component(FREERTOS_KERNEL_PATH ${_POSSIBLE_PATH} REALPATH)
59 | message("Setting FREERTOS_KERNEL_PATH to '${FREERTOS_KERNEL_PATH}' found relative to enclosing project")
60 | break()
61 | endif()
62 | endforeach()
63 | if (FREERTOS_KERNEL_PATH)
64 | break()
65 | endif()
66 | endif()
67 |
68 | # user must have specified
69 | if (FREERTOS_KERNEL_PATH)
70 | if (EXISTS "${FREERTOS_KERNEL_PATH}/${FREERTOS_KERNEL_RP2040_RELATIVE_PATH}")
71 | break()
72 | endif()
73 | endif()
74 | endforeach ()
75 |
76 | if (NOT FREERTOS_KERNEL_PATH)
77 | message(FATAL_ERROR "FreeRTOS location was not specified. Please set FREERTOS_KERNEL_PATH.")
78 | endif()
79 |
80 | set(FREERTOS_KERNEL_PATH "${FREERTOS_KERNEL_PATH}" CACHE PATH "Path to the FreeRTOS Kernel")
81 |
82 | get_filename_component(FREERTOS_KERNEL_PATH "${FREERTOS_KERNEL_PATH}" REALPATH BASE_DIR "${CMAKE_BINARY_DIR}")
83 | if (NOT EXISTS ${FREERTOS_KERNEL_PATH})
84 | message(FATAL_ERROR "Directory '${FREERTOS_KERNEL_PATH}' not found")
85 | endif()
86 | if (NOT EXISTS ${FREERTOS_KERNEL_PATH}/${FREERTOS_KERNEL_RP2040_RELATIVE_PATH}/CMakeLists.txt)
87 | message(FATAL_ERROR "Directory '${FREERTOS_KERNEL_PATH}' does not contain a '${PICO_PLATFORM}' port here: ${FREERTOS_KERNEL_RP2040_RELATIVE_PATH}")
88 | endif()
89 | set(FREERTOS_KERNEL_PATH ${FREERTOS_KERNEL_PATH} CACHE PATH "Path to the FreeRTOS_KERNEL" FORCE)
90 |
91 | add_subdirectory(${FREERTOS_KERNEL_PATH}/${FREERTOS_KERNEL_RP2040_RELATIVE_PATH} FREERTOS_KERNEL)
92 |
--------------------------------------------------------------------------------
/GCC/CORTEX_A9_Zynq7000/port_asm_vectors.S:
--------------------------------------------------------------------------------
1 | /*
2 | * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
3 | * Copyright (C) 2009-2021 Xilinx, Inc. All rights reserved.
4 | * Copyright (c) 2022 Advanced Micro Devices, Inc. All Rights Reserved.
5 | *
6 | * SPDX-License-Identifier: MIT
7 | *
8 | * Permission is hereby granted, free of charge, to any person obtaining a copy of
9 | * this software and associated documentation files (the "Software"), to deal in
10 | * the Software without restriction, including without limitation the rights to
11 | * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
12 | * the Software, and to permit persons to whom the Software is furnished to do so,
13 | * subject to the following conditions:
14 | *
15 | * The above copyright notice and this permission notice shall be included in all
16 | * copies or substantial portions of the Software.
17 | *
18 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
20 | * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
21 | * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
22 | * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
23 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
24 | *
25 | * https://www.FreeRTOS.org
26 | * https://github.com/FreeRTOS
27 | *
28 | */
29 | /*****************************************************************************/
30 | /**
31 | * @file asm_vectors.s
32 | *
33 | * This file contains the initial vector table for the Cortex A9 processor
34 | *
35 | *
36 | * MODIFICATION HISTORY:
37 | *
38 | * Ver Who Date Changes
39 | * ----- ------- -------- ---------------------------------------------------
40 | * 1.00a ecm/sdm 10/20/09 Initial version
41 | * 3.05a sdm 02/02/12 Save lr when profiling is enabled
42 | * 3.10a srt 04/18/13 Implemented ARM Erratas. Please refer to file
43 | * 'xil_errata.h' for errata description
44 | *
45 | *
46 | * @note
47 | *
48 | * None.
49 | *
50 | ******************************************************************************/
51 |
52 | #include "xil_errata.h"
53 |
54 | .org 0
55 | .text
56 | .arm
57 |
58 | .global _boot
59 | .global _freertos_vector_table
60 | .global _vector_table
61 |
62 | .global FIQInterrupt
63 | .global DataAbortInterrupt
64 | .global PrefetchAbortInterrupt
65 | .global vPortInstallFreeRTOSVectorTable
66 |
67 | .extern FreeRTOS_IRQ_Handler
68 | .extern FreeRTOS_SWI_Handler
69 |
70 | .text
71 | .section .vectors
72 | _vector_table:
73 | _freertos_vector_table:
74 | B _boot
75 | B FreeRTOS_Undefined
76 | ldr pc, _swi
77 | B FreeRTOS_PrefetchAbortHandler
78 | B FreeRTOS_DataAbortHandler
79 | NOP /* Placeholder for address exception vector*/
80 | LDR PC, _irq
81 | B FreeRTOS_FIQHandler
82 |
83 | _irq: .word FreeRTOS_IRQ_Handler
84 | _swi: .word FreeRTOS_SWI_Handler
85 |
86 |
87 | .align 4
88 | FreeRTOS_FIQHandler: /* FIQ vector handler */
89 | stmdb sp!,{r0-r3,r12,lr} /* state save from compiled code */
90 | FIQLoop:
91 | blx FIQInterrupt /* FIQ vector */
92 | ldmia sp!,{r0-r3,r12,lr} /* state restore from compiled code */
93 | subs pc, lr, #4 /* adjust return */
94 |
95 | .align 4
96 | FreeRTOS_Undefined: /* Undefined handler */
97 | stmdb sp!,{r0-r3,r12,lr} /* state save from compiled code */
98 | ldr r0, =UndefinedExceptionAddr
99 | sub r1, lr, #4
100 | str r1, [r0] /* Store address of instruction causing undefined exception */
101 |
102 | blx UndefinedException /* UndefinedException: call C function here */
103 | ldmia sp!,{r0-r3,r12,lr} /* state restore from compiled code */
104 | movs pc, lr
105 |
106 | .align 4
107 | FreeRTOS_DataAbortHandler: /* Data Abort handler */
108 | #ifdef CONFIG_ARM_ERRATA_775420
109 | dsb
110 | #endif
111 | stmdb sp!,{r0-r3,r12,lr} /* state save from compiled code */
112 | ldr r0, =DataAbortAddr
113 | sub r1, lr, #8
114 | str r1, [r0] /* Store address of instruction causing undefined exception */
115 | blx DataAbortInterrupt /*DataAbortInterrupt :call C function here */
116 | ldmia sp!,{r0-r3,r12,lr} /* state restore from compiled code */
117 | subs pc, lr, #4 /* adjust return */
118 |
119 | .align 4
120 | FreeRTOS_PrefetchAbortHandler: /* Prefetch Abort handler */
121 | #ifdef CONFIG_ARM_ERRATA_775420
122 | dsb
123 | #endif
124 | stmdb sp!,{r0-r3,r12,lr} /* state save from compiled code */
125 | ldr r0, =PrefetchAbortAddr
126 | sub r1, lr, #4
127 | str r1, [r0] /* Stores instruction causing prefetch abort */
128 | blx PrefetchAbortInterrupt /* PrefetchAbortInterrupt: call C function here */
129 | ldmia sp!,{r0-r3,r12,lr} /* state restore from compiled code */
130 | subs pc, lr, #4 /* adjust return */
131 |
132 | .align 4
133 | .type vPortInstallFreeRTOSVectorTable, %function
134 | vPortInstallFreeRTOSVectorTable:
135 |
136 | /* Set VBAR to the vector table that contains the FreeRTOS handlers. */
137 | ldr r0, =_freertos_vector_table
138 | mcr p15, 0, r0, c12, c0, 0
139 | dsb
140 | isb
141 | bx lr
142 |
143 |
144 | .end
145 |
--------------------------------------------------------------------------------
/CCS/C2000_C28x/portmacro.h:
--------------------------------------------------------------------------------
1 | //-------------------------------------------------------------------------------------------------
2 | // Author: Ivan Zaitsev, ivan.zaitsev@gmail.com
3 | //
4 | // This file follows the FreeRTOS distribution license.
5 | //
6 | // FreeRTOS is free software; you can redistribute it and/or modify it under
7 | // the terms of the GNU General Public License (version 2) as published by the
8 | // Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.
9 | //
10 | // ***************************************************************************
11 | // >>! NOTE: The modification to the GPL is included to allow you to !<<
12 | // >>! distribute a combined work that includes FreeRTOS without being !<<
13 | // >>! obliged to provide the source code for proprietary components !<<
14 | // >>! outside of the FreeRTOS kernel. !<<
15 | // ***************************************************************************
16 | //
17 | // FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
18 | // WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
19 | // FOR A PARTICULAR PURPOSE. Full license text is available on the following
20 | // link: http://www.freertos.org/a00114.html
21 | //-------------------------------------------------------------------------------------------------
22 |
23 | #ifndef PORTMACRO_H
24 | #define PORTMACRO_H
25 |
26 | //-------------------------------------------------------------------------------------------------
27 | // Port specific definitions.
28 | //
29 | // The settings in this file configure FreeRTOS correctly for the
30 | // given hardware and compiler.
31 | //
32 | // These settings should not be altered.
33 | //-------------------------------------------------------------------------------------------------
34 |
35 | //-------------------------------------------------------------------------------------------------
36 | // Hardware includes
37 | //-------------------------------------------------------------------------------------------------
38 |
39 | //-------------------------------------------------------------------------------------------------
40 | // Type definitions.
41 | //-------------------------------------------------------------------------------------------------
42 | #define portCHAR uint16_t
43 | #define portFLOAT float
44 | #define portDOUBLE double
45 | #define portLONG uint32_t
46 | #define portSHORT uint16_t
47 | #define portBASE_TYPE uint16_t
48 | #define uint8_t uint16_t
49 | #define int8_t int16_t
50 | #define portSTACK_TYPE uint16_t
51 |
52 | typedef portSTACK_TYPE StackType_t;
53 | typedef int16_t BaseType_t;
54 | typedef uint16_t UBaseType_t;
55 |
56 | #if( configUSE_16_BIT_TICKS == 1 )
57 | typedef uint16_t TickType_t;
58 | #define portMAX_DELAY ( TickType_t ) 0xffff
59 | #else
60 | typedef uint32_t TickType_t;
61 | #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
62 | #endif
63 |
64 | //-------------------------------------------------------------------------------------------------
65 | // Interrupt control macros.
66 | //-------------------------------------------------------------------------------------------------
67 | #define portDISABLE_INTERRUPTS() __asm(" setc INTM")
68 | #define portENABLE_INTERRUPTS() __asm(" clrc INTM")
69 |
70 | //-------------------------------------------------------------------------------------------------
71 | // Critical section control macros.
72 | //-------------------------------------------------------------------------------------------------
73 | extern void vPortEnterCritical( void );
74 | extern void vPortExitCritical( void );
75 | #define portENTER_CRITICAL() vPortEnterCritical()
76 | #define portEXIT_CRITICAL() vPortExitCritical()
77 |
78 | //-------------------------------------------------------------------------------------------------
79 | // Task utilities.
80 | //-------------------------------------------------------------------------------------------------
81 | #define portYIELD() do{bYield = 1; __asm(" INTR INT14");}while(0)
82 | #define portYIELD_FROM_ISR( x ) do{if(x == pdTRUE){bYield = 1; __asm(" OR IFR, #0x2000");}}while(0)
83 |
84 | extern void portTICK_ISR( void );
85 | extern void portRESTORE_FIRST_CONTEXT( void );
86 | extern void vTaskSwitchContext( void );
87 | extern volatile uint16_t bYield;
88 |
89 | //-------------------------------------------------------------------------------------------------
90 | // Hardware specifics.
91 | //-------------------------------------------------------------------------------------------------
92 | #define portBYTE_ALIGNMENT 2
93 | #define portSTACK_GROWTH ( 1 )
94 | #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
95 | #define portNOP() __asm(" NOP")
96 |
97 | //-------------------------------------------------------------------------------------------------
98 | // Task function macros as described on the FreeRTOS.org WEB site.
99 | //-------------------------------------------------------------------------------------------------
100 | #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
101 | #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
102 |
103 | #endif /* PORTMACRO_H */
104 |
--------------------------------------------------------------------------------
/GCC/MSP430FR5969/portmacro.h:
--------------------------------------------------------------------------------
1 | /*
2 | * FreeRTOS Kernel V10.4.2
3 | * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
4 | *
5 | * Permission is hereby granted, free of charge, to any person obtaining a copy of
6 | * this software and associated documentation files (the "Software"), to deal in
7 | * the Software without restriction, including without limitation the rights to
8 | * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
9 | * the Software, and to permit persons to whom the Software is furnished to do so,
10 | * subject to the following conditions:
11 | *
12 | * The above copyright notice and this permission notice shall be included in all
13 | * copies or substantial portions of the Software.
14 | *
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
17 | * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
18 | * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
19 | * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
20 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
21 | *
22 | * https://www.FreeRTOS.org
23 | * https://github.com/FreeRTOS
24 | *
25 | */
26 |
27 | #ifndef PORTMACRO_H
28 | #define PORTMACRO_H
29 |
30 | /*-----------------------------------------------------------
31 | * Port specific definitions.
32 | *
33 | * The settings in this file configure FreeRTOS correctly for the
34 | * given hardware and compiler.
35 | *
36 | * These settings should not be altered.
37 | *-----------------------------------------------------------
38 | */
39 |
40 | /* Hardware includes. */
41 | #include
42 |
43 | /* Type definitions. */
44 | #define portCHAR char
45 | #define portFLOAT float
46 | #define portDOUBLE double
47 | #define portLONG long
48 | #define portSHORT int
49 | #define portBASE_TYPE short
50 |
51 | /* The stack type changes depending on the data model. */
52 | #ifdef __LARGE_DATA_MODEL__
53 | #define portSTACK_TYPE uint32_t
54 | #else
55 | #define portSTACK_TYPE uint16_t
56 | #define portPOINTER_SIZE_TYPE uint16_t
57 | #endif
58 |
59 | typedef portSTACK_TYPE StackType_t;
60 | typedef short BaseType_t;
61 | typedef unsigned short UBaseType_t;
62 |
63 | #if( configUSE_16_BIT_TICKS == 1 )
64 | typedef uint16_t TickType_t;
65 | #define portMAX_DELAY ( TickType_t ) 0xffff
66 | #else
67 | typedef uint32_t TickType_t;
68 | #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
69 | #endif
70 |
71 | /*-----------------------------------------------------------*/
72 |
73 | /* Interrupt control macros. */
74 | #define portDISABLE_INTERRUPTS() asm volatile ( "NOP" ); asm volatile ( "DINT" ); asm volatile ( "NOP" )
75 | #define portENABLE_INTERRUPTS() asm volatile ( "NOP" ); asm volatile ( "EINT" ); asm volatile ( "NOP" )
76 | /*-----------------------------------------------------------*/
77 |
78 | /* Critical section control macros. */
79 | #define portNO_CRITICAL_SECTION_NESTING ( ( uint16_t ) 0 )
80 |
81 | #define portENTER_CRITICAL() \
82 | { \
83 | extern volatile uint16_t usCriticalNesting; \
84 | \
85 | portDISABLE_INTERRUPTS(); \
86 | \
87 | /* Now interrupts are disabled ulCriticalNesting can be accessed */ \
88 | /* directly. Increment ulCriticalNesting to keep a count of how many */ \
89 | /* times portENTER_CRITICAL() has been called. */ \
90 | usCriticalNesting++; \
91 | }
92 |
93 | #define portEXIT_CRITICAL() \
94 | { \
95 | extern volatile uint16_t usCriticalNesting; \
96 | \
97 | if( usCriticalNesting > portNO_CRITICAL_SECTION_NESTING ) \
98 | { \
99 | /* Decrement the nesting count as we are leaving a critical section. */ \
100 | usCriticalNesting--; \
101 | \
102 | /* If the nesting level has reached zero then interrupts should be */ \
103 | /* re-enabled. */ \
104 | if( usCriticalNesting == portNO_CRITICAL_SECTION_NESTING ) \
105 | { \
106 | portENABLE_INTERRUPTS(); \
107 | } \
108 | } \
109 | }
110 | /*-----------------------------------------------------------*/
111 |
112 | /* Task utilities. */
113 | extern void vPortYield( void ) __attribute__ ( ( naked ) );
114 | #define portYIELD() vPortYield()
115 | #define portNOP() asm volatile ( "NOP" )
116 | /*-----------------------------------------------------------*/
117 |
118 | /* Hardware specifics. */
119 | #define portBYTE_ALIGNMENT 2
120 | #define portSTACK_GROWTH ( -1 )
121 | #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
122 | /*-----------------------------------------------------------*/
123 |
124 | /* Task function macros as described on the FreeRTOS.org WEB site. */
125 | #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
126 | #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
127 |
128 | extern void vTaskSwitchContext(void);
129 | #define portYIELD_FROM_ISR( x ) if( x ) vPortYield()
130 | void vApplicationSetupTimerInterrupt( void );
131 |
132 | #endif /* PORTMACRO_H */
133 |
--------------------------------------------------------------------------------
/CCRH/RH850_F1KM_S4/portmacro.h:
--------------------------------------------------------------------------------
1 | /*
2 | * FreeRTOS Kernel V11.0.1
3 | * Copyright (C) 2023 Amazon.com, Inc. or its affiliates. All Rights Reserved.
4 | *
5 | * SPDX-License-Identifier: MIT
6 | *
7 | * Permission is hereby granted, free of charge, to any person obtaining a copy of
8 | * this software and associated documentation files (the "Software"), to deal in
9 | * the Software without restriction, including without limitation the rights to
10 | * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
11 | * the Software, and to permit persons to whom the Software is furnished to do so,
12 | * subject to the following conditions:
13 | *
14 | * The above copyright notice and this permission notice shall be included in all
15 | * copies or substantial portions of the Software.
16 | *
17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
19 | * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
20 | * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
21 | * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
22 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
23 | *
24 | * https://www.FreeRTOS.org
25 | * https://github.com/FreeRTOS
26 | *
27 | */
28 |
29 | #ifndef PORTMACRO_H
30 | #define PORTMACRO_H
31 |
32 | #if __cplusplus
33 | extern "C"
34 | {
35 | #endif
36 |
37 | /*-----------------------------------------------------------
38 | * Port specific definitions.
39 | *
40 | * The settings in this file configure FreeRTOS correctly for the
41 | * given hardware and compiler.
42 | *
43 | * These settings should not be altered.
44 | *-----------------------------------------------------------
45 | */
46 |
47 | /* Type definitions - These are a bit legacy and not really used now, other
48 | * than portSTACK_TYPE and portBASE_TYPE. */
49 | #define portCHAR char
50 | #define portFLOAT float
51 | #define portDOUBLE double
52 | #define portLONG long
53 | #define portSHORT short
54 | #define portSTACK_TYPE uint32_t
55 | #define portBASE_TYPE long
56 |
57 | typedef portSTACK_TYPE StackType_t;
58 | typedef long BaseType_t;
59 | typedef unsigned long UBaseType_t;
60 |
61 | /* Defines the maximum time when using a wait command in a task */
62 | #if (configUSE_16_BIT_TICKS == 1)
63 | typedef uint16_t TickType_t;
64 | #define portMAX_DELAY (TickType_t) 0xffff
65 | #else
66 | typedef uint32_t TickType_t;
67 | #define portMAX_DELAY (TickType_t) 0xffffffffUL
68 |
69 | /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
70 | * not need to be guarded with a critical section. */
71 | #define portTICK_TYPE_IS_ATOMIC (1)
72 | #endif
73 |
74 | /* Structure passed to pvParameters when task creation code is generated. */
75 | typedef struct st_rm_freertos_port_parameters
76 | {
77 | void * p_context; // Pointer to user data
78 | } rm_freertos_port_parameters_t;
79 |
80 | /*-----------------------------------------------------------*/
81 |
82 | /* Architecture specifics */
83 |
84 | /* Determine the descending of the stack from high address to address */
85 | #define portSTACK_GROWTH (-1)
86 |
87 | /* Determine the time (in milliseconds) corresponding to each tick */
88 | #define portTICK_PERIOD_MS ((TickType_t) 1000 / configTICK_RATE_HZ)
89 |
90 | /* It is a multiple of 4 (the two lower-order bits of the address = 0),
91 | * otherwise it will cause MAE (Misaligned Exception) according to the manual */
92 | #define portBYTE_ALIGNMENT (8)
93 |
94 | /* Interrupt control macros. */
95 |
96 | #define portENABLE_INTERRUPTS() __EI() /* Macro to enable all maskable interrupts. */
97 | #define portDISABLE_INTERRUPTS() __DI() /* Macro to disable all maskable interrupts. */
98 |
99 | /*-----------------------------------------------------------*/
100 |
101 | /* Scheduler utilities */
102 |
103 | /* Use to transfer control from one task to perform other tasks of higher priority */
104 | extern void vPortYield(void);
105 |
106 | /* Called at the end of an ISR that can cause a context switch */
107 |
108 | #define portEND_SWITCHING_ISR(xSwitchRequired) \
109 | { \
110 | extern volatile BaseType_t xPortSwitchRequired; \
111 | \
112 | if (xSwitchRequired != pdFALSE) \
113 | { \
114 | xPortSwitchRequired = pdTRUE; \
115 | } \
116 | }
117 |
118 | #define portYIELD_FROM_ISR(x) portEND_SWITCHING_ISR(x)
119 | #define portYIELD() vPortYield()
120 |
121 | /* Critical section management. */
122 |
123 | /* Critical nesting counts are stored in the TCB. */
124 |
125 | #define portCRITICAL_NESTING_IN_TCB (1)
126 |
127 | /* The critical nesting functions defined within tasks.c */
128 |
129 | extern void vTaskEnterCritical(void);
130 | extern void vTaskExitCritical(void);
131 |
132 | /* Macro to mark the start of a critical code region */
133 | #define portENTER_CRITICAL() vTaskEnterCritical()
134 |
135 | /* Macro to mark the end of a critical code region */
136 | #define portEXIT_CRITICAL() vTaskExitCritical()
137 |
138 | /*-----------------------------------------------------------*/
139 |
140 | /* As this port allows interrupt nesting... */
141 |
142 | #define portSET_INTERRUPT_MASK_FROM_ISR() __stsr_rh(5, 0); __DI() /* Stores the contents of the system register,
143 | * and disable all maskable interrupts */
144 |
145 | #define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) __ldsr_rh(5, 0, x) /* Load the contents into the system register */
146 |
147 | /*-----------------------------------------------------------*/
148 | /* Task function macros as described on the FreeRTOS.org WEB site. */
149 |
150 | #define portTASK_FUNCTION_PROTO(vFunction, pvParameters) void vFunction(void * pvParameters)
151 | #define portTASK_FUNCTION(vFunction, pvParameters) void vFunction(void * pvParameters)
152 |
153 | #ifdef __cplusplus
154 | }
155 | #endif
156 |
157 | #endif /* PORTMACRO_H */
158 |
--------------------------------------------------------------------------------
/CCRH/RH850_F1KM_S4/portasm.s:
--------------------------------------------------------------------------------
1 | ;/*
2 | ;* FreeRTOS Kernel V11.0.1
3 | ;* Copyright (C) 2023 Amazon.com, Inc. or its affiliates. All Rights Reserved.
4 | ;*
5 | ;* SPDX-License-Identifier: MIT
6 | ;*
7 | ;* Permission is hereby granted, free of charge, to any person obtaining a copy of
8 | ;* this software and associated documentation files (the "Software"), to deal in
9 | ;* the Software without restriction, including without limitation the rights to
10 | ;* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
11 | ;* the Software, and to permit persons to whom the Software is furnished to do so,
12 | ;* subject to the following conditions:
13 | ;*
14 | ;* The above copyright notice and this permission notice shall be included in all
15 | ;* copies or substantial portions of the Software.
16 | ;*
17 | ;* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 | ;* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
19 | ;* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
20 | ;* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
21 | ;* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
22 | ;* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
23 | ;*
24 | ;* https://www.FreeRTOS.org
25 | ;* https://github.com/FreeRTOS
26 | ;*
27 | ;*/
28 |
29 | ;------------------------------------------------------------------------------
30 | ; Extern symbols
31 | ;------------------------------------------------------------------------------
32 | .extern _vTaskSwitchContext
33 | .extern _pxCurrentTCB
34 | .extern _xInterruptNesting
35 | .extern _xPortSwitchRequired
36 | .extern _bsp_common_interrupt_handler
37 |
38 | .public _vPortYield
39 | .public _TRAP0_Handler
40 | .public _Irq_Handler
41 | .public _vPortStartFirstTask
42 |
43 | .section ".text", text
44 | ;------------------------------------------------------------------------------
45 | ; Macro definitions
46 | ;------------------------------------------------------------------------------
47 | EIPC .set 0
48 | EIPSW .set 1
49 | EIIC .set 13
50 | EIIC_MSK .set 0x00000FFF
51 |
52 | ;------------------------------------------------------------------------------
53 | ; Context saving
54 | ;------------------------------------------------------------------------------
55 | portSAVE_CONTEXT .macro
56 | prepare lp, 0
57 |
58 | ;Save general-purpose registers and EIPSW, EIPC, EIIC into stack.
59 | pushsp r5, r30
60 | $nowarning
61 | pushsp r1, r2
62 | $warning
63 |
64 | stsr EIPSW, r17
65 | stsr EIPC, r18
66 | pushsp r17, r18
67 |
68 | ;Save the stack pointer in the TCB
69 | mov #_pxCurrentTCB, r2
70 | ld.w 0[r2], r2
71 | st.w sp, 0[r2]
72 | .endm
73 |
74 | ;------------------------------------------------------------------------------
75 | ; Context restoring
76 | ;------------------------------------------------------------------------------
77 | portRESTORE_CONTEXT .macro
78 | ;Set the SP to point to the stack of the task being restored.
79 | mov #_pxCurrentTCB, r2
80 | ld.w 0[r2], r2
81 | ld.w 0[r2], sp
82 |
83 | ;Restore general-purpose registers and EIPSW, EIPC, EIIC.
84 | popsp r17, r18
85 | ldsr r18, EIPC
86 | ldsr r17, EIPSW
87 |
88 | $nowarning
89 | popsp r1, r2
90 | $warning
91 | popsp r5, r30
92 |
93 | dispose 0, lp
94 | .endm
95 |
96 | ;------------------------------------------------------------------------------
97 | ; Start the first task.
98 | ;------------------------------------------------------------------------------
99 | _vPortStartFirstTask:
100 |
101 | portRESTORE_CONTEXT
102 |
103 | eiret
104 |
105 | ;------------------------------------------------------------------------------
106 | ; _vPortYield
107 | ;------------------------------------------------------------------------------
108 | _vPortYield:
109 | trap 0
110 | jmp [lp]
111 |
112 | ;------------------------------------------------------------------------------
113 | ; _TRAP0_Handler
114 | ; FreeRTOS yield handler. This is installed as the TRAP exception handler.
115 | ;------------------------------------------------------------------------------
116 | _TRAP0_Handler:
117 | ;Save the context of the current task.
118 | portSAVE_CONTEXT
119 |
120 | ;Call the scheduler to select the next task.
121 | jarl _vTaskSwitchContext, lp
122 |
123 | ;Restore the context of the next task to run.
124 | portRESTORE_CONTEXT
125 |
126 | eiret
127 |
128 | ;------------------------------------------------------------------------------
129 | ; Interrupt start processing.
130 | ;------------------------------------------------------------------------------
131 |
132 | _Irq_Handler:
133 | ;Save used registers.
134 | pushsp r5, r19
135 | $nowarning
136 | pushsp r1, r2
137 | $warning
138 |
139 | stsr EIPSW, r19
140 | stsr EIPC, r18
141 | stsr EIIC, r17
142 | mov lp, r16
143 | mov ep, r15
144 |
145 | pushsp r15, r19
146 |
147 | ;Increment nesting count.
148 | mov #_xInterruptNesting, r19
149 | ld.w 0[r19], r18
150 | addi 0x1, r18, r17
151 | st.w r17, 0[r19]
152 |
153 | pushsp r18, r19
154 |
155 | ;Call the interrupt handler.
156 | stsr EIIC, r6
157 | andi EIIC_MSK, r6, r6
158 | jarl _bsp_common_interrupt_handler, lp
159 | synce
160 | popsp r18, r19
161 |
162 | ;Restore the old nesting count.
163 | st.w r18, 0[r19]
164 |
165 | ;A context switch if no nesting interrupt.
166 | cmp 0x0, r18
167 | bne exit_without_switch
168 |
169 | ;Check if context switch is requested.
170 | mov #_xPortSwitchRequired, r19
171 | ld.w 0[r19], r18
172 | cmp 0x0, r18
173 | bne switch_before_exit
174 |
175 | exit_without_switch:
176 | ;No context switch. Restore used registers
177 | popsp r15, r19
178 |
179 | mov r15, ep
180 | mov r16, lp
181 | ldsr r17, EIIC
182 | ldsr r18, EIPC
183 | ldsr r19, EIPSW
184 |
185 | $nowarning
186 | popsp r1, r2
187 | $warning
188 | popsp r5, r19
189 |
190 | eiret
191 |
192 | switch_before_exit:
193 | ;Clear the context switch pending flag.
194 | st.w r0, 0[r19]
195 |
196 | ;Restore used registers before saving the context to the task stack.
197 | popsp r15, r19
198 |
199 | mov r15, ep
200 | mov r16, lp
201 | ldsr r17, EIIC
202 | ldsr r18, EIPC
203 | ldsr r19, EIPSW
204 |
205 | $nowarning
206 | popsp r1, r2
207 | $warning
208 | popsp r5, r19
209 |
210 | portSAVE_CONTEXT
211 | jarl _vTaskSwitchContext, lp
212 | portRESTORE_CONTEXT
213 |
214 | eiret
215 |
216 |
--------------------------------------------------------------------------------
/CCS/C2000_C28x/port.c:
--------------------------------------------------------------------------------
1 | //-------------------------------------------------------------------------------------------------
2 | // Author: Ivan Zaitsev, ivan.zaitsev@gmail.com
3 | //
4 | // This file follows the FreeRTOS distribution license.
5 | //
6 | // FreeRTOS is free software; you can redistribute it and/or modify it under
7 | // the terms of the GNU General Public License (version 2) as published by the
8 | // Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.
9 | //
10 | // ***************************************************************************
11 | // >>! NOTE: The modification to the GPL is included to allow you to !<<
12 | // >>! distribute a combined work that includes FreeRTOS without being !<<
13 | // >>! obliged to provide the source code for proprietary components !<<
14 | // >>! outside of the FreeRTOS kernel. !<<
15 | // ***************************************************************************
16 | //
17 | // FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
18 | // WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
19 | // FOR A PARTICULAR PURPOSE. Full license text is available on the following
20 | // link: http://www.freertos.org/a00114.html
21 | //-------------------------------------------------------------------------------------------------
22 |
23 | //-------------------------------------------------------------------------------------------------
24 | // Scheduler includes.
25 | //-------------------------------------------------------------------------------------------------
26 | #include "FreeRTOS.h"
27 | #include "task.h"
28 |
29 | //-------------------------------------------------------------------------------------------------
30 | // Implementation of functions defined in portable.h for the C28x port.
31 | //-------------------------------------------------------------------------------------------------
32 |
33 | // Constants required for hardware setup.
34 | #define portINITIAL_CRITICAL_NESTING ( ( uint16_t ) 10 )
35 | #define portFLAGS_INT_ENABLED ( ( StackType_t ) 0x08 )
36 | #if defined(__TMS320C28XX_FPU64__)
37 | # define AUX_REGISTERS_TO_SAVE 27 // XAR + FPU registers
38 | # define XAR4_REGISTER_POSITION 6 // XAR4 position in AUX registers array
39 | # define STF_REGISTER_POSITION 10 // STF position in AUX registers array
40 | #elif defined(__TMS320C28XX_FPU32__)
41 | # define AUX_REGISTERS_TO_SAVE 19 // XAR + FPU registers
42 | # define XAR4_REGISTER_POSITION 6 // XAR4 position in AUX registers array
43 | # define STF_REGISTER_POSITION 10 // STF position in AUX registers array
44 | #else
45 | # define AUX_REGISTERS_TO_SAVE 9 // XAR registers only
46 | # define XAR4_REGISTER_POSITION 5 // XAR4 position in AUX registers array
47 | #endif
48 |
49 | extern uint32_t getSTF( void );
50 | extern void vApplicationSetupTimerInterrupt( void );
51 |
52 | // Each task maintains a count of the critical section nesting depth. Each
53 | // time a critical section is entered the count is incremented. Each time a
54 | // critical section is exited the count is decremented - with interrupts only
55 | // being re-enabled if the count is zero.
56 | //
57 | // ulCriticalNesting will get set to zero when the scheduler starts, but must
58 | // not be initialised to zero as this will cause problems during the startup
59 | // sequence.
60 | // ulCriticalNesting should be 32 bit value to keep stack alignment unchanged.
61 | volatile uint32_t ulCriticalNesting = portINITIAL_CRITICAL_NESTING;
62 | volatile uint16_t bYield = 0;
63 | volatile uint16_t bPreemptive = 0;
64 |
65 | //-------------------------------------------------------------------------------------------------
66 | // Initialise the stack of a task to look exactly as if
67 | // timer interrupt was executed.
68 | //-------------------------------------------------------------------------------------------------
69 | StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
70 | {
71 | uint16_t i;
72 | uint16_t base = 0;
73 |
74 | pxTopOfStack[base++] = 0x0080; // ST0. PSM = 0(No shift)
75 | pxTopOfStack[base++] = 0x0000; // T
76 | pxTopOfStack[base++] = 0x0000; // AL
77 | pxTopOfStack[base++] = 0x0000; // AH
78 | pxTopOfStack[base++] = 0xFFFF; // PL
79 | pxTopOfStack[base++] = 0xFFFF; // PH
80 | pxTopOfStack[base++] = 0xFFFF; // AR0
81 | pxTopOfStack[base++] = 0xFFFF; // AR1
82 | pxTopOfStack[base++] = 0x8A08; // ST1
83 | pxTopOfStack[base++] = 0x0000; // DP
84 | pxTopOfStack[base++] = 0x0000; // IER
85 | pxTopOfStack[base++] = 0x0000; // DBGSTAT
86 | pxTopOfStack[base++] = ((uint32_t)pxCode) & 0xFFFFU; // PCL
87 | pxTopOfStack[base++] = ((uint32_t)pxCode >> 16) & 0x00FFU; // PCH
88 | pxTopOfStack[base++] = 0xAAAA; // Alignment
89 | pxTopOfStack[base++] = 0xBBBB; // Alignment
90 |
91 | // Fill the rest of the registers with dummy values.
92 | for(i = 0; i < (2 * AUX_REGISTERS_TO_SAVE); i++)
93 | {
94 | uint16_t low = 0x0000;
95 | uint16_t high = 0x0000;
96 |
97 | if(i == (2 * XAR4_REGISTER_POSITION))
98 | {
99 | low = ((uint32_t)pvParameters) & 0xFFFFU;
100 | high = ((uint32_t)pvParameters >> 16) & 0xFFFFU;
101 | }
102 |
103 | #if defined(__TMS320C28XX_FPU32__)
104 | if(i == (2 * STF_REGISTER_POSITION))
105 | {
106 | uint32_t stf = getSTF();
107 |
108 | low = stf & 0xFFFFU;
109 | high = (stf >> 16) & 0xFFFFU;
110 | }
111 | #endif
112 |
113 | pxTopOfStack[base + i] = low;
114 | i++;
115 | pxTopOfStack[base + i] = high;
116 | }
117 |
118 | base += i;
119 |
120 | // Reserve place for ST1 which will be used in context switch
121 | // to set correct SPA bit ASAP.
122 | pxTopOfStack[base++] = 0x8A18; // ST1 with SPA bit set
123 | pxTopOfStack[base++] = 0x0000; // DP
124 | pxTopOfStack[base++] = 0x0000; // placeholder for 32 bit ulCriticalNesting
125 | pxTopOfStack[base++] = 0x0000;
126 |
127 | // Return a pointer to the top of the stack we have generated so this can
128 | // be stored in the task control block for the task.
129 | return pxTopOfStack + base;
130 | }
131 |
132 | //-------------------------------------------------------------------------------------------------
133 | void vPortEndScheduler( void )
134 | {
135 | // It is unlikely that the TMS320 port will get stopped.
136 | // If required simply disable the tick interrupt here.
137 | }
138 |
139 | //-------------------------------------------------------------------------------------------------
140 | // See header file for description.
141 | //-------------------------------------------------------------------------------------------------
142 | BaseType_t xPortStartScheduler(void)
143 | {
144 | vApplicationSetupTimerInterrupt();
145 |
146 | ulCriticalNesting = 0;
147 |
148 | #if(configUSE_PREEMPTION == 1)
149 | bPreemptive = 1;
150 | #else
151 | bPreemptive = 0;
152 | #endif
153 |
154 | portENABLE_INTERRUPTS();
155 | portRESTORE_FIRST_CONTEXT();
156 |
157 | // Should not get here!
158 | return pdFAIL;
159 | }
160 |
161 | //-------------------------------------------------------------------------------------------------
162 | void vPortEnterCritical( void )
163 | {
164 | portDISABLE_INTERRUPTS();
165 | ulCriticalNesting++;
166 | }
167 |
168 | //-------------------------------------------------------------------------------------------------
169 | void vPortExitCritical( void )
170 | {
171 | ulCriticalNesting--;
172 | if( ulCriticalNesting == 0 )
173 | {
174 | portENABLE_INTERRUPTS();
175 | }
176 | }
177 |
--------------------------------------------------------------------------------
/GCC/CORTEX_A9_Zynq7000/build/lscript.ld:
--------------------------------------------------------------------------------
1 | /*
2 | * Cortx-A9 linker script automatically generated under Vitis 2021.1
3 | *
4 | * Adapted to support FreeRTOS v11.1.0 Symmetric Multi-Processing
5 | *
6 | */
7 |
8 | _STACK_SIZE = DEFINED(_STACK_SIZE) ? _STACK_SIZE : 0x2000;
9 | _HEAP_SIZE = DEFINED(_HEAP_SIZE) ? _HEAP_SIZE : 0x2000;
10 |
11 | _ABORT_STACK_SIZE = DEFINED(_ABORT_STACK_SIZE) ? _ABORT_STACK_SIZE : 1024;
12 | _SUPERVISOR_STACK_SIZE = DEFINED(_SUPERVISOR_STACK_SIZE) ? _SUPERVISOR_STACK_SIZE : 2048;
13 | _IRQ_STACK_SIZE = DEFINED(_IRQ_STACK_SIZE) ? _IRQ_STACK_SIZE : 1024;
14 | _FIQ_STACK_SIZE = DEFINED(_FIQ_STACK_SIZE) ? _FIQ_STACK_SIZE : 1024;
15 | _UNDEF_STACK_SIZE = DEFINED(_UNDEF_STACK_SIZE) ? _UNDEF_STACK_SIZE : 1024;
16 |
17 | /* Define Memories in the system */
18 |
19 | MEMORY
20 | {
21 | ps7_ddr_0 : ORIGIN = 0x100000, LENGTH = 0x1FF00000
22 | ps7_qspi_linear_0 : ORIGIN = 0xFC000000, LENGTH = 0x1000000
23 | ps7_ram_0 : ORIGIN = 0x0, LENGTH = 0x30000
24 | ps7_ram_1 : ORIGIN = 0xFFFF0000, LENGTH = 0xFE00
25 | }
26 |
27 | /* Specify the default entry point to the program */
28 |
29 | ENTRY(_vector_table)
30 |
31 | /* Define the sections, and where they are mapped in memory */
32 |
33 | SECTIONS
34 | {
35 | .text : {
36 | KEEP (*(.vectors))
37 | *(.boot)
38 | *(.text)
39 | *(.text.*)
40 | *(.gnu.linkonce.t.*)
41 | *(.plt)
42 | *(.gnu_warning)
43 | *(.gcc_execpt_table)
44 | *(.glue_7)
45 | *(.glue_7t)
46 | *(.vfp11_veneer)
47 | *(.ARM.extab)
48 | *(.gnu.linkonce.armextab.*)
49 | } > ps7_ddr_0
50 |
51 | .init : {
52 | KEEP (*(.init))
53 | } > ps7_ddr_0
54 |
55 | .fini : {
56 | KEEP (*(.fini))
57 | } > ps7_ddr_0
58 |
59 | .rodata : {
60 | __rodata_start = .;
61 | *(.rodata)
62 | *(.rodata.*)
63 | *(.gnu.linkonce.r.*)
64 | __rodata_end = .;
65 | } > ps7_ddr_0
66 |
67 | .rodata1 : {
68 | __rodata1_start = .;
69 | *(.rodata1)
70 | *(.rodata1.*)
71 | __rodata1_end = .;
72 | } > ps7_ddr_0
73 |
74 | .sdata2 : {
75 | __sdata2_start = .;
76 | *(.sdata2)
77 | *(.sdata2.*)
78 | *(.gnu.linkonce.s2.*)
79 | __sdata2_end = .;
80 | } > ps7_ddr_0
81 |
82 | .sbss2 : {
83 | __sbss2_start = .;
84 | *(.sbss2)
85 | *(.sbss2.*)
86 | *(.gnu.linkonce.sb2.*)
87 | __sbss2_end = .;
88 | } > ps7_ddr_0
89 |
90 | .data : {
91 | __data_start = .;
92 | *(.data)
93 | *(.data.*)
94 | *(.gnu.linkonce.d.*)
95 | *(.jcr)
96 | *(.got)
97 | *(.got.plt)
98 | __data_end = .;
99 | } > ps7_ddr_0
100 |
101 | .data1 : {
102 | __data1_start = .;
103 | *(.data1)
104 | *(.data1.*)
105 | __data1_end = .;
106 | } > ps7_ddr_0
107 |
108 | .got : {
109 | *(.got)
110 | } > ps7_ddr_0
111 |
112 | .note.gnu.build-id : {
113 | KEEP (*(.note.gnu.build-id))
114 | } > ps7_ddr_0
115 |
116 | .ctors : {
117 | __CTOR_LIST__ = .;
118 | ___CTORS_LIST___ = .;
119 | KEEP (*crtbegin.o(.ctors))
120 | KEEP (*(EXCLUDE_FILE(*crtend.o) .ctors))
121 | KEEP (*(SORT(.ctors.*)))
122 | KEEP (*(.ctors))
123 | __CTOR_END__ = .;
124 | ___CTORS_END___ = .;
125 | } > ps7_ddr_0
126 |
127 | .dtors : {
128 | __DTOR_LIST__ = .;
129 | ___DTORS_LIST___ = .;
130 | KEEP (*crtbegin.o(.dtors))
131 | KEEP (*(EXCLUDE_FILE(*crtend.o) .dtors))
132 | KEEP (*(SORT(.dtors.*)))
133 | KEEP (*(.dtors))
134 | __DTOR_END__ = .;
135 | ___DTORS_END___ = .;
136 | } > ps7_ddr_0
137 |
138 | .fixup : {
139 | __fixup_start = .;
140 | *(.fixup)
141 | __fixup_end = .;
142 | } > ps7_ddr_0
143 |
144 | .eh_frame : {
145 | *(.eh_frame)
146 | } > ps7_ddr_0
147 |
148 | .eh_framehdr : {
149 | __eh_framehdr_start = .;
150 | *(.eh_framehdr)
151 | __eh_framehdr_end = .;
152 | } > ps7_ddr_0
153 |
154 | .gcc_except_table : {
155 | *(.gcc_except_table)
156 | } > ps7_ddr_0
157 |
158 | .mmu_tbl (ALIGN(16384)) : {
159 | __mmu_tbl_start = .;
160 | *(.mmu_tbl)
161 | __mmu_tbl_end = .;
162 | } > ps7_ddr_0
163 |
164 | .ARM.exidx : {
165 | __exidx_start = .;
166 | *(.ARM.exidx*)
167 | *(.gnu.linkonce.armexidix.*.*)
168 | __exidx_end = .;
169 | } > ps7_ddr_0
170 |
171 | .preinit_array : {
172 | __preinit_array_start = .;
173 | KEEP (*(SORT(.preinit_array.*)))
174 | KEEP (*(.preinit_array))
175 | __preinit_array_end = .;
176 | } > ps7_ddr_0
177 |
178 | .init_array : {
179 | __init_array_start = .;
180 | KEEP (*(SORT(.init_array.*)))
181 | KEEP (*(.init_array))
182 | __init_array_end = .;
183 | } > ps7_ddr_0
184 |
185 | .fini_array : {
186 | __fini_array_start = .;
187 | KEEP (*(SORT(.fini_array.*)))
188 | KEEP (*(.fini_array))
189 | __fini_array_end = .;
190 | } > ps7_ddr_0
191 |
192 | .ARM.attributes : {
193 | __ARM.attributes_start = .;
194 | *(.ARM.attributes)
195 | __ARM.attributes_end = .;
196 | } > ps7_ddr_0
197 |
198 | .sdata : {
199 | __sdata_start = .;
200 | *(.sdata)
201 | *(.sdata.*)
202 | *(.gnu.linkonce.s.*)
203 | __sdata_end = .;
204 | } > ps7_ddr_0
205 |
206 | .sbss (NOLOAD) : {
207 | __sbss_start = .;
208 | *(.sbss)
209 | *(.sbss.*)
210 | *(.gnu.linkonce.sb.*)
211 | __sbss_end = .;
212 | } > ps7_ddr_0
213 |
214 | .tdata : {
215 | __tdata_start = .;
216 | *(.tdata)
217 | *(.tdata.*)
218 | *(.gnu.linkonce.td.*)
219 | __tdata_end = .;
220 | } > ps7_ddr_0
221 |
222 | .tbss : {
223 | __tbss_start = .;
224 | *(.tbss)
225 | *(.tbss.*)
226 | *(.gnu.linkonce.tb.*)
227 | __tbss_end = .;
228 | } > ps7_ddr_0
229 |
230 | .bss (NOLOAD) : {
231 | __bss_start = .;
232 | *(.bss)
233 | *(.bss.*)
234 | *(.gnu.linkonce.b.*)
235 | *(COMMON)
236 | __bss_end = .;
237 | } > ps7_ddr_0
238 |
239 | _SDA_BASE_ = __sdata_start + ((__sbss_end - __sdata_start) / 2 );
240 |
241 | _SDA2_BASE_ = __sdata2_start + ((__sbss2_end - __sdata2_start) / 2 );
242 |
243 | /* Generate Stack and Heap definitions */
244 |
245 | .heap (NOLOAD) : {
246 | . = ALIGN(16);
247 | _heap = .;
248 | HeapBase = .;
249 | _heap_start = .;
250 | . += _HEAP_SIZE;
251 | _heap_end = .;
252 | HeapLimit = .;
253 | } > ps7_ddr_0
254 |
255 | /* CORE0 modes stack */
256 | .stack (NOLOAD) : {
257 | . = ALIGN(16);
258 | _stack_end = .;
259 | . += _STACK_SIZE;
260 | . = ALIGN(16);
261 | _stack = .;
262 | __stack = _stack;
263 | . = ALIGN(16);
264 | _irq_stack_end = .;
265 | . += _IRQ_STACK_SIZE;
266 | . = ALIGN(16);
267 | __irq_stack = .;
268 | _supervisor_stack_end = .;
269 | . += _SUPERVISOR_STACK_SIZE;
270 | . = ALIGN(16);
271 | __supervisor_stack = .;
272 | _abort_stack_end = .;
273 | . += _ABORT_STACK_SIZE;
274 | . = ALIGN(16);
275 | __abort_stack = .;
276 | _fiq_stack_end = .;
277 | . += _FIQ_STACK_SIZE;
278 | . = ALIGN(16);
279 | __fiq_stack = .;
280 | _undef_stack_end = .;
281 | . += _UNDEF_STACK_SIZE;
282 | . = ALIGN(16);
283 | __undef_stack = .;
284 | } > ps7_ddr_0
285 |
286 | /* CORE1 modes stack */
287 | .stack1 (NOLOAD) : {
288 | . = ALIGN(16);
289 | _stack1_end = .;
290 | . += _STACK_SIZE;
291 | . = ALIGN(16);
292 | _stack1 = .;
293 | __stack1 = _stack1;
294 | . = ALIGN(16);
295 | _irq_stack1_end = .;
296 | . += _IRQ_STACK_SIZE;
297 | . = ALIGN(16);
298 | __irq_stack1 = .;
299 | _supervisor_stack1_end = .;
300 | . += _SUPERVISOR_STACK_SIZE;
301 | . = ALIGN(16);
302 | __supervisor_stack1 = .;
303 | _abort_stack1_end = .;
304 | . += _ABORT_STACK_SIZE;
305 | . = ALIGN(16);
306 | __abort_stack1 = .;
307 | _fiq_stack1_end = .;
308 | . += _FIQ_STACK_SIZE;
309 | . = ALIGN(16);
310 | __fiq_stack1 = .;
311 | _undef_stack1_end = .;
312 | . += _UNDEF_STACK_SIZE;
313 | . = ALIGN(16);
314 | __undef_stack1 = .;
315 | } > ps7_ddr_0
316 |
317 |
318 | _end = .;
319 | }
320 |
321 |
--------------------------------------------------------------------------------
/GCC/CORTEX_A53_64-bit_UltraScale_MPSoC/bsp_patches/cpu.c:
--------------------------------------------------------------------------------
1 | /******************************************************************************
2 | * Copyright (c) 2024 - 2028 MindCurise, Inc. All rights reserved.
3 | * SPDX-License-Identifier: MIT
4 |
5 | * Ver Who Date Changes
6 | * ----- ---- -------- -------------------------------------------------------
7 | * 1.00 yafeng.yun 5/31/24 Initial version
8 | ******************************************************************************/
9 |
10 | #include "cpu.h"
11 |
12 | #define CPU_OK 0
13 | #define CPU_FAIL 1
14 |
15 | #define CPU_A53_0 (uint32_t)(0x0u)
16 | #define CPU_A53_1 (uint32_t)(0x1u)
17 | #define CPU_A53_2 (uint32_t)(0x2u)
18 | #define CPU_A53_3 (uint32_t)(0x3u)
19 |
20 |
21 |
22 | static uint32_t PowerUpIsland(uint32_t PwrIslandMask)
23 | {
24 | uint32_t RegVal;
25 | uint32_t Status = CPU_OK;
26 |
27 | /* Power up request enable */
28 | Xil_Out32(PMU_GLOBAL_REQ_PWRUP_INT_EN, PwrIslandMask);
29 |
30 | /* Trigger power up request */
31 | Xil_Out32(PMU_GLOBAL_REQ_PWRUP_TRIG, PwrIslandMask);
32 |
33 | /* Poll for Power up complete */
34 | do {
35 | RegVal = Xil_In32(PMU_GLOBAL_REQ_PWRUP_STATUS) & PwrIslandMask;
36 | } while (RegVal != 0x0U);
37 |
38 | return Status;
39 | }
40 |
41 | static uint32_t ReleaseReset_A53 (uint32_t CpuID)
42 | {
43 | uint32_t RegValue;
44 | uint32_t Status;
45 | uint32_t PwrStateMask;
46 | switch(CpuID)
47 | {
48 |
49 | case CPU_A53_0:
50 | PwrStateMask = PMU_GLOBAL_PWR_STATE_ACPU0_MASK | PMU_GLOBAL_PWR_STATE_FP_MASK | PMU_GLOBAL_PWR_STATE_L2_BANK0_MASK;
51 | Status = PowerUpIsland(PwrStateMask);
52 | if (Status != CPU_OK) {
53 | goto END;
54 | }
55 |
56 | /**
57 | * Enable the clock
58 | */
59 | RegValue = Xil_In32(CRF_APB_ACPU_CTRL);
60 | RegValue |= (CRF_APB_ACPU_CTRL_CLKACT_FULL_MASK | CRF_APB_ACPU_CTRL_CLKACT_HALF_MASK);
61 | Xil_Out32(CRF_APB_ACPU_CTRL, RegValue);
62 |
63 | /**
64 | * Release reset
65 | */
66 | RegValue = Xil_In32(CRF_APB_RST_FPD_APU);
67 | RegValue &= ~(CRF_APB_RST_FPD_APU_ACPU0_RESET_MASK | CRF_APB_RST_FPD_APU_APU_L2_RESET_MASK | CRF_APB_RST_FPD_APU_ACPU0_PWRON_RESET_MASK);
68 | Xil_Out32(CRF_APB_RST_FPD_APU, RegValue);
69 | break;
70 |
71 | case CPU_A53_1:
72 | PwrStateMask = PMU_GLOBAL_PWR_STATE_ACPU1_MASK | PMU_GLOBAL_PWR_STATE_FP_MASK | PMU_GLOBAL_PWR_STATE_L2_BANK0_MASK;
73 | Status = PowerUpIsland(PwrStateMask);
74 | if (Status != CPU_OK) {
75 | goto END;
76 | }
77 |
78 | /**
79 | * Enable the clock
80 | */
81 | RegValue = Xil_In32(CRF_APB_ACPU_CTRL);
82 | RegValue |= (CRF_APB_ACPU_CTRL_CLKACT_FULL_MASK | CRF_APB_ACPU_CTRL_CLKACT_HALF_MASK);
83 | Xil_Out32(CRF_APB_ACPU_CTRL, RegValue);
84 |
85 | /**
86 | * Release reset
87 | */
88 | RegValue = Xil_In32(CRF_APB_RST_FPD_APU);
89 | RegValue &= ~(CRF_APB_RST_FPD_APU_ACPU1_RESET_MASK | CRF_APB_RST_FPD_APU_APU_L2_RESET_MASK | CRF_APB_RST_FPD_APU_ACPU1_PWRON_RESET_MASK);
90 | Xil_Out32(CRF_APB_RST_FPD_APU, RegValue);
91 | break;
92 |
93 | case CPU_A53_2:
94 | PwrStateMask = PMU_GLOBAL_PWR_STATE_ACPU2_MASK | PMU_GLOBAL_PWR_STATE_FP_MASK | PMU_GLOBAL_PWR_STATE_L2_BANK0_MASK;
95 | Status = PowerUpIsland(PwrStateMask);
96 | if (Status != CPU_OK) {
97 | goto END;
98 | }
99 |
100 | /**
101 | * Enable the clock
102 | */
103 | RegValue = Xil_In32(CRF_APB_ACPU_CTRL);
104 | RegValue |= (CRF_APB_ACPU_CTRL_CLKACT_FULL_MASK | CRF_APB_ACPU_CTRL_CLKACT_HALF_MASK);
105 | Xil_Out32(CRF_APB_ACPU_CTRL, RegValue);
106 |
107 | /**
108 | * Release reset
109 | */
110 | RegValue = Xil_In32(CRF_APB_RST_FPD_APU);
111 | RegValue &= ~(CRF_APB_RST_FPD_APU_ACPU2_RESET_MASK | CRF_APB_RST_FPD_APU_APU_L2_RESET_MASK | CRF_APB_RST_FPD_APU_ACPU2_PWRON_RESET_MASK);
112 | Xil_Out32(CRF_APB_RST_FPD_APU, RegValue);
113 | break;
114 |
115 | case CPU_A53_3:
116 | PwrStateMask = PMU_GLOBAL_PWR_STATE_ACPU3_MASK | PMU_GLOBAL_PWR_STATE_FP_MASK | PMU_GLOBAL_PWR_STATE_L2_BANK0_MASK;
117 | Status = PowerUpIsland(PwrStateMask);
118 | if (Status != CPU_OK) {
119 | goto END;
120 | }
121 |
122 | /**
123 | * Enable the clock
124 | */
125 | RegValue = Xil_In32(CRF_APB_ACPU_CTRL);
126 | RegValue |= (CRF_APB_ACPU_CTRL_CLKACT_FULL_MASK | CRF_APB_ACPU_CTRL_CLKACT_HALF_MASK);
127 | Xil_Out32(CRF_APB_ACPU_CTRL, RegValue);
128 |
129 | /**
130 | * Release reset
131 | */
132 | RegValue = Xil_In32(CRF_APB_RST_FPD_APU);
133 | RegValue &= ~(CRF_APB_RST_FPD_APU_ACPU3_RESET_MASK | CRF_APB_RST_FPD_APU_APU_L2_RESET_MASK | CRF_APB_RST_FPD_APU_ACPU3_PWRON_RESET_MASK);
134 | Xil_Out32(CRF_APB_RST_FPD_APU, RegValue);
135 | break;
136 |
137 | default:
138 | Status = CPU_FAIL;
139 | break;
140 | }
141 |
142 | END:
143 | return Status;
144 | }
145 |
146 | static void SetCoreResetVector_A53 (uint32_t CpuID, uint64_t VectorAddr)
147 | {
148 | uint32_t VectorAddrLow;
149 | uint32_t VectorAddrHigh;
150 | uint32_t LowAddressReg;
151 | uint32_t HighAddressReg;
152 |
153 | /**
154 | * for A53 cpu, write 64bit handoff address
155 | * to the RVBARADDR in APU
156 | */
157 | VectorAddrLow = (uint32_t )(VectorAddr & 0xFFFFFFFFU);
158 | VectorAddrHigh = (uint32_t )((VectorAddr>>32) & 0xFFFFFFFFU);
159 | switch (CpuID)
160 | {
161 | case CPU_A53_0:
162 | LowAddressReg = APU_RVBARADDR0L;
163 | HighAddressReg = APU_RVBARADDR0H;
164 | break;
165 | case CPU_A53_1:
166 | LowAddressReg = APU_RVBARADDR1L;
167 | HighAddressReg = APU_RVBARADDR1H;
168 | break;
169 | case CPU_A53_2:
170 | LowAddressReg = APU_RVBARADDR2L;
171 | HighAddressReg = APU_RVBARADDR2H;
172 | break;
173 | case CPU_A53_3:
174 | LowAddressReg = APU_RVBARADDR3L;
175 | HighAddressReg = APU_RVBARADDR3H;
176 | break;
177 |
178 | default:
179 | /**
180 | * error can be triggered here
181 | */
182 | LowAddressReg = 0U;
183 | HighAddressReg = 0U;
184 | break;
185 | }
186 | Xil_Out32(LowAddressReg, VectorAddrLow);
187 | Xil_Out32(HighAddressReg, VectorAddrHigh);
188 |
189 | return;
190 | }
191 |
192 |
193 | uint32_t CpuUp_A53(uint32_t CpuID, uint64_t ResetAddress)
194 | {
195 | Xil_DCacheDisable();
196 |
197 | // Step 1: Setup Reset vector of the core
198 | SetCoreResetVector_A53(CpuID, ResetAddress);
199 |
200 | // Step 2: Take the core out of reset
201 | ReleaseReset_A53(CpuID);
202 |
203 | Xil_DCacheEnable();
204 |
205 | return 0;
206 | }
207 |
208 |
209 | void StartAndWaitSecondaryCpuUp(uint64_t CpuID, uint64_t ResetAddr)
210 | {
211 | static volatile uint32_t CpuUpFlags[4] = {0};
212 | if (CpuID == 0)
213 | {
214 | CpuUpFlags[CpuID] = 1;
215 | for (CpuID = 1; CpuID < 4; ++CpuID)
216 | {
217 |
218 | extern void Xil_Assert(const char *File, int32_t Line);
219 | if (CpuUp_A53((uint32_t)CpuID, ResetAddr) != 0)
220 | {
221 | Xil_Assert(__FILE__, __LINE__);
222 | }
223 | }
224 |
225 | // Wait for secondary CPUs up
226 | int CpuIndx = 0;
227 | while (CpuIndx < 4)
228 | {
229 | if (CpuUpFlags[CpuIndx] != 0)
230 | {
231 | CpuIndx++;
232 | }
233 | }
234 | }
235 | else
236 | {
237 | CpuUpFlags[CpuID] = 1;
238 | }
239 | }
240 |
241 |
--------------------------------------------------------------------------------
/GCC/TriCore_38xa/portmacro.h:
--------------------------------------------------------------------------------
1 | /*
2 | * FreeRTOS Kernel V10.4.1
3 | * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
4 | *
5 | * Permission is hereby granted, free of charge, to any person obtaining a copy of
6 | * this software and associated documentation files (the "Software"), to deal in
7 | * the Software without restriction, including without limitation the rights to
8 | * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
9 | * the Software, and to permit persons to whom the Software is furnished to do so,
10 | * subject to the following conditions:
11 | *
12 | * The above copyright notice and this permission notice shall be included in all
13 | * copies or substantial portions of the Software.
14 | *
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
17 | * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
18 | * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
19 | * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
20 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
21 | *
22 | * https://www.FreeRTOS.org
23 | * https://github.com/FreeRTOS
24 | *
25 | * 1 tab == 4 spaces!
26 | */
27 |
28 | #ifndef _PORTABLE_GCC_TRICORE_PORTMACRO_H_
29 | #define _PORTABLE_GCC_TRICORE_PORTMACRO_H_
30 |
31 | /* *INDENT-OFF* */
32 | #ifdef __cplusplus
33 | extern "C" {
34 | #endif
35 | /* *INDENT-ON* */
36 |
37 | #include "port.h"
38 |
39 | /* System Includes. */
40 | #include
41 | #include
42 |
43 | /*-----------------------------------------------------------
44 | * Port specific definitions.
45 | *
46 | * The settings in this file configure FreeRTOS correctly for the
47 | * given hardware and compiler.
48 | *
49 | * These settings should not be altered.
50 | *-----------------------------------------------------------
51 | */
52 |
53 | /* Type definitions. */
54 | #define portCHAR char
55 | #define portFLOAT float
56 | #define portDOUBLE double
57 | #define portLONG long
58 | #define portSHORT short
59 | #define portSTACK_TYPE uint32_t
60 | #define portBASE_TYPE unsigned long
61 |
62 | typedef portSTACK_TYPE StackType_t;
63 | typedef long BaseType_t;
64 | typedef unsigned long UBaseType_t;
65 |
66 | #if( configUSE_16_BIT_TICKS == 1 )
67 | typedef uint16_t TickType_t;
68 | #define portMAX_DELAY ( TickType_t ) 0xffff
69 | #else
70 | typedef uint32_t TickType_t;
71 | #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
72 |
73 | /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
74 | not need to be guarded with a critical section. */
75 | #define portTICK_TYPE_IS_ATOMIC 1
76 | #endif
77 | /*---------------------------------------------------------------------------*/
78 |
79 | /* Architecture specifics. */
80 | #define portSTACK_GROWTH ( -1 )
81 | #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
82 | #define portBYTE_ALIGNMENT 4
83 | #define portNOP() __asm volatile( " nop " )
84 | #define portCRITICAL_NESTING_IN_TCB 1
85 | #define portRESTORE_FIRST_TASK_PRIORITY_LEVEL 1
86 |
87 |
88 | /*---------------------------------------------------------------------------*/
89 |
90 | typedef struct MPU_SETTINGS { uint32_t ulNotUsed; } xMPU_SETTINGS;
91 |
92 | /* Define away the instruction from the Restore Context Macro. */
93 | #define portPRIVILEGE_BIT 0x0UL
94 |
95 | #define portCCPN_MASK ( 0x000000FFUL )
96 |
97 | extern void vTaskEnterCritical( void );
98 | extern void vTaskExitCritical( void );
99 | #define portENTER_CRITICAL() vTaskEnterCritical()
100 | #define portEXIT_CRITICAL() vTaskExitCritical()
101 | /*---------------------------------------------------------------------------*/
102 |
103 | /* CSA Manipulation. */
104 | #define portCSA_TO_ADDRESS( pCSA ) ( ( uint32_t * )( ( ( ( pCSA ) & 0x000F0000 ) << 12 ) | ( ( ( pCSA ) & 0x0000FFFF ) << 6 ) ) )
105 | #define portADDRESS_TO_CSA( pAddress ) ( ( uint32_t )( ( ( ( (uint32_t)( pAddress ) ) & 0xF0000000 ) >> 12 ) | ( ( ( uint32_t )( pAddress ) & 0x003FFFC0 ) >> 6 ) ) )
106 | /*---------------------------------------------------------------------------*/
107 |
108 | #define portYIELD() _syscall( 0 )
109 | /* Port Restore is implicit in the platform when the function is returned from the original PSW is automatically replaced. */
110 | #define portSYSCALL_TASK_YIELD 0
111 | #define portSYSCALL_RAISE_PRIORITY 1
112 | /*---------------------------------------------------------------------------*/
113 |
114 | /* Critical section management. */
115 |
116 | /* Set ICR.CCPN to configMAX_SYSCALL_INTERRUPT_PRIORITY. */
117 | #define portDISABLE_INTERRUPTS() { \
118 | uint32_t ulICR; \
119 | _disable(); \
120 | ulICR = __MFCR( $ICR ); /* Get current ICR value. */ \
121 | ulICR &= ~portCCPN_MASK; /* Clear down mask bits. */ \
122 | ulICR |= configMAX_SYSCALL_INTERRUPT_PRIORITY; /* Set mask bits to required priority mask. */ \
123 | _mtcr( $ICR, ulICR ); /* Write back updated ICR. */ \
124 | _isync(); \
125 | _enable(); \
126 | }
127 |
128 | /* Clear ICR.CCPN to allow all interrupt priorities. */
129 | #define portENABLE_INTERRUPTS() { \
130 | uint32_t ulICR; \
131 | _disable(); \
132 | ulICR = __MFCR( $ICR ); /* Get current ICR value. */ \
133 | ulICR &= ~portCCPN_MASK; /* Clear down mask bits. */ \
134 | _mtcr( $ICR, ulICR ); /* Write back updated ICR. */ \
135 | _isync(); \
136 | _enable(); \
137 | }
138 |
139 | /* Set ICR.CCPN to uxSavedMaskValue. */
140 | #define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedMaskValue ) { \
141 | uint32_t ulICR; \
142 | _disable(); \
143 | ulICR = __MFCR( $ICR ); /* Get current ICR value. */ \
144 | ulICR &= ~portCCPN_MASK; /* Clear down mask bits. */ \
145 | ulICR |= uxSavedMaskValue; /* Set mask bits to previously saved mask value. */ \
146 | _mtcr( $ICR, ulICR ); /* Write back updated ICR. */ \
147 | _isync(); \
148 | _enable(); \
149 | }
150 |
151 |
152 | /* Set ICR.CCPN to configMAX_SYSCALL_INTERRUPT_PRIORITY */
153 | extern uint32_t uxPortSetInterruptMaskFromISR( void );
154 | #define portSET_INTERRUPT_MASK_FROM_ISR() uxPortSetInterruptMaskFromISR()
155 |
156 | /* Pend a priority 1 interrupt, which will take care of the context switch. */
157 | #define portYIELD_FROM_ISR( xHigherPriorityTaskWoken ) if( xHigherPriorityTaskWoken != pdFALSE ) { _isync(); }
158 |
159 | /*---------------------------------------------------------------------------*/
160 |
161 | /* Task function macros as described on the FreeRTOS.org WEB site. */
162 | #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
163 | #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
164 | /*---------------------------------------------------------------------------*/
165 |
166 | /*
167 | * Port specific clean up macro required to free the CSAs that were consumed by
168 | * a task that has since been deleted.
169 | */
170 | void vPortReclaimCSA( uint32_t *pxTCB );
171 | #define portCLEAN_UP_TCB( pxTCB ) vPortReclaimCSA( ( uint32_t * ) ( pxTCB ) )
172 |
173 | /* *INDENT-OFF* */
174 | #ifdef __cplusplus
175 | }
176 | #endif
177 | /* *INDENT-ON* */
178 |
179 | #endif /* _PORTABLE_GCC_TRICORE_PORTMACRO_H_ */
180 |
--------------------------------------------------------------------------------
/GCC/RISC-V/chip_specific_extensions/THEAD_RV32/freertos_risc_v_chip_specific_extensions.h:
--------------------------------------------------------------------------------
1 | /*
2 | * FreeRTOS Kernel V10.4.0
3 | * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
4 | *
5 | * Permission is hereby granted, free of charge, to any person obtaining a copy of
6 | * this software and associated documentation files (the "Software"), to deal in
7 | * the Software without restriction, including without limitation the rights to
8 | * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
9 | * the Software, and to permit persons to whom the Software is furnished to do so,
10 | * subject to the following conditions:
11 | *
12 | * The above copyright notice and this permission notice shall be included in all
13 | * copies or substantial portions of the Software.
14 | *
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
17 | * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
18 | * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
19 | * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
20 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
21 | *
22 | * https://www.FreeRTOS.org
23 | * https://github.com/FreeRTOS
24 | *
25 | * 1 tab == 4 spaces!
26 | */
27 |
28 | /*
29 | * The FreeRTOS kernel's RISC-V port is split between the the code that is
30 | * common across all currently supported RISC-V chips (implementations of the
31 | * RISC-V ISA), and code that tailors the port to a specific RISC-V chip:
32 | *
33 | * + FreeRTOS\Source\portable\GCC\RISC-V-RV32\portASM.S contains the code that
34 | * is common to all currently supported RISC-V chips. There is only one
35 | * portASM.S file because the same file is built for all RISC-V target chips.
36 | *
37 | * + Header files called freertos_risc_v_chip_specific_extensions.h contain the
38 | * code that tailors the FreeRTOS kernel's RISC-V port to a specific RISC-V
39 | * chip. There are multiple freertos_risc_v_chip_specific_extensions.h files
40 | * as there are multiple RISC-V chip implementations.
41 | *
42 | * !!!NOTE!!!
43 | * TAKE CARE TO INCLUDE THE CORRECT freertos_risc_v_chip_specific_extensions.h
44 | * HEADER FILE FOR THE CHIP IN USE. This is done using the assembler's (not the
45 | * compiler's!) include path. For example, if the chip in use includes a core
46 | * local interrupter (CLINT) and does not include any chip specific register
47 | * extensions then add the path below to the assembler's include path:
48 | * FreeRTOS\Source\portable\GCC\RISC-V-RV32\chip_specific_extensions\RV32I_CLINT_no_extensions
49 | *
50 | */
51 |
52 |
53 | #ifndef __FREERTOS_RISC_V_EXTENSIONS_H__
54 | #define __FREERTOS_RISC_V_EXTENSIONS_H__
55 |
56 | #define portasmHANDLE_INTERRUPT Default_IRQHandler
57 | #define portasmHAS_SIFIVE_CLINT 1
58 | #define portasmHAS_MTIME 0
59 | #define portasmADDITIONAL_CONTEXT_SIZE 0 /* Must be even number on 32-bit cores. */
60 |
61 | .macro portasmSAVE_ADDITIONAL_REGISTERS
62 | /* save float registers */
63 | #if __riscv_flen == 64
64 | addi sp, sp, -(128+128)
65 |
66 | fsd f31, (0 + 0 )(sp)
67 | fsd f30, (4 + 4 )(sp)
68 | fsd f29, (8 + 8 )(sp)
69 | fsd f28, (12 + 12)(sp)
70 | fsd f27, (16 + 16)(sp)
71 | fsd f26, (20 + 20)(sp)
72 | fsd f25, (24 + 24)(sp)
73 | fsd f24, (28 + 28)(sp)
74 | fsd f23, (32 + 32)(sp)
75 | fsd f22, (36 + 36)(sp)
76 | fsd f21, (40 + 40)(sp)
77 | fsd f20, (44 + 44)(sp)
78 | fsd f19, (48 + 48)(sp)
79 | fsd f18, (52 + 52)(sp)
80 | fsd f17, (56 + 56)(sp)
81 | fsd f16, (60 + 60)(sp)
82 | fsd f15, (64 + 64)(sp)
83 | fsd f14, (68 + 68)(sp)
84 | fsd f13, (72 + 72)(sp)
85 | fsd f12, (76 + 76)(sp)
86 | fsd f11, (80 + 80)(sp)
87 | fsd f10, (84 + 84)(sp)
88 | fsd f9, (88 + 88)(sp)
89 | fsd f8, (92 + 92)(sp)
90 | fsd f7, (96 + 96)(sp)
91 | fsd f6, (100+100)(sp)
92 | fsd f5, (104+104)(sp)
93 | fsd f4, (108+108)(sp)
94 | fsd f3, (112+112)(sp)
95 | fsd f2, (116+116)(sp)
96 | fsd f1, (120+120)(sp)
97 | fsd f0, (124+124)(sp)
98 | #elif __riscv_flen == 32
99 | addi sp, sp, -(128)
100 |
101 | fsw f31, (0 )(sp)
102 | fsw f30, (4 )(sp)
103 | fsw f29, (8 )(sp)
104 | fsw f28, (12 )(sp)
105 | fsw f27, (16 )(sp)
106 | fsw f26, (20 )(sp)
107 | fsw f25, (24 )(sp)
108 | fsw f24, (28 )(sp)
109 | fsw f23, (32 )(sp)
110 | fsw f22, (36 )(sp)
111 | fsw f21, (40 )(sp)
112 | fsw f20, (44 )(sp)
113 | fsw f19, (48 )(sp)
114 | fsw f18, (52 )(sp)
115 | fsw f17, (56 )(sp)
116 | fsw f16, (60 )(sp)
117 | fsw f15, (64 )(sp)
118 | fsw f14, (68 )(sp)
119 | fsw f13, (72 )(sp)
120 | fsw f12, (76 )(sp)
121 | fsw f11, (80 )(sp)
122 | fsw f10, (84 )(sp)
123 | fsw f9, (88 )(sp)
124 | fsw f8, (92 )(sp)
125 | fsw f7, (96 )(sp)
126 | fsw f6, (100)(sp)
127 | fsw f5, (104)(sp)
128 | fsw f4, (108)(sp)
129 | fsw f3, (112)(sp)
130 | fsw f2, (116)(sp)
131 | fsw f1, (120)(sp)
132 | fsw f0, (124)(sp)
133 | #endif
134 | .endm
135 |
136 | .macro portasmRESTORE_ADDITIONAL_REGISTERS
137 | /* load float registers */
138 | #if __riscv_flen == 64
139 | fld f31, (0 + 0 )(sp)
140 | fld f30, (4 + 4 )(sp)
141 | fld f29, (8 + 8 )(sp)
142 | fld f28, (12 + 12)(sp)
143 | fld f27, (16 + 16)(sp)
144 | fld f26, (20 + 20)(sp)
145 | fld f25, (24 + 24)(sp)
146 | fld f24, (28 + 28)(sp)
147 | fld f23, (32 + 32)(sp)
148 | fld f22, (36 + 36)(sp)
149 | fld f21, (40 + 40)(sp)
150 | fld f20, (44 + 44)(sp)
151 | fld f19, (48 + 48)(sp)
152 | fld f18, (52 + 52)(sp)
153 | fld f17, (56 + 56)(sp)
154 | fld f16, (60 + 60)(sp)
155 | fld f15, (64 + 64)(sp)
156 | fld f14, (68 + 68)(sp)
157 | fld f13, (72 + 72)(sp)
158 | fld f12, (76 + 76)(sp)
159 | fld f11, (80 + 80)(sp)
160 | fld f10, (84 + 84)(sp)
161 | fld f9, (88 + 88)(sp)
162 | fld f8, (92 + 92)(sp)
163 | fld f7, (96 + 96)(sp)
164 | fld f6, (100+100)(sp)
165 | fld f5, (104+104)(sp)
166 | fld f4, (108+108)(sp)
167 | fld f3, (112+112)(sp)
168 | fld f2, (116+116)(sp)
169 | fld f1, (120+120)(sp)
170 | fld f0, (124+124)(sp)
171 |
172 | addi sp, sp, (128+128)
173 | #elif __riscv_flen == 32
174 | flw f31, (0 )(sp)
175 | flw f30, (4 )(sp)
176 | flw f29, (8 )(sp)
177 | flw f28, (12 )(sp)
178 | flw f27, (16 )(sp)
179 | flw f26, (20 )(sp)
180 | flw f25, (24 )(sp)
181 | flw f24, (28 )(sp)
182 | flw f23, (32 )(sp)
183 | flw f22, (36 )(sp)
184 | flw f21, (40 )(sp)
185 | flw f20, (44 )(sp)
186 | flw f19, (48 )(sp)
187 | flw f18, (52 )(sp)
188 | flw f17, (56 )(sp)
189 | flw f16, (60 )(sp)
190 | flw f15, (64 )(sp)
191 | flw f14, (68 )(sp)
192 | flw f13, (72 )(sp)
193 | flw f12, (76 )(sp)
194 | flw f11, (80 )(sp)
195 | flw f10, (84 )(sp)
196 | flw f9, (88 )(sp)
197 | flw f8, (92 )(sp)
198 | flw f7, (96 )(sp)
199 | flw f6, (100)(sp)
200 | flw f5, (104)(sp)
201 | flw f4, (108)(sp)
202 | flw f3, (112)(sp)
203 | flw f2, (116)(sp)
204 | flw f1, (120)(sp)
205 | flw f0, (124)(sp)
206 |
207 | addi sp, sp, (128)
208 | #endif
209 | .endm
210 | #endif /* __FREERTOS_RISC_V_EXTENSIONS_H__ */
211 |
--------------------------------------------------------------------------------
/GCC/CORTEX_A53_64-bit_UltraScale_MPSoC/port_asm_vectors.S:
--------------------------------------------------------------------------------
1 | /******************************************************************************
2 | *
3 | * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
4 | * Copyright (C) 2014 - 2020 Xilinx, Inc. All rights reserved.
5 | *
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy of
7 | * this software and associated documentation files (the "Software"), to deal in
8 | * the Software without restriction, including without limitation the rights to
9 | * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
10 | * the Software, and to permit persons to whom the Software is furnished to do so,
11 | * subject to the following conditions:
12 | *
13 | * The above copyright notice and this permission notice shall be included in all
14 | * copies or substantial portions of the Software.
15 | *
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
18 | * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
19 | * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
20 | * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
21 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
22 | *
23 | * http://www.FreeRTOS.org
24 | * http://aws.amazon.com/freertos
25 | *
26 | * 1 tab == 4 spaces!
27 | *
28 | ******************************************************************************/
29 | /*****************************************************************************/
30 | /**
31 | * @file asm_vectors.s
32 | *
33 | * This file contains the initial vector table for the Cortex A53 processor
34 | * Currently NEON registers are not saved on stack if interrupt is taken.
35 | * It will be implemented.
36 | *
37 | *
38 | * MODIFICATION HISTORY:
39 | *
40 | * Ver Who Date Changes
41 | * ----- ------- -------- ---------------------------------------------------
42 | * 5.00 pkp 5/21/14 Initial version
43 | *
44 | *
45 | * @note
46 | *
47 | * None.
48 | *
49 | ******************************************************************************/
50 |
51 | #if defined (versal) && !defined(ARMR5)
52 | #define GICv3
53 | #else
54 | #define GICv2
55 | #endif
56 |
57 |
58 | .org 0
59 | .text
60 |
61 | .globl _boot
62 | .globl _vector_table
63 | .globl _freertos_vector_table
64 |
65 | .globl FIQInterrupt
66 | .globl IRQInterrupt
67 | .globl SErrorInterrupt
68 | .globl SynchronousInterrupt
69 |
70 |
71 | .org 0
72 |
73 | .section .vectors, "a"
74 |
75 | _vector_table:
76 |
77 | .set VBAR, _vector_table
78 |
79 | .org VBAR
80 | b _boot
81 |
82 | .org (VBAR + 0x80)
83 | b .
84 |
85 | .org (VBAR + 0x100)
86 | b .
87 |
88 | .org (VBAR + 0x180)
89 | b .
90 |
91 |
92 | .org (VBAR + 0x200)
93 | b .
94 |
95 | .org (VBAR + 0x280)
96 | b .
97 |
98 | .org (VBAR + 0x300)
99 | b .
100 |
101 | .org (VBAR + 0x380)
102 | b .
103 |
104 |
105 |
106 | .org (VBAR + 0x400)
107 | b .
108 |
109 | .org (VBAR + 0x480)
110 | b .
111 |
112 | .org (VBAR + 0x500)
113 | b .
114 |
115 | .org (VBAR + 0x580)
116 | b .
117 |
118 | .org (VBAR + 0x600)
119 | b .
120 |
121 | .org (VBAR + 0x680)
122 | b .
123 |
124 | .org (VBAR + 0x700)
125 | b .
126 |
127 | .org (VBAR + 0x780)
128 | b .
129 |
130 |
131 |
132 | /******************************************************************************
133 | * Vector table to use when FreeRTOS is running.
134 | *****************************************************************************/
135 | .set FREERTOS_VBAR, (VBAR+0x1000)
136 |
137 | .org(FREERTOS_VBAR)
138 | _freertos_vector_table:
139 | b FreeRTOS_SWI_Handler
140 |
141 | .org (FREERTOS_VBAR + 0x80)
142 | b FreeRTOS_IRQ_Handler
143 |
144 | .org (FREERTOS_VBAR + 0x100)
145 | #if defined(GICv3)
146 | b FreeRTOS_IRQ_Handler
147 | #else
148 | b .
149 | #endif
150 | .org (FREERTOS_VBAR + 0x180)
151 | b .
152 |
153 | .org (FREERTOS_VBAR + 0x200)
154 | b FreeRTOS_SWI_Handler
155 |
156 | .org (FREERTOS_VBAR + 0x280)
157 | b FreeRTOS_IRQ_Handler
158 |
159 | .org (FREERTOS_VBAR + 0x300)
160 | b FreeRTOS_IRQ_Handler
161 |
162 | .org (FREERTOS_VBAR + 0x380)
163 | b .
164 |
165 | .org (FREERTOS_VBAR + 0x400)
166 | b .
167 |
168 | .org (FREERTOS_VBAR + 0x480)
169 | b .
170 |
171 | .org (FREERTOS_VBAR + 0x500)
172 | b .
173 |
174 | .org (FREERTOS_VBAR + 0x580)
175 | b .
176 |
177 | .org (FREERTOS_VBAR + 0x600)
178 | b .
179 |
180 | .org (FREERTOS_VBAR + 0x680)
181 | b .
182 |
183 | .org (FREERTOS_VBAR + 0x700)
184 | b .
185 |
186 | .org (FREERTOS_VBAR + 0x780)
187 | b .
188 |
189 | .org (FREERTOS_VBAR + 0x800)
190 |
191 |
192 |
193 |
194 | SynchronousInterruptHandler:
195 | stp X0,X1, [sp,#-0x10]!
196 | stp X2,X3, [sp,#-0x10]!
197 | stp X4,X5, [sp,#-0x10]!
198 | stp X6,X7, [sp,#-0x10]!
199 | stp X8,X9, [sp,#-0x10]!
200 | stp X10,X11, [sp,#-0x10]!
201 | stp X12,X13, [sp,#-0x10]!
202 | stp X14,X15, [sp,#-0x10]!
203 | stp X16,X17, [sp,#-0x10]!
204 | stp X18,X19, [sp,#-0x10]!
205 | stp X29,X30, [sp,#-0x10]!
206 |
207 | bl SynchronousInterrupt
208 |
209 | ldp X29,X30, [sp], #0x10
210 | ldp X18,X19, [sp], #0x10
211 | ldp X16,X17, [sp], #0x10
212 | ldp X14,X15, [sp], #0x10
213 | ldp X12,X13, [sp], #0x10
214 | ldp X10,X11, [sp], #0x10
215 | ldp X8,X9, [sp], #0x10
216 | ldp X6,X7, [sp], #0x10
217 | ldp X4,X5, [sp], #0x10
218 | ldp X2,X3, [sp], #0x10
219 | ldp X0,X1, [sp], #0x10
220 |
221 | eret
222 |
223 | IRQInterruptHandler:
224 | stp X0,X1, [sp,#-0x10]!
225 | stp X2,X3, [sp,#-0x10]!
226 | stp X4,X5, [sp,#-0x10]!
227 | stp X6,X7, [sp,#-0x10]!
228 | stp X8,X9, [sp,#-0x10]!
229 | stp X10,X11, [sp,#-0x10]!
230 | stp X12,X13, [sp,#-0x10]!
231 | stp X14,X15, [sp,#-0x10]!
232 | stp X16,X17, [sp,#-0x10]!
233 | stp X18,X19, [sp,#-0x10]!
234 | stp X29,X30, [sp,#-0x10]!
235 |
236 | bl IRQInterrupt
237 |
238 | ldp X29,X30, [sp], #0x10
239 | ldp X18,X19, [sp], #0x10
240 | ldp X16,X17, [sp], #0x10
241 | ldp X14,X15, [sp], #0x10
242 | ldp X12,X13, [sp], #0x10
243 | ldp X10,X11, [sp], #0x10
244 | ldp X8,X9, [sp], #0x10
245 | ldp X6,X7, [sp], #0x10
246 | ldp X4,X5, [sp], #0x10
247 | ldp X2,X3, [sp], #0x10
248 | ldp X0,X1, [sp], #0x10
249 |
250 | eret
251 |
252 | FIQInterruptHandler:
253 |
254 | stp X0,X1, [sp,#-0x10]!
255 | stp X2,X3, [sp,#-0x10]!
256 | stp X4,X5, [sp,#-0x10]!
257 | stp X6,X7, [sp,#-0x10]!
258 | stp X8,X9, [sp,#-0x10]!
259 | stp X10,X11, [sp,#-0x10]!
260 | stp X12,X13, [sp,#-0x10]!
261 | stp X14,X15, [sp,#-0x10]!
262 | stp X16,X17, [sp,#-0x10]!
263 | stp X18,X19, [sp,#-0x10]!
264 | stp X29,X30, [sp,#-0x10]!
265 |
266 | bl FIQInterrupt
267 |
268 | ldp X29,X30, [sp], #0x10
269 | ldp X18,X19, [sp], #0x10
270 | ldp X16,X17, [sp], #0x10
271 | ldp X14,X15, [sp], #0x10
272 | ldp X12,X13, [sp], #0x10
273 | ldp X10,X11, [sp], #0x10
274 | ldp X8,X9, [sp], #0x10
275 | ldp X6,X7, [sp], #0x10
276 | ldp X4,X5, [sp], #0x10
277 | ldp X2,X3, [sp], #0x10
278 | ldp X0,X1, [sp], #0x10
279 |
280 | eret
281 |
282 | SErrorInterruptHandler:
283 |
284 | stp X0,X1, [sp,#-0x10]!
285 | stp X2,X3, [sp,#-0x10]!
286 | stp X4,X5, [sp,#-0x10]!
287 | stp X6,X7, [sp,#-0x10]!
288 | stp X8,X9, [sp,#-0x10]!
289 | stp X10,X11, [sp,#-0x10]!
290 | stp X12,X13, [sp,#-0x10]!
291 | stp X14,X15, [sp,#-0x10]!
292 | stp X16,X17, [sp,#-0x10]!
293 | stp X18,X19, [sp,#-0x10]!
294 | stp X29,X30, [sp,#-0x10]!
295 |
296 | bl SErrorInterrupt
297 |
298 | ldp X29,X30, [sp], #0x10
299 | ldp X18,X19, [sp], #0x10
300 | ldp X16,X17, [sp], #0x10
301 | ldp X14,X15, [sp], #0x10
302 | ldp X12,X13, [sp], #0x10
303 | ldp X10,X11, [sp], #0x10
304 | ldp X8,X9, [sp], #0x10
305 | ldp X6,X7, [sp], #0x10
306 | ldp X4,X5, [sp], #0x10
307 | ldp X2,X3, [sp], #0x10
308 | ldp X0,X1, [sp], #0x10
309 |
310 | eret
311 |
312 | .end
313 |
--------------------------------------------------------------------------------
/GCC/CORTEX_A9_Zynq7000/Percepio View 4.10.3 patch/trcHardwarePort.c:
--------------------------------------------------------------------------------
1 | /*
2 | * Trace Recorder for Tracealyzer v4.10.3
3 | * Copyright 2023 Percepio AB
4 | * www.percepio.com
5 | *
6 | * SPDX-License-Identifier: Apache-2.0
7 | *
8 | * The hardware abstraction layer for the trace recorder.
9 | */
10 |
11 | #include
12 |
13 | #if (TRC_USE_TRACEALYZER_RECORDER == 1)
14 |
15 | /* If using DWT timestamping (default on ARM Cortex-M3, M4 and M7), make sure the DWT unit is initialized. */
16 | #if (((TRC_CFG_HARDWARE_PORT == TRC_HARDWARE_PORT_ARM_Cortex_M) || (TRC_CFG_HARDWARE_PORT == TRC_HARDWARE_PORT_ARM_Cortex_M_NRF_SD)) && (defined (__CORTEX_M) && (__CORTEX_M >= 0x03)))
17 | #if (TRC_CFG_RECORDER_MODE == TRC_RECORDER_MODE_STREAMING)
18 | #ifndef TRC_CFG_ARM_CM_USE_SYSTICK
19 |
20 | void xTraceHardwarePortInitCortexM(void)
21 | {
22 | /* Make sure the DWT registers are unlocked, in case the debugger doesn't do this. */
23 | TRC_REG_ITM_LOCKACCESS = TRC_ITM_LOCKACCESS_UNLOCK;
24 |
25 | /* Make sure DWT is enabled is enabled, if supported */
26 | TRC_REG_DEMCR |= TRC_DEMCR_TRCENA;
27 |
28 | do
29 | {
30 | /* Verify that DWT is supported */
31 | if (TRC_REG_DEMCR == 0)
32 | {
33 | /* This function is called on Cortex-M3, M4 and M7 devices to initialize
34 | the DWT unit, assumed present. The DWT cycle counter is used for timestamping.
35 |
36 | If the below error is produced, the DWT unit does not seem to be available.
37 |
38 | In that case, define the macro TRC_CFG_ARM_CM_USE_SYSTICK in your build
39 | to use SysTick timestamping instead, or define your own timestamping by
40 | setting TRC_CFG_HARDWARE_PORT to TRC_HARDWARE_PORT_APPLICATION_DEFINED
41 | and make the necessary definitions, as explained in trcHardwarePort.h.*/
42 |
43 | xTraceError(TRC_ERROR_DWT_NOT_SUPPORTED);
44 | break;
45 | }
46 |
47 | /* Verify that DWT_CYCCNT is supported */
48 | if (TRC_REG_DWT_CTRL & TRC_DWT_CTRL_NOCYCCNT)
49 | {
50 | /* This function is called on Cortex-M3, M4 and M7 devices to initialize
51 | the DWT unit, assumed present. The DWT cycle counter is used for timestamping.
52 |
53 | If the below error is produced, the cycle counter does not seem to be available.
54 |
55 | In that case, define the macro TRC_CFG_ARM_CM_USE_SYSTICK in your build
56 | to use SysTick timestamping instead, or define your own timestamping by
57 | setting TRC_CFG_HARDWARE_PORT to TRC_HARDWARE_PORT_APPLICATION_DEFINED
58 | and make the necessary definitions, as explained in trcHardwarePort.h.*/
59 |
60 | xTraceError(TRC_ERROR_DWT_CYCCNT_NOT_SUPPORTED);
61 | break;
62 | }
63 |
64 | /* Reset the cycle counter */
65 | TRC_REG_DWT_CYCCNT = 0;
66 |
67 | /* Enable the cycle counter */
68 | TRC_REG_DWT_CTRL |= TRC_DWT_CTRL_CYCCNTENA;
69 |
70 | } while (0); /* breaks above jump here */
71 | }
72 | #endif /* TRC_CFG_ARM_CM_USE_SYSTICK */
73 |
74 | #endif /* (TRC_CFG_RECORDER_MODE == TRC_RECORDER_MODE_STREAMING) */
75 | #endif /* (((TRC_CFG_HARDWARE_PORT == TRC_HARDWARE_PORT_ARM_Cortex_M) || (TRC_CFG_HARDWARE_PORT == TRC_HARDWARE_PORT_ARM_Cortex_M_NRF_SD)) && (defined (__CORTEX_M) && (__CORTEX_M >= 0x03))) */
76 |
77 | #if ((TRC_CFG_HARDWARE_PORT == TRC_HARDWARE_PORT_ARM_CORTEX_A9) || (TRC_CFG_HARDWARE_PORT == TRC_HARDWARE_PORT_XILINX_ZyncUltraScaleR5) || (TRC_CFG_HARDWARE_PORT == TRC_HARDWARE_PORT_CYCLONE_V_HPS) || (TRC_CFG_HARDWARE_PORT == TRC_HARDWARE_PORT_ARMv8AR_A32))
78 |
79 | #define CS_TYPE_NONE 0
80 | #define CS_TYPE_TASK 1
81 |
82 | #define CS_TYPE_INVALID 0xFFFFFFFF
83 |
84 | #if ( (TRC_CFG_CORE_COUNT > 1) && (TRC_CFG_HARDWARE_PORT == TRC_HARDWARE_PORT_ARM_CORTEX_A9) )
85 |
86 | #define CS_TYPE_ISR 2
87 |
88 | uint32_t cortex_a9_r5_enter_critical(uint32_t* pulSavedInterruptStatus)
89 | {
90 | TraceUnsignedBaseType_t cs_type = CS_TYPE_INVALID;
91 |
92 | #if (TRC_CFG_RECORDER_MODE == TRC_RECORDER_MODE_STREAMING)
93 | TraceUnsignedBaseType_t uxTraceSystemState;
94 |
95 | xTraceStateGet(&uxTraceSystemState);
96 | #endif
97 |
98 | if ((prvGetCPSR() & 0x001F) == 0x13) // CSPR (ASPR) mode = SVC
99 | {
100 | /* The processor executes in SVC mode in an ISR other than the context-switch.
101 | * Differently from a context-swtich, inside an ISR interrupts might have been enabled
102 | * to allow interrupt nesting, motivating a critical section entry.
103 | * This is needed because the implementation of ulPortSetInterruptMask and vPortClearInterruptMask
104 | * depends on the number of cores. In the single-core implementation vPortClearInterruptMask
105 | * completely unmasks the interrupts while in multi-core it sets the ICC_PMR to the
106 | * previous mask. For this reason, the former function does not need any variable to
107 | * store the saved mask while the latter does. */
108 | *pulSavedInterruptStatus = (uint32_t) portENTER_CRITICAL_FROM_ISR();
109 | cs_type = CS_TYPE_ISR;
110 | }
111 | #if (TRC_CFG_RECORDER_MODE == TRC_RECORDER_MODE_STREAMING)
112 | else if (uxTraceSystemState == TRC_STATE_IN_TASKSWITCH)
113 | #else
114 | else if (uiTraceSystemState == TRC_STATE_IN_TASKSWITCH)
115 | #endif
116 | {
117 | // In the context-switch code. All interrupts are already masked here, so don't modify the mask.
118 | cs_type = CS_TYPE_NONE;
119 | }
120 | #if (TRC_CFG_RECORDER_MODE == TRC_RECORDER_MODE_STREAMING)
121 | else if (uxTraceSystemState != TRC_STATE_IN_TASKSWITCH)
122 | #else
123 | else if (uiTraceSystemState != TRC_STATE_IN_TASKSWITCH)
124 | #endif
125 | {
126 | // Not within ISR or task-switch context, use a regular critical section.
127 | portENTER_CRITICAL();
128 | cs_type = CS_TYPE_TASK;
129 | }
130 |
131 | return (uint32_t)cs_type;
132 | }
133 |
134 | void cortex_a9_r5_exit_critical(uint32_t cs_type, uint32_t ulSavedInterruptStatus)
135 | {
136 | switch (cs_type)
137 | {
138 | case CS_TYPE_TASK:
139 | portEXIT_CRITICAL();
140 | break;
141 |
142 | case CS_TYPE_ISR:
143 | portEXIT_CRITICAL_FROM_ISR( ulSavedInterruptStatus );
144 | break;
145 |
146 | case CS_TYPE_NONE:
147 | // No action in these two cases.
148 | break;
149 |
150 | default:
151 | // Error, should not be possible;
152 | for (;;);
153 | }
154 | }
155 |
156 |
157 | #else /* ((TRC_CFG_CORE_COUNT > 1) && (TRC_CFG_HARDWARE_PORT == TRC_HARDWARE_PORT_ARM_CORTEX_A9)) */
158 |
159 | #define CS_TYPE_ISR_MASK_CHANGED 2
160 | #define CS_TYPE_ISR_MASK_NOT_CHANGED 3
161 |
162 | uint32_t cortex_a9_r5_enter_critical(void)
163 | {
164 | TraceUnsignedBaseType_t cs_type = CS_TYPE_INVALID;
165 | #if (TRC_CFG_RECORDER_MODE == TRC_RECORDER_MODE_STREAMING)
166 | TraceUnsignedBaseType_t uxTraceSystemState;
167 |
168 | xTraceStateGet(&uxTraceSystemState);
169 | #endif
170 |
171 | if ((prvGetCPSR() & 0x001F) == 0x13) // CSPR (ASPR) mode = SVC
172 | {
173 | /* Executing in an ISR other than the context-switch (where interrupts might have been enabled, motivating a critical section). */
174 | if (ulPortSetInterruptMask() == pdTRUE)
175 | {
176 | cs_type = CS_TYPE_ISR_MASK_NOT_CHANGED;
177 | }
178 | else
179 | {
180 | cs_type = CS_TYPE_ISR_MASK_CHANGED;
181 | }
182 | }
183 | #if (TRC_CFG_RECORDER_MODE == TRC_RECORDER_MODE_STREAMING)
184 | else if (uxTraceSystemState == TRC_STATE_IN_TASKSWITCH)
185 | #else
186 | else if (uiTraceSystemState == TRC_STATE_IN_TASKSWITCH)
187 | #endif
188 | {
189 | // In the context-switch code. All interrupts are already masked here, so don't modify the mask.
190 | cs_type = CS_TYPE_NONE;
191 | }
192 | #if (TRC_CFG_RECORDER_MODE == TRC_RECORDER_MODE_STREAMING)
193 | else if (uxTraceSystemState != TRC_STATE_IN_TASKSWITCH)
194 | #else
195 | else if (uiTraceSystemState != TRC_STATE_IN_TASKSWITCH)
196 | #endif
197 | {
198 | // Not within ISR or task-switch context, use a regular critical section.
199 | portENTER_CRITICAL();
200 | cs_type = CS_TYPE_TASK;
201 | }
202 |
203 | return (uint32_t)cs_type;
204 | }
205 |
206 | void cortex_a9_r5_exit_critical(uint32_t cs_type)
207 | {
208 | switch (cs_type)
209 | {
210 | case CS_TYPE_TASK:
211 | portEXIT_CRITICAL();
212 | break;
213 |
214 | case CS_TYPE_ISR_MASK_CHANGED:
215 | vPortClearInterruptMask(pdFALSE); // pdFALSE means it will reset the IRQ mask.
216 | break;
217 |
218 | case CS_TYPE_ISR_MASK_NOT_CHANGED:
219 | case CS_TYPE_NONE:
220 | // No action in these two cases.
221 | break;
222 |
223 | default:
224 | // Error, should not be possible;
225 | for (;;);
226 | }
227 | }
228 | #endif /* ((TRC_CFG_CORE_COUNT > 1) && (TRC_CFG_HARDWARE_PORT == TRC_HARDWARE_PORT_ARM_CORTEX_A9)) */
229 |
230 | #endif /* ((TRC_CFG_HARDWARE_PORT == TRC_HARDWARE_PORT_ARM_CORTEX_A9) || (TRC_CFG_HARDWARE_PORT == TRC_HARDWARE_PORT_XILINX_ZyncUltraScaleR5)) */
231 |
232 | #endif /* (TRC_USE_TRACEALYZER_RECORDER == 1) */
233 |
--------------------------------------------------------------------------------
/GCC/CORTEX_A53_64-bit_UltraScale_MPSoC/portZynqUltrascale.c:
--------------------------------------------------------------------------------
1 | /*
2 | * FreeRTOS Kernel V10.3.0
3 | * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
4 | * Copyright (C) 2014 - 2020 Xilinx, Inc. All rights reserved.
5 | *
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy of
7 | * this software and associated documentation files (the "Software"), to deal in
8 | * the Software without restriction, including without limitation the rights to
9 | * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
10 | * the Software, and to permit persons to whom the Software is furnished to do so,
11 | * subject to the following conditions:
12 | *
13 | * The above copyright notice and this permission notice shall be included in all
14 | * copies or substantial portions of the Software.
15 | *
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
18 | * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
19 | * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
20 | * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
21 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
22 | *
23 | * http://www.FreeRTOS.org
24 | * http://aws.amazon.com/freertos
25 | *
26 | * 1 tab == 4 spaces!
27 | */
28 |
29 | /* FreeRTOS includes. */
30 | #include "FreeRTOS.h"
31 | #include "task.h"
32 |
33 | /* Xilinx includes. */
34 | #include "xttcps.h"
35 | #include "xscugic.h"
36 |
37 | void vApplicationAssert( const char *pcFileName, uint32_t ulLine )
38 | __attribute__((weak));
39 |
40 | /* Timer used to generate the tick interrupt. */
41 | XTtcPs xTimerInstance;
42 | XScuGic xInterruptController;
43 | /*-----------------------------------------------------------*/
44 |
45 | void FreeRTOS_SetupTickInterrupt( void )
46 | {
47 | BaseType_t xStatus;
48 | XTtcPs_Config *pxTimerConfiguration;
49 | XInterval usInterval;
50 | uint8_t ucPrescale;
51 | const uint8_t ucLevelSensitive = 1;
52 |
53 | pxTimerConfiguration = XTtcPs_LookupConfig( configTIMER_ID );
54 |
55 | /* Initialise the device. */
56 | xStatus = XTtcPs_CfgInitialize( &xTimerInstance, pxTimerConfiguration, pxTimerConfiguration->BaseAddress );
57 |
58 | if( xStatus != XST_SUCCESS )
59 | {
60 | /* Not sure how to do this before XTtcPs_CfgInitialize is called as
61 | *xRTOSTickTimerInstance is set within XTtcPs_CfgInitialize(). */
62 | XTtcPs_Stop( &xTimerInstance );
63 | xStatus = XTtcPs_CfgInitialize( &xTimerInstance, pxTimerConfiguration, pxTimerConfiguration->BaseAddress );
64 | configASSERT( xStatus == XST_SUCCESS );
65 | }
66 |
67 | /* Set the options. */
68 | XTtcPs_SetOptions( &xTimerInstance, ( XTTCPS_OPTION_INTERVAL_MODE | XTTCPS_OPTION_WAVE_DISABLE ) );
69 | /*
70 | * The Xilinx implementation of generating run time task stats uses the same timer used for generating
71 | * FreeRTOS ticks. In case user decides to generate run time stats the timer time out interval is changed
72 | * as "configured tick rate * 10". The multiplying factor of 10 is hard coded for Xilinx FreeRTOS ports.
73 | */
74 | #if (configGENERATE_RUN_TIME_STATS == 1)
75 | XTtcPs_CalcIntervalFromFreq( &xTimerInstance, configTICK_RATE_HZ*10, &usInterval, &ucPrescale );
76 | #else
77 | XTtcPs_CalcIntervalFromFreq( &xTimerInstance, configTICK_RATE_HZ, &( usInterval ), &( ucPrescale ) );
78 | #endif
79 |
80 | /* Set the interval and prescale. */
81 | XTtcPs_SetInterval( &xTimerInstance, usInterval );
82 | XTtcPs_SetPrescaler( &xTimerInstance, ucPrescale );
83 |
84 | xPortInstallInterruptHandler(configTIMER_INTERRUPT_ID,
85 | ( Xil_InterruptHandler ) FreeRTOS_Tick_Handler,
86 | ( void * ) &xTimerInstance);
87 | /* The priority must be the lowest possible. */
88 | XScuGic_SetPriorityTriggerType( &xInterruptController, configTIMER_INTERRUPT_ID, portLOWEST_USABLE_INTERRUPT_PRIORITY << portPRIORITY_SHIFT, ucLevelSensitive );
89 |
90 | vPortEnableInterrupt(configTIMER_INTERRUPT_ID);
91 |
92 | /* Enable the interrupts in the timer. */
93 | XTtcPs_EnableInterrupts( &xTimerInstance, XTTCPS_IXR_INTERVAL_MASK );
94 |
95 | /* Start the timer. */
96 | XTtcPs_Start( &xTimerInstance );
97 | }
98 | /*-----------------------------------------------------------*/
99 |
100 | void FreeRTOS_ClearTickInterrupt( void )
101 | {
102 |
103 | XTtcPs_ClearInterruptStatus( &xTimerInstance, XTtcPs_GetInterruptStatus( &xTimerInstance ) );
104 | __asm volatile( "DSB SY" );
105 | __asm volatile( "ISB SY" );
106 | }
107 | /*-----------------------------------------------------------*/
108 |
109 | void vApplicationIRQHandler( uint32_t ulICCIAR )
110 | {
111 | extern const XScuGic_Config XScuGic_ConfigTable[];
112 | static const XScuGic_VectorTableEntry *pxVectorTable = XScuGic_ConfigTable[ XPAR_SCUGIC_SINGLE_DEVICE_ID ].HandlerTable;
113 | uint32_t ulInterruptID;
114 | const XScuGic_VectorTableEntry *pxVectorEntry;
115 |
116 | /* Interrupts cannot be re-enabled until the source of the interrupt is
117 | cleared. The ID of the interrupt is obtained by bitwise ANDing the ICCIAR
118 | value with 0x3FF. */
119 | ulInterruptID = ulICCIAR & 0x3FFUL;
120 |
121 | if( ulInterruptID < XSCUGIC_MAX_NUM_INTR_INPUTS )
122 | {
123 | /* Call the function installed in the array of installed handler
124 | functions. */
125 | pxVectorEntry = &( pxVectorTable[ ulInterruptID ] );
126 | configASSERT( pxVectorEntry );
127 | pxVectorEntry->Handler( pxVectorEntry->CallBackRef );
128 | }
129 | }
130 |
131 | /*-----------------------------------------------------------*/
132 |
133 | /* This version of vApplicationAssert() is declared as a weak symbol to allow it
134 | to be overridden by a version implemented within the application that is using
135 | this BSP. */
136 | void vApplicationAssert( const char *pcFileName, uint32_t ulLine )
137 | {
138 | volatile uint32_t ul = 0;
139 | volatile const char *pcLocalFileName = pcFileName; /* To prevent pcFileName being optimized away. */
140 | volatile uint32_t ulLocalLine = ulLine; /* To prevent ulLine being optimized away. */
141 |
142 | /* Prevent compile warnings about the following two variables being set but
143 | not referenced. They are intended for viewing in the debugger. */
144 | ( void ) pcLocalFileName;
145 | ( void ) ulLocalLine;
146 |
147 | xil_printf( "Assert failed in file %s, line %lu\r\n", pcLocalFileName, ulLocalLine );
148 |
149 | /* If this function is entered then a call to configASSERT() failed in the
150 | FreeRTOS code because of a fatal error. The pcFileName and ulLine
151 | parameters hold the file name and line number in that file of the assert
152 | that failed. Additionally, if using the debugger, the function call stack
153 | can be viewed to find which line failed its configASSERT() test. Finally,
154 | the debugger can be used to set ul to a non-zero value, then step out of
155 | this function to find where the assert function was entered. */
156 | taskENTER_CRITICAL();
157 | {
158 | while( ul == 0 )
159 | {
160 | __asm volatile( "NOP" );
161 | }
162 | }
163 | taskEXIT_CRITICAL();
164 | }
165 | /*-----------------------------------------------------------*/
166 |
167 | #if 0
168 | /* This default tick hook does nothing and is declared as a weak symbol to allow
169 | the application writer to override this default by providing their own
170 | implementation in the application code. */
171 | void vApplicationTickHook( void )
172 | {
173 | }
174 | /*-----------------------------------------------------------*/
175 |
176 | /* This default idle hook does nothing and is declared as a weak symbol to allow
177 | the application writer to override this default by providing their own
178 | implementation in the application code. */
179 | void vApplicationIdleHook( void )
180 | {
181 | }
182 | /*-----------------------------------------------------------*/
183 |
184 | /* This default malloc failed hook does nothing and is declared as a weak symbol
185 | to allow the application writer to override this default by providing their own
186 | implementation in the application code. */
187 | void vApplicationMallocFailedHook( void )
188 | {
189 | xil_printf( "vApplicationMallocFailedHook() called\n" );
190 | }
191 | /*-----------------------------------------------------------*/
192 |
193 | /* This default stack overflow hook will stop the application for executing. It
194 | is declared as a weak symbol to allow the application writer to override this
195 | default by providing their own implementation in the application code. */
196 | void vApplicationStackOverflowHook( TaskHandle_t xTask, char *pcTaskName )
197 | {
198 | /* Attempt to prevent the handle and name of the task that overflowed its stack
199 | from being optimised away because they are not used. */
200 | volatile TaskHandle_t xOverflowingTaskHandle = xTask;
201 | volatile char *pcOverflowingTaskName = pcTaskName;
202 |
203 | ( void ) xOverflowingTaskHandle;
204 | ( void ) pcOverflowingTaskName;
205 |
206 | xil_printf( "HALT: Task %s overflowed its stack.", pcOverflowingTaskName );
207 | portDISABLE_INTERRUPTS();
208 | for( ;; );
209 | }
210 | #endif
211 |
212 |
--------------------------------------------------------------------------------
/Z88DK/Z180/port.c:
--------------------------------------------------------------------------------
1 | /*
2 | * Copyright (C) 2025 Phillip Stevens All Rights Reserved.
3 | *
4 | * Permission is hereby granted, free of charge, to any person obtaining a copy of
5 | * this software and associated documentation files (the "Software"), to deal in
6 | * the Software without restriction, including without limitation the rights to
7 | * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
8 | * the Software, and to permit persons to whom the Software is furnished to do so,
9 | * subject to the following conditions:
10 | *
11 | * The above copyright notice and this permission notice shall be included in all
12 | * copies or substantial portions of the Software.
13 | *
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
16 | * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
17 | * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
18 | * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
19 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
20 | *
21 | * https://www.FreeRTOS.org
22 | * https://github.com/FreeRTOS
23 | *
24 | */
25 |
26 |
27 | #include
28 |
29 | #include "include/FreeRTOS.h"
30 |
31 | #if __SDCC
32 | #include "include/sdcc/task.h"
33 | #elif __SCCZ80
34 | #include "include/sccz80/task.h"
35 | #endif
36 |
37 | /*-----------------------------------------------------------*/
38 |
39 | /* We require the address of the pxCurrentTCB variable, but don't want to know
40 | any details of its type. */
41 | /* Make unitialised in BSS for RomWBW HBIOS (to ensure above 0x8000) */
42 | typedef void TCB_t;
43 | extern volatile TCB_t * volatile pxCurrentTCB;
44 |
45 | /*-----------------------------------------------------------*/
46 |
47 | /*
48 | * Macros to set up, restart (reload), and stop the PRT1 Timer used for
49 | * the System Tick.
50 | */
51 |
52 | #define configTICK_RATE_HZ (256) /* Timer configured */
53 | #define configISR_ORG ASMPC /* ISR relocation */
54 | #define configISR_IVT 0xFFE6 /* PRT1 address */
55 |
56 | #define configSETUP_TIMER_INTERRUPT() \
57 | do{ \
58 | __asm__( \
59 | "EXTERN __CPU_CLOCK \n" \
60 | "EXTERN RLDR1L, RLDR1H \n" \
61 | "EXTERN TCR, TCR_TIE1, TCR_TDE1 \n" \
62 | "ld de,_timer_isr \n" \
63 | "ld hl,"string(configISR_IVT)" ; PRT1 address \n" \
64 | "ld (hl),e \n" \
65 | "inc hl \n" \
66 | "ld (hl),d \n" \
67 | "; we do configTICK_RATE_HZ ticks per second \n" \
68 | "ld hl,__CPU_CLOCK/"string(configTICK_RATE_HZ)"/20-1 \n" \
69 | "out0(RLDR1L),l \n" \
70 | "out0(RLDR1H),h \n" \
71 | "in0 a,(TCR) \n" \
72 | "or TCR_TIE1|TCR_TDE1 \n" \
73 | "out0 (TCR),a \n" \
74 | ); \
75 | }while(0)
76 |
77 | #define configRESET_TIMER_INTERRUPT() \
78 | do{ \
79 | __asm__( \
80 | "EXTERN TCR, TMDR1L \n" \
81 | "in0 a,(TCR) \n" \
82 | "in0 a,(TMDR1L) \n" \
83 | ); \
84 | }while(0)
85 |
86 | #define configSTOP_TIMER_INTERRUPT() \
87 | do{ \
88 | __asm__( \
89 | "EXTERN TCR, TCR_TIE1, TCR_TDE1 \n" \
90 | "; disable down counting and interrupts for PRT1\n" \
91 | "in0 a,(TCR) \n" \
92 | "xor TCR_TIE1|TCR_TDE1 \n" \
93 | "out0 (TCR),a \n" \
94 | ); \
95 | }while(0)
96 |
97 |
98 | /*-----------------------------------------------------------*/
99 |
100 | /*
101 | * Perform hardware setup to enable ticks from Timer.
102 | */
103 | static void prvSetupTimerInterrupt( void ) __preserves_regs(iyh,iyl);
104 |
105 | /*-----------------------------------------------------------*/
106 |
107 | /*
108 | * See header file for description.
109 | */
110 | StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
111 | {
112 | /* Place the parameter on the stack in the expected location. */
113 | *pxTopOfStack-- = ( StackType_t ) pvParameters;
114 |
115 | /* Place the task return address on stack. Not used */
116 | *pxTopOfStack-- = ( StackType_t ) 0;
117 |
118 | /* The start of the task code will be popped off the stack last, so place
119 | it on first. */
120 | *pxTopOfStack-- = ( StackType_t ) pxCode;
121 |
122 | /* Now the registers. */
123 | *pxTopOfStack-- = ( StackType_t ) 0xAFAF; /* AF */
124 | *pxTopOfStack-- = ( StackType_t ) 0x0404; /* IF */
125 | *pxTopOfStack-- = ( StackType_t ) 0xBCBC; /* BC */
126 | *pxTopOfStack-- = ( StackType_t ) 0xDEDE; /* DE */
127 | *pxTopOfStack-- = ( StackType_t ) 0xEFEF; /* HL */
128 | *pxTopOfStack-- = ( StackType_t ) 0xFAFA; /* AF' */
129 | *pxTopOfStack-- = ( StackType_t ) 0xCBCB; /* BC' */
130 | *pxTopOfStack-- = ( StackType_t ) 0xEDED; /* DE' */
131 | *pxTopOfStack-- = ( StackType_t ) 0xFEFE; /* HL' */
132 | *pxTopOfStack-- = ( StackType_t ) 0xCEFA; /* IX */
133 | *pxTopOfStack = ( StackType_t ) 0xADDE; /* IY */
134 |
135 | return pxTopOfStack;
136 | }
137 | /*-----------------------------------------------------------*/
138 |
139 | BaseType_t xPortStartScheduler( void ) __preserves_regs(a,b,c,d,e,iyh,iyl) __naked
140 | {
141 | /* Setup the relevant timer hardware to generate the tick. */
142 | prvSetupTimerInterrupt();
143 |
144 | /* Restore the context of the first task that is going to run. */
145 | portRESTORE_CONTEXT();
146 |
147 | /* Should not get here. */
148 | return pdFALSE;
149 | }
150 | /*-----------------------------------------------------------*/
151 |
152 | void vPortEndScheduler( void ) __preserves_regs(b,c,d,e,h,l,iyh,iyl)
153 | {
154 | /*
155 | * It is unlikely that the Z80 port will get stopped.
156 | * If required simply disable the tick interrupt here.
157 | */
158 | configSTOP_TIMER_INTERRUPT();
159 | }
160 | /*-----------------------------------------------------------*/
161 |
162 | /*
163 | * Manual context switch. The first thing we do is save the registers so we
164 | * can use a naked attribute. This is called by the application, so we don't have
165 | * to check which bank is loaded.
166 | */
167 | void vPortYield( void ) __preserves_regs(a,b,c,d,e,h,l,iyh,iyl) __naked
168 | {
169 | portSAVE_CONTEXT();
170 | vTaskSwitchContext();
171 | portRESTORE_CONTEXT();
172 | }
173 | /*-----------------------------------------------------------*/
174 |
175 | /*
176 | * Manual context switch callable from ISRs. The first thing we do is save
177 | * the registers so we can use a naked attribute.
178 | */
179 | void vPortYieldFromISR(void) __preserves_regs(a,b,c,d,e,h,l,iyh,iyl) __naked
180 | void vPortYieldFromISR(void)
181 | {
182 | portSAVE_CONTEXT_IN_ISR();
183 | vTaskSwitchContext();
184 | portRESTORE_CONTEXT_IN_ISR();
185 | }
186 | /*-----------------------------------------------------------*/
187 |
188 | /*
189 | * Initialize Timer (PRT1 for YAZ180, and SCZ180 HBIOS).
190 | */
191 | void prvSetupTimerInterrupt( void ) __preserves_regs(iyh,iyl)
192 | {
193 | configSETUP_TIMER_INTERRUPT();
194 | }
195 | /*-----------------------------------------------------------*/
196 |
197 | void timer_isr(void) __preserves_regs(a,b,c,d,e,h,l,iyh,iyl) __naked
198 | {
199 | #if configUSE_PREEMPTION == 1
200 | /*
201 | * Tick ISR for preemptive scheduler. We can use a naked attribute as
202 | * the context is saved at the start of timer_isr(). The tick
203 | * count is incremented after the context is saved.
204 | *
205 | * Context switch function used by the tick. This must be identical to
206 | * vPortYield() from the call to vTaskSwitchContext() onwards. The only
207 | * difference from vPortYield() is the tick count is incremented as the
208 | * call comes from the tick ISR.
209 | */
210 | portSAVE_CONTEXT_IN_ISR();
211 | configRESET_TIMER_INTERRUPT();
212 | xTaskIncrementTick();
213 | vTaskSwitchContext();
214 | portRESTORE_CONTEXT_IN_ISR();
215 | #else
216 | /*
217 | * Tick ISR for the cooperative scheduler. All this does is increment the
218 | * tick count. We don't need to switch context, this can only be done by
219 | * manual calls to taskYIELD();
220 | */
221 | portSAVE_CONTEXT_IN_ISR();
222 | configRESET_TIMER_INTERRUPT();
223 | xTaskIncrementTick();
224 | portRESTORE_CONTEXT_IN_ISR();
225 | #endif
226 | } // configUSE_PREEMPTION
227 |
--------------------------------------------------------------------------------