├── .github ├── CODE_OF_CONDUCT.md ├── CONTRIBUTING.md ├── SECURITY.md └── pull_request_template.md ├── CCRH ├── LICENSE └── U2x │ ├── README.md │ ├── port.c │ ├── portasm.s │ └── portmacro.h ├── Cadence └── Xtensa │ ├── LICENSE │ ├── Makefile │ ├── asm-offsets.c │ ├── mpu.S │ ├── port.c │ ├── portasm.S │ ├── portbenchmark.h │ ├── portclib.c │ ├── portmacro.h │ ├── portmpu.c │ ├── porttrace.h │ ├── readme_xtensa.txt │ ├── relnotes.txt │ ├── xtensa_api.h │ ├── xtensa_config.h │ ├── xtensa_context.S │ ├── xtensa_context.h │ ├── xtensa_coproc_handler.S │ ├── xtensa_intr.c │ ├── xtensa_intr_asm.S │ ├── xtensa_intr_wrapper.c │ ├── xtensa_overlay_os_hook.c │ ├── xtensa_rtos.h │ ├── xtensa_timer.h │ ├── xtensa_vectors.S │ └── xtensa_vectors_xea3.S ├── GCC ├── AVR_AVRDx │ ├── LICENSE │ ├── port.c │ ├── porthardware.h │ └── portmacro.h └── AVR_Mega0 │ ├── LICENSE │ ├── port.c │ ├── porthardware.h │ └── portmacro.h ├── GHS └── U2x │ ├── LICENSE │ ├── README.md │ ├── port.c │ ├── portasm.850 │ └── portmacro.h ├── LICENSE ├── README.md ├── TI └── CORTEX_A53_64-BIT_TI_AM64_SMP │ ├── LICENSE │ ├── port.c │ ├── portASM.S │ └── portmacro.h └── Tasking └── AURIX_TC3xx ├── LICENSE ├── port.c └── portmacro.h /.github/CODE_OF_CONDUCT.md: -------------------------------------------------------------------------------- 1 | ## Code of Conduct 2 | This project has adopted the [Amazon Open Source Code of Conduct](https://aws.github.io/code-of-conduct). 3 | For more information see the [Code of Conduct FAQ](https://aws.github.io/code-of-conduct-faq) or contact 4 | opensource-codeofconduct@amazon.com with any additional questions or comments. 5 | -------------------------------------------------------------------------------- /.github/CONTRIBUTING.md: -------------------------------------------------------------------------------- 1 | # Contribution guidelines 2 | 3 | Thank you for your interest in contributing to our project. Whether it's a bug report, new feature, code, or 4 | documentation, we welcome our community to be involved in this project. 5 | 6 | Please read through this document before submitting any issues or pull requests to ensure we are able to help you and all members of the community as effectively as possible. 7 | 8 | ## Code of conduct 9 | This project has adopted the [Amazon Open Source Code of Conduct](https://aws.github.io/code-of-conduct). 10 | For more information see the [Code of Conduct FAQ](https://aws.github.io/code-of-conduct-faq) or contact 11 | opensource-codeofconduct@amazon.com with any additional questions or comments. 12 | 13 | 14 | ## Security issue notifications 15 | If you discover a potential security issue in this project we ask that you notify AWS/Amazon Security via our [vulnerability reporting page](http://aws.amazon.com/security/vulnerability-reporting/). Please do **not** create a public github issue. 16 | 17 | 18 | ## Submitting a bugs/feature request 19 | Have a bug to report or feature to request? Follow these steps: 20 | 1. Search on the [FreeRTOS Community Support Forums](https://forums.freertos.org/) and [GitHub issue tracker](https://github.com/FreeRTOS/FreeRTOS/issues?utf8=%E2%9C%93&q=is%3Aissue) to be sure this hasn't been already reported or discussed. 21 | 2. If your search turns up empty, create a new topic in the [forums](https://forums.freertos.org/) and work with the community to help clarify issues or refine the idea. Include as many of the details listed below. 22 | 3. Once the community has had time to discuss and digest, we welcome you to create an [issue](https://github.com/FreeRTOS/FreeRTOS/issues) to report bugs or suggest features. 23 | 24 | When creating a new topic on the forums or filing an issue, please include as many relevant details as possible. Examples include: 25 | 26 | * A clear description of the situation — what you observe, what you expect, and your view on how the two differ. 27 | * A reproducible test case or sequence of steps. 28 | * The version of our code being used. 29 | * Any modifications you've made relevant to the bug. 30 | * Details of your environment or deployment. Highlight anything unusual. 31 | 32 | 33 | ## Contributing via pull request 34 | Contributions via pull requests are much appreciated. Before sending us a pull request, please ensure that: 35 | 36 | 1. You are working against the latest source on the *master* branch. 37 | 2. You check existing open, and recently merged, pull requests to make sure someone else hasn't addressed the problem already. 38 | 3. You open an issue to discuss any significant work - we would hate for your time to be wasted. 39 | 40 | To send us a pull request, please: 41 | 42 | 1. Fork the repository. 43 | 2. Modify the source; focus on the specific change you are contributing. If you also reformat all the code, it will be hard for us to focus on your change. 44 | 3. Follow the [coding style guide](https://www.freertos.org/FreeRTOS-Coding-Standard-and-Style-Guide.html). 45 | 4. Commit to your fork using clear commit messages. 46 | 5. Send us a pull request, answering any default questions in the pull request interface. 47 | NOTE: Please make sure the default option (Allow edits from maintainers) is left checked. 48 | 6. Pay attention to any automated CI failures reported in the pull request, and stay involved in the conversation. 49 | 50 | GitHub provides additional document on [forking a repository](https://help.github.com/articles/fork-a-repo/) and 51 | [creating a pull request](https://help.github.com/articles/creating-a-pull-request/). 52 | 53 | ## Coding style 54 | * Please ensure that your code complies to the [FreeRTOS coding style guidelines](https://www.freertos.org/FreeRTOS-Coding-Standard-and-Style-Guide.html). 55 | 56 | 57 | ## Getting your pull request merged 58 | All pull requests must be approved by our review team before it can be merged in. We appreciate your patience while pull requests are reviewed. The time it takes to review will depend on complexity and consideration of wider implications. 59 | 60 | 61 | ## Finding contributions to work on 62 | Looking at the existing issues is a great way to find something to contribute on. As our projects, by default, use the default GitHub issue labels (enhancement/bug/duplicate/help wanted/invalid/question/wontfix), tackling open 'help wanted' issues is a great place to start. 63 | 64 | 65 | ## Licensing 66 | The FreeRTOS kernel is released under the MIT open source license, the text of which can be found [here](https://github.com/FreeRTOS/FreeRTOS/blob/master/FreeRTOS/License/license.txt) 67 | 68 | Additional license files can be found in the folders containing any supplementary libraries licensed by their respective copyright owners where applicable. 69 | 70 | We may ask you to sign a [Contributor License Agreement (CLA)](http://en.wikipedia.org/wiki/Contributor_License_Agreement) for larger changes. 71 | -------------------------------------------------------------------------------- /.github/SECURITY.md: -------------------------------------------------------------------------------- 1 | ## Reporting a Vulnerability 2 | 3 | If you discover a potential security issue in this project we ask that you notify AWS/Amazon Security 4 | via our [vulnerability reporting page](http://aws.amazon.com/security/vulnerability-reporting/) or directly via email to aws-security@amazon.com. 5 | Please do **not** create a public github issue. 6 | -------------------------------------------------------------------------------- /.github/pull_request_template.md: -------------------------------------------------------------------------------- 1 | 2 | 3 | Description 4 | ----------- 5 | 6 | 7 | Test Steps 8 | ----------- 9 | 10 | 11 | Related Issue 12 | ----------- 13 | 14 | 15 | 16 | By submitting this pull request, I confirm that you can use, modify, copy, and redistribute this contribution, under the terms of your choice. 17 | -------------------------------------------------------------------------------- /CCRH/LICENSE: -------------------------------------------------------------------------------- 1 | FreeRTOS Kernel V11.1.0 2 | Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. 3 | 4 | SPDX-License-Identifier: MIT 5 | 6 | Permission is hereby granted, free of charge, to any person obtaining a copy of 7 | this software and associated documentation files (the "Software"), to deal in 8 | the Software without restriction, including without limitation the rights to 9 | use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of 10 | the Software, and to permit persons to whom the Software is furnished to do so, 11 | subject to the following conditions: 12 | 13 | The above copyright notice and this permission notice shall be included in all 14 | copies or substantial portions of the Software. 15 | 16 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS 18 | FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR 19 | COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER 20 | IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 21 | CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 22 | 23 | https://www.FreeRTOS.org 24 | https://github.com/FreeRTOS 25 | -------------------------------------------------------------------------------- /CCRH/U2x/README.md: -------------------------------------------------------------------------------- 1 | # RH850/U2x FreeRTOS Port with CC-RH Compiler 2 | 3 | ## Introduction 4 | 5 | This repository contains the port of FreeRTOS for Renesas RH850/U2x microcontrollers using the CC-RH compiler. The following sections provide instructions on how to use this port, a link to the test project, and other relevant information. 6 | 7 | ## Prerequisites 8 | - Compiler: CC-RH 9 | - FreeRTOS version 11.1.0 10 | 11 | | Device | FPU | FXU | SMP | 12 | |----------|-----|-----|-----| 13 | | U2A6 | Yes | No | Yes | 14 | | U2A8 | Yes | No | Yes | 15 | | U2A16 | Yes | No | Yes | 16 | | U2B6 | Yes | Yes | Yes | 17 | | U2B10 | Yes | Yes | Yes | 18 | 19 | ## Link to Test Project 20 | 21 | The test project can be found in [RH850_U2Ax_CCRH](https://github.com/renesas/FreeRTOS-Partner-Supported-Demos/tree/u2x_port/) and [RH850_U2Bx_CCRH](https://github.com/renesas/FreeRTOS-Partner-Supported-Demos/tree/u2x_port/). This project contains example tasks and configurations to help you get started with FreeRTOS on the RH850/U2Ax and U2Bx. 22 | 23 | ## Note 24 | 1. The minimal stack size (configMINIMAL_STACK_SIZE) must be included the reserved memory for nested interrupt. This formula can be referred: `(task_context_size) * (2 + configMAX_INT_NESTING) + Stack_depth_of_taskcode` 25 | In which, `task_context_size` is calculated as `36*4bytes = 144bytes` (when FPU enabled) or `34*4bytes = 136` (when FPU disabled), configMAX_INT_NESTING is `02` as default (Note that a value of `0` is not allowed). 26 | 2. Users need to create a memory section named `mev_address` in `CRAM` for Exclusive Control functionality. Users should initialize the `mev_address` section in the startup file. 27 | 28 | Example: 29 | ``` 30 | ; .mev_address section in CRAM is used for Sync flags 31 | mov #__s.mev_address.bss, r20 32 | st.w r0, 0[r20] 33 | ``` 34 | 3. The `FXU unit` is only available on `core 0`. Users must ensure that FXU operations are restricted to `core 0` by using the `vTaskCoreAffinitySet` function provided by FreeRTOS SMP. 35 | 4. FXU can be enabled by specific compiler option `-DconfigENABLE_FXU`. FPU can be enabled by specific compiler option `-DconfigENABLE_FPU` 36 | 5. The macros `configENABLE_FXU` and `configENABLE_FPU` must be defined in `FreeRTOSConfig.h`. 37 | 6. This port supports both U2Ax and U2Bx devices. The user must configure `configDEVICE_NAME` with the value `U2Bx_DEVICES` or `U2Ax_DEVICES` to specify which device is being used. 38 | 7. The User can configure the interrupt priority of the OSTM Timer using `configTIMER_INT_PRIORITY`, with 16 levels available (0 being the highest priority and 15 the lowest). 39 | 8. This port also supports the configuration of contiguous CPU cores in FreeRTOS, allowing the user to set task affinity for execution on specific cores or subsets of cores. 40 | 41 | 42 | ## Other Relevant Information 43 | 44 | - **Documentation:** 45 | - Refer to the official [FreeRTOS documentation](https://www.freertos.org/Documentation/RTOS_book.html) for detailed information on configuring and using FreeRTOS. 46 | - Consult the [RH850 U2A group user manual hardware manual](https://www.renesas.com/en/document/mah/rh850u2a-eva-group-users-manual-hardware-0?r=1546621) for specific details about the microcontroller. 47 | - Consult the [RH850 U2B group user manual hardware manual](https://www.renesas.com/en/document/mah/rh850u2b-flash-memory-users-manual-r01uh0927ej0100?srsltid=AfmBOooTd6sk-_EsdVV0L_Rw0vGMsaoCQ0SSzpmtoScRcxgcwVkLrQwY) for specific details about the microcontroller. 48 | - For more information about Renesas RH850 microcontrolers, please visit [this website](https://www.renesas.com/us/en/products/microcontrollers-microprocessors/rh850-automotive-mcus) 49 | - The CC-RH compiler can be downloaded [here](https://www.renesas.com/us/en/software-tool/c-compiler-package-rh850-family#downloads) 50 | 51 | - **Support:** 52 | - If you encounter any issues or have questions about this port, please open an issue in this repository or contact the maintainer. 53 | 54 | - **Contributing:** 55 | - Contributions to improve this port are welcome. Please fork the repository, make your changes, and submit a pull request. -------------------------------------------------------------------------------- /CCRH/U2x/portasm.s: -------------------------------------------------------------------------------- 1 | ;/* 2 | ; * FreeRTOS Kernel V11.1.0 3 | ; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. 4 | ; * 5 | ; * SPDX-License-Identifier: MIT 6 | ; * 7 | ; * Permission is hereby granted, free of charge, to any person obtaining a copy of 8 | ; * this software and associated documentation files (the "Software"), to deal in 9 | ; * the Software without restriction, including without limitation the rights to 10 | ; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of 11 | ; * the Software, and to permit persons to whom the Software is furnished to do so, 12 | ; * subject to the following conditions: 13 | ; * 14 | ; * The above copyright notice and this permission notice shall be included in all 15 | ; * copies or substantial portions of the Software. 16 | ; * 17 | ; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 | ; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS 19 | ; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR 20 | ; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER 21 | ; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 22 | ; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 23 | ; * 24 | ; * https://www.FreeRTOS.org 25 | ; * https://github.com/FreeRTOS 26 | ; * 27 | ; */ 28 | 29 | 30 | ;------------------------------------------------------------------------------ 31 | ; Extern symbols 32 | ;------------------------------------------------------------------------------ 33 | .extern _uxInterruptNesting 34 | .extern _uxPortMaxInterruptDepth 35 | .extern _xPortScheduleStatus 36 | .extern _vTaskSwitchContext 37 | .extern _pvPortGetCurrentTCB 38 | .extern _vCommonISRHandler 39 | .extern _xPortGET_CORE_ID 40 | 41 | .public _vIrq_Handler 42 | .public _vPortStartFirstTask 43 | .public _vPortYield 44 | .public _vTRAP0_Handler 45 | ;------------------------------------------------------------------------------ 46 | ; Macro definitions 47 | ;------------------------------------------------------------------------------ 48 | EIPC .set 0 49 | EIPSW .set 1 50 | PSW .set 5 51 | FPSR .set 6 52 | FPEPC .set 7 53 | FXSR .set 6 54 | FXXP .set 13 55 | EIIC .set 13 56 | CTPC .set 16 57 | CTPSW .set 17 58 | EIIC_MSK .set 0x00000FFF 59 | 60 | ;------------------------------------------------------------------------------ 61 | ; portSAVE_CONTEXT 62 | ; Context saving 63 | ;------------------------------------------------------------------------------ 64 | portSAVE_CONTEXT .macro 65 | prepare lp, 0 66 | 67 | ; Save general-purpose registers and EIPSW, EIPC, EIIC, CTPSW, CTPC into stack. 68 | pushsp r5, r30 69 | $nowarning 70 | pushsp r1, r2 71 | $warning 72 | 73 | stsr EIPSW, r15 74 | stsr EIPC, r16 75 | stsr EIIC, r17 76 | stsr CTPSW, r18 77 | stsr CTPC, r19 78 | pushsp r15, r19 79 | 80 | ; Save FPU registers to stack if FPU is enabled 81 | $ifdef configENABLE_FPU 82 | stsr FPSR, r18 83 | stsr FPEPC, r19 84 | pushsp r18, r19 85 | $endif 86 | 87 | ; Save FXU registers to stack if FXU is enabled 88 | $ifdef configENABLE_FXU 89 | mov r0, r20 90 | mov r0, r21 91 | stsr 0, r19, 2 ; Get PEID 92 | cmp r19, r0 ; Confirm PEID value is PE0 93 | bne 8 ; Branch 2 instructions if is not PE0 94 | ; to avoid unprivileged access 95 | stsr FXSR, r20, 10 ; If PE0, save FXU register 96 | stsr FXXP, r21, 10 ; If PE0, save FXU register 97 | pushsp r20, r21 98 | $endif 99 | 100 | ; Get current TCB, the return value is stored in r10 (CCRH compiler) 101 | jarl _pvPortGetCurrentTCB, lp 102 | st.w sp, 0[r10] 103 | 104 | .endm 105 | 106 | ;------------------------------------------------------------------------------ 107 | ; portRESTORE_CONTEXT 108 | ; Context restoring 109 | ;------------------------------------------------------------------------------ 110 | portRESTORE_CONTEXT .macro 111 | ; Current TCB is returned by r10 (CCRH compiler) 112 | jarl _pvPortGetCurrentTCB, lp 113 | ld.w 0[r10], sp ; Restore the stack pointer from the TCB 114 | 115 | ; Restore FXU registers if FXU is enabled 116 | $ifdef configENABLE_FXU 117 | popsp r20, r21 118 | stsr 0, r19, 2 ; Get PEID 119 | cmp r19, r0 ; Confirm PEID value is PE0 120 | bne 8 ; Branch 2 instructions if is not PE0 121 | ; to avoid unprivileged access 122 | ldsr r21, FXXP, 10 ; If PE0, restore FXU register 123 | ldsr r20, FXSR, 10 ; If PE0, restore FXU register 124 | $endif 125 | 126 | ; Restore FPU registers if FPU is enabled 127 | $ifdef configENABLE_FPU 128 | popsp r18, r19 129 | ldsr r19, FPEPC 130 | ldsr r18, FPSR 131 | $endif 132 | 133 | ;Restore general-purpose registers and EIPSW, EIPC, EIIC, CTPSW, CTPC 134 | popsp r15, r19 135 | ldsr r19, CTPC 136 | ldsr r18, CTPSW 137 | ldsr r17, EIIC 138 | ldsr r16, EIPC 139 | ldsr r15, EIPSW 140 | 141 | $nowarning 142 | popsp r1, r2 143 | $warning 144 | popsp r5, r30 145 | 146 | dispose 0, lp 147 | .endm 148 | 149 | ;------------------------------------------------------------------------------ 150 | ; Save used registers 151 | ;------------------------------------------------------------------------------ 152 | SAVE_REGISTER .macro 153 | ; Save general-purpose registers and EIPSW, EIPC, EIIC, CTPSW, CTPC into stack. 154 | ; Callee-Save registers (r20 to r30) are not used in interrupt handler and 155 | ; guaranteed no change after function call. So, do not need to save register 156 | ; to optimize the used stack memory. 157 | pushsp r5, r21 158 | $nowarning 159 | pushsp r1, r2 160 | $warning 161 | 162 | stsr EIPSW, r19 163 | stsr EIPC, r18 164 | stsr EIIC, r17 165 | mov lp, r16 166 | mov ep, r15 167 | stsr CTPSW, r14 168 | stsr CTPC, r13 169 | pushsp r13, r19 170 | 171 | $ifdef configENABLE_FPU 172 | stsr FPSR, r18 173 | stsr FPEPC, r19 174 | pushsp r18, r19 175 | $endif 176 | 177 | ; Save FXU registers to stack if FXU is enabled 178 | $ifdef configENABLE_FXU 179 | mov r0, r20 180 | mov r0, r21 181 | stsr 0, r19, 2 ; Get PEID 182 | cmp r19, r0 ; Confirm PEID value is PE0 183 | bne 8 ; Branch 2 instructions if is not PE0 184 | ; to avoid unprivileged access 185 | stsr FXSR, r20, 10 ; If PE0, save FXU register 186 | stsr FXXP, r21, 10 ; If PE0, save FXU register 187 | pushsp r20, r21 188 | $endif 189 | 190 | .endm 191 | ;------------------------------------------------------------------------------ 192 | ; Restore used registers 193 | ;------------------------------------------------------------------------------ 194 | RESTORE_REGISTER .macro 195 | ; Restore FXU registers if FXU is enabled 196 | $ifdef configENABLE_FXU 197 | popsp r20, r21 198 | stsr 0, r19, 2 ; Get PEID 199 | cmp r19, r0 ; Confirm PEID value is PE0 200 | bne 8 ; Branch 2 instructions if is not PE0 201 | ; to avoid unprivileged access 202 | ldsr r21, FXXP, 10 ; If PE0, restore FXU register 203 | ldsr r20, FXSR, 10 ; If PE0, restore FXU register 204 | $endif 205 | 206 | $ifdef configENABLE_FPU 207 | popsp r18, r19 208 | ldsr r19, FPEPC 209 | ldsr r18, FPSR 210 | $endif 211 | 212 | popsp r13, r19 213 | ldsr r13, CTPC 214 | ldsr r14, CTPSW 215 | mov r15, ep 216 | mov r16, lp 217 | ldsr r17, EIIC 218 | ldsr r18, EIPC 219 | ldsr r19, EIPSW 220 | 221 | $nowarning 222 | popsp r1, r2 223 | $warning 224 | popsp r5, r21 225 | .endm 226 | 227 | ;------------------------------------------------------------------------------ 228 | ; Start the first task. 229 | ;------------------------------------------------------------------------------ 230 | _vPortStartFirstTask: 231 | portRESTORE_CONTEXT 232 | eiret 233 | 234 | ;------------------------------------------------------------------------------ 235 | ; _vPortYield 236 | ;------------------------------------------------------------------------------ 237 | _vPortYield: 238 | trap 0 239 | jmp [lp] ; Return to caller function 240 | 241 | ;------------------------------------------------------------------------------ 242 | ; PortYield handler. This is installed as the TRAP exception handler. 243 | ;------------------------------------------------------------------------------ 244 | _vTRAP0_Handler: 245 | ;Save the context of the current task. 246 | portSAVE_CONTEXT 247 | 248 | ; The use case that portYield() is called from interrupt context as nested interrupt. 249 | ; Context switch should be executed at the most outer of interrupt tree. 250 | ; In that case, set xPortScheduleStatus to flag context switch in interrupt handler. 251 | jarl _xPortGET_CORE_ID, lp ; return value is contained in r10 (CCRH compiler) 252 | mov r10, r11 253 | shl 2, r11 254 | mov #_uxInterruptNesting, r19 255 | add r11, r19 256 | ld.w 0[r19], r18 257 | cmp r0, r18 258 | be _vTRAP0_Handler_ContextSwitch 259 | 260 | mov #_xPortScheduleStatus, r19 261 | add r11, r19 262 | 263 | ; Set xPortScheduleStatus[coreID]=PORT_SCHEDULER_TASKSWITCH 264 | mov 1, r17 265 | st.w r17, 0[r19] 266 | br _vTRAP0_Handler_Exit 267 | 268 | _vTRAP0_Handler_ContextSwitch: 269 | ; Pass coreID (r10) as parameter by r6 (CCRH compiler) in SMP support. 270 | mov r10, r6 271 | ; Call the scheduler to select the next task. 272 | ; vPortYeild may be called to current core again at the end of vTaskSwitchContext. 273 | ; This may case nested interrupt, however, it is not necessary to set 274 | ; uxInterruptNesting (currently 0) for nested trap0 exception. The user interrupt 275 | ; (EI level interrupt) is not accepted inside of trap0 exception. 276 | jarl _vTaskSwitchContext, lp 277 | 278 | _vTRAP0_Handler_Exit: 279 | ; Restore the context of the next task to run. 280 | portRESTORE_CONTEXT 281 | eiret 282 | 283 | ;------------------------------------------------------------------------------ 284 | ; _Irq_Handler 285 | ; Handler interrupt service routine (ISR). 286 | ;------------------------------------------------------------------------------ 287 | _vIrq_Handler: 288 | ; Save used registers. 289 | SAVE_REGISTER 290 | 291 | ; Get core ID by HTCFG0, thread configuration register. 292 | ; Then, increase nesting count for current core. 293 | jarl _xPortGET_CORE_ID, lp ; return value is contained in r10 (CCRH compiler) 294 | mov r10, r17 295 | shl 2, r17 296 | 297 | mov #_uxInterruptNesting, r19 298 | add r17, r19 299 | ld.w 0[r19], r18 300 | addi 0x1, r18, r16 301 | st.w r16, 0[r19] 302 | 303 | pushsp r17, r19 304 | 305 | ;Call the interrupt handler. 306 | stsr EIIC, r6 307 | andi EIIC_MSK, r6, r6 308 | 309 | ; Do not enable interrupt for nesting. Stackover flow may occurs if the 310 | ; depth of nesting interrupt is exceeded. 311 | mov #_uxPortMaxInterruptDepth, r19 312 | ld.w 0[r19], r15 313 | cmp r15, r16 314 | bge 4 ; Jump over ei instruction 315 | ei 316 | jarl _vCommonISRHandler, lp 317 | di 318 | synce 319 | 320 | popsp r17, r19 321 | st.w r18, 0[r19] ; Restore the old nesting count. 322 | 323 | ; A context switch if no nesting interrupt. 324 | cmp 0x0, r18 325 | bne _vIrq_Handler_NotSwitchContext 326 | 327 | ; Check if context switch is requested. 328 | mov #_xPortScheduleStatus, r19 329 | add r17, r19 330 | ld.w 0[r19], r18 331 | cmp r0, r18 332 | bne _vIrq_Handler_SwitchContext 333 | 334 | _vIrq_Handler_NotSwitchContext: 335 | ; No context switch. Restore used registers 336 | RESTORE_REGISTER 337 | eiret 338 | 339 | ;This sequence is executed for primary core only to switch context 340 | _vIrq_Handler_SwitchContext: 341 | ; Clear the context switch pending flag. 342 | st.w r0, 0[r19] 343 | add -1, r18 344 | bnz _vIrq_Handler_StartFirstTask 345 | 346 | ; Restore used registers before saving the context to the task stack. 347 | RESTORE_REGISTER 348 | portSAVE_CONTEXT 349 | 350 | ; Get Core ID and pass to vTaskSwitchContext as parameter (CCRH compiler) 351 | ; The parameter is unused in single core, no problem with this redudant setting 352 | jarl _xPortGET_CORE_ID, lp ; return value is contained in r10 (CCRH compiler) 353 | mov r10, r6 354 | 355 | ; vPortYeild may be called to current core again at the end of vTaskSwitchContext. 356 | ; This may case nested interrupt, however, it is not necessary to set 357 | ; uxInterruptNesting (currently 0) for trap0 exception. The user interrupt 358 | ; (EI level interrupt) is not accepted inside of trap0 exception. 359 | jarl _vTaskSwitchContext, lp 360 | portRESTORE_CONTEXT 361 | eiret 362 | 363 | _vIrq_Handler_StartFirstTask: 364 | RESTORE_REGISTER 365 | jr _vPortStartFirstTask 366 | 367 | -------------------------------------------------------------------------------- /CCRH/U2x/portmacro.h: -------------------------------------------------------------------------------- 1 | /* 2 | * FreeRTOS Kernel V11.1.0 3 | * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. 4 | * 5 | * SPDX-License-Identifier: MIT 6 | * 7 | * Permission is hereby granted, free of charge, to any person obtaining a copy of 8 | * this software and associated documentation files (the "Software"), to deal in 9 | * the Software without restriction, including without limitation the rights to 10 | * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of 11 | * the Software, and to permit persons to whom the Software is furnished to do so, 12 | * subject to the following conditions: 13 | * 14 | * The above copyright notice and this permission notice shall be included in all 15 | * copies or substantial portions of the Software. 16 | * 17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS 19 | * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR 20 | * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER 21 | * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 22 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 23 | * 24 | * https://www.FreeRTOS.org 25 | * https://github.com/FreeRTOS 26 | * 27 | */ 28 | 29 | #ifndef PORTMACRO_H 30 | #define PORTMACRO_H 31 | 32 | #ifdef __cplusplus 33 | extern "C" 34 | { 35 | #endif 36 | 37 | /*----------------------------------------------------------- 38 | * Port specific definitions. 39 | * 40 | * The settings in this file configure FreeRTOS correctly for the 41 | * given hardware and compiler. 42 | * 43 | * These settings should not be altered. 44 | *----------------------------------------------------------- 45 | */ 46 | 47 | /* Type definitions - These are a bit legacy and not really used now, other 48 | * than portSTACK_TYPE and portBASE_TYPE. */ 49 | #define portCHAR char 50 | #define portFLOAT float 51 | #define portDOUBLE double 52 | #define portLONG long 53 | #define portSHORT short 54 | #define portSTACK_TYPE uint32_t 55 | #define portBASE_TYPE long 56 | #define portREGISTER_SEL_0 0 57 | 58 | typedef portSTACK_TYPE StackType_t; 59 | typedef long BaseType_t; 60 | typedef unsigned long UBaseType_t; 61 | 62 | /* Defines the maximum time when using a wait command in a task */ 63 | #if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) 64 | typedef uint16_t TickType_t; 65 | #define portMAX_DELAY ( TickType_t ) 0xffff 66 | #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) 67 | typedef uint32_t TickType_t; 68 | #define portMAX_DELAY ( TickType_t ) 0xffffffffUL 69 | 70 | /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do 71 | * not need to be guarded with a critical section. */ 72 | #define portTICK_TYPE_IS_ATOMIC 1 73 | #else 74 | #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. 75 | #endif 76 | 77 | /*-----------------------------------------------------------*/ 78 | 79 | /* Architecture specifics */ 80 | #define portLDSR( reg, sel, val ) __ldsr_rh( ( reg ), ( sel ), ( val ) ) 81 | #define portSTSR( reg, sel ) __stsr_rh( ( reg ), ( sel ) ) 82 | #define portSYNCM() __syncm() 83 | 84 | /* Specify 16 interrupt priority levels */ 85 | #define portINT_PRIORITY_HIGHEST ( 0x0000U ) /* Level 0 (highest) */ 86 | #define portINT_PRIORITY_LEVEL1 ( 0x0001U ) /* Level 1 */ 87 | #define portINT_PRIORITY_LEVEL2 ( 0x0002U ) /* Level 2 */ 88 | #define portINT_PRIORITY_LEVEL3 ( 0x0003U ) /* Level 3 */ 89 | #define portINT_PRIORITY_LEVEL4 ( 0x0004U ) /* Level 4 */ 90 | #define portINT_PRIORITY_LEVEL5 ( 0x0005U ) /* Level 5 */ 91 | #define portINT_PRIORITY_LEVEL6 ( 0x0006U ) /* Level 6 */ 92 | #define portINT_PRIORITY_LEVEL7 ( 0x0007U ) /* Level 7 */ 93 | #define portINT_PRIORITY_LEVEL8 ( 0x0008U ) /* Level 8 */ 94 | #define portINT_PRIORITY_LEVEL9 ( 0x0009U ) /* Level 9 */ 95 | #define portINT_PRIORITY_LEVEL10 ( 0x000AU ) /* Level 10 */ 96 | #define portINT_PRIORITY_LEVEL11 ( 0x000BU ) /* Level 11 */ 97 | #define portINT_PRIORITY_LEVEL12 ( 0x000CU ) /* Level 12 */ 98 | #define portINT_PRIORITY_LEVEL13 ( 0x000DU ) /* Level 13 */ 99 | #define portINT_PRIORITY_LEVEL14 ( 0x000EU ) /* Level 14 */ 100 | #define portINT_PRIORITY_LOWEST ( 0x000FU ) /* Level 15 (lowest) */ 101 | 102 | /* Determine the descending of the stack from high address to address */ 103 | #define portSTACK_GROWTH ( -1 ) 104 | 105 | /* Determine the time (in milliseconds) corresponding to each tick */ 106 | #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) 107 | 108 | /* It is a multiple of 4 (the two lower-order bits of the address = 0), 109 | * otherwise it will cause MAE (Misaligned Exception) according to the manual */ 110 | #define portBYTE_ALIGNMENT ( 4 ) 111 | 112 | /* Interrupt control macros. */ 113 | 114 | #define portENABLE_INTERRUPTS() __EI() /* Macro to enable all maskable interrupts. */ 115 | #define portDISABLE_INTERRUPTS() __DI() /* Macro to disable all maskable interrupts. */ 116 | #define taskENABLE_INTERRUPTS() portENABLE_INTERRUPTS() 117 | #define taskDISABLE_INTERRUPTS() portDISABLE_INTERRUPTS() 118 | 119 | /* SMP build which means configNUM_CORES is relevant */ 120 | #define portSUPPORT_SMP 1 121 | 122 | #ifndef configNUMBER_OF_CORES 123 | #define configNUMBER_OF_CORES 1 124 | #endif 125 | 126 | /*-----------------------------------------------------------*/ 127 | /* Scheduler utilities */ 128 | 129 | /* Called at the end of an ISR that can cause a context switch */ 130 | extern void vPortSetSwitch( BaseType_t xSwitchRequired ); 131 | 132 | #define portEND_SWITCHING_ISR( x ) vPortSetSwitch( x ) 133 | 134 | #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) 135 | 136 | /* Use to transfer control from one task to perform other tasks of higher priority */ 137 | extern void vPortYield( void ); 138 | 139 | #define portYIELD() vPortYield() 140 | 141 | /* Return the core ID on which the code is running. */ 142 | extern BaseType_t xPortGET_CORE_ID(); 143 | 144 | #define portGET_CORE_ID() xPortGET_CORE_ID() 145 | #define coreid xPortGET_CORE_ID() 146 | 147 | #if ( configNUMBER_OF_CORES > 1 ) 148 | 149 | /* Request the core ID x to yield. */ 150 | extern void vPortYieldCore( uint32_t coreID ); 151 | 152 | #define portYIELD_CORE( x ) vPortYieldCore( x ) 153 | 154 | #define portENTER_CRITICAL_FROM_ISR() vTaskEnterCriticalFromISR() 155 | #define portEXIT_CRITICAL_FROM_ISR( x ) vTaskExitCriticalFromISR( x ) 156 | 157 | #endif /* if ( configNUMBER_OF_CORES > 1 ) */ 158 | 159 | #if ( configNUMBER_OF_CORES == 1 ) 160 | #define portGET_ISR_LOCK( xCoreID ) 161 | #define portRELEASE_ISR_LOCK( xCoreID ) 162 | #define portGET_TASK_LOCK( xCoreID ) 163 | #define portRELEASE_TASK_LOCK( xCoreID ) 164 | #else 165 | extern void vPortRecursiveLockAcquire( BaseType_t xCoreID, BaseType_t xFromIsr ); 166 | extern void vPortRecursiveLockRelease( BaseType_t xCoreID, BaseType_t xFromIsr ); 167 | 168 | #define portGET_ISR_LOCK( xCoreID ) vPortRecursiveLockAcquire( ( xCoreID ), pdTRUE ) 169 | #define portRELEASE_ISR_LOCK( xCoreID ) vPortRecursiveLockRelease( ( xCoreID ), pdTRUE ) 170 | #define portGET_TASK_LOCK( xCoreID ) vPortRecursiveLockAcquire( ( xCoreID ), pdFALSE ) 171 | #define portRELEASE_TASK_LOCK( xCoreID ) vPortRecursiveLockRelease( ( xCoreID ), pdFALSE ) 172 | #endif /* if ( configNUMBER_OF_CORES == 1 ) */ 173 | 174 | /*-----------------------------------------------------------*/ 175 | /* Critical section management. */ 176 | 177 | /* The critical nesting functions defined within tasks.c */ 178 | 179 | extern void vTaskEnterCritical( void ); 180 | extern void vTaskExitCritical( void ); 181 | 182 | /* Macro to mark the start of a critical code region */ 183 | #define portENTER_CRITICAL() vTaskEnterCritical() 184 | 185 | /* Macro to mark the end of a critical code region */ 186 | #define portEXIT_CRITICAL() vTaskExitCritical() 187 | 188 | /*-----------------------------------------------------------*/ 189 | /* Macros to set and clear the interrupt mask. */ 190 | portLONG xPortSetInterruptMask(); 191 | void vPortClearInterruptMask( portLONG ); 192 | 193 | #define portSET_INTERRUPT_MASK() xPortSetInterruptMask() 194 | #define portCLEAR_INTERRUPT_MASK( x ) vPortClearInterruptMask( ( x ) ) 195 | #define portSET_INTERRUPT_MASK_FROM_ISR() xPortSetInterruptMask() 196 | #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vPortClearInterruptMask( ( x ) ) 197 | 198 | /*-----------------------------------------------------------*/ 199 | /* Task function macros as described on the FreeRTOS.org WEB site. */ 200 | 201 | #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) 202 | #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) 203 | 204 | /*-----------------------------------------------------------*/ 205 | 206 | #ifdef __cplusplus 207 | } 208 | #endif 209 | #endif /* PORTMACRO_H */ 210 | -------------------------------------------------------------------------------- /Cadence/Xtensa/LICENSE: -------------------------------------------------------------------------------- 1 | MIT License 2 | 3 | Permission is hereby granted, free of charge, to any person obtaining a copy 4 | of this software and associated documentation files (the "Software"), to deal 5 | in the Software without restriction, including without limitation the rights 6 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 7 | copies of the Software, and to permit persons to whom the Software is 8 | furnished to do so, subject to the following conditions: 9 | 10 | The above copyright notice and this permission notice shall be included in all 11 | copies or substantial portions of the Software. 12 | 13 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 16 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 17 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 18 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 19 | SOFTWARE. 20 | -------------------------------------------------------------------------------- /Cadence/Xtensa/Makefile: -------------------------------------------------------------------------------- 1 | ### Makefile to build the FreeRTOS library ### 2 | 3 | # Build target (options: sim, board) 4 | 5 | TARGET = sim 6 | SMALL = 7 | 8 | # Tools 9 | 10 | CC = xt-clang 11 | AS = xt-clang 12 | AR = xt-ar 13 | ISS = xt-run 14 | XT_CORE = $(patsubst %-params,%,$(notdir $(shell xt-clang --show-config=core))) 15 | CONFIGDIR = $(shell xt-clang --show-config=config) 16 | 17 | # For platform-specific commands 18 | 19 | include $(CONFIGDIR)/misc/hostenv.mk 20 | 21 | # Source code and build locations 22 | 23 | # Build with MPU support 24 | ifeq ($(MPU),1) 25 | MPUFLAGS = -DportUSING_MPU_WRAPPERS=1 -DportALIGN_SECTIONS 26 | endif 27 | 28 | # Build with overlay support 29 | ifeq ($(OVERLAY),1) 30 | OVLYFLAGS = -DXT_USE_THREAD_SAFE_CLIB=1 -DXT_USE_OVLY=1 31 | endif 32 | 33 | SRCROOT = $(subst /,$(S),$(CURDIR)) 34 | TSTROOT = $(subst /,$(S),$(abspath $(SRCROOT)$(S)..$(S)..$(S)..$(S)..$(S)..$(S)..$(S)Demo$(S)ThirdParty$(S)Partner-Supported-Demos$(S)Cadence_Xtensa_ISS_xt-clang$(SMALL))) 35 | BLDROOT = $(TSTROOT)$(S)build 36 | BLDAUX ?= 37 | BLDDIR = $(BLDROOT)$(S)$(XT_CORE)$(BLDAUX) 38 | 39 | FR_SRCDIR = $(abspath $(SRCROOT)$(S)..$(S)..$(S)..$(S)..$(S)..) 40 | FR_SRCDIR2 = $(FR_SRCDIR)$(S)portable$(S)MemMang 41 | ifeq ($(MPU),1) 42 | FR_SRCDIR3 = $(FR_SRCDIR)$(S)portable$(S)Common 43 | endif 44 | XT_SRCDIR = $(SRCROOT) 45 | 46 | vpath %.c $(FR_SRCDIR) $(FR_SRCDIR2) $(FR_SRCDIR3) $(XT_SRCDIR) 47 | vpath %.S $(XT_SRCDIR) 48 | 49 | # File lists 50 | # NOTE: Only heap_4.c is included in the default FreeRTOS build. 51 | # If you want to use another heap manager then edit this file 52 | # and specify the one you want. 53 | 54 | FR_C_FILES = $(notdir $(wildcard $(FR_SRCDIR)/*.c)) \ 55 | $(notdir $(wildcard $(FR_SRCDIR3)/*.c)) \ 56 | heap_4.c 57 | XT_C_FILES = $(notdir $(wildcard $(XT_SRCDIR)/*.c)) 58 | XT_S_FILES = $(notdir $(wildcard $(XT_SRCDIR)/*.S)) 59 | 60 | # List of all .o files that will go into the library 61 | 62 | LIB_C_O = $(patsubst %.c,%.o,$(filter-out asm-offsets.c,$(XT_C_FILES) $(FR_C_FILES))) 63 | LIB_S_O = $(patsubst %.S,%.o,$(XT_S_FILES)) 64 | LIB_O_LIST = $(addprefix $(BLDDIR)/,$(LIB_C_O) $(LIB_S_O)) 65 | 66 | # Output files 67 | 68 | OSLIB = $(BLDDIR)$(S)libfreertos.a 69 | 70 | # Build options 71 | 72 | ifeq ($(TARGET),sim) 73 | DFLAGS = -DXT_SIMULATOR 74 | endif 75 | ifeq ($(TARGET),board) 76 | DFLAGS = -DXT_BOARD 77 | endif 78 | 79 | IFLAGS = \ 80 | -I$(FR_SRCDIR)$(S)include -I$(XT_SRCDIR) -I$(TSTROOT)$(S)common$(S)config_files -I$(BLDDIR) 81 | 82 | CSTD = -std=c99 83 | ifeq ($(OVERLAY),1) 84 | CFLAGS = -Os -g 85 | else 86 | CFLAGS = -O2 -g 87 | endif 88 | WFLAGS = -Werror -Wall -Wextra 89 | CFGFLAGS ?= 90 | CCFLAGS = $(CSTD) $(CFGFLAGS) $(CFLAGS) $(WFLAGS) -mno-coproc -mlongcalls -ffunction-sections -mno-l32r-flix $(DFLAGS) $(MPUFLAGS) $(OVLYFLAGS) 91 | ASFLAGS = $(CCFLAGS) 92 | 93 | # File-specific flags 94 | 95 | FLAGS_xtensa_vectors_xea3 = -mtext-section-literals 96 | 97 | FLAGS_mpu = -mtext-section-literals 98 | FLAGS_portasm = -mtext-section-literals 99 | FLAGS_xtensa_context = -mtext-section-literals -Wno-error 100 | FLAGS_xtensa_coproc_handler = -mtext-section-literals 101 | 102 | # Include dependency rules (generated using -MD) 103 | 104 | -include $(wildcard $(BLDDIR)/*.d) 105 | 106 | # Targets 107 | 108 | all : $(BLDDIR)/.mkdir $(BLDDIR)/reent.h $(OSLIB) 109 | 110 | $(BLDDIR)/.mkdir : 111 | @$(MKPATH) $(BLDDIR) 112 | @echo "" > $@ 113 | 114 | $(BLDDIR)/reent.h : $(BLDDIR)/.mkdir 115 | -$(CP) $(subst /,$(S),$(CONFIGDIR))$(S)xtensa-elf$(S)include$(S)sys$(S)reent.h $(BLDDIR)$(S)reent.h 116 | 117 | $(LIB_O_LIST) : $(BLDDIR)/asm-offsets.h 118 | 119 | $(OSLIB) : $(LIB_O_LIST) 120 | $(AR) -rs $@ $^ 121 | 122 | $(BLDDIR)/asm-offsets.h : asm-offsets.c $(BLDDIR)/.mkdir 123 | $(CC) $(CCFLAGS) $(IFLAGS) -MD -MF $(subst .h,.d,$@) -MT $@ -ffunction-sections -fdata-sections -Wl,--gc-sections -o $@.exe $< 124 | $(ISS) $@.exe > $@ 125 | $(RM) $(subst /,$(S),$@.exe) 126 | 127 | $(BLDDIR)/%.o : %.c $(BLDDIR)/.mkdir 128 | $(CC) $(CCFLAGS) $(IFLAGS) $(FLAGS_$*) -mtext-section-literals -MD -MF $(subst .o,.d,$@) -c -o $@ $< 129 | 130 | $(BLDDIR)/%.o : %.S $(BLDDIR)/.mkdir 131 | $(CC) $(ASFLAGS) $(IFLAGS) $(FLAGS_$*) -MD -MF $(subst .o,.d,$@) -c -o $@ $< 132 | 133 | clean : 134 | $(RM_R) $(BLDDIR) 135 | 136 | clean_all : 137 | $(RM_R) $(BLDROOT) 138 | 139 | .PHONY : all clean clean_all 140 | -------------------------------------------------------------------------------- /Cadence/Xtensa/asm-offsets.c: -------------------------------------------------------------------------------- 1 | #include 2 | #include 3 | #include "../../../../../tasks.c" 4 | 5 | #define DEFINE(sym,val) \ 6 | printf("#define %s %d /* %s */\n", #sym, (val), #val) 7 | 8 | int main(void) 9 | { 10 | DEFINE(TCB_TOP_OF_STACK_OFF, offsetof(TCB_t, pxTopOfStack)); 11 | #if portUSING_MPU_WRAPPERS 12 | DEFINE(TCB_MPU_SETTINGS_OFF, offsetof(TCB_t, xMPUSettings.mpumap)); 13 | DEFINE(MPU_ENTRY_SIZE, sizeof(xthal_MPU_entry)); 14 | DEFINE(MPU_ENTRY_AS_OFF, offsetof(xthal_MPU_entry, as)); 15 | DEFINE(MPU_ENTRY_AT_OFF, offsetof(xthal_MPU_entry, at)); 16 | DEFINE(TCB_TASK_NAME_OFF, offsetof(TCB_t, pcTaskName)); 17 | #endif 18 | #if ( ( portSTACK_GROWTH > 0 ) || ( configRECORD_STACK_HIGH_ADDRESS == 1 ) ) 19 | DEFINE(TCB_END_OF_STACK_OFF, offsetof(TCB_t, pxEndOfStack)); 20 | #endif 21 | #if ( configUSE_C_RUNTIME_TLS_SUPPORT == 1 ) 22 | DEFINE(TCB_IMPURE_PTR_OFF, offsetof(TCB_t, xTLSBlock)); 23 | #endif 24 | } 25 | -------------------------------------------------------------------------------- /Cadence/Xtensa/mpu.S: -------------------------------------------------------------------------------- 1 | /* 2 | * FreeRTOS Kernel 3 | * Copyright (C) 2015-2024 Cadence Design Systems, Inc. 4 | * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. 5 | * 6 | * SPDX-License-Identifier: MIT 7 | * 8 | * Permission is hereby granted, free of charge, to any person obtaining a copy of 9 | * this software and associated documentation files (the "Software"), to deal in 10 | * the Software without restriction, including without limitation the rights to 11 | * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of 12 | * the Software, and to permit persons to whom the Software is furnished to do so, 13 | * subject to the following conditions: 14 | * 15 | * The above copyright notice and this permission notice shall be included in all 16 | * copies or substantial portions of the Software. 17 | * 18 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS 20 | * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR 21 | * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER 22 | * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 23 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 24 | * 25 | * https://www.FreeRTOS.org 26 | * https://github.com/FreeRTOS 27 | * 28 | */ 29 | 30 | #include "xtensa_rtos.h" 31 | #include "portmacro.h" 32 | #include "asm-offsets.h" 33 | 34 | #include 35 | 36 | /******************************************************************************* 37 | 38 | _xt_mpu_restore 39 | 40 | !! MUST BE CALLED ONLY BY 'CALL0' INSTRUCTION !! 41 | 42 | Restores task's MPU state 43 | 44 | Entry Conditions: 45 | A0 = Return address in caller. 46 | 47 | *******************************************************************************/ 48 | #if portUSING_MPU_WRAPPERS 49 | 50 | #if XCHAL_HAVE_XEA3 && (!defined __XTENSA_CALL0_ABI__) 51 | #define A2 a10 52 | #define A3 a11 53 | #define A4 a12 54 | #define A5 a13 55 | #define A6 a14 56 | #else 57 | #define A2 a2 58 | #define A3 a3 59 | #define A4 a4 60 | #define A5 a5 61 | #define A6 a6 62 | #endif 63 | 64 | .altmacro 65 | 66 | .macro mpu_set_entry entry 67 | /* 68 | * Load both first and last entry for a range to avoid memory access 69 | * when region is partially modified which may result in a TLB multihit. 70 | */ 71 | l32i A3, A2, (TCB_MPU_SETTINGS_OFF + (MPU_ENTRY_SIZE * ((portNUM_MAX_SWAPPED_MPU_PAIRS - \entry) * 2 + 1)) + MPU_ENTRY_AT_OFF) 72 | l32i A4, A2, (TCB_MPU_SETTINGS_OFF + (MPU_ENTRY_SIZE * ((portNUM_MAX_SWAPPED_MPU_PAIRS - \entry) * 2 + 1)) + MPU_ENTRY_AS_OFF) 73 | l32i A5, A2, (TCB_MPU_SETTINGS_OFF + (MPU_ENTRY_SIZE * ((portNUM_MAX_SWAPPED_MPU_PAIRS - \entry) * 2 + 0)) + MPU_ENTRY_AT_OFF) 74 | l32i A6, A2, (TCB_MPU_SETTINGS_OFF + (MPU_ENTRY_SIZE * ((portNUM_MAX_SWAPPED_MPU_PAIRS - \entry) * 2 + 0)) + MPU_ENTRY_AS_OFF) 75 | wptlb A3, A4 76 | wptlb A5, A6 77 | .endm 78 | 79 | .section "privileged_functions" 80 | .global _xt_mpu_restore 81 | .type _xt_mpu_restore,@function 82 | .align 4 83 | _xt_mpu_restore: 84 | 85 | movi A2, pxCurrentTCB 86 | l32i A2, A2, 0 87 | beqz A2, .Lset 88 | 89 | movi A3, g_num_used_mpu_entries 90 | l32i A3, A3, 0 91 | movi A4, .Lset 92 | 93 | /* 94 | * A3 = .Lset - 18 * g_num_used_mpu_entries -- is the address of code 95 | * that loads MPU entries of the first g_num_used_mpu_entries regions. 96 | * 18 is the size of piece of code generated by one mpu_set_entry macro 97 | */ 98 | slli A5, A3, 4 99 | addx2 A5, A3, A5 100 | sub A3, A4, A5 101 | 102 | jx A3 103 | 104 | .begin no-transform 105 | 106 | /* Load MPU entries from last to first (not in MPU order, 107 | * in pxCurrentTCB->xMPUSettings order). 108 | */ 109 | .set i, 1 110 | .rept portNUM_MAX_SWAPPED_MPU_PAIRS 111 | mpu_set_entry %i 112 | .set i, i+1 113 | .endr 114 | .Lset: 115 | .end no-transform 116 | isync 117 | 118 | ret 119 | 120 | #ifdef portALIGN_SECTIONS 121 | .section privileged_functions 122 | .align XCHAL_MPU_ALIGN 123 | 124 | .section privileged_data 125 | .align XCHAL_MPU_ALIGN 126 | 127 | .section freertos_system_calls 128 | .align XCHAL_MPU_ALIGN 129 | 130 | .section .text 131 | .align XCHAL_MPU_ALIGN 132 | 133 | .section .data 134 | .align XCHAL_MPU_ALIGN 135 | 136 | .section .literal 137 | .align XCHAL_MPU_ALIGN 138 | 139 | .section .bss 140 | .align XCHAL_MPU_ALIGN 141 | 142 | .section .rodata 143 | .align XCHAL_MPU_ALIGN 144 | 145 | .section private_region1 146 | .align XCHAL_MPU_ALIGN 147 | .section private_region2 148 | .align XCHAL_MPU_ALIGN 149 | .section private_region3 150 | .align XCHAL_MPU_ALIGN 151 | .section private_stack 152 | .align XCHAL_MPU_ALIGN 153 | #endif 154 | 155 | #endif // portUSING_MPU_WRAPPERS 156 | -------------------------------------------------------------------------------- /Cadence/Xtensa/portbenchmark.h: -------------------------------------------------------------------------------- 1 | /* 2 | * FreeRTOS Kernel 3 | * Copyright (C) 2015-2024 Cadence Design Systems, Inc. 4 | * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. 5 | * 6 | * SPDX-License-Identifier: MIT 7 | * 8 | * Permission is hereby granted, free of charge, to any person obtaining a copy of 9 | * this software and associated documentation files (the "Software"), to deal in 10 | * the Software without restriction, including without limitation the rights to 11 | * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of 12 | * the Software, and to permit persons to whom the Software is furnished to do so, 13 | * subject to the following conditions: 14 | * 15 | * The above copyright notice and this permission notice shall be included in all 16 | * copies or substantial portions of the Software. 17 | * 18 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS 20 | * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR 21 | * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER 22 | * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 23 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 24 | * 25 | * https://www.FreeRTOS.org 26 | * https://github.com/FreeRTOS 27 | * 28 | */ 29 | 30 | /* 31 | * This utility helps benchmarking interrupt latency and context switches. 32 | * In order to enable it, set configBENCHMARK to 1 in FreeRTOSConfig.h. 33 | * You will also need to download the FreeRTOS_trace patch that contains 34 | * portbenchmark.c and the complete version of portbenchmark.h 35 | */ 36 | 37 | #ifndef PORTBENCHMARK_H 38 | #define PORTBENCHMARK_H 39 | 40 | #if configBENCHMARK 41 | #error "You need to download the FreeRTOS_trace patch that overwrites this file" 42 | #endif 43 | 44 | #define portbenchmarkINTERRUPT_DISABLE() 45 | #define portbenchmarkINTERRUPT_RESTORE(newstate) 46 | #define portbenchmarkIntLatency() 47 | #define portbenchmarkIntWait() 48 | #define portbenchmarkReset() 49 | #define portbenchmarkPrint() 50 | 51 | #endif /* PORTBENCHMARK */ 52 | -------------------------------------------------------------------------------- /Cadence/Xtensa/portclib.c: -------------------------------------------------------------------------------- 1 | /* 2 | * FreeRTOS Kernel 3 | * Copyright (C) 2015-2024 Cadence Design Systems, Inc. 4 | * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. 5 | * 6 | * SPDX-License-Identifier: MIT 7 | * 8 | * Permission is hereby granted, free of charge, to any person obtaining a copy of 9 | * this software and associated documentation files (the "Software"), to deal in 10 | * the Software without restriction, including without limitation the rights to 11 | * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of 12 | * the Software, and to permit persons to whom the Software is furnished to do so, 13 | * subject to the following conditions: 14 | * 15 | * The above copyright notice and this permission notice shall be included in all 16 | * copies or substantial portions of the Software. 17 | * 18 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS 20 | * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR 21 | * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER 22 | * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 23 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 24 | * 25 | * https://www.FreeRTOS.org 26 | * https://github.com/FreeRTOS 27 | * 28 | */ 29 | 30 | #include "FreeRTOS.h" 31 | 32 | #if XT_USE_THREAD_SAFE_CLIB 33 | 34 | #if XSHAL_CLIB == XTHAL_CLIB_XCLIB 35 | 36 | #include 37 | #include 38 | 39 | #include "semphr.h" 40 | 41 | typedef SemaphoreHandle_t _Rmtx; 42 | 43 | //----------------------------------------------------------------------------- 44 | // Override this and set to nonzero to enable locking. 45 | //----------------------------------------------------------------------------- 46 | int32_t _xclib_use_mt = 1; 47 | 48 | 49 | //----------------------------------------------------------------------------- 50 | // Init lock. 51 | //----------------------------------------------------------------------------- 52 | void 53 | _Mtxinit(_Rmtx * mtx) 54 | { 55 | // There is a little problem here with recursion. At startup _Initlocks() 56 | // is called (within xclib) which attempts to create all the locks which 57 | // comes here and can result in a call to malloc() which can try to lock 58 | // access to the heap which results in another call to _Initlocks(). This 59 | // infinite recursion must be avoided. What we do here is temporarily set 60 | // the _xclib_use_mt to zero so that recursive calls to _Initlocks() will 61 | // become nops. This allows the xSemaphoreCreateRecursiveMutex() function 62 | // to call malloc() safely. 63 | // Note that we could have used statically allocated mutexes instead but 64 | // that requires configSUPPORT_STATIC_ALLOCATION to be defined which in 65 | // turn requires other data such as idle task TCB/stack, timer task TCB/ 66 | // stack to be statically defined. 67 | 68 | _xclib_use_mt = 0; 69 | *mtx = xSemaphoreCreateRecursiveMutex(); 70 | _xclib_use_mt = 1; 71 | } 72 | 73 | //----------------------------------------------------------------------------- 74 | // Destroy lock. 75 | //----------------------------------------------------------------------------- 76 | void 77 | _Mtxdst(_Rmtx * mtx) 78 | { 79 | if ((mtx != NULL) && (*mtx != NULL)) { 80 | vSemaphoreDelete(*mtx); 81 | } 82 | } 83 | 84 | //----------------------------------------------------------------------------- 85 | // Lock. 86 | //----------------------------------------------------------------------------- 87 | void 88 | _Mtxlock(_Rmtx * mtx) 89 | { 90 | if ((mtx != NULL) && (*mtx != NULL)) { 91 | xSemaphoreTakeRecursive(*mtx, portMAX_DELAY); 92 | } 93 | } 94 | 95 | //----------------------------------------------------------------------------- 96 | // Unlock. 97 | //----------------------------------------------------------------------------- 98 | void 99 | _Mtxunlock(_Rmtx * mtx) 100 | { 101 | if ((mtx != NULL) && (*mtx != NULL)) { 102 | xSemaphoreGiveRecursive(*mtx); 103 | } 104 | } 105 | 106 | //----------------------------------------------------------------------------- 107 | // Called by malloc() to allocate blocks of memory from the heap. 108 | //----------------------------------------------------------------------------- 109 | void * 110 | _sbrk_r (struct _reent * reent, int32_t incr) 111 | { 112 | extern char _end[]; 113 | extern char _heap_sentry; 114 | static char * _heap_sentry_ptr = &_heap_sentry; 115 | static char * heap_ptr; 116 | char * base; 117 | 118 | if (!heap_ptr) 119 | heap_ptr = (char *) &_end[0]; 120 | 121 | base = heap_ptr; 122 | if (heap_ptr + incr >= _heap_sentry_ptr) { 123 | reent->_errno = ENOMEM; 124 | return (char *) -1; 125 | } 126 | 127 | heap_ptr += incr; 128 | return base; 129 | } 130 | 131 | //----------------------------------------------------------------------------- 132 | // Global initialization for C library. 133 | //----------------------------------------------------------------------------- 134 | void 135 | vPortClibInit(void) 136 | { 137 | } 138 | 139 | //----------------------------------------------------------------------------- 140 | // Per-thread cleanup stub provided for linking, does nothing. 141 | //----------------------------------------------------------------------------- 142 | void 143 | _reclaim_reent(struct _reent * ptr) 144 | { 145 | (void ) ptr; /* Avoid compiler warning */ 146 | } 147 | 148 | #endif /* XSHAL_CLIB == XTHAL_CLIB_XCLIB */ 149 | 150 | #if XSHAL_CLIB == XTHAL_CLIB_NEWLIB 151 | 152 | #include 153 | #include 154 | #include 155 | #include 156 | #include 157 | 158 | #include "semphr.h" 159 | 160 | static SemaphoreHandle_t xClibMutex; 161 | static uint32_t ulClibInitDone = 0; 162 | 163 | //----------------------------------------------------------------------------- 164 | // Get C library lock. 165 | //----------------------------------------------------------------------------- 166 | void 167 | __malloc_lock(struct _reent * ptr) 168 | { 169 | // Suppress compiler warning. 170 | (void) ptr; 171 | 172 | if (!ulClibInitDone) 173 | return; 174 | 175 | xSemaphoreTakeRecursive(xClibMutex, portMAX_DELAY); 176 | } 177 | 178 | //----------------------------------------------------------------------------- 179 | // Release C library lock. 180 | //----------------------------------------------------------------------------- 181 | void 182 | __malloc_unlock(struct _reent * ptr) 183 | { 184 | // Suppress compiler warning. 185 | (void) ptr; 186 | 187 | if (!ulClibInitDone) 188 | return; 189 | 190 | xSemaphoreGiveRecursive(xClibMutex); 191 | } 192 | 193 | //----------------------------------------------------------------------------- 194 | // Lock for environment. Since we have only one global lock we can just call 195 | // the malloc() lock function. 196 | //----------------------------------------------------------------------------- 197 | void 198 | __env_lock(struct _reent * ptr) 199 | { 200 | __malloc_lock(ptr); 201 | } 202 | 203 | 204 | //----------------------------------------------------------------------------- 205 | // Unlock environment. 206 | //----------------------------------------------------------------------------- 207 | void 208 | __env_unlock(struct _reent * ptr) 209 | { 210 | __malloc_unlock(ptr); 211 | } 212 | 213 | //----------------------------------------------------------------------------- 214 | // Called by malloc() to allocate blocks of memory from the heap. 215 | //----------------------------------------------------------------------------- 216 | void * 217 | _sbrk_r (struct _reent * reent, int32_t incr) 218 | { 219 | extern char _end[]; 220 | extern char _heap_sentry; 221 | static char * _heap_sentry_ptr = &_heap_sentry; 222 | static char * heap_ptr; 223 | char * base; 224 | 225 | if (!heap_ptr) 226 | heap_ptr = (char *) &_end[0]; 227 | 228 | base = heap_ptr; 229 | if (heap_ptr + incr >= _heap_sentry_ptr) { 230 | reent->_errno = ENOMEM; 231 | return (char *) -1; 232 | } 233 | 234 | heap_ptr += incr; 235 | return base; 236 | } 237 | 238 | //----------------------------------------------------------------------------- 239 | // Global initialization for C library. 240 | //----------------------------------------------------------------------------- 241 | void 242 | vPortClibInit(void) 243 | { 244 | configASSERT(!ulClibInitDone); 245 | 246 | xClibMutex = xSemaphoreCreateRecursiveMutex(); 247 | ulClibInitDone = 1; 248 | } 249 | 250 | //----------------------------------------------------------------------------- 251 | // Per-thread cleanup stub provided for linking, does nothing. 252 | //----------------------------------------------------------------------------- 253 | void 254 | _reclaim_reent(struct _reent * ptr) 255 | { 256 | (void ) ptr; /* Avoid compiler warning */ 257 | } 258 | 259 | #endif /* XSHAL_CLIB == XTHAL_CLIB_NEWLIB */ 260 | 261 | #endif /* XT_USE_THREAD_SAFE_CLIB */ 262 | -------------------------------------------------------------------------------- /Cadence/Xtensa/porttrace.h: -------------------------------------------------------------------------------- 1 | /* 2 | * FreeRTOS Kernel 3 | * Copyright (C) 2015-2024 Cadence Design Systems, Inc. 4 | * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. 5 | * 6 | * SPDX-License-Identifier: MIT 7 | * 8 | * Permission is hereby granted, free of charge, to any person obtaining a copy of 9 | * this software and associated documentation files (the "Software"), to deal in 10 | * the Software without restriction, including without limitation the rights to 11 | * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of 12 | * the Software, and to permit persons to whom the Software is furnished to do so, 13 | * subject to the following conditions: 14 | * 15 | * The above copyright notice and this permission notice shall be included in all 16 | * copies or substantial portions of the Software. 17 | * 18 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS 20 | * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR 21 | * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER 22 | * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 23 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 24 | * 25 | * https://www.FreeRTOS.org 26 | * https://github.com/FreeRTOS 27 | * 28 | */ 29 | 30 | /* 31 | * This utility helps tracing the entering and exiting from tasks. 32 | * It maintains a circular buffer of tasks in the order they execute, 33 | * and their execution time. To enable it, set configUSE_TRACE_FACILITY_2 34 | * to 1 in FreeRTOSConfig.h. You will also need to download the 35 | * FreeRTOS_trace patch that contains porttrace.c and the complete version 36 | * of porttrace.h. 37 | */ 38 | 39 | #ifndef PORTTRACE_H 40 | #define PORTTRACE_H 41 | 42 | #if configUSE_TRACE_FACILITY_2 43 | #error "You need to download the FreeRTOS_trace patch that overwrites this file" 44 | #endif 45 | 46 | #define porttracePrint(nelements) 47 | #define porttraceStamp(stamp, count_incr) 48 | 49 | #endif /* PORTTRACE_H */ 50 | -------------------------------------------------------------------------------- /Cadence/Xtensa/relnotes.txt: -------------------------------------------------------------------------------- 1 | Notes for Version 3.00 2 | ---------------------- 3 | 4 | - This version supports FreeRTOS version 11.0.0. 5 | 6 | - The directory structure and makefiles have been reorganized to conform 7 | to the structure of FreeRTOS version 11.0.0. 8 | 9 | 10 | Notes for Version 2.40 11 | ---------------------- 12 | 13 | - Now supports Xtensa LX processors with up to 128 interrupts. 14 | Note: XT_USE_SWPRI only supported on LX processors with <= 32 interrupts. 15 | 16 | 17 | Notes for Version 2.30 18 | ---------------------- 19 | 20 | - Code overlay support enabled (for Xtensa LX only). An example 21 | is provided in the demos/cadence/sim directory. Code overlay 22 | support requires mutexes. 23 | 24 | 25 | Notes for Version 2.20 26 | ---------------------- 27 | 28 | - FreeRTOS kernel version updated to 10.4.4. 29 | 30 | - XAF config defaults brought back into 10.4.4-stable branch. 31 | Variable frequency support is merged into this branch as well. 32 | 33 | 34 | Notes for Version 2.10 35 | ---------------------- 36 | 37 | - Now supports Xtensa NX processors. 38 | 39 | 40 | Notes for Version 2.01 41 | ---------------------- 42 | 43 | - Modified debug exception handling to allow user-supplied handler to 44 | be installed. The user handler can be a C function and is installed 45 | like so - 46 | 47 | xt_set_exception_handler( EXCCAUSE_DEBUG, dbg_handler ); 48 | 49 | 50 | Notes for version 2.0 51 | --------------------- 52 | 53 | - Extensive refactor of code to eliminate use of MPU struct for saving 54 | coprocessor state. Coprocessor exception handling has been redone. 55 | 56 | - Low power sleep support (tickless idle) added. 57 | 58 | - Removed use of XTOS header files and macros. Renamed port macros to 59 | avoid name conflicts with XTOS macros. 60 | 61 | - More compiler warnings enabled for build (-Werror -Wextra -std=c99). 62 | 63 | - Interrupt and exception API reworked. Timer setup and handling mostly 64 | converted to C code and simplified. 65 | 66 | 67 | Notes for version 1.7 68 | --------------------- 69 | 70 | - portSTACK_TYPE changed to uint32_t from uint8_t. Stack size definitions 71 | adjusted accordingly. 72 | 73 | - portYIELD_FROM_ISR changed to call _frxt_setup_switch conditionally. 74 | 75 | - Tick handler calls xTaskIncrementTick inside critical region to prevent 76 | interrupt nesting issues. 77 | 78 | 79 | Notes for version 1.6 80 | --------------------- 81 | 82 | - This version supports FreeRTOS version 10.0.0. 83 | 84 | - The directory structure and makefiles have been reorganized to conform 85 | to the structure of FreeRTOS version 10.0.0. 86 | 87 | 88 | Notes for version 1.5 89 | --------------------- 90 | 91 | - This version supports FreeRTOS version 9.0.0. 92 | 93 | - This version supports thread safe operation with the Xtensa C Library 94 | (xclib) in addition to the Newlib C library (newlib). 95 | The xtensa_config.h file is set up to enable thread safe operation by 96 | default if xclib or newlib is detected. Use -D XT_USE_THREAD_SAFE_CLIB=0 97 | on the command line or in the project definition to disable this. 98 | 99 | - Incorrect function prototypes for xt_ints_on/xt_ints_off have been fixed. 100 | 101 | 102 | Notes for version 1.4.2 103 | ----------------------- 104 | 105 | - This version implements a bugfix. The bug was that even when the 106 | config parameter "configUSE_TIME_SLICING" was set to zero, time 107 | slicing would still occur due to a problem in the Xtensa interrupt 108 | processing code. 109 | 110 | - The "small_test" test has been added to illustrate how FreeRTOS 111 | can be configured to reduce the memory footprint. 112 | 113 | 114 | Notes for version 1.4 115 | --------------------- 116 | 117 | - This version supports FreeRTOS version 8.2.0. 118 | 119 | - This version adds a new test xt_intr.c for interrupts testing. 120 | 121 | - This version separates the trace and benchmark facilities into a 122 | separate downloadable. 123 | 124 | 125 | Notes for version 1.3 126 | --------------------- 127 | 128 | - This version implements a separate interrupt stack. The interrupt 129 | dispatch code saves the current task's state on to the task's own 130 | stack and then switches to the interrupt stack for the interrupt 131 | processing. Nested interrupts will continue to use the interrupt 132 | stack. This helps to reduce the sizes of task stacks, since task 133 | stacks no longer have to account for space to accommodate possible 134 | nested interrupts. The size of the interrupt stack is controlled 135 | by a config parameter. 136 | 137 | 138 | Notes for version 1.2 139 | --------------------- 140 | 141 | - This version supports FreeRTOS version 8.1.2. 142 | 143 | - This version supports both CALL0 and windowed Xtensa configurations. 144 | 145 | - This version supports thread safe operation for the Newlib C library. 146 | 147 | - This version introduces an API for installing low/medium priority 148 | interrupt handlers and exception handlers, which can be written in C. 149 | See xtensa_api.h for details. 150 | 151 | - This version supports software prioritization of interrupts at the 152 | same level. Define XT_USE_SWPRI to use this feature. Higher-numbered 153 | interrupts are handled at a higher priority than lower-numbered ones. 154 | 155 | - The FreeRTOS demo application requires a stack size of at least 4 KB. 156 | The standalone tests should be able to run with smaller stack sizes. 157 | The minimum stack size depends on the specific Xtensa configuration. 158 | Adjust the stack size of your application as required. 159 | 160 | - The examples are all defined with a heap size of 256 KB. This could 161 | be a problem with Xtensa configurations that have only small amounts 162 | of memory. Adjust the heap size to suit your platform and application. 163 | There is an example of a small-footprint configuration in the directory 164 | Xtensa_XCC_small. 165 | 166 | - NOTE: Code overlay support is not yet enabled for this port, even though 167 | the support code is present. This feature is not enabled nor tested. 168 | Do not define XT_USE_OVLY when building. 169 | 170 | -End- 171 | -------------------------------------------------------------------------------- /Cadence/Xtensa/xtensa_api.h: -------------------------------------------------------------------------------- 1 | /* 2 | * FreeRTOS Kernel 3 | * Copyright (C) 2015-2024 Cadence Design Systems, Inc. 4 | * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. 5 | * 6 | * SPDX-License-Identifier: MIT 7 | * 8 | * Permission is hereby granted, free of charge, to any person obtaining a copy of 9 | * this software and associated documentation files (the "Software"), to deal in 10 | * the Software without restriction, including without limitation the rights to 11 | * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of 12 | * the Software, and to permit persons to whom the Software is furnished to do so, 13 | * subject to the following conditions: 14 | * 15 | * The above copyright notice and this permission notice shall be included in all 16 | * copies or substantial portions of the Software. 17 | * 18 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS 20 | * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR 21 | * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER 22 | * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 23 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 24 | * 25 | * https://www.FreeRTOS.org 26 | * https://github.com/FreeRTOS 27 | * 28 | */ 29 | 30 | /* 31 | * Xtensa-specific API for RTOS ports. 32 | */ 33 | 34 | #ifndef __XTENSA_API_H__ 35 | #define __XTENSA_API_H__ 36 | 37 | #include 38 | #include 39 | 40 | #include "mpu_wrappers.h" 41 | #include "xtensa_context.h" 42 | 43 | 44 | /* Typedef for C-callable interrupt handler function */ 45 | typedef void (*xt_handler)(void *); 46 | 47 | /* Typedef for C-callable exception handler function */ 48 | typedef void (*xt_exc_handler)(XtExcFrame *); 49 | 50 | 51 | /* 52 | ------------------------------------------------------------------------------- 53 | Call this function to set a handler for the specified exception. 54 | 55 | n - Exception number (type) 56 | f - Handler function address, NULL to uninstall handler. 57 | 58 | The handler will be passed a pointer to the exception frame, which is created 59 | on the stack of the thread that caused the exception. 60 | 61 | If the handler returns, the thread context will be restored and the faulting 62 | instruction will be retried. Any values in the exception frame that are 63 | modified by the handler will be restored as part of the context. For details 64 | of the exception frame structure see xtensa_context.h. 65 | ------------------------------------------------------------------------------- 66 | */ 67 | extern xt_exc_handler xt_set_exception_handler( uint32_t n, xt_exc_handler f ) PRIVILEGED_FUNCTION; 68 | 69 | 70 | /* 71 | ------------------------------------------------------------------------------- 72 | Call this function to set a handler for the specified interrupt. 73 | 74 | n - Interrupt number. 75 | f - Handler function address, NULL to uninstall handler. 76 | arg - Argument to be passed to handler. 77 | ------------------------------------------------------------------------------- 78 | */ 79 | extern xt_handler xt_set_interrupt_handler( uint32_t n, xt_handler f, void * arg ) PRIVILEGED_FUNCTION; 80 | 81 | 82 | /* 83 | ------------------------------------------------------------------------------- 84 | Call this function to enable the specified interrupt. 85 | 86 | intnum - Interrupt number to be enabled. 87 | 88 | Returns: Nothing. 89 | ------------------------------------------------------------------------------- 90 | */ 91 | extern void xt_interrupt_enable( uint32_t intnum ) PRIVILEGED_FUNCTION; 92 | 93 | 94 | /* 95 | ------------------------------------------------------------------------------- 96 | Call this function to disable the specified interrupt. 97 | 98 | intnum - Interrupt number to be disabled. 99 | 100 | Returns: Nothing. 101 | ------------------------------------------------------------------------------- 102 | */ 103 | extern void xt_interrupt_disable( uint32_t intnum ) PRIVILEGED_FUNCTION; 104 | 105 | 106 | /* 107 | ------------------------------------------------------------------------------- 108 | Call this function to check the enable state of the specified interrupt. 109 | 110 | intnum - Interrupt number to be checked. 111 | 112 | Returns: 1 if the specified interrupt is enabled, zero if the interrupt is 113 | disabled, zero if the interrupt number is invalid. 114 | ------------------------------------------------------------------------------- 115 | */ 116 | uint32_t 117 | xt_interrupt_enabled( uint32_t intnum ) PRIVILEGED_FUNCTION; 118 | 119 | 120 | /* 121 | ------------------------------------------------------------------------------- 122 | Call this function to trigger the specified (s/w) interrupt. 123 | 124 | intnum - Interrupt number to be triggered. 125 | 126 | Returns: Nothing. 127 | ------------------------------------------------------------------------------- 128 | */ 129 | extern void xt_interrupt_trigger( uint32_t intnum ) PRIVILEGED_FUNCTION; 130 | 131 | 132 | /* 133 | ------------------------------------------------------------------------------- 134 | Call this function to clear the specified (s/w or edge-triggered) 135 | interrupt. 136 | 137 | intnum - Interrupt number to be cleared. 138 | 139 | Returns: Nothing. 140 | ------------------------------------------------------------------------------- 141 | */ 142 | extern void xt_interrupt_clear( uint32_t intnum ) PRIVILEGED_FUNCTION; 143 | 144 | 145 | /* 146 | ------------------------------------------------------------------------------- 147 | Update CPU core/timer frequency. 148 | 149 | This is implemented when configUSE_TICKLESS_IDLE is set to 1. 150 | XT_CLOCK_FREQ or xtbsp_clock_freq_hz must return new clock frequency 151 | when this function is called. 152 | 153 | This function should be called as soon as the core frequency has changed. 154 | It is safe to call it from an interrupt service routine. 155 | It will update deadline of the internal tick timer and cache new core 156 | frequency. 157 | 158 | Returns: Nothing 159 | ------------------------------------------------------------------------------- 160 | */ 161 | extern void xt_update_clock_frequency( void ) PRIVILEGED_FUNCTION; 162 | 163 | /* 164 | * These map directly to HAL functions. 165 | */ 166 | #define xt_get_ccount xthal_get_ccount 167 | #define xt_get_ccompare(t) xthal_get_ccompare(t) 168 | #define xt_set_ccompare(t,v) xthal_set_ccompare(t,v) 169 | 170 | 171 | #endif /* __XTENSA_API_H__ */ 172 | -------------------------------------------------------------------------------- /Cadence/Xtensa/xtensa_config.h: -------------------------------------------------------------------------------- 1 | /* 2 | * FreeRTOS Kernel 3 | * Copyright (C) 2015-2024 Cadence Design Systems, Inc. 4 | * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. 5 | * 6 | * SPDX-License-Identifier: MIT 7 | * 8 | * Permission is hereby granted, free of charge, to any person obtaining a copy of 9 | * this software and associated documentation files (the "Software"), to deal in 10 | * the Software without restriction, including without limitation the rights to 11 | * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of 12 | * the Software, and to permit persons to whom the Software is furnished to do so, 13 | * subject to the following conditions: 14 | * 15 | * The above copyright notice and this permission notice shall be included in all 16 | * copies or substantial portions of the Software. 17 | * 18 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS 20 | * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR 21 | * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER 22 | * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 23 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 24 | * 25 | * https://www.FreeRTOS.org 26 | * https://github.com/FreeRTOS 27 | * 28 | */ 29 | 30 | /* 31 | * Configuration-specific information for Xtensa build. This file must be 32 | * included in FreeRTOSConfig.h to properly set up the config-dependent 33 | * parameters correctly. 34 | * 35 | * NOTE: To enable thread-safe C library support, XT_USE_THREAD_SAFE_CLIB must 36 | * be defined to be > 0 somewhere above or on the command line. 37 | */ 38 | 39 | #ifndef XTENSA_CONFIG_H 40 | #define XTENSA_CONFIG_H 41 | 42 | /* *INDENT-OFF* */ 43 | #ifdef __cplusplus 44 | extern "C" { 45 | #endif 46 | /* *INDENT-ON* */ 47 | 48 | #include 49 | #include 50 | #include /* required for XSHAL_CLIB */ 51 | 52 | #include "xtensa_context.h" 53 | 54 | 55 | /*----------------------------------------------------------------------------- 56 | * STACK REQUIREMENTS 57 | * 58 | * This section defines the minimum stack size, and the extra space required to 59 | * be allocated for saving coprocessor state on the stack when needed. The sizes 60 | * are in bytes. 61 | * 62 | * Stack sizes for individual tasks should be derived from these minima based on 63 | * the maximum call depth of the task. A minimum stack size is defined by the 64 | * XT_STACK_MIN_SIZE value. This minimum is based on the requirement for a task 65 | * that calls nothing else but can be interrupted. 66 | * 67 | * If the Xtensa processor configuration includes coprocessors, then space is 68 | * allocated to save the coprocessor state on the stack. 69 | * 70 | * If thread safety is enabled for the C runtime library, (XT_USE_THREAD_SAFE_CLIB 71 | * is defined) then space is allocated to save the C library context in the TCB. 72 | * 73 | * Allocating insufficient stack space is a common source of hard-to-find errors. 74 | * During development, it is best to enable the FreeRTOS stack checking features. 75 | * 76 | * Usage: 77 | * 78 | * XT_USE_THREAD_SAFE_CLIB -- Define this to a nonzero value to enable thread-safe 79 | * use of the C library. 80 | * 81 | * NOTE: The Xtensa toolchain supports multiple C libraries and not all of them 82 | * support thread safety. Check your core configuration to see which C library 83 | * was chosen for your system. 84 | * 85 | * XT_STACK_MIN_SIZE -- The minimum stack size for any task. It is recommended 86 | * that you do not use a stack smaller than this for any 87 | * task. In case you want to use stacks smaller than this 88 | * size, you must verify that the smaller size(s) will work 89 | * under all operating conditions. 90 | * 91 | * XT_STACK_EXTRA -- The amount of extra stack space to be allocated for the 92 | * system overhead (coprocessor state, exception frame etc.). 93 | * Add this to the amount of stack space required by the 94 | * task itself. 95 | * 96 | * XT_SYSTEM_STACK_SIZE -- The size of the system interrupt stack. You will need to 97 | * size this according to your system requirements. 98 | -----------------------------------------------------------------------------*/ 99 | 100 | /* Extra space required for interrupt/exception hooks. */ 101 | #ifdef XT_INTEXC_HOOKS 102 | #ifdef __XTENSA_CALL0_ABI__ 103 | #define STK_INTEXC_EXTRA 0x200 104 | #else 105 | #define STK_INTEXC_EXTRA 0x180 106 | #endif 107 | #else 108 | #define STK_INTEXC_EXTRA 0 109 | #endif 110 | 111 | /* Check C library thread safety support and compute size of C library save area. 112 | For the supported libraries, we enable thread safety by default, and this can 113 | be overridden from the compiler/make command line. */ 114 | #if (XSHAL_CLIB == XTHAL_CLIB_NEWLIB) || (XSHAL_CLIB == XTHAL_CLIB_XCLIB) 115 | #ifndef XT_USE_THREAD_SAFE_CLIB 116 | #define XT_USE_THREAD_SAFE_CLIB 1 117 | #endif 118 | #else 119 | #define XT_USE_THREAD_SAFE_CLIB 0 120 | #endif 121 | 122 | #if XT_USE_THREAD_SAFE_CLIB > 0u 123 | #if XSHAL_CLIB == XTHAL_CLIB_XCLIB 124 | #define XT_HAVE_THREAD_SAFE_CLIB 1 125 | #if !defined __ASSEMBLER__ 126 | #include 127 | #define XT_CLIB_CONTEXT_AREA_SIZE ((sizeof(struct _reent) + 15) + (-16)) 128 | #define XT_CLIB_GLOBAL_PTR _reent_ptr 129 | #define _REENT_INIT_PTR _init_reent 130 | #define _impure_ptr _reent_ptr 131 | 132 | void _reclaim_reent(struct _reent * ptr); 133 | #endif 134 | #elif XSHAL_CLIB == XTHAL_CLIB_NEWLIB 135 | #define XT_HAVE_THREAD_SAFE_CLIB 1 136 | #if !defined __ASSEMBLER__ 137 | #include 138 | #define XT_CLIB_CONTEXT_AREA_SIZE ((sizeof(struct _reent) + 15) + (-16)) 139 | #define XT_CLIB_GLOBAL_PTR _impure_ptr 140 | 141 | void _reclaim_reent(struct _reent * ptr); 142 | #endif 143 | #else 144 | #define XT_HAVE_THREAD_SAFE_CLIB 0 145 | #error The selected C runtime library is not thread safe. 146 | #endif 147 | #else 148 | #define XT_CLIB_CONTEXT_AREA_SIZE 0 149 | #endif 150 | 151 | /*------------------------------------------------------------------------------ 152 | Extra size -- interrupt frame plus coprocessor save area plus hook space. 153 | NOTE: Make sure XT_INTEXC_HOOKS is undefined unless you really need the hooks. 154 | ------------------------------------------------------------------------------*/ 155 | #ifdef __XTENSA_CALL0_ABI__ 156 | #define XT_XTRA_SIZE (XT_STK_FRMSZ + STK_INTEXC_EXTRA + 0x10 + XT_CP_SIZE) 157 | #else 158 | #define XT_XTRA_SIZE (XT_STK_FRMSZ + STK_INTEXC_EXTRA + 0x20 + XT_CP_SIZE) 159 | #endif 160 | 161 | /*------------------------------------------------------------------------------ 162 | Space allocated for user code -- function calls and local variables. 163 | NOTE: This number can be adjusted to suit your needs. You must verify that the 164 | amount of space you reserve is adequate for the worst-case conditions in your 165 | application. 166 | NOTE: The windowed ABI requires more stack, since space has to be reserved 167 | for spilling register windows. 168 | ------------------------------------------------------------------------------*/ 169 | #ifdef __XTENSA_CALL0_ABI__ 170 | #define XT_USER_SIZE 0x200 171 | #else 172 | #define XT_USER_SIZE 0x400 173 | #endif 174 | 175 | /* Minimum recommended stack size. */ 176 | #define XT_STACK_MIN_SIZE ((XT_XTRA_SIZE + XT_USER_SIZE) / sizeof(unsigned char)) 177 | 178 | /* OS overhead. */ 179 | #define XT_STACK_EXTRA (XT_XTRA_SIZE) 180 | 181 | /* Default system (interrupt) stack size */ 182 | #define XT_SYSTEM_STACK_SIZE 0x400 183 | 184 | /* *INDENT-OFF* */ 185 | #ifdef __cplusplus 186 | } 187 | #endif 188 | /* *INDENT-ON* */ 189 | 190 | #endif /* XTENSA_CONFIG_H */ 191 | -------------------------------------------------------------------------------- /Cadence/Xtensa/xtensa_intr.c: -------------------------------------------------------------------------------- 1 | /* 2 | * FreeRTOS Kernel 3 | * Copyright (C) 2015-2024 Cadence Design Systems, Inc. 4 | * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. 5 | * 6 | * SPDX-License-Identifier: MIT 7 | * 8 | * Permission is hereby granted, free of charge, to any person obtaining a copy of 9 | * this software and associated documentation files (the "Software"), to deal in 10 | * the Software without restriction, including without limitation the rights to 11 | * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of 12 | * the Software, and to permit persons to whom the Software is furnished to do so, 13 | * subject to the following conditions: 14 | * 15 | * The above copyright notice and this permission notice shall be included in all 16 | * copies or substantial portions of the Software. 17 | * 18 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS 20 | * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR 21 | * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER 22 | * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 23 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 24 | * 25 | * https://www.FreeRTOS.org 26 | * https://github.com/FreeRTOS 27 | * 28 | */ 29 | 30 | /* 31 | * Xtensa-specific interrupt and exception functions for RTOS ports. 32 | * Also see xtensa_intr_asm.S. 33 | */ 34 | 35 | #include 36 | 37 | #include 38 | #include 39 | #if XCHAL_HAVE_INTERRUPTS 40 | #include 41 | #endif 42 | 43 | #include "xtensa_api.h" 44 | 45 | 46 | #if XCHAL_HAVE_EXCEPTIONS 47 | 48 | /* Handler table is in xtensa_intr_asm.S */ 49 | extern xt_exc_handler xt_exception_table[XCHAL_EXCCAUSE_NUM]; 50 | 51 | 52 | /* 53 | Default handler for unhandled exceptions. 54 | */ 55 | void 56 | xt_unhandled_exception( XtExcFrame * frame ) 57 | { 58 | (void) frame; 59 | exit( -1 ); 60 | } 61 | 62 | 63 | /* 64 | This function registers a handler for the specified exception. 65 | The function returns the address of the previous handler. 66 | On error, it returns NULL. 67 | */ 68 | xt_exc_handler 69 | xt_set_exception_handler( uint32_t n, xt_exc_handler f ) 70 | { 71 | xt_exc_handler old; 72 | 73 | if ( n >= (uint32_t) XCHAL_EXCCAUSE_NUM ) 74 | { 75 | // Invalid exception number. 76 | return NULL; 77 | } 78 | 79 | old = xt_exception_table[n]; 80 | 81 | if ( f != NULL ) 82 | { 83 | xt_exception_table[n] = f; 84 | } 85 | else 86 | { 87 | xt_exception_table[n] = &xt_unhandled_exception; 88 | } 89 | 90 | return old; 91 | } 92 | 93 | #endif 94 | 95 | #if XCHAL_HAVE_INTERRUPTS 96 | 97 | #if XCHAL_HAVE_XEA2 && (XCHAL_NUM_INTERRUPTS <= 32) 98 | /* Defined in xtensa_intr_asm.S */ 99 | extern uint32_t xt_intenable; 100 | extern uint32_t xt_vpri_mask; 101 | #endif 102 | 103 | /* Handler table is in xtensa_intr_asm.S */ 104 | typedef struct xt_handler_table_entry { 105 | xt_handler handler; 106 | void * arg; 107 | } xt_handler_table_entry; 108 | 109 | #if (XT_USE_INT_WRAPPER || XCHAL_HAVE_XEA3) 110 | extern xt_handler_table_entry _xt_interrupt_table[XCHAL_NUM_INTERRUPTS + 1]; 111 | #else 112 | extern xt_handler_table_entry _xt_interrupt_table[XCHAL_NUM_INTERRUPTS]; 113 | #endif 114 | 115 | 116 | /* 117 | Default handler for unhandled interrupts. 118 | */ 119 | void 120 | xt_unhandled_interrupt( void * arg ) 121 | { 122 | (void) arg; 123 | exit( -1 ); 124 | } 125 | 126 | 127 | /* 128 | This function registers a handler for the specified interrupt. The "arg" 129 | parameter specifies the argument to be passed to the handler when it is 130 | invoked. The function returns the address of the previous handler. 131 | On error, it returns NULL. 132 | */ 133 | xt_handler 134 | xt_set_interrupt_handler( uint32_t n, xt_handler f, void * arg ) 135 | { 136 | xt_handler_table_entry * entry; 137 | xt_handler old; 138 | 139 | if ( n >= (uint32_t) XCHAL_NUM_INTERRUPTS ) 140 | { 141 | // Invalid interrupt number. 142 | return NULL; 143 | } 144 | 145 | #if XCHAL_HAVE_XEA2 146 | if ( Xthal_intlevel[n] > XCHAL_EXCM_LEVEL ) 147 | { 148 | // Priority level too high to safely handle in C. 149 | return NULL; 150 | } 151 | #endif 152 | 153 | #if (XT_USE_INT_WRAPPER || XCHAL_HAVE_XEA3) 154 | entry = _xt_interrupt_table + n + 1; 155 | #else 156 | entry = _xt_interrupt_table + n; 157 | #endif 158 | old = entry->handler; 159 | 160 | if ( f != NULL ) 161 | { 162 | entry->handler = f; 163 | entry->arg = arg; 164 | } 165 | else 166 | { 167 | entry->handler = &xt_unhandled_interrupt; 168 | entry->arg = (void*)n; 169 | } 170 | 171 | return old; 172 | } 173 | 174 | 175 | /* 176 | This function enables the interrupt whose number is specified as 177 | the argument. 178 | */ 179 | void 180 | xt_interrupt_enable( uint32_t intnum ) 181 | { 182 | #if XCHAL_HAVE_XEA2 && (XCHAL_NUM_INTERRUPTS <= 32) 183 | if ( intnum < (uint32_t) XCHAL_NUM_INTERRUPTS ) 184 | { 185 | int ps = XT_RSIL( 15 ); 186 | 187 | // New INTENABLE = (xt_intenable | mask) & xt_vpri_mask. 188 | xt_intenable |= ( 1U << intnum ); 189 | XT_WSR_INTENABLE( xt_intenable & xt_vpri_mask ); 190 | XT_WSR_PS( ps ); 191 | XT_RSYNC(); 192 | } 193 | #else 194 | xthal_interrupt_enable( intnum ); 195 | #endif 196 | } 197 | 198 | 199 | /* 200 | This function disables the interrupt whose number is specified as 201 | the argument. 202 | */ 203 | void 204 | xt_interrupt_disable( uint32_t intnum ) 205 | { 206 | #if XCHAL_HAVE_XEA2 && (XCHAL_NUM_INTERRUPTS <= 32) 207 | if ( intnum < (uint32_t) XCHAL_NUM_INTERRUPTS ) 208 | { 209 | int ps = XT_RSIL( 15 ); 210 | 211 | // New INTENABLE = (xt_intenable & ~mask) & xt_vpri_mask. 212 | xt_intenable &= ~( 1U << intnum ); 213 | XT_WSR_INTENABLE( xt_intenable & xt_vpri_mask ); 214 | XT_WSR_PS( ps ); 215 | XT_RSYNC(); 216 | } 217 | #else 218 | xthal_interrupt_disable( intnum ); 219 | #endif 220 | } 221 | 222 | 223 | /* 224 | This function returns : 1 if the specified interrupt is enabled, zero 225 | if the interrupt is disabled, zero if the interrupt number is invalid. 226 | */ 227 | uint32_t 228 | xt_interrupt_enabled( uint32_t intnum ) 229 | { 230 | #if XCHAL_HAVE_XEA2 && (XCHAL_NUM_INTERRUPTS <= 32) 231 | if ( intnum < (uint32_t) XCHAL_NUM_INTERRUPTS ) 232 | { 233 | return ( (xt_intenable & (1U << intnum)) != 0 ) ? 1U : 0; 234 | } 235 | return 0; 236 | #else 237 | return xthal_interrupt_enabled( intnum ); 238 | #endif 239 | } 240 | 241 | 242 | /* 243 | This function triggers the specified interrupt. 244 | */ 245 | void 246 | xt_interrupt_trigger( uint32_t intnum ) 247 | { 248 | xthal_interrupt_trigger( intnum ); 249 | } 250 | 251 | 252 | /* 253 | This function clears the specified interrupt. 254 | */ 255 | void 256 | xt_interrupt_clear( uint32_t intnum ) 257 | { 258 | xthal_interrupt_clear( intnum ); 259 | } 260 | 261 | 262 | #endif /* XCHAL_HAVE_INTERRUPTS */ 263 | -------------------------------------------------------------------------------- /Cadence/Xtensa/xtensa_intr_asm.S: -------------------------------------------------------------------------------- 1 | /* 2 | * FreeRTOS Kernel 3 | * Copyright (C) 2015-2024 Cadence Design Systems, Inc. 4 | * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. 5 | * 6 | * SPDX-License-Identifier: MIT 7 | * 8 | * Permission is hereby granted, free of charge, to any person obtaining a copy of 9 | * this software and associated documentation files (the "Software"), to deal in 10 | * the Software without restriction, including without limitation the rights to 11 | * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of 12 | * the Software, and to permit persons to whom the Software is furnished to do so, 13 | * subject to the following conditions: 14 | * 15 | * The above copyright notice and this permission notice shall be included in all 16 | * copies or substantial portions of the Software. 17 | * 18 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS 20 | * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR 21 | * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER 22 | * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 23 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 24 | * 25 | * https://www.FreeRTOS.org 26 | * https://github.com/FreeRTOS 27 | * 28 | */ 29 | 30 | /* 31 | * Xtensa interrupt handling data and assembly routines. 32 | * Also see xtensa_intr.c and xtensa_vectors.S. 33 | */ 34 | 35 | #include 36 | #include 37 | 38 | #include 39 | 40 | #include "xtensa_context.h" 41 | #include "xtensa_config.h" 42 | 43 | #if XCHAL_HAVE_INTERRUPTS 44 | 45 | /* 46 | ------------------------------------------------------------------------------- 47 | INTENABLE virtualization information. 48 | ------------------------------------------------------------------------------- 49 | */ 50 | 51 | #if XCHAL_HAVE_XEA2 && (XCHAL_NUM_INTERRUPTS <= 32) 52 | 53 | .data 54 | .global xt_intdata 55 | .align 8 56 | xt_intdata: 57 | .global xt_intenable 58 | .type xt_intenable,@object 59 | .size xt_intenable,4 60 | .global xt_vpri_mask 61 | .type xt_vpri_mask,@object 62 | .size xt_vpri_mask,4 63 | 64 | xt_intenable: .word 0 /* Virtual INTENABLE */ 65 | xt_vpri_mask: .word 0xFFFFFFFF /* Virtual priority mask */ 66 | 67 | #endif 68 | 69 | /* 70 | ------------------------------------------------------------------------------- 71 | System interrupt stack. 72 | ------------------------------------------------------------------------------- 73 | */ 74 | 75 | #if (XCHAL_HAVE_XEA2 || XCHAL_HAVE_ISB) 76 | .data 77 | #else 78 | .section .intr.top, "aw" 79 | #endif 80 | 81 | .global xt_interrupt_stack 82 | .global xt_interrupt_stack_top 83 | .align 16 84 | 85 | xt_interrupt_stack: 86 | .space configISR_STACK_SIZE 87 | xt_interrupt_stack_top: 88 | 89 | 90 | /* 91 | ------------------------------------------------------------------------------- 92 | Table of C-callable interrupt handlers for each interrupt. For XEA2 configs, 93 | not all slots can be filled, because interrupts at level > EXCM_LEVEL will 94 | not be dispatched to a C handler by default. 95 | ------------------------------------------------------------------------------- 96 | */ 97 | 98 | #if (XCHAL_HAVE_XEA2 || XCHAL_HAVE_ISB) 99 | .data 100 | #else 101 | .section .intr.data, "aw" 102 | #endif 103 | 104 | .global _xt_interrupt_table 105 | .align 16 106 | 107 | _xt_interrupt_table: 108 | 109 | /* 110 | ------------------------------------------------------------------------------- 111 | If using the interrupt wrapper, make the first entry in the interrupt table 112 | point to the wrapper (XEA3) or leave it empty (XEA2). 113 | ------------------------------------------------------------------------------- 114 | */ 115 | #if XCHAL_HAVE_XEA3 116 | .word xt_interrupt_wrapper 117 | .word 0 118 | #elif XT_USE_INT_WRAPPER 119 | .word 0 120 | .word 0 121 | #endif 122 | 123 | .set i, 0 124 | .rept XCHAL_NUM_INTERRUPTS 125 | .word xt_unhandled_interrupt /* handler address */ 126 | .word i /* handler arg (default: intnum) */ 127 | .set i, i+1 128 | .endr 129 | 130 | #endif /* XCHAL_HAVE_INTERRUPTS */ 131 | 132 | 133 | #if XCHAL_HAVE_EXCEPTIONS 134 | 135 | /* 136 | ------------------------------------------------------------------------------- 137 | Table of C-callable exception handlers for each exception. Note that not all 138 | slots will be active, because some exceptions (e.g. coprocessor exceptions) 139 | are always handled by the OS and cannot be hooked by user handlers. 140 | ------------------------------------------------------------------------------- 141 | */ 142 | 143 | .data 144 | .global xt_exception_table 145 | .align 4 146 | 147 | xt_exception_table: 148 | .rept XCHAL_EXCCAUSE_NUM 149 | .word xt_unhandled_exception /* handler address */ 150 | .endr 151 | 152 | #endif 153 | -------------------------------------------------------------------------------- /Cadence/Xtensa/xtensa_intr_wrapper.c: -------------------------------------------------------------------------------- 1 | /* 2 | * FreeRTOS Kernel 3 | * Copyright (C) 2015-2024 Cadence Design Systems, Inc. 4 | * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. 5 | * 6 | * SPDX-License-Identifier: MIT 7 | * 8 | * Permission is hereby granted, free of charge, to any person obtaining a copy of 9 | * this software and associated documentation files (the "Software"), to deal in 10 | * the Software without restriction, including without limitation the rights to 11 | * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of 12 | * the Software, and to permit persons to whom the Software is furnished to do so, 13 | * subject to the following conditions: 14 | * 15 | * The above copyright notice and this permission notice shall be included in all 16 | * copies or substantial portions of the Software. 17 | * 18 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS 20 | * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR 21 | * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER 22 | * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 23 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 24 | * 25 | * https://www.FreeRTOS.org 26 | * https://github.com/FreeRTOS 27 | * 28 | */ 29 | 30 | #include 31 | #include 32 | 33 | #include "xtensa_rtos.h" 34 | #include "xtensa_api.h" 35 | #include "portmacro.h" 36 | 37 | 38 | #if (XCHAL_HAVE_XEA3 && XCHAL_HAVE_INTERRUPTS) 39 | 40 | /* Handler table is in xtensa_intr_asm.S */ 41 | 42 | typedef struct xt_handler_table_entry { 43 | void * handler; 44 | void * arg; 45 | } xt_handler_table_entry; 46 | 47 | extern xt_handler_table_entry _xt_interrupt_table[XCHAL_NUM_INTERRUPTS + 1]; 48 | 49 | extern int32_t xt_sw_intnum; 50 | extern int32_t port_switch_flag; 51 | extern uint32_t port_interruptNesting; 52 | 53 | static int32_t xt_wflag; 54 | 55 | 56 | /**************************************************************************/ 57 | /* Wrapper for interrupt handlers. Argument is (intnum << 2). */ 58 | /* Execution comes here from the dispatch code if the wrapper is */ 59 | /* enabled. */ 60 | /**************************************************************************/ 61 | void 62 | xt_interrupt_wrapper(void * arg) 63 | { 64 | uint32_t intnum = (uint32_t)(arg) >> 2; 65 | uint32_t state; 66 | xt_handler_table_entry * entry; 67 | xt_handler handler; 68 | 69 | state = portENTER_CRITICAL_NESTED(); 70 | port_interruptNesting++; 71 | portEXIT_CRITICAL_NESTED(state); 72 | 73 | /* Load handler address and argument from table. Note that the 74 | first entry in the table points to this wrapper, so we have 75 | to skip ahead one. 76 | */ 77 | entry = _xt_interrupt_table + intnum + 1; 78 | handler = (xt_handler) entry->handler; 79 | 80 | (*handler)(entry->arg); 81 | 82 | /* If a context switch is pending, trigger the SW interrupt 83 | to process the switch. Set an internal flag so we don't 84 | trigger the sw interrupt again when handling it. 85 | */ 86 | if (xt_wflag != 0) { 87 | xt_wflag = 0; 88 | } 89 | else if (port_switch_flag) { 90 | xt_wflag = 1; 91 | xt_interrupt_trigger(xt_sw_intnum); 92 | } 93 | 94 | state = portENTER_CRITICAL_NESTED(); 95 | port_interruptNesting--; 96 | portEXIT_CRITICAL_NESTED(state); 97 | } 98 | 99 | #endif /* XCHAL_HAVE_XEA3 && XCHAL_HAVE_INTERRUPTS */ 100 | -------------------------------------------------------------------------------- /Cadence/Xtensa/xtensa_overlay_os_hook.c: -------------------------------------------------------------------------------- 1 | /* 2 | * FreeRTOS Kernel 3 | * Copyright (C) 2015-2024 Cadence Design Systems, Inc. 4 | * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. 5 | * 6 | * SPDX-License-Identifier: MIT 7 | * 8 | * Permission is hereby granted, free of charge, to any person obtaining a copy of 9 | * this software and associated documentation files (the "Software"), to deal in 10 | * the Software without restriction, including without limitation the rights to 11 | * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of 12 | * the Software, and to permit persons to whom the Software is furnished to do so, 13 | * subject to the following conditions: 14 | * 15 | * The above copyright notice and this permission notice shall be included in all 16 | * copies or substantial portions of the Software. 17 | * 18 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS 20 | * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR 21 | * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER 22 | * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 23 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 24 | * 25 | * https://www.FreeRTOS.org 26 | * https://github.com/FreeRTOS 27 | * 28 | */ 29 | 30 | /* 31 | * xtensa_overlay_os_hook.c -- Overlay manager OS hooks for FreeRTOS. 32 | */ 33 | 34 | #ifdef XT_USE_OVLY 35 | 36 | #include 37 | 38 | #include "FreeRTOS.h" 39 | #include "semphr.h" 40 | 41 | #ifdef __XTENSA_CALL0_ABI__ 42 | #error "Windowed ABI is required for overlays" 43 | #elif !XCHAL_HAVE_XEA2 44 | #error "Overlays supported only on Xtensa LX" 45 | #endif 46 | 47 | #if configUSE_MUTEXES 48 | 49 | /* Mutex object that controls access to the overlay. Currently only one 50 | * overlay region is supported so one mutex suffices. 51 | */ 52 | static SemaphoreHandle_t xt_overlay_mutex; 53 | 54 | 55 | /* This function should be overridden to provide OS specific init such 56 | * as the creation of a mutex lock that can be used for overlay locking. 57 | * Typically this mutex would be set up with priority inheritance. See 58 | * overlay manager documentation for more details. 59 | */ 60 | void xt_overlay_init_os(void) 61 | { 62 | /* Create the mutex for overlay access. Priority inheritance is 63 | * required. 64 | */ 65 | xt_overlay_mutex = xSemaphoreCreateMutex(); 66 | } 67 | 68 | 69 | /* This function locks access to shared overlay resources, typically 70 | * by acquiring a mutex. 71 | */ 72 | void xt_overlay_lock(void) 73 | { 74 | xSemaphoreTake(xt_overlay_mutex, portMAX_DELAY); 75 | } 76 | 77 | 78 | /* This function releases access to shared overlay resources, typically 79 | * by unlocking a mutex. 80 | */ 81 | void xt_overlay_unlock(void) 82 | { 83 | xSemaphoreGive(xt_overlay_mutex); 84 | } 85 | 86 | #else 87 | 88 | #error "Mutex support is required for overlays" 89 | 90 | #endif /* configUSE_MUTEXES */ 91 | 92 | #endif /* XT_USE_OVLY */ 93 | -------------------------------------------------------------------------------- /Cadence/Xtensa/xtensa_rtos.h: -------------------------------------------------------------------------------- 1 | /* 2 | * FreeRTOS Kernel 3 | * Copyright (C) 2015-2024 Cadence Design Systems, Inc. 4 | * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. 5 | * 6 | * SPDX-License-Identifier: MIT 7 | * 8 | * Permission is hereby granted, free of charge, to any person obtaining a copy of 9 | * this software and associated documentation files (the "Software"), to deal in 10 | * the Software without restriction, including without limitation the rights to 11 | * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of 12 | * the Software, and to permit persons to whom the Software is furnished to do so, 13 | * subject to the following conditions: 14 | * 15 | * The above copyright notice and this permission notice shall be included in all 16 | * copies or substantial portions of the Software. 17 | * 18 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS 20 | * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR 21 | * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER 22 | * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 23 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 24 | * 25 | * https://www.FreeRTOS.org 26 | * https://github.com/FreeRTOS 27 | * 28 | */ 29 | 30 | /* 31 | * RTOS-SPECIFIC INFORMATION FOR XTENSA RTOS ASSEMBLER SOURCES 32 | * (FreeRTOS Port) 33 | * 34 | * This header is the primary glue between generic Xtensa RTOS support 35 | * sources and a specific RTOS port for Xtensa. It contains definitions 36 | * and macros for use primarily by Xtensa assembly coded source files. 37 | * 38 | * Macros in this header map callouts from generic Xtensa files to specific 39 | * RTOS functions. It may also be included in C source files. 40 | * 41 | * Xtensa RTOS ports support all RTOS-compatible configurations of the Xtensa 42 | * architecture, using the Xtensa hardware abstraction layer (HAL) to deal 43 | * with configuration specifics. 44 | * 45 | * Should be included by all Xtensa generic and RTOS port-specific sources. 46 | */ 47 | 48 | #ifndef XTENSA_RTOS_H 49 | #define XTENSA_RTOS_H 50 | 51 | #ifdef __ASSEMBLER__ 52 | #include 53 | #else 54 | #include 55 | #endif 56 | 57 | #include 58 | #include 59 | #include 60 | 61 | /* 62 | Include any RTOS specific definitions that are needed by this header. 63 | */ 64 | #include 65 | 66 | /* 67 | Convert FreeRTOSConfig definitions to XTENSA definitions. 68 | However these can still be overridden from the command line. 69 | */ 70 | 71 | #ifndef XT_SIMULATOR 72 | #if configXT_SIMULATOR 73 | #define XT_SIMULATOR 1 /* Simulator mode */ 74 | #endif 75 | #endif 76 | 77 | #ifndef XT_BOARD 78 | #if defined (configXT_BOARD) && (configXT_BOARD != 0) 79 | #define XT_BOARD 1 /* Board mode */ 80 | #endif 81 | #endif 82 | 83 | #ifndef XT_TIMER_INDEX 84 | #if defined configXT_TIMER_INDEX 85 | #define XT_TIMER_INDEX configXT_TIMER_INDEX /* Index of hardware timer to be used */ 86 | #endif 87 | #endif 88 | 89 | #ifndef XT_INTEXC_HOOKS 90 | #if configXT_INTEXC_HOOKS 91 | #define XT_INTEXC_HOOKS 1 /* Enables exception hooks */ 92 | #endif 93 | #endif 94 | 95 | #if XCHAL_HAVE_XEA2 && (XCHAL_NUM_INTERRUPTS > 32) && (defined XT_INTEXC_HOOKS) 96 | #error "FreeRTOS/XTENSA XEA2 interrupt/exception hooks require <= 32 interrupts." 97 | #endif 98 | 99 | #if (!XT_SIMULATOR) && (!XT_BOARD) 100 | #error Either XT_SIMULATOR or XT_BOARD must be defined. 101 | #endif 102 | 103 | 104 | /* 105 | Name of RTOS (for messages). 106 | */ 107 | #define XT_RTOS_NAME FreeRTOS 108 | 109 | #define UNUSED(x) ((void)(x)) 110 | /* 111 | Check some Xtensa configuration requirements and report error if not met. 112 | Error messages can be customize to the RTOS port. 113 | */ 114 | 115 | #if !XCHAL_HAVE_XEA2 && !XCHAL_HAVE_XEA3 116 | #error "FreeRTOS/Xtensa requires XEA2 or XEA3 exception architecture." 117 | #endif 118 | 119 | 120 | /******************************************************************************* 121 | 122 | RTOS CALLOUT MACROS MAPPED TO RTOS PORT-SPECIFIC FUNCTIONS. 123 | 124 | Define callout macros used in generic Xtensa code to interact with the RTOS. 125 | The macros are simply the function names for use in calls from assembler code. 126 | Some of these functions may call back to generic functions in xtensa_context.h . 127 | 128 | *******************************************************************************/ 129 | 130 | /* 131 | Inform RTOS of entry into an interrupt handler that will affect it. 132 | Allows RTOS to manage switch to any system stack and count nesting level. 133 | Called after minimal context has been saved, with interrupts disabled. 134 | RTOS port can call0 _xt_context_save to save the rest of the context. 135 | May only be called from assembly code by the 'call0' instruction. 136 | */ 137 | // void XT_RTOS_INT_ENTER(void) 138 | #define XT_RTOS_INT_ENTER _frxt_int_enter 139 | 140 | /* 141 | Inform RTOS of completion of an interrupt handler, and give control to 142 | RTOS to perform thread/task scheduling, switch back from any system stack 143 | and restore the context, and return to the exit dispatcher saved in the 144 | stack frame at XT_STK_EXIT. RTOS port can call0 _xt_context_restore 145 | to save the context saved in XT_RTOS_INT_ENTER via _xt_context_save, 146 | leaving only a minimal part of the context to be restored by the exit 147 | dispatcher. This function does not return to the place it was called from. 148 | May only be called from assembly code by the 'call0' instruction. 149 | */ 150 | // void XT_RTOS_INT_EXIT(void) 151 | #define XT_RTOS_INT_EXIT _frxt_int_exit 152 | 153 | /* 154 | Inform RTOS of the occurrence of a tick timer interrupt. 155 | If RTOS has no tick timer, leave XT_RTOS_TIMER_INT undefined. 156 | May be coded in or called from C or assembly, per ABI conventions. 157 | RTOS may optionally define XT_TICK_PER_SEC in its own way (eg. macro). 158 | */ 159 | // void XT_RTOS_TIMER_INT(void) 160 | #define XT_RTOS_TIMER_INT _frxt_timer_int 161 | #define XT_TICK_PER_SEC configTICK_RATE_HZ 162 | 163 | /* 164 | Return in a15 the base address of the co-processor state save area for the 165 | thread that triggered a co-processor exception, or 0 if no thread was running. 166 | The state save area is structured as defined in xtensa_context.h and has size 167 | XT_CP_SIZE. Co-processor instructions should only be used in thread code, never 168 | in interrupt handlers or the RTOS kernel. May only be called from assembly code 169 | and by the 'call0' instruction. A result of 0 indicates an unrecoverable error. 170 | The implementation may use only a2-4, a15 (all other regs must be preserved). 171 | */ 172 | // void* XT_RTOS_CP_STATE(void) 173 | #define XT_RTOS_CP_STATE _xt_task_coproc_state 174 | 175 | 176 | /******************************************************************************* 177 | 178 | HOOKS TO DYNAMICALLY INSTALL INTERRUPT AND EXCEPTION HANDLERS PER LEVEL. 179 | 180 | This Xtensa RTOS port provides hooks for dynamically installing exception 181 | and interrupt handlers to facilitate automated testing where each test 182 | case can install its own handler for user exceptions and each interrupt 183 | priority (level). This consists of an array of function pointers indexed 184 | by interrupt priority, with index 0 being the user exception handler hook. 185 | Each entry in the array is initially 0, and may be replaced by a function 186 | pointer of type XT_INTEXC_HOOK. A handler may be uninstalled by installing 0. 187 | 188 | The handler for low and medium priority obeys ABI conventions so may be coded 189 | in C. For the exception handler, the cause is the contents of the EXCCAUSE 190 | reg, and the result is -1 if handled, else the cause (still needs handling). 191 | For interrupt handlers, the cause is a mask of pending enabled interrupts at 192 | that level, and the result is the same mask with the bits for the handled 193 | interrupts cleared (those not cleared still need handling). This allows a test 194 | case to either pre-handle or override the default handling for the exception 195 | or interrupt level (see xtensa_vectors.S). 196 | 197 | High priority handlers (including NMI) must be coded in assembly, are always 198 | called by 'call0' regardless of ABI, must preserve all registers except a0, 199 | and must not use or modify the interrupted stack. The hook argument 'cause' 200 | is not passed and the result is ignored, so as not to burden the caller with 201 | saving and restoring a2 (it assumes only one interrupt per level - see the 202 | discussion in high priority interrupts in xtensa_vectors.S). The handler 203 | therefore should be coded to prototype 'void h(void)' even though it plugs 204 | into an array of handlers of prototype 'unsigned h(unsigned)'. 205 | 206 | To enable interrupt/exception hooks, compile the RTOS with '-DXT_INTEXC_HOOKS'. 207 | 208 | *******************************************************************************/ 209 | 210 | #define XT_INTEXC_HOOK_NUM (1 + XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI) 211 | 212 | #ifndef __ASSEMBLER__ 213 | typedef unsigned (*XT_INTEXC_HOOK)(unsigned cause); 214 | extern volatile XT_INTEXC_HOOK _xt_intexc_hooks[XT_INTEXC_HOOK_NUM]; 215 | #endif 216 | 217 | 218 | /******************************************************************************* 219 | 220 | Define a debug exception cause for XEA2. This is needed to reserve an entry 221 | in the exception table for a user-defined handler, and also for registering 222 | a user handler. Must use one of the unused/reserved exception causes. 223 | 224 | *******************************************************************************/ 225 | 226 | #ifndef EXCCAUSE_DEBUG 227 | #define EXCCAUSE_DEBUG 21 228 | #endif 229 | 230 | 231 | /******************************************************************************* 232 | 233 | CONVENIENCE INCLUSIONS. 234 | 235 | Ensures RTOS specific files need only include this one Xtensa-generic header. 236 | These headers are included last so they can use the RTOS definitions above. 237 | 238 | *******************************************************************************/ 239 | 240 | #include "xtensa_context.h" 241 | 242 | #ifdef XT_RTOS_TIMER_INT 243 | #include "xtensa_timer.h" 244 | #endif 245 | 246 | 247 | /******************************************************************************* 248 | 249 | Xtensa Port Version. 250 | 251 | *******************************************************************************/ 252 | 253 | #define XTENSA_PORT_VERSION 3.00 254 | #define XTENSA_PORT_VERSION_STRING "3.00" 255 | 256 | #define XT_IRQ_LOCK_LEVEL XCHAL_EXCM_LEVEL 257 | 258 | #endif /* XTENSA_RTOS_H */ 259 | -------------------------------------------------------------------------------- /Cadence/Xtensa/xtensa_timer.h: -------------------------------------------------------------------------------- 1 | /* 2 | * FreeRTOS Kernel 3 | * Copyright (C) 2015-2024 Cadence Design Systems, Inc. 4 | * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. 5 | * 6 | * SPDX-License-Identifier: MIT 7 | * 8 | * Permission is hereby granted, free of charge, to any person obtaining a copy of 9 | * this software and associated documentation files (the "Software"), to deal in 10 | * the Software without restriction, including without limitation the rights to 11 | * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of 12 | * the Software, and to permit persons to whom the Software is furnished to do so, 13 | * subject to the following conditions: 14 | * 15 | * The above copyright notice and this permission notice shall be included in all 16 | * copies or substantial portions of the Software. 17 | * 18 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS 20 | * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR 21 | * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER 22 | * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 23 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 24 | * 25 | * https://www.FreeRTOS.org 26 | * https://github.com/FreeRTOS 27 | * 28 | */ 29 | 30 | /* 31 | * XTENSA INFORMATION FOR RTOS TICK TIMER AND CLOCK FREQUENCY 32 | * 33 | * This header contains definitions and macros for use primarily by Xtensa 34 | * RTOS assembly coded source files. It includes and uses the Xtensa hardware 35 | * abstraction layer (HAL) to deal with config specifics. It may also be 36 | * included in C source files. 37 | * 38 | * Edit this file to modify timer selection and to specify clock frequency and 39 | * tick duration to match timer interrupt to the real-time tick duration. 40 | * 41 | * If the RTOS has no timer interrupt, then there is no tick timer and the 42 | * clock frequency is irrelevant, so all of these macros are left undefined 43 | * and the Xtensa core configuration need not have a timer. 44 | */ 45 | 46 | #ifndef XTENSA_TIMER_H 47 | #define XTENSA_TIMER_H 48 | 49 | #ifdef __ASSEMBLER__ 50 | #include 51 | #endif 52 | 53 | #include 54 | #include 55 | 56 | #include 57 | 58 | /* 59 | Select timer to use for periodic tick, and determine its interrupt number 60 | and priority. User may specify a timer by defining XT_TIMER_INDEX with -D, 61 | in which case its validity is checked (it must exist in this core and must 62 | not be on a high priority interrupt - an error will be reported in invalid). 63 | Otherwise select the highest priority low or medium priority interrupt timer 64 | available. 65 | */ 66 | #if XCHAL_NUM_TIMERS == 0 67 | 68 | #error "This Xtensa configuration is unsupported, it has no timers." 69 | 70 | #else 71 | 72 | #ifndef XT_TIMER_INDEX 73 | #if XCHAL_TIMER3_INTERRUPT != XTHAL_TIMER_UNCONFIGURED 74 | #if XCHAL_INT_LEVEL(XCHAL_TIMER3_INTERRUPT) <= XCHAL_EXCM_LEVEL 75 | #undef XT_TIMER_INDEX 76 | #define XT_TIMER_INDEX 3 77 | #undef XT_TIMER_LEVEL 78 | #define XT_TIMER_LEVEL XCHAL_INT_LEVEL(XCHAL_TIMER3_INTERRUPT) 79 | #endif 80 | #endif 81 | #if XCHAL_TIMER2_INTERRUPT != XTHAL_TIMER_UNCONFIGURED 82 | #if XCHAL_INT_LEVEL(XCHAL_TIMER2_INTERRUPT) <= XCHAL_EXCM_LEVEL && \ 83 | (!defined(XT_TIMER_INDEX) || \ 84 | XCHAL_INT_LEVEL(XCHAL_TIMER2_INTERRUPT) > XT_TIMER_LEVEL) 85 | #undef XT_TIMER_INDEX 86 | #define XT_TIMER_INDEX 2 87 | #undef XT_TIMER_LEVEL 88 | #define XT_TIMER_LEVEL XCHAL_INT_LEVEL(XCHAL_TIMER2_INTERRUPT) 89 | #endif 90 | #endif 91 | #if XCHAL_TIMER1_INTERRUPT != XTHAL_TIMER_UNCONFIGURED 92 | #if XCHAL_INT_LEVEL(XCHAL_TIMER1_INTERRUPT) <= XCHAL_EXCM_LEVEL && \ 93 | (!defined(XT_TIMER_INDEX) || \ 94 | XCHAL_INT_LEVEL(XCHAL_TIMER1_INTERRUPT) > XT_TIMER_LEVEL) 95 | #undef XT_TIMER_INDEX 96 | #define XT_TIMER_INDEX 1 97 | #undef XT_TIMER_LEVEL 98 | #define XT_TIMER_LEVEL XCHAL_INT_LEVEL(XCHAL_TIMER1_INTERRUPT) 99 | #endif 100 | #endif 101 | #if XCHAL_TIMER0_INTERRUPT != XTHAL_TIMER_UNCONFIGURED 102 | #if XCHAL_INT_LEVEL(XCHAL_TIMER0_INTERRUPT) <= XCHAL_EXCM_LEVEL && \ 103 | (!defined(XT_TIMER_INDEX) || \ 104 | XCHAL_INT_LEVEL(XCHAL_TIMER0_INTERRUPT) > XT_TIMER_LEVEL) 105 | #undef XT_TIMER_INDEX 106 | #define XT_TIMER_INDEX 0 107 | #undef XT_TIMER_LEVEL 108 | #define XT_TIMER_LEVEL XCHAL_INT_LEVEL(XCHAL_TIMER0_INTERRUPT) 109 | #endif 110 | #endif 111 | #endif 112 | #ifndef XT_TIMER_INDEX 113 | #error "There is no suitable timer in this Xtensa configuration." 114 | #endif 115 | 116 | #define XT_CCOMPARE (CCOMPARE + XT_TIMER_INDEX) 117 | #define XT_TIMER_INTNUM XCHAL_TIMER_INTERRUPT(XT_TIMER_INDEX) 118 | #define XT_TIMER_INTPRI XCHAL_INT_LEVEL(XT_TIMER_INTNUM) 119 | 120 | /* 121 | * Xtensa LX8 supports up to 128 interrupts whereas LX7 supports up to 32. 122 | * 123 | * Redefine the legacy XT_TIMER_INTEN (which limited the interrupt number to 124 | * be in the lower 32 or lower 64 bits depending on data type) as two defines 125 | * describing the INTEN bit within a 32-bit component and a 4-block component, 126 | * where each block contains a group of 32 interrupt bits. 127 | * 128 | * Name changes are intentional such that any dependencies are caught at 129 | * compile-time and are found regardless of timer configuration. 130 | */ 131 | #define XT_TIMER_INTEN_BIT (1 << (XT_TIMER_INTNUM & 31U)) 132 | #define XT_TIMER_INTEN_BLK (XT_TIMER_INTNUM >> 5) 133 | 134 | #if XT_TIMER_INTNUM == XTHAL_TIMER_UNCONFIGURED 135 | #error "The timer selected by XT_TIMER_INDEX does not exist in this core." 136 | #elif XT_TIMER_INTPRI > XCHAL_EXCM_LEVEL 137 | #error "The timer interrupt cannot be high priority (use medium or low)." 138 | #endif 139 | 140 | #endif /* XCHAL_NUM_TIMERS */ 141 | 142 | /* 143 | Set processor clock frequency, used to determine clock divisor for timer tick. 144 | User should BE SURE TO ADJUST THIS for the Xtensa platform being used. 145 | If using a supported board via the board-independent API defined in xtbsp.h, 146 | this may be left undefined and frequency and tick divisor will be computed 147 | and cached during run-time initialization. 148 | 149 | NOTE ON SIMULATOR: 150 | Under the Xtensa instruction set simulator, the frequency can only be estimated 151 | because it depends on the speed of the host and the version of the simulator. 152 | Also because it runs much slower than hardware, it is not possible to achieve 153 | real-time performance for most applications under the simulator. A frequency 154 | too low does not allow enough time between timer interrupts, starving threads. 155 | To obtain a more convenient but non-real-time tick duration on the simulator, 156 | compile with the option "-DXT_SIMULATOR". 157 | Adjust this frequency to taste (it's not real-time anyway!). 158 | */ 159 | #if defined(XT_SIMULATOR) && !defined(XT_CLOCK_FREQ) 160 | #define XT_CLOCK_FREQ configCPU_CLOCK_HZ 161 | #endif 162 | 163 | #if !defined(XT_CLOCK_FREQ) && !defined(XT_BOARD) 164 | #error "XT_CLOCK_FREQ must be defined for the target platform." 165 | #endif 166 | 167 | /* 168 | Default number of timer "ticks" per second (default 100 for 10ms tick). 169 | RTOS may define this in its own way (if applicable) in xtensa_rtos.h. 170 | User may redefine this to an optimal value for the application, either by 171 | editing this here or in xtensa_rtos.h, or compiling with the option 172 | "-DXT_TICK_PER_SEC=" where is a suitable number. 173 | */ 174 | #ifndef XT_TICK_PER_SEC 175 | #define XT_TICK_PER_SEC configTICK_RATE_HZ /* 10 ms tick = 100 ticks per second */ 176 | #endif 177 | 178 | /* 179 | Derivation of clock divisor for timer tick and interrupt (one per tick). 180 | */ 181 | #ifdef XT_CLOCK_FREQ 182 | #define XT_TICK_DIVISOR (XT_CLOCK_FREQ / XT_TICK_PER_SEC) 183 | #endif 184 | 185 | #ifndef __ASSEMBLER__ 186 | extern unsigned _xt_tick_divisor; 187 | extern void _xt_tick_divisor_init(void); 188 | #endif 189 | 190 | #endif /* XTENSA_TIMER_H */ 191 | -------------------------------------------------------------------------------- /GCC/AVR_AVRDx/LICENSE: -------------------------------------------------------------------------------- 1 | FreeRTOS Kernel 2 | Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. 3 | 4 | SPDX-License-Identifier: MIT 5 | 6 | Permission is hereby granted, free of charge, to any person obtaining a copy of 7 | this software and associated documentation files (the "Software"), to deal in 8 | the Software without restriction, including without limitation the rights to 9 | use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of 10 | the Software, and to permit persons to whom the Software is furnished to do so, 11 | subject to the following conditions: 12 | 13 | The above copyright notice and this permission notice shall be included in all 14 | copies or substantial portions of the Software. 15 | 16 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS 18 | FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR 19 | COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER 20 | IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 21 | CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 22 | 23 | https://www.FreeRTOS.org 24 | https://github.com/FreeRTOS 25 | -------------------------------------------------------------------------------- /GCC/AVR_AVRDx/porthardware.h: -------------------------------------------------------------------------------- 1 | /* 2 | * FreeRTOS Kernel 3 | * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. 4 | * 5 | * SPDX-License-Identifier: MIT 6 | * 7 | * Permission is hereby granted, free of charge, to any person obtaining a copy of 8 | * this software and associated documentation files (the "Software"), to deal in 9 | * the Software without restriction, including without limitation the rights to 10 | * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of 11 | * the Software, and to permit persons to whom the Software is furnished to do so, 12 | * subject to the following conditions: 13 | * 14 | * The above copyright notice and this permission notice shall be included in all 15 | * copies or substantial portions of the Software. 16 | * 17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS 19 | * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR 20 | * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER 21 | * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 22 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 23 | * 24 | * https://www.FreeRTOS.org 25 | * https://github.com/FreeRTOS 26 | * 27 | */ 28 | 29 | #ifndef PORTHARDWARE_H 30 | #define PORTHARDWARE_H 31 | 32 | #include "FreeRTOSConfig.h" 33 | 34 | /*-----------------------------------------------------------*/ 35 | 36 | #define CLR_INT( FLAG_REG, FLAG_MASK ) \ 37 | asm volatile ( \ 38 | "push r16\n\t" \ 39 | "ldi r16, %1\n\t" \ 40 | "sts %0, r16\n\t" \ 41 | "pop r16\n\t" \ 42 | : \ 43 | : "i" ( _SFR_MEM_ADDR( FLAG_REG ) ), "i" ( ( uint8_t ) ( FLAG_MASK ) ) \ 44 | ); 45 | 46 | #if ( configUSE_TIMER_INSTANCE == 0 ) 47 | 48 | #define TICK_INT_vect TCB0_INT_vect 49 | #define INT_FLAGS TCB0_INTFLAGS 50 | #define INT_MASK TCB_CAPT_bm 51 | 52 | #define TICK_init() \ 53 | { \ 54 | TCB0.CCMP = configCPU_CLOCK_HZ / configTICK_RATE_HZ; \ 55 | TCB0.INTCTRL = TCB_CAPT_bm; \ 56 | TCB0.CTRLA = TCB_ENABLE_bm; \ 57 | } 58 | 59 | #define TICK_TMR_STOP() TCB0.CTRLA = 0x00; 60 | #define TICK_TMR_START() \ 61 | { \ 62 | TCB0.INTFLAGS = TCB_CAPT_bm; \ 63 | TCB0.CTRLA = TCB_ENABLE_bm; \ 64 | } 65 | #define TICK_TMR_READ() TCB0.CNT 66 | #define TICK_INT_READY() (TCB0.INTCTRL & TCB_CAPT_bm) 67 | 68 | #elif ( configUSE_TIMER_INSTANCE == 1 ) 69 | 70 | #define TICK_INT_vect TCB1_INT_vect 71 | #define INT_FLAGS TCB1_INTFLAGS 72 | #define INT_MASK TCB_CAPT_bm 73 | 74 | #define TICK_init() \ 75 | { \ 76 | TCB1.CCMP = configCPU_CLOCK_HZ / configTICK_RATE_HZ; \ 77 | TCB1.INTCTRL = TCB_CAPT_bm; \ 78 | TCB1.CTRLA = TCB_ENABLE_bm; \ 79 | } 80 | 81 | #define TICK_TMR_STOP() TCB1.CTRLA = 0x00; 82 | #define TICK_TMR_START() \ 83 | { \ 84 | TCB1.INTFLAGS = TCB_CAPT_bm; \ 85 | TCB1.CTRLA = TCB_ENABLE_bm; \ 86 | } 87 | #define TICK_TMR_READ() TCB1.CNT 88 | #define TICK_INT_READY() (TCB1.INTCTRL & TCB_CAPT_bm) 89 | 90 | #elif ( configUSE_TIMER_INSTANCE == 2 ) 91 | 92 | #define TICK_INT_vect TCB2_INT_vect 93 | #define INT_FLAGS TCB2_INTFLAGS 94 | #define INT_MASK TCB_CAPT_bm 95 | 96 | #define TICK_init() \ 97 | { \ 98 | TCB2.CCMP = configCPU_CLOCK_HZ / configTICK_RATE_HZ; \ 99 | TCB2.INTCTRL = TCB_CAPT_bm; \ 100 | TCB2.CTRLA = TCB_ENABLE_bm; \ 101 | } 102 | 103 | #define TICK_TMR_STOP() TCB2.CTRLA = 0x00; 104 | #define TICK_TMR_START() \ 105 | { \ 106 | TCB2.INTFLAGS = TCB_CAPT_bm; \ 107 | TCB2.CTRLA = TCB_ENABLE_bm; \ 108 | } 109 | #define TICK_TMR_READ() TCB2.CNT 110 | #define TICK_INT_READY() (TCB2.INTCTRL & TCB_CAPT_bm) 111 | 112 | #elif ( configUSE_TIMER_INSTANCE == 3 ) 113 | 114 | #define TICK_INT_vect TCB3_INT_vect 115 | #define INT_FLAGS TCB3_INTFLAGS 116 | #define INT_MASK TCB_CAPT_bm 117 | 118 | #define TICK_init() \ 119 | { \ 120 | TCB3.CCMP = configCPU_CLOCK_HZ / configTICK_RATE_HZ; \ 121 | TCB3.INTCTRL = TCB_CAPT_bm; \ 122 | TCB3.CTRLA = TCB_ENABLE_bm; \ 123 | } 124 | 125 | #define TICK_TMR_STOP() TCB3.CTRLA = 0x00; 126 | #define TICK_TMR_START() \ 127 | { \ 128 | TCB3.INTFLAGS = TCB_CAPT_bm; \ 129 | TCB3.CTRLA = TCB_ENABLE_bm; \ 130 | } 131 | #define TICK_TMR_READ() TCB3.CNT 132 | #define TICK_INT_READY() (TCB3.INTCTRL & TCB_CAPT_bm) 133 | 134 | #elif ( configUSE_TIMER_INSTANCE == 4 ) 135 | 136 | #define TICK_INT_vect TCB4_INT_vect 137 | #define INT_FLAGS TCB4_INTFLAGS 138 | #define INT_MASK TCB_CAPT_bm 139 | 140 | #define TICK_init() \ 141 | { \ 142 | TCB4.CCMP = configCPU_CLOCK_HZ / configTICK_RATE_HZ; \ 143 | TCB4.INTCTRL = TCB_CAPT_bm; \ 144 | TCB4.CTRLA = TCB_ENABLE_bm; \ 145 | } 146 | #define TICK_TMR_STOP() TCB4.CTRLA = 0x00; 147 | #define TICK_TMR_START() \ 148 | { \ 149 | TCB4.INTFLAGS = TCB_CAPT_bm; \ 150 | TCB4.CTRLA = TCB_ENABLE_bm; \ 151 | } 152 | #define TICK_TMR_READ() TCB4.CNT 153 | #define TICK_INT_READY() (TCB4.INTCTRL & TCB_CAPT_bm) 154 | 155 | #elif ( configUSE_TIMER_INSTANCE == 5 ) 156 | 157 | #if ( configUSE_TICKLESS_IDLE == 1 ) 158 | 159 | /* RTC is not supported as tick timer when tickless mode is used */ 160 | #error Invalid timer setting. 161 | 162 | #else 163 | 164 | #define TICK_INT_vect RTC_CNT_vect 165 | #define INT_FLAGS RTC_INTFLAGS 166 | #define INT_MASK RTC_OVF_bm 167 | 168 | /* Hertz to period for RTC setup */ 169 | #define RTC_PERIOD_HZ( x ) ( 32768 * ( ( 1.0 / x ) ) ) 170 | #define TICK_init() \ 171 | { \ 172 | while( RTC.STATUS > 0 ) {; } \ 173 | RTC.CTRLA = RTC_PRESCALER_DIV1_gc | 1 << RTC_RTCEN_bp; \ 174 | RTC.PER = RTC_PERIOD_HZ( configTICK_RATE_HZ ); \ 175 | RTC.INTCTRL |= 1 << RTC_OVF_bp; \ 176 | } 177 | #undef TICK_TMR_STOP 178 | #undef TICK_TMR_START 179 | #undef TICK_TMR_READ 180 | #undef TICK_INT_READY 181 | #endif 182 | 183 | #else /* if ( configUSE_TIMER_INSTANCE == 0 ) */ 184 | #undef TICK_INT_vect 185 | #undef INT_FLAGS 186 | #undef INT_MASK 187 | #undef TICK_init 188 | #undef TICK_TMR_STOP 189 | #undef TICK_TMR_START 190 | #undef TICK_TMR_READ 191 | #undef TICK_INT_READY 192 | #error Invalid timer setting. 193 | #endif /* if ( configUSE_TIMER_INSTANCE == 0 ) */ 194 | 195 | /*-----------------------------------------------------------*/ 196 | 197 | 198 | #if ( configUSE_TICKLESS_IDLE == 1 ) 199 | 200 | #define LOW_POWER_CLOCK (32768UL) 201 | 202 | #define RTC_TICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) 203 | #define RTC_TICKS_TO_COUNTS(tick_cnt) (uint32_t)(((float)(tick_cnt * LOW_POWER_CLOCK)/configTICK_RATE_HZ) - 0.5) 204 | #define RTC_COUNTS_TO_TICKS(counts) (uint32_t)((float)((counts * 1.0) * configTICK_RATE_HZ)/LOW_POWER_CLOCK ) 205 | 206 | 207 | #define RTC_INIT() \ 208 | { \ 209 | while( RTC.STATUS > 0 ) {; } \ 210 | RTC.PER = 0xFFFF; \ 211 | RTC.CMP = 0x3FFF; \ 212 | RTC.CNT = 0; \ 213 | RTC.INTFLAGS = RTC_OVF_bm | RTC_CMP_bm; \ 214 | RTC.CTRLA = RTC_RUNSTDBY_bm | RTC_PRESCALER_DIV1_gc | RTC_RTCEN_bm ; \ 215 | RTC.INTCTRL = RTC_OVF_bm | RTC_CMP_bm; \ 216 | } 217 | 218 | #endif 219 | 220 | 221 | #endif /* PORTHARDWARE_H */ 222 | -------------------------------------------------------------------------------- /GCC/AVR_AVRDx/portmacro.h: -------------------------------------------------------------------------------- 1 | /* 2 | * FreeRTOS Kernel 3 | * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. 4 | * 5 | * SPDX-License-Identifier: MIT 6 | * 7 | * Permission is hereby granted, free of charge, to any person obtaining a copy of 8 | * this software and associated documentation files (the "Software"), to deal in 9 | * the Software without restriction, including without limitation the rights to 10 | * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of 11 | * the Software, and to permit persons to whom the Software is furnished to do so, 12 | * subject to the following conditions: 13 | * 14 | * The above copyright notice and this permission notice shall be included in all 15 | * copies or substantial portions of the Software. 16 | * 17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS 19 | * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR 20 | * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER 21 | * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 22 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 23 | * 24 | * https://www.FreeRTOS.org 25 | * https://github.com/FreeRTOS 26 | * 27 | */ 28 | 29 | #ifndef PORTMACRO_H 30 | #define PORTMACRO_H 31 | 32 | /* *INDENT-OFF* */ 33 | #ifdef __cplusplus 34 | extern "C" { 35 | #endif 36 | /* *INDENT-ON* */ 37 | 38 | #include 39 | /*----------------------------------------------------------- 40 | * Port specific definitions. 41 | * 42 | * The settings in this file configure FreeRTOS correctly for the 43 | * given hardware and compiler. 44 | * 45 | * These settings should not be altered. 46 | *----------------------------------------------------------- 47 | */ 48 | 49 | /* Type definitions. */ 50 | #define portCHAR char 51 | #define portFLOAT float 52 | #define portDOUBLE double 53 | #define portLONG long 54 | #define portSHORT int 55 | #define portSTACK_TYPE uint8_t 56 | #define portBASE_TYPE char 57 | 58 | #define portPOINTER_SIZE_TYPE uint16_t 59 | 60 | typedef portSTACK_TYPE StackType_t; 61 | typedef signed char BaseType_t; 62 | typedef unsigned char UBaseType_t; 63 | 64 | #if ( configUSE_16_BIT_TICKS == 1 ) 65 | typedef uint16_t TickType_t; 66 | #define portMAX_DELAY ( TickType_t ) 0xffff 67 | #else 68 | typedef uint32_t TickType_t; 69 | #define portMAX_DELAY ( TickType_t ) 0xffffffffUL 70 | #endif 71 | /*-----------------------------------------------------------*/ 72 | 73 | /* Critical section management. */ 74 | #define portENTER_CRITICAL() \ 75 | asm volatile ( "in __tmp_reg__, __SREG__" ); \ 76 | asm volatile ( "cli" ); \ 77 | asm volatile ( "push __tmp_reg__" ) 78 | 79 | #define portEXIT_CRITICAL() \ 80 | asm volatile ( "pop __tmp_reg__" ); \ 81 | asm volatile ( "out __SREG__, __tmp_reg__" ) 82 | 83 | #define portDISABLE_INTERRUPTS() asm volatile ( "cli" ::); 84 | #define portENABLE_INTERRUPTS() asm volatile ( "sei" ::); 85 | /*-----------------------------------------------------------*/ 86 | 87 | /* Architecture specifics. */ 88 | #define portSTACK_GROWTH ( -1 ) 89 | #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) 90 | #define portBYTE_ALIGNMENT 1 91 | #define portNOP() asm volatile ( "nop" ); 92 | /*-----------------------------------------------------------*/ 93 | 94 | /* Kernel utilities. */ 95 | extern void vPortYield( void ) __attribute__( ( naked ) ); 96 | #define portYIELD() vPortYield() 97 | 98 | /*-----------------------------------------------------------*/ 99 | 100 | /* Task function macros as described on the FreeRTOS.org WEB site. */ 101 | #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) 102 | #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) 103 | 104 | /* Macros for tickless idle/low power functionality. */ 105 | #ifndef portSUPPRESS_TICKS_AND_SLEEP 106 | 107 | extern void vPortSuppressTicksAndSleep(TickType_t xExpectedIdleTime); 108 | #define portSUPPRESS_TICKS_AND_SLEEP(xExpectedIdleTime) vPortSuppressTicksAndSleep(xExpectedIdleTime) 109 | #endif 110 | 111 | #ifndef configPRE_PWR_DOWN_PROCESSING 112 | #define configPRE_PWR_DOWN_PROCESSING() 113 | #endif 114 | 115 | #ifndef configPOST_PWR_DOWN_PROCESSING 116 | #define configPOST_PWR_DOWN_PROCESSING() 117 | #endif 118 | 119 | /*-----------------------------------------------------------*/ 120 | 121 | /* Helper macros for portSAVE_CONTEXT/ portRESTORE_CONTEXT - common support for Mega-0 and AVR-Dx families */ 122 | 123 | #if defined(__AVR_HAVE_RAMPZ__) 124 | 125 | #define portSAVE_RAMPZ() \ 126 | asm volatile("in r0, __RAMPZ__ \n\t" \ 127 | "push r0 \n\t"); 128 | 129 | #define portRESTORE_RAMPZ() \ 130 | asm volatile("pop r0 \n\t" \ 131 | "out __RAMPZ__, r0 \n\t"); 132 | 133 | #else 134 | 135 | #define portSAVE_RAMPZ() 136 | #define portRESTORE_RAMPZ() 137 | 138 | #endif 139 | 140 | /* Macro to save all the general purpose registers, the save the stack pointer 141 | * into the TCB. 142 | 143 | * The first thing we do is save the flags then disable interrupts. This is to 144 | * guard our stack against having a context switch interrupt after we have already 145 | * pushed the registers onto the stack - causing the 32 registers to be on the 146 | * stack twice. 147 | 148 | * r1 is set to zero as the compiler expects it to be thus, however some 149 | * of the math routines make use of R1. 150 | 151 | * The interrupts will have been disabled during the call to portSAVE_CONTEXT() 152 | * so we need not worry about reading/writing to the stack pointer. */ 153 | 154 | #define portSAVE_CONTEXT() \ 155 | { \ 156 | asm volatile("push r0 \n\t" \ 157 | "in r0, __SREG__ \n\t" \ 158 | "cli \n\t" \ 159 | "push r0 \n\t"); \ 160 | portSAVE_RAMPZ(); \ 161 | asm volatile("push r1 \n\t" \ 162 | "clr r1 \n\t" \ 163 | "push r2 \n\t" \ 164 | "push r3 \n\t" \ 165 | "push r4 \n\t" \ 166 | "push r5 \n\t" \ 167 | "push r6 \n\t" \ 168 | "push r7 \n\t" \ 169 | "push r8 \n\t" \ 170 | "push r9 \n\t" \ 171 | "push r10 \n\t" \ 172 | "push r11 \n\t" \ 173 | "push r12 \n\t" \ 174 | "push r13 \n\t" \ 175 | "push r14 \n\t" \ 176 | "push r15 \n\t" \ 177 | "push r16 \n\t" \ 178 | "push r17 \n\t" \ 179 | "push r18 \n\t" \ 180 | "push r19 \n\t" \ 181 | "push r20 \n\t" \ 182 | "push r21 \n\t" \ 183 | "push r22 \n\t" \ 184 | "push r23 \n\t" \ 185 | "push r24 \n\t" \ 186 | "push r25 \n\t" \ 187 | "push r26 \n\t" \ 188 | "push r27 \n\t" \ 189 | "push r28 \n\t" \ 190 | "push r29 \n\t" \ 191 | "push r30 \n\t" \ 192 | "push r31 \n\t" \ 193 | "lds r26, pxCurrentTCB \n\t" \ 194 | "lds r27, pxCurrentTCB + 1 \n\t" \ 195 | "in r0, __SP_L__ \n\t" \ 196 | "st x+, r0 \n\t" \ 197 | "in r0, __SP_H__ \n\t" \ 198 | "st x+, r0 \n\t"); \ 199 | } 200 | 201 | /* Opposite to portSAVE_CONTEXT(). Interrupts will have been disabled during 202 | * the context save so we can write to the stack pointer. */ 203 | #define portRESTORE_CONTEXT() \ 204 | { \ 205 | asm volatile("lds r26, pxCurrentTCB \n\t" \ 206 | "lds r27, pxCurrentTCB + 1 \n\t" \ 207 | "ld r28, x+ \n\t" \ 208 | "out __SP_L__, r28 \n\t" \ 209 | "ld r29, x+ \n\t" \ 210 | "out __SP_H__, r29 \n\t" \ 211 | "pop r31 \n\t" \ 212 | "pop r30 \n\t" \ 213 | "pop r29 \n\t" \ 214 | "pop r28 \n\t" \ 215 | "pop r27 \n\t" \ 216 | "pop r26 \n\t" \ 217 | "pop r25 \n\t" \ 218 | "pop r24 \n\t" \ 219 | "pop r23 \n\t" \ 220 | "pop r22 \n\t" \ 221 | "pop r21 \n\t" \ 222 | "pop r20 \n\t" \ 223 | "pop r19 \n\t" \ 224 | "pop r18 \n\t" \ 225 | "pop r17 \n\t" \ 226 | "pop r16 \n\t" \ 227 | "pop r15 \n\t" \ 228 | "pop r14 \n\t" \ 229 | "pop r13 \n\t" \ 230 | "pop r12 \n\t" \ 231 | "pop r11 \n\t" \ 232 | "pop r10 \n\t" \ 233 | "pop r9 \n\t" \ 234 | "pop r8 \n\t" \ 235 | "pop r7 \n\t" \ 236 | "pop r6 \n\t" \ 237 | "pop r5 \n\t" \ 238 | "pop r4 \n\t" \ 239 | "pop r3 \n\t" \ 240 | "pop r2 \n\t" \ 241 | "pop r1 \n\t"); \ 242 | portRESTORE_RAMPZ(); \ 243 | asm volatile("pop r0 \n\t" \ 244 | "out __SREG__, r0 \n\t" \ 245 | "pop r0 \n\t"); \ 246 | } 247 | /*-----------------------------------------------------------*/ 248 | 249 | #define portSET_MODE_AND_SLEEP(mode) \ 250 | { \ 251 | set_sleep_mode(mode); \ 252 | sleep_enable(); \ 253 | portENABLE_INTERRUPTS(); \ 254 | sleep_cpu(); \ 255 | portDISABLE_INTERRUPTS(); \ 256 | sleep_disable(); \ 257 | } 258 | 259 | /* *INDENT-OFF* */ 260 | #ifdef __cplusplus 261 | } 262 | #endif 263 | /* *INDENT-ON* */ 264 | 265 | #endif /* PORTMACRO_H */ 266 | -------------------------------------------------------------------------------- /GCC/AVR_Mega0/LICENSE: -------------------------------------------------------------------------------- 1 | FreeRTOS Kernel 2 | Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. 3 | 4 | SPDX-License-Identifier: MIT 5 | 6 | Permission is hereby granted, free of charge, to any person obtaining a copy of 7 | this software and associated documentation files (the "Software"), to deal in 8 | the Software without restriction, including without limitation the rights to 9 | use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of 10 | the Software, and to permit persons to whom the Software is furnished to do so, 11 | subject to the following conditions: 12 | 13 | The above copyright notice and this permission notice shall be included in all 14 | copies or substantial portions of the Software. 15 | 16 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS 18 | FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR 19 | COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER 20 | IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 21 | CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 22 | 23 | https://www.FreeRTOS.org 24 | https://github.com/FreeRTOS 25 | -------------------------------------------------------------------------------- /GCC/AVR_Mega0/porthardware.h: -------------------------------------------------------------------------------- 1 | /* 2 | * FreeRTOS Kernel 3 | * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. 4 | * 5 | * SPDX-License-Identifier: MIT 6 | * 7 | * Permission is hereby granted, free of charge, to any person obtaining a copy of 8 | * this software and associated documentation files (the "Software"), to deal in 9 | * the Software without restriction, including without limitation the rights to 10 | * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of 11 | * the Software, and to permit persons to whom the Software is furnished to do so, 12 | * subject to the following conditions: 13 | * 14 | * The above copyright notice and this permission notice shall be included in all 15 | * copies or substantial portions of the Software. 16 | * 17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS 19 | * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR 20 | * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER 21 | * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 22 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 23 | * 24 | * https://www.FreeRTOS.org 25 | * https://github.com/FreeRTOS 26 | * 27 | */ 28 | 29 | #ifndef PORTHARDWARE_H 30 | #define PORTHARDWARE_H 31 | 32 | #include "FreeRTOSConfig.h" 33 | 34 | /*-----------------------------------------------------------*/ 35 | 36 | #define CLR_INT( FLAG_REG, FLAG_MASK ) \ 37 | asm volatile ( \ 38 | "push r16\n\t" \ 39 | "ldi r16, %1\n\t" \ 40 | "sts %0, r16\n\t" \ 41 | "pop r16\n\t" \ 42 | : \ 43 | : "i" ( _SFR_MEM_ADDR( FLAG_REG ) ), "i" ( ( uint8_t ) ( FLAG_MASK ) ) \ 44 | ); 45 | 46 | #if ( configUSE_TIMER_INSTANCE == 0 ) 47 | 48 | #define TICK_INT_vect TCB0_INT_vect 49 | #define INT_FLAGS TCB0_INTFLAGS 50 | #define INT_MASK TCB_CAPT_bm 51 | 52 | #define TICK_init() \ 53 | { \ 54 | TCB0.CCMP = configCPU_CLOCK_HZ / configTICK_RATE_HZ; \ 55 | TCB0.INTCTRL = TCB_CAPT_bm; \ 56 | TCB0.CTRLA = TCB_ENABLE_bm; \ 57 | } 58 | 59 | #define TICK_TMR_STOP() TCB0.CTRLA = 0x00; 60 | #define TICK_TMR_START() \ 61 | { \ 62 | TCB0.INTFLAGS = TCB_CAPT_bm; \ 63 | TCB0.CTRLA = TCB_ENABLE_bm; \ 64 | } 65 | #define TICK_TMR_READ() TCB0.CNT 66 | #define TICK_INT_READY() (TCB0.INTCTRL & TCB_CAPT_bm) 67 | 68 | #elif ( configUSE_TIMER_INSTANCE == 1 ) 69 | 70 | #define TICK_INT_vect TCB1_INT_vect 71 | #define INT_FLAGS TCB1_INTFLAGS 72 | #define INT_MASK TCB_CAPT_bm 73 | 74 | #define TICK_init() \ 75 | { \ 76 | TCB1.CCMP = configCPU_CLOCK_HZ / configTICK_RATE_HZ; \ 77 | TCB1.INTCTRL = TCB_CAPT_bm; \ 78 | TCB1.CTRLA = TCB_ENABLE_bm; \ 79 | } 80 | 81 | #define TICK_TMR_STOP() TCB1.CTRLA = 0x00; 82 | #define TICK_TMR_START() \ 83 | { \ 84 | TCB1.INTFLAGS = TCB_CAPT_bm; \ 85 | TCB1.CTRLA = TCB_ENABLE_bm; \ 86 | } 87 | #define TICK_TMR_READ() TCB1.CNT 88 | #define TICK_INT_READY() (TCB1.INTCTRL & TCB_CAPT_bm) 89 | 90 | #elif ( configUSE_TIMER_INSTANCE == 2 ) 91 | 92 | #define TICK_INT_vect TCB2_INT_vect 93 | #define INT_FLAGS TCB2_INTFLAGS 94 | #define INT_MASK TCB_CAPT_bm 95 | 96 | #define TICK_init() \ 97 | { \ 98 | TCB2.CCMP = configCPU_CLOCK_HZ / configTICK_RATE_HZ; \ 99 | TCB2.INTCTRL = TCB_CAPT_bm; \ 100 | TCB2.CTRLA = TCB_ENABLE_bm; \ 101 | } 102 | 103 | #define TICK_TMR_STOP() TCB2.CTRLA = 0x00; 104 | #define TICK_TMR_START() \ 105 | { \ 106 | TCB2.INTFLAGS = TCB_CAPT_bm; \ 107 | TCB2.CTRLA = TCB_ENABLE_bm; \ 108 | } 109 | #define TICK_TMR_READ() TCB2.CNT 110 | #define TICK_INT_READY() (TCB2.INTCTRL & TCB_CAPT_bm) 111 | 112 | #elif ( configUSE_TIMER_INSTANCE == 3 ) 113 | 114 | #define TICK_INT_vect TCB3_INT_vect 115 | #define INT_FLAGS TCB3_INTFLAGS 116 | #define INT_MASK TCB_CAPT_bm 117 | 118 | #define TICK_init() \ 119 | { \ 120 | TCB3.CCMP = configCPU_CLOCK_HZ / configTICK_RATE_HZ; \ 121 | TCB3.INTCTRL = TCB_CAPT_bm; \ 122 | TCB3.CTRLA = TCB_ENABLE_bm; \ 123 | } 124 | 125 | #define TICK_TMR_STOP() TCB3.CTRLA = 0x00; 126 | #define TICK_TMR_START() \ 127 | { \ 128 | TCB3.INTFLAGS = TCB_CAPT_bm; \ 129 | TCB3.CTRLA = TCB_ENABLE_bm; \ 130 | } 131 | #define TICK_TMR_READ() TCB3.CNT 132 | #define TICK_INT_READY() (TCB3.INTCTRL & TCB_CAPT_bm) 133 | 134 | #elif ( configUSE_TIMER_INSTANCE == 4 ) 135 | 136 | #define TICK_INT_vect RTC_CNT_vect 137 | #define INT_FLAGS RTC_INTFLAGS 138 | #define INT_MASK RTC_OVF_bm 139 | 140 | /* Hertz to period for RTC setup */ 141 | #define RTC_PERIOD_HZ( x ) ( 32768 * ( ( 1.0 / x ) ) ) 142 | #define TICK_init() \ 143 | { \ 144 | while( RTC.STATUS > 0 ) {; } \ 145 | RTC.CTRLA = RTC_PRESCALER_DIV1_gc | 1 << RTC_RTCEN_bp; \ 146 | RTC.PER = RTC_PERIOD_HZ( configTICK_RATE_HZ ); \ 147 | RTC.INTCTRL |= 1 << RTC_OVF_bp; \ 148 | } 149 | 150 | #else /* if ( configUSE_TIMER_INSTANCE == 0 ) */ 151 | #undef TICK_INT_vect 152 | #undef INT_FLAGS 153 | #undef INT_MASK 154 | #undef TICK_init 155 | #error Invalid timer setting. 156 | #endif /* if ( configUSE_TIMER_INSTANCE == 0 ) */ 157 | 158 | 159 | #if ( configUSE_TICKLESS_IDLE == 1 ) 160 | 161 | #define LOW_POWER_CLOCK (32768UL) 162 | 163 | #define RTC_TICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) 164 | #define RTC_TICKS_TO_COUNTS(tick_cnt) (uint32_t)(((float)(tick_cnt * LOW_POWER_CLOCK)/configTICK_RATE_HZ) - 0.5) 165 | #define RTC_COUNTS_TO_TICKS(counts) (uint32_t)((float)((counts * 1.0) * configTICK_RATE_HZ)/LOW_POWER_CLOCK ) 166 | 167 | 168 | #define RTC_INIT() \ 169 | { \ 170 | while( RTC.STATUS > 0 ) {; } \ 171 | RTC.PER = 0xFFFF; \ 172 | RTC.CMP = 0x3FFF; \ 173 | RTC.CNT = 0; \ 174 | RTC.INTFLAGS = RTC_OVF_bm | RTC_CMP_bm; \ 175 | RTC.CTRLA = RTC_RUNSTDBY_bm | RTC_PRESCALER_DIV1_gc | RTC_RTCEN_bm ; \ 176 | RTC.INTCTRL = RTC_OVF_bm | RTC_CMP_bm; \ 177 | } 178 | 179 | #endif 180 | 181 | /*-----------------------------------------------------------*/ 182 | 183 | #endif /* PORTHARDWARE_H */ 184 | -------------------------------------------------------------------------------- /GCC/AVR_Mega0/portmacro.h: -------------------------------------------------------------------------------- 1 | /* 2 | * FreeRTOS Kernel 3 | * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. 4 | * 5 | * SPDX-License-Identifier: MIT 6 | * 7 | * Permission is hereby granted, free of charge, to any person obtaining a copy of 8 | * this software and associated documentation files (the "Software"), to deal in 9 | * the Software without restriction, including without limitation the rights to 10 | * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of 11 | * the Software, and to permit persons to whom the Software is furnished to do so, 12 | * subject to the following conditions: 13 | * 14 | * The above copyright notice and this permission notice shall be included in all 15 | * copies or substantial portions of the Software. 16 | * 17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS 19 | * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR 20 | * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER 21 | * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 22 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 23 | * 24 | * https://www.FreeRTOS.org 25 | * https://github.com/FreeRTOS 26 | * 27 | */ 28 | 29 | #ifndef PORTMACRO_H 30 | #define PORTMACRO_H 31 | 32 | /* *INDENT-OFF* */ 33 | #ifdef __cplusplus 34 | extern "C" { 35 | #endif 36 | /* *INDENT-ON* */ 37 | 38 | #include 39 | /*----------------------------------------------------------- 40 | * Port specific definitions. 41 | * 42 | * The settings in this file configure FreeRTOS correctly for the 43 | * given hardware and compiler. 44 | * 45 | * These settings should not be altered. 46 | *----------------------------------------------------------- 47 | */ 48 | 49 | /* Type definitions. */ 50 | #define portCHAR char 51 | #define portFLOAT float 52 | #define portDOUBLE double 53 | #define portLONG long 54 | #define portSHORT int 55 | #define portSTACK_TYPE uint8_t 56 | #define portBASE_TYPE char 57 | 58 | #define portPOINTER_SIZE_TYPE uint16_t 59 | 60 | typedef portSTACK_TYPE StackType_t; 61 | typedef signed char BaseType_t; 62 | typedef unsigned char UBaseType_t; 63 | 64 | #if ( configUSE_16_BIT_TICKS == 1 ) 65 | typedef uint16_t TickType_t; 66 | #define portMAX_DELAY ( TickType_t ) 0xffff 67 | #else 68 | typedef uint32_t TickType_t; 69 | #define portMAX_DELAY ( TickType_t ) 0xffffffffUL 70 | #endif 71 | /*-----------------------------------------------------------*/ 72 | 73 | /* Critical section management. */ 74 | #define portENTER_CRITICAL() \ 75 | asm volatile ( "in __tmp_reg__, __SREG__" ); \ 76 | asm volatile ( "cli" ); \ 77 | asm volatile ( "push __tmp_reg__" ) 78 | 79 | #define portEXIT_CRITICAL() \ 80 | asm volatile ( "pop __tmp_reg__" ); \ 81 | asm volatile ( "out __SREG__, __tmp_reg__" ) 82 | 83 | #define portDISABLE_INTERRUPTS() asm volatile ( "cli" ::); 84 | #define portENABLE_INTERRUPTS() asm volatile ( "sei" ::); 85 | /*-----------------------------------------------------------*/ 86 | 87 | /* Architecture specifics. */ 88 | #define portSTACK_GROWTH ( -1 ) 89 | #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) 90 | #define portBYTE_ALIGNMENT 1 91 | #define portNOP() asm volatile ( "nop" ); 92 | /*-----------------------------------------------------------*/ 93 | 94 | /* Kernel utilities. */ 95 | extern void vPortYield( void ) __attribute__( ( naked ) ); 96 | #define portYIELD() vPortYield() 97 | 98 | extern void vPortYieldFromISR( void ) __attribute__( ( naked ) ); 99 | #define portYIELD_FROM_ISR() vPortYieldFromISR() 100 | /*-----------------------------------------------------------*/ 101 | 102 | /* Task function macros as described on the FreeRTOS.org WEB site. */ 103 | #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) 104 | #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) 105 | 106 | /* Macros for tickless idle/low power functionality. */ 107 | #ifndef portSUPPRESS_TICKS_AND_SLEEP 108 | 109 | extern void vPortSuppressTicksAndSleep(TickType_t xExpectedIdleTime); 110 | #define portSUPPRESS_TICKS_AND_SLEEP(xExpectedIdleTime) vPortSuppressTicksAndSleep(xExpectedIdleTime) 111 | #endif 112 | 113 | #ifndef configPRE_PWR_DOWN_PROCESSING 114 | #define configPRE_PWR_DOWN_PROCESSING() 115 | #endif 116 | 117 | #ifndef configPOST_PWR_DOWN_PROCESSING 118 | #define configPOST_PWR_DOWN_PROCESSING() 119 | #endif 120 | 121 | /*-----------------------------------------------------------*/ 122 | 123 | /* Helper macros for portSAVE_CONTEXT/ portRESTORE_CONTEXT - common support for Mega-0 and AVR-Dx families */ 124 | 125 | #if defined(__AVR_HAVE_RAMPZ__) 126 | 127 | #define portSAVE_RAMPZ() \ 128 | asm volatile("in r0, __RAMPZ__ \n\t" \ 129 | "push r0 \n\t"); 130 | 131 | #define portRESTORE_RAMPZ() \ 132 | asm volatile("pop r0 \n\t" \ 133 | "out __RAMPZ__, r0 \n\t"); 134 | 135 | #else 136 | 137 | #define portSAVE_RAMPZ() 138 | #define portRESTORE_RAMPZ() 139 | 140 | #endif 141 | 142 | /* Macro to save all the general purpose registers, the save the stack pointer 143 | * into the TCB. 144 | 145 | * The first thing we do is save the flags then disable interrupts. This is to 146 | * guard our stack against having a context switch interrupt after we have already 147 | * pushed the registers onto the stack - causing the 32 registers to be on the 148 | * stack twice. 149 | 150 | * r1 is set to zero as the compiler expects it to be thus, however some 151 | * of the math routines make use of R1. 152 | 153 | * The interrupts will have been disabled during the call to portSAVE_CONTEXT() 154 | * so we need not worry about reading/writing to the stack pointer. */ 155 | 156 | #define portSAVE_CONTEXT() \ 157 | { \ 158 | asm volatile("push r0 \n\t" \ 159 | "in r0, __SREG__ \n\t" \ 160 | "cli \n\t" \ 161 | "push r0 \n\t"); \ 162 | portSAVE_RAMPZ(); \ 163 | asm volatile("push r1 \n\t" \ 164 | "clr r1 \n\t" \ 165 | "push r2 \n\t" \ 166 | "push r3 \n\t" \ 167 | "push r4 \n\t" \ 168 | "push r5 \n\t" \ 169 | "push r6 \n\t" \ 170 | "push r7 \n\t" \ 171 | "push r8 \n\t" \ 172 | "push r9 \n\t" \ 173 | "push r10 \n\t" \ 174 | "push r11 \n\t" \ 175 | "push r12 \n\t" \ 176 | "push r13 \n\t" \ 177 | "push r14 \n\t" \ 178 | "push r15 \n\t" \ 179 | "push r16 \n\t" \ 180 | "push r17 \n\t" \ 181 | "push r18 \n\t" \ 182 | "push r19 \n\t" \ 183 | "push r20 \n\t" \ 184 | "push r21 \n\t" \ 185 | "push r22 \n\t" \ 186 | "push r23 \n\t" \ 187 | "push r24 \n\t" \ 188 | "push r25 \n\t" \ 189 | "push r26 \n\t" \ 190 | "push r27 \n\t" \ 191 | "push r28 \n\t" \ 192 | "push r29 \n\t" \ 193 | "push r30 \n\t" \ 194 | "push r31 \n\t" \ 195 | "lds r26, pxCurrentTCB \n\t" \ 196 | "lds r27, pxCurrentTCB + 1 \n\t" \ 197 | "in r0, __SP_L__ \n\t" \ 198 | "st x+, r0 \n\t" \ 199 | "in r0, __SP_H__ \n\t" \ 200 | "st x+, r0 \n\t"); \ 201 | } 202 | 203 | /* Opposite to portSAVE_CONTEXT(). Interrupts will have been disabled during 204 | * the context save so we can write to the stack pointer. */ 205 | #define portRESTORE_CONTEXT() \ 206 | { \ 207 | asm volatile("lds r26, pxCurrentTCB \n\t" \ 208 | "lds r27, pxCurrentTCB + 1 \n\t" \ 209 | "ld r28, x+ \n\t" \ 210 | "out __SP_L__, r28 \n\t" \ 211 | "ld r29, x+ \n\t" \ 212 | "out __SP_H__, r29 \n\t" \ 213 | "pop r31 \n\t" \ 214 | "pop r30 \n\t" \ 215 | "pop r29 \n\t" \ 216 | "pop r28 \n\t" \ 217 | "pop r27 \n\t" \ 218 | "pop r26 \n\t" \ 219 | "pop r25 \n\t" \ 220 | "pop r24 \n\t" \ 221 | "pop r23 \n\t" \ 222 | "pop r22 \n\t" \ 223 | "pop r21 \n\t" \ 224 | "pop r20 \n\t" \ 225 | "pop r19 \n\t" \ 226 | "pop r18 \n\t" \ 227 | "pop r17 \n\t" \ 228 | "pop r16 \n\t" \ 229 | "pop r15 \n\t" \ 230 | "pop r14 \n\t" \ 231 | "pop r13 \n\t" \ 232 | "pop r12 \n\t" \ 233 | "pop r11 \n\t" \ 234 | "pop r10 \n\t" \ 235 | "pop r9 \n\t" \ 236 | "pop r8 \n\t" \ 237 | "pop r7 \n\t" \ 238 | "pop r6 \n\t" \ 239 | "pop r5 \n\t" \ 240 | "pop r4 \n\t" \ 241 | "pop r3 \n\t" \ 242 | "pop r2 \n\t" \ 243 | "pop r1 \n\t"); \ 244 | portRESTORE_RAMPZ(); \ 245 | asm volatile("pop r0 \n\t" \ 246 | "out __SREG__, r0 \n\t" \ 247 | "pop r0 \n\t"); \ 248 | } 249 | /*-----------------------------------------------------------*/ 250 | 251 | #define portSET_MODE_AND_SLEEP(mode) \ 252 | { \ 253 | set_sleep_mode(mode); \ 254 | sleep_enable(); \ 255 | portENABLE_INTERRUPTS(); \ 256 | sleep_cpu(); \ 257 | portDISABLE_INTERRUPTS(); \ 258 | sleep_disable(); \ 259 | } 260 | 261 | /* *INDENT-OFF* */ 262 | #ifdef __cplusplus 263 | } 264 | #endif 265 | /* *INDENT-ON* */ 266 | 267 | #endif /* PORTMACRO_H */ 268 | -------------------------------------------------------------------------------- /GHS/U2x/LICENSE: -------------------------------------------------------------------------------- 1 | FreeRTOS Kernel V11.1.0 2 | Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. 3 | 4 | SPDX-License-Identifier: MIT 5 | 6 | Permission is hereby granted, free of charge, to any person obtaining a copy of 7 | this software and associated documentation files (the "Software"), to deal in 8 | the Software without restriction, including without limitation the rights to 9 | use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of 10 | the Software, and to permit persons to whom the Software is furnished to do so, 11 | subject to the following conditions: 12 | 13 | The above copyright notice and this permission notice shall be included in all 14 | copies or substantial portions of the Software. 15 | 16 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS 18 | FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR 19 | COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER 20 | IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 21 | CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 22 | 23 | https://www.FreeRTOS.org 24 | https://github.com/FreeRTOS 25 | -------------------------------------------------------------------------------- /GHS/U2x/README.md: -------------------------------------------------------------------------------- 1 | # RH850/U2x FreeRTOS Port with GHS Compiler 2 | 3 | ## Introduction 4 | 5 | This repository contains the port of FreeRTOS for Renesas RH850/U2x microcontrollers using the GHS compiler. The following sections provide instructions on how to use this port, a link to the test project, and other relevant information. 6 | 7 | ## Prerequisites 8 | - Compiler: GHS 9 | - FreeRTOS version 11.1.0 10 | 11 | | Device | FPU | FXU | SMP | 12 | |----------|-----|-----|-----| 13 | | U2A6 | Yes | No | Yes | 14 | | U2A8 | Yes | No | Yes | 15 | | U2A16 | Yes | No | Yes | 16 | | U2B6 | Yes | Yes | Yes | 17 | | U2B10 | Yes | Yes | Yes | 18 | 19 | ## Link to Test Project 20 | 21 | The test project can be found in [RH850_U2Ax_GHS](https://github.com/renesas/FreeRTOS-Partner-Supported-Demos/tree/u2x_port/) and [RH850_U2Bx_GHS](https://github.com/renesas/FreeRTOS-Partner-Supported-Demos/tree/u2x_port/). This project contains example tasks and configurations to help you get started with FreeRTOS on the RH850/U2Ax and U2Bx. 22 | 23 | ## Note 24 | 1. The minimal stack size `configMINIMAL_STACK_SIZE` must be included the reserved memory for nested interrupt. This formula can be referred: `(task_context_size) * (2 + configMAX_INT_NESTING) + Stack_depth_of_taskcode` 25 | In which, `task_context_size` is calculated as `36*4bytes = 144bytes` (when FPU enabled) or `34*4bytes = 136` (when FPU disabled), configMAX_INT_NESTING is `02` as default (Note that a value of `0` is not allowed). 26 | 2. Users need to create a memory section named `mev_address` in `CRAM` for Exclusive Control functionality. Users should initialize the `mev_address` section in the startup file. 27 | 28 | Example: 29 | ``` 30 | -- .mev_address section in CRAM is used for Sync flags 31 | mov ___ghsbegin_mev_address, r20 32 | st.w r0, 0[r20] 33 | ``` 34 | 3. The `FXU unit` is only available on `core 0`. Users must ensure that FXU operations are restricted to `core 0` by using the `vTaskCoreAffinitySet` function provided by FreeRTOS SMP. 35 | 4. Set the macro `configENABLE_FXU` to `1` to enable the `FXU unit`; otherwise set `0` to disable `FXU unit`. 36 | 5. This port supports both U2Ax and U2Bx devices. The user must configure `configDEVICE_NAME` with the value `U2Bx_DEVICES` or `U2Ax_DEVICES` to specify which device is being used. 37 | 6. The User can configure the interrupt priority of the OSTM Timer using `configTIMER_INT_PRIORITY`, with 16 levels available (0 being the highest priority and 15 the lowest). 38 | 7. This port also supports the configuration of contiguous CPU cores in FreeRTOS, allowing the user to set task affinity for execution on specific cores or subsets of cores. 39 | 40 | ## Other Relevant Information 41 | 42 | - **Documentation:** 43 | - Refer to the official [FreeRTOS documentation](https://www.freertos.org/Documentation/RTOS_book.html) for detailed information on configuring and using FreeRTOS. 44 | - Consult the [RH850 U2A group user manual hardware manual](https://www.renesas.com/en/document/mah/rh850u2a-eva-group-users-manual-hardware-0?r=1546621) for specific details about the microcontroller. 45 | - Consult the [RH850 U2B group user manual hardware manual](https://www.renesas.com/en/document/mah/rh850u2b-flash-memory-users-manual-r01uh0927ej0100?srsltid=AfmBOooTd6sk-_EsdVV0L_Rw0vGMsaoCQ0SSzpmtoScRcxgcwVkLrQwY) for specific details about the microcontroller. 46 | - For more information about Renesas RH850 microcontrolers, please visit [this website](https://www.renesas.com/us/en/products/microcontrollers-microprocessors/rh850-automotive-mcus) 47 | 48 | - **Support:** 49 | - If you encounter any issues or have questions about this port, please open an issue in this repository or contact the maintainer. 50 | 51 | - **Contributing:** 52 | - Contributions to improve this port are welcome. Please fork the repository, make your changes, and submit a pull request. -------------------------------------------------------------------------------- /GHS/U2x/portasm.850: -------------------------------------------------------------------------------- 1 | --/* 2 | -- * FreeRTOS Kernel V11.1.0 3 | -- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. 4 | -- * 5 | -- * SPDX-License-Identifier: MIT 6 | -- * 7 | -- * Permission is hereby granted, free of charge, to any person obtaining a copy of 8 | -- * this software and associated documentation files (the "Software"), to deal in 9 | -- * the Software without restriction, including without limitation the rights to 10 | -- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of 11 | -- * the Software, and to permit persons to whom the Software is furnished to do so, 12 | -- * subject to the following conditions: 13 | -- * 14 | -- * The above copyright notice and this permission notice shall be included in all 15 | -- * copies or substantial portions of the Software. 16 | -- * 17 | -- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 | -- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS 19 | -- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR 20 | -- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER 21 | -- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 22 | -- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 23 | -- * 24 | -- * https://www.FreeRTOS.org 25 | -- * https://github.com/FreeRTOS 26 | -- * 27 | -- */ 28 | 29 | #include "FreeRTOSConfig.h" 30 | 31 | ------------------------------------------------------------------------------- 32 | -- Extern symbols 33 | ------------------------------------------------------------------------------- 34 | .extern _uxInterruptNesting 35 | .extern _uxPortMaxInterruptDepth 36 | .extern _xPortScheduleStatus 37 | .extern _vTaskSwitchContext 38 | .extern _pvPortGetCurrentTCB 39 | .extern _vCommonISRHandler 40 | .extern _xPortGET_CORE_ID 41 | 42 | .global _vIrq_Handler 43 | .global _vPortStartFirstTask 44 | .global _vPortYield 45 | .global _vTRAP0_Handler 46 | -------------------------------------------------------------------------------- 47 | -- Macro definitions 48 | -------------------------------------------------------------------------------- 49 | .set EIPC, 0 50 | .set EIPSW, 1 51 | .set PSW, 5 52 | .set FPSR, 6 53 | .set FPEPC, 7 54 | .set FXSR, 6 55 | .set FXXP, 13 56 | .set EIIC, 13 57 | .set CTPC, 16 58 | .set CTPSW, 17 59 | .set EIIC_MSK, 0x00000FFF 60 | -------------------------------------------------------------------------------- 61 | -- portSAVE_CONTEXT 62 | -- Context saving 63 | -------------------------------------------------------------------------------- 64 | .macro portSAVE_CONTEXT 65 | prepare {lp}, 0 66 | 67 | -- Save general-purpose registers and EIPSW, EIPC, EIIC, CTPSW, CTPC into stack. 68 | pushsp r5-r30 69 | --$nowarning 70 | pushsp r1-r2 71 | --$warning 72 | 73 | stsr EIPSW, r15 74 | stsr EIPC, r16 75 | stsr EIIC, r17 76 | stsr CTPSW, r18 77 | stsr CTPC, r19 78 | pushsp r15-r19 79 | 80 | -- Save FPU registers to stack if FPU is enabled 81 | #if (1 == configENABLE_FPU) 82 | stsr FPSR, r18 83 | stsr FPEPC, r19 84 | pushsp r18-r19 85 | #endif 86 | 87 | -- Save FXU registers to stack if FXU is enabled 88 | #if (1 == configENABLE_FXU) 89 | mov r0, r20 90 | mov r0, r21 91 | stsr 0, r19, 2 -- Get PEID 92 | cmp r19, r0 -- Confirm PEID value is PE0 93 | bne 8 -- branch 2 instructions if is not PE0 94 | -- to avoid unprivileged access 95 | stsr FXSR, r20, 10 -- If PE0, save FXU register 96 | stsr FXXP, r21, 10 -- If PE0, save FXU register 97 | pushsp r20-r21 98 | #endif 99 | 100 | -- Get current TCB, the return value is stored in r10 101 | jarl _pvPortGetCurrentTCB, lp 102 | st.w sp, 0[r10] 103 | 104 | .endm 105 | 106 | -------------------------------------------------------------------------------- 107 | -- portRESTORE_CONTEXT 108 | -- Context restoring 109 | -------------------------------------------------------------------------------- 110 | .macro portRESTORE_CONTEXT 111 | -- Current TCB is returned by r10 112 | jarl _pvPortGetCurrentTCB, lp 113 | ld.w 0[r10], sp -- Restore the stack pointer from the TCB 114 | 115 | -- Restore FXU registers if FXU is enabled 116 | #if (1 == configENABLE_FXU) 117 | popsp r20-r21 118 | stsr 0, r19, 2 -- Get PEID 119 | cmp r19, r0 -- Confirm PEID value is PE0 120 | bne 8 -- branch 2 instructions if is not PE0 121 | -- to avoid unprivileged access 122 | ldsr r21, FXXP, 10 -- If PE0, restore FXU register 123 | ldsr r20, FXSR, 10 -- If PE0, restore FXU register 124 | #endif 125 | 126 | -- Restore FPU registers if FPU is enabled 127 | #if (1 == configENABLE_FPU) 128 | popsp r18-r19 129 | ldsr r19, FPEPC 130 | ldsr r18, FPSR 131 | #endif 132 | 133 | --Restore general-purpose registers and EIPSW, EIPC, EIIC, CTPSW, CTPC 134 | popsp r15-r19 135 | ldsr r19, CTPC 136 | ldsr r18, CTPSW 137 | ldsr r17, EIIC 138 | ldsr r16, EIPC 139 | ldsr r15, EIPSW 140 | 141 | --$nowarning 142 | popsp r1-r2 143 | --$warning 144 | popsp r5-r30 145 | 146 | dispose 0, {lp} 147 | .endm 148 | 149 | -------------------------------------------------------------------------------- 150 | -- Save used registers 151 | -------------------------------------------------------------------------------- 152 | .macro SAVE_REGISTER 153 | pushsp r5-r30 154 | --$nowarning 155 | pushsp r1-r2 156 | --$warning 157 | 158 | stsr EIPSW, r19 159 | stsr EIPC, r18 160 | stsr EIIC, r17 161 | mov lp, r16 162 | mov ep, r15 163 | stsr CTPSW, r14 164 | stsr CTPC, r13 165 | pushsp r13-r19 166 | 167 | #if (1 == configENABLE_FPU) 168 | stsr FPSR, r18 169 | stsr FPEPC, r19 170 | pushsp r18-r19 171 | #endif 172 | 173 | -- Save FXU registers to stack if FXU is enabled 174 | #if (1 == configENABLE_FXU) 175 | mov r0, r20 176 | mov r0, r21 177 | stsr 0, r19, 2 -- Get PEID 178 | cmp r19, r0 -- Confirm PEID value is PE0 179 | bne 8 -- Branch 2 instructions if is not PE0 180 | -- to avoid unprivileged access 181 | stsr FXSR, r20, 10 -- If PE0, save FXU register 182 | stsr FXXP, r21, 10 -- If PE0, save FXU register 183 | pushsp r20-r21 184 | #endif 185 | 186 | .endm 187 | -------------------------------------------------------------------------------- 188 | -- Restore used registers 189 | -------------------------------------------------------------------------------- 190 | .macro RESTORE_REGISTER 191 | -- Restore FXU registers if FXU is enabled 192 | #if (1 == configENABLE_FXU) 193 | popsp r20-r21 194 | stsr 0, r19, 2 -- Get PEID 195 | cmp r19, r0 -- Confirm PEID value is PE0 196 | bne 8 -- Branch 2 instructions if is not PE0 197 | -- to avoid unprivileged access 198 | ldsr r21, FXXP, 10 -- If PE0, restore FXU register 199 | ldsr r20, FXSR, 10 -- If PE0, restore FXU register 200 | #endif 201 | 202 | #if (1 == configENABLE_FPU) 203 | popsp r18-r19 204 | ldsr r19, FPEPC 205 | ldsr r18, FPSR 206 | #endif 207 | 208 | popsp r13-r19 209 | ldsr r13, CTPC 210 | ldsr r14, CTPSW 211 | mov r15, ep 212 | mov r16, lp 213 | ldsr r17, EIIC 214 | ldsr r18, EIPC 215 | ldsr r19, EIPSW 216 | 217 | --$nowarning 218 | popsp r1-r2 219 | --$warning 220 | popsp r5-r30 221 | .endm 222 | 223 | -------------------------------------------------------------------------------- 224 | -- Start the first task. 225 | -------------------------------------------------------------------------------- 226 | _vPortStartFirstTask: 227 | portRESTORE_CONTEXT 228 | eiret 229 | 230 | -------------------------------------------------------------------------------- 231 | -- _vPortYield 232 | -------------------------------------------------------------------------------- 233 | _vPortYield: 234 | trap 0 235 | jmp [lp] -- Return to caller function 236 | 237 | -------------------------------------------------------------------------------- 238 | -- PortYield handler. This is installed as the TRAP exception handler. 239 | -------------------------------------------------------------------------------- 240 | _vTRAP0_Handler: 241 | --Save the context of the current task. 242 | portSAVE_CONTEXT 243 | 244 | -- The use case that portYield() is called from interrupt context as nested interrupt. 245 | -- Context switch should be executed at the most outer of interrupt tree. 246 | -- In that case, set xPortScheduleStatus to flag context switch in interrupt handler. 247 | jarl _xPortGET_CORE_ID, lp -- return value is contained in r10 248 | mov r10, r11 249 | shl 2, r11 250 | mov _uxInterruptNesting, r19 251 | add r11, r19 252 | ld.w 0[r19], r18 253 | cmp r0, r18 254 | be _vTRAP0_Handler_ContextSwitch 255 | 256 | mov _xPortScheduleStatus, r19 257 | add r11, r19 258 | 259 | -- Set xPortScheduleStatus[coreID]=PORT_SCHEDULER_TASKSWITCH 260 | mov 1, r17 261 | st.w r17, 0[r19] 262 | br _vTRAP0_Handler_Exit 263 | 264 | _vTRAP0_Handler_ContextSwitch: 265 | -- Pass coreID (r10) as parameter by r6 in SMP support. 266 | mov r10, r6 267 | -- Call the scheduler to select the next task. 268 | -- vPortYeild may be called to current core again at the end of vTaskSwitchContext. 269 | -- This may case nested interrupt, however, it is not necessary to set 270 | -- uxInterruptNesting (currently 0) for nested trap0 exception. The user interrupt 271 | -- (EI level interrupt) is not accepted inside of trap0 exception. 272 | jarl _vTaskSwitchContext, lp 273 | 274 | _vTRAP0_Handler_Exit: 275 | -- Restore the context of the next task to run. 276 | portRESTORE_CONTEXT 277 | eiret 278 | 279 | -------------------------------------------------------------------------------- 280 | -- _Irq_Handler 281 | -- Handler interrupt service routine (ISR). 282 | -------------------------------------------------------------------------------- 283 | _vIrq_Handler: 284 | -- Save used registers. 285 | SAVE_REGISTER 286 | 287 | -- Get core ID by HTCFG0, thread configuration register. 288 | -- Then, increase nesting count for current core. 289 | jarl _xPortGET_CORE_ID, lp -- return value is contained in r10 290 | mov r10, r17 291 | shl 2, r17 292 | 293 | mov _uxInterruptNesting, r19 294 | add r17, r19 295 | ld.w 0[r19], r18 296 | addi 0x1, r18, r16 297 | st.w r16, 0[r19] 298 | 299 | pushsp r17-r19 300 | 301 | --Call the interrupt handler. 302 | stsr EIIC, r6 303 | andi EIIC_MSK, r6, r6 304 | 305 | -- Do not enable interrupt for nesting. Stackover flow may occurs if the 306 | -- depth of nesting interrupt is exceeded. 307 | mov _uxPortMaxInterruptDepth, r19 308 | ld.w 0[r19], r15 309 | cmp r15, r16 310 | bge 4 -- Jump over ei instruction 311 | ei 312 | jarl _vCommonISRHandler, lp 313 | di 314 | synce 315 | 316 | popsp r17-r19 317 | st.w r18, 0[r19] -- Restore the old nesting count. 318 | 319 | -- A context switch if no nesting interrupt. 320 | cmp 0x0, r18 321 | bne _vIrq_Handler_NotSwitchContext 322 | 323 | -- Check if context switch is requested. 324 | mov _xPortScheduleStatus, r19 325 | add r17, r19 326 | ld.w 0[r19], r18 327 | cmp r0, r18 328 | bne _vIrq_Handler_SwitchContext 329 | 330 | _vIrq_Handler_NotSwitchContext: 331 | -- No context switch. Restore used registers 332 | RESTORE_REGISTER 333 | eiret 334 | 335 | --This sequence is executed for primary core only to switch context 336 | _vIrq_Handler_SwitchContext: 337 | -- Clear the context switch pending flag. 338 | st.w r0, 0[r19] 339 | 340 | add -1, r18 341 | bnz _vIrq_Handler_StartFirstTask 342 | -- Restore used registers before saving the context to the task stack. 343 | RESTORE_REGISTER 344 | portSAVE_CONTEXT 345 | 346 | -- Get Core ID and pass to vTaskSwitchContext as parameter 347 | -- The parameter is unused in single core, no problem with this redudant setting 348 | jarl _xPortGET_CORE_ID, lp -- return value is contained in r10 349 | mov r10, r6 350 | 351 | -- vPortYeild may be called to current core again at the end of vTaskSwitchContext. 352 | -- This may case nested interrupt, however, it is not necessary to set 353 | -- uxInterruptNesting (currently 0) for trap0 exception. The user interrupt 354 | -- (EI level interrupt) is not accepted inside of trap0 exception. 355 | jarl _vTaskSwitchContext, lp 356 | portRESTORE_CONTEXT 357 | eiret 358 | 359 | _vIrq_Handler_StartFirstTask: 360 | RESTORE_REGISTER 361 | jr _vPortStartFirstTask 362 | 363 | -------------------------------------------------------------------------------- /GHS/U2x/portmacro.h: -------------------------------------------------------------------------------- 1 | /* 2 | * FreeRTOS Kernel V11.1.0 3 | * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. 4 | * 5 | * SPDX-License-Identifier: MIT 6 | * 7 | * Permission is hereby granted, free of charge, to any person obtaining a copy of 8 | * this software and associated documentation files (the "Software"), to deal in 9 | * the Software without restriction, including without limitation the rights to 10 | * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of 11 | * the Software, and to permit persons to whom the Software is furnished to do so, 12 | * subject to the following conditions: 13 | * 14 | * The above copyright notice and this permission notice shall be included in all 15 | * copies or substantial portions of the Software. 16 | * 17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS 19 | * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR 20 | * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER 21 | * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 22 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 23 | * 24 | * https://www.FreeRTOS.org 25 | * https://github.com/FreeRTOS 26 | * 27 | */ 28 | 29 | #ifndef PORTMACRO_H 30 | #define PORTMACRO_H 31 | 32 | #ifdef __cplusplus 33 | extern "C" 34 | { 35 | #endif 36 | 37 | /*----------------------------------------------------------- 38 | * Port specific definitions. 39 | * 40 | * The settings in this file configure FreeRTOS correctly for the 41 | * given hardware and compiler. 42 | * 43 | * These settings should not be altered. 44 | *----------------------------------------------------------- 45 | */ 46 | 47 | /* Type definitions - These are a bit legacy and not really used now, other 48 | * than portSTACK_TYPE and portBASE_TYPE. */ 49 | #define portCHAR char 50 | #define portFLOAT float 51 | #define portDOUBLE double 52 | #define portLONG long 53 | #define portSHORT short 54 | #define portSTACK_TYPE uint32_t 55 | #define portBASE_TYPE long 56 | #define portREGISTER_SEL_0 0 57 | 58 | typedef portSTACK_TYPE StackType_t; 59 | typedef long BaseType_t; 60 | typedef unsigned long UBaseType_t; 61 | 62 | /* Defines the maximum time when using a wait command in a task */ 63 | #if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) 64 | typedef uint16_t TickType_t; 65 | #define portMAX_DELAY ( TickType_t ) 0xffff 66 | #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) 67 | typedef uint32_t TickType_t; 68 | #define portMAX_DELAY ( TickType_t ) 0xffffffffUL 69 | 70 | /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do 71 | * not need to be guarded with a critical section. */ 72 | #define portTICK_TYPE_IS_ATOMIC 1 73 | #else 74 | #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. 75 | #endif 76 | 77 | /*-----------------------------------------------------------*/ 78 | 79 | /* Task utilities. */ 80 | extern void vPortYield( void ); 81 | extern void portSAVE_CONTEXT( void ); 82 | extern void portRESTORE_CONTEXT( void ); 83 | unsigned int __STSR( int regID, 84 | int selID ); 85 | void __LDSR( int regID, 86 | int selID, 87 | unsigned int val ); 88 | 89 | /* Architecture specifics */ 90 | 91 | #define portLDSR( reg, sel, val ) __LDSR( ( reg ), ( sel ), ( val ) ) 92 | #define portSTSR( reg, sel ) __STSR( ( reg ), ( sel ) ) 93 | #define portSYNCM( void ) __asm( "syncm" ) 94 | 95 | /* Specify 16 interrupt priority levels */ 96 | #define portINT_PRIORITY_HIGHEST ( 0x0000U ) /* Level 0 (highest) */ 97 | #define portINT_PRIORITY_LEVEL1 ( 0x0001U ) /* Level 1 */ 98 | #define portINT_PRIORITY_LEVEL2 ( 0x0002U ) /* Level 2 */ 99 | #define portINT_PRIORITY_LEVEL3 ( 0x0003U ) /* Level 3 */ 100 | #define portINT_PRIORITY_LEVEL4 ( 0x0004U ) /* Level 4 */ 101 | #define portINT_PRIORITY_LEVEL5 ( 0x0005U ) /* Level 5 */ 102 | #define portINT_PRIORITY_LEVEL6 ( 0x0006U ) /* Level 6 */ 103 | #define portINT_PRIORITY_LEVEL7 ( 0x0007U ) /* Level 7 */ 104 | #define portINT_PRIORITY_LEVEL8 ( 0x0008U ) /* Level 8 */ 105 | #define portINT_PRIORITY_LEVEL9 ( 0x0009U ) /* Level 9 */ 106 | #define portINT_PRIORITY_LEVEL10 ( 0x000AU ) /* Level 10 */ 107 | #define portINT_PRIORITY_LEVEL11 ( 0x000BU ) /* Level 11 */ 108 | #define portINT_PRIORITY_LEVEL12 ( 0x000CU ) /* Level 12 */ 109 | #define portINT_PRIORITY_LEVEL13 ( 0x000DU ) /* Level 13 */ 110 | #define portINT_PRIORITY_LEVEL14 ( 0x000EU ) /* Level 14 */ 111 | #define portINT_PRIORITY_LOWEST ( 0x000FU ) /* Level 15 (lowest) */ 112 | 113 | /* Determine the descending of the stack from high address to address */ 114 | #define portSTACK_GROWTH ( -1 ) 115 | 116 | /* Determine the time (in milliseconds) corresponding to each tick */ 117 | #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) 118 | 119 | /* It is a multiple of 4 (the two lower-order bits of the address = 0), 120 | * otherwise it will cause MAE (Misaligned Exception) according to the manual */ 121 | #define portBYTE_ALIGNMENT ( 4 ) 122 | 123 | /* Interrupt control macros. */ 124 | 125 | #define portENABLE_INTERRUPTS() __EI() /* Macro to enable all maskable interrupts. */ 126 | #define portDISABLE_INTERRUPTS() __DI() /* Macro to disable all maskable interrupts. */ 127 | #define taskENABLE_INTERRUPTS() portENABLE_INTERRUPTS() 128 | #define taskDISABLE_INTERRUPTS() portDISABLE_INTERRUPTS() 129 | 130 | /* SMP build which means configNUM_CORES is relevant */ 131 | #define portSUPPORT_SMP 1 132 | 133 | #ifndef configNUMBER_OF_CORES 134 | #define configNUMBER_OF_CORES 1 135 | #endif 136 | 137 | /*-----------------------------------------------------------*/ 138 | /* Scheduler utilities */ 139 | 140 | /* Called at the end of an ISR that can cause a context switch */ 141 | extern void vPortSetSwitch( BaseType_t xSwitchRequired ); 142 | 143 | #define portEND_SWITCHING_ISR( x ) vPortSetSwitch( x ) 144 | 145 | #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) 146 | 147 | /* Use to transfer control from one task to perform other tasks of higher priority */ 148 | #define portYIELD() vPortYield() 149 | 150 | /* Return the core ID on which the code is running. */ 151 | extern BaseType_t xPortGET_CORE_ID( void ); 152 | 153 | #define portGET_CORE_ID() xPortGET_CORE_ID() 154 | #define coreid xPortGET_CORE_ID() 155 | 156 | #if ( configNUMBER_OF_CORES > 1 ) 157 | 158 | /* Handler for inter-processos interrupt in second cores. The interrupt is 159 | * triggered by portYIELD_CORE(). vTaskSwitchContext() is invoked to switch tasks */ 160 | extern void vPortIPIHander( void ); 161 | 162 | /* Request the core ID x to yield. */ 163 | extern void vPortYieldCore( uint32_t coreID ); 164 | 165 | #define portYIELD_CORE( x ) vPortYieldCore( x ) 166 | 167 | #define portENTER_CRITICAL_FROM_ISR() vTaskEnterCriticalFromISR() 168 | #define portEXIT_CRITICAL_FROM_ISR( x ) vTaskExitCriticalFromISR( x ) 169 | 170 | #endif /* if ( configNUMBER_OF_CORES > 1 ) */ 171 | 172 | #if ( configNUMBER_OF_CORES == 1 ) 173 | #define portGET_ISR_LOCK( xCoreID ) 174 | #define portRELEASE_ISR_LOCK( xCoreID ) 175 | #define portGET_TASK_LOCK( xCoreID ) 176 | #define portRELEASE_TASK_LOCK( xCoreID ) 177 | #else 178 | extern void vPortRecursiveLockAcquire( BaseType_t xCoreID, BaseType_t xFromIsr ); 179 | extern void vPortRecursiveLockRelease( BaseType_t xCoreID, BaseType_t xFromIsr ); 180 | 181 | #define portGET_ISR_LOCK( xCoreID ) vPortRecursiveLockAcquire( ( xCoreID ), pdTRUE ) 182 | #define portRELEASE_ISR_LOCK( xCoreID ) vPortRecursiveLockRelease( ( xCoreID ), pdTRUE ) 183 | #define portGET_TASK_LOCK( xCoreID ) vPortRecursiveLockAcquire( ( xCoreID ), pdFALSE ) 184 | #define portRELEASE_TASK_LOCK( xCoreID ) vPortRecursiveLockRelease( ( xCoreID ), pdFALSE ) 185 | #endif /* if ( configNUMBER_OF_CORES == 1 ) */ 186 | 187 | /*-----------------------------------------------------------*/ 188 | /* Critical section management. */ 189 | 190 | /* The critical nesting functions defined within tasks.c */ 191 | 192 | extern void vTaskEnterCritical( void ); 193 | extern void vTaskExitCritical( void ); 194 | 195 | /* Macro to mark the start of a critical code region */ 196 | #define portENTER_CRITICAL() vTaskEnterCritical() 197 | 198 | /* Macro to mark the end of a critical code region */ 199 | #define portEXIT_CRITICAL() vTaskExitCritical() 200 | 201 | /*-----------------------------------------------------------*/ 202 | /* Task function macros as described on the FreeRTOS.org WEB site. */ 203 | 204 | #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) 205 | #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) 206 | 207 | /*-----------------------------------------------------------*/ 208 | 209 | /*-----------------------------------------------------------*/ 210 | /* Macros to set and clear the interrupt mask. */ 211 | extern portLONG xPortSetInterruptMask( void ); 212 | extern void vPortClearInterruptMask( portLONG ); 213 | 214 | #define portSET_INTERRUPT_MASK() xPortSetInterruptMask() 215 | #define portCLEAR_INTERRUPT_MASK( x ) vPortClearInterruptMask( ( x ) ) 216 | #define portSET_INTERRUPT_MASK_FROM_ISR() xPortSetInterruptMask() 217 | #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vPortClearInterruptMask( ( x ) ) 218 | 219 | #ifdef __cplusplus 220 | } 221 | #endif 222 | #endif /* PORTMACRO_H */ 223 | -------------------------------------------------------------------------------- /LICENSE: -------------------------------------------------------------------------------- 1 | This repository contains multiple directories, each individually licensed. Please see the LICENSE file in each directory. 2 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | ## FreeRTOS Partner Supported Ports 2 | 3 | This repository contains FreeRTOS ports supported by FreeRTOS partners. For a 4 | partner supported FreeRTOS port: 5 | 6 | * The code has not been reviewed by the FreeRTOS team. 7 | * FreeRTOS team has not verified the tests results but tests exist and are 8 | reported to be successful by the partner. 9 | * Customer queries as well as bugs are addressed by the partner. 10 | 11 | A new FreeRTOS port can be directly contributed by a partner. Follow the steps 12 | below to contribute a FreeRTOS port to this repository: 13 | 14 | 1. Write the FreeRTOS port for your Compiler and Architecture. 15 | 2. Create a project in the [FreeRTOS Partner Supported Demos Repository](https://github.com/FreeRTOS/FreeRTOS-Partner-Supported-Demos/tree/main) 16 | for your hardware for running tests as mentioned [here](https://github.com/FreeRTOS/FreeRTOS/blob/main/FreeRTOS/Demo/ThirdParty/Template/README.md). 17 | 3. Make sure all the tests pass. Add the test results in the Pull Request description. 18 | 4. Add a README file with the following information: 19 | 1. How to use this port? 20 | 2. Link to the test project created in Step 2. 21 | 3. Any other relevant information. 22 | 5. Raise a PR to merge the FreeRTOS port. 23 | 6. Raise another PR to merge the test project in the [FreeRTOS-Partner-Supported-Demos Repository](https://github.com/FreeRTOS/FreeRTOS/tree/main/FreeRTOS/Demo/ThirdParty/Community-Supported). 24 | 25 | 26 | ## License 27 | 28 | This repository contains multiple directories, each individually licensed. Please see the LICENSE file in each directory. 29 | -------------------------------------------------------------------------------- /TI/CORTEX_A53_64-BIT_TI_AM64_SMP/LICENSE: -------------------------------------------------------------------------------- 1 | FreeRTOS Kernel 2 | Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. 3 | 4 | SPDX-License-Identifier: MIT 5 | 6 | Permission is hereby granted, free of charge, to any person obtaining a copy of 7 | this software and associated documentation files (the "Software"), to deal in 8 | the Software without restriction, including without limitation the rights to 9 | use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of 10 | the Software, and to permit persons to whom the Software is furnished to do so, 11 | subject to the following conditions: 12 | 13 | The above copyright notice and this permission notice shall be included in all 14 | copies or substantial portions of the Software. 15 | 16 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS 18 | FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR 19 | COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER 20 | IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 21 | CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 22 | 23 | https://www.FreeRTOS.org 24 | https://github.com/FreeRTOS 25 | 26 | 27 | 28 | Copyright (C) 2018-2022 Texas Instruments Incorporated 29 | 30 | Redistribution and use in source and binary forms, with or without 31 | modification, are permitted provided that the following conditions 32 | are met: 33 | 34 | Redistributions of source code must retain the above copyright 35 | notice, this list of conditions and the following disclaimer. 36 | 37 | Redistributions in binary form must reproduce the above copyright 38 | notice, this list of conditions and the following disclaimer in the 39 | documentation and/or other materials provided with the 40 | distribution. 41 | 42 | Neither the name of Texas Instruments Incorporated nor the names of 43 | its contributors may be used to endorse or promote products derived 44 | from this software without specific prior written permission. 45 | 46 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 47 | "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 48 | LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 49 | A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 50 | OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 51 | SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 52 | LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 53 | DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 54 | THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 55 | (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 56 | OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 57 | -------------------------------------------------------------------------------- /TI/CORTEX_A53_64-BIT_TI_AM64_SMP/portmacro.h: -------------------------------------------------------------------------------- 1 | /* 2 | * FreeRTOS Kernel V10.4.3 3 | * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. 4 | * 5 | * Permission is hereby granted, free of charge, to any person obtaining a copy of 6 | * this software and associated documentation files (the "Software"), to deal in 7 | * the Software without restriction, including without limitation the rights to 8 | * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of 9 | * the Software, and to permit persons to whom the Software is furnished to do so, 10 | * subject to the following conditions: 11 | * 12 | * The above copyright notice and this permission notice shall be included in all 13 | * copies or substantial portions of the Software. 14 | * 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS 17 | * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR 18 | * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER 19 | * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 20 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 21 | * 22 | * https://www.FreeRTOS.org 23 | * https://github.com/FreeRTOS 24 | * 25 | * 1 tab == 4 spaces! 26 | */ 27 | /* 28 | * Copyright (C) 2018-2022 Texas Instruments Incorporated 29 | * 30 | * Redistribution and use in source and binary forms, with or without 31 | * modification, are permitted provided that the following conditions 32 | * are met: 33 | * 34 | * Redistributions of source code must retain the above copyright 35 | * notice, this list of conditions and the following disclaimer. 36 | * 37 | * Redistributions in binary form must reproduce the above copyright 38 | * notice, this list of conditions and the following disclaimer in the 39 | * documentation and/or other materials provided with the 40 | * distribution. 41 | * 42 | * Neither the name of Texas Instruments Incorporated nor the names of 43 | * its contributors may be used to endorse or promote products derived 44 | * from this software without specific prior written permission. 45 | * 46 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 47 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 48 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 49 | * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 50 | * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 51 | * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 52 | * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 53 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 54 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 55 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 56 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 57 | */ 58 | 59 | #ifndef PORTMACRO_H 60 | #define PORTMACRO_H 61 | 62 | #ifdef __cplusplus 63 | extern "C" { 64 | #endif 65 | 66 | #include 67 | #include 68 | #include 69 | 70 | /*----------------------------------------------------------- 71 | * Port specific definitions. 72 | * 73 | * The settings in this file configure FreeRTOS correctly for the given hardware 74 | * and compiler. 75 | * 76 | * These settings should not be altered. 77 | *----------------------------------------------------------- 78 | */ 79 | 80 | /* Type definitions. */ 81 | #define portCHAR char 82 | #define portFLOAT float 83 | #define portDOUBLE double 84 | #define portLONG long 85 | #define portSHORT short 86 | #define portSTACK_TYPE size_t 87 | #define portBASE_TYPE long 88 | 89 | typedef portSTACK_TYPE StackType_t; 90 | typedef portBASE_TYPE BaseType_t; 91 | typedef uint64_t UBaseType_t; 92 | 93 | typedef uint32_t TickType_t; 94 | #define portMAX_DELAY ( ( TickType_t ) 0xffffffff ) 95 | 96 | /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do 97 | not need to be guarded with a critical section. */ 98 | #define portTICK_TYPE_IS_ATOMIC 1 99 | 100 | /* Hardware specifics. */ 101 | #define portSTACK_GROWTH ( -1 ) 102 | #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) 103 | #define portBYTE_ALIGNMENT 16 104 | #define portPOINTER_SIZE_TYPE uint64_t 105 | #define portCRITICAL_NESTING_IN_TCB 1 106 | 107 | /* Task utilities. */ 108 | 109 | extern uint64_t ullPortYieldRequired[]; 110 | /* Called at the end of an ISR that can cause a context switch. */ 111 | #define portEND_SWITCHING_ISR( xSwitchRequired ) \ 112 | { \ 113 | \ 114 | if( xSwitchRequired != pdFALSE ) \ 115 | { \ 116 | ullPortYieldRequired[portGET_CORE_ID()] = pdTRUE; \ 117 | } \ 118 | } 119 | 120 | #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) 121 | #define portYIELD() __asm volatile ( "SVC 0" ::: "memory" ) 122 | 123 | /*----------------------------------------------------------- 124 | * Critical section control 125 | *----------------------------------------------------------*/ 126 | 127 | extern void vTaskEnterCritical( void ); 128 | extern void vTaskExitCritical( void ); 129 | 130 | #define portDISABLE_INTERRUPTS() HwiP_disable() 131 | #define portENABLE_INTERRUPTS() HwiP_enable() 132 | #define portENTER_CRITICAL() vTaskEnterCritical(); 133 | #define portEXIT_CRITICAL() vTaskExitCritical(); 134 | #define portSET_INTERRUPT_MASK_FROM_ISR() ({ \ 135 | uint64_t x = HwiP_disable(); \ 136 | vTaskEnterCritical(); \ 137 | x; \ 138 | }) 139 | 140 | #define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) ({ \ 141 | vTaskExitCritical(); \ 142 | HwiP_restore(x); \ 143 | }) 144 | 145 | /* Task function macros as described on the FreeRTOS.org WEB site. These are 146 | not required for this port but included in case common demo code that uses these 147 | macros is used. */ 148 | #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) 149 | #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) 150 | 151 | /* Any task that uses the floating point unit MUST call vPortTaskUsesFPU() 152 | before any floating point instructions are executed. */ 153 | void vPortTaskUsesFPU( void ); 154 | #define portTASK_USES_FLOATING_POINT() vPortTaskUsesFPU() 155 | 156 | /* Architecture specific optimisations. */ 157 | #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION 158 | #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 159 | #endif 160 | 161 | #if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 162 | 163 | /* Store/clear the ready priorities in a bit map. */ 164 | #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) 165 | #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) 166 | 167 | #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31 - __builtin_clz( uxReadyPriorities ) ) 168 | 169 | #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ 170 | 171 | #define portNOP() __asm volatile( "NOP" ) 172 | #define portINLINE __inline 173 | #define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" ) 174 | 175 | /* port for SMP */ 176 | #define portGET_CORE_ID() Armv8_getCoreId() 177 | #define portRESTORE_INTERRUPTS( ulState ) HwiP_restore ( ulState ) 178 | #define portCHECK_IF_IN_ISR() HwiP_inISR() 179 | 180 | /*----------------------------------------------------------- 181 | * Critical section locks 182 | *----------------------------------------------------------*/ 183 | 184 | #define ISR_LOCK (0u) 185 | #define TASK_LOCK (1u) 186 | 187 | #define portRTOS_LOCK_COUNT 2 188 | #define portMAX_CORE_COUNT 2 189 | 190 | #define portRELEASE_ISR_LOCK( xCoreID ) vPortRecursiveLock( ( xCoreID ), ISR_LOCK, pdFALSE ) 191 | #define portGET_ISR_LOCK( xCoreID ) vPortRecursiveLock( ( xCoreID ), ISR_LOCK, pdTRUE ) 192 | 193 | #define portRELEASE_TASK_LOCK( xCoreID ) vPortRecursiveLock( ( xCoreID ), TASK_LOCK, pdFALSE ) 194 | #define portGET_TASK_LOCK( xCoreID ) vPortRecursiveLock( ( xCoreID ), TASK_LOCK, pdTRUE ) 195 | 196 | /* Interrupt number to interrupt a core for task yield */ 197 | #define YIELD_CORE_INTERRUPT_NO (0U) 198 | 199 | extern int32_t Signal_coreIntr( CSL_gic500_gicrRegs *pGic500GicrRegs, uint32_t coreId, uint32_t intrNum ); 200 | 201 | #define portYIELD_CORE( xCoreID ) do { \ 202 | Signal_coreIntr((CSL_gic500_gicrRegs *) ( HWIP_GIC_BASE_ADDR + \ 203 | CSL_GIC500_GICR_CORE_CONTROL_CTLR(0U)), xCoreID, YIELD_CORE_INTERRUPT_NO); \ 204 | }while(0); 205 | 206 | 207 | uint64_t Get_64(volatile uint64_t* x); 208 | void Set_64(volatile uint64_t* x, uint64_t value); 209 | 210 | /* Which core owns the lock */ 211 | volatile uint64_t ucOwnedByCore[ portMAX_CORE_COUNT ]; 212 | /* Lock count a core owns */ 213 | volatile uint64_t ucRecursionCountByLock[ portRTOS_LOCK_COUNT ]; 214 | 215 | /* Index 0 is used for ISR lock and Index 1 is used for task lock */ 216 | uint32_t GateWord[ portRTOS_LOCK_COUNT ]; 217 | 218 | int32_t GateSmp_tryLock(uint32_t* gateWord); 219 | void GateSmp_unlock(uint32_t* gateWord); 220 | 221 | static inline void vPortRecursiveLock(BaseType_t xCoreID, uint32_t ulLockNum, BaseType_t uxAcquire) 222 | { 223 | uint32_t ulLockBit = 1u << ulLockNum; 224 | 225 | /* Lock acquire */ 226 | if (uxAcquire) 227 | { 228 | 229 | /* Check if spinlock is available */ 230 | /* If spinlock is not available check if the core owns the lock */ 231 | /* If the core owns the lock wait increment the lock count by the core */ 232 | /* If core does not own the lock wait for the spinlock */ 233 | if( GateSmp_tryLock( &GateWord[ulLockNum] ) != 0) 234 | { 235 | /* Check if the core owns the spinlock */ 236 | if( Get_64(&ucOwnedByCore[xCoreID]) & ulLockBit ) 237 | { 238 | configASSERT( Get_64(&ucRecursionCountByLock[ulLockNum]) != 255u); 239 | Set_64(&ucRecursionCountByLock[ulLockNum], (Get_64(&ucRecursionCountByLock[ulLockNum])+1)); 240 | return; 241 | } 242 | 243 | /* Preload the gate word into the cache */ 244 | uint32_t dummy = GateWord[ulLockNum]; 245 | dummy++; 246 | 247 | /* Wait for spinlock */ 248 | while( GateSmp_tryLock(&GateWord[ulLockNum]) != 0); 249 | } 250 | 251 | /* Add barrier to ensure lock is taken before we proceed */ 252 | __asm__ __volatile__ ( 253 | "dmb sy" 254 | ::: "memory" 255 | ); 256 | 257 | /* Assert the lock count is 0 when the spinlock is free and is acquired */ 258 | configASSERT(Get_64(&ucRecursionCountByLock[ulLockNum]) == 0); 259 | 260 | /* Set lock count as 1 */ 261 | Set_64(&ucRecursionCountByLock[ulLockNum], 1); 262 | /* Set ucOwnedByCore */ 263 | Set_64(&ucOwnedByCore[xCoreID], (Get_64(&ucOwnedByCore[xCoreID]) | ulLockBit)); 264 | } 265 | /* Lock release */ 266 | else 267 | { 268 | /* Assert the lock is not free already */ 269 | configASSERT( (Get_64(&ucOwnedByCore[xCoreID]) & ulLockBit) != 0 ); 270 | configASSERT( Get_64(&ucRecursionCountByLock[ulLockNum]) != 0 ); 271 | 272 | /* Reduce ucRecursionCountByLock by 1 */ 273 | Set_64(&ucRecursionCountByLock[ulLockNum], (Get_64(&ucRecursionCountByLock[ulLockNum]) - 1) ); 274 | 275 | if( !Get_64(&ucRecursionCountByLock[ulLockNum]) ) 276 | { 277 | Set_64(&ucOwnedByCore[xCoreID], (Get_64(&ucOwnedByCore[xCoreID]) & ~ulLockBit)); 278 | GateSmp_unlock(&GateWord[ulLockNum]); 279 | /* Add barrier to ensure lock is taken before we proceed */ 280 | __asm__ __volatile__ ( 281 | "dmb sy" 282 | ::: "memory" 283 | ); 284 | } 285 | } 286 | } 287 | 288 | #ifdef __cplusplus 289 | } /* extern C */ 290 | #endif 291 | 292 | #endif /* PORTMACRO_H */ 293 | 294 | -------------------------------------------------------------------------------- /Tasking/AURIX_TC3xx/LICENSE: -------------------------------------------------------------------------------- 1 | Copyright (c) 2023 Infineon Technologies AG. All rights reserved. 2 | IMPORTANT NOTICE 3 | Use of this file is subject to the terms of use agreed between (i) you or 4 | the company in which ordinary course of business you are acting and (ii) 5 | Infineon Technologies AG or its licensees. If and as long as no such 6 | terms of use are agreed, use of this file is subject to following: 7 | Boost Software License - Version 1.0 - August 17th, 2003 8 | Permission is hereby granted, free of charge, to any person or 9 | organization obtaining a copy of the software and accompanying 10 | documentation covered by this license (the "Software") to use, reproduce, 11 | display, distribute, execute, and transmit the Software, and to prepare 12 | derivative works of the Software, and to permit third-parties to whom the 13 | Software is furnished to do so, all subject to the following: 14 | The copyright notices in the Software and this entire statement, including 15 | the above license grant, this restriction and the following disclaimer, must 16 | be included in all copies of the Software, in whole or in part, and all 17 | derivative works of the Software, unless such copies or derivative works are 18 | solely in the form of machine-executable object code generated by a source 19 | language processor. 20 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 21 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 22 | FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT 23 | SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE 24 | FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE, 25 | ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 26 | DEALINGS IN THE SOFTWARE. 27 | 28 | SPDX-License-Identifier: BSL-1.0 29 | -------------------------------------------------------------------------------- /Tasking/AURIX_TC3xx/portmacro.h: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2023 Infineon Technologies AG. All rights reserved. 3 | * 4 | * 5 | * IMPORTANT NOTICE 6 | * 7 | * 8 | * Use of this file is subject to the terms of use agreed between (i) you or 9 | * the company in which ordinary course of business you are acting and (ii) 10 | * Infineon Technologies AG or its licensees. If and as long as no such 11 | * terms of use are agreed, use of this file is subject to following: 12 | * 13 | * Boost Software License - Version 1.0 - August 17th, 2003 14 | * 15 | * Permission is hereby granted, free of charge, to any person or 16 | * organization obtaining a copy of the software and accompanying 17 | * documentation covered by this license (the "Software") to use, reproduce, 18 | * display, distribute, execute, and transmit the Software, and to prepare 19 | * derivative works of the Software, and to permit third-parties to whom the 20 | * Software is furnished to do so, all subject to the following: 21 | * 22 | * The copyright notices in the Software and this entire statement, including 23 | * the above license grant, this restriction and the following disclaimer, must 24 | * be included in all copies of the Software, in whole or in part, and all 25 | * derivative works of the Software, unless such copies or derivative works are 26 | * solely in the form of machine-executable object code generated by a source 27 | * language processor. 28 | * 29 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 30 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 31 | * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT 32 | * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE 33 | * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE, 34 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 35 | * DEALINGS IN THE SOFTWARE. 36 | * 37 | * SPDX-License-Identifier: BSL-1.0 38 | */ 39 | 40 | #ifndef PORTMACRO_H 41 | #define PORTMACRO_H 42 | 43 | #ifdef __cplusplus 44 | extern "C" 45 | #endif 46 | 47 | #include "FreeRTOSConfig.h" 48 | 49 | #define portCPU_PSW 0xFE04 50 | #define portCPU_PSW_IS_OFF ( 9 ) 51 | #define portCPU_PSW_CSC_MSK ( 0x7F ) 52 | #define portCPU_ICR 0xFE2C 53 | #define portCPU_ICR_CCPN_OFF ( 0 ) 54 | #define portCPU_ICR_CCPN_MSK ( 0x000000FFUL ) 55 | #define portCPU_FCX 0xFE38 56 | #define portCPU_PCXI 0xFE00 57 | #define portCPU_CORE_ID 0xFE1C 58 | 59 | /* Register defintions */ 60 | #define portSRC_SRCR_SRPN_OFF 0 61 | #define portSRC_SRCR_SRE_OFF 10 62 | #define portSRC_SRCR_TOS_OFF 11 63 | #define portSRC_SRCR_SRR_OFF 24 64 | #define portSRC_SRCR_SETR_OFF 26 65 | 66 | /* Type definitions. */ 67 | #define portCHAR char 68 | #define portSHORT short 69 | #define portLONG long 70 | #define portFLOAT float 71 | #define portDOUBLE double 72 | #define portSTACK_TYPE uint32_t 73 | #define portBASE_TYPE long 74 | #define portPOINTER_SIZE_TYPE uintptr_t 75 | 76 | typedef portSTACK_TYPE StackType_t; 77 | typedef long BaseType_t; 78 | typedef unsigned long UBaseType_t; 79 | 80 | #if ( configUSE_16_BIT_TICKS == 1 ) 81 | typedef unsigned short TickType_t; 82 | #define portMAX_DELAY ( TickType_t ) 0xffff 83 | #else 84 | typedef unsigned int TickType_t; 85 | #define portMAX_DELAY ( TickType_t ) 0xffffffffUL 86 | #endif 87 | 88 | /* FreeRTOS parameters */ 89 | #define portTICK_TYPE_IS_ATOMIC 1 90 | #define portSTACK_GROWTH ( -1 ) 91 | #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) 92 | #define portBYTE_ALIGNMENT 8 93 | #define portCRITICAL_NESTING_IN_TCB 0 94 | 95 | /* Attributes */ 96 | #define portDONT_DISCARD __attribute__( ( used ) ) 97 | #define portNORETURN __attribute__( ( noreturn ) ) 98 | 99 | /* Instructions */ 100 | #define portNOP() __nop() 101 | #define portMEMORY_BARRIER() __dsync() 102 | 103 | /* Critical section management */ 104 | extern void vPortEnterCritical( void ); 105 | extern void vPortExitCritical( void ); 106 | #define portENTER_CRITICAL() vPortEnterCritical() 107 | #define portEXIT_CRITICAL() vPortExitCritical() 108 | #define portENABLE_INTERRUPTS() vPortSetCCPN( 0 ); 109 | #define portDISABLE_INTERRUPTS() vPortSetCCPN( configMAX_API_CALL_INTERRUPT_PRIORITY ) 110 | #define portASSERT_IF_IN_ISR() configASSERT( ( __mfcr( portCPU_PSW ) & ( 1 << portCPU_PSW_IS_OFF ) ) == 0 ) 111 | #define portCLEAR_INTERRUPT_MASK_FROM_ISR( ulSavedMaskValue ) vPortSetICR( ulSavedMaskValue ) 112 | #define portSET_INTERRUPT_MASK_FROM_ISR() xPortSetCCPN( configMAX_API_CALL_INTERRUPT_PRIORITY ) 113 | 114 | 115 | #ifndef configYIELD_SYSCALL_ID 116 | #define configYIELD_SYSCALL_ID 0 117 | #endif 118 | 119 | #define portYIELD() __syscall( configYIELD_SYSCALL_ID ) 120 | #define portYIELD_FROM_ISR( xHigherPriorityTaskWoken ) \ 121 | { \ 122 | const uint32_t xTrigger = ( ( *configCONTEXT_SRC >> portSRC_SRCR_SRR_OFF ) & 0x1 ) != 1 && ( xHigherPriorityTaskWoken != 0 ); \ 123 | *configCONTEXT_SRC |= ( xTrigger << portSRC_SRCR_SETR_OFF ); \ 124 | \ 125 | /* Wait until write request completes to trigger IRQ */ \ 126 | __dsync(); \ 127 | __isync(); \ 128 | } 129 | 130 | 131 | #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION 132 | #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 133 | #endif 134 | 135 | #if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 ) 136 | 137 | /* Check the configuration. */ 138 | #if ( configMAX_PRIORITIES > 32 ) 139 | #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice. 140 | #endif 141 | 142 | /* Store/clear the ready priorities in a bit map. */ 143 | #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) 144 | #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) 145 | 146 | #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( ( uint32_t ) __clz( ( uxReadyPriorities ) ) ) ) 147 | 148 | #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ 149 | 150 | /* Function prototypes */ 151 | #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) 152 | #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) 153 | 154 | /* TCB handling */ 155 | extern void vPortReclaimCSA( unsigned long ** pxTCB ); 156 | #define portCLEAN_UP_TCB( pxTCB ) vPortReclaimCSA( ( unsigned long ** ) ( pxTCB ) ) 157 | 158 | 159 | /* ICR & CCPN modifying functions to enable and disable interrupts. 160 | * Only interrupts with a priority lower than 161 | */ 162 | static void __attribute__( ( used, always_inline ) ) vPortSetCCPN( unsigned char ucCCPN ) 163 | { 164 | __disable(); 165 | __mtcr( portCPU_ICR, ( __mfcr( portCPU_ICR ) & ~portCPU_ICR_CCPN_MSK ) | ( ucCCPN & portCPU_ICR_CCPN_MSK ) ); 166 | __enable(); 167 | } 168 | 169 | static void __attribute__( ( used, always_inline ) ) vPortSetICR( portBASE_TYPE ulICR ) 170 | { 171 | __disable(); 172 | __mtcr( portCPU_ICR, ( unsigned int ) ulICR ); 173 | __enable(); 174 | } 175 | 176 | static portBASE_TYPE __attribute__( ( used, always_inline ) ) xPortSetCCPN( unsigned char ucCCPN ) 177 | { 178 | uint32_t xICR; 179 | 180 | __disable(); 181 | xICR = __mfcr( portCPU_ICR ); 182 | __mtcr( portCPU_ICR, ( xICR & ~portCPU_ICR_CCPN_MSK ) | ( ucCCPN & portCPU_ICR_CCPN_MSK ) ); 183 | __enable(); 184 | return ( portBASE_TYPE ) xICR; 185 | } 186 | 187 | #ifdef __cplusplus 188 | } 189 | #endif 190 | 191 | #endif /* PORTMACRO_H */ 192 | --------------------------------------------------------------------------------