├── CNN_Accelerator_Vivado_project ├── Accelerator.cache │ ├── sim │ │ └── ssm.db │ └── wt │ │ ├── project.wpc │ │ └── xsim.wdf ├── Accelerator.gen │ └── sources_1 │ │ ├── bd │ │ ├── Accelerator │ │ │ ├── Accelerator.bda │ │ │ ├── Accelerator.bxml │ │ │ └── ip │ │ │ │ └── Accelerator_processing_system7_0_0 │ │ │ │ └── Accelerator_processing_system7_0_0.xml │ │ ├── Accelerator_block_design │ │ │ ├── Accelerator_block_design.bda │ │ │ ├── Accelerator_block_design.bxml │ │ │ ├── hdl │ │ │ │ └── Accelerator_block_design_wrapper.v │ │ │ └── ip │ │ │ │ ├── Accelerator_block_design_CNN_Control_1_0 │ │ │ │ └── Accelerator_block_design_CNN_Control_1_0.xml │ │ │ │ ├── Accelerator_block_design_INACT_DATA_FIFO_0 │ │ │ │ └── Accelerator_block_design_INACT_DATA_FIFO_0.xml │ │ │ │ ├── Accelerator_block_design_Windows_Data_Convert_0_5 │ │ │ │ └── Accelerator_block_design_Windows_Data_Convert_0_5.xml │ │ │ │ ├── Accelerator_block_design_auto_ds_0 │ │ │ │ └── Accelerator_block_design_auto_ds_0.xml │ │ │ │ ├── Accelerator_block_design_auto_ds_1 │ │ │ │ └── Accelerator_block_design_auto_ds_1.xml │ │ │ │ ├── Accelerator_block_design_auto_pc_0 │ │ │ │ └── Accelerator_block_design_auto_pc_0.xml │ │ │ │ ├── Accelerator_block_design_auto_pc_1 │ │ │ │ └── Accelerator_block_design_auto_pc_1.xml │ │ │ │ ├── Accelerator_block_design_auto_us_0 │ │ │ │ └── Accelerator_block_design_auto_us_0.xml │ │ │ │ ├── Accelerator_block_design_axi_dma_0_0 │ │ │ │ └── Accelerator_block_design_axi_dma_0_0.xml │ │ │ │ ├── Accelerator_block_design_axi_dma_0_1 │ │ │ │ └── Accelerator_block_design_axi_dma_0_1.xml │ │ │ │ ├── Accelerator_block_design_axi_dma_0_2 │ │ │ │ └── Accelerator_block_design_axi_dma_0_2.xml │ │ │ │ ├── Accelerator_block_design_axi_dma_0_3 │ │ │ │ └── Accelerator_block_design_axi_dma_0_3.xml │ │ │ │ ├── Accelerator_block_design_axi_gpio_0_0 │ │ │ │ └── Accelerator_block_design_axi_gpio_0_0.xml │ │ │ │ ├── Accelerator_block_design_axi_intc_0_0 │ │ │ │ └── Accelerator_block_design_axi_intc_0_0.xml │ │ │ │ ├── Accelerator_block_design_axi_interconnect_0_0 │ │ │ │ └── Accelerator_block_design_axi_interconnect_0_0.xml │ │ │ │ ├── Accelerator_block_design_axi_interconnect_0_1 │ │ │ │ └── Accelerator_block_design_axi_interconnect_0_1.xml │ │ │ │ ├── Accelerator_block_design_axis_data_fifo_0_0 │ │ │ │ └── Accelerator_block_design_axis_data_fifo_0_0.xml │ │ │ │ ├── Accelerator_block_design_axis_data_fifo_0_1 │ │ │ │ └── Accelerator_block_design_axis_data_fifo_0_1.xml │ │ │ │ ├── Accelerator_block_design_axis_data_fifo_0_2 │ │ │ │ └── Accelerator_block_design_axis_data_fifo_0_2.xml │ │ │ │ ├── Accelerator_block_design_axis_data_fifo_1_0 │ │ │ │ └── Accelerator_block_design_axis_data_fifo_1_0.xml │ │ │ │ ├── Accelerator_block_design_proc_sys_reset_0_0 │ │ │ │ └── Accelerator_block_design_proc_sys_reset_0_0.xml │ │ │ │ ├── Accelerator_block_design_processing_system7_0_0 │ │ │ │ ├── Accelerator_block_design_processing_system7_0_0.xml │ │ │ │ └── ps7_parameters.xml │ │ │ │ ├── Accelerator_block_design_s00_data_fifo_0 │ │ │ │ └── Accelerator_block_design_s00_data_fifo_0.xml │ │ │ │ ├── Accelerator_block_design_xbar_0 │ │ │ │ └── Accelerator_block_design_xbar_0.xml │ │ │ │ ├── Accelerator_block_design_xbar_1 │ │ │ │ └── Accelerator_block_design_xbar_1.xml │ │ │ │ └── Accelerator_block_design_xlconcat_0_0 │ │ │ │ └── Accelerator_block_design_xlconcat_0_0.xml │ │ ├── CNN_Module │ │ │ ├── CNN_Module.bda │ │ │ ├── CNN_Module.bxml │ │ │ ├── CNN_Module_ooc.xdc │ │ │ ├── hdl │ │ │ │ └── CNN_Module_wrapper.v │ │ │ ├── hw_handoff │ │ │ │ └── CNN_Module.hwh │ │ │ ├── ip │ │ │ │ ├── CNN_Module_CNN_Control_1_0 │ │ │ │ │ ├── CNN_Module_CNN_Control_1_0.xml │ │ │ │ │ └── sim │ │ │ │ │ │ └── CNN_Module_CNN_Control_1_0.v │ │ │ │ ├── CNN_Module_INACT_DATA_FIFO_0 │ │ │ │ │ ├── CNN_Module_INACT_DATA_FIFO_0.xml │ │ │ │ │ └── sim │ │ │ │ │ │ └── CNN_Module_INACT_DATA_FIFO_0.v │ │ │ │ ├── CNN_Module_PICTURE_DATA_FIFO_0 │ │ │ │ │ ├── CNN_Module_PICTURE_DATA_FIFO_0.xml │ │ │ │ │ └── sim │ │ │ │ │ │ └── CNN_Module_PICTURE_DATA_FIFO_0.v │ │ │ │ ├── CNN_Module_RESULT_DATA_FIFO1_0 │ │ │ │ │ ├── CNN_Module_RESULT_DATA_FIFO1_0.xml │ │ │ │ │ └── sim │ │ │ │ │ │ └── CNN_Module_RESULT_DATA_FIFO1_0.v │ │ │ │ ├── CNN_Module_WEIGHT_CONV_ACT_FULLCON_FIFO_0 │ │ │ │ │ ├── CNN_Module_WEIGHT_CONV_ACT_FULLCON_FIFO_0.xml │ │ │ │ │ └── sim │ │ │ │ │ │ └── CNN_Module_WEIGHT_CONV_ACT_FULLCON_FIFO_0.v │ │ │ │ ├── CNN_Module_WEIGHT_FULLCON_FIFO_0 │ │ │ │ │ ├── CNN_Module_WEIGHT_FULLCON_FIFO_0.xml │ │ │ │ │ └── sim │ │ │ │ │ │ └── CNN_Module_WEIGHT_FULLCON_FIFO_0.v │ │ │ │ └── CNN_Module_Windows_Data_Convert_0_0 │ │ │ │ │ ├── CNN_Module_Windows_Data_Convert_0_0.xml │ │ │ │ │ └── sim │ │ │ │ │ └── CNN_Module_Windows_Data_Convert_0_0.v │ │ │ ├── ipshared │ │ │ │ ├── 8713 │ │ │ │ │ └── hdl │ │ │ │ │ │ ├── axis_infrastructure_v1_1_0.vh │ │ │ │ │ │ └── axis_infrastructure_v1_1_vl_rfs.v │ │ │ │ └── 0bd2 │ │ │ │ │ └── hdl │ │ │ │ │ └── axis_data_fifo_v2_0_vl_rfs.v │ │ │ ├── sim │ │ │ │ ├── CNN_Module.protoinst │ │ │ │ └── CNN_Module.v │ │ │ └── synth │ │ │ │ ├── CNN_Module.hwdef │ │ │ │ └── CNN_Module.v │ │ ├── Windows_data_Test │ │ │ ├── Windows_data_Test.bda │ │ │ ├── Windows_data_Test.bxml │ │ │ ├── hdl │ │ │ │ └── Windows_data_Test_wrapper.v │ │ │ └── ip │ │ │ │ ├── Windows_data_Test_INACT_DATA_FIFO_0 │ │ │ │ └── Windows_data_Test_INACT_DATA_FIFO_0.xml │ │ │ │ ├── Windows_data_Test_INACT_DATA_FIFO_1 │ │ │ │ └── Windows_data_Test_INACT_DATA_FIFO_1.xml │ │ │ │ ├── Windows_data_Test_Windows_Data_Convert_0_1 │ │ │ │ └── Windows_data_Test_Windows_Data_Convert_0_1.xml │ │ │ │ ├── Windows_data_Test_auto_pc_0 │ │ │ │ └── Windows_data_Test_auto_pc_0.xml │ │ │ │ ├── Windows_data_Test_auto_pc_1 │ │ │ │ └── Windows_data_Test_auto_pc_1.xml │ │ │ │ ├── Windows_data_Test_auto_pc_2 │ │ │ │ └── Windows_data_Test_auto_pc_2.xml │ │ │ │ ├── Windows_data_Test_auto_pc_3 │ │ │ │ └── Windows_data_Test_auto_pc_3.xml │ │ │ │ ├── Windows_data_Test_axi_dma_0_0 │ │ │ │ └── Windows_data_Test_axi_dma_0_0.xml │ │ │ │ ├── Windows_data_Test_axi_dma_1_0 │ │ │ │ └── Windows_data_Test_axi_dma_1_0.xml │ │ │ │ ├── Windows_data_Test_axi_interconnect_0_0 │ │ │ │ └── Windows_data_Test_axi_interconnect_0_0.xml │ │ │ │ ├── Windows_data_Test_axi_interconnect_1_0 │ │ │ │ └── Windows_data_Test_axi_interconnect_1_0.xml │ │ │ │ ├── Windows_data_Test_ila_0_0 │ │ │ │ └── Windows_data_Test_ila_0_0.xml │ │ │ │ ├── Windows_data_Test_ila_0_3 │ │ │ │ └── Windows_data_Test_ila_0_3.xml │ │ │ │ ├── Windows_data_Test_proc_sys_reset_0_0 │ │ │ │ └── Windows_data_Test_proc_sys_reset_0_0.xml │ │ │ │ ├── Windows_data_Test_processing_system7_0_1 │ │ │ │ ├── Windows_data_Test_processing_system7_0_1.xml │ │ │ │ └── ps7_parameters.xml │ │ │ │ ├── Windows_data_Test_xbar_0 │ │ │ │ └── Windows_data_Test_xbar_0.xml │ │ │ │ ├── Windows_data_Test_xbar_1 │ │ │ │ └── Windows_data_Test_xbar_1.xml │ │ │ │ └── Windows_data_Test_xlconcat_0_0 │ │ │ │ └── Windows_data_Test_xlconcat_0_0.xml │ │ └── mref │ │ │ ├── CNN_Accelerator │ │ │ ├── component.xml │ │ │ └── xgui │ │ │ │ └── CNN_Accelerator_v1_0.tcl │ │ │ ├── CNN_Control │ │ │ ├── component.xml │ │ │ └── xgui │ │ │ │ └── CNN_Control_v1_0.tcl │ │ │ ├── Conv_Array_Control │ │ │ ├── component.xml │ │ │ └── xgui │ │ │ │ └── Conv_Array_Control_v1_0.tcl │ │ │ ├── FullCon_PE_Control │ │ │ ├── component.xml │ │ │ └── xgui │ │ │ │ └── FullCon_PE_Control_v1_0.tcl │ │ │ ├── Pooling_Array_Control │ │ │ ├── component.xml │ │ │ └── xgui │ │ │ │ └── Pooling_Array_Control_v1_0.tcl │ │ │ ├── Relu_Array_Control │ │ │ ├── component.xml │ │ │ └── xgui │ │ │ │ └── Relu_Array_Control_v1_0.tcl │ │ │ └── Windows_Data_Convert_v1_0 │ │ │ ├── component.xml │ │ │ └── xgui │ │ │ └── Windows_Data_Convert_v1_0_v1_0.tcl │ │ └── ip │ │ ├── axi_vip_0 │ │ └── axi_vip_0.xml │ │ └── div_gen_0 │ │ ├── div_gen_0.xml │ │ ├── hdl │ │ ├── axi_utils_v2_0_vh_rfs.vhd │ │ ├── div_gen_v5_1_vh_rfs.vhd │ │ ├── floating_point_v7_0_vh_rfs.vhd │ │ ├── mult_gen_v12_0_vh_rfs.vhd │ │ ├── xbip_bram18k_v3_0_vh_rfs.vhd │ │ ├── xbip_dsp48_addsub_v3_0_vh_rfs.vhd │ │ ├── xbip_dsp48_mult_v3_0_vh_rfs.vhd │ │ ├── xbip_dsp48_multadd_v3_0_vh_rfs.vhd │ │ ├── xbip_dsp48_wrapper_v3_0_vh_rfs.vhd │ │ ├── xbip_pipe_v3_0_vh_rfs.vhd │ │ └── xbip_utils_v3_0_vh_rfs.vhd │ │ └── sim │ │ └── div_gen_0.vhd ├── Accelerator.hw │ └── Accelerator.lpr ├── Accelerator.ip_user_files │ ├── README.txt │ ├── bd │ │ └── CNN_Module │ │ │ ├── ip │ │ │ ├── CNN_Module_CNN_Control_1_0 │ │ │ │ └── sim │ │ │ │ │ └── CNN_Module_CNN_Control_1_0.v │ │ │ ├── CNN_Module_INACT_DATA_FIFO_0 │ │ │ │ └── sim │ │ │ │ │ └── CNN_Module_INACT_DATA_FIFO_0.v │ │ │ ├── CNN_Module_PICTURE_DATA_FIFO_0 │ │ │ │ └── sim │ │ │ │ │ └── CNN_Module_PICTURE_DATA_FIFO_0.v │ │ │ ├── CNN_Module_RESULT_DATA_FIFO1_0 │ │ │ │ └── sim │ │ │ │ │ └── CNN_Module_RESULT_DATA_FIFO1_0.v │ │ │ ├── CNN_Module_WEIGHT_CONV_ACT_FULLCON_FIFO_0 │ │ │ │ └── sim │ │ │ │ │ └── CNN_Module_WEIGHT_CONV_ACT_FULLCON_FIFO_0.v │ │ │ ├── CNN_Module_WEIGHT_FULLCON_FIFO_0 │ │ │ │ └── sim │ │ │ │ │ └── CNN_Module_WEIGHT_FULLCON_FIFO_0.v │ │ │ └── CNN_Module_Windows_Data_Convert_0_0 │ │ │ │ └── sim │ │ │ │ └── CNN_Module_Windows_Data_Convert_0_0.v │ │ │ └── sim │ │ │ ├── CNN_Module.protoinst │ │ │ └── CNN_Module.v │ ├── mem_init_files │ │ └── CNN_Module.bda │ └── sim_scripts │ │ └── CNN_Module │ │ ├── README.txt │ │ ├── activehdl │ │ ├── CNN_Module.bda │ │ ├── CNN_Module.sh │ │ ├── CNN_Module.udo │ │ ├── README.txt │ │ ├── compile.do │ │ ├── file_info.txt │ │ ├── glbl.v │ │ ├── simulate.do │ │ └── wave.do │ │ ├── modelsim │ │ ├── CNN_Module.bda │ │ ├── CNN_Module.sh │ │ ├── CNN_Module.udo │ │ ├── README.txt │ │ ├── compile.do │ │ ├── file_info.txt │ │ ├── glbl.v │ │ ├── simulate.do │ │ └── wave.do │ │ ├── questa │ │ ├── CNN_Module.bda │ │ ├── CNN_Module.sh │ │ ├── CNN_Module.udo │ │ ├── README.txt │ │ ├── compile.do │ │ ├── elaborate.do │ │ ├── file_info.txt │ │ ├── glbl.v │ │ ├── simulate.do │ │ └── wave.do │ │ ├── riviera │ │ ├── CNN_Module.bda │ │ ├── CNN_Module.sh │ │ ├── CNN_Module.udo │ │ ├── README.txt │ │ ├── compile.do │ │ ├── file_info.txt │ │ ├── glbl.v │ │ ├── simulate.do │ │ └── wave.do │ │ ├── vcs │ │ ├── CNN_Module.bda │ │ ├── CNN_Module.sh │ │ ├── README.txt │ │ ├── file_info.txt │ │ ├── glbl.v │ │ └── simulate.do │ │ ├── xcelium │ │ ├── CNN_Module.bda │ │ ├── CNN_Module.sh │ │ ├── README.txt │ │ ├── file_info.txt │ │ ├── glbl.v │ │ └── run.f │ │ └── xsim │ │ ├── CNN_Module.bda │ │ ├── CNN_Module.sh │ │ ├── README.txt │ │ ├── cmd.tcl │ │ ├── elab.opt │ │ ├── file_info.txt │ │ ├── glbl.v │ │ ├── protoinst_files │ │ └── CNN_Module.protoinst │ │ ├── vlog.prj │ │ └── xsim.ini ├── Accelerator.sim │ └── sim_1 │ │ ├── behav │ │ └── xsim │ │ │ ├── CNN_Module_tb.tcl │ │ │ ├── CNN_Module_tb_behav.wdb │ │ │ ├── CNN_Module_tb_vhdl.prj │ │ │ ├── CNN_Module_tb_vlog.prj │ │ │ ├── compile.bat │ │ │ ├── elaborate.bat │ │ │ ├── elaborate.log │ │ │ ├── glbl.v │ │ │ ├── protoinst_files │ │ │ └── CNN_Module.protoinst │ │ │ ├── simulate.bat │ │ │ ├── simulate.log │ │ │ ├── xelab.pb │ │ │ ├── xsim.dir │ │ │ ├── CNN_Module_tb_behav │ │ │ │ ├── Compile_Options.txt │ │ │ │ ├── TempBreakPointFile.txt │ │ │ │ ├── obj │ │ │ │ │ ├── xsim_0.win64.obj │ │ │ │ │ ├── xsim_1.win64.obj │ │ │ │ │ ├── xsim_2.win64.obj │ │ │ │ │ ├── xsim_3.win64.obj │ │ │ │ │ ├── xsim_4.win64.obj │ │ │ │ │ ├── xsim_5.c │ │ │ │ │ └── xsim_5.win64.obj │ │ │ │ ├── xsim.dbg │ │ │ │ ├── xsim.mem │ │ │ │ ├── xsim.reloc │ │ │ │ ├── xsim.rlx │ │ │ │ ├── xsim.rtti │ │ │ │ ├── xsim.svtype │ │ │ │ ├── xsim.type │ │ │ │ ├── xsim.xdbg │ │ │ │ ├── xsimSettings.ini │ │ │ │ ├── xsimcrash.log │ │ │ │ ├── xsimk.exe │ │ │ │ └── xsimkernel.log │ │ │ └── xil_defaultlib │ │ │ │ ├── @c@n@n_@accelerator.sdb │ │ │ │ ├── @c@n@n_@control.sdb │ │ │ │ ├── @c@n@n_@control_v1_0_@s00_@a@x@i.sdb │ │ │ │ ├── @c@n@n_@module.sdb │ │ │ │ ├── @c@n@n_@module_@c@n@n_@control_1_0.sdb │ │ │ │ ├── @c@n@n_@module_@i@n@a@c@t_@d@a@t@a_@f@i@f@o_0.sdb │ │ │ │ ├── @c@n@n_@module_@p@i@c@t@u@r@e_@d@a@t@a_@f@i@f@o_0.sdb │ │ │ │ ├── @c@n@n_@module_@r@e@s@u@l@t_@d@a@t@a_@f@i@f@o1_0.sdb │ │ │ │ ├── @c@n@n_@module_@w@e@i@g@h@t_@c@o@n@v_@a@c@t_@f@u@l@l@c@o@n_@f@i@f@o_0.sdb │ │ │ │ ├── @c@n@n_@module_@w@e@i@g@h@t_@f@u@l@l@c@o@n_@f@i@f@o_0.sdb │ │ │ │ ├── @c@n@n_@module_@windows_@data_@convert_0_0.sdb │ │ │ │ ├── @c@n@n_@module_tb.sdb │ │ │ │ ├── @c@n@n_@module_wrapper.sdb │ │ │ │ ├── @conv_@array_@control.sdb │ │ │ │ ├── @conv_@p@e.sdb │ │ │ │ ├── @conv_@systolic@array.sdb │ │ │ │ ├── @full@con_@p@e.sdb │ │ │ │ ├── @full@con_@p@e_@control.sdb │ │ │ │ ├── @pool_@p@e.sdb │ │ │ │ ├── @pooling_@array_@control.sdb │ │ │ │ ├── @pooling_@systolic@array.sdb │ │ │ │ ├── @relu.sdb │ │ │ │ ├── @relu_@array_@control.sdb │ │ │ │ ├── @windows_@data_@convert_v1_0.sdb │ │ │ │ ├── @windows_@data_@convert_v1_0_@m00_@a@x@i@s.sdb │ │ │ │ ├── @windows_@data_@convert_v1_0_@s00_@a@x@i@s.sdb │ │ │ │ ├── @windows_@data_@convert_v1_0_@s01_@a@x@i.sdb │ │ │ │ ├── div_gen_0.vdb │ │ │ │ ├── glbl.sdb │ │ │ │ ├── windows.sdb │ │ │ │ └── xil_defaultlib.rlx │ │ │ ├── xsim.ini │ │ │ ├── xsim.ini.bak │ │ │ ├── xvhdl.log │ │ │ ├── xvhdl.pb │ │ │ ├── xvlog.log │ │ │ └── xvlog.pb │ │ ├── sim_txt │ │ ├── input_fcweight_data.txt │ │ ├── input_feature_data.txt │ │ ├── input_pool_max_data.txt │ │ └── input_weight_data.txt │ │ └── wave │ │ └── CNN_Module_tb_behav.wcfg ├── Accelerator.srcs │ ├── constrs_1 │ │ └── new │ │ │ └── pynq_z2.xdc │ ├── sim_1 │ │ ├── imports │ │ │ ├── CNN_System_tb │ │ │ │ └── CNN_Accelerator_system_Test_behav.wcfg │ │ │ └── behav │ │ │ │ ├── cnn │ │ │ │ └── CNN_Accelerator_tb_behav.wcfg │ │ │ │ ├── conv │ │ │ │ └── conv_tb_behav.wcfg │ │ │ │ └── window_tb │ │ │ │ ├── window_tb_behav.wcfg │ │ │ │ └── windows_data_axi_test_behav.wcfg │ │ └── new │ │ │ ├── CNN_Accelerator_tb.v │ │ │ ├── CNN_Module_tb.v │ │ │ ├── Relu_tb.v │ │ │ ├── Test_Windows_data_tb.sv │ │ │ ├── conv_tb.v │ │ │ ├── fullcon_tb.v │ │ │ ├── pool_tb.v │ │ │ ├── tanh_tb.v │ │ │ └── window_tb.v │ ├── sources_1 │ │ ├── bd │ │ │ ├── Accelerator │ │ │ │ ├── Accelerator.bd │ │ │ │ ├── Accelerator.bda │ │ │ │ ├── ip │ │ │ │ │ └── Accelerator_processing_system7_0_0 │ │ │ │ │ │ └── Accelerator_processing_system7_0_0.xci │ │ │ │ └── ui │ │ │ │ │ └── bd_fb33126b.ui │ │ │ ├── Accelerator_block_design │ │ │ │ ├── Accelerator_block_design.bd │ │ │ │ ├── Accelerator_block_design.bda │ │ │ │ ├── ip │ │ │ │ │ ├── Accelerator_block_design_CNN_Control_1_0 │ │ │ │ │ │ └── Accelerator_block_design_CNN_Control_1_0.xci │ │ │ │ │ ├── Accelerator_block_design_INACT_DATA_FIFO_0 │ │ │ │ │ │ └── Accelerator_block_design_INACT_DATA_FIFO_0.xci │ │ │ │ │ ├── Accelerator_block_design_Windows_Data_Convert_0_5 │ │ │ │ │ │ └── Accelerator_block_design_Windows_Data_Convert_0_5.xci │ │ │ │ │ ├── Accelerator_block_design_auto_ds_0 │ │ │ │ │ │ └── Accelerator_block_design_auto_ds_0.xci │ │ │ │ │ ├── Accelerator_block_design_auto_ds_1 │ │ │ │ │ │ └── Accelerator_block_design_auto_ds_1.xci │ │ │ │ │ ├── Accelerator_block_design_auto_pc_0 │ │ │ │ │ │ └── Accelerator_block_design_auto_pc_0.xci │ │ │ │ │ ├── Accelerator_block_design_auto_pc_1 │ │ │ │ │ │ └── Accelerator_block_design_auto_pc_1.xci │ │ │ │ │ ├── Accelerator_block_design_auto_us_0 │ │ │ │ │ │ └── Accelerator_block_design_auto_us_0.xci │ │ │ │ │ ├── Accelerator_block_design_axi_dma_0_0 │ │ │ │ │ │ └── Accelerator_block_design_axi_dma_0_0.xci │ │ │ │ │ ├── Accelerator_block_design_axi_dma_0_1 │ │ │ │ │ │ └── Accelerator_block_design_axi_dma_0_1.xci │ │ │ │ │ ├── Accelerator_block_design_axi_dma_0_2 │ │ │ │ │ │ └── Accelerator_block_design_axi_dma_0_2.xci │ │ │ │ │ ├── Accelerator_block_design_axi_dma_0_3 │ │ │ │ │ │ └── Accelerator_block_design_axi_dma_0_3.xci │ │ │ │ │ ├── Accelerator_block_design_axi_gpio_0_0 │ │ │ │ │ │ └── Accelerator_block_design_axi_gpio_0_0.xci │ │ │ │ │ ├── Accelerator_block_design_axi_intc_0_0 │ │ │ │ │ │ └── Accelerator_block_design_axi_intc_0_0.xci │ │ │ │ │ ├── Accelerator_block_design_axi_interconnect_0_0 │ │ │ │ │ │ └── Accelerator_block_design_axi_interconnect_0_0.xci │ │ │ │ │ ├── Accelerator_block_design_axi_interconnect_0_1 │ │ │ │ │ │ └── Accelerator_block_design_axi_interconnect_0_1.xci │ │ │ │ │ ├── Accelerator_block_design_axis_data_fifo_0_0 │ │ │ │ │ │ └── Accelerator_block_design_axis_data_fifo_0_0.xci │ │ │ │ │ ├── Accelerator_block_design_axis_data_fifo_0_1 │ │ │ │ │ │ └── Accelerator_block_design_axis_data_fifo_0_1.xci │ │ │ │ │ ├── Accelerator_block_design_axis_data_fifo_0_2 │ │ │ │ │ │ └── Accelerator_block_design_axis_data_fifo_0_2.xci │ │ │ │ │ ├── Accelerator_block_design_axis_data_fifo_1_0 │ │ │ │ │ │ └── Accelerator_block_design_axis_data_fifo_1_0.xci │ │ │ │ │ ├── Accelerator_block_design_proc_sys_reset_0_0 │ │ │ │ │ │ └── Accelerator_block_design_proc_sys_reset_0_0.xci │ │ │ │ │ ├── Accelerator_block_design_processing_system7_0_0 │ │ │ │ │ │ └── Accelerator_block_design_processing_system7_0_0.xci │ │ │ │ │ ├── Accelerator_block_design_s00_data_fifo_0 │ │ │ │ │ │ └── Accelerator_block_design_s00_data_fifo_0.xci │ │ │ │ │ ├── Accelerator_block_design_xbar_0 │ │ │ │ │ │ └── Accelerator_block_design_xbar_0.xci │ │ │ │ │ ├── Accelerator_block_design_xbar_1 │ │ │ │ │ │ └── Accelerator_block_design_xbar_1.xci │ │ │ │ │ └── Accelerator_block_design_xlconcat_0_0 │ │ │ │ │ │ └── Accelerator_block_design_xlconcat_0_0.xci │ │ │ │ └── ui │ │ │ │ │ ├── bd_7beb0d1f.ui │ │ │ │ │ ├── bd_9a70492b.ui │ │ │ │ │ └── bd_ab2a7024.ui │ │ │ ├── CNN_Module │ │ │ │ ├── CNN_Module.bd │ │ │ │ ├── CNN_Module.bda │ │ │ │ ├── ip │ │ │ │ │ ├── CNN_Module_CNN_Control_1_0 │ │ │ │ │ │ └── CNN_Module_CNN_Control_1_0.xci │ │ │ │ │ ├── CNN_Module_INACT_DATA_FIFO_0 │ │ │ │ │ │ └── CNN_Module_INACT_DATA_FIFO_0.xci │ │ │ │ │ ├── CNN_Module_PICTURE_DATA_FIFO_0 │ │ │ │ │ │ └── CNN_Module_PICTURE_DATA_FIFO_0.xci │ │ │ │ │ ├── CNN_Module_RESULT_DATA_FIFO1_0 │ │ │ │ │ │ └── CNN_Module_RESULT_DATA_FIFO1_0.xci │ │ │ │ │ ├── CNN_Module_WEIGHT_CONV_ACT_FULLCON_FIFO_0 │ │ │ │ │ │ └── CNN_Module_WEIGHT_CONV_ACT_FULLCON_FIFO_0.xci │ │ │ │ │ ├── CNN_Module_WEIGHT_FULLCON_FIFO_0 │ │ │ │ │ │ └── CNN_Module_WEIGHT_FULLCON_FIFO_0.xci │ │ │ │ │ └── CNN_Module_Windows_Data_Convert_0_0 │ │ │ │ │ │ └── CNN_Module_Windows_Data_Convert_0_0.xci │ │ │ │ └── ui │ │ │ │ │ └── bd_7fdb3988.ui │ │ │ └── Windows_data_Test │ │ │ │ ├── Windows_data_Test.bd │ │ │ │ ├── Windows_data_Test.bda │ │ │ │ ├── ip │ │ │ │ ├── Windows_data_Test_INACT_DATA_FIFO_0 │ │ │ │ │ └── Windows_data_Test_INACT_DATA_FIFO_0.xci │ │ │ │ ├── Windows_data_Test_INACT_DATA_FIFO_1 │ │ │ │ │ └── Windows_data_Test_INACT_DATA_FIFO_1.xci │ │ │ │ ├── Windows_data_Test_Windows_Data_Convert_0_1 │ │ │ │ │ └── Windows_data_Test_Windows_Data_Convert_0_1.xci │ │ │ │ ├── Windows_data_Test_auto_pc_0 │ │ │ │ │ └── Windows_data_Test_auto_pc_0.xci │ │ │ │ ├── Windows_data_Test_auto_pc_1 │ │ │ │ │ └── Windows_data_Test_auto_pc_1.xci │ │ │ │ ├── Windows_data_Test_auto_pc_2 │ │ │ │ │ └── Windows_data_Test_auto_pc_2.xci │ │ │ │ ├── Windows_data_Test_auto_pc_3 │ │ │ │ │ └── Windows_data_Test_auto_pc_3.xci │ │ │ │ ├── Windows_data_Test_axi_dma_0_0 │ │ │ │ │ └── Windows_data_Test_axi_dma_0_0.xci │ │ │ │ ├── Windows_data_Test_axi_dma_1_0 │ │ │ │ │ └── Windows_data_Test_axi_dma_1_0.xci │ │ │ │ ├── Windows_data_Test_axi_interconnect_0_0 │ │ │ │ │ └── Windows_data_Test_axi_interconnect_0_0.xci │ │ │ │ ├── Windows_data_Test_axi_interconnect_1_0 │ │ │ │ │ └── Windows_data_Test_axi_interconnect_1_0.xci │ │ │ │ ├── Windows_data_Test_ila_0_0 │ │ │ │ │ └── Windows_data_Test_ila_0_0.xci │ │ │ │ ├── Windows_data_Test_ila_0_3 │ │ │ │ │ └── Windows_data_Test_ila_0_3.xci │ │ │ │ ├── Windows_data_Test_proc_sys_reset_0_0 │ │ │ │ │ └── Windows_data_Test_proc_sys_reset_0_0.xci │ │ │ │ ├── Windows_data_Test_processing_system7_0_1 │ │ │ │ │ └── Windows_data_Test_processing_system7_0_1.xci │ │ │ │ ├── Windows_data_Test_xbar_0 │ │ │ │ │ └── Windows_data_Test_xbar_0.xci │ │ │ │ ├── Windows_data_Test_xbar_1 │ │ │ │ │ └── Windows_data_Test_xbar_1.xci │ │ │ │ └── Windows_data_Test_xlconcat_0_0 │ │ │ │ │ └── Windows_data_Test_xlconcat_0_0.xci │ │ │ │ └── ui │ │ │ │ └── bd_22a3e04b.ui │ │ ├── imports │ │ │ └── window_ip │ │ │ │ ├── Windows_Data_Convert_v1_0.v │ │ │ │ ├── Windows_Data_Convert_v1_0_M00_AXIS.v │ │ │ │ ├── Windows_Data_Convert_v1_0_S00_AXIS.v │ │ │ │ ├── Windows_Data_Convert_v1_0_S01_AXI.v │ │ │ │ └── windows.v │ │ ├── ip │ │ │ ├── axi_vip_0 │ │ │ │ └── axi_vip_0.xci │ │ │ └── div_gen_0 │ │ │ │ └── div_gen_0.xci │ │ └── new │ │ │ ├── CNN_Accelerator.v │ │ │ ├── CNN_Control.v │ │ │ ├── CNN_Control │ │ │ ├── CNN_Accelerator.v │ │ │ ├── CNN_Control.v │ │ │ ├── CNN_Control_S00_AXI.v │ │ │ ├── Conv_Array_Control.v │ │ │ ├── Conv_PE.v │ │ │ ├── Conv_SystolicArray.v │ │ │ ├── FullCon_PE.v │ │ │ ├── FullCon_PE_Control.v │ │ │ ├── Pool_PE.v │ │ │ ├── Pooling_Array_Control.v │ │ │ ├── Pooling_SystolicArray.v │ │ │ ├── Relu.v │ │ │ └── Relu_Array_Control.v │ │ │ ├── CNN_Control_S00_AXI.v │ │ │ ├── Conv_Array_Control.v │ │ │ ├── Conv_PE.v │ │ │ ├── Conv_SystolicArray.v │ │ │ ├── FullCon_PE.v │ │ │ ├── FullCon_PE_Control.v │ │ │ ├── Pool_PE.v │ │ │ ├── Pooling_Array_Control.v │ │ │ ├── Pooling_SystolicArray.v │ │ │ ├── Relu.v │ │ │ ├── Relu_Array_Control.v │ │ │ ├── Window.v │ │ │ └── tanh.v │ └── utils_1 │ │ └── imports │ │ └── synth_1 │ │ └── Conv_SystolicArray.dcp ├── Accelerator.tcl ├── Accelerator.tmp │ ├── cnn_control_v2_0_project │ │ ├── CNN_Control_v2_0_project.cache │ │ │ └── wt │ │ │ │ └── project.wpc │ │ ├── CNN_Control_v2_0_project.hw │ │ │ └── CNN_Control_v2_0_project.lpr │ │ └── CNN_Control_v2_0_project.xpr │ └── windows_data_convert_v1_0_project │ │ ├── Windows_Data_Convert_v1_0_project.cache │ │ └── wt │ │ │ └── project.wpc │ │ ├── Windows_Data_Convert_v1_0_project.hw │ │ └── Windows_Data_Convert_v1_0_project.lpr │ │ └── Windows_Data_Convert_v1_0_project.xpr ├── Accelerator.xpr ├── ip_upgrade.log ├── vivado.jou ├── vivado.log ├── vivado_11920.backup.jou ├── vivado_11920.backup.log ├── vivado_1444.backup.jou ├── vivado_1444.backup.log ├── vivado_19848.backup.jou ├── vivado_19848.backup.log ├── vivado_20584.backup.jou ├── vivado_20584.backup.log └── vivado_pid12020.str ├── LICENSE ├── README.md └── Software_project ├── Software └── software_jupyter │ ├── Accelerator_System_design.ipynb │ ├── AlexNet_16 │ ├── Alexnet_conv2_weight.txt │ ├── Alexnet_conv3_weight.txt │ ├── Alexnet_conv4_weight.txt │ ├── Alexnet_conv5_weight.txt │ ├── Alexnet_conv_weight.txt │ ├── Alexnet_fc1_weight.txt │ ├── Alexnet_fc2_weight.txt │ └── Alexnet_fc3_weight.txt │ ├── AlexNet_Test.ipynb │ ├── LeNet_Number_Test.ipynb │ ├── Lenet_new_weight │ ├── Conv1_weight0combine6_0.txt │ ├── Conv2_weight00combine6_0.txt │ ├── Conv2_weight01combine6_0.txt │ ├── Conv2_weight10combine6_0.txt │ ├── Conv2_weight11combine6_0.txt │ ├── Conv2_weight20combine6_0.txt │ ├── Conv2_weight21combine6_0.txt │ ├── Conv2_weight30combine6_0.txt │ ├── Conv2_weight31combine6_0.txt │ ├── Conv2_weight40combine6_0.txt │ ├── Conv2_weight41combine6_0.txt │ ├── Conv2_weight50combine6_0.txt │ ├── Conv2_weight51combine6_0.txt │ ├── fc_weight_combine2.txt │ └── fc_weight_combine8.txt │ ├── number │ ├── 0 │ │ ├── 0_0.jpg │ │ ├── 0_1.jpg │ │ ├── 0_10.jpg │ │ ├── 0_11.jpg │ │ ├── 0_12.jpg │ │ ├── 0_13.jpg │ │ ├── 0_14.jpg │ │ ├── 0_15.jpg │ │ ├── 0_16.jpg │ │ ├── 0_17.jpg │ │ ├── 0_18.jpg │ │ ├── 0_19.jpg │ │ ├── 0_2.jpg │ │ ├── 0_20.jpg │ │ ├── 0_21.jpg │ │ ├── 0_22.jpg │ │ ├── 0_23.jpg │ │ ├── 0_24.jpg │ │ ├── 0_25.jpg │ │ ├── 0_26.jpg │ │ ├── 0_27.jpg │ │ ├── 0_28.jpg │ │ ├── 0_29.jpg │ │ ├── 0_3.jpg │ │ ├── 0_30.jpg │ │ ├── 0_31.jpg │ │ ├── 0_32.jpg │ │ ├── 0_33.jpg │ │ ├── 0_34.jpg │ │ ├── 0_35.jpg │ │ ├── 0_36.jpg │ │ ├── 0_37.jpg │ │ ├── 0_38.jpg │ │ ├── 0_39.jpg │ │ ├── 0_4.jpg │ │ ├── 0_40.jpg │ │ ├── 0_41.jpg │ │ ├── 0_42.jpg │ │ ├── 0_43.jpg │ │ ├── 0_44.jpg │ │ ├── 0_45.jpg │ │ ├── 0_46.jpg │ │ ├── 0_47.jpg │ │ ├── 0_48.jpg │ │ ├── 0_49.jpg │ │ ├── 0_5.jpg │ │ ├── 0_50.jpg │ │ ├── 0_51.jpg │ │ ├── 0_52.jpg │ │ ├── 0_53.jpg │ │ ├── 0_54.jpg │ │ ├── 0_55.jpg │ │ ├── 0_56.jpg │ │ ├── 0_57.jpg │ │ ├── 0_58.jpg │ │ ├── 0_59.jpg │ │ ├── 0_6.jpg │ │ ├── 0_60.jpg │ │ ├── 0_61.jpg │ │ ├── 0_62.jpg │ │ ├── 0_63.jpg │ │ ├── 0_64.jpg │ │ ├── 0_65.jpg │ │ ├── 0_66.jpg │ │ ├── 0_67.jpg │ │ ├── 0_68.jpg │ │ ├── 0_69.jpg │ │ ├── 0_7.jpg │ │ ├── 0_70.jpg │ │ ├── 0_71.jpg │ │ ├── 0_72.jpg │ │ ├── 0_73.jpg │ │ ├── 0_74.jpg │ │ ├── 0_75.jpg │ │ ├── 0_76.jpg │ │ ├── 0_77.jpg │ │ ├── 0_78.jpg │ │ ├── 0_79.jpg │ │ ├── 0_8.jpg │ │ ├── 0_80.jpg │ │ ├── 0_81.jpg │ │ ├── 0_82.jpg │ │ ├── 0_83.jpg │ │ ├── 0_84.jpg │ │ ├── 0_85.jpg │ │ ├── 0_86.jpg │ │ ├── 0_87.jpg │ │ ├── 0_88.jpg │ │ ├── 0_89.jpg │ │ ├── 0_9.jpg │ │ ├── 0_90.jpg │ │ ├── 0_91.jpg │ │ ├── 0_92.jpg │ │ ├── 0_93.jpg │ │ ├── 0_94.jpg │ │ ├── 0_95.jpg │ │ ├── 0_96.jpg │ │ ├── 0_97.jpg │ │ ├── 0_98.jpg │ │ └── 0_99.jpg │ ├── 1 │ │ ├── 0.png │ │ ├── 1.png │ │ ├── 2.png │ │ ├── 3.png │ │ ├── 4.png │ │ ├── 5.png │ │ ├── 6.png │ │ ├── 7.png │ │ ├── 8.png │ │ └── 9.png │ ├── 2 │ │ ├── 0.png │ │ ├── 1.png │ │ ├── 2.png │ │ ├── 3.png │ │ ├── 4.png │ │ ├── 5.png │ │ ├── 6.png │ │ ├── 7.png │ │ ├── 8.png │ │ └── 9.png │ ├── 3 │ │ ├── 0.png │ │ ├── 1.png │ │ ├── 2.png │ │ ├── 3.png │ │ ├── 4.png │ │ ├── 5.png │ │ ├── 6.png │ │ ├── 7.png │ │ ├── 8.png │ │ └── 9.png │ ├── 4 │ │ ├── 0.png │ │ ├── 1.png │ │ ├── 2.png │ │ ├── 3.png │ │ ├── 4.png │ │ ├── 5.png │ │ ├── 6.png │ │ ├── 7.png │ │ ├── 8.png │ │ └── 9.png │ ├── 5 │ │ ├── 0.png │ │ ├── 1.png │ │ ├── 2.png │ │ ├── 3.png │ │ ├── 4.png │ │ ├── 5.png │ │ ├── 6.png │ │ ├── 7.png │ │ ├── 8.png │ │ └── 9.png │ ├── 6 │ │ ├── 0.png │ │ ├── 1.png │ │ ├── 2.png │ │ ├── 3.png │ │ ├── 4.png │ │ ├── 5.png │ │ ├── 6.png │ │ ├── 7.png │ │ ├── 8.png │ │ └── 9.png │ ├── 7 │ │ ├── 0.png │ │ ├── 1.png │ │ ├── 2.png │ │ ├── 3.png │ │ ├── 4.png │ │ ├── 5.png │ │ ├── 6.png │ │ ├── 7.png │ │ ├── 8.png │ │ └── 9.png │ ├── 8 │ │ ├── 0.png │ │ ├── 1.png │ │ ├── 2.png │ │ ├── 3.png │ │ ├── 4.png │ │ ├── 5.png │ │ ├── 6.png │ │ ├── 7.png │ │ ├── 8.png │ │ └── 9.png │ └── 9 │ │ ├── 0.png │ │ ├── 1.png │ │ ├── 2.png │ │ ├── 3.png │ │ ├── 4.png │ │ ├── 5.png │ │ ├── 6.png │ │ ├── 7.png │ │ ├── 8.png │ │ └── 9.png │ └── number_txt │ └── 暂存量化后的输入图片.txt └── bitstream文件 ├── Accelerator_Alexnet.bit ├── Accelerator_Alexnet.hwh ├── Accelerator_bigger.bit ├── Accelerator_bigger.hwh ├── Accelerator_number.bit └── Accelerator_number.hwh /CNN_Accelerator_Vivado_project/Accelerator.cache/wt/project.wpc: -------------------------------------------------------------------------------- 1 | version:1 2 | 6d6f64655f636f756e7465727c4755494d6f6465:1 3 | eof: 4 | -------------------------------------------------------------------------------- /CNN_Accelerator_Vivado_project/Accelerator.cache/wt/xsim.wdf: -------------------------------------------------------------------------------- 1 | version:1 2 | 7873696d:7873696d5c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73696d5f6d6f6465:6265686176696f72616c:00:00 3 | 7873696d:7873696d5c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73696d5f74797065:64656661756c743a3a:00:00 4 | eof:2427094519 5 | -------------------------------------------------------------------------------- /CNN_Accelerator_Vivado_project/Accelerator.gen/sources_1/bd/Accelerator/Accelerator.bda: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | active 25 | 2 26 | PM 27 | 28 | 29 | Accelerator 30 | BC 31 | 32 | 33 | 2 34 | Accelerator 35 | VR 36 | 37 | 38 | 39 | 40 | 41 | -------------------------------------------------------------------------------- /CNN_Accelerator_Vivado_project/Accelerator.gen/sources_1/bd/Accelerator/Accelerator.bxml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | Composite Fileset 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | -------------------------------------------------------------------------------- /CNN_Accelerator_Vivado_project/Accelerator.gen/sources_1/bd/Accelerator_block_design/Accelerator_block_design.bxml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | Composite Fileset 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | -------------------------------------------------------------------------------- /CNN_Accelerator_Vivado_project/Accelerator.gen/sources_1/bd/CNN_Module/CNN_Module_ooc.xdc: -------------------------------------------------------------------------------- 1 | ################################################################################ 2 | 3 | # This XDC is used only for OOC mode of synthesis, implementation 4 | # This constraints file contains default clock frequencies to be used during 5 | # out-of-context flows such as OOC Synthesis and Hierarchical Designs. 6 | # This constraints file is not used in normal top-down synthesis (default flow 7 | # of Vivado) 8 | ################################################################################ 9 | create_clock -name s_axis_aclk -period 20 [get_ports s_axis_aclk] 10 | 11 | ################################################################################ -------------------------------------------------------------------------------- /CNN_Accelerator_Vivado_project/Accelerator.gen/sources_1/bd/CNN_Module/synth/CNN_Module.hwdef: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Futuresxy/General-CNN-Accelerator/09c07c86f0b739fc420f5e620bc1d10288eb774d/CNN_Accelerator_Vivado_project/Accelerator.gen/sources_1/bd/CNN_Module/synth/CNN_Module.hwdef -------------------------------------------------------------------------------- /CNN_Accelerator_Vivado_project/Accelerator.gen/sources_1/bd/Windows_data_Test/Windows_data_Test.bxml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | Composite Fileset 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | -------------------------------------------------------------------------------- /CNN_Accelerator_Vivado_project/Accelerator.gen/sources_1/bd/mref/Conv_Array_Control/xgui/Conv_Array_Control_v1_0.tcl: -------------------------------------------------------------------------------- 1 | # Definitional proc to organize widgets for parameters. 2 | proc init_gui { IPINST } { 3 | ipgui::add_param $IPINST -name "Component_Name" 4 | #Adding Page 5 | set Page_0 [ipgui::add_page $IPINST -name "Page 0"] 6 | ipgui::add_param $IPINST -name "Conv_Kernel_Num" -parent ${Page_0} 7 | ipgui::add_param $IPINST -name "Conv_Kernel_Size" -parent ${Page_0} 8 | ipgui::add_param $IPINST -name "Data_width" -parent ${Page_0} 9 | 10 | 11 | } 12 | 13 | proc update_PARAM_VALUE.Conv_Kernel_Num { PARAM_VALUE.Conv_Kernel_Num } { 14 | # Procedure called to update Conv_Kernel_Num when any of the dependent parameters in the arguments change 15 | } 16 | 17 | proc validate_PARAM_VALUE.Conv_Kernel_Num { PARAM_VALUE.Conv_Kernel_Num } { 18 | # Procedure called to validate Conv_Kernel_Num 19 | return true 20 | } 21 | 22 | proc update_PARAM_VALUE.Conv_Kernel_Size { PARAM_VALUE.Conv_Kernel_Size } { 23 | # Procedure called to update Conv_Kernel_Size when any of the dependent parameters in the arguments change 24 | } 25 | 26 | proc validate_PARAM_VALUE.Conv_Kernel_Size { PARAM_VALUE.Conv_Kernel_Size } { 27 | # Procedure called to validate Conv_Kernel_Size 28 | return true 29 | } 30 | 31 | proc update_PARAM_VALUE.Data_width { PARAM_VALUE.Data_width } { 32 | # Procedure called to update Data_width when any of the dependent parameters in the arguments change 33 | } 34 | 35 | proc validate_PARAM_VALUE.Data_width { PARAM_VALUE.Data_width } { 36 | # Procedure called to validate Data_width 37 | return true 38 | } 39 | 40 | 41 | proc update_MODELPARAM_VALUE.Data_width { MODELPARAM_VALUE.Data_width PARAM_VALUE.Data_width } { 42 | # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value 43 | set_property value [get_property value ${PARAM_VALUE.Data_width}] ${MODELPARAM_VALUE.Data_width} 44 | } 45 | 46 | proc update_MODELPARAM_VALUE.Conv_Kernel_Size { MODELPARAM_VALUE.Conv_Kernel_Size PARAM_VALUE.Conv_Kernel_Size } { 47 | # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value 48 | set_property value [get_property value ${PARAM_VALUE.Conv_Kernel_Size}] ${MODELPARAM_VALUE.Conv_Kernel_Size} 49 | } 50 | 51 | proc update_MODELPARAM_VALUE.Conv_Kernel_Num { MODELPARAM_VALUE.Conv_Kernel_Num PARAM_VALUE.Conv_Kernel_Num } { 52 | # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value 53 | set_property value [get_property value ${PARAM_VALUE.Conv_Kernel_Num}] ${MODELPARAM_VALUE.Conv_Kernel_Num} 54 | } 55 | 56 | -------------------------------------------------------------------------------- /CNN_Accelerator_Vivado_project/Accelerator.gen/sources_1/bd/mref/Pooling_Array_Control/xgui/Pooling_Array_Control_v1_0.tcl: -------------------------------------------------------------------------------- 1 | # Definitional proc to organize widgets for parameters. 2 | proc init_gui { IPINST } { 3 | ipgui::add_param $IPINST -name "Component_Name" 4 | #Adding Page 5 | set Page_0 [ipgui::add_page $IPINST -name "Page 0"] 6 | ipgui::add_param $IPINST -name "Data_width" -parent ${Page_0} 7 | ipgui::add_param $IPINST -name "Pool_Kernel_Size" -parent ${Page_0} 8 | 9 | 10 | } 11 | 12 | proc update_PARAM_VALUE.Data_width { PARAM_VALUE.Data_width } { 13 | # Procedure called to update Data_width when any of the dependent parameters in the arguments change 14 | } 15 | 16 | proc validate_PARAM_VALUE.Data_width { PARAM_VALUE.Data_width } { 17 | # Procedure called to validate Data_width 18 | return true 19 | } 20 | 21 | proc update_PARAM_VALUE.Pool_Kernel_Size { PARAM_VALUE.Pool_Kernel_Size } { 22 | # Procedure called to update Pool_Kernel_Size when any of the dependent parameters in the arguments change 23 | } 24 | 25 | proc validate_PARAM_VALUE.Pool_Kernel_Size { PARAM_VALUE.Pool_Kernel_Size } { 26 | # Procedure called to validate Pool_Kernel_Size 27 | return true 28 | } 29 | 30 | 31 | proc update_MODELPARAM_VALUE.Data_width { MODELPARAM_VALUE.Data_width PARAM_VALUE.Data_width } { 32 | # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value 33 | set_property value [get_property value ${PARAM_VALUE.Data_width}] ${MODELPARAM_VALUE.Data_width} 34 | } 35 | 36 | proc update_MODELPARAM_VALUE.Pool_Kernel_Size { MODELPARAM_VALUE.Pool_Kernel_Size PARAM_VALUE.Pool_Kernel_Size } { 37 | # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value 38 | set_property value [get_property value ${PARAM_VALUE.Pool_Kernel_Size}] ${MODELPARAM_VALUE.Pool_Kernel_Size} 39 | } 40 | 41 | -------------------------------------------------------------------------------- /CNN_Accelerator_Vivado_project/Accelerator.gen/sources_1/bd/mref/Relu_Array_Control/xgui/Relu_Array_Control_v1_0.tcl: -------------------------------------------------------------------------------- 1 | # Definitional proc to organize widgets for parameters. 2 | proc init_gui { IPINST } { 3 | ipgui::add_param $IPINST -name "Component_Name" 4 | #Adding Page 5 | set Page_0 [ipgui::add_page $IPINST -name "Page 0"] 6 | ipgui::add_param $IPINST -name "Data_width" -parent ${Page_0} 7 | ipgui::add_param $IPINST -name "Relu_Num" -parent ${Page_0} 8 | 9 | 10 | } 11 | 12 | proc update_PARAM_VALUE.Data_width { PARAM_VALUE.Data_width } { 13 | # Procedure called to update Data_width when any of the dependent parameters in the arguments change 14 | } 15 | 16 | proc validate_PARAM_VALUE.Data_width { PARAM_VALUE.Data_width } { 17 | # Procedure called to validate Data_width 18 | return true 19 | } 20 | 21 | proc update_PARAM_VALUE.Relu_Num { PARAM_VALUE.Relu_Num } { 22 | # Procedure called to update Relu_Num when any of the dependent parameters in the arguments change 23 | } 24 | 25 | proc validate_PARAM_VALUE.Relu_Num { PARAM_VALUE.Relu_Num } { 26 | # Procedure called to validate Relu_Num 27 | return true 28 | } 29 | 30 | 31 | proc update_MODELPARAM_VALUE.Data_width { MODELPARAM_VALUE.Data_width PARAM_VALUE.Data_width } { 32 | # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value 33 | set_property value [get_property value ${PARAM_VALUE.Data_width}] ${MODELPARAM_VALUE.Data_width} 34 | } 35 | 36 | proc update_MODELPARAM_VALUE.Relu_Num { MODELPARAM_VALUE.Relu_Num PARAM_VALUE.Relu_Num } { 37 | # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value 38 | set_property value [get_property value ${PARAM_VALUE.Relu_Num}] ${MODELPARAM_VALUE.Relu_Num} 39 | } 40 | 41 | -------------------------------------------------------------------------------- /CNN_Accelerator_Vivado_project/Accelerator.hw/Accelerator.lpr: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | -------------------------------------------------------------------------------- /CNN_Accelerator_Vivado_project/Accelerator.ip_user_files/README.txt: -------------------------------------------------------------------------------- 1 | The files in this directory structure are automatically generated and managed by Vivado. Editing these files is not recommended. 2 | -------------------------------------------------------------------------------- /CNN_Accelerator_Vivado_project/Accelerator.ip_user_files/sim_scripts/CNN_Module/activehdl/CNN_Module.udo: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Futuresxy/General-CNN-Accelerator/09c07c86f0b739fc420f5e620bc1d10288eb774d/CNN_Accelerator_Vivado_project/Accelerator.ip_user_files/sim_scripts/CNN_Module/activehdl/CNN_Module.udo -------------------------------------------------------------------------------- /CNN_Accelerator_Vivado_project/Accelerator.ip_user_files/sim_scripts/CNN_Module/activehdl/README.txt: -------------------------------------------------------------------------------- 1 | ################################################################################ 2 | # Vivado (TM) v2022.1 (64-bit) 3 | # 4 | # README.txt: Please read the sections below to understand the steps required to 5 | # run the exported script and information about the source files. 6 | # 7 | # Generated by export_simulation on Sun Feb 09 15:31:56 +0800 2025 8 | # 9 | ################################################################################ 10 | 11 | 1. How to run the generated simulation script:- 12 | 13 | From the shell prompt in the current directory, issue the following command:- 14 | 15 | ./CNN_Module.sh 16 | 17 | This command will launch the 'compile', 'elaborate' and 'simulate' functions 18 | implemented in the script file for the 3-step flow. These functions are called 19 | from the main 'run' function in the script file. 20 | 21 | The 'run' function first executes the 'setup' function, the purpose of which is to 22 | create simulator specific setup files, create design library mappings and library 23 | directories and copy 'glbl.v' from the Vivado software install location into the 24 | current directory. 25 | 26 | The 'setup' function is also used for removing the simulator generated data in 27 | order to reset the current directory to the original state when export_simulation 28 | was launched from Vivado. This generated data can be removed by specifying the 29 | '-reset_run' switch to the './CNN_Module.sh' script. 30 | 31 | ./CNN_Module.sh -reset_run 32 | 33 | To keep the generated data from the previous run but regenerate the setup files and 34 | library directories, use the '-noclean_files' switch. 35 | 36 | ./CNN_Module.sh -noclean_files 37 | 38 | For more information on the script, please type './CNN_Module.sh -help'. 39 | 40 | 2. Additional design information files:- 41 | 42 | export_simulation generates following additional file that can be used for fetching 43 | the design files information or for integrating with external custom scripts. 44 | 45 | Name : file_info.txt 46 | Purpose: This file contains detail design file information based on the compile order 47 | when export_simulation was executed from Vivado. The file contains information 48 | about the file type, name, whether it is part of the IP, associated library 49 | and the file path information. 50 | -------------------------------------------------------------------------------- /CNN_Accelerator_Vivado_project/Accelerator.ip_user_files/sim_scripts/CNN_Module/activehdl/glbl.v: -------------------------------------------------------------------------------- 1 | // $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ 2 | `ifndef GLBL 3 | `define GLBL 4 | `timescale 1 ps / 1 ps 5 | 6 | module glbl (); 7 | 8 | parameter ROC_WIDTH = 100000; 9 | parameter TOC_WIDTH = 0; 10 | parameter GRES_WIDTH = 10000; 11 | parameter GRES_START = 10000; 12 | 13 | //-------- STARTUP Globals -------------- 14 | wire GSR; 15 | wire GTS; 16 | wire GWE; 17 | wire PRLD; 18 | wire GRESTORE; 19 | tri1 p_up_tmp; 20 | tri (weak1, strong0) PLL_LOCKG = p_up_tmp; 21 | 22 | wire PROGB_GLBL; 23 | wire CCLKO_GLBL; 24 | wire FCSBO_GLBL; 25 | wire [3:0] DO_GLBL; 26 | wire [3:0] DI_GLBL; 27 | 28 | reg GSR_int; 29 | reg GTS_int; 30 | reg PRLD_int; 31 | reg GRESTORE_int; 32 | 33 | //-------- JTAG Globals -------------- 34 | wire JTAG_TDO_GLBL; 35 | wire JTAG_TCK_GLBL; 36 | wire JTAG_TDI_GLBL; 37 | wire JTAG_TMS_GLBL; 38 | wire JTAG_TRST_GLBL; 39 | 40 | reg JTAG_CAPTURE_GLBL; 41 | reg JTAG_RESET_GLBL; 42 | reg JTAG_SHIFT_GLBL; 43 | reg JTAG_UPDATE_GLBL; 44 | reg JTAG_RUNTEST_GLBL; 45 | 46 | reg JTAG_SEL1_GLBL = 0; 47 | reg JTAG_SEL2_GLBL = 0 ; 48 | reg JTAG_SEL3_GLBL = 0; 49 | reg JTAG_SEL4_GLBL = 0; 50 | 51 | reg JTAG_USER_TDO1_GLBL = 1'bz; 52 | reg JTAG_USER_TDO2_GLBL = 1'bz; 53 | reg JTAG_USER_TDO3_GLBL = 1'bz; 54 | reg JTAG_USER_TDO4_GLBL = 1'bz; 55 | 56 | assign (strong1, weak0) GSR = GSR_int; 57 | assign (strong1, weak0) GTS = GTS_int; 58 | assign (weak1, weak0) PRLD = PRLD_int; 59 | assign (strong1, weak0) GRESTORE = GRESTORE_int; 60 | 61 | initial begin 62 | GSR_int = 1'b1; 63 | PRLD_int = 1'b1; 64 | #(ROC_WIDTH) 65 | GSR_int = 1'b0; 66 | PRLD_int = 1'b0; 67 | end 68 | 69 | initial begin 70 | GTS_int = 1'b1; 71 | #(TOC_WIDTH) 72 | GTS_int = 1'b0; 73 | end 74 | 75 | initial begin 76 | GRESTORE_int = 1'b0; 77 | #(GRES_START); 78 | GRESTORE_int = 1'b1; 79 | #(GRES_WIDTH); 80 | GRESTORE_int = 1'b0; 81 | end 82 | 83 | endmodule 84 | `endif 85 | -------------------------------------------------------------------------------- /CNN_Accelerator_Vivado_project/Accelerator.ip_user_files/sim_scripts/CNN_Module/activehdl/simulate.do: -------------------------------------------------------------------------------- 1 | onbreak {quit -force} 2 | onerror {quit -force} 3 | 4 | asim +access +r +m+CNN_Module -L xilinx_vip -L xpm -L xil_defaultlib -L axis_infrastructure_v1_1_0 -L axis_data_fifo_v2_0_8 -L xilinx_vip -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.CNN_Module xil_defaultlib.glbl 5 | 6 | set NumericStdNoWarnings 1 7 | set StdArithNoWarnings 1 8 | 9 | do {wave.do} 10 | 11 | view wave 12 | view structure 13 | 14 | do {CNN_Module.udo} 15 | 16 | run -all 17 | 18 | endsim 19 | 20 | quit -force 21 | -------------------------------------------------------------------------------- /CNN_Accelerator_Vivado_project/Accelerator.ip_user_files/sim_scripts/CNN_Module/activehdl/wave.do: -------------------------------------------------------------------------------- 1 | add wave * 2 | add wave /glbl/GSR 3 | -------------------------------------------------------------------------------- /CNN_Accelerator_Vivado_project/Accelerator.ip_user_files/sim_scripts/CNN_Module/modelsim/CNN_Module.udo: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Futuresxy/General-CNN-Accelerator/09c07c86f0b739fc420f5e620bc1d10288eb774d/CNN_Accelerator_Vivado_project/Accelerator.ip_user_files/sim_scripts/CNN_Module/modelsim/CNN_Module.udo -------------------------------------------------------------------------------- /CNN_Accelerator_Vivado_project/Accelerator.ip_user_files/sim_scripts/CNN_Module/modelsim/README.txt: -------------------------------------------------------------------------------- 1 | ################################################################################ 2 | # Vivado (TM) v2022.1 (64-bit) 3 | # 4 | # README.txt: Please read the sections below to understand the steps required to 5 | # run the exported script and information about the source files. 6 | # 7 | # Generated by export_simulation on Sun Feb 09 15:31:56 +0800 2025 8 | # 9 | ################################################################################ 10 | 11 | 1. How to run the generated simulation script:- 12 | 13 | From the shell prompt in the current directory, issue the following command:- 14 | 15 | ./CNN_Module.sh 16 | 17 | This command will launch the 'compile', 'elaborate' and 'simulate' functions 18 | implemented in the script file for the 3-step flow. These functions are called 19 | from the main 'run' function in the script file. 20 | 21 | The 'run' function first executes the 'setup' function, the purpose of which is to 22 | create simulator specific setup files, create design library mappings and library 23 | directories and copy 'glbl.v' from the Vivado software install location into the 24 | current directory. 25 | 26 | The 'setup' function is also used for removing the simulator generated data in 27 | order to reset the current directory to the original state when export_simulation 28 | was launched from Vivado. This generated data can be removed by specifying the 29 | '-reset_run' switch to the './CNN_Module.sh' script. 30 | 31 | ./CNN_Module.sh -reset_run 32 | 33 | To keep the generated data from the previous run but regenerate the setup files and 34 | library directories, use the '-noclean_files' switch. 35 | 36 | ./CNN_Module.sh -noclean_files 37 | 38 | For more information on the script, please type './CNN_Module.sh -help'. 39 | 40 | 2. Additional design information files:- 41 | 42 | export_simulation generates following additional file that can be used for fetching 43 | the design files information or for integrating with external custom scripts. 44 | 45 | Name : file_info.txt 46 | Purpose: This file contains detail design file information based on the compile order 47 | when export_simulation was executed from Vivado. The file contains information 48 | about the file type, name, whether it is part of the IP, associated library 49 | and the file path information. 50 | -------------------------------------------------------------------------------- /CNN_Accelerator_Vivado_project/Accelerator.ip_user_files/sim_scripts/CNN_Module/modelsim/glbl.v: -------------------------------------------------------------------------------- 1 | // $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ 2 | `ifndef GLBL 3 | `define GLBL 4 | `timescale 1 ps / 1 ps 5 | 6 | module glbl (); 7 | 8 | parameter ROC_WIDTH = 100000; 9 | parameter TOC_WIDTH = 0; 10 | parameter GRES_WIDTH = 10000; 11 | parameter GRES_START = 10000; 12 | 13 | //-------- STARTUP Globals -------------- 14 | wire GSR; 15 | wire GTS; 16 | wire GWE; 17 | wire PRLD; 18 | wire GRESTORE; 19 | tri1 p_up_tmp; 20 | tri (weak1, strong0) PLL_LOCKG = p_up_tmp; 21 | 22 | wire PROGB_GLBL; 23 | wire CCLKO_GLBL; 24 | wire FCSBO_GLBL; 25 | wire [3:0] DO_GLBL; 26 | wire [3:0] DI_GLBL; 27 | 28 | reg GSR_int; 29 | reg GTS_int; 30 | reg PRLD_int; 31 | reg GRESTORE_int; 32 | 33 | //-------- JTAG Globals -------------- 34 | wire JTAG_TDO_GLBL; 35 | wire JTAG_TCK_GLBL; 36 | wire JTAG_TDI_GLBL; 37 | wire JTAG_TMS_GLBL; 38 | wire JTAG_TRST_GLBL; 39 | 40 | reg JTAG_CAPTURE_GLBL; 41 | reg JTAG_RESET_GLBL; 42 | reg JTAG_SHIFT_GLBL; 43 | reg JTAG_UPDATE_GLBL; 44 | reg JTAG_RUNTEST_GLBL; 45 | 46 | reg JTAG_SEL1_GLBL = 0; 47 | reg JTAG_SEL2_GLBL = 0 ; 48 | reg JTAG_SEL3_GLBL = 0; 49 | reg JTAG_SEL4_GLBL = 0; 50 | 51 | reg JTAG_USER_TDO1_GLBL = 1'bz; 52 | reg JTAG_USER_TDO2_GLBL = 1'bz; 53 | reg JTAG_USER_TDO3_GLBL = 1'bz; 54 | reg JTAG_USER_TDO4_GLBL = 1'bz; 55 | 56 | assign (strong1, weak0) GSR = GSR_int; 57 | assign (strong1, weak0) GTS = GTS_int; 58 | assign (weak1, weak0) PRLD = PRLD_int; 59 | assign (strong1, weak0) GRESTORE = GRESTORE_int; 60 | 61 | initial begin 62 | GSR_int = 1'b1; 63 | PRLD_int = 1'b1; 64 | #(ROC_WIDTH) 65 | GSR_int = 1'b0; 66 | PRLD_int = 1'b0; 67 | end 68 | 69 | initial begin 70 | GTS_int = 1'b1; 71 | #(TOC_WIDTH) 72 | GTS_int = 1'b0; 73 | end 74 | 75 | initial begin 76 | GRESTORE_int = 1'b0; 77 | #(GRES_START); 78 | GRESTORE_int = 1'b1; 79 | #(GRES_WIDTH); 80 | GRESTORE_int = 1'b0; 81 | end 82 | 83 | endmodule 84 | `endif 85 | -------------------------------------------------------------------------------- /CNN_Accelerator_Vivado_project/Accelerator.ip_user_files/sim_scripts/CNN_Module/modelsim/simulate.do: -------------------------------------------------------------------------------- 1 | onbreak {quit -f} 2 | onerror {quit -f} 3 | 4 | vsim -voptargs="+acc" -L xilinx_vip -L xpm -L xil_defaultlib -L axis_infrastructure_v1_1_0 -L axis_data_fifo_v2_0_8 -L xilinx_vip -L unisims_ver -L unimacro_ver -L secureip -lib xil_defaultlib xil_defaultlib.CNN_Module xil_defaultlib.glbl 5 | 6 | set NumericStdNoWarnings 1 7 | set StdArithNoWarnings 1 8 | 9 | do {wave.do} 10 | 11 | view wave 12 | view structure 13 | view signals 14 | 15 | do {CNN_Module.udo} 16 | 17 | run -all 18 | 19 | quit -force 20 | -------------------------------------------------------------------------------- /CNN_Accelerator_Vivado_project/Accelerator.ip_user_files/sim_scripts/CNN_Module/modelsim/wave.do: -------------------------------------------------------------------------------- 1 | add wave * 2 | add wave /glbl/GSR 3 | -------------------------------------------------------------------------------- /CNN_Accelerator_Vivado_project/Accelerator.ip_user_files/sim_scripts/CNN_Module/questa/CNN_Module.udo: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Futuresxy/General-CNN-Accelerator/09c07c86f0b739fc420f5e620bc1d10288eb774d/CNN_Accelerator_Vivado_project/Accelerator.ip_user_files/sim_scripts/CNN_Module/questa/CNN_Module.udo -------------------------------------------------------------------------------- /CNN_Accelerator_Vivado_project/Accelerator.ip_user_files/sim_scripts/CNN_Module/questa/README.txt: -------------------------------------------------------------------------------- 1 | ################################################################################ 2 | # Vivado (TM) v2022.1 (64-bit) 3 | # 4 | # README.txt: Please read the sections below to understand the steps required to 5 | # run the exported script and information about the source files. 6 | # 7 | # Generated by export_simulation on Sun Feb 09 15:31:56 +0800 2025 8 | # 9 | ################################################################################ 10 | 11 | 1. How to run the generated simulation script:- 12 | 13 | From the shell prompt in the current directory, issue the following command:- 14 | 15 | ./CNN_Module.sh 16 | 17 | This command will launch the 'compile', 'elaborate' and 'simulate' functions 18 | implemented in the script file for the 3-step flow. These functions are called 19 | from the main 'run' function in the script file. 20 | 21 | The 'run' function first executes the 'setup' function, the purpose of which is to 22 | create simulator specific setup files, create design library mappings and library 23 | directories and copy 'glbl.v' from the Vivado software install location into the 24 | current directory. 25 | 26 | The 'setup' function is also used for removing the simulator generated data in 27 | order to reset the current directory to the original state when export_simulation 28 | was launched from Vivado. This generated data can be removed by specifying the 29 | '-reset_run' switch to the './CNN_Module.sh' script. 30 | 31 | ./CNN_Module.sh -reset_run 32 | 33 | To keep the generated data from the previous run but regenerate the setup files and 34 | library directories, use the '-noclean_files' switch. 35 | 36 | ./CNN_Module.sh -noclean_files 37 | 38 | For more information on the script, please type './CNN_Module.sh -help'. 39 | 40 | 2. Additional design information files:- 41 | 42 | export_simulation generates following additional file that can be used for fetching 43 | the design files information or for integrating with external custom scripts. 44 | 45 | Name : file_info.txt 46 | Purpose: This file contains detail design file information based on the compile order 47 | when export_simulation was executed from Vivado. The file contains information 48 | about the file type, name, whether it is part of the IP, associated library 49 | and the file path information. 50 | -------------------------------------------------------------------------------- /CNN_Accelerator_Vivado_project/Accelerator.ip_user_files/sim_scripts/CNN_Module/questa/elaborate.do: -------------------------------------------------------------------------------- 1 | vopt +acc=npr -l elaborate.log -L xil_defaultlib -L xilinx_vip -L xpm -L axis_infrastructure_v1_1_0 -L axis_data_fifo_v2_0_8 -L xilinx_vip -L unisims_ver -L unimacro_ver -L secureip -work xil_defaultlib xil_defaultlib.CNN_Module xil_defaultlib.glbl -o CNN_Module_opt 2 | -------------------------------------------------------------------------------- /CNN_Accelerator_Vivado_project/Accelerator.ip_user_files/sim_scripts/CNN_Module/questa/glbl.v: -------------------------------------------------------------------------------- 1 | // $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ 2 | `ifndef GLBL 3 | `define GLBL 4 | `timescale 1 ps / 1 ps 5 | 6 | module glbl (); 7 | 8 | parameter ROC_WIDTH = 100000; 9 | parameter TOC_WIDTH = 0; 10 | parameter GRES_WIDTH = 10000; 11 | parameter GRES_START = 10000; 12 | 13 | //-------- STARTUP Globals -------------- 14 | wire GSR; 15 | wire GTS; 16 | wire GWE; 17 | wire PRLD; 18 | wire GRESTORE; 19 | tri1 p_up_tmp; 20 | tri (weak1, strong0) PLL_LOCKG = p_up_tmp; 21 | 22 | wire PROGB_GLBL; 23 | wire CCLKO_GLBL; 24 | wire FCSBO_GLBL; 25 | wire [3:0] DO_GLBL; 26 | wire [3:0] DI_GLBL; 27 | 28 | reg GSR_int; 29 | reg GTS_int; 30 | reg PRLD_int; 31 | reg GRESTORE_int; 32 | 33 | //-------- JTAG Globals -------------- 34 | wire JTAG_TDO_GLBL; 35 | wire JTAG_TCK_GLBL; 36 | wire JTAG_TDI_GLBL; 37 | wire JTAG_TMS_GLBL; 38 | wire JTAG_TRST_GLBL; 39 | 40 | reg JTAG_CAPTURE_GLBL; 41 | reg JTAG_RESET_GLBL; 42 | reg JTAG_SHIFT_GLBL; 43 | reg JTAG_UPDATE_GLBL; 44 | reg JTAG_RUNTEST_GLBL; 45 | 46 | reg JTAG_SEL1_GLBL = 0; 47 | reg JTAG_SEL2_GLBL = 0 ; 48 | reg JTAG_SEL3_GLBL = 0; 49 | reg JTAG_SEL4_GLBL = 0; 50 | 51 | reg JTAG_USER_TDO1_GLBL = 1'bz; 52 | reg JTAG_USER_TDO2_GLBL = 1'bz; 53 | reg JTAG_USER_TDO3_GLBL = 1'bz; 54 | reg JTAG_USER_TDO4_GLBL = 1'bz; 55 | 56 | assign (strong1, weak0) GSR = GSR_int; 57 | assign (strong1, weak0) GTS = GTS_int; 58 | assign (weak1, weak0) PRLD = PRLD_int; 59 | assign (strong1, weak0) GRESTORE = GRESTORE_int; 60 | 61 | initial begin 62 | GSR_int = 1'b1; 63 | PRLD_int = 1'b1; 64 | #(ROC_WIDTH) 65 | GSR_int = 1'b0; 66 | PRLD_int = 1'b0; 67 | end 68 | 69 | initial begin 70 | GTS_int = 1'b1; 71 | #(TOC_WIDTH) 72 | GTS_int = 1'b0; 73 | end 74 | 75 | initial begin 76 | GRESTORE_int = 1'b0; 77 | #(GRES_START); 78 | GRESTORE_int = 1'b1; 79 | #(GRES_WIDTH); 80 | GRESTORE_int = 1'b0; 81 | end 82 | 83 | endmodule 84 | `endif 85 | -------------------------------------------------------------------------------- /CNN_Accelerator_Vivado_project/Accelerator.ip_user_files/sim_scripts/CNN_Module/questa/simulate.do: -------------------------------------------------------------------------------- 1 | onbreak {quit -f} 2 | onerror {quit -f} 3 | 4 | vsim -lib xil_defaultlib CNN_Module_opt 5 | 6 | set NumericStdNoWarnings 1 7 | set StdArithNoWarnings 1 8 | 9 | do {wave.do} 10 | 11 | view wave 12 | view structure 13 | view signals 14 | 15 | do {CNN_Module.udo} 16 | 17 | run -all 18 | 19 | quit -force 20 | -------------------------------------------------------------------------------- /CNN_Accelerator_Vivado_project/Accelerator.ip_user_files/sim_scripts/CNN_Module/questa/wave.do: -------------------------------------------------------------------------------- 1 | add wave * 2 | add wave /glbl/GSR 3 | -------------------------------------------------------------------------------- /CNN_Accelerator_Vivado_project/Accelerator.ip_user_files/sim_scripts/CNN_Module/riviera/CNN_Module.udo: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Futuresxy/General-CNN-Accelerator/09c07c86f0b739fc420f5e620bc1d10288eb774d/CNN_Accelerator_Vivado_project/Accelerator.ip_user_files/sim_scripts/CNN_Module/riviera/CNN_Module.udo -------------------------------------------------------------------------------- /CNN_Accelerator_Vivado_project/Accelerator.ip_user_files/sim_scripts/CNN_Module/riviera/README.txt: -------------------------------------------------------------------------------- 1 | ################################################################################ 2 | # Vivado (TM) v2022.1 (64-bit) 3 | # 4 | # README.txt: Please read the sections below to understand the steps required to 5 | # run the exported script and information about the source files. 6 | # 7 | # Generated by export_simulation on Sun Feb 09 15:31:56 +0800 2025 8 | # 9 | ################################################################################ 10 | 11 | 1. How to run the generated simulation script:- 12 | 13 | From the shell prompt in the current directory, issue the following command:- 14 | 15 | ./CNN_Module.sh 16 | 17 | This command will launch the 'compile', 'elaborate' and 'simulate' functions 18 | implemented in the script file for the 3-step flow. These functions are called 19 | from the main 'run' function in the script file. 20 | 21 | The 'run' function first executes the 'setup' function, the purpose of which is to 22 | create simulator specific setup files, create design library mappings and library 23 | directories and copy 'glbl.v' from the Vivado software install location into the 24 | current directory. 25 | 26 | The 'setup' function is also used for removing the simulator generated data in 27 | order to reset the current directory to the original state when export_simulation 28 | was launched from Vivado. This generated data can be removed by specifying the 29 | '-reset_run' switch to the './CNN_Module.sh' script. 30 | 31 | ./CNN_Module.sh -reset_run 32 | 33 | To keep the generated data from the previous run but regenerate the setup files and 34 | library directories, use the '-noclean_files' switch. 35 | 36 | ./CNN_Module.sh -noclean_files 37 | 38 | For more information on the script, please type './CNN_Module.sh -help'. 39 | 40 | 2. Additional design information files:- 41 | 42 | export_simulation generates following additional file that can be used for fetching 43 | the design files information or for integrating with external custom scripts. 44 | 45 | Name : file_info.txt 46 | Purpose: This file contains detail design file information based on the compile order 47 | when export_simulation was executed from Vivado. The file contains information 48 | about the file type, name, whether it is part of the IP, associated library 49 | and the file path information. 50 | -------------------------------------------------------------------------------- /CNN_Accelerator_Vivado_project/Accelerator.ip_user_files/sim_scripts/CNN_Module/riviera/glbl.v: -------------------------------------------------------------------------------- 1 | // $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ 2 | `ifndef GLBL 3 | `define GLBL 4 | `timescale 1 ps / 1 ps 5 | 6 | module glbl (); 7 | 8 | parameter ROC_WIDTH = 100000; 9 | parameter TOC_WIDTH = 0; 10 | parameter GRES_WIDTH = 10000; 11 | parameter GRES_START = 10000; 12 | 13 | //-------- STARTUP Globals -------------- 14 | wire GSR; 15 | wire GTS; 16 | wire GWE; 17 | wire PRLD; 18 | wire GRESTORE; 19 | tri1 p_up_tmp; 20 | tri (weak1, strong0) PLL_LOCKG = p_up_tmp; 21 | 22 | wire PROGB_GLBL; 23 | wire CCLKO_GLBL; 24 | wire FCSBO_GLBL; 25 | wire [3:0] DO_GLBL; 26 | wire [3:0] DI_GLBL; 27 | 28 | reg GSR_int; 29 | reg GTS_int; 30 | reg PRLD_int; 31 | reg GRESTORE_int; 32 | 33 | //-------- JTAG Globals -------------- 34 | wire JTAG_TDO_GLBL; 35 | wire JTAG_TCK_GLBL; 36 | wire JTAG_TDI_GLBL; 37 | wire JTAG_TMS_GLBL; 38 | wire JTAG_TRST_GLBL; 39 | 40 | reg JTAG_CAPTURE_GLBL; 41 | reg JTAG_RESET_GLBL; 42 | reg JTAG_SHIFT_GLBL; 43 | reg JTAG_UPDATE_GLBL; 44 | reg JTAG_RUNTEST_GLBL; 45 | 46 | reg JTAG_SEL1_GLBL = 0; 47 | reg JTAG_SEL2_GLBL = 0 ; 48 | reg JTAG_SEL3_GLBL = 0; 49 | reg JTAG_SEL4_GLBL = 0; 50 | 51 | reg JTAG_USER_TDO1_GLBL = 1'bz; 52 | reg JTAG_USER_TDO2_GLBL = 1'bz; 53 | reg JTAG_USER_TDO3_GLBL = 1'bz; 54 | reg JTAG_USER_TDO4_GLBL = 1'bz; 55 | 56 | assign (strong1, weak0) GSR = GSR_int; 57 | assign (strong1, weak0) GTS = GTS_int; 58 | assign (weak1, weak0) PRLD = PRLD_int; 59 | assign (strong1, weak0) GRESTORE = GRESTORE_int; 60 | 61 | initial begin 62 | GSR_int = 1'b1; 63 | PRLD_int = 1'b1; 64 | #(ROC_WIDTH) 65 | GSR_int = 1'b0; 66 | PRLD_int = 1'b0; 67 | end 68 | 69 | initial begin 70 | GTS_int = 1'b1; 71 | #(TOC_WIDTH) 72 | GTS_int = 1'b0; 73 | end 74 | 75 | initial begin 76 | GRESTORE_int = 1'b0; 77 | #(GRES_START); 78 | GRESTORE_int = 1'b1; 79 | #(GRES_WIDTH); 80 | GRESTORE_int = 1'b0; 81 | end 82 | 83 | endmodule 84 | `endif 85 | -------------------------------------------------------------------------------- /CNN_Accelerator_Vivado_project/Accelerator.ip_user_files/sim_scripts/CNN_Module/riviera/simulate.do: -------------------------------------------------------------------------------- 1 | onbreak {quit -force} 2 | onerror {quit -force} 3 | 4 | asim +access +r +m+CNN_Module -L xilinx_vip -L xpm -L xil_defaultlib -L axis_infrastructure_v1_1_0 -L axis_data_fifo_v2_0_8 -L xilinx_vip -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.CNN_Module xil_defaultlib.glbl 5 | 6 | set NumericStdNoWarnings 1 7 | set StdArithNoWarnings 1 8 | 9 | do {wave.do} 10 | 11 | view wave 12 | view structure 13 | 14 | do {CNN_Module.udo} 15 | 16 | run -all 17 | 18 | endsim 19 | 20 | quit -force 21 | -------------------------------------------------------------------------------- /CNN_Accelerator_Vivado_project/Accelerator.ip_user_files/sim_scripts/CNN_Module/riviera/wave.do: -------------------------------------------------------------------------------- 1 | add wave * 2 | add wave /glbl/GSR 3 | -------------------------------------------------------------------------------- /CNN_Accelerator_Vivado_project/Accelerator.ip_user_files/sim_scripts/CNN_Module/vcs/README.txt: -------------------------------------------------------------------------------- 1 | ################################################################################ 2 | # Vivado (TM) v2022.1 (64-bit) 3 | # 4 | # README.txt: Please read the sections below to understand the steps required to 5 | # run the exported script and information about the source files. 6 | # 7 | # Generated by export_simulation on Sun Feb 09 15:31:56 +0800 2025 8 | # 9 | ################################################################################ 10 | 11 | 1. How to run the generated simulation script:- 12 | 13 | From the shell prompt in the current directory, issue the following command:- 14 | 15 | ./CNN_Module.sh 16 | 17 | This command will launch the 'compile', 'elaborate' and 'simulate' functions 18 | implemented in the script file for the 3-step flow. These functions are called 19 | from the main 'run' function in the script file. 20 | 21 | The 'run' function first executes the 'setup' function, the purpose of which is to 22 | create simulator specific setup files, create design library mappings and library 23 | directories and copy 'glbl.v' from the Vivado software install location into the 24 | current directory. 25 | 26 | The 'setup' function is also used for removing the simulator generated data in 27 | order to reset the current directory to the original state when export_simulation 28 | was launched from Vivado. This generated data can be removed by specifying the 29 | '-reset_run' switch to the './CNN_Module.sh' script. 30 | 31 | ./CNN_Module.sh -reset_run 32 | 33 | To keep the generated data from the previous run but regenerate the setup files and 34 | library directories, use the '-noclean_files' switch. 35 | 36 | ./CNN_Module.sh -noclean_files 37 | 38 | For more information on the script, please type './CNN_Module.sh -help'. 39 | 40 | 2. Additional design information files:- 41 | 42 | export_simulation generates following additional file that can be used for fetching 43 | the design files information or for integrating with external custom scripts. 44 | 45 | Name : file_info.txt 46 | Purpose: This file contains detail design file information based on the compile order 47 | when export_simulation was executed from Vivado. The file contains information 48 | about the file type, name, whether it is part of the IP, associated library 49 | and the file path information. 50 | -------------------------------------------------------------------------------- /CNN_Accelerator_Vivado_project/Accelerator.ip_user_files/sim_scripts/CNN_Module/vcs/glbl.v: -------------------------------------------------------------------------------- 1 | // $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ 2 | `ifndef GLBL 3 | `define GLBL 4 | `timescale 1 ps / 1 ps 5 | 6 | module glbl (); 7 | 8 | parameter ROC_WIDTH = 100000; 9 | parameter TOC_WIDTH = 0; 10 | parameter GRES_WIDTH = 10000; 11 | parameter GRES_START = 10000; 12 | 13 | //-------- STARTUP Globals -------------- 14 | wire GSR; 15 | wire GTS; 16 | wire GWE; 17 | wire PRLD; 18 | wire GRESTORE; 19 | tri1 p_up_tmp; 20 | tri (weak1, strong0) PLL_LOCKG = p_up_tmp; 21 | 22 | wire PROGB_GLBL; 23 | wire CCLKO_GLBL; 24 | wire FCSBO_GLBL; 25 | wire [3:0] DO_GLBL; 26 | wire [3:0] DI_GLBL; 27 | 28 | reg GSR_int; 29 | reg GTS_int; 30 | reg PRLD_int; 31 | reg GRESTORE_int; 32 | 33 | //-------- JTAG Globals -------------- 34 | wire JTAG_TDO_GLBL; 35 | wire JTAG_TCK_GLBL; 36 | wire JTAG_TDI_GLBL; 37 | wire JTAG_TMS_GLBL; 38 | wire JTAG_TRST_GLBL; 39 | 40 | reg JTAG_CAPTURE_GLBL; 41 | reg JTAG_RESET_GLBL; 42 | reg JTAG_SHIFT_GLBL; 43 | reg JTAG_UPDATE_GLBL; 44 | reg JTAG_RUNTEST_GLBL; 45 | 46 | reg JTAG_SEL1_GLBL = 0; 47 | reg JTAG_SEL2_GLBL = 0 ; 48 | reg JTAG_SEL3_GLBL = 0; 49 | reg JTAG_SEL4_GLBL = 0; 50 | 51 | reg JTAG_USER_TDO1_GLBL = 1'bz; 52 | reg JTAG_USER_TDO2_GLBL = 1'bz; 53 | reg JTAG_USER_TDO3_GLBL = 1'bz; 54 | reg JTAG_USER_TDO4_GLBL = 1'bz; 55 | 56 | assign (strong1, weak0) GSR = GSR_int; 57 | assign (strong1, weak0) GTS = GTS_int; 58 | assign (weak1, weak0) PRLD = PRLD_int; 59 | assign (strong1, weak0) GRESTORE = GRESTORE_int; 60 | 61 | initial begin 62 | GSR_int = 1'b1; 63 | PRLD_int = 1'b1; 64 | #(ROC_WIDTH) 65 | GSR_int = 1'b0; 66 | PRLD_int = 1'b0; 67 | end 68 | 69 | initial begin 70 | GTS_int = 1'b1; 71 | #(TOC_WIDTH) 72 | GTS_int = 1'b0; 73 | end 74 | 75 | initial begin 76 | GRESTORE_int = 1'b0; 77 | #(GRES_START); 78 | GRESTORE_int = 1'b1; 79 | #(GRES_WIDTH); 80 | GRESTORE_int = 1'b0; 81 | end 82 | 83 | endmodule 84 | `endif 85 | -------------------------------------------------------------------------------- /CNN_Accelerator_Vivado_project/Accelerator.ip_user_files/sim_scripts/CNN_Module/vcs/simulate.do: -------------------------------------------------------------------------------- 1 | run 2 | quit 3 | -------------------------------------------------------------------------------- /CNN_Accelerator_Vivado_project/Accelerator.ip_user_files/sim_scripts/CNN_Module/xcelium/README.txt: -------------------------------------------------------------------------------- 1 | ################################################################################ 2 | # Vivado (TM) v2022.1 (64-bit) 3 | # 4 | # README.txt: Please read the sections below to understand the steps required to 5 | # run the exported script and information about the source files. 6 | # 7 | # Generated by export_simulation on Sun Feb 09 15:31:56 +0800 2025 8 | # 9 | ################################################################################ 10 | 11 | 1. How to run the generated simulation script:- 12 | 13 | From the shell prompt in the current directory, issue the following command:- 14 | 15 | ./CNN_Module.sh 16 | 17 | This command will launch the 'execute' function for the single-step flow. This 18 | function is called from the main 'run' function in the script file. 19 | 20 | The 'run' function first executes the 'setup' function, the purpose of which is to 21 | create simulator specific setup files, create design library mappings and library 22 | directories and copy 'glbl.v' from the Vivado software install location into the 23 | current directory. 24 | 25 | The 'setup' function is also used for removing the simulator generated data in 26 | order to reset the current directory to the original state when export_simulation 27 | was launched from Vivado. This generated data can be removed by specifying the 28 | '-reset_run' switch to the './CNN_Module.sh' script. 29 | 30 | ./CNN_Module.sh -reset_run 31 | 32 | To keep the generated data from the previous run but regenerate the setup files and 33 | library directories, use the '-noclean_files' switch. 34 | 35 | ./CNN_Module.sh -noclean_files 36 | 37 | For more information on the script, please type './CNN_Module.sh -help'. 38 | 39 | 2. Additional design information files:- 40 | 41 | export_simulation generates following additional file that can be used for fetching 42 | the design files information or for integrating with external custom scripts. 43 | 44 | Name : file_info.txt 45 | Purpose: This file contains detail design file information based on the compile order 46 | when export_simulation was executed from Vivado. The file contains information 47 | about the file type, name, whether it is part of the IP, associated library 48 | and the file path information. 49 | -------------------------------------------------------------------------------- /CNN_Accelerator_Vivado_project/Accelerator.ip_user_files/sim_scripts/CNN_Module/xcelium/glbl.v: -------------------------------------------------------------------------------- 1 | // $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ 2 | `ifndef GLBL 3 | `define GLBL 4 | `timescale 1 ps / 1 ps 5 | 6 | module glbl (); 7 | 8 | parameter ROC_WIDTH = 100000; 9 | parameter TOC_WIDTH = 0; 10 | parameter GRES_WIDTH = 10000; 11 | parameter GRES_START = 10000; 12 | 13 | //-------- STARTUP Globals -------------- 14 | wire GSR; 15 | wire GTS; 16 | wire GWE; 17 | wire PRLD; 18 | wire GRESTORE; 19 | tri1 p_up_tmp; 20 | tri (weak1, strong0) PLL_LOCKG = p_up_tmp; 21 | 22 | wire PROGB_GLBL; 23 | wire CCLKO_GLBL; 24 | wire FCSBO_GLBL; 25 | wire [3:0] DO_GLBL; 26 | wire [3:0] DI_GLBL; 27 | 28 | reg GSR_int; 29 | reg GTS_int; 30 | reg PRLD_int; 31 | reg GRESTORE_int; 32 | 33 | //-------- JTAG Globals -------------- 34 | wire JTAG_TDO_GLBL; 35 | wire JTAG_TCK_GLBL; 36 | wire JTAG_TDI_GLBL; 37 | wire JTAG_TMS_GLBL; 38 | wire JTAG_TRST_GLBL; 39 | 40 | reg JTAG_CAPTURE_GLBL; 41 | reg JTAG_RESET_GLBL; 42 | reg JTAG_SHIFT_GLBL; 43 | reg JTAG_UPDATE_GLBL; 44 | reg JTAG_RUNTEST_GLBL; 45 | 46 | reg JTAG_SEL1_GLBL = 0; 47 | reg JTAG_SEL2_GLBL = 0 ; 48 | reg JTAG_SEL3_GLBL = 0; 49 | reg JTAG_SEL4_GLBL = 0; 50 | 51 | reg JTAG_USER_TDO1_GLBL = 1'bz; 52 | reg JTAG_USER_TDO2_GLBL = 1'bz; 53 | reg JTAG_USER_TDO3_GLBL = 1'bz; 54 | reg JTAG_USER_TDO4_GLBL = 1'bz; 55 | 56 | assign (strong1, weak0) GSR = GSR_int; 57 | assign (strong1, weak0) GTS = GTS_int; 58 | assign (weak1, weak0) PRLD = PRLD_int; 59 | assign (strong1, weak0) GRESTORE = GRESTORE_int; 60 | 61 | initial begin 62 | GSR_int = 1'b1; 63 | PRLD_int = 1'b1; 64 | #(ROC_WIDTH) 65 | GSR_int = 1'b0; 66 | PRLD_int = 1'b0; 67 | end 68 | 69 | initial begin 70 | GTS_int = 1'b1; 71 | #(TOC_WIDTH) 72 | GTS_int = 1'b0; 73 | end 74 | 75 | initial begin 76 | GRESTORE_int = 1'b0; 77 | #(GRES_START); 78 | GRESTORE_int = 1'b1; 79 | #(GRES_WIDTH); 80 | GRESTORE_int = 1'b0; 81 | end 82 | 83 | endmodule 84 | `endif 85 | -------------------------------------------------------------------------------- /CNN_Accelerator_Vivado_project/Accelerator.ip_user_files/sim_scripts/CNN_Module/xcelium/run.f: -------------------------------------------------------------------------------- 1 | -makelib xcelium_lib/xilinx_vip -sv \ 2 | "F:/Xilinx/Vivado/2022.1/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv" \ 3 | "F:/Xilinx/Vivado/2022.1/data/xilinx_vip/hdl/axi_vip_axi4pc.sv" \ 4 | "F:/Xilinx/Vivado/2022.1/data/xilinx_vip/hdl/xil_common_vip_pkg.sv" \ 5 | "F:/Xilinx/Vivado/2022.1/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv" \ 6 | "F:/Xilinx/Vivado/2022.1/data/xilinx_vip/hdl/axi_vip_pkg.sv" \ 7 | "F:/Xilinx/Vivado/2022.1/data/xilinx_vip/hdl/axi4stream_vip_if.sv" \ 8 | "F:/Xilinx/Vivado/2022.1/data/xilinx_vip/hdl/axi_vip_if.sv" \ 9 | "F:/Xilinx/Vivado/2022.1/data/xilinx_vip/hdl/clk_vip_if.sv" \ 10 | "F:/Xilinx/Vivado/2022.1/data/xilinx_vip/hdl/rst_vip_if.sv" \ 11 | -endlib 12 | -makelib xcelium_lib/xpm -sv \ 13 | "F:/Xilinx/Vivado/2022.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ 14 | "F:/Xilinx/Vivado/2022.1/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \ 15 | "F:/Xilinx/Vivado/2022.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ 16 | -endlib 17 | -makelib xcelium_lib/xpm \ 18 | "F:/Xilinx/Vivado/2022.1/data/ip/xpm/xpm_VCOMP.vhd" \ 19 | -endlib 20 | -makelib xcelium_lib/xil_defaultlib \ 21 | "../../../bd/CNN_Module/ip/CNN_Module_CNN_Control_1_0/sim/CNN_Module_CNN_Control_1_0.v" \ 22 | -endlib 23 | -makelib xcelium_lib/axis_infrastructure_v1_1_0 \ 24 | "../../../../Accelerator.gen/sources_1/bd/CNN_Module/ipshared/8713/hdl/axis_infrastructure_v1_1_vl_rfs.v" \ 25 | -endlib 26 | -makelib xcelium_lib/axis_data_fifo_v2_0_8 \ 27 | "../../../../Accelerator.gen/sources_1/bd/CNN_Module/ipshared/0bd2/hdl/axis_data_fifo_v2_0_vl_rfs.v" \ 28 | -endlib 29 | -makelib xcelium_lib/xil_defaultlib \ 30 | "../../../bd/CNN_Module/ip/CNN_Module_INACT_DATA_FIFO_0/sim/CNN_Module_INACT_DATA_FIFO_0.v" \ 31 | "../../../bd/CNN_Module/ip/CNN_Module_PICTURE_DATA_FIFO_0/sim/CNN_Module_PICTURE_DATA_FIFO_0.v" \ 32 | "../../../bd/CNN_Module/ip/CNN_Module_RESULT_DATA_FIFO1_0/sim/CNN_Module_RESULT_DATA_FIFO1_0.v" \ 33 | "../../../bd/CNN_Module/ip/CNN_Module_WEIGHT_CONV_ACT_FULLCON_FIFO_0/sim/CNN_Module_WEIGHT_CONV_ACT_FULLCON_FIFO_0.v" \ 34 | "../../../bd/CNN_Module/ip/CNN_Module_WEIGHT_FULLCON_FIFO_0/sim/CNN_Module_WEIGHT_FULLCON_FIFO_0.v" \ 35 | "../../../bd/CNN_Module/ip/CNN_Module_Windows_Data_Convert_0_0/sim/CNN_Module_Windows_Data_Convert_0_0.v" \ 36 | "../../../bd/CNN_Module/sim/CNN_Module.v" \ 37 | -endlib 38 | -makelib xcelium_lib/xil_defaultlib \ 39 | glbl.v 40 | -endlib 41 | 42 | -------------------------------------------------------------------------------- /CNN_Accelerator_Vivado_project/Accelerator.ip_user_files/sim_scripts/CNN_Module/xsim/README.txt: -------------------------------------------------------------------------------- 1 | ################################################################################ 2 | # Vivado (TM) v2022.1 (64-bit) 3 | # 4 | # README.txt: Please read the sections below to understand the steps required to 5 | # run the exported script and information about the source files. 6 | # 7 | # Generated by export_simulation on Sun Feb 09 15:31:56 +0800 2025 8 | # 9 | ################################################################################ 10 | 11 | 1. How to run the generated simulation script:- 12 | 13 | From the shell prompt in the current directory, issue the following command:- 14 | 15 | ./CNN_Module.sh 16 | 17 | This command will launch the 'compile', 'elaborate' and 'simulate' functions 18 | implemented in the script file for the 3-step flow. These functions are called 19 | from the main 'run' function in the script file. 20 | 21 | The 'run' function first executes the 'setup' function, the purpose of which is to 22 | create simulator specific setup files, create design library mappings and library 23 | directories and copy 'glbl.v' from the Vivado software install location into the 24 | current directory. 25 | 26 | The 'setup' function is also used for removing the simulator generated data in 27 | order to reset the current directory to the original state when export_simulation 28 | was launched from Vivado. This generated data can be removed by specifying the 29 | '-reset_run' switch to the './CNN_Module.sh' script. 30 | 31 | ./CNN_Module.sh -reset_run 32 | 33 | To keep the generated data from the previous run but regenerate the setup files and 34 | library directories, use the '-noclean_files' switch. 35 | 36 | ./CNN_Module.sh -noclean_files 37 | 38 | For more information on the script, please type './CNN_Module.sh -help'. 39 | 40 | 2. Additional design information files:- 41 | 42 | export_simulation generates following additional file that can be used for fetching 43 | the design files information or for integrating with external custom scripts. 44 | 45 | Name : file_info.txt 46 | Purpose: This file contains detail design file information based on the compile order 47 | when export_simulation was executed from Vivado. The file contains information 48 | about the file type, name, whether it is part of the IP, associated library 49 | and the file path information. 50 | -------------------------------------------------------------------------------- /CNN_Accelerator_Vivado_project/Accelerator.ip_user_files/sim_scripts/CNN_Module/xsim/cmd.tcl: -------------------------------------------------------------------------------- 1 | set curr_wave [current_wave_config] 2 | if { [string length $curr_wave] == 0 } { 3 | if { [llength [get_objects]] > 0} { 4 | add_wave / 5 | set_property needs_save false [current_wave_config] 6 | } else { 7 | send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." 8 | } 9 | } 10 | 11 | run -all 12 | quit 13 | -------------------------------------------------------------------------------- /CNN_Accelerator_Vivado_project/Accelerator.ip_user_files/sim_scripts/CNN_Module/xsim/elab.opt: -------------------------------------------------------------------------------- 1 | --incr --debug typical --relax --mt auto -L xil_defaultlib -L axis_infrastructure_v1_1_0 -L axis_data_fifo_v2_0_8 -L xilinx_vip -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot CNN_Module xil_defaultlib.CNN_Module xil_defaultlib.glbl -log elaborate.log 2 | -------------------------------------------------------------------------------- /CNN_Accelerator_Vivado_project/Accelerator.ip_user_files/sim_scripts/CNN_Module/xsim/file_info.txt: -------------------------------------------------------------------------------- 1 | CNN_Module_CNN_Control_1_0.v,verilog,xil_defaultlib,../../../bd/CNN_Module/ip/CNN_Module_CNN_Control_1_0/sim/CNN_Module_CNN_Control_1_0.v,incdir="$ref_dir/../../../../Accelerator.gen/sources_1/bd/CNN_Module/ipshared/8713/hdl"incdir="../../../../Accelerator.gen/sources_1/bd/CNN_Module/ipshared/8713/hdl" 2 | CNN_Module_INACT_DATA_FIFO_0.v,verilog,xil_defaultlib,../../../bd/CNN_Module/ip/CNN_Module_INACT_DATA_FIFO_0/sim/CNN_Module_INACT_DATA_FIFO_0.v,incdir="$ref_dir/../../../../Accelerator.gen/sources_1/bd/CNN_Module/ipshared/8713/hdl"incdir="../../../../Accelerator.gen/sources_1/bd/CNN_Module/ipshared/8713/hdl" 3 | CNN_Module_PICTURE_DATA_FIFO_0.v,verilog,xil_defaultlib,../../../bd/CNN_Module/ip/CNN_Module_PICTURE_DATA_FIFO_0/sim/CNN_Module_PICTURE_DATA_FIFO_0.v,incdir="$ref_dir/../../../../Accelerator.gen/sources_1/bd/CNN_Module/ipshared/8713/hdl"incdir="../../../../Accelerator.gen/sources_1/bd/CNN_Module/ipshared/8713/hdl" 4 | CNN_Module_RESULT_DATA_FIFO1_0.v,verilog,xil_defaultlib,../../../bd/CNN_Module/ip/CNN_Module_RESULT_DATA_FIFO1_0/sim/CNN_Module_RESULT_DATA_FIFO1_0.v,incdir="$ref_dir/../../../../Accelerator.gen/sources_1/bd/CNN_Module/ipshared/8713/hdl"incdir="../../../../Accelerator.gen/sources_1/bd/CNN_Module/ipshared/8713/hdl" 5 | CNN_Module_WEIGHT_CONV_ACT_FULLCON_FIFO_0.v,verilog,xil_defaultlib,../../../bd/CNN_Module/ip/CNN_Module_WEIGHT_CONV_ACT_FULLCON_FIFO_0/sim/CNN_Module_WEIGHT_CONV_ACT_FULLCON_FIFO_0.v,incdir="$ref_dir/../../../../Accelerator.gen/sources_1/bd/CNN_Module/ipshared/8713/hdl"incdir="../../../../Accelerator.gen/sources_1/bd/CNN_Module/ipshared/8713/hdl" 6 | CNN_Module_WEIGHT_FULLCON_FIFO_0.v,verilog,xil_defaultlib,../../../bd/CNN_Module/ip/CNN_Module_WEIGHT_FULLCON_FIFO_0/sim/CNN_Module_WEIGHT_FULLCON_FIFO_0.v,incdir="$ref_dir/../../../../Accelerator.gen/sources_1/bd/CNN_Module/ipshared/8713/hdl"incdir="../../../../Accelerator.gen/sources_1/bd/CNN_Module/ipshared/8713/hdl" 7 | CNN_Module_Windows_Data_Convert_0_0.v,verilog,xil_defaultlib,../../../bd/CNN_Module/ip/CNN_Module_Windows_Data_Convert_0_0/sim/CNN_Module_Windows_Data_Convert_0_0.v,incdir="$ref_dir/../../../../Accelerator.gen/sources_1/bd/CNN_Module/ipshared/8713/hdl"incdir="../../../../Accelerator.gen/sources_1/bd/CNN_Module/ipshared/8713/hdl" 8 | CNN_Module.v,verilog,xil_defaultlib,../../../bd/CNN_Module/sim/CNN_Module.v,incdir="$ref_dir/../../../../Accelerator.gen/sources_1/bd/CNN_Module/ipshared/8713/hdl"incdir="../../../../Accelerator.gen/sources_1/bd/CNN_Module/ipshared/8713/hdl" 9 | glbl.v,Verilog,xil_defaultlib,glbl.v 10 | -------------------------------------------------------------------------------- /CNN_Accelerator_Vivado_project/Accelerator.ip_user_files/sim_scripts/CNN_Module/xsim/glbl.v: -------------------------------------------------------------------------------- 1 | // $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ 2 | `ifndef GLBL 3 | `define GLBL 4 | `timescale 1 ps / 1 ps 5 | 6 | module glbl (); 7 | 8 | parameter ROC_WIDTH = 100000; 9 | parameter TOC_WIDTH = 0; 10 | parameter GRES_WIDTH = 10000; 11 | parameter GRES_START = 10000; 12 | 13 | //-------- STARTUP Globals -------------- 14 | wire GSR; 15 | wire GTS; 16 | wire GWE; 17 | wire PRLD; 18 | wire GRESTORE; 19 | tri1 p_up_tmp; 20 | tri (weak1, strong0) PLL_LOCKG = p_up_tmp; 21 | 22 | wire PROGB_GLBL; 23 | wire CCLKO_GLBL; 24 | wire FCSBO_GLBL; 25 | wire [3:0] DO_GLBL; 26 | wire [3:0] DI_GLBL; 27 | 28 | reg GSR_int; 29 | reg GTS_int; 30 | reg PRLD_int; 31 | reg GRESTORE_int; 32 | 33 | //-------- JTAG Globals -------------- 34 | wire JTAG_TDO_GLBL; 35 | wire JTAG_TCK_GLBL; 36 | wire JTAG_TDI_GLBL; 37 | wire JTAG_TMS_GLBL; 38 | wire JTAG_TRST_GLBL; 39 | 40 | reg JTAG_CAPTURE_GLBL; 41 | reg JTAG_RESET_GLBL; 42 | reg JTAG_SHIFT_GLBL; 43 | reg JTAG_UPDATE_GLBL; 44 | reg JTAG_RUNTEST_GLBL; 45 | 46 | reg JTAG_SEL1_GLBL = 0; 47 | reg JTAG_SEL2_GLBL = 0 ; 48 | reg JTAG_SEL3_GLBL = 0; 49 | reg JTAG_SEL4_GLBL = 0; 50 | 51 | reg JTAG_USER_TDO1_GLBL = 1'bz; 52 | reg JTAG_USER_TDO2_GLBL = 1'bz; 53 | reg JTAG_USER_TDO3_GLBL = 1'bz; 54 | reg JTAG_USER_TDO4_GLBL = 1'bz; 55 | 56 | assign (strong1, weak0) GSR = GSR_int; 57 | assign (strong1, weak0) GTS = GTS_int; 58 | assign (weak1, weak0) PRLD = PRLD_int; 59 | assign (strong1, weak0) GRESTORE = GRESTORE_int; 60 | 61 | initial begin 62 | GSR_int = 1'b1; 63 | PRLD_int = 1'b1; 64 | #(ROC_WIDTH) 65 | GSR_int = 1'b0; 66 | PRLD_int = 1'b0; 67 | end 68 | 69 | initial begin 70 | GTS_int = 1'b1; 71 | #(TOC_WIDTH) 72 | GTS_int = 1'b0; 73 | end 74 | 75 | initial begin 76 | GRESTORE_int = 1'b0; 77 | #(GRES_START); 78 | GRESTORE_int = 1'b1; 79 | #(GRES_WIDTH); 80 | GRESTORE_int = 1'b0; 81 | end 82 | 83 | endmodule 84 | `endif 85 | -------------------------------------------------------------------------------- /CNN_Accelerator_Vivado_project/Accelerator.ip_user_files/sim_scripts/CNN_Module/xsim/vlog.prj: -------------------------------------------------------------------------------- 1 | verilog xil_defaultlib --include "F:/Xilinx/Vivado/2022.1/data/xilinx_vip/include" --include "../../../../Accelerator.gen/sources_1/bd/CNN_Module/ipshared/8713/hdl" \ 2 | "../../../bd/CNN_Module/ip/CNN_Module_CNN_Control_1_0/sim/CNN_Module_CNN_Control_1_0.v" \ 3 | "../../../bd/CNN_Module/ip/CNN_Module_INACT_DATA_FIFO_0/sim/CNN_Module_INACT_DATA_FIFO_0.v" \ 4 | "../../../bd/CNN_Module/ip/CNN_Module_PICTURE_DATA_FIFO_0/sim/CNN_Module_PICTURE_DATA_FIFO_0.v" \ 5 | "../../../bd/CNN_Module/ip/CNN_Module_RESULT_DATA_FIFO1_0/sim/CNN_Module_RESULT_DATA_FIFO1_0.v" \ 6 | "../../../bd/CNN_Module/ip/CNN_Module_WEIGHT_CONV_ACT_FULLCON_FIFO_0/sim/CNN_Module_WEIGHT_CONV_ACT_FULLCON_FIFO_0.v" \ 7 | "../../../bd/CNN_Module/ip/CNN_Module_WEIGHT_FULLCON_FIFO_0/sim/CNN_Module_WEIGHT_FULLCON_FIFO_0.v" \ 8 | "../../../bd/CNN_Module/ip/CNN_Module_Windows_Data_Convert_0_0/sim/CNN_Module_Windows_Data_Convert_0_0.v" \ 9 | "../../../bd/CNN_Module/sim/CNN_Module.v" \ 10 | 11 | verilog xil_defaultlib "glbl.v" 12 | 13 | nosort 14 | -------------------------------------------------------------------------------- /CNN_Accelerator_Vivado_project/Accelerator.sim/sim_1/behav/xsim/CNN_Module_tb.tcl: -------------------------------------------------------------------------------- 1 | set curr_wave [current_wave_config] 2 | if { [string length $curr_wave] == 0 } { 3 | if { [llength [get_objects]] > 0} { 4 | add_wave / 5 | set_property needs_save false [current_wave_config] 6 | } else { 7 | send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." 8 | } 9 | } 10 | 11 | run 1000ns 12 | -------------------------------------------------------------------------------- /CNN_Accelerator_Vivado_project/Accelerator.sim/sim_1/behav/xsim/CNN_Module_tb_behav.wdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Futuresxy/General-CNN-Accelerator/09c07c86f0b739fc420f5e620bc1d10288eb774d/CNN_Accelerator_Vivado_project/Accelerator.sim/sim_1/behav/xsim/CNN_Module_tb_behav.wdb -------------------------------------------------------------------------------- /CNN_Accelerator_Vivado_project/Accelerator.sim/sim_1/behav/xsim/CNN_Module_tb_vhdl.prj: -------------------------------------------------------------------------------- 1 | # compile vhdl design source files 2 | vhdl xil_defaultlib \ 3 | "../../../../Accelerator.gen/sources_1/ip/div_gen_0/sim/div_gen_0.vhd" \ 4 | 5 | # Do not sort compile order 6 | nosort 7 | -------------------------------------------------------------------------------- /CNN_Accelerator_Vivado_project/Accelerator.sim/sim_1/behav/xsim/compile.bat: -------------------------------------------------------------------------------- 1 | @echo off 2 | REM **************************************************************************** 3 | REM Vivado (TM) v2022.1 (64-bit) 4 | REM 5 | REM Filename : compile.bat 6 | REM Simulator : Xilinx Vivado Simulator 7 | REM Description : Script for compiling the simulation design source files 8 | REM 9 | REM Generated by Vivado on Sun Feb 09 15:53:08 +0800 2025 10 | REM SW Build 3526262 on Mon Apr 18 15:48:16 MDT 2022 11 | REM 12 | REM IP Build 3524634 on Mon Apr 18 20:55:01 MDT 2022 13 | REM 14 | REM usage: compile.bat 15 | REM 16 | REM **************************************************************************** 17 | REM compile Verilog/System Verilog design sources 18 | echo "xvlog --incr --relax -L xilinx_vip -prj CNN_Module_tb_vlog.prj" 19 | call xvlog --incr --relax -L xilinx_vip -prj CNN_Module_tb_vlog.prj -log xvlog.log 20 | call type xvlog.log > compile.log 21 | REM compile VHDL design sources 22 | echo "xvhdl --incr --relax -prj CNN_Module_tb_vhdl.prj" 23 | call xvhdl --incr --relax -prj CNN_Module_tb_vhdl.prj -log xvhdl.log 24 | call type xvhdl.log >> compile.log 25 | if "%errorlevel%"=="1" goto END 26 | if "%errorlevel%"=="0" goto SUCCESS 27 | :END 28 | exit 1 29 | :SUCCESS 30 | exit 0 31 | -------------------------------------------------------------------------------- /CNN_Accelerator_Vivado_project/Accelerator.sim/sim_1/behav/xsim/elaborate.bat: -------------------------------------------------------------------------------- 1 | @echo off 2 | REM **************************************************************************** 3 | REM Vivado (TM) v2022.1 (64-bit) 4 | REM 5 | REM Filename : elaborate.bat 6 | REM Simulator : Xilinx Vivado Simulator 7 | REM Description : Script for elaborating the compiled design 8 | REM 9 | REM Generated by Vivado on Sun Feb 09 15:53:19 +0800 2025 10 | REM SW Build 3526262 on Mon Apr 18 15:48:16 MDT 2022 11 | REM 12 | REM IP Build 3524634 on Mon Apr 18 20:55:01 MDT 2022 13 | REM 14 | REM usage: elaborate.bat 15 | REM 16 | REM **************************************************************************** 17 | REM elaborate design 18 | echo "xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L xbip_pipe_v3_0_6 -L xbip_dsp48_wrapper_v3_0_4 -L xbip_dsp48_addsub_v3_0_6 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_18 -L floating_point_v7_0_20 -L xbip_dsp48_mult_v3_0_6 -L xbip_dsp48_multadd_v3_0_6 -L div_gen_v5_1_19 -L axis_infrastructure_v1_1_0 -L axis_data_fifo_v2_0_8 -L xilinx_vip -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot CNN_Module_tb_behav xil_defaultlib.CNN_Module_tb xil_defaultlib.glbl -log elaborate.log" 19 | call xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L xbip_pipe_v3_0_6 -L xbip_dsp48_wrapper_v3_0_4 -L xbip_dsp48_addsub_v3_0_6 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_18 -L floating_point_v7_0_20 -L xbip_dsp48_mult_v3_0_6 -L xbip_dsp48_multadd_v3_0_6 -L div_gen_v5_1_19 -L axis_infrastructure_v1_1_0 -L axis_data_fifo_v2_0_8 -L xilinx_vip -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot CNN_Module_tb_behav xil_defaultlib.CNN_Module_tb xil_defaultlib.glbl -log elaborate.log 20 | if "%errorlevel%"=="0" goto SUCCESS 21 | if "%errorlevel%"=="1" goto END 22 | :END 23 | exit 1 24 | :SUCCESS 25 | exit 0 26 | -------------------------------------------------------------------------------- /CNN_Accelerator_Vivado_project/Accelerator.sim/sim_1/behav/xsim/glbl.v: -------------------------------------------------------------------------------- 1 | // $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ 2 | `ifndef GLBL 3 | `define GLBL 4 | `timescale 1 ps / 1 ps 5 | 6 | module glbl (); 7 | 8 | parameter ROC_WIDTH = 100000; 9 | parameter TOC_WIDTH = 0; 10 | parameter GRES_WIDTH = 10000; 11 | parameter GRES_START = 10000; 12 | 13 | //-------- STARTUP Globals -------------- 14 | wire GSR; 15 | wire GTS; 16 | wire GWE; 17 | wire PRLD; 18 | wire GRESTORE; 19 | tri1 p_up_tmp; 20 | tri (weak1, strong0) PLL_LOCKG = p_up_tmp; 21 | 22 | wire PROGB_GLBL; 23 | wire CCLKO_GLBL; 24 | wire FCSBO_GLBL; 25 | wire [3:0] DO_GLBL; 26 | wire [3:0] DI_GLBL; 27 | 28 | reg GSR_int; 29 | reg GTS_int; 30 | reg PRLD_int; 31 | reg GRESTORE_int; 32 | 33 | //-------- JTAG Globals -------------- 34 | wire JTAG_TDO_GLBL; 35 | wire JTAG_TCK_GLBL; 36 | wire JTAG_TDI_GLBL; 37 | wire JTAG_TMS_GLBL; 38 | wire JTAG_TRST_GLBL; 39 | 40 | reg JTAG_CAPTURE_GLBL; 41 | reg JTAG_RESET_GLBL; 42 | reg JTAG_SHIFT_GLBL; 43 | reg JTAG_UPDATE_GLBL; 44 | reg JTAG_RUNTEST_GLBL; 45 | 46 | reg JTAG_SEL1_GLBL = 0; 47 | reg JTAG_SEL2_GLBL = 0 ; 48 | reg JTAG_SEL3_GLBL = 0; 49 | reg JTAG_SEL4_GLBL = 0; 50 | 51 | reg JTAG_USER_TDO1_GLBL = 1'bz; 52 | reg JTAG_USER_TDO2_GLBL = 1'bz; 53 | reg JTAG_USER_TDO3_GLBL = 1'bz; 54 | reg JTAG_USER_TDO4_GLBL = 1'bz; 55 | 56 | assign (strong1, weak0) GSR = GSR_int; 57 | assign (strong1, weak0) GTS = GTS_int; 58 | assign (weak1, weak0) PRLD = PRLD_int; 59 | assign (strong1, weak0) GRESTORE = GRESTORE_int; 60 | 61 | initial begin 62 | GSR_int = 1'b1; 63 | PRLD_int = 1'b1; 64 | #(ROC_WIDTH) 65 | GSR_int = 1'b0; 66 | PRLD_int = 1'b0; 67 | end 68 | 69 | initial begin 70 | GTS_int = 1'b1; 71 | #(TOC_WIDTH) 72 | GTS_int = 1'b0; 73 | end 74 | 75 | initial begin 76 | GRESTORE_int = 1'b0; 77 | #(GRES_START); 78 | GRESTORE_int = 1'b1; 79 | #(GRES_WIDTH); 80 | GRESTORE_int = 1'b0; 81 | end 82 | 83 | endmodule 84 | `endif 85 | -------------------------------------------------------------------------------- /CNN_Accelerator_Vivado_project/Accelerator.sim/sim_1/behav/xsim/simulate.bat: -------------------------------------------------------------------------------- 1 | @echo off 2 | REM **************************************************************************** 3 | REM Vivado (TM) v2022.1 (64-bit) 4 | REM 5 | REM Filename : simulate.bat 6 | REM Simulator : Xilinx Vivado Simulator 7 | REM Description : Script for simulating the design by launching the simulator 8 | REM 9 | REM Generated by Vivado on Sun Feb 09 15:32:39 +0800 2025 10 | REM SW Build 3526262 on Mon Apr 18 15:48:16 MDT 2022 11 | REM 12 | REM IP Build 3524634 on Mon Apr 18 20:55:01 MDT 2022 13 | REM 14 | REM usage: simulate.bat 15 | REM 16 | REM **************************************************************************** 17 | REM simulate design 18 | echo "xsim CNN_Module_tb_behav -key {Behavioral:sim_1:Functional:CNN_Module_tb} -tclbatch CNN_Module_tb.tcl -protoinst "protoinst_files/CNN_Module.protoinst" -log simulate.log" 19 | call xsim CNN_Module_tb_behav -key {Behavioral:sim_1:Functional:CNN_Module_tb} -tclbatch CNN_Module_tb.tcl -protoinst "protoinst_files/CNN_Module.protoinst" -log simulate.log 20 | if "%errorlevel%"=="0" goto SUCCESS 21 | if "%errorlevel%"=="1" goto END 22 | :END 23 | exit 1 24 | :SUCCESS 25 | exit 0 26 | -------------------------------------------------------------------------------- /CNN_Accelerator_Vivado_project/Accelerator.sim/sim_1/behav/xsim/xelab.pb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Futuresxy/General-CNN-Accelerator/09c07c86f0b739fc420f5e620bc1d10288eb774d/CNN_Accelerator_Vivado_project/Accelerator.sim/sim_1/behav/xsim/xelab.pb -------------------------------------------------------------------------------- /CNN_Accelerator_Vivado_project/Accelerator.sim/sim_1/behav/xsim/xsim.dir/CNN_Module_tb_behav/Compile_Options.txt: -------------------------------------------------------------------------------- 1 | --incr --debug "typical" --relax --mt "2" -L "xil_defaultlib" -L "xbip_utils_v3_0_10" -L "axi_utils_v2_0_6" -L "xbip_pipe_v3_0_6" -L "xbip_dsp48_wrapper_v3_0_4" -L "xbip_dsp48_addsub_v3_0_6" -L "xbip_bram18k_v3_0_6" -L "mult_gen_v12_0_18" -L "floating_point_v7_0_20" -L "xbip_dsp48_mult_v3_0_6" -L "xbip_dsp48_multadd_v3_0_6" -L "div_gen_v5_1_19" -L "axis_infrastructure_v1_1_0" -L "axis_data_fifo_v2_0_8" -L "xilinx_vip" -L "unisims_ver" -L "unimacro_ver" -L "secureip" -L "xpm" --snapshot "CNN_Module_tb_behav" "xil_defaultlib.CNN_Module_tb" "xil_defaultlib.glbl" -log "elaborate.log" 2 | -------------------------------------------------------------------------------- /CNN_Accelerator_Vivado_project/Accelerator.sim/sim_1/behav/xsim/xsim.dir/CNN_Module_tb_behav/TempBreakPointFile.txt: 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/CNN_Accelerator_Vivado_project/Accelerator.sim/sim_1/behav/xsim/xsim.dir/CNN_Module_tb_behav/xsim.rlx: -------------------------------------------------------------------------------- 1 | 2 | { 3 | crc : 8359638873892910658 , 4 | ccp_crc : 0 , 5 | cmdline : " --incr --debug typical --relax --mt 2 -L xil_defaultlib -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L xbip_pipe_v3_0_6 -L xbip_dsp48_wrapper_v3_0_4 -L xbip_dsp48_addsub_v3_0_6 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_18 -L floating_point_v7_0_20 -L xbip_dsp48_mult_v3_0_6 -L xbip_dsp48_multadd_v3_0_6 -L div_gen_v5_1_19 -L axis_infrastructure_v1_1_0 -L axis_data_fifo_v2_0_8 -L xilinx_vip -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot CNN_Module_tb_behav xil_defaultlib.CNN_Module_tb xil_defaultlib.glbl" , 6 | buildDate : "Apr 18 2022" , 7 | buildTime : "16:05:34" , 8 | linkCmd : "F:\\Xilinx\\Vivado\\2022.1\\data\\..\\tps\\mingw\\6.2.0\\win64.o\\nt\\bin\\gcc.exe -Wa,-W -O -Wl,--stack,104857600 -o \"xsim.dir/CNN_Module_tb_behav/xsimk.exe\" \"xsim.dir/CNN_Module_tb_behav/obj/xsim_0.win64.obj\" \"xsim.dir/CNN_Module_tb_behav/obj/xsim_1.win64.obj\" \"xsim.dir/CNN_Module_tb_behav/obj/xsim_2.win64.obj\" \"xsim.dir/CNN_Module_tb_behav/obj/xsim_3.win64.obj\" \"xsim.dir/CNN_Module_tb_behav/obj/xsim_4.win64.obj\" \"xsim.dir/CNN_Module_tb_behav/obj/xsim_5.win64.obj\" -L\"F:\\Xilinx\\Vivado\\2022.1\\lib\\win64.o\" -lrdi_simulator_kernel -lrdi_simbridge_kernel" , 9 | aggregate_nets : 10 | [ 11 | ] 12 | } -------------------------------------------------------------------------------- /CNN_Accelerator_Vivado_project/Accelerator.sim/sim_1/behav/xsim/xsim.dir/CNN_Module_tb_behav/xsim.rtti: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Futuresxy/General-CNN-Accelerator/09c07c86f0b739fc420f5e620bc1d10288eb774d/CNN_Accelerator_Vivado_project/Accelerator.sim/sim_1/behav/xsim/xsim.dir/CNN_Module_tb_behav/xsim.rtti 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VHDL_PROCEDURE_SCOPE_FILTER=false 11 | VERILOG_MODULE_SCOPE_FILTER=true 12 | VERILOG_PACKAGE_SCOPE_FILTER=false 13 | VERILOG_BLOCK_SCOPE_FILTER=false 14 | VERILOG_TASK_SCOPE_FILTER=false 15 | VERILOG_PROCESS_SCOPE_FILTER=false 16 | INPUT_OBJECT_FILTER=true 17 | OUTPUT_OBJECT_FILTER=true 18 | INOUT_OBJECT_FILTER=true 19 | INTERNAL_OBJECT_FILTER=true 20 | CONSTANT_OBJECT_FILTER=true 21 | VARIABLE_OBJECT_FILTER=true 22 | INPUT_PROTOINST_FILTER=true 23 | OUTPUT_PROTOINST_FILTER=true 24 | INOUT_PROTOINST_FILTER=true 25 | INTERNAL_PROTOINST_FILTER=true 26 | CONSTANT_PROTOINST_FILTER=true 27 | VARIABLE_PROTOINST_FILTER=true 28 | SCOPE_NAME_COLUMN_WIDTH=464 29 | SCOPE_DESIGN_UNIT_COLUMN_WIDTH=236 30 | SCOPE_BLOCK_TYPE_COLUMN_WIDTH=75 31 | OBJECT_NAME_COLUMN_WIDTH=416 32 | OBJECT_VALUE_COLUMN_WIDTH=118 33 | OBJECT_DATA_TYPE_COLUMN_WIDTH=75 34 | PROCESS_NAME_COLUMN_WIDTH=75 35 | PROCESS_TYPE_COLUMN_WIDTH=75 36 | FRAME_INDEX_COLUMN_WIDTH=75 37 | FRAME_NAME_COLUMN_WIDTH=75 38 | FRAME_FILE_NAME_COLUMN_WIDTH=75 39 | FRAME_LINE_NUM_COLUMN_WIDTH=416 40 | LOCAL_NAME_COLUMN_WIDTH=118 41 | LOCAL_VALUE_COLUMN_WIDTH=75 42 | LOCAL_DATA_TYPE_COLUMN_WIDTH=0 43 | PROTO_NAME_COLUMN_WIDTH=0 44 | PROTO_VALUE_COLUMN_WIDTH=0 45 | INPUT_LOCAL_FILTER=1 46 | OUTPUT_LOCAL_FILTER=1 47 | INOUT_LOCAL_FILTER=1 48 | INTERNAL_LOCAL_FILTER=1 49 | CONSTANT_LOCAL_FILTER=1 50 | VARIABLE_LOCAL_FILTER=1 51 | -------------------------------------------------------------------------------- /CNN_Accelerator_Vivado_project/Accelerator.sim/sim_1/behav/xsim/xsim.dir/CNN_Module_tb_behav/xsimcrash.log: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Futuresxy/General-CNN-Accelerator/09c07c86f0b739fc420f5e620bc1d10288eb774d/CNN_Accelerator_Vivado_project/Accelerator.sim/sim_1/behav/xsim/xsim.dir/CNN_Module_tb_behav/xsimcrash.log -------------------------------------------------------------------------------- /CNN_Accelerator_Vivado_project/Accelerator.sim/sim_1/behav/xsim/xsim.dir/CNN_Module_tb_behav/xsimk.exe: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Futuresxy/General-CNN-Accelerator/09c07c86f0b739fc420f5e620bc1d10288eb774d/CNN_Accelerator_Vivado_project/Accelerator.sim/sim_1/behav/xsim/xsim.dir/CNN_Module_tb_behav/xsimk.exe -------------------------------------------------------------------------------- /CNN_Accelerator_Vivado_project/Accelerator.sim/sim_1/behav/xsim/xsim.dir/CNN_Module_tb_behav/xsimkernel.log: -------------------------------------------------------------------------------- 1 | Running: xsim.dir/CNN_Module_tb_behav/xsimk.exe -simmode gui -wdb CNN_Module_tb_behav.wdb -simrunnum 0 -socket 64059 2 | Design successfully loaded 3 | Design Loading Memory Usage: 11712 KB (Peak: 11712 KB) 4 | Design Loading CPU Usage: 15 ms 5 | Simulation completed 6 | Simulation Memory Usage: 14808 KB (Peak: 14808 KB) 7 | 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11111111 44 | 4 11111111 0 11111111 45 | 5 11111111 0 11111111 46 | 6 11111111 0 11111111 47 | 7 11111111 0 11111111 48 | 8 11111111 0 11111111 49 | 9 11111111 0 11111111 50 | 0 11111111 0 11111111 51 | 1 11111111 0 11111111 52 | 2 11111111 0 11111111 53 | 3 11111111 0 11111111 54 | 4 11111111 0 11111111 55 | 5 11111111 0 11111111 56 | 6 11111111 0 11111111 57 | 7 11111111 0 11111111 58 | 8 11111111 0 11111111 59 | 9 11111111 0 11111111 60 | 0 11111111 0 11111111 61 | 1 11111111 0 11111111 62 | 2 11111111 0 11111111 63 | 3 11111111 0 11111111 64 | 4 11111111 1 11111111 -------------------------------------------------------------------------------- /CNN_Accelerator_Vivado_project/Accelerator.sim/sim_1/sim_txt/input_pool_max_data.txt: -------------------------------------------------------------------------------- 1 | 0 11111111 0 11111111 2 | 1 11111111 0 11111111 3 | 2 11111111 0 11111111 4 | 3 11111111 0 11111111 5 | 4 11111111 0 11111111 6 | 5 11111111 0 11111111 7 | 6 11111111 0 11111111 8 | 7 11111111 0 11111111 9 | 8 11111111 0 11111111 10 | 9 11111111 0 11111111 11 | 0 11111111 0 11111111 12 | 1 11111111 0 11111111 13 | 2 11111111 0 11111111 14 | 3 11111111 0 11111111 15 | 4 11111111 0 11111111 16 | 5 11111111 0 11111111 17 | 6 11111111 0 11111111 18 | 7 11111111 0 11111111 19 | 8 11111111 0 11111111 20 | 9 11111111 0 11111111 21 | 0 11111111 0 11111111 22 | 1 11111111 0 11111111 23 | 2 11111111 0 11111111 24 | 3 11111111 0 11111111 25 | 4 11111111 0 11111111 26 | 5 11111111 0 11111111 27 | 6 11111111 0 11111111 28 | 7 11111111 0 11111111 29 | 8 11111111 0 11111111 30 | 9 11111111 0 11111111 31 | 0 11111111 0 11111111 32 | 1 11111111 0 11111111 33 | 2 11111111 0 11111111 34 | 3 11111111 0 11111111 35 | 4 11111111 0 11111111 36 | 5 11111111 0 11111111 37 | 6 11111111 0 11111111 38 | 7 11111111 0 11111111 39 | 8 11111111 0 11111111 40 | 9 11111111 0 11111111 41 | 0 11111111 0 11111111 42 | 1 11111111 0 11111111 43 | 2 11111111 0 11111111 44 | 3 11111111 0 11111111 45 | 4 11111111 0 11111111 46 | 5 11111111 0 11111111 47 | 6 11111111 0 11111111 48 | 7 11111111 0 11111111 49 | 8 11111111 0 11111111 50 | 9 11111111 0 11111111 51 | 0 11111111 0 11111111 52 | 1 11111111 0 11111111 53 | 2 11111111 0 11111111 54 | 3 11111111 0 11111111 55 | 4 11111111 0 11111111 56 | 5 11111111 0 11111111 57 | 6 11111111 0 11111111 58 | 7 11111111 0 11111111 59 | 8 11111111 0 11111111 60 | 9 11111111 0 11111111 61 | 0 11111111 0 11111111 62 | 1 11111111 0 11111111 63 | 2 11111111 0 11111111 64 | 3 11111111 1 11111111 -------------------------------------------------------------------------------- /CNN_Accelerator_Vivado_project/Accelerator.sim/sim_1/sim_txt/input_weight_data.txt: -------------------------------------------------------------------------------- 1 | 0000000008040201 11111111 0 11111111 2 | 0000000010080402 11111111 0 11111111 3 | 00000000180c0603 11111111 0 11111111 4 | 0000000020100804 11111111 1 11111111 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/CNN_Accelerator_Vivado_project/Accelerator.srcs/sources_1/bd/Accelerator/ui/bd_fb33126b.ui: -------------------------------------------------------------------------------- 1 | { 2 | "ActiveEmotionalView":"Default View", 3 | "Default View_ScaleFactor":"1.25", 4 | "Default View_TopLeft":"-213,-135", 5 | "ExpandedHierarchyInLayout":"", 6 | "guistr":"# # String gsaved with Nlview 7.0r6 2020-01-29 bk=1.5227 VDI=41 GEI=36 GUI=JA:10.0 non-TLS 7 | # -string -flagsOSRD 8 | preplace inst processing_system7_0 -pg 1 -lvl 1 -x 210 -y 0 -defaultsOSRD 9 | levelinfo -pg 1 0 210 420 10 | pagesize -pg 1 -db -bbox -sgen 0 -100 420 200 11 | " 12 | } 13 | 14 | -------------------------------------------------------------------------------- /CNN_Accelerator_Vivado_project/Accelerator.srcs/sources_1/bd/Accelerator_block_design/ui/bd_7beb0d1f.ui: -------------------------------------------------------------------------------- 1 | { 2 | "ActiveEmotionalView":"Default View", 3 | "Default View_ScaleFactor":"1.25", 4 | "Default View_TopLeft":"-332,-62", 5 | "ExpandedHierarchyInLayout":"", 6 | "guistr":"# # String gsaved with Nlview 7.0r6 2020-01-29 bk=1.5227 VDI=41 GEI=36 GUI=JA:10.0 non-TLS 7 | # -string -flagsOSRD 8 | preplace port port-id_clk -pg 1 -lvl 0 -x -20 -y 50 -defaultsOSRD 9 | preplace port port-id_rstn -pg 1 -lvl 0 -x -20 -y 70 -defaultsOSRD 10 | preplace inst Conv_Array_Control_0 -pg 1 -lvl 1 -x 170 -y 110 -defaultsOSRD 11 | preplace inst Pooling_Array_Control_0 -pg 1 -lvl 2 -x 510 -y 100 -defaultsOSRD 12 | preplace inst FullCon_PE_Control_0 -pg 1 -lvl 1 -x 170 -y 330 -defaultsOSRD 13 | preplace netloc clk_1 1 0 2 10 440 330 14 | preplace netloc rstn_1 1 0 2 0 450 340 15 | levelinfo -pg 1 -20 170 510 680 16 | pagesize -pg 1 -db -bbox -sgen -100 -10 680 630 17 | " 18 | } 19 | 20 | -------------------------------------------------------------------------------- /CNN_Accelerator_Vivado_project/Accelerator.srcs/sources_1/bd/CNN_Module/ui/bd_7fdb3988.ui: -------------------------------------------------------------------------------- 1 | { 2 | "ActiveEmotionalView":"Default View", 3 | "Default View_ScaleFactor":"0.900318", 4 | "Default View_TopLeft":"-293,-103", 5 | "ExpandedHierarchyInLayout":"", 6 | "guistr":"# # String gsaved with Nlview 7.0r6 2020-01-29 bk=1.5227 VDI=41 GEI=36 GUI=JA:10.0 non-TLS 7 | # -string -flagsOSRD 8 | preplace port AXI4_LITE_Control_Accelerator -pg 1 -lvl 0 -x -40 -y 480 -defaultsOSRD 9 | preplace port AXI4_LITE_Control_Window -pg 1 -lvl 0 -x -40 -y 360 -defaultsOSRD 10 | preplace port M_AXIS -pg 1 -lvl 6 -x 1510 -y 290 -defaultsOSRD 11 | preplace port S_AXIS -pg 1 -lvl 0 -x -40 -y 60 -defaultsOSRD 12 | preplace port S_AXIS1 -pg 1 -lvl 0 -x -40 -y 200 -defaultsOSRD 13 | preplace port S_AXIS2 -pg 1 -lvl 0 -x -40 -y 260 -defaultsOSRD 14 | preplace port port-id_cnn_done -pg 1 -lvl 6 -x 1510 -y 420 -defaultsOSRD 15 | preplace port port-id_s_axis_aclk -pg 1 -lvl 0 -x -40 -y 300 -defaultsOSRD 16 | preplace port port-id_s_axis_aresetn -pg 1 -lvl 0 -x -40 -y 280 -defaultsOSRD 17 | preplace portBus cnn_cnt_0 -pg 1 -lvl 6 -x 1510 -y 440 -defaultsOSRD 18 | preplace inst INACT_DATA_FIFO -pg 1 -lvl 3 -x 710 -y 370 -defaultsOSRD 19 | preplace inst PICTURE_DATA_FIFO -pg 1 -lvl 1 -x 130 -y 280 -defaultsOSRD 20 | preplace inst RESULT_DATA_FIFO1 -pg 1 -lvl 5 -x 1370 -y 290 -defaultsOSRD 21 | preplace inst WEIGHT_CONV_ACT_FULLCON_FIFO -pg 1 -lvl 3 -x 710 -y 220 -defaultsOSRD 22 | preplace inst WEIGHT_FULLCON_FIFO -pg 1 -lvl 3 -x 710 -y 80 -defaultsOSRD 23 | preplace inst Windows_Data_Convert_0 -pg 1 -lvl 2 -x 430 -y 350 -defaultsOSRD 24 | preplace inst CNN_Control_1 -pg 1 -lvl 4 -x 1050 -y 420 -defaultsOSRD 25 | preplace netloc CNN_Control_1_cnn_cnt 1 4 2 NJ 440 NJ 26 | preplace netloc CNN_Control_1_cnn_done 1 4 2 NJ 420 NJ 27 | preplace netloc s_axis_aclk_1 1 0 5 -10 170 280 170 590 450 880 310 NJ 28 | preplace netloc s_axis_aresetn_1 1 0 5 0 180 260 210 580 460 870 290 NJ 29 | preplace netloc CNN_Control_0_result 1 4 1 1210 270n 30 | preplace netloc Conn1 1 5 1 NJ 290 31 | preplace netloc Conn2 1 0 1 NJ 260 32 | preplace netloc Conn4 1 0 3 NJ 60 NJ 60 NJ 33 | preplace netloc Conn5 1 0 3 -20J 190 270J 200 NJ 34 | preplace netloc Conn6 1 0 2 10J 200 250J 35 | preplace netloc INACT_DATA_FIFO_M_AXIS 1 3 1 N 370 36 | preplace netloc PICTURE_DATA_FIFO_M_AXIS 1 1 1 N 280 37 | preplace netloc WEIGHT_CONV_ACT_FULLCON_FIFO_M_AXIS 1 3 1 850 220n 38 | preplace netloc WEIGHT_FULLCON_FIFO_M_AXIS 1 3 1 860 80n 39 | preplace netloc Windows_Data_Convert_0_m00_axis 1 2 1 N 350 40 | preplace netloc s00_axi_1 1 0 4 NJ 480 NJ 480 NJ 480 890J 41 | levelinfo -pg 1 -40 130 430 710 1050 1370 1510 42 | pagesize -pg 1 -db -bbox -sgen -300 0 1660 650 43 | " 44 | } 45 | 0 46 | -------------------------------------------------------------------------------- /CNN_Accelerator_Vivado_project/Accelerator.srcs/sources_1/imports/window_ip/Windows_Data_Convert_v1_0.v: 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wire [2*DATA_WIDTH-1:0] _GEN_0 = io_inwtValid ? $signed(io_inWtPS) : $signed({{DATA_WIDTH{weightReg[DATA_WIDTH-1]}},weightReg}); 24 | 25 | //传递权重或者部分和 26 | assign io_outWtPS = io_inwtValid ? $signed({{DATA_WIDTH{weightReg[DATA_WIDTH-1]}},weightReg}) : $signed(parSumReg); 27 | 28 | assign io_outAct = actReg; 29 | 30 | 31 | always @(posedge clk or negedge rstn) begin 32 | if(!rstn||refresh) 33 | begin 34 | weightReg<=0; 35 | actReg <= 0; 36 | parSumReg <=0; 37 | end 38 | 39 | else begin 40 | weightReg <= _GEN_0[DATA_WIDTH-1:0]; 41 | actReg <= io_inAct; // @[Conv_PE.scala 18:DATA_WIDTH-1] 42 | parSumReg <= $signed(io_inWtPS) + $signed(_parSumReg_T); // @[Conv_PE.scala 19:28] 43 | end 44 | 45 | end 46 | 47 | 48 | 49 | 50 | 51 | 52 | 53 | endmodule -------------------------------------------------------------------------------- /CNN_Accelerator_Vivado_project/Accelerator.srcs/sources_1/new/CNN_Control/FullCon_PE.v: -------------------------------------------------------------------------------- 1 | module FullCon_PE#( 2 | parameter DATA_WIDTH=16, 3 | parameter OutData_width=32 4 | ) ( 5 | input clk, 6 | input rstn, 7 | input signed [DATA_WIDTH-1 :0] io_inAct, 8 | input signed [DATA_WIDTH-1 :0] io_inWeight, 9 | output signed [DATA_WIDTH-1 :0] io_outAct, 10 | output signed [OutData_width-1:0] io_outSum, 11 | input io_inValid, 12 | input io_clear, 13 | output io_outValid 14 | ); 15 | 16 | reg [OutData_width-1:0] reg_outsum; 17 | reg [DATA_WIDTH-1 :0] reg_outact; 18 | reg [DATA_WIDTH-1 :0] reg_outweight; 19 | reg valid; 20 | assign io_outAct=reg_outact; 21 | assign io_outSum=reg_outsum; 22 | assign io_outValid=valid; 23 | 24 | 25 | always @(posedge clk or negedge rstn) begin 26 | if (!rstn) begin 27 | valid<=0; 28 | reg_outsum<=0; 29 | end 30 | else begin 31 | valid<=io_inValid; 32 | if(io_clear==1) 33 | reg_outsum<=0; 34 | else 35 | reg_outsum<=valid?reg_outweight*reg_outact+reg_outsum:reg_outsum; 36 | end 37 | end 38 | 39 | 40 | always @(posedge clk or negedge rstn) begin 41 | if (!rstn) begin 42 | reg_outact<=0; 43 | 44 | reg_outweight<=0; 45 | end 46 | else begin 47 | reg_outact<=io_inAct; 48 | reg_outweight<=io_inWeight; 49 | 50 | end 51 | 52 | end 53 | 54 | 55 | 56 | endmodule -------------------------------------------------------------------------------- /CNN_Accelerator_Vivado_project/Accelerator.srcs/sources_1/new/CNN_Control/FullCon_PE_Control.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Futuresxy/General-CNN-Accelerator/09c07c86f0b739fc420f5e620bc1d10288eb774d/CNN_Accelerator_Vivado_project/Accelerator.srcs/sources_1/new/CNN_Control/FullCon_PE_Control.v -------------------------------------------------------------------------------- /CNN_Accelerator_Vivado_project/Accelerator.srcs/sources_1/new/CNN_Control/Pool_PE.v: -------------------------------------------------------------------------------- 1 | module Pool_PE#( 2 | parameter DATA_WIDTH=16 3 | ) 4 | ( 5 | input clk, 6 | input rstn, 7 | input refresh, 8 | input signed [DATA_WIDTH-1:0] io_inAct1, 9 | input signed [DATA_WIDTH-1:0] io_inAct2, 10 | output signed [DATA_WIDTH-1:0] io_outAnswer, 11 | input io_Max_MeanValid 12 | ); 13 | reg [15:0] outAnswer_reg; // @[Pool_PE.scala 15:28] 14 | 15 | 16 | 17 | always @(posedge clk ) begin 18 | if(!rstn||refresh) 19 | begin 20 | outAnswer_reg <=0; 21 | end 22 | else begin 23 | if(io_Max_MeanValid==1) 24 | outAnswer_reg <= $signed(io_inAct1) > $signed(io_inAct2) ? $signed(io_inAct1) : $signed(io_inAct2); 25 | else 26 | outAnswer_reg <= $signed(io_inAct1) + $signed(io_inAct2); 27 | end 28 | end 29 | 30 | assign io_outAnswer = outAnswer_reg; 31 | 32 | 33 | endmodule -------------------------------------------------------------------------------- /CNN_Accelerator_Vivado_project/Accelerator.srcs/sources_1/new/CNN_Control/Pooling_Array_Control.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Futuresxy/General-CNN-Accelerator/09c07c86f0b739fc420f5e620bc1d10288eb774d/CNN_Accelerator_Vivado_project/Accelerator.srcs/sources_1/new/CNN_Control/Pooling_Array_Control.v -------------------------------------------------------------------------------- /CNN_Accelerator_Vivado_project/Accelerator.srcs/sources_1/new/CNN_Control/Pooling_SystolicArray.v: -------------------------------------------------------------------------------- 1 | module Pooling_SystolicArray#( 2 | parameter DATA_WIDTH=16, 3 | parameter PARA_WIDTH=32, 4 | parameter POOL_KERNEL_SIZE=2 5 | )( 6 | input clk , 7 | input rstn, 8 | input refresh, 9 | input [PARA_WIDTH-1 :0] Pool_Kernel_Size, 10 | input signed [POOL_KERNEL_SIZE*POOL_KERNEL_SIZE*DATA_WIDTH-1:0] io_inAct, 11 | output signed [DATA_WIDTH-1 :0] io_outSum, 12 | input io_Max_MeanValid 13 | ); 14 | 15 | 16 | reg [DATA_WIDTH-1:0] reg_outAnswer [POOL_KERNEL_SIZE*POOL_KERNEL_SIZE-1:0]; 17 | 18 | genvar i; 19 | 20 | generate 21 | for (i=0;i $signed(io_inAct2) ? $signed(io_inAct1) : $signed(io_inAct2); 25 | else 26 | outAnswer_reg <= $signed(io_inAct1) + $signed(io_inAct2); 27 | end 28 | end 29 | 30 | assign io_outAnswer = outAnswer_reg; 31 | 32 | 33 | endmodule -------------------------------------------------------------------------------- /CNN_Accelerator_Vivado_project/Accelerator.srcs/sources_1/new/Pooling_Array_Control.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Futuresxy/General-CNN-Accelerator/09c07c86f0b739fc420f5e620bc1d10288eb774d/CNN_Accelerator_Vivado_project/Accelerator.srcs/sources_1/new/Pooling_Array_Control.v -------------------------------------------------------------------------------- /CNN_Accelerator_Vivado_project/Accelerator.srcs/sources_1/new/Pooling_SystolicArray.v: -------------------------------------------------------------------------------- 1 | module Pooling_SystolicArray#( 2 | parameter DATA_WIDTH=16, 3 | parameter PARA_WIDTH=8, 4 | parameter POOL_KERNEL_SIZE=2 5 | )( 6 | input clk , 7 | input rstn, 8 | input refresh, 9 | input [PARA_WIDTH-1 :0] Pool_Kernel_Size, 10 | input [PARA_WIDTH-1 :0] Pool_Whole_Size, 11 | input signed [POOL_KERNEL_SIZE*POOL_KERNEL_SIZE*DATA_WIDTH-1:0] io_inAct, 12 | output signed [2*DATA_WIDTH-1 :0] io_outSum, 13 | input io_Max_MeanValid 14 | ); 15 | 16 | 17 | reg [2*DATA_WIDTH-1:0] reg_outAnswer [POOL_KERNEL_SIZE*POOL_KERNEL_SIZE-2:0]; 18 | 19 | genvar i; 20 | 21 | generate 22 | for (i=0;i 2 | 3 | 4 | 5 | 6 | 7 | -------------------------------------------------------------------------------- /CNN_Accelerator_Vivado_project/Accelerator.tmp/windows_data_convert_v1_0_project/Windows_Data_Convert_v1_0_project.cache/wt/project.wpc: -------------------------------------------------------------------------------- 1 | version:1 2 | 6d6f64655f636f756e7465727c4755494d6f6465:1 3 | eof: 4 | -------------------------------------------------------------------------------- /CNN_Accelerator_Vivado_project/Accelerator.tmp/windows_data_convert_v1_0_project/Windows_Data_Convert_v1_0_project.hw/Windows_Data_Convert_v1_0_project.lpr: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | -------------------------------------------------------------------------------- /CNN_Accelerator_Vivado_project/vivado.log: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Futuresxy/General-CNN-Accelerator/09c07c86f0b739fc420f5e620bc1d10288eb774d/CNN_Accelerator_Vivado_project/vivado.log -------------------------------------------------------------------------------- /CNN_Accelerator_Vivado_project/vivado_1444.backup.jou: -------------------------------------------------------------------------------- 1 | #----------------------------------------------------------- 2 | # Vivado v2022.1 (64-bit) 3 | # SW Build 3526262 on Mon Apr 18 15:48:16 MDT 2022 4 | # IP Build 3524634 on Mon Apr 18 20:55:01 MDT 2022 5 | # Start of session at: Thu May 23 23:07:44 2024 6 | # Process ID: 1444 7 | # Current directory: E:/Accelerator/CNN_Accelerator_Vivado_project 8 | # Command line: vivado.exe -gui_launcher_event rodinguilauncherevent15792 E:\Accelerator\CNN_Accelerator_Vivado_project\Accelerator.xpr 9 | # Log file: E:/Accelerator/CNN_Accelerator_Vivado_project/vivado.log 10 | # Journal file: E:/Accelerator/CNN_Accelerator_Vivado_project\vivado.jou 11 | # Running On: DESKTOP-JO2RAF5, OS: Windows, CPU Frequency: 2496 MHz, CPU Physical cores: 4, Host memory: 17041 MB 12 | #----------------------------------------------------------- 13 | start_gui 14 | open_project E:/Accelerator/CNN_Accelerator_Vivado_project/Accelerator.xpr 15 | update_compile_order -fileset sources_1 16 | open_bd_design {E:/Accelerator/CNN_Accelerator_Vivado_project/Accelerator.srcs/sources_1/bd/Accelerator_block_design/Accelerator_block_design.bd} 17 | regenerate_bd_layout 18 | startgroup 19 | create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_0 20 | endgroup 21 | set_property location {4 1727 665} [get_bd_cells axi_gpio_0] 22 | set_property -dict [list CONFIG.C_GPIO_WIDTH {1} CONFIG.C_ALL_INPUTS {1} CONFIG.C_INTERRUPT_PRESENT {1}] [get_bd_cells axi_gpio_0] 23 | connect_bd_net [get_bd_pins axi_gpio_0/gpio_io_i] [get_bd_pins CNN_ACCELERATOR/cnn_done] 24 | connect_bd_intf_net -boundary_type upper [get_bd_intf_pins axi_interconnect_1/M07_AXI] [get_bd_intf_pins axi_gpio_0/S_AXI] 25 | connect_bd_net [get_bd_pins axi_gpio_0/s_axi_aclk] [get_bd_pins processing_system7_0/FCLK_CLK0] 26 | connect_bd_net [get_bd_pins axi_gpio_0/s_axi_aresetn] [get_bd_pins proc_sys_reset_0/peripheral_aresetn] 27 | save_bd_design 28 | assign_bd_address 29 | validate_bd_design 30 | reset_run Accelerator_block_design_processing_system7_0_0_synth_1 31 | save_bd_design 32 | reset_run synth_1 33 | launch_runs synth_1 -jobs 8 34 | wait_on_run synth_1 35 | set_property ip_repo_paths {} [current_project] 36 | update_ip_catalog 37 | launch_runs impl_1 -jobs 8 38 | wait_on_run impl_1 39 | launch_runs impl_1 -to_step write_bitstream -jobs 8 40 | wait_on_run impl_1 41 | -------------------------------------------------------------------------------- /CNN_Accelerator_Vivado_project/vivado_20584.backup.jou: -------------------------------------------------------------------------------- 1 | #----------------------------------------------------------- 2 | # Vivado v2022.1 (64-bit) 3 | # SW Build 3526262 on Mon Apr 18 15:48:16 MDT 2022 4 | # IP Build 3524634 on Mon Apr 18 20:55:01 MDT 2022 5 | # Start of session at: Mon Apr 29 21:54:10 2024 6 | # Process ID: 20584 7 | # Current directory: E:/Accelerator/Accelerator_100M 8 | # Command line: vivado.exe -gui_launcher_event rodinguilauncherevent7356 E:\Accelerator\Accelerator_100M\Accelerator.xpr 9 | # Log file: E:/Accelerator/Accelerator_100M/vivado.log 10 | # Journal file: E:/Accelerator/Accelerator_100M\vivado.jou 11 | # Running On: DESKTOP-JO2RAF5, OS: Windows, CPU Frequency: 2496 MHz, CPU Physical cores: 4, Host memory: 17041 MB 12 | #----------------------------------------------------------- 13 | start_gui 14 | open_project E:/Accelerator/Accelerator_100M/Accelerator.xpr 15 | update_compile_order -fileset sources_1 16 | -------------------------------------------------------------------------------- /CNN_Accelerator_Vivado_project/vivado_pid12020.str: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Futuresxy/General-CNN-Accelerator/09c07c86f0b739fc420f5e620bc1d10288eb774d/CNN_Accelerator_Vivado_project/vivado_pid12020.str -------------------------------------------------------------------------------- /LICENSE: -------------------------------------------------------------------------------- 1 | MIT License 2 | 3 | Copyright (c) 2025 song xiaoyou from WHU and THU 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in all 13 | copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 | SOFTWARE. 22 | -------------------------------------------------------------------------------- /Software_project/Software/software_jupyter/AlexNet_16/Alexnet_conv2_weight.txt: -------------------------------------------------------------------------------- 1 | 0101010101010101 2 | 0101010101010101 3 | 0101010101010101 4 | 0101010101010101 5 | 0101010101010101 6 | 0101010101010101 7 | 0101010101010101 8 | 0101010101010101 9 | 0101010101010101 10 | 0101010101010101 11 | 0101010101010101 12 | 0101010101010101 13 | 0101010101010101 14 | 0101010101010101 15 | 0101010101010101 16 | 0101010101010101 17 | 0101010101010101 18 | 0101010101010101 19 | -------------------------------------------------------------------------------- /Software_project/Software/software_jupyter/AlexNet_16/Alexnet_conv3_weight.txt: -------------------------------------------------------------------------------- 1 | 0101010101010101 2 | 0101010101010101 3 | 0101010101010101 4 | 0101010101010101 5 | 0101010101010101 6 | 0101010101010101 7 | 0101010101010101 8 | 0101010101010101 9 | 0101010101010101 10 | 0101010101010101 11 | 0101010101010101 12 | 0101010101010101 13 | 0101010101010101 14 | 0101010101010101 15 | 0101010101010101 16 | 0101010101010101 17 | 0101010101010101 18 | 0101010101010101 19 | -------------------------------------------------------------------------------- /Software_project/Software/software_jupyter/AlexNet_16/Alexnet_conv4_weight.txt: -------------------------------------------------------------------------------- 1 | 0101010101010101 2 | 0101010101010101 3 | 0101010101010101 4 | 0101010101010101 5 | 0101010101010101 6 | 0101010101010101 7 | 0101010101010101 8 | 0101010101010101 9 | 0101010101010101 10 | 0101010101010101 11 | 0101010101010101 12 | 0101010101010101 13 | 0101010101010101 14 | 0101010101010101 15 | 0101010101010101 16 | 0101010101010101 17 | 0101010101010101 18 | 0101010101010101 19 | -------------------------------------------------------------------------------- /Software_project/Software/software_jupyter/AlexNet_16/Alexnet_conv5_weight.txt: -------------------------------------------------------------------------------- 1 | 0101010101010101 2 | 0101010101010101 3 | 0101010101010101 4 | 0101010101010101 5 | 0101010101010101 6 | 0101010101010101 7 | 0101010101010101 8 | 0101010101010101 9 | 0101010101010101 10 | 0101010101010101 11 | 0101010101010101 12 | 0101010101010101 13 | 0101010101010101 14 | 0101010101010101 15 | 0101010101010101 16 | 0101010101010101 17 | 0101010101010101 18 | 0101010101010101 19 | -------------------------------------------------------------------------------- /Software_project/Software/software_jupyter/AlexNet_16/Alexnet_conv_weight.txt: -------------------------------------------------------------------------------- 1 | 0101010101010101 2 | 0101010101010101 3 | 0101010101010101 4 | 0101010101010101 5 | 0101010101010101 6 | 0101010101010101 7 | 0101010101010101 8 | 0101010101010101 9 | 0101010101010101 10 | 0101010101010101 11 | 0101010101010101 12 | 0101010101010101 13 | 0101010101010101 14 | 0101010101010101 15 | 0101010101010101 16 | 0101010101010101 17 | 0101010101010101 18 | 0101010101010101 19 | -------------------------------------------------------------------------------- /Software_project/Software/software_jupyter/Lenet_new_weight/Conv1_weight0combine6_0.txt: -------------------------------------------------------------------------------- 1 | 0xf82518d7b83a 2 | 0x2957faf08cff 3 | 0x2a6fadfe93ef 4 | 0x4a42a4028d0a 5 | 0x4f20813dcb24 6 | 0xd83024fdf861 7 | 0xcd3e3c0e061d 8 | 0x22530a0f020d 9 | 0x52e9b7270303 10 | 0x3fded83f2b0b 11 | 0x815417c25423 12 | 0xbb661eea381b 13 | 0xf8e74f32650c 14 | 0x57e73c3d5716 15 | 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0xeb0d04032619 2 | 0x2502ceea3e05 3 | 0x32f9a5f518e4 4 | 0xdd3c11ef1c4 5 | 0xf70f042c16ed 6 | 0xe24135ebe323 7 | 0x817caeddcee 8 | 0xff11b72af69e 9 | 0xc3a03f3dbbb 10 | 0xdb405dbff6ba 11 | 0x45d411eeedf1 12 | 0x59e6df4326ae 13 | 0x7f11f40b2ebe 14 | 0x23482ac5bcd6 15 | 0xcd2938d6d1eb 16 | 0x22c4c11c73a8 17 | 0x40fcf90d7fbb 18 | 0x250109d762e8 19 | 0xe0febd535f9 20 | 0x62df0141b0e 21 | 0x29eed9fd4bff 22 | 0xc12dccf3a2e 23 | 0xc629e4f11325 24 | 0xe042eef61512 25 | 0xdf3cf9260d04 26 | -------------------------------------------------------------------------------- /Software_project/Software/software_jupyter/Lenet_new_weight/Conv2_weight11combine6_0.txt: -------------------------------------------------------------------------------- 1 | 0x26294bfa3436 2 | 0x3f3437ca49e8 3 | 0x721d3efc54fe 4 | 0x5f1a1b070813 5 | 0xfe3229f6d601 6 | 0x5df14b075f39 7 | 0x7bdb36e44c5b 8 | 0x55ebf907ff3b 9 | 0x12de0ff4f91e 10 | 0x1dc51c11e809 11 | 0x1a22f705bb63 12 | 0x3a4c27e2d244 13 | 0x225fffc8ea25 14 | 0x62700ec0f5b6 15 | 0x1b28eedae8d3 16 | 0x25e1cd3e24d 17 | 0x516d1adbed00 18 | 0x3d7703daeffe 19 | 0x4162fec8c9fb 20 | 0x3035fbc32beb 21 | 0x4a252d06fa0f 22 | 0x4dee26521725 23 | 0x38b7f232fd08 24 | 0x12bb0f3ee9e3 25 | 0x1adafb17f7b4 26 | -------------------------------------------------------------------------------- /Software_project/Software/software_jupyter/Lenet_new_weight/Conv2_weight20combine6_0.txt: -------------------------------------------------------------------------------- 1 | 0x3225c51e2c 2 | 0x21427d62c0d 3 | 0x1d12c5230ffa 4 | 0xe10cc239f0ed 5 | 0xc105fe100f08 6 | 0xe41031d7b628 7 | 0xf2e613c3e4 8 | 0xf409b722ccaa 9 | 0xd52bf30dbcdb 10 | 0xb832fb03e80c 11 | 0xff82d1abb0a 12 | 0x25f7f036dfc4 13 | 0xdfff12ab8b2 14 | 0xd01903ecd31b 15 | 0xbc1213ec0d0e 16 | 0x1dc2a502fe5 17 | 0xffc4f3333edd 18 | 0xfdd4fce5e701 19 | 0x6e90a0f075a 20 | 0xe11cf2fe2126 21 | 0xeab4f02b05d2 22 | 0xeabefaf4f9f4 23 | 0x8ef07ea0531 24 | 0x32ebee112c3c 25 | 0x10070402331b 26 | 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0xc01cf8d3fb16 2 | 0xc625ecf808ff 3 | 0x9c15a405f9b3 4 | 0xb512cc00fe9c 5 | 0xb83a03f4ffda 6 | 0xf00829d995e7 7 | 0x1912f6f0afe5 8 | 0xff31d6f5c989 9 | 0x841dfc0a68c 10 | 0xd53c12f2d6e5 11 | 0x4bc43ad92493 12 | 0x69ca2ee247b0 13 | 0x791a17c235b0 14 | 0x400cf4cefecb 15 | 0x1105fde70bff 16 | 0xe2fd3bdc29d7 17 | 0xce13eb93500 18 | 0x2eee20c943fd 19 | 0x5bfecded1219 20 | 0x33f5c2f30c1c 21 | 0xa4d5e5f1e420 22 | 0x9cf11b0ae919 23 | 0xd7fc41e815fd 24 | 0xfeef1aeff603 25 | 0x22e4f5059e06 26 | -------------------------------------------------------------------------------- /Software_project/Software/software_jupyter/Lenet_new_weight/Conv2_weight31combine6_0.txt: -------------------------------------------------------------------------------- 1 | 0x21c92c092dec 2 | 0x2cfa11fa31ff 3 | 0x31def20f2308 4 | 0x1afaea1df303 5 | 0x341d082e0d0c 6 | 0x46cf1047143c 7 | 0x43071108d218 8 | 0x362021fd1c28 9 | 0x3ef1003a0c20 10 | 0x80d062bdf1c 11 | 0x1f4cfa1dc715 12 | 0x3a5836eac1ff 13 | 0x236934b6fdfd 14 | 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