├── README.md ├── Sdc.tcl ├── SynFlow.tcl └── main2.py /README.md: -------------------------------------------------------------------------------- 1 | # DC脚本使用步骤 2 | 3 | DC_script 4 | 5 | syn script for Design Compiler 6 | How to use: 7 | 8 | 1 确保要综合的RTL代码在的目录下没有别的多余文件和存放非RTL代码文件的子目录,同时新建一个空的目录作为工作目录。并拷贝python脚本至工作目录， 9 | 10 | `cp main2.py {WorkDir}` 11 | 12 | 2 设置要综合的RTL地址和top_module以及工艺库 13 | 14 | ```tcl 15 | main2.py修改3~5行 16 | 对应项目的指定目录 17 | script1_file_dir = "/xxx/SynFlow.tcl" 18 | script2_file_dir = "/xxx/Sdc.tcl" 19 | design_file_dir = "/xxxxx/xxx/" 20 | 21 | Sdc.tcl修改2~3行 22 | 对应顶层的时钟和复位 23 | set RST_NAME rst_n 24 | set CLK_NAME clk 25 | 26 | SynFlow.tcl修改第2~5行和24行 27 | 设置工艺库路径{2~5} 28 | set DESIGN_PATH /opt/PDKs/smic_180/SM00LB501-FE-00000-r0p0-00rel0/aci/sc-m/synopsys 29 | set search_path "$search_path $DESIGN_PATH" 30 | set target_library "ss_1v62_125c.db" 31 | set link_library "* $target_library" 32 | 设置顶层RTL的module{24} 33 | set TOP_DESIGN top_module 34 | ``` 35 | 36 | 3 根据不同设计修改script（可选） 37 | 38 | ​ 也可在编译的脚本后修改syn下的script；但需要手动开启DC也就是注释掉main.py最后一行改为 39 | 40 | `os.system('cd WORK ') ` 41 | 42 | 4 在工作目录下编译脚本 43 | 44 | `python3 main2.py ` 45 | 46 | 一定要用3.0以上的版本；原来写的脚本要在3.6以上的版本跑，我这个带EDA的虚拟机没装上zlib呜呜。白写了qwq 47 | 48 | 其中main2.py实现的功能有 49 | 50 | 1 将RTL和SDC自动拷贝至工作目录下/rtl和/syn/scripts下 51 | 52 | 2 自动创建/syn/mapped unmapped report WORK文件夹 53 | 54 | 3 自动生成RTL的filelist,文件多可以不用手敲了 55 | SynFlow中是DC脚本操作的流程 56 | Sdc中是时序和面积和IO约束（所有约束采用变量引用的方式书写，改动只需在文件头修改变量即可） 57 | 58 | 4 启动DC，进入工作目录WORK，读入script（新增功能是可以自动打开DC并链接脚本；若不想直接打开DC可以注释掉main.py最后一行） 59 | 60 | 61 | 62 | 63 | 64 | -------------------------------------------------------------------------------- /Sdc.tcl: -------------------------------------------------------------------------------- 1 | #==================================Env Vars=================================== 2 | set RST_NAME reset 3 | set CLK_NAME clk 4 | 5 | set CLK_PERIOD_I 10 6 | set CLK_PERIOD [expr $CLK_PERIOD_I*0.95] 7 | set CLK_SKEW [expr $CLK_PERIOD*0.05] 8 | set CLK_SOURCE_LATENCY [expr $CLK_PERIOD*0.1] 9 | set CLK_NETWORK_LATENCY [expr $CLK_PERIOD*0.1] 10 | set CLK_TRAN [expr $CLK_PERIOD*0.01] 11 | 12 | set INPUT_DELAY_MAX [expr $CLK_PERIOD*0.4] 13 | set INPUT_DELAY_MIN 0 14 | set OUTPUT_DELAY_MAX [expr $CLK_PERIOD*0.4] 15 | set OUTPUT_DELAY_MIN 0 16 | 17 | set MAX_FANOUT 6 18 | set MAX_TRAN 5 19 | set MAX_CAP 1.5 20 | 21 | set ALL_INPUT_EX_CLK [remove_from_collection [all_inputs] [get_ports $CLK_NAME]] 22 | #==================================Define Design Environment========================= 23 | #GUIDANCE: use the default 24 | set_max_area 0 25 | #set_max_transition $MAX_TRAN [current_design] 26 | #set_max_fanout $MAX_FANOUT [current_design] 27 | #set_max_capacitance $MAX_CAP [current_design] 28 | 29 | #============================= Set Design Constraints========================= 30 | #--------------------------------Clock and Reset Definition---------------------------- 31 | set_drive 0 [get_ports $CLK_NAME] 32 | create_clock -name $CLK_NAME -period $CLK_PERIOD [get_ports $CLK_NAME] 33 | set_dont_touch_network [get_ports $CLK_NAME] 34 | 35 | set_clock_uncertainty $CLK_SKEW [get_clocks $CLK_NAME] 36 | set_clock_transition $CLK_TRAN [all_clocks] 37 | set_clock_latency -source $CLK_SOURCE_LATENCY [get_clocks $CLK_NAME] 38 | set_clock_latency -max $CLK_NETWORK_LATENCY [get_clocks $CLK_NAME] 39 | #rst_ports 40 | set_drive 0 [get_ports $RST_NAME] 41 | set_dont_touch_network [get_ports $RST_NAME] 42 | set_false_path -from [get_ports $RST_NAME] 43 | set_ideal_network -no_propagate [get_ports $RST_NAME] 44 | 45 | 46 | #--------------------------------I/O Constraint----------------------------- 47 | set_input_delay -max $INPUT_DELAY_MAX -clock $CLK_NAME $ALL_INPUT_EX_CLK 48 | set_input_delay -min $INPUT_DELAY_MIN -clock $CLK_NAME $ALL_INPUT_EX_CLK -add 49 | set_output_delay -max $OUTPUT_DELAY_MAX -clock $CLK_NAME [all_outputs] 50 | set_output_delay -min $OUTPUT_DELAY_MIN -clock $CLK_NAME [all_outputs] -add 51 | set_load 0.2 [all_outputs] 52 | 53 | 54 | -------------------------------------------------------------------------------- /SynFlow.tcl: -------------------------------------------------------------------------------- 1 | #--------------------------Specify Libraries-------------------------- 2 | set DESIGN_PATH /opt/PDKs/smic_180/SM00LB501-FE-00000-r0p0-00rel0/aci/sc-m/synopsys 3 | set search_path "$search_path $DESIGN_PATH" 4 | set target_library "ss_1v62_125c.db" 5 | set link_library "* $target_library" 6 | echo "\n\nSettings:" 7 | echo "search_path: $search_path" 8 | echo "link_library: $link_library" 9 | echo "target_library: $target_library" 10 | echo "\n\nI'm Ready!" 11 | #set search_path "$TAR_PATH $MEM_LINK_PATH" 12 | 13 | #--------------------------Prepare Filelist--------------------------- 14 | set FILE_LIST "" 15 | set f [open "../files_syn.fl" r] 16 | while {![eof $f]} { 17 | gets $f line 18 | append FILE_LIST "$line " 19 | } 20 | echo $FILE_LIST 21 | close $f 22 | 23 | #--------------------------Read Designs------------------------------ 24 | set TOP_DESIGN pipeline 25 | analyze -format verilog $FILE_LIST 26 | elaborate $TOP_DESIGN 27 | 28 | #------------------------Set Current Design&&Link Designs-------------------------- 29 | #current_design $TOP_DESIGN(auto) 30 | #link(auto) 31 | 32 | #-------------------------------SDC---------------------------------- 33 | source ../syn/script/Sdc.tcl 34 | 35 | #--------------------Map and Optimize the Design--------------------- 36 | compile_ultra -no_autoungroup -incremental -no_boundary_optimization 37 | #----------------------Save Design Database-------------------------- 38 | change_names -rules verilog -hierarchy 39 | set_fix_multiple_port_nets -all -buffer_constants 40 | #---------------Check the Synthesized Design for Consistency--------- 41 | check_design -summary > ../syn/report/check_design.rpt 42 | check_timing > ../syn/report/check_timing.rpt 43 | #---------------------Report Timing and Area------------------------- 44 | report_qor > ../syn/report/$TOP_DESIGN.qor_rpt 45 | report_timing -max_paths 1000 > ../syn/report/$TOP_DESIGN.timing_rpt 46 | report_timing -path full > ../syn/report/$TOP_DESIGN.full_timing_rpt 47 | report_timing -delay max > ../syn/report/$TOP_DESIGN.setup_timing_rpt 48 | report_timing -delay min > ../syn/report/$TOP_DESIGN.hold_timing_rpt 49 | report_reference > ../syn/report/$TOP_DESIGN.ref_rpt 50 | report_area > ../syn/report/$TOP_DESIGN.area_rpt 51 | report_constraints > ../syn/report/$TOP_DESIGN.const_rpt 52 | report_constraint -all_violators > ../syn/report/$TOP_DESIGN.violators_rpt 53 | report_power > ../syn/report/$TOP_DESIGN.power_rpt 54 | check_timing > ../syn/log/last_check_timing.log 55 | #---------------------Generate Files ------------------------- 56 | write -f verilog -hierarchy -output ../syn/mapped/$TOP_DESIGN.v 57 | write_sdc ../syn/mapped/$TOP_DESIGN.sdc 58 | write_sdf -context verilog ../syn/mapped/$TOP_DESIGN.sdf 59 | -------------------------------------------------------------------------------- /main2.py: -------------------------------------------------------------------------------- 1 | import os 2 | 3 | script1_file_dir = "/home/IC/q/SynFlow.tcl" 4 | script2_file_dir = "/home/IC/q/Sdc.tcl" 5 | design_file_dir = "/home/IC/ridecore-master/src/fpga" 6 | 7 | def CopyScript(): 8 | os.system('cp {} ./syn/script/'.format(script1_file_dir)) 9 | os.system('cp {} ./syn/script/'.format(script2_file_dir)) 10 | 11 | def WriteFilelist(filename,wdata): 12 | with open(filename,'a') as file: 13 | file.write(wdata+"\n") 14 | 15 | def CopyAndCreatFilelist(file_dir): 16 | work_dir = "./rtl" 17 | os.system('rm -rf {}'.format(work_dir)) 18 | os.system('mkdir rtl') 19 | for root,dirs,files in os.walk(file_dir): 20 | for file in files: 21 | design = os.path.splitext(file)[0] 22 | if os.path.splitext(file)[1] == ".v": 23 | wdata ="{}/{}.v".format(root,design) 24 | WriteFilelist('./files_syn.fl',wdata) 25 | dir_path ="{}/{}.v".format(work_dir,design) 26 | source_path="{}/{}.v".format(root,design) 27 | os.system('cp {} {}'.format(source_path,dir_path)) 28 | elif os.path.splitext(file)[1] == ".vh": 29 | wdata ="{}/{}.vh".format(root,design) 30 | WriteFilelist("./files_syn.fl",wdata) 31 | dir_path ="{}/{}.vh".format(work_dir,design) 32 | source_path="{}/{}.vh".format(root,design) 33 | os.system('cp {} {}'.format(source_path,dir_path)) 34 | 35 | os.system('rm -rf ./rtl ./syn ./files_syn.fl ./WORK') 36 | os.system('mkdir -p ./rtl ./syn/mapped ./syn/report ./syn/script ./syn/unmapped ./WORK ./syn/log') 37 | CopyAndCreatFilelist(design_file_dir) 38 | CopyScript() 39 | os.system('cd WORK && dc_shell -f ../syn/script/SynFlow.tcl -gui -output_log_file ../syn/log/top_syn.log') 40 | --------------------------------------------------------------------------------