├── FederatedLearningFPGA
├── testbench
│ ├── tb_layer
│ │ ├── tb_hidden_layer.v
│ │ └── tb_input_layer.v
│ ├── tb_alu
│ │ ├── tb_ieee754_natural_exponential.v
│ │ ├── tb_ieee754_to_parts.v
│ │ ├── tb_ieee754_compare.v
│ │ ├── tb_ieee754_multiplier.v
│ │ ├── tb_ieee754_adder.v
│ │ └── tb_ieee754_divider.v
│ ├── tb_miscellaneous
│ │ ├── tb_memory.v
│ │ ├── tb_register.v
│ │ ├── tb_multiplexer_parametrized.v
│ │ └── tb_memory_32bit.v
│ └── tb_neuron
│ │ └── tb_relu.v
├── db
│ ├── NeuralNetworkFPGA.map.logdb
│ ├── NeuralNetworkFPGA.map_bb.logdb
│ ├── NeuralNetworkFPGA.smart_action.txt
│ ├── .cmp.kpt
│ ├── NeuralNetworkFPGA_partition_pins.json
│ ├── NeuralNetworkFPGA.hif
│ ├── NeuralNetworkFPGA.cbx.xml
│ ├── NeuralNetworkFPGA.asm.rdb
│ ├── NeuralNetworkFPGA.cmp.bpm
│ ├── NeuralNetworkFPGA.cmp.cdb
│ ├── NeuralNetworkFPGA.cmp.hdb
│ ├── NeuralNetworkFPGA.cmp.idb
│ ├── NeuralNetworkFPGA.cmp.rdb
│ ├── NeuralNetworkFPGA.lpc.rdb
│ ├── NeuralNetworkFPGA.map.ammdb
│ ├── NeuralNetworkFPGA.map.bpm
│ ├── NeuralNetworkFPGA.map.cdb
│ ├── NeuralNetworkFPGA.map.hdb
│ ├── NeuralNetworkFPGA.map.kpt
│ ├── NeuralNetworkFPGA.map.rdb
│ ├── NeuralNetworkFPGA.pplq.rdb
│ ├── NeuralNetworkFPGA.rtlv.hdb
│ ├── NeuralNetworkFPGA.sgate.nvd
│ ├── NeuralNetworkFPGA.sta.rdb
│ ├── NeuralNetworkFPGA.vpr.ammdb
│ ├── NeuralNetworkFPGA.(0).cnf.cdb
│ ├── NeuralNetworkFPGA.(0).cnf.hdb
│ ├── NeuralNetworkFPGA.(1).cnf.cdb
│ ├── NeuralNetworkFPGA.(1).cnf.hdb
│ ├── NeuralNetworkFPGA.(2).cnf.cdb
│ ├── NeuralNetworkFPGA.(2).cnf.hdb
│ ├── NeuralNetworkFPGA.(3).cnf.cdb
│ ├── NeuralNetworkFPGA.(3).cnf.hdb
│ ├── NeuralNetworkFPGA.(4).cnf.cdb
│ ├── NeuralNetworkFPGA.(4).cnf.hdb
│ ├── NeuralNetworkFPGA.(5).cnf.cdb
│ ├── NeuralNetworkFPGA.(5).cnf.hdb
│ ├── NeuralNetworkFPGA.(6).cnf.cdb
│ ├── NeuralNetworkFPGA.(6).cnf.hdb
│ ├── NeuralNetworkFPGA.(7).cnf.cdb
│ ├── NeuralNetworkFPGA.(7).cnf.hdb
│ ├── NeuralNetworkFPGA.(8).cnf.cdb
│ ├── NeuralNetworkFPGA.(8).cnf.hdb
│ ├── NeuralNetworkFPGA.(9).cnf.cdb
│ ├── NeuralNetworkFPGA.(9).cnf.hdb
│ ├── NeuralNetworkFPGA.map_bb.cdb
│ ├── NeuralNetworkFPGA.map_bb.hdb
│ ├── NeuralNetworkFPGA.pre_map.hdb
│ ├── NeuralNetworkFPGA.routing.rdb
│ ├── NeuralNetworkFPGA.rtlv_sg.cdb
│ ├── NeuralNetworkFPGA.(10).cnf.cdb
│ ├── NeuralNetworkFPGA.(10).cnf.hdb
│ ├── NeuralNetworkFPGA.(11).cnf.cdb
│ ├── NeuralNetworkFPGA.(11).cnf.hdb
│ ├── NeuralNetworkFPGA.(12).cnf.cdb
│ ├── NeuralNetworkFPGA.(12).cnf.hdb
│ ├── NeuralNetworkFPGA.(13).cnf.cdb
│ ├── NeuralNetworkFPGA.(13).cnf.hdb
│ ├── NeuralNetworkFPGA.(14).cnf.cdb
│ ├── NeuralNetworkFPGA.(14).cnf.hdb
│ ├── NeuralNetworkFPGA.(15).cnf.cdb
│ ├── NeuralNetworkFPGA.(15).cnf.hdb
│ ├── NeuralNetworkFPGA.(16).cnf.cdb
│ ├── NeuralNetworkFPGA.(16).cnf.hdb
│ ├── NeuralNetworkFPGA.(17).cnf.cdb
│ ├── NeuralNetworkFPGA.(17).cnf.hdb
│ ├── NeuralNetworkFPGA.(18).cnf.cdb
│ ├── NeuralNetworkFPGA.(18).cnf.hdb
│ ├── NeuralNetworkFPGA.(19).cnf.cdb
│ ├── NeuralNetworkFPGA.(19).cnf.hdb
│ ├── NeuralNetworkFPGA.(20).cnf.cdb
│ ├── NeuralNetworkFPGA.(20).cnf.hdb
│ ├── NeuralNetworkFPGA.(21).cnf.cdb
│ ├── NeuralNetworkFPGA.(21).cnf.hdb
│ ├── NeuralNetworkFPGA.(22).cnf.cdb
│ ├── NeuralNetworkFPGA.(22).cnf.hdb
│ ├── NeuralNetworkFPGA.(23).cnf.cdb
│ ├── NeuralNetworkFPGA.(23).cnf.hdb
│ ├── NeuralNetworkFPGA.(24).cnf.cdb
│ ├── NeuralNetworkFPGA.(24).cnf.hdb
│ ├── NeuralNetworkFPGA.(25).cnf.cdb
│ ├── NeuralNetworkFPGA.(25).cnf.hdb
│ ├── NeuralNetworkFPGA.(26).cnf.cdb
│ ├── NeuralNetworkFPGA.(26).cnf.hdb
│ ├── NeuralNetworkFPGA.(27).cnf.cdb
│ ├── NeuralNetworkFPGA.(27).cnf.hdb
│ ├── NeuralNetworkFPGA.asm_labs.ddb
│ ├── NeuralNetworkFPGA.atom_fit.nvd
│ ├── NeuralNetworkFPGA.atom_map.nvd
│ ├── NeuralNetworkFPGA.cmp_merge.kpt
│ ├── NeuralNetworkFPGA.sgate_sm.nvd
│ ├── NeuralNetworkFPGA.rtlv_sg_swap.cdb
│ ├── NeuralNetworkFPGA.sgate_sm_bdd.nvd
│ ├── NeuralNetworkFPGA.tis_db_list.ddb
│ ├── NeuralNetworkFPGA.sld_design_entry.sci
│ ├── NeuralNetworkFPGA.db_info
│ ├── NeuralNetworkFPGA.sld_design_entry_dsc.sci
│ ├── NeuralNetworkFPGA.tiscmp.fast_1200mv_0c.ddb
│ ├── NeuralNetworkFPGA.tiscmp.slow_1200mv_0c.ddb
│ ├── NeuralNetworkFPGA.tiscmp.slow_1200mv_85c.ddb
│ ├── NeuralNetworkFPGA.root_partition.map.reg_db.cdb
│ ├── NeuralNetworkFPGA.sta_cmp.7_slow_1200mv_85c.tdb
│ ├── NeuralNetworkFPGA.cycloneive_io_sim_cache.45um_ff_1200mv_0c_fast.hsd
│ ├── NeuralNetworkFPGA.cycloneive_io_sim_cache.45um_ii_1200mv_0c_slow.hsd
│ ├── NeuralNetworkFPGA.cycloneive_io_sim_cache.45um_ii_1200mv_85c_slow.hsd
│ ├── NeuralNetworkFPGA.tmw_info
│ ├── NeuralNetworkFPGA.npp.qmsg
│ ├── NeuralNetworkFPGA.asm.qmsg
│ ├── NeuralNetworkFPGA.eda.qmsg
│ └── NeuralNetworkFPGA.smp_dump.txt
├── output_files
│ ├── NeuralNetworkFPGA.sld
│ ├── NeuralNetworkFPGA.done
│ ├── NeuralNetworkFPGA.sof
│ ├── NeuralNetworkFPGA.fit.rpt
│ ├── NeuralNetworkFPGA.sta.summary
│ ├── NeuralNetworkFPGA.map.smsg
│ ├── NeuralNetworkFPGA.jdi
│ ├── Processor.v.bak
│ ├── NeuralNetworkFPGA.cdf
│ ├── NeuralNetworkFPGA.map.summary
│ ├── NeuralNetworkFPGA.fit.summary
│ ├── NeuralNetworkFPGA.fit.smsg
│ └── NeuralNetworkFPGA.asm.rpt
├── incremental_db
│ ├── compiled_partitions
│ │ ├── NeuralNetworkFPGA.root_partition.cmp.logdb
│ │ ├── NeuralNetworkFPGA.root_partition.map.hbdb.sig
│ │ ├── NeuralNetworkFPGA.rrp.hdb
│ │ ├── NeuralNetworkFPGA.db_info
│ │ ├── NeuralNetworkFPGA.root_partition.cmp.cdb
│ │ ├── NeuralNetworkFPGA.root_partition.cmp.dfp
│ │ ├── NeuralNetworkFPGA.root_partition.cmp.hdb
│ │ ├── NeuralNetworkFPGA.root_partition.map.cdb
│ │ ├── NeuralNetworkFPGA.root_partition.map.dpi
│ │ ├── NeuralNetworkFPGA.root_partition.map.hdb
│ │ ├── NeuralNetworkFPGA.root_partition.map.kpt
│ │ ├── NeuralNetworkFPGA.root_partition.cmp.ammdb
│ │ ├── NeuralNetworkFPGA.root_partition.cmp.rcfdb
│ │ ├── NeuralNetworkFPGA.root_partition.map.hbdb.cdb
│ │ ├── NeuralNetworkFPGA.root_partition.map.hbdb.hdb
│ │ └── NeuralNetworkFPGA.root_partition.map.hbdb.hb_info
│ └── README
├── simulation
│ └── questa
│ │ ├── NeuralNetworkFPGA.sft
│ │ ├── NeuralNetworkFPGA_run_msim_gate_verilog.do
│ │ ├── NeuralNetworkFPGA_run_msim_gate_verilog.do.bak
│ │ ├── NeuralNetworkFPGA_run_msim_rtl_verilog.do
│ │ └── NeuralNetworkFPGA_run_msim_rtl_verilog.do.bak
├── .qsys_edit
│ ├── filters.xml
│ └── preferences.xml
├── NeuralNetworkFPGA.qws
├── NeuralNetworkFPGA.v.bak
├── Readme
├── NeuralNetworkFPGA_nativelink_simulation.rpt
├── test_adder.v
├── ieee745ALU.v.bak
├── NeuralNetworkFPGA.qpf
├── memory_32bit.v
├── miscellaneous.v
├── z_module_analysis.py
├── NeuralNetworkFPGA.qsf
└── layer.v
├── DeepLearning
├── main
├── dataset
│ ├── spliter
│ ├── converter
│ ├── normalizer
│ ├── winetocsv
│ ├── iris
│ │ ├── database.sqlite
│ │ ├── datasetevaluation.csv
│ │ ├── datasettraining.csv
│ │ └── Iris.csv
│ ├── wine
│ │ ├── Index
│ │ ├── datasetevaluation.csv
│ │ ├── wine.names
│ │ └── datasetevaluationnormalized.csv
│ ├── glass
│ │ ├── Index
│ │ ├── glass.tag
│ │ ├── glass.names
│ │ └── datasetevaluation.csv
│ ├── datasetcsvonehot.c
│ ├── datasetnormalization.c
│ ├── datasetspliter.c
│ └── winetocsv.c
├── .gitignore
├── Makefile
└── federatedlearning.h
├── ProjectImages
├── struct.png
├── systemflow.png
└── hardwaresetup.png
├── CP210X driver
├── Windows
│ ├── slabvcp.cat
│ ├── x64
│ │ ├── silabser.sys
│ │ ├── WdfCoInstaller01009.dll
│ │ └── WdfCoInstaller01011.dll
│ ├── x86
│ │ ├── silabser.sys
│ │ ├── WdfCoInstaller01009.dll
│ │ └── WdfCoInstaller01011.dll
│ ├── CP210xVCPInstaller_x64.exe
│ └── CP210xVCPInstaller_x86.exe
└── Linux
│ ├── Linux_2.6.x_VCP_Driver_Source
│ ├── Makefile
│ ├── CP210x_VCP_Linux_2.6.x_Release_Notes.txt
│ └── cp210x_gpio_example.c
│ └── Linux_3.x.x_VCP_Driver_Source
│ ├── Makefile
│ ├── cp210x_gpio_example.c
│ └── CP210x_VCP_Linux_3.13.x_Release_Notes.txt
├── FederatedLearningServer
├── lib
│ ├── websocketserver.h
│ ├── httpserver.h
│ ├── websockethandlers.h
│ ├── JSONConverter.h
│ ├── httphandlers.h
│ └── federatedlearning.h
├── README.md
├── static
│ └── index.html
├── datasetevaluation.csv
├── data
│ └── datasetevaluation.csv
├── Makefile
├── src
│ ├── websockethandlers.c
│ └── httpserver.c
├── main.c
└── fedlearning.json
├── FederatedLearningESP32
├── components
│ ├── websocket
│ │ ├── websocketclient.h
│ │ ├── CMakeLists.txt
│ │ └── websocketclient.c
│ ├── cJSON
│ │ ├── JSONConverter.h
│ │ └── CMakeLists.txt
│ ├── federatedlearning
│ │ ├── CMakeLists.txt
│ │ └── federatedlearning.h
│ ├── http
│ │ ├── CMakeLists.txt
│ │ └── httpclient.h
│ ├── README
│ └── espwebsocketclient
│ │ └── CMakeLists.txt
├── main
│ ├── CMakeLists.txt
│ ├── espconfiguration.h
│ ├── main.c
│ └── espconfiguration.c
├── partitions.csv
├── CMakeLists.txt
├── data
│ ├── dataset1.csv
│ ├── dataset2.csv
│ ├── dataset3.csv
│ └── dataset.csv
└── README.md
└── .gitignore
/FederatedLearningFPGA/testbench/tb_layer/tb_hidden_layer.v:
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1 |
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/FederatedLearningFPGA/testbench/tb_layer/tb_input_layer.v:
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1 |
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/FederatedLearningFPGA/db/NeuralNetworkFPGA.map.logdb:
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1 | v1
2 |
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/FederatedLearningFPGA/db/NeuralNetworkFPGA.map_bb.logdb:
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1 | v1
2 |
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/FederatedLearningFPGA/db/NeuralNetworkFPGA.smart_action.txt:
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1 | DONE
2 |
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/FederatedLearningFPGA/output_files/NeuralNetworkFPGA.sld:
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1 |
2 |
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/FederatedLearningFPGA/output_files/NeuralNetworkFPGA.done:
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1 | Fri Dec 13 02:14:08 2024
2 |
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/DeepLearning/main:
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/FederatedLearningFPGA/incremental_db/compiled_partitions/NeuralNetworkFPGA.root_partition.cmp.logdb:
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1 | v1
2 |
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/FederatedLearningFPGA/simulation/questa/NeuralNetworkFPGA.sft:
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1 | set tool_name "Questa Intel FPGA (Verilog)"
2 |
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/FederatedLearningFPGA/.qsys_edit/filters.xml:
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1 |
2 |
3 |
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1 | c5eb7f6cdd530884c3b884e0a3668ea4
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/DeepLearning/.gitignore:
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1 | main
2 | main.exe
3 | dataset.exe
4 | dataset/converter
5 | dataset/normalizer
6 | dataset/spliter
7 | dataset/winetocsv
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/CP210X driver/Windows/x64/silabser.sys:
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/DeepLearning/Makefile:
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1 | all: clean build run
2 |
3 | clean:
4 | rm -rf main
5 | build:
6 | gcc -o main main.c -lm -Wall -Wextra -Ilib
7 | run:
8 | ./main
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/DeepLearning/dataset/wine/Index:
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1 | Index of wine
2 |
3 | 02 Dec 1996 105 Index
4 | 30 Oct 1995 10782 wine.data
5 | 19 Sep 1992 2643 wine.names
6 |
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/FederatedLearningFPGA/NeuralNetworkFPGA.qws:
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/FederatedLearningFPGA/db/NeuralNetworkFPGA_partition_pins.json:
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1 | {
2 | "partitions" : [
3 | {
4 | "name" : "Top",
5 | "pins" : []
6 | }
7 | ]
8 | }
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/FederatedLearningServer/lib/websocketserver.h:
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1 | #ifndef WEBSOCKETSERVER_H
2 | #define WEBSOCKETSERVER_H
3 |
4 | void *start_websocketserver(void *args);
5 |
6 | #endif
7 |
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/DeepLearning/dataset/glass/Index:
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1 | Index of glass
2 |
3 | 02 Dec 1996 139 Index
4 | 02 Mar 1993 11903 glass.data
5 | 16 Jul 1992 780 glass.tag
6 | 30 May 1989 3506 glass.names
7 |
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1 | Quartus_Version = Version 23.1std.1 Build 993 05/14/2024 SC Lite Edition
2 | Version_Index = 570679552
3 | Creation_Time = Fri Dec 13 09:19:37 2024
4 |
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/FederatedLearningServer/lib/httpserver.h:
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1 | #ifndef HTTPSERVER_H
2 | #define HTTPSERVER_H
3 |
4 | #define IP_ADDRESS "192.168.15.50"
5 |
6 | void *start_httpserver(void *args);
7 |
8 |
9 |
10 |
11 | #endif
12 |
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/FederatedLearningESP32/components/websocket/websocketclient.h:
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1 | #ifndef _websocketclient
2 | #define _websocketclient
3 |
4 | #define WEBSOCKET_SERVER "ws://192.168.15.50:8080/"
5 |
6 | void websocket_send_local_model();
7 |
8 | #endif
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1 | Quartus_Version = Version 23.1std.1 Build 993 05/14/2024 SC Lite Edition
2 | Version_Index = 570679552
3 | Creation_Time = Thu Sep 19 02:01:58 2024
4 |
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/FederatedLearningESP32/main/CMakeLists.txt:
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1 | idf_component_register(SRCS "espconfiguration.c" "main.c"
2 | INCLUDE_DIRS "."
3 |
4 |
5 | )
6 |
7 | spiffs_create_partition_image(storage ../data FLASH_IN_PROJECT)
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/CP210X driver/Linux/Linux_2.6.x_VCP_Driver_Source/Makefile:
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1 | obj-m = cp210x.o
2 | KVERSION = $(shell uname -r)
3 | all:
4 | make -C /lib/modules/$(KVERSION)/build M=$(PWD) modules
5 | clean:
6 | make -C /lib/modules/$(KVERSION)/build M=$(PWD) clean
7 |
8 |
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/CP210X driver/Linux/Linux_3.x.x_VCP_Driver_Source/Makefile:
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1 | obj-m = cp210x.o
2 | KVERSION = $(shell uname -r)
3 | all:
4 | make -C /lib/modules/$(KVERSION)/build M=$(PWD) modules
5 | clean:
6 | make -C /lib/modules/$(KVERSION)/build M=$(PWD) clean
7 |
8 |
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/FederatedLearningServer/lib/websockethandlers.h:
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1 | #ifndef WEBSOCKETHANDLERS_H
2 | #define WEBSOCKETHANDLERS_H
3 |
4 | #define IP_ADDRESS "192.168.15.50"
5 |
6 | void handle_clint_model_message(const char * message, int length,char *ip_addr);
7 |
8 | #endif
9 |
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/FederatedLearningFPGA/incremental_db/compiled_partitions/NeuralNetworkFPGA.root_partition.map.hbdb.hdb:
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https://raw.githubusercontent.com/GitScrider/FederatedEdgeComputing/HEAD/FederatedLearningFPGA/incremental_db/compiled_partitions/NeuralNetworkFPGA.root_partition.map.hbdb.hdb
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/.gitignore:
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1 | .vscode
2 | FederatedLearningESP32/build
3 | FederatedLearningESP32/.devcontainer
4 | FederatedLearningESP32/.vscode
5 | FederatedLearningServer/.vscode
6 | FederatedLearningServer/.build
7 | FederatedLearningServer/FederatedLearningServer
8 |
9 |
10 |
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/FederatedLearningFPGA/incremental_db/compiled_partitions/NeuralNetworkFPGA.root_partition.map.hbdb.hb_info:
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https://raw.githubusercontent.com/GitScrider/FederatedEdgeComputing/HEAD/FederatedLearningFPGA/incremental_db/compiled_partitions/NeuralNetworkFPGA.root_partition.map.hbdb.hb_info
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/FederatedLearningFPGA/output_files/NeuralNetworkFPGA.sta.summary:
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1 | ------------------------------------------------------------
2 | Timing Analyzer Summary
3 | ------------------------------------------------------------
4 |
5 | ------------------------------------------------------------
6 |
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/FederatedLearningFPGA/output_files/NeuralNetworkFPGA.map.smsg:
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1 | Warning (10268): Verilog HDL information at Processor.v(31): always construct contains both blocking and non-blocking assignments File: C:/Development/FederatedEdgeComputing/FederatedLearningFPGA/output_files/Processor.v Line: 31
2 |
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/FederatedLearningFPGA/simulation/questa/NeuralNetworkFPGA_run_msim_gate_verilog.do:
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1 | transcript on
2 | if {[file exists gate_work]} {
3 | vdel -lib gate_work -all
4 | }
5 | vlib gate_work
6 | vmap work gate_work
7 |
8 | vlog -vlog01compat -work work +incdir+. {NeuralNetworkFPGA.vo}
9 |
10 |
--------------------------------------------------------------------------------
/FederatedLearningFPGA/simulation/questa/NeuralNetworkFPGA_run_msim_gate_verilog.do.bak:
--------------------------------------------------------------------------------
1 | transcript on
2 | if {[file exists gate_work]} {
3 | vdel -lib gate_work -all
4 | }
5 | vlib gate_work
6 | vmap work gate_work
7 |
8 | vlog -vlog01compat -work work +incdir+. {NeuralNetworkFPGA.vo}
9 |
10 |
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/FederatedLearningFPGA/output_files/NeuralNetworkFPGA.jdi:
--------------------------------------------------------------------------------
1 |
2 |
3 |
4 |
5 |
6 |
7 |
8 |
9 |
--------------------------------------------------------------------------------
/FederatedLearningESP32/partitions.csv:
--------------------------------------------------------------------------------
1 | # Name, Type, SubType, Offset, Size, Flags
2 | nvs, data, nvs, 0x9000, 0x4000,
3 | phy_init, data, phy, 0xf000, 0x1000,
4 | factory, app, factory, 0x10000, 0x200000,
5 | storage, data, spiffs, 0x210000, 0x100000,
6 |
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/FederatedLearningServer/lib/JSONConverter.h:
--------------------------------------------------------------------------------
1 | #ifndef HTTPHANDLERS_H
2 | #define HTTPHANDLERS_H
3 |
4 | #include "federatedlearning.h"
5 | #include "../lib/cJSON.h"
6 |
7 | cJSON* FederatedLearningToJSON(FederatedLearning* federatedLearning);
8 | FederatedLearning* JSONToFederatedLearning(const cJSON* json);
9 |
10 | #endif
--------------------------------------------------------------------------------
/FederatedLearningESP32/components/cJSON/JSONConverter.h:
--------------------------------------------------------------------------------
1 | #ifndef _jsonconverter
2 | #define _jsonconverter
3 |
4 | #include "federatedlearning.h"
5 | #include "cJSON.h"
6 |
7 | cJSON* federatedLearningToJSON(const FederatedLearning* federatedLearning);
8 | FederatedLearning* JSONToFederatedLearning(const cJSON* json);
9 |
10 | #endif
--------------------------------------------------------------------------------
/FederatedLearningFPGA/NeuralNetworkFPGA.v.bak:
--------------------------------------------------------------------------------
1 | module NeuralNetworkFPGA(
2 | input wire CLOCK_50,
3 | output reg [7:0] LEDG
4 | );
5 |
6 | reg [24:0] counter;
7 |
8 | always @(posedge CLOCK_50) begin
9 | counter <= counter + 1;
10 | if (counter == 0) begin
11 | LEDG <= ~LEDG;
12 | end
13 | end
14 |
15 | endmodule
--------------------------------------------------------------------------------
/FederatedLearningFPGA/output_files/Processor.v.bak:
--------------------------------------------------------------------------------
1 |
2 |
3 |
4 | module arithmetic_logic_unit ();
5 |
6 | module
7 |
8 | module cache_data ();
9 |
10 | endmodule
11 |
12 | module instruction chache ();
13 |
14 | endmodule
15 |
16 |
17 | module clock_control ();
18 |
19 | endmodule
20 |
21 | module processor ();
22 |
23 | endmodule
--------------------------------------------------------------------------------
/FederatedLearningESP32/components/cJSON/CMakeLists.txt:
--------------------------------------------------------------------------------
1 | # CMakeLists.txt inside lib/FederatedLearning
2 |
3 | idf_component_register(
4 | SRCS "cJSON.c" "JSONConverter.c"
5 | INCLUDE_DIRS "."
6 | REQUIRES federatedlearning
7 | )
8 |
9 | # Adicione esta linha para tornar o diretório um componente IDF
10 | # set(COMPONENT_ADD_INCLUDEDIRS ".")
11 |
--------------------------------------------------------------------------------
/FederatedLearningFPGA/output_files/NeuralNetworkFPGA.cdf:
--------------------------------------------------------------------------------
1 | /* Quartus Prime Version 23.1std.1 Build 993 05/14/2024 SC Lite Edition */
2 | JedecChain;
3 | FileRevision(JESD32A);
4 | DefaultMfr(6E);
5 |
6 | P ActionCode(Ign)
7 | Device PartName(EP4CE115) MfrSpec(OpMask(0));
8 |
9 | ChainEnd;
10 |
11 | AlteraBegin;
12 | ChainType(JTAG);
13 | AlteraEnd;
14 |
--------------------------------------------------------------------------------
/FederatedLearningESP32/components/federatedlearning/CMakeLists.txt:
--------------------------------------------------------------------------------
1 | # CMakeLists.txt inside lib/FederatedLearning
2 |
3 | idf_component_register(
4 | SRCS "federatedlearning.c"
5 | INCLUDE_DIRS "."
6 | REQUIRES spiffs
7 | )
8 |
9 | # Adicione esta linha para tornar o diretório um componente IDF
10 | # set(COMPONENT_ADD_INCLUDEDIRS ".")
11 |
12 |
13 |
14 |
--------------------------------------------------------------------------------
/FederatedLearningESP32/components/http/CMakeLists.txt:
--------------------------------------------------------------------------------
1 | # CMakeLists.txt inside lib/FederatedLearning
2 |
3 | idf_component_register(
4 | SRCS "httpclient.c"
5 | INCLUDE_DIRS "."
6 | REQUIRES esp_http_client esp_timer federatedlearning cJSON
7 | )
8 |
9 | # Adicione esta linha para tornar o diretório um componente IDF
10 | # set(COMPONENT_ADD_INCLUDEDIRS ".")
11 |
--------------------------------------------------------------------------------
/FederatedLearningESP32/components/websocket/CMakeLists.txt:
--------------------------------------------------------------------------------
1 | # CMakeLists.txt inside lib/
2 |
3 | idf_component_register(
4 | SRCS "websocketclient.c"
5 | INCLUDE_DIRS "."
6 | REQUIRES esp_event espwebsocketclient cJSON federatedlearning
7 | )
8 |
9 | # Adicione esta linha para tornar o diretório um componente IDF
10 | # set(COMPONENT_ADD_INCLUDEDIRS ".")
11 |
--------------------------------------------------------------------------------
/FederatedLearningFPGA/db/NeuralNetworkFPGA.tmw_info:
--------------------------------------------------------------------------------
1 | start_full_compilation:s:00:00:35
2 | start_analysis_synthesis:s:00:00:12-start_full_compilation
3 | start_analysis_elaboration:s-start_full_compilation
4 | start_fitter:s:00:00:13-start_full_compilation
5 | start_assembler:s:00:00:04-start_full_compilation
6 | start_timing_analyzer:s:00:00:04-start_full_compilation
7 | start_eda_netlist_writer:s:00:00:02-start_full_compilation
8 |
--------------------------------------------------------------------------------
/FederatedLearningFPGA/.qsys_edit/preferences.xml:
--------------------------------------------------------------------------------
1 |
2 |
3 |
4 |
5 |
6 |
7 |
8 |
9 |
10 |
11 |
12 |
13 |
--------------------------------------------------------------------------------
/DeepLearning/federatedlearning.h:
--------------------------------------------------------------------------------
1 | #ifndef _federatedlearning
2 | #define _federatedlearning
3 |
4 | //activation function
5 | #define PERCEPTRON 1
6 | #define RELU 2
7 | #define SIGMOID 3
8 |
9 | //output activation function
10 |
11 | #define SOFTMAX 4
12 |
13 | //loss function
14 | #define MINIMAL_MEAN_SQUARE 1
15 | #define CATEGORICAL_CROSS_ENTROPY 2
16 |
17 | //regularization
18 | #define NONE_REGULARIZATION 0
19 | #define L2 2
20 | #define L1 1
21 |
22 | #endif
--------------------------------------------------------------------------------
/FederatedLearningServer/README.md:
--------------------------------------------------------------------------------
1 | # FederatedLearningServer
2 |
3 |
4 | This is the Federated Server responsible for merge and distribute the global model for the ESP32 Clients for the training.
5 |
6 | The directory src have the necessary files and the lib directory is the .h correlated.
7 |
8 | The Makefile is configured as follows:
9 | * make: compile and generated the program
10 | * make clean: force remove of .o files inside the .build directory and the program file
11 | * make run: execute the program file
--------------------------------------------------------------------------------
/FederatedLearningFPGA/output_files/NeuralNetworkFPGA.map.summary:
--------------------------------------------------------------------------------
1 | Analysis & Synthesis Status : Successful - Fri Dec 13 02:13:09 2024
2 | Quartus Prime Version : 23.1std.1 Build 993 05/14/2024 SC Lite Edition
3 | Revision Name : NeuralNetworkFPGA
4 | Top-level Entity Name : NeuralNetworkFPGA
5 | Family : Cyclone IV E
6 | Total logic elements : 0
7 | Total combinational functions : 0
8 | Dedicated logic registers : 0
9 | Total registers : 0
10 | Total pins : 76
11 | Total virtual pins : 0
12 | Total memory bits : 0
13 | Embedded Multiplier 9-bit elements : 0
14 | Total PLLs : 0
15 |
--------------------------------------------------------------------------------
/FederatedLearningFPGA/simulation/questa/NeuralNetworkFPGA_run_msim_rtl_verilog.do:
--------------------------------------------------------------------------------
1 | transcript on
2 | if {[file exists rtl_work]} {
3 | vdel -lib rtl_work -all
4 | }
5 | vlib rtl_work
6 | vmap work rtl_work
7 |
8 | vlog -vlog01compat -work work +incdir+C:/Development/FederatedEdgeComputing/FederatedLearningFPGA {C:/Development/FederatedEdgeComputing/FederatedLearningFPGA/NeuralNetworkFPGA.v}
9 | vlog -vlog01compat -work work +incdir+C:/Development/FederatedEdgeComputing/FederatedLearningFPGA/output_files {C:/Development/FederatedEdgeComputing/FederatedLearningFPGA/output_files/Processor.v}
10 |
11 |
--------------------------------------------------------------------------------
/FederatedLearningFPGA/simulation/questa/NeuralNetworkFPGA_run_msim_rtl_verilog.do.bak:
--------------------------------------------------------------------------------
1 | transcript on
2 | if {[file exists rtl_work]} {
3 | vdel -lib rtl_work -all
4 | }
5 | vlib rtl_work
6 | vmap work rtl_work
7 |
8 | vlog -vlog01compat -work work +incdir+C:/Development/FederatedEdgeComputing/FederatedLearningFPGA {C:/Development/FederatedEdgeComputing/FederatedLearningFPGA/NeuralNetworkFPGA.v}
9 | vlog -vlog01compat -work work +incdir+C:/Development/FederatedEdgeComputing/FederatedLearningFPGA/output_files {C:/Development/FederatedEdgeComputing/FederatedLearningFPGA/output_files/Processor.v}
10 |
11 |
--------------------------------------------------------------------------------
/FederatedLearningESP32/main/espconfiguration.h:
--------------------------------------------------------------------------------
1 | #ifndef _espconfiguration
2 | #define _espconfiguration
3 |
4 | #include "driver/gpio.h"
5 | #include "driver/uart.h"
6 |
7 | #include "nvs_flash.h"
8 |
9 | #include "esp_log.h"
10 | #include "esp_wifi.h"
11 | #include "esp_spiffs.h"
12 |
13 |
14 | #define LED_PIN_ERROR 12
15 | #define LED_PIN_WORKING 14
16 | #define LED_PIN_SYNC 27
17 | #define BUTTON_PIN 26
18 |
19 |
20 | #define WIFI_SSID "56kbps2.4GHz"
21 | #define WIFI_PASSWORD "3392F15f16"
22 |
23 | void WIFIConfiguration();
24 | void UARTConfiguration();
25 | void GPIOConfiguration();
26 | void SPIFFSConfiguration();
27 | #endif
--------------------------------------------------------------------------------
/FederatedLearningServer/lib/httphandlers.h:
--------------------------------------------------------------------------------
1 | #ifndef HTTPHANDLERS_H
2 | #define HTTPHANDLERS_H
3 |
4 | //test
5 | void handle_testpost_request(int client_socket, const char *request_body);
6 | void handle_testget_request(int client_socket);
7 | //page
8 | void handle_root_request(int client_socket);
9 | //api
10 | void handle_get_noderegister(int client_socket,char *ip_addr);
11 | void handle_get_globalmodel(int client_socket);
12 | void handle_post_globalmodel(int client_socket,const char *request_body);
13 | void handle_get_checkmodelstatus(int client_socket,char *ip_addr);
14 | void handle_not_found_request(int client_socket);
15 |
16 | #endif
17 |
--------------------------------------------------------------------------------
/FederatedLearningFPGA/Readme:
--------------------------------------------------------------------------------
1 |
2 |
3 | iverilog -o icarus_testbench .\testbench\tb_alu\tb_ieee754_multiplier.v .\alu.v
4 | vvp .\icarus_testbench
5 |
6 |
7 | *Behavior Level
8 |
9 | *RTL (Register Transfer Level)
10 |
11 | *Formal Verification ABV - SVA / PSL
12 |
13 | *TestBench
14 |
15 | *Circuit Level
16 |
17 |
18 |
19 | MODULES
20 |
21 | ->ALU
22 | add mul div natexp
23 |
24 | ->NEURON
25 | z memory mux
26 | ->InputNeuron
27 |
28 | ->HiddenNeuron
29 | relu
30 | ->OutputNeuron
31 | softmax
32 |
33 | ->LAYER
34 |
35 | ->NEURAL-NETWORK
36 |
37 |
38 |
39 |
40 |
--------------------------------------------------------------------------------
/FederatedLearningServer/static/index.html:
--------------------------------------------------------------------------------
1 |
2 |
3 |
4 | Minha Página
5 |
6 |
7 |
8 |
9 |
10 |
11 |
12 |
13 | Federated Learning Server
14 |
15 |
16 |
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/FederatedLearningESP32/CMakeLists.txt:
--------------------------------------------------------------------------------
1 | # The following lines of boilerplate have to be in your project's CMakeLists
2 | # in this exact order for cmake to work correctly
3 | cmake_minimum_required(VERSION 3.16)
4 |
5 | include($ENV{IDF_PATH}/tools/cmake/project.cmake)
6 | project(FederatedLearningESP32)
7 |
8 | idf_build_set_property(COMPILE_OPTIONS "-Wno-error" APPEND)
9 |
10 |
11 | list(APPEND EXTRA_COMPONENT_DIRS "components/federatedfearning")
12 | list(APPEND EXTRA_COMPONENT_DIRS "components/http")
13 | list(APPEND EXTRA_COMPONENT_DIRS "components/CJSON")
14 | list(APPEND EXTRA_COMPONENT_DIRS "components/websocket")
15 | list(APPEND EXTRA_COMPONENT_DIRS "components/espwebsocketclient")
16 |
--------------------------------------------------------------------------------
/FederatedLearningFPGA/incremental_db/README:
--------------------------------------------------------------------------------
1 | This folder contains data for incremental compilation.
2 |
3 | The compiled_partitions sub-folder contains previous compilation results for each partition.
4 | As long as this folder is preserved, incremental compilation results from earlier compiles
5 | can be re-used. To perform a clean compilation from source files for all partitions, both
6 | the db and incremental_db folder should be removed.
7 |
8 | The imported_partitions sub-folder contains the last imported QXP for each imported partition.
9 | As long as this folder is preserved, imported partitions will be automatically re-imported
10 | when the db or incremental_db/compiled_partitions folders are removed.
11 |
12 |
--------------------------------------------------------------------------------
/FederatedLearningFPGA/output_files/NeuralNetworkFPGA.fit.summary:
--------------------------------------------------------------------------------
1 | Fitter Status : Successful - Fri Dec 13 02:13:22 2024
2 | Quartus Prime Version : 23.1std.1 Build 993 05/14/2024 SC Lite Edition
3 | Revision Name : NeuralNetworkFPGA
4 | Top-level Entity Name : NeuralNetworkFPGA
5 | Family : Cyclone IV E
6 | Device : EP4CE115F29C7
7 | Timing Models : Final
8 | Total logic elements : 0 / 114,480 ( 0 % )
9 | Total combinational functions : 0 / 114,480 ( 0 % )
10 | Dedicated logic registers : 0 / 114,480 ( 0 % )
11 | Total registers : 0
12 | Total pins : 76 / 529 ( 14 % )
13 | Total virtual pins : 0
14 | Total memory bits : 0 / 3,981,312 ( 0 % )
15 | Embedded Multiplier 9-bit elements : 0 / 532 ( 0 % )
16 | Total PLLs : 0 / 4 ( 0 % )
17 |
--------------------------------------------------------------------------------
/FederatedLearningFPGA/output_files/NeuralNetworkFPGA.fit.smsg:
--------------------------------------------------------------------------------
1 | Extra Info (176273): Performing register packing on registers with non-logic cell location assignments
2 | Extra Info (176274): Completed register packing on registers with non-logic cell location assignments
3 | Extra Info (176236): Started Fast Input/Output/OE register processing
4 | Extra Info (176237): Finished Fast Input/Output/OE register processing
5 | Extra Info (176238): Start inferring scan chains for DSP blocks
6 | Extra Info (176239): Inferring scan chains for DSP blocks is complete
7 | Extra Info (176248): Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density
8 | Extra Info (176249): Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks
9 |
--------------------------------------------------------------------------------
/FederatedLearningESP32/components/http/httpclient.h:
--------------------------------------------------------------------------------
1 | #ifndef _httpclient
2 | #define _httpclient
3 |
4 | #include "esp_http_client.h"
5 | #include "federatedlearning.h"
6 | #include "JSONConverter.h"
7 |
8 |
9 | #define MAX_RETRIES 3
10 | #define TIMEOUT_MS 1000
11 |
12 | #define GET_GLOBAL_MODEL "http://192.168.15.50:8888/api/getglobalmodel"
13 | #define GET_GLOBAL_MODEL_STATUS "http://192.168.15.50:8888/api/checkglobalmodel"
14 | #define GET_REGISTER_NODE "http://192.168.15.50:8888/api/noderegister"
15 | #define POST_GLOBAL_MODEL "http://192.168.15.50:8888/api/postglobalmodel"
16 |
17 | FederatedLearning* getglobalmodel();
18 | int getglobalmodelstatus();
19 | void postglobalmodel();
20 | void getregisternode();
21 | void http_post_task(void *pvParameters);
22 |
23 | #endif
--------------------------------------------------------------------------------
/FederatedLearningFPGA/testbench/tb_alu/tb_ieee754_natural_exponential.v:
--------------------------------------------------------------------------------
1 | `timescale 1ns/1ns
2 |
3 | module tb_ieee754_divider;
4 |
5 | parameter ITER = 10;
6 |
7 | reg clock;
8 | reg reset;
9 | reg [31:0] A;
10 | wire [31:0] result;
11 | wire done;
12 |
13 | ieee754_natural_exponential #(ITER) uut (
14 | .clock(clock),
15 | .reset(reset),
16 | .A(A),
17 | .result(result),
18 | .done(done)
19 | );
20 |
21 | always #10 clock = ~clock;
22 |
23 | initial begin
24 |
25 | clock = 0;
26 | reset = 1;
27 | A = 32'h40400000; // 3.0
28 |
29 | #25;
30 | reset = 0;
31 |
32 | wait(done);
33 | $display("Time: %t | A: %h | Result: %h",$time, A, result);
34 | $finish;
35 |
36 | end
37 |
38 | endmodule
--------------------------------------------------------------------------------
/CP210X driver/Linux/Linux_3.x.x_VCP_Driver_Source/cp210x_gpio_example.c:
--------------------------------------------------------------------------------
1 | #include
2 | #include
3 | #include
4 | #include
5 |
6 | using namespace std;
7 |
8 | int main()
9 | {
10 | int fd;
11 | cout << "CP210x Serial Test\n";
12 | fd = open("/dev/ttyUSB0", O_RDWR | O_NOCTTY | O_NDELAY);
13 | if (fd == -1)
14 | {
15 | cout << "Error opening port /dev/ttyUSB0\n";
16 | return -1;
17 | }
18 |
19 | unsigned long gpio;
20 |
21 | ioctl(fd, 0x8000, &gpio);
22 | cout << "original gpio = ";
23 | cout << hex << gpio << endl;
24 | gpio = ~gpio;
25 | gpio = gpio << 8;
26 | gpio |= 0x00FF;
27 | cout << "gpio = ";
28 | cout << hex << gpio << endl;
29 | ioctl(fd, 0x8001, &gpio);
30 | ioctl(fd, 0x8000, &gpio);
31 | cout << "new gpio = ";
32 | cout << hex << gpio << endl;
33 |
34 | close(fd);
35 |
36 | return 0;
37 | }
38 |
--------------------------------------------------------------------------------
/DeepLearning/dataset/glass/glass.tag:
--------------------------------------------------------------------------------
1 | An original file donated by Vina Speihler
2 |
3 | ID, N -- numeric identifier of the instance
4 | RI, N -- refractive index
5 | NA2O, N -- Sodium oxide
6 | MGO, N -- magnesium oxide
7 | AL2O3, N -- aluminum oxide
8 | SIO2, N -- silcon oxide
9 | K2O, N -- potassium oxide
10 | CAO, N -- calcium oxide
11 | BAO, N -- barium oxide
12 | FE2O3, N -- iron oxide
13 | TYPE, N -- An unknown, but must correspond to the types in the paper
14 | CAMG, N -- Unsure
15 |
16 | Types include:
17 | 1. WF (Float Window)
18 | 2. WNF (Non-float Window)
19 | 3. C (Container)
20 | 4. T (Tableware)
21 | 5. H (Headlamp) 214 2568 14127 glass.dat
22 | 19 92 518 glass.tag
23 | 62 742 4775 glassx.dat
24 | 51 610 3928 nonwindo.dat
25 | 6 14 120 phones
26 | 163 1955 12552 window.dat
27 | 515 5981 36020 total
28 |
--------------------------------------------------------------------------------
/DeepLearning/dataset/iris/datasetevaluation.csv:
--------------------------------------------------------------------------------
1 | 75,6.4,2.9,4.3,1.3,0,1,0
2 | 121,6.9,3.2,5.7,2.3,0,0,1
3 | 145,6.7,3.3,5.7,2.5,0,0,1
4 | 65,5.6,2.9,3.6,1.3,0,1,0
5 | 133,6.4,2.8,5.6,2.2,0,0,1
6 | 108,7.3,2.9,6.3,1.8,0,0,1
7 | 34,5.5,4.2,1.4,0.2,1,0,0
8 | 80,5.7,2.6,3.5,1.0,0,1,0
9 | 62,5.9,3.0,4.2,1.5,0,1,0
10 | 135,6.1,2.6,5.6,1.4,0,0,1
11 | 123,7.7,2.8,6.7,2.0,0,0,1
12 | 18,5.1,3.5,1.4,0.3,1,0,0
13 | 47,5.1,3.8,1.6,0.2,1,0,0
14 | 124,6.3,2.7,4.9,1.8,0,0,1
15 | 76,6.6,3.0,4.4,1.4,0,1,0
16 | 19,5.7,3.8,1.7,0.3,1,0,0
17 | 36,5.0,3.2,1.2,0.2,1,0,0
18 | 97,5.7,2.9,4.2,1.3,0,1,0
19 | 149,6.2,3.4,5.4,2.3,0,0,1
20 | 27,5.0,3.4,1.6,0.4,1,0,0
21 | 82,5.5,2.4,3.7,1.0,0,1,0
22 | 86,6.0,3.4,4.5,1.6,0,1,0
23 | 81,5.5,2.4,3.8,1.1,0,1,0
24 | 141,6.7,3.1,5.6,2.4,0,0,1
25 | 16,5.7,4.4,1.5,0.4,1,0,0
26 | 137,6.3,3.4,5.6,2.4,0,0,1
27 | 78,6.7,3.0,5.0,1.7,0,1,0
28 | 58,4.9,2.4,3.3,1.0,0,1,0
29 | 69,6.2,2.2,4.5,1.5,0,1,0
30 | 64,6.1,2.9,4.7,1.4,0,1,0
--------------------------------------------------------------------------------
/FederatedLearningServer/datasetevaluation.csv:
--------------------------------------------------------------------------------
1 | 75,6.4,2.9,4.3,1.3,0,1,0
2 | 121,6.9,3.2,5.7,2.3,0,0,1
3 | 145,6.7,3.3,5.7,2.5,0,0,1
4 | 65,5.6,2.9,3.6,1.3,0,1,0
5 | 133,6.4,2.8,5.6,2.2,0,0,1
6 | 108,7.3,2.9,6.3,1.8,0,0,1
7 | 34,5.5,4.2,1.4,0.2,1,0,0
8 | 80,5.7,2.6,3.5,1.0,0,1,0
9 | 62,5.9,3.0,4.2,1.5,0,1,0
10 | 135,6.1,2.6,5.6,1.4,0,0,1
11 | 123,7.7,2.8,6.7,2.0,0,0,1
12 | 18,5.1,3.5,1.4,0.3,1,0,0
13 | 47,5.1,3.8,1.6,0.2,1,0,0
14 | 124,6.3,2.7,4.9,1.8,0,0,1
15 | 76,6.6,3.0,4.4,1.4,0,1,0
16 | 19,5.7,3.8,1.7,0.3,1,0,0
17 | 36,5.0,3.2,1.2,0.2,1,0,0
18 | 97,5.7,2.9,4.2,1.3,0,1,0
19 | 149,6.2,3.4,5.4,2.3,0,0,1
20 | 27,5.0,3.4,1.6,0.4,1,0,0
21 | 82,5.5,2.4,3.7,1.0,0,1,0
22 | 86,6.0,3.4,4.5,1.6,0,1,0
23 | 81,5.5,2.4,3.8,1.1,0,1,0
24 | 141,6.7,3.1,5.6,2.4,0,0,1
25 | 16,5.7,4.4,1.5,0.4,1,0,0
26 | 137,6.3,3.4,5.6,2.4,0,0,1
27 | 78,6.7,3.0,5.0,1.7,0,1,0
28 | 58,4.9,2.4,3.3,1.0,0,1,0
29 | 69,6.2,2.2,4.5,1.5,0,1,0
30 | 64,6.1,2.9,4.7,1.4,0,1,0
--------------------------------------------------------------------------------
/FederatedLearningServer/data/datasetevaluation.csv:
--------------------------------------------------------------------------------
1 | 75,6.4,2.9,4.3,1.3,0,1,0
2 | 121,6.9,3.2,5.7,2.3,0,0,1
3 | 145,6.7,3.3,5.7,2.5,0,0,1
4 | 65,5.6,2.9,3.6,1.3,0,1,0
5 | 133,6.4,2.8,5.6,2.2,0,0,1
6 | 108,7.3,2.9,6.3,1.8,0,0,1
7 | 34,5.5,4.2,1.4,0.2,1,0,0
8 | 80,5.7,2.6,3.5,1.0,0,1,0
9 | 62,5.9,3.0,4.2,1.5,0,1,0
10 | 135,6.1,2.6,5.6,1.4,0,0,1
11 | 123,7.7,2.8,6.7,2.0,0,0,1
12 | 18,5.1,3.5,1.4,0.3,1,0,0
13 | 47,5.1,3.8,1.6,0.2,1,0,0
14 | 124,6.3,2.7,4.9,1.8,0,0,1
15 | 76,6.6,3.0,4.4,1.4,0,1,0
16 | 19,5.7,3.8,1.7,0.3,1,0,0
17 | 36,5.0,3.2,1.2,0.2,1,0,0
18 | 97,5.7,2.9,4.2,1.3,0,1,0
19 | 149,6.2,3.4,5.4,2.3,0,0,1
20 | 27,5.0,3.4,1.6,0.4,1,0,0
21 | 82,5.5,2.4,3.7,1.0,0,1,0
22 | 86,6.0,3.4,4.5,1.6,0,1,0
23 | 81,5.5,2.4,3.8,1.1,0,1,0
24 | 141,6.7,3.1,5.6,2.4,0,0,1
25 | 16,5.7,4.4,1.5,0.4,1,0,0
26 | 137,6.3,3.4,5.6,2.4,0,0,1
27 | 78,6.7,3.0,5.0,1.7,0,1,0
28 | 58,4.9,2.4,3.3,1.0,0,1,0
29 | 69,6.2,2.2,4.5,1.5,0,1,0
30 | 64,6.1,2.9,4.7,1.4,0,1,0
--------------------------------------------------------------------------------
/FederatedLearningServer/Makefile:
--------------------------------------------------------------------------------
1 | CC = gcc
2 | CFLAGS = -Wall -Wextra
3 | DEBUGFLAGS = -g
4 | SRCDIR = src
5 | INCDIR = lib
6 | BUILDDIR = .build
7 | PROGRAM_NAME = FederatedLearningServer
8 | TARGET = $(PROGRAM_NAME)
9 | LIBS = -lpthread -lwebsockets -lm
10 |
11 | SOURCES := $(wildcard $(SRCDIR)/*.c)
12 | INCLUDES := $(wildcard $(INCDIR)/*.h)
13 | OBJECTS := $(filter-out $(SRCDIR)/main.c, $(SOURCES:$(SRCDIR)/%.c=$(BUILDDIR)/%.o))
14 |
15 | all: clean build run
16 |
17 | alldebug: clean builddebug rundebug
18 |
19 | build: $(TARGET)
20 |
21 | $(TARGET): $(OBJECTS)
22 | $(CC) $(CFLAGS) $^ main.c -o $@ $(LIBS)
23 |
24 | $(BUILDDIR)/%.o: $(SRCDIR)/%.c $(INCLUDES)
25 | $(CC) $(CFLAGS) -I$(INCDIR) -c $< -o $@
26 |
27 | builddebug:
28 | $(CC) $(CFLAGS) $(DEBUGFLAGS) $(SOURCES) main.c -o $(TARGET) $(LIBS)
29 |
30 | clean:
31 | rm -f $(BUILDDIR)/*.o $(TARGET)
32 |
33 | run:
34 | ./$(PROGRAM_NAME)
35 |
36 | rundebug:
37 | gdb ./$(TARGET)
--------------------------------------------------------------------------------
/FederatedLearningFPGA/testbench/tb_alu/tb_ieee754_to_parts.v:
--------------------------------------------------------------------------------
1 | `timescale 1ns / 1ps
2 |
3 | module tb_ieee754_to_parts;
4 |
5 | // Definição dos sinais de entrada e saída
6 | reg [31:0] ieee754;
7 | wire [31:0] integer_part;
8 | wire [31:0] fractional_part;
9 | wire sign;
10 |
11 | // Instancia o módulo que está sendo testado
12 | ieee754_to_parts uut (
13 | .ieee754(ieee754),
14 | .integer_part(integer_part),
15 | .fractional_part(fractional_part),
16 | .sign(sign)
17 | );
18 |
19 | initial begin
20 | // Inicializa a entrada com o valor de teste
21 | ieee754 = 32'b01000000111100000000000000000000; // 6.0 em IEEE 754
22 |
23 | // Aguarda um tempo para o módulo processar
24 | #10;
25 |
26 | // Exibe os resultados no console
27 | $display("IEEE 754: %b", ieee754);
28 | $display("Parte Inteira: %b (%d)", integer_part, integer_part);
29 | $display("Parte Fracionada: %b (%d)", fractional_part,fractional_part);
30 | $display("Sinal: %b", sign);
31 |
32 | // Termina a simulação
33 | $finish;
34 | end
35 |
36 | endmodule
37 |
--------------------------------------------------------------------------------
/FederatedLearningFPGA/NeuralNetworkFPGA_nativelink_simulation.rpt:
--------------------------------------------------------------------------------
1 | Info: Start Nativelink Simulation process
2 |
3 | ========= EDA Simulation Settings =====================
4 |
5 | Sim Mode : Gate
6 | Family : cycloneive
7 | Quartus root : c:/intelfpga_lite/23.1std/quartus/bin64/
8 | Quartus sim root : c:/intelfpga_lite/23.1std/quartus/eda/sim_lib
9 | Simulation Tool : questa intel fpga
10 | Simulation Language : verilog
11 | Simulation Mode : GUI
12 | Sim Output File : NeuralNetworkFPGA.vo
13 | Sim SDF file : NeuralNetworkFPGA__verilog.sdo
14 | Sim dir : simulation\questa
15 |
16 | =======================================================
17 |
18 | Info: Starting NativeLink simulation with Questa Intel FPGA software
19 | Sourced NativeLink script c:/intelfpga_lite/23.1std/quartus/common/tcl/internal/nativelink/modelsim.tcl
20 | Warning: File NeuralNetworkFPGA_run_msim_gate_verilog.do already exists - backing up current file as NeuralNetworkFPGA_run_msim_gate_verilog.do.bak
21 | Info: Spawning Questa Intel FPGA Simulation software
22 | Info: NativeLink simulation flow was successful
23 |
--------------------------------------------------------------------------------
/FederatedLearningESP32/data/dataset1.csv:
--------------------------------------------------------------------------------
1 | 1,5.1,3.5,1.4,0.2,1,0,0
2 | 143,5.8,2.7,5.1,1.9,0,0,1
3 | 2,4.9,3.0,1.4,0.2,1,0,0
4 | 29,5.2,3.4,1.4,0.2,1,0,0
5 | 79,6.0,2.9,4.5,1.5,0,1,0
6 | 15,5.8,4.0,1.2,0.2,1,0,0
7 | 38,4.9,3.1,1.5,0.1,1,0,0
8 | 148,6.5,3.0,5.2,2.0,0,0,1
9 | 42,4.5,2.3,1.3,0.3,1,0,0
10 | 63,6.0,2.2,4.0,1.0,0,1,0
11 | 134,6.3,2.8,5.1,1.5,0,0,1
12 | 32,5.4,3.4,1.5,0.4,1,0,0
13 | 88,6.3,2.3,4.4,1.3,0,1,0
14 | 71,5.9,3.2,4.8,1.8,0,1,0
15 | 106,7.6,3.0,6.6,2.1,0,0,1
16 | 41,5.0,3.5,1.3,0.3,1,0,0
17 | 150,5.9,3.0,5.1,1.8,0,0,1
18 | 17,5.4,3.9,1.3,0.4,1,0,0
19 | 128,6.1,3.0,4.9,1.8,0,0,1
20 | 30,4.7,3.2,1.6,0.2,1,0,0
21 | 110,7.2,3.6,6.1,2.5,0,0,1
22 | 125,6.7,3.3,5.7,2.1,0,0,1
23 | 100,5.7,2.8,4.1,1.3,0,1,0
24 | 117,6.5,3.0,5.5,1.8,0,0,1
25 | 40,5.1,3.4,1.5,0.2,1,0,0
26 | 116,6.4,3.2,5.3,2.3,0,0,1
27 | 28,5.2,3.5,1.5,0.2,1,0,0
28 | 70,5.6,2.5,3.9,1.1,0,1,0
29 | 114,5.7,2.5,5.0,2.0,0,0,1
30 | 91,5.5,2.6,4.4,1.2,0,1,0
31 | 98,6.2,2.9,4.3,1.3,0,1,0
32 | 144,6.8,3.2,5.9,2.3,0,0,1
33 | 66,6.7,3.1,4.4,1.4,0,1,0
34 | 7,4.6,3.4,1.4,0.3,1,0,0
35 | 113,6.8,3.0,5.5,2.1,0,0,1
36 | 59,6.6,2.9,4.6,1.3,0,1,0
37 | 10,4.9,3.1,1.5,0.1,1,0,0
38 | 126,7.2,3.2,6.0,1.8,0,0,1
39 | 56,5.7,2.8,4.5,1.3,0,1,0
40 | 55,6.5,2.8,4.6,1.5,0,1,0
--------------------------------------------------------------------------------
/FederatedLearningESP32/data/dataset2.csv:
--------------------------------------------------------------------------------
1 | 92,6.1,3.0,4.6,1.4,0,1,0
2 | 9,4.4,2.9,1.4,0.2,1,0,0
3 | 35,4.9,3.1,1.5,0.1,1,0,0
4 | 101,6.3,3.3,6.0,2.5,0,0,1
5 | 68,5.8,2.7,4.1,1.0,0,1,0
6 | 49,5.3,3.7,1.5,0.2,1,0,0
7 | 37,5.5,3.5,1.3,0.2,1,0,0
8 | 89,5.6,3.0,4.1,1.3,0,1,0
9 | 44,5.0,3.5,1.6,0.6,1,0,0
10 | 60,5.2,2.7,3.9,1.4,0,1,0
11 | 115,5.8,2.8,5.1,2.4,0,0,1
12 | 23,4.6,3.6,1.0,0.2,1,0,0
13 | 136,7.7,3.0,6.1,2.3,0,0,1
14 | 13,4.8,3.0,1.4,0.1,1,0,0
15 | 45,5.1,3.8,1.9,0.4,1,0,0
16 | 85,5.4,3.0,4.5,1.5,0,1,0
17 | 46,4.8,3.0,1.4,0.3,1,0,0
18 | 94,5.0,2.3,3.3,1.0,0,1,0
19 | 132,7.9,3.8,6.4,2.0,0,0,1
20 | 93,5.8,2.6,4.0,1.2,0,1,0
21 | 74,6.1,2.8,4.7,1.2,0,1,0
22 | 102,5.8,2.7,5.1,1.9,0,0,1
23 | 50,5.0,3.3,1.4,0.2,1,0,0
24 | 33,5.2,4.1,1.5,0.1,1,0,0
25 | 90,5.5,2.5,4.0,1.3,0,1,0
26 | 146,6.7,3.0,5.2,2.3,0,0,1
27 | 3,4.7,3.2,1.3,0.2,1,0,0
28 | 31,4.8,3.1,1.6,0.2,1,0,0
29 | 127,6.2,2.8,4.8,1.8,0,0,1
30 | 12,4.8,3.4,1.6,0.2,1,0,0
31 | 57,6.3,3.3,4.7,1.6,0,1,0
32 | 95,5.6,2.7,4.2,1.3,0,1,0
33 | 53,6.9,3.1,4.9,1.5,0,1,0
34 | 118,7.7,3.8,6.7,2.2,0,0,1
35 | 131,7.4,2.8,6.1,1.9,0,0,1
36 | 104,6.3,2.9,5.6,1.8,0,0,1
37 | 107,4.9,2.5,4.5,1.7,0,0,1
38 | 5,5.0,3.6,1.4,0.2,1,0,0
39 | 130,7.2,3.0,5.8,1.6,0,0,1
40 | 67,5.6,3.0,4.5,1.5,0,1,0
--------------------------------------------------------------------------------
/FederatedLearningESP32/data/dataset3.csv:
--------------------------------------------------------------------------------
1 | 52,6.4,3.2,4.5,1.5,0,1,0
2 | 48,4.6,3.2,1.4,0.2,1,0,0
3 | 73,6.3,2.5,4.9,1.5,0,1,0
4 | 61,5.0,2.0,3.5,1.0,0,1,0
5 | 96,5.7,3.0,4.2,1.2,0,1,0
6 | 112,6.4,2.7,5.3,1.9,0,0,1
7 | 147,6.3,2.5,5.0,1.9,0,0,1
8 | 54,5.5,2.3,4.0,1.3,0,1,0
9 | 26,5.0,3.0,1.6,0.2,1,0,0
10 | 129,6.4,2.8,5.6,2.1,0,0,1
11 | 20,5.1,3.8,1.5,0.3,1,0,0
12 | 120,6.0,2.2,5.0,1.5,0,0,1
13 | 72,6.1,2.8,4.0,1.3,0,1,0
14 | 8,5.0,3.4,1.5,0.2,1,0,0
15 | 87,6.7,3.1,4.7,1.5,0,1,0
16 | 139,6.0,3.0,4.8,1.8,0,0,1
17 | 109,6.7,2.5,5.8,1.8,0,0,1
18 | 51,7.0,3.2,4.7,1.4,0,1,0
19 | 43,4.4,3.2,1.3,0.2,1,0,0
20 | 119,7.7,2.6,6.9,2.3,0,0,1
21 | 83,5.8,2.7,3.9,1.2,0,1,0
22 | 77,6.8,2.8,4.8,1.4,0,1,0
23 | 105,6.5,3.0,5.8,2.2,0,0,1
24 | 39,4.4,3.0,1.3,0.2,1,0,0
25 | 11,5.4,3.7,1.5,0.2,1,0,0
26 | 99,5.1,2.5,3.0,1.1,0,1,0
27 | 138,6.4,3.1,5.5,1.8,0,0,1
28 | 142,6.9,3.1,5.1,2.3,0,0,1
29 | 111,6.5,3.2,5.1,2.0,0,0,1
30 | 22,5.1,3.7,1.5,0.4,1,0,0
31 | 21,5.4,3.4,1.7,0.2,1,0,0
32 | 4,4.6,3.1,1.5,0.2,1,0,0
33 | 24,5.1,3.3,1.7,0.5,1,0,0
34 | 25,4.8,3.4,1.9,0.2,1,0,0
35 | 84,6.0,2.7,5.1,1.6,0,1,0
36 | 6,5.4,3.9,1.7,0.4,1,0,0
37 | 103,7.1,3.0,5.9,2.1,0,0,1
38 | 14,4.3,3.0,1.1,0.1,1,0,0
39 | 122,5.6,2.8,4.9,2.0,0,0,1
40 | 140,6.9,3.1,5.4,2.1,0,0,1
--------------------------------------------------------------------------------
/FederatedLearningFPGA/test_adder.v:
--------------------------------------------------------------------------------
1 | module test_adder;
2 | reg [31:0] A, B;
3 | wire [31:0] result;
4 |
5 | ieee754_adder #(32) adder (
6 | .A(A),
7 | .B(B),
8 | .result(result)
9 | );
10 |
11 | initial begin
12 | $display("=== IEEE754 Adder Test ===");
13 |
14 | // Test 1: 0.5 + 1.0 = 1.5
15 | A = 32'h3f000000; // 0.5
16 | B = 32'h3f800000; // 1.0
17 | #10;
18 | $display("Test 1: %h + %h = %h (Expected: 1.5)", A, B, result);
19 |
20 | // Test 2: 1.5 + 1.0 = 2.5
21 | A = 32'h3fc00000; // 1.5
22 | B = 32'h3f800000; // 1.0
23 | #10;
24 | $display("Test 2: %h + %h = %h (Expected: 2.5)", A, B, result);
25 |
26 | // Test 3: 2.5 + 1.5 = 4.0
27 | A = 32'h40200000; // 2.5
28 | B = 32'h3fc00000; // 1.5
29 | #10;
30 | $display("Test 3: %h + %h = %h (Expected: 4.0)", A, B, result);
31 |
32 | // Test 4: 4.0 + 2.0 = 6.0
33 | A = 32'h40800000; // 4.0
34 | B = 32'h40000000; // 2.0
35 | #10;
36 | $display("Test 4: %h + %h = %h (Expected: 6.0)", A, B, result);
37 |
38 | $finish;
39 | end
40 | endmodule
41 |
--------------------------------------------------------------------------------
/FederatedLearningESP32/components/README:
--------------------------------------------------------------------------------
1 |
2 | This directory is intended for project specific (private) libraries.
3 | PlatformIO will compile them to static libraries and link into executable file.
4 |
5 | The source code of each library should be placed in a an own separate directory
6 | ("lib/your_library_name/[here are source files]").
7 |
8 | For example, see a structure of the following two libraries `Foo` and `Bar`:
9 |
10 | |--lib
11 | | |
12 | | |--Bar
13 | | | |--docs
14 | | | |--examples
15 | | | |--src
16 | | | |- Bar.c
17 | | | |- Bar.h
18 | | | |- library.json (optional, custom build options, etc) https://docs.platformio.org/page/librarymanager/config.html
19 | | |
20 | | |--Foo
21 | | | |- Foo.c
22 | | | |- Foo.h
23 | | |
24 | | |- README --> THIS FILE
25 | |
26 | |- platformio.ini
27 | |--src
28 | |- main.c
29 |
30 | and a contents of `src/main.c`:
31 | ```
32 | #include
33 | #include
34 |
35 | int main (void)
36 | {
37 | ...
38 | }
39 |
40 | ```
41 |
42 | PlatformIO Library Dependency Finder will find automatically dependent
43 | libraries scanning project source files.
44 |
45 | More information about PlatformIO Library Dependency Finder
46 | - https://docs.platformio.org/page/librarymanager/ldf.html
47 |
--------------------------------------------------------------------------------
/FederatedLearningESP32/components/espwebsocketclient/CMakeLists.txt:
--------------------------------------------------------------------------------
1 | # idf_build_get_property(target IDF_TARGET)
2 |
3 | # if(NOT CONFIG_WS_TRANSPORT AND NOT CMAKE_BUILD_EARLY_EXPANSION)
4 | # message(STATUS "Websocket transport is disabled so the esp_websocket_client component will not be built")
5 | # # note: the component is still included in the build so it can become visible again in config
6 | # # without needing to re-run CMake. However no source or header files are built.
7 | # idf_component_register()
8 | # return()
9 | # endif()
10 |
11 | # if(${IDF_TARGET} STREQUAL "linux")
12 | # idf_component_register(SRCS "esp_websocket_client.c"
13 | # REQUIRES esp-tls tcp_transport http_parser esp_event nvs_flash esp_stubs
14 | # PRIV_REQUIRES esp_timer)
15 | # else()
16 | # idf_component_register(SRCS "esp_websocket_client.c"
17 | # REQUIRES lwip esp-tls tcp_transport http_parser
18 | # PRIV_REQUIRES esp_timer esp_event)
19 | # endif()
20 |
21 | set(CMAKE_C_FLAGS "${CMAKE_C_FLAGS} -DDEBUG_FLAG")
22 |
23 |
24 | idf_component_register(
25 | SRCS "esp_websocket_client.c"
26 | INCLUDE_DIRS "."
27 | REQUIRES lwip esp-tls tcp_transport http_parser esp_event
28 | )
--------------------------------------------------------------------------------
/FederatedLearningFPGA/testbench/tb_miscellaneous/tb_memory.v:
--------------------------------------------------------------------------------
1 | `timescale 1ns / 1ps
2 |
3 | module memory_tb;
4 |
5 | parameter WORDS = 16;
6 |
7 | reg clock;
8 | reg reset;
9 | reg write_enable;
10 | reg [31:0] write_data;
11 | reg [$clog2(WORDS)-1:0] address;
12 | wire [31:0] read_data;
13 |
14 | memory_parametrized #(WORDS) uut (
15 | .clock(clock),
16 | .reset(reset),
17 | .write_enable(write_enable),
18 | .write_data(write_data),
19 | .address(address),
20 | .read_data(read_data)
21 | );
22 |
23 | initial begin
24 | clock = 0;
25 | forever #5 clock = ~clock;
26 | end
27 |
28 |
29 | initial begin
30 |
31 | reset = 1;
32 | write_enable = 0;
33 | write_data = 32'b0;
34 | address = 0;
35 |
36 | #10 reset = 0;
37 |
38 | #10 write_enable = 1; address = 3; write_data = 32'hDEADBEEF;
39 | #10 write_enable = 1; address = 5; write_data = 32'hCAFEBABE;
40 |
41 | #10 write_enable = 0; address = 3;
42 | #10 address = 5;
43 |
44 | #20 $finish;
45 | end
46 |
47 | initial begin
48 | $monitor("Time: %0t | Reset: %b | Write_Enable: %b | Address: %0d | Write_Data: %h | Read_Data: %h",
49 | $time, reset, write_enable, address, write_data, read_data);
50 | end
51 |
52 | endmodule
53 |
--------------------------------------------------------------------------------
/FederatedLearningFPGA/ieee745ALU.v.bak:
--------------------------------------------------------------------------------
1 | module ieee754_to_parts (
2 | input [31:0] ieee754, // Entrada: número em IEEE 754
3 | output reg [31:0] integer_part, // Saída: parte inteira em binário
4 | output reg [31:0] fractional_part, // Saída: parte fracionada em binário
5 | output reg sign // Saída: bit de sinal (0 para positivo, 1 para negativo)
6 | );
7 |
8 | always @(*) begin
9 | // Extrair o sinal
10 | sign = ieee754[31];
11 |
12 | // Extrair o expoente
13 | reg [7:0] exponent = ieee754[30:23] - 8'b01111111; // Subtrai o bias (127)
14 |
15 | // Extrair a mantissa (com bit implícito)
16 | reg [23:0] mantissa = {1'b1, ieee754[22:0]}; // Adiciona o bit implícito
17 |
18 | // Calcular a parte inteira e a parte fracionada
19 | integer_part = 0;
20 | fractional_part = 0;
21 |
22 | // Calcular a parte inteira
23 | if (exponent >= 0) begin
24 | integer_part = mantissa << exponent; // Desloca para a esquerda para calcular a parte inteira
25 | end else begin
26 | // Para expoentes negativos, a parte inteira será zero
27 | integer_part = 0;
28 | end
29 |
30 | // Calcular a parte fracionada
31 | fractional_part = mantissa >> (8 - exponent); // Ajusta para obter a parte fracionada
32 | end
33 |
34 | endmodule
35 |
--------------------------------------------------------------------------------
/FederatedLearningServer/src/websockethandlers.c:
--------------------------------------------------------------------------------
1 | #include "../lib/websockethandlers.h"
2 | #include "../lib/federatedlearning.h"
3 | #include "../lib/JSONConverter.h"
4 | #include
5 | #include
6 | #include
7 |
8 | void handle_clint_model_message(const char * message, int length,char *ip_addr){
9 |
10 | char* json_string;
11 | json_string =strndup(message, length);
12 |
13 | if (json_string != NULL) {
14 | cJSON *json_model = cJSON_Parse(json_string);
15 | if (json_model != NULL) {
16 |
17 | FederatedLearning *FederatedLearningInstance= getFederatedLearningInstance();
18 | ClientNode *currentclientnode = FederatedLearningInstance->nodecontrol->firstclientnode;
19 |
20 | while(currentclientnode!=NULL){
21 | if(strcmp(currentclientnode->ip_id,ip_addr)==0){
22 | break;
23 | }
24 | currentclientnode = currentclientnode->nextclientnode;
25 | }
26 |
27 | FederatedLearning *clientmodel = JSONToFederatedLearning(json_model);
28 | if(clientmodel != NULL){
29 | currentclientnode->interaction++;
30 | printf("Aggregating Local Model %s\n",ip_addr);
31 |
32 | AggregationModel(clientmodel);
33 | }
34 | cJSON_Delete(json_model);
35 | }
36 | free(json_string);
37 | }
38 | }
39 |
--------------------------------------------------------------------------------
/FederatedLearningFPGA/NeuralNetworkFPGA.qpf:
--------------------------------------------------------------------------------
1 | # -------------------------------------------------------------------------- #
2 | #
3 | # Copyright (C) 2023 Intel Corporation. All rights reserved.
4 | # Your use of Intel Corporation's design tools, logic functions
5 | # and other software and tools, and any partner logic
6 | # functions, and any output files from any of the foregoing
7 | # (including device programming or simulation files), and any
8 | # associated documentation or information are expressly subject
9 | # to the terms and conditions of the Intel Program License
10 | # Subscription Agreement, the Intel Quartus Prime License Agreement,
11 | # the Intel FPGA IP License Agreement, or other applicable license
12 | # agreement, including, without limitation, that your use is for
13 | # the sole purpose of programming logic devices manufactured by
14 | # Intel and sold by Intel or its authorized distributors. Please
15 | # refer to the applicable agreement for further details, at
16 | # https://fpgasoftware.intel.com/eula.
17 | #
18 | # -------------------------------------------------------------------------- #
19 | #
20 | # Quartus Prime
21 | # Version 23.1std.0 Build 991 11/28/2023 SC Lite Edition
22 | # Date created = 23:24:35 May 18, 2024
23 | #
24 | # -------------------------------------------------------------------------- #
25 |
26 | QUARTUS_VERSION = "23.1"
27 | DATE = "23:24:35 May 18, 2024"
28 |
29 | # Revisions
30 |
31 | PROJECT_REVISION = "NeuralNetworkFPGA"
32 |
--------------------------------------------------------------------------------
/FederatedLearningFPGA/testbench/tb_miscellaneous/tb_register.v:
--------------------------------------------------------------------------------
1 | `timescale 1ns / 1ps
2 |
3 | module register_tb;
4 |
5 | // Sinais do módulo
6 | reg clock;
7 | reg reset;
8 | reg [31:0] data;
9 | wire [31:0] register;
10 |
11 | // Instanciação do módulo
12 | register uut (
13 | .clock(clock),
14 | .reset(reset),
15 | .data(data),
16 | .register(register)
17 | );
18 |
19 | // Geração do clock (período = 10 ns)
20 | initial begin
21 | clock = 0;
22 | forever #5 clock = ~clock; // Inverte o clock a cada 5 ns
23 | end
24 |
25 | // Estímulos de teste
26 | initial begin
27 | // Inicializa sinais
28 | reset = 0;
29 | data = 32'h00000000;
30 |
31 | // Cenário 1: Reset ativo
32 | #10;
33 | reset = 1; // Ativa reset
34 | #10;
35 | reset = 0; // Desativa reset
36 |
37 | // Cenário 2: Carrega dados no registrador
38 | #10;
39 | data = 32'hA5A5A5A5; // Define o dado
40 | #10;
41 | data = 32'h5A5A5A5A;
42 |
43 | // Cenário 3: Verifica comportamento com reset durante operação
44 | #10;
45 | reset = 1; // Ativa reset novamente
46 | #10;
47 | reset = 0; // Desativa reset
48 |
49 | // Finaliza a simulação
50 | #20;
51 | $finish;
52 | end
53 |
54 | // Monitor para acompanhar os sinais
55 | initial begin
56 | $monitor("Time: %0t | Reset: %b | Data: %h | Register: %h", $time, reset, data, register);
57 | end
58 |
59 | endmodule
60 |
--------------------------------------------------------------------------------
/FederatedLearningFPGA/memory_32bit.v:
--------------------------------------------------------------------------------
1 | module memory_32bit #(
2 | parameter MEMORY_DEPTH = 256, // Default 256 words, can be changed
3 | parameter ADDR_WIDTH = $clog2(MEMORY_DEPTH)
4 | )(
5 | input wire clock, // Clock signal
6 | input wire reset, // Reset signal (active high)
7 | input wire write_enable, // Write enable signal
8 | input wire [ADDR_WIDTH-1:0] address, // Memory address
9 | input wire [31:0] write_data, // Data to write (32-bit)
10 | output reg [31:0] read_data // Data read from memory (32-bit)
11 | );
12 |
13 | // Memory array declaration
14 | reg [31:0] memory_array [0:MEMORY_DEPTH-1];
15 |
16 | // Loop variable for initialization
17 | integer i;
18 |
19 | // Memory initialization
20 | initial begin
21 | for (i = 0; i < MEMORY_DEPTH; i = i + 1) begin
22 | memory_array[i] = 32'h00000000; // Initialize all memory locations to 0
23 | end
24 | end
25 |
26 | // Write operation - synchronous
27 | always @(posedge clock) begin
28 | if (reset) begin
29 | // Reset all memory locations to 0
30 | for (i = 0; i < MEMORY_DEPTH; i = i + 1) begin
31 | memory_array[i] <= 32'h00000000;
32 | end
33 | end else if (write_enable) begin
34 | // Write data to specified address
35 | memory_array[address] <= write_data;
36 | end
37 | end
38 |
39 | // Read operation - asynchronous (combinational)
40 | always @(*) begin
41 | read_data = memory_array[address];
42 | end
43 |
44 | endmodule
--------------------------------------------------------------------------------
/FederatedLearningFPGA/testbench/tb_miscellaneous/tb_multiplexer_parametrized.v:
--------------------------------------------------------------------------------
1 | `timescale 1ns/1ps
2 |
3 | module tb_multiplexer_parametrized;
4 |
5 | // Parâmetros
6 | parameter NUM_INPUTS = 4; // Número de entradas
7 | parameter DATA_WIDTH = 32; // Largura de cada entrada
8 |
9 | // Sinais do módulo
10 | reg [NUM_INPUTS*DATA_WIDTH-1:0] in; // Entradas achatadas
11 | reg [$clog2(NUM_INPUTS)-1:0] sel; // Sinal de seleção
12 | wire [DATA_WIDTH-1:0] out; // Saída do MUX
13 |
14 | // Instância do módulo sob teste
15 | multiplexer_parametrized #(
16 | .NUM_INPUTS(NUM_INPUTS),
17 | .DATA_WIDTH(DATA_WIDTH)
18 | ) uut (
19 | .in(in),
20 | .sel(sel),
21 | .out(out)
22 | );
23 |
24 | // Inicialização dos sinais e teste
25 | initial begin
26 | // Inicializa os sinais
27 | in = 0;
28 | sel = 0;
29 |
30 | // Monitoramento dos sinais
31 | $monitor("Time: %0t | sel: %0d | out: %h", $time, sel, out);
32 |
33 | // Atribui valores para as entradas achatadas
34 | in = {32'hAAAA_BBBB, 32'hCCCC_DDDD, 32'hEEEE_FFFF, 32'h1234_5678}; // 4 entradas de 32 bits
35 |
36 | // Testa cada valor de `sel`
37 | #5 sel = 2'b00; // Deve selecionar a primeira entrada (32'hAAAA_BBBB)
38 | #5 sel = 2'b01; // Deve selecionar a segunda entrada (32'hCCCC_DDDD)
39 | #5 sel = 2'b10; // Deve selecionar a terceira entrada (32'hEEEE_FFFF)
40 | #5 sel = 2'b11; // Deve selecionar a quarta entrada (32'h1234_5678)
41 |
42 | // Finaliza a simulação
43 | #5 $finish;
44 | end
45 |
46 | endmodule
47 |
--------------------------------------------------------------------------------
/FederatedLearningServer/main.c:
--------------------------------------------------------------------------------
1 | #include "lib/httpserver.h"
2 | #include "lib/websocketserver.h"
3 | #include "lib/federatedlearning.h"
4 | #include "lib/JSONConverter.h"
5 | #include "lib/cJSON.h"
6 | #include
7 | #include
8 | #include
9 | #include
10 |
11 | struct ThreadArgs {
12 | int port;
13 | // Adicione outros argumentos conforme necessário
14 | };
15 |
16 |
17 | int main() {
18 |
19 | FederatedLearning *FDI = getFederatedLearningInstance();
20 | setFederatedLearningGlobalModel();
21 | //PerformanceMetrics(30,0.5);
22 |
23 | //PrintNeuralNeuralNetwork(FDI->neuralnetwork);
24 |
25 | cJSON *jsondata = FederatedLearningToJSON(FDI);
26 |
27 | //Imprimir o JSON resultante
28 | char* jsonString = cJSON_Print(jsondata);
29 | printf("%s\n", jsonString);
30 |
31 | //Liberar a memória alocada
32 | cJSON_Delete(jsondata);
33 | free(jsonString);
34 |
35 | // Inicializar o servidor HTTP em uma thread
36 | pthread_t http_thread;
37 | struct ThreadArgs threadArgsHTTP = {8888}; // Preencha os argumentos conforme necessário
38 | pthread_create(&http_thread, NULL, start_httpserver, (void *)&threadArgsHTTP);
39 |
40 |
41 | // Inicializar o servidor WebSocket em outra thread
42 | pthread_t websocket_thread;
43 | struct ThreadArgs threadArgsWebSocket = {8080}; // Preencha os argumentos conforme necessário
44 | pthread_create(&websocket_thread, NULL, start_websocketserver, (void *)&threadArgsWebSocket);
45 |
46 |
47 | // Aguardar as threads terminarem (não atingido neste exemplo)
48 | pthread_join(websocket_thread, NULL);
49 | pthread_join(http_thread, NULL);
50 |
51 | return 0;
52 |
53 | }
54 |
--------------------------------------------------------------------------------
/FederatedLearningFPGA/testbench/tb_alu/tb_ieee754_compare.v:
--------------------------------------------------------------------------------
1 | `timescale 1ns/1ps
2 |
3 | module tb_ieee754_compare;
4 |
5 | // Inputs
6 | reg [31:0] A;
7 | reg [31:0] B;
8 |
9 | // Output
10 | wire result;
11 |
12 | // Instância do módulo
13 | ieee754_compare uut (
14 | .A(A),
15 | .B(B),
16 | .result(result)
17 | );
18 |
19 | // Procedimento de teste
20 | initial begin
21 | $display("Início do Testbench");
22 | $monitor("Time: %0t | A: %d | B: %d | Result: %b", $time, A, B, result);
23 |
24 | // Caso 1: A > B (positivos)
25 | A = 32'h40480000; // 3.125 (positiva)
26 | B = 32'h40400000; // 3.0 (positiva)
27 | #10;
28 |
29 | // Caso 2: A < B (positivos)
30 | A = 32'h40400000; // 3.0 (positiva)
31 | B = 32'h40480000; // 3.125 (positiva)
32 | #10;
33 |
34 | // Caso 3: A e B iguais
35 | A = 32'h40480000; // 3.125
36 | B = 32'h40480000; // 3.125
37 | #10;
38 |
39 | // Caso 4: A > B (negativos)
40 | A = 32'hC0400000; // -3.0 (negativa)
41 | B = 32'hC0480000; // -3.125 (negativa)
42 | #10;
43 |
44 | // Caso 5: A < B (negativos)
45 | A = 32'hC0480000; // -3.125 (negativa)
46 | B = 32'hC0400000; // -3.0 (negativa)
47 | #10;
48 |
49 | // Caso 6: Sinais diferentes (A positivo, B negativo)
50 | A = 32'h40400000; // 3.0 (positiva)
51 | B = 32'hC0400000; // -3.0 (negativa)
52 | #10;
53 |
54 | // Caso 7: Sinais diferentes (A negativo, B positivo)
55 | A = 32'hC0400000; // -3.0 (negativa)
56 | B = 32'h40400000; // 3.0 (positiva)
57 | #10;
58 |
59 | // Fim do teste
60 | $display("Fim do Testbench");
61 | $finish;
62 | end
63 |
64 | endmodule
65 |
--------------------------------------------------------------------------------
/FederatedLearningFPGA/testbench/tb_alu/tb_ieee754_multiplier.v:
--------------------------------------------------------------------------------
1 | `timescale 1ns / 1ps
2 |
3 | module tb_ieee754_multiplier;
4 |
5 | reg [31:0] A, B;
6 | wire [31:0] result;
7 |
8 | // Instância do módulo ieee754_multiplier
9 | ieee754_multiplier #(32) uut (
10 | .A(A),
11 | .B(B),
12 | .result(result)
13 | );
14 |
15 | initial begin
16 |
17 | // Testes
18 | $display("Iniciando os testes...");
19 |
20 | // Teste 1: A = 3.2, B = 4.2
21 | A = 32'b01000000010011001100110011001100; // 3.2
22 | B = 32'b01000000100001100110011001100110; // 4.2
23 | #40; // Espera dois ciclos de clock
24 | $display("Teste 1: A = 3.2, B = 4.2, Resultado = %h", result);
25 |
26 | // Teste 2: A = 0.66, B = 0.51
27 | A = 32'b0_01111110_01010001111010111000010; // 0.66
28 | B = 32'b0_01111110_00000101000111101011100; // 0.51
29 | #40;
30 | $display("Teste 2: A = 0.66, B = 0.51, Resultado = %h", result);
31 |
32 | // Teste 3: A = -0.5, B = -6.4
33 | A = 32'b1_01111110_00000000000000000000000; // -0.5
34 | B = 32'b1_10000001_10011001100110011001100; // -6.4
35 | #40;
36 | $display("Teste 3: A = -0.5, B = -6.4, Resultado = %h", result);
37 |
38 | // Teste 4: A = -0.5, B = 6.4
39 | A = 32'b1_01111110_00000000000000000000000; // -0.5
40 | B = 32'b0_10000001_10011001100110011001100; // 6.4
41 | #40;
42 | $display("Teste 4: A = -0.5, B = 6.4, Resultado = %h", result);
43 |
44 | // Teste 5: Valores em hexadecimal
45 | A = 32'h4034b4b5; // 2.8235295
46 | B = 32'hbf70f0f1; // -0.9411765
47 | #40;
48 | $display("Teste 5: A = 2.8235295, B = -0.9411765, Resultado = %h", result);
49 |
50 | $finish;
51 | end
52 | endmodule
53 |
--------------------------------------------------------------------------------
/FederatedLearningESP32/README.md:
--------------------------------------------------------------------------------
1 | | Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-S2 | ESP32-S3 |
2 | | ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- |
3 |
4 | # _Sample project_
5 |
6 | (See the README.md file in the upper level 'examples' directory for more information about examples.)
7 |
8 | This is the simplest buildable example. The example is used by command `idf.py create-project`
9 | that copies the project to user specified path and set it's name. For more information follow the [docs page](https://docs.espressif.com/projects/esp-idf/en/latest/api-guides/build-system.html#start-a-new-project)
10 |
11 |
12 |
13 | ## How to use example
14 | We encourage the users to use the example as a template for the new projects.
15 | A recommended way is to follow the instructions on a [docs page](https://docs.espressif.com/projects/esp-idf/en/latest/api-guides/build-system.html#start-a-new-project).
16 |
17 | ## Example folder contents
18 |
19 | The project **sample_project** contains one source file in C language [main.c](main/main.c). The file is located in folder [main](main).
20 |
21 | ESP-IDF projects are built using CMake. The project build configuration is contained in `CMakeLists.txt`
22 | files that provide set of directives and instructions describing the project's source files and targets
23 | (executable, library, or both).
24 |
25 | Below is short explanation of remaining files in the project folder.
26 |
27 | ```
28 | ├── CMakeLists.txt
29 | ├── main
30 | │ ├── CMakeLists.txt
31 | │ └── main.c
32 | └── README.md This is the file you are currently reading
33 | ```
34 | Additionally, the sample project contains Makefile and component.mk files, used for the legacy Make based build system.
35 | They are not used or needed when building with CMake and idf.py.
36 |
--------------------------------------------------------------------------------
/FederatedLearningFPGA/testbench/tb_alu/tb_ieee754_adder.v:
--------------------------------------------------------------------------------
1 | `timescale 1ns / 1ps
2 |
3 | module tb_ieee754_adder;
4 |
5 | reg [31:0] A, B;
6 | wire [31:0] result;
7 |
8 | // Instância do módulo ieee754_adder
9 | ieee754_adder #(32) uut (
10 | .A(A),
11 | .B(B),
12 | .result(result)
13 | );
14 |
15 | // Clock Generator
16 |
17 |
18 | initial begin
19 |
20 |
21 | // Testes
22 | $display("Iniciando os testes...");
23 |
24 | // Teste 1: A = 3.2, B = 4.2
25 | A = 32'b0_10000000_10011001100110011001100; // 3.2
26 | B = 32'b0_10000001_00001100110011001100110; // 4.2
27 | #40; // Espera dois ciclos de clock
28 | $display("Teste 1: A = 3.2, B = 4.2, Resultado = %h", result);
29 |
30 | // Teste 2: A = 0.66, B = 0.51
31 | A = 32'b0_01111110_01010001111010111000010; // 0.66
32 | B = 32'b0_01111110_00000101000111101011100; // 0.51
33 | #40;
34 | $display("Teste 2: A = 0.66, B = 0.51, Resultado = %h", result);
35 |
36 | // Teste 3: A = -0.5, B = -6.4
37 | A = 32'b1_01111110_00000000000000000000000; // -0.5
38 | B = 32'b1_10000001_10011001100110011001100; // -6.4
39 | #40;
40 | $display("Teste 3: A = -0.5, B = -6.4, Resultado = %h", result);
41 |
42 | // Teste 4: A = -0.5, B = 6.4
43 | A = 32'b1_01111110_00000000000000000000000; // -0.5
44 | B = 32'b0_10000001_10011001100110011001100; // 6.4
45 | #40;
46 | $display("Teste 4: A = -0.5, B = 6.4, Resultado = %h", result);
47 |
48 | // Teste 5: Valores em hexadecimal
49 | A = 32'h4034b4b5; // 2.8235295
50 | B = 32'hbf70f0f1; // -0.9411765
51 | #40;
52 | $display("Teste 5: A = 2.8235295, B = -0.9411765, Resultado = %h",result);
53 |
54 | $finish;
55 | end
56 | endmodule
57 |
--------------------------------------------------------------------------------
/FederatedLearningESP32/components/websocket/websocketclient.c:
--------------------------------------------------------------------------------
1 | #include
2 | #include
3 |
4 | #include "esp_log.h"
5 | #include "esp_event.h"
6 |
7 | #include "esp_websocket_client.h"
8 |
9 | #include "websocketclient.h"
10 | #include "cJSON.h"
11 | #include "JSONConverter.h"
12 | #include "federatedlearning.h"
13 |
14 | static const char *TAG = "WebSocketClient";
15 |
16 |
17 | static void websocket_event_handler(void *handler_args, esp_event_base_t base, int32_t event_id, void *event_data)
18 | {
19 | esp_websocket_event_data_t *data = (esp_websocket_event_data_t *)event_data;
20 | switch (event_id) {
21 | case WEBSOCKET_EVENT_CONNECTED:
22 | ESP_LOGI(TAG, "WEBSOCKET_EVENT_CONNECTED");
23 | break;
24 | case WEBSOCKET_EVENT_DATA:
25 | ESP_LOGW(TAG, "Received=%.*s\n", data->data_len, (char *)data->data_ptr);
26 | break;
27 | }
28 | }
29 |
30 | void websocket_send_local_model(){
31 |
32 | // Define the websocket connection
33 | esp_websocket_client_config_t websocket_cfg = {};
34 | websocket_cfg.uri = WEBSOCKET_SERVER;
35 | ESP_LOGI(TAG, "Connecting to %s ...", websocket_cfg.uri);
36 |
37 | // Connect to Websocket Server
38 | esp_websocket_client_handle_t client = esp_websocket_client_init(&websocket_cfg);
39 | esp_websocket_register_events(client, WEBSOCKET_EVENT_ANY, websocket_event_handler, (void *)client);
40 |
41 |
42 | esp_websocket_client_start(client);
43 |
44 | char *json_string = cJSON_Print(federatedLearningToJSON(getFederatedLearningInstance()));
45 |
46 | if (esp_websocket_client_is_connected(client)) {
47 | esp_websocket_client_send_text(client, json_string, strlen(json_string), portMAX_DELAY);
48 | }
49 | free(json_string);
50 |
51 | // Stop websocket connection
52 | esp_websocket_client_stop(client);
53 | ESP_LOGI(TAG, "Websocket Stopped");
54 | esp_websocket_client_destroy(client);
55 | }
--------------------------------------------------------------------------------
/FederatedLearningESP32/components/federatedlearning/federatedlearning.h:
--------------------------------------------------------------------------------
1 | #ifndef _federatedlearning
2 | #define _federatedlearning
3 |
4 | //activation function
5 | #define PERCEPTRON 1
6 | #define RELU 2
7 | #define SIGMOID 3
8 |
9 | //output activation function
10 | #define SOFTMAX 4
11 |
12 | //loss function
13 | #define MINIMAL_MEAN_SQUARE 1
14 | #define CATEGORICAL_CROSS_ENTROPY 2
15 |
16 | //regularization
17 | #define NONE_REGULARIZATION 0
18 | #define L1 1
19 | #define L2 2
20 |
21 | typedef struct Weight {
22 | float weight;
23 | struct Weight * previousweight, * nextweight;
24 | }Weight;
25 |
26 | typedef struct Neuron {
27 | char neurontype[20];
28 | int weights;
29 | float activationfunctionvalue;
30 | float bias;
31 | struct Weight * firstweight, * lastweight;
32 | struct Neuron * nextneuron, * previousneuron;
33 | }Neuron;
34 |
35 | typedef struct Layer {
36 | int activationfunctiontype;
37 | int neurons;
38 | struct Neuron * firstneuron, * lastneuron;
39 | struct Layer * previouslayer, * nextlayer;
40 | }Layer;
41 |
42 | typedef struct LayerConfig{
43 | struct LayerConfig *first, *next;
44 | int neurons;
45 | int activationfunctiontype;
46 | }LayerConfig;
47 |
48 | typedef struct NeuralNetwork {
49 | int epoch;
50 | float alpha;
51 | int regularization;
52 | float lambda;
53 | int percentualtraining;
54 | int lossfunctiontype;
55 | int layers;
56 | struct Layer * firstlayer, * lastlayer;
57 | }NeuralNetwork;
58 |
59 | typedef struct FederatedLearning{
60 | int globalmodelstatus;
61 | int trainingscounter;
62 | NeuralNetwork *neuralnetwork;
63 | }FederatedLearning;
64 |
65 | FederatedLearning *getFederatedLearningInstance();
66 | void replaceNeuralNetwork(FederatedLearning * newfederatedlearninginstance);
67 | void mergeNeuralNetwork(FederatedLearning * newfederatedlearninginstance);
68 | void PrintNeuralNetwork(NeuralNetwork * neuralnetwork);
69 | //void NeuralNetworkTraining(NeuralNetwork * neuralnetwork, float LearningRate,int epoch,int PercentualTraining);
70 | void NeuralNetworkTraining();
71 | void teste();
72 |
73 | #endif
--------------------------------------------------------------------------------
/DeepLearning/dataset/datasetcsvonehot.c:
--------------------------------------------------------------------------------
1 | #include
2 | #include
3 | #include
4 |
5 | #define MAX_LINE 256
6 | #define NUM_FEATURES 10 // ID + 9 atributos (sem TYPE)
7 | #define NUM_CLASSES 7 // Tipos 1 a 6
8 |
9 | void convert_glass_data_to_csv(const char *input_file, const char *output_file) {
10 | FILE *in = fopen(input_file, "r");
11 | FILE *out = fopen(output_file, "w");
12 |
13 | if (!in || !out) {
14 | printf("❌ Erro ao abrir arquivo.\n");
15 | if (in) fclose(in);
16 | if (out) fclose(out);
17 | return;
18 | }
19 |
20 | char line[MAX_LINE];
21 | while (fgets(line, sizeof(line), in)) {
22 | // Remove o \n no final da linha
23 | line[strcspn(line, "\r\n")] = 0;
24 |
25 | // Ignora linhas vazias
26 | if (strlen(line) == 0)
27 | continue;
28 |
29 | // Quebra a linha pelos delimitadores ","
30 | char *token = strtok(line, ",");
31 | double values[NUM_FEATURES + 1]; // +1 para TYPE
32 | int count = 0;
33 |
34 | while (token && count < NUM_FEATURES + 1) {
35 | values[count++] = atof(token);
36 | token = strtok(NULL, ",");
37 | }
38 |
39 | if (count < NUM_FEATURES + 1)
40 | continue; // pula linha incompleta
41 |
42 | int id = (int)values[0];
43 | int type = (int)values[NUM_FEATURES]; // última coluna é TYPE
44 |
45 | // Escreve as features (sem o campo TYPE original)
46 | fprintf(out, "%d", id);
47 | for (int i = 1; i < NUM_FEATURES; i++)
48 | fprintf(out, ",%.5f", values[i]);
49 |
50 | // Faz o one-hot encoding das classes (1 a 6)
51 | for (int c = 1; c <= NUM_CLASSES; c++)
52 | fprintf(out, ",%d", (c == type) ? 1 : 0);
53 |
54 | fprintf(out, "\n");
55 | }
56 |
57 | fclose(in);
58 | fclose(out);
59 | printf("✅ Conversão concluída!\n");
60 | printf("Arquivo de saída: %s\n", output_file);
61 | }
62 |
63 |
64 |
65 | int main() {
66 | convert_glass_data_to_csv("glass/glass.data", "glass/glass.csv");
67 | return 0;
68 | }
69 |
--------------------------------------------------------------------------------
/CP210X driver/Linux/Linux_2.6.x_VCP_Driver_Source/CP210x_VCP_Linux_2.6.x_Release_Notes.txt:
--------------------------------------------------------------------------------
1 | This bundle contains a modified CP210x driver for the 2.6.38 kernel (Ubuntu 11.04).
2 |
3 | It contains:
4 |
5 | - Fix for CP2104, now sets the baudrate via "SET_BAUDRATE/GET_BAUDRATE" command
6 | - Fix for CP2105, now stores the interface number for the device for multi interface support
7 | - Fix to support GPIO on all parts
8 | - Fix to correct control request for MHS, Line Control and Break support
9 |
10 | NOTE: This driver is an example of how to perform GPIO operations within the CP210x driver since
11 | the driver on kernel.org does not support GPIO at this time. This driver has only been written
12 | and tested on the Linux 2.6.38 kernel on Ubuntu 11.04. This driver is a modified version of the
13 | existing driver in the Linux 2.6.38 kernel, which is maintained at kernel.org. It is recommened
14 | to use the driver there that matches your specific kernel version:
15 |
16 | www.kernel.org
17 |
18 | Build instrutions:
19 |
20 | Ubuntu:
21 | 1. make ( your cp210x driver )
22 | 2. cp cp210x.ko to /lib/modules//kernel/drivers/usb/serial
23 | 3. insmod /lib/modules//kernel/drivers/usb/serial
32 | 6a. insmod /lib/modules//kernel/drivers/usb/serial
23 | 3. insmod /lib/modules//kernel/drivers/usb/serial
32 | 6a. insmod /lib/modules/
2 | #include
3 | #include
4 |
5 | #define MAX_LINES 1000
6 | #define MAX_COLS 100
7 | #define MAX_LINE_LEN 1024
8 |
9 | // Ajuste para o número de colunas de one-hot no seu CSV
10 | #define NUM_CLASSES 3
11 |
12 | int main() {
13 | FILE *in = fopen("wine/datasetevaluation.csv", "r");
14 | FILE *out = fopen("wine/datasetevaluationnormalized.csv", "w");
15 | if (!in || !out) {
16 | printf("Erro ao abrir arquivo.\n");
17 | return 1;
18 | }
19 |
20 | char line[MAX_LINE_LEN];
21 | float data[MAX_LINES][MAX_COLS];
22 | int n_lines = 0;
23 | int n_cols = 0;
24 |
25 | // Leitura do CSV
26 | while (fgets(line, sizeof(line), in)) {
27 | line[strcspn(line, "\r\n")] = 0; // remove newline
28 | char *token = strtok(line, ",");
29 | int col = 0;
30 | while (token != NULL) {
31 | data[n_lines][col++] = atof(token);
32 | token = strtok(NULL, ",");
33 | }
34 | if (n_lines == 0) n_cols = col; // define número de colunas
35 | n_lines++;
36 | if (n_lines >= MAX_LINES) break;
37 | }
38 |
39 | // Normalização min-max entre 0 e 1 (pula primeira coluna e one-hot)
40 | for (int col = 1; col < n_cols - NUM_CLASSES; col++) {
41 | float min = data[0][col];
42 | float max = data[0][col];
43 | for (int row = 0; row < n_lines; row++) {
44 | if (data[row][col] < min) min = data[row][col];
45 | if (data[row][col] > max) max = data[row][col];
46 | }
47 | float range = max - min;
48 | if (range == 0) range = 1; // evita divisão por zero
49 | for (int row = 0; row < n_lines; row++) {
50 | data[row][col] = (data[row][col] - min) / range;
51 | }
52 | }
53 |
54 | // Escrita do CSV normalizado
55 | for (int row = 0; row < n_lines; row++) {
56 | fprintf(out, "%.0f", data[row][0]); // primeira coluna (index) sem normalização
57 | for (int col = 1; col < n_cols; col++) {
58 | fprintf(out, ",%.6f", data[row][col]);
59 | }
60 | fprintf(out, "\n");
61 | }
62 |
63 | fclose(in);
64 | fclose(out);
65 |
66 | printf("Arquivo datasetnormalized.csv gerado com %d linhas e %d colunas.\n", n_lines, n_cols);
67 | return 0;
68 | }
69 |
--------------------------------------------------------------------------------
/DeepLearning/dataset/wine/datasetevaluation.csv:
--------------------------------------------------------------------------------
1 | 15,14.38,1.87,2.38,12,102,3.3,3.64,.29,2.96,7.5,1.2,3,1547,1,0,0
2 | 153,13.11,1.9,2.75,25.5,116,2.2,1.28,.26,1.56,7.1,.61,1.33,425,0,0,1
3 | 1,14.23,1.71,2.43,15.6,127,2.8,3.06,.28,2.29,5.64,1.04,3.92,1065,1,0,0
4 | 167,13.45,3.7,2.6,23,111,1.7,.92,.43,1.46,10.68,.85,1.56,695,0,0,1
5 | 27,13.39,1.77,2.62,16.1,93,2.85,2.94,.34,1.45,4.8,.92,3.22,1195,1,0,0
6 | 52,13.83,1.65,2.6,17.2,94,2.45,2.99,.22,2.29,5.6,1.24,3.37,1265,1,0,0
7 | 132,12.88,2.99,2.4,20,104,1.3,1.22,.24,.83,5.4,.74,1.42,530,0,0,1
8 | 36,13.48,1.81,2.41,20.5,100,2.7,2.98,.26,1.86,5.1,1.04,3.47,920,1,0,0
9 | 47,14.38,3.59,2.28,16,102,3.25,3.17,.27,2.19,4.9,1.04,3.44,1065,1,0,0
10 | 101,12.08,2.08,1.7,17.5,97,2.23,2.17,.26,1.4,3.3,1.27,2.96,710,0,1,0
11 | 60,12.37,.94,1.36,10.6,88,1.98,.57,.28,.42,1.95,1.05,1.82,520,0,1,0
12 | 8,14.06,2.15,2.61,17.6,121,2.6,2.51,.31,1.25,5.05,1.06,3.58,1295,1,0,0
13 | 133,12.81,2.31,2.4,24,98,1.15,1.09,.27,.83,5.7,.66,1.36,560,0,0,1
14 | 152,12.79,2.67,2.48,22,112,1.48,1.36,.24,1.26,10.8,.48,1.47,480,0,0,1
15 | 160,13.48,1.67,2.64,22.5,89,2.6,1.1,.52,2.29,11.75,.57,1.78,620,0,0,1
16 | 129,12.37,1.63,2.3,24.5,88,2.22,2.45,.4,1.9,2.12,.89,2.78,342,0,1,0
17 | 143,13.52,3.17,2.72,23.5,97,1.55,.52,.5,.55,4.35,.89,2.06,520,0,0,1
18 | 34,13.76,1.53,2.7,19.5,132,2.95,2.74,.5,1.35,5.4,1.25,3,1235,1,0,0
19 | 150,13.08,3.9,2.36,21.5,113,1.41,1.39,.34,1.14,9.40,.57,1.33,550,0,0,1
20 | 170,13.4,4.6,2.86,25,112,1.98,.96,.27,1.11,8.5,.67,1.92,630,0,0,1
21 | 29,13.87,1.9,2.8,19.4,107,2.95,2.97,.37,1.76,4.5,1.25,3.4,915,1,0,0
22 | 48,13.9,1.68,2.12,16,101,3.1,3.39,.21,2.14,6.1,.91,3.33,985,1,0,0
23 | 121,11.45,2.4,2.42,20,96,2.9,2.79,.32,1.83,3.25,.8,3.39,625,0,1,0
24 | 64,12.37,1.13,2.16,19,87,3.5,3.1,.19,1.87,4.45,1.22,2.87,420,0,1,0
25 | 106,12.42,2.55,2.27,22,90,1.68,1.84,.66,1.42,2.7,.86,3.3,315,0,1,0
26 | 77,13.03,.9,1.71,16,86,1.95,2.03,.24,1.46,4.6,1.19,2.48,392,0,1,0
27 | 164,12.96,3.45,2.35,18.5,106,1.39,.7,.4,.94,5.28,.68,1.75,675,0,0,1
28 | 104,11.82,1.72,1.88,19.5,86,2.5,1.64,.37,1.42,2.06,.94,2.44,415,0,1,0
29 | 44,13.24,3.98,2.29,17.5,103,2.64,2.63,.32,1.66,4.36,.82,3,680,1,0,0
30 | 171,12.2,3.03,2.32,19,96,1.25,.49,.4,.73,5.5,.66,1.83,510,0,0,1
31 | 94,12.29,2.83,2.22,18,88,2.45,2.25,.25,1.99,2.15,1.15,3.3,290,0,1,0
32 | 50,13.94,1.73,2.27,17.4,108,2.88,3.54,.32,2.08,8.90,1.12,3.1,1260,1,0,0
33 | 79,12.33,.99,1.95,14.8,136,1.9,1.85,.35,2.76,3.4,1.06,2.31,750,0,1,0
34 | 68,12.37,1.17,1.92,19.6,78,2.11,2,.27,1.04,4.68,1.12,3.48,510,0,1,0
35 | 151,13.5,3.12,2.62,24,123,1.4,1.57,.22,1.25,8.60,.59,1.3,500,0,0,1
36 |
--------------------------------------------------------------------------------
/FederatedLearningFPGA/db/NeuralNetworkFPGA.npp.qmsg:
--------------------------------------------------------------------------------
1 | { "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1734066845017 ""}
2 | { "Info" "IQEXE_START_BANNER_PRODUCT" "Netlist Viewers Preprocess Quartus Prime " "Running Quartus Prime Netlist Viewers Preprocess" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 23.1std.1 Build 993 05/14/2024 SC Lite Edition " "Version 23.1std.1 Build 993 05/14/2024 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1734066845017 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Dec 13 02:14:04 2024 " "Processing started: Fri Dec 13 02:14:04 2024" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1734066845017 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Netlist Viewers Preprocess" 0 -1 1734066845017 ""}
3 | { "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_npp NeuralNetworkFPGA -c NeuralNetworkFPGA --netlist_type=sgate " "Command: quartus_npp NeuralNetworkFPGA -c NeuralNetworkFPGA --netlist_type=sgate" { } { } 0 0 "Command: %1!s!" 0 0 "Netlist Viewers Preprocess" 0 -1 1734066845017 ""}
4 | { "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Netlist Viewers Preprocess" 0 -1 1734066845270 ""}
5 | { "Info" "IQEXE_ERROR_COUNT" "Netlist Viewers Preprocess 0 s 1 Quartus Prime " "Quartus Prime Netlist Viewers Preprocess was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4606 " "Peak virtual memory: 4606 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1734066848336 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Dec 13 02:14:08 2024 " "Processing ended: Fri Dec 13 02:14:08 2024" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1734066848336 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Elapsed time: 00:00:04" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1734066848336 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Total CPU time (on all processors): 00:00:03" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1734066848336 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Netlist Viewers Preprocess" 0 -1 1734066848336 ""}
6 |
--------------------------------------------------------------------------------
/CP210X driver/Linux/Linux_2.6.x_VCP_Driver_Source/cp210x_gpio_example.c:
--------------------------------------------------------------------------------
1 | #include
2 | #include
3 | #include
4 | #include
5 |
6 | using namespace std;
7 |
8 | #define TTY_DEVICE "/dev/ttyUSB0"
9 |
10 | #define IOCTL_GPIOGET 0x8000
11 | #define IOCTL_GPIOSET 0x8001
12 |
13 | int main()
14 | {
15 | int fd;
16 | int result = 0;
17 |
18 | cout << "CP210x GPIO Example\n";
19 | fd = open(TTY_DEVICE, O_RDWR | O_NOCTTY | O_NDELAY);
20 | if (fd == -1)
21 | {
22 | cout << "Error opening port " << TTY_DEVICE << endl;
23 | return -1;
24 | }
25 |
26 | unsigned long gpio;
27 |
28 | // Display the original GPIO value
29 | result = ioctl(fd, IOCTL_GPIOGET, &gpio);
30 | cout << "Original GPIO = " << hex << gpio << ", result = " << result << endl;
31 |
32 | // Now set GPIO, value defined as bit 0-15, mask, and bit 16-31, value:
33 | //
34 | // Bit 0 = GPIO0 Mask
35 | // Bit 1 = GPIO1 Mask
36 | // Bit 2 = GPIO2 Mask
37 | // Bit 3 = GPIO3 Mask
38 | // Bit 4 = GPIO4 Mask
39 | // Bit 5 = GPIO5 Mask
40 | // Bit 6 = GPIO6 Mask
41 | // Bit 7 = GPIO7 Mask
42 | // Bit 8 = GPIO8 Mask
43 | // Bit 9 = GPIO9 Mask
44 | // Bit 10 = GPIO10 Mask
45 | // Bit 11 = GPIO11 Mask
46 | // Bit 12 = GPIO12 Mask
47 | // Bit 13 = GPIO13 Mask
48 | // Bit 14 = GPIO14 Mask
49 | // Bit 15 = GPIO15 Mask
50 | // Bit 16 = GPIO0 Value
51 | // Bit 17 = GPIO1 Value
52 | // Bit 18 = GPIO2 Value
53 | // Bit 19 = GPIO3 Value
54 | // Bit 20 = GPIO4 Value
55 | // Bit 21 = GPIO5 Value
56 | // Bit 22 = GPIO6 Value
57 | // Bit 23 = GPIO7 Value
58 | // Bit 24 = GPIO8 Value
59 | // Bit 25 = GPIO9 Value
60 | // Bit 26 = GPIO10 Value
61 | // Bit 27 = GPIO11 Value
62 | // Bit 28 = GPIO12 Value
63 | // Bit 29 = GPIO13 Value
64 | // Bit 30 = GPIO14 Value
65 | // Bit 31 = GPIO15 Value
66 | //
67 | // Note: Each device supports a different number of GPIO -
68 | // check the data sheet for exact GPIO values available.
69 | //
70 | // GPIO on CP2105 is exclusive to the COM port interface,
71 | // while on CP2108 all GPIO is accessible to any interface
72 |
73 | // Flip the GPIO state:
74 | // Reverse the bits, then shift left 8 bits
75 | // to declare the new values, then or in FF
76 | // to set the mask to write all values
77 | gpio = ~gpio;
78 | //gpio = gpio << 8;
79 | //gpio |= 0x00FF;
80 | gpio = gpio << 16;
81 | gpio |= 0xFFFF;
82 | result = ioctl(fd, IOCTL_GPIOSET, &gpio);
83 | cout << "GPIO to set = " << hex << gpio << ", result = " << result << endl;
84 |
85 | // Now check the new GPIO value
86 | result = ioctl(fd, IOCTL_GPIOGET, &gpio);
87 | cout << "New GPIO = " << hex << gpio << ", result = " << result << endl;
88 |
89 | close(fd);
90 |
91 | return 0;
92 | }
93 |
--------------------------------------------------------------------------------
/DeepLearning/dataset/datasetspliter.c:
--------------------------------------------------------------------------------
1 | #include
2 | #include
3 | #include
4 | #include
5 |
6 | #define MAX_LINES 1000 // máximo de linhas esperadas no CSV
7 | #define MAX_LINE_LEN 512 // tamanho máximo de cada linha
8 |
9 | // Função para embaralhar as linhas
10 | void shuffle_lines(char *lines[], int count) {
11 | srand((unsigned int)time(NULL));
12 | for (int i = count - 1; i > 0; i--) {
13 | int j = rand() % (i + 1);
14 | char *temp = lines[i];
15 | lines[i] = lines[j];
16 | lines[j] = temp;
17 | }
18 | }
19 |
20 | void split_csv_dataset(const char *input_file,
21 | const char *train_file,
22 | const char *eval_file,
23 | double eval_ratio) {
24 | FILE *in = fopen(input_file, "r");
25 | if (!in) {
26 | printf("❌ Erro ao abrir %s\n", input_file);
27 | return;
28 | }
29 |
30 | char *lines[MAX_LINES];
31 | int count = 0;
32 | char buffer[MAX_LINE_LEN];
33 |
34 | // Lê todas as linhas do arquivo CSV
35 | while (fgets(buffer, sizeof(buffer), in)) {
36 | buffer[strcspn(buffer, "\r\n")] = 0; // remove \n
37 | if (strlen(buffer) == 0)
38 | continue;
39 | lines[count] = strdup(buffer);
40 | count++;
41 | if (count >= MAX_LINES) break;
42 | }
43 | fclose(in);
44 |
45 | if (count == 0) {
46 | printf("⚠️ Nenhuma linha encontrada.\n");
47 | return;
48 | }
49 |
50 | // Embaralha as linhas
51 | shuffle_lines(lines, count);
52 |
53 | // Calcula tamanhos
54 | int eval_size = (int)(count * eval_ratio);
55 | int train_size = count - eval_size;
56 |
57 | FILE *train = fopen(train_file, "w");
58 | FILE *eval = fopen(eval_file, "w");
59 |
60 | if (!train || !eval) {
61 | printf("❌ Erro ao criar arquivos de saída.\n");
62 | if (train) fclose(train);
63 | if (eval) fclose(eval);
64 | return;
65 | }
66 |
67 | // Escreve as linhas embaralhadas
68 | for (int i = 0; i < count; i++) {
69 | FILE *target = (i < train_size) ? train : eval;
70 | fprintf(target, "%s\n", lines[i]);
71 | free(lines[i]);
72 | }
73 |
74 | fclose(train);
75 | fclose(eval);
76 |
77 | printf("✅ Dataset dividido com sucesso!\n");
78 | printf(" - %s: %d linhas (treino)\n", train_file, train_size);
79 | printf(" - %s: %d linhas (avaliação)\n", eval_file, eval_size);
80 | }
81 |
82 | int main() {
83 | split_csv_dataset("wine/wine.csv",
84 | "wine/datasettraining.csv",
85 | "wine/datasetevaluation.csv",
86 | 0.20); // 20% para avaliação
87 | return 0;
88 | }
89 |
--------------------------------------------------------------------------------
/FederatedLearningServer/lib/federatedlearning.h:
--------------------------------------------------------------------------------
1 | #ifndef FEDERATEDLEARNING_H
2 | #define FEDERATEDLEARNING_H
3 |
4 | #include "../lib/cJSON.h"
5 | #include
6 |
7 | //activation function
8 | #define PERCEPTRON 1
9 | #define RELU 2
10 | #define SIGMOID 3
11 |
12 | //output activation function
13 | #define SOFTMAX 4
14 |
15 | //loss function
16 | #define MINIMAL_MEAN_SQUARE 1
17 | #define CATEGORICAL_CROSS_ENTROPY 2
18 |
19 | //regularization
20 | #define NONE_REGULARIZATION 0
21 | #define L1 1
22 | #define L2 2
23 |
24 | //weight value
25 | #define WEIGHT_VALUE_ZERO 0
26 | #define WEIGHT_VALUE_RANDOM 1
27 | #define WEIGHT_VALUE_HALF 2
28 |
29 | //////////
30 |
31 | typedef struct Weight {
32 | float weight;
33 | struct Weight * previousweight, * nextweight;
34 | }Weight;
35 |
36 | typedef struct Neuron {
37 | char neurontype[20];
38 | int weights;
39 | float activationfunctionvalue;
40 | float bias;
41 | struct Weight * firstweight, * lastweight;
42 | struct Neuron * nextneuron, * previousneuron;
43 | }Neuron;
44 |
45 | typedef struct Layer {
46 | int activationfunctiontype;
47 | int neurons;
48 | struct Neuron * firstneuron, * lastneuron;
49 | struct Layer * previouslayer, * nextlayer;
50 | }Layer;
51 |
52 | typedef struct NeuralNetwork {
53 | int epoch;
54 | float alpha;
55 | int regularization;
56 | float lambda;
57 | int percentualtraining;
58 | int lossfunctiontype;
59 | int layers;
60 | struct Layer * firstlayer, * lastlayer;
61 | }NeuralNetwork;
62 |
63 | //////////
64 |
65 | typedef struct ClientNode{
66 | char ip_id[15];
67 | int interaction;
68 | struct ClientNode *previousclientnode, *nextclientnode;
69 | }ClientNode;
70 |
71 | typedef struct NodeControl{
72 | int currentinteraction;
73 | int interactioncycle;
74 | int clientnodes;
75 | int clientnodesregistered;
76 | NeuralNetwork *neuralnetwork;
77 | struct ClientNode *firstclientnode, *lastclientnode;
78 | }NodeControl;
79 |
80 | //////////
81 |
82 | typedef struct FederatedLearning{
83 | int globalmodelstatus;
84 | int trainingscounter;
85 | NeuralNetwork *neuralnetwork;
86 | NodeControl *nodecontrol;
87 | }FederatedLearning;
88 |
89 | //////////
90 |
91 | typedef struct LayerConfig{
92 | struct LayerConfig *first, *next;
93 | int neurons;
94 | int activationfunctiontype;
95 | }LayerConfig;
96 |
97 | //Methods
98 | FederatedLearning *getFederatedLearningInstance();
99 | void PrintNeuralNeuralNetwork(NeuralNetwork * neuralnetwork);
100 | void setFederatedLearningGlobalModel();
101 | void AggregationModel(FederatedLearning * clientmodel);
102 | void PerformanceMetrics(NeuralNetwork * neuralnetwork,int PercentualEvaluation,float Threshold);
103 | #endif
104 |
--------------------------------------------------------------------------------
/FederatedLearningFPGA/miscellaneous.v:
--------------------------------------------------------------------------------
1 | module multiplexer_parametrized #(
2 | parameter NUM_INPUTS = 4,
3 | parameter DATA_WIDTH = 32
4 | )(
5 | input [NUM_INPUTS*DATA_WIDTH-1:0] in,
6 | input [$clog2(NUM_INPUTS)-1:0] sel,
7 | output reg [DATA_WIDTH-1:0] out
8 | );
9 |
10 | always @(*) begin
11 | out = in[sel*DATA_WIDTH +: DATA_WIDTH];
12 | end
13 |
14 | endmodule
15 |
16 | module register(
17 | input clock,
18 | input reset,
19 | input [31:0] data,
20 | output reg [31:0] register
21 | );
22 |
23 | always @(posedge clock) begin
24 | if (reset) begin
25 | register <= 32'b0;
26 | end else begin
27 | register <= data;
28 | end
29 | end
30 |
31 | endmodule
32 |
33 | module memory_parametrized #(
34 | parameter WORDS = 256
35 | )(
36 | input clock,
37 | input reset,
38 | input write_enable,
39 | input [31:0] write_data,
40 | input [$clog2(WORDS)-1:0] address,
41 | output reg [31:0] read_data
42 | );
43 |
44 | reg [31:0] mem [0:WORDS-1];
45 |
46 | integer i;
47 |
48 | initial begin
49 | for (i = 0; i < WORDS; i = i + 1) begin
50 | mem[i] <= 32'h3f000000;
51 | end
52 | end
53 |
54 | always @(posedge clock) begin
55 | if (reset) begin
56 | for (i = 0; i < WORDS; i = i + 1) begin
57 | mem[i] <= 32'b0;
58 | end
59 | end else if (write_enable) begin
60 | mem[address] <= write_data;
61 | end
62 | end
63 |
64 | always @(address) begin
65 | if (!write_enable) begin
66 | read_data <= mem[address];
67 | end
68 | end
69 |
70 | endmodule
71 |
72 |
73 | module bin_to_7seg (
74 | input [3:0] binary,
75 | output reg [6:0] seg
76 | );
77 |
78 | always @(*) begin
79 | case (binary)
80 | 4'b0000: seg = 7'b1000000; // 0
81 | 4'b0001: seg = 7'b1111001; // 1
82 | 4'b0010: seg = 7'b0100100; // 2
83 | 4'b0011: seg = 7'b0110000; // 3
84 | 4'b0100: seg = 7'b0011001; // 4
85 | 4'b0101: seg = 7'b0010010; // 5
86 | 4'b0110: seg = 7'b0000010; // 6
87 | 4'b0111: seg = 7'b1111000; // 7
88 | 4'b1000: seg = 7'b0000000; // 8
89 | 4'b1001: seg = 7'b0010000; // 9
90 | 4'b1010: seg = 7'b0001000; // A
91 | 4'b1011: seg = 7'b0000011; // b
92 | 4'b1100: seg = 7'b1000110; // C
93 | 4'b1101: seg = 7'b0100001; // d
94 | 4'b1110: seg = 7'b0000110; // E
95 | 4'b1111: seg = 7'b0001110; // F
96 | default: seg = 7'b1111111; // clean display
97 | endcase
98 | end
99 |
100 | endmodule
--------------------------------------------------------------------------------
/DeepLearning/dataset/winetocsv.c:
--------------------------------------------------------------------------------
1 | #include
2 | #include
3 | #include
4 | #include
5 |
6 | #define MAX_LINE_LEN 1024
7 | #define EXPECTED_TOKENS 14 // 1 classe + 13 features
8 |
9 | /* remove espaços no início/fim */
10 | char *trim_inplace(char *s) {
11 | char *end;
12 | while (*s && isspace((unsigned char)*s)) s++;
13 | if (*s == 0) return s;
14 | end = s + strlen(s) - 1;
15 | while (end > s && isspace((unsigned char)*end)) end--;
16 | end[1] = '\0';
17 | return s;
18 | }
19 |
20 | int main(void) {
21 | FILE *in = fopen("wine/wine.data", "r");
22 | FILE *out = fopen("wine/wine.csv", "w");
23 | if (!in || !out) {
24 | fprintf(stderr, "Erro ao abrir arquivo(s).\n");
25 | if (in) fclose(in);
26 | if (out) fclose(out);
27 | return 1;
28 | }
29 |
30 | char line[MAX_LINE_LEN];
31 | int total = 0;
32 | int skipped = 0;
33 |
34 | // Cabeçalho
35 | fprintf(out, "index,");
36 | for (int i = 1; i <= 13; ++i) {
37 | fprintf(out, "feature%d,", i);
38 | }
39 | fprintf(out, "class1,class2,class3\n");
40 |
41 | while (fgets(line, sizeof(line), in)) {
42 | // Remove quebra de linha
43 | line[strcspn(line, "\r\n")] = '\0';
44 |
45 | // Ignora linhas vazias
46 | char *p = line;
47 | while (*p && isspace((unsigned char)*p)) p++;
48 | if (*p == '\0') continue;
49 |
50 | // Tokeniza por vírgula
51 | char *tokens[20];
52 | int nt = 0;
53 | char *tok = strtok(line, ",");
54 | while (tok && nt < 20) {
55 | tokens[nt++] = trim_inplace(tok);
56 | tok = strtok(NULL, ",");
57 | }
58 |
59 | // Verifica se tem número esperado de colunas
60 | if (nt < EXPECTED_TOKENS) {
61 | fprintf(stderr, "Linha ignorada (colunas=%d < %d): \"%s\"\n", nt, EXPECTED_TOKENS, p);
62 | skipped++;
63 | continue;
64 | }
65 |
66 | // Classe
67 | int classe = atoi(tokens[0]);
68 | if (classe < 1 || classe > 3) {
69 | fprintf(stderr, "Linha ignorada (classe inválida=%d): \"%s\"\n", classe, p);
70 | skipped++;
71 | continue;
72 | }
73 |
74 | // Índice começa em 1
75 | fprintf(out, "%d,", total + 1);
76 |
77 | // Features (tokens[1..13])
78 | fprintf(out, "%s", tokens[1]);
79 | for (int i = 2; i <= 13; ++i) {
80 | fprintf(out, ",%s", tokens[i]);
81 | }
82 |
83 | // One-hot
84 | if (classe == 1) fprintf(out, ",1,0,0\n");
85 | else if (classe == 2) fprintf(out, ",0,1,0\n");
86 | else fprintf(out, ",0,0,1\n");
87 |
88 | total++;
89 | }
90 |
91 | fclose(in);
92 | fclose(out);
93 |
94 | printf("Concluído: %d linhas processadas, %d ignoradas.\n", total, skipped);
95 | printf("Arquivo gerado: wine.csv\n");
96 | return 0;
97 | }
98 |
--------------------------------------------------------------------------------
/FederatedLearningFPGA/db/NeuralNetworkFPGA.asm.qmsg:
--------------------------------------------------------------------------------
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8 |
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/FederatedLearningFPGA/db/NeuralNetworkFPGA.eda.qmsg:
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2 | { "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus Prime " "Running Quartus Prime EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 23.1std.1 Build 993 05/14/2024 SC Lite Edition " "Version 23.1std.1 Build 993 05/14/2024 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1734066811857 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Dec 13 02:13:31 2024 " "Processing started: Fri Dec 13 02:13:31 2024" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1734066811857 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1734066811857 ""}
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7 |
--------------------------------------------------------------------------------
/FederatedLearningFPGA/testbench/tb_miscellaneous/tb_memory_32bit.v:
--------------------------------------------------------------------------------
1 | `timescale 1ns / 1ps
2 |
3 | module tb_memory_32bit;
4 |
5 | // Test parameters
6 | parameter MEMORY_DEPTH = 16; // Small memory for testing
7 | parameter ADDR_WIDTH = $clog2(MEMORY_DEPTH);
8 |
9 | // Test signals
10 | reg clock;
11 | reg reset;
12 | reg write_enable;
13 | reg [ADDR_WIDTH-1:0] address;
14 | reg [31:0] write_data;
15 | wire [31:0] read_data;
16 |
17 | // Instantiate the memory module
18 | memory_32bit #(
19 | .MEMORY_DEPTH(MEMORY_DEPTH)
20 | ) uut (
21 | .clock(clock),
22 | .reset(reset),
23 | .write_enable(write_enable),
24 | .address(address),
25 | .write_data(write_data),
26 | .read_data(read_data)
27 | );
28 |
29 | // Clock generation
30 | initial begin
31 | clock = 0;
32 | forever #5 clock = ~clock; // 100MHz clock (10ns period)
33 | end
34 |
35 | // Test stimulus
36 | initial begin
37 | // Initialize signals
38 | reset = 1;
39 | write_enable = 0;
40 | address = 0;
41 | write_data = 32'h00000000;
42 |
43 | // Test 1: Reset functionality
44 | #20;
45 | reset = 0;
46 | #10;
47 |
48 | // Test 2: Write operations
49 | write_enable = 1;
50 | address = 0; write_data = 32'hAABBCCDD;
51 | #10;
52 | address = 1; write_data = 32'h11223344;
53 | #10;
54 | address = 2; write_data = 32'hDEADBEEF;
55 | #10;
56 | address = 3; write_data = 32'hCAFEBABE;
57 | #10;
58 |
59 | // Test 3: Read operations
60 | write_enable = 0;
61 | address = 0;
62 | #10;
63 | address = 1;
64 | #10;
65 | address = 2;
66 | #10;
67 | address = 3;
68 | #10;
69 |
70 | // Test 4: Write to different addresses
71 | write_enable = 1;
72 | address = 15; write_data = 32'hFEDCBA98;
73 | #10;
74 | address = 8; write_data = 32'h87654321;
75 | #10;
76 |
77 | // Test 5: Read from newly written addresses
78 | write_enable = 0;
79 | address = 15;
80 | #10;
81 | address = 8;
82 | #10;
83 |
84 | // Test 6: Reset during operation
85 | reset = 1;
86 | #10;
87 | reset = 0;
88 | #10;
89 |
90 | // Test 7: Read after reset (should be all zeros)
91 | address = 0;
92 | #10;
93 | address = 1;
94 | #10;
95 | address = 15;
96 | #10;
97 |
98 | // End simulation
99 | #20 $finish;
100 | end
101 |
102 | // Monitor and display results
103 | initial begin
104 | $monitor("Time: %0t | Reset: %b | Write_Enable: %b | Address: %0d | Write_Data: %h | Read_Data: %h",
105 | $time, reset, write_enable, address, write_data, read_data);
106 | end
107 |
108 | // Additional verification
109 | initial begin
110 | $display("=== 32-bit Memory Testbench Started ===");
111 | $display("Memory Depth: %0d words", MEMORY_DEPTH);
112 | $display("Address Width: %0d bits", ADDR_WIDTH);
113 | $display("=====================================");
114 | end
115 |
116 | endmodule
--------------------------------------------------------------------------------
/DeepLearning/dataset/wine/wine.names:
--------------------------------------------------------------------------------
1 | 1. Title of Database: Wine recognition data
2 | Updated Sept 21, 1998 by C.Blake : Added attribute information
3 |
4 | 2. Sources:
5 | (a) Forina, M. et al, PARVUS - An Extendible Package for Data
6 | Exploration, Classification and Correlation. Institute of Pharmaceutical
7 | and Food Analysis and Technologies, Via Brigata Salerno,
8 | 16147 Genoa, Italy.
9 |
10 | (b) Stefan Aeberhard, email: stefan@coral.cs.jcu.edu.au
11 | (c) July 1991
12 | 3. Past Usage:
13 |
14 | (1)
15 | S. Aeberhard, D. Coomans and O. de Vel,
16 | Comparison of Classifiers in High Dimensional Settings,
17 | Tech. Rep. no. 92-02, (1992), Dept. of Computer Science and Dept. of
18 | Mathematics and Statistics, James Cook University of North Queensland.
19 | (Also submitted to Technometrics).
20 |
21 | The data was used with many others for comparing various
22 | classifiers. The classes are separable, though only RDA
23 | has achieved 100% correct classification.
24 | (RDA : 100%, QDA 99.4%, LDA 98.9%, 1NN 96.1% (z-transformed data))
25 | (All results using the leave-one-out technique)
26 |
27 | In a classification context, this is a well posed problem
28 | with "well behaved" class structures. A good data set
29 | for first testing of a new classifier, but not very
30 | challenging.
31 |
32 | (2)
33 | S. Aeberhard, D. Coomans and O. de Vel,
34 | "THE CLASSIFICATION PERFORMANCE OF RDA"
35 | Tech. Rep. no. 92-01, (1992), Dept. of Computer Science and Dept. of
36 | Mathematics and Statistics, James Cook University of North Queensland.
37 | (Also submitted to Journal of Chemometrics).
38 |
39 | Here, the data was used to illustrate the superior performance of
40 | the use of a new appreciation function with RDA.
41 |
42 | 4. Relevant Information:
43 |
44 | -- These data are the results of a chemical analysis of
45 | wines grown in the same region in Italy but derived from three
46 | different cultivars.
47 | The analysis determined the quantities of 13 constituents
48 | found in each of the three types of wines.
49 |
50 | -- I think that the initial data set had around 30 variables, but
51 | for some reason I only have the 13 dimensional version.
52 | I had a list of what the 30 or so variables were, but a.)
53 | I lost it, and b.), I would not know which 13 variables
54 | are included in the set.
55 |
56 | -- The attributes are (dontated by Riccardo Leardi,
57 | riclea@anchem.unige.it )
58 | 1) Alcohol
59 | 2) Malic acid
60 | 3) Ash
61 | 4) Alcalinity of ash
62 | 5) Magnesium
63 | 6) Total phenols
64 | 7) Flavanoids
65 | 8) Nonflavanoid phenols
66 | 9) Proanthocyanins
67 | 10)Color intensity
68 | 11)Hue
69 | 12)OD280/OD315 of diluted wines
70 | 13)Proline
71 |
72 | 5. Number of Instances
73 |
74 | class 1 59
75 | class 2 71
76 | class 3 48
77 |
78 | 6. Number of Attributes
79 |
80 | 13
81 |
82 | 7. For Each Attribute:
83 |
84 | All attributes are continuous
85 |
86 | No statistics available, but suggest to standardise
87 | variables for certain uses (e.g. for us with classifiers
88 | which are NOT scale invariant)
89 |
90 | NOTE: 1st attribute is class identifier (1-3)
91 |
92 | 8. Missing Attribute Values:
93 |
94 | None
95 |
96 | 9. Class Distribution: number of instances per class
97 |
98 | class 1 59
99 | class 2 71
100 | class 3 48
101 |
--------------------------------------------------------------------------------
/FederatedLearningFPGA/testbench/tb_neuron/tb_relu.v:
--------------------------------------------------------------------------------
1 | `timescale 1ns/1ns
2 |
3 | module tb_relu;
4 |
5 | reg [31:0] Z;
6 | wire [31:0] a;
7 |
8 | // Instantiate the ReLU module
9 | relu uut (
10 | .Z(Z),
11 | .a(a)
12 | );
13 |
14 | // Test cases
15 | initial begin
16 | $display("=== ReLU Activation Function Testbench ===");
17 | $display("Time | Input (Z) | Output (a) | Expected | Status");
18 | $display("-----|-----------|------------|----------|--------");
19 |
20 | // Test 1: Positive number
21 | #10 Z = 32'h40400000; // 3.0
22 | #5 $display("%4t | %h | %h | %h | %s", $time, Z, a, 32'h40400000,
23 | (a == 32'h40400000) ? "PASS" : "FAIL");
24 |
25 | // Test 2: Negative number
26 | #10 Z = 32'hC0400000; // -3.0
27 | #5 $display("%4t | %h | %h | %h | %s", $time, Z, a, 32'h00000000,
28 | (a == 32'h00000000) ? "PASS" : "FAIL");
29 |
30 | // Test 3: Zero
31 | #10 Z = 32'h00000000; // 0.0
32 | #5 $display("%4t | %h | %h | %h | %s", $time, Z, a, 32'h00000000,
33 | (a == 32'h00000000) ? "PASS" : "FAIL");
34 |
35 | // Test 4: Small positive number
36 | #10 Z = 32'h3F800000; // 1.0
37 | #5 $display("%4t | %h | %h | %h | %s", $time, Z, a, 32'h3F800000,
38 | (a == 32'h3F800000) ? "PASS" : "FAIL");
39 |
40 | // Test 5: Small negative number
41 | #10 Z = 32'hBF800000; // -1.0
42 | #5 $display("%4t | %h | %h | %h | %s", $time, Z, a, 32'h00000000,
43 | (a == 32'h00000000) ? "PASS" : "FAIL");
44 |
45 | // Test 6: Large positive number
46 | #10 Z = 32'h41200000; // 10.0
47 | #5 $display("%4t | %h | %h | %h | %s", $time, Z, a, 32'h41200000,
48 | (a == 32'h41200000) ? "PASS" : "FAIL");
49 |
50 | // Test 7: Large negative number
51 | #10 Z = 32'hC1200000; // -10.0
52 | #5 $display("%4t | %h | %h | %h | %s", $time, Z, a, 32'h00000000,
53 | (a == 32'h00000000) ? "PASS" : "FAIL");
54 |
55 | // Test 8: Very small positive number
56 | #10 Z = 32'h3A83126F; // 0.001
57 | #5 $display("%4t | %h | %h | %h | %s", $time, Z, a, 32'h3A83126F,
58 | (a == 32'h3A83126F) ? "PASS" : "FAIL");
59 |
60 | // Test 9: Very small negative number
61 | #10 Z = 32'hBA83126F; // -0.001
62 | #5 $display("%4t | %h | %h | %h | %s", $time, Z, a, 32'h00000000,
63 | (a == 32'h00000000) ? "PASS" : "FAIL");
64 |
65 | // Test 10: Positive infinity
66 | #10 Z = 32'h7F800000; // +inf
67 | #5 $display("%4t | %h | %h | %h | %s", $time, Z, a, 32'h7F800000,
68 | (a == 32'h7F800000) ? "PASS" : "FAIL");
69 |
70 | // Test 11: Negative infinity
71 | #10 Z = 32'hFF800000; // -inf
72 | #5 $display("%4t | %h | %h | %h | %s", $time, Z, a, 32'h00000000,
73 | (a == 32'h00000000) ? "PASS" : "FAIL");
74 |
75 | // Test 12: NaN
76 | #10 Z = 32'h7FFFFFFF; // NaN
77 | #5 $display("%4t | %h | %h | %h | %s", $time, Z, a, 32'h7FFFFFFF,
78 | (a == 32'h7FFFFFFF) ? "PASS" : "FAIL");
79 |
80 | $display("=== ReLU Test Complete ===");
81 | $finish;
82 | end
83 |
84 | // Monitor changes
85 | initial begin
86 | $monitor("Time: %t | Z: %h | a: %h", $time, Z, a);
87 | end
88 |
89 | endmodule
--------------------------------------------------------------------------------
/FederatedLearningESP32/data/dataset.csv:
--------------------------------------------------------------------------------
1 | 1,5.1,3.5,1.4,0.2,1,0,0
2 | 143,5.8,2.7,5.1,1.9,0,0,1
3 | 2,4.9,3.0,1.4,0.2,1,0,0
4 | 29,5.2,3.4,1.4,0.2,1,0,0
5 | 79,6.0,2.9,4.5,1.5,0,1,0
6 | 15,5.8,4.0,1.2,0.2,1,0,0
7 | 38,4.9,3.1,1.5,0.1,1,0,0
8 | 148,6.5,3.0,5.2,2.0,0,0,1
9 | 42,4.5,2.3,1.3,0.3,1,0,0
10 | 63,6.0,2.2,4.0,1.0,0,1,0
11 | 134,6.3,2.8,5.1,1.5,0,0,1
12 | 32,5.4,3.4,1.5,0.4,1,0,0
13 | 88,6.3,2.3,4.4,1.3,0,1,0
14 | 71,5.9,3.2,4.8,1.8,0,1,0
15 | 106,7.6,3.0,6.6,2.1,0,0,1
16 | 41,5.0,3.5,1.3,0.3,1,0,0
17 | 150,5.9,3.0,5.1,1.8,0,0,1
18 | 17,5.4,3.9,1.3,0.4,1,0,0
19 | 128,6.1,3.0,4.9,1.8,0,0,1
20 | 30,4.7,3.2,1.6,0.2,1,0,0
21 | 110,7.2,3.6,6.1,2.5,0,0,1
22 | 125,6.7,3.3,5.7,2.1,0,0,1
23 | 100,5.7,2.8,4.1,1.3,0,1,0
24 | 117,6.5,3.0,5.5,1.8,0,0,1
25 | 40,5.1,3.4,1.5,0.2,1,0,0
26 | 116,6.4,3.2,5.3,2.3,0,0,1
27 | 28,5.2,3.5,1.5,0.2,1,0,0
28 | 70,5.6,2.5,3.9,1.1,0,1,0
29 | 114,5.7,2.5,5.0,2.0,0,0,1
30 | 91,5.5,2.6,4.4,1.2,0,1,0
31 | 98,6.2,2.9,4.3,1.3,0,1,0
32 | 144,6.8,3.2,5.9,2.3,0,0,1
33 | 66,6.7,3.1,4.4,1.4,0,1,0
34 | 7,4.6,3.4,1.4,0.3,1,0,0
35 | 113,6.8,3.0,5.5,2.1,0,0,1
36 | 59,6.6,2.9,4.6,1.3,0,1,0
37 | 10,4.9,3.1,1.5,0.1,1,0,0
38 | 126,7.2,3.2,6.0,1.8,0,0,1
39 | 56,5.7,2.8,4.5,1.3,0,1,0
40 | 55,6.5,2.8,4.6,1.5,0,1,0
41 | 92,6.1,3.0,4.6,1.4,0,1,0
42 | 9,4.4,2.9,1.4,0.2,1,0,0
43 | 35,4.9,3.1,1.5,0.1,1,0,0
44 | 101,6.3,3.3,6.0,2.5,0,0,1
45 | 68,5.8,2.7,4.1,1.0,0,1,0
46 | 49,5.3,3.7,1.5,0.2,1,0,0
47 | 37,5.5,3.5,1.3,0.2,1,0,0
48 | 89,5.6,3.0,4.1,1.3,0,1,0
49 | 44,5.0,3.5,1.6,0.6,1,0,0
50 | 60,5.2,2.7,3.9,1.4,0,1,0
51 | 115,5.8,2.8,5.1,2.4,0,0,1
52 | 23,4.6,3.6,1.0,0.2,1,0,0
53 | 136,7.7,3.0,6.1,2.3,0,0,1
54 | 13,4.8,3.0,1.4,0.1,1,0,0
55 | 45,5.1,3.8,1.9,0.4,1,0,0
56 | 85,5.4,3.0,4.5,1.5,0,1,0
57 | 46,4.8,3.0,1.4,0.3,1,0,0
58 | 94,5.0,2.3,3.3,1.0,0,1,0
59 | 132,7.9,3.8,6.4,2.0,0,0,1
60 | 93,5.8,2.6,4.0,1.2,0,1,0
61 | 74,6.1,2.8,4.7,1.2,0,1,0
62 | 102,5.8,2.7,5.1,1.9,0,0,1
63 | 50,5.0,3.3,1.4,0.2,1,0,0
64 | 33,5.2,4.1,1.5,0.1,1,0,0
65 | 90,5.5,2.5,4.0,1.3,0,1,0
66 | 146,6.7,3.0,5.2,2.3,0,0,1
67 | 3,4.7,3.2,1.3,0.2,1,0,0
68 | 31,4.8,3.1,1.6,0.2,1,0,0
69 | 127,6.2,2.8,4.8,1.8,0,0,1
70 | 12,4.8,3.4,1.6,0.2,1,0,0
71 | 57,6.3,3.3,4.7,1.6,0,1,0
72 | 95,5.6,2.7,4.2,1.3,0,1,0
73 | 53,6.9,3.1,4.9,1.5,0,1,0
74 | 118,7.7,3.8,6.7,2.2,0,0,1
75 | 131,7.4,2.8,6.1,1.9,0,0,1
76 | 104,6.3,2.9,5.6,1.8,0,0,1
77 | 107,4.9,2.5,4.5,1.7,0,0,1
78 | 5,5.0,3.6,1.4,0.2,1,0,0
79 | 130,7.2,3.0,5.8,1.6,0,0,1
80 | 67,5.6,3.0,4.5,1.5,0,1,0
81 | 52,6.4,3.2,4.5,1.5,0,1,0
82 | 48,4.6,3.2,1.4,0.2,1,0,0
83 | 73,6.3,2.5,4.9,1.5,0,1,0
84 | 61,5.0,2.0,3.5,1.0,0,1,0
85 | 96,5.7,3.0,4.2,1.2,0,1,0
86 | 112,6.4,2.7,5.3,1.9,0,0,1
87 | 147,6.3,2.5,5.0,1.9,0,0,1
88 | 54,5.5,2.3,4.0,1.3,0,1,0
89 | 26,5.0,3.0,1.6,0.2,1,0,0
90 | 129,6.4,2.8,5.6,2.1,0,0,1
91 | 20,5.1,3.8,1.5,0.3,1,0,0
92 | 120,6.0,2.2,5.0,1.5,0,0,1
93 | 72,6.1,2.8,4.0,1.3,0,1,0
94 | 8,5.0,3.4,1.5,0.2,1,0,0
95 | 87,6.7,3.1,4.7,1.5,0,1,0
96 | 139,6.0,3.0,4.8,1.8,0,0,1
97 | 109,6.7,2.5,5.8,1.8,0,0,1
98 | 51,7.0,3.2,4.7,1.4,0,1,0
99 | 43,4.4,3.2,1.3,0.2,1,0,0
100 | 119,7.7,2.6,6.9,2.3,0,0,1
101 | 83,5.8,2.7,3.9,1.2,0,1,0
102 | 77,6.8,2.8,4.8,1.4,0,1,0
103 | 105,6.5,3.0,5.8,2.2,0,0,1
104 | 39,4.4,3.0,1.3,0.2,1,0,0
105 | 11,5.4,3.7,1.5,0.2,1,0,0
106 | 99,5.1,2.5,3.0,1.1,0,1,0
107 | 138,6.4,3.1,5.5,1.8,0,0,1
108 | 142,6.9,3.1,5.1,2.3,0,0,1
109 | 111,6.5,3.2,5.1,2.0,0,0,1
110 | 22,5.1,3.7,1.5,0.4,1,0,0
111 | 21,5.4,3.4,1.7,0.2,1,0,0
112 | 4,4.6,3.1,1.5,0.2,1,0,0
113 | 24,5.1,3.3,1.7,0.5,1,0,0
114 | 25,4.8,3.4,1.9,0.2,1,0,0
115 | 84,6.0,2.7,5.1,1.6,0,1,0
116 | 6,5.4,3.9,1.7,0.4,1,0,0
117 | 103,7.1,3.0,5.9,2.1,0,0,1
118 | 14,4.3,3.0,1.1,0.1,1,0,0
119 | 122,5.6,2.8,4.9,2.0,0,0,1
120 | 140,6.9,3.1,5.4,2.1,0,0,1
--------------------------------------------------------------------------------
/DeepLearning/dataset/iris/datasettraining.csv:
--------------------------------------------------------------------------------
1 | 1,5.1,3.5,1.4,0.2,1,0,0
2 | 143,5.8,2.7,5.1,1.9,0,0,1
3 | 2,4.9,3.0,1.4,0.2,1,0,0
4 | 29,5.2,3.4,1.4,0.2,1,0,0
5 | 79,6.0,2.9,4.5,1.5,0,1,0
6 | 15,5.8,4.0,1.2,0.2,1,0,0
7 | 38,4.9,3.1,1.5,0.1,1,0,0
8 | 148,6.5,3.0,5.2,2.0,0,0,1
9 | 42,4.5,2.3,1.3,0.3,1,0,0
10 | 63,6.0,2.2,4.0,1.0,0,1,0
11 | 134,6.3,2.8,5.1,1.5,0,0,1
12 | 32,5.4,3.4,1.5,0.4,1,0,0
13 | 88,6.3,2.3,4.4,1.3,0,1,0
14 | 71,5.9,3.2,4.8,1.8,0,1,0
15 | 106,7.6,3.0,6.6,2.1,0,0,1
16 | 41,5.0,3.5,1.3,0.3,1,0,0
17 | 150,5.9,3.0,5.1,1.8,0,0,1
18 | 17,5.4,3.9,1.3,0.4,1,0,0
19 | 128,6.1,3.0,4.9,1.8,0,0,1
20 | 30,4.7,3.2,1.6,0.2,1,0,0
21 | 110,7.2,3.6,6.1,2.5,0,0,1
22 | 125,6.7,3.3,5.7,2.1,0,0,1
23 | 100,5.7,2.8,4.1,1.3,0,1,0
24 | 117,6.5,3.0,5.5,1.8,0,0,1
25 | 40,5.1,3.4,1.5,0.2,1,0,0
26 | 116,6.4,3.2,5.3,2.3,0,0,1
27 | 28,5.2,3.5,1.5,0.2,1,0,0
28 | 70,5.6,2.5,3.9,1.1,0,1,0
29 | 114,5.7,2.5,5.0,2.0,0,0,1
30 | 91,5.5,2.6,4.4,1.2,0,1,0
31 | 98,6.2,2.9,4.3,1.3,0,1,0
32 | 144,6.8,3.2,5.9,2.3,0,0,1
33 | 66,6.7,3.1,4.4,1.4,0,1,0
34 | 7,4.6,3.4,1.4,0.3,1,0,0
35 | 113,6.8,3.0,5.5,2.1,0,0,1
36 | 59,6.6,2.9,4.6,1.3,0,1,0
37 | 10,4.9,3.1,1.5,0.1,1,0,0
38 | 126,7.2,3.2,6.0,1.8,0,0,1
39 | 56,5.7,2.8,4.5,1.3,0,1,0
40 | 55,6.5,2.8,4.6,1.5,0,1,0
41 | 92,6.1,3.0,4.6,1.4,0,1,0
42 | 9,4.4,2.9,1.4,0.2,1,0,0
43 | 35,4.9,3.1,1.5,0.1,1,0,0
44 | 101,6.3,3.3,6.0,2.5,0,0,1
45 | 68,5.8,2.7,4.1,1.0,0,1,0
46 | 49,5.3,3.7,1.5,0.2,1,0,0
47 | 37,5.5,3.5,1.3,0.2,1,0,0
48 | 89,5.6,3.0,4.1,1.3,0,1,0
49 | 44,5.0,3.5,1.6,0.6,1,0,0
50 | 60,5.2,2.7,3.9,1.4,0,1,0
51 | 115,5.8,2.8,5.1,2.4,0,0,1
52 | 23,4.6,3.6,1.0,0.2,1,0,0
53 | 136,7.7,3.0,6.1,2.3,0,0,1
54 | 13,4.8,3.0,1.4,0.1,1,0,0
55 | 45,5.1,3.8,1.9,0.4,1,0,0
56 | 85,5.4,3.0,4.5,1.5,0,1,0
57 | 46,4.8,3.0,1.4,0.3,1,0,0
58 | 94,5.0,2.3,3.3,1.0,0,1,0
59 | 132,7.9,3.8,6.4,2.0,0,0,1
60 | 93,5.8,2.6,4.0,1.2,0,1,0
61 | 74,6.1,2.8,4.7,1.2,0,1,0
62 | 102,5.8,2.7,5.1,1.9,0,0,1
63 | 50,5.0,3.3,1.4,0.2,1,0,0
64 | 33,5.2,4.1,1.5,0.1,1,0,0
65 | 90,5.5,2.5,4.0,1.3,0,1,0
66 | 146,6.7,3.0,5.2,2.3,0,0,1
67 | 3,4.7,3.2,1.3,0.2,1,0,0
68 | 31,4.8,3.1,1.6,0.2,1,0,0
69 | 127,6.2,2.8,4.8,1.8,0,0,1
70 | 12,4.8,3.4,1.6,0.2,1,0,0
71 | 57,6.3,3.3,4.7,1.6,0,1,0
72 | 95,5.6,2.7,4.2,1.3,0,1,0
73 | 53,6.9,3.1,4.9,1.5,0,1,0
74 | 118,7.7,3.8,6.7,2.2,0,0,1
75 | 131,7.4,2.8,6.1,1.9,0,0,1
76 | 104,6.3,2.9,5.6,1.8,0,0,1
77 | 107,4.9,2.5,4.5,1.7,0,0,1
78 | 5,5.0,3.6,1.4,0.2,1,0,0
79 | 130,7.2,3.0,5.8,1.6,0,0,1
80 | 67,5.6,3.0,4.5,1.5,0,1,0
81 | 52,6.4,3.2,4.5,1.5,0,1,0
82 | 48,4.6,3.2,1.4,0.2,1,0,0
83 | 73,6.3,2.5,4.9,1.5,0,1,0
84 | 61,5.0,2.0,3.5,1.0,0,1,0
85 | 96,5.7,3.0,4.2,1.2,0,1,0
86 | 112,6.4,2.7,5.3,1.9,0,0,1
87 | 147,6.3,2.5,5.0,1.9,0,0,1
88 | 54,5.5,2.3,4.0,1.3,0,1,0
89 | 26,5.0,3.0,1.6,0.2,1,0,0
90 | 129,6.4,2.8,5.6,2.1,0,0,1
91 | 20,5.1,3.8,1.5,0.3,1,0,0
92 | 120,6.0,2.2,5.0,1.5,0,0,1
93 | 72,6.1,2.8,4.0,1.3,0,1,0
94 | 8,5.0,3.4,1.5,0.2,1,0,0
95 | 87,6.7,3.1,4.7,1.5,0,1,0
96 | 139,6.0,3.0,4.8,1.8,0,0,1
97 | 109,6.7,2.5,5.8,1.8,0,0,1
98 | 51,7.0,3.2,4.7,1.4,0,1,0
99 | 43,4.4,3.2,1.3,0.2,1,0,0
100 | 119,7.7,2.6,6.9,2.3,0,0,1
101 | 83,5.8,2.7,3.9,1.2,0,1,0
102 | 77,6.8,2.8,4.8,1.4,0,1,0
103 | 105,6.5,3.0,5.8,2.2,0,0,1
104 | 39,4.4,3.0,1.3,0.2,1,0,0
105 | 11,5.4,3.7,1.5,0.2,1,0,0
106 | 99,5.1,2.5,3.0,1.1,0,1,0
107 | 138,6.4,3.1,5.5,1.8,0,0,1
108 | 142,6.9,3.1,5.1,2.3,0,0,1
109 | 111,6.5,3.2,5.1,2.0,0,0,1
110 | 22,5.1,3.7,1.5,0.4,1,0,0
111 | 21,5.4,3.4,1.7,0.2,1,0,0
112 | 4,4.6,3.1,1.5,0.2,1,0,0
113 | 24,5.1,3.3,1.7,0.5,1,0,0
114 | 25,4.8,3.4,1.9,0.2,1,0,0
115 | 84,6.0,2.7,5.1,1.6,0,1,0
116 | 6,5.4,3.9,1.7,0.4,1,0,0
117 | 103,7.1,3.0,5.9,2.1,0,0,1
118 | 14,4.3,3.0,1.1,0.1,1,0,0
119 | 122,5.6,2.8,4.9,2.0,0,0,1
120 | 140,6.9,3.1,5.4,2.1,0,0,1
--------------------------------------------------------------------------------
/FederatedLearningESP32/main/main.c:
--------------------------------------------------------------------------------
1 | #include
2 |
3 | #include "freertos/FreeRTOS.h"
4 | #include "freertos/task.h"
5 | #include "freertos/timers.h"
6 | #include "freertos/event_groups.h"
7 |
8 | #include "espconfiguration.h"
9 | #include "httpclient.h"
10 | #include "websocketclient.h"
11 | #include "federatedlearning.h"
12 | #include "JSONConverter.h"
13 | #include "esp_spiffs.h"
14 |
15 |
16 | #include "driver/i2c.h"
17 | #include "esp_system.h"
18 |
19 |
20 | // Defina o endereço I2C do INA219 (geralmente é 0x40)
21 | #define INA219_ADDR 0x40
22 |
23 | // Pinos I2C
24 | #define SDA_PIN 21
25 | #define SCL_PIN 22
26 |
27 | void brink_error_led(int blink){
28 |
29 | for(int i=0;ineuralnetwork);
95 | NeuralNetworkTraining();
96 | //FederatedLearning *FDI = getFederatedLearningInstance();
97 | //PrintNeuralNetwork(FDI->neuralnetwork);
98 | }
99 | }
100 |
101 |
102 | void start_esp32_configuration(){
103 |
104 | UARTConfiguration();
105 | GPIOConfiguration();
106 | WIFIConfiguration();
107 | SPIFFSConfiguration();
108 |
109 | gpio_set_level(LED_PIN_ERROR, 0);
110 | gpio_set_level(LED_PIN_SYNC, 0);
111 | vTaskDelay(2000 / portTICK_PERIOD_MS);
112 |
113 | }
114 |
115 | void start_federated_learning_system_button(){
116 | int startled = 0;
117 | while (gpio_get_level(BUTTON_PIN)){
118 | startled = ~startled;
119 | gpio_set_level(LED_PIN_WORKING, startled);
120 | vTaskDelay(250 / portTICK_PERIOD_MS);
121 | }
122 | gpio_set_level(LED_PIN_WORKING, 1);
123 | }
124 |
125 | void app_main(void){
126 | start_esp32_configuration();
127 | start_federated_learning_system_button();
128 | node_register();
129 | deep_learning();
130 | }
131 |
--------------------------------------------------------------------------------
/DeepLearning/dataset/glass/glass.names:
--------------------------------------------------------------------------------
1 | 1. Title: Glass Identification Database
2 |
3 | 2. Sources:
4 | (a) Creator: B. German
5 | -- Central Research Establishment
6 | Home Office Forensic Science Service
7 | Aldermaston, Reading, Berkshire RG7 4PN
8 | (b) Donor: Vina Spiehler, Ph.D., DABFT
9 | Diagnostic Products Corporation
10 | (213) 776-0180 (ext 3014)
11 | (c) Date: September, 1987
12 |
13 | 3. Past Usage:
14 | -- Rule Induction in Forensic Science
15 | -- Ian W. Evett and Ernest J. Spiehler
16 | -- Central Research Establishment
17 | Home Office Forensic Science Service
18 | Aldermaston, Reading, Berkshire RG7 4PN
19 | -- Unknown technical note number (sorry, not listed here)
20 | -- General Results: nearest neighbor held its own with respect to the
21 | rule-based system
22 |
23 | 4. Relevant Information:n
24 | Vina conducted a comparison test of her rule-based system, BEAGLE, the
25 | nearest-neighbor algorithm, and discriminant analysis. BEAGLE is
26 | a product available through VRS Consulting, Inc.; 4676 Admiralty Way,
27 | Suite 206; Marina Del Ray, CA 90292 (213) 827-7890 and FAX: -3189.
28 | In determining whether the glass was a type of "float" glass or not,
29 | the following results were obtained (# incorrect answers):
30 |
31 | Type of Sample Beagle NN DA
32 | Windows that were float processed (87) 10 12 21
33 | Windows that were not: (76) 19 16 22
34 |
35 | The study of classification of types of glass was motivated by
36 | criminological investigation. At the scene of the crime, the glass left
37 | can be used as evidence...if it is correctly identified!
38 |
39 | 5. Number of Instances: 214
40 |
41 | 6. Number of Attributes: 10 (including an Id#) plus the class attribute
42 | -- all attributes are continuously valued
43 |
44 | 7. Attribute Information:
45 | 1. Id number: 1 to 214
46 | 2. RI: refractive index
47 | 3. Na: Sodium (unit measurement: weight percent in corresponding oxide, as
48 | are attributes 4-10)
49 | 4. Mg: Magnesium
50 | 5. Al: Aluminum
51 | 6. Si: Silicon
52 | 7. K: Potassium
53 | 8. Ca: Calcium
54 | 9. Ba: Barium
55 | 10. Fe: Iron
56 | 11. Type of glass: (class attribute)
57 | -- 1 building_windows_float_processed
58 | -- 2 building_windows_non_float_processed
59 | -- 3 vehicle_windows_float_processed
60 | -- 4 vehicle_windows_non_float_processed (none in this database)
61 | -- 5 containers
62 | -- 6 tableware
63 | -- 7 headlamps
64 |
65 | 8. Missing Attribute Values: None
66 |
67 | Summary Statistics:
68 | Attribute: Min Max Mean SD Correlation with class
69 | 2. RI: 1.5112 1.5339 1.5184 0.0030 -0.1642
70 | 3. Na: 10.73 17.38 13.4079 0.8166 0.5030
71 | 4. Mg: 0 4.49 2.6845 1.4424 -0.7447
72 | 5. Al: 0.29 3.5 1.4449 0.4993 0.5988
73 | 6. Si: 69.81 75.41 72.6509 0.7745 0.1515
74 | 7. K: 0 6.21 0.4971 0.6522 -0.0100
75 | 8. Ca: 5.43 16.19 8.9570 1.4232 0.0007
76 | 9. Ba: 0 3.15 0.1750 0.4972 0.5751
77 | 10. Fe: 0 0.51 0.0570 0.0974 -0.1879
78 |
79 | 9. Class Distribution: (out of 214 total instances)
80 | -- 163 Window glass (building windows and vehicle windows)
81 | -- 87 float processed
82 | -- 70 building windows
83 | -- 17 vehicle windows
84 | -- 76 non-float processed
85 | -- 76 building windows
86 | -- 0 vehicle windows
87 | -- 51 Non-window glass
88 | -- 13 containers
89 | -- 9 tableware
90 | -- 29 headlamps
91 |
92 |
93 |
94 |
95 |
--------------------------------------------------------------------------------
/FederatedLearningServer/src/httpserver.c:
--------------------------------------------------------------------------------
1 | #include "../lib/httpserver.h"
2 | #include "../lib/httphandlers.h"
3 | #include "../lib/cJSON.h"
4 |
5 | #include
6 | #include
7 | #include
8 | #include
9 | #include
10 |
11 | #define BUFFER_SIZE 4096
12 |
13 | struct ThreadArgs {
14 | int port;
15 | };
16 |
17 |
18 | void handle_request(int client_socket,struct sockaddr_in client_address) {
19 |
20 | char buffer[BUFFER_SIZE] = {0};
21 | read(client_socket, buffer, BUFFER_SIZE - 1);
22 | //printf("Request received:\n%s\n", buffer);
23 | //Extracting the bory from the request.
24 | char *body_start = strstr(buffer, "\r\n\r\n");
25 | const char *request_body = (body_start != NULL) ? body_start + 4 : "";
26 |
27 | char client_ip[INET_ADDRSTRLEN];
28 | inet_ntop(AF_INET, &(client_address.sin_addr), client_ip, INET_ADDRSTRLEN);
29 |
30 | //Processing the request. Redirecting to the endpoints handlers.
31 | if (strstr(buffer, "GET /api/checkglobalmodel HTTP/1.1") != NULL){
32 | handle_get_checkmodelstatus(client_socket,client_ip);
33 | }
34 | else if(strstr(buffer, "GET /api/noderegister HTTP/1.1") != NULL){
35 |
36 | handle_get_noderegister(client_socket,client_ip);
37 | }
38 | else if (strstr(buffer, "GET /api/getglobalmodel HTTP/1.1") != NULL){
39 | handle_get_globalmodel(client_socket);
40 | }
41 | else if (strstr(buffer, "POST /api/postglobalmodel HTTP/1.1") != NULL){
42 |
43 | handle_post_globalmodel(client_socket, request_body);
44 | }
45 | else if (strstr(buffer, "POST /api/testpost") != NULL) {
46 | handle_testpost_request(client_socket, request_body);
47 | }
48 | else if (strstr(buffer, "GET /api/testget HTTP/1.1") != NULL){
49 | handle_testget_request(client_socket);
50 | }
51 | else if (strstr(buffer, "GET / HTTP/1.1") != NULL){
52 | handle_root_request(client_socket);
53 | }
54 | else {
55 | handle_not_found_request(client_socket);
56 | }
57 |
58 | close(client_socket);
59 | }
60 |
61 | void *start_httpserver(void *args) {
62 | struct ThreadArgs *threadArgs = (struct ThreadArgs *)args;
63 | int server_socket, client_socket;
64 | struct sockaddr_in server_addr, client_addr;
65 | socklen_t addr_size = sizeof(client_addr);
66 |
67 | //Creating the socket
68 | if ((server_socket = socket(AF_INET, SOCK_STREAM, 0)) == -1) {
69 | perror("Error to run the socket");
70 | exit(EXIT_FAILURE);
71 | }
72 |
73 | //Setting the serve address
74 | server_addr.sin_family = AF_INET;
75 | server_addr.sin_addr.s_addr = inet_addr(IP_ADDRESS);
76 |
77 | server_addr.sin_port = htons((int)threadArgs->port);
78 |
79 | //Associating the socket to the server address
80 | if (bind(server_socket, (struct sockaddr*)&server_addr, sizeof(server_addr)) == -1) {
81 | perror("Error to associate the socket to the server address");
82 | exit(EXIT_FAILURE);
83 | }
84 |
85 | //Set the socket in listening mode
86 | if (listen(server_socket, 10) == -1) {
87 | perror("Error to set the socket in listening mode");
88 | exit(EXIT_FAILURE);
89 | }
90 |
91 | printf("HTTP Server running in http://%s:%d/\n", IP_ADDRESS,(int)threadArgs->port);
92 |
93 | while (1) {
94 | // Waiting for some conection
95 | if ((client_socket = accept(server_socket, (struct sockaddr*)&client_addr, &addr_size)) == -1) {
96 | perror("Erro ao aceitar a conexão");
97 | continue;
98 | }
99 |
100 | // Handles the customer's request
101 | handle_request(client_socket,client_addr);
102 | }
103 |
104 | // Close the server socket
105 | close(server_socket);
106 | }
107 |
--------------------------------------------------------------------------------
/FederatedLearningFPGA/testbench/tb_alu/tb_ieee754_divider.v:
--------------------------------------------------------------------------------
1 | `timescale 1ns/1ns
2 |
3 | module tb_ieee754_divider;
4 |
5 | // Definição de parâmetros
6 | parameter ITER = 3; // Parâmetro para número de iterações
7 | parameter USE_ENABLE = 0; // Parâmetro para uso do enable
8 |
9 | // Sinais de entrada e saída
10 | reg clock;
11 | reg [31:0] A, B;
12 | wire [31:0] result;
13 |
14 | // Instância do módulo com múltiplos parâmetros
15 | ieee754_divider #(
16 | .ITER(ITER), // Passa o parâmetro ITER
17 | .USE_ENABLE(USE_ENABLE) // Passa o parâmetro USE_ENABLE
18 | ) uut (
19 | .clock(clock),
20 | .A(A),
21 | .B(B),
22 | .result(result)
23 | );
24 |
25 | always #10 clock = ~clock;
26 |
27 | initial begin
28 |
29 | clock = 0;
30 |
31 | // Test 1: 8.0 / 1.0
32 | A = 32'h40400000; // 8.0
33 | B = 32'h3f800000; // 1.0
34 | #120;
35 | $display("Test 1 | Time: %t | A: %h | B: %h | Result: %h",$time, A, B, result);
36 |
37 | // Test 2: 8.0 / 2.0
38 | A = 32'h40400000; // 8.0
39 | B = 32'h40000000; // 2.0
40 | #120;
41 | $display("Test 2 | Time: %t | A: %h | B: %h | Result: %h",$time, A, B, result);
42 |
43 | // Test 3: 8.0 / 4.0
44 | A = 32'h40400000; // 8.0
45 | B = 32'h40800000; // 4.0
46 | #120;
47 | $display("Test 3 | Time: %t | A: %h | B: %h | Result: %h",$time, A, B, result);
48 |
49 | // Test 4: 3.0 / 2.0
50 | A = 32'h40400000; // 3.0
51 | B = 32'h40000000; // 2.0
52 | #120;
53 | $display("Test 4 | Time: %t | A: %h | B: %h | Result: %h",$time, A, B, result);
54 |
55 | // Test 5: 5.0 / 2.0
56 | A = 32'h40a00000; // 5.0
57 | B = 32'h40000000; // 2.0
58 | #120;
59 | $display("Test 5 | Time: %t | A: %h | B: %h | Result: %h",$time, A, B, result);
60 |
61 | // Test 6: 0.0 / 3.0
62 | A = 32'h00000000; // 0.0
63 | B = 32'h40400000; // 3.0
64 | #120;
65 | $display("Test 6 | Time: %t | A: %h | B: %h | Result: %h",$time, A, B, result);
66 |
67 | // Test 7: 2.0 / 8.0
68 | A = 32'h40000000; // 2.0
69 | B = 32'h40400000; // 8.0
70 | #120;
71 | $display("Test 7 | Time: %t | A: %h | B: %h | Result: %h",$time, A, B, result);
72 |
73 | // Test 8: 2.5 / 1.2
74 | A = 32'h40200000; // 2.5
75 | B = 32'h3f99999a; // 1.2
76 | #120;
77 | $display("Test 8 | Time: %t | A: %h | B: %h | Result: %h",$time, A, B, result);
78 |
79 | // Test 9: 0.75 / 0.5
80 | A = 32'h3f400000; // 0.75
81 | B = 32'h3f000000; // 0.5
82 | #120;
83 | $display("Test 9 | Time: %t | A: %h | B: %h | Result: %h",$time, A, B, result);
84 |
85 | // Test 10: -8.0 / 2.0
86 | A = 32'hc1000000; // -8.0
87 | B = 32'h40000000; // 2.0
88 | #120;
89 | $display("Test 10 | Time: %t | A: %h | B: %h | Result: %h",$time, A, B, result);
90 |
91 | // Test 11: 8.0 / -2.0
92 | A = 32'h41000000; // 8.0
93 | B = 32'hc0000000; // -2.0
94 | #120;
95 | $display("Test 11 | Time: %t | A: %h | B: %h | Result: %h",$time, A, B, result);
96 |
97 | // Test 12: -8.0 / -2.0
98 | A = 32'hc1000000; // -8.0
99 | B = 32'hc0000000; // -2.0
100 | #120;
101 | $display("Test 12 | Time: %t | A: %h | B: %h | Result: %h",$time, A, B, result);
102 |
103 | // Test 13: 3.0 / 0.0 (division by zero)
104 | A = 32'h40400000; // 3.0
105 | B = 32'h00000000; // 0.0
106 | #120;
107 | $display("Test 13 | Time: %t | A: %h | B: %h | Result: %h",$time, A, B, result);
108 |
109 | $finish;
110 |
111 | end
112 |
113 | endmodule
--------------------------------------------------------------------------------
/DeepLearning/dataset/glass/datasetevaluation.csv:
--------------------------------------------------------------------------------
1 | 130,1.52020,13.98000,1.35000,1.63000,71.76000,0.39000,10.56000,0.00000,0.18000,0,1,0,0,0,0,0
2 | 15,1.51763,12.61000,3.59000,1.31000,73.29000,0.58000,8.50000,0.00000,0.00000,1,0,0,0,0,0,0
3 | 198,1.51727,14.70000,0.00000,2.34000,73.28000,0.00000,8.95000,0.66000,0.00000,0,0,0,0,0,0,1
4 | 207,1.51645,14.94000,0.00000,1.87000,73.11000,0.00000,8.67000,1.38000,0.00000,0,0,0,0,0,0,1
5 | 24,1.51751,12.81000,3.57000,1.35000,73.02000,0.62000,8.59000,0.00000,0.00000,1,0,0,0,0,0,0
6 | 197,1.51556,13.87000,0.00000,2.54000,73.23000,0.14000,9.41000,0.81000,0.01000,0,0,0,0,0,0,1
7 | 94,1.51590,13.24000,3.34000,1.47000,73.10000,0.39000,8.22000,0.00000,0.00000,0,1,0,0,0,0,0
8 | 157,1.51655,13.41000,3.39000,1.28000,72.64000,0.52000,8.65000,0.00000,0.00000,0,0,1,0,0,0,0
9 | 70,1.52300,13.31000,3.58000,0.82000,71.99000,0.12000,10.17000,0.00000,0.03000,1,0,0,0,0,0,0
10 | 185,1.51115,17.38000,0.00000,0.34000,75.41000,0.00000,6.65000,0.00000,0.00000,0,0,0,0,0,1,0
11 | 193,1.51623,14.20000,0.00000,2.79000,73.46000,0.04000,9.04000,0.40000,0.09000,0,0,0,0,0,0,1
12 | 82,1.51593,13.25000,3.45000,1.43000,73.17000,0.61000,7.86000,0.00000,0.00000,0,1,0,0,0,0,0
13 | 99,1.51689,12.67000,2.88000,1.71000,73.21000,0.73000,8.54000,0.00000,0.00000,0,1,0,0,0,0,0
14 | 159,1.51776,13.53000,3.41000,1.52000,72.04000,0.58000,8.79000,0.00000,0.00000,0,0,1,0,0,0,0
15 | 115,1.51847,13.10000,3.97000,1.19000,72.44000,0.60000,8.43000,0.00000,0.00000,0,1,0,0,0,0,0
16 | 89,1.51618,13.01000,3.50000,1.48000,72.89000,0.60000,8.12000,0.00000,0.00000,0,1,0,0,0,0,0
17 | 106,1.52475,11.45000,0.00000,1.88000,72.19000,0.81000,13.24000,0.00000,0.34000,0,1,0,0,0,0,0
18 | 6,1.51596,12.79000,3.61000,1.62000,72.97000,0.64000,8.07000,0.00000,0.26000,1,0,0,0,0,0,0
19 | 188,1.52315,13.44000,3.34000,1.23000,72.38000,0.60000,8.83000,0.00000,0.00000,0,0,0,0,0,0,1
20 | 151,1.51665,13.14000,3.45000,1.76000,72.48000,0.60000,8.38000,0.00000,0.17000,0,0,1,0,0,0,0
21 | 87,1.51569,13.24000,3.49000,1.47000,73.25000,0.38000,8.03000,0.00000,0.00000,0,1,0,0,0,0,0
22 | 171,1.52369,13.44000,0.00000,1.58000,72.22000,0.32000,12.24000,0.00000,0.00000,0,0,0,0,1,0,0
23 | 126,1.51872,12.93000,3.66000,1.56000,72.51000,0.58000,8.55000,0.00000,0.12000,0,1,0,0,0,0,0
24 | 186,1.51131,13.69000,3.20000,1.81000,72.81000,1.76000,5.43000,1.19000,0.00000,0,0,0,0,0,0,1
25 | 110,1.51818,13.72000,0.00000,0.56000,74.45000,0.00000,10.99000,0.00000,0.00000,0,1,0,0,0,0,0
26 | 163,1.52211,14.19000,3.78000,0.91000,71.36000,0.23000,9.14000,0.00000,0.37000,0,0,1,0,0,0,0
27 | 177,1.51905,14.00000,2.39000,1.56000,72.37000,0.00000,9.57000,0.00000,0.00000,0,0,0,0,0,1,0
28 | 121,1.51844,13.25000,3.76000,1.32000,72.40000,0.58000,8.42000,0.00000,0.00000,0,1,0,0,0,0,0
29 | 208,1.51831,14.39000,0.00000,1.82000,72.86000,1.41000,6.47000,2.88000,0.00000,0,0,0,0,0,0,1
30 | 51,1.52320,13.72000,3.72000,0.51000,71.75000,0.09000,10.06000,0.00000,0.16000,1,0,0,0,0,0,0
31 | 59,1.51754,13.48000,3.74000,1.17000,72.99000,0.59000,8.03000,0.00000,0.00000,1,0,0,0,0,0,0
32 | 132,1.52614,13.70000,0.00000,1.36000,71.24000,0.19000,13.44000,0.00000,0.10000,0,1,0,0,0,0,0
33 | 91,1.51841,12.93000,3.74000,1.11000,72.28000,0.64000,8.96000,0.00000,0.22000,0,1,0,0,0,0,0
34 | 71,1.51574,14.86000,3.67000,1.74000,71.87000,0.16000,7.36000,0.00000,0.12000,0,1,0,0,0,0,0
35 | 204,1.51658,14.80000,0.00000,1.99000,73.11000,0.00000,8.28000,1.71000,0.00000,0,0,0,0,0,0,1
36 | 85,1.51409,14.25000,3.09000,2.08000,72.28000,1.10000,7.08000,0.00000,0.00000,0,1,0,0,0,0,0
37 | 74,1.51631,13.34000,3.57000,1.57000,72.87000,0.61000,7.89000,0.00000,0.00000,0,1,0,0,0,0,0
38 | 192,1.51602,14.85000,0.00000,2.38000,73.28000,0.00000,8.76000,0.64000,0.09000,0,0,0,0,0,0,1
39 | 162,1.51934,13.64000,3.54000,0.75000,72.65000,0.16000,8.89000,0.15000,0.24000,0,0,1,0,0,0,0
40 | 88,1.51645,13.40000,3.49000,1.52000,72.65000,0.67000,8.08000,0.00000,0.10000,0,1,0,0,0,0,0
41 | 60,1.51754,13.39000,3.66000,1.19000,72.79000,0.57000,8.27000,0.00000,0.11000,1,0,0,0,0,0,0
42 | 117,1.51829,13.24000,3.90000,1.41000,72.33000,0.55000,8.31000,0.00000,0.10000,0,1,0,0,0,0,0
43 |
--------------------------------------------------------------------------------
/FederatedLearningFPGA/db/NeuralNetworkFPGA.smp_dump.txt:
--------------------------------------------------------------------------------
1 |
2 | State Machine - |NeuralNetworkFPGA|output_softmax_layer:sl|softmax_neuron:sn3|neuron_backpropagation_state
3 | Name neuron_backpropagation_state.01
4 | neuron_backpropagation_state.00 0
5 | neuron_backpropagation_state.01 1
6 |
7 | State Machine - |NeuralNetworkFPGA|output_softmax_layer:sl|softmax_neuron:sn3|neuron_deltafunction_state
8 | Name neuron_deltafunction_state.01
9 | neuron_deltafunction_state.00 0
10 | neuron_deltafunction_state.01 1
11 |
12 | State Machine - |NeuralNetworkFPGA|output_softmax_layer:sl|softmax_neuron:sn2|neuron_backpropagation_state
13 | Name neuron_backpropagation_state.01
14 | neuron_backpropagation_state.00 0
15 | neuron_backpropagation_state.01 1
16 |
17 | State Machine - |NeuralNetworkFPGA|output_softmax_layer:sl|softmax_neuron:sn2|neuron_deltafunction_state
18 | Name neuron_deltafunction_state.01
19 | neuron_deltafunction_state.00 0
20 | neuron_deltafunction_state.01 1
21 |
22 | State Machine - |NeuralNetworkFPGA|output_softmax_layer:sl|softmax_neuron:sn1|neuron_backpropagation_state
23 | Name neuron_backpropagation_state.01
24 | neuron_backpropagation_state.00 0
25 | neuron_backpropagation_state.01 1
26 |
27 | State Machine - |NeuralNetworkFPGA|output_softmax_layer:sl|softmax_neuron:sn1|neuron_deltafunction_state
28 | Name neuron_deltafunction_state.01
29 | neuron_deltafunction_state.00 0
30 | neuron_deltafunction_state.01 1
31 |
32 | State Machine - |NeuralNetworkFPGA|hidden_layer:hl2|hidden_neuron:n2|neuron_backpropagation_state
33 | Name neuron_backpropagation_state.01
34 | neuron_backpropagation_state.00 0
35 | neuron_backpropagation_state.01 1
36 |
37 | State Machine - |NeuralNetworkFPGA|hidden_layer:hl2|hidden_neuron:n2|neuron_deltafunction_state
38 | Name neuron_deltafunction_state.01
39 | neuron_deltafunction_state.00 0
40 | neuron_deltafunction_state.01 1
41 |
42 | State Machine - |NeuralNetworkFPGA|hidden_layer:hl2|hidden_neuron:n1|neuron_backpropagation_state
43 | Name neuron_backpropagation_state.01
44 | neuron_backpropagation_state.00 0
45 | neuron_backpropagation_state.01 1
46 |
47 | State Machine - |NeuralNetworkFPGA|hidden_layer:hl2|hidden_neuron:n1|neuron_deltafunction_state
48 | Name neuron_deltafunction_state.01
49 | neuron_deltafunction_state.00 0
50 | neuron_deltafunction_state.01 1
51 |
52 | State Machine - |NeuralNetworkFPGA|hidden_layer:hl2|hidden_neuron:n0|neuron_backpropagation_state
53 | Name neuron_backpropagation_state.01
54 | neuron_backpropagation_state.00 0
55 | neuron_backpropagation_state.01 1
56 |
57 | State Machine - |NeuralNetworkFPGA|hidden_layer:hl2|hidden_neuron:n0|neuron_deltafunction_state
58 | Name neuron_deltafunction_state.01
59 | neuron_deltafunction_state.00 0
60 | neuron_deltafunction_state.01 1
61 |
62 | State Machine - |NeuralNetworkFPGA|hidden_layer:hl1|hidden_neuron:n2|neuron_backpropagation_state
63 | Name neuron_backpropagation_state.01
64 | neuron_backpropagation_state.00 0
65 | neuron_backpropagation_state.01 1
66 |
67 | State Machine - |NeuralNetworkFPGA|hidden_layer:hl1|hidden_neuron:n2|neuron_deltafunction_state
68 | Name neuron_deltafunction_state.01
69 | neuron_deltafunction_state.00 0
70 | neuron_deltafunction_state.01 1
71 |
72 | State Machine - |NeuralNetworkFPGA|hidden_layer:hl1|hidden_neuron:n1|neuron_backpropagation_state
73 | Name neuron_backpropagation_state.01
74 | neuron_backpropagation_state.00 0
75 | neuron_backpropagation_state.01 1
76 |
77 | State Machine - |NeuralNetworkFPGA|hidden_layer:hl1|hidden_neuron:n1|neuron_deltafunction_state
78 | Name neuron_deltafunction_state.01
79 | neuron_deltafunction_state.00 0
80 | neuron_deltafunction_state.01 1
81 |
82 | State Machine - |NeuralNetworkFPGA|hidden_layer:hl1|hidden_neuron:n0|neuron_backpropagation_state
83 | Name neuron_backpropagation_state.01
84 | neuron_backpropagation_state.00 0
85 | neuron_backpropagation_state.01 1
86 |
87 | State Machine - |NeuralNetworkFPGA|hidden_layer:hl1|hidden_neuron:n0|neuron_deltafunction_state
88 | Name neuron_deltafunction_state.01
89 | neuron_deltafunction_state.00 0
90 | neuron_deltafunction_state.01 1
91 |
--------------------------------------------------------------------------------
/FederatedLearningServer/fedlearning.json:
--------------------------------------------------------------------------------
1 | {
2 | "trainingsnumber": 0,
3 | "neuronnetwork": {
4 | "layers": 4,
5 | "layersArray": [
6 | {
7 | "neurons": 4,
8 | "neuronsArray": [
9 | {
10 | "neurontype": "INPUT",
11 | "weights": 0,
12 | "weightsArray": [
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14 | ]
15 | },
16 | {
17 | "neurontype": "INPUT",
18 | "weights": 0,
19 | "weightsArray": [
20 |
21 | ]
22 | },
23 | {
24 | "neurontype": "INPUT",
25 | "weights": 0,
26 | "weightsArray": [
27 |
28 | ]
29 | },
30 | {
31 | "neurontype": "INPUT",
32 | "weights": 0,
33 | "weightsArray": [
34 |
35 | ]
36 | }
37 | ]
38 | },
39 | {
40 | "neurons": 4,
41 | "neuronsArray": [
42 | {
43 | "neurontype": "HIDDEN",
44 | "weights": 4,
45 | "weightsArray": [
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47 | 0.20000000298023224,
48 | 0.23000000417232513,
49 | 0.88999998569488525
50 | ]
51 | },
52 | {
53 | "neurontype": "HIDDEN",
54 | "weights": 4,
55 | "weightsArray": [
56 | 0.81999999284744263,
57 | 0.49000000953674316,
58 | 0.0599999986588955,
59 | 0.46000000834465027
60 | ]
61 | },
62 | {
63 | "neurontype": "HIDDEN",
64 | "weights": 4,
65 | "weightsArray": [
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67 | 0.18000000715255737,
68 | 0,
69 | 0.25
70 | ]
71 | },
72 | {
73 | "neurontype": "HIDDEN",
74 | "weights": 4,
75 | "weightsArray": [
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77 | 0.10000000149011612,
78 | 0.34000000357627869,
79 | 0.600000023841858
80 | ]
81 | }
82 | ]
83 | },
84 | {
85 | "neurons": 2,
86 | "neuronsArray": [
87 | {
88 | "neurontype": "HIDDEN",
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90 | "weightsArray": [
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92 | 0.509999990463257,
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96 | },
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102 | 0.649999976158142,
103 | 0.2800000011920929,
104 | 0.34999999403953552
105 | ]
106 | }
107 | ]
108 | },
109 | {
110 | "neurons": 3,
111 | "neuronsArray": [
112 | {
113 | "neurontype": "OUTPUT",
114 | "weights": 2,
115 | "weightsArray": [
116 | 0.479999989271164,
117 | 0.0900000035762787
118 | ]
119 | },
120 | {
121 | "neurontype": "OUTPUT",
122 | "weights": 2,
123 | "weightsArray": [
124 | 0.76999998092651367,
125 | 0.68000000715255737
126 | ]
127 | },
128 | {
129 | "neurontype": "OUTPUT",
130 | "weights": 2,
131 | "weightsArray": [
132 | 0.8399999737739563,
133 | 0.649999976158142
134 | ]
135 | }
136 | ]
137 | }
138 | ]
139 | }
140 | }
--------------------------------------------------------------------------------
/FederatedLearningFPGA/z_module_analysis.py:
--------------------------------------------------------------------------------
1 | import struct
2 |
3 | def ieee754_hex_to_float(hex_string):
4 | """Convert IEEE754 hexadecimal string to float"""
5 | try:
6 | hex_val = hex_string.replace('h', '').replace('0x', '')
7 | bytes_val = int(hex_val, 16).to_bytes(4, byteorder='big')
8 | float_val = struct.unpack('>f', bytes_val)[0]
9 | return float_val
10 | except Exception as e:
11 | return f"Error converting {hex_string}: {e}"
12 |
13 | def analyze_z_module_execution():
14 | """Analyze the Z module execution step by step"""
15 |
16 | print("=== Z Module Execution Analysis ===")
17 | print("Test Case 1: Feedforward with inputs [4.0, 3.0, 2.0, 1.0]")
18 | print("Weights: All 0.5 (3f000000)")
19 | print("=" * 50)
20 |
21 | # Test inputs and expected calculations
22 | inputs = [4.0, 3.0, 2.0, 1.0]
23 | weight = 0.5 # 3f000000
24 |
25 | print("\n--- Expected Calculations ---")
26 | expected_sum = 0
27 | for i, input_val in enumerate(inputs):
28 | product = input_val * weight
29 | expected_sum += product
30 | print(f"Input {i}: {input_val} × {weight} = {product}")
31 | print(f"Expected Total Sum: {expected_sum}")
32 | print(f"Expected Final Result (with bias=0): {expected_sum}")
33 |
34 | # Actual execution from test output
35 | print("\n--- Actual Z Module Execution ---")
36 | print("From test output:")
37 |
38 | execution_steps = [
39 | {"index": 0, "M1_A1": "3f000000", "A1_Z": "3f000000", "Z": "3f000000", "A2_OUT": "00800000"},
40 | {"index": 1, "M1_A1": "3f800000", "A1_Z": "3f800000", "Z": "3f800000", "A2_OUT": "3f000000"},
41 | {"index": 2, "M1_A1": "40000000", "A1_Z": "40000000", "Z": "40000000", "A2_OUT": "3f800000"},
42 | {"index": 3, "M1_A1": "3fc00000", "A1_Z": "3fc00000", "Z": "3fc00000", "A2_OUT": "40000000"},
43 | {"index": 4, "result": "40600000"}
44 | ]
45 |
46 | for step in execution_steps:
47 | if "result" in step:
48 | print(f"Index {step['index']}: result = {step['result']} = {ieee754_hex_to_float(step['result'])}")
49 | else:
50 | m1_a1 = ieee754_hex_to_float(step['M1_A1'])
51 | a1_z = ieee754_hex_to_float(step['A1_Z'])
52 | z = ieee754_hex_to_float(step['Z'])
53 | a2_out = ieee754_hex_to_float(step['A2_OUT'])
54 |
55 | print(f"Index {step['index']}: M1_A1={step['M1_A1']}({m1_a1}) | A1_Z={step['A1_Z']}({a1_z}) | Z={step['Z']}({z}) | A2_OUT={step['A2_OUT']}({a2_out})")
56 |
57 | print("\n--- Analysis of the Problem ---")
58 | print("Looking at the execution steps:")
59 | print("1. Index 0: Z starts at 0, M1_A1 = 0.5 (4.0 × 0.5), A1_Z = 0.5 (0 + 0.5), Z becomes 0.5")
60 | print("2. Index 1: Z = 0.5, M1_A1 = 1.0 (3.0 × 0.5), A1_Z = 1.0 (0.5 + 1.0), Z becomes 1.0")
61 | print("3. Index 2: Z = 1.0, M1_A1 = 2.0 (2.0 × 0.5), A1_Z = 2.0 (1.0 + 2.0), Z becomes 2.0")
62 | print("4. Index 3: Z = 2.0, M1_A1 = 1.5 (1.0 × 0.5), A1_Z = 1.5 (2.0 + 1.5), Z becomes 1.5")
63 | print("5. Final result = 3.5")
64 |
65 | print("\n--- The Issue ---")
66 | print("The problem is in step 4 (Index 3):")
67 | print("- Z should be 2.0 from previous step")
68 | print("- M1_A1 should be 1.5 (1.0 × 0.5)")
69 | print("- A1_Z should be 3.5 (2.0 + 1.5)")
70 | print("- But Z becomes 1.5 instead of 3.5")
71 | print("- This suggests Z is being overwritten with M1_A1 instead of A1_Z")
72 |
73 | print("\n--- Root Cause Analysis ---")
74 | print("Looking at the Z module code:")
75 | print("Z = A1_Z; // This should work correctly")
76 | print("But the test output shows Z = M1_A1 instead of Z = A1_Z")
77 | print("This suggests a timing issue or the adder A1 is not working correctly")
78 |
79 | print("\n--- Verification ---")
80 | print("Expected final Z value: 5.0")
81 | print("Actual final Z value: 3.5")
82 | print("Difference: 1.5 (which is exactly the last M1_A1 value)")
83 | print("This confirms that Z is being set to M1_A1 instead of A1_Z")
84 |
85 | if __name__ == "__main__":
86 | analyze_z_module_execution()
87 |
--------------------------------------------------------------------------------
/DeepLearning/dataset/iris/Iris.csv:
--------------------------------------------------------------------------------
1 | 1,5.1,3.5,1.4,0.2,1,0,0
2 | 2,4.9,3.0,1.4,0.2,1,0,0
3 | 3,4.7,3.2,1.3,0.2,1,0,0
4 | 4,4.6,3.1,1.5,0.2,1,0,0
5 | 5,5.0,3.6,1.4,0.2,1,0,0
6 | 6,5.4,3.9,1.7,0.4,1,0,0
7 | 7,4.6,3.4,1.4,0.3,1,0,0
8 | 8,5.0,3.4,1.5,0.2,1,0,0
9 | 9,4.4,2.9,1.4,0.2,1,0,0
10 | 10,4.9,3.1,1.5,0.1,1,0,0
11 | 11,5.4,3.7,1.5,0.2,1,0,0
12 | 12,4.8,3.4,1.6,0.2,1,0,0
13 | 13,4.8,3.0,1.4,0.1,1,0,0
14 | 14,4.3,3.0,1.1,0.1,1,0,0
15 | 15,5.8,4.0,1.2,0.2,1,0,0
16 | 16,5.7,4.4,1.5,0.4,1,0,0
17 | 17,5.4,3.9,1.3,0.4,1,0,0
18 | 18,5.1,3.5,1.4,0.3,1,0,0
19 | 19,5.7,3.8,1.7,0.3,1,0,0
20 | 20,5.1,3.8,1.5,0.3,1,0,0
21 | 21,5.4,3.4,1.7,0.2,1,0,0
22 | 22,5.1,3.7,1.5,0.4,1,0,0
23 | 23,4.6,3.6,1.0,0.2,1,0,0
24 | 24,5.1,3.3,1.7,0.5,1,0,0
25 | 25,4.8,3.4,1.9,0.2,1,0,0
26 | 26,5.0,3.0,1.6,0.2,1,0,0
27 | 27,5.0,3.4,1.6,0.4,1,0,0
28 | 28,5.2,3.5,1.5,0.2,1,0,0
29 | 29,5.2,3.4,1.4,0.2,1,0,0
30 | 30,4.7,3.2,1.6,0.2,1,0,0
31 | 31,4.8,3.1,1.6,0.2,1,0,0
32 | 32,5.4,3.4,1.5,0.4,1,0,0
33 | 33,5.2,4.1,1.5,0.1,1,0,0
34 | 34,5.5,4.2,1.4,0.2,1,0,0
35 | 35,4.9,3.1,1.5,0.1,1,0,0
36 | 36,5.0,3.2,1.2,0.2,1,0,0
37 | 37,5.5,3.5,1.3,0.2,1,0,0
38 | 38,4.9,3.1,1.5,0.1,1,0,0
39 | 39,4.4,3.0,1.3,0.2,1,0,0
40 | 40,5.1,3.4,1.5,0.2,1,0,0
41 | 41,5.0,3.5,1.3,0.3,1,0,0
42 | 42,4.5,2.3,1.3,0.3,1,0,0
43 | 43,4.4,3.2,1.3,0.2,1,0,0
44 | 44,5.0,3.5,1.6,0.6,1,0,0
45 | 45,5.1,3.8,1.9,0.4,1,0,0
46 | 46,4.8,3.0,1.4,0.3,1,0,0
47 | 47,5.1,3.8,1.6,0.2,1,0,0
48 | 48,4.6,3.2,1.4,0.2,1,0,0
49 | 49,5.3,3.7,1.5,0.2,1,0,0
50 | 50,5.0,3.3,1.4,0.2,1,0,0
51 | 51,7.0,3.2,4.7,1.4,0,1,0
52 | 52,6.4,3.2,4.5,1.5,0,1,0
53 | 53,6.9,3.1,4.9,1.5,0,1,0
54 | 54,5.5,2.3,4.0,1.3,0,1,0
55 | 55,6.5,2.8,4.6,1.5,0,1,0
56 | 56,5.7,2.8,4.5,1.3,0,1,0
57 | 57,6.3,3.3,4.7,1.6,0,1,0
58 | 58,4.9,2.4,3.3,1.0,0,1,0
59 | 59,6.6,2.9,4.6,1.3,0,1,0
60 | 60,5.2,2.7,3.9,1.4,0,1,0
61 | 61,5.0,2.0,3.5,1.0,0,1,0
62 | 62,5.9,3.0,4.2,1.5,0,1,0
63 | 63,6.0,2.2,4.0,1.0,0,1,0
64 | 64,6.1,2.9,4.7,1.4,0,1,0
65 | 65,5.6,2.9,3.6,1.3,0,1,0
66 | 66,6.7,3.1,4.4,1.4,0,1,0
67 | 67,5.6,3.0,4.5,1.5,0,1,0
68 | 68,5.8,2.7,4.1,1.0,0,1,0
69 | 69,6.2,2.2,4.5,1.5,0,1,0
70 | 70,5.6,2.5,3.9,1.1,0,1,0
71 | 71,5.9,3.2,4.8,1.8,0,1,0
72 | 72,6.1,2.8,4.0,1.3,0,1,0
73 | 73,6.3,2.5,4.9,1.5,0,1,0
74 | 74,6.1,2.8,4.7,1.2,0,1,0
75 | 75,6.4,2.9,4.3,1.3,0,1,0
76 | 76,6.6,3.0,4.4,1.4,0,1,0
77 | 77,6.8,2.8,4.8,1.4,0,1,0
78 | 78,6.7,3.0,5.0,1.7,0,1,0
79 | 79,6.0,2.9,4.5,1.5,0,1,0
80 | 80,5.7,2.6,3.5,1.0,0,1,0
81 | 81,5.5,2.4,3.8,1.1,0,1,0
82 | 82,5.5,2.4,3.7,1.0,0,1,0
83 | 83,5.8,2.7,3.9,1.2,0,1,0
84 | 84,6.0,2.7,5.1,1.6,0,1,0
85 | 85,5.4,3.0,4.5,1.5,0,1,0
86 | 86,6.0,3.4,4.5,1.6,0,1,0
87 | 87,6.7,3.1,4.7,1.5,0,1,0
88 | 88,6.3,2.3,4.4,1.3,0,1,0
89 | 89,5.6,3.0,4.1,1.3,0,1,0
90 | 90,5.5,2.5,4.0,1.3,0,1,0
91 | 91,5.5,2.6,4.4,1.2,0,1,0
92 | 92,6.1,3.0,4.6,1.4,0,1,0
93 | 93,5.8,2.6,4.0,1.2,0,1,0
94 | 94,5.0,2.3,3.3,1.0,0,1,0
95 | 95,5.6,2.7,4.2,1.3,0,1,0
96 | 96,5.7,3.0,4.2,1.2,0,1,0
97 | 97,5.7,2.9,4.2,1.3,0,1,0
98 | 98,6.2,2.9,4.3,1.3,0,1,0
99 | 99,5.1,2.5,3.0,1.1,0,1,0
100 | 100,5.7,2.8,4.1,1.3,0,1,0
101 | 101,6.3,3.3,6.0,2.5,0,0,1
102 | 102,5.8,2.7,5.1,1.9,0,0,1
103 | 103,7.1,3.0,5.9,2.1,0,0,1
104 | 104,6.3,2.9,5.6,1.8,0,0,1
105 | 105,6.5,3.0,5.8,2.2,0,0,1
106 | 106,7.6,3.0,6.6,2.1,0,0,1
107 | 107,4.9,2.5,4.5,1.7,0,0,1
108 | 108,7.3,2.9,6.3,1.8,0,0,1
109 | 109,6.7,2.5,5.8,1.8,0,0,1
110 | 110,7.2,3.6,6.1,2.5,0,0,1
111 | 111,6.5,3.2,5.1,2.0,0,0,1
112 | 112,6.4,2.7,5.3,1.9,0,0,1
113 | 113,6.8,3.0,5.5,2.1,0,0,1
114 | 114,5.7,2.5,5.0,2.0,0,0,1
115 | 115,5.8,2.8,5.1,2.4,0,0,1
116 | 116,6.4,3.2,5.3,2.3,0,0,1
117 | 117,6.5,3.0,5.5,1.8,0,0,1
118 | 118,7.7,3.8,6.7,2.2,0,0,1
119 | 119,7.7,2.6,6.9,2.3,0,0,1
120 | 120,6.0,2.2,5.0,1.5,0,0,1
121 | 121,6.9,3.2,5.7,2.3,0,0,1
122 | 122,5.6,2.8,4.9,2.0,0,0,1
123 | 123,7.7,2.8,6.7,2.0,0,0,1
124 | 124,6.3,2.7,4.9,1.8,0,0,1
125 | 125,6.7,3.3,5.7,2.1,0,0,1
126 | 126,7.2,3.2,6.0,1.8,0,0,1
127 | 127,6.2,2.8,4.8,1.8,0,0,1
128 | 128,6.1,3.0,4.9,1.8,0,0,1
129 | 129,6.4,2.8,5.6,2.1,0,0,1
130 | 130,7.2,3.0,5.8,1.6,0,0,1
131 | 131,7.4,2.8,6.1,1.9,0,0,1
132 | 132,7.9,3.8,6.4,2.0,0,0,1
133 | 133,6.4,2.8,5.6,2.2,0,0,1
134 | 134,6.3,2.8,5.1,1.5,0,0,1
135 | 135,6.1,2.6,5.6,1.4,0,0,1
136 | 136,7.7,3.0,6.1,2.3,0,0,1
137 | 137,6.3,3.4,5.6,2.4,0,0,1
138 | 138,6.4,3.1,5.5,1.8,0,0,1
139 | 139,6.0,3.0,4.8,1.8,0,0,1
140 | 140,6.9,3.1,5.4,2.1,0,0,1
141 | 141,6.7,3.1,5.6,2.4,0,0,1
142 | 142,6.9,3.1,5.1,2.3,0,0,1
143 | 143,5.8,2.7,5.1,1.9,0,0,1
144 | 144,6.8,3.2,5.9,2.3,0,0,1
145 | 145,6.7,3.3,5.7,2.5,0,0,1
146 | 146,6.7,3.0,5.2,2.3,0,0,1
147 | 147,6.3,2.5,5.0,1.9,0,0,1
148 | 148,6.5,3.0,5.2,2.0,0,0,1
149 | 149,6.2,3.4,5.4,2.3,0,0,1
150 | 150,5.9,3.0,5.1,1.8,0,0,1
151 |
--------------------------------------------------------------------------------
/FederatedLearningESP32/main/espconfiguration.c:
--------------------------------------------------------------------------------
1 | #include "espconfiguration.h"
2 |
3 | static const char* TAG = "FileSystem";
4 |
5 | static void wifi_event_handler(void *event_handler_arg, esp_event_base_t event_base, int32_t event_id, void *event_data)
6 | {
7 | switch (event_id)
8 | {
9 | case WIFI_EVENT_STA_START:
10 | printf("WiFi connecting ... \n");
11 | break;
12 | case WIFI_EVENT_STA_CONNECTED:
13 | printf("WiFi connected ... \n");
14 | break;
15 | case WIFI_EVENT_STA_DISCONNECTED:
16 | printf("WiFi lost connection ... \n");
17 | break;
18 | case IP_EVENT_STA_GOT_IP:
19 | printf("WiFi got IP ... \n\n");
20 | break;
21 | default:
22 | //printf("ERROR ... \n\n");
23 |
24 | break;
25 | }
26 | }
27 |
28 | void WIFIConfiguration()
29 | {
30 |
31 | nvs_flash_init();
32 |
33 | printf("Starting NVS Flash...\n");
34 | esp_err_t nvs_ret = nvs_flash_init();
35 |
36 | if (nvs_ret == ESP_OK) {
37 | printf("NVS Flash started!\n");
38 | } else {
39 | printf("Error to start NVS Flash. Error Code: %d\n", nvs_ret);
40 | }
41 |
42 | printf("Wi-Fi/LwIP Init Phase\n");
43 | // 1 - Wi-Fi/LwIP Init Phase
44 | esp_netif_init(); // TCP/IP initiation s1.1
45 | esp_event_loop_create_default(); // event loop s1.2
46 | esp_netif_create_default_wifi_sta(); // WiFi station s1.3
47 | wifi_init_config_t wifi_initiation = WIFI_INIT_CONFIG_DEFAULT();
48 | esp_wifi_init(&wifi_initiation); // s1.4
49 | printf("Wi-Fi Configuration Phase\n");
50 | // 2 - Wi-Fi Configuration Phase
51 | esp_event_handler_register(WIFI_EVENT, ESP_EVENT_ANY_ID, wifi_event_handler, NULL);
52 | esp_event_handler_register(IP_EVENT, IP_EVENT_STA_GOT_IP, wifi_event_handler, NULL);
53 | esp_wifi_set_mode(WIFI_MODE_STA);
54 | wifi_config_t wifi_configuration = {
55 | .sta = {
56 | .ssid = WIFI_SSID,
57 | .password = WIFI_PASSWORD}};
58 | esp_wifi_set_config(ESP_IF_WIFI_STA, &wifi_configuration);
59 | printf("Wi-Fi Start Phase\n");
60 | // 3 - Wi-Fi Start Phase
61 | esp_wifi_start();
62 | printf("Wi-Fi Connect Phase\n");
63 | // 4- Wi-Fi Connect Phase
64 | esp_wifi_connect();
65 | printf("WI-FI was initiated\n");
66 |
67 | }
68 |
69 | void UARTConfiguration(){
70 |
71 | uart_config_t uart_config = {
72 | .baud_rate = 115200,
73 | .data_bits = UART_DATA_8_BITS,
74 | .parity = UART_PARITY_DISABLE,
75 | .stop_bits = UART_STOP_BITS_1,
76 | .flow_ctrl = UART_HW_FLOWCTRL_DISABLE
77 | };
78 | uart_param_config(UART_NUM_0, &uart_config);
79 | uart_driver_install(UART_NUM_0, 1024, 0, 0, NULL, 0);
80 | }
81 |
82 | void GPIOConfiguration(){
83 | gpio_config_t io_conf;
84 |
85 | // Configurar a porta GPIO12 como saída (LED_PIN_ERROR)
86 | io_conf.intr_type = GPIO_INTR_DISABLE;
87 | io_conf.mode = GPIO_MODE_OUTPUT;
88 | io_conf.pin_bit_mask = (1ULL << LED_PIN_ERROR);
89 | io_conf.pull_down_en = 0;
90 | io_conf.pull_up_en = 0;
91 | gpio_config(&io_conf);
92 |
93 | // Configurar a porta GPIO14 como saída (LED_PIN_WORKING)
94 | io_conf.intr_type = GPIO_INTR_DISABLE;
95 | io_conf.mode = GPIO_MODE_OUTPUT;
96 | io_conf.pin_bit_mask = (1ULL << LED_PIN_WORKING);
97 | io_conf.pull_down_en = 0;
98 | io_conf.pull_up_en = 0;
99 | gpio_config(&io_conf);
100 |
101 | // Configurar a porta GPIO27 como saída (LED_PIN_SYNC)
102 | io_conf.intr_type = GPIO_INTR_DISABLE;
103 | io_conf.mode = GPIO_MODE_OUTPUT;
104 | io_conf.pin_bit_mask = (1ULL << LED_PIN_SYNC);
105 | io_conf.pull_down_en = 0;
106 | io_conf.pull_up_en = 0;
107 | gpio_config(&io_conf);
108 |
109 | // Configurar a porta GPIO26 como entrada (botão)
110 | io_conf.intr_type = GPIO_INTR_DISABLE;
111 | io_conf.mode = GPIO_MODE_INPUT;
112 | io_conf.pin_bit_mask = (1ULL << BUTTON_PIN);
113 | io_conf.pull_down_en = GPIO_PULLDOWN_DISABLE;
114 | io_conf.pull_up_en = GPIO_PULLUP_ENABLE; // Ativar resistor de pull-up interno
115 | gpio_config(&io_conf);
116 |
117 | }
118 |
119 | void SPIFFSConfiguration(){
120 |
121 |
122 | //Monta o sistema de arquivos SPIFFS
123 | esp_vfs_spiffs_conf_t conf = {
124 | .base_path = "/storage",
125 | .partition_label = "storage",
126 | .max_files = 5,
127 | .format_if_mount_failed = true
128 | };
129 |
130 | esp_err_t ret = esp_vfs_spiffs_register(&conf);
131 |
132 | if(ret != ESP_OK){
133 | ESP_LOGE(TAG,"Failed to initialize SPIFFS : (%s)",esp_err_to_name(ret) );
134 | return;
135 | }
136 |
137 | size_t total = 0, used = 0;
138 | ret = esp_spiffs_info(conf.partition_label,&total,&used);
139 | if (ret != ESP_OK) {
140 | ESP_LOGE(TAG,"Failed to read partition : (%s)",esp_err_to_name(ret) );
141 | }else{
142 | ESP_LOGI(TAG,"Partition size - total %d, used %d",total,used);
143 | }
144 |
145 | }
146 |
--------------------------------------------------------------------------------
/FederatedLearningFPGA/output_files/NeuralNetworkFPGA.asm.rpt:
--------------------------------------------------------------------------------
1 | Assembler report for NeuralNetworkFPGA
2 | Fri Dec 13 02:13:27 2024
3 | Quartus Prime Version 23.1std.1 Build 993 05/14/2024 SC Lite Edition
4 |
5 |
6 | ---------------------
7 | ; Table of Contents ;
8 | ---------------------
9 | 1. Legal Notice
10 | 2. Assembler Summary
11 | 3. Assembler Settings
12 | 4. Assembler Generated Files
13 | 5. Assembler Device Options: C:/Development/FederatedEdgeComputing/FederatedLearningFPGA/output_files/NeuralNetworkFPGA.sof
14 | 6. Assembler Messages
15 |
16 |
17 |
18 | ----------------
19 | ; Legal Notice ;
20 | ----------------
21 | Copyright (C) 2024 Intel Corporation. All rights reserved.
22 | Your use of Intel Corporation's design tools, logic functions
23 | and other software and tools, and any partner logic
24 | functions, and any output files from any of the foregoing
25 | (including device programming or simulation files), and any
26 | associated documentation or information are expressly subject
27 | to the terms and conditions of the Intel Program License
28 | Subscription Agreement, the Intel Quartus Prime License Agreement,
29 | the Intel FPGA IP License Agreement, or other applicable license
30 | agreement, including, without limitation, that your use is for
31 | the sole purpose of programming logic devices manufactured by
32 | Intel and sold by Intel or its authorized distributors. Please
33 | refer to the applicable agreement for further details, at
34 | https://fpgasoftware.intel.com/eula.
35 |
36 |
37 |
38 | +---------------------------------------------------------------+
39 | ; Assembler Summary ;
40 | +-----------------------+---------------------------------------+
41 | ; Assembler Status ; Successful - Fri Dec 13 02:13:26 2024 ;
42 | ; Revision Name ; NeuralNetworkFPGA ;
43 | ; Top-level Entity Name ; NeuralNetworkFPGA ;
44 | ; Family ; Cyclone IV E ;
45 | ; Device ; EP4CE115F29C7 ;
46 | +-----------------------+---------------------------------------+
47 |
48 |
49 | +----------------------------------+
50 | ; Assembler Settings ;
51 | +--------+---------+---------------+
52 | ; Option ; Setting ; Default Value ;
53 | +--------+---------+---------------+
54 |
55 |
56 | +------------------------------------------------------------------------------------------------+
57 | ; Assembler Generated Files ;
58 | +------------------------------------------------------------------------------------------------+
59 | ; File Name ;
60 | +------------------------------------------------------------------------------------------------+
61 | ; C:/Development/FederatedEdgeComputing/FederatedLearningFPGA/output_files/NeuralNetworkFPGA.sof ;
62 | +------------------------------------------------------------------------------------------------+
63 |
64 |
65 | +--------------------------------------------------------------------------------------------------------------------------+
66 | ; Assembler Device Options: C:/Development/FederatedEdgeComputing/FederatedLearningFPGA/output_files/NeuralNetworkFPGA.sof ;
67 | +----------------+---------------------------------------------------------------------------------------------------------+
68 | ; Option ; Setting ;
69 | +----------------+---------------------------------------------------------------------------------------------------------+
70 | ; JTAG usercode ; 0x0056533A ;
71 | ; Checksum ; 0x0056533A ;
72 | +----------------+---------------------------------------------------------------------------------------------------------+
73 |
74 |
75 | +--------------------+
76 | ; Assembler Messages ;
77 | +--------------------+
78 | Info: *******************************************************************
79 | Info: Running Quartus Prime Assembler
80 | Info: Version 23.1std.1 Build 993 05/14/2024 SC Lite Edition
81 | Info: Processing started: Fri Dec 13 02:13:23 2024
82 | Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off NeuralNetworkFPGA -c NeuralNetworkFPGA
83 | Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
84 | Info (115031): Writing out detailed assembly data for power analysis
85 | Info (115030): Assembler is generating device programming files
86 | Info: Quartus Prime Assembler was successful. 0 errors, 1 warning
87 | Info: Peak virtual memory: 4706 megabytes
88 | Info: Processing ended: Fri Dec 13 02:13:27 2024
89 | Info: Elapsed time: 00:00:04
90 | Info: Total CPU time (on all processors): 00:00:03
91 |
92 |
93 |
--------------------------------------------------------------------------------
/DeepLearning/dataset/wine/datasetevaluationnormalized.csv:
--------------------------------------------------------------------------------
1 | 15,1.000000,0.262162,0.680000,0.093960,0.413793,0.914894,1.000000,0.212766,1.000000,0.566327,0.911393,0.648855,1.000000,1.000000,0.000000,0.000000
2 | 153,0.566553,0.270270,0.926667,1.000000,0.655172,0.446809,0.250794,0.148936,0.448819,0.525510,0.164557,0.011450,0.107399,0.000000,0.000000,1.000000
3 | 1,0.948805,0.218919,0.713333,0.335570,0.844828,0.702128,0.815873,0.191489,0.736220,0.376531,0.708861,1.000000,0.616547,1.000000,0.000000,0.000000
4 | 167,0.682594,0.756757,0.826667,0.832215,0.568965,0.234043,0.136508,0.510638,0.409449,0.890816,0.468354,0.099237,0.322196,0.000000,0.000000,1.000000
5 | 27,0.662116,0.235135,0.840000,0.369128,0.258621,0.723404,0.777778,0.319149,0.405512,0.290816,0.556962,0.732824,0.719968,1.000000,0.000000,0.000000
6 | 52,0.812287,0.202703,0.826667,0.442953,0.275862,0.553192,0.793651,0.063830,0.736220,0.372449,0.962025,0.790076,0.775656,1.000000,0.000000,0.000000
7 | 132,0.488055,0.564865,0.693333,0.630872,0.448276,0.063830,0.231746,0.106383,0.161417,0.352041,0.329114,0.045802,0.190931,0.000000,0.000000,1.000000
8 | 36,0.692833,0.245946,0.700000,0.664430,0.379310,0.659575,0.790476,0.148936,0.566929,0.321429,0.708861,0.828244,0.501193,1.000000,0.000000,0.000000
9 | 47,1.000000,0.727027,0.613333,0.362416,0.413793,0.893617,0.850794,0.170213,0.696850,0.301020,0.708861,0.816794,0.616547,1.000000,0.000000,0.000000
10 | 101,0.215017,0.318919,0.226667,0.463087,0.327586,0.459574,0.533333,0.148936,0.385827,0.137755,1.000000,0.633588,0.334129,0.000000,1.000000,0.000000
11 | 60,0.313993,0.010811,0.000000,0.000000,0.172414,0.353192,0.025397,0.191489,0.000000,0.000000,0.721519,0.198473,0.182975,0.000000,1.000000,0.000000
12 | 8,0.890785,0.337838,0.833333,0.469799,0.741379,0.617021,0.641270,0.255319,0.326772,0.316327,0.734177,0.870229,0.799523,1.000000,0.000000,0.000000
13 | 133,0.464164,0.381081,0.693333,0.899329,0.344828,0.000000,0.190476,0.170213,0.161417,0.382653,0.227848,0.022901,0.214797,0.000000,0.000000,1.000000
14 | 152,0.457338,0.478378,0.746667,0.765101,0.586207,0.140426,0.276190,0.106383,0.330709,0.903061,0.000000,0.064886,0.151154,0.000000,0.000000,1.000000
15 | 160,0.692833,0.208108,0.853333,0.798658,0.189655,0.617021,0.193651,0.702128,0.736220,1.000000,0.113924,0.183206,0.262530,0.000000,0.000000,1.000000
16 | 129,0.313993,0.197297,0.626667,0.932886,0.172414,0.455319,0.622222,0.446808,0.582677,0.017347,0.518987,0.564885,0.041368,0.000000,1.000000,0.000000
17 | 143,0.706485,0.613514,0.906667,0.865772,0.327586,0.170213,0.009524,0.659574,0.051181,0.244898,0.518987,0.290076,0.182975,0.000000,0.000000,1.000000
18 | 34,0.788396,0.170270,0.893333,0.597315,0.931035,0.765958,0.714286,0.659574,0.366142,0.352041,0.974684,0.648855,0.751790,1.000000,0.000000,0.000000
19 | 150,0.556314,0.810811,0.666667,0.731544,0.603448,0.110638,0.285714,0.319149,0.283465,0.760204,0.113924,0.011450,0.206842,0.000000,0.000000,1.000000
20 | 170,0.665529,1.000000,1.000000,0.966443,0.586207,0.353192,0.149206,0.170213,0.271654,0.668367,0.240506,0.236641,0.270485,0.000000,0.000000,1.000000
21 | 29,0.825939,0.270270,0.960000,0.590604,0.500000,0.765958,0.787302,0.382979,0.527559,0.260204,0.974684,0.801527,0.497216,1.000000,0.000000,0.000000
22 | 48,0.836177,0.210811,0.506667,0.362416,0.396552,0.829787,0.920635,0.042553,0.677165,0.423469,0.544304,0.774809,0.552904,1.000000,0.000000,0.000000
23 | 121,0.000000,0.405405,0.706667,0.630872,0.310345,0.744681,0.730159,0.276596,0.555118,0.132653,0.405063,0.797710,0.266508,0.000000,1.000000,0.000000
24 | 64,0.313993,0.062162,0.533333,0.563758,0.155172,1.000000,0.828571,0.000000,0.570866,0.255102,0.936709,0.599237,0.103421,0.000000,1.000000,0.000000
25 | 106,0.331058,0.445946,0.606667,0.765101,0.206897,0.225532,0.428571,1.000000,0.393701,0.076531,0.481013,0.763359,0.019889,0.000000,1.000000,0.000000
26 | 77,0.539249,0.000000,0.233333,0.362416,0.137931,0.340426,0.488889,0.106383,0.409449,0.270408,0.898734,0.450382,0.081146,0.000000,1.000000,0.000000
27 | 164,0.515358,0.689189,0.660000,0.530201,0.482759,0.102128,0.066667,0.446808,0.204724,0.339796,0.253165,0.171756,0.306285,0.000000,0.000000,1.000000
28 | 104,0.126280,0.221622,0.346667,0.597315,0.137931,0.574468,0.365079,0.382979,0.393701,0.011224,0.582278,0.435115,0.099443,0.000000,1.000000,0.000000
29 | 44,0.610921,0.832432,0.620000,0.463087,0.431034,0.634043,0.679365,0.276596,0.488189,0.245918,0.430380,0.648855,0.310263,1.000000,0.000000,0.000000
30 | 171,0.255973,0.575676,0.640000,0.563758,0.310345,0.042553,0.000000,0.446808,0.122047,0.362245,0.227848,0.202290,0.175020,0.000000,0.000000,1.000000
31 | 94,0.286689,0.521622,0.573333,0.496644,0.172414,0.553192,0.558730,0.127660,0.618110,0.020408,0.848101,0.763359,0.000000,0.000000,1.000000,0.000000
32 | 50,0.849829,0.224324,0.606667,0.456376,0.517241,0.736170,0.968254,0.276596,0.653543,0.709184,0.810127,0.687023,0.771679,1.000000,0.000000,0.000000
33 | 79,0.300341,0.024324,0.393333,0.281879,1.000000,0.319149,0.431746,0.340425,0.921260,0.147959,0.734177,0.385496,0.365951,0.000000,1.000000,0.000000
34 | 68,0.313993,0.072973,0.373333,0.604027,0.000000,0.408511,0.479365,0.170213,0.244094,0.278571,0.810127,0.832061,0.175020,0.000000,1.000000,0.000000
35 | 151,0.699659,0.600000,0.840000,0.899329,0.775862,0.106383,0.342857,0.063830,0.326772,0.678571,0.139240,0.000000,0.167064,0.000000,0.000000,1.000000
36 |
--------------------------------------------------------------------------------
/FederatedLearningFPGA/NeuralNetworkFPGA.qsf:
--------------------------------------------------------------------------------
1 | # -------------------------------------------------------------------------- #
2 | #
3 | # Copyright (C) 2023 Intel Corporation. All rights reserved.
4 | # Your use of Intel Corporation's design tools, logic functions
5 | # and other software and tools, and any partner logic
6 | # functions, and any output files from any of the foregoing
7 | # (including device programming or simulation files), and any
8 | # associated documentation or information are expressly subject
9 | # to the terms and conditions of the Intel Program License
10 | # Subscription Agreement, the Intel Quartus Prime License Agreement,
11 | # the Intel FPGA IP License Agreement, or other applicable license
12 | # agreement, including, without limitation, that your use is for
13 | # the sole purpose of programming logic devices manufactured by
14 | # Intel and sold by Intel or its authorized distributors. Please
15 | # refer to the applicable agreement for further details, at
16 | # https://fpgasoftware.intel.com/eula.
17 | #
18 | # -------------------------------------------------------------------------- #
19 | #
20 | # Quartus Prime
21 | # Version 23.1std.0 Build 991 11/28/2023 SC Lite Edition
22 | # Date created = 23:24:35 May 18, 2024
23 | #
24 | # -------------------------------------------------------------------------- #
25 | #
26 | # Notes:
27 | #
28 | # 1) The default values for assignments are stored in the file:
29 | # NeuralNetworkFPGA_assignment_defaults.qdf
30 | # If this file doesn't exist, see file:
31 | # assignment_defaults.qdf
32 | #
33 | # 2) Intel recommends that you do not modify this file. This
34 | # file is updated automatically by the Quartus Prime software
35 | # and any changes you make may be lost or overwritten.
36 | #
37 | # -------------------------------------------------------------------------- #
38 |
39 |
40 | set_global_assignment -name FAMILY "Cyclone IV E"
41 | set_global_assignment -name DEVICE EP4CE115F29C7
42 | set_global_assignment -name TOP_LEVEL_ENTITY NeuralNetworkFPGA
43 | set_global_assignment -name ORIGINAL_QUARTUS_VERSION 23.1STD.0
44 | set_global_assignment -name PROJECT_CREATION_TIME_DATE "23:24:35 MAY 18, 2024"
45 | set_global_assignment -name LAST_QUARTUS_VERSION "23.1std.1 Lite Edition"
46 | set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
47 | set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
48 | set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
49 | set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
50 | set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
51 | set_global_assignment -name EDA_SIMULATION_TOOL "Questa Intel FPGA (Verilog)"
52 | set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
53 | set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation
54 | set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_timing
55 | set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_symbol
56 | set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_signal_integrity
57 | set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_boundary_scan
58 | set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
59 | set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
60 | set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
61 | set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
62 | set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
63 | set_location_assignment PIN_AG14 -to CLOCK_50
64 | set_location_assignment PIN_G18 -to HEX0[0]
65 | set_location_assignment PIN_F22 -to HEX0[1]
66 | set_location_assignment PIN_E17 -to HEX0[2]
67 | set_location_assignment PIN_L26 -to HEX0[3]
68 | set_location_assignment PIN_L25 -to HEX0[4]
69 | set_location_assignment PIN_J22 -to HEX0[5]
70 | set_location_assignment PIN_H22 -to HEX0[6]
71 | set_location_assignment PIN_M23 -to KEY0
72 | set_location_assignment PIN_AB28 -to SW[0]
73 | set_location_assignment PIN_AC28 -to SW[1]
74 | set_location_assignment PIN_AC27 -to SW[2]
75 | set_location_assignment PIN_AD27 -to SW[3]
76 | set_location_assignment PIN_AB27 -to SW[4]
77 | set_location_assignment PIN_AC26 -to SW[5]
78 | set_location_assignment PIN_AD26 -to SW[6]
79 | set_location_assignment PIN_AB26 -to SW[7]
80 | set_location_assignment PIN_AC25 -to SW[8]
81 | set_location_assignment PIN_AB25 -to SW[9]
82 | set_location_assignment PIN_AC24 -to SW[10]
83 | set_location_assignment PIN_AB24 -to SW[11]
84 | set_location_assignment PIN_AB23 -to SW[12]
85 | set_location_assignment PIN_AA24 -to SW[13]
86 | set_location_assignment PIN_AA23 -to SW[14]
87 | set_location_assignment PIN_AA22 -to SW[15]
88 | set_location_assignment PIN_Y24 -to SW[16]
89 | set_location_assignment PIN_Y23 -to SW[17]
90 | set_location_assignment PIN_AA14 -to HEX7[6]
91 | set_location_assignment PIN_AG18 -to HEX7[5]
92 | set_location_assignment PIN_AG17 -to HEX7[2]
93 | set_location_assignment PIN_AH17 -to HEX7[3]
94 | set_location_assignment PIN_AF17 -to HEX7[4]
95 | set_location_assignment PIN_AD17 -to HEX7[0]
96 | set_location_assignment PIN_AE17 -to HEX7[1]
97 | set_global_assignment -name VERILOG_FILE neuron.v
98 | set_global_assignment -name VERILOG_FILE miscellaneous.v
99 | set_global_assignment -name VERILOG_FILE layer.v
100 | set_global_assignment -name VERILOG_FILE alu.v
101 | set_global_assignment -name VERILOG_FILE NeuralNetworkFPGA.v
102 | set_global_assignment -name VERILOG_FILE output_files/Processor.v
103 | set_global_assignment -name VERILOG_FILE output_files/NeuralNetwork.v
104 | set_global_assignment -name VERILOG_FILE ieee745ALU.v
105 | set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
--------------------------------------------------------------------------------
/FederatedLearningFPGA/layer.v:
--------------------------------------------------------------------------------
1 | module input_layer #(
2 | parameter NUM_NEURONS = 4
3 | ) (
4 | input clock,
5 | input [(32*NUM_NEURONS)-1:0] input_layer,
6 | input layer_enable,
7 | output [(32*NUM_NEURONS)-1:0] output_layer
8 | );
9 |
10 | input_neuron n0 (
11 | .inputdata(input_layer[31:0]),
12 | .clock(clock),
13 | .neuron_enable(layer_enable),
14 | .outputdata(output_layer[31:0])
15 | );
16 |
17 | input_neuron n1 (
18 | .inputdata(input_layer[63:32]),
19 | .clock(clock),
20 | .neuron_enable(layer_enable),
21 | .outputdata(output_layer[63:32])
22 | );
23 |
24 | input_neuron n2 (
25 | .inputdata(input_layer[95:64]),
26 | .clock(clock),
27 | .neuron_enable(layer_enable),
28 | .outputdata(output_layer[95:64])
29 | );
30 |
31 | input_neuron n3 (
32 | .inputdata(input_layer[127:96]),
33 | .clock(clock),
34 | .neuron_enable(layer_enable),
35 | .outputdata(output_layer[127:96])
36 | );
37 |
38 | endmodule
39 |
40 | module hidden_layer #(
41 | parameter NUM_NEURONS = 4
42 | ) (
43 | input clock,
44 | input layer_enable,
45 | input [31:0] alpha,
46 | input [(32*NUM_NEURONS)-1:0] input_layer,
47 | input [$clog2(NUM_NEURONS)-1:0] weight_memory_address,
48 | input [1:0] layer_state,
49 | input [(32*NUM_NEURONS)-1:0] deltafunctions_value,
50 | output [(32*NUM_NEURONS)-1:0] neurons_weight,
51 | output [(32*NUM_NEURONS)-1:0] output_layer
52 | );
53 |
54 | hidden_neuron #(
55 | .NUM_INPUTS(4)
56 | ) n0 (
57 | .clock(clock),
58 | .neuron_enable(layer_enable),
59 | .inputdata(input_layer),
60 | .alpha(alpha),
61 | .deltafunction_value(deltafunctions_value[31:0]),
62 | .weight_memory_address(weight_memory_address),
63 | .neuron_state(layer_state),
64 | .weight(neurons_weight[31:0]),
65 | .a(output_layer[31:0])
66 | );
67 |
68 | hidden_neuron #(
69 | .NUM_INPUTS(4)
70 | ) n1 (
71 | .clock(clock),
72 | .neuron_enable(layer_enable),
73 | .inputdata(input_layer),
74 | .alpha(alpha),
75 | .deltafunction_value(deltafunctions_value[63:32]),
76 | .weight_memory_address(weight_memory_address),
77 | .neuron_state(layer_state),
78 | .weight(neurons_weight[63:32]),
79 | .a(output_layer[63:32])
80 | );
81 |
82 | hidden_neuron #(
83 | .NUM_INPUTS(4)
84 | ) n2 (
85 | .clock(clock),
86 | .neuron_enable(layer_enable),
87 | .inputdata(input_layer),
88 | .alpha(alpha),
89 | .deltafunction_value(deltafunctions_value[95:64]),
90 | .weight_memory_address(weight_memory_address),
91 | .neuron_state(layer_state),
92 | .weight(neurons_weight[95:64]),
93 | .a(output_layer[95:64])
94 | );
95 |
96 | endmodule
97 |
98 | module output_softmax_layer #(
99 | parameter NUM_NEURONS = 4
100 | )(
101 | input clock,
102 | input layer_enable,
103 | input [31:0] alpha,
104 | input [(32*NUM_NEURONS)-1:0] input_layer,
105 |
106 | input [$clog2(NUM_NEURONS)-1:0] weight_memory_address,
107 | input [(32*NUM_NEURONS)-1:0] deltafunctions_value,
108 | input [1:0] layer_state,
109 | output [(32*NUM_NEURONS)-1:0] neurons_weight,
110 | output [(32*NUM_NEURONS)-1:0] output_layer
111 | );
112 |
113 | wire [31:0] ss_n, ns1_ss,ns2_ss,ns3_ss;
114 |
115 | softmax_sum #(.NUM_INPUTS(4)) ss (
116 |
117 | .input_data({ns3_ss,ns2_ss,ns1_ss,32'h00000000}),
118 | .output_data(ss_n)
119 |
120 | );
121 |
122 | softmax_neuron #(.NUM_INPUTS(4)) sn1 (
123 |
124 | .clock(clock),
125 | .neuron_enable(layer_enable),
126 | .alpha(alpha),
127 | .inputdata(input_layer),
128 | .exp_sum(ss_n),
129 |
130 | .deltafunction_value(deltafunctions_value[31:0]),
131 | .weight_memory_address(weight_memory_address),
132 | .neuron_state(layer_state),
133 |
134 | .exp(ns1_ss),
135 | .weight(neurons_weight[31:0]),
136 | .a(output_layer[31:0])
137 |
138 | );
139 |
140 | softmax_neuron #(.NUM_INPUTS(4)) sn2 (
141 |
142 | .clock(clock),
143 | .neuron_enable(layer_enable),
144 | .alpha(alpha),
145 | .inputdata(input_layer),
146 | .exp_sum(ss_n),
147 |
148 | .deltafunction_value(deltafunctions_value[63:32]),
149 | .weight_memory_address(weight_memory_address),
150 | .neuron_state(layer_state),
151 |
152 | .exp(ns2_ss),
153 | .weight(neurons_weight[63:32]),
154 | .a(output_layer[63:32])
155 |
156 | );
157 |
158 | softmax_neuron #(.NUM_INPUTS(4)) sn3 (
159 |
160 | .clock(clock),
161 | .neuron_enable(layer_enable),
162 | .alpha(alpha),
163 | .inputdata(input_layer),
164 | .exp_sum(ss_n),
165 |
166 | .deltafunction_value(deltafunctions_value[95:64]),
167 | .weight_memory_address(weight_memory_address),
168 | .neuron_state(layer_state),
169 |
170 | .exp(ns3_ss),
171 | .weight(neurons_weight[95:64]),
172 | .a(output_layer[95:64])
173 | );
174 |
175 | endmodule
176 |
177 | module layer_control #(parameter
178 | MAX_NUM_NEURONS = 4,
179 | NUM_LAYERS = 4
180 | ) (
181 |
182 | input clock,
183 | input [(32*MAX_NUM_NEURONS)-1:0] neurons_weight,
184 | input [(32*MAX_NUM_NEURONS)-1:0] output_sofmax_layer,
185 | output reg [$clog2(MAX_NUM_NEURONS)-1:0] weight_memory_address,
186 | output reg [1:0] layer_state,
187 | output reg [NUM_LAYERS-1:0] enable_layers,
188 | output reg [(32*MAX_NUM_NEURONS)-1:0] deltafunction
189 | );
190 |
191 |
192 | // always @(*) begin
193 |
194 | // end
195 |
196 |
197 | endmodule
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