├── .gitattributes ├── README.md ├── analysis ├── LPF.fda ├── LPF.m ├── ReadFPGAdata.m ├── TwoComplement.m ├── coef.mat ├── databin.mem ├── databin.txt ├── datain.txt ├── main.m └── point2bin.m └── project ├── FirDesign.gise ├── FirDesign.xise ├── _xmsgs ├── pn_parser.xmsgs └── xst.xmsgs ├── dataout.txt ├── fir.cmd_log ├── fir.lso ├── fir.ngc ├── fir.ngr ├── fir.prj ├── fir.stx ├── fir.syr ├── fir.v ├── fir.xst ├── fir_envsettings.html ├── fir_isim_beh.exe ├── fir_summary.html ├── fir_tb.v ├── fir_tb_beh.prj ├── fir_tb_isim_beh.exe ├── fir_tb_isim_beh.wdb ├── fir_tb_isim_beh1.wdb ├── fir_tb_stx_beh.prj ├── fir_xst.xrpt ├── fuse.log ├── fuse.xmsgs ├── fuseRelaunch.cmd ├── iseconfig ├── FirDesign.projectmgr └── fir.xreport ├── isim.cmd ├── isim.log ├── isim ├── fir_tb_isim_beh.exe.sim │ ├── ISimEngine-DesignHierarchy.dbg │ ├── fir_tb_isim_beh.exe │ ├── isimcrash.log │ ├── isimkernel.log │ ├── libPortability.dll │ ├── netId.dat │ ├── tmp_save │ │ └── _1 │ └── work │ │ ├── fir_tb_isim_beh.exe_main.c │ │ ├── fir_tb_isim_beh.exe_main.nt64.obj │ │ ├── m_00000000000044543037_3538921338.c │ │ ├── m_00000000000044543037_3538921338.didat │ │ ├── m_00000000000044543037_3538921338.nt64.obj │ │ ├── m_00000000000407611705_1143523637.c │ │ ├── m_00000000000407611705_1143523637.didat │ │ ├── m_00000000000407611705_1143523637.nt64.obj │ │ ├── m_00000000004134447467_2073120511.c │ │ ├── m_00000000004134447467_2073120511.didat │ │ └── m_00000000004134447467_2073120511.nt64.obj ├── isim_usage_statistics.html ├── pn_info ├── temp │ ├── fir.sdb │ ├── fir_tb.sdb │ └── glbl.sdb └── work │ ├── fir.sdb │ ├── fir_tb.sdb │ └── glbl.sdb ├── result.wcfg ├── webtalk_pn.xml ├── xilinxsim.ini └── xst └── work ├── hdllib.ref └── vlg75 └── fir.bin /.gitattributes: -------------------------------------------------------------------------------- 1 | *.v linguist-language=Verilog 2 | *.c linguist-language=Verilog 3 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # Overview 2 | **FIR implement in Verilog** 3 | 4 | FIR implement in Verilog, all files in this repo associated with `./analysis`. 5 | 6 | - tools : xilinx ise14.7 7 | 8 | - key files : fir.v and fir_tb.v 9 | 10 | **FIR analysis using Matlab** 11 | 12 | FIR analysis using Matlab, including fixed-point and float-point domain , and deal with physical FIR output data. And analysis verilog simulation output through import test bench output. 13 | 14 | **Directory description** 15 | 16 | ``` 17 | Verilog-FIR 18 | ├─analysis: matlab analysis .m file 19 | └─project: ise project 20 | ``` 21 | 22 | -------------------------------------------------------------------------------- /analysis/LPF.fda: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Grootzz/Verilog-FIR/3b332498ee356fe0e0a0554d3ca5f483909b4b05/analysis/LPF.fda -------------------------------------------------------------------------------- /analysis/LPF.m: -------------------------------------------------------------------------------- 1 | function Hd = LPF 2 | %LPF Returns a discrete-time filter object. 3 | 4 | % MATLAB Code 5 | % Generated by MATLAB(R) 9.2 and the DSP System Toolbox 9.4. 6 | % Generated on: 02-Aug-2017 13:23:03 7 | 8 | % Equiripple Lowpass filter designed using the FIRPM function. 9 | 10 | % All frequency values are normalized to 1. 11 | 12 | Fpass = 0.1; % Passband Frequency 13 | Fstop = 0.4; % Stopband Frequency 14 | Dpass = 0.057501127785; % Passband Ripple 15 | Dstop = 0.0001; % Stopband Attenuation 16 | dens = 20; % Density Factor 17 | 18 | % Calculate the order from the parameters using FIRPMORD. 19 | [N, Fo, Ao, W] = firpmord([Fpass, Fstop], [1 0], [Dpass, Dstop]); 20 | 21 | % Calculate the coefficients using the FIRPM function. 22 | b = firpm(N, Fo, Ao, W, {dens}); 23 | Hd = dfilt.dffir(b); 24 | 25 | % [EOF] 26 | -------------------------------------------------------------------------------- /analysis/ReadFPGAdata.m: -------------------------------------------------------------------------------- 1 | % read data solved by physical FIR 2 | % dataout.txt is the read object 3 | fid = fopen('E:\ISEProjece\FirDesign\dataout.txt'); 4 | fpga_data = textscan(fid, '%d'); 5 | fclose(fid); 6 | 7 | subplot(211); 8 | % begin output is 0 ,because use 5-level pipeline in physical FIR 9 | plot(fpga_data{1}(6:end));xlabel('The resule of physical FIR'); 10 | 11 | subplot(212); 12 | plot(result_scale);xlabel('The resule of simulation in matlab'); 13 | 14 | fprintf('eror (sum of squared) between simulation and physical fir is : %d \n' , sumsqr(double(fpga_data{1}(6:end)) - result_scale')); 15 | -------------------------------------------------------------------------------- /analysis/TwoComplement.m: -------------------------------------------------------------------------------- 1 | % transforminteger number (including positive and negaitive) to Two complement 2 | 3 | WIDTH = 16; 4 | 5 | signal_trans2c = dec2bin(signal_scale + 2^WIDTH * (signal_scale<0) , WIDTH); 6 | 7 | signal_trans2c = signal_trans2c'; 8 | fdata = fopen('databin.mem' , 'wb'); 9 | 10 | for index = 1:length(signal_scale) 11 | for i = 1:WIDTH 12 | fprintf( fdata ,'%s' , signal_trans2c((index-1) * WIDTH + i)); 13 | end 14 | fprintf(fdata , '\r\n'); % entering a enter and new a line 15 | end 16 | fclose(fdata); -------------------------------------------------------------------------------- /analysis/coef.mat: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Grootzz/Verilog-FIR/3b332498ee356fe0e0a0554d3ca5f483909b4b05/analysis/coef.mat -------------------------------------------------------------------------------- /analysis/databin.mem: -------------------------------------------------------------------------------- 1 | 0000000000000000 2 | 0011100101100101 3 | 1110100011000000 4 | 0111000010100101 5 | 0001011101000000 6 | 0100000000000000 7 | 0110001001111100 8 | 1111011011101001 9 | 0110001001111100 10 | 1110111000101001 11 | 0000000000000000 12 | 0001000111010111 13 | 1001110110000100 14 | 0000100100010111 15 | 1001110110000100 16 | 1100000000000000 17 | 1110100011000000 18 | 1000111101011011 19 | 0001011101000000 20 | 1100011010011011 21 | 0000000000000000 22 | 0011100101100101 23 | 1110100011000000 24 | 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1100011010011011 201 | 0000000000000000 202 | 0011100101100101 203 | 1110100011000000 204 | 0111000010100101 205 | 0001011101000000 206 | 0100000000000000 207 | 0110001001111100 208 | 1111011011101001 209 | 0110001001111100 210 | 1110111000101001 211 | 0000000000000000 212 | 0001000111010111 213 | 1001110110000100 214 | 0000100100010111 215 | 1001110110000100 216 | 1100000000000000 217 | 1110100011000000 218 | 1000111101011011 219 | 0001011101000000 220 | 1100011010011011 221 | 0000000000000000 222 | 0011100101100101 223 | 1110100011000000 224 | 0111000010100101 225 | 0001011101000000 226 | 0100000000000000 227 | 0110001001111100 228 | 1111011011101001 229 | 0110001001111100 230 | 1110111000101001 231 | 0000000000000000 232 | 0001000111010111 233 | 1001110110000100 234 | 0000100100010111 235 | 1001110110000100 236 | 1100000000000000 237 | 1110100011000000 238 | 1000111101011011 239 | 0001011101000000 240 | 1100011010011011 241 | 0000000000000000 242 | -------------------------------------------------------------------------------- /analysis/databin.txt: -------------------------------------------------------------------------------- 1 | 0 2 | 14693 3 | -5952 4 | 28837 5 | 5952 6 | 16384 7 | 25212 8 | -2327 9 | 25212 10 | -4567 11 | -0 12 | 4567 13 | -25212 14 | 2327 15 | -25212 16 | -16384 17 | -5952 18 | -28837 19 | 5952 20 | -14693 21 | -0 22 | 14693 23 | -5952 24 | 28837 25 | 5952 26 | 16384 27 | 25212 28 | -2327 29 | 25212 30 | -4567 31 | -0 32 | 4567 33 | -25212 34 | 2327 35 | -25212 36 | -16384 37 | -5952 38 | -28837 39 | 5952 40 | -14693 41 | -0 42 | 14693 43 | -5952 44 | 28837 45 | 5952 46 | 16384 47 | 25212 48 | -2327 49 | 25212 50 | -4567 51 | -0 52 | 4567 53 | -25212 54 | 2327 55 | -25212 56 | -16384 57 | -5952 58 | -28837 59 | 5952 60 | -14693 61 | -0 62 | 14693 63 | -5952 64 | 28837 65 | 5952 66 | 16384 67 | 25212 68 | -2327 69 | 25212 70 | -4567 71 | -0 72 | 4567 73 | -25212 74 | 2327 75 | -25212 76 | -16384 77 | -5952 78 | -28837 79 | 5952 80 | -14693 81 | -0 82 | 14693 83 | -5952 84 | 28837 85 | 5952 86 | 16384 87 | 25212 88 | -2327 89 | 25212 90 | -4567 91 | -0 92 | 4567 93 | -25212 94 | 2327 95 | -25212 96 | -16384 97 | -5952 98 | -28837 99 | 5952 100 | -14693 101 | -0 102 | 14693 103 | -5952 104 | 28837 105 | 5952 106 | 16384 107 | 25212 108 | -2327 109 | 25212 110 | -4567 111 | -0 112 | 4567 113 | -25212 114 | 2327 115 | -25212 116 | -16384 117 | -5952 118 | -28837 119 | 5952 120 | -14693 121 | -0 122 | 14693 123 | -5952 124 | 28837 125 | 5952 126 | 16384 127 | 25212 128 | -2327 129 | 25212 130 | -4567 131 | 0 132 | 4567 133 | -25212 134 | 2327 135 | -25212 136 | -16384 137 | -5952 138 | -28837 139 | 5952 140 | -14693 141 | -0 142 | 14693 143 | -5952 144 | 28837 145 | 5952 146 | 16384 147 | 25212 148 | -2327 149 | 25212 150 | -4567 151 | 0 152 | 4567 153 | -25212 154 | 2327 155 | -25212 156 | -16384 157 | -5952 158 | -28837 159 | 5952 160 | -14693 161 | -0 162 | 14693 163 | -5952 164 | 28837 165 | 5952 166 | 16384 167 | 25212 168 | -2327 169 | 25212 170 | -4567 171 | 0 172 | 4567 173 | -25212 174 | 2327 175 | -25212 176 | -16384 177 | -5952 178 | -28837 179 | 5952 180 | -14693 181 | -0 182 | 14693 183 | -5952 184 | 28837 185 | 5952 186 | 16384 187 | 25212 188 | -2327 189 | 25212 190 | -4567 191 | 0 192 | 4567 193 | -25212 194 | 2327 195 | -25212 196 | -16384 197 | -5952 198 | -28837 199 | 5952 200 | -14693 201 | -0 202 | 14693 203 | -5952 204 | 28837 205 | 5952 206 | 16384 207 | 25212 208 | -2327 209 | 25212 210 | -4567 211 | 0 212 | 4567 213 | -25212 214 | 2327 215 | -25212 216 | -16384 217 | -5952 218 | -28837 219 | 5952 220 | -14693 221 | -0 222 | 14693 223 | -5952 224 | 28837 225 | 5952 226 | 16384 227 | 25212 228 | -2327 229 | 25212 230 | -4567 231 | 0 232 | 4567 233 | -25212 234 | 2327 235 | -25212 236 | -16384 237 | -5952 238 | -28837 239 | 5952 240 | -14693 241 | -0 242 | -------------------------------------------------------------------------------- /analysis/datain.txt: -------------------------------------------------------------------------------- 1 | 0 2 | 14693 3 | -5952 4 | 28837 5 | 5952 6 | 16384 7 | 25212 8 | -2327 9 | 25212 10 | -4567 11 | -0 12 | 4567 13 | -25212 14 | 2327 15 | -25212 16 | -16384 17 | -5952 18 | -28837 19 | 5952 20 | -14693 21 | -0 22 | 14693 23 | -5952 24 | 28837 25 | 5952 26 | 16384 27 | 25212 28 | -2327 29 | 25212 30 | -4567 31 | -0 32 | 4567 33 | -25212 34 | 2327 35 | -25212 36 | -16384 37 | -5952 38 | -28837 39 | 5952 40 | -14693 41 | -0 42 | 14693 43 | -5952 44 | 28837 45 | 5952 46 | 16384 47 | 25212 48 | -2327 49 | 25212 50 | -4567 51 | -0 52 | 4567 53 | -25212 54 | 2327 55 | -25212 56 | -16384 57 | -5952 58 | -28837 59 | 5952 60 | -14693 61 | -0 62 | 14693 63 | -5952 64 | 28837 65 | 5952 66 | 16384 67 | 25212 68 | -2327 69 | 25212 70 | -4567 71 | -0 72 | 4567 73 | -25212 74 | 2327 75 | -25212 76 | -16384 77 | -5952 78 | -28837 79 | 5952 80 | -14693 81 | -0 82 | 14693 83 | -5952 84 | 28837 85 | 5952 86 | 16384 87 | 25212 88 | -2327 89 | 25212 90 | -4567 91 | -0 92 | 4567 93 | -25212 94 | 2327 95 | -25212 96 | -16384 97 | -5952 98 | -28837 99 | 5952 100 | -14693 101 | -0 102 | 14693 103 | -5952 104 | 28837 105 | 5952 106 | 16384 107 | 25212 108 | -2327 109 | 25212 110 | -4567 111 | -0 112 | 4567 113 | -25212 114 | 2327 115 | -25212 116 | -16384 117 | -5952 118 | -28837 119 | 5952 120 | -14693 121 | -0 122 | 14693 123 | -5952 124 | 28837 125 | 5952 126 | 16384 127 | 25212 128 | -2327 129 | 25212 130 | -4567 131 | 0 132 | 4567 133 | -25212 134 | 2327 135 | -25212 136 | -16384 137 | -5952 138 | -28837 139 | 5952 140 | -14693 141 | -0 142 | 14693 143 | -5952 144 | 28837 145 | 5952 146 | 16384 147 | 25212 148 | -2327 149 | 25212 150 | -4567 151 | 0 152 | 4567 153 | -25212 154 | 2327 155 | -25212 156 | -16384 157 | -5952 158 | -28837 159 | 5952 160 | -14693 161 | -0 162 | 14693 163 | -5952 164 | 28837 165 | 5952 166 | 16384 167 | 25212 168 | -2327 169 | 25212 170 | -4567 171 | 0 172 | 4567 173 | -25212 174 | 2327 175 | -25212 176 | -16384 177 | -5952 178 | -28837 179 | 5952 180 | -14693 181 | -0 182 | 14693 183 | -5952 184 | 28837 185 | 5952 186 | 16384 187 | 25212 188 | -2327 189 | 25212 190 | -4567 191 | 0 192 | 4567 193 | -25212 194 | 2327 195 | -25212 196 | -16384 197 | -5952 198 | -28837 199 | 5952 200 | -14693 201 | -0 202 | 14693 203 | -5952 204 | 28837 205 | 5952 206 | 16384 207 | 25212 208 | -2327 209 | 25212 210 | -4567 211 | 0 212 | 4567 213 | -25212 214 | 2327 215 | -25212 216 | -16384 217 | -5952 218 | -28837 219 | 5952 220 | -14693 221 | -0 222 | 14693 223 | -5952 224 | 28837 225 | 5952 226 | 16384 227 | 25212 228 | -2327 229 | 25212 230 | -4567 231 | 0 232 | 4567 233 | -25212 234 | 2327 235 | -25212 236 | -16384 237 | -5952 238 | -28837 239 | 5952 240 | -14693 241 | -0 242 | -------------------------------------------------------------------------------- /analysis/main.m: -------------------------------------------------------------------------------- 1 | % analysis of floating-point domain and fixed-point for FIR 2 | % FIR coef stem from FilterDesigner tool 3 | % floating-point conversion to fixed-point 4 | 5 | clc ,clear, close all; 6 | fs = 48000; % simpling frequency 7 | fpass = 2400; 8 | fstop = 9600; 9 | t = 0:1/fs:0.005; % 0.005 s signal 10 | signal = sin(2*pi*fpass*t) + sin(2*pi*2*fstop*t); 11 | 12 | figure(1),subplot(2,1,1); 13 | plot(t , signal);xlabel('signal with noise'); 14 | 15 | re_signal = filter(LPF , signal); 16 | subplot(2,1,2); 17 | plot(t,re_signal);xlabel('filtered signal without noise'); 18 | 19 | % floating-point conversion to fixed-point 20 | % filter coefficients 21 | coefStruct = load('coef'); 22 | coef = coefStruct.Num; 23 | % define input word length and determined the scaling length 24 | WL = 16;% input word length 25 | IN_SCALE = 14;% input scaling length 26 | COEF_SCALE = 16;% coefficients scaling length 27 | 28 | % quantize 29 | signal_scale = round(signal * 2^IN_SCALE); 30 | coef_scale = round(coef * 2^COEF_SCALE); 31 | result_scale = filter(coef_scale , 1 , signal_scale);% filtering signal 32 | 33 | err_signal = signal_scale * 2^(-IN_SCALE) - signal; 34 | err_coef = coef_scale * 2^(-COEF_SCALE) - coef; 35 | 36 | % de-scale result_scale 37 | result_approximate = result_scale * 2^(-(IN_SCALE + COEF_SCALE)); 38 | fprintf('error of scaleing signal and the law singal : %d\n' , sumsqr(result_approximate-re_signal)); 39 | 40 | figure(2); 41 | subplot(211);plot(t , err_signal); xlabel(['quantized err of signal,','sumsqr:',num2str(sumsqr(err_signal))]); 42 | subplot(212);plot(0:length(coef)-1 , err_coef);xlabel(['quantized err of coef,','sumsqr:',num2str(sumsqr(err_coef))]); 43 | 44 | figure(3); 45 | subplot(211);plot(t,signal_scale);xlabel('scaled signal input'); 46 | subplot(212);plot(t,result_scale);xlabel('scaled filter output'); 47 | 48 | figure(4); 49 | plot(t , result_approximate-re_signal);xlabel('Error of between fixed-output and float-output'); 50 | 51 | f = fopen('databin.txt' , 'w'); 52 | fprintf(f ,'%g\n' , signal_scale'); 53 | fclose(f); 54 | -------------------------------------------------------------------------------- /analysis/point2bin.m: -------------------------------------------------------------------------------- 1 | WIDTH = 16; 2 | 3 | signal_trans2c = dec2bin(signal_scale + 2^WIDTH * (signal_scale<0) , WIDTH); 4 | 5 | signal_trans2c = signal_trans2c'; 6 | fdata = fopen('databin.mem' , 'wb'); 7 | 8 | for index = 1:length(signal_scale) 9 | for i = 1:WIDTH 10 | fprintf( fdata ,'%s' , signal_trans2c((index-1) * WIDTH + i)); 11 | end 12 | fprintf(fdata , '\r\n'); % entering a enter and new a line 13 | end 14 | fclose(fdata); -------------------------------------------------------------------------------- /project/FirDesign.gise: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 11.1 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 | 39 | 40 | 41 | 42 | 43 | 44 | 45 | 46 | 47 | 48 | 49 | 50 | 51 | 52 | 53 | 54 | 55 | 56 | 57 | 58 | 59 | 60 | 61 | 62 | 63 | 64 | 65 | 66 | 67 | 68 | 69 | 70 | 71 | 72 | 73 | 74 | 75 | 76 | 77 | 78 | 79 | 80 | 81 | 82 | 83 | 84 | 85 | 86 | 87 | 88 | 89 | 90 | 91 | 92 | 93 | 94 | 95 | 96 | 97 | 98 | 99 | 100 | 101 | 102 | 103 | 104 | 105 | 106 | 107 | 108 | 109 | 110 | 111 | 112 | 113 | 114 | 115 | 116 | 117 | 118 | 119 | 120 | 121 | 122 | 123 | 124 | 125 | 126 | 127 | 128 | 129 | 130 | 131 | 132 | 133 | 134 | 135 | 136 | 137 | 138 | 139 | 140 | 141 | 142 | 143 | 144 | 145 | 146 | 147 | 148 | 149 | 150 | 151 | 152 | 153 | 154 | 155 | 156 | 157 | 158 | 159 | 160 | 161 | 162 | 163 | 164 | 165 | 166 | 167 | -------------------------------------------------------------------------------- /project/FirDesign.xise: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 |
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14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 | 39 | 40 | 41 | 42 | 43 | 44 | 45 | 46 | 47 | 48 | 49 | 50 | 51 | 52 | 53 | 54 | 55 | 56 | 57 | 58 | 59 | 60 | 61 | 62 | 63 | 64 | 65 | 66 | 67 | 68 | 69 | 70 | 71 | 72 | 73 | 74 | 75 | 76 | 77 | 78 | 79 | 80 | 81 | 82 | 83 | 84 | 85 | 86 | 87 | 88 | 89 | 90 | 91 | 92 | 93 | 94 | 95 | 96 | 97 | 98 | 99 | 100 | 101 | 102 | 103 | 104 | 105 | 106 | 107 | 108 | 109 | 110 | 111 | 112 | 113 | 114 | 115 | 116 | 117 | 118 | 119 | 120 | 121 | 122 | 123 | 124 | 125 | 126 | 127 | 128 | 129 | 130 | 131 | 132 | 133 | 134 | 135 | 136 | 137 | 138 | 139 | 140 | 141 | 142 | 143 | 144 | 145 | 146 | 147 | 148 | 149 | 150 | 151 | 152 | 153 | 154 | 155 | 156 | 157 | 158 | 159 | 160 | 161 | 162 | 163 | 164 | 165 | 166 | 167 | 168 | 169 | 170 | 171 | 172 | 173 | 174 | 175 | 176 | 177 | 178 | 179 | 180 | 181 | 182 | 183 | 184 | 185 | 186 | 187 | 188 | 189 | 190 | 191 | 192 | 193 | 194 | 195 | 196 | 197 | 198 | 199 | 200 | 201 | 202 | 203 | 204 | 205 | 206 | 207 | 208 | 209 | 210 | 211 | 212 | 213 | 214 | 215 | 216 | 217 | 218 | 219 | 220 | 221 | 222 | 223 | 224 | 225 | 226 | 227 | 228 | 229 | 230 | 231 | 232 | 233 | 234 | 235 | 236 | 237 | 238 | 239 | 240 | 241 | 242 | 243 | 244 | 245 | 246 | 247 | 248 | 249 | 250 | 251 | 252 | 253 | 254 | 255 | 256 | 257 | 258 | 259 | 260 | 261 | 262 | 263 | 264 | 265 | 266 | 267 | 268 | 269 | 270 | 271 | 272 | 273 | 274 | 275 | 276 | 277 | 278 | 279 | 280 | 281 | 282 | 283 | 284 | 285 | 286 | 287 | 288 | 289 | 290 | 291 | 292 | 293 | 294 | 295 | 296 | 297 | 298 | 299 | 300 | 301 | 302 | 303 | 304 | 305 | 306 | 307 | 308 | 309 | 310 | 311 | 312 | 313 | 314 | 315 | 316 | 317 | 318 | 319 | 320 | 321 | 322 | 323 | 324 | 325 | 326 | 327 | 328 | 329 | 330 | 331 | 332 | 333 | 334 | 335 | 336 | 337 | 338 | 339 | 340 | 341 | 342 | 343 | 344 | 345 | 346 | 347 | 348 | 349 | 350 | 351 | 352 | 353 | 354 | 355 | 356 | 357 | 358 | 359 | 360 | 361 | 362 | 363 | 364 | 365 | 366 | 367 | 368 | 369 | -------------------------------------------------------------------------------- /project/_xmsgs/pn_parser.xmsgs: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | Analyzing Verilog file "E:/ISEProjece/FirDesign/fir.v" into library work 12 | 13 | 14 | Analyzing Verilog file "E:/ISEProjece/FirDesign/fir_tb.v" into library work 15 | 16 | 17 | 18 | 19 | -------------------------------------------------------------------------------- /project/_xmsgs/xst.xmsgs: -------------------------------------------------------------------------------- 1 | 2 | 7 | 8 | "fir.v" line 170: One or more signals are missing in the sensitivity list of always block. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are: 9 | <rst> 10 | 11 | 12 | HDL ADVISOR - 272 flip-flops were inferred for signal <delay_pipeline>. You may be trying to describe a RAM in a way that is incompatible with block and distributed RAM resources available on Xilinx devices, or with a specific template that is not supported. Please review the Xilinx resources documentation and the XST user manual for coding guidelines. Taking advantage of RAM resources will lead to improved device usage and reduced synthesis time. 13 | 14 | 15 | HDL ADVISOR - 544 flip-flops were inferred for signal <product>. You may be trying to describe a RAM in a way that is incompatible with block and distributed RAM resources available on Xilinx devices, or with a specific template that is not supported. Please review the Xilinx resources documentation and the XST user manual for coding guidelines. Taking advantage of RAM resources will lead to improved device usage and reduced synthesis time. 16 | 17 | 18 | The FF/Latch <product_9_30> in Unit <fir> is equivalent to the following FF/Latch, which will be removed : <product_9_31> 19 | 20 | 21 | The FF/Latch <product_10_30> in Unit <fir> is equivalent to the following FF/Latch, which will be removed : <product_10_31> 22 | 23 | 24 | The FF/Latch <product_6_30> in Unit <fir> is equivalent to the following FF/Latch, which will be removed : <product_6_31> 25 | 26 | 27 | The FF/Latch <product_5_29> in Unit <fir> is equivalent to the following 2 FFs/Latches, which will be removed : <product_5_30> <product_5_31> 28 | 29 | 30 | The FF/Latch <product_0_21> in Unit <fir> is equivalent to the following 10 FFs/Latches, which will be removed : <product_0_22> <product_0_23> <product_0_24> <product_0_25> <product_0_26> <product_0_27> <product_0_28> <product_0_29> <product_0_30> <product_0_31> 31 | 32 | 33 | The FF/Latch <product_14_25> in Unit <fir> is equivalent to the following 6 FFs/Latches, which will be removed : <product_14_26> <product_14_27> <product_14_28> <product_14_29> <product_14_30> <product_14_31> 34 | 35 | 36 | The FF/Latch <product_8_30> in Unit <fir> is equivalent to the following FF/Latch, which will be removed : <product_8_31> 37 | 38 | 39 | The FF/Latch <product_4_28> in Unit <fir> is equivalent to the following 3 FFs/Latches, which will be removed : <product_4_29> <product_4_30> <product_4_31> 40 | 41 | 42 | The FF/Latch <product_13_27> in Unit <fir> is equivalent to the following 4 FFs/Latches, which will be removed : <product_13_28> <product_13_29> <product_13_30> <product_13_31> 43 | 44 | 45 | The FF/Latch <product_2_25> in Unit <fir> is equivalent to the following 6 FFs/Latches, which will be removed : <product_2_26> <product_2_27> <product_2_28> <product_2_29> <product_2_30> <product_2_31> 46 | 47 | 48 | The FF/Latch <product_3_27> in Unit <fir> is equivalent to the following 4 FFs/Latches, which will be removed : <product_3_28> <product_3_29> <product_3_30> <product_3_31> 49 | 50 | 51 | The FF/Latch <product_15_22> in Unit <fir> is equivalent to the following 9 FFs/Latches, which will be removed : <product_15_23> <product_15_24> <product_15_25> <product_15_26> <product_15_27> <product_15_28> <product_15_29> <product_15_30> <product_15_31> 52 | 53 | 54 | The FF/Latch <product_7_30> in Unit <fir> is equivalent to the following FF/Latch, which will be removed : <product_7_31> 55 | 56 | 57 | The FF/Latch <product_16_21> in Unit <fir> is equivalent to the following 10 FFs/Latches, which will be removed : <product_16_22> <product_16_23> <product_16_24> <product_16_25> <product_16_26> <product_16_27> <product_16_28> <product_16_29> <product_16_30> <product_16_31> 58 | 59 | 60 | The FF/Latch <product_1_22> in Unit <fir> is equivalent to the following 9 FFs/Latches, which will be removed : <product_1_23> <product_1_24> <product_1_25> <product_1_26> <product_1_27> <product_1_28> <product_1_29> <product_1_30> <product_1_31> 61 | 62 | 63 | The FF/Latch <product_11_29> in Unit <fir> is equivalent to the following 2 FFs/Latches, which will be removed : <product_11_30> <product_11_31> 64 | 65 | 66 | The FF/Latch <product_12_28> in Unit <fir> is equivalent to the following 3 FFs/Latches, which will be removed : <product_12_29> <product_12_30> <product_12_31> 67 | 68 | 69 | 70 | 71 | -------------------------------------------------------------------------------- /project/dataout.txt: -------------------------------------------------------------------------------- 1 | 0 2 | 0 3 | 0 4 | 0 5 | 0 6 | 0 7 | -249781 8 | 1012150 9 | 5840755 10 | 20747624 11 | 53890635 12 | 114346375 13 | 209673314 14 | 339306784 15 | 494797130 16 | 657147014 17 | 800486271 18 | 898805151 19 | 928946899 20 | 878806721 21 | 746771315 22 | 542375179 23 | 285386772 24 | 0 25 | -285386772 26 | -542375179 27 | -747021096 28 | -877794571 29 | -923106144 30 | -878057527 31 | -746595636 32 | -542800639 33 | -285123816 34 | 0 35 | 285123816 36 | 542800639 37 | 746595636 38 | 878057527 39 | 923106144 40 | 877794571 41 | 747021096 42 | 542375179 43 | 285386772 44 | 0 45 | -285386772 46 | -542375179 47 | -747021096 48 | -877794571 49 | -923106144 50 | -878057527 51 | -746595636 52 | -542800639 53 | -285123816 54 | 0 55 | 285123816 56 | 542800639 57 | 746595636 58 | 878057527 59 | 923106144 60 | 877794571 61 | 747021096 62 | 542375179 63 | 285386772 64 | 0 65 | -285386772 66 | -542375179 67 | -747021096 68 | -877794571 69 | -923106144 70 | -878057527 71 | -746595636 72 | -542800639 73 | -285123816 74 | 0 75 | 285123816 76 | 542800639 77 | 746595636 78 | 878057527 79 | 923106144 80 | 877794571 81 | 747021096 82 | 542375179 83 | 285386772 84 | 0 85 | -285386772 86 | -542375179 87 | -747021096 88 | -877794571 89 | -923106144 90 | -878057527 91 | -746595636 92 | -542800639 93 | -285123816 94 | 0 95 | 285123816 96 | 542800639 97 | 746595636 98 | 878057527 99 | 923106144 100 | 877794571 101 | 747021096 102 | 542375179 103 | 285386772 104 | 0 105 | -285386772 106 | -542375179 107 | -747021096 108 | -877794571 109 | -923106144 110 | -878057527 111 | -746595636 112 | -542800639 113 | -285123816 114 | 0 115 | 285123816 116 | 542800639 117 | 746595636 118 | 878057527 119 | 923106144 120 | 877794571 121 | 747021096 122 | 542375179 123 | 285386772 124 | 0 125 | -285386772 126 | -542375179 127 | -747021096 128 | -877794571 129 | -923106144 130 | -878057527 131 | -746595636 132 | -542800639 133 | -285123816 134 | 0 135 | 285123816 136 | 542800639 137 | 746595636 138 | 878057527 139 | 923106144 140 | 877794571 141 | 747021096 142 | 542375179 143 | 285386772 144 | 0 145 | -285386772 146 | -542375179 147 | -747021096 148 | -877794571 149 | -923106144 150 | -878057527 151 | -746595636 152 | -542800639 153 | -285123816 154 | 0 155 | 285123816 156 | 542800639 157 | 746595636 158 | 878057527 159 | 923106144 160 | 877794571 161 | 747021096 162 | 542375179 163 | 285386772 164 | 0 165 | -285386772 166 | -542375179 167 | -747021096 168 | -877794571 169 | -923106144 170 | -878057527 171 | -746595636 172 | -542800639 173 | -285123816 174 | 0 175 | 285123816 176 | 542800639 177 | 746595636 178 | 878057527 179 | 923106144 180 | 877794571 181 | 747021096 182 | 542375179 183 | 285386772 184 | 0 185 | -285386772 186 | -542375179 187 | -747021096 188 | -877794571 189 | -923106144 190 | -878057527 191 | -746595636 192 | -542800639 193 | -285123816 194 | 0 195 | 285123816 196 | 542800639 197 | 746595636 198 | 878057527 199 | 923106144 200 | 877794571 201 | 747021096 202 | 542375179 203 | 285386772 204 | 0 205 | -285386772 206 | -542375179 207 | -747021096 208 | -877794571 209 | -923106144 210 | -878057527 211 | -746595636 212 | -542800639 213 | -285123816 214 | 0 215 | 285123816 216 | 542800639 217 | 746595636 218 | 878057527 219 | 923106144 220 | 877794571 221 | 747021096 222 | 542375179 223 | 285386772 224 | 0 225 | -285386772 226 | -542375179 227 | -747021096 228 | -877794571 229 | -923106144 230 | -878057527 231 | -746595636 232 | -542800639 233 | -285123816 234 | 0 235 | 285123816 236 | 542800639 237 | 746595636 238 | 878057527 239 | 923106144 240 | 877794571 241 | 747021096 242 | 542375179 243 | 285386772 244 | 0 245 | -285386772 246 | -542375179 247 | x 248 | x 249 | x 250 | x 251 | -------------------------------------------------------------------------------- /project/fir.cmd_log: -------------------------------------------------------------------------------- 1 | xst -intstyle ise -ifn "E:/ISEProjece/FirDesign/fir.xst" -ofn "E:/ISEProjece/FirDesign/fir.syr" 2 | xst -intstyle ise -ifn "E:/ISEProjece/FirDesign/fir.xst" -ofn "E:/ISEProjece/FirDesign/fir.syr" 3 | xst -intstyle ise -ifn "E:/ISEProjece/FirDesign/fir.xst" -ofn "E:/ISEProjece/FirDesign/fir.syr" 4 | xst -intstyle ise -ifn "E:/ISEProjece/FirDesign/fir.xst" -ofn "E:/ISEProjece/FirDesign/fir.syr" 5 | xst -intstyle ise -ifn "E:/ISEProjece/FirDesign/fir.xst" -ofn "E:/ISEProjece/FirDesign/fir.syr" 6 | xst -intstyle ise -ifn "E:/ISEProjece/FirDesign/fir.xst" -ofn "E:/ISEProjece/FirDesign/fir.syr" 7 | xst -intstyle ise -ifn "E:/ISEProjece/FirDesign/fir.xst" -ofn "E:/ISEProjece/FirDesign/fir.syr" 8 | -------------------------------------------------------------------------------- /project/fir.lso: -------------------------------------------------------------------------------- 1 | work 2 | -------------------------------------------------------------------------------- /project/fir.prj: -------------------------------------------------------------------------------- 1 | verilog work "fir.v" 2 | -------------------------------------------------------------------------------- /project/fir.stx: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Grootzz/Verilog-FIR/3b332498ee356fe0e0a0554d3ca5f483909b4b05/project/fir.stx -------------------------------------------------------------------------------- /project/fir.syr: -------------------------------------------------------------------------------- 1 | Release 14.7 - xst P.20131013 (nt64) 2 | Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. 3 | --> Parameter TMPDIR set to xst/projnav.tmp 4 | 5 | 6 | Total REAL time to Xst completion: 0.00 secs 7 | Total CPU time to Xst completion: 0.08 secs 8 | 9 | --> Parameter xsthdpdir set to xst 10 | 11 | 12 | Total REAL time to Xst completion: 0.00 secs 13 | Total CPU time to Xst completion: 0.08 secs 14 | 15 | --> Reading design: fir.prj 16 | 17 | TABLE OF CONTENTS 18 | 1) Synthesis Options Summary 19 | 2) HDL Compilation 20 | 3) Design Hierarchy Analysis 21 | 4) HDL Analysis 22 | 5) HDL Synthesis 23 | 5.1) HDL Synthesis Report 24 | 6) Advanced HDL Synthesis 25 | 6.1) Advanced HDL Synthesis Report 26 | 7) Low Level Synthesis 27 | 8) Partition Report 28 | 9) Final Report 29 | 9.1) Device utilization summary 30 | 9.2) Partition Resource Summary 31 | 9.3) TIMING REPORT 32 | 33 | 34 | ========================================================================= 35 | * Synthesis Options Summary * 36 | ========================================================================= 37 | ---- Source Parameters 38 | Input File Name : "fir.prj" 39 | Input Format : mixed 40 | Ignore Synthesis Constraint File : NO 41 | 42 | ---- Target Parameters 43 | Output File Name : "fir" 44 | Output Format : NGC 45 | Target Device : xc5vfx70t-1-ff1136 46 | 47 | ---- Source Options 48 | Top Module Name : fir 49 | Automatic FSM Extraction : YES 50 | FSM Encoding Algorithm : Auto 51 | Safe Implementation : No 52 | FSM Style : LUT 53 | RAM Extraction : Yes 54 | RAM Style : Auto 55 | ROM Extraction : Yes 56 | Mux Style : Auto 57 | Decoder Extraction : YES 58 | Priority Encoder Extraction : Yes 59 | Shift Register Extraction : YES 60 | Logical Shifter Extraction : YES 61 | XOR Collapsing : YES 62 | ROM Style : Auto 63 | Mux Extraction : Yes 64 | Resource Sharing : YES 65 | Asynchronous To Synchronous : NO 66 | Use DSP Block : Auto 67 | Automatic Register Balancing : No 68 | 69 | ---- Target Options 70 | LUT Combining : Auto 71 | Reduce Control Sets : Auto 72 | Add IO Buffers : YES 73 | Global Maximum Fanout : 100000 74 | Add Generic Clock Buffer(BUFG) : 32 75 | Register Duplication : YES 76 | Slice Packing : YES 77 | Optimize Instantiated Primitives : NO 78 | Use Clock Enable : Auto 79 | Use Synchronous Set : Auto 80 | Use Synchronous Reset : Auto 81 | Pack IO Registers into IOBs : Auto 82 | Equivalent register Removal : YES 83 | 84 | ---- General Options 85 | Optimization Goal : Speed 86 | Optimization Effort : 1 87 | Power Reduction : NO 88 | Keep Hierarchy : No 89 | Netlist Hierarchy : As_Optimized 90 | RTL Output : Yes 91 | Global Optimization : AllClockNets 92 | Read Cores : YES 93 | Write Timing Constraints : NO 94 | Cross Clock Analysis : NO 95 | Hierarchy Separator : / 96 | Bus Delimiter : <> 97 | Case Specifier : Maintain 98 | Slice Utilization Ratio : 100 99 | BRAM Utilization Ratio : 100 100 | DSP48 Utilization Ratio : 100 101 | Verilog 2001 : YES 102 | Auto BRAM Packing : NO 103 | Slice Utilization Ratio Delta : 5 104 | 105 | ========================================================================= 106 | 107 | 108 | ========================================================================= 109 | * HDL Compilation * 110 | ========================================================================= 111 | Compiling verilog file "fir.v" in library work 112 | Module compiled 113 | No errors in compilation 114 | Analysis of file <"fir.prj"> succeeded. 115 | 116 | 117 | ========================================================================= 118 | * Design Hierarchy Analysis * 119 | ========================================================================= 120 | Analyzing hierarchy for module in library with parameters. 121 | order = "00000000000000000000000000010000" 122 | word_width = "00000000000000000000000000010000" 123 | 124 | 125 | ========================================================================= 126 | * HDL Analysis * 127 | ========================================================================= 128 | Analyzing top module . 129 | order = 32'sb00000000000000000000000000010000 130 | word_width = 32'sb00000000000000000000000000010000 131 | WARNING:Xst:905 - "fir.v" line 170: One or more signals are missing in the sensitivity list of always block. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are: 132 | 133 | Module is correct for synthesis. 134 | 135 | 136 | ========================================================================= 137 | * HDL Synthesis * 138 | ========================================================================= 139 | 140 | Performing bidirectional port resolution... 141 | 142 | Synthesizing Unit . 143 | Related source file is "fir.v". 144 | Found 16-bit register for signal . 145 | Found 272-bit register for signal . 146 | Found 544-bit register for signal . 147 | Found 16x16-bit multiplier for signal created at line 138. 148 | Found 16x16-bit multiplier for signal created at line 139. 149 | Found 16x16-bit multiplier for signal created at line 148. 150 | Found 16x16-bit multiplier for signal created at line 149. 151 | Found 16x16-bit multiplier for signal created at line 150. 152 | Found 16x16-bit multiplier for signal created at line 151. 153 | Found 16x16-bit multiplier for signal created at line 152. 154 | Found 16x16-bit multiplier for signal created at line 153. 155 | Found 16x16-bit multiplier for signal created at line 154. 156 | Found 16x16-bit multiplier for signal created at line 140. 157 | Found 16x16-bit multiplier for signal created at line 141. 158 | Found 16x16-bit multiplier for signal created at line 142. 159 | Found 16x16-bit multiplier for signal created at line 143. 160 | Found 16x16-bit multiplier for signal created at line 144. 161 | Found 16x16-bit multiplier for signal created at line 145. 162 | Found 16x16-bit multiplier for signal created at line 146. 163 | Found 16x16-bit multiplier for signal created at line 147. 164 | Found 32-bit register for signal . 165 | Found 33-bit adder for signal created at line 164. 166 | Found 34-bit adder for signal created at line 164. 167 | Found 35-bit adder for signal created at line 164. 168 | Found 36-bit adder for signal created at line 164. 169 | Found 37-bit adder for signal created at line 164. 170 | Found 38-bit adder for signal created at line 164. 171 | Found 39-bit adder for signal created at line 164. 172 | Found 40-bit adder for signal created at line 164. 173 | Found 41-bit adder for signal created at line 164. 174 | Found 42-bit adder for signal created at line 164. 175 | Found 43-bit adder for signal created at line 164. 176 | Found 44-bit adder for signal created at line 164. 177 | Found 45-bit adder for signal created at line 164. 178 | Found 46-bit adder for signal created at line 164. 179 | Found 32-bit adder for signal created at line 164. 180 | Found 32-bit adder for signal created at line 164. 181 | INFO:Xst:738 - HDL ADVISOR - 272 flip-flops were inferred for signal . You may be trying to describe a RAM in a way that is incompatible with block and distributed RAM resources available on Xilinx devices, or with a specific template that is not supported. Please review the Xilinx resources documentation and the XST user manual for coding guidelines. Taking advantage of RAM resources will lead to improved device usage and reduced synthesis time. 182 | INFO:Xst:738 - HDL ADVISOR - 544 flip-flops were inferred for signal . You may be trying to describe a RAM in a way that is incompatible with block and distributed RAM resources available on Xilinx devices, or with a specific template that is not supported. Please review the Xilinx resources documentation and the XST user manual for coding guidelines. Taking advantage of RAM resources will lead to improved device usage and reduced synthesis time. 183 | Summary: 184 | inferred 864 D-type flip-flop(s). 185 | inferred 16 Adder/Subtractor(s). 186 | inferred 17 Multiplier(s). 187 | Unit synthesized. 188 | 189 | 190 | ========================================================================= 191 | HDL Synthesis Report 192 | 193 | Macro Statistics 194 | # Multipliers : 17 195 | 16x16-bit multiplier : 17 196 | # Adders/Subtractors : 16 197 | 32-bit adder : 2 198 | 33-bit adder : 1 199 | 34-bit adder : 1 200 | 35-bit adder : 1 201 | 36-bit adder : 1 202 | 37-bit adder : 1 203 | 38-bit adder : 1 204 | 39-bit adder : 1 205 | 40-bit adder : 1 206 | 41-bit adder : 1 207 | 42-bit adder : 1 208 | 43-bit adder : 1 209 | 44-bit adder : 1 210 | 45-bit adder : 1 211 | 46-bit adder : 1 212 | # Registers : 36 213 | 16-bit register : 18 214 | 32-bit register : 18 215 | 216 | ========================================================================= 217 | 218 | ========================================================================= 219 | * Advanced HDL Synthesis * 220 | ========================================================================= 221 | 222 | 223 | ========================================================================= 224 | Advanced HDL Synthesis Report 225 | 226 | Macro Statistics 227 | # Multipliers : 17 228 | 16x16-bit multiplier : 17 229 | # Adders/Subtractors : 16 230 | 32-bit adder : 5 231 | 33-bit adder : 1 232 | 34-bit adder : 1 233 | 35-bit adder : 1 234 | 36-bit adder : 1 235 | 37-bit adder : 1 236 | 38-bit adder : 1 237 | 39-bit adder : 1 238 | 40-bit adder : 1 239 | 41-bit adder : 1 240 | 42-bit adder : 1 241 | 43-bit adder : 1 242 | # Registers : 864 243 | Flip-Flops : 864 244 | 245 | ========================================================================= 246 | 247 | ========================================================================= 248 | * Low Level Synthesis * 249 | ========================================================================= 250 | INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : 251 | INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : 252 | INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : 253 | INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches, which will be removed : 254 | INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 10 FFs/Latches, which will be removed : 255 | INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 6 FFs/Latches, which will be removed : 256 | INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : 257 | INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches, which will be removed : 258 | INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 4 FFs/Latches, which will be removed : 259 | INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 6 FFs/Latches, which will be removed : 260 | INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 4 FFs/Latches, which will be removed : 261 | INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 9 FFs/Latches, which will be removed : 262 | INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : 263 | INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 10 FFs/Latches, which will be removed : 264 | INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 9 FFs/Latches, which will be removed : 265 | INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches, which will be removed : 266 | INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches, which will be removed : 267 | 268 | Optimizing unit ... 269 | 270 | Mapping all equations... 271 | Building and optimizing final netlist ... 272 | Found area constraint ratio of 100 (+ 5) on block fir, actual ratio is 3. 273 | 274 | Final Macro Processing ... 275 | 276 | ========================================================================= 277 | Final Register Report 278 | 279 | Macro Statistics 280 | # Registers : 791 281 | Flip-Flops : 791 282 | 283 | ========================================================================= 284 | 285 | ========================================================================= 286 | * Partition Report * 287 | ========================================================================= 288 | 289 | Partition Implementation Status 290 | ------------------------------- 291 | 292 | No Partitions were found in this design. 293 | 294 | ------------------------------- 295 | 296 | ========================================================================= 297 | * Final Report * 298 | ========================================================================= 299 | Final Results 300 | RTL Top Level Output File Name : fir.ngr 301 | Top Level Output File Name : fir 302 | Output Format : NGC 303 | Optimization Goal : Speed 304 | Keep Hierarchy : No 305 | 306 | Design Statistics 307 | # IOs : 50 308 | 309 | Cell Usage : 310 | # BELS : 1489 311 | # GND : 1 312 | # INV : 1 313 | # LUT2 : 481 314 | # LUT3 : 30 315 | # LUT4 : 9 316 | # LUT5 : 1 317 | # LUT6 : 20 318 | # MUXCY : 465 319 | # VCC : 1 320 | # XORCY : 480 321 | # FlipFlops/Latches : 791 322 | # FDC : 791 323 | # Clock Buffers : 1 324 | # BUFGP : 1 325 | # IO Buffers : 49 326 | # IBUF : 17 327 | # OBUF : 32 328 | # DSPs : 17 329 | # DSP48E : 17 330 | ========================================================================= 331 | 332 | Device utilization summary: 333 | --------------------------- 334 | 335 | Selected Device : 5vfx70tff1136-1 336 | 337 | 338 | Slice Logic Utilization: 339 | Number of Slice Registers: 791 out of 44800 1% 340 | Number of Slice LUTs: 542 out of 44800 1% 341 | Number used as Logic: 542 out of 44800 1% 342 | 343 | Slice Logic Distribution: 344 | Number of LUT Flip Flop pairs used: 1274 345 | Number with an unused Flip Flop: 483 out of 1274 37% 346 | Number with an unused LUT: 732 out of 1274 57% 347 | Number of fully used LUT-FF pairs: 59 out of 1274 4% 348 | Number of unique control sets: 1 349 | 350 | IO Utilization: 351 | Number of IOs: 50 352 | Number of bonded IOBs: 50 out of 640 7% 353 | 354 | Specific Feature Utilization: 355 | Number of BUFG/BUFGCTRLs: 1 out of 32 3% 356 | Number of DSP48Es: 17 out of 128 13% 357 | 358 | --------------------------- 359 | Partition Resource Summary: 360 | --------------------------- 361 | 362 | No Partitions were found in this design. 363 | 364 | --------------------------- 365 | 366 | 367 | ========================================================================= 368 | TIMING REPORT 369 | 370 | NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE. 371 | FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT 372 | GENERATED AFTER PLACE-and-ROUTE. 373 | 374 | Clock Information: 375 | ------------------ 376 | -----------------------------------+------------------------+-------+ 377 | Clock Signal | Clock buffer(FF name) | Load | 378 | -----------------------------------+------------------------+-------+ 379 | clk | BUFGP | 791 | 380 | -----------------------------------+------------------------+-------+ 381 | 382 | Asynchronous Control Signals Information: 383 | ---------------------------------------- 384 | -----------------------------------+------------------------+-------+ 385 | Control Signal | Buffer(FF name) | Load | 386 | -----------------------------------+------------------------+-------+ 387 | rst_inv(rst_inv361_INV_0:O) | NONE(data_in_buf_0) | 791 | 388 | -----------------------------------+------------------------+-------+ 389 | 390 | Timing Summary: 391 | --------------- 392 | Speed Grade: -1 393 | 394 | Minimum period: 20.609ns (Maximum Frequency: 48.523MHz) 395 | Minimum input arrival time before clock: 1.154ns 396 | Maximum output required time after clock: 3.833ns 397 | Maximum combinational path delay: 4.403ns 398 | 399 | Timing Detail: 400 | -------------- 401 | All values displayed in nanoseconds (ns) 402 | 403 | ========================================================================= 404 | Timing constraint: Default period analysis for Clock 'clk' 405 | Clock period: 20.609ns (frequency: 48.523MHz) 406 | Total number of paths / destination ports: 5480833266277056 / 775 407 | ------------------------------------------------------------------------- 408 | Delay: 20.609ns (Levels of Logic = 60) 409 | Source: product_0_0 (FF) 410 | Destination: sum_buf_31 (FF) 411 | Source Clock: clk rising 412 | Destination Clock: clk rising 413 | 414 | Data Path: product_0_0 to sum_buf_31 415 | Gate Net 416 | Cell:in->out fanout Delay Delay Logical Name (Net Name) 417 | ---------------------------------------- ------------ 418 | FDC:C->Q 1 0.471 0.576 product_0_0 (product_0_0) 419 | LUT2:I0->O 1 0.094 0.000 Madd_sum_buf_add0000_lut<0> (Madd_sum_buf_add0000_lut<0>) 420 | MUXCY:S->O 1 0.372 0.000 Madd_sum_buf_add0000_cy<0> (Madd_sum_buf_add0000_cy<0>) 421 | MUXCY:CI->O 1 0.026 0.000 Madd_sum_buf_add0000_cy<1> (Madd_sum_buf_add0000_cy<1>) 422 | MUXCY:CI->O 1 0.026 0.000 Madd_sum_buf_add0000_cy<2> (Madd_sum_buf_add0000_cy<2>) 423 | MUXCY:CI->O 1 0.026 0.000 Madd_sum_buf_add0000_cy<3> (Madd_sum_buf_add0000_cy<3>) 424 | MUXCY:CI->O 1 0.026 0.000 Madd_sum_buf_add0000_cy<4> (Madd_sum_buf_add0000_cy<4>) 425 | MUXCY:CI->O 1 0.026 0.000 Madd_sum_buf_add0000_cy<5> (Madd_sum_buf_add0000_cy<5>) 426 | MUXCY:CI->O 1 0.026 0.000 Madd_sum_buf_add0000_cy<6> (Madd_sum_buf_add0000_cy<6>) 427 | MUXCY:CI->O 1 0.026 0.000 Madd_sum_buf_add0000_cy<7> (Madd_sum_buf_add0000_cy<7>) 428 | MUXCY:CI->O 1 0.026 0.000 Madd_sum_buf_add0000_cy<8> (Madd_sum_buf_add0000_cy<8>) 429 | MUXCY:CI->O 1 0.026 0.000 Madd_sum_buf_add0000_cy<9> (Madd_sum_buf_add0000_cy<9>) 430 | MUXCY:CI->O 1 0.026 0.000 Madd_sum_buf_add0000_cy<10> (Madd_sum_buf_add0000_cy<10>) 431 | MUXCY:CI->O 1 0.026 0.000 Madd_sum_buf_add0000_cy<11> (Madd_sum_buf_add0000_cy<11>) 432 | MUXCY:CI->O 1 0.026 0.000 Madd_sum_buf_add0000_cy<12> (Madd_sum_buf_add0000_cy<12>) 433 | MUXCY:CI->O 1 0.026 0.000 Madd_sum_buf_add0000_cy<13> (Madd_sum_buf_add0000_cy<13>) 434 | MUXCY:CI->O 1 0.026 0.000 Madd_sum_buf_add0000_cy<14> (Madd_sum_buf_add0000_cy<14>) 435 | MUXCY:CI->O 1 0.026 0.000 Madd_sum_buf_add0000_cy<15> (Madd_sum_buf_add0000_cy<15>) 436 | XORCY:CI->O 1 0.357 0.480 Madd_sum_buf_add0000_xor<16> (sum_buf_add0000<16>) 437 | LUT2:I1->O 1 0.094 0.000 Madd_sum_buf_add0001_lut<16> (Madd_sum_buf_add0001_lut<16>) 438 | MUXCY:S->O 1 0.372 0.000 Madd_sum_buf_add0001_cy<16> (Madd_sum_buf_add0001_cy<16>) 439 | XORCY:CI->O 1 0.357 0.480 Madd_sum_buf_add0001_xor<17> (sum_buf_add0001<17>) 440 | LUT2:I1->O 1 0.094 0.000 Madd_sum_buf_add0002_lut<17> (Madd_sum_buf_add0002_lut<17>) 441 | MUXCY:S->O 1 0.372 0.000 Madd_sum_buf_add0002_cy<17> (Madd_sum_buf_add0002_cy<17>) 442 | XORCY:CI->O 1 0.357 0.480 Madd_sum_buf_add0002_xor<18> (sum_buf_add0002<18>) 443 | LUT2:I1->O 1 0.094 0.000 Madd_sum_buf_add0003_lut<18> (Madd_sum_buf_add0003_lut<18>) 444 | MUXCY:S->O 1 0.372 0.000 Madd_sum_buf_add0003_cy<18> (Madd_sum_buf_add0003_cy<18>) 445 | XORCY:CI->O 1 0.357 0.480 Madd_sum_buf_add0003_xor<19> (sum_buf_add0003<19>) 446 | LUT2:I1->O 1 0.094 0.000 Madd_sum_buf_add0004_lut<19> (Madd_sum_buf_add0004_lut<19>) 447 | MUXCY:S->O 1 0.372 0.000 Madd_sum_buf_add0004_cy<19> (Madd_sum_buf_add0004_cy<19>) 448 | XORCY:CI->O 1 0.357 0.480 Madd_sum_buf_add0004_xor<20> (sum_buf_add0004<20>) 449 | LUT2:I1->O 1 0.094 0.000 Madd_sum_buf_add0005_lut<20> (Madd_sum_buf_add0005_lut<20>) 450 | MUXCY:S->O 1 0.372 0.000 Madd_sum_buf_add0005_cy<20> (Madd_sum_buf_add0005_cy<20>) 451 | XORCY:CI->O 1 0.357 0.480 Madd_sum_buf_add0005_xor<21> (sum_buf_add0005<21>) 452 | LUT2:I1->O 1 0.094 0.000 Madd_sum_buf_add0006_lut<21> (Madd_sum_buf_add0006_lut<21>) 453 | MUXCY:S->O 1 0.372 0.000 Madd_sum_buf_add0006_cy<21> (Madd_sum_buf_add0006_cy<21>) 454 | XORCY:CI->O 1 0.357 0.480 Madd_sum_buf_add0006_xor<22> (sum_buf_add0006<22>) 455 | LUT2:I1->O 1 0.094 0.000 Madd_sum_buf_add0007_lut<22> (Madd_sum_buf_add0007_lut<22>) 456 | MUXCY:S->O 1 0.372 0.000 Madd_sum_buf_add0007_cy<22> (Madd_sum_buf_add0007_cy<22>) 457 | XORCY:CI->O 1 0.357 0.480 Madd_sum_buf_add0007_xor<23> (sum_buf_add0007<23>) 458 | LUT2:I1->O 1 0.094 0.000 Madd_sum_buf_add0008_lut<23> (Madd_sum_buf_add0008_lut<23>) 459 | MUXCY:S->O 1 0.372 0.000 Madd_sum_buf_add0008_cy<23> (Madd_sum_buf_add0008_cy<23>) 460 | XORCY:CI->O 1 0.357 0.480 Madd_sum_buf_add0008_xor<24> (sum_buf_add0008<24>) 461 | LUT2:I1->O 1 0.094 0.000 Madd_sum_buf_add0009_lut<24> (Madd_sum_buf_add0009_lut<24>) 462 | MUXCY:S->O 1 0.372 0.000 Madd_sum_buf_add0009_cy<24> (Madd_sum_buf_add0009_cy<24>) 463 | XORCY:CI->O 1 0.357 0.480 Madd_sum_buf_add0009_xor<25> (sum_buf_add0009<25>) 464 | LUT2:I1->O 1 0.094 0.000 Madd_sum_buf_add0010_lut<25> (Madd_sum_buf_add0010_lut<25>) 465 | MUXCY:S->O 1 0.372 0.000 Madd_sum_buf_add0010_cy<25> (Madd_sum_buf_add0010_cy<25>) 466 | XORCY:CI->O 1 0.357 0.480 Madd_sum_buf_add0010_xor<26> (sum_buf_add0010<26>) 467 | LUT2:I1->O 1 0.094 0.000 Madd_sum_buf_add0011_Madd_lut<26> (Madd_sum_buf_add0011_Madd_lut<26>) 468 | MUXCY:S->O 1 0.372 0.000 Madd_sum_buf_add0011_Madd_cy<26> (Madd_sum_buf_add0011_Madd_cy<26>) 469 | XORCY:CI->O 1 0.357 0.480 Madd_sum_buf_add0011_Madd_xor<27> (sum_buf_add0011<27>) 470 | LUT2:I1->O 1 0.094 0.000 Madd_sum_buf_add0012_Madd_lut<27> (Madd_sum_buf_add0012_Madd_lut<27>) 471 | MUXCY:S->O 1 0.372 0.000 Madd_sum_buf_add0012_Madd_cy<27> (Madd_sum_buf_add0012_Madd_cy<27>) 472 | XORCY:CI->O 1 0.357 0.480 Madd_sum_buf_add0012_Madd_xor<28> (sum_buf_add0012<28>) 473 | LUT2:I1->O 1 0.094 0.000 Madd_sum_buf_add0013_Madd_lut<28> (Madd_sum_buf_add0013_Madd_lut<28>) 474 | MUXCY:S->O 1 0.372 0.000 Madd_sum_buf_add0013_Madd_cy<28> (Madd_sum_buf_add0013_Madd_cy<28>) 475 | XORCY:CI->O 3 0.357 0.587 Madd_sum_buf_add0013_Madd_xor<29> (sum_buf_add0013<29>) 476 | LUT4:I2->O 1 0.094 0.000 Madd_sum_buf_add0014_Madd_lut<30> (Madd_sum_buf_add0014_Madd_lut<30>) 477 | MUXCY:S->O 0 0.372 0.000 Madd_sum_buf_add0014_Madd_cy<30> (Madd_sum_buf_add0014_Madd_cy<30>) 478 | XORCY:CI->O 1 0.357 0.000 Madd_sum_buf_add0014_Madd_xor<31> (sum_buf_add0014<31>) 479 | FDC:D -0.018 sum_buf_31 480 | ---------------------------------------- 481 | Total 20.609ns (13.206ns logic, 7.403ns route) 482 | (64.1% logic, 35.9% route) 483 | 484 | ========================================================================= 485 | Timing constraint: Default OFFSET IN BEFORE for Clock 'clk' 486 | Total number of paths / destination ports: 16 / 16 487 | ------------------------------------------------------------------------- 488 | Offset: 1.154ns (Levels of Logic = 1) 489 | Source: filter_in<0> (PAD) 490 | Destination: data_in_buf_0 (FF) 491 | Destination Clock: clk rising 492 | 493 | Data Path: filter_in<0> to data_in_buf_0 494 | Gate Net 495 | Cell:in->out fanout Delay Delay Logical Name (Net Name) 496 | ---------------------------------------- ------------ 497 | IBUF:I->O 1 0.818 0.336 filter_in_0_IBUF (filter_in_0_IBUF) 498 | FDC:D -0.018 data_in_buf_0 499 | ---------------------------------------- 500 | Total 1.154ns (0.818ns logic, 0.336ns route) 501 | (70.9% logic, 29.1% route) 502 | 503 | ========================================================================= 504 | Timing constraint: Default OFFSET OUT AFTER for Clock 'clk' 505 | Total number of paths / destination ports: 32 / 32 506 | ------------------------------------------------------------------------- 507 | Offset: 3.833ns (Levels of Logic = 2) 508 | Source: sum_buf_31 (FF) 509 | Destination: filter_out<31> (PAD) 510 | Source Clock: clk rising 511 | 512 | Data Path: sum_buf_31 to filter_out<31> 513 | Gate Net 514 | Cell:in->out fanout Delay Delay Logical Name (Net Name) 515 | ---------------------------------------- ------------ 516 | FDC:C->Q 1 0.471 0.480 sum_buf_31 (sum_buf_31) 517 | LUT2:I1->O 1 0.094 0.336 filter_out<31>1 (filter_out_31_OBUF) 518 | OBUF:I->O 2.452 filter_out_31_OBUF (filter_out<31>) 519 | ---------------------------------------- 520 | Total 3.833ns (3.017ns logic, 0.816ns route) 521 | (78.7% logic, 21.3% route) 522 | 523 | ========================================================================= 524 | Timing constraint: Default path analysis 525 | Total number of paths / destination ports: 32 / 32 526 | ------------------------------------------------------------------------- 527 | Delay: 4.403ns (Levels of Logic = 3) 528 | Source: rst (PAD) 529 | Destination: filter_out<31> (PAD) 530 | 531 | Data Path: rst to filter_out<31> 532 | Gate Net 533 | Cell:in->out fanout Delay Delay Logical Name (Net Name) 534 | ---------------------------------------- ------------ 535 | IBUF:I->O 33 0.818 0.703 rst_IBUF (rst_IBUF) 536 | LUT2:I0->O 1 0.094 0.336 filter_out<9>1 (filter_out_9_OBUF) 537 | OBUF:I->O 2.452 filter_out_9_OBUF (filter_out<9>) 538 | ---------------------------------------- 539 | Total 4.403ns (3.364ns logic, 1.039ns route) 540 | (76.4% logic, 23.6% route) 541 | 542 | ========================================================================= 543 | 544 | 545 | Total REAL time to Xst completion: 14.00 secs 546 | Total CPU time to Xst completion: 14.59 secs 547 | 548 | --> 549 | 550 | Total memory usage is 402652 kilobytes 551 | 552 | Number of errors : 0 ( 0 filtered) 553 | Number of warnings : 1 ( 0 filtered) 554 | Number of infos : 19 ( 0 filtered) 555 | 556 | -------------------------------------------------------------------------------- /project/fir.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: anxu chan 5 | // 6 | // Create Date: 16:17:14 08/02/2017 7 | // Design Name: FIR filter 8 | // Module Name: fir 9 | // Project Name: FirDesign 10 | // Target Devices: Xilinix V5 11 | // Description: fir res file 12 | // Revision: 1.0 13 | // Revision 0.01 - File Created 14 | // Additional Comments: 15 | // 16 | ////////////////////////////////////////////////////////////////////////////////// 17 | module fir( 18 | input clk, 19 | input rst, 20 | input wire signed [15:0] filter_in, 21 | output reg signed [31:0] filter_out 22 | ); 23 | 24 | parameter word_width = 16; 25 | parameter order = 16; 26 | 27 | // define delay unit , input width is 16 , filter order is 16 28 | reg signed [word_width-1:0] delay_pipeline[order:0]; 29 | 30 | // define coef 31 | wire signed [word_width-1:0] coef[order:0]; 32 | assign coef[0] = -17; 33 | assign coef[1] = 62; 34 | assign coef[2] = 456; 35 | assign coef[3] = 1482; 36 | assign coef[4] = 3367; 37 | assign coef[5] = 6013; 38 | assign coef[6] = 8880; 39 | assign coef[7] = 11129; 40 | assign coef[8] = 11983; 41 | assign coef[9] = 11129; 42 | assign coef[10] = 8880; 43 | assign coef[11] = 6013; 44 | assign coef[12] = 3367; 45 | assign coef[13] = 1482; 46 | assign coef[14] = 456; 47 | assign coef[15] = 62; 48 | assign coef[16] = -17; 49 | 50 | // define multipler 51 | reg signed [31:0] product[16:0]; 52 | 53 | // define sum buffer 54 | reg signed [31:0] sum_buf; 55 | 56 | // define input data buffer 57 | reg signed [15:0] data_in_buf; 58 | 59 | // data buffer 60 | always @(posedge clk or negedge rst) begin 61 | if (!rst) begin 62 | data_in_buf <= 0; 63 | end 64 | else begin 65 | data_in_buf <= filter_in; 66 | end 67 | end 68 | 69 | // delay units pipeline 70 | always @(posedge clk or negedge rst) begin 71 | if (!rst) begin 72 | delay_pipeline[0] <= 0 ; 73 | delay_pipeline[1] <= 0 ; 74 | delay_pipeline[2] <= 0 ; 75 | delay_pipeline[3] <= 0 ; 76 | delay_pipeline[4] <= 0 ; 77 | delay_pipeline[5] <= 0 ; 78 | delay_pipeline[6] <= 0 ; 79 | delay_pipeline[7] <= 0 ; 80 | delay_pipeline[8] <= 0 ; 81 | delay_pipeline[9] <= 0 ; 82 | delay_pipeline[10] <= 0 ; 83 | delay_pipeline[11] <= 0 ; 84 | delay_pipeline[12] <= 0 ; 85 | delay_pipeline[13] <= 0 ; 86 | delay_pipeline[14] <= 0 ; 87 | delay_pipeline[15] <= 0 ; 88 | delay_pipeline[16] <= 0 ; 89 | end 90 | else begin 91 | delay_pipeline[0] <= data_in_buf ; 92 | delay_pipeline[1] <= delay_pipeline[0] ; 93 | delay_pipeline[2] <= delay_pipeline[1] ; 94 | delay_pipeline[3] <= delay_pipeline[2] ; 95 | delay_pipeline[4] <= delay_pipeline[3] ; 96 | delay_pipeline[5] <= delay_pipeline[4] ; 97 | delay_pipeline[6] <= delay_pipeline[5] ; 98 | delay_pipeline[7] <= delay_pipeline[6] ; 99 | delay_pipeline[8] <= delay_pipeline[7] ; 100 | delay_pipeline[9] <= delay_pipeline[8] ; 101 | delay_pipeline[10] <= delay_pipeline[9] ; 102 | delay_pipeline[11] <= delay_pipeline[10] ; 103 | delay_pipeline[12] <= delay_pipeline[11] ; 104 | delay_pipeline[13] <= delay_pipeline[12] ; 105 | delay_pipeline[14] <= delay_pipeline[13] ; 106 | delay_pipeline[15] <= delay_pipeline[14] ; 107 | delay_pipeline[16] <= delay_pipeline[15] ; 108 | end 109 | end 110 | 111 | // implement product with coef 112 | always @(posedge clk or negedge rst) begin 113 | if (!rst) begin 114 | product[0] <= 0; 115 | product[1] <= 0; 116 | product[2] <= 0; 117 | product[3] <= 0; 118 | product[4] <= 0; 119 | product[5] <= 0; 120 | product[6] <= 0; 121 | product[7] <= 0; 122 | product[8] <= 0; 123 | product[9] <= 0; 124 | product[10] <= 0; 125 | product[11] <= 0; 126 | product[12] <= 0; 127 | product[13] <= 0; 128 | product[14] <= 0; 129 | product[15] <= 0; 130 | product[16] <= 0; 131 | end 132 | else begin 133 | product[0] <= coef[0] * delay_pipeline[0]; 134 | product[1] <= coef[1] * delay_pipeline[1]; 135 | product[2] <= coef[2] * delay_pipeline[2]; 136 | product[3] <= coef[3] * delay_pipeline[3]; 137 | product[4] <= coef[4] * delay_pipeline[4]; 138 | product[5] <= coef[5] * delay_pipeline[5]; 139 | product[6] <= coef[6] * delay_pipeline[6]; 140 | product[7] <= coef[7] * delay_pipeline[7]; 141 | product[8] <= coef[8] * delay_pipeline[8]; 142 | product[9] <= coef[9] * delay_pipeline[9]; 143 | product[10] <= coef[10] * delay_pipeline[10]; 144 | product[11] <= coef[11] * delay_pipeline[11]; 145 | product[12] <= coef[12] * delay_pipeline[12]; 146 | product[13] <= coef[13] * delay_pipeline[13]; 147 | product[14] <= coef[14] * delay_pipeline[14]; 148 | product[15] <= coef[15] * delay_pipeline[15]; 149 | product[16] <= coef[16] * delay_pipeline[16]; 150 | end 151 | end 152 | 153 | // accumulation 154 | always @(posedge clk or negedge rst) begin 155 | if (!rst) begin 156 | sum_buf <= 0; 157 | end 158 | else begin 159 | sum_buf <= product[0] + product[1]+ product[2]+ product[3]+ product[4] 160 | + product[5]+ product[6]+ product[7]+ product[8]+ product[9]+ product[10] 161 | + product[11]+ product[12]+ product[13]+ product[14]+ product[15]+ product[16]; 162 | end 163 | end 164 | 165 | always @(sum_buf) begin 166 | if (!rst) begin 167 | filter_out = 0; 168 | end 169 | else begin 170 | filter_out = sum_buf; 171 | end 172 | end 173 | 174 | endmodule 175 | -------------------------------------------------------------------------------- /project/fir.xst: -------------------------------------------------------------------------------- 1 | set -tmpdir "xst/projnav.tmp" 2 | set -xsthdpdir "xst" 3 | run 4 | -ifn fir.prj 5 | -ifmt mixed 6 | -ofn fir 7 | -ofmt NGC 8 | -p xc5vfx70t-1-ff1136 9 | -top fir 10 | -opt_mode Speed 11 | -opt_level 1 12 | -power NO 13 | -iuc NO 14 | -keep_hierarchy No 15 | -netlist_hierarchy As_Optimized 16 | -rtlview Yes 17 | -glob_opt AllClockNets 18 | -read_cores YES 19 | -write_timing_constraints NO 20 | -cross_clock_analysis NO 21 | -hierarchy_separator / 22 | -bus_delimiter <> 23 | -case Maintain 24 | -slice_utilization_ratio 100 25 | -bram_utilization_ratio 100 26 | -dsp_utilization_ratio 100 27 | -lc Auto 28 | -reduce_control_sets Auto 29 | -verilog2001 YES 30 | -fsm_extract YES -fsm_encoding Auto 31 | -safe_implementation No 32 | -fsm_style LUT 33 | -ram_extract Yes 34 | -ram_style Auto 35 | -rom_extract Yes 36 | -mux_style Auto 37 | -decoder_extract YES 38 | -priority_extract Yes 39 | -shreg_extract YES 40 | -shift_extract YES 41 | -xor_collapse YES 42 | -rom_style Auto 43 | -auto_bram_packing NO 44 | -mux_extract Yes 45 | -resource_sharing YES 46 | -async_to_sync NO 47 | -use_dsp48 Auto 48 | -iobuf YES 49 | -max_fanout 100000 50 | -bufg 32 51 | -register_duplication YES 52 | -register_balancing No 53 | -slice_packing YES 54 | -optimize_primitives NO 55 | -use_clock_enable Auto 56 | -use_sync_set Auto 57 | -use_sync_reset Auto 58 | -iob Auto 59 | -equivalent_register_removal YES 60 | -slice_utilization_ratio_maxmargin 5 61 | -------------------------------------------------------------------------------- /project/fir_envsettings.html: -------------------------------------------------------------------------------- 1 | Xilinx System Settings Report 2 | 3 |
System Settings

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6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 | 39 | 40 | 41 | 42 | 43 | 44 | 45 | 46 | 47 | 48 | 49 | 50 | 51 | 52 | 53 | 54 | 55 | 56 | 57 | 58 |
Environment Settings
Environment Variablexstngdbuildmappar
PATHEXT.COM;
.EXE;
.BAT;
.CMD;
.VBS;
.VBE;
.JS;
.JSE;
.WSF;
.WSH;
.MSC		< data not available >< data not available >< data not available >
PathD:\Xilinx\14.7\ISE_DS\ISE\\lib\nt64;
D:\Xilinx\14.7\ISE_DS\ISE\\bin\nt64;
D:\Xilinx\14.7\ISE_DS\ISE\bin\nt64;
D:\Xilinx\14.7\ISE_DS\ISE\lib\nt64;
D:\Xilinx\14.7\ISE_DS\ISE\..\..\..\DocNav;
D:\Xilinx\14.7\ISE_DS\PlanAhead\bin;
D:\Xilinx\14.7\ISE_DS\EDK\bin\nt64;
D:\Xilinx\14.7\ISE_DS\EDK\lib\nt64;
D:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\nt\bin;
D:\Xilinx\14.7\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin;
D:\Xilinx\14.7\ISE_DS\EDK\gnuwin\bin;
D:\Xilinx\14.7\ISE_DS\EDK\gnu\arm\nt\bin;
D:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_be\bin;
D:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_le\bin;
D:\Xilinx\14.7\ISE_DS\common\bin\nt64;
D:\Xilinx\14.7\ISE_DS\common\lib\nt64;
C:\ProgramData\Oracle\Java\javapath;
C:\Windows\system32;
C:\Windows;
C:\Windows\System32\Wbem;
C:\Windows\System32\WindowsPowerShell\v1.0\;
C:\Program Files (x86)\NVIDIA Corporation\PhysX\Common;
D:\Program Files\MATLAB\R2017a\runtime\win64;
D:\Program Files\MATLAB\R2017a\bin;
D:\Program Files\Java\jdk1.8\bin;
D:\Program Files\Java\jdk1.8\jre\bin;
D:\Program Files\Git\cmd		< data not available >< data not available >< data not available >
XILINXD:\Xilinx\14.7\ISE_DS\ISE\< data not available >< data not available >< data not available >
XILINX_DSPD:\Xilinx\14.7\ISE_DS\ISE< data not available >< data not available >< data not available >
XILINX_EDKD:\Xilinx\14.7\ISE_DS\EDK< data not available >< data not available >< data not available >
XILINX_PLANAHEADD:\Xilinx\14.7\ISE_DS\PlanAhead< data not available >< data not available >< data not available >
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Synthesis Property Settings
Switch NameProperty NameValueDefault Value
-ifn fir.prj 
-ifmt mixedMIXED
-ofn fir 
-ofmt NGCNGC
-p xc5vfx70t-1-ff1136 
-top fir 
-opt_modeOptimization GoalSpeedSPEED
-opt_levelOptimization Effort11
-powerPower ReductionNONO
-iucUse synthesis Constraints FileNONO
-keep_hierarchyKeep HierarchyNoNO
-netlist_hierarchyNetlist HierarchyAs_Optimizedas_optimized
-rtlviewGenerate RTL SchematicYesNO
-glob_optGlobal Optimization GoalAllClockNetsALLCLOCKNETS
-read_coresRead CoresYESYES
-write_timing_constraintsWrite Timing ConstraintsNONO
-cross_clock_analysisCross Clock AnalysisNONO
-bus_delimiterBus Delimiter<><>
-slice_utilization_ratioSlice Utilization Ratio100100%
-bram_utilization_ratioBRAM Utilization Ratio100100%
-dsp_utilization_ratioDSP Utilization Ratio100100%
-reduce_control_sets AutoOFF
-verilog2001Verilog 2001YESYES
-fsm_extract YESYES
-fsm_encoding AutoAUTO
-safe_implementation NoNO
-fsm_style LUTLUT
-ram_extract YesYES
-ram_style AutoAUTO
-rom_extract YesYES
-shreg_extract YESYES
-rom_style AutoAUTO
-auto_bram_packing NONO
-resource_sharing YESYES
-async_to_sync NONO
-use_dsp48 AutoAUTO
-iobuf YESYES
-max_fanout 100000100000
-bufg 3232
-register_duplication YESYES
-register_balancing NoNO
-optimize_primitives NONO
-use_clock_enable AutoAUTO
-use_sync_set AutoAUTO
-use_sync_reset AutoAUTO
-iob AutoAUTO
-equivalent_register_removal YESYES
-slice_utilization_ratio_maxmargin 50%
359 | 360 |  
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Operating System Information
Operating System Informationxstngdbuildmappar
CPU Architecture/SpeedIntel(R) Core(TM) i3-3240 CPU @ 3.40GHz/3392 MHz<  data not available  ><  data not available  ><  data not available  >
HostAnish-PC<  data not available  ><  data not available  ><  data not available  >
OS NameMicrosoft Windows 7 , 64-bit<  data not available  ><  data not available  ><  data not available  >
OS ReleaseService Pack 1 (build 7601)<  data not available  ><  data not available  ><  data not available  >
400 | -------------------------------------------------------------------------------- /project/fir_isim_beh.exe: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Grootzz/Verilog-FIR/3b332498ee356fe0e0a0554d3ca5f483909b4b05/project/fir_isim_beh.exe -------------------------------------------------------------------------------- /project/fir_summary.html: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Grootzz/Verilog-FIR/3b332498ee356fe0e0a0554d3ca5f483909b4b05/project/fir_summary.html -------------------------------------------------------------------------------- /project/fir_tb.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | //////////////////////////////////////////////////////////////////////////////// 4 | // Company: 5 | // Engineer: anxu chan 6 | // 7 | // Create Date: 16:17:14 08/02/2017 8 | // Design Name: FIR filter 9 | // Module Name: fir 10 | // Project Name: FirDesign 11 | // Target Devices: Xilinix V5 12 | // Description: test bench 13 | // Revision: 1.0 14 | // Revision 0.01 - File Created 15 | // Additional Comments: 16 | // 17 | //////////////////////////////////////////////////////////////////////////////// 18 | 19 | module fir_tb; 20 | 21 | // Inputs 22 | reg clk; 23 | reg rst; 24 | reg signed [15:0] filter_in; 25 | 26 | // Outputs 27 | wire signed [31:0] filter_out; 28 | 29 | // Instantiate the Unit Under Test (UUT) 30 | fir uut ( 31 | .clk(clk), 32 | .rst(rst), 33 | .filter_in(filter_in), 34 | .filter_out(filter_out) 35 | ); 36 | 37 | // define reset time 38 | initial begin 39 | rst = 0; 40 | #15; 41 | rst = 1; 42 | end 43 | 44 | // define clock 45 | initial begin 46 | clk = 0; 47 | forever #10 clk = ~clk; 48 | end 49 | 50 | // define a ram store input signal 51 | reg signed[15:0] mem[241:0]; 52 | // read data from disk 53 | initial begin 54 | $readmemb("E:/MatlabProject/databin.mem" , mem); 55 | end 56 | 57 | // send data to filter 58 | integer i=0; 59 | initial begin 60 | #15; 61 | for(i = 0 ; i < 242 ; i = i+1) begin 62 | filter_in = mem[i]; 63 | #20; 64 | end 65 | end 66 | 67 | // write data to txt File 68 | integer file; 69 | integer cnt=0; 70 | initial begin 71 | file = $fopen("dataout1.txt" , "w"); 72 | end 73 | 74 | // write data was filtered by fir to txt file 75 | always @(posedge clk) begin 76 | $fdisplay(file , filter_out); 77 | end 78 | 79 | always @(posedge clk) begin 80 | $display("data out (%d)------> : %d ," , cnt, filter_out); 81 | cnt = cnt + 1; 82 | if (cnt == 250) begin 83 | #20 $fclose(file); 84 | rst = 0; 85 | #20 $stop; 86 | end 87 | end 88 | 89 | endmodule 90 | 91 | -------------------------------------------------------------------------------- /project/fir_tb_beh.prj: -------------------------------------------------------------------------------- 1 | verilog work "fir.v" 2 | verilog work "fir_tb.v" 3 | verilog work "D:/Xilinx/14.7/ISE_DS/ISE//verilog/src/glbl.v" 4 | -------------------------------------------------------------------------------- /project/fir_tb_isim_beh.exe: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Grootzz/Verilog-FIR/3b332498ee356fe0e0a0554d3ca5f483909b4b05/project/fir_tb_isim_beh.exe -------------------------------------------------------------------------------- /project/fir_tb_isim_beh.wdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Grootzz/Verilog-FIR/3b332498ee356fe0e0a0554d3ca5f483909b4b05/project/fir_tb_isim_beh.wdb -------------------------------------------------------------------------------- /project/fir_tb_isim_beh1.wdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Grootzz/Verilog-FIR/3b332498ee356fe0e0a0554d3ca5f483909b4b05/project/fir_tb_isim_beh1.wdb -------------------------------------------------------------------------------- /project/fir_tb_stx_beh.prj: -------------------------------------------------------------------------------- 1 | verilog isim_temp "fir.v" 2 | verilog isim_temp "fir_tb.v" 3 | verilog isim_temp "D:/Xilinx/14.7/ISE_DS/ISE//verilog/src/glbl.v" 4 | -------------------------------------------------------------------------------- /project/fir_xst.xrpt: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 7 | 8 | 9 |
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197 | 198 | 199 | 200 | -------------------------------------------------------------------------------- /project/fuse.log: -------------------------------------------------------------------------------- 1 | Running: D:\Xilinx\14.7\ISE_DS\ISE\bin\nt64\unwrapped\fuse.exe -intstyle ise -incremental -lib unisims_ver -lib unimacro_ver -lib xilinxcorelib_ver -lib secureip -o E:/ISEProjece/FirDesign/fir_tb_isim_beh.exe -prj E:/ISEProjece/FirDesign/fir_tb_beh.prj work.fir_tb work.glbl 2 | ISim P.20131013 (signature 0x7708f090) 3 | Number of CPUs detected in this system: 4 4 | Turning on mult-threading, number of parallel sub-compilation jobs: 8 5 | Determining compilation order of HDL files 6 | Analyzing Verilog file "E:/ISEProjece/FirDesign/fir.v" into library work 7 | Analyzing Verilog file "E:/ISEProjece/FirDesign/fir_tb.v" into library work 8 | Analyzing Verilog file "D:/Xilinx/14.7/ISE_DS/ISE//verilog/src/glbl.v" into library work 9 | Starting static elaboration 10 | Completed static elaboration 11 | Compiling module fir 12 | Compiling module fir_tb 13 | Compiling module glbl 14 | Time Resolution for simulation is 1ps. 15 | Waiting for 3 sub-compilation(s) to finish... 16 | Compiled 3 Verilog Units 17 | Built simulation executable E:/ISEProjece/FirDesign/fir_tb_isim_beh.exe 18 | Fuse Memory Usage: 28452 KB 19 | Fuse CPU Usage: 374 ms 20 | -------------------------------------------------------------------------------- /project/fuse.xmsgs: -------------------------------------------------------------------------------- 1 | 2 | 7 | 8 | 9 | 10 | -------------------------------------------------------------------------------- /project/fuseRelaunch.cmd: -------------------------------------------------------------------------------- 1 | -intstyle "ise" -incremental -lib "unisims_ver" -lib "unimacro_ver" -lib "xilinxcorelib_ver" -lib "secureip" -o "E:/ISEProjece/FirDesign/fir_tb_isim_beh.exe" -prj "E:/ISEProjece/FirDesign/fir_tb_beh.prj" "work.fir_tb" "work.glbl" 2 | -------------------------------------------------------------------------------- /project/iseconfig/FirDesign.projectmgr: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 2 10 | 11 | 12 | fir (E:/ISEProjece/FirDesign/fir.v) 13 | 14 | 0 15 | 0 16 | 000000ff00000000000000010000000100000000000000000000000000000000020200000001000000010000006400000094000000020000000000000000000000000200000064ffffffff000000810000000300000002000000940000000100000003000000000000000100000003 17 | true 18 | fir (E:/ISEProjece/FirDesign/fir.v) 19 | 20 | 21 | 22 | 1 23 | Design Utilities/Compile HDL Simulation Libraries 24 | 25 | 26 | Design Utilities 27 | 28 | 0 29 | 0 30 | 000000ff0000000000000001000000010000000000000000000000000000000000000000000000026d000000010000000100000000000000000000000064ffffffff0000008100000000000000010000026d0000000100000000 31 | false 32 | Design Utilities 33 | 34 | 35 | 36 | 1 37 | 38 | 39 | 0 40 | 0 41 | 000000ff000000000000000100000000000000000100000000000000000000000000000000000002b3000000040101000100000000000000000000000064ffffffff0000008100000000000000040000003d0000000100000000000000240000000100000000000000780000000100000000000001da0000000100000000 42 | false 43 | fir.v 44 | 45 | 46 | 47 | 1 48 | work 49 | 50 | 51 | 0 52 | 0 53 | 000000ff00000000000000010000000000000000010000000000000000000000000000000000000121000000010001000100000000000000000000000064ffffffff000000810000000000000001000001210000000100000000 54 | false 55 | work 56 | 57 | 58 | 59 | 1 60 | Configure Target Device 61 | Design Utilities/Compile HDL Simulation Libraries 62 | Implement Design 63 | User Constraints 64 | 65 | 66 | Synthesize - XST 67 | 68 | 0 69 | 0 70 | 000000ff0000000000000001000000010000000000000000000000000000000000000000000000025c000000010000000100000000000000000000000064ffffffff0000008100000000000000010000025c0000000100000000 71 | false 72 | Synthesize - XST 73 | 74 | 75 | 76 | 2 77 | 78 | 79 | fir_tb (E:/ISEProjece/FirDesign/fir_tb.v) 80 | 81 | 0 82 | 0 83 | 000000ff000000000000000100000001000000000000000000000000000000000202000000010000000100000064000000a2000000020000000000000000000000000200000064ffffffff000000810000000300000002000000a20000000100000003000000000000000100000003 84 | false 85 | fir_tb (E:/ISEProjece/FirDesign/fir_tb.v) 86 | 87 | 88 | 89 | 1 90 | Design Utilities 91 | 92 | 93 | 94 | 95 | 0 96 | 0 97 | 000000ff0000000000000001000000010000000000000000000000000000000000000000000000026d000000010000000100000000000000000000000064ffffffff0000008100000000000000010000026d0000000100000000 98 | false 99 | 100 | 101 | 102 | 103 | 1 104 | 105 | 106 | ISim Simulator 107 | 108 | 0 109 | 0 110 | 000000ff0000000000000001000000010000000000000000000000000000000000000000000000026d000000010000000100000000000000000000000064ffffffff0000008100000000000000010000026d0000000100000000 111 | false 112 | ISim Simulator 113 | 114 | 000000ff0000000000000002000000b4000000a301000000050100000002 115 | Behavioral Simulation 116 | 117 | -------------------------------------------------------------------------------- /project/iseconfig/fir.xreport: -------------------------------------------------------------------------------- 1 | 2 | 3 |
4 | 2017-08-04T13:08:51 5 | fir 6 | 2017-08-04T09:41:35 7 | E:/ISEProjece/FirDesign/iseconfig/fir.xreport 8 | E:/ISEProjece/FirDesign\ 9 | 2017-08-03T19:52:46 10 | false 11 |
12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 32 | 33 | 37 | 38 | 43 | 44 | 45 | 56 | 57 | 83 | 148 | 149 | 214 | 215 | 216 | -------------------------------------------------------------------------------- /project/isim.cmd: -------------------------------------------------------------------------------- 1 | onerror {resume} 2 | wave add / 3 | run 5000 ns; 4 | -------------------------------------------------------------------------------- /project/isim.log: -------------------------------------------------------------------------------- 1 | ISim log file 2 | Running: E:\ISEProjece\FirDesign\fir_tb_isim_beh.exe -intstyle ise -gui -tclbatch isim.cmd -wdb E:/ISEProjece/FirDesign/fir_tb_isim_beh.wdb 3 | ISim P.20131013 (signature 0x7708f090) 4 | This is a Full version of ISim. 5 | Time resolution is 1 ps 6 | # onerror resume 7 | # wave add / 8 | # run 5000 ns 9 | Simulator is doing circuit initialization process. 10 | Finished circuit initialization process. 11 | data out ( 0)------> : 0 , 12 | data out ( 1)------> : 0 , 13 | data out ( 2)------> : 0 , 14 | data out ( 3)------> : 0 , 15 | data out ( 4)------> : 0 , 16 | data out ( 5)------> : 0 , 17 | data out ( 6)------> : -249781 , 18 | data out ( 7)------> : 1012150 , 19 | data out ( 8)------> : 5840755 , 20 | data out ( 9)------> : 20747624 , 21 | data out ( 10)------> : 53890635 , 22 | data out ( 11)------> : 114346375 , 23 | data out ( 12)------> : 209673314 , 24 | data out ( 13)------> : 339306784 , 25 | data out ( 14)------> : 494797130 , 26 | data out ( 15)------> : 657147014 , 27 | data out ( 16)------> : 800486271 , 28 | data out ( 17)------> : 898805151 , 29 | data out ( 18)------> : 928946899 , 30 | data out ( 19)------> : 878806721 , 31 | data out ( 20)------> : 746771315 , 32 | data out ( 21)------> : 542375179 , 33 | data out ( 22)------> : 285386772 , 34 | data out ( 23)------> : 0 , 35 | data out ( 24)------> : -285386772 , 36 | data out ( 25)------> : -542375179 , 37 | data out ( 26)------> : -747021096 , 38 | data out ( 27)------> : -877794571 , 39 | data out ( 28)------> : -923106144 , 40 | data out ( 29)------> : -878057527 , 41 | data out ( 30)------> : -746595636 , 42 | data out ( 31)------> : -542800639 , 43 | data out ( 32)------> : -285123816 , 44 | data out ( 33)------> : 0 , 45 | data out ( 34)------> : 285123816 , 46 | data out ( 35)------> : 542800639 , 47 | data out ( 36)------> : 746595636 , 48 | data out ( 37)------> : 878057527 , 49 | data out ( 38)------> : 923106144 , 50 | data out ( 39)------> : 877794571 , 51 | data out ( 40)------> : 747021096 , 52 | data out ( 41)------> : 542375179 , 53 | data out ( 42)------> : 285386772 , 54 | data out ( 43)------> : 0 , 55 | data out ( 44)------> : -285386772 , 56 | data out ( 45)------> : -542375179 , 57 | data out ( 46)------> : -747021096 , 58 | data out ( 47)------> : -877794571 , 59 | data out ( 48)------> : -923106144 , 60 | data out ( 49)------> : -878057527 , 61 | data out ( 50)------> : -746595636 , 62 | data out ( 51)------> : -542800639 , 63 | data out ( 52)------> : -285123816 , 64 | data out ( 53)------> : 0 , 65 | data out ( 54)------> : 285123816 , 66 | data out ( 55)------> : 542800639 , 67 | data out ( 56)------> : 746595636 , 68 | data out ( 57)------> : 878057527 , 69 | data out ( 58)------> : 923106144 , 70 | data out ( 59)------> : 877794571 , 71 | data out ( 60)------> : 747021096 , 72 | data out ( 61)------> : 542375179 , 73 | data out ( 62)------> : 285386772 , 74 | data out ( 63)------> : 0 , 75 | data out ( 64)------> : -285386772 , 76 | data out ( 65)------> : -542375179 , 77 | data out ( 66)------> : -747021096 , 78 | data out ( 67)------> : -877794571 , 79 | data out ( 68)------> : -923106144 , 80 | data out ( 69)------> : -878057527 , 81 | data out ( 70)------> : -746595636 , 82 | data out ( 71)------> : -542800639 , 83 | data out ( 72)------> : -285123816 , 84 | data out ( 73)------> : 0 , 85 | data out ( 74)------> : 285123816 , 86 | data out ( 75)------> : 542800639 , 87 | data out ( 76)------> : 746595636 , 88 | data out ( 77)------> : 878057527 , 89 | data out ( 78)------> : 923106144 , 90 | data out ( 79)------> : 877794571 , 91 | data out ( 80)------> : 747021096 , 92 | data out ( 81)------> : 542375179 , 93 | data out ( 82)------> : 285386772 , 94 | data out ( 83)------> : 0 , 95 | data out ( 84)------> : -285386772 , 96 | data out ( 85)------> : -542375179 , 97 | data out ( 86)------> : -747021096 , 98 | data out ( 87)------> : -877794571 , 99 | data out ( 88)------> : -923106144 , 100 | data out ( 89)------> : -878057527 , 101 | data out ( 90)------> : -746595636 , 102 | data out ( 91)------> : -542800639 , 103 | data out ( 92)------> : -285123816 , 104 | data out ( 93)------> : 0 , 105 | data out ( 94)------> : 285123816 , 106 | data out ( 95)------> : 542800639 , 107 | data out ( 96)------> : 746595636 , 108 | data out ( 97)------> : 878057527 , 109 | data out ( 98)------> : 923106144 , 110 | data out ( 99)------> : 877794571 , 111 | data out ( 100)------> : 747021096 , 112 | data out ( 101)------> : 542375179 , 113 | data out ( 102)------> : 285386772 , 114 | data out ( 103)------> : 0 , 115 | data out ( 104)------> : -285386772 , 116 | data out ( 105)------> : -542375179 , 117 | data out ( 106)------> : -747021096 , 118 | data out ( 107)------> : -877794571 , 119 | data out ( 108)------> : -923106144 , 120 | data out ( 109)------> : -878057527 , 121 | data out ( 110)------> : -746595636 , 122 | data out ( 111)------> : -542800639 , 123 | data out ( 112)------> : -285123816 , 124 | data out ( 113)------> : 0 , 125 | data out ( 114)------> : 285123816 , 126 | data out ( 115)------> : 542800639 , 127 | data out ( 116)------> : 746595636 , 128 | data out ( 117)------> : 878057527 , 129 | data out ( 118)------> : 923106144 , 130 | data out ( 119)------> : 877794571 , 131 | data out ( 120)------> : 747021096 , 132 | data out ( 121)------> : 542375179 , 133 | data out ( 122)------> : 285386772 , 134 | data out ( 123)------> : 0 , 135 | data out ( 124)------> : -285386772 , 136 | data out ( 125)------> : -542375179 , 137 | data out ( 126)------> : -747021096 , 138 | data out ( 127)------> : -877794571 , 139 | data out ( 128)------> : -923106144 , 140 | data out ( 129)------> : -878057527 , 141 | data out ( 130)------> : -746595636 , 142 | data out ( 131)------> : -542800639 , 143 | data out ( 132)------> : -285123816 , 144 | data out ( 133)------> : 0 , 145 | data out ( 134)------> : 285123816 , 146 | data out ( 135)------> : 542800639 , 147 | data out ( 136)------> : 746595636 , 148 | data out ( 137)------> : 878057527 , 149 | data out ( 138)------> : 923106144 , 150 | data out ( 139)------> : 877794571 , 151 | data out ( 140)------> : 747021096 , 152 | data out ( 141)------> : 542375179 , 153 | data out ( 142)------> : 285386772 , 154 | data out ( 143)------> : 0 , 155 | data out ( 144)------> : -285386772 , 156 | data out ( 145)------> : -542375179 , 157 | data out ( 146)------> : -747021096 , 158 | data out ( 147)------> : -877794571 , 159 | data out ( 148)------> : -923106144 , 160 | data out ( 149)------> : -878057527 , 161 | data out ( 150)------> : -746595636 , 162 | data out ( 151)------> : -542800639 , 163 | data out ( 152)------> : -285123816 , 164 | data out ( 153)------> : 0 , 165 | data out ( 154)------> : 285123816 , 166 | data out ( 155)------> : 542800639 , 167 | data out ( 156)------> : 746595636 , 168 | data out ( 157)------> : 878057527 , 169 | data out ( 158)------> : 923106144 , 170 | data out ( 159)------> : 877794571 , 171 | data out ( 160)------> : 747021096 , 172 | data out ( 161)------> : 542375179 , 173 | data out ( 162)------> : 285386772 , 174 | data out ( 163)------> : 0 , 175 | data out ( 164)------> : -285386772 , 176 | data out ( 165)------> : -542375179 , 177 | data out ( 166)------> : -747021096 , 178 | data out ( 167)------> : -877794571 , 179 | data out ( 168)------> : -923106144 , 180 | data out ( 169)------> : -878057527 , 181 | data out ( 170)------> : -746595636 , 182 | data out ( 171)------> : -542800639 , 183 | data out ( 172)------> : -285123816 , 184 | data out ( 173)------> : 0 , 185 | data out ( 174)------> : 285123816 , 186 | data out ( 175)------> : 542800639 , 187 | data out ( 176)------> : 746595636 , 188 | data out ( 177)------> : 878057527 , 189 | data out ( 178)------> : 923106144 , 190 | data out ( 179)------> : 877794571 , 191 | data out ( 180)------> : 747021096 , 192 | data out ( 181)------> : 542375179 , 193 | data out ( 182)------> : 285386772 , 194 | data out ( 183)------> : 0 , 195 | data out ( 184)------> : -285386772 , 196 | data out ( 185)------> : -542375179 , 197 | data out ( 186)------> : -747021096 , 198 | data out ( 187)------> : -877794571 , 199 | data out ( 188)------> : -923106144 , 200 | data out ( 189)------> : -878057527 , 201 | data out ( 190)------> : -746595636 , 202 | data out ( 191)------> : -542800639 , 203 | data out ( 192)------> : -285123816 , 204 | data out ( 193)------> : 0 , 205 | data out ( 194)------> : 285123816 , 206 | data out ( 195)------> : 542800639 , 207 | data out ( 196)------> : 746595636 , 208 | data out ( 197)------> : 878057527 , 209 | data out ( 198)------> : 923106144 , 210 | data out ( 199)------> : 877794571 , 211 | data out ( 200)------> : 747021096 , 212 | data out ( 201)------> : 542375179 , 213 | data out ( 202)------> : 285386772 , 214 | data out ( 203)------> : 0 , 215 | data out ( 204)------> : -285386772 , 216 | data out ( 205)------> : -542375179 , 217 | data out ( 206)------> : -747021096 , 218 | data out ( 207)------> : -877794571 , 219 | data out ( 208)------> : -923106144 , 220 | data out ( 209)------> : -878057527 , 221 | data out ( 210)------> : -746595636 , 222 | data out ( 211)------> : -542800639 , 223 | data out ( 212)------> : -285123816 , 224 | data out ( 213)------> : 0 , 225 | data out ( 214)------> : 285123816 , 226 | data out ( 215)------> : 542800639 , 227 | data out ( 216)------> : 746595636 , 228 | data out ( 217)------> : 878057527 , 229 | data out ( 218)------> : 923106144 , 230 | data out ( 219)------> : 877794571 , 231 | data out ( 220)------> : 747021096 , 232 | data out ( 221)------> : 542375179 , 233 | data out ( 222)------> : 285386772 , 234 | data out ( 223)------> : 0 , 235 | data out ( 224)------> : -285386772 , 236 | data out ( 225)------> : -542375179 , 237 | data out ( 226)------> : -747021096 , 238 | data out ( 227)------> : -877794571 , 239 | data out ( 228)------> : -923106144 , 240 | data out ( 229)------> : -878057527 , 241 | data out ( 230)------> : -746595636 , 242 | data out ( 231)------> : -542800639 , 243 | data out ( 232)------> : -285123816 , 244 | data out ( 233)------> : 0 , 245 | data out ( 234)------> : 285123816 , 246 | data out ( 235)------> : 542800639 , 247 | data out ( 236)------> : 746595636 , 248 | data out ( 237)------> : 878057527 , 249 | data out ( 238)------> : 923106144 , 250 | data out ( 239)------> : 877794571 , 251 | data out ( 240)------> : 747021096 , 252 | data out ( 241)------> : 542375179 , 253 | data out ( 242)------> : 285386772 , 254 | data out ( 243)------> : 0 , 255 | data out ( 244)------> : -285386772 , 256 | data out ( 245)------> : -542375179 , 257 | data out ( 246)------> : x , 258 | data out ( 247)------> : x , 259 | data out ( 248)------> : x , 260 | data out ( 249)------> : x , 261 | -------------------------------------------------------------------------------- /project/isim/fir_tb_isim_beh.exe.sim/ISimEngine-DesignHierarchy.dbg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Grootzz/Verilog-FIR/3b332498ee356fe0e0a0554d3ca5f483909b4b05/project/isim/fir_tb_isim_beh.exe.sim/ISimEngine-DesignHierarchy.dbg -------------------------------------------------------------------------------- /project/isim/fir_tb_isim_beh.exe.sim/fir_tb_isim_beh.exe: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Grootzz/Verilog-FIR/3b332498ee356fe0e0a0554d3ca5f483909b4b05/project/isim/fir_tb_isim_beh.exe.sim/fir_tb_isim_beh.exe -------------------------------------------------------------------------------- /project/isim/fir_tb_isim_beh.exe.sim/isimcrash.log: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Grootzz/Verilog-FIR/3b332498ee356fe0e0a0554d3ca5f483909b4b05/project/isim/fir_tb_isim_beh.exe.sim/isimcrash.log -------------------------------------------------------------------------------- /project/isim/fir_tb_isim_beh.exe.sim/isimkernel.log: -------------------------------------------------------------------------------- 1 | Command line: 2 | fir_tb_isim_beh.exe 3 | -simmode gui 4 | -simrunnum 0 5 | -socket 1133 6 | 7 | Fri Aug 04 13:09:02 2017 8 | 9 | 10 | Elaboration Time: 0.109201 sec 11 | 12 | Current Memory Usage: 1162.33 Meg 13 | 14 | Total Signals : 18 15 | Total Nets : 335 16 | Total Signal Drivers : 26 17 | Total Blocks : 3 18 | Total Primitive Blocks : 2 19 | Total Processes : 39 20 | Total Traceable Variables : 32 21 | Total Scalar Nets and Variables : 5361 22 | 23 | Total Simulation Time: 0.249602 sec 24 | 25 | Current Memory Usage: 847.745 Meg 26 | 27 | Fri Aug 04 20:50:55 2017 28 | 29 | -------------------------------------------------------------------------------- /project/isim/fir_tb_isim_beh.exe.sim/libPortability.dll: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Grootzz/Verilog-FIR/3b332498ee356fe0e0a0554d3ca5f483909b4b05/project/isim/fir_tb_isim_beh.exe.sim/libPortability.dll -------------------------------------------------------------------------------- /project/isim/fir_tb_isim_beh.exe.sim/netId.dat: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Grootzz/Verilog-FIR/3b332498ee356fe0e0a0554d3ca5f483909b4b05/project/isim/fir_tb_isim_beh.exe.sim/netId.dat -------------------------------------------------------------------------------- /project/isim/fir_tb_isim_beh.exe.sim/tmp_save/_1: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Grootzz/Verilog-FIR/3b332498ee356fe0e0a0554d3ca5f483909b4b05/project/isim/fir_tb_isim_beh.exe.sim/tmp_save/_1 -------------------------------------------------------------------------------- /project/isim/fir_tb_isim_beh.exe.sim/work/fir_tb_isim_beh.exe_main.c: -------------------------------------------------------------------------------- 1 | /**********************************************************************/ 2 | /* ____ ____ */ 3 | /* / /\/ / */ 4 | /* /___/ \ / */ 5 | /* \ \ \/ */ 6 | /* \ \ Copyright (c) 2003-2009 Xilinx, Inc. */ 7 | /* / / All Right Reserved. */ 8 | /* /---/ /\ */ 9 | /* \ \ / \ */ 10 | /* \___\/\___\ */ 11 | /***********************************************************************/ 12 | 13 | #include "xsi.h" 14 | 15 | struct XSI_INFO xsi_info; 16 | 17 | 18 | 19 | int main(int argc, char **argv) 20 | { 21 | xsi_init_design(argc, argv); 22 | xsi_register_info(&xsi_info); 23 | 24 | xsi_register_min_prec_unit(-12); 25 | work_m_00000000000407611705_1143523637_init(); 26 | work_m_00000000000044543037_3538921338_init(); 27 | work_m_00000000004134447467_2073120511_init(); 28 | 29 | 30 | xsi_register_tops("work_m_00000000000044543037_3538921338"); 31 | xsi_register_tops("work_m_00000000004134447467_2073120511"); 32 | 33 | 34 | return xsi_run_simulation(argc, argv); 35 | 36 | } 37 | -------------------------------------------------------------------------------- /project/isim/fir_tb_isim_beh.exe.sim/work/fir_tb_isim_beh.exe_main.nt64.obj: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Grootzz/Verilog-FIR/3b332498ee356fe0e0a0554d3ca5f483909b4b05/project/isim/fir_tb_isim_beh.exe.sim/work/fir_tb_isim_beh.exe_main.nt64.obj -------------------------------------------------------------------------------- /project/isim/fir_tb_isim_beh.exe.sim/work/m_00000000000044543037_3538921338.c: -------------------------------------------------------------------------------- 1 | /**********************************************************************/ 2 | /* ____ ____ */ 3 | /* / /\/ / */ 4 | /* /___/ \ / */ 5 | /* \ \ \/ */ 6 | /* \ \ Copyright (c) 2003-2009 Xilinx, Inc. */ 7 | /* / / All Right Reserved. */ 8 | /* /---/ /\ */ 9 | /* \ \ / \ */ 10 | /* \___\/\___\ */ 11 | /***********************************************************************/ 12 | 13 | /* This file is designed for use with ISim build 0x7708f090 */ 14 | 15 | #define XSI_HIDE_SYMBOL_SPEC true 16 | #include "xsi.h" 17 | #include 18 | #ifdef __GNUC__ 19 | #include 20 | #else 21 | #include 22 | #define alloca _alloca 23 | #endif 24 | static const char *ng0 = "E:/ISEProjece/FirDesign/fir_tb.v"; 25 | static int ng1[] = {0, 0}; 26 | static int ng2[] = {1, 0}; 27 | static const char *ng3 = "E:/MatlabProject/databin.mem"; 28 | static int ng4[] = {242, 0}; 29 | static const char *ng5 = "dataout1.txt"; 30 | static const char *ng6 = "w"; 31 | static const char *ng7 = ""; 32 | static const char *ng8 = "data out (%d)------> : %d ,"; 33 | static int ng9[] = {250, 0}; 34 | 35 | 36 | 37 | static void Initial_44_0(char *t0) 38 | { 39 | char *t1; 40 | char *t2; 41 | char *t3; 42 | 43 | LAB0: t1 = (t0 + 3328U); 44 | t2 = *((char **)t1); 45 | if (t2 == 0) 46 | goto LAB2; 47 | 48 | LAB3: goto *t2; 49 | 50 | LAB2: xsi_set_current_line(44, ng0); 51 | 52 | LAB4: xsi_set_current_line(45, ng0); 53 | t2 = ((char*)((ng1))); 54 | t3 = (t0 + 1608); 55 | xsi_vlogvar_assign_value(t3, t2, 0, 0, 1); 56 | xsi_set_current_line(46, ng0); 57 | t2 = (t0 + 3136); 58 | xsi_process_wait(t2, 15000LL); 59 | *((char **)t1) = &&LAB5; 60 | 61 | LAB1: return; 62 | LAB5: xsi_set_current_line(47, ng0); 63 | t2 = ((char*)((ng2))); 64 | t3 = (t0 + 1608); 65 | xsi_vlogvar_assign_value(t3, t2, 0, 0, 1); 66 | goto LAB1; 67 | 68 | } 69 | 70 | static void Initial_51_1(char *t0) 71 | { 72 | char t4[8]; 73 | char *t1; 74 | char *t2; 75 | char *t3; 76 | char *t5; 77 | char *t6; 78 | char *t7; 79 | unsigned int t8; 80 | unsigned int t9; 81 | unsigned int t10; 82 | unsigned int t11; 83 | unsigned int t12; 84 | char *t13; 85 | char *t14; 86 | char *t15; 87 | unsigned int t16; 88 | unsigned int t17; 89 | unsigned int t18; 90 | unsigned int t19; 91 | unsigned int t20; 92 | unsigned int t21; 93 | unsigned int t22; 94 | unsigned int t23; 95 | char *t24; 96 | 97 | LAB0: t1 = (t0 + 3576U); 98 | t2 = *((char **)t1); 99 | if (t2 == 0) 100 | goto LAB2; 101 | 102 | LAB3: goto *t2; 103 | 104 | LAB2: xsi_set_current_line(51, ng0); 105 | 106 | LAB4: xsi_set_current_line(52, ng0); 107 | t2 = ((char*)((ng1))); 108 | t3 = (t0 + 1448); 109 | xsi_vlogvar_assign_value(t3, t2, 0, 0, 1); 110 | xsi_set_current_line(53, ng0); 111 | 112 | LAB5: xsi_set_current_line(53, ng0); 113 | t2 = (t0 + 3384); 114 | xsi_process_wait(t2, 10000LL); 115 | *((char **)t1) = &&LAB6; 116 | 117 | LAB1: return; 118 | LAB6: xsi_set_current_line(53, ng0); 119 | t3 = (t0 + 1448); 120 | t5 = (t3 + 56U); 121 | t6 = *((char **)t5); 122 | memset(t4, 0, 8); 123 | t7 = (t6 + 4); 124 | t8 = *((unsigned int *)t7); 125 | t9 = (~(t8)); 126 | t10 = *((unsigned int *)t6); 127 | t11 = (t10 & t9); 128 | t12 = (t11 & 1U); 129 | if (t12 != 0) 130 | goto LAB10; 131 | 132 | LAB8: if (*((unsigned int *)t7) == 0) 133 | goto LAB7; 134 | 135 | LAB9: t13 = (t4 + 4); 136 | *((unsigned int *)t4) = 1; 137 | *((unsigned int *)t13) = 1; 138 | 139 | LAB10: t14 = (t4 + 4); 140 | t15 = (t6 + 4); 141 | t16 = *((unsigned int *)t6); 142 | t17 = (~(t16)); 143 | *((unsigned int *)t4) = t17; 144 | *((unsigned int *)t14) = 0; 145 | if (*((unsigned int *)t15) != 0) 146 | goto LAB12; 147 | 148 | LAB11: t22 = *((unsigned int *)t4); 149 | *((unsigned int *)t4) = (t22 & 1U); 150 | t23 = *((unsigned int *)t14); 151 | *((unsigned int *)t14) = (t23 & 1U); 152 | t24 = (t0 + 1448); 153 | xsi_vlogvar_assign_value(t24, t4, 0, 0, 1); 154 | goto LAB5; 155 | 156 | LAB7: *((unsigned int *)t4) = 1; 157 | goto LAB10; 158 | 159 | LAB12: t18 = *((unsigned int *)t4); 160 | t19 = *((unsigned int *)t15); 161 | *((unsigned int *)t4) = (t18 | t19); 162 | t20 = *((unsigned int *)t14); 163 | t21 = *((unsigned int *)t15); 164 | *((unsigned int *)t14) = (t20 | t21); 165 | goto LAB11; 166 | 167 | LAB13: goto LAB1; 168 | 169 | } 170 | 171 | static void Initial_59_2(char *t0) 172 | { 173 | char *t1; 174 | 175 | LAB0: xsi_set_current_line(59, ng0); 176 | 177 | LAB2: xsi_set_current_line(60, ng0); 178 | t1 = (t0 + 1928); 179 | xsi_vlogfile_readmemb(ng3, 0, t1, 0, 0, 0, 0); 180 | 181 | LAB1: return; 182 | } 183 | 184 | static void Initial_65_3(char *t0) 185 | { 186 | char t6[8]; 187 | char t16[8]; 188 | char *t1; 189 | char *t2; 190 | char *t3; 191 | char *t4; 192 | char *t5; 193 | char *t7; 194 | unsigned int t8; 195 | unsigned int t9; 196 | unsigned int t10; 197 | unsigned int t11; 198 | unsigned int t12; 199 | char *t13; 200 | char *t14; 201 | char *t15; 202 | char *t17; 203 | char *t18; 204 | char *t19; 205 | char *t20; 206 | char *t21; 207 | char *t22; 208 | char *t23; 209 | char *t24; 210 | char *t25; 211 | char *t26; 212 | 213 | LAB0: t1 = (t0 + 4072U); 214 | t2 = *((char **)t1); 215 | if (t2 == 0) 216 | goto LAB2; 217 | 218 | LAB3: goto *t2; 219 | 220 | LAB2: xsi_set_current_line(65, ng0); 221 | 222 | LAB4: xsi_set_current_line(66, ng0); 223 | t2 = (t0 + 3880); 224 | xsi_process_wait(t2, 15000LL); 225 | *((char **)t1) = &&LAB5; 226 | 227 | LAB1: return; 228 | LAB5: xsi_set_current_line(67, ng0); 229 | xsi_set_current_line(67, ng0); 230 | t2 = ((char*)((ng1))); 231 | t3 = (t0 + 2088); 232 | xsi_vlogvar_assign_value(t3, t2, 0, 0, 32); 233 | 234 | LAB6: t2 = (t0 + 2088); 235 | t3 = (t2 + 56U); 236 | t4 = *((char **)t3); 237 | t5 = ((char*)((ng4))); 238 | memset(t6, 0, 8); 239 | xsi_vlog_signed_less(t6, 32, t4, 32, t5, 32); 240 | t7 = (t6 + 4); 241 | t8 = *((unsigned int *)t7); 242 | t9 = (~(t8)); 243 | t10 = *((unsigned int *)t6); 244 | t11 = (t10 & t9); 245 | t12 = (t11 != 0); 246 | if (t12 > 0) 247 | goto LAB7; 248 | 249 | LAB8: goto LAB1; 250 | 251 | LAB7: xsi_set_current_line(67, ng0); 252 | 253 | LAB9: xsi_set_current_line(68, ng0); 254 | t13 = (t0 + 1928); 255 | t14 = (t13 + 56U); 256 | t15 = *((char **)t14); 257 | t17 = (t0 + 1928); 258 | t18 = (t17 + 72U); 259 | t19 = *((char **)t18); 260 | t20 = (t0 + 1928); 261 | t21 = (t20 + 64U); 262 | t22 = *((char **)t21); 263 | t23 = (t0 + 2088); 264 | t24 = (t23 + 56U); 265 | t25 = *((char **)t24); 266 | xsi_vlog_generic_get_array_select_value(t16, 16, t15, t19, t22, 1, 1, t25, 32, 1); 267 | t26 = (t0 + 1768); 268 | xsi_vlogvar_assign_value(t26, t16, 0, 0, 16); 269 | xsi_set_current_line(69, ng0); 270 | t2 = (t0 + 3880); 271 | xsi_process_wait(t2, 20000LL); 272 | *((char **)t1) = &&LAB10; 273 | goto LAB1; 274 | 275 | LAB10: xsi_set_current_line(67, ng0); 276 | t2 = (t0 + 2088); 277 | t3 = (t2 + 56U); 278 | t4 = *((char **)t3); 279 | t5 = ((char*)((ng2))); 280 | memset(t6, 0, 8); 281 | xsi_vlog_signed_add(t6, 32, t4, 32, t5, 32); 282 | t7 = (t0 + 2088); 283 | xsi_vlogvar_assign_value(t7, t6, 0, 0, 32); 284 | goto LAB6; 285 | 286 | } 287 | 288 | static void Initial_76_4(char *t0) 289 | { 290 | char t1[8]; 291 | char *t2; 292 | char *t3; 293 | 294 | LAB0: xsi_set_current_line(76, ng0); 295 | 296 | LAB2: xsi_set_current_line(77, ng0); 297 | *((int *)t1) = xsi_vlogfile_file_open_of_cname_ctype(ng5, ng6); 298 | t2 = (t1 + 4); 299 | *((int *)t2) = 0; 300 | t3 = (t0 + 2248); 301 | xsi_vlogvar_assign_value(t3, t1, 0, 0, 32); 302 | 303 | LAB1: return; 304 | } 305 | 306 | static void Always_81_5(char *t0) 307 | { 308 | char *t1; 309 | char *t2; 310 | char *t3; 311 | char *t4; 312 | char *t5; 313 | char *t6; 314 | char *t7; 315 | char *t8; 316 | 317 | LAB0: t1 = (t0 + 4568U); 318 | t2 = *((char **)t1); 319 | if (t2 == 0) 320 | goto LAB2; 321 | 322 | LAB3: goto *t2; 323 | 324 | LAB2: xsi_set_current_line(81, ng0); 325 | t2 = (t0 + 5136); 326 | *((int *)t2) = 1; 327 | t3 = (t0 + 4600); 328 | *((char **)t3) = t2; 329 | *((char **)t1) = &&LAB4; 330 | 331 | LAB1: return; 332 | LAB4: xsi_set_current_line(81, ng0); 333 | 334 | LAB5: xsi_set_current_line(82, ng0); 335 | t4 = (t0 + 2248); 336 | t5 = (t4 + 56U); 337 | t6 = *((char **)t5); 338 | t7 = (t0 + 1048U); 339 | t8 = *((char **)t7); 340 | xsi_vlogfile_fwrite(*((unsigned int *)t6), 1, 0, 0, ng7, 2, t0, (char)119, t8, 32); 341 | goto LAB2; 342 | 343 | } 344 | 345 | static void Always_85_6(char *t0) 346 | { 347 | char t9[8]; 348 | char *t1; 349 | char *t2; 350 | char *t3; 351 | char *t4; 352 | char *t5; 353 | char *t6; 354 | char *t7; 355 | char *t8; 356 | unsigned int t10; 357 | unsigned int t11; 358 | unsigned int t12; 359 | unsigned int t13; 360 | unsigned int t14; 361 | char *t15; 362 | char *t16; 363 | 364 | LAB0: t1 = (t0 + 4816U); 365 | t2 = *((char **)t1); 366 | if (t2 == 0) 367 | goto LAB2; 368 | 369 | LAB3: goto *t2; 370 | 371 | LAB2: xsi_set_current_line(85, ng0); 372 | t2 = (t0 + 5152); 373 | *((int *)t2) = 1; 374 | t3 = (t0 + 4848); 375 | *((char **)t3) = t2; 376 | *((char **)t1) = &&LAB4; 377 | 378 | LAB1: return; 379 | LAB4: xsi_set_current_line(85, ng0); 380 | 381 | LAB5: xsi_set_current_line(86, ng0); 382 | t4 = (t0 + 2408); 383 | t5 = (t4 + 56U); 384 | t6 = *((char **)t5); 385 | t7 = (t0 + 1048U); 386 | t8 = *((char **)t7); 387 | xsi_vlogfile_write(1, 0, 0, ng8, 3, t0, (char)119, t6, 32, (char)119, t8, 32); 388 | xsi_set_current_line(87, ng0); 389 | t2 = (t0 + 2408); 390 | t3 = (t2 + 56U); 391 | t4 = *((char **)t3); 392 | t5 = ((char*)((ng2))); 393 | memset(t9, 0, 8); 394 | xsi_vlog_signed_add(t9, 32, t4, 32, t5, 32); 395 | t6 = (t0 + 2408); 396 | xsi_vlogvar_assign_value(t6, t9, 0, 0, 32); 397 | xsi_set_current_line(88, ng0); 398 | t2 = (t0 + 2408); 399 | t3 = (t2 + 56U); 400 | t4 = *((char **)t3); 401 | t5 = ((char*)((ng9))); 402 | memset(t9, 0, 8); 403 | xsi_vlog_signed_equal(t9, 32, t4, 32, t5, 32); 404 | t6 = (t9 + 4); 405 | t10 = *((unsigned int *)t6); 406 | t11 = (~(t10)); 407 | t12 = *((unsigned int *)t9); 408 | t13 = (t12 & t11); 409 | t14 = (t13 != 0); 410 | if (t14 > 0) 411 | goto LAB6; 412 | 413 | LAB7: 414 | LAB8: goto LAB2; 415 | 416 | LAB6: xsi_set_current_line(88, ng0); 417 | 418 | LAB9: xsi_set_current_line(89, ng0); 419 | t7 = (t0 + 4624); 420 | xsi_process_wait(t7, 20000LL); 421 | *((char **)t1) = &&LAB10; 422 | goto LAB1; 423 | 424 | LAB10: xsi_set_current_line(89, ng0); 425 | t8 = (t0 + 2248); 426 | t15 = (t8 + 56U); 427 | t16 = *((char **)t15); 428 | xsi_vlogfile_fclose(*((unsigned int *)t16)); 429 | xsi_set_current_line(90, ng0); 430 | t2 = ((char*)((ng1))); 431 | t3 = (t0 + 1608); 432 | xsi_vlogvar_assign_value(t3, t2, 0, 0, 1); 433 | xsi_set_current_line(91, ng0); 434 | t2 = (t0 + 4624); 435 | xsi_process_wait(t2, 20000LL); 436 | *((char **)t1) = &&LAB11; 437 | goto LAB1; 438 | 439 | LAB11: xsi_set_current_line(91, ng0); 440 | xsi_vlog_stop(1); 441 | goto LAB8; 442 | 443 | } 444 | 445 | 446 | extern void work_m_00000000000044543037_3538921338_init() 447 | { 448 | static char *pe[] = {(void *)Initial_44_0,(void *)Initial_51_1,(void *)Initial_59_2,(void *)Initial_65_3,(void *)Initial_76_4,(void *)Always_81_5,(void *)Always_85_6}; 449 | xsi_register_didat("work_m_00000000000044543037_3538921338", "isim/fir_tb_isim_beh.exe.sim/work/m_00000000000044543037_3538921338.didat"); 450 | xsi_register_executes(pe); 451 | } 452 | -------------------------------------------------------------------------------- /project/isim/fir_tb_isim_beh.exe.sim/work/m_00000000000044543037_3538921338.didat: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Grootzz/Verilog-FIR/3b332498ee356fe0e0a0554d3ca5f483909b4b05/project/isim/fir_tb_isim_beh.exe.sim/work/m_00000000000044543037_3538921338.didat -------------------------------------------------------------------------------- /project/isim/fir_tb_isim_beh.exe.sim/work/m_00000000000044543037_3538921338.nt64.obj: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Grootzz/Verilog-FIR/3b332498ee356fe0e0a0554d3ca5f483909b4b05/project/isim/fir_tb_isim_beh.exe.sim/work/m_00000000000044543037_3538921338.nt64.obj -------------------------------------------------------------------------------- /project/isim/fir_tb_isim_beh.exe.sim/work/m_00000000000407611705_1143523637.didat: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Grootzz/Verilog-FIR/3b332498ee356fe0e0a0554d3ca5f483909b4b05/project/isim/fir_tb_isim_beh.exe.sim/work/m_00000000000407611705_1143523637.didat -------------------------------------------------------------------------------- /project/isim/fir_tb_isim_beh.exe.sim/work/m_00000000000407611705_1143523637.nt64.obj: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Grootzz/Verilog-FIR/3b332498ee356fe0e0a0554d3ca5f483909b4b05/project/isim/fir_tb_isim_beh.exe.sim/work/m_00000000000407611705_1143523637.nt64.obj -------------------------------------------------------------------------------- /project/isim/fir_tb_isim_beh.exe.sim/work/m_00000000004134447467_2073120511.c: -------------------------------------------------------------------------------- 1 | /**********************************************************************/ 2 | /* ____ ____ */ 3 | /* / /\/ / */ 4 | /* /___/ \ / */ 5 | /* \ \ \/ */ 6 | /* \ \ Copyright (c) 2003-2009 Xilinx, Inc. */ 7 | /* / / All Right Reserved. */ 8 | /* /---/ /\ */ 9 | /* \ \ / \ */ 10 | /* \___\/\___\ */ 11 | /***********************************************************************/ 12 | 13 | /* This file is designed for use with ISim build 0x7708f090 */ 14 | 15 | #define XSI_HIDE_SYMBOL_SPEC true 16 | #include "xsi.h" 17 | #include 18 | #ifdef __GNUC__ 19 | #include 20 | #else 21 | #include 22 | #define alloca _alloca 23 | #endif 24 | static const char *ng0 = "D:/Xilinx/14.7/ISE_DS/ISE/verilog/src/glbl.v"; 25 | static unsigned int ng1[] = {1U, 0U}; 26 | static unsigned int ng2[] = {0U, 0U}; 27 | 28 | 29 | 30 | static void NetDecl_16_0(char *t0) 31 | { 32 | char *t1; 33 | char *t2; 34 | char *t3; 35 | char *t4; 36 | char *t5; 37 | char *t6; 38 | char *t7; 39 | unsigned int t8; 40 | unsigned int t9; 41 | char *t10; 42 | unsigned int t11; 43 | unsigned int t12; 44 | char *t13; 45 | unsigned int t14; 46 | unsigned int t15; 47 | char *t16; 48 | 49 | LAB0: t1 = (t0 + 6960U); 50 | t2 = *((char **)t1); 51 | if (t2 == 0) 52 | goto LAB2; 53 | 54 | LAB3: goto *t2; 55 | 56 | LAB2: xsi_set_current_line(16, ng0); 57 | t2 = (t0 + 1960U); 58 | t3 = *((char **)t2); 59 | t2 = (t0 + 8648); 60 | t4 = (t2 + 56U); 61 | t5 = *((char **)t4); 62 | t6 = (t5 + 56U); 63 | t7 = *((char **)t6); 64 | memset(t7, 0, 8); 65 | t8 = 1U; 66 | t9 = t8; 67 | t10 = (t3 + 4); 68 | t11 = *((unsigned int *)t3); 69 | t8 = (t8 & t11); 70 | t12 = *((unsigned int *)t10); 71 | t9 = (t9 & t12); 72 | t13 = (t7 + 4); 73 | t14 = *((unsigned int *)t7); 74 | *((unsigned int *)t7) = (t14 | t8); 75 | t15 = *((unsigned int *)t13); 76 | *((unsigned int *)t13) = (t15 | t9); 77 | xsi_driver_vfirst_trans(t2, 0, 0U); 78 | t16 = (t0 + 8520); 79 | *((int *)t16) = 1; 80 | 81 | LAB1: return; 82 | } 83 | 84 | static void Cont_48_1(char *t0) 85 | { 86 | char *t1; 87 | char *t2; 88 | char *t3; 89 | char *t4; 90 | char *t5; 91 | char *t6; 92 | char *t7; 93 | char *t8; 94 | char *t9; 95 | unsigned int t10; 96 | unsigned int t11; 97 | char *t12; 98 | unsigned int t13; 99 | unsigned int t14; 100 | char *t15; 101 | unsigned int t16; 102 | unsigned int t17; 103 | char *t18; 104 | 105 | LAB0: t1 = (t0 + 7208U); 106 | t2 = *((char **)t1); 107 | if (t2 == 0) 108 | goto LAB2; 109 | 110 | LAB3: goto *t2; 111 | 112 | LAB2: xsi_set_current_line(48, ng0); 113 | t2 = (t0 + 3640); 114 | t3 = (t2 + 56U); 115 | t4 = *((char **)t3); 116 | t5 = (t0 + 8712); 117 | t6 = (t5 + 56U); 118 | t7 = *((char **)t6); 119 | t8 = (t7 + 56U); 120 | t9 = *((char **)t8); 121 | memset(t9, 0, 8); 122 | t10 = 1U; 123 | t11 = t10; 124 | t12 = (t4 + 4); 125 | t13 = *((unsigned int *)t4); 126 | t10 = (t10 & t13); 127 | t14 = *((unsigned int *)t12); 128 | t11 = (t11 & t14); 129 | t15 = (t9 + 4); 130 | t16 = *((unsigned int *)t9); 131 | *((unsigned int *)t9) = (t16 | t10); 132 | t17 = *((unsigned int *)t15); 133 | *((unsigned int *)t15) = (t17 | t11); 134 | xsi_driver_vfirst_trans(t5, 0, 0); 135 | t18 = (t0 + 8536); 136 | *((int *)t18) = 1; 137 | 138 | LAB1: return; 139 | } 140 | 141 | static void Cont_49_2(char *t0) 142 | { 143 | char *t1; 144 | char *t2; 145 | char *t3; 146 | char *t4; 147 | char *t5; 148 | char *t6; 149 | char *t7; 150 | char *t8; 151 | char *t9; 152 | unsigned int t10; 153 | unsigned int t11; 154 | char *t12; 155 | unsigned int t13; 156 | unsigned int t14; 157 | char *t15; 158 | unsigned int t16; 159 | unsigned int t17; 160 | char *t18; 161 | 162 | LAB0: t1 = (t0 + 7456U); 163 | t2 = *((char **)t1); 164 | if (t2 == 0) 165 | goto LAB2; 166 | 167 | LAB3: goto *t2; 168 | 169 | LAB2: xsi_set_current_line(49, ng0); 170 | t2 = (t0 + 3800); 171 | t3 = (t2 + 56U); 172 | t4 = *((char **)t3); 173 | t5 = (t0 + 8776); 174 | t6 = (t5 + 56U); 175 | t7 = *((char **)t6); 176 | t8 = (t7 + 56U); 177 | t9 = *((char **)t8); 178 | memset(t9, 0, 8); 179 | t10 = 1U; 180 | t11 = t10; 181 | t12 = (t4 + 4); 182 | t13 = *((unsigned int *)t4); 183 | t10 = (t10 & t13); 184 | t14 = *((unsigned int *)t12); 185 | t11 = (t11 & t14); 186 | t15 = (t9 + 4); 187 | t16 = *((unsigned int *)t9); 188 | *((unsigned int *)t9) = (t16 | t10); 189 | t17 = *((unsigned int *)t15); 190 | *((unsigned int *)t15) = (t17 | t11); 191 | xsi_driver_vfirst_trans(t5, 0, 0); 192 | t18 = (t0 + 8552); 193 | *((int *)t18) = 1; 194 | 195 | LAB1: return; 196 | } 197 | 198 | static void Cont_50_3(char *t0) 199 | { 200 | char *t1; 201 | char *t2; 202 | char *t3; 203 | char *t4; 204 | char *t5; 205 | char *t6; 206 | char *t7; 207 | char *t8; 208 | char *t9; 209 | unsigned int t10; 210 | unsigned int t11; 211 | char *t12; 212 | unsigned int t13; 213 | unsigned int t14; 214 | char *t15; 215 | unsigned int t16; 216 | unsigned int t17; 217 | char *t18; 218 | 219 | LAB0: t1 = (t0 + 7704U); 220 | t2 = *((char **)t1); 221 | if (t2 == 0) 222 | goto LAB2; 223 | 224 | LAB3: goto *t2; 225 | 226 | LAB2: xsi_set_current_line(50, ng0); 227 | t2 = (t0 + 3960); 228 | t3 = (t2 + 56U); 229 | t4 = *((char **)t3); 230 | t5 = (t0 + 8840); 231 | t6 = (t5 + 56U); 232 | t7 = *((char **)t6); 233 | t8 = (t7 + 56U); 234 | t9 = *((char **)t8); 235 | memset(t9, 0, 8); 236 | t10 = 1U; 237 | t11 = t10; 238 | t12 = (t4 + 4); 239 | t13 = *((unsigned int *)t4); 240 | t10 = (t10 & t13); 241 | t14 = *((unsigned int *)t12); 242 | t11 = (t11 & t14); 243 | t15 = (t9 + 4); 244 | t16 = *((unsigned int *)t9); 245 | *((unsigned int *)t9) = (t16 | t10); 246 | t17 = *((unsigned int *)t15); 247 | *((unsigned int *)t15) = (t17 | t11); 248 | xsi_driver_vfirst_trans(t5, 0, 0); 249 | t18 = (t0 + 8568); 250 | *((int *)t18) = 1; 251 | 252 | LAB1: return; 253 | } 254 | 255 | static void Initial_52_4(char *t0) 256 | { 257 | char *t1; 258 | char *t2; 259 | char *t3; 260 | char *t4; 261 | 262 | LAB0: t1 = (t0 + 7952U); 263 | t2 = *((char **)t1); 264 | if (t2 == 0) 265 | goto LAB2; 266 | 267 | LAB3: goto *t2; 268 | 269 | LAB2: xsi_set_current_line(52, ng0); 270 | 271 | LAB4: xsi_set_current_line(53, ng0); 272 | t2 = ((char*)((ng1))); 273 | t3 = (t0 + 3640); 274 | xsi_vlogvar_assign_value(t3, t2, 0, 0, 1); 275 | xsi_set_current_line(54, ng0); 276 | t2 = ((char*)((ng1))); 277 | t3 = (t0 + 3960); 278 | xsi_vlogvar_assign_value(t3, t2, 0, 0, 1); 279 | xsi_set_current_line(55, ng0); 280 | t2 = (t0 + 7760); 281 | xsi_process_wait(t2, 100000LL); 282 | *((char **)t1) = &&LAB5; 283 | 284 | LAB1: return; 285 | LAB5: xsi_set_current_line(56, ng0); 286 | t3 = ((char*)((ng2))); 287 | t4 = (t0 + 3640); 288 | xsi_vlogvar_assign_value(t4, t3, 0, 0, 1); 289 | xsi_set_current_line(57, ng0); 290 | t2 = ((char*)((ng2))); 291 | t3 = (t0 + 3960); 292 | xsi_vlogvar_assign_value(t3, t2, 0, 0, 1); 293 | goto LAB1; 294 | 295 | } 296 | 297 | static void Initial_60_5(char *t0) 298 | { 299 | char *t1; 300 | char *t2; 301 | char *t3; 302 | char *t4; 303 | 304 | LAB0: t1 = (t0 + 8200U); 305 | t2 = *((char **)t1); 306 | if (t2 == 0) 307 | goto LAB2; 308 | 309 | LAB3: goto *t2; 310 | 311 | LAB2: xsi_set_current_line(60, ng0); 312 | 313 | LAB4: xsi_set_current_line(61, ng0); 314 | t2 = ((char*)((ng1))); 315 | t3 = (t0 + 3800); 316 | xsi_vlogvar_assign_value(t3, t2, 0, 0, 1); 317 | xsi_set_current_line(62, ng0); 318 | t2 = (t0 + 8008); 319 | xsi_process_wait(t2, 0LL); 320 | *((char **)t1) = &&LAB5; 321 | 322 | LAB1: return; 323 | LAB5: xsi_set_current_line(63, ng0); 324 | t3 = ((char*)((ng2))); 325 | t4 = (t0 + 3800); 326 | xsi_vlogvar_assign_value(t4, t3, 0, 0, 1); 327 | goto LAB1; 328 | 329 | } 330 | 331 | 332 | extern void work_m_00000000004134447467_2073120511_init() 333 | { 334 | static char *pe[] = {(void *)NetDecl_16_0,(void *)Cont_48_1,(void *)Cont_49_2,(void *)Cont_50_3,(void *)Initial_52_4,(void *)Initial_60_5}; 335 | xsi_register_didat("work_m_00000000004134447467_2073120511", "isim/fir_tb_isim_beh.exe.sim/work/m_00000000004134447467_2073120511.didat"); 336 | xsi_register_executes(pe); 337 | } 338 | -------------------------------------------------------------------------------- /project/isim/fir_tb_isim_beh.exe.sim/work/m_00000000004134447467_2073120511.didat: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Grootzz/Verilog-FIR/3b332498ee356fe0e0a0554d3ca5f483909b4b05/project/isim/fir_tb_isim_beh.exe.sim/work/m_00000000004134447467_2073120511.didat -------------------------------------------------------------------------------- /project/isim/fir_tb_isim_beh.exe.sim/work/m_00000000004134447467_2073120511.nt64.obj: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Grootzz/Verilog-FIR/3b332498ee356fe0e0a0554d3ca5f483909b4b05/project/isim/fir_tb_isim_beh.exe.sim/work/m_00000000004134447467_2073120511.nt64.obj -------------------------------------------------------------------------------- /project/isim/isim_usage_statistics.html: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 |
ISim Statistics
Xilinx HDL Libraries Used=
Fuse Resource Usage=374 ms, 28452 KB
Total Signals=18
Total Nets=335
Total Blocks=3
Total Processes=39
Total Simulation Time=5 us
Simulation Resource Usage=0.249602 sec, 665399 KB
Simulation Mode=gui
Hardware CoSim=0
17 | -------------------------------------------------------------------------------- /project/isim/pn_info: -------------------------------------------------------------------------------- 1 | 14.7 2 | -------------------------------------------------------------------------------- /project/isim/temp/fir.sdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Grootzz/Verilog-FIR/3b332498ee356fe0e0a0554d3ca5f483909b4b05/project/isim/temp/fir.sdb -------------------------------------------------------------------------------- /project/isim/temp/fir_tb.sdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Grootzz/Verilog-FIR/3b332498ee356fe0e0a0554d3ca5f483909b4b05/project/isim/temp/fir_tb.sdb -------------------------------------------------------------------------------- /project/isim/temp/glbl.sdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Grootzz/Verilog-FIR/3b332498ee356fe0e0a0554d3ca5f483909b4b05/project/isim/temp/glbl.sdb -------------------------------------------------------------------------------- /project/isim/work/fir.sdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Grootzz/Verilog-FIR/3b332498ee356fe0e0a0554d3ca5f483909b4b05/project/isim/work/fir.sdb -------------------------------------------------------------------------------- /project/isim/work/fir_tb.sdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Grootzz/Verilog-FIR/3b332498ee356fe0e0a0554d3ca5f483909b4b05/project/isim/work/fir_tb.sdb -------------------------------------------------------------------------------- /project/isim/work/glbl.sdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Grootzz/Verilog-FIR/3b332498ee356fe0e0a0554d3ca5f483909b4b05/project/isim/work/glbl.sdb -------------------------------------------------------------------------------- /project/result.wcfg: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | filter_out[31:0] 16 | filter_out[31:0] 17 | SIGNEDDECRADIX 18 | 19 | 20 | clk 21 | clk 22 | 23 | 24 | rst 25 | rst 26 | 27 | 28 | filter_in[15:0] 29 | filter_in[15:0] 30 | SIGNEDDECRADIX 31 | 32 | 33 | mem[241:0,15:0] 34 | mem[241:0,15:0] 35 | SIGNEDDECRADIX 36 | 37 | 38 | i[31:0] 39 | i[31:0] 40 | SIGNEDDECRADIX 41 | 42 | 43 | file[31:0] 44 | file[31:0] 45 | SIGNEDDECRADIX 46 | 47 | 48 | cnt[31:0] 49 | cnt[31:0] 50 | SIGNEDDECRADIX 51 | 52 | 53 | -------------------------------------------------------------------------------- /project/webtalk_pn.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 6 | 7 |
8 | 9 | 10 | 11 | 12 |
13 |
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49 | 50 | 51 | -------------------------------------------------------------------------------- /project/xilinxsim.ini: -------------------------------------------------------------------------------- 1 | work=isim/work 2 | -------------------------------------------------------------------------------- /project/xst/work/hdllib.ref: -------------------------------------------------------------------------------- 1 | MO fir NULL fir.v vlg75/fir.bin 1501811731 2 | -------------------------------------------------------------------------------- /project/xst/work/vlg75/fir.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Grootzz/Verilog-FIR/3b332498ee356fe0e0a0554d3ca5f483909b4b05/project/xst/work/vlg75/fir.bin --------------------------------------------------------------------------------