├── .github └── workflows │ └── ci.yml ├── .gitignore ├── .gitlab-ci.yml ├── README.md ├── docs ├── Lab1 │ ├── ALU_RegFile │ │ ├── ALU.md │ │ └── RegFile.md │ ├── FSM │ │ └── FSM.md │ └── Lab1.md ├── Lab2 │ └── Lab2.md ├── Lab3 │ ├── Lab3.md │ ├── attachment │ │ ├── divider_tb.v │ │ ├── multiplier_signed_starter.v │ │ └── multiplier_tb.v │ ├── divider.md │ ├── floating_point_adder.md │ ├── multiplier.md │ └── pic │ │ ├── multiplier_signed.png │ │ ├── multiplier_unsigned.png │ │ └── multiplier_v3.png ├── Lab4 │ ├── DataPath_CtrlUnit.md │ ├── Lab4.md │ ├── attachment │ │ ├── ImmGen.vcd │ │ ├── ImmGen_tb.v │ │ ├── ImmGen_tb_gen.py │ │ ├── Lab4_header.vh │ │ ├── SCPU_ctrl_tb.v │ │ ├── riscv-privileged-20211203.pdf │ │ ├── riscv-spec-20191213.pdf │ │ └── test.s │ ├── exception_interruption.md │ ├── instr_extension.md │ └── pic │ │ ├── 6_0.png │ │ ├── ecall_seg.png │ │ ├── ill_seg.png │ │ ├── int_seg.png │ │ ├── mcause.png │ │ ├── mepc.png │ │ ├── mstatus.png │ │ ├── mtval.png │ │ └── mtvec.png ├── Lab5 │ ├── Lab5.md │ ├── pipeline_basic.md │ └── pipeline_hazard.md ├── Other │ ├── Decoder_and_Testbench.md │ ├── RISC_V.md │ ├── Verilog_Simulation.md │ ├── about_git.md │ ├── attachment │ │ └── testbench_gen.py │ └── pic │ │ ├── 5_0.png │ │ ├── image-20220709133941789.png │ │ ├── image-20220709134207573.png │ │ ├── image-20220709134431211.png │ │ ├── image-20220709135134820.png │ │ ├── image-20220709135829566.png │ │ └── pic0.png ├── _css │ └── style.css ├── attachment │ └── 计组实验报告模板.zip ├── index.md └── warmup │ ├── Lab0.md │ ├── Vivado_installation.md │ └── pic │ ├── 00.png │ ├── 01.png │ ├── 02.png │ └── 03.png └── mkdocs.yml /.github/workflows/ci.yml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Guahao31/2023_CO/HEAD/.github/workflows/ci.yml -------------------------------------------------------------------------------- /.gitignore: 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