├── .gitattributes ├── .gitignore ├── COPYING ├── MANIFEST.in ├── docs ├── Makefile ├── conf.py ├── hdlmake.action.rst ├── hdlmake.fetch.rst ├── hdlmake.rst ├── hdlmake.tools.active_hdl.rst ├── hdlmake.tools.common.rst ├── hdlmake.tools.diamond.rst ├── hdlmake.tools.ghdl.rst ├── hdlmake.tools.ise.rst ├── hdlmake.tools.isim.rst ├── hdlmake.tools.iverilog.rst ├── hdlmake.tools.libero.rst ├── hdlmake.tools.modelsim.rst ├── hdlmake.tools.planahead.rst ├── hdlmake.tools.quartus.rst ├── hdlmake.tools.riviera.rst ├── hdlmake.tools.rst ├── hdlmake.tools.vivado.rst ├── hdlmake.util.rst ├── images │ ├── CERN_logo.jpg │ ├── GPLv3_logo.png │ ├── by-sa.png │ ├── gl_research.png │ └── ohr_logo.png ├── index.rst └── make.bat ├── ez_setup.py ├── hdlmake ├── .gitignore ├── __init__.py ├── __main__.py ├── _version.py ├── action │ ├── __init__.py │ ├── action.py │ ├── core.py │ └── tree.py ├── dep_file.py ├── env.py ├── fetch │ ├── __init__.py │ ├── constants.py │ ├── fetcher.py │ ├── git.py │ ├── local.py │ └── svn.py ├── manifest_parser │ ├── __init__.py │ ├── configparser.py │ └── variables.py ├── module │ ├── __init__.py │ ├── content.py │ ├── core.py │ └── module.py ├── module_pool.py ├── new_dep_solver.py ├── srcfile.py ├── tools │ ├── __init__.py │ ├── active_hdl.py │ ├── diamond.py │ ├── ghdl.py │ ├── icestorm.py │ ├── ise.py │ ├── isim.py │ ├── iverilog.py │ ├── libero.py │ ├── make_sim.py │ ├── make_syn.py │ ├── makefile.py │ ├── makefile_writer.py │ ├── modelsim.py │ ├── planahead.py │ ├── quartus.py │ ├── riviera.py │ ├── sim_makefile_support.py │ ├── vivado.py │ ├── vivado_sim.py │ └── xilinx.py ├── util │ ├── __init__.py │ ├── path.py │ ├── shell.py │ └── termcolor.py ├── vhdl_parser.py └── vlog_parser.py ├── setup.py └── tests └── counter ├── modules └── counter │ ├── verilog │ ├── Manifest.py │ └── counter.v │ └── vhdl │ ├── Manifest.py │ └── counter.vhd ├── sim ├── active_hdl │ ├── play_sim.do │ ├── verilog │ │ └── Manifest.py │ └── vhdl │ │ └── Manifest.py ├── ghdl │ └── vhdl │ │ └── Manifest.py ├── isim │ ├── isim_cmd │ ├── verilog │ │ └── Manifest.py │ └── vhdl │ │ └── Manifest.py ├── iverilog │ ├── verilog │ │ └── Manifest.py │ └── vhdl │ │ └── Manifest.py ├── modelsim │ ├── verilog │ │ └── Manifest.py │ ├── vhdl │ │ └── Manifest.py │ └── vsim.do ├── riviera │ ├── verilog │ │ └── Manifest.py │ ├── vhdl │ │ └── Manifest.py │ └── vsim.do └── vivado │ ├── verilog │ └── Manifest.py │ └── vhdl │ └── Manifest.py ├── syn ├── brevia2_dk_diamond │ ├── verilog │ │ └── Manifest.py │ └── vhdl │ │ └── Manifest.py ├── cyclone3_sk_quartus │ ├── verilog │ │ └── Manifest.py │ └── vhdl │ │ └── Manifest.py ├── icestick_icestorm │ └── verilog │ │ └── Manifest.py ├── proasic3_sk_libero │ ├── verilog │ │ └── Manifest.py │ └── vhdl │ │ └── Manifest.py ├── spec_v4_ise │ ├── verilog │ │ └── Manifest.py │ └── vhdl │ │ └── Manifest.py ├── spec_v4_planahead │ ├── verilog │ │ └── Manifest.py │ └── vhdl │ │ └── Manifest.py └── zedboard_vivado │ ├── verilog │ └── Manifest.py │ └── vhdl │ └── Manifest.py ├── testbench └── counter_tb │ ├── verilog │ ├── Manifest.py │ └── counter_tb.v │ └── vhdl │ ├── Manifest.py │ └── counter_tb.vhd └── top ├── brevia2_dk ├── brevia2_top.lpf ├── verilog │ ├── Manifest.py │ └── brevia2_top.v └── vhdl │ ├── Manifest.py │ └── brevia2_top.vhd ├── cyclone3_sk ├── module.tcl ├── pinout.tcl ├── verilog │ ├── Manifest.py │ └── cyclone3_top.v └── vhdl │ ├── Manifest.py │ └── cyclone3_top.vhd ├── icestick ├── icestick.pcf └── verilog │ ├── Manifest.py │ └── icestick_top.v ├── proasic3_sk ├── proasic3_top.pdc ├── proasic3_top.sdc ├── verilog │ ├── Manifest.py │ └── proasic3_top.v └── vhdl │ ├── Manifest.py │ └── proasic3_top.vhd ├── spec_v4 ├── spec_top.ucf ├── verilog │ ├── Manifest.py │ └── spec_top.v └── vhdl │ ├── Manifest.py │ └── spec_top.vhd └── zedboard ├── verilog ├── Manifest.py └── zedboard_top.v ├── vhdl ├── Manifest.py └── zedboard_top.vhd └── zedboard_top.xdc /.gitattributes: -------------------------------------------------------------------------------- 1 | hdlmake2 binary 2 | -------------------------------------------------------------------------------- /.gitignore: -------------------------------------------------------------------------------- 1 | misc 2 | src/build_hash.py 3 | examples 4 | hdlmake.pdf 5 | hdlmake.log 6 | *~ 7 | *.swp 8 | *.swap 9 | *.odt 10 | *.orig 11 | *.pyc 12 | *.egg-info/ 13 | .svn 14 | /pyenv/ 15 | /cyg_pyenv/ 16 | docs/_build 17 | dist/ 18 | build/ -------------------------------------------------------------------------------- /MANIFEST.in: -------------------------------------------------------------------------------- 1 | include COPYING 2 | include ez_setup.py 3 | recursive-include docs * 4 | recursive-include scripts * 5 | recursive-include tests * 6 | prune docs/_build 7 | -------------------------------------------------------------------------------- /docs/Makefile: -------------------------------------------------------------------------------- 1 | # Makefile for Sphinx documentation 2 | # 3 | 4 | # You can set these variables from the command line. 5 | SPHINXOPTS = 6 | SPHINXBUILD = sphinx-build 7 | PAPER = 8 | BUILDDIR = _build 9 | 10 | # User-friendly check for sphinx-build 11 | ifeq ($(shell which $(SPHINXBUILD) >/dev/null 2>&1; echo $$?), 1) 12 | $(error The '$(SPHINXBUILD)' command was not found. Make sure you have Sphinx installed, then set the SPHINXBUILD environment variable to point to the full path of the '$(SPHINXBUILD)' executable. Alternatively you can add the directory with the executable to your PATH. If you don't have Sphinx installed, grab it from http://sphinx-doc.org/) 13 | endif 14 | 15 | # Internal variables. 16 | PAPEROPT_a4 = -D latex_paper_size=a4 17 | PAPEROPT_letter = -D latex_paper_size=letter 18 | ALLSPHINXOPTS = -d $(BUILDDIR)/doctrees $(PAPEROPT_$(PAPER)) $(SPHINXOPTS) . 19 | # the i18n builder cannot share the environment and doctrees with the others 20 | I18NSPHINXOPTS = $(PAPEROPT_$(PAPER)) $(SPHINXOPTS) . 21 | 22 | .PHONY: help clean html dirhtml singlehtml pickle json htmlhelp qthelp devhelp epub latex latexpdf text man changes linkcheck doctest gettext 23 | 24 | help: 25 | @echo "Please use \`make ' where is one of" 26 | @echo " html to make standalone HTML files" 27 | @echo " dirhtml to make HTML files named index.html in directories" 28 | @echo " singlehtml to make a single large HTML file" 29 | @echo " pickle to make pickle files" 30 | @echo " json to make JSON files" 31 | @echo " htmlhelp to make HTML files and a HTML help project" 32 | @echo " qthelp to make HTML files and a qthelp project" 33 | @echo " devhelp to make HTML files and a Devhelp project" 34 | @echo " epub to make an epub" 35 | @echo " latex to make LaTeX files, you can set PAPER=a4 or PAPER=letter" 36 | @echo " latexpdf to make LaTeX files and run them through pdflatex" 37 | @echo " latexpdfja to make LaTeX files and run them through platex/dvipdfmx" 38 | @echo " text to make text files" 39 | @echo " man to make manual pages" 40 | @echo " texinfo to make Texinfo files" 41 | @echo " info to make Texinfo files and run them through makeinfo" 42 | @echo " gettext to make PO message catalogs" 43 | @echo " changes to make an overview of all changed/added/deprecated items" 44 | @echo " xml to make Docutils-native XML files" 45 | @echo " pseudoxml to make pseudoxml-XML files for display purposes" 46 | @echo " linkcheck to check all external links for integrity" 47 | @echo " doctest to run all doctests embedded in the documentation (if enabled)" 48 | 49 | clean: 50 | rm -rf $(BUILDDIR)/* 51 | 52 | html: 53 | $(SPHINXBUILD) -b html $(ALLSPHINXOPTS) $(BUILDDIR)/html 54 | @echo 55 | @echo "Build finished. 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The epub file is in $(BUILDDIR)/epub." 105 | 106 | latex: 107 | $(SPHINXBUILD) -b latex $(ALLSPHINXOPTS) $(BUILDDIR)/latex 108 | @echo 109 | @echo "Build finished; the LaTeX files are in $(BUILDDIR)/latex." 110 | @echo "Run \`make' in that directory to run these through (pdf)latex" \ 111 | "(use \`make latexpdf' here to do that automatically)." 112 | 113 | latexpdf: 114 | $(SPHINXBUILD) -b latex $(ALLSPHINXOPTS) $(BUILDDIR)/latex 115 | @echo "Running LaTeX files through pdflatex..." 116 | $(MAKE) -C $(BUILDDIR)/latex all-pdf 117 | @echo "pdflatex finished; the PDF files are in $(BUILDDIR)/latex." 118 | 119 | latexpdfja: 120 | $(SPHINXBUILD) -b latex $(ALLSPHINXOPTS) $(BUILDDIR)/latex 121 | @echo "Running LaTeX files through platex and dvipdfmx..." 122 | $(MAKE) -C $(BUILDDIR)/latex all-pdf-ja 123 | @echo "pdflatex finished; the PDF files are in $(BUILDDIR)/latex." 124 | 125 | text: 126 | $(SPHINXBUILD) -b text $(ALLSPHINXOPTS) $(BUILDDIR)/text 127 | @echo 128 | @echo "Build finished. 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The message catalogs are in $(BUILDDIR)/locale." 152 | 153 | changes: 154 | $(SPHINXBUILD) -b changes $(ALLSPHINXOPTS) $(BUILDDIR)/changes 155 | @echo 156 | @echo "The overview file is in $(BUILDDIR)/changes." 157 | 158 | linkcheck: 159 | $(SPHINXBUILD) -b linkcheck $(ALLSPHINXOPTS) $(BUILDDIR)/linkcheck 160 | @echo 161 | @echo "Link check complete; look for any errors in the above output " \ 162 | "or in $(BUILDDIR)/linkcheck/output.txt." 163 | 164 | doctest: 165 | $(SPHINXBUILD) -b doctest $(ALLSPHINXOPTS) $(BUILDDIR)/doctest 166 | @echo "Testing of doctests in the sources finished, look at the " \ 167 | "results in $(BUILDDIR)/doctest/output.txt." 168 | 169 | xml: 170 | $(SPHINXBUILD) -b xml $(ALLSPHINXOPTS) $(BUILDDIR)/xml 171 | @echo 172 | @echo "Build finished. The XML files are in $(BUILDDIR)/xml." 173 | 174 | pseudoxml: 175 | $(SPHINXBUILD) -b pseudoxml $(ALLSPHINXOPTS) $(BUILDDIR)/pseudoxml 176 | @echo 177 | @echo "Build finished. The pseudo-XML files are in $(BUILDDIR)/pseudoxml." 178 | -------------------------------------------------------------------------------- /docs/hdlmake.action.rst: -------------------------------------------------------------------------------- 1 | hdlmake.action package 2 | ====================== 3 | 4 | Submodules 5 | ---------- 6 | 7 | hdlmake.action.action module 8 | ---------------------------- 9 | 10 | .. automodule:: hdlmake.action.action 11 | :members: 12 | :undoc-members: 13 | :show-inheritance: 14 | 15 | hdlmake.action.core module 16 | ------------------------------------- 17 | 18 | .. automodule:: hdlmake.action.core 19 | :members: 20 | :undoc-members: 21 | :show-inheritance: 22 | 23 | hdlmake.action.tree module 24 | ------------------------------------ 25 | 26 | .. automodule:: hdlmake.action.tree 27 | :members: 28 | :undoc-members: 29 | :show-inheritance: 30 | 31 | hdlmake.action.qsys_hw_tcl_update module 32 | ---------------------------------------- 33 | 34 | .. automodule:: hdlmake.action.qsys_hw_tcl_update 35 | :members: 36 | :undoc-members: 37 | :show-inheritance: 38 | 39 | 40 | Module contents 41 | --------------- 42 | 43 | .. automodule:: hdlmake.action 44 | :members: 45 | :undoc-members: 46 | :show-inheritance: 47 | -------------------------------------------------------------------------------- /docs/hdlmake.fetch.rst: -------------------------------------------------------------------------------- 1 | hdlmake.fetch package 2 | ===================== 3 | 4 | Submodules 5 | ---------- 6 | 7 | hdlmake.fetch.backend_factory module 8 | ------------------------------------ 9 | 10 | .. automodule:: hdlmake.fetch.backend_factory 11 | :members: 12 | :undoc-members: 13 | :show-inheritance: 14 | 15 | hdlmake.fetch.constants module 16 | ------------------------------ 17 | 18 | .. automodule:: hdlmake.fetch.constants 19 | :members: 20 | :undoc-members: 21 | :show-inheritance: 22 | 23 | hdlmake.fetch.fetcher module 24 | ---------------------------- 25 | 26 | .. automodule:: hdlmake.fetch.fetcher 27 | :members: 28 | :undoc-members: 29 | :show-inheritance: 30 | 31 | hdlmake.fetch.git module 32 | ------------------------ 33 | 34 | .. automodule:: hdlmake.fetch.git 35 | :members: 36 | :undoc-members: 37 | :show-inheritance: 38 | 39 | hdlmake.fetch.svn module 40 | ------------------------ 41 | 42 | .. automodule:: hdlmake.fetch.svn 43 | :members: 44 | :undoc-members: 45 | :show-inheritance: 46 | 47 | 48 | Module contents 49 | --------------- 50 | 51 | .. automodule:: hdlmake.fetch 52 | :members: 53 | :undoc-members: 54 | :show-inheritance: 55 | -------------------------------------------------------------------------------- /docs/hdlmake.rst: -------------------------------------------------------------------------------- 1 | hdlmake package 2 | =============== 3 | 4 | Subpackages 5 | ----------- 6 | 7 | .. toctree:: 8 | 9 | hdlmake.action 10 | hdlmake.fetch 11 | hdlmake.tools 12 | hdlmake.util 13 | 14 | Submodules 15 | ---------- 16 | 17 | hdlmake.dep_file module 18 | ----------------------- 19 | 20 | .. automodule:: hdlmake.dep_file 21 | :members: 22 | :undoc-members: 23 | :show-inheritance: 24 | 25 | hdlmake.new_dep_solver module 26 | ------------------------- 27 | 28 | .. automodule:: hdlmake.new_dep_solver 29 | :members: 30 | :undoc-members: 31 | :show-inheritance: 32 | 33 | hdlmake.env module 34 | ------------------ 35 | 36 | .. automodule:: hdlmake.env 37 | :members: 38 | :undoc-members: 39 | :show-inheritance: 40 | 41 | hdlmake.manifest_parser module 42 | ------------------------------ 43 | 44 | .. automodule:: hdlmake.manifest_parser 45 | :members: 46 | :undoc-members: 47 | :show-inheritance: 48 | 49 | hdlmake.module module 50 | --------------------- 51 | 52 | .. automodule:: hdlmake.module 53 | :members: 54 | :undoc-members: 55 | :show-inheritance: 56 | 57 | hdlmake.module_pool module 58 | -------------------------- 59 | 60 | .. automodule:: hdlmake.module_pool 61 | :members: 62 | :undoc-members: 63 | :show-inheritance: 64 | 65 | hdlmake.srcfile module 66 | ---------------------- 67 | 68 | .. automodule:: hdlmake.srcfile 69 | :members: 70 | :undoc-members: 71 | :show-inheritance: 72 | 73 | hdlmake.vhdl_parser module 74 | -------------------------- 75 | 76 | .. automodule:: hdlmake.vhdl_parser 77 | :members: 78 | :undoc-members: 79 | :show-inheritance: 80 | 81 | hdlmake.vlog_parser module 82 | -------------------------- 83 | 84 | .. automodule:: hdlmake.vlog_parser 85 | :members: 86 | :undoc-members: 87 | :show-inheritance: 88 | 89 | 90 | Module contents 91 | --------------- 92 | 93 | .. automodule:: hdlmake 94 | :members: 95 | :undoc-members: 96 | :show-inheritance: 97 | -------------------------------------------------------------------------------- /docs/hdlmake.tools.active_hdl.rst: -------------------------------------------------------------------------------- 1 | hdlmake.tools.active_hdl package 2 | =========================== 3 | 4 | Module contents 5 | --------------- 6 | 7 | .. automodule:: hdlmake.tools.active_hdl 8 | :members: 9 | :undoc-members: 10 | :show-inheritance: 11 | -------------------------------------------------------------------------------- /docs/hdlmake.tools.common.rst: -------------------------------------------------------------------------------- 1 | hdlmake.tools.sim_makefile_support package 2 | ========================================== 3 | 4 | Module contents 5 | --------------- 6 | 7 | .. automodule:: hdlmake.tools.sim_makefile_support 8 | :members: 9 | :undoc-members: 10 | :show-inheritance: 11 | -------------------------------------------------------------------------------- /docs/hdlmake.tools.diamond.rst: -------------------------------------------------------------------------------- 1 | hdlmake.tools.diamond package 2 | ============================= 3 | 4 | Module contents 5 | --------------- 6 | 7 | .. automodule:: hdlmake.tools.diamond 8 | :members: 9 | :undoc-members: 10 | :show-inheritance: 11 | -------------------------------------------------------------------------------- /docs/hdlmake.tools.ghdl.rst: -------------------------------------------------------------------------------- 1 | hdlmake.tools.ghdl package 2 | ========================== 3 | 4 | Module contents 5 | --------------- 6 | 7 | .. automodule:: hdlmake.tools.ghdl 8 | :members: 9 | :undoc-members: 10 | :show-inheritance: 11 | -------------------------------------------------------------------------------- /docs/hdlmake.tools.ise.rst: -------------------------------------------------------------------------------- 1 | hdlmake.tools.ise package 2 | ========================= 3 | 4 | Module contents 5 | --------------- 6 | 7 | .. automodule:: hdlmake.tools.ise 8 | :members: 9 | :undoc-members: 10 | :show-inheritance: 11 | -------------------------------------------------------------------------------- /docs/hdlmake.tools.isim.rst: -------------------------------------------------------------------------------- 1 | hdlmake.tools.isim package 2 | ========================== 3 | 4 | Module contents 5 | --------------- 6 | 7 | .. automodule:: hdlmake.tools.isim 8 | :members: 9 | :undoc-members: 10 | :show-inheritance: 11 | -------------------------------------------------------------------------------- /docs/hdlmake.tools.iverilog.rst: -------------------------------------------------------------------------------- 1 | hdlmake.tools.iverilog package 2 | ============================== 3 | 4 | Module contents 5 | --------------- 6 | 7 | .. automodule:: hdlmake.tools.iverilog 8 | :members: 9 | :undoc-members: 10 | :show-inheritance: 11 | -------------------------------------------------------------------------------- /docs/hdlmake.tools.libero.rst: -------------------------------------------------------------------------------- 1 | hdlmake.tools.libero package 2 | ============================ 3 | 4 | Module contents 5 | --------------- 6 | 7 | .. automodule:: hdlmake.tools.libero 8 | :members: 9 | :undoc-members: 10 | :show-inheritance: 11 | -------------------------------------------------------------------------------- /docs/hdlmake.tools.modelsim.rst: -------------------------------------------------------------------------------- 1 | hdlmake.tools.modelsim package 2 | ============================== 3 | 4 | Module contents 5 | --------------- 6 | 7 | .. automodule:: hdlmake.tools.modelsim 8 | :members: 9 | :undoc-members: 10 | :show-inheritance: 11 | -------------------------------------------------------------------------------- /docs/hdlmake.tools.planahead.rst: -------------------------------------------------------------------------------- 1 | hdlmake.tools.planahead package 2 | =============================== 3 | 4 | Module contents 5 | --------------- 6 | 7 | .. automodule:: hdlmake.tools.planahead 8 | :members: 9 | :undoc-members: 10 | :show-inheritance: 11 | -------------------------------------------------------------------------------- /docs/hdlmake.tools.quartus.rst: -------------------------------------------------------------------------------- 1 | hdlmake.tools.quartus package 2 | ============================= 3 | 4 | Module contents 5 | --------------- 6 | 7 | .. automodule:: hdlmake.tools.quartus 8 | :members: 9 | :undoc-members: 10 | :show-inheritance: 11 | -------------------------------------------------------------------------------- /docs/hdlmake.tools.riviera.rst: -------------------------------------------------------------------------------- 1 | hdlmake.tools.riviera package 2 | ============================= 3 | 4 | Module contents 5 | --------------- 6 | 7 | .. automodule:: hdlmake.tools.riviera 8 | :members: 9 | :undoc-members: 10 | :show-inheritance: 11 | -------------------------------------------------------------------------------- /docs/hdlmake.tools.rst: -------------------------------------------------------------------------------- 1 | hdlmake.tools package 2 | ===================== 3 | 4 | Subpackages 5 | ----------- 6 | 7 | .. toctree:: 8 | 9 | hdlmake.tools.active_hdl 10 | hdlmake.tools.common 11 | hdlmake.tools.diamond 12 | hdlmake.tools.ghdl 13 | hdlmake.tools.ise 14 | hdlmake.tools.isim 15 | hdlmake.tools.iverilog 16 | hdlmake.tools.libero 17 | hdlmake.tools.modelsim 18 | hdlmake.tools.planahead 19 | hdlmake.tools.quartus 20 | hdlmake.tools.riviera 21 | hdlmake.tools.vivado 22 | 23 | Module contents 24 | --------------- 25 | 26 | .. automodule:: hdlmake.tools 27 | :members: 28 | :undoc-members: 29 | :show-inheritance: 30 | -------------------------------------------------------------------------------- /docs/hdlmake.tools.vivado.rst: -------------------------------------------------------------------------------- 1 | hdlmake.tools.vivado package 2 | ============================ 3 | 4 | Module contents 5 | --------------- 6 | 7 | .. automodule:: hdlmake.tools.vivado 8 | :members: 9 | :undoc-members: 10 | :show-inheritance: 11 | -------------------------------------------------------------------------------- /docs/hdlmake.util.rst: -------------------------------------------------------------------------------- 1 | hdlmake.util package 2 | ==================== 3 | 4 | Submodules 5 | ---------- 6 | 7 | hdlmake.util.path module 8 | ------------------------ 9 | 10 | .. automodule:: hdlmake.util.path 11 | :members: 12 | :undoc-members: 13 | :show-inheritance: 14 | 15 | hdlmake.util.termcolor module 16 | ----------------------------- 17 | 18 | .. automodule:: hdlmake.util.termcolor 19 | :members: 20 | :undoc-members: 21 | :show-inheritance: 22 | 23 | 24 | Module contents 25 | --------------- 26 | 27 | .. automodule:: hdlmake.util 28 | :members: 29 | :undoc-members: 30 | :show-inheritance: 31 | -------------------------------------------------------------------------------- /docs/images/CERN_logo.jpg: -------------------------------------------------------------------------------- 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https://raw.githubusercontent.com/HDLMake/hdl-make/a6fb09a7e0d6fe646fa9eff86e1e2445f3d3c539/docs/images/gl_research.png -------------------------------------------------------------------------------- /docs/images/ohr_logo.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/HDLMake/hdl-make/a6fb09a7e0d6fe646fa9eff86e1e2445f3d3c539/docs/images/ohr_logo.png -------------------------------------------------------------------------------- /docs/make.bat: -------------------------------------------------------------------------------- 1 | @ECHO OFF 2 | 3 | REM Command file for Sphinx documentation 4 | 5 | if "%SPHINXBUILD%" == "" ( 6 | set SPHINXBUILD=sphinx-build 7 | ) 8 | set BUILDDIR=_build 9 | set ALLSPHINXOPTS=-d %BUILDDIR%/doctrees %SPHINXOPTS% . 10 | set I18NSPHINXOPTS=%SPHINXOPTS% . 11 | if NOT "%PAPER%" == "" ( 12 | set ALLSPHINXOPTS=-D latex_paper_size=%PAPER% %ALLSPHINXOPTS% 13 | set I18NSPHINXOPTS=-D latex_paper_size=%PAPER% %I18NSPHINXOPTS% 14 | ) 15 | 16 | if "%1" == "" goto help 17 | 18 | if "%1" == "help" ( 19 | :help 20 | echo.Please use `make ^` where ^ is one of 21 | echo. html to make standalone HTML files 22 | echo. dirhtml to make HTML files named index.html in directories 23 | echo. singlehtml to make a single large HTML file 24 | echo. pickle to make pickle files 25 | echo. json to make JSON files 26 | echo. htmlhelp to make HTML files and a HTML help project 27 | echo. qthelp to make HTML files and a qthelp project 28 | echo. devhelp to make HTML files and a Devhelp project 29 | echo. epub to make an epub 30 | echo. latex to make LaTeX files, you can set PAPER=a4 or PAPER=letter 31 | echo. text to make text files 32 | echo. man to make manual pages 33 | echo. texinfo to make Texinfo files 34 | echo. gettext to make PO message catalogs 35 | echo. changes to make an overview over all changed/added/deprecated items 36 | echo. xml to make Docutils-native XML files 37 | echo. pseudoxml to make pseudoxml-XML files for display purposes 38 | echo. linkcheck to check all external links for integrity 39 | echo. doctest to run all doctests embedded in the documentation if enabled 40 | goto end 41 | ) 42 | 43 | if "%1" == "clean" ( 44 | for /d %%i in (%BUILDDIR%\*) do rmdir /q /s %%i 45 | del /q /s %BUILDDIR%\* 46 | goto end 47 | ) 48 | 49 | 50 | %SPHINXBUILD% 2> nul 51 | if errorlevel 9009 ( 52 | echo. 53 | echo.The 'sphinx-build' command was not found. Make sure you have Sphinx 54 | echo.installed, then set the SPHINXBUILD environment variable to point 55 | echo.to the full path of the 'sphinx-build' executable. Alternatively you 56 | echo.may add the Sphinx directory to PATH. 57 | echo. 58 | echo.If you don't have Sphinx installed, grab it from 59 | echo.http://sphinx-doc.org/ 60 | exit /b 1 61 | ) 62 | 63 | if "%1" == "html" ( 64 | %SPHINXBUILD% -b html %ALLSPHINXOPTS% %BUILDDIR%/html 65 | if errorlevel 1 exit /b 1 66 | echo. 67 | echo.Build finished. The HTML pages are in %BUILDDIR%/html. 68 | goto end 69 | ) 70 | 71 | if "%1" == "dirhtml" ( 72 | %SPHINXBUILD% -b dirhtml %ALLSPHINXOPTS% %BUILDDIR%/dirhtml 73 | if errorlevel 1 exit /b 1 74 | echo. 75 | echo.Build finished. The HTML pages are in %BUILDDIR%/dirhtml. 76 | goto end 77 | ) 78 | 79 | if "%1" == "singlehtml" ( 80 | %SPHINXBUILD% -b singlehtml %ALLSPHINXOPTS% %BUILDDIR%/singlehtml 81 | if errorlevel 1 exit /b 1 82 | echo. 83 | echo.Build finished. The HTML pages are in %BUILDDIR%/singlehtml. 84 | goto end 85 | ) 86 | 87 | if "%1" == "pickle" ( 88 | %SPHINXBUILD% -b pickle %ALLSPHINXOPTS% %BUILDDIR%/pickle 89 | if errorlevel 1 exit /b 1 90 | echo. 91 | echo.Build finished; now you can process the pickle files. 92 | goto end 93 | ) 94 | 95 | if "%1" == "json" ( 96 | %SPHINXBUILD% -b json %ALLSPHINXOPTS% %BUILDDIR%/json 97 | if errorlevel 1 exit /b 1 98 | echo. 99 | echo.Build finished; now you can process the JSON files. 100 | goto end 101 | ) 102 | 103 | if "%1" == "htmlhelp" ( 104 | %SPHINXBUILD% -b htmlhelp %ALLSPHINXOPTS% %BUILDDIR%/htmlhelp 105 | if errorlevel 1 exit /b 1 106 | echo. 107 | echo.Build finished; now you can run HTML Help Workshop with the ^ 108 | .hhp project file in %BUILDDIR%/htmlhelp. 109 | goto end 110 | ) 111 | 112 | if "%1" == "qthelp" ( 113 | %SPHINXBUILD% -b qthelp %ALLSPHINXOPTS% %BUILDDIR%/qthelp 114 | if errorlevel 1 exit /b 1 115 | echo. 116 | echo.Build finished; now you can run "qcollectiongenerator" with the ^ 117 | .qhcp project file in %BUILDDIR%/qthelp, like this: 118 | echo.^> qcollectiongenerator %BUILDDIR%\qthelp\hdlmake.qhcp 119 | echo.To view the help file: 120 | echo.^> assistant -collectionFile %BUILDDIR%\qthelp\hdlmake.ghc 121 | goto end 122 | ) 123 | 124 | if "%1" == "devhelp" ( 125 | %SPHINXBUILD% -b devhelp %ALLSPHINXOPTS% %BUILDDIR%/devhelp 126 | if errorlevel 1 exit /b 1 127 | echo. 128 | echo.Build finished. 129 | goto end 130 | ) 131 | 132 | if "%1" == "epub" ( 133 | %SPHINXBUILD% -b epub %ALLSPHINXOPTS% %BUILDDIR%/epub 134 | if errorlevel 1 exit /b 1 135 | echo. 136 | echo.Build finished. The epub file is in %BUILDDIR%/epub. 137 | goto end 138 | ) 139 | 140 | if "%1" == "latex" ( 141 | %SPHINXBUILD% -b latex %ALLSPHINXOPTS% %BUILDDIR%/latex 142 | if errorlevel 1 exit /b 1 143 | echo. 144 | echo.Build finished; the LaTeX files are in %BUILDDIR%/latex. 145 | goto end 146 | ) 147 | 148 | if "%1" == "latexpdf" ( 149 | %SPHINXBUILD% -b latex %ALLSPHINXOPTS% %BUILDDIR%/latex 150 | cd %BUILDDIR%/latex 151 | make all-pdf 152 | cd %BUILDDIR%/.. 153 | echo. 154 | echo.Build finished; the PDF files are in %BUILDDIR%/latex. 155 | goto end 156 | ) 157 | 158 | if "%1" == "latexpdfja" ( 159 | %SPHINXBUILD% -b latex %ALLSPHINXOPTS% %BUILDDIR%/latex 160 | cd %BUILDDIR%/latex 161 | make all-pdf-ja 162 | cd %BUILDDIR%/.. 163 | echo. 164 | echo.Build finished; the PDF files are in %BUILDDIR%/latex. 165 | goto end 166 | ) 167 | 168 | if "%1" == "text" ( 169 | %SPHINXBUILD% -b text %ALLSPHINXOPTS% %BUILDDIR%/text 170 | if errorlevel 1 exit /b 1 171 | echo. 172 | echo.Build finished. The text files are in %BUILDDIR%/text. 173 | goto end 174 | ) 175 | 176 | if "%1" == "man" ( 177 | %SPHINXBUILD% -b man %ALLSPHINXOPTS% %BUILDDIR%/man 178 | if errorlevel 1 exit /b 1 179 | echo. 180 | echo.Build finished. The manual pages are in %BUILDDIR%/man. 181 | goto end 182 | ) 183 | 184 | if "%1" == "texinfo" ( 185 | %SPHINXBUILD% -b texinfo %ALLSPHINXOPTS% %BUILDDIR%/texinfo 186 | if errorlevel 1 exit /b 1 187 | echo. 188 | echo.Build finished. The Texinfo files are in %BUILDDIR%/texinfo. 189 | goto end 190 | ) 191 | 192 | if "%1" == "gettext" ( 193 | %SPHINXBUILD% -b gettext %I18NSPHINXOPTS% %BUILDDIR%/locale 194 | if errorlevel 1 exit /b 1 195 | echo. 196 | echo.Build finished. The message catalogs are in %BUILDDIR%/locale. 197 | goto end 198 | ) 199 | 200 | if "%1" == "changes" ( 201 | %SPHINXBUILD% -b changes %ALLSPHINXOPTS% %BUILDDIR%/changes 202 | if errorlevel 1 exit /b 1 203 | echo. 204 | echo.The overview file is in %BUILDDIR%/changes. 205 | goto end 206 | ) 207 | 208 | if "%1" == "linkcheck" ( 209 | %SPHINXBUILD% -b linkcheck %ALLSPHINXOPTS% %BUILDDIR%/linkcheck 210 | if errorlevel 1 exit /b 1 211 | echo. 212 | echo.Link check complete; look for any errors in the above output ^ 213 | or in %BUILDDIR%/linkcheck/output.txt. 214 | goto end 215 | ) 216 | 217 | if "%1" == "doctest" ( 218 | %SPHINXBUILD% -b doctest %ALLSPHINXOPTS% %BUILDDIR%/doctest 219 | if errorlevel 1 exit /b 1 220 | echo. 221 | echo.Testing of doctests in the sources finished, look at the ^ 222 | results in %BUILDDIR%/doctest/output.txt. 223 | goto end 224 | ) 225 | 226 | if "%1" == "xml" ( 227 | %SPHINXBUILD% -b xml %ALLSPHINXOPTS% %BUILDDIR%/xml 228 | if errorlevel 1 exit /b 1 229 | echo. 230 | echo.Build finished. The XML files are in %BUILDDIR%/xml. 231 | goto end 232 | ) 233 | 234 | if "%1" == "pseudoxml" ( 235 | %SPHINXBUILD% -b pseudoxml %ALLSPHINXOPTS% %BUILDDIR%/pseudoxml 236 | if errorlevel 1 exit /b 1 237 | echo. 238 | echo.Build finished. The pseudo-XML files are in %BUILDDIR%/pseudoxml. 239 | goto end 240 | ) 241 | 242 | :end 243 | -------------------------------------------------------------------------------- /hdlmake/.gitignore: -------------------------------------------------------------------------------- 1 | *pyc 2 | *.orig 3 | *~ 4 | -------------------------------------------------------------------------------- /hdlmake/__init__.py: -------------------------------------------------------------------------------- 1 | """This file is the entry point for the complete HDLMake package""" 2 | -------------------------------------------------------------------------------- /hdlmake/__main__.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/python 2 | # -*- coding: utf-8 -*- 3 | # 4 | # Copyright (c) 2013 - 2015 CERN 5 | # Author: Pawel Szostek (pawel.szostek@cern.ch) 6 | # Multi-tool support by Javier D. Garcia-Lasheras (javier@garcialasheras.com) 7 | # 8 | # This file is part of Hdlmake. 9 | # 10 | # Hdlmake is free software: you can redistribute it and/or modify 11 | # it under the terms of the GNU General Public License as published by 12 | # the Free Software Foundation, either version 3 of the License, or 13 | # (at your option) any later version. 14 | # 15 | # Hdlmake is distributed in the hope that it will be useful, 16 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 17 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 | # GNU General Public License for more details. 19 | # 20 | # You should have received a copy of the GNU General Public License 21 | # along with Hdlmake. If not, see . 22 | 23 | """This is the entry point for HDLMake working in command line app mode""" 24 | 25 | from __future__ import print_function 26 | from __future__ import absolute_import 27 | import argparse 28 | import sys 29 | 30 | from .manifest_parser import ManifestParser 31 | from .module_pool import ModulePool 32 | from ._version import __version__ 33 | 34 | 35 | def main(): 36 | """This is the main function, where HDLMake starts. 37 | Here, we make the next processes: 38 | -- parse command 39 | -- check and set the environment 40 | -- prepare the global module containing the heavy common stuff 41 | """ 42 | 43 | # 44 | # SET & GET PARSER 45 | # 46 | parser = _get_parser() 47 | 48 | # 49 | # PARSE & GET OPTIONS 50 | # 51 | options = _get_options(sys, parser) 52 | 53 | # Create a ModulePool object, this will become our workspace 54 | modules_pool = ModulePool(options) 55 | 56 | # Execute the appropriated action for the freshly created modules pool 57 | _action_runner(modules_pool) 58 | 59 | 60 | def _action_runner(modules_pool): 61 | """Funtion that decodes and executed the action selected by the user""" 62 | options = modules_pool.options 63 | if options.command == "manifest-help": 64 | ManifestParser().print_help() 65 | quit() 66 | elif options.command == "makefile": 67 | modules_pool.makefile() 68 | elif options.command == "fetch": 69 | modules_pool.fetch() 70 | elif options.command == "clean": 71 | modules_pool.clean() 72 | elif options.command == "list-mods": 73 | modules_pool.list_modules() 74 | elif options.command == "list-files": 75 | modules_pool.list_files() 76 | elif options.command == "tree": 77 | modules_pool.generate_tree() 78 | 79 | 80 | def _get_parser(): 81 | """This is the parser function, where options and commands are defined. 82 | Here, we make the next processes: 83 | """ 84 | description = ("A tool designed to help FPGA designers to manage " 85 | + "and share their HDL code by automatically finding file " 86 | + "dependencies, writing synthesis & simulation Makefiles, " 87 | + "and fetching IP-Core libraries from remote repositories.") 88 | parser = argparse.ArgumentParser("hdlmake", description=description) 89 | subparsers = parser.add_subparsers(title="commands", dest="command") 90 | makefile = subparsers.add_parser( 91 | "makefile", 92 | help="write the Makefile (default action for hdlmake)") 93 | makefile.add_argument( 94 | "-f", "--filename", 95 | help="name for the Makefile file to be created", 96 | default=None, 97 | dest="filename") 98 | subparsers.add_parser( 99 | "fetch", 100 | help="fetch and/or update all of the remote modules") 101 | subparsers.add_parser( 102 | "clean", 103 | help="clean all of the already fetched remote modules") 104 | listmod = subparsers.add_parser( 105 | "list-mods", 106 | help="list all modules together with their files") 107 | listmod.add_argument( 108 | "--with-files", 109 | help="list modules together with their files", 110 | default=False, 111 | action="store_true", 112 | dest="withfiles") 113 | listmod.add_argument( 114 | "--terse", 115 | help="do not print comments", 116 | default=False, 117 | action="store_true", 118 | dest="terse") 119 | listfiles = subparsers.add_parser( 120 | "list-files", 121 | help="list all of the files in the design hierarchy") 122 | listfiles.add_argument( 123 | "--delimiter", 124 | help="set delimitier for the list of files", 125 | dest="delimiter", 126 | default=None) 127 | listfiles.add_argument( 128 | "--reverse", 129 | help="reverse the order for the list of files", 130 | dest="reverse", 131 | default=False, 132 | action="store_true") 133 | listfiles.add_argument( 134 | "--top", 135 | help="print only those files required to build 'top'", 136 | dest="top", 137 | default=None) 138 | tree = subparsers.add_parser( 139 | "tree", 140 | help="generate a module hierarchy tree graph") 141 | tree.add_argument( 142 | "--with-files", 143 | help="add files to the module hierarchy tree", 144 | default=False, 145 | action="store_true", 146 | dest="withfiles") 147 | tree.add_argument( 148 | "--graphviz", 149 | dest="graphviz", 150 | default=None, 151 | help="qctivate graphviz and specify the program to be used to plot " 152 | "the graph (twopi, gvcolor, wc, ccomps, tred, sccmap, fdp, " 153 | "circo, neato, acyclic, nop, gvpr, dot, sfdp)") 154 | tree.add_argument( 155 | "--web", 156 | help="export the tree hierarchy in a web friendly JSON format", 157 | default=False, 158 | action="store_true", 159 | dest="web") 160 | tree.add_argument( 161 | "--solved", 162 | help="enable the parser", 163 | default=False, 164 | action="store_true", 165 | dest="solved") 166 | subparsers.add_parser( 167 | "manifest-help", 168 | help="print manifest file variables description") 169 | parser.add_argument( 170 | '-v', 171 | '--version', 172 | action='version', 173 | help="print the version of this program", 174 | version=parser.prog + 175 | " " + 176 | __version__) 177 | parser.add_argument( 178 | "--log", 179 | dest="log", 180 | default="info", 181 | help="logging level: debug, info, warning, error, critical") 182 | parser.add_argument( 183 | "-p", "--prefix", 184 | dest="prefix_code", 185 | default="", 186 | help="Python code executed before every Manifest.py") 187 | parser.add_argument( 188 | "-s", "--sufix", 189 | dest="sufix_code", 190 | default="", 191 | help="Python code executed after every Manifest.py") 192 | return parser 193 | 194 | 195 | def _get_options(sys_aux, parser): 196 | """Function that decodes and set the provided command user options""" 197 | options = None 198 | if len(sys_aux.argv[1:]) == 0: 199 | options = parser.parse_args(['makefile']) 200 | elif len(sys_aux.argv[1:]) == 2 and ( 201 | sys_aux.argv[1] == '-f' or sys_aux.argv[1] == '--filename'): 202 | options = parser.parse_args(['makefile'] + sys_aux.argv[1:]) 203 | else: 204 | options = parser.parse_args(sys_aux.argv[1:]) 205 | return options 206 | 207 | 208 | if __name__ == "__main__": 209 | main() 210 | -------------------------------------------------------------------------------- /hdlmake/_version.py: -------------------------------------------------------------------------------- 1 | """Current HDLMake version""" 2 | 3 | __version__ = "3.0" 4 | -------------------------------------------------------------------------------- /hdlmake/action/__init__.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/python 2 | # -*- coding: utf-8 -*- 3 | # 4 | # Copyright (c) 2013, 2014 CERN 5 | # Author: Pawel Szostek (pawel.szostek@cern.ch) 6 | # Multi-tool support by Javier D. Garcia-Lasheras (javier@garcialasheras.com) 7 | # 8 | # This file is part of Hdlmake. 9 | # 10 | # Hdlmake is free software: you can redistribute it and/or modify 11 | # it under the terms of the GNU General Public License as published by 12 | # the Free Software Foundation, either version 3 of the License, or 13 | # (at your option) any later version. 14 | # 15 | # Hdlmake is distributed in the hope that it will be useful, 16 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 17 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 | # GNU General Public License for more details. 19 | # 20 | # You should have received a copy of the GNU General Public License 21 | # along with Hdlmake. If not, see . 22 | 23 | """The Action package provides the full set of provided user functionalities""" 24 | 25 | from .core import ActionCore 26 | from .tree import ActionTree 27 | -------------------------------------------------------------------------------- /hdlmake/action/tree.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/python 2 | # -*- coding: utf-8 -*- 3 | # 4 | # Copyright (c) 2013 CERN 5 | # Author: Pawel Szostek (pawel.szostek@cern.ch) 6 | # 7 | # This file is part of Hdlmake. 8 | # 9 | # Hdlmake is free software: you can redistribute it and/or modify 10 | # it under the terms of the GNU General Public License as published by 11 | # the Free Software Foundation, either version 3 of the License, or 12 | # (at your option) any later version. 13 | # 14 | # Hdlmake is distributed in the hope that it will be useful, 15 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 16 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 | # GNU General Public License for more details. 18 | # 19 | # You should have received a copy of the GNU General Public License 20 | # along with Hdlmake. If not, see . 21 | 22 | """Module providing graph funtionalities to HDLMake""" 23 | 24 | from __future__ import absolute_import 25 | from hdlmake.util import path 26 | 27 | import logging 28 | 29 | from .action import Action 30 | 31 | 32 | class ActionTree(Action): 33 | 34 | """Class providing methods to create a graph from pool and to analyze it""" 35 | 36 | def __init__(self, *args): 37 | super(ActionTree, self).__init__(*args) 38 | 39 | def _generate_tree_web(self, hierarchy, top_id): 40 | """Create a JSON file containing the graph hierarchy from pool""" 41 | if self.options.web: 42 | try: 43 | import json 44 | from networkx.readwrite import json_graph 45 | except ImportError as error_import: 46 | logging.error(error_import) 47 | quit() 48 | data = json_graph.tree_data(hierarchy, root=top_id) 49 | json_string = json.dumps(data) 50 | json_file = open("hierarchy.json", "w") 51 | json_file.write(json_string) 52 | json_file.close() 53 | 54 | def _generate_tree_graphviz(self, hierarchy, top_id): 55 | """Define the program used to write the graphviz: 56 | Program should be one of: 57 | twopi, gvcolor, wc, ccomps, tred, sccmap, fdp, 58 | circo, neato, acyclic, nop, gvpr, dot, sfdp 59 | """ 60 | if self.options.graphviz: 61 | try: 62 | import matplotlib.pyplot as plt 63 | import networkx as nx 64 | except ImportError as error_import: 65 | logging.error(error_import) 66 | quit() 67 | pos = nx.graphviz_layout(hierarchy, 68 | prog=self.options.graphviz, 69 | root=top_id) 70 | nx.draw(hierarchy, pos, 71 | with_labels=True, 72 | alpha=0.5, 73 | node_size=100) 74 | plt.savefig("hierarchy.png") 75 | plt.show() 76 | 77 | def generate_tree(self): 78 | """Generate the graph from pool and create the requested outcomes""" 79 | try: 80 | import networkx as nx 81 | except ImportError as error_import: 82 | logging.error(error_import) 83 | quit() 84 | unfetched_modules = False 85 | hierarchy = nx.DiGraph() 86 | 87 | if self.options.solved: 88 | logging.warning("This is the solved tree") 89 | else: 90 | for mod_aux in self: 91 | if not mod_aux.isfetched: 92 | unfetched_modules = True 93 | else: 94 | if mod_aux.parent: 95 | hierarchy.add_node(mod_aux.path) 96 | hierarchy.add_edge(mod_aux.parent.path, mod_aux.path) 97 | else: 98 | hierarchy.add_node(mod_aux.path) 99 | top_id = mod_aux.path 100 | if self.options.withfiles: 101 | if len(mod_aux.files): 102 | for file_aux in mod_aux.files: 103 | hierarchy.add_edge(mod_aux.path, 104 | path.relpath(file_aux.path)) 105 | 106 | if unfetched_modules: 107 | logging.warning("Some of the modules have not been fetched!") 108 | 109 | self._generate_tree_web(hierarchy, top_id) 110 | self._generate_tree_graphviz(hierarchy, top_id) 111 | -------------------------------------------------------------------------------- /hdlmake/env.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/python 2 | # -*- coding: utf-8 -*- 3 | # 4 | # Copyright (c) 2013, 2014 CERN 5 | # Author: Pawel Szostek (pawel.szostek@cern.ch) 6 | # Multi-tool support by Javier D. Garcia-Lasheras (javier@garcialasheras.com) 7 | # 8 | # This file is part of Hdlmake. 9 | # 10 | # Hdlmake is free software: you can redistribute it and/or modify 11 | # it under the terms of the GNU General Public License as published by 12 | # the Free Software Foundation, either version 3 of the License, or 13 | # (at your option) any later version. 14 | # 15 | # Hdlmake is distributed in the hope that it will be useful, 16 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 17 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 | # GNU General Public License for more details. 19 | # 20 | # You should have received a copy of the GNU General Public License 21 | # along with Hdlmake. If not, see . 22 | # 23 | 24 | """Package providing the bridge with the Host O.S. environment""" 25 | 26 | from __future__ import print_function 27 | from __future__ import absolute_import 28 | import os 29 | import os.path 30 | import logging 31 | import six 32 | 33 | 34 | class Env(dict): 35 | 36 | """The Env (Environment) is a dictionary containing the environmental 37 | variables related with HDLMake for a proper use in the Python code""" 38 | 39 | def __init__(self, options): 40 | dict.__init__(self) 41 | self.options = options 42 | 43 | def _report_and_set_hdlmake_var(self, name): 44 | """Create a new entry in the Env dictionary and initialize the value 45 | to the obtained from the O.S. environmental variable if defined""" 46 | def _get(name): 47 | """Ask the Host O.S. for the value of an HDLMAKE_(name) 48 | environmental variable""" 49 | assert not name.startswith("HDLMAKE_") 50 | assert isinstance(name, six.string_types) 51 | name = name.upper() 52 | return os.environ.get("HDLMAKE_%s" % name) 53 | name = name.upper() 54 | val = _get(name) 55 | if val: 56 | logging.debug('Environmental variable HDLMAKE_%s is set: "%s".', 57 | name, val) 58 | self[name.lower()] = val 59 | return True 60 | else: 61 | logging.warning("Environmental variable HDLMAKE_%s is not set.", 62 | name) 63 | self[name.lower()] = None 64 | return False 65 | -------------------------------------------------------------------------------- /hdlmake/fetch/__init__.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/python 2 | # -*- coding: utf-8 -*- 3 | # 4 | # Copyright (c) 2013 CERN 5 | # Author: Pawel Szostek (pawel.szostek@cern.ch) 6 | # 7 | # This file is part of Hdlmake. 8 | # 9 | # Hdlmake is free software: you can redistribute it and/or modify 10 | # it under the terms of the GNU General Public License as published by 11 | # the Free Software Foundation, either version 3 of the License, or 12 | # (at your option) any later version. 13 | # 14 | # Hdlmake is distributed in the hope that it will be useful, 15 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 16 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 | # GNU General Public License for more details. 18 | # 19 | # You should have received a copy of the GNU General Public License 20 | # along with Hdlmake. If not, see . 21 | 22 | """This package provides stuff to handle local and remote repositories""" 23 | 24 | from .constants import (GIT, SVN, LOCAL) 25 | from .git import Git 26 | from .svn import Svn 27 | from .local import Local 28 | -------------------------------------------------------------------------------- /hdlmake/fetch/constants.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/python 2 | # -*- coding: utf-8 -*- 3 | # 4 | # Copyright (c) 2015 CERN 5 | # Author: Pawel Szostek (pawel.szostek@cern.ch) 6 | # 7 | # This file is part of Hdlmake. 8 | # 9 | # Hdlmake is free software: you can redistribute it and/or modify 10 | # it under the terms of the GNU General Public License as published by 11 | # the Free Software Foundation, either version 3 of the License, or 12 | # (at your option) any later version. 13 | # 14 | # Hdlmake is distributed in the hope that it will be useful, 15 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 16 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 | # GNU General Public License for more details. 18 | # 19 | # You should have received a copy of the GNU General Public License 20 | # along with Hdlmake. If not, see . 21 | 22 | # Note that the order here is important. The constants must be 23 | # defined first! If they are not, there will likely be an obscure error 24 | # when doing the imports within the imports that come afterwards. 25 | 26 | """Module providing the constants required for the fetch process""" 27 | 28 | GIT = 1 29 | SVN = 2 30 | LOCAL = 3 31 | -------------------------------------------------------------------------------- /hdlmake/fetch/fetcher.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/python 2 | # -*- coding: utf-8 -*- 3 | # 4 | # Copyright (c) 2013 CERN 5 | # Author: Pawel Szostek (pawel.szostek@cern.ch) 6 | # 7 | # This file is part of Hdlmake. 8 | # 9 | # Hdlmake is free software: you can redistribute it and/or modify 10 | # it under the terms of the GNU General Public License as published by 11 | # the Free Software Foundation, either version 3 of the License, or 12 | # (at your option) any later version. 13 | # 14 | # Hdlmake is distributed in the hope that it will be useful, 15 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 16 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 | # GNU General Public License for more details. 18 | # 19 | # You should have received a copy of the GNU General Public License 20 | # along with Hdlmake. If not, see . 21 | 22 | """Module providing the base class for the different code fetchers""" 23 | 24 | from __future__ import absolute_import 25 | import os 26 | from hdlmake.util import shell 27 | 28 | 29 | class Fetcher(object): 30 | 31 | """Base class for the code fetcher objects""" 32 | 33 | def fetch(self, module): 34 | """Stub method, this must be implemented by the code fetcher""" 35 | pass 36 | 37 | @staticmethod 38 | def check_id(path, command): 39 | """Use the provided command to get the specific ID from 40 | the repository at path""" 41 | cur_dir = os.getcwd() 42 | os.chdir(path) 43 | identifier = shell.run(command) 44 | os.chdir(cur_dir) 45 | return identifier 46 | -------------------------------------------------------------------------------- /hdlmake/fetch/git.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/python 2 | # -*- coding: utf-8 -*- 3 | # 4 | # Copyright (c) 2013 CERN 5 | # Author: Pawel Szostek (pawel.szostek@cern.ch) 6 | # 7 | # This file is part of Hdlmake. 8 | # 9 | # Hdlmake is free software: you can redistribute it and/or modify 10 | # it under the terms of the GNU General Public License as published by 11 | # the Free Software Foundation, either version 3 of the License, or 12 | # (at your option) any later version. 13 | # 14 | # Hdlmake is distributed in the hope that it will be useful, 15 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 16 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 | # GNU General Public License for more details. 18 | # 19 | # You should have received a copy of the GNU General Public License 20 | # along with Hdlmake. If not, see . 21 | 22 | """Module providing the stuff for handling Git repositories""" 23 | 24 | from __future__ import absolute_import 25 | import os 26 | from hdlmake.util import path as path_utils 27 | from hdlmake.util import shell 28 | import logging 29 | from .fetcher import Fetcher 30 | 31 | 32 | class Git(Fetcher): 33 | 34 | """This class provides the Git fetcher instances, that are 35 | used to fetch and handle Git repositories""" 36 | 37 | def __init__(self): 38 | pass 39 | 40 | @staticmethod 41 | def get_git_toplevel(): 42 | """Get the top level for the Git repository""" 43 | return shell.run("git rev-parse --show-toplevel") 44 | 45 | @staticmethod 46 | def get_submodule_commit(submodule_dir): 47 | """Get the commit for a repository if defined in Git submodules""" 48 | status_line = shell.run("git submodule status %s" % submodule_dir) 49 | status_line = status_line.split() 50 | if len(status_line) == 2: 51 | return status_line[0][1:] 52 | else: 53 | return None 54 | 55 | def fetch(self, module): 56 | """Get the code from the remote Git repository""" 57 | fetchto = module.fetchto() 58 | if not os.path.exists(fetchto): 59 | os.mkdir(fetchto) 60 | basename = path_utils.url_basename(module.url) 61 | mod_path = os.path.join(fetchto, basename) 62 | if basename.endswith(".git"): 63 | basename = basename[:-4] # remove trailing .git 64 | if not module.isfetched: 65 | logging.info("Fetching git module %s", mod_path) 66 | cmd = "(cd {0} && git clone {1})" 67 | cmd = cmd.format(fetchto, module.url) 68 | if os.system(cmd) != 0: 69 | return False 70 | else: 71 | logging.info("Updating git module %s", mod_path) 72 | checkout_id = None 73 | if module.branch is not None: 74 | checkout_id = module.branch 75 | logging.debug("Git branch requested: %s", checkout_id) 76 | elif module.revision is not None: 77 | checkout_id = module.revision 78 | logging.debug("Git commit requested: %s", checkout_id) 79 | else: 80 | checkout_id = self.get_submodule_commit(module.path) 81 | logging.debug("Git submodule commit: %s", checkout_id) 82 | if checkout_id is not None: 83 | logging.info("Checking out version %s", checkout_id) 84 | cmd = "(cd {0} && git checkout {1})" 85 | cmd = cmd.format(mod_path, checkout_id) 86 | if os.system(cmd) != 0: 87 | return False 88 | module.isfetched = True 89 | module.path = mod_path 90 | return True 91 | 92 | @staticmethod 93 | def check_git_commit(path): 94 | """Get the revision number for the Git repository at path""" 95 | git_cmd = 'git log -1 --format="%H" | cut -c1-32' 96 | return Fetcher.check_id(path, git_cmd) 97 | -------------------------------------------------------------------------------- /hdlmake/fetch/local.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/python 2 | # -*- coding: utf-8 -*- 3 | # 4 | # Copyright (c) 2013 CERN 5 | # Author: Pawel Szostek (pawel.szostek@cern.ch) 6 | # 7 | # This file is part of Hdlmake. 8 | # 9 | # Hdlmake is free software: you can redistribute it and/or modify 10 | # it under the terms of the GNU General Public License as published by 11 | # the Free Software Foundation, either version 3 of the License, or 12 | # (at your option) any later version. 13 | # 14 | # Hdlmake is distributed in the hope that it will be useful, 15 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 16 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 | # GNU General Public License for more details. 18 | # 19 | # You should have received a copy of the GNU General Public License 20 | # along with Hdlmake. If not, see . 21 | 22 | """Module providing the fetcher for local HDLMake modules""" 23 | 24 | from .fetcher import Fetcher 25 | 26 | 27 | class Local(Fetcher): 28 | 29 | """This class provides the Local fetcher instances""" 30 | 31 | def __init__(self): 32 | pass 33 | 34 | def fetch(self, module): 35 | pass 36 | 37 | @staticmethod 38 | def check_md5sum(path): 39 | """Get the ID for Local sources... maybe sha256 or md5sum?""" 40 | pass 41 | -------------------------------------------------------------------------------- /hdlmake/fetch/svn.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/python 2 | # -*- coding: utf-8 -*- 3 | # 4 | # Copyright (c) 2013 CERN 5 | # Author: Pawel Szostek (pawel.szostek@cern.ch) 6 | # 7 | # This file is part of Hdlmake. 8 | # 9 | # Hdlmake is free software: you can redistribute it and/or modify 10 | # it under the terms of the GNU General Public License as published by 11 | # the Free Software Foundation, either version 3 of the License, or 12 | # (at your option) any later version. 13 | # 14 | # Hdlmake is distributed in the hope that it will be useful, 15 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 16 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 | # GNU General Public License for more details. 18 | # 19 | # You should have received a copy of the GNU General Public License 20 | # along with Hdlmake. If not, see . 21 | 22 | """Module providing the stuff for handling SVN repositories""" 23 | 24 | from __future__ import absolute_import 25 | import os 26 | import logging 27 | from hdlmake.util import path as path_utils 28 | from .fetcher import Fetcher 29 | 30 | 31 | class Svn(Fetcher): 32 | 33 | """This class provides the SVN fetcher instances, that are 34 | used to fetch and handle SVN repositories""" 35 | 36 | def __init__(self): 37 | pass 38 | 39 | def fetch(self, module): 40 | """Get the code from the remote SVN repository""" 41 | fetchto = module.fetchto() 42 | if not os.path.exists(fetchto): 43 | os.mkdir(fetchto) 44 | cur_dir = module.pool.top_module.path 45 | os.chdir(fetchto) 46 | basename = path_utils.svn_basename(module.url) 47 | mod_path = os.path.join(fetchto, basename) 48 | cmd = "svn checkout {0} " + module.basename 49 | if module.revision: 50 | cmd = cmd.format(module.url + '@' + module.revision) 51 | else: 52 | cmd = cmd.format(module.url) 53 | success = True 54 | logging.info("Checking out module %s", mod_path) 55 | logging.debug(cmd) 56 | if os.system(cmd) != 0: 57 | success = False 58 | os.chdir(cur_dir) 59 | module.isfetched = True 60 | module.path = os.path.join(fetchto, module.basename) 61 | return success 62 | 63 | @staticmethod 64 | def check_svn_revision(path): 65 | """Get the revision number for the SVN repository at path""" 66 | svn_cmd = "svn info 2>/dev/null | awk '{if(NR == 5) {print $2}}'" 67 | return Fetcher.check_id(path, svn_cmd) 68 | -------------------------------------------------------------------------------- /hdlmake/manifest_parser/__init__.py: -------------------------------------------------------------------------------- 1 | """Python Package providing the Manifest.py parser for HDLMake""" 2 | 3 | from .variables import ManifestParser 4 | -------------------------------------------------------------------------------- /hdlmake/module/__init__.py: -------------------------------------------------------------------------------- 1 | """Package providing the Module functionality to HDLMake""" 2 | 3 | from .module import Module, ModuleArgs 4 | -------------------------------------------------------------------------------- /hdlmake/module/content.py: -------------------------------------------------------------------------------- 1 | """This provides the stuff related with the HDLMake module, 2 | from files to required submodules""" 3 | 4 | from __future__ import absolute_import 5 | import logging 6 | from hdlmake import fetch 7 | from hdlmake.util import path as path_mod 8 | from .core import ModuleCore 9 | import six 10 | import os 11 | 12 | 13 | class ModuleArgs(object): 14 | 15 | """This class is just a container for the main Module args""" 16 | 17 | def __init__(self): 18 | self.parent = None 19 | self.url = None 20 | self.source = fetch.LOCAL 21 | self.fetchto = None 22 | 23 | def set_args(self, parent, url, source, fetchto): 24 | """Set the module arguments""" 25 | self.parent = parent 26 | self.url = url 27 | if source == None: 28 | self.source = fetch.LOCAL 29 | else: 30 | self.source = source 31 | self.fetchto = fetchto 32 | 33 | def get_args(self): 34 | """Get the module arguments""" 35 | return self.parent, self.url, self.source, self.fetchto 36 | 37 | 38 | class ModuleContent(ModuleCore): 39 | 40 | """Class providing the HDLMake module content""" 41 | 42 | def __init__(self): 43 | # Manifest Files Properties 44 | self.files = None 45 | # Manifest Modules Properties 46 | self.local = [] 47 | self.git = [] 48 | self.svn = [] 49 | self.incl_makefiles = [] 50 | super(ModuleContent, self).__init__() 51 | 52 | def process_manifest(self): 53 | """Process the content section of the manifest_dic""" 54 | self._process_manifest_files() 55 | self._process_manifest_modules() 56 | self._process_manifest_makefiles() 57 | super(ModuleContent, self).process_manifest() 58 | 59 | def _process_manifest_files(self): 60 | """Process the files instantiated by the HDLMake module""" 61 | from hdlmake.srcfile import SourceFileSet 62 | # HDL files provided by the module 63 | if "files" not in self.manifest_dict: 64 | self.files = SourceFileSet() 65 | try: 66 | logging.debug("No files in the manifest at %s", 67 | self.path) 68 | except AttributeError: 69 | pass 70 | else: 71 | self.manifest_dict["files"] = path_mod.flatten_list( 72 | self.manifest_dict["files"]) 73 | logging.debug("Files in %s: %s", 74 | self.path, str(self.manifest_dict["files"])) 75 | paths = self._make_list_of_paths(self.manifest_dict["files"]) 76 | self.files = self._create_file_list_from_paths(paths=paths) 77 | 78 | def _get_fetchto(self): 79 | """Calculate the fetchto folder""" 80 | if ("fetchto" in self.manifest_dict and 81 | self.manifest_dict["fetchto"] is not None): 82 | fetchto = path_mod.rel2abs(self.manifest_dict["fetchto"], 83 | self.path) 84 | else: 85 | fetchto = self.fetchto() 86 | return fetchto 87 | 88 | def _process_manifest_modules(self): 89 | """Process the submodules required by the HDLMake module""" 90 | # Process required modules 91 | fetchto = self._get_fetchto() 92 | if "modules" in self.manifest_dict: 93 | 94 | if "local" in self.manifest_dict["modules"]: 95 | local_paths = path_mod.flatten_list( 96 | self.manifest_dict["modules"]["local"]) 97 | local_mods = [] 98 | for path in local_paths: 99 | if path_mod.is_abs_path(path): 100 | logging.error("Found an absolute path (" + path + 101 | ") in a manifest(" + self.path + ")") 102 | quit() 103 | path = path_mod.rel2abs(path, self.path) 104 | local_mods.append(self.pool.new_module(parent=self, 105 | url=path, 106 | source=fetch.LOCAL, 107 | fetchto=fetchto)) 108 | self.local = local_mods 109 | else: 110 | self.local = [] 111 | 112 | if "svn" in self.manifest_dict["modules"]: 113 | self.manifest_dict["modules"]["svn"] = path_mod.flatten_list( 114 | self.manifest_dict["modules"]["svn"]) 115 | svn_mods = [] 116 | for url in self.manifest_dict["modules"]["svn"]: 117 | svn_mods.append(self.pool.new_module(parent=self, 118 | url=url, 119 | source=fetch.SVN, 120 | fetchto=fetchto)) 121 | self.svn = svn_mods 122 | else: 123 | self.svn = [] 124 | 125 | if "git" in self.manifest_dict["modules"]: 126 | self.manifest_dict["modules"]["git"] = path_mod.flatten_list( 127 | self.manifest_dict["modules"]["git"]) 128 | git_mods = [] 129 | for url in self.manifest_dict["modules"]["git"]: 130 | git_mods.append(self.pool.new_module(parent=self, 131 | url=url, 132 | source=fetch.GIT, 133 | fetchto=fetchto)) 134 | self.git = git_mods 135 | else: 136 | self.git = [] 137 | 138 | def _process_manifest_makefiles(self): 139 | """Get the extra makefiles defined in the HDLMake module""" 140 | # Included Makefiles 141 | included_makefiles_aux = [] 142 | if "incl_makefiles" in self.manifest_dict: 143 | if isinstance(self.manifest_dict["incl_makefiles"], 144 | six.string_types): 145 | included_makefiles_aux.append( 146 | self.manifest_dict["incl_makefiles"]) 147 | else: # list 148 | included_makefiles_aux = self.manifest_dict["incl_makefiles"][:] 149 | makefiles_paths = self._make_list_of_paths(included_makefiles_aux) 150 | self.incl_makefiles.extend(makefiles_paths) 151 | 152 | def _create_file_list_from_paths(self, paths): 153 | """ 154 | Build a Source File Set containing the files indicated by the 155 | provided list of paths 156 | """ 157 | from hdlmake.srcfile import create_source_file, SourceFileSet 158 | srcs = SourceFileSet() 159 | # Check if this is the top module and grab the include_dirs 160 | if self.parent is None: 161 | if 'include_dirs' in self.manifest_dict: 162 | include_dirs = self.manifest_dict['include_dirs'] 163 | else: 164 | include_dirs = [] 165 | else: 166 | if 'include_dirs' in self.manifest_dict: 167 | include_dirs = self.top_module.manifest_dict['include_dirs'] 168 | else: 169 | include_dirs = [] 170 | for path_aux in paths: 171 | if os.path.isdir(path_aux): 172 | dir_ = os.listdir(path_aux) 173 | for f_dir in dir_: 174 | f_dir = os.path.join(self.path, path_aux, f_dir) 175 | if not os.path.isdir(f_dir): 176 | srcs.add(create_source_file(path=f_dir, 177 | module=self, 178 | library=self.library, 179 | include_dirs=include_dirs)) 180 | else: 181 | srcs.add(create_source_file(path=path_aux, 182 | module=self, 183 | library=self.library, 184 | include_dirs=include_dirs)) 185 | return srcs 186 | -------------------------------------------------------------------------------- /hdlmake/module/core.py: -------------------------------------------------------------------------------- 1 | """Provides the core functionality for the HDLMake module""" 2 | 3 | from __future__ import absolute_import 4 | import os 5 | import sys 6 | import logging 7 | 8 | from hdlmake import fetch 9 | from hdlmake.util import path as path_mod 10 | 11 | 12 | class ModuleConfig(object): 13 | 14 | """This class containt the base properties and methods that 15 | need to be initialized for a proper behavior""" 16 | 17 | def __init__(self): 18 | self.source = None 19 | self.parent = None 20 | self.url = None 21 | self.branch = None 22 | self.revision = None 23 | self.path = None 24 | self.isfetched = False 25 | 26 | def process_manifest(self): 27 | """process_manifest does nothing for ModuleConfig""" 28 | pass 29 | 30 | def basename(self): 31 | """Get the basename for the module""" 32 | if self.source == fetch.SVN: 33 | return path_mod.svn_basename(self.url) 34 | else: 35 | return path_mod.url_basename(self.url) 36 | 37 | def fetchto(self): 38 | """Get the fetchto folder for the module""" 39 | return os.path.dirname(self.path) 40 | 41 | def init_config(self, module_args): 42 | """This initializes the module configuration. 43 | The function is executed by Module constructor""" 44 | parent = module_args.parent 45 | url = module_args.url 46 | source = module_args.source 47 | fetchto = module_args.fetchto 48 | 49 | self.source = source 50 | self.parent = parent 51 | 52 | if self.source != fetch.LOCAL: 53 | self.url, self.branch, self.revision = \ 54 | path_mod.url_parse(url) 55 | basename = self.basename() 56 | path = path_mod.relpath(os.path.abspath( 57 | os.path.join(fetchto, basename))) 58 | # Check if the module dir exists and is not empty 59 | if os.path.exists(path) and os.listdir(path): 60 | self.path = path 61 | self.isfetched = True 62 | logging.debug("Module %s (parent: %s) is fetched.", 63 | url, self.parent.path) 64 | else: 65 | self.path = path 66 | self.isfetched = False 67 | logging.debug("Module %s (parent: %s) is NOT fetched.", 68 | url, self.parent.path) 69 | else: 70 | self.url, self.branch, self.revision = url, None, None 71 | 72 | if not os.path.exists(url): 73 | logging.error( 74 | "Path to the local module doesn't exist:\n" + url 75 | + "\nThis module was instantiated in: " + str(self.parent)) 76 | quit() 77 | self.path = url 78 | self.isfetched = True 79 | 80 | def _check_filepath(self, filepath): 81 | """Check the provided filepath against several conditions""" 82 | if filepath: 83 | if path_mod.is_abs_path(filepath): 84 | logging.warning( 85 | "Specified path seems to be an absolute path: " + 86 | filepath + "\nOmitting.") 87 | return False 88 | filepath = os.path.join(self.path, filepath) 89 | if not os.path.exists(filepath): 90 | logging.error( 91 | "Path specified in manifest in %s doesn't exist: %s", 92 | self.path, filepath) 93 | sys.exit("Exiting") 94 | 95 | filepath = path_mod.rel2abs(filepath, self.path) 96 | if os.path.isdir(filepath): 97 | logging.warning( 98 | "Path specified in manifest %s is a directory: %s", 99 | self.path, filepath) 100 | return True 101 | 102 | def _make_list_of_paths(self, list_of_paths): 103 | """Get a list with only the valid absolute paths from the provided""" 104 | paths = [] 105 | for filepath in list_of_paths: 106 | if self._check_filepath(filepath): 107 | paths.append(path_mod.rel2abs(filepath, self.path)) 108 | return paths 109 | 110 | 111 | class ModuleCore(ModuleConfig): 112 | 113 | """This is the class providing the module core functionality""" 114 | 115 | def __init__(self): 116 | # Universal Manifest Properties 117 | self.library = "work" 118 | self.action = None 119 | self.pool = None 120 | self.top_module = None 121 | self.manifest_dict = None 122 | super(ModuleCore, self).__init__() 123 | 124 | def set_pool(self, pool): 125 | """Set the associated pool for the module instance""" 126 | self.pool = pool 127 | self.top_module = pool.get_top_module() 128 | 129 | def process_manifest(self): 130 | """Method that process the core manifest section""" 131 | self._process_manifest_universal() 132 | super(ModuleCore, self).process_manifest() 133 | 134 | def _process_manifest_universal(self): 135 | """Method processing the universal manifest directives""" 136 | # if "top_module" in self.manifest_dict: 137 | # self.top_module = self.manifest_dict["top_module"] 138 | # Libraries 139 | if "library" in self.manifest_dict: 140 | self.library = self.manifest_dict["library"] 141 | if "action" in self.manifest_dict: 142 | self.action = self.manifest_dict["action"].lower() 143 | -------------------------------------------------------------------------------- /hdlmake/module/module.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/python 2 | # -*- coding: utf-8 -*- 3 | # 4 | # Copyright (c) 2013-2016 CERN 5 | # Author: Pawel Szostek (pawel.szostek@cern.ch) 6 | # Multi-tool support by Javier D. Garcia-Lasheras (javier@garcialasheras.com) 7 | # 8 | # This file is part of Hdlmake. 9 | # 10 | # Hdlmake is free software: you can redistribute it and/or modify 11 | # it under the terms of the GNU General Public License as published by 12 | # the Free Software Foundation, either version 3 of the License, or 13 | # (at your option) any later version. 14 | # 15 | # Hdlmake is distributed in the hope that it will be useful, 16 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 17 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 | # GNU General Public License for more details. 19 | # 20 | # You should have received a copy of the GNU General Public License 21 | # along with Hdlmake. If not, see . 22 | 23 | """ 24 | This python module is the one in charge to support the HDLMake modules 25 | It includes the base Module class, that inherits several action 26 | specific parent modules providing specific methods and attributes. 27 | 28 | """ 29 | 30 | from __future__ import print_function 31 | from __future__ import absolute_import 32 | import os 33 | import logging 34 | 35 | from hdlmake.util import path as path_mod 36 | from hdlmake.util import shell 37 | from hdlmake.manifest_parser import ManifestParser 38 | from .content import ModuleContent, ModuleArgs 39 | import six 40 | 41 | 42 | class Module(ModuleContent): 43 | 44 | """ 45 | This is the class providing the HDLMake module, the basic element 46 | providing the modular behavior allowing for structured designs. 47 | """ 48 | 49 | def __init__(self, module_args, pool): 50 | """Calculate and initialize the origin attributes: path, source...""" 51 | assert module_args.url is not None 52 | assert module_args.source is not None 53 | super(Module, self).__init__() 54 | self.init_config(module_args) 55 | self.set_pool(pool) 56 | self.module_args = ModuleArgs() 57 | self.module_args = module_args 58 | 59 | def __str__(self): 60 | return self.module_args.url 61 | 62 | @property 63 | def is_fetched_to(self): 64 | """Get the path where the module instance resides""" 65 | return os.path.dirname(self.path) 66 | 67 | def submodules(self): 68 | """Get a list with all the submodules this module instance requires""" 69 | def __nonull(submodule_list): 70 | """Returns a list with the submodules, being empty if null""" 71 | if not submodule_list: 72 | return [] 73 | else: 74 | return submodule_list 75 | return __nonull(self.local) + __nonull(self.git) \ 76 | + __nonull(self.svn) 77 | 78 | def remove_dir_from_disk(self): 79 | """Delete the module dir if it is already fetched and available""" 80 | if not self.isfetched: 81 | return 82 | logging.debug("Removing " + self.path) 83 | command_tmp = shell.rmdir_command() + " " + self.path 84 | shell.run(command_tmp) 85 | 86 | def process_manifest(self): 87 | """ 88 | This method processes the different manifest dictionary sections 89 | contained in the action specific inherited Python modules. 90 | """ 91 | logging.debug("Process manifest at: " + os.path.dirname(self.path)) 92 | super(Module, self).process_manifest() 93 | 94 | def get_include_dirs_list(self): 95 | """Private method that processes the included directory list""" 96 | # Include dirs 97 | include_dirs = [] 98 | if "include_dirs" in self.manifest_dict: 99 | if isinstance(self.manifest_dict["include_dirs"], 100 | six.string_types): 101 | dir_list = path_mod.compose( 102 | self.path, self.manifest_dict["include_dirs"]) 103 | include_dirs.append(dir_list) 104 | else: 105 | dir_list = [path_mod.compose(x, self.path) for 106 | x in self.manifest_dict["include_dirs"]] 107 | include_dirs.extend(dir_list) 108 | # Analyze included dirs and report if any issue is found 109 | for dir_ in include_dirs: 110 | if path_mod.is_abs_path(dir_): 111 | logging.warning("%s contains absolute path to an include " 112 | "directory: %s", self.path, dir_) 113 | if not os.path.exists(dir_): 114 | logging.warning(self.path + 115 | " has an unexisting include directory: " + 116 | dir_) 117 | return include_dirs 118 | 119 | def parse_manifest(self): 120 | """ 121 | Create a dictionary from the module Manifest.py and assign it 122 | to the manifest_dict property. 123 | In order to do this, it creates a ManifestParser object and 124 | feeds it with: 125 | - the arbitrary code from pool's top_module options 126 | (it assumes a top_module exists before any parsing!) 127 | - the Manifest.py (if exists) 128 | - the extra_context: 129 | - If this is the root module (has not parent), 130 | use an empty extra_context in the parser 131 | - If this is a submodule (has a parent), 132 | inherit the extra_context as: 133 | - the full manifest_dict from the top_module... 134 | - ...but deleting some key fields that needs to be respected. 135 | """ 136 | 137 | if self.manifest_dict or self.isfetched is False: 138 | return 139 | if self.path is None: 140 | raise RuntimeError() 141 | 142 | logging.debug(""" 143 | *********************************************************** 144 | PARSE START: %s 145 | ***********************************************************""", self.path) 146 | 147 | manifest_parser = ManifestParser() 148 | 149 | manifest_parser.add_prefix_code( 150 | self.pool.options.prefix_code) 151 | manifest_parser.add_sufix_code( 152 | self.pool.options.sufix_code) 153 | 154 | manifest_parser.add_manifest(self.path) 155 | 156 | if self.parent is None: 157 | extra_context = {} 158 | else: 159 | extra_context = dict(self.top_module.manifest_dict) 160 | extra_context["__manifest"] = self.path 161 | 162 | # The parse method is where the most of the parser action takes place! 163 | opt_map = None 164 | try: 165 | opt_map = manifest_parser.parse(extra_context=extra_context) 166 | except NameError as name_error: 167 | logging.error( 168 | "Error while parsing {0}:\n{1}: {2}.".format( 169 | self.path, type(name_error), name_error)) 170 | quit() 171 | self.manifest_dict = opt_map 172 | 173 | # Process the parsed manifest_dict to assign the module properties 174 | self.process_manifest() 175 | 176 | # Parse every detected submodule 177 | for module_aux in self.submodules(): 178 | module_aux.parse_manifest() 179 | 180 | logging.debug(""" 181 | *********************************************************** 182 | PARSE END: %s 183 | *********************************************************** 184 | 185 | """, self.path) 186 | -------------------------------------------------------------------------------- /hdlmake/module_pool.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/python 2 | # -*- coding: utf-8 -*- 3 | # 4 | # Copyright (c) 2013-2016 CERN 5 | # Author: Pawel Szostek (pawel.szostek@cern.ch) 6 | # Garcia-Lasheras (javier@garcialasheras.com) 7 | # 8 | # This file is part of Hdlmake. 9 | # 10 | # Hdlmake is free software: you can redistribute it and/or modify 11 | # it under the terms of the GNU General Public License as published by 12 | # the Free Software Foundation, either version 3 of the License, or 13 | # (at your option) any later version. 14 | # 15 | # Hdlmake is distributed in the hope that it will be useful, 16 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 17 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 | # GNU General Public License for more details. 19 | # 20 | # You should have received a copy of the GNU General Public License 21 | # along with Hdlmake. If not, see . 22 | # 23 | 24 | """This is the Python module providing the container for the HDL Modules""" 25 | 26 | from .action import ActionCore, ActionTree 27 | 28 | 29 | class ModulePool(ActionCore, ActionTree): 30 | 31 | """ 32 | The ModulePool class acts as the container for the HDLMake modules that 33 | are progressively being added to the design hierarchy. 34 | """ 35 | 36 | def __init__(self, *args): 37 | ActionCore.__init__(self, *args) 38 | ActionTree.__init__(self, *args) 39 | -------------------------------------------------------------------------------- /hdlmake/new_dep_solver.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/python 2 | # 3 | # Copyright (c) 2013, 2014 CERN 4 | # Author: Pawel Szostek (pawel.szostek@cern.ch) 5 | # Multi-tool support by Javier D. Garcia-Lasheras (javier@garcialasheras.com) 6 | # 7 | # This file is part of Hdlmake. 8 | # 9 | # Hdlmake is free software: you can redistribute it and/or modify 10 | # it under the terms of the GNU General Public License as published by 11 | # the Free Software Foundation, either version 3 of the License, or 12 | # (at your option) any later version. 13 | # 14 | # Hdlmake is distributed in the hope that it will be useful, 15 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 16 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 | # GNU General Public License for more details. 18 | # 19 | # You should have received a copy of the GNU General Public License 20 | # along with Hdlmake. If not, see . 21 | # 22 | 23 | """This package provides the functions and classes to parse and solve 24 | HDLMake filesets""" 25 | 26 | from __future__ import print_function 27 | from __future__ import absolute_import 28 | import logging 29 | 30 | from .dep_file import DepFile 31 | 32 | 33 | class DepParser(object): 34 | 35 | """Base Class for the different HDL parsers (VHDL and Verilog)""" 36 | 37 | def __init__(self, dep_file): 38 | self.dep_file = dep_file 39 | 40 | def parse(self, dep_file): 41 | """Base dummy interface method for the HDL parse execution""" 42 | pass 43 | 44 | 45 | def solve(fileset, standard_libs=None): 46 | """Function that Parses and Solves the provided HDL fileset. Note 47 | that it doesn't return a new fileset, but modifies the original one""" 48 | from .srcfile import SourceFileSet 49 | from .dep_file import DepRelation 50 | assert isinstance(fileset, SourceFileSet) 51 | fset = fileset.filter(DepFile) 52 | # print(fileset) 53 | # print(fset) 54 | not_satisfied = 0 55 | logging.debug("PARSE BEGIN: Here, we will parse all the files in the " 56 | "fileset: no parsing should be done beyond this point") 57 | for investigated_file in fset: 58 | logging.debug("INVESTIGATED FILE: %s", investigated_file) 59 | if not investigated_file.is_parsed: 60 | logging.debug("Not parsed yet, let's go!") 61 | investigated_file.parser.parse(investigated_file) 62 | logging.debug("PARSE END: now the parsing is done") 63 | logging.debug("SOLVE BEGIN") 64 | for investigated_file in fset: 65 | # logging.info("INVESTIGATED FILE: %s" % investigated_file) 66 | # print(investigated_file.rels) 67 | for rel in investigated_file.rels: 68 | # logging.info("- relation: %s" % rel) 69 | # logging.info("- direction: %s" % rel.direction) 70 | # Only analyze USE relations, we are looking for dependencies 71 | if rel.direction == DepRelation.USE: 72 | satisfied_by = set() 73 | for dep_file in fset: 74 | if dep_file.satisfies(rel): 75 | if dep_file is not investigated_file: 76 | investigated_file.depends_on.add(dep_file) 77 | satisfied_by.add(dep_file) 78 | if len(satisfied_by) > 1: 79 | logging.warning( 80 | "Relation %s satisfied by multpiple (%d) files: %s", 81 | str(rel), 82 | len(satisfied_by), 83 | '\n'.join([file_aux.path for 84 | file_aux in list(satisfied_by)])) 85 | elif len(satisfied_by) == 0: 86 | # if relation is a USE PACKAGE, check against 87 | # the standard libs provided by the tool HDL compiler 88 | required_lib = rel.obj_name.split('.')[0] 89 | if (not standard_libs is None and 90 | required_lib in standard_libs and 91 | rel.direction is DepRelation.USE and 92 | rel.rel_type is DepRelation.PACKAGE): 93 | logging.debug("Not satisfied relation %s in %s will " 94 | "be covered by the target compiler " 95 | "standard libs.", 96 | str(rel), investigated_file.name) 97 | else: 98 | logging.warning("Relation %s in %s not satisfied by " 99 | "any source file", 100 | str(rel), investigated_file.name) 101 | not_satisfied += 1 102 | logging.debug("SOLVE END") 103 | if not_satisfied != 0: 104 | logging.warning( 105 | "Dependencies solved, but %d relations were not satisfied", 106 | not_satisfied) 107 | else: 108 | logging.info( 109 | "Dependencies solved, all of the relations were satisfied!") 110 | 111 | 112 | def make_dependency_sorted_list(fileset, reverse=False): 113 | """Sort files in order of dependency. 114 | Files with no dependencies first. 115 | All files that another depends on will be earlier in the list.""" 116 | dependable = [f for f in fileset if isinstance(f, DepFile)] 117 | non_dependable = [f for f in fileset if not isinstance(f, DepFile)] 118 | dependable.sort(key=lambda f: f.file_path.lower()) 119 | # Not necessary, but will tend to group files more nicely 120 | # in the output. 121 | dependable.sort(key=DepFile.get_dep_level) 122 | sorted_list = non_dependable + dependable 123 | if reverse: 124 | sorted_list = list(reversed(sorted_list)) 125 | return sorted_list 126 | 127 | 128 | def make_dependency_set(fileset, top_level_entity): 129 | """Create the set of all files required to build the named 130 | top_level_entity.""" 131 | from hdlmake.srcfile import SourceFileSet 132 | from hdlmake.dep_file import DepRelation 133 | assert isinstance(fileset, SourceFileSet) 134 | fset = fileset.filter(DepFile) 135 | # Find the file that provides the named top level entity 136 | top_rel_vhdl = DepRelation( 137 | "%s.%s" % 138 | ("work", top_level_entity), DepRelation.PROVIDE, DepRelation.ENTITY) 139 | top_rel_vlog = DepRelation( 140 | "%s.%s" % 141 | ("work", top_level_entity), DepRelation.PROVIDE, DepRelation.MODULE) 142 | top_file = None 143 | for chk_file in fset: 144 | for rel in chk_file.rels: 145 | if (rel == top_rel_vhdl) or (rel == top_rel_vlog): 146 | top_file = chk_file 147 | break 148 | if top_file: 149 | break 150 | if top_file is None: 151 | logging.critical('Could not find a top level file that provides the ' 152 | 'top_module="%s". Continuing with the full file set.', 153 | top_level_entity) 154 | return fileset 155 | # Collect only the files that the top level entity is dependant on, by 156 | # walking the dependancy tree. 157 | try: 158 | dep_file_set = set() 159 | file_set = set([top_file]) 160 | while True: 161 | chk_file = file_set.pop() 162 | dep_file_set.add(chk_file) 163 | file_set.update(chk_file.depends_on - dep_file_set) 164 | except KeyError: 165 | # no files left 166 | pass 167 | logging.info("Found %d files as dependancies of %s.", 168 | len(dep_file_set), top_level_entity) 169 | # for dep_file in dep_file_set: 170 | # logging.info("\t" + str(dep_file)) 171 | return dep_file_set 172 | -------------------------------------------------------------------------------- /hdlmake/tools/__init__.py: -------------------------------------------------------------------------------- 1 | """Package that provides all the tool specific stuff""" 2 | 3 | from .makefile_writer import load_syn_tool, load_sim_tool 4 | -------------------------------------------------------------------------------- /hdlmake/tools/active_hdl.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/python 2 | # -*- coding: utf-8 -*- 3 | # 4 | # Copyright (c) 2013 - 2015 CERN 5 | # Author: Pawel Szostek (pawel.szostek@cern.ch) 6 | # Multi-tool support by Javier D. Garcia-Lasheras (javier@garcialasheras.com) 7 | # 8 | # This file is part of Hdlmake. 9 | # 10 | # Hdlmake is free software: you can redistribute it and/or modify 11 | # it under the terms of the GNU General Public License as published by 12 | # the Free Software Foundation, either version 3 of the License, or 13 | # (at your option) any later version. 14 | # 15 | # Hdlmake is distributed in the hope that it will be useful, 16 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 17 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 | # GNU General Public License for more details. 19 | # 20 | # You should have received a copy of the GNU General Public License 21 | # along with Hdlmake. If not, see . 22 | # 23 | 24 | """Module providing support for Aldec Active-HDL simulator""" 25 | 26 | from __future__ import absolute_import 27 | from .make_sim import ToolSim 28 | from hdlmake.srcfile import VHDLFile, VerilogFile, SVFile 29 | 30 | 31 | class ToolActiveHDL(ToolSim): 32 | 33 | """Class providing the interface to control an Active-HDL simulation""" 34 | 35 | TOOL_INFO = { 36 | 'name': 'Aldec Active-HDL', 37 | 'id': 'active_hdl', 38 | 'windows_bin': 'vsimsa.exe', 39 | 'linux_bin': None} 40 | 41 | STANDARD_LIBS = ['ieee', 'std'] 42 | 43 | HDL_FILES = {VHDLFile: None, VerilogFile: None, SVFile: None} 44 | 45 | CLEAN_TARGETS = {'clean': ["run.command", "library.cfg", "work"], 46 | 'mrproper': ["*.vcd", "*.asdb"]} 47 | 48 | def __init__(self): 49 | super(ToolActiveHDL, self).__init__() 50 | self._tool_info.update(ToolActiveHDL.TOOL_INFO) 51 | self._hdl_files.update(ToolActiveHDL.HDL_FILES) 52 | self._standard_libs.extend(ToolActiveHDL.STANDARD_LIBS) 53 | self._clean_targets.update(ToolActiveHDL.CLEAN_TARGETS) 54 | 55 | def _makefile_sim_compilation(self): 56 | """Print Makefile compilation target for Aldec Active-HDL simulator""" 57 | fileset = self.fileset 58 | self.writeln("simulation:") 59 | self.writeln("\t\techo \"# Active-HDL command file," 60 | " generated by HDLMake\" > run.command") 61 | self.writeln() 62 | self.writeln("\t\techo \"# Create library and set as" 63 | " default target\" >> run.command") 64 | self.writeln("\t\techo \"alib work\" >> run.command") 65 | self.writeln("\t\techo \"set worklib work\" >> run.command") 66 | self.writeln() 67 | self.writeln( 68 | "\t\techo \"# Compiling HDL source files\" >> run.command") 69 | for vl_file in fileset.filter(VerilogFile): 70 | self.writeln( 71 | "\t\techo \"alog " + 72 | vl_file.rel_path( 73 | ) + 74 | "\" >> run.command") 75 | for sv_file in fileset.filter(SVFile): 76 | self.writeln( 77 | "\t\techo \"alog " + 78 | sv_file.rel_path( 79 | ) + 80 | "\" >> run.command") 81 | for vhdl_file in fileset.filter(VHDLFile): 82 | self.writeln( 83 | "\t\techo \"acom " + 84 | vhdl_file.rel_path( 85 | ) + 86 | "\" >> run.command") 87 | self.writeln() 88 | self.writeln("\t\tvsimsa -do run.command") 89 | -------------------------------------------------------------------------------- /hdlmake/tools/diamond.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/python 2 | # -*- coding: utf-8 -*- 3 | # 4 | # Copyright (c) 2013 - 2015 CERN 5 | # Author: Pawel Szostek (pawel.szostek@cern.ch) 6 | # Multi-tool support by Javier D. Garcia-Lasheras (javier@garcialasheras.com) 7 | # 8 | # This file is part of Hdlmake. 9 | # 10 | # Hdlmake is free software: you can redistribute it and/or modify 11 | # it under the terms of the GNU General Public License as published by 12 | # the Free Software Foundation, either version 3 of the License, or 13 | # (at your option) any later version. 14 | # 15 | # Hdlmake is distributed in the hope that it will be useful, 16 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 17 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 | # GNU General Public License for more details. 19 | # 20 | # You should have received a copy of the GNU General Public License 21 | # along with Hdlmake. If not, see . 22 | # 23 | 24 | """Module providing support for Lattice Diamond IDE""" 25 | 26 | 27 | from __future__ import absolute_import 28 | from .make_syn import ToolSyn 29 | from hdlmake.srcfile import EDFFile, LPFFile, VHDLFile, VerilogFile 30 | 31 | 32 | class ToolDiamond(ToolSyn): 33 | 34 | """Class providing the interface for Lattice Diamond synthesis""" 35 | 36 | TOOL_INFO = { 37 | 'name': 'Diamond', 38 | 'id': 'diamond', 39 | 'windows_bin': 'pnmainc.exe', 40 | 'linux_bin': 'diamondc', 41 | 'project_ext': 'ldf'} 42 | 43 | STANDARD_LIBS = ['ieee', 'std'] 44 | 45 | _LATTICE_SOURCE = 'prj_src {0} "$$filename"' 46 | 47 | SUPPORTED_FILES = { 48 | EDFFile: _LATTICE_SOURCE.format('add'), 49 | LPFFile: _LATTICE_SOURCE.format('add -exclude') + '; ' + 50 | _LATTICE_SOURCE.format('enable')} 51 | 52 | HDL_FILES = { 53 | VHDLFile: _LATTICE_SOURCE.format('add'), 54 | VerilogFile: _LATTICE_SOURCE.format('add')} 55 | 56 | CLEAN_TARGETS = {'clean': ["*.sty", "$(PROJECT)"], 57 | 'mrproper': ["*.jed"]} 58 | 59 | TCL_CONTROLS = {'create': 'prj_project new -name $(PROJECT)' 60 | ' -impl $(PROJECT)' 61 | ' -dev {0} -synthesis \"synplify\"', 62 | 'open': 'prj_project open $(PROJECT).ldf', 63 | 'save': 'prj_project save', 64 | 'close': 'prj_project close', 65 | 'project': '$(TCL_CREATE)\n' 66 | '$(TCL_FILES)\n' 67 | '$(TCL_SAVE)\n' 68 | '$(TCL_CLOSE)', 69 | 'par': '$(TCL_OPEN)\n' 70 | 'prj_run PAR -impl $(PROJECT)\n' 71 | '$(TCL_SAVE)\n' 72 | '$(TCL_CLOSE)', 73 | 'bitstream': '$(TCL_OPEN)\n' 74 | 'prj_run Export' 75 | ' -impl $(PROJECT) -task Bitgen\n' 76 | '$(TCL_SAVE)\n' 77 | '$(TCL_CLOSE)', 78 | 'install_source': '$(PROJECT)/$(PROJECT)_$(PROJECT).jed'} 79 | 80 | def __init__(self): 81 | super(ToolDiamond, self).__init__() 82 | self._tool_info.update(ToolDiamond.TOOL_INFO) 83 | self._hdl_files.update(ToolDiamond.HDL_FILES) 84 | self._supported_files.update(ToolDiamond.SUPPORTED_FILES) 85 | self._standard_libs.extend(ToolDiamond.STANDARD_LIBS) 86 | self._clean_targets.update(ToolDiamond.CLEAN_TARGETS) 87 | self._tcl_controls.update(ToolDiamond.TCL_CONTROLS) 88 | 89 | def _makefile_syn_tcl(self): 90 | """Create a Diamond synthesis project by TCL""" 91 | syn_device = self.manifest_dict["syn_device"] 92 | syn_grade = self.manifest_dict["syn_grade"] 93 | syn_package = self.manifest_dict["syn_package"] 94 | create_tmp = self._tcl_controls["create"] 95 | target = syn_device + syn_grade + syn_package 96 | self._tcl_controls["create"] = create_tmp.format(target.upper()) 97 | super(ToolDiamond, self)._makefile_syn_tcl() 98 | -------------------------------------------------------------------------------- /hdlmake/tools/ghdl.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/python 2 | # -*- coding: utf-8 -*- 3 | # 4 | # Copyright (c) 2013 - 2015 CERN 5 | # Author: Pawel Szostek (pawel.szostek@cern.ch) 6 | # Multi-tool support by Javier D. Garcia-Lasheras (javier@garcialasheras.com) 7 | # 8 | # This file is part of Hdlmake. 9 | # 10 | # Hdlmake is free software: you can redistribute it and/or modify 11 | # it under the terms of the GNU General Public License as published by 12 | # the Free Software Foundation, either version 3 of the License, or 13 | # (at your option) any later version. 14 | # 15 | # Hdlmake is distributed in the hope that it will be useful, 16 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 17 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 | # GNU General Public License for more details. 19 | # 20 | # You should have received a copy of the GNU General Public License 21 | # along with Hdlmake. If not, see . 22 | # 23 | 24 | """Module providing support for GHDL simulator""" 25 | 26 | from __future__ import absolute_import 27 | import string 28 | 29 | from .make_sim import ToolSim 30 | from hdlmake.srcfile import VHDLFile 31 | 32 | 33 | class ToolGHDL(ToolSim): 34 | 35 | """Class providing the interface for GHDL simulator""" 36 | 37 | TOOL_INFO = { 38 | 'name': 'GHDL', 39 | 'id': 'ghdl', 40 | 'windows_bin': None, 41 | 'linux_bin': 'ghdl'} 42 | 43 | STANDARD_LIBS = ['ieee', 'std'] 44 | 45 | HDL_FILES = {VHDLFile: ''} 46 | 47 | CLEAN_TARGETS = {'clean': ["*.cf", "*.o", "$(TOP_MODULE)", "work"], 48 | 'mrproper': ["*.vcd"]} 49 | 50 | SIMULATOR_CONTROLS = {'vlog': None, 51 | 'vhdl': 'ghdl -a $<', 52 | 'compiler': 'ghdl -e $(TOP_MODULE)'} 53 | 54 | def __init__(self): 55 | super(ToolGHDL, self).__init__() 56 | self._tool_info.update(ToolGHDL.TOOL_INFO) 57 | self._hdl_files.update(ToolGHDL.HDL_FILES) 58 | self._standard_libs.extend(ToolGHDL.STANDARD_LIBS) 59 | self._clean_targets.update(ToolGHDL.CLEAN_TARGETS) 60 | self._simulator_controls.update(ToolGHDL.SIMULATOR_CONTROLS) 61 | 62 | def _makefile_sim_options(self): 63 | """Print the GHDL options to the Makefile""" 64 | ghdl_opt = self.manifest_dict.get("ghdl_opt", '') 65 | ghdl_string = string.Template( 66 | """GHDL_OPT := ${ghdl_opt}\n""") 67 | self.writeln(ghdl_string.substitute( 68 | ghdl_opt=ghdl_opt)) 69 | 70 | def _makefile_sim_compilation(self): 71 | """Print the GDHL simulation compilation target""" 72 | self.writeln("simulation: $(VERILOG_OBJ) $(VHDL_OBJ)") 73 | self.writeln("\t\t" + self._simulator_controls['compiler']) 74 | self.writeln('\n') 75 | self._makefile_sim_dep_files() 76 | -------------------------------------------------------------------------------- /hdlmake/tools/icestorm.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/python 2 | # -*- coding: utf-8 -*- 3 | # 4 | # Copyright (c) 2013 - 2017 CERN 5 | # Author: Javier D. Garcia Lasheras (jgarcia@gl-research.com) 6 | # 7 | # This file is part of Hdlmake. 8 | # 9 | # Hdlmake is free software: you can redistribute it and/or modify 10 | # it under the terms of the GNU General Public License as published by 11 | # the Free Software Foundation, either version 3 of the License, or 12 | # (at your option) any later version. 13 | # 14 | # Hdlmake is distributed in the hope that it will be useful, 15 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 16 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 | # GNU General Public License for more details. 18 | # 19 | # You should have received a copy of the GNU General Public License 20 | # along with Hdlmake. If not, see . 21 | # 22 | 23 | """Module providing support for the IceStorm flow""" 24 | 25 | 26 | from __future__ import absolute_import 27 | 28 | from .make_syn import ToolSyn 29 | from hdlmake.srcfile import VerilogFile, PCFFile 30 | 31 | 32 | class ToolIcestorm(ToolSyn): 33 | 34 | """Class providing the interface for IceStorm synthesis""" 35 | 36 | TOOL_INFO = { 37 | 'name': 'IceStorm', 38 | 'id': 'icestorm', 39 | 'windows_bin': None, 40 | 'linux_bin': 'yosys -c', 41 | 'project_ext': ''} 42 | 43 | STANDARD_LIBS = [] 44 | 45 | SUPPORTED_FILES = {PCFFile: None} 46 | 47 | HDL_FILES = {VerilogFile: 'read_verilog $(sourcefile)'} 48 | 49 | CLEAN_TARGETS = {'clean': ["$(PROJECT).asc", "$(PROJECT).blif"], 50 | 'mrproper': ["$(PROJECT).bin"]} 51 | 52 | TCL_CONTROLS = { 53 | 'synthesize': 'yosys -import\n' + 54 | 'source files.tcl\n' + 55 | 'synth_ice40 -top $(TOP_MODULE) -blif $(PROJECT).blif', 56 | 'par': 'catch {exec arachne-pnr' + 57 | ' -d $(SYN_DEVICE)' + 58 | ' -P $(SYN_PACKAGE)' + 59 | ' -p $(SOURCES_PCFFile)' + 60 | ' -o $(PROJECT).asc' + 61 | ' $(PROJECT).blif}', 62 | 'bitstream': 'catch {exec icepack $(PROJECT).asc $(PROJECT).bin}', 63 | 'install_source': ''} 64 | 65 | def __init__(self): 66 | super(ToolIcestorm, self).__init__() 67 | self._tool_info.update(ToolIcestorm.TOOL_INFO) 68 | self._hdl_files.update(ToolIcestorm.HDL_FILES) 69 | self._supported_files.update(ToolIcestorm.SUPPORTED_FILES) 70 | self._standard_libs.extend(ToolIcestorm.STANDARD_LIBS) 71 | self._clean_targets.update(ToolIcestorm.CLEAN_TARGETS) 72 | self._tcl_controls.update(ToolIcestorm.TCL_CONTROLS) 73 | 74 | def _makefile_syn_top(self): 75 | self.manifest_dict["syn_family"] = 'iCE40' 76 | super(ToolIcestorm, self)._makefile_syn_top() 77 | 78 | -------------------------------------------------------------------------------- /hdlmake/tools/ise.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/python 2 | # -*- coding: utf-8 -*- 3 | # 4 | # Copyright (c) 2013 - 2015 CERN 5 | # Author: Pawel Szostek (pawel.szostek@cern.ch) 6 | # Multi-tool support by Javier D. Garcia-Lasheras (javier@garcialasheras.com) 7 | # 8 | # This file is part of Hdlmake. 9 | # 10 | # Hdlmake is free software: you can redistribute it and/or modify 11 | # it under the terms of the GNU General Public License as published by 12 | # the Free Software Foundation, either version 3 of the License, or 13 | # (at your option) any later version. 14 | # 15 | # Hdlmake is distributed in the hope that it will be useful, 16 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 17 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 | # GNU General Public License for more details. 19 | # 20 | # You should have received a copy of the GNU General Public License 21 | # along with Hdlmake. If not, see . 22 | # 23 | 24 | """Module providing the classes that are used to handle Xilinx ISE""" 25 | 26 | from __future__ import print_function 27 | from __future__ import absolute_import 28 | import logging 29 | 30 | from .make_syn import ToolSyn 31 | 32 | from hdlmake.util import shell 33 | from hdlmake.srcfile import (VHDLFile, VerilogFile, SVFile, 34 | UCFFile, CDCFile, NGCFile) 35 | 36 | FAMILY_NAMES = { 37 | "XC6S": "Spartan6", 38 | "XC3S": "Spartan3", 39 | "XC6V": "Virtex6", 40 | "XC5V": "Virtex5", 41 | "XC4V": "Virtex4", 42 | "XC7Z": "Zynq", 43 | "XC7V": "Virtex7", 44 | "XC7K": "Kintex7", 45 | "XC7A": "Artix7"} 46 | 47 | ISE_STANDARD_LIBS = ['ieee', 'ieee_proposed', 'iSE', 'simprims', 'std', 48 | 'synopsys', 'unimacro', 'unisim', 'XilinxCoreLib'] 49 | 50 | 51 | class ToolISE(ToolSyn): 52 | 53 | """Class providing the methods to create and build a Xilinx ISE project""" 54 | 55 | TOOL_INFO = { 56 | 'name': 'ISE', 57 | 'id': 'ise', 58 | 'windows_bin': 'xtclsh.exe', 59 | 'linux_bin': 'xtclsh', 60 | 'project_ext': 'xise'} 61 | 62 | STANDARD_LIBS = ['ieee', 'ieee_proposed', 'iSE', 'simprims', 'std', 63 | 'synopsys', 'unimacro', 'unisim', 'XilinxCoreLib'] 64 | 65 | SUPPORTED_FILES = { 66 | UCFFile: 'xfile add $(sourcefile)', 67 | CDCFile: 'xfile add $(sourcefile)', 68 | NGCFile: 'xfile add $(sourcefile)'} 69 | 70 | HDL_FILES = { 71 | VHDLFile: 'xfile add $(sourcefile)', 72 | VerilogFile: 'xfile add $(sourcefile)', 73 | SVFile: 'xfile add $(sourcefile)'} 74 | 75 | CLEAN_TARGETS = {'clean': ["xst", "xlnx_auto_0_xdb", "iseconfig _xmsgs", 76 | "_ngo", "*.b", "*_summary.html", 77 | "*.bld", "*.cmd_log", "*.drc", "*.lso", "*.ncd", 78 | "*.ngc", "*.ngd", "*.ngr", "*.pad", "*.par", 79 | "*.pcf", "*.prj", "*.ptwx", "*.stx", "*.syr", 80 | "*.twr", "*.twx", "*.gise", "*.gise", "*.bgn", 81 | "*.unroutes", "*.ut", "*.xpi", "*.xst", 82 | "*.xise", "*.xwbt", 83 | "*_envsettings.html", "*_guide.ncd", 84 | "*_map.map", "*_map.mrp", "*_map.ncd", 85 | "*_map.ngm", "*_map.xrpt", "*_ngdbuild.xrpt", 86 | "*_pad.csv", "*_pad.txt", "*_par.xrpt", 87 | "*_summary.xml", "*_usage.xml", "*_xst.xrpt", 88 | "usage_statistics_webtalk.html", "webtalk.log", 89 | "par_usage_statistics.html", "webtalk_pn.xml"], 90 | 'mrproper': ["*.bit", "*.bin", "*.mcs"]} 91 | 92 | _ISE_RUN = '''\ 93 | $(TCL_OPEN) 94 | set process {{{0}}} 95 | process run '$$'process 96 | set result [process get '$$'process status] 97 | if {{ '$$'result == \\"errors\\" }} {{ 98 | exit 1 99 | }} 100 | $(TCL_SAVE) 101 | $(TCL_CLOSE)''' 102 | 103 | TCL_CONTROLS = { 104 | 'create': 'project new $(PROJECT_FILE)', 105 | 'open': 'project open $(PROJECT_FILE)', 106 | 'save': 'project save', 107 | 'close': 'project close', 108 | 'project': '$(TCL_CREATE)\n' 109 | 'source files.tcl\n' 110 | '{0}\n' 111 | 'project set top $(TOP_MODULE)\n' 112 | '$(TCL_SAVE)\n' 113 | '$(TCL_CLOSE)', 114 | 'synthesize': _ISE_RUN.format("Synthesize - XST"), 115 | 'translate': _ISE_RUN.format("Translate"), 116 | 'map': _ISE_RUN.format("Map"), 117 | 'par': _ISE_RUN.format("Place " 118 | + ("^&" if shell.check_windows() else "'&'") 119 | + " Route"), 120 | 'bitstream': _ISE_RUN.format("Generate Programming File"), 121 | 'install_source': "*.bit *.bin"} 122 | 123 | def __init__(self): 124 | super(ToolISE, self).__init__() 125 | self._tool_info.update(ToolISE.TOOL_INFO) 126 | self._hdl_files.update(ToolISE.HDL_FILES) 127 | self._supported_files.update(ToolISE.SUPPORTED_FILES) 128 | self._standard_libs.extend(ToolISE.STANDARD_LIBS) 129 | self._clean_targets.update(ToolISE.CLEAN_TARGETS) 130 | self._tcl_controls.update(ToolISE.TCL_CONTROLS) 131 | 132 | def _makefile_syn_top(self): 133 | """Create the top part of the synthesis Makefile for ISE""" 134 | syn_family = self.manifest_dict.get("syn_family", None) 135 | if syn_family is None: 136 | syn_family = FAMILY_NAMES.get( 137 | self.manifest_dict["syn_device"][0:4].upper()) 138 | if syn_family is None: 139 | logging.error( 140 | "syn_family is not defined in Manifest.py" 141 | " and can not be guessed!") 142 | quit(-1) 143 | self.manifest_dict["syn_family"] = syn_family 144 | super(ToolISE, self)._makefile_syn_top() 145 | 146 | 147 | def _makefile_syn_tcl(self): 148 | """Create a Xilinx synthesis project by TCL""" 149 | syn_properties = self.manifest_dict.get("syn_properties") 150 | project_new = [] 151 | project_tcl = self._tcl_controls["project"] 152 | if shell.check_windows(): 153 | tmp = 'project set "{0}" "{1}"' 154 | else: 155 | tmp = 'project set \\"{0}\\" \\"{1}\\"' 156 | properties = [ 157 | ['family', '$(SYN_FAMILY)'], 158 | ['device', '$(SYN_DEVICE)'], 159 | ['package', '$(SYN_PACKAGE)'], 160 | ['speed', '$(SYN_GRADE)'], 161 | ['Manual Implementation Compile Order', 'false'], 162 | ['Auto Implementation Top', 'false'], 163 | ['Create Binary Configuration File', 'true']] 164 | if not syn_properties is None: 165 | properties.extend(syn_properties) 166 | for prop in properties: 167 | project_new.append(tmp.format(prop[0], prop[1])) 168 | project_new.append('set compile_directory .') 169 | self._tcl_controls["project"] = project_tcl.format( 170 | "\n".join(project_new)) 171 | super(ToolISE, self)._makefile_syn_tcl() 172 | -------------------------------------------------------------------------------- /hdlmake/tools/iverilog.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/python 2 | # -*- coding: utf-8 -*- 3 | # 4 | # Copyright (c) 2013 - 2015 CERN 5 | # Author: Pawel Szostek (pawel.szostek@cern.ch) 6 | # Multi-tool support by Javier D. Garcia-Lasheras (javier@garcialasheras.com) 7 | # 8 | # This file is part of Hdlmake. 9 | # 10 | # Hdlmake is free software: you can redistribute it and/or modify 11 | # it under the terms of the GNU General Public License as published by 12 | # the Free Software Foundation, either version 3 of the License, or 13 | # (at your option) any later version. 14 | # 15 | # Hdlmake is distributed in the hope that it will be useful, 16 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 17 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 | # GNU General Public License for more details. 19 | # 20 | # You should have received a copy of the GNU General Public License 21 | # along with Hdlmake. If not, see . 22 | # 23 | 24 | """Module providing support for IVerilog (Icarus Verilog) simulator""" 25 | 26 | from __future__ import absolute_import 27 | import string 28 | 29 | from .make_sim import ToolSim 30 | from hdlmake.srcfile import VerilogFile, VHDLFile, SVFile 31 | 32 | 33 | class ToolIVerilog(ToolSim): 34 | 35 | """Class providing the interface for Icarus Verilog simulator""" 36 | 37 | TOOL_INFO = { 38 | 'name': 'Icarus Verilog', 39 | 'id': 'iverilog', 40 | 'windows_bin': None, 41 | 'linux_bin': 'iverilog'} 42 | 43 | STANDARD_LIBS = ['std', 'ieee', 'ieee_proposed', 'vl', 'synopsys'] 44 | 45 | HDL_FILES = {VerilogFile: '', VHDLFile: '', SVFile: ''} 46 | 47 | CLEAN_TARGETS = {'clean': ["run.command", "ivl_vhdl_work", "work"], 48 | 'mrproper': ["*.vcd", "*.vvp"]} 49 | 50 | SIMULATOR_CONTROLS = {'vlog': 'echo $< >> run.command', 51 | 'vhdl': 'echo $< >> run.command', 52 | 'compiler': 'iverilog $(IVERILOG_OPT) ' 53 | '-s $(TOP_MODULE) ' 54 | '-o $(TOP_MODULE).vvp ' 55 | '-c run.command'} 56 | 57 | def __init__(self): 58 | super(ToolIVerilog, self).__init__() 59 | self._tool_info.update(ToolIVerilog.TOOL_INFO) 60 | self._hdl_files.update(ToolIVerilog.HDL_FILES) 61 | self._standard_libs.extend(ToolIVerilog.STANDARD_LIBS) 62 | self._clean_targets.update(ToolIVerilog.CLEAN_TARGETS) 63 | self._simulator_controls.update(ToolIVerilog.SIMULATOR_CONTROLS) 64 | 65 | def _makefile_sim_compilation(self): 66 | """Generate compile simulation Makefile target for IVerilog""" 67 | self.writeln("simulation: include_dirs $(VERILOG_OBJ) $(VHDL_OBJ)") 68 | self.writeln("\t\t" + self._simulator_controls['compiler']) 69 | self.writeln() 70 | self.writeln("include_dirs:") 71 | self.writeln("\t\techo \"# IVerilog command file," 72 | " generated by HDLMake\" > run.command") 73 | self.writeln() 74 | for inc in self.manifest_dict.get("include_dirs", []): 75 | self.writeln("\t\techo \"+incdir+" + inc + "\" >> run.command") 76 | self.writeln('\n') 77 | self._makefile_sim_dep_files() 78 | 79 | def _makefile_sim_options(self): 80 | """Print the IVerilog options to the Makefile""" 81 | iverilog_opt = self.manifest_dict.get("iverilog_opt", '') 82 | iverilog_string = string.Template( 83 | """IVERILOG_OPT := ${iverilog_opt}\n""") 84 | self.writeln(iverilog_string.substitute( 85 | iverilog_opt=iverilog_opt)) 86 | -------------------------------------------------------------------------------- /hdlmake/tools/libero.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/python 2 | # -*- coding: utf-8 -*- 3 | # 4 | # Copyright (c) 2013 - 2015 CERN 5 | # Author: Pawel Szostek (pawel.szostek@cern.ch) 6 | # Multi-tool support by Javier D. Garcia-Lasheras (javier@garcialasheras.com) 7 | # 8 | # This file is part of Hdlmake. 9 | # 10 | # Hdlmake is free software: you can redistribute it and/or modify 11 | # it under the terms of the GNU General Public License as published by 12 | # the Free Software Foundation, either version 3 of the License, or 13 | # (at your option) any later version. 14 | # 15 | # Hdlmake is distributed in the hope that it will be useful, 16 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 17 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 | # GNU General Public License for more details. 19 | # 20 | # You should have received a copy of the GNU General Public License 21 | # along with Hdlmake. If not, see . 22 | # 23 | 24 | """Module providing support for Microsemi Libero IDE synthesis""" 25 | 26 | 27 | from __future__ import absolute_import 28 | from .make_syn import ToolSyn 29 | from hdlmake.srcfile import VHDLFile, VerilogFile, SDCFile, PDCFile 30 | 31 | 32 | class ToolLibero(ToolSyn): 33 | 34 | """Class providing the interface for Microsemi Libero IDE synthesis""" 35 | 36 | TOOL_INFO = { 37 | 'name': 'Libero', 38 | 'id': 'libero', 39 | 'windows_bin': 'libero.exe SCRIPT:', 40 | 'linux_bin': 'libero SCRIPT:', 41 | 'project_ext': 'prjx'} 42 | 43 | STANDARD_LIBS = ['ieee', 'std'] 44 | 45 | _LIBERO_SOURCE = 'create_links {0} {{$$filename}}' 46 | 47 | SUPPORTED_FILES = { 48 | SDCFile: _LIBERO_SOURCE.format('-sdc'), 49 | PDCFile: _LIBERO_SOURCE.format('-pdc')} 50 | 51 | HDL_FILES = { 52 | VHDLFile: _LIBERO_SOURCE.format('-hdl_source'), 53 | VerilogFile: _LIBERO_SOURCE.format('-hdl_source')} 54 | 55 | CLEAN_TARGETS = {'clean': ["$(PROJECT)"], 56 | 'mrproper': ["*.pdb", "*.stp"]} 57 | 58 | TCL_CONTROLS = { 59 | 'create': 'new_project -location {{./{0}}} -name {{{0}}}' 60 | ' -hdl {{VHDL}} -family {{ProASIC3}} -die {{{1}}}' 61 | ' -package {{{2}}} -speed {{{3}}} -die_voltage {{1.5}}', 62 | 'open': 'open_project -file {$(PROJECT)/$(PROJECT_FILE)}', 63 | 'save': 'save_project', 64 | 'close': 'close_project', 65 | 'project': '$(TCL_CREATE)\n' 66 | '$(TCL_FILES)\n' 67 | '{0}\n' 68 | '$(TCL_SAVE)\n' 69 | '$(TCL_CLOSE)', 70 | 'bitstream': '$(TCL_OPEN)\n' 71 | 'update_and_run_tool' 72 | ' -name {GENERATEPROGRAMMINGDATA}\n' 73 | '$(TCL_SAVE)\n' 74 | '$(TCL_CLOSE)', 75 | 'install_source': '$(PROJECT)/designer/impl1/$(SYN_TOP).pdb'} 76 | 77 | def __init__(self): 78 | super(ToolLibero, self).__init__() 79 | self._tool_info.update(ToolLibero.TOOL_INFO) 80 | self._hdl_files.update(ToolLibero.HDL_FILES) 81 | self._supported_files.update(ToolLibero.SUPPORTED_FILES) 82 | self._standard_libs.extend(ToolLibero.STANDARD_LIBS) 83 | self._clean_targets.update(ToolLibero.CLEAN_TARGETS) 84 | self._tcl_controls.update(ToolLibero.TCL_CONTROLS) 85 | 86 | def _makefile_syn_tcl(self): 87 | """Create a Libero synthesis project by TCL""" 88 | syn_project = self.manifest_dict["syn_project"] 89 | syn_device = self.manifest_dict["syn_device"] 90 | syn_grade = self.manifest_dict["syn_grade"] 91 | syn_package = self.manifest_dict["syn_package"] 92 | create_tmp = self._tcl_controls["create"] 93 | self._tcl_controls["create"] = create_tmp.format(syn_project, 94 | syn_device.upper(), 95 | syn_package.upper(), 96 | syn_grade) 97 | project_tmp = self._tcl_controls["project"] 98 | synthesis_constraints = [] 99 | compilation_constraints = [] 100 | ret = [] 101 | # First stage: linking files 102 | for file_aux in self.fileset: 103 | if isinstance(file_aux, SDCFile): 104 | synthesis_constraints.append(file_aux) 105 | compilation_constraints.append(file_aux) 106 | elif isinstance(file_aux, PDCFile): 107 | compilation_constraints.append(file_aux) 108 | else: 109 | continue 110 | # Second stage: Organizing / activating synthesis constraints (the top 111 | # module needs to be present!) 112 | if synthesis_constraints: 113 | line = 'organize_tool_files -tool {SYNTHESIZE} ' 114 | for file_aux in synthesis_constraints: 115 | line = line + '-file {' + file_aux.rel_path() + '} ' 116 | line = line + \ 117 | '-module {$(TOP_MODULE)::work} -input_type {constraint}' 118 | ret.append(line) 119 | # Third stage: Organizing / activating compilation constraints (the top 120 | # module needs to be present!) 121 | if compilation_constraints: 122 | line = 'organize_tool_files -tool {COMPILE} ' 123 | for file_aux in compilation_constraints: 124 | line = line + '-file {' + file_aux.rel_path() + '} ' 125 | line = line + \ 126 | '-module {$(TOP_MODULE)::work} -input_type {constraint}' 127 | ret.append(line) 128 | # Fourth stage: set root/top module 129 | line = 'set_root -module {$(TOP_MODULE)::work}' 130 | ret.append(line) 131 | self._tcl_controls['project'] = project_tmp.format('\n'.join(ret)) 132 | super(ToolLibero, self)._makefile_syn_tcl() 133 | -------------------------------------------------------------------------------- /hdlmake/tools/make_sim.py: -------------------------------------------------------------------------------- 1 | """Module providing the simulation functionality for writing Makefiles""" 2 | 3 | from __future__ import absolute_import 4 | import os 5 | import sys 6 | import string 7 | import logging 8 | 9 | from .makefile import ToolMakefile 10 | from hdlmake.util import shell 11 | from hdlmake.srcfile import VerilogFile, VHDLFile, SVFile 12 | 13 | 14 | def _check_simulation_manifest(manifest_dict): 15 | """Check if the simulation keys are provided by the top manifest""" 16 | if not manifest_dict["sim_top"]: 17 | logging.error("sim_top variable must be set in the top manifest.") 18 | sys.exit("Exiting") 19 | if not manifest_dict["sim_tool"]: 20 | logging.error("sim_tool variable must be set in the top manifest.") 21 | sys.exit("Exiting") 22 | 23 | 24 | class ToolSim(ToolMakefile): 25 | 26 | """Class that provides the Makefile writing methods and status""" 27 | 28 | def __init__(self): 29 | super(ToolSim, self).__init__() 30 | self._simulator_controls = {} 31 | 32 | def write_makefile(self, config, fileset, filename=None): 33 | """Execute the simulation action""" 34 | _check_simulation_manifest(config) 35 | self.makefile_setup(config, fileset, filename=filename) 36 | self.makefile_check_tool('sim_path') 37 | self._makefile_sim_top() 38 | self._makefile_sim_options() 39 | self._makefile_sim_local() 40 | self._makefile_sim_sources() 41 | self._makefile_sim_compilation() 42 | self._makefile_sim_command() 43 | self._makefile_sim_clean() 44 | self._makefile_sim_phony() 45 | 46 | def _makefile_sim_top(self): 47 | """Generic method to write the simulation Makefile top section""" 48 | top_parameter = string.Template("""\ 49 | TOP_MODULE := ${top_module} 50 | PWD := $$(shell pwd) 51 | """) 52 | self.writeln(top_parameter.substitute( 53 | top_module=self.manifest_dict["sim_top"])) 54 | 55 | def _makefile_sim_options(self): 56 | """End stub method to write the simulation Makefile options section""" 57 | pass 58 | 59 | def _makefile_sim_compilation(self): 60 | """End stub method to write the simulation Makefile compilation 61 | section""" 62 | pass 63 | 64 | def _makefile_sim_local(self): 65 | """Generic method to write the simulation Makefile local target""" 66 | self.writeln("#target for performing local simulation\n" 67 | "local: sim_pre_cmd simulation sim_post_cmd\n") 68 | 69 | def _makefile_sim_sources(self): 70 | """Generic method to write the simulation Makefile HDL sources""" 71 | fileset = self.fileset 72 | self.write("VERILOG_SRC := ") 73 | for vlog in fileset.filter(VerilogFile): 74 | self.writeln(vlog.rel_path() + " \\") 75 | self.writeln() 76 | self.write("VERILOG_OBJ := ") 77 | for vlog in fileset.filter(VerilogFile): 78 | # make a file compilation indicator (these .dat files are made even 79 | # if the compilation process fails) and add an ending according 80 | # to file's extension (.sv and .vhd files may have the same 81 | # corename and this causes a mess 82 | self.writeln( 83 | os.path.join( 84 | vlog.library, 85 | vlog.purename, 86 | "." + 87 | vlog.purename + 88 | "_" + 89 | vlog.extension( 90 | )) + 91 | " \\") 92 | self.writeln() 93 | self.write("VHDL_SRC := ") 94 | for vhdl in fileset.filter(VHDLFile): 95 | self.write(vhdl.rel_path() + " \\\n") 96 | self.writeln() 97 | # list vhdl objects (_primary.dat files) 98 | self.write("VHDL_OBJ := ") 99 | for vhdl in fileset.filter(VHDLFile): 100 | # file compilation indicator (important: add _vhd ending) 101 | self.writeln( 102 | os.path.join( 103 | vhdl.library, 104 | vhdl.purename, 105 | "." + 106 | vhdl.purename + 107 | "_" + 108 | vhdl.extension( 109 | )) + 110 | " \\") 111 | self.writeln() 112 | 113 | def _makefile_sim_dep_files(self): 114 | """Print dummy targets to handle file dependencies""" 115 | fileset = self.fileset 116 | for file_aux in fileset: 117 | if any(isinstance(file_aux, file_type) 118 | for file_type in self._hdl_files): 119 | self.write("%s: %s" % (os.path.join( 120 | file_aux.library, file_aux.purename, 121 | ".%s_%s" % (file_aux.purename, file_aux.extension())), 122 | file_aux.rel_path())) 123 | # list dependencies, do not include the target file 124 | for dep_file in [dfile for dfile in file_aux.depends_on 125 | if dfile is not file_aux]: 126 | if dep_file in fileset: 127 | name = dep_file.purename 128 | extension = dep_file.extension() 129 | self.write(" \\\n" + os.path.join( 130 | dep_file.library, name, ".%s_%s" % 131 | (name, extension))) 132 | else: 133 | # the file is included -> we depend directly on it 134 | self.write(" \\\n" + dep_file.rel_path()) 135 | self.writeln() 136 | if isinstance(file_aux, VHDLFile): 137 | command_key = 'vhdl' 138 | elif (isinstance(file_aux, VerilogFile) or 139 | isinstance(file_aux, SVFile)): 140 | command_key = 'vlog' 141 | self.writeln("\t\t" + self._simulator_controls[command_key]) 142 | self.write("\t\t@" + shell.mkdir_command() + " $(dir $@)") 143 | self.writeln(" && " + shell.touch_command() + " $@ \n") 144 | self.writeln() 145 | 146 | def _makefile_sim_command(self): 147 | """Generic method to write the simulation Makefile user commands""" 148 | sim_pre_cmd = self.manifest_dict.get("sim_pre_cmd", '') 149 | sim_post_cmd = self.manifest_dict.get("sim_post_cmd", '') 150 | sim_command = string.Template("""# USER SIM COMMANDS 151 | sim_pre_cmd: 152 | \t\t${sim_pre_cmd} 153 | sim_post_cmd: 154 | \t\t${sim_post_cmd} 155 | """) 156 | self.writeln(sim_command.substitute(sim_pre_cmd=sim_pre_cmd, 157 | sim_post_cmd=sim_post_cmd)) 158 | 159 | def _makefile_sim_clean(self): 160 | """Generic method to write the simulation Makefile user clean target""" 161 | self.makefile_clean() 162 | self.makefile_mrproper() 163 | 164 | def _makefile_sim_phony(self): 165 | """Print simulation PHONY target list to the Makefile""" 166 | self.writeln( 167 | ".PHONY: mrproper clean sim_pre_cmd sim_post_cmd simulation") 168 | -------------------------------------------------------------------------------- /hdlmake/tools/makefile.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/python 2 | # -*- coding: utf-8 -*- 3 | # 4 | # Copyright (c) 2013, 2014 CERN 5 | # Author: Pawel Szostek (pawel.szostek@cern.ch) 6 | # Modified to allow ISim simulation by Lucas Russo (lucas.russo@lnls.br) 7 | # Multi-tool support by Javier D. Garcia-Lasheras (javier@garcialasheras.com) 8 | # 9 | # This file is part of Hdlmake. 10 | # 11 | # Hdlmake is free software: you can redistribute it and/or modify 12 | # it under the terms of the GNU General Public License as published by 13 | # the Free Software Foundation, either version 3 of the License, or 14 | # (at your option) any later version. 15 | # 16 | # Hdlmake is distributed in the hope that it will be useful, 17 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 18 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 | # GNU General Public License for more details. 20 | # 21 | # You should have received a copy of the GNU General Public License 22 | # along with Hdlmake. If not, see . 23 | 24 | """Module providing the core functionality for writing Makefiles""" 25 | 26 | from __future__ import absolute_import 27 | import os 28 | import logging 29 | import six 30 | 31 | from hdlmake.util import shell 32 | 33 | 34 | class ToolMakefile(object): 35 | 36 | """Class that provides the Makefile writing methods and status""" 37 | 38 | def __init__(self): 39 | super(ToolMakefile, self).__init__() 40 | self._file = None 41 | self._initialized = False 42 | self._tool_info = {} 43 | self._clean_targets = {} 44 | self._tcl_controls = {} 45 | self._hdl_files = {} 46 | self._supported_files = {} 47 | self._standard_libs = [] 48 | self.fileset = None 49 | self.manifest_dict = {} 50 | self._filename = "Makefile" 51 | 52 | def __del__(self): 53 | if self._file: 54 | self._file.close() 55 | 56 | def get_standard_libs(self): 57 | """Get the standard libs supported by the tool""" 58 | return self._standard_libs 59 | 60 | def get_parseable_files(self): 61 | """Get the parseable HDL file types supported by the tool""" 62 | return self._hdl_files 63 | 64 | def get_privative_files(self): 65 | """Get the privative format file types supported by the tool""" 66 | return self._supported_files 67 | 68 | def makefile_setup(self, manifest_project_dict, fileset, filename=None): 69 | """Set the Makefile configuration""" 70 | self.manifest_dict = manifest_project_dict 71 | self.fileset = fileset 72 | if filename: 73 | self._filename = filename 74 | 75 | def _get_name_bin(self): 76 | """Get the name and binary values""" 77 | if shell.check_windows(): 78 | bin_name = self._tool_info['windows_bin'] 79 | else: 80 | bin_name = self._tool_info['linux_bin'] 81 | return bin_name 82 | 83 | def _get_path(self): 84 | """Get the directory in which the tool binary is at Host""" 85 | bin_name = self._get_name_bin() 86 | locations = shell.which(bin_name) 87 | if len(locations) == 0: 88 | return 89 | logging.debug("location for %s: %s", bin_name, locations[0]) 90 | return os.path.dirname(locations[0]) 91 | 92 | def _is_in_path(self, path_key): 93 | """Check if the directory is in the system path""" 94 | path = self.manifest_dict.get(path_key) 95 | bin_name = self._get_name_bin() 96 | if path is not None: 97 | return os.path.exists(os.path.join(path, bin_name)) 98 | else: 99 | assert isinstance(bin_name, six.string_types) 100 | path = self._get_path() 101 | return len(path) > 0 102 | 103 | def _check_in_system_path(self): 104 | """Check if if in the system path exists a file named (name)""" 105 | path = self._get_path() 106 | if path: 107 | return True 108 | else: 109 | return False 110 | 111 | def makefile_check_tool(self, path_key): 112 | """Check if the binary is available in the O.S. environment""" 113 | name = self._tool_info['name'] 114 | logging.debug("Checking if " + name + " tool is available on PATH") 115 | if path_key in self.manifest_dict: 116 | if self._is_in_path(path_key): 117 | logging.info("%s found under HDLMAKE_%s: %s", 118 | name, path_key.upper(), 119 | self.manifest_dict[path_key]) 120 | else: 121 | logging.warning("%s NOT found under HDLMAKE_%s: %s", 122 | name, path_key.upper(), 123 | self.manifest_dict[path_key]) 124 | self.manifest_dict[path_key] = '' 125 | else: 126 | if self._check_in_system_path(): 127 | self.manifest_dict[path_key] = self._get_path() 128 | logging.info("%s found in system PATH: %s", 129 | name, self.manifest_dict[path_key]) 130 | else: 131 | logging.warning("%s cannnot be found in system PATH", name) 132 | self.manifest_dict[path_key] = '' 133 | 134 | def makefile_includes(self): 135 | """Add the included makefiles that need to be previously loaded""" 136 | #for file_aux in self.top_module.incl_makefiles: 137 | # if os.path.exists(file_aux): 138 | # self.write("include %s\n" % file_aux) 139 | pass 140 | 141 | def makefile_clean(self): 142 | """Print the Makefile target for cleaning intermediate files""" 143 | self.writeln("CLEAN_TARGETS := $(LIBS) " + 144 | ' '.join(self._clean_targets["clean"]) + "\n") 145 | self.writeln("clean:") 146 | tmp = "\t\t" + shell.del_command() + " $(CLEAN_TARGETS)" 147 | self.writeln(tmp) 148 | if shell.check_windows(): 149 | tmp = "\t\t@-" + shell.rmdir_command() + \ 150 | " $(CLEAN_TARGETS) >nul 2>&1" 151 | self.writeln(tmp) 152 | 153 | def makefile_mrproper(self): 154 | """Print the Makefile target for cleaning final files""" 155 | self.writeln("mrproper: clean") 156 | tmp = "\t\t" + shell.del_command() + \ 157 | " " + ' '.join(self._clean_targets["mrproper"]) + "\n" 158 | self.writeln(tmp) 159 | 160 | def initialize(self): 161 | """Open the Makefile file and print a header if not initialized""" 162 | if not self._initialized: 163 | if os.path.exists(self._filename): 164 | if os.path.isfile(self._filename): 165 | os.remove(self._filename) 166 | elif os.path.isdir(self._filename): 167 | os.rmdir(self._filename) 168 | 169 | self._file = open(self._filename, "a+") 170 | self._initialized = True 171 | self.writeln("########################################") 172 | self.writeln("# This file was generated by hdlmake #") 173 | self.writeln("# http://ohwr.org/projects/hdl-make/ #") 174 | self.writeln("########################################") 175 | self.writeln() 176 | elif not self._file: 177 | self._file = open(self._filename, "a+") 178 | 179 | def write(self, line=None): 180 | """Write a string in the manifest, no new line""" 181 | if not self._initialized: 182 | self.initialize() 183 | if shell.check_windows(): 184 | self._file.write(line.replace('\\"', '"')) 185 | else: 186 | self._file.write(line) 187 | 188 | def writeln(self, text=None): 189 | """Write a string in the manifest, automatically add new line""" 190 | if text is None: 191 | self.write("\n") 192 | else: 193 | self.write(text + "\n") 194 | -------------------------------------------------------------------------------- /hdlmake/tools/makefile_writer.py: -------------------------------------------------------------------------------- 1 | """Module providing the synthesis functionality for writing Makefiles""" 2 | 3 | 4 | import logging 5 | 6 | def load_syn_tool(tool_name): 7 | """Funtion that checks the provided module_pool and generate an 8 | initialized instance of the the appropriated synthesis tool""" 9 | from .ise import ToolISE 10 | from .planahead import ToolPlanAhead 11 | from .vivado import ToolVivado 12 | from .quartus import ToolQuartus 13 | from .diamond import ToolDiamond 14 | from .libero import ToolLibero 15 | from .icestorm import ToolIcestorm 16 | available_tools = {'ise': ToolISE, 17 | 'planahead': ToolPlanAhead, 18 | 'vivado': ToolVivado, 19 | 'quartus': ToolQuartus, 20 | 'diamond': ToolDiamond, 21 | 'libero': ToolLibero, 22 | 'icestorm': ToolIcestorm} 23 | if tool_name in available_tools: 24 | logging.debug("Synthesis tool to be used found: %s", tool_name) 25 | return available_tools[tool_name]() 26 | else: 27 | logging.error("Unknown synthesis tool: %s", tool_name) 28 | quit() 29 | 30 | 31 | def load_sim_tool(tool_name): 32 | """Funtion that checks the provided module_pool and generate an 33 | initialized instance of the the appropriated simulation tool""" 34 | from .iverilog import ToolIVerilog 35 | from .isim import ToolISim 36 | from .modelsim import ToolModelsim 37 | from .active_hdl import ToolActiveHDL 38 | from .riviera import ToolRiviera 39 | from .ghdl import ToolGHDL 40 | from .vivado_sim import ToolVivadoSim 41 | available_tools = {'iverilog': ToolIVerilog, 42 | 'isim': ToolISim, 43 | 'modelsim': ToolModelsim, 44 | 'active_hdl': ToolActiveHDL, 45 | 'riviera': ToolRiviera, 46 | 'ghdl': ToolGHDL, 47 | 'vivado_sim': ToolVivadoSim} 48 | if tool_name in available_tools: 49 | logging.debug("Simulation tool to be used found: %s", tool_name) 50 | return available_tools[tool_name]() 51 | else: 52 | logging.error("Unknown simulation tool: %s", tool_name) 53 | quit() 54 | -------------------------------------------------------------------------------- /hdlmake/tools/modelsim.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/python 2 | # -*- coding: utf-8 -*- 3 | # 4 | # Copyright (c) 2013 - 2015 CERN 5 | # Author: Pawel Szostek (pawel.szostek@cern.ch) 6 | # Multi-tool support by Javier D. Garcia-Lasheras (javier@garcialasheras.com) 7 | # 8 | # This file is part of Hdlmake. 9 | # 10 | # Hdlmake is free software: you can redistribute it and/or modify 11 | # it under the terms of the GNU General Public License as published by 12 | # the Free Software Foundation, either version 3 of the License, or 13 | # (at your option) any later version. 14 | # 15 | # Hdlmake is distributed in the hope that it will be useful, 16 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 17 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 | # GNU General Public License for more details. 19 | # 20 | # You should have received a copy of the GNU General Public License 21 | # along with Hdlmake. If not, see . 22 | # 23 | 24 | """Module providing support for Mentor Modelsim simulation""" 25 | 26 | from __future__ import print_function 27 | from __future__ import absolute_import 28 | import os 29 | 30 | from .sim_makefile_support import VsimMakefileWriter 31 | 32 | 33 | class ToolModelsim(VsimMakefileWriter): 34 | 35 | """Class providing the interface for Mentor Modelsim simulator""" 36 | 37 | TOOL_INFO = {'name': 'Modelsim', 38 | 'id': 'modelsim', 39 | 'windows_bin': 'vsim.exe', 40 | 'linux_bin': 'vsim'} 41 | 42 | STANDARD_LIBS = ['ieee', 'std', 'altera_mf'] 43 | 44 | CLEAN_TARGETS = {'clean': ["modelsim.ini", "transcript"], 45 | 'mrproper': ["*.vcd", "*.wlf"]} 46 | 47 | def __init__(self): 48 | super(ToolModelsim, self).__init__() 49 | self.copy_rules["modelsim.ini"] = os.path.join( 50 | "$(MODELSIM_INI_PATH)", "modelsim.ini") 51 | self.additional_deps.append("modelsim.ini") 52 | self._tool_info.update(ToolModelsim.TOOL_INFO) 53 | self._clean_targets.update(ToolModelsim.CLEAN_TARGETS) 54 | self._standard_libs.extend(ToolModelsim.STANDARD_LIBS) 55 | 56 | def _makefile_sim_options(self): 57 | """Print the Modelsim options to the Makefile""" 58 | if "sim_path" in self.manifest_dict: 59 | modelsim_ini_path = os.path.join( 60 | self.manifest_dict["sim_path"], 61 | "..") 62 | else: 63 | modelsim_ini_path = os.path.join("$(HDLMAKE_MODELSIM_PATH)", "..") 64 | self.custom_variables["MODELSIM_INI_PATH"] = modelsim_ini_path 65 | modelsim_ini = "-modelsimini modelsim.ini " 66 | vcom_opt = self.manifest_dict.get("vcom_opt", '') 67 | self.manifest_dict["vcom_opt"] = modelsim_ini + vcom_opt 68 | vlog_opt = self.manifest_dict.get("vlog_opt", '') 69 | self.manifest_dict["vlog_opt"] = modelsim_ini + vlog_opt 70 | vmap_opt = self.manifest_dict.get("vmap_opt", '') 71 | self.manifest_dict["vmap_opt"] = modelsim_ini + vmap_opt 72 | super(ToolModelsim, self)._makefile_sim_options() 73 | -------------------------------------------------------------------------------- /hdlmake/tools/planahead.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/python 2 | # -*- coding: utf-8 -*- 3 | # 4 | # Copyright (c) 2013 - 2015 CERN 5 | # Author: Pawel Szostek (pawel.szostek@cern.ch) 6 | # Multi-tool support by Javier D. Garcia-Lasheras (javier@garcialasheras.com) 7 | # 8 | # This file is part of Hdlmake. 9 | # 10 | # Hdlmake is free software: you can redistribute it and/or modify 11 | # it under the terms of the GNU General Public License as published by 12 | # the Free Software Foundation, either version 3 of the License, or 13 | # (at your option) any later version. 14 | # 15 | # Hdlmake is distributed in the hope that it will be useful, 16 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 17 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 | # GNU General Public License for more details. 19 | # 20 | # You should have received a copy of the GNU General Public License 21 | # along with Hdlmake. If not, see . 22 | # 23 | 24 | """Module providing support for Xilinx PlanAhead synthesis""" 25 | 26 | from __future__ import absolute_import 27 | from .xilinx import ToolXilinx 28 | from hdlmake.srcfile import (UCFFile, NGCFile, XMPFile, XCOFile) 29 | 30 | 31 | class ToolPlanAhead(ToolXilinx): 32 | 33 | """Class providing the interface for Xilinx PlanAhead synthesis""" 34 | 35 | TOOL_INFO = { 36 | 'name': 'PlanAhead', 37 | 'id': 'planahead', 38 | 'windows_bin': 'planAhead.exe -mode tcl -source', 39 | 'linux_bin': 'planAhead -mode tcl -source', 40 | 'project_ext': 'ppr'} 41 | 42 | STANDARD_LIBS = ['ieee', 'ieee_proposed', 'simprims', 'std', 43 | 'synopsys', 'unimacro', 'unisim', 'XilinxCoreLib'] 44 | 45 | SUPPORTED_FILES = { 46 | UCFFile: ToolXilinx._XILINX_SOURCE, 47 | NGCFile: ToolXilinx._XILINX_SOURCE, 48 | XMPFile: ToolXilinx._XILINX_SOURCE, 49 | XCOFile: ToolXilinx._XILINX_SOURCE} 50 | 51 | CLEAN_TARGETS = {'clean': ["planAhead_*", "planAhead.*", 52 | ".Xil", "$(PROJECT).cache", "$(PROJECT).data", 53 | " $(PROJECT).runs", "$(PROJECT).ppr"]} 54 | 55 | TCL_CONTROLS = {'bitstream': '$(TCL_OPEN)\n' 56 | 'launch_runs impl_1 -to_step Bitgen\n' 57 | 'wait_on_run impl_1\n' 58 | '$(TCL_CLOSE)'} 59 | 60 | def __init__(self): 61 | super(ToolPlanAhead, self).__init__() 62 | self._tool_info.update(ToolPlanAhead.TOOL_INFO) 63 | self._supported_files.update(ToolPlanAhead.SUPPORTED_FILES) 64 | self._standard_libs.extend(ToolPlanAhead.STANDARD_LIBS) 65 | self._clean_targets.update(ToolPlanAhead.CLEAN_TARGETS) 66 | self._tcl_controls.update(ToolPlanAhead.TCL_CONTROLS) 67 | -------------------------------------------------------------------------------- /hdlmake/tools/riviera.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/python 2 | # -*- coding: utf-8 -*- 3 | # 4 | # Copyright (c) 2013 - 2015 CERN 5 | # Author: Pawel Szostek (pawel.szostek@cern.ch) 6 | # Multi-tool support by Javier D. Garcia-Lasheras (javier@garcialasheras.com) 7 | # Riviera tool added by Josh Smith (joshrsmith@gmail.com) 8 | # 9 | # This file is part of Hdlmake. 10 | # 11 | # Hdlmake is free software: you can redistribute it and/or modify 12 | # it under the terms of the GNU General Public License as published by 13 | # the Free Software Foundation, either version 3 of the License, or 14 | # (at your option) any later version. 15 | # 16 | # Hdlmake is distributed in the hope that it will be useful, 17 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 18 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 | # GNU General Public License for more details. 20 | # 21 | # You should have received a copy of the GNU General Public License 22 | # along with Hdlmake. If not, see . 23 | # 24 | 25 | """Module providing support for Aldec Riviera-PRO simulation""" 26 | 27 | from __future__ import print_function 28 | from .sim_makefile_support import VsimMakefileWriter 29 | 30 | # as of 2014.06, these are the standard libraries 31 | # included in an installation 32 | RIVIERA_STANDARD_LIBS = [ 33 | 'ieee', 'std', 'cpld', 34 | 'vl', 'vital95', 'vital2000', 35 | 'synopsys', 'aldec', 'vtl', 36 | 'vtl_dbg', 'assertions', 'ieee_proposed', 37 | 'ovm_2_0_3', 'ovm_2_1_2', 'uvm_1_0p1', 38 | 'uvm_1_1d', 'uvm', 'osvvm', 39 | ] 40 | 41 | # there are many vendor specific libraries available 42 | # a few of them are listed here 43 | RIVIERA_XILINX_VHDL_LIBRARIES = [ 44 | 'cpld', 45 | 'secureip', 46 | 'simprim', 47 | 'unimacro', 48 | 'unisim', 49 | 'xilinxcorelib' 50 | ] 51 | RIVIERA_XILINX_VLOG_LIBRARIES = [ 52 | 'cpld_ver', 53 | 'secureip', 54 | 'simprims_ver', 55 | 'uni9000_ver', 56 | 'unimacro_ver', 57 | 'unisims_ver', 58 | 'xilinxcorelib_ver' 59 | ] 60 | 61 | RIVIERA_STANDARD_LIBS.extend(RIVIERA_XILINX_VHDL_LIBRARIES) 62 | RIVIERA_STANDARD_LIBS.extend(RIVIERA_XILINX_VLOG_LIBRARIES) 63 | 64 | 65 | class ToolRiviera(VsimMakefileWriter): 66 | 67 | """Class providing the interface for Aldec Riviera-PRO simulator""" 68 | 69 | TOOL_INFO = { 70 | 'name': 'Riviera', 71 | 'id': 'riviera', 72 | 'windows_bin': 'vsim.exe', 73 | 'linux_bin': 'vsim'} 74 | 75 | STANDARD_LIBS = RIVIERA_STANDARD_LIBS 76 | 77 | CLEAN_TARGETS = {'clean': ["*.asdb"], 78 | 'mrproper': ["*.vcd"]} 79 | 80 | def __init__(self): 81 | super(ToolRiviera, self).__init__() 82 | self._tool_info.update(ToolRiviera.TOOL_INFO) 83 | self._standard_libs.extend(ToolRiviera.STANDARD_LIBS) 84 | self._clean_targets.update(ToolRiviera.CLEAN_TARGETS) 85 | 86 | def _makefile_sim_options(self): 87 | """Print the Riviera options to the Makefile""" 88 | vcom_opt = self.manifest_dict.get("vcom_opt", '') 89 | self.manifest_dict["vcom_opt"] = "-2008 " + vcom_opt 90 | super(ToolRiviera, self)._makefile_sim_options() 91 | -------------------------------------------------------------------------------- /hdlmake/tools/sim_makefile_support.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/python 2 | # -*- coding: utf-8 -*- 3 | # 4 | # Copyright (c) 2013 - 2015 CERN 5 | # Author: Pawel Szostek (pawel.szostek@cern.ch) 6 | # Multi-tool support by Javier D. Garcia-Lasheras (javier@garcialasheras.com) 7 | # 8 | # This file is part of Hdlmake. 9 | # 10 | # Hdlmake is free software: you can redistribute it and/or modify 11 | # it under the terms of the GNU General Public License as published by 12 | # the Free Software Foundation, either version 3 of the License, or 13 | # (at your option) any later version. 14 | # 15 | # Hdlmake is distributed in the hope that it will be useful, 16 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 17 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 | # GNU General Public License for more details. 19 | # 20 | # You should have received a copy of the GNU General Public License 21 | # along with Hdlmake. If not, see . 22 | # 23 | 24 | """Module providing common stuff for Modelsim, Vsim... like simulators""" 25 | 26 | from __future__ import absolute_import 27 | import os 28 | import string 29 | 30 | from .make_sim import ToolSim 31 | from hdlmake.util import shell 32 | from hdlmake.srcfile import VerilogFile, VHDLFile, SVFile 33 | import six 34 | 35 | 36 | class VsimMakefileWriter(ToolSim): 37 | 38 | """A Makefile writer for simulation suitable for vsim based simulators. 39 | 40 | Currently used by: 41 | - Modelsim 42 | - Riviera 43 | """ 44 | 45 | HDL_FILES = {VerilogFile: '', VHDLFile: '', SVFile: ''} 46 | 47 | def __init__(self): 48 | super(VsimMakefileWriter, self).__init__() 49 | # These are variables that will be set in the makefile 50 | # The key is the variable name, and the value is the variable value 51 | self.custom_variables = {} 52 | # Additional sim dependencies (e.g. modelsim.ini) 53 | self.additional_deps = [] 54 | # These are files copied into your working directory by a make rule 55 | # The key is the filename, the value is the file source path 56 | self.copy_rules = {} 57 | self._hdl_files.update(VsimMakefileWriter.HDL_FILES) 58 | 59 | def _makefile_sim_options(self): 60 | """Print the vsim options to the Makefile""" 61 | def __get_rid_of_vsim_incdirs(vlog_opt=""): 62 | """Parse the VLOG options and purge the included dirs""" 63 | if not vlog_opt: 64 | vlog_opt = "" 65 | vlogs = vlog_opt.split(' ') 66 | ret = [] 67 | for vlog_aux in vlogs: 68 | if not vlog_aux.startswith("+incdir+"): 69 | ret.append(vlog_aux) 70 | return ' '.join(ret) 71 | vcom_flags = "-quiet " + self.manifest_dict.get("vcom_opt", '') 72 | vsim_flags = "" + self.manifest_dict.get("vsim_opt", '') 73 | vlog_flags = "-quiet " + __get_rid_of_vsim_incdirs( 74 | self.manifest_dict.get("vlog_opt", '')) 75 | vmap_flags = "" + self.manifest_dict.get("vmap_opt", '') 76 | for var, value in six.iteritems(self.custom_variables): 77 | self.writeln("%s := %s" % (var, value)) 78 | self.writeln() 79 | self.writeln("VCOM_FLAGS := %s" % vcom_flags) 80 | self.writeln("VSIM_FLAGS := %s" % vsim_flags) 81 | self.writeln("VLOG_FLAGS := %s" % vlog_flags) 82 | self.writeln("VMAP_FLAGS := %s" % vmap_flags) 83 | 84 | def _makefile_sim_compilation(self): 85 | """Write a properly formatted Makefile for the simulator. 86 | The Makefile format is shared, but flags, dependencies, clean rules, 87 | etc are defined by the specific tool. 88 | """ 89 | def __create_copy_rule(name, src): 90 | """Get a Makefile rule named name, which depends on src, 91 | copying it to the local directory.""" 92 | rule = """%s: %s 93 | \t\t%s $< . 2>&1 94 | """ % (name, src, shell.copy_command()) 95 | return rule 96 | fileset = self.fileset 97 | # self.writeln("INCLUDE_DIRS := +incdir+%s" % 98 | # ('+'.join(top_module.include_dirs))) 99 | libs = set(f.library for f in fileset) 100 | self.write('LIBS := ') 101 | self.write(' '.join(libs)) 102 | self.write('\n') 103 | # tell how to make libraries 104 | self.write('LIB_IND := ') 105 | self.write(' '.join([lib + shell.slash_char() + 106 | "." + lib for lib in libs])) 107 | self.write('\n') 108 | self.writeln() 109 | self.writeln( 110 | "simulation: %s $(LIB_IND) $(VERILOG_OBJ) $(VHDL_OBJ)" % 111 | (' '.join(self.additional_deps)),) 112 | self.writeln("$(VERILOG_OBJ) : " + ' '.join(self.additional_deps)) 113 | self.writeln( 114 | "$(VHDL_OBJ): $(LIB_IND) " + 115 | ' '.join( 116 | self.additional_deps)) 117 | self.writeln() 118 | for filename, filesource in six.iteritems(self.copy_rules): 119 | self.write(__create_copy_rule(filename, filesource)) 120 | for lib in libs: 121 | self.write(lib + shell.slash_char() + "." + lib + ":\n") 122 | vmap_command = "vmap $(VMAP_FLAGS)" 123 | self.write(' '.join(["\t(vlib", lib, "&&", vmap_command, lib, "&&", 124 | shell.touch_command(), lib + shell.slash_char() + 125 | "." + lib, ")"])) 126 | self.write(' '.join(["||", shell.del_command(), lib, "\n"])) 127 | self.write('\n\n') 128 | # rules for all _primary.dat files for sv 129 | for vlog in fileset.filter(VerilogFile): 130 | self.write("%s: %s" % (os.path.join( 131 | vlog.library, vlog.purename, 132 | ".%s_%s" % (vlog.purename, vlog.extension())), 133 | vlog.rel_path())) 134 | # list dependencies, do not include the target file 135 | for dep_file in [dfile for dfile 136 | in vlog.depends_on if dfile is not vlog]: 137 | if dep_file in fileset: 138 | name = dep_file.purename 139 | extension = dep_file.extension() 140 | self.write(" \\\n" + os.path.join( 141 | dep_file.library, name, ".%s_%s" % (name, extension))) 142 | else: # the file is included -> we depend directly on the file 143 | self.write(" \\\n" + dep_file.rel_path()) 144 | self.writeln() 145 | compile_template = string.Template( 146 | "\t\tvlog -work ${library} $$(VLOG_FLAGS) " 147 | "${sv_option} $${INCLUDE_DIRS} $$<") 148 | compile_line = compile_template.substitute( 149 | library=vlog.library, sv_option="-sv" 150 | if isinstance(vlog, SVFile) else "") 151 | self.writeln(compile_line) 152 | self.write("\t\t@" + shell.mkdir_command() + " $(dir $@)") 153 | self.writeln(" && " + shell.touch_command() + " $@ \n\n") 154 | self.writeln() 155 | # list rules for all _primary.dat files for vhdl 156 | for vhdl in fileset.filter(VHDLFile): 157 | lib = vhdl.library 158 | purename = vhdl.purename 159 | # each .dat depends on corresponding .vhd file 160 | self.write("%s: %s" % (os.path.join( 161 | lib, purename, "." + purename + "_" + vhdl.extension()), 162 | vhdl.rel_path())) 163 | # list dependencies, do not include the target file 164 | for dep_file in [dfile for dfile in vhdl.depends_on 165 | if dfile is not vhdl]: 166 | if dep_file in fileset: 167 | name = dep_file.purename 168 | extension = dep_file.extension() 169 | self.write(" \\\n" + os.path.join(dep_file.library, 170 | name, ".%s_%s" % (name, extension))) 171 | else: 172 | self.write(" \\\n" + dep_file.rel_path()) 173 | self.writeln() 174 | self.writeln(' '.join(["\t\tvcom $(VCOM_FLAGS)", 175 | "-work", lib, "$< "])) 176 | self.writeln("\t\t@" + shell.mkdir_command() + 177 | " $(dir $@) && " + shell.touch_command() + " $@ \n\n") 178 | -------------------------------------------------------------------------------- /hdlmake/tools/vivado.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/python 2 | # -*- coding: utf-8 -*- 3 | # 4 | # Copyright (c) 2013 - 2015 CERN 5 | # Author: Pawel Szostek (pawel.szostek@cern.ch) 6 | # Multi-tool support by Javier D. Garcia-Lasheras (javier@garcialasheras.com) 7 | # 8 | # This file is part of Hdlmake. 9 | # 10 | # Hdlmake is free software: you can redistribute it and/or modify 11 | # it under the terms of the GNU General Public License as published by 12 | # the Free Software Foundation, either version 3 of the License, or 13 | # (at your option) any later version. 14 | # 15 | # Hdlmake is distributed in the hope that it will be useful, 16 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 17 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 | # GNU General Public License for more details. 19 | # 20 | # You should have received a copy of the GNU General Public License 21 | # along with Hdlmake. If not, see . 22 | # 23 | 24 | """Module providing support for Xilinx Vivado synthesis""" 25 | 26 | 27 | from __future__ import absolute_import 28 | from .xilinx import ToolXilinx 29 | from hdlmake.srcfile import (XDCFile, XCIFile, NGCFile, XMPFile, 30 | XCOFile, COEFile, BDFile, TCLFile, 31 | MIFFile, RAMFile, VHOFile, VEOFile) 32 | 33 | 34 | class ToolVivado(ToolXilinx): 35 | 36 | """Class providing the interface for Xilinx Vivado synthesis""" 37 | 38 | TOOL_INFO = { 39 | 'name': 'vivado', 40 | 'id': 'vivado', 41 | 'windows_bin': 'vivado -mode tcl -source', 42 | 'linux_bin': 'vivado -mode tcl -source', 43 | 'project_ext': 'xpr' 44 | } 45 | 46 | STANDARD_LIBS = ['ieee', 'std'] 47 | 48 | SUPPORTED_FILES = { 49 | XDCFile: ToolXilinx._XILINX_SOURCE, 50 | XCIFile: ToolXilinx._XILINX_SOURCE, 51 | NGCFile: ToolXilinx._XILINX_SOURCE, 52 | XMPFile: ToolXilinx._XILINX_SOURCE, 53 | XCOFile: ToolXilinx._XILINX_SOURCE, 54 | COEFile: ToolXilinx._XILINX_SOURCE, 55 | BDFile: ToolXilinx._XILINX_SOURCE, 56 | TCLFile: ToolXilinx._XILINX_SOURCE, 57 | MIFFile: ToolXilinx._XILINX_SOURCE, 58 | RAMFile: ToolXilinx._XILINX_SOURCE, 59 | VHOFile: ToolXilinx._XILINX_SOURCE, 60 | VEOFile: ToolXilinx._XILINX_SOURCE} 61 | 62 | CLEAN_TARGETS = {'clean': [".Xil", "*.jou", "*.log", "*.pb", "*.dmp", 63 | "$(PROJECT).cache", "$(PROJECT).data", "work", 64 | "$(PROJECT).runs", "$(PROJECT).hw", 65 | "$(PROJECT).ip_user_files", "$(PROJECT_FILE)"]} 66 | 67 | TCL_CONTROLS = {'bitstream': '$(TCL_OPEN)\n' 68 | 'launch_runs impl_1 -to_step write_bitstream' 69 | '\n' 70 | 'wait_on_run impl_1\n' 71 | '$(TCL_CLOSE)'} 72 | 73 | def __init__(self): 74 | super(ToolVivado, self).__init__() 75 | self._tool_info.update(ToolVivado.TOOL_INFO) 76 | self._supported_files.update(ToolVivado.SUPPORTED_FILES) 77 | self._standard_libs.extend(ToolVivado.STANDARD_LIBS) 78 | self._clean_targets.update(ToolVivado.CLEAN_TARGETS) 79 | self._tcl_controls.update(ToolVivado.TCL_CONTROLS) 80 | -------------------------------------------------------------------------------- /hdlmake/tools/vivado_sim.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/python 2 | # -*- coding: utf-8 -*- 3 | # 4 | # Copyright (c) 2013 - 2015 CERN 5 | # Author: Pawel Szostek (pawel.szostek@cern.ch) 6 | # Multi-tool support by Javier D. Garcia-Lasheras (javier@garcialasheras.com) 7 | # 8 | # This file is part of Hdlmake. 9 | # 10 | # Hdlmake is free software: you can redistribute it and/or modify 11 | # it under the terms of the GNU General Public License as published by 12 | # the Free Software Foundation, either version 3 of the License, or 13 | # (at your option) any later version. 14 | # 15 | # Hdlmake is distributed in the hope that it will be useful, 16 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 17 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 | # GNU General Public License for more details. 19 | # 20 | # You should have received a copy of the GNU General Public License 21 | # along with Hdlmake. If not, see . 22 | # 23 | 24 | """Module providing support for Xilinx Vivado simulation""" 25 | 26 | 27 | from __future__ import absolute_import 28 | from .make_sim import ToolSim 29 | from hdlmake.srcfile import VerilogFile, VHDLFile, SVFile 30 | 31 | class ToolVivadoSim(ToolSim): 32 | 33 | """Class providing the interface for Xilinx Vivado synthesis""" 34 | 35 | TOOL_INFO = { 36 | 'name': 'vivado-sim', 37 | 'id': 'vivado-sim', 38 | 'windows_bin': 'vivado -mode tcl -source', 39 | 'linux_bin': 'vivado -mode tcl -source', 40 | } 41 | 42 | STANDARD_LIBS = ['ieee', 'std'] 43 | 44 | HDL_FILES = {VerilogFile: '', VHDLFile: '', SVFile: ''} 45 | 46 | CLEAN_TARGETS = {'clean': [".Xil", "*.jou", "*.log", "*.pb", 47 | "work", "xsim.dir"], 48 | 'mrproper': ["*.wdb", "*.vcd"]} 49 | 50 | SIMULATOR_CONTROLS = {'vlog': 'xvlog $<', 51 | 'vhdl': 'xvhdl $<', 52 | 'compiler': 'xelab -debug all $(TOP_MODULE) ' 53 | '-s $(TOP_MODULE)'} 54 | 55 | def __init__(self): 56 | super(ToolVivadoSim, self).__init__() 57 | self._tool_info.update(ToolVivadoSim.TOOL_INFO) 58 | self._standard_libs.extend(ToolVivadoSim.STANDARD_LIBS) 59 | self._clean_targets.update(ToolVivadoSim.CLEAN_TARGETS) 60 | self._simulator_controls.update(ToolVivadoSim.SIMULATOR_CONTROLS) 61 | self._hdl_files.update(ToolVivadoSim.HDL_FILES) 62 | 63 | def _makefile_sim_compilation(self): 64 | """Generate compile simulation Makefile target for Vivado Simulator""" 65 | self.writeln("simulation: $(VERILOG_OBJ) $(VHDL_OBJ)") 66 | self.writeln("\t\t" + ToolVivadoSim.SIMULATOR_CONTROLS['compiler']) 67 | self.writeln() 68 | self._makefile_sim_dep_files() 69 | -------------------------------------------------------------------------------- /hdlmake/tools/xilinx.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/python 2 | # -*- coding: utf-8 -*- 3 | # 4 | # Copyright (c) 2013 - 2015 CERN 5 | # Author: Pawel Szostek (pawel.szostek@cern.ch) 6 | # Multi-tool support by Javier D. Garcia-Lasheras (javier@garcialasheras.com) 7 | # 8 | # This file is part of Hdlmake. 9 | # 10 | # Hdlmake is free software: you can redistribute it and/or modify 11 | # it under the terms of the GNU General Public License as published by 12 | # the Free Software Foundation, either version 3 of the License, or 13 | # (at your option) any later version. 14 | # 15 | # Hdlmake is distributed in the hope that it will be useful, 16 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 17 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 | # GNU General Public License for more details. 19 | # 20 | # You should have received a copy of the GNU General Public License 21 | # along with Hdlmake. If not, see . 22 | # 23 | 24 | """Module providing generic support for Xilinx synthesis tools""" 25 | 26 | 27 | from __future__ import absolute_import 28 | from .make_syn import ToolSyn 29 | from hdlmake.srcfile import VHDLFile, VerilogFile, SVFile, TCLFile 30 | import logging 31 | 32 | 33 | class ToolXilinx(ToolSyn): 34 | 35 | """Class providing the interface for Xilinx Vivado synthesis""" 36 | 37 | _XILINX_SOURCE = ( 38 | "add_files -norecurse $(sourcefile); " 39 | "set_property IS_GLOBAL_INCLUDE 1 [get_files $(sourcefile)]") 40 | 41 | HDL_FILES = { 42 | VHDLFile: _XILINX_SOURCE, 43 | VerilogFile: _XILINX_SOURCE, 44 | SVFile: _XILINX_SOURCE} 45 | 46 | SUPPORTED_FILES = {TCLFile: 'source $(sourcefile)'} 47 | 48 | CLEAN_TARGETS = {'mrproper': ["*.bit", "*.bin"]} 49 | 50 | _XILINX_RUN = '''\ 51 | $(TCL_OPEN) 52 | {1} 53 | reset_run {0} 54 | launch_runs {0} 55 | wait_on_run {0} 56 | set result [get_property STATUS [get_runs {0}]] 57 | set keyword [lindex [split '$$'result " "] end] 58 | if {{ '$$'keyword != \\"Complete!\\" }} {{ 59 | exit 1 60 | }} 61 | $(TCL_CLOSE)''' 62 | 63 | TCL_CONTROLS = {'create': 'create_project $(PROJECT) ./', 64 | 'open': 'open_project $(PROJECT_FILE)', 65 | 'close': 'exit', 66 | 'project': '$(TCL_CREATE)\n' 67 | '{0}\n' 68 | 'source files.tcl\n' 69 | 'update_compile_order -fileset sources_1\n' 70 | 'update_compile_order -fileset sim_1\n' 71 | '$(TCL_CLOSE)', 72 | 'synthesize': _XILINX_RUN, 73 | 'par': _XILINX_RUN, 74 | 'install_source': '$(PROJECT).runs/impl_1/$(SYN_TOP).bit'} 75 | 76 | def __init__(self): 77 | super(ToolXilinx, self).__init__() 78 | self._hdl_files.update(ToolXilinx.HDL_FILES) 79 | self._supported_files.update(ToolXilinx.SUPPORTED_FILES) 80 | self._clean_targets.update(ToolXilinx.CLEAN_TARGETS) 81 | self._tcl_controls.update(ToolXilinx.TCL_CONTROLS) 82 | 83 | def _get_properties(self): 84 | """Create the property list""" 85 | syn_properties = self.manifest_dict.get("syn_properties") 86 | properties = [ 87 | ['part', '$(SYN_DEVICE)' + 88 | '$(SYN_PACKAGE)' + 89 | '$(SYN_GRADE)', 'current_project'], 90 | ['target_language', 'VHDL', 'current_project'], 91 | ['top', '$(TOP_MODULE)', 'get_property srcset [current_run]']] 92 | fetchto = self.manifest_dict.get("fetchto") 93 | if not fetchto is None: 94 | properties.append(['ip_repo_paths', fetchto, 'current_fileset']) 95 | if not syn_properties is None: 96 | properties.extend(syn_properties) 97 | return properties 98 | 99 | def _makefile_syn_tcl(self): 100 | """Create a Xilinx synthesis project by TCL""" 101 | prop_val = 'set_property "{0}" "{1}" [{2}]' 102 | prop_opt = 'set_property -name {{{0}}} -value {{{1}}} -objects [{2}]' 103 | project_new = ['# project properties'] 104 | synthesize_new = ['# synthesize properties'] 105 | par_new = ['# par properties'] 106 | properties = self._get_properties() 107 | for prop in properties: 108 | if len(prop) > 1: 109 | tmp = prop_val 110 | name_list = prop[0].split() 111 | if len(name_list) == 2: 112 | if name_list[1] == "options": 113 | tmp = prop_opt 114 | else: 115 | logging.error('Unknown project property: %s', prop[0]) 116 | if len(prop) == 2: 117 | name_hierarchy = name_list[0].split(".") 118 | if name_hierarchy[0] == "steps": 119 | if name_hierarchy[1] == "synth_design": 120 | synthesize_new.append(tmp.format( 121 | prop[0], prop[1], 'get_runs synth_1')) 122 | else: 123 | par_new.append(tmp.format( 124 | prop[0], prop[1], 'get_runs impl_1')) 125 | else: 126 | project_new.append(tmp.format( 127 | prop[0], prop[1], 'current_project')) 128 | elif len(prop) == 3: 129 | project_new.append(tmp.format(prop[0], prop[1], prop[2])) 130 | else: 131 | logging.error('Unknown project property: %s', prop[0]) 132 | tmp_dict = {} 133 | tmp_dict["project"] = self._tcl_controls["project"] 134 | tmp_dict["synthesize"] = self._tcl_controls["synthesize"] 135 | tmp_dict["par"] = self._tcl_controls["par"] 136 | self._tcl_controls["project"] = tmp_dict["project"].format( 137 | "\n".join(project_new)) 138 | self._tcl_controls["synthesize"] = tmp_dict["synthesize"].format( 139 | "synth_1", 140 | "\n".join(synthesize_new)) 141 | self._tcl_controls["par"] = tmp_dict["par"].format( 142 | "impl_1", 143 | "\n".join(par_new)) 144 | super(ToolXilinx, self)._makefile_syn_tcl() 145 | -------------------------------------------------------------------------------- /hdlmake/util/__init__.py: -------------------------------------------------------------------------------- 1 | """This package provides common utils... but not used ad package yet!""" 2 | -------------------------------------------------------------------------------- /hdlmake/util/path.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/python 2 | # -*- coding: utf-8 -*- 3 | # 4 | # Copyright (c) 2013 CERN 5 | # Author: Pawel Szostek (pawel.szostek@cern.ch) 6 | # 7 | # This file is part of Hdlmake. 8 | # 9 | # Hdlmake is free software: you can redistribute it and/or modify 10 | # it under the terms of the GNU General Public License as published by 11 | # the Free Software Foundation, either version 3 of the License, or 12 | # (at your option) any later version. 13 | # 14 | # Hdlmake is distributed in the hope that it will be useful, 15 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 16 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 | # GNU General Public License for more details. 18 | # 19 | # You should have received a copy of the GNU General Public License 20 | # along with Hdlmake. If not, see . 21 | # 22 | 23 | """This module provides a set of functions that are commonly used in HDLMake""" 24 | 25 | from __future__ import print_function 26 | from __future__ import absolute_import 27 | import os 28 | 29 | 30 | def url_parse(url): 31 | """ 32 | Check if link to a repo seems to be correct. Filter revision 33 | number and branch 34 | """ 35 | url_clean, branch, rev = None, None, None 36 | if "@@" in url: 37 | url_clean, rev = url.split("@@") 38 | elif "::" in url: 39 | url_clean, branch = url.split("::") 40 | else: 41 | url_clean = url 42 | 43 | return (url_clean, branch, rev) 44 | 45 | 46 | def url_basename(url): 47 | """ 48 | Get basename from an url 49 | """ 50 | if url.endswith(".git"): 51 | parts = url[:-4].split("/") 52 | elif url[-1] == '/': 53 | parts = url[:-1].split("/") 54 | else: 55 | parts = url.split("/") 56 | ret = parts[-1] 57 | return ret 58 | 59 | 60 | def svn_basename(url): 61 | """ 62 | Get basename from an SVN url 63 | """ 64 | words = url.split('//') 65 | try: 66 | words = words[1].split('/') 67 | return '/'.join(words[1:]) 68 | except IndexError: 69 | return None 70 | 71 | 72 | def pathsplit(path, rest=None): 73 | """ 74 | Split the provided path and return as a tuple 75 | """ 76 | if rest is None: 77 | rest = [] 78 | (head, tail) = os.path.split(path) 79 | if len(head) < 1: 80 | return [tail] + rest 81 | if len(tail) < 1: 82 | return [head] + rest 83 | return pathsplit(head, [tail] + rest) 84 | 85 | 86 | def commonpath(path1, path2, common=None): 87 | """ 88 | Return the common path for the provided paths 89 | """ 90 | if common is None: 91 | common = [] 92 | if len(path1) < 1: 93 | return (common, path1, path2) 94 | if len(path2) < 1: 95 | return (common, path1, path2) 96 | if path1[0] != path2[0]: 97 | return (common, path1, path2) 98 | return commonpath(path1[1:], path2[1:], common + [path1[0]]) 99 | 100 | 101 | def is_rel_path(path): 102 | """Check if the given path is relative""" 103 | return not os.path.isabs(path) 104 | 105 | 106 | def is_abs_path(path): 107 | """Check if the given path is absolute""" 108 | return os.path.isabs(path) 109 | 110 | 111 | def relpath(path1, path2=None): 112 | """Return the relative path of one path with respect to the other""" 113 | if path2 is None: 114 | path2 = os.getcwd() 115 | if path1 == path2: 116 | return '.' 117 | return os.path.relpath(path1, path2) 118 | 119 | 120 | def rel2abs(path, base=None): 121 | """ 122 | converts a relative path to an absolute path. 123 | 124 | @param path the path to convert - if already absolute, is returned 125 | without conversion. 126 | @param base - optional. Defaults to the current directory. 127 | The base is intelligently concatenated to the given relative path. 128 | @return the relative path of path from base 129 | """ 130 | if base is None: 131 | base = os.getcwd() 132 | if os.path.isabs(path): 133 | return path 134 | retval = os.path.join(base, path) 135 | return os.path.abspath(retval) 136 | 137 | 138 | def compose(path, base=None): 139 | """Get the relative path composition of the provided path""" 140 | if base is None: 141 | base = os.getcwd() 142 | return os.path.relpath(os.path.abspath( 143 | os.path.join(base, path))) 144 | 145 | 146 | def flatten_list(sth): 147 | """Convert the argument in a list, being an empty list if none""" 148 | if sth is not None: 149 | if not isinstance(sth, (list, tuple)): 150 | sth = [sth] 151 | else: 152 | sth = [] 153 | return sth 154 | -------------------------------------------------------------------------------- /hdlmake/util/shell.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/python 2 | # -*- coding: utf-8 -*- 3 | # 4 | # Copyright (c) 2017 CERN 5 | # Author: Javier Garcia (jgarcia@gl-research.com) 6 | # 7 | # This file is part of Hdlmake. 8 | # 9 | # Hdlmake is free software: you can redistribute it and/or modify 10 | # it under the terms of the GNU General Public License as published by 11 | # the Free Software Foundation, either version 3 of the License, or 12 | # (at your option) any later version. 13 | # 14 | # Hdlmake is distributed in the hope that it will be useful, 15 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 16 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 | # GNU General Public License for more details. 18 | # 19 | # You should have received a copy of the GNU General Public License 20 | # along with Hdlmake. If not, see . 21 | # 22 | 23 | """This module provides stuff for cross shell and O.S. support""" 24 | 25 | from __future__ import print_function 26 | from __future__ import absolute_import 27 | import os 28 | import sys 29 | import platform 30 | import logging 31 | from subprocess import PIPE, Popen, CalledProcessError 32 | 33 | 34 | def run(command): 35 | """Execute a command in the shell and print the output lines as a list""" 36 | try: 37 | command_out = Popen(command, 38 | stdout=PIPE, 39 | stdin=PIPE, 40 | stderr=PIPE, 41 | close_fds=not check_windows(), 42 | shell=True) 43 | lines = command_out.stdout.readlines() 44 | if len(lines) == 0: 45 | return None 46 | return lines[0].strip() 47 | except CalledProcessError as process_error: 48 | logging.error("Cannot clean the module: %s", 49 | process_error.output) 50 | quit() 51 | 52 | 53 | def tclpath(path): 54 | """Convert a O.S. specific path into a TCL friendly one""" 55 | return path.replace(slash_char(), "/") 56 | 57 | 58 | def check_windows(): 59 | """Check if we are operating on a Windows filesystem""" 60 | if platform.system() == 'Windows' or sys.platform == 'cygwin': 61 | return True 62 | else: 63 | return False 64 | 65 | 66 | def del_command(): 67 | """Get a string with the O.S. specific delete command""" 68 | if check_windows(): 69 | return "del /s /q /f" 70 | else: 71 | return "rm -rf" 72 | 73 | 74 | def rmdir_command(): 75 | """Get a string with the O.S. specific remove directory command""" 76 | if check_windows(): 77 | return "rmdir /s /q" 78 | else: 79 | return "rm -rf" 80 | 81 | 82 | def copy_command(): 83 | """Get a string with the O.S. specific copy command""" 84 | if check_windows(): 85 | return "copy" 86 | else: 87 | return "cp" 88 | 89 | 90 | def mkdir_command(): 91 | """Get a string with the O.S. specific mkdir command""" 92 | if check_windows(): 93 | return "mkdir" 94 | else: 95 | return "mkdir -p" 96 | 97 | 98 | def touch_command(): 99 | """Get a string with the O.S. specific mkdir command""" 100 | if check_windows(): 101 | return "type nul >>" 102 | else: 103 | return "touch" 104 | 105 | 106 | def which(filename): 107 | """Implement the which function and return the paths as a string list""" 108 | locations = os.environ.get("PATH").split(os.pathsep) 109 | candidates = [] 110 | for location in locations: 111 | candidate = os.path.join(location, filename) 112 | if os.path.isfile(candidate.split()[0]): 113 | candidates.append(candidate) 114 | return candidates 115 | 116 | 117 | def which_cmd(): 118 | """Get a string with the O.S. specific which command""" 119 | if check_windows(): 120 | return "where" 121 | else: 122 | return "which" 123 | 124 | 125 | def slash_char(): 126 | """Get a string with the O.S. specific path separator""" 127 | if check_windows(): 128 | return "\\" 129 | else: 130 | return "/" 131 | 132 | 133 | def architecture(): 134 | """Get a string with the O.S. bus width""" 135 | import struct 136 | return 64 if struct.calcsize('P') * 8 == 64 else 32 137 | -------------------------------------------------------------------------------- /hdlmake/util/termcolor.py: -------------------------------------------------------------------------------- 1 | # coding: utf-8 2 | # Copyright (c) 2008-2011 Volvox Development Team 3 | # 4 | # Permission is hereby granted, free of charge, to any person obtaining a copy 5 | # of this software and associated documentation files (the "Software"), to deal 6 | # in the Software without restriction, including without limitation the rights 7 | # to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 8 | # copies of the Software, and to permit persons to whom the Software is 9 | # furnished to do so, subject to the following conditions: 10 | # 11 | # The above copyright notice and this permission notice shall be included in 12 | # all copies or substantial portions of the Software. 13 | # 14 | # THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 | # IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 | # FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 17 | # AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 18 | # LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 19 | # OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 20 | # THE SOFTWARE. 21 | # 22 | # Author: Konstantin Lepa 23 | 24 | """ANSII Color formatting for output in terminal.""" 25 | 26 | from __future__ import print_function 27 | from __future__ import absolute_import 28 | import os 29 | 30 | 31 | __ALL__ = ['colored', 'cprint'] 32 | 33 | VERSION = (1, 1, 0) 34 | 35 | ATTRIBUTES = dict( 36 | list(zip([ 37 | 'bold', 38 | 'dark', 39 | '', 40 | 'underline', 41 | 'blink', 42 | '', 43 | 'reverse', 44 | 'concealed' 45 | ], 46 | list(range(1, 9)) 47 | )) 48 | ) 49 | del ATTRIBUTES[''] 50 | 51 | 52 | HIGHLIGHTS = dict( 53 | list(zip([ 54 | 'on_grey', 55 | 'on_red', 56 | 'on_green', 57 | 'on_yellow', 58 | 'on_blue', 59 | 'on_magenta', 60 | 'on_cyan', 61 | 'on_white' 62 | ], 63 | list(range(40, 48)) 64 | )) 65 | ) 66 | 67 | 68 | COLORS = dict( 69 | list(zip([ 70 | 'grey', 71 | 'red', 72 | 'green', 73 | 'yellow', 74 | 'blue', 75 | 'magenta', 76 | 'cyan', 77 | 'white', 78 | ], 79 | list(range(30, 38)) 80 | )) 81 | ) 82 | 83 | 84 | RESET = '\033[0m' 85 | 86 | 87 | def colored(text, color=None, on_color=None, attrs=None): 88 | """Colorize text. 89 | 90 | Available text colors: 91 | red, green, yellow, blue, magenta, cyan, white. 92 | 93 | Available text highlights: 94 | on_red, on_green, on_yellow, on_blue, on_magenta, on_cyan, on_white. 95 | 96 | Available attributes: 97 | bold, dark, underline, blink, reverse, concealed. 98 | 99 | Example: 100 | colored('Hello, World!', 'red', 'on_grey', ['blue', 'blink']) 101 | colored('Hello, World!', 'green') 102 | """ 103 | if os.getenv('ANSI_COLORS_DISABLED') is None: 104 | fmt_str = '\033[%dm%s' 105 | if color is not None: 106 | text = fmt_str % (COLORS[color], text) 107 | 108 | if on_color is not None: 109 | text = fmt_str % (HIGHLIGHTS[on_color], text) 110 | 111 | if attrs is not None: 112 | for attr in attrs: 113 | text = fmt_str % (ATTRIBUTES[attr], text) 114 | 115 | text += RESET 116 | return text 117 | 118 | 119 | def cprint(text, color=None, on_color=None, attrs=None, **kwargs): 120 | """Print colorize text. 121 | 122 | It accepts arguments of print function. 123 | """ 124 | 125 | print((colored(text, color, on_color, attrs)), **kwargs) 126 | 127 | 128 | if __name__ == '__main__': 129 | print('Current terminal type: %s' % os.getenv('TERM')) 130 | print('Test basic colors:') 131 | cprint('Grey color', 'grey') 132 | cprint('Red color', 'red') 133 | cprint('Green color', 'green') 134 | cprint('Yellow color', 'yellow') 135 | cprint('Blue color', 'blue') 136 | cprint('Magenta color', 'magenta') 137 | cprint('Cyan color', 'cyan') 138 | cprint('White color', 'white') 139 | print(('-' * 78)) 140 | 141 | print('Test highlights:') 142 | cprint('On grey color', on_color='on_grey') 143 | cprint('On red color', on_color='on_red') 144 | cprint('On green color', on_color='on_green') 145 | cprint('On yellow color', on_color='on_yellow') 146 | cprint('On blue color', on_color='on_blue') 147 | cprint('On magenta color', on_color='on_magenta') 148 | cprint('On cyan color', on_color='on_cyan') 149 | cprint('On white color', color='grey', on_color='on_white') 150 | print('-' * 78) 151 | 152 | print('Test attributes:') 153 | cprint('Bold grey color', 'grey', attrs=['bold']) 154 | cprint('Dark red color', 'red', attrs=['dark']) 155 | cprint('Underline green color', 'green', attrs=['underline']) 156 | cprint('Blink yellow color', 'yellow', attrs=['blink']) 157 | cprint('Reversed blue color', 'blue', attrs=['reverse']) 158 | cprint('Concealed Magenta color', 'magenta', attrs=['concealed']) 159 | cprint('Bold underline reverse cyan color', 'cyan', 160 | attrs=['bold', 'underline', 'reverse']) 161 | cprint('Dark blink concealed white color', 'white', 162 | attrs=['dark', 'blink', 'concealed']) 163 | print(('-' * 78)) 164 | 165 | print('Test mixing:') 166 | cprint('Underline red on grey color', 'red', 'on_grey', 167 | ['underline']) 168 | cprint('Reversed green on red color', 'green', 'on_red', ['reverse']) 169 | -------------------------------------------------------------------------------- /setup.py: -------------------------------------------------------------------------------- 1 | import ez_setup 2 | ez_setup.use_setuptools() 3 | 4 | from setuptools import (setup, find_packages) 5 | 6 | exec(open('hdlmake/_version.py').read()) 7 | 8 | try: 9 | __version__ 10 | except Exception: 11 | __version__ = "0.0" # default if for some reason the exec did not work 12 | 13 | setup( 14 | name="hdlmake", 15 | version=__version__, 16 | description="Hdlmake generates multi-purpose makefiles for HDL projects management.", 17 | author="Javier D. Garcia-Lasheras", 18 | author_email="hdl-make@ohwr.org", 19 | license="GPLv3", 20 | url="http://www.ohwr.org/projects/hdl-make", 21 | packages=find_packages(), 22 | entry_points={ 23 | 'console_scripts': [ 24 | 'hdlmake = hdlmake.__main__:main', 25 | ], 26 | }, 27 | include_package_data=True, # use MANIFEST.in during install 28 | classifiers=[ 29 | "Development Status :: 5 - Production/Stable", 30 | "Environment :: Console", 31 | "Topic :: Utilities", 32 | "License :: OSI Approved :: GNU General Public License v3 (GPLv3)", 33 | "Topic :: Software Development :: Build Tools", 34 | ], 35 | ) 36 | -------------------------------------------------------------------------------- /tests/counter/modules/counter/verilog/Manifest.py: -------------------------------------------------------------------------------- 1 | files = [ 2 | "counter.v", 3 | ] 4 | 5 | -------------------------------------------------------------------------------- /tests/counter/modules/counter/verilog/counter.v: -------------------------------------------------------------------------------- 1 | //----------------------------------------------------- 2 | // Design : Simple 8-bit verilog counter 3 | // Author : Javier D. Garcia-Lasheras 4 | //----------------------------------------------------- 5 | 6 | module counter ( 7 | clock, 8 | clear, 9 | count, 10 | Q 11 | ); 12 | 13 | //--------- Cycles per second ------------------------- 14 | parameter cycles_per_second = 12000000; 15 | 16 | //--------- Output Ports ------------------------------ 17 | output [7:0] Q; 18 | 19 | //--------- Input Ports ------------------------------- 20 | input clock, clear, count; 21 | 22 | //--------- Internal Variables ------------------------ 23 | reg ready = 0; 24 | reg [23:0] divider; 25 | reg [7:0] Q; 26 | 27 | //--------- Code Starts Here -------------------------- 28 | 29 | always @(posedge clock) begin 30 | if (ready) 31 | begin 32 | if (divider == cycles_per_second) 33 | begin 34 | divider <= 0; 35 | Q <= {Q[6:0], Q[7]}; 36 | end 37 | else 38 | divider <= divider + 1; 39 | end 40 | else 41 | begin 42 | ready <= 1; 43 | Q <= 8'b00010001; 44 | divider <= 0; 45 | end 46 | end 47 | 48 | 49 | endmodule 50 | -------------------------------------------------------------------------------- /tests/counter/modules/counter/vhdl/Manifest.py: -------------------------------------------------------------------------------- 1 | files = [ 2 | "counter.vhd", 3 | ] 4 | 5 | -------------------------------------------------------------------------------- /tests/counter/modules/counter/vhdl/counter.vhd: -------------------------------------------------------------------------------- 1 | ------------------------------------------------------- 2 | -- Design : Simple 8-bit VHDL counter 3 | -- Author : Javier D. Garcia-Lasheras 4 | ------------------------------------------------------- 5 | 6 | library ieee ; 7 | use ieee.std_logic_1164.all; 8 | use ieee.numeric_std.all; 9 | 10 | ------------------------------------------------------- 11 | 12 | entity counter is 13 | 14 | generic (cycles_per_second : integer := 12000000); 15 | 16 | port( 17 | clock: in std_logic; 18 | clear: in std_logic; 19 | count: in std_logic; 20 | Q: out std_logic_vector(7 downto 0) 21 | ); 22 | end counter; 23 | 24 | ------------------------------------------------------- 25 | 26 | architecture behv of counter is 27 | signal ready: std_logic; 28 | signal Pre_Q: unsigned(7 downto 0); 29 | signal divider: unsigned(23 downto 0); 30 | 31 | begin 32 | 33 | process(clock, count, clear) 34 | begin 35 | if (clock='1' and clock'event) then 36 | if ready = '1' then 37 | if divider = cycles_per_second then 38 | divider <= (others => '0'); 39 | Pre_Q(7 downto 1) <= Pre_Q(6 downto 0); 40 | Pre_Q(0) <= Pre_Q(7); 41 | else 42 | divider <= divider + 1; 43 | end if; 44 | else 45 | ready <= '1'; 46 | Pre_Q <= "00010001"; 47 | divider <= (others => '0'); 48 | end if; 49 | end if; 50 | end process; 51 | 52 | Q <= std_logic_vector(Pre_Q); 53 | 54 | end behv; 55 | 56 | ------------------------------------------------------- 57 | -------------------------------------------------------------------------------- /tests/counter/sim/active_hdl/play_sim.do: -------------------------------------------------------------------------------- 1 | asim +access +r counter_tb 2 | trace -rec * 3 | run 6 us 4 | endsim 5 | quit 6 | -------------------------------------------------------------------------------- /tests/counter/sim/active_hdl/verilog/Manifest.py: -------------------------------------------------------------------------------- 1 | action = "simulation" 2 | sim_tool = "active_hdl" 3 | sim_top = "counter_tb" 4 | 5 | sim_post_cmd = "vsimsa -do ../play_sim.do; avhdl wave.asdb" 6 | 7 | modules = { 8 | "local" : [ "../../../testbench/counter_tb/verilog" ], 9 | } 10 | 11 | -------------------------------------------------------------------------------- /tests/counter/sim/active_hdl/vhdl/Manifest.py: -------------------------------------------------------------------------------- 1 | action = "simulation" 2 | sim_tool = "active_hdl" 3 | sim_top = "counter_tb" 4 | 5 | sim_post_cmd = "vsimsa -do ../play_sim.do; avhdl wave.asdb" 6 | 7 | modules = { 8 | "local" : [ "../../../testbench/counter_tb/vhdl" ], 9 | } 10 | 11 | -------------------------------------------------------------------------------- /tests/counter/sim/ghdl/vhdl/Manifest.py: -------------------------------------------------------------------------------- 1 | action = "simulation" 2 | sim_tool = "ghdl" 3 | sim_top = "counter_tb" 4 | 5 | sim_post_cmd = "ghdl -r counter_tb --stop-time=6us --vcd=counter_tb.vcd; gtkwave counter_tb.vcd" 6 | 7 | modules = { 8 | "local" : [ "../../../testbench/counter_tb/vhdl" ], 9 | } 10 | -------------------------------------------------------------------------------- /tests/counter/sim/isim/isim_cmd: -------------------------------------------------------------------------------- 1 | wave add / 2 | vcd dumpfile counter_tb.vcd 3 | vcd dumpvars -m counter_tb -l 1 4 | run 6000 ns 5 | #exit 6 | -------------------------------------------------------------------------------- /tests/counter/sim/isim/verilog/Manifest.py: -------------------------------------------------------------------------------- 1 | action = "simulation" 2 | target = "xilinx" 3 | sim_tool = "isim" 4 | sim_top = "counter_tb" 5 | 6 | sim_post_cmd = "./isim_proj -gui -tclbatch ../isim_cmd" 7 | 8 | modules = { 9 | "local" : [ "../../../testbench/counter_tb/verilog" ], 10 | } 11 | 12 | 13 | -------------------------------------------------------------------------------- /tests/counter/sim/isim/vhdl/Manifest.py: -------------------------------------------------------------------------------- 1 | action = "simulation" 2 | target = "xilinx" 3 | sim_tool = "isim" 4 | sim_top = "counter_tb" 5 | 6 | sim_post_cmd = "./isim_proj -gui -tclbatch ../isim_cmd" 7 | 8 | modules = { 9 | "local" : [ "../../../testbench/counter_tb/vhdl" ], 10 | } 11 | 12 | 13 | -------------------------------------------------------------------------------- /tests/counter/sim/iverilog/verilog/Manifest.py: -------------------------------------------------------------------------------- 1 | action = "simulation" 2 | sim_tool = "iverilog" 3 | sim_top = "counter_tb" 4 | 5 | sim_post_cmd = "vvp counter_tb.vvp; gtkwave counter_tb.vcd" 6 | 7 | modules = { 8 | "local" : [ "../../../testbench/counter_tb/verilog" ], 9 | } 10 | 11 | -------------------------------------------------------------------------------- /tests/counter/sim/iverilog/vhdl/Manifest.py: -------------------------------------------------------------------------------- 1 | action = "simulation" 2 | sim_tool = "iverilog" 3 | sim_top = "counter_tb" 4 | 5 | iverilog_opt = "-g2012" 6 | 7 | sim_pre_cmd ="echo IMPORTANT, IVerilog always needs a Verilog testbench, no matter if the DUT is written in VHDL!" 8 | sim_post_cmd = "vvp counter_tb.vvp; gtkwave counter_tb.vcd" 9 | 10 | files = [ 11 | "../../../modules/counter/vhdl/counter.vhd", 12 | "../../../testbench/counter_tb/verilog/counter_tb.v", 13 | ] 14 | 15 | -------------------------------------------------------------------------------- /tests/counter/sim/modelsim/verilog/Manifest.py: -------------------------------------------------------------------------------- 1 | action = "simulation" 2 | sim_tool = "modelsim" 3 | sim_top = "counter_tb" 4 | 5 | sim_post_cmd = "vsim -novopt -do ../vsim.do -i counter_tb" 6 | 7 | modules = { 8 | "local" : [ "../../../testbench/counter_tb/verilog" ], 9 | } 10 | -------------------------------------------------------------------------------- /tests/counter/sim/modelsim/vhdl/Manifest.py: -------------------------------------------------------------------------------- 1 | action = "simulation" 2 | sim_tool = "modelsim" 3 | sim_top = "counter_tb" 4 | 5 | sim_post_cmd = "vsim -do ../vsim.do -i counter_tb" 6 | 7 | modules = { 8 | "local" : [ "../../../testbench/counter_tb/vhdl" ], 9 | } 10 | -------------------------------------------------------------------------------- /tests/counter/sim/modelsim/vsim.do: -------------------------------------------------------------------------------- 1 | vcd file counter_tb.vcd; 2 | vcd add -r /*; 3 | add wave * 4 | run 6000ns; 5 | view wave; 6 | 7 | -------------------------------------------------------------------------------- /tests/counter/sim/riviera/verilog/Manifest.py: -------------------------------------------------------------------------------- 1 | action = "simulation" 2 | sim_tool = "riviera" 3 | sim_top = "counter_tb" 4 | 5 | sim_post_cmd = "vsim -do ../vsim.do" 6 | 7 | modules = { 8 | "local" : [ "../../../testbench/counter_tb/verilog" ], 9 | } 10 | -------------------------------------------------------------------------------- /tests/counter/sim/riviera/vhdl/Manifest.py: -------------------------------------------------------------------------------- 1 | action = "simulation" 2 | sim_tool = "riviera" 3 | sim_top = "counter_tb" 4 | 5 | sim_post_cmd = "vsim -do ../vsim.do" 6 | 7 | modules = { 8 | "local" : [ "../../../testbench/counter_tb/vhdl" ], 9 | } 10 | -------------------------------------------------------------------------------- /tests/counter/sim/riviera/vsim.do: -------------------------------------------------------------------------------- 1 | vsim counter_tb +access +r; 2 | add wave *; 3 | run 6000ns; 4 | -------------------------------------------------------------------------------- /tests/counter/sim/vivado/verilog/Manifest.py: -------------------------------------------------------------------------------- 1 | action = "simulation" 2 | sim_tool = "vivado_sim" 3 | sim_top = "counter_tb" 4 | 5 | sim_post_cmd = "xsim %s -gui" % sim_top 6 | 7 | modules = { 8 | "local" : [ "../../../testbench/counter_tb/verilog" ], 9 | } 10 | -------------------------------------------------------------------------------- /tests/counter/sim/vivado/vhdl/Manifest.py: -------------------------------------------------------------------------------- 1 | action = "simulation" 2 | sim_tool = "vivado_sim" 3 | sim_top = "counter_tb" 4 | 5 | sim_post_cmd = "xsim %s -gui" % sim_top 6 | 7 | modules = { 8 | "local" : [ "../../../testbench/counter_tb/vhdl" ], 9 | } 10 | -------------------------------------------------------------------------------- /tests/counter/syn/brevia2_dk_diamond/verilog/Manifest.py: -------------------------------------------------------------------------------- 1 | target = "lattice" 2 | action = "synthesis" 3 | 4 | syn_device = "lfxp2-5e" 5 | syn_grade = "-6" 6 | syn_package = "tn144c" 7 | syn_top = "brevia2_top" 8 | syn_project = "demo" 9 | syn_tool = "diamond" 10 | 11 | modules = { 12 | "local" : [ "../../../top/brevia2_dk/verilog" ], 13 | } 14 | 15 | -------------------------------------------------------------------------------- /tests/counter/syn/brevia2_dk_diamond/vhdl/Manifest.py: -------------------------------------------------------------------------------- 1 | target = "lattice" 2 | action = "synthesis" 3 | 4 | syn_device = "lfxp2-5e" 5 | syn_grade = "-6" 6 | syn_package = "tn144c" 7 | syn_top = "brevia2_top" 8 | syn_project = "demo" 9 | syn_tool = "diamond" 10 | 11 | modules = { 12 | "local" : [ "../../../top/brevia2_dk/vhdl" ], 13 | } 14 | 15 | -------------------------------------------------------------------------------- /tests/counter/syn/cyclone3_sk_quartus/verilog/Manifest.py: -------------------------------------------------------------------------------- 1 | target = "altera" 2 | action = "synthesis" 3 | 4 | syn_device = "ep3c25" 5 | syn_grade = "c6" 6 | syn_package = "f324" 7 | syn_top = "cyclone3_top" 8 | syn_project = "demo" 9 | syn_tool = "quartus" 10 | 11 | quartus_preflow = "../../../top/cyclone3_sk/pinout.tcl" 12 | quartus_postmodule = "../../../top/cyclone3_sk/module.tcl" 13 | 14 | modules = { 15 | "local" : [ "../../../top/cyclone3_sk/verilog" ], 16 | } 17 | 18 | -------------------------------------------------------------------------------- /tests/counter/syn/cyclone3_sk_quartus/vhdl/Manifest.py: -------------------------------------------------------------------------------- 1 | target = "altera" 2 | action = "synthesis" 3 | 4 | syn_device = "ep3c25" 5 | syn_grade = "c6" 6 | syn_package = "f324" 7 | syn_top = "cyclone3_top" 8 | syn_project = "demo" 9 | syn_tool = "quartus" 10 | 11 | quartus_preflow = "../../../top/cyclone3_sk/pinout.tcl" 12 | quartus_postmodule = "../../../top/cyclone3_sk/module.tcl" 13 | 14 | modules = { 15 | "local" : [ "../../../top/cyclone3_sk/vhdl" ], 16 | } 17 | 18 | -------------------------------------------------------------------------------- /tests/counter/syn/icestick_icestorm/verilog/Manifest.py: -------------------------------------------------------------------------------- 1 | action = "synthesis" 2 | 3 | syn_device = "1k" 4 | syn_grade = "dummy" 5 | syn_package = "tq144" 6 | syn_top = "icestick_top" 7 | syn_project = "demo" 8 | syn_tool = "icestorm" 9 | 10 | modules = { 11 | "local" : [ "../../../top/icestick/verilog" ] 12 | } 13 | 14 | -------------------------------------------------------------------------------- /tests/counter/syn/proasic3_sk_libero/verilog/Manifest.py: -------------------------------------------------------------------------------- 1 | target = "microsemi" 2 | action = "synthesis" 3 | 4 | syn_device = "a3p250" 5 | syn_grade = "-2" 6 | syn_package = "208 pqfp" 7 | syn_top = "proasic3_top" 8 | syn_project = "demo" 9 | syn_tool = "libero" 10 | 11 | modules = { 12 | "local" : [ "../../../top/proasic3_sk/verilog" ], 13 | } 14 | 15 | 16 | -------------------------------------------------------------------------------- /tests/counter/syn/proasic3_sk_libero/vhdl/Manifest.py: -------------------------------------------------------------------------------- 1 | target = "microsemi" 2 | action = "synthesis" 3 | 4 | syn_device = "a3p250" 5 | syn_grade = "-2" 6 | syn_package = "208 pqfp" 7 | syn_top = "proasic3_top" 8 | syn_project = "demo" 9 | syn_tool = "libero" 10 | 11 | modules = { 12 | "local" : [ "../../../top/proasic3_sk/vhdl" ], 13 | } 14 | 15 | 16 | -------------------------------------------------------------------------------- /tests/counter/syn/spec_v4_ise/verilog/Manifest.py: -------------------------------------------------------------------------------- 1 | target = "xilinx" 2 | action = "synthesis" 3 | 4 | syn_device = "xc6slx45t" 5 | syn_grade = "-3" 6 | syn_package = "fgg484" 7 | syn_top = "spec_top" 8 | syn_project = "demo.xise" 9 | syn_tool = "ise" 10 | 11 | modules = { 12 | "local" : [ "../../../top/spec_v4/verilog" ], 13 | } 14 | 15 | -------------------------------------------------------------------------------- /tests/counter/syn/spec_v4_ise/vhdl/Manifest.py: -------------------------------------------------------------------------------- 1 | target = "xilinx" 2 | action = "synthesis" 3 | 4 | syn_device = "xc6slx45t" 5 | syn_grade = "-3" 6 | syn_package = "fgg484" 7 | syn_top = "spec_top" 8 | syn_project = "demo.xise" 9 | syn_tool = "ise" 10 | 11 | modules = { 12 | "local" : [ "../../../top/spec_v4/vhdl" ], 13 | } 14 | 15 | -------------------------------------------------------------------------------- /tests/counter/syn/spec_v4_planahead/verilog/Manifest.py: -------------------------------------------------------------------------------- 1 | target = "xilinx" 2 | action = "synthesis" 3 | 4 | syn_device = "xc6slx45t" 5 | syn_grade = "-3" 6 | syn_package = "fgg484" 7 | syn_top = "spec_top" 8 | syn_project = "demo" 9 | syn_tool = "planahead" 10 | 11 | modules = { 12 | "local" : [ "../../../top/spec_v4/verilog" ], 13 | } 14 | 15 | -------------------------------------------------------------------------------- /tests/counter/syn/spec_v4_planahead/vhdl/Manifest.py: -------------------------------------------------------------------------------- 1 | target = "xilinx" 2 | action = "synthesis" 3 | 4 | syn_device = "xc6slx45t" 5 | syn_grade = "-3" 6 | syn_package = "fgg484" 7 | syn_top = "spec_top" 8 | syn_project = "demo" 9 | syn_tool = "planahead" 10 | 11 | modules = { 12 | "local" : [ "../../../top/spec_v4/vhdl" ], 13 | } 14 | 15 | -------------------------------------------------------------------------------- /tests/counter/syn/zedboard_vivado/verilog/Manifest.py: -------------------------------------------------------------------------------- 1 | action = "synthesis" 2 | 3 | syn_device = "xc7z020" 4 | syn_grade = "-1" 5 | syn_package = "clg484" 6 | syn_top = "zedboard_top" 7 | syn_project = "zedboard_top" 8 | syn_tool = "vivado" 9 | 10 | modules = { 11 | "local" : [ "../../../top/zedboard/verilog" ], 12 | } 13 | 14 | 15 | -------------------------------------------------------------------------------- /tests/counter/syn/zedboard_vivado/vhdl/Manifest.py: -------------------------------------------------------------------------------- 1 | action = "synthesis" 2 | 3 | syn_device = "xc7z020" 4 | syn_grade = "-1" 5 | syn_package = "clg484" 6 | syn_top = "zedboard_top" 7 | syn_project = "zedboard_top" 8 | syn_tool = "vivado" 9 | 10 | modules = { 11 | "local" : [ "../../../top/zedboard/vhdl" ], 12 | } 13 | 14 | -------------------------------------------------------------------------------- /tests/counter/testbench/counter_tb/verilog/Manifest.py: -------------------------------------------------------------------------------- 1 | files = [ 2 | "counter_tb.v", 3 | ] 4 | 5 | modules = { 6 | "local" : [ "../../../modules/counter/verilog" ], 7 | } 8 | -------------------------------------------------------------------------------- /tests/counter/testbench/counter_tb/verilog/counter_tb.v: -------------------------------------------------------------------------------- 1 | //-------------------------------------------------------- 2 | // Design : Simple testbench for an 8-bit verilog counter 3 | // Author : Javier D. Garcia-Lasheras 4 | //-------------------------------------------------------- 5 | 6 | module counter_tb(); 7 | // Declare inputs as regs and outputs as wires 8 | reg clock, clear, count; 9 | wire [7:0] Q; 10 | 11 | defparam U_counter.cycles_per_second = 500; 12 | 13 | // Initialize all variables 14 | initial begin 15 | $dumpfile("counter_tb.vcd"); 16 | $dumpvars(0,counter_tb); 17 | $display ("time\t clock clear count Q"); 18 | $monitor ("%g\t %b %b %b %b", 19 | $time, clock, clear, count, Q); 20 | clock = 1; // initial value of clock 21 | clear = 0; // initial value of clear 22 | count = 0; // initial value of count enable 23 | #5 clear = 1; // Assert the clear signal 24 | #10 clear = 0; // De-assert clear signal 25 | #10 count = 1; // Start count 26 | #10000 count = 0; // De-assert count enable 27 | #5 $finish; // Terminate simulation 28 | end 29 | 30 | // Clock generator 31 | always begin 32 | #1 clock = ~clock; // Toggle clock every 5 ticks 33 | end 34 | 35 | // Connect DUT to test bench 36 | counter U_counter ( 37 | clock, 38 | clear, 39 | count, 40 | Q 41 | ); 42 | 43 | endmodule 44 | -------------------------------------------------------------------------------- /tests/counter/testbench/counter_tb/vhdl/Manifest.py: -------------------------------------------------------------------------------- 1 | files = [ 2 | "counter_tb.vhd", 3 | ] 4 | 5 | modules = { 6 | "local" : [ "../../../modules/counter/vhdl" ], 7 | } 8 | -------------------------------------------------------------------------------- /tests/counter/testbench/counter_tb/vhdl/counter_tb.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------- 2 | -- Design : Simple testbench for an 8-bit VHDL counter 3 | -- Author : Javier D. Garcia-Lasheras 4 | ---------------------------------------------------------- 5 | 6 | library ieee; 7 | use ieee.std_logic_1164.all; 8 | 9 | entity counter_tb is -- entity declaration 10 | end counter_tb; 11 | 12 | ----------------------------------------------------------------------- 13 | 14 | architecture testbench of counter_tb is 15 | 16 | component counter 17 | generic( 18 | cycles_per_second: integer 19 | ); 20 | port( 21 | clock: in std_logic; 22 | clear: in std_logic; 23 | count: in std_logic; 24 | Q: out std_logic_vector(7 downto 0) 25 | ); 26 | end component; 27 | 28 | signal t_clock: std_logic; 29 | signal t_clear: std_logic; 30 | signal t_count: std_logic; 31 | signal t_Q: std_logic_vector(7 downto 0); 32 | 33 | begin 34 | 35 | U_counter: counter 36 | generic map (cycles_per_second => 500) 37 | port map (t_clock, t_clear, t_count, t_Q); 38 | 39 | process 40 | begin 41 | t_clock <= '0'; -- clock cycle is 10 ns 42 | wait for 5 ns; 43 | t_clock <= '1'; 44 | wait for 5 ns; 45 | end process; 46 | 47 | process 48 | begin 49 | 50 | t_clear <= '1'; -- start counting 51 | t_count <= '1'; 52 | wait for 50 ns; 53 | 54 | t_clear <= '0'; -- clear output 55 | wait for 1000 ns; 56 | 57 | report "Testbench of Adder completed successfully!" 58 | severity note; 59 | wait; 60 | 61 | end process; 62 | 63 | end testbench; 64 | 65 | ---------------------------------------------------------------- 66 | -------------------------------------------------------------------------------- /tests/counter/top/brevia2_dk/brevia2_top.lpf: -------------------------------------------------------------------------------- 1 | BLOCK RESETPATHS ; 2 | BLOCK ASYNCPATHS ; 3 | LOCATE COMP "led_o_0" SITE "46" ; 4 | LOCATE COMP "led_o_1" SITE "45" ; 5 | LOCATE COMP "led_o_2" SITE "44" ; 6 | LOCATE COMP "led_o_3" SITE "43" ; 7 | LOCATE COMP "led_o_4" SITE "40" ; 8 | LOCATE COMP "led_o_5" SITE "39" ; 9 | LOCATE COMP "led_o_6" SITE "38" ; 10 | LOCATE COMP "led_o_7" SITE "37" ; 11 | LOCATE COMP "clear_i" SITE "50" ; 12 | LOCATE COMP "count_i" SITE "53" ; 13 | LOCATE COMP "clock_i" SITE "21" ; 14 | LOCATE COMP "clken_o" SITE "22" ; 15 | 16 | -------------------------------------------------------------------------------- /tests/counter/top/brevia2_dk/verilog/Manifest.py: -------------------------------------------------------------------------------- 1 | files = [ 2 | "brevia2_top.v", 3 | "../brevia2_top.lpf", 4 | ] 5 | 6 | modules = { 7 | "local" : [ "../../../modules/counter/verilog" ], 8 | } 9 | -------------------------------------------------------------------------------- /tests/counter/top/brevia2_dk/verilog/brevia2_top.v: -------------------------------------------------------------------------------- 1 | //-------------------------------------------------------- 2 | // Design : Counter verilog top module, Lattice Brevia2 3 | // Author : Javier D. Garcia-Lasheras 4 | //-------------------------------------------------------- 5 | 6 | module brevia2_top ( 7 | clear_i, 8 | count_i, 9 | clock_i, 10 | clken_o, 11 | led_o 12 | ); 13 | 14 | input clear_i, count_i, clock_i; 15 | output clken_o; 16 | output [7:0] led_o; 17 | 18 | wire s_clock, s_clear, s_count; 19 | wire [7:0] s_Q; 20 | 21 | counter u1( 22 | .clock(s_clock), 23 | .clear(s_clear), 24 | .count(s_count), 25 | .Q(s_Q) 26 | ); 27 | 28 | assign s_clock = clock_i; 29 | assign clken_o = 1; 30 | assign s_clear = ~clear_i; 31 | assign s_count = ~count_i; 32 | assign led_o[7:0] = ~s_Q[7:0]; 33 | 34 | endmodule 35 | -------------------------------------------------------------------------------- /tests/counter/top/brevia2_dk/vhdl/Manifest.py: -------------------------------------------------------------------------------- 1 | files = [ 2 | "brevia2_top.vhd", 3 | "../brevia2_top.lpf", 4 | ] 5 | 6 | modules = { 7 | "local" : [ "../../../modules/counter/vhdl" ], 8 | } 9 | -------------------------------------------------------------------------------- /tests/counter/top/brevia2_dk/vhdl/brevia2_top.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------- 2 | -- Design : Counter VHDL top module, Lattice Brevia2 3 | -- Author : Javier D. Garcia-Lasheras 4 | ---------------------------------------------------------- 5 | 6 | library ieee; 7 | use ieee.std_logic_1164.all; 8 | use ieee.std_logic_unsigned.all; 9 | use ieee.std_logic_arith.all; 10 | 11 | entity brevia2_top is 12 | port ( 13 | clear_i: in std_logic; 14 | count_i: in std_logic; 15 | clock_i: in std_logic; 16 | clken_o: out std_logic; 17 | led_o: out std_logic_vector(7 downto 0) 18 | ); 19 | end brevia2_top; 20 | 21 | ---------------------------------------------------------- 22 | 23 | architecture structure of brevia2_top is 24 | 25 | component counter 26 | port ( 27 | clock: in std_logic; 28 | clear: in std_logic; 29 | count: in std_logic; 30 | Q: out std_logic_vector(7 downto 0) 31 | ); 32 | end component; 33 | 34 | signal s_clock: std_logic; 35 | signal s_clear: std_logic; 36 | signal s_count: std_logic; 37 | signal s_Q: std_logic_vector(7 downto 0); 38 | 39 | begin 40 | 41 | U_counter: counter 42 | port map ( 43 | clock => s_clock, 44 | clear => s_clear, 45 | count => s_count, 46 | Q => s_Q 47 | ); 48 | 49 | s_clock <= clock_i; 50 | clken_o <= '1'; 51 | s_clear <= not clear_i; 52 | s_count <= not count_i; 53 | led_o <= not s_Q; 54 | 55 | end architecture structure; 56 | 57 | ---------------------------------------------------------------- 58 | -------------------------------------------------------------------------------- /tests/counter/top/cyclone3_sk/module.tcl: -------------------------------------------------------------------------------- 1 | 2 | set module [lindex $quartus(args) 0] 3 | 4 | 5 | if [string match "quartus_map" $module] { 6 | 7 | # Include commands here that are run 8 | # after analysis and synthesis 9 | post_message "Running after analysis & synthesis" 10 | } 11 | 12 | 13 | if [string match "quartus_fit" $module] { 14 | 15 | # Include commands here that are run 16 | # after fitter (Place & Route) 17 | post_message "Running after place & route" 18 | } 19 | 20 | 21 | if [string match "quartus_asm" $module] { 22 | 23 | # Include commands here that are run 24 | # after assembler (Generate programming files) 25 | post_message "Running after timing analysis" 26 | } 27 | 28 | 29 | if [string match "quartus_tan" $module] { 30 | 31 | # Include commands here that are run 32 | # after timing analysis 33 | post_message "Running after timing analysis" 34 | } 35 | 36 | 37 | -------------------------------------------------------------------------------- /tests/counter/top/cyclone3_sk/pinout.tcl: -------------------------------------------------------------------------------- 1 | 2 | post_message "Assigning pinout" 3 | 4 | # Load Quartus II Tcl Project package 5 | package require ::quartus::project 6 | 7 | project_open -revision demo demo 8 | 9 | set_location_assignment PIN_F1 -to clear_i 10 | set_location_assignment PIN_F2 -to count_i 11 | set_location_assignment PIN_B9 -to clock_i 12 | set_location_assignment PIN_N9 -to led_o[3] 13 | set_location_assignment PIN_N12 -to led_o[2] 14 | set_location_assignment PIN_P12 -to led_o[1] 15 | set_location_assignment PIN_P13 -to led_o[0] 16 | 17 | # Commit assignments 18 | export_assignments 19 | project_close 20 | 21 | -------------------------------------------------------------------------------- /tests/counter/top/cyclone3_sk/verilog/Manifest.py: -------------------------------------------------------------------------------- 1 | files = [ 2 | "cyclone3_top.v", 3 | ] 4 | 5 | modules = { 6 | "local" : [ "../../../modules/counter/verilog" ], 7 | } 8 | -------------------------------------------------------------------------------- /tests/counter/top/cyclone3_sk/verilog/cyclone3_top.v: -------------------------------------------------------------------------------- 1 | //-------------------------------------------------------------------- 2 | // Design : Counter verilog top module, Altera CycloneIII Starter Kit 3 | // Author : Javier D. Garcia-Lasheras 4 | //-------------------------------------------------------------------- 5 | 6 | module cyclone3_top ( 7 | clear_i, 8 | count_i, 9 | clock_i, 10 | led_o 11 | ); 12 | 13 | input clear_i, count_i, clock_i; 14 | output [3:0] led_o; 15 | 16 | wire s_clock, s_clear, s_count; 17 | wire [7:0] s_Q; 18 | 19 | counter u1( 20 | .clock(s_clock), 21 | .clear(s_clear), 22 | .count(s_count), 23 | .Q(s_Q) 24 | ); 25 | 26 | assign s_clock = clock_i; 27 | assign s_clear = ~clear_i; 28 | assign s_count = ~count_i; 29 | assign led_o[3:0] = ~s_Q[7:4]; 30 | 31 | endmodule 32 | -------------------------------------------------------------------------------- /tests/counter/top/cyclone3_sk/vhdl/Manifest.py: -------------------------------------------------------------------------------- 1 | files = [ 2 | "cyclone3_top.vhd", 3 | ] 4 | 5 | modules = { 6 | "local" : [ "../../../modules/counter/vhdl" ], 7 | } 8 | -------------------------------------------------------------------------------- /tests/counter/top/cyclone3_sk/vhdl/cyclone3_top.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------------- 2 | -- Design : Counter VHDL top module, Altera CycloneIII Starter Kit 3 | -- Author : Javier D. Garcia-Lasheras 4 | ---------------------------------------------------------------------- 5 | 6 | library ieee; 7 | use ieee.std_logic_1164.all; 8 | use ieee.std_logic_unsigned.all; 9 | use ieee.std_logic_arith.all; 10 | 11 | entity cyclone3_top is 12 | port ( 13 | clear_i: in std_logic; 14 | count_i: in std_logic; 15 | clock_i: in std_logic; 16 | led_o: out std_logic_vector(3 downto 0) 17 | ); 18 | end cyclone3_top; 19 | 20 | ---------------------------------------------------------------------- 21 | 22 | architecture structure of cyclone3_top is 23 | 24 | component counter 25 | port ( 26 | clock: in std_logic; 27 | clear: in std_logic; 28 | count: in std_logic; 29 | Q: out std_logic_vector(7 downto 0) 30 | ); 31 | end component; 32 | 33 | signal s_clock: std_logic; 34 | signal s_clear: std_logic; 35 | signal s_count: std_logic; 36 | signal s_Q: std_logic_vector(7 downto 0); 37 | 38 | begin 39 | 40 | U_counter: counter 41 | port map ( 42 | clock => s_clock, 43 | clear => s_clear, 44 | count => s_count, 45 | Q => s_Q 46 | ); 47 | 48 | s_clock <= clock_i; 49 | s_clear <= not clear_i; 50 | s_count <= not count_i; 51 | led_o(3 downto 0) <= not s_Q(7 downto 4); 52 | 53 | end architecture structure; 54 | 55 | ----------------------------------------------------------------------- 56 | 57 | -------------------------------------------------------------------------------- /tests/counter/top/icestick/icestick.pcf: -------------------------------------------------------------------------------- 1 | set_io led_o_0 99 2 | set_io led_o_1 98 3 | set_io led_o_2 97 4 | set_io led_o_3 96 5 | set_io led_o_4 95 6 | set_io clock_i 21 7 | 8 | -------------------------------------------------------------------------------- /tests/counter/top/icestick/verilog/Manifest.py: -------------------------------------------------------------------------------- 1 | files = [ "icestick_top.v", "../icestick.pcf" ] 2 | 3 | modules = { 4 | "local" : [ "../../../modules/counter/verilog" ], 5 | } 6 | -------------------------------------------------------------------------------- /tests/counter/top/icestick/verilog/icestick_top.v: -------------------------------------------------------------------------------- 1 | //--------------------------------------------------------------------- 2 | // Design : Counter verilog top module, iCEstick (Lattice iCE40) 3 | // Author : Javier D. Garcia-Lasheras 4 | //--------------------------------------------------------------------- 5 | 6 | module icestick_top ( 7 | clock_i, 8 | led_o_0, 9 | led_o_1, 10 | led_o_2, 11 | led_o_3, 12 | led_o_4, 13 | ); 14 | 15 | input clock_i; 16 | output led_o_0, led_o_1, led_o_2, led_o_3, led_o_4; 17 | 18 | wire s_clock, s_clear, s_count; 19 | wire [7:0] s_Q; 20 | 21 | counter u1( 22 | .clock(s_clock), 23 | .clear(s_clear), 24 | .count(s_count), 25 | .Q(s_Q) 26 | ); 27 | 28 | assign s_clock = clock_i; 29 | assign s_clear = 0; 30 | assign s_count = 1; 31 | assign led_o_4 = s_Q[7]; 32 | assign led_o_3 = s_Q[6]; 33 | assign led_o_2 = s_Q[5]; 34 | assign led_o_1 = s_Q[4]; 35 | assign led_o_0 = s_Q[3]; 36 | 37 | endmodule 38 | -------------------------------------------------------------------------------- /tests/counter/top/proasic3_sk/proasic3_top.pdc: -------------------------------------------------------------------------------- 1 | # Microsemi Physical design constraints file 2 | # Family: ProASIC3 , Die: A3P250 , Package: 208 PQFP , Speed grade: -2 3 | 4 | # 5 | # IO banks setting 6 | # 7 | 8 | set_iobank Bank3 -vcci 3.30 -fixed no 9 | set_iobank Bank2 -vcci 3.30 -fixed no 10 | set_iobank Bank1 -vcci 3.30 -fixed no 11 | set_iobank Bank0 -vcci 3.30 -fixed no 12 | 13 | # 14 | # I/O constraints 15 | # 16 | 17 | set_io led_o\[0\] -iostd LVTTL -REGISTER No -OUT_DRIVE 12 -SLEW High -RES_PULL None -SKEW Off -OUT_LOAD 35 -pinname 63 -fixed yes 18 | set_io led_o\[1\] -iostd LVTTL -REGISTER No -OUT_DRIVE 12 -SLEW High -RES_PULL None -SKEW Off -OUT_LOAD 35 -pinname 61 -fixed yes 19 | set_io led_o\[2\] -iostd LVTTL -REGISTER No -OUT_DRIVE 12 -SLEW High -RES_PULL None -SKEW Off -OUT_LOAD 35 -pinname 60 -fixed yes 20 | set_io led_o\[3\] -iostd LVTTL -REGISTER No -OUT_DRIVE 12 -SLEW High -RES_PULL None -SKEW Off -OUT_LOAD 35 -pinname 59 -fixed yes 21 | set_io led_o\[4\] -iostd LVTTL -REGISTER No -OUT_DRIVE 12 -SLEW High -RES_PULL None -SKEW Off -OUT_LOAD 35 -pinname 58 -fixed yes 22 | set_io led_o\[5\] -iostd LVTTL -REGISTER No -OUT_DRIVE 12 -SLEW High -RES_PULL None -SKEW Off -OUT_LOAD 35 -pinname 57 -fixed yes 23 | set_io led_o\[6\] -iostd LVTTL -REGISTER No -OUT_DRIVE 12 -SLEW High -RES_PULL None -SKEW Off -OUT_LOAD 35 -pinname 56 -fixed yes 24 | set_io led_o\[7\] -iostd LVTTL -REGISTER No -OUT_DRIVE 12 -SLEW High -RES_PULL None -SKEW Off -OUT_LOAD 35 -pinname 55 -fixed yes 25 | 26 | set_io clear_i -iostd LVTTL -REGISTER No -RES_PULL None -pinname 68 -fixed yes 27 | set_io count_i -iostd LVTTL -REGISTER No -RES_PULL None -pinname 67 -fixed yes 28 | 29 | # 40MHz clock 30 | set_io clock_i -iostd LVTTL -REGISTER No -RES_PULL None -pinname 26 -fixed yes 31 | 32 | -------------------------------------------------------------------------------- /tests/counter/top/proasic3_sk/proasic3_top.sdc: -------------------------------------------------------------------------------- 1 | # Top Level Design Parameters 2 | 3 | # Clocks 4 | 5 | 6 | # False Paths Between Clocks 7 | 8 | 9 | # False Path Constraints 10 | 11 | 12 | # Maximum Delay Constraints 13 | 14 | 15 | # Multicycle Constraints 16 | 17 | 18 | # Virtual Clocks 19 | # Output Load Constraints 20 | # Driving Cell Constraints 21 | # Wire Loads 22 | # set_wire_load_mode top 23 | 24 | # Other Constraints 25 | -------------------------------------------------------------------------------- /tests/counter/top/proasic3_sk/verilog/Manifest.py: -------------------------------------------------------------------------------- 1 | files = [ 2 | "proasic3_top.v", 3 | "../proasic3_top.pdc", 4 | "../proasic3_top.sdc", 5 | ] 6 | 7 | modules = { 8 | "local" : [ "../../../modules/counter/verilog" ], 9 | } 10 | -------------------------------------------------------------------------------- /tests/counter/top/proasic3_sk/verilog/proasic3_top.v: -------------------------------------------------------------------------------- 1 | //--------------------------------------------------------------------- 2 | // Design : Counter verilog top module, Microsemi ProASIC3 Starter Kit 3 | // Author : Javier D. Garcia-Lasheras 4 | //--------------------------------------------------------------------- 5 | 6 | module proasic3_top ( 7 | clear_i, 8 | count_i, 9 | clock_i, 10 | led_o 11 | ); 12 | 13 | input clear_i, count_i, clock_i; 14 | output [7:0] led_o; 15 | 16 | wire s_clock, s_clear, s_count; 17 | wire [7:0] s_Q; 18 | 19 | counter u1( 20 | .clock(s_clock), 21 | .clear(s_clear), 22 | .count(s_count), 23 | .Q(s_Q) 24 | ); 25 | 26 | assign s_clock = clock_i; 27 | assign s_clear = clear_i; 28 | assign s_count = count_i; 29 | assign led_o[7:0] = s_Q[7:0]; 30 | 31 | endmodule 32 | -------------------------------------------------------------------------------- /tests/counter/top/proasic3_sk/vhdl/Manifest.py: -------------------------------------------------------------------------------- 1 | files = [ 2 | "proasic3_top.vhd", 3 | "../proasic3_top.pdc", 4 | "../proasic3_top.sdc", 5 | ] 6 | 7 | modules = { 8 | "local" : [ "../../../modules/counter/vhdl" ], 9 | } 10 | -------------------------------------------------------------------------------- /tests/counter/top/proasic3_sk/vhdl/proasic3_top.vhd: -------------------------------------------------------------------------------- 1 | ----------------------------------------------------------------------- 2 | -- Design : Counter VHDL top module, Microsemi ProASIC3 Starter Kit 3 | -- Author : Javier D. Garcia-Lasheras 4 | ----------------------------------------------------------------------- 5 | 6 | library ieee; 7 | use ieee.std_logic_1164.all; 8 | use ieee.std_logic_unsigned.all; 9 | use ieee.std_logic_arith.all; 10 | 11 | entity proasic3_top is 12 | port ( 13 | clear_i: in std_logic; 14 | count_i: in std_logic; 15 | clock_i: in std_logic; 16 | led_o: out std_logic_vector(7 downto 0) 17 | ); 18 | end proasic3_top; 19 | 20 | ----------------------------------------------------------------------- 21 | 22 | architecture structure of proasic3_top is 23 | 24 | component counter 25 | port ( 26 | clock: in std_logic; 27 | clear: in std_logic; 28 | count: in std_logic; 29 | Q: out std_logic_vector(7 downto 0) 30 | ); 31 | end component; 32 | 33 | signal s_clock: std_logic; 34 | signal s_clear: std_logic; 35 | signal s_count: std_logic; 36 | signal s_Q: std_logic_vector(7 downto 0); 37 | 38 | begin 39 | 40 | U_counter: counter 41 | port map ( 42 | clock => s_clock, 43 | clear => s_clear, 44 | count => s_count, 45 | Q => s_Q 46 | ); 47 | 48 | s_clock <= clock_i; 49 | s_clear <= clear_i; 50 | s_count <= count_i; 51 | led_o <= s_Q; 52 | 53 | end architecture structure; 54 | 55 | ---------------------------------------------------------------- 56 | -------------------------------------------------------------------------------- /tests/counter/top/spec_v4/spec_top.ucf: -------------------------------------------------------------------------------- 1 | 2 | NET "CLOCK_I" LOC = H12; 3 | NET "CLOCK_I" IOSTANDARD = "LVCMOS18"; 4 | 5 | NET "COUNT_I" LOC = C22; 6 | NET "COUNT_I" IOSTANDARD = "LVCMOS18"; 7 | 8 | NET "CLEAR_I" LOC = D21; 9 | NET "CLEAR_I" IOSTANDARD = "LVCMOS18"; 10 | 11 | NET "LED_O[0]" LOC = G19; 12 | NET "LED_O[0]" IOSTANDARD = "LVCMOS18"; 13 | NET "LED_O[1]" LOC = F20; 14 | NET "LED_O[1]" IOSTANDARD = "LVCMOS18"; 15 | NET "LED_O[2]" LOC = F18; 16 | NET "LED_O[2]" IOSTANDARD = "LVCMOS18"; 17 | NET "LED_O[3]" LOC = C20; 18 | NET "LED_O[3]" IOSTANDARD = "LVCMOS18"; 19 | 20 | -------------------------------------------------------------------------------- /tests/counter/top/spec_v4/verilog/Manifest.py: -------------------------------------------------------------------------------- 1 | files = [ "spec_top.v", "../spec_top.ucf" ] 2 | 3 | modules = { 4 | "local" : [ "../../../modules/counter/verilog" ], 5 | } 6 | -------------------------------------------------------------------------------- /tests/counter/top/spec_v4/verilog/spec_top.v: -------------------------------------------------------------------------------- 1 | //--------------------------------------------------------------------- 2 | // Design : Counter verilog top module, SPEC (Simple PCIe Carrier) 3 | // Author : Javier D. Garcia-Lasheras 4 | //--------------------------------------------------------------------- 5 | 6 | module spec_top ( 7 | clear_i, 8 | count_i, 9 | clock_i, 10 | led_o 11 | ); 12 | 13 | input clear_i, count_i, clock_i; 14 | output [3:0] led_o; 15 | 16 | wire s_clock, s_clear, s_count; 17 | wire [7:0] s_Q; 18 | 19 | counter u1( 20 | .clock(s_clock), 21 | .clear(s_clear), 22 | .count(s_count), 23 | .Q(s_Q) 24 | ); 25 | 26 | assign s_clock = clock_i; 27 | assign s_clear = ~clear_i; 28 | assign s_count = ~count_i; 29 | assign led_o[3:0] = ~s_Q[7:4]; 30 | 31 | endmodule 32 | -------------------------------------------------------------------------------- /tests/counter/top/spec_v4/vhdl/Manifest.py: -------------------------------------------------------------------------------- 1 | files = [ "spec_top.vhd", "../spec_top.ucf" ] 2 | 3 | modules = { 4 | "local" : [ "../../../modules/counter/vhdl" ], 5 | } 6 | -------------------------------------------------------------------------------- /tests/counter/top/spec_v4/vhdl/spec_top.vhd: -------------------------------------------------------------------------------- 1 | ----------------------------------------------------------------------- 2 | -- Design : Counter VHDL top module, SPEC (Simple PCIe Carrier) 3 | -- Author : Javier D. Garcia-Lasheras 4 | ----------------------------------------------------------------------- 5 | 6 | library IEEE; 7 | use IEEE.STD_LOGIC_1164.all; 8 | use IEEE.NUMERIC_STD.all; 9 | 10 | library UNISIM; 11 | use UNISIM.vcomponents.all; 12 | 13 | 14 | entity spec_top is 15 | port ( 16 | clear_i: in std_logic; 17 | count_i: in std_logic; 18 | clock_i: in std_logic; 19 | led_o: out std_logic_vector(3 downto 0) 20 | ); 21 | end spec_top; 22 | 23 | ----------------------------------------------------------------------- 24 | 25 | architecture structure of spec_top is 26 | 27 | component counter 28 | port ( 29 | clock: in std_logic; 30 | clear: in std_logic; 31 | count: in std_logic; 32 | Q: out std_logic_vector(7 downto 0) 33 | ); 34 | end component; 35 | 36 | signal s_clock: std_logic; 37 | signal s_clear: std_logic; 38 | signal s_count: std_logic; 39 | signal s_Q: std_logic_vector(7 downto 0); 40 | 41 | begin 42 | 43 | U_counter: counter 44 | port map ( 45 | clock => s_clock, 46 | clear => s_clear, 47 | count => s_count, 48 | Q => s_Q 49 | ); 50 | 51 | s_clock <= clock_i; 52 | s_clear <= not clear_i; 53 | s_count <= not count_i; 54 | led_o(3 downto 0) <= not s_Q(7 downto 4); 55 | 56 | end architecture structure; 57 | 58 | ----------------------------------------------------------------------- 59 | 60 | -------------------------------------------------------------------------------- /tests/counter/top/zedboard/verilog/Manifest.py: -------------------------------------------------------------------------------- 1 | files = [ 2 | "zedboard_top.v", 3 | "../zedboard_top.xdc", 4 | ] 5 | 6 | modules = { 7 | "local" : [ "../../../modules/counter/verilog" ], 8 | } 9 | -------------------------------------------------------------------------------- /tests/counter/top/zedboard/verilog/zedboard_top.v: -------------------------------------------------------------------------------- 1 | //--------------------------------------------------------------------- 2 | // Design : Counter verilog top module, Avnet Zedboard Starter Kit 3 | // Author : Javier D. Garcia-Lasheras 4 | //--------------------------------------------------------------------- 5 | 6 | module zedboard_top ( 7 | clear_i, 8 | count_i, 9 | clock_i, 10 | led_o 11 | ); 12 | 13 | input clear_i, count_i, clock_i; 14 | output [7:0] led_o; 15 | 16 | wire s_clock, s_clear, s_count; 17 | wire [7:0] s_Q; 18 | 19 | counter u1( 20 | .clock(s_clock), 21 | .clear(s_clear), 22 | .count(s_count), 23 | .Q(s_Q) 24 | ); 25 | 26 | assign s_clock = clock_i; 27 | assign s_clear = clear_i; 28 | assign s_count = count_i; 29 | assign led_o[7:0] = s_Q[7:0]; 30 | 31 | endmodule 32 | -------------------------------------------------------------------------------- /tests/counter/top/zedboard/vhdl/Manifest.py: -------------------------------------------------------------------------------- 1 | files = [ 2 | "zedboard_top.vhd", 3 | "../zedboard_top.xdc", 4 | ] 5 | 6 | modules = { 7 | "local" : [ "../../../modules/counter/vhdl" ], 8 | } 9 | -------------------------------------------------------------------------------- /tests/counter/top/zedboard/vhdl/zedboard_top.vhd: -------------------------------------------------------------------------------- 1 | ----------------------------------------------------------------------- 2 | -- Design : Counter VHDL top module, Avnet Zedboard Starter Kit 3 | -- Author : Javier D. Garcia-Lasheras 4 | ----------------------------------------------------------------------- 5 | 6 | library ieee; 7 | use ieee.std_logic_1164.all; 8 | use ieee.std_logic_unsigned.all; 9 | use ieee.std_logic_arith.all; 10 | 11 | entity zedboard_top is 12 | port ( 13 | clear_i: in std_logic; 14 | count_i: in std_logic; 15 | clock_i: in std_logic; 16 | led_o: out std_logic_vector(7 downto 0) 17 | ); 18 | end zedboard_top; 19 | 20 | ----------------------------------------------------------------------- 21 | 22 | architecture structure of zedboard_top is 23 | 24 | component counter 25 | port ( 26 | clock: in std_logic; 27 | clear: in std_logic; 28 | count: in std_logic; 29 | Q: out std_logic_vector(7 downto 0) 30 | ); 31 | end component; 32 | 33 | signal s_clock: std_logic; 34 | signal s_clear: std_logic; 35 | signal s_count: std_logic; 36 | signal s_Q: std_logic_vector(7 downto 0); 37 | 38 | begin 39 | 40 | U_counter: counter 41 | port map ( 42 | clock => s_clock, 43 | clear => s_clear, 44 | count => s_count, 45 | Q => s_Q 46 | ); 47 | 48 | s_clock <= clock_i; 49 | s_clear <= clear_i; 50 | s_count <= count_i; 51 | led_o <= s_Q; 52 | 53 | end architecture structure; 54 | 55 | ---------------------------------------------------------------- 56 | -------------------------------------------------------------------------------- /tests/counter/top/zedboard/zedboard_top.xdc: -------------------------------------------------------------------------------- 1 | # ---------------------------------------------------------------------------- 2 | # Clock Source - Bank 13 3 | # ---------------------------------------------------------------------------- 4 | set_property PACKAGE_PIN Y9 [get_ports clock_i] 5 | set_property IOSTANDARD LVCMOS33 [get_ports clock_i] 6 | create_clock -add -name sys_clk_pin -period 8.00 -waveform {0 4} [get_ports clock_i] 7 | 8 | 9 | # ---------------------------------------------------------------------------- 10 | # Reset - BTNC (user button center) 11 | # ---------------------------------------------------------------------------- 12 | set_property PACKAGE_PIN P16 [get_ports {clear_i}] 13 | set_property IOSTANDARD LVCMOS33 [get_ports {clear_i}] 14 | 15 | 16 | # ---------------------------------------------------------------------------- 17 | # Count - BTNU (user button up) 18 | # ---------------------------------------------------------------------------- 19 | set_property PACKAGE_PIN T18 [get_ports {count_i}] 20 | set_property IOSTANDARD LVCMOS33 [get_ports {count_i}] 21 | 22 | 23 | # ---------------------------------------------------------------------------- 24 | # USER LEDs 25 | # ---------------------------------------------------------------------------- 26 | set_property PACKAGE_PIN T22 [get_ports "led_o[0]"] 27 | set_property IOSTANDARD LVCMOS33 [get_ports "led_o[0]"] 28 | set_property PACKAGE_PIN T21 [get_ports "led_o[1]"] 29 | set_property IOSTANDARD LVCMOS33 [get_ports "led_o[1]"] 30 | set_property PACKAGE_PIN U22 [get_ports "led_o[2]"] 31 | set_property IOSTANDARD LVCMOS33 [get_ports "led_o[2]"] 32 | set_property PACKAGE_PIN U21 [get_ports "led_o[3]"] 33 | set_property IOSTANDARD LVCMOS33 [get_ports "led_o[3]"] 34 | set_property PACKAGE_PIN V22 [get_ports "led_o[4]"] 35 | set_property IOSTANDARD LVCMOS33 [get_ports "led_o[4]"] 36 | set_property PACKAGE_PIN W22 [get_ports "led_o[5]"] 37 | set_property IOSTANDARD LVCMOS33 [get_ports "led_o[5]"] 38 | set_property PACKAGE_PIN U19 [get_ports "led_o[6]"] 39 | set_property IOSTANDARD LVCMOS33 [get_ports "led_o[6]"] 40 | set_property PACKAGE_PIN U14 [get_ports "led_o[7]"] 41 | set_property IOSTANDARD LVCMOS33 [get_ports "led_o[7]"] 42 | --------------------------------------------------------------------------------